--- gcc-6-6.4.0.orig/debian/FAQ.gcj
+++ gcc-6-6.4.0/debian/FAQ.gcj
@@ -0,0 +1,494 @@
+The GCJ FAQ
+===========
+
+      The latest version of this document is always available at
+      http://gcc.gnu.org/java/faq.html.
+
+        General Questions
+
+            What license is used for libgcj?
+            How can I report a bug in libgcj?
+            How can I contribute to libgcj
+            Is libgcj part of GCC?
+            Will gcj and libgcj work on my machine?
+            How can I debug my Java program?
+            Can I interface byte-compiled and native java code?
+
+
+        Java Feature Support
+
+            What Java API's are supported? How complete is
+              the support?
+            Does GCJ support using straight C native methods
+              ala JNI?
+            Why does GCJ use CNI?
+            What is the state of AWT support?
+            How about support for Swing ?
+            What support is there for RMI ?
+            Can I use any code from other OpenSource projects
+              to supplement libgcj's current features ?
+            What features of the Java language are/arn't supported
+
+
+        Build Issues
+
+            I need something more recent than the last release; how
+                  should I build it?
+            Linker bug on Solaris
+            Can I configure/build in the source tree?
+            My libgcj build fails with "invalid use of undefined type
+                  struct sigcontext_struct"
+
+
+        Gcj Compile/Link Questions
+
+            Why do I get undefined reference to `main' errors?
+            Can GCJ only handle source code?
+            "gcj -C" Doesn't seem to work like javac/jikes. Whats going on?
+            Where does GCJ look for files?
+            How does gcj resolve wether to compile .class or .java files?
+            I'm getting link errors!
+            I'm getting 'undefined symbol: __dso_handle'
+
+
+        Runtime Questions
+
+            My program is dumping core! What's going on?
+            When I run the debugger I get a SEGV in the GC! What's going on?
+            I have just compiled and benchmarked my Java application
+            and it seems to be running slower than than XXX JIT JVM. Is there
+            anything I can do to make it go faster?
+            Can I profile Garbage Collection?
+            How do I increase the runtime's initial and maximum heap sizes?
+            How can I profile my application?
+            My program seems to hang and doesn't produce any output
+
+
+        Programming Issues
+
+            Are there any examples of how to use CNI?
+            Is it possible to invoke GCJ compiled Java code from a
+            C++ application?
+
+General Questions
+=================
+
+      1.1 What license is used for libgcj?
+
+          libgcj is distributed under the GPL, with the 'libgcc exception'.
+          This means that linking with libgcj does not by itself cause
+          your program to fall under the GPL.  See LIBGCJ_LICENSE in
+          the source tree for more details.
+
+      1.2 How can I report a bug in libgcj?
+
+          libgcj has a corresponding Gnats bug database which you can
+          browse. You can also submit new bug reports from the Gnats
+          page.
+
+      1.3 How can I contribute to libgcj?
+
+          You can send simple bug fixes in as patches. Please follow
+          the GCC guidelines for submitting patches. For more complex
+          changes, you must sign copyright over to the Free Software
+          Foundation. See the contribution page for details.
+
+      1.4 Is libgcj part of GCC?
+
+          Yes, libgcj is now part of GCC. It can be downloaded,
+          configured and built as one single tree.
+
+      1.5 Will gcj and libgcj work on my machine?
+
+          Gcj and libgcj are known to work more or less with IA-32 and
+          Sparc Solaris, Tru64 Unix, as well as IA-32, IA-64, Alpha,
+          and PowerPC Linux. They might work on other
+          systems. Generally speaking, porting to a new system should
+          not be hard. This would be a good way to volunteer.
+
+      1.6 How can I debug my Java program?
+
+          gdb 5.0 includes support for debugging gcj-compiled Java
+          programs. For more information please read Java Debugging
+          with gdb.
+
+      1.7 Can I interface byte-compiled and native java code
+
+          libgcj has a bytecode interpreter that allows you to mix
+          .class files with compiled code. It works pretty
+          transparently: if a compiled version of a class is not found
+          in the application binary or linked shared libraries, the
+          class loader will search for a bytecode version in your
+          classpath, much like a VM would. Be sure to build libgcj
+          with the --enable-interpreter option to enable this
+          functionality.
+
+          The program "gij" provides a front end to the interpreter
+          that behaves much like a traditional virtual machine. You
+          can even use "gij" to run a shared library which is compiled
+          from java code and contains a main method:
+
+          $ gcj -shared -o lib-HelloWorld.so HelloWorld.java
+          $ gij HelloWorld
+
+          This works because gij uses Class.forName, which knows how
+          to load shared objects.
+
+Java Feature Support
+====================
+
+      2.1 What Java API's are supported? How complete is
+        the support?
+
+          Matt Welsh writes:
+
+            Just look in the 'libjava' directory of libgcj and see
+            what classes are there. Most GUI stuff isn't there yet,
+            that's true, but many of the other classes are easy to add
+            if they don't yet exist.
+
+            I think it's important to stress that there is a big
+            difference between Java and the many libraries which Java
+            supports. Unfortunately, Sun's promise of "write once, run
+            everywhere" assumes much more than a JVM: you also need
+            the full set of JDK libraries. Considering that new Java
+            APIs come out every week, it's going to be impossible to
+            track everything.
+
+            To make things worse, you can't simply run Sun's JDK
+            classes on any old JVM -- they assume that a bunch of
+            native methods are also defined. Since this native method
+            requirement isn't defined by the JDK specs, you're
+            effectively constrained to using Sun's JVMs if you want to
+            use Sun's JDK libraries. Oh yes -- you could also
+            reimplement all of those native methods yourself, and make
+            sure they behave exactly as Sun's do. Note that they're
+            undocumented!
+
+      2.2 Does GCJ support using straight C native methods
+         ala JNI?
+
+          Yes. libgcj now has experimental support for JNI, in
+          addition to its native Compiled Native Interface (CNI). gcjh
+          will generate JNI stubs and headers using the "-jni"
+          option. However, we do prefer CNI: it is more efficient,
+          easier to write, and (at least potentially) easier to debug.
+
+      2.3 Why does GCJ use CNI?
+
+          Per Bothner explains:
+
+            We use CNI because we think it is a better solution,
+            especially for a Java implementation that is based on the
+            idea that Java is just another programming language that
+            can be implemented using standard compilation
+            techniques. Given that, and the idea that languages
+            implemented using Gcc should be compatible where it makes
+            sense, it follows that the Java calling convention should
+            be as similar as practical to that used for other
+            languages, especially C++, since we can think of Java as a
+            subset of C++. CNI is just a set of helper functions and
+            conventions built on the idea that C++ and Java have the
+            *same* calling convention and object layout; they are
+            binary compatible. (This is a simplification, but close
+            enough.)
+
+      2.4 What is the state of AWT support?
+
+          Work is in progress to implement AWT and Java2D. We intend
+          to support both GTK and xlib peers written using CNI. Some
+          components are already working atop the xlib peers.
+
+      2.5 How about support for Swing?
+
+          Once AWT support is working then Swing support can be
+          considered. There is at least one free-software partial
+          implementations of Swing that may be usable.
+
+      2.6 What support is there for RMI?
+
+         RMI code exists on the CVS trunk (aka gcc 3.1), but it has
+         not been heavily tested.  This code was donated by
+         Transvirtual Technologies.
+
+      2.7 Can I use any code from other OpenSource
+          projects to supplement libgcj's current features?
+
+           Certainly. However, in many cases, if you wanted to
+           contribute the code back into the official libgcj
+           distribution, we would require that the original author(s)
+           assign copyright to the Free Software Foundation.  As of
+           March 6, 2000, libgcj has been relicenced, and copyright
+           has been assigned to the FSF. This allows us to share and
+           merge much of the libgcj codebase with the Classpath
+           project.  Our eventual goal is for Classpath to be an
+           upstream source provider for libgcj, however it will be
+           some time before this becomes reality: libgcj and Classpath
+           have different implementations of many core java
+           classes. In order to merge them, we need to select the best
+           (most efficient, cleanest) implementation of each
+           method/class/package, resolve any conflicts created by the
+           merge, and test the final result.  Needless to say, this is
+           a lot of work. If you can help out, please let us know!
+
+      2.8 What features of the Java language are/aren't supported.
+
+          GCJ supports all Java language constructs as per the Java
+          language Specification.  Recent GCJ snapshots have added
+          support for most JDK1.1 (and beyond) language features,
+          including inner classes.
+
+Build Issues
+============
+
+      3.1 I need something more recent than the last release.
+          How should I build it?
+
+          Please read here: http://gcc.gnu.org/java/build-snapshot.html
+
+      3.2 Linker bug on Solaris
+
+          There is a known problem with the native Solaris linker when
+          using gcc/gcj. A good indication you've run into this
+          problem is if you get an error that looks like the following
+          when building libgcj:
+
+ld: warning: option -o appears more than once, first setting taken
+ld: fatal: file libfoo.so: cannot open file: No such file or directory
+ld: fatal: File processing errors. No output written to .libs/libfoo.so
+collect2: ld returned 1 exit status
+
+          A known workaround for this and other reported link problems
+          on the various releases of Solaris is to build gcc/gcj with
+          the latest GNU binutils instead of the native Solaris
+          ld. The most straightforward way to do this is to build and
+          install binutils, and then reference it in the configure for
+          gcc via --with-ld=/path_to_binutils_install/bin/ld
+          (--with-as may also be similarly specified but is not
+          believed to be required).
+
+          Please note, gcc/gcj must be built using GNU ld prior to
+          doing a clean build of libgcj!
+
+      3.3 Can I configure/build in the source tree?
+
+          No.  You cannot configure/build in the source tree.  If you
+          try, you'll see something like:
+
+              $ ./configure [...]
+              Configuring for a i686-pc-linux-gnu host.
+              *** Cannot currently configure in source tree.
+
+          Instead, you must build in another directory.  E.g.:
+
+              $ mkdir build
+              $ cd build
+              $ ../configure [...]
+
+      3.4 My libgcj build fails with "invalid use of undefined type
+          struct sigcontext_struct"
+
+          If you're using Linux, this probably means you need to
+          upgrade to a newwer, glibc (libc6) based Linux
+          distribution. libgcj does not support the older linux libc5.
+          It might be possible to get a working libgcj by changing
+          occurances of "sigcontext_struct" to "sigcontext", however
+          this has not been tested.  Even if it works, it is likely
+          that there are other issues with older libc versions that
+          would prevent libgcj from working correctly (threads bugs,
+          for example).
+
+Gcj Compile/Link Questions
+==========================
+
+      4.1 Why do I get undefined reference to `main' errors?
+
+          When using gcj to link a Java program, you must use the --main=
+          option to indicate the class that has the desired main method.
+          This is because every Java class can have a main method, thus
+          you have to tell gcj which one to use.
+
+      4.2 Can GCJ only handle source code?
+
+          GCJ will compile both source (.java) and bytecode (.class)
+          files. However, in many cases the native code produced by
+          compiling from source is better optimized than that compiled
+          from .class files.
+
+          Per Bothner explains:
+
+            The reason is that when you compile to bytecode you lose a
+            lot of information about program structure etc. That
+            information helps in generating better code. We can in
+            theory recover the information we need by analysing the
+            structure of the bytecodes, but it is sometimes difficult
+            - or sometimes it just that no-one has gotten around to
+            it.  Specific examples include loop structure (gcc
+            generates better code with explicit loops rather than with
+            the equivalent spaghetti code), array initializers, and
+            the JDK 1.1 `CLASS.class' syntax, all of which are
+            represented using more low-level constructs in bytecode.
+
+      4.3 "gcj -C" Doesn't seem to work like javac/jikes.  Whats going on?
+
+          The behavior of "gcj -C" is not at all like javac or jikes,
+          which will compile (not just scan) all .java's which are out
+          of date with regard to their .class's.
+
+      4.4 Where does GCJ look for files?
+
+          GCJ looks for classes to compile based on the CLASSPATH
+          environment variable. libgcj.jar and other files are found
+          relative to the path of the compiler itself, so it is safe
+          to move the entire compiler tree to a different path, and
+          there is no need to include libgcj.jar in your CLASSPATH.
+
+      4.5 How does gcj resolve whether to compile .class or .java files?
+
+          GCJ compiles only the files presented to it on the command
+          line. However, it also needs to scan other files in order to
+          determine the layout of other classes and check for errors
+          in your code.  For these dependencies, GCJ will favour
+          .class files if they are available because it is faster to
+          parse a class file than source code.
+
+      4.6 I'm getting link errors
+
+          If you get errors at link time that refer to 'undefined
+          reference to `java::lang::Object type_info function', verify
+          that you have compiled any CNI C++ files with the -fno-rtti
+          option. This is only required for versions of GCJ earlier
+          than 3.0.
+
+      4.7 I'm getting 'undefined symbol: __dso_handle'
+
+          Some versions of the GNU linker have broken support for the
+          '.hidden' directive, which results in problems with shared
+          libraries built with recent versions of gcc.
+
+          There are three solutions:
+
+            - downgrade to binutils that don't support .hidden at all,
+            - upgrade to a recent binutils, or
+            - undef the HAVE_GAS_HIDDEN definition in gcc's auto-host.h
+              (and rebuild gcc).
+
+Runtime Questions
+=================
+
+      5.1 My program is dumping core! What's going on?
+
+          It could be any number of things. One common mistake is
+          having your CLASSPATH environment variable pointing at a
+          third party's java.lang and friends. Either unset CLASSPATH,
+          or make sure it does not refer to core libraries other than
+          those found in libgcj.jar.Note that newwer versions of GCJ
+          will reject the core class library if it wasn't generated by
+          GCJ itself.
+
+      5.2 When I run the debugger I get a SEGV in the GC! What's going on?
+
+          This is "normal"; the Garbage Collector (GC) uses it to
+          determine stack boundaries. It is ordinarily caught and
+          handled by the GC -- you can see this in the debugger by
+          using cont to continue to the "real" segv.
+
+      5.3 I have just compiled and benchmarked my Java application
+          and it seems to be running slower than than XXX JIT JVM. Is there
+          anything I can do to make it go faster?
+
+        A few things:
+
+          - If your programs allocate many small, short lived objects,
+            the heap could be filling and triggering GC too
+            regularly. Try increasing the initial and maximum heap sizes
+            as per 5.5 How do I increase the runtime's initial and
+            maximum heap size?
+          - RE - array accesses. We have sub-optimal runtime checking
+            code, and the compiler is still not so smart about
+            automatically removing array checks. If your code is ready,
+            and it doesn't rely on them, try compiling with
+            --no-bounds-check.
+          - Try static linking.  On many platforms, dynamic (PIC)
+            function calls are more expensive than static ones. In
+            particular, the interaction with boehm-gc seems to incur
+            extra overhead when shared libraries are used.
+          - If your Java application doesn't need threads, try
+            building libgcj using --enable-threads=none. Portions of the
+            libgcj runtime are still more efficient when
+            single-threaded.
+
+       5.4 Can I profile Garbage Collection?
+
+          It is possible to turn on verbose GC output by supressing
+          the -DSILENT flag during build. One way to do this is to
+          comment out the line with #define SILENT 1 from
+          boehm-gc/configure before configuring libgcj.  The GC will
+          print collection statistics to stdout. (Rebuilding boehm-gc
+          alone without this flag doesn't seem to work.)
+
+      5.5 How do I increase the runtime's initial and maximum heap sizes?
+
+          Some programs that allocate many small, short-lived objects
+          can cause the default-sized heap to fill quickly and GC
+          often. With the 2.95.1 release there is no means to adjust
+          the heap at runtime. Recent snapshots provide the -ms and
+          -mx arguments to gij to specify the initial and maximum heap
+          sizes, respectively.
+
+      5.6 How can I profile my application?
+
+          Currently, only single threaded Java code may be used by the
+          profiler (gprof). POSIX threads seem to be incompatible with
+          the gmon stuff.  A couple of other tools that have been
+          mentioned on the GCJ mailing list are sprof and cprof.  The
+          former is part of GNU libc.
+
+      5.7 My program seems to hang and doesn't produce any output
+
+          Some versions had a bug in the iconv support. You can work
+          around it by setting LANG=en_US.UTF-8 at runtime, or give
+          the following option during compile time
+          -Dfile.encoding=UTF-8.  This problem should no longer occur
+          as of November 1, 2000.
+
+Programming Issues
+==================
+
+      6.1 Are there any examples of how to use CNI?
+
+          Glenn Chambers has created a couple of trivial examples for
+          version 2.95 and version 3.0.  As a comparison, here is the
+          same example as a JNI application using Kaffe.  The same
+          code will work with GCJ, as shown here.
+
+          Note that for version 2.95, you must compile the C++ files
+          used for CNI with the -fno-rtti option.  This constraint
+          does not apply in version 3.0 and later.
+
+          The primary source of documentation for CNI is at
+          http://gcc.gnu.org/java/papers/cni/t1.html
+
+      6.2 Is it possible to invoke GCJ compiled Java code from a
+          C++ application?
+
+          Yes, GCJ 3.1 supports a CNI-based invocation interface as
+          well as the traditional JNI invocation API.  See the GCJ
+          Manual for more details on how to use the CNI interface.
+
+Please send FSF & GNU inquiries & questions tognu@gnu.org.There are
+also other waysto contact the FSF.
+
+These pages are maintained by The GCC team.
+
+Please send comments on these web pages and GCC to our publicmailing
+list at gcc@gnu.org orgcc@gcc.gnu.org, send other questions to
+gnu@gnu.org.
+
+Copyright (C) Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA  02111,  USA.
+
+Verbatim copying and distribution of this entire article is permitted
+in any medium, provided this notice is preserved.
+
+Last modified 2003-04-30
--- gcc-6-6.4.0.orig/debian/NEWS.gcc
+++ gcc-6-6.4.0/debian/NEWS.gcc
@@ -0,0 +1,707 @@
+This file contains information about GCC releases which has been generated
+automatically from the online release notes.  It covers releases of GCC
+(and the former EGCS project) since EGCS 1.0, on the line of development
+that led to GCC 3. For information on GCC 2.8.1 and older releases of GCC 2,
+see ONEWS.
+
+======================================================================
+http://gcc.gnu.org/gcc-6/index.html
+                              GCC 6 Release Series
+
+   April 27, 2015
+
+   The [1]GNU project and the GCC developers are pleased to announce the
+   release of GCC 6.1.
+
+   This release is a major release, containing new features (as well as
+   many other improvements) relative to GCC 5.x.
+
+Release History
+
+   GCC 6.1
+          April 27, 2015 ([2]changes, [3]documentation)
+
+References and Acknowledgements
+
+   GCC used to stand for the GNU C Compiler, but since the compiler
+   supports several other languages aside from C, it now stands for the
+   GNU Compiler Collection.
+
+   A list of [4]successful builds is updated as new information becomes
+   available.
+
+   The GCC developers would like to thank the numerous people that have
+   contributed new features, improvements, bug fixes, and other changes as
+   well as test results to GCC. This [5]amazing group of volunteers is
+   what makes GCC successful.
+
+   For additional information about GCC please refer to the [6]GCC project
+   web site or contact the [7]GCC development mailing list.
+
+   To obtain GCC please use [8]our mirror sites or [9]our SVN server.
+
+
+    For questions related to the use of GCC, please consult these web
+    pages and the [10]GCC manuals. If that fails, the
+    [11]gcc-help@gcc.gnu.org mailing list might help. Comments on these
+    web pages and the development of GCC are welcome on our developer
+    list at [12]gcc@gcc.gnu.org. All of [13]our lists have public
+    archives.
+
+   Copyright (C) [14]Free Software Foundation, Inc. Verbatim copying and
+   distribution of this entire article is permitted in any medium,
+   provided this notice is preserved.
+
+   These pages are [15]maintained by the GCC team. Last modified
+   2016-04-27[16].
+
+References
+
+   1. http://www.gnu.org/
+   2. http://gcc.gnu.org/gcc-6/changes.html
+   3. http://gcc.gnu.org/onlinedocs/6.1.0/
+   4. http://gcc.gnu.org/gcc-6/buildstat.html
+   5. http://gcc.gnu.org/onlinedocs/gcc/Contributors.html
+   6. http://gcc.gnu.org/index.html
+   7. mailto:gcc@gcc.gnu.org
+   8. http://gcc.gnu.org/mirrors.html
+   9. http://gcc.gnu.org/svn.html
+  10. https://gcc.gnu.org/onlinedocs/
+  11. mailto:gcc-help@gcc.gnu.org
+  12. mailto:gcc@gcc.gnu.org
+  13. https://gcc.gnu.org/lists.html
+  14. http://www.fsf.org/
+  15. https://gcc.gnu.org/about.html
+  16. http://validator.w3.org/check/referer
+======================================================================
+http://gcc.gnu.org/gcc-6/changes.html
+                              GCC 6 Release Series
+                        Changes, New Features, and Fixes
+
+   This page is a brief summary of some of the huge number of improvements
+   in GCC 6. For more information, see the [1]Porting to GCC 6 page and
+   the [2]full GCC documentation.
+
+Caveats
+
+     * The default mode for C++ is now -std=gnu++14 instead of
+       -std=gnu++98.
+     * Support for a number of older systems and recently unmaintained or
+       untested target ports of GCC has been declared obsolete in GCC 6.
+       Unless there is activity to revive them, the next release of GCC
+       will have their sources permanently removed.
+       The following ports for individual systems on particular
+       architectures have been obsoleted:
+          + SH5 / SH64 (sh64-*-*) as announced [3]here.
+
+General Optimizer Improvements
+
+     * UndefinedBehaviorSanitizer gained a new sanitization option,
+       -fsanitize=bounds-strict, which enables strict checking of array
+       bounds. In particular, it enables -fsanitize=bounds as well as
+       instrumentation of flexible array member-like arrays.
+     * Type-based alias analysis now disambiguates accesses to different
+       pointers. This improves precision of the alias oracle by about
+       20-30% on higher-level C++ programs. Programs doing invalid type
+       punning of pointer types may now need -fno-strict-aliasing to work
+       correctly.
+     * Alias analysis now correctly supports weakref and alias attributes.
+       This makes it possible to access both a variable and its alias in
+       one translation unit which is common with link-time optimization.
+     * Value range propagation now assumes that the this pointer of C++
+       member functions is non-null. This eliminates common null pointer
+       checks but also breaks some non-conforming code-bases (such as
+       Qt-5, Chromium, KDevelop). As a temporary work-around
+       -fno-delete-null-pointer-checks can be used. Wrong code can be
+       identified by using -fsanitize=undefined.
+     * Link-time optimization improvements:
+          + warning and error attributes are now correctly preserved by
+            declaration linking and thus -D_FORTIFY_SOURCE=2 is now
+            supported with -flto.
+          + Type merging was fixed to handle C and Fortran
+            interoperability rules as defined by the Fortran 2008 language
+            standard.
+            As an exception, CHARACTER(KIND=C_CHAR) is not inter-operable
+            with char in all cases because it is an array while char is
+            scalar. INTEGER(KIND=C_SIGNED_CHAR) should be used instead. In
+            general, this inter-operability cannot be implemented, for
+            example, on targets where function passing conventions of
+            arrays differs from scalars.
+          + More type information is now preserved at link time reducing
+            the loss of accuracy of the type based alias analysis compared
+            to builds without link-time optimization.
+          + Invalid type punning on global variables and declarations is
+            now reported with -Wodr-type-mismatch.
+          + The size of LTO object files was reduced by about 11%
+            (measured by compiling Firefox 46.0).
+          + Link-time parallelization (enabled using -flto=n) was
+            significantly improved by decreasing the size of streamed data
+            when partitioning programs. The size of streamed IL while
+            compiling Firefox 46.0 was reduced by 66%.
+          + The linker plugin was extended to pass information about type
+            of binary produced to GCC back end (that can be also manually
+            controlled by -flinker-output). This makes it possible to
+            properly configure the code generator and support incremental
+            linking. Incremental linking of LTO objects by gcc -r is now
+            supported on plugin-enabled setups.
+            There are two ways to perform incremental linking:
+              1. Linking by ld -r will result in an object file with all
+                 sections from individual object files mechanically
+                 merged. This delays the actual link time optimization to
+                 final linking step and thus permits whole program
+                 optimization. Linking final binary with such object files
+                 is however slower.
+              2. Linking by gcc -r will lead to link time optimization and
+                 produce final binary into the object file. Linking such
+                 object file is fast but avoids any benefits from whole
+                 program optimization.
+            GCC 7 will support incremental link-time optimization with gcc
+            -r.
+     * Inter-procedural optimization improvements:
+          + Basic jump threading is now performed before profile
+            construction and inline analysis, resulting in more realistic
+            size and time estimates that drive the heuristics of the of
+            inliner and function cloning passes.
+          + Function cloning now more aggressively eliminates unused
+            function parameters.
+
+New Languages and Language specific improvements
+
+   Compared to GCC 5, the GCC 6 release series includes a much improved
+   implementation of the [4]OpenACC 2.0a specification. Highlights are:
+     * In addition to single-threaded host-fallback execution, offloading
+       is supported for nvptx (Nvidia GPUs) on x86_64 and PowerPC 64-bit
+       little-endian GNU/Linux host systems. For nvptx offloading, with
+       the OpenACC parallel construct, the execution model allows for an
+       arbitrary number of gangs, up to 32 workers, and 32 vectors.
+     * Initial support for parallelized execution of OpenACC kernels
+       constructs:
+          + Parallelization of a kernels region is switched on by
+            -fopenacc combined with -O2 or higher.
+          + Code is offloaded onto multiple gangs, but executes with just
+            one worker, and a vector length of 1.
+          + Directives inside a kernels region are not supported.
+          + Loops with reductions can be parallelized.
+          + Only kernels regions with one loop nest are parallelized.
+          + Only the outer-most loop of a loop nest can be parallelized.
+          + Loop nests containing sibling loops are not parallelized.
+       Typically, using the OpenACC parallel construct gives much better
+       performance, compared to the initial support of the OpenACC kernels
+       construct.
+     * The device_type clause is not supported. The bind and nohost
+       clauses are not supported. The host_data directive is not supported
+       in Fortran.
+     * Nested parallelism (cf. CUDA dynamic parallelism) is not supported.
+     * Usage of OpenACC constructs inside multithreaded contexts (such as
+       created by OpenMP, or pthread programming) is not supported.
+     * If a call to the acc_on_device function has a compile-time constant
+       argument, the function call evaluates to a compile-time constant
+       value only for C and C++ but not for Fortran.
+
+   See the [5]OpenACC and [6]Offloading wiki pages for further
+   information.
+
+  C family
+
+     * Version 4.5 of the [7]OpenMP specification is now supported in the
+       C and C++ compilers.
+     * The C and C++ compilers now support attributes on enumerators. For
+       instance, it is now possible to mark enumerators as deprecated:
+
+enum {
+  newval,
+  oldval __attribute__ ((deprecated ("too old")))
+};
+
+     * Source locations for the C and C++ compilers are now tracked as
+       ranges, rather than just points, making it easier to identify the
+       subexpression of interest within a complicated expression. For
+       example:
+
+test.cc: In function 'int test(int, int, foo, int, int)':
+test.cc:5:16: error: no match for 'operator*' (operand types are 'int' and 'foo'
+)
+   return p + q * r * s + t;
+              ~~^~~
+
+       In addition, there is now initial support for precise diagnostic
+       locations within strings:
+
+format-strings.c:3:14: warning: field width specifier '*' expects a matching 'in
+t' argument [-Wformat=]
+   printf("%*d");
+            ^
+
+     * Diagnostics can now contain "fix-it hints", which are displayed in
+       context underneath the relevant source code. For example:
+
+fixits.c: In function 'bad_deref':
+fixits.c:11:13: error: 'ptr' is a pointer; did you mean to use '->'?
+   return ptr.x;
+             ^
+             ->
+
+     * The C and C++ compilers now offer suggestions for misspelled field
+       names:
+
+spellcheck-fields.cc:52:13: error: 'struct s' has no member named 'colour'; did
+you mean 'color'?
+   return ptr->colour;
+               ^~~~~~
+
+     * New command-line options have been added for the C and C++
+       compilers:
+          + -Wshift-negative-value warns about left shifting a negative
+            value.
+          + -Wshift-overflow warns about left shift overflows. This
+            warning is enabled by default. -Wshift-overflow=2 also warns
+            about left-shifting 1 into the sign bit.
+          + -Wtautological-compare warns if a self-comparison always
+            evaluates to true or false. This warning is enabled by -Wall.
+          + -Wnull-dereference warns if the compiler detects paths that
+            trigger erroneous or undefined behavior due to dereferencing a
+            null pointer. This option is only active when
+            -fdelete-null-pointer-checks is active, which is enabled by
+            optimizations in most targets. The precision of the warnings
+            depends on the optimization options used.
+          + -Wduplicated-cond warns about duplicated conditions in an
+            if-else-if chain.
+          + -Wmisleading-indentation warns about places where the
+            indentation of the code gives a misleading idea of the block
+            structure of the code to a human reader. For example, given
+            [8]CVE-2014-1266:
+
+sslKeyExchange.c: In function 'SSLVerifySignedServerKeyExchange':
+sslKeyExchange.c:629:3: warning: this 'if' clause does not guard... [-Wmisleadin
+g-indentation]
+    if ((err = SSLHashSHA1.update(&hashCtx, &signedParams)) != 0)
+    ^~
+sslKeyExchange.c:631:5: note: ...this statement, but the latter is misleadingly
+indented as if it is guarded by the 'if'
+        goto fail;
+        ^~~~
+
+            This warning is enabled by -Wall.
+     * The C and C++ compilers now emit saner error messages if
+       merge-conflict markers are present in a source file.
+
+test.c:3:1: error: version control conflict marker in file
+ <<<<<<< HEAD
+ ^~~~~~~
+
+  C
+
+     * It is possible to disable warnings when an initialized field of a
+       structure or a union with side effects is being overridden when
+       using designated initializers via a new warning option
+       -Woverride-init-side-effects.
+     * A new type attribute scalar_storage_order applying to structures
+       and unions has been introduced. It specifies the storage order (aka
+       endianness) in memory of scalar fields in structures or unions.
+
+  C++
+
+     * The default mode has been changed to -std=gnu++14.
+     * [9]C++ Concepts are now supported when compiling with -fconcepts.
+     * -flifetime-dse is more aggressive in dead-store elimination in
+       situations where a memory store to a location precedes a
+       constructor to the memory location.
+     * G++ now supports [10]C++17 fold expressions, u8 character literals,
+       extended static_assert, and nested namespace definitions.
+     * G++ now allows constant evaluation for all non-type template
+       arguments.
+     * G++ now supports C++ Transactional Memory when compiling with
+       -fgnu-tm.
+
+    Runtime Library (libstdc++)
+
+     * Extensions to the C++ Library to support mathematical special
+       functions (ISO/IEC 29124:2010), thanks to Edward Smith-Rowland.
+     * Experimental support for C++17, including the following new
+       features:
+          + std::uncaught_exceptions function (this is also available for
+            -std=gnu++NN modes);
+          + new member functions try_emplace and insert_or_assign for
+            unique_key maps;
+          + non-member functions std::size, std::empty, and std::data for
+            accessing containers and arrays;
+          + std::invoke;
+          + std::shared_mutex;
+          + std::void_t and std::bool_constant metaprogramming utilities.
+       Thanks to Ville Voutilainen for contributing many of the C++17
+       features.
+     * An experimental implementation of the File System TS.
+     * Experimental support for most features of the second version of the
+       Library Fundamentals TS. This includes polymorphic memory resources
+       and array support in shared_ptr, thanks to Fan You.
+     * Some assertions checked by Debug Mode can now also be enabled by
+       _GLIBCXX_ASSERTIONS. The subset of checks enabled by the new macro
+       have less run-time overhead than the full _GLIBCXX_DEBUG checks and
+       don't affect the library ABI, so can be enabled per-translation
+       unit.
+     * Timed mutex types are supported on more targets, including Darwin.
+     * Improved std::locale support for DragonFly and FreeBSD, thanks to
+       John Marino and Andreas Tobler.
+
+  Fortran
+
+     * The MATMUL intrinsic is now inlined for straightforward cases if
+       front-end optimization is active. The maximum size for inlining can
+       be set to n with the -finline-matmul-limit=n option and turned off
+       with -finline-matmul-llimit=0.
+     * The -Wconversion-extra option will warn about REAL constants which
+       have excess precision for their kind.
+     * The -Winteger-division option has been added, which warns about
+       divisions of integer constants which are truncated. This option is
+       included in -Wall by default.
+
+libgccjit
+
+     * The driver code is now run in-process within libgccjit, providing a
+       small speed-up of the compilation process.
+     * The API has gained entrypoints for
+          + [11]timing how long was spent in different parts of code,
+          + [12]creating switch statements,
+          + [13]allowing unreachable basic blocks in a function, and
+          + [14]adding arbitrary command-line options to a compilation.
+
+New Targets and Target Specific Improvements
+
+  AArch64
+
+     * The new command line options -march=native, -mcpu=native and
+       -mtune=native are now available on native AArch64 GNU/Linux
+       systems. Specifying these options will cause GCC to auto-detect the
+       host CPU and rewrite these options to the optimal setting for that
+       system. If GCC is unable to detect the host CPU these options have
+       no effect.
+     * -fpic is now supported by the AArch64 target when generating code
+       for the small code model (-mcmodel=small). The size of the global
+       offset table (GOT) is limited to 28KiB under the LP64 SysV ABI ,
+       and 15KiB under the ILP32 SysV ABI.
+     * The AArch64 port now supports target attributes and pragmas. Please
+       refer to the [15]documentation for details of available attributes
+       and pragmas as well as usage instructions.
+     * Link-time optimization across translation units with different
+       target-specific options is now supported.
+
+  ARM
+
+     * Support for revisions of the ARM architecture prior to ARMv4t has
+       been deprecated and will be removed in a future GCC release. The
+       -mcpu and -mtune values that are deprecated are: arm2, arm250,
+       arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7d, arm7di,
+       arm70, arm700, arm700i, arm710, arm720, arm710c, arm7100, arm7500,
+       arm7500fe, arm7m, arm7dm, arm7dmi, arm8, arm810, strongarm,
+       strongarm110, strongarm1100, strongarm1110, fa526, fa626. The value
+       arm7tdmi is still supported. The values of -march that are
+       deprecated are: armv2,armv2a,armv3,armv3m,armv4.
+     * The ARM port now supports target attributes and pragmas. Please
+       refer to the [16]documentation for details of available attributes
+       and pragmas as well as usage instructions.
+     * Support has been added for the following processors (GCC
+       identifiers in parentheses): ARM Cortex-A32 (cortex-a32), ARM
+       Cortex-A35 (cortex-a35). The GCC identifiers can be used as
+       arguments to the -mcpu or -mtune options, for example:
+       -mcpu=cortex-a32 or -mtune=cortex-a35.
+
+  Heterogeneous Systems Architecture
+
+     * GCC can now generate HSAIL (Heterogeneous System Architecture
+       Intermediate Language) for simple OpenMP device constructs if
+       configured with --enable-offload-targets=hsa. A new libgomp plugin
+       then runs the HSA GPU kernels implementing these constructs on HSA
+       capable GPUs via a standard HSA run time.
+       If the HSA compilation back end determines it cannot output HSAIL
+       for a particular input, it gives a warning by default. These
+       warnings can be suppressed with -Wno-hsa. To give a few examples,
+       the HSA back end does not implement compilation of code using
+       function pointers, automatic allocation of variable sized arrays,
+       functions with variadic arguments as well as a number of other less
+       common programming constructs.
+       When compilation for HSA is enabled, the compiler attempts to
+       compile composite OpenMP constructs
+
+#pragma omp target teams distribute parallel for
+
+       into parallel HSA GPU kernels.
+
+  IA-32/x86-64
+
+     * GCC now supports the Intel CPU named Skylake with AVX-512
+       extensions through -march=skylake-avx512. The switch enables the
+       following ISA extensions: AVX-512F, AVX512VL, AVX-512CD, AVX-512BW,
+       AVX-512DQ.
+     * Support for new AMD instructions monitorx and mwaitx has been
+       added. This includes new intrinsic and built-in support. It is
+       enabled through option -mmwaitx. The instructions monitorx and
+       mwaitx implement the same functionality as the old monitor and
+       mwait instructions. In addition mwaitx adds a configurable timer.
+       The timer value is received as third argument and stored in
+       register %ebx.
+     * x86-64 targets now allow stack realignment from a word-aligned
+       stack pointer using the command-line option -mstackrealign or
+       __attribute__ ((force_align_arg_pointer)). This allows functions
+       compiled with a vector-aligned stack to be invoked from objects
+       that keep only word-alignment.
+     * Support for address spaces __seg_fs, __seg_gs, and __seg_tls. These
+       can be used to access data via the %fs and %gs segments without
+       having to resort to inline assembly. Please refer to the
+       [17]documentation for usage instructions.
+     * Support for AMD Zen (family 17h) processors is now available
+       through the -march=znver1 and -mtune=znver1 options.
+
+  MeP
+
+     * Support for the MeP (mep-elf) architecture has been deprecated and
+       will be removed in a future GCC release.
+
+  MSP430
+
+     * The MSP430 compiler now has the ability to automatically distribute
+       code and data between low memory (addresses below 64K) and high
+       memory. This only applies to parts that actually have both memory
+       regions and only if the linker script for the part has been
+       specifically set up to support this feature.
+       A new attribute of either can be applied to both functions and
+       data, and this tells the compiler to place the object into low
+       memory if there is room and into high memory otherwise. Two other
+       new attributes - lower and upper - can be used to explicitly state
+       that an object should be placed in the specified memory region. If
+       there is not enough left in that region the compilation will fail.
+       Two new command-line options - -mcode-region=[lower|upper|either]
+       and -mdata-region=[lower|upper|either] - can be used to tell the
+       compiler what to do with objects that do not have one of these new
+       attributes.
+
+  PowerPC / PowerPC64 / RS6000
+
+     * PowerPC64 now supports IEEE 128-bit floating-point using the
+       __float128 data type. In GCC 6, this is NOT enabled by default, but
+       you can enable it with -mfloat128. The IEEE 128-bit floating-point
+       support requires the use of the VSX instruction set. IEEE 128-bit
+       floating-point values are passed and returned as a single vector
+       value. The software emulator for IEEE 128-bit floating-point
+       support is only built on PowerPC Linux systems where the default
+       cpu is at least power7. On future ISA 3.0 systems (power9 and
+       later), you will be able to use the -mfloat128-hardware option to
+       use the ISA 3.0 instructions that support IEEE 128-bit
+       floating-point. An additional type (__ibm128) has been added to
+       refer to the IBM extended double type that normally implements long
+       double. This will allow for a future transition to implementing
+       long double with IEEE 128-bit floating-point.
+     * Basic support has been added for POWER9 hardware that will use the
+       recently published OpenPOWER ISA 3.0 instructions. The following
+       new switches are available:
+          + -mcpu=power9: Implement all of the ISA 3.0 instructions
+            supported by the compiler.
+          + -mtune=power9: In the future, apply tuning for POWER9 systems.
+            Currently, POWER8 tunings are used.
+          + -mmodulo: Generate code using the ISA 3.0 integer instructions
+            (modulus, count trailing zeros, array index support, integer
+            multiply/add).
+          + -mpower9-fusion: Generate code to suitably fuse instruction
+            sequences for a POWER9 system.
+          + -mpower9-dform: Generate code to use the new D-form (register
+            +offset) memory instructions for the vector registers.
+          + -mpower9-vector: Generate code using the new ISA 3.0 vector
+            (VSX or Altivec) instructions.
+          + -mpower9-minmax: Reserved for future development.
+          + -mtoc-fusion: Keep TOC entries together to provide more fusion
+            opportunities.
+     * New constraints have been added to support IEEE 128-bit
+       floating-point and ISA 3.0 instructions:
+          + wb: Altivec register if -mpower9-dform is enabled.
+          + we: VSX register if -mpower9-vector is enabled for 64-bit code
+            generation.
+          + wo: VSX register if -mpower9-vector is enabled.
+          + wp: Reserved for future use if long double is implemented with
+            IEEE 128-bit floating-point instead of IBM extended double.
+          + wq: VSX register if -mfloat128 is enabled.
+          + wF: Memory operand suitable for POWER9 fusion load/store.
+          + wG: Memory operand suitable for TOC fusion memory references.
+          + wL: Integer constant identifying the element number mfvsrld
+            accesses within a vector.
+     * Support has been added for __builtin_cpu_is () and
+       __builtin_cpu_supports (), allowing for very fast access to
+       AT_PLATFORM, AT_HWCAP, and AT_HWCAP2 values. This requires use of
+       glibc 2.23 or later.
+     * All hardware transactional memory builtins now correctly behave as
+       memory barriers. Programmers can use #ifdef __TM_FENCE__ to
+       determine whether their "old" compiler treats the builtins as
+       barriers.
+     * Split-stack support has been added for gccgo on PowerPC64 for both
+       big- and little-endian (but NOT for 32-bit). The gold linker from
+       at least binutils 2.25.1 must be available in the PATH when
+       configuring and building gccgo to enable split stack. (The
+       requirement for binutils 2.25.1 applies to PowerPC64 only.) The
+       split-stack feature allows a small initial stack size to be
+       allocated for each goroutine, which increases as needed.
+     * GCC on PowerPC now supports the standard lround function.
+     * A new configuration option ---with-advance-toolchain=at was added
+       for PowerPC 64-bit GNU/Linux systems to use the header files,
+       library files, and the dynamic linker from a specific Advance
+       Toolchain release instead of the default versions that are provided
+       by the GNU/Linux distribution. In general, this option is intended
+       for the developers of GCC, and it is not intended for general use.
+     * The "q", "S", "T", and "t" asm-constraints have been removed.
+     * The "b", "B", "m", "M", and "W" format modifiers have been removed.
+
+  S/390, System z, IBM z Systems
+
+     * Support for the IBM z13 processor has been added. When using the
+       -march=z13 option, the compiler will generate code making use of
+       the new instructions and registers introduced with the vector
+       extension facility. The -mtune=z13 option enables z13 specific
+       instruction scheduling without making use of new instructions.
+       Compiling code with -march=z13 reduces the default alignment of
+       vector types bigger than 8 bytes to 8. This is an ABI change and
+       care must be taken when linking modules compiled with different
+       arch levels which interchange variables containing vector type
+       values. For newly compiled code the GNU linker will emit a warning.
+     * The -mzvector option enables a C/C++ language extension. This
+       extension provides a new keyword vector which can be used to define
+       vector type variables. (Note: This is not available when enforcing
+       strict standard compliance e.g. with -std=c99. Either enable GNU
+       extensions with e.g. -std=gnu99 or use __vector instead of vector.)
+       Additionally a set of overloaded builtins is provided which is
+       partially compatible to the PowerPC Altivec builtins. In order to
+       make use of these builtins the vecintrin.h header file needs to be
+       included.
+     * The new command line options -march=native, and -mtune=native are
+       now available on native IBM z Systems. Specifying these options
+       will cause GCC to auto-detect the host CPU and rewrite these
+       options to the optimal setting for that system. If GCC is unable to
+       detect the host CPU these options have no effect.
+     * The IBM z Systems port now supports target attributes and pragmas.
+       Please refer to the [18]documentation for details of available
+       attributes and pragmas as well as usage instructions.
+     * -fsplit-stack is now supported as part of the IBM z Systems port.
+       This feature requires a recent gold linker to be used.
+     * Support for the g5 and g6 -march=/-mtune= CPU level switches has
+       been deprecated and will be removed in a future GCC release. -m31
+       from now on defaults to -march=z900 if not specified otherwise.
+       -march=native on a g5/g6 machine will default to -march=z900.
+
+  SH
+
+     * Support for SH5 / SH64 has been declared obsolete and will be
+       removed in future releases.
+     * Support for the FDPIC ABI has been added. It can be enabled using
+       the new -mfdpic target option and --enable-fdpic configure option.
+
+  SPARC
+
+     * An ABI bug has been fixed in 64-bit mode. Unfortunately, this
+       change will break binary compatibility with earlier releases for
+       code it affects, but this should be pretty rare in practice. The
+       conditions are: a 16-byte structure containing a double or a 8-byte
+       vector in the second half is passed to a subprogram in slot #15,
+       for example as 16th parameter if the first 15 ones have at most 8
+       bytes. The double or vector was wrongly passed in floating-point
+       register %d32 in lieu of on the stack as per the SPARC calling
+       conventions.
+
+Operating Systems
+
+  Linux
+
+     * Support for the [19]musl C library was added for the AArch64, ARM,
+       MicroBlaze, MIPS, MIPS64, PowerPC, PowerPC64, SH, i386, x32 and
+       x86_64 targets. It can be selected using the new -mmusl option in
+       case musl is not the default libc. GCC defaults to musl libc if it
+       is built with a target triplet matching the *-linux-musl* pattern.
+
+  RTEMS
+
+     * The RTEMS thread model implementation changed. Mutexes now use
+       self-contained objects defined in Newlib <sys/lock.h> instead of
+       Classic API semaphores. The keys for thread specific data and the
+       once function are directly defined via <pthread.h>. Self-contained
+       condition variables are provided via Newlib <sys/lock.h>. The RTEMS
+       thread model also supports C++11 threads.
+     * OpenMP support now uses self-contained objects provided by Newlib
+       <sys/lock.h> and offers a significantly better performance compared
+       to the POSIX configuration of libgomp. It is possible to configure
+       thread pools for each scheduler instance via the environment
+       variable GOMP_RTEMS_THREAD_POOLS.
+
+  AIX
+
+     * DWARF debugging support for AIX 7.1 has been enabled as an optional
+       debugging format. A more recent Technology Level (TL) and GCC built
+       with that level are required for full exploitation of DWARF
+       debugging capabilities.
+
+  Solaris
+
+     * Solaris 12 is now fully supported. Minimal support had already been
+       present in GCC 5.3.
+     * Solaris 12 provides a full set of startup files (crt1.o, crti.o,
+       crtn.o), which GCC now prefers over its own ones.
+     * Position independent executables (PIE) are now supported on Solaris
+       12.
+     * Constructor priority is now supported on Solaris 12 with the system
+       linker.
+     * libvtv has been ported to Solaris 11 and up.
+
+  Windows
+
+     * The option -mstackrealign is now automatically activated in 32-bit
+       mode whenever the use of SSE instructions is requested.
+
+Other significant improvements
+
+     * The gcc and g++ driver programs will now provide suggestions for
+       misspelled command line options.
+
+$ gcc -static-libfortran test.f95
+gcc: error: unrecognized command line option '-static-libfortran'; did you mean
+'-static-libgfortran'?
+
+     * The --enable-default-pie configure option enables generation of PIE
+       by default.
+
+
+    For questions related to the use of GCC, please consult these web
+    pages and the [20]GCC manuals. If that fails, the
+    [21]gcc-help@gcc.gnu.org mailing list might help. Comments on these
+    web pages and the development of GCC are welcome on our developer
+    list at [22]gcc@gcc.gnu.org. All of [23]our lists have public
+    archives.
+
+   Copyright (C) [24]Free Software Foundation, Inc. Verbatim copying and
+   distribution of this entire article is permitted in any medium,
+   provided this notice is preserved.
+
+   These pages are [25]maintained by the GCC team. Last modified
+   2016-04-25[26].
+
+References
+
+   1. http://gcc.gnu.org/gcc-6/porting_to.html
+   2. http://gcc.gnu.org/onlinedocs/index.html#current
+   3. https://gcc.gnu.org/ml/gcc/2015-08/msg00101.html
+   4. http://www.openacc.org/
+   5. https://gcc.gnu.org/wiki/OpenACC
+   6. https://gcc.gnu.org/wiki/Offloading
+   7. http://openmp.org/wp/openmp-specifications/
+   8. https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2014-1266
+   9. http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2015/n4377.pdf
+  10. https://gcc.gnu.org/projects/cxx-status.html#cxx1z.html
+  11. https://gcc.gnu.org/onlinedocs/jit/topics/performance.html
+  12. https://gcc.gnu.org/onlinedocs/jit/topics/functions.html#gcc_jit_block_end_with_switch
+  13. https://gcc.gnu.org/onlinedocs/jit/topics/contexts.html#gcc_jit_context_set_bool_allow_unreachable_blocks
+  14. https://gcc.gnu.org/onlinedocs/jit/topics/contexts.html#gcc_jit_context_add_command_line_option
+  15. https://gcc.gnu.org/onlinedocs/gcc/AArch64-Function-Attributes.html#AArch64-Function-Attributes
+  16. https://gcc.gnu.org/onlinedocs/gcc/ARM-Function-Attributes.html#ARM-Function-Attributes
+  17. https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html#Named-Address-Spaces
+  18. https://gcc.gnu.org/onlinedocs/gcc/S_002f390-Function-Attributes.html#S_002f390-Function-Attributes
+  19. http://www.musl-libc.org/
+  20. https://gcc.gnu.org/onlinedocs/
+  21. mailto:gcc-help@gcc.gnu.org
+  22. mailto:gcc@gcc.gnu.org
+  23. https://gcc.gnu.org/lists.html
+  24. http://www.fsf.org/
+  25. https://gcc.gnu.org/about.html
+  26. http://validator.w3.org/check/referer
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+  <!DOCTYPE html
+            PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+            "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+ 
+
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+ 
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+
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+     <html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
+  
+  
+   <head>
+ 
+    <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+    <link rev="made" href="mailto:gcc@gcc.gnu.org" />
+    <link rel="stylesheet" type="text/css" href="https://gcc.gnu.org/gcc.css" />
+  
+ <title>
+GCC 6 Release Series &mdash; Changes, New Features, and Fixes
+- GNU Project - Free Software Foundation (FSF)</title>
+   </head>
+ 
+
+<!-- GCC maintainers, please do not hesitate to update/contribute entries
+     concerning those part of GCC you maintain!  2002-03-23, Gerald.
+-->
+
+<body>
+
+
+
+<h1>GCC 6 Release Series<br />Changes, New Features, and Fixes</h1>
+
+<p>
+This page is a brief summary of some of the huge number of improvements in GCC 6.
+For more information, see the
+<a href="porting_to.html">Porting to GCC 6</a> page and the
+<a href="../onlinedocs/index.html#current">full GCC documentation</a>.
+</p>
+
+<!-- .................................................................. -->
+<h2>Caveats</h2>
+  <ul>
+    <li>The default mode for C++ is now <code>-std=gnu++14</code> instead of
+        <code>-std=gnu++98</code>.</li>
+
+    <li><p>Support for a number of older systems and recently
+    unmaintained or untested target ports of GCC has been declared
+    obsolete in GCC 6.  Unless there is activity to revive them, the
+    next release of GCC will have their sources permanently
+    <strong>removed</strong>.</p>
+
+    <p>The following ports for individual systems on
+    particular architectures have been obsoleted:</p>
+
+    <ul>
+	  <li>SH5 / SH64 (sh64-*-*) as announced
+	  <a href="https://gcc.gnu.org/ml/gcc/2015-08/msg00101.html">
+	      here</a>.</li>
+    </ul>
+    </li>
+
+  </ul>
+
+<!-- .................................................................. -->
+<h2 id="general">General Optimizer Improvements</h2>
+  <ul>
+    <li>UndefinedBehaviorSanitizer gained a new sanitization option,
+	<code>-fsanitize=bounds-strict</code>, which enables strict checking
+	of array bounds.  In particular, it enables
+	<code>-fsanitize=bounds</code> as well as instrumentation of
+	flexible array member-like arrays.</li>
+    <li>Type-based alias analysis now disambiguates accesses to different
+	pointers. This improves precision of the alias oracle by about 20-30%
+	on higher-level C++ programs. Programs doing invalid type punning
+	of pointer types may now need <code>-fno-strict-aliasing</code>
+	to work correctly.</li>
+    <li>Alias analysis now correctly supports <code>weakref</code> and
+	<code>alias</code> attributes. This makes it possible to access
+	both a variable and its alias in one translation unit which is common
+	with link-time optimization.</li>
+    <li>Value range propagation now assumes that the <code>this</code> pointer
+	of C++ member functions is non-null.  This eliminates
+	common null pointer checks
+	but also breaks some non-conforming code-bases (such as Qt-5, Chromium,
+	KDevelop). As a temporary work-around
+	<code>-fno-delete-null-pointer-checks</code> can be used. Wrong
+	code can be identified by using <code>-fsanitize=undefined</code>.</li>
+    <li>Link-time optimization improvements:
+    <ul>
+      <li><code>warning</code> and <code>error</code> attributes are now
+	  correctly preserved by declaration linking and thus
+	  <code>-D_FORTIFY_SOURCE=2</code> is now supported with <code>-flto</code>.</li>
+      <li><p>Type merging was fixed to handle C and Fortran interoperability
+	  rules as defined by the Fortran 2008 language standard.</p>
+	  <p>
+	  As an exception, <code>CHARACTER(KIND=C_CHAR)</code> is not inter-operable
+	  with <code>char</code> in all cases because it is an array while
+	  <code>char</code> is scalar.
+	  <code>INTEGER(KIND=C_SIGNED_CHAR)</code> should be used instead.
+	  In general, this inter-operability cannot be implemented, for
+	  example, on targets where function passing conventions of arrays
+	  differs from scalars.</p></li>
+      <li>More type information is now preserved at link time reducing
+	  the loss of accuracy of the type based alias analysis compared
+	  to builds without link-time optimization.</li>
+      <li>Invalid type punning on global variables and declarations is now
+	  reported with <code>-Wodr-type-mismatch</code>.</li>
+      <li>The size of LTO object files was reduced by about 11% (measured
+	  by compiling Firefox 46.0).</li>
+      <li>Link-time parallelization (enabled using <code>-flto=n</code>)
+	  was significantly improved by decreasing the size of streamed
+	  data when partitioning programs.  The size of streamed
+	  IL while compiling Firefox 46.0 was reduced by 66%.</li>
+      <li><p>The linker plugin was extended to pass information about type of
+	  binary produced to GCC back end (that can be also manually controlled
+	  by <code>-flinker-output</code>).  This makes it possible to
+	  properly configure the code generator and support incremental
+	  linking. Incremental linking of LTO objects by <code>gcc -r</code> is
+	  now supported on plugin-enabled setups.</p>
+	  <p>There are two ways to perform incremental linking:</p>
+	  <ol>
+	     <li>Linking by <code>ld -r</code> will result in an object file
+	     with all sections from individual object files mechanically merged.
+	     This delays the actual link time optimization to final linking step
+	     and thus permits whole program optimization.  Linking final binary
+	     with such object files is however slower.</li>
+	     <li>Linking by <code>gcc -r</code> will lead to link time optimization
+	     and produce final binary into the object file.  Linking such object
+	     file is fast but avoids any benefits from whole program optimization.</li>
+	  </ol>
+	  GCC 7 will support incremental link-time optimization with <code>gcc -r</code>.</li>
+    </ul></li>
+    <li>Inter-procedural optimization improvements:
+    <ul>
+      <li>Basic jump threading is now performed before profile construction
+	  and inline analysis, resulting in more realistic size and time estimates
+	  that drive the heuristics of the of inliner and function cloning passes.</li>
+      <li>Function cloning now more aggressively eliminates unused function
+	  parameters.</li>
+    </ul></li>
+  </ul>
+
+<!-- .................................................................. -->
+<h2 id="languages">New Languages and Language specific improvements</h2>
+
+<!-- <ul>
+  <li> -->Compared to GCC 5, the GCC 6 release series includes a much improved
+    implementation of the <a href="http://www.openacc.org/">OpenACC 2.0a
+      specification</a>.  Highlights are:
+    <ul>
+      <li>In addition to single-threaded host-fallback execution, offloading is
+	supported for nvptx (Nvidia GPUs) on x86_64 and PowerPC 64-bit
+	little-endian GNU/Linux host systems.  For nvptx offloading, with the
+	OpenACC parallel construct, the execution model allows for an arbitrary
+	number of gangs, up to 32 workers, and 32 vectors.</li>
+      <li>Initial support for parallelized execution of OpenACC kernels
+	constructs:
+	<ul>
+	  <li>Parallelization of a kernels region is switched on
+	    by <code>-fopenacc</code> combined with <code>-O2</code> or
+	    higher.</li>
+	  <li>Code is offloaded onto multiple gangs, but executes with just one
+	    worker, and a vector length of 1.</li>
+	  <li>Directives inside a kernels region are not supported.</li>
+	  <li>Loops with reductions can be parallelized.</li>
+	  <li>Only kernels regions with one loop nest are parallelized.</li>
+	  <li>Only the outer-most loop of a loop nest can be parallelized.</li>
+	  <li>Loop nests containing sibling loops are not parallelized.</li>
+	</ul>
+	Typically, using the OpenACC parallel construct gives much better
+	performance, compared to the initial support of the OpenACC kernels
+	construct.</li>
+      <li>The <code>device_type</code> clause is not supported.
+	The <code>bind</code> and <code>nohost</code> clauses are not
+	supported.  The <code>host_data</code> directive is not supported in
+	Fortran.</li>
+      <li>Nested parallelism (cf. CUDA dynamic parallelism) is not
+	supported.</li>
+      <li>Usage of OpenACC constructs inside multithreaded contexts (such as
+	created by OpenMP, or pthread programming) is not supported.</li>
+      <li>If a call to the <code>acc_on_device</code> function has a
+	compile-time constant argument, the function call evaluates to a
+	compile-time constant value only for C and C++ but not for
+	Fortran.</li>
+    </ul>
+    See the <a href="https://gcc.gnu.org/wiki/OpenACC">OpenACC</a>
+    and <a href="https://gcc.gnu.org/wiki/Offloading">Offloading</a> wiki pages
+    for further information.
+  <!-- </li>
+</ul> -->
+
+<!-- <h3 id="ada">Ada</h3> -->
+
+<h3 id="c-family">C family</h3>
+  <ul>
+    <li>Version 4.5 of the <a href="http://openmp.org/wp/openmp-specifications/"
+	>OpenMP specification</a> is now supported in the C and C++ compilers.</li>
+
+    <li>The C and C++ compilers now support attributes on enumerators.  For instance,
+	it is now possible to mark enumerators as deprecated:
+<blockquote><pre>
+enum {
+  newval,
+  oldval __attribute__ ((deprecated ("too old")))
+};
+</pre></blockquote></li>
+<li>Source locations for the C and C++ compilers are now tracked as ranges,
+  rather than just points, making it easier to identify the subexpression
+  of interest within a complicated expression.
+  For example:
+<blockquote><pre>
+<b>test.cc:</b> In function <b>'int test(int, int, foo, int, int)'</b>:
+<b>test.cc:5:16:</b> <span class="boldred">error:</span> no match for <b>'operator*'</b> (operand types are <b>'int'</b> and <b>'foo'</b>)
+   return p + <span class="boldred">q * r</span> * s + t;
+              <span class="boldred">~~^~~</span>
+</pre></blockquote>
+In addition, there is now initial support for precise diagnostic locations
+within strings:
+<blockquote><pre>
+<b>format-strings.c:3:14:</b> <span class="boldmagenta">warning:</span> field width specifier <b>'*'</b> expects a matching <b>'int'</b> argument [<span class="boldmagenta">-Wformat=</span>]
+   printf("%*d");
+            <span class="boldmagenta">^</span>
+</pre></blockquote></li>
+    <li>Diagnostics can now contain "fix-it hints", which are displayed
+      in context underneath the relevant source code.  For example:
+      <!-- this is currently the only example in the tree; various others are pending  -->
+<blockquote><pre>
+<b>fixits.c:</b> In function <b>'bad_deref'</b>:
+<b>fixits.c:11:13:</b> <span class="boldred">error:</span> <b>'ptr'</b> is a pointer; did you mean to use <b>'->'</b>?
+   return ptr<span class="boldred">.</span>x;
+             <span class="boldred">^</span>
+             <span class="boldred">-&gt;</span>
+</pre></blockquote></li>
+    <li>The C and C++ compilers now offer suggestions for misspelled field names:
+<blockquote><pre>
+<b>spellcheck-fields.cc:52:13:</b> <span class="boldred">error:</span> <b>'struct s'</b> has no member named <b>'colour'</b>; did you mean <b>'color'</b>?
+   return ptr-&gt;<span class="boldred">colour</span>;
+               <span class="boldred">^~~~~~</span>
+</pre></blockquote></li>
+    <!-- also, pending patch to add fix-it hints to the above -->
+    <li>New command-line options have been added for the C and C++ compilers:
+      <ul>
+        <li><code>-Wshift-negative-value</code> warns about left shifting a
+          negative value.</li>
+        <li><code>-Wshift-overflow</code> warns about left shift overflows.
+          This warning is enabled by default.
+          <code>-Wshift-overflow=2</code> also warns about left-shifting 1 into
+          the sign bit.</li>
+        <li><code>-Wtautological-compare</code> warns if a self-comparison
+          always evaluates to true or false.  This warning is enabled by
+          <code>-Wall</code>.</li>
+        <li><code>-Wnull-dereference</code> warns if the compiler detects paths
+          that trigger erroneous or undefined behavior due to dereferencing a
+          null pointer. This option is only active when
+          <code>-fdelete-null-pointer-checks</code> is active, which is enabled
+          by optimizations in most targets. The precision of the warnings
+          depends on the optimization options used.</li>
+        <li><code>-Wduplicated-cond</code> warns about duplicated conditions
+	  in an if-else-if chain.</li>
+        <li><code>-Wmisleading-indentation</code> warns about places where the
+          indentation of the code gives a misleading idea of the block
+          structure of the code to a human reader.  For example, given
+          <a href="https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2014-1266">CVE-2014-1266</a>:
+<blockquote><pre>
+<b>sslKeyExchange.c:</b> In function <b>'SSLVerifySignedServerKeyExchange'</b>:
+<b>sslKeyExchange.c:629:3:</b> <span class="boldmagenta">warning:</span> this <b>'if'</b> clause does not guard... [<span class="boldmagenta">-Wmisleading-indentation</span>]
+    <span class="boldcyan">if</span> ((err = SSLHashSHA1.update(&amp;hashCtx, &amp;signedParams)) != 0)
+    <span class="boldcyan">^~</span>
+<b>sslKeyExchange.c:631:5:</b> <span class="boldcyan">note:</span> ...this statement, but the latter is misleadingly indented as if it is guarded by the <b>'if'</b>
+        <span class="boldmagenta">goto</span> fail;
+        <span class="boldmagenta">^~~~</span>
+</pre></blockquote>
+          This warning is enabled by <code>-Wall</code>.</li>
+      </ul>
+    </li>
+    <li>The C and C++ compilers now emit saner error messages if
+      merge-conflict markers are present in a source file.
+<blockquote><pre>
+<b>test.c:3:1:</b> <span class="boldred">error:</span> version control conflict marker in file
+ <span class="boldred">&lt;&lt;&lt;&lt;&lt;&lt;&lt;</span> HEAD
+ <span class="boldred">^~~~~~~</span>
+</pre></blockquote></li>
+  </ul>
+
+<h3 id="c">C</h3>
+  <ul>
+    <li>It is possible to disable warnings when an initialized field of
+	a structure or a union with side effects is being overridden when
+	using designated initializers via a new warning option
+	<code>-Woverride-init-side-effects</code>.</li>
+   <li>A new type attribute <code>scalar_storage_order</code> applying to
+       structures and unions has been introduced.  It specifies the storage
+       order (aka endianness) in memory of scalar fields in structures
+       or unions.</li>
+  </ul>
+
+<h3 id="cxx">C++</h3>
+  <ul>
+    <li>The default mode has been changed to <code>-std=gnu++14</code>.</li>
+    <li><a href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2015/n4377.pdf">C++
+	Concepts</a> are now supported when compiling with
+        <code>-fconcepts</code>.</li>
+    <li><code>-flifetime-dse</code> is more
+    aggressive in dead-store elimination in situations where
+    a memory store to a location precedes a constructor to the
+    memory location.</li>
+    <li>G++ now supports
+        <a href="https://gcc.gnu.org/projects/cxx-status.html#cxx1z.html">C++17</a>
+        fold expressions, <code>u8</code> character literals,
+        extended <code>static_assert</code>, and nested namespace definitions.</li>
+    <li>G++ now allows constant evaluation for all non-type template arguments.</li>
+    <li>G++ now supports C++ Transactional Memory when compiling with
+        <code>-fgnu-tm</code>. </li>
+  </ul>
+
+<h4 id="libstdcxx">Runtime Library (libstdc++)</h4>
+  <ul>
+    <li>Extensions to the C++ Library to support mathematical special
+        functions (ISO/IEC 29124:2010), thanks to Edward Smith-Rowland. </li>
+    <li>Experimental support for C++17, including the following
+      new features:
+      <ul>
+        <li><code>std::uncaught_exceptions</code> function (this is also
+            available for <tt>-std=gnu++NN</tt> modes); </li>
+        <li>new member functions <code>try_emplace</code> and
+            <code>insert_or_assign</code> for unique_key maps;</li>
+        <li>non-member functions <code>std::size</code>,
+            <code>std::empty</code>, and <code>std::data</code> for
+            accessing containers and arrays;</li>
+        <li><code>std::invoke</code>;</li>
+        <li><code>std::shared_mutex</code>;</li>
+        <li><code>std::void_t</code> and <code>std::bool_constant</code>
+            metaprogramming utilities. </li>
+      </ul>
+      Thanks to Ville Voutilainen for contributing many of the C++17 features.
+    </li>
+    <li>An experimental implementation of the File System TS.</li>
+    <li>Experimental support for most features of the second version of the
+        Library Fundamentals TS. This includes polymorphic memory resources
+        and array support in <code>shared_ptr</code>, thanks to Fan You.</li>
+    <li>Some assertions checked by Debug Mode can now also be enabled by
+        <code>_GLIBCXX_ASSERTIONS</code>. The subset of checks enabled by
+        the new macro have less run-time overhead than the full
+        <code>_GLIBCXX_DEBUG</code> checks and don't affect the library
+        ABI, so can be enabled per-translation unit.
+    </li>
+    <li>Timed mutex types are supported on more targets, including Darwin.
+    </li>
+    <li>Improved <code>std::locale</code> support for DragonFly and FreeBSD,
+        thanks to John Marino and Andreas Tobler.
+    </li>
+  </ul>
+
+
+<h3 id="fortran">Fortran</h3>
+  <ul>
+    <li>The <code>MATMUL</code> intrinsic is now inlined for straightforward
+      cases if front-end optimization is active.  The maximum size for
+      inlining can be set to <code>n</code> with the
+      <code>-finline-matmul-limit=n</code> option and turned off
+      with <code>-finline-matmul-llimit=0</code>.</li>
+    <li>The <code>-Wconversion-extra</code> option will warn about
+      <code>REAL</code> constants which have excess precision for
+      their kind.</li>
+    <li>The <code>-Winteger-division</code> option has been added, which
+      warns about divisions of integer constants which are truncated.
+      This option is included in <code>-Wall</code> by default.</li>
+  </ul>
+
+<!-- <h3 id="go">Go</h3> -->
+
+<!-- <h3 id="java">Java (GCJ)</h3> -->
+
+
+<!-- .................................................................. -->
+<h2 id="jit">libgccjit</h2>
+  <ul>
+    <li>The driver code is now run in-process within libgccjit,
+      providing a small speed-up of the compilation process.</li>
+    <li>The API has gained entrypoints for
+      <ul>
+        <li><a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/jit/topics/performance.html">timing how long was spent in different parts of code</a>,</li>
+        <li><a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/jit/topics/functions.html#gcc_jit_block_end_with_switch">creating switch statements</a>,</li>
+        <li><a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/jit/topics/contexts.html#gcc_jit_context_set_bool_allow_unreachable_blocks">allowing unreachable basic blocks in a function</a>, and</li>
+        <li><a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/jit/topics/contexts.html#gcc_jit_context_add_command_line_option">adding arbitrary command-line options to a compilation</a>.</li>
+      </ul>
+    </li>
+  </ul>
+
+<!-- .................................................................. -->
+<h2 id="targets">New Targets and Target Specific Improvements</h2>
+
+<h3 id="aarch64">AArch64</h3>
+   <ul>
+     <li>
+       The new command line options <code>-march=native</code>,
+       <code>-mcpu=native</code> and <code>-mtune=native</code> are now
+       available on native AArch64 GNU/Linux systems.  Specifying
+       these options will cause GCC to auto-detect the host CPU and
+       rewrite these options to the optimal setting for that system.
+       If GCC is unable to detect the host CPU these options have no effect.
+     </li>
+     <li>
+       <code>-fpic</code> is now supported by the AArch64 target when generating
+       code for the small code model (<code>-mcmodel=small</code>).  The size of
+       the global offset table (GOT) is limited to 28KiB under the LP64 SysV ABI
+       , and 15KiB under the ILP32 SysV ABI.
+     </li>
+     <li>
+       The AArch64 port now supports target attributes and pragmas.  Please
+       refer to the <a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/gcc/AArch64-Function-Attributes.html#AArch64-Function-Attributes">
+       documentation</a> for details of available attributes and
+       pragmas as well as usage instructions.
+     </li>
+     <li>
+       Link-time optimization across translation units with different
+       target-specific options is now supported.
+     </li>
+   </ul>
+
+<h3 id="arm">ARM</h3>
+   <ul>
+     <li>
+       Support for revisions of the ARM architecture prior to ARMv4t has
+       been deprecated and will be removed in a future GCC release.
+       The <code>-mcpu</code> and <code>-mtune</code> values that are
+       deprecated are:
+       <code>arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7,
+       arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720, arm710c,
+       arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dmi, arm8, arm810,
+       strongarm, strongarm110, strongarm1100, strongarm1110, fa526,
+       fa626</code>.  The value
+       <code>arm7tdmi</code> is still supported.
+       The values of <code>-march</code> that are deprecated are:
+       <code>armv2,armv2a,armv3,armv3m,armv4</code>.
+     </li>
+     <li>
+       The ARM port now supports target attributes and pragmas.  Please
+       refer to the <a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/gcc/ARM-Function-Attributes.html#ARM-Function-Attributes">
+       documentation</a> for details of available attributes and
+       pragmas as well as usage instructions.
+     </li>
+     <li>
+       Support has been added for the following processors
+       (GCC identifiers in parentheses): ARM Cortex-A32
+       (<code>cortex-a32</code>), ARM Cortex-A35 (<code>cortex-a35</code>).
+       The GCC identifiers can be used
+       as arguments to the <code>-mcpu</code> or <code>-mtune</code> options,
+       for example: <code>-mcpu=cortex-a32</code> or
+       <code>-mtune=cortex-a35</code>.
+     </li>
+   </ul>
+<!-- <h3 id="avr">AVR</h3> -->
+
+<h3 id="hsa">Heterogeneous Systems Architecture</h3>
+   <ul>
+     <li><p>GCC can now generate HSAIL (Heterogeneous System Architecture
+       Intermediate Language) for simple OpenMP device constructs if
+       configured with <code>--enable-offload-targets=hsa</code>.  A new
+       libgomp plugin then runs the HSA GPU kernels implementing these
+       constructs on HSA capable GPUs via a standard HSA run time.</p>
+       
+       <p>If the HSA compilation back end determines it cannot output HSAIL
+       for a particular input, it gives a warning by default.  These
+       warnings can be suppressed with <code>-Wno-hsa</code>.  To give a few
+       examples, the HSA back end does not implement compilation of code
+       using function pointers, automatic allocation of variable sized
+       arrays, functions with variadic arguments as well as a number of
+       other less common programming constructs.</p>
+
+       <p>When compilation for HSA is enabled, the compiler attempts to
+       compile composite OpenMP constructs</p>
+	 <blockquote><pre>
+#pragma omp target teams distribute parallel for</pre></blockquote>
+       <p>into parallel HSA GPU kernels.</p>
+     </li>
+   </ul>
+
+<h3 id="x86">IA-32/x86-64</h3>
+   <ul>
+     <li>GCC now supports the Intel CPU named Skylake with AVX-512 extensions
+      through <code>-march=skylake-avx512</code>. The switch enables the following
+      ISA extensions: AVX-512F, AVX512VL, AVX-512CD, AVX-512BW, AVX-512DQ.
+     </li>
+     <li>
+       Support for new AMD instructions <code>monitorx</code> and
+       <code>mwaitx</code> has been added. This includes new intrinsic
+       and built-in support. It is enabled through option <code>-mmwaitx</code>.
+       The instructions <code>monitorx</code> and <code>mwaitx</code>
+       implement the same functionality as the old <code>monitor</code>
+       and <code>mwait</code> instructions. In addition <code>mwaitx</code>
+       adds a configurable timer. The timer value is received as third
+       argument and stored in register <code>%ebx</code>.
+     </li>
+     <li>
+       x86-64 targets now allow stack realignment from a word-aligned stack
+       pointer using the command-line option <code>-mstackrealign</code> or
+       <code>__attribute__ ((force_align_arg_pointer))</code>.  This allows
+       functions compiled with a vector-aligned stack to be invoked from
+       objects that keep only word-alignment.
+     </li>
+     <li>
+       Support for address spaces <code>__seg_fs</code>, <code>__seg_gs</code>,
+       and <code>__seg_tls</code>.  These can be used to access data via the
+       <code>%fs</code> and <code>%gs</code> segments without having to
+       resort to inline assembly.
+       Please refer to the <a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/gcc/Named-Address-Spaces.html#Named-Address-Spaces">
+       documentation</a> for usage instructions.
+     </li>
+     <li>
+      Support for AMD Zen (family 17h) processors is now available through
+      the <code>-march=znver1</code> and <code>-mtune=znver1</code> options.
+     </li>
+   </ul>
+<!-- <h3 id="mips">MIPS</h3> -->
+
+<h3 id="mep">MeP</h3>
+  <ul>
+    <li><p>Support for the MeP (mep-elf) architecture has been
+      deprecated and will be removed in a future GCC release.</p>
+    </li>
+  </ul>
+
+<h3 id="msp430">MSP430</h3>
+  <ul>
+    <li><p>The MSP430 compiler now has the ability to automatically distribute code
+      and data between low memory (addresses below 64K) and high memory.  This only
+      applies to parts that actually have both memory regions and only if the
+      linker script for the part has been specifically set up to support this
+      feature.</p>
+
+      <p>A new attribute of <code>either</code> can be applied to both functions
+      and data, and this tells the compiler to place the object into low memory
+      if there is room and into high memory otherwise.  Two other new attributes
+      - <code>lower</code> and <code>upper</code> - can be used to explicitly
+      state that an object should be placed in the specified memory region.  If
+      there is not enough left in that region the compilation will fail.</p>
+
+      <p>Two new command-line options - <code>-mcode-region=[lower|upper|either]</code>
+      and <code>-mdata-region=[lower|upper|either]</code> - can be used to tell
+      the compiler what to do with objects that do not have one of these new
+      attributes.</p></li>
+  </ul>
+
+<!-- <h3 id="nds32">NDS32</h3> -->
+
+<h3 id="powerpc">PowerPC / PowerPC64 / RS6000</h3>
+  <ul>
+    <li><p>PowerPC64 now supports IEEE 128-bit floating-point using the
+	__float128 data type.  In GCC 6, this is NOT enabled by default,
+	but you can enable it with -mfloat128.  The IEEE 128-bit
+	floating-point support requires the use of the VSX instruction
+	set.  IEEE 128-bit floating-point values are passed and returned
+	as a single vector value.  The software emulator for IEEE 128-bit
+	floating-point support is only built on PowerPC Linux systems
+	where the default cpu is at least power7.  On future ISA 3.0
+	systems (power9 and later), you will be able to use the
+	-mfloat128-hardware option to use the ISA 3.0 instructions
+	that support IEEE 128-bit floating-point.  An additional type
+	(__ibm128) has been added to refer to the IBM extended double
+	type that normally implements long double.  This will allow
+	for a future transition to implementing long double with IEEE
+	128-bit floating-point.</p></li>
+    <li><p>Basic support has been added for POWER9 hardware that will use the
+	recently published OpenPOWER ISA 3.0 instructions.  The following
+	new switches are available:</p>
+	<ul>
+	  <li><p><u>-mcpu=power9</u>:  Implement all of the ISA 3.0
+	      instructions supported by the compiler.</p></li>
+	  <li><p><u>-mtune=power9</u>:  In the future, apply tuning for
+	      POWER9 systems.  Currently, POWER8 tunings are used.</p></li>
+	  <li><p><u>-mmodulo</u>:  Generate code using the ISA 3.0
+	      integer instructions (modulus, count trailing zeros, array
+	      index support, integer multiply/add).</p></li>
+	  <li><p><u>-mpower9-fusion</u>:  Generate code to suitably fuse
+	      instruction sequences for a POWER9 system.</p></li>
+	  <li><p><u>-mpower9-dform</u>:  Generate code to use the new D-form
+	      (register +offset) memory instructions for the vector
+	      registers.</p></li>
+	  <li><p><u>-mpower9-vector</u>:  Generate code using the new ISA
+	      3.0 vector (VSX or Altivec) instructions.</p></li>
+	  <li><p><u>-mpower9-minmax</u>:  Reserved for future development.
+	  </p></li>
+	  <li><p><u>-mtoc-fusion</u>:  Keep TOC entries together to provide
+	      more fusion opportunities.</p></li>
+	</ul></li>
+    <li><p>New constraints have been added to support IEEE 128-bit
+	floating-point and ISA 3.0 instructions:</p>
+	<ul>
+	  <li><p><u>wb</u>:  Altivec register if -mpower9-dform is
+	      enabled.</p></li>
+	  <li><p><u>we</u>:  VSX register if -mpower9-vector is enabled
+	      for 64-bit code generation.</p></li>
+	  <li><p><u>wo</u>:  VSX register if -mpower9-vector is
+	      enabled.</p></li>
+	  <li><p><u>wp</u>:  Reserved for future use if long double
+	      is implemented with IEEE 128-bit floating-point instead
+	      of IBM extended double.</p></li>
+	  <li><p><u>wq</u>:  VSX register if -mfloat128 is enabled.</p></li>
+	  <li><p><u>wF</u>:  Memory operand suitable for POWER9 fusion
+	      load/store.</p></li>
+	  <li><p><u>wG</u>:  Memory operand suitable for TOC fusion memory
+	      references.</p></li>
+	  <li><p><u>wL</u>:  Integer constant identifying the element
+	      number mfvsrld accesses within a vector.</p></li>
+	</ul></li>
+    <li><p>Support has been added for __builtin_cpu_is () and
+	__builtin_cpu_supports (), allowing for very fast access to
+	AT_PLATFORM, AT_HWCAP, and AT_HWCAP2 values.  This requires
+	use of glibc 2.23 or later.</p></li>
+    <li><p>All hardware transactional memory builtins now correctly
+	behave as memory barriers.  Programmers can use #ifdef __TM_FENCE__
+	to determine whether their "old" compiler treats the builtins
+	as barriers.</p></li>
+    <li><p>Split-stack support has been added for gccgo on PowerPC64
+	for both big- and little-endian (but NOT for 32-bit).  The gold
+	linker from at least binutils 2.25.1 must be available in the PATH
+	when configuring and building gccgo to enable split stack.  (The
+	requirement for binutils 2.25.1 applies to PowerPC64 only.)  The
+	split-stack feature allows a small initial stack size to be
+	allocated for each goroutine, which increases as needed.</p></li>
+    <li><p>GCC on PowerPC now supports the standard lround function.</p></li>
+    <li><p>A new configuration option -<code>--with-advance-toolchain=at</code>
+    was added for PowerPC 64-bit GNU/Linux systems to use the header files, library
+    files, and the dynamic linker from a specific Advance Toolchain release
+    instead of the default versions that are provided by the GNU/Linux
+    distribution.  In general, this option is intended for the developers of
+    GCC, and it is not intended for general use.</p></li>
+    <li><p>The "q", "S", "T", and "t" asm-constraints have been
+    removed.</p></li>
+    <li><p>The "b", "B", "m", "M", and "W" format modifiers have
+    been removed.</p></li>
+  </ul>
+
+<h3 id="s390">S/390, System z, IBM z Systems</h3>
+  <ul>
+    <li>Support for the IBM z13 processor has been added.  When using
+      the <code>-march=z13</code> option, the compiler will generate
+      code making use of the new instructions and registers introduced
+      with the vector extension facility.  The <code>-mtune=z13</code>
+      option enables z13 specific instruction scheduling without
+      making use of new instructions.<br/>
+
+      Compiling code with <code>-march=z13</code> reduces the default
+      alignment of vector types bigger than 8 bytes to 8.  This is an
+      ABI change and care must be taken when linking modules compiled
+      with different arch levels which interchange variables
+      containing vector type values.  For newly compiled code the GNU
+      linker will emit a warning.</li>
+
+    <li>The <code>-mzvector</code> option enables a C/C++ language
+      extension.  This extension provides a new
+      keyword <code>vector</code> which can be used to define vector
+      type variables.  (Note: This is not available when
+      enforcing strict standard compliance
+      e.g. with <code>-std=c99</code>.  Either enable GNU extensions
+      with e.g. <code>-std=gnu99</code> or use
+      <code>__vector</code> instead of <code>vector</code>.)<br/>
+
+      Additionally a set of overloaded builtins is provided which is
+      partially compatible to the PowerPC Altivec builtins.  In order
+      to make use of these builtins the <code>vecintrin.h</code>
+      header file needs to be included.</li>
+
+    <li>The new command line options <code>-march=native</code>,
+      and <code>-mtune=native</code> are now available on native IBM
+      z Systems.  Specifying these options will cause GCC to
+      auto-detect the host CPU and rewrite these options to the
+      optimal setting for that system.  If GCC is unable to detect
+      the host CPU these options have no effect.</li>
+
+    <li>The IBM z Systems port now supports target attributes and
+      pragmas.  Please refer to the
+      <a href="https://gcc.gnu.org/onlinedocs/gcc-6.1.0/gcc/S_002f390-Function-Attributes.html#S_002f390-Function-Attributes">
+	documentation</a> for details of available attributes and
+      pragmas as well as usage instructions.
+    </li>
+
+    <li><code>-fsplit-stack</code> is now supported as part of the IBM
+      z Systems port.  This feature requires a recent gold linker to
+      be used.</li>
+
+    <li>Support for the <code>g5</code> and <code>g6
+      -march=/-mtune=</code> CPU level switches has been deprecated
+      and will be removed in a future GCC release. <code>-m31</code>
+      from now on defaults to <code>-march=z900</code> if not
+      specified otherwise.  <code>-march=native</code> on a g5/g6
+      machine will default to <code>-march=z900</code>.</li>
+  </ul>
+
+<!-- <h3 id="rx">RX</h3> -->
+
+<h3 id="sh">SH</h3>
+  <ul>
+    <li>Support for SH5 / SH64 has been declared obsolete and will be removed
+    in future releases.</li>
+
+    <li>Support for the FDPIC ABI has been added.  It can be enabled using the
+    new <code>-mfdpic</code> target option and <code>--enable-fdpic</code>
+    configure option.</li>
+  </ul>
+
+<h3 id="sparc">SPARC</h3>
+  <ul>
+    <li>An ABI bug has been fixed in 64-bit mode.  Unfortunately, this change
+    will break binary compatibility with earlier releases for code it affects,
+    but this should be pretty rare in practice.  The conditions are: a 16-byte
+    structure containing a <code>double</code> or a 8-byte vector in the second
+    half is passed to a subprogram in slot #15, for example as 16th parameter
+    if the first 15 ones have at most 8 bytes.  The <code>double</code> or
+    vector was wrongly passed in floating-point register <code>%d32</code>
+    in lieu of on the stack as per the SPARC calling conventions.</li>
+  </ul>
+
+<!-- .................................................................. -->
+<h2 id="os">Operating Systems</h2>
+
+<!-- <h3 id="dragonfly">DragonFly BSD</h3> -->
+
+<!-- <h3 id="freebsd">FreeBSD</h3> -->
+
+<h3 id="linux">Linux</h3>
+  <ul>
+    <li>Support for the <a href="http://www.musl-libc.org">musl C library</a>
+    was added for the AArch64, ARM, MicroBlaze, MIPS, MIPS64, PowerPC,
+    PowerPC64, SH, i386, x32 and x86_64 targets.  It can be selected using the
+    new <code>-mmusl</code> option in case musl is not the default libc.  GCC
+    defaults to musl libc if it is built with a target triplet matching the
+    <code>*-linux-musl*</code> pattern.</li>
+  </ul>
+
+<h3 id="rtems">RTEMS</h3>
+  <ul>
+    <li>The RTEMS thread model implementation changed.  Mutexes now
+    use self-contained objects defined in Newlib &lt;sys/lock.h&gt;
+    instead of Classic API semaphores.  The keys for thread specific data and
+    the <code>once</code> function are directly defined via &lt;pthread.h&gt;.
+    Self-contained condition variables are provided via Newlib
+    &lt;sys/lock.h&gt;.  The RTEMS thread model also supports C++11
+    threads.</li>
+
+    <li>OpenMP support now uses self-contained objects provided by Newlib
+    &lt;sys/lock.h&gt; and offers a significantly better performance compared
+    to the POSIX configuration of <code>libgomp</code>.  It is possible to
+    configure thread pools for each scheduler instance via the environment
+    variable <code>GOMP_RTEMS_THREAD_POOLS</code>.</li>
+  </ul>
+
+<h3 id="aix">AIX</h3>
+  <ul>
+    <li>DWARF debugging support for AIX 7.1 has been enabled as an optional
+    debugging format.  A more recent Technology Level (TL) and GCC built
+    with that level are required for full exploitation of DWARF debugging
+    capabilities.</li>
+  </ul>
+
+<h3 id="solaris">Solaris</h3>
+  <ul>
+    <li>Solaris 12 is now fully supported.  Minimal support had already
+      been present in GCC 5.3.</li>
+    <li>Solaris 12 provides a full set of startup files (<code>crt1.o</code>,
+      <code>crti.o</code>, <code>crtn.o</code>), which GCC now prefers over
+      its own ones.</li>
+    <li>Position independent executables (PIE) are now supported on
+      Solaris 12.</li>
+    <li>Constructor priority is now supported on Solaris 12 with the system
+      linker.</li>
+    <li><code>libvtv</code> has been ported to Solaris 11 and up.</li>
+  </ul>
+
+<h3 id="windows">Windows</h3>
+  <ul>
+   <li>The option <code>-mstackrealign</code> is now automatically activated
+   in 32-bit mode whenever the use of SSE instructions is requested.</li>
+  </ul>
+<!-- <h3 id="vxmils">VxWorks MILS</h3> -->
+
+
+<!-- .................................................................. -->
+<!-- <h2>Documentation improvements</h2> -->
+
+
+<!-- .................................................................. -->
+<h2>Other significant improvements</h2>
+
+  <ul>
+    <li>The <code>gcc</code> and <code>g++</code> driver programs will now
+      provide suggestions for misspelled command line options.
+<blockquote><pre>
+$ gcc -static-libfortran test.f95
+gcc: <span class="boldred">error:</span> unrecognized command line option <b>'-static-libfortran'</b>; did you mean <b>'-static-libgfortran'</b>?
+</pre></blockquote></li>
+    <li>The <code>--enable-default-pie</code> configure option enables
+	generation of PIE by default.</li>
+  </ul>
+
+
+
+
+<!-- ==================================================================== -->
+
+<div class="copyright">
+
+<address>For questions related to the use of GCC,
+please consult these web pages and the
+<a href="https://gcc.gnu.org/onlinedocs/">GCC manuals</a>. If that fails,
+the <a href="mailto:gcc-help@gcc.gnu.org">gcc-help@gcc.gnu.org</a>
+mailing list might help.
+Comments on these web pages and the development of GCC are welcome on our
+developer list at <a href="mailto:gcc@gcc.gnu.org">gcc@gcc.gnu.org</a>.
+All of <a href="https://gcc.gnu.org/lists.html">our lists</a>
+have public archives.
+</address>
+
+<p>Copyright (C)
+<a href="http://www.fsf.org">Free Software Foundation, Inc.</a>
+Verbatim copying and distribution of this entire article is
+permitted in any medium, provided this notice is preserved.</p>
+
+<p>These pages are
+<a href="https://gcc.gnu.org/about.html">maintained by the GCC team</a>.
+Last modified 2016-04-27<!-- IGNORE DIFF
+--><a href="http://validator.w3.org/check/referer">.</a></p>
+
+</div>
+
+<!-- ==================================================================== -->
+
+</body>
+     </html>
+  
+ 
--- gcc-6-6.4.0.orig/debian/README.Bugs.m4
+++ gcc-6-6.4.0/debian/README.Bugs.m4
@@ -0,0 +1,333 @@
+Reporting Bugs in the GNU Compiler Collection for DIST
+========================================================
+
+Before reporting a bug, please
+------------------------------
+
+- Check that the behaviour really is a bug. Have a look into some
+  ANSI standards document.
+
+- Check the list of well known bugs: http://gcc.gnu.org/bugs.html#known
+
+- Try to reproduce the bug with a current GCC development snapshot. You
+  usually can get a recent development snapshot from the gcc-snapshot
+ifelse(DIST,`Debian',`dnl
+  package in the unstable (or experimental) distribution.
+
+  See: http://packages.debian.org/gcc-snapshot
+', DIST, `Ubuntu',`dnl
+  package in the current development distribution.
+
+  See: http://archive.ubuntu.com/ubuntu/pool/universe/g/gcc-snapshot/
+')dnl
+
+- Try to find out if the bug is a regression (an older GCC version does
+  not show the bug).
+
+- Check if the bug is already reported in the bug tracking systems.
+
+ifelse(DIST,`Debian',`dnl
+    Debian:   http://bugs.debian.org/debian-gcc@lists.debian.org
+', DIST, `Ubuntu',`dnl
+    Ubuntu:   https://bugs.launchpad.net/~ubuntu-toolchain/+packagebugs
+    Debian:   http://bugs.debian.org/debian-gcc@lists.debian.org
+')dnl
+    Upstream: http://gcc.gnu.org/bugzilla/
+
+
+Where to report a bug
+---------------------
+
+ifelse(DIST,`Debian',`dnl
+Please report bugs found in the packaging of GCC to the Debian bug tracking
+system. See http://www.debian.org/Bugs/ for instructions (or use the
+reportbug script).
+', DIST, `Ubuntu',`dnl
+Please report bugs found in the packaging of GCC to Launchpad. See below
+how issues should be reported.
+')dnl
+
+DIST's current policy is to closely follow the upstream development and
+only apply a minimal set of patches (which are summarized in the README.Debian
+document).
+
+ifelse(DIST,`Debian',`dnl
+If you think you have found an upstream bug, you did check the section
+above ("Before reporting a bug") and are able to provide a complete bug
+report (see below "How to report a bug"), then you may help the Debian
+GCC package maintainers, if you report the bug upstream and then submit
+a bug report to the Debian BTS and tell us the upstream report number.
+This way you are able to follow the upstream bug handling as well. If in
+doubt, report the bug to the Debian BTS (but read "How to report a bug"
+below).
+', DIST, `Ubuntu',`dnl
+If you think you have found an upstream bug, you did check the section
+above ("Before reporting a bug") and are able to provide a complete bug
+report (see below "How to report a bug"), then you may help the Ubuntu
+GCC package maintainers, if you report the bug upstream and then submit
+a bug report to Launchpad and tell us the upstream report number.
+This way you are able to follow the upstream bug handling as well. If in
+doubt, report the bug to Launchpad (but read "How to report a bug" below).
+
+Report the issue to https://bugs.launchpad.net/ubuntu/+source/SRCNAME.
+')dnl
+
+
+How to report a bug
+-------------------
+
+There are complete instructions in the gcc info manual (found in the
+gcc-doc package), section Bugs.
+
+The manual can be read using `M-x info' in Emacs, or if the GNU info
+program is installed on your system by `info --node "(gcc)Bugs"'. Or see
+the file BUGS included with the gcc source code.
+
+Online bug reporting instructions can be found at
+
+	http://gcc.gnu.org/bugs.html
+
+[Some paragraphs taken from the above URL]
+
+The main purpose of a bug report is to enable us to fix the bug. The
+most important prerequisite for this is that the report must be
+complete and self-contained, which we explain in detail below.
+
+Before you report a bug, please check the list of well-known bugs and,
+if possible in any way, try a current development snapshot.
+
+Summarized bug reporting instructions
+-------------------------------------
+
+What we need
+
+Please include in your bug report all of the following items, the
+first three of which can be obtained from the output of gcc -v:
+
+    * the exact version of GCC;
+    * the system type;
+    * the options given when GCC was configured/built;
+    * the complete command line that triggers the bug;
+    * the compiler output (error messages, warnings, etc.); and
+    * the preprocessed file (*.i*) that triggers the bug, generated by
+      adding -save-temps to the complete compilation command, or, in
+      the case of a bug report for the GNAT front end, a complete set
+      of source files (see below).
+
+What we do not want
+
+    * A source file that #includes header files that are left out
+      of the bug report (see above)
+    * That source file and a collection of header files.
+    * An attached archive (tar, zip, shar, whatever) containing all
+      (or some :-) of the above.
+    * A code snippet that won't cause the compiler to produce the
+      exact output mentioned in the bug report (e.g., a snippet with
+      just a few lines around the one that apparently triggers the
+      bug, with some pieces replaced with ellipses or comments for
+      extra obfuscation :-)
+    * The location (URL) of the package that failed to build (we won't
+      download it, anyway, since you've already given us what we need
+      to duplicate the bug, haven't you? :-)
+    * An error that occurs only some of the times a certain file is
+      compiled, such that retrying a sufficient number of times
+      results in a successful compilation; this is a symptom of a
+      hardware problem, not of a compiler bug (sorry)
+    * E-mail messages that complement previous, incomplete bug
+      reports. Post a new, self-contained, full bug report instead, if
+      possible as a follow-up to the original bug report
+    * Assembly files (*.s) produced by the compiler, or any binary files,
+      such as object files, executables, core files, or precompiled
+      header files
+    * Duplicate bug reports, or reports of bugs already fixed in the
+      development tree, especially those that have already been
+      reported as fixed last week :-)
+    * Bugs in the assembler, the linker or the C library. These are
+      separate projects, with separate mailing lists and different bug
+      reporting procedures
+    * Bugs in releases or snapshots of GCC not issued by the GNU
+      Project. Report them to whoever provided you with the release
+    * Questions about the correctness or the expected behavior of
+      certain constructs that are not GCC extensions. Ask them in
+      forums dedicated to the discussion of the programming language
+
+
+Known Bugs and Non-Bugs
+-----------------------
+
+[Please see /usr/share/doc/gcc/FAQ or http://gcc.gnu.org/faq.html first]
+
+
+C++ exceptions don't work with C libraries
+------------------------------------------
+
+[Taken from the closed bug report #22769] C++ exceptions don't work
+with C libraries, if the C code wasn't designed to be thrown through.
+A solution could be to translate all C libraries with -fexceptions.
+Mostly trying to throw an exception in a callback function (qsort,
+Tcl command callbacks, etc ...). Example:
+
+    #include <stdio.h>
+    #include <tcl.h>
+
+    class A {};
+
+    static
+    int SortCondition(void const*, void const*)
+    {
+        printf("throwing 'sortcondition' exception\n");
+        throw A();
+    }
+
+    int main(int argc, char *argv[])
+    {
+        int list[2];
+
+        try {
+            SortCondition(NULL,NULL);
+        } catch (A) {
+            printf("caught test-sortcondition exception\n");
+        }
+        try {
+            qsort(&list, sizeof(list)/sizeof(list[0]),sizeof(list[0]),
+                 &SortCondition);
+        } catch (A) {
+            printf("caught real-sortcondition exception\n");
+        }
+        return 0;
+}
+
+Andrew Macleod <amacleod@cygnus.com> responded:
+
+When compiled with the table driven exception handling, exception can only
+be thrown through functions which have been compiled with the table driven EH.
+If a function isn't compiled that way, then we do not have the frame
+unwinding information required to restore the registers when unwinding.
+
+I believe the setjmp/longjmp mechanism will throw through things like this, 
+but its produces much messier code.  (-fsjlj-exceptions)
+
+The C compiler does support exceptions, you just have to turn them on
+with -fexceptions.
+
+Your main options are to:
+  a) Don't use callbacks, or at least don't throw through them.
+  b) Get the source and compile the library with -fexceptions (You have to
+     explicitly turn on exceptions in the C compiler)
+  c) always use -fsjlj-exceptions (boo, bad choice :-)
+
+
+g++: "undefined reference" to static const array in class
+---------------------------------------------------------
+
+The following code compiles under GNU C++ 2.7.2 with correct results,
+but produces the same linker error with GNU C++ 2.95.2.
+Alexandre Oliva <oliva@lsd.ic.unicamp.br> responded:
+
+All of them are correct.  A static data member *must* be defined
+outside the class body even if it is initialized within the class
+body, but no diagnostic is required if the definition is missing.  It
+turns out that some releases do emit references to the missing symbol,
+while others optimize it away.
+
+#include <iostream>
+
+class Test
+{
+  public:
+    Test(const char *q);
+  protected:
+    static const unsigned char  Jam_signature[4]   = "JAM";
+};
+
+Test::Test(const char *q)
+{
+  if (memcmp(q, Jam_signature, sizeof(Jam_signature)) != 0)
+  cerr << "Hello world!\n";
+}
+
+int main(void)
+{
+  Test::Test("JAM");
+  return 0;
+}
+
+g++: g++ causes passing non const ptr to ptr to a func with const arg
+     to cause an error (not a bug)
+---------------------------------------------------------------------
+
+Example:
+
+#include <stdio.h>
+void test(const char **b){
+        printf ("%s\n",*b);
+}
+int main(void){
+        char *test1="aoeu";
+        test(&test1);
+}
+
+make const
+g++     const.cc   -o const
+const.cc: In function `int main()':
+const.cc:7: passing `char **' as argument 1 of `test(const char **)' adds cv-quals without intervening `const'
+make: *** [const] Error 1
+
+Answer from "Martin v. Loewis" <martin@loewis.home.cs.tu-berlin.de>:
+
+> ok... maybe I missed something.. I haven't really kept up with the latest in
+> C++ news.  But I've never heard anything even remotly close to passing a non
+> const var into a const arg being an error before.
+
+Thanks for your bug report. This is a not a bug in the compiler, but
+in your code. The standard, in 4.4/4, puts it that way
+
+# A conversion can add cv-qualifiers at levels other than the first in
+# multi-level pointers, subject to the following rules:
+# Two pointer types T1 and T2 are similar if there exists a type T and
+# integer n > 0 such that:
+#   T1 is cv(1,0) pointer to cv(1,1) pointer to ... cv(1,n-1)
+#   pointer to cv(1,n) T
+# and
+#   T2 is cv(2,0) pointer to cv(2,1) pointer to ... cv(2,n-1)
+#   pointer to cv(2,n) T
+# where each cv(i,j) is const, volatile, const volatile, or
+# nothing. The n-tuple of cv-qualifiers after the first in a pointer
+# type, e.g., cv(1,1) , cv(1,2) , ... , cv(1,n) in the pointer type
+# T1, is called the cv-qualification signature of the pointer type. An
+# expression of type T1 can be converted to type T2 if and only if the
+# following conditions are satisfied:
+#  - the pointer types are similar.
+#  - for every j > 0, if const is in cv(1,j) then const is in cv(2,j) ,
+#    and similarly for volatile.
+#  - if the cv(1,j) and cv(2,j) are different, then const is in every
+#    cv(2,k) for 0 < k < j.
+
+It is the last rule that your code violates. The standard gives then
+the following example as a rationale:
+
+# [Note: if a program could assign a pointer of type T** to a pointer
+# of type const T** (that is, if line //1 below was allowed), a
+# program could inadvertently modify a const object (as it is done on
+# line //2). For example,
+# int main() { 
+#   const char c = 'c'; 
+#   char* pc; 
+#   const char** pcc = &pc; //1: not allowed 
+#   *pcc = &c; 
+#   *pc = 'C'; //2: modifies a const object 
+# }
+# - end note]
+
+If you question this line of reasoning, please discuss it in one of
+the public C++ fora first, eg. comp.lang.c++.moderated, or
+comp.std.c++.
+
+
+cpp removes blank lines
+-----------------------
+
+With the new cpp, you need to add -traditional to the "cpp -P" args, else 
+blank lines get removed.
+
+[EDIT ME: scan Debian bug reports and write some nice summaries ...]
--- gcc-6-6.4.0.orig/debian/README.C++
+++ gcc-6-6.4.0/debian/README.C++
@@ -0,0 +1,35 @@
+libstdc++ is an implementation of the Standard C++ Library, including the
+Standard Template Library (i.e. as specified by ANSI and ISO).
+
+Some notes on porting applications from libstdc++-2.90 (or earlier versions)    
+to libstdc++-v3 can be found in the libstdc++6-4.3-doc package. After the
+installation of the package, look at:
+
+  file:///usr/share/doc/gcc-4.3-base/libstdc++/html/17_intro/porting-howto.html
+
+On Debian GNU/Linux you find additional documentation in the
+libstdc++6-4.3-doc package. After installing these packages,
+point your browser to
+
+  file:///usr/share/doc/libstdc++6-4.3-doc/libstdc++/html/index.html
+
+Other documentation can be found:
+
+    http://www.sgi.com/tech/stl/
+
+with a good, recent, book on C++.
+
+A great deal of useful C++ documentation can be found in the C++ FAQ-Lite,
+maintained by Marshall Cline <cline@parashift.com>.  It can be found at the
+mirror sites linked from the following URL (this was last updated on
+2010/09/11):
+
+     http://www.parashift.com/c++-faq/
+
+or use some search engin site to find it, e.g.:
+
+     http://www.google.com/search?q=c%2B%2B+faq+lite
+
+Be careful not to use outdated mirors.
+
+Please send updates to this list as bug report for the g++ package.
--- gcc-6-6.4.0.orig/debian/README.Debian
+++ gcc-6-6.4.0/debian/README.Debian
@@ -0,0 +1,45 @@
+               The Debian GNU Compiler Collection setup
+               ========================================
+
+Please see the README.Debian in /usr/share/doc/gcc, contained in the
+gcc package for a description of the setup of the different compiler
+versions.
+
+For general discussion about the Debian toolchain (GCC, glibc, binutils)
+please use the mailing list debian-toolchain@lists.debian.org; for GCC
+specific things, please use debian-gcc@lists.debian.org.  When in doubt
+use the debian-toolchain ML.
+
+
+Maintainers of these packages
+-----------------------------
+
+Matthias Klose <doko@debian.org>
+Ludovic Brenta <ludovic@ludovic-brenta.org>	(gnat)
+Iain Buclaw <ibuclaw@ubuntu.com>		(gdc)
+Aurelien Jarno <aurel32@debian.org>		(mips*-linux)
+Aurelien Jarno <aurel32@debian.org>		(s390X*-linux)
+
+The following ports lack maintenance in Debian: powerpc, ppc64,
+sparc, sparc64 (unmentioned ports are usually handled by the Debian
+porters).
+
+Former and/or inactive maintainers of these packages
+----------------------------------------------------
+
+Falk Hueffner <falk@debian.org>			(alpha-linux)
+Ray Dassen <jdassen@debian.org>
+Jeff Bailey <jbailey@nisa.net>			(hurd-i386)
+Joel Baker <fenton@debian.org>			(netbsd-i386)
+Randolph Chung <tausq@debian.org>		(ia64-linux)
+Philip Blundell <pb@debian.org>			(arm-linux)
+Ben Collins <bcollins@debian.org>		(sparc-linux)
+Dan Jacobowitz <dan@debian.org>			(powerpc-linux)
+Thiemo Seufer <ths@networkno.de>		(mips*-linux)
+Matt Taggart <taggart@carmen.fc.hp.com>		(hppa-linux)
+Gerhard Tonn <GerhardTonn@swol.de>		(s390-linux)
+Roman Zippel <zippel@linux-m68k.org>		(m68k-linux)
+Arthur Loiret <arthur.loiret@gmail.com>		(gdc)
+
+===============================================================================
+
--- gcc-6-6.4.0.orig/debian/README.cross
+++ gcc-6-6.4.0/debian/README.cross
@@ -0,0 +1,144 @@
+Building cross-compiler Debian packages
+---------------------------------------
+
+It is possible to build C and C++ cross compilers and support libraries
+from gcc-4.0 source package. This document describes how to do so.
+Cross-compiler build support is not perfect yet, please send fixes
+and improvements to debian-gcc@lists.debian.org and 
+debian-embedded@lists.debian.org
+
+Before you start, you should probably check available pre-built
+cross-toolchain debs. Available at http://www.emdebian.org
+
+Old patches could be reached at
+  http://zigzag.lvk.cs.msu.su/~nikita/debian/
+  
+If they are no longer there, you may check EmDebian web site at
+  http://www.emdebian.org/
+or ask debian-embedded@lists.debian.org for newer location.
+
+Please check http://bugs.debian.org/391445 if you are about building
+gcc-4.3 or above.
+
+Most of them has been merged with gcc debian sources.
+
+0. What's wrong with toolchain-source approach
+
+Package toolchain-source contains sources for binutils and gcc, as well as
+some support scripts to build cross-compiler packages. They seem to work.
+
+However, there is one fundamental problem with this approach.
+Gcc package is actively maintained and frequently updated. These updates
+do contain bug fixes and improvements, especially for non-x86 architectures.
+Cross-compilers built using toolchain-source will not get those fixes unless
+toolchain-source package is updated after each binutils and gcc update.
+The later is not hapenning in real life. For example, toolchain-source
+was upgraded from gcc-3.2 to gcc-3.3 half a year later than gcc-3.3 became
+Debian default compiler.
+
+Keeping toolchain-source package up-to-date requires lots of work, and seems
+to be a waste of time. It is much better to build cross-compilers directly
+from gcc source package.
+
+
+1. What is needed to build a cross-compiler from gcc-4.3 source
+
+1.1. dpkg-cross package
+
+Dpkg-cross package contains several tools to manage cross-compile environment.
+
+It can convert native debian library and lib-dev packages for the target
+architecture to binary-all packages that keep libraries and headers under
+/usr/$(TARGET)/.
+
+Also it contains helper tools for cross-compiling debian packages. Some of
+these tools are used while building libgcc1 and libstdc++ library packages.
+The resulting library packages follow the same convensions as library packages
+converted by dpkg-cross.
+
+Currently, at least version 1.18 of dpkg-cross is needed for cross-gcc
+package build. Version 1.32 of dpkg-cross is needed in order to build gcc-4.3.
+
+1.2. cross-binutils for the target
+
+You need cross-binutils for your target to build cross-compiler.
+Binutils-multiarch package will not work because it does not provide cross-
+assemblers.
+
+If you don't want to use pre-built cross-binutils packages, you may build
+your own from binutils debian source package, using patches posted to
+bug #231707. Please use the latest of patch versions available there.
+
+Alternatively, you may use toolchain-source package to build cross-binutils
+(but in this case you will probably also want to use toolchain-source
+to build cross-compiler itself). However, multilib'ed cross-compilers may
+not build or work with these binutils.
+
+1.3. libc for target
+
+You also need libc library and development packages for the target
+architecture installed.
+
+To get those, download linux-kernel-headers, libc6, and libc6-dev binary
+debs for your target, convert those using dpkg-cross -b, and install
+resulting -arch-cross debs. Consult dpkg-cross manual page for more
+information.
+
+Building with/for alternative libc's is not supported yet (but this is in
+TODO).
+
+Note that if you plan to use your cross-toolchain to develop kernel drivers
+or similar low-level things, you will probably also need kernel headers
+for the exact kernel version that your target hardware uses.
+
+
+2. Building cross-compiler packages
+
+Get gcc-4.3 source package.
+
+Unpack it using dpkg-source -x, and cd to the package directory.
+
+Set GCC_TARGET environment variable to the target architectire name. Note
+that currently you should use debian architecture name (i.e 'powerpc' or 'arm'),
+not GNU system type (i.e. 'powerpc-linux' or 'arm-linux'). Setting GCC_TARGET
+to GNU system type will cause cross-compiler build to fail.
+
+Instead of setting GCC_TARGET, target architecture name may be put into
+debian/target file. If both GCC_TARGET is defined and debian/target file
+exists, GCC_TARGET is used.
+
+Run debian/rules control. This will change debian/control file,
+adjusting build-depends.  By default, the packages will not depend on the
+system -base package. A variable DEB_CROSS_INDEPENDENT has been merged with DEB_CROSS variable.
+
+You can then build with either
+
+$ GCC_TARGET=[arch] dpkg-buildpackage -rfakeroot
+
+3. Using crosshurd
+
+Jeff Bailey <jbailey@raspberryginger.com> suggests alternate way to setup
+environment to build cross-compiler, using 'crosshurd' package. 
+Crosshurd is like debootstrap but cross-arch, and works on the Hurd,
+Linux and FreeBSD.  (The name is historical).
+
+If you setup your environment with crosshurd, you will need to fix symlinks
+in lib and usr/lib to be relative instead of absolute. For example:
+
+lrwxrwxrwx    1 root     root           20 2004-05-06 23:02 libcom_err.so -> /lib/libcom_err.so.2
+
+Needs to be changed to:
+
+lrwxrwxrwx    1 root     root           20 2004-05-06 23:02 libcom_err.so -> ../../lib/libcom_err.so.2
+
+Also, if you choose this method, set the environment variable 'with_sysroot'
+to point to the ABSOLUTE PATH where the crosshurd was done.
+
+Note however that build-depends of cross-gcc and dependencies in generated
+libgcc1 and libstdc++ packages assume that you use dpkg-cross to set up
+your environment, and may be wrong or incomplete if you use alternate methods.
+But probably you don't care.
+
+--
+Nikita V. Youshchenko <yoush@debian.org> - Jun 2004
+Hector Oron Martinez  <hector.oron@gmail.com> - Oct 2006
--- gcc-6-6.4.0.orig/debian/README.gnat
+++ gcc-6-6.4.0/debian/README.gnat
@@ -0,0 +1,35 @@
+If you want to develop Ada programs and libraries on Debian, please
+read the Debian Policy for Ada:
+
+http://people.debian.org/~lbrenta/debian-ada-policy.html
+
+The default Ada compiler is and always will be the package `gnat'.
+Debian contains many programs and libraries compiled with it, which
+are all ABI-compatible.
+
+Starting with gnat-4.2, Debian provides both zero-cost and
+setjump/longjump versions of the run-time library.  The zero-cost
+exception handling mechanism is the default as it provides the best
+performance.  The setjump/longjump exception handling mechanism is new
+and only provided as a static library.  It is necessary to use this
+exception handling mechanism in distributed (annex E) programs.  If
+you wish to use the new sjlj library:
+
+1) call gnatmake with --RTS=sjlj
+2) call gnatbind with -static
+
+Do NOT link your programs with libgnat-4.2.so, because it uses the ZCX
+mechanism.
+
+
+This package also includes small tools covering specific needs.
+
+* When linking objects compiled from both Ada and C sources, you need
+  to use compatible versions of the Ada and C compilers. The
+  /usr/bin/gnatgcc symbolic link targets a version of the C compiler
+  compatible with the default Ada compiler, and may differ from the
+  default C compiler /usr/bin/gcc.
+
+* When packaging Ada sources for Debian, you may want to read the
+  /usr/share/ada/debian_packaging.mk Makefile snippet and/or include
+  it from debian/rules in order to set sensible defaults.
--- gcc-6-6.4.0.orig/debian/README.libstdc++-baseline.in
+++ gcc-6-6.4.0/debian/README.libstdc++-baseline.in
@@ -0,0 +1,2 @@
+The libstdc++ baseline file is a list of symbols exported by the
+libstdc++ library.
--- gcc-6-6.4.0.orig/debian/README.maintainers
+++ gcc-6-6.4.0/debian/README.maintainers
@@ -0,0 +1,196 @@
+-*- Outline -*-
+
+Read this file if you are a Debian Developer or would like to become
+one, or if you would like to create your own binary packages of GCC.
+
+* Overview
+
+From the GCC sources, Debian currently builds 3 source packages and
+almost 100 binary packages, using a single set of build scripts.  The
+3 source packages are:
+
+gcc-x.y: C, C++, Fortran, Objective-C and Objective-C++, plus many
+         common libraries like libssp and libgcc.
+gcj-x.y: Java.
+gnat-x.y: Ada.
+
+The way we do this is quite peculiar, so listen up :)
+
+When we build from the gcc-x.y source package, we produce, among many
+others, a gcc-x.y-source binary package that contains the pristine
+upstream tarball and some Debian-specific patches.  Any user can then
+install this package on their Debian system, and will have the full
+souces in /usr/src/gcc-x.y/gcc-<timestamp>.tar.bz2, along with the
+Makefile snippets that unpack and patch them.
+
+The intended use for this package is twofold: (a) allow users to build
+their own cross-compilers, and (b) build the other two packages,
+gcj-x.y and gnat-x.y.
+
+- gcc-x.y requires only a C compiler to build and produces C, C++,
+  Fortran, Go and Objective-C compilers and libraries. It also
+  produces the binary package gcc-x.y-source containing all the
+  sources and patches in a tarball.
+
+- gcj-x.y build-depends on gcc-x.y-source and C++ and Java compilers.
+  Its .orig.tar.bz2 file only contains an empty directory; the real
+  sources from which it builds the binary packages are in
+  gcc-x.y-source.
+
+- gnat-x.y build-depends on gcc-x.y-source and an Ada compiler.  It
+  does not even have an .orig.tar.bz2 package; it is a Debian native
+  package.
+
+The benefits of this split are many:
+
+- bootstrapping a subset of languages is much faster than
+  bootstrapping all languages and libraries (which can take a full
+  week on slow architectures like mips or arm)
+
+- the language maintainers don't have to wait for each other
+
+- for new ports, the absence of a port of, say, gnat-x.y does not
+  block the porting of gcc-x.y.
+
+gcc-x.y-source is also intended for interested users to build
+cross-compiler packages.  Debian cannot provide all possible
+cross-compiler packages (i.e. all possible host, target, language and
+library combinations), so instead tries to facilitate building them.
+
+* The build sequence
+
+As for all other Debian packages, you build GCC by calling
+debian/rules.
+
+The first thing debian/rules does it to look at the top-most entry in
+debian/changelog: this tells it which source package it is building.
+For example, if the first entry in debian/changelog reads:
+
+gcj-4.3 (4.3-20070609-1) unstable; urgency=low
+
+  * Upload as gcj-4.3.
+
+ -- Ludovic Brenta <lbrenta@debian.org>  Tue, 26 Jun 2007 00:26:42 +0200
+
+then, debian/rules will build only the Java binary packages.
+
+The second step is to build debian/control from debian/control.m4 and
+a complex set of rules specified in debian/rules.conf.  The resulting
+control file contains only the binary packages to be built.
+
+The third step is to select which patches to apply (this is done in
+debian/rules.defs), and then to apply the selected patches (see
+debian/rules.patch).  The result of this step is a generated
+debian/patches/series file for use by quilt.
+
+The fourth step is to unpack the GCC source tarball.  This tarball is
+either in the build directory (when building gcc-x.y), or in
+/usr/src/gcc-x.y/gcc-x.y.z.tar.xz (when building the other source
+packages).
+
+The fifth step is to apply all patches to the unpacked sources with
+quilt.
+
+The sixth step is to create a "build" directory, cd into it, call
+../src/configure, and bootstrap the compiler and libraries selected.
+This is in debian/rules2.
+
+The seventh step is to call "make install" in the build directory:
+this installs the compiler and libraries into debian/tmp
+(i.e. debian/tmp/usr/bin/gcc, etc.)
+
+The eighth step is to run the GCC test suite.  This actually takes at
+least as much time as bootstrapping, and you can disable it by setting
+WITHOUT_CHECK to "yes" in the environment.
+
+The ninth step is to build the binary packages, i.e. the .debs.  This
+is done by a set of language- and architecture-dependent Makefile
+snippets in the debian/rules.d/ directory, which move files from the
+debian/tmp tree to the debian/<package> trees.
+
+* Making your own packages
+
+In this example, we will build our own gnat-x.y package.
+
+1) Install gcc-x.y-source, which contains the real sources:
+
+# aptitude install gcc-x.y-source
+
+2) Create a build directory:
+
+$ mkdir gnat-x.y-x.y.z; cd gnat-x.y-x.y.z
+
+3) Checkout from Subversion:
+
+$ svn checkout svn://svn.debian.org/gcccvs/branches/sid/gcc-x.y/debian
+
+4) Edit the debian/changelog file, adding a new entry at the top that
+   starts with "gnat-x.y".
+
+5) Generate the debian/control file, adjusted for gnat:
+
+$ debian/rules control
+
+8) Build:
+
+$ dpkg-buildpackage
+
+* Hints
+
+You need a powerful machine to build GCC.  The larger, the better.
+The build scripts take advantage of as many CPU threads as are
+available in your box (for example: 2 threads on a dual-core amd64; 4
+threads on a dual-core POWER5; 32 threads on an 8-core UltraSPARC T1,
+etc.).
+
+If you have 2 GB or more of physical RAM, you can achieve maximum
+performance by building in a tmpfs, like this:
+
+1) as root, create the new tmpfs:
+
+# mount -t tmpfs -o size=1280m none /home/lbrenta/src/debian/ram
+
+By default, the tmpfs will be limited to half your physical RAM.  The
+beauty of it is that it only consumes as much physical RAM as
+necessary to hold the files in it; deleting files frees up RAM.
+
+2) As your regular user, create the working directory in the tmpfs
+
+$ cp --archive ~/src/debian/gcc-x.y-x.y.z ~/src/debian/ram
+
+3) Build in there.  On my dual-core, 2 GHz amd64, it takes 34 minutes
+   to build gnat, and the tmpfs takes 992 MiB of physical RAM but
+   exceeds 1 GiB during the build.
+
+Note that the build process uses a lot of temporary files.  Your $TEMP
+directory should therefore also be in a ram disk.  You can achieve
+that either by mounting it as tmpfs, or by setting TEMP to point to
+~/src/debian/ram.
+
+Also note that each thread in your processor(s) will run a compiler in
+it and use up RAM.  Therefore your physical memory should be:
+
+Physical_RAM >= 1.2 + 0.4 * Threads (in GiB)
+
+(this is an estimate; your mileage may vary).  If you have less
+physical RAM than recommended, reduce the number of threads allocated
+to the build process, or do not use a tmpfs to build.
+
+* Patching GCC
+
+Debian applies a large number of patches to GCC as part of the build
+process.  It uses quilt but the necessary debian/patches/series is not
+part of the packaging scripts; instead, "debian/rules patch" generates
+this file by looking at debian/control (which is itself generated!),
+debian/changelog and other files.  Then it applies all the patches.
+At this point, you can use quilt as usual:
+
+$ cd ~/src/debian/gcc-x.y
+$ export QUILT_PATCHES=$PWD/debian/patches
+$ quilt series
+
+If you add new patches, remember to add them to the version control
+system too.
+
+-- 
+Ludovic Brenta, 2012-04-02.
--- gcc-6-6.4.0.orig/debian/README.snapshot
+++ gcc-6-6.4.0/debian/README.snapshot
@@ -0,0 +1,36 @@
+Debian gcc-snapshot package
+===========================
+
+This package contains  a recent development SNAPSHOT of all files
+contained in the GNU Compiler Collection (GCC).
+
+DO NOT USE THIS SNAPSHOT FOR BUILDING DEBIAN PACKAGES!
+
+This package will NEVER hit the testing distribution. It's used for
+tracking gcc bugs submitted to the Debian BTS in recent development
+versions of gcc.
+
+To use this snapshot, you should set the following environment variables:
+
+	LD_LIBRARY_PATH=/usr/lib/gcc-snapshot/lib:$LD_LIBRARY_PATH
+	PATH=/usr/lib/gcc-snapshot/bin:$PATH
+
+You might also like to use a shell script to wrap up this 
+funcationality, e.g. 
+ 
+place in /usr/local/bin/gcc-snapshot and chmod +x it 
+ 
+----------- snip ----------
+#! /bin/sh
+LD_LIBRARY_PATH=/usr/lib/gcc-snapshot/lib:$LD_LIBRARY_PATH
+PATH=/usr/lib/gcc-snapshot/bin:$PATH
+gcc "$@"
+----------- snip ----------
+
+Make the same for g++, g77, gij, gcj, cpp, ...
+ 
+Don't forget the quotes around the $@ or gcc will not parse it's 
+command line correctly! 
+
+Unset these variables before building Debian packages destined for an
+upload to ftp-master.debian.org.
--- gcc-6-6.4.0.orig/debian/README.source
+++ gcc-6-6.4.0/debian/README.source
@@ -0,0 +1,16 @@
+Patches applied to the Debian version of GCC
+--------------------------------------------
+
+Debian specific patches can be found in the debian/patches directory.
+Quilt is used as the patch system.  See /usr/share/doc/quilt/README.source
+for details about quilt.
+
+Patches are applied by calling `debian/rules patch'.  The `series'
+file is constructed on the fly based on the files found in the to
+debian/rules.patch "debian_patches" variable, configure scripts are
+regenerated in the `patch' target. The gcc source is unpacked under
+src/ this needs to be reflected in the patch header.
+
+The source packages gcj-x.y and gnat-x.y do not contain copies of the
+source code but build-depend on the appropriate gcc-x.y-source package
+instead.
--- gcc-6-6.4.0.orig/debian/README.ssp
+++ gcc-6-6.4.0/debian/README.ssp
@@ -0,0 +1,28 @@
+Stack smashing protection is a feature of GCC that enables a program to
+detect buffer overflows and immediately terminate execution, rather than
+continuing execution with corrupt internal data structures. It uses
+"canaries" and local variable reordering to reduce the likelihood of
+stack corruption through buffer overflows.
+
+Options that affect stack smashing protection:
+
+-fstack-protector
+    Enables protection for functions that are vulnerable to stack
+    smashing, such as those that call alloca() or use pointers.
+
+-fstack-protector-all
+    Enables protection for all functions.
+
+-Wstack-protector
+    Warns about functions that will not be protected. Only active when
+    -fstack-protector has been used.
+
+Applications built with stack smashing protection should link with the
+ssp library by using the option "-lssp" for systems with glibc-2.3.x or
+older; glibc-2.4 and newer versions provide this functionality in libc.
+
+The Debian architectures alpha, hppa, ia64, m68k, mips, mipsel do not
+have support for stack smashing protection.
+
+More documentation can be found at the project's website:
+http://researchweb.watson.ibm.com/trl/projects/security/ssp/
--- gcc-6-6.4.0.orig/debian/TODO
+++ gcc-6-6.4.0/debian/TODO
@@ -0,0 +1,50 @@
+(It is recommended to edit this file with emacs' todoo mode)
+Last updated: 2008-05-02
+
+* General
+
+- Clean up the sprawl of debian/rules.  I'm sure there are neater
+  ways to do some of it; perhaps split it up into some more files?
+  Partly done.
+
+- Make debian/rules control build the control file without unpacking
+  the sources or applying patches.  Currently, it unpacks the sources,
+  patches them, creates the control file, and a subsequent
+  dpkg-buildpackage deletes the sources, re-unpacks them, and
+  re-patches them.
+
+- Reorganise debian/rules.defs to decide which packages to build in a
+  more straightforward and less error-prone fashion: (1) start with
+  all languages; override the list of languages depending on the name
+  of the source package (gcc-4.3, gnat-4.3, gdc-4.3, gcj-4.3).  (2)
+  filter the list of languages depending on the target platform; (3)
+  depending on the languages to build, decide on which libraries to
+  build.
+
+o [Ludovic Brenta] Ada
+
+- Done: Link the gnat tools with libgnat.so, instead of statically.
+
+- Done: Build libgnatvsn containing parts of the compiler (version
+  string, etc.) under GNAT-Modified GPL.  Link the gnat tools with it.
+
+- Done: Build libgnatprj containing parts of the compiler (the project
+  manager) under pure GPL.  Link the gnat tools with it.
+
+- Done: Build both the zero-cost and setjump/longjump exceptions
+  versions of libgnat.  In particular, gnat-glade (distributed systems)
+  works best with SJLJ.
+
+- Done: Re-enable running the test suite.
+
+- Add support for building cross-compilers.
+
+- Add support for multilib (not yet supported upstream).
+
+* Fortran
+
+- gfortran man page generation
+
+* Java
+
+- build java-gcj-compat from the gcc source?
--- gcc-6-6.4.0.orig/debian/acats-killer.sh
+++ gcc-6-6.4.0/debian/acats-killer.sh
@@ -0,0 +1,62 @@
+#! /bin/sh
+
+# on ia64 systems, the acats hangs in unaligned memory accesses.
+# kill these testcases.
+
+pidfile=acats-killer.pid
+
+usage()
+{
+    echo >&2 "usage: `basename $0` [-p <pidfile>] <ada logfile> <next logfile>"
+    exit 1
+}
+
+while [ $# -gt 0 ]; do
+    case $1 in
+    -p)
+	pidfile=$2
+	shift
+	shift
+	;;
+    -*)
+	usage
+	;;
+    *)
+	break
+    esac
+done
+
+[ $# -eq 2 ] || usage
+
+logfile=$1
+stopfile=$2
+interval=30
+
+echo $$ > $pidfile
+
+while true; do
+    if [ -f "$stopfile" ]; then
+	echo "`basename $0`: finished."
+	rm -f $pidfile
+	exit 0
+    fi
+    sleep $interval
+    if [ ! -f "$logfile" ]; then
+	continue
+    fi
+    pids=$(ps aux | awk '/testsuite\/ada\/acats\/tests/ { print $2 }')
+    if [ -n "$pids" ]; then
+	sleep $interval
+        pids2=$(ps aux | awk '/testsuite\/ada\/acats\/tests/ { print $2 }')
+	if [ "$pids" = "$pids2" ]; then
+	    #echo kill: $pids
+	    kill $pids
+	    sleep 1
+            pids2=$(ps aux | awk '/testsuite\/ada\/acats\/tests/ { print $2 }')
+	    if [ "$pids" = "$pids2" ]; then
+	        #echo kill -9: $pids
+	        kill -9 $pids
+	    fi
+	fi
+    fi
+done
--- gcc-6-6.4.0.orig/debian/ada/confirm_debian_bugs.py
+++ gcc-6-6.4.0/debian/ada/confirm_debian_bugs.py
@@ -0,0 +1,968 @@
+#!/usr/bin/env python
+
+# Helper when migrating bugs from a gnat version to another.
+
+from __future__ import print_function
+import os.path
+import re
+import shutil
+import subprocess
+import tempfile
+
+os.environ ['LC_ALL'] = 'C'
+
+# If == new_version, "reassign" -> "found" and "retitle" -> "fixed".
+# Once the bug tracking system is informed,
+# please update this number.
+old_version = "5"
+
+# The current version.
+new_version = "6"
+
+for line in subprocess.check_output (("dpkg", "--status", "gnat-" + new_version)).split ("\n"):
+    if line.startswith ("Version: "):
+        deb_version = line [len ("Version: "):]
+        break
+# Will cause an error later if deb_version is not defined.
+
+# Each bug has its own subdirectory in WORKSPACE.
+# Every bug subdir is removed if the bug is confirmed,
+# and WORKSPACE is removed if empty.
+workspace = tempfile.mkdtemp (suffix = "-gnat-" + deb_version + "-bugs")
+
+def attempt_to_reproduce (bug, make, sources):
+    tmp_dir = os.path.join (workspace, "bug{}".format (bug))
+    os.mkdir (tmp_dir)
+
+    for (name, contents) in sources:
+        with open (os.path.join (tmp_dir, name), "w") as f:
+            f.write (contents)
+
+    path = os.path.join (tmp_dir, "stderr.log")
+    with open (path, "w") as e:
+        status = subprocess.call (make, stderr=e, cwd=tmp_dir)
+    with open (path, "r") as e:
+        stderr = e.read ()
+    return tmp_dir, status, stderr
+
+def reassign_and_remove_dir (bug, tmp_dir):
+    if old_version == new_version:
+        print ("found {} {}".format (bug, deb_version))
+    else:
+        print ("reassign {} {} {}".format (bug, "gnat-" + new_version, deb_version))
+    shutil.rmtree (tmp_dir)
+
+def report (bug, message, output):
+    print ("# {}: {}.".format (bug, message))
+    for line in output.split ("\n"):
+        print ("# " + line)
+
+def report_and_retitle (bug, message, output):
+    report (bug, message, output)
+    if old_version == new_version:
+        print ("fixed {} {}".format (bug, deb_version))
+    else:
+        print ("retitle {} [Fixed in {}] <current title>".format (bug, new_version))
+
+def check_compiles_but_should_not (bug, make, sources):
+    tmp_dir, status, stderr = attempt_to_reproduce (bug, make, sources)
+    if status == 0:
+        reassign_and_remove_dir (bug, tmp_dir)
+    else:
+        report_and_retitle (bug, "now fails to compile (bug is fixed?)", stderr)
+
+def check_reports_an_error_but_should_not (bug, make, sources, regex):
+    tmp_dir, status, stderr = attempt_to_reproduce (bug, make, sources)
+    if status == 0:
+        report_and_retitle (bug, "now compiles (bug is fixed?)", stderr)
+    elif re.search (regex, stderr):
+        reassign_and_remove_dir (bug, tmp_dir)
+    else:
+        report (bug, "still fails to compile, but with a new stderr", stderr)
+
+def check_reports_error_but_forgets_one (bug, make, sources, regex):
+    tmp_dir, status, stderr = attempt_to_reproduce (bug, make, sources)
+    if status == 0:
+        report (bug, "now compiles (?)", stderr);
+    elif re.search (regex, stderr):
+        report_and_retitle (bug, "now reports the error (bug is fixed ?)", stderr)
+    else:
+        reassign_and_remove_dir (bug, tmp_dir)
+
+def check_produces_a_faulty_executable (bug, make, sources, regex, trigger):
+    tmp_dir, status, stderr = attempt_to_reproduce (bug, make, sources)
+    if status != 0:
+        report (bug, "cannot compile the trigger anymore", stderr)
+    else:
+        output = subprocess.check_output ((os.path.join (tmp_dir, trigger),), cwd=tmp_dir)
+        if re.search (regex, output):
+            reassign_and_remove_dir (bug, tmp_dir)
+        else:
+            report_and_retitle (bug, "output of the trigger changed (bug fixed?)", output)
+
+######################################################################
+
+check_reports_an_error_but_should_not (
+    bug = 244936,
+    make = ("gnatmake", "p"),
+    regex = 'p\.ads:3:25: "foo" is hidden within declaration of instance',
+    sources = (
+        ("foo.ads", """generic
+procedure foo;
+"""),
+        ("foo.adb", """procedure foo is
+begin
+   null;
+end foo;
+"""), ("p.ads", """with foo;
+package p is
+   procedure FOO is new foo;        -- OK
+end p;
+""")))
+
+check_compiles_but_should_not (
+    bug = 244970,
+    make = ("gnatmake", "pak5"),
+    sources = (
+        ("pak1.ads", """generic
+package pak1 is
+end pak1;
+"""),
+        ("pak1-pak2.ads", """generic
+package pak1.pak2 is
+end pak1.pak2;
+"""),
+        ("pak5.ads", """with pak1.pak2;
+generic
+   with package new_pak2 is new pak1.pak2;  -- ERROR: illegal use of pak1
+package pak5 is
+end pak5;
+""")))
+
+check_reports_an_error_but_should_not (
+    bug = 246187,
+    make = ("gnatmake", "test_43"),
+    regex = "Error detected at system.ads:156:5",
+    sources = (
+        ("test_43.ads", """package Test_43 is
+  type T1 is private;
+
+private
+
+   type T2 is record
+      a: T1;
+   end record;
+   type T2_Ptr is access T2;
+
+   type T1 is record
+      n: T2_Ptr := new T2;
+   end record;
+
+end Test_43;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 247013,
+    make = ("gnatmake", "test_53"),
+    sources = (
+        ("test_53.ads", """generic
+   type T1 is private;
+package Test_53 is
+   type T2 (x: integer) is new T1;  -- ERROR: x not used
+end Test_53;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 247017,
+    make = ("gnatmake", "test_59"),
+    sources = (
+        ("test_59.adb", """procedure Test_59 is
+
+    generic
+       type T1 (<>) is private;
+    procedure p1(x: out T1);
+
+    procedure p1 (x: out T1) is
+    b: boolean := x'constrained;   --ERROR: not a discriminated type
+    begin
+       null;
+    end p1;
+
+begin
+   null;
+end Test_59;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 247018,
+    make = ("gnatmake", "test_60"),
+    sources = (
+        ("pak1.ads", """package pak1 is
+   generic
+   package pak2 is
+   end pak2;
+end pak1;
+"""),
+        ("test_60.ads", """with pak1;
+package Test_60 is
+   package PAK1 is new pak1.pak2;   --ERROR: illegal reference to pak1
+end Test_60;
+""")))
+
+check_compiles_but_should_not (
+    bug =  247019,
+    make = ("gnatmake", "test_61"),
+    sources = (
+        ("test_61.adb", """procedure Test_61 is
+   procedure p1;
+
+   generic
+   package pak1 is
+      procedure p2 renames p1;
+   end pak1;
+
+   package new_pak1 is new pak1;
+   procedure p1 renames new_pak1.p2;   --ERROR: circular renames
+begin
+   p1;
+end Test_61;
+"""),))
+
+check_produces_a_faulty_executable (
+    bug = 247569,
+    make = ("gnatmake", "test_75"),
+    trigger = "test_75",
+    regex = "failed: wrong p1 called",
+    sources = (
+        ("test_75.adb", """with text_io;
+procedure Test_75 is
+   generic
+   package pak1 is
+      type T1 is null record;
+   end pak1;
+
+   generic
+      with package A is new pak1(<>);
+      with package B is new pak1(<>);
+   package pak2 is
+      procedure p1(x: B.T1);
+      procedure p1(x: A.T1);
+   end pak2;
+
+   package body pak2 is
+
+      procedure p1(x: B.T1) is
+      begin
+         text_io.put_line("failed: wrong p1 called");
+      end p1;
+
+      procedure p1(x: A.T1) is
+      begin
+         text_io.put_line("passed");
+      end p1;
+
+      x: A.T1;
+   begin
+      p1(x);
+   end pak2;
+
+   package new_pak1 is new pak1;
+   package new_pak2 is new pak2(new_pak1, new_pak1); -- (1)
+
+begin
+   null;
+end Test_75;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 247570,
+    make = ("gnatmake", "test_76"),
+    sources = (
+        ("test_76.adb", """procedure Test_76 is
+
+   generic
+   procedure p1;
+
+   pragma Convention (Ada, p1);
+
+   procedure p1 is
+   begin
+      null;
+   end p1;
+
+   procedure new_p1 is new p1;
+   pragma Convention (Ada, new_p1);    --ERROR: new_p1 already frozen
+
+begin
+   null;
+end Test_76;
+"""),))
+
+check_produces_a_faulty_executable (
+    bug =  247571,
+    make = ("gnatmake", "test_77"),
+    trigger = "test_77",
+    regex = "failed: wrong p1 called",
+    sources = (
+        ("pak.ads", """package pak is
+   procedure p1;
+   procedure p1(x: integer);
+   pragma export(ada, p1);
+end pak;
+"""),
+        ("pak.adb", """with text_io; use text_io;
+package body pak is
+   procedure p1 is
+   begin
+      put_line("passed");
+   end;
+
+   procedure p1(x: integer) is
+   begin
+      put_line("failed: wrong p1 called");
+   end;
+end pak;
+"""),
+        ("test_77.adb", """with pak;
+procedure Test_77 is
+   procedure p1;
+   pragma import(ada, p1);
+begin
+   p1;
+end Test_77;
+""")))
+
+check_compiles_but_should_not (
+    bug = 248166,
+    make = ("gnatmake", "test_82"),
+    sources = (
+        ("test_82.adb", """procedure Test_82 is
+   package pak1 is
+      type T1 is tagged null record;
+   end pak1;
+
+   package body pak1 is
+      -- type T1 is tagged null record;  -- line 7
+
+      function "=" (x, y : T1'class) return boolean is -- line 9
+      begin
+         return true;
+      end "=";
+
+      procedure proc (x, y : T1'class) is
+         b : boolean;
+      begin
+         b := x = y;     --ERROR: ambiguous "="
+      end proc;
+
+   end pak1;
+
+begin
+   null;
+end Test_82;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 248168,
+    make = ("gnatmake", "test_84"),
+    sources = (
+        ("test_84.adb", """procedure Test_84 is
+   package pak1 is
+      type T1 is abstract tagged null record;
+      procedure p1(x: in out T1) is abstract;
+   end pak1;
+
+   type T2 is new pak1.T1 with null record;
+
+   protected type T3 is
+   end T3;
+
+   protected body T3 is
+   end T3;
+
+   procedure p1(x: in out T2) is    --ERROR: declared after body of T3
+   begin
+      null;
+   end p1;
+
+begin
+   null;
+end Test_84;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 248678,
+    make = ("gnatmake", "test_80"),
+    sources = (
+        ("test_80.ads", """package Test_80 is
+   generic
+      type T1(<>) is private;
+      with function "=" (Left, Right : T1) return Boolean is <>;
+   package pak1 is
+   end pak1;
+
+   package pak2 is
+      type T2 is abstract tagged null record;
+      package new_pak1 is new pak1 (T2'Class);  --ERROR: no matching "="
+   end pak2;
+end Test_80;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 248680,
+    make = ("gnatmake", "test_90"),
+    sources = (
+        ("test_90.adb", """procedure Test_90 is
+   type T1 is tagged null record;
+
+   procedure p1 (x : access T1) is
+      b: boolean;
+      y: aliased T1;
+   begin
+      B := Y'Access = X;     -- ERROR: no matching "="
+--    B := X = Y'Access;     -- line 11: error detected
+   end p1;
+
+begin
+   null;
+end Test_90;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 248681,
+    make = ("gnatmake", "test_91"),
+    sources = (
+        ("test_91.adb", """--  RM 8.5.4(5)
+--  ...the convention of the renamed subprogram shall not be
+--  Intrinsic.
+with unchecked_deallocation;
+procedure Test_91 is
+   generic -- when non generic, we get the expected error
+   package pak1 is
+      type int_ptr is access integer;
+      procedure free(x: in out int_ptr);
+   end pak1;
+
+   package body pak1 is
+      procedure deallocate is new
+        unchecked_deallocation(integer, int_ptr);
+      procedure free(x: in out int_ptr) renames
+        deallocate;  --ERROR: renaming as body can't rename intrinsic
+   end pak1;
+begin
+   null;
+end Test_91;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 248682,
+    make = ("gnatmake", "main"),
+    sources = (
+        ("main.adb", """--  RM 6.3.1(9)
+--  The default calling convention is Intrinsic for ...  an attribute
+--  that is a subprogram;
+
+--  RM 8.5.4(5)
+--  ...the convention of the renamed subprogram shall not be
+--  Intrinsic.
+procedure main is
+   package pak1 is
+      function f1(x: integer'base) return integer'base;
+   end pak1;
+
+   package body pak1 is
+      function f1(x: integer'base) return integer'base renames
+        integer'succ;  --ERROR: renaming as body can't rename intrinsic
+   end pak1;
+begin
+   null;
+end;
+"""),))
+
+check_reports_an_error_but_should_not (
+    bug = 253737,
+    make = ("gnatmake", "test_4"),
+    regex = 'test_4.ads:.:01: "pak2" not declared in "pak1"',
+    sources = (
+        ("parent.ads", """generic
+package parent is
+end parent;
+"""),
+        ("parent-pak2.ads", """generic
+package parent.pak2 is
+end parent.pak2;
+"""),
+        ("parent-pak2-pak3.ads", """generic
+package parent.pak2.pak3 is
+end parent.pak2.pak3;
+"""),
+        ("parent-pak2-pak4.ads", """with parent.pak2.pak3;
+generic
+package parent.pak2.pak4 is
+   package pak3 is new parent.pak2.pak3;
+end parent.pak2.pak4;
+"""),
+        ("pak1.ads", """with parent;
+package pak1 is new parent;
+"""),
+        ("pak6.ads", """with parent.pak2;
+with pak1;
+package pak6 is new pak1.pak2;
+"""),
+        ("test_4.ads", """with parent.pak2.pak4;
+with pak6;
+package Test_4 is new pak6.pak4;
+""")))
+
+check_compiles_but_should_not (
+    bug = 269948,
+    make = ("gnatmake", "test_119"),
+    sources = (
+        ("test_119.ads", """--  RM 3.9.3/11 A generic actual subprogram shall not be an abstract
+--  subprogram.  works OK if unrelated line (A) is commented out.
+package Test_119 is
+   generic
+      with function "=" (X, Y : integer) return Boolean is <>;   -- Removing this allows GCC to detect the problem.
+   package pak1 is
+      function "=" (X, Y: float) return Boolean is abstract;
+      generic
+         with function Equal (X, Y : float) return Boolean is "=";  --ERROR:
+      package pak2 is
+      end pak2;
+   end pak1;
+
+   package new_pak1 is new pak1;
+   package new_pak2 is new new_pak1.pak2;
+end Test_119;
+"""),))
+
+check_compiles_but_should_not (
+    bug = 269951,
+    make = ("gnatmake", "test_118"),
+    sources = (
+        ("pak1.ads", """generic
+package pak1 is
+end pak1;
+"""),
+        ("pak1-foo.ads", """generic
+package pak1.foo is
+end pak1.foo;
+"""),
+        ("test_118.ads", """with pak1.foo;
+package Test_118 is
+   package pak3 is
+      foo: integer;
+   end pak3;
+   use pak3;
+
+   package new_pak1 is new pak1;
+   use new_pak1;
+
+   x: integer := foo;       -- ERROR: foo hidden by use clauses
+end Test_118;
+"""),))
+
+# As long as 24:14 is detected, it inhibits detection of 25:21.
+check_reports_error_but_forgets_one (
+    bug = 276224,
+    make = ("gnatmake", "test_121"),
+    regex = "test_121\.adb:25:21: dynamically tagged expression not allowed",
+    sources = (
+        ("test_121.adb", """--  If the expected type for an expression or name is some specific
+--  tagged type, then the expression or name shall not be dynamically
+--  tagged unless it is a controlling operand in a call on a
+--  dispatching operation.
+procedure Test_121 is
+   package pak1 is
+      type T1 is tagged null record;
+      function f1 (x1: T1) return T1;
+   end pak1;
+
+   package body pak1 is
+      function f1 (x1: T1) return T1 is
+      begin
+         return x1;
+      end;
+   end pak1;
+   use pak1;
+
+   type T2 is record
+      a1: T1;
+   end record;
+
+   z0: T1'class := T1'(null record);
+   z1: T1 := f1(z0);           -- ERROR: gnat correctly rejects
+   z2: T2 := (a1 => f1(z0));   -- ERROR: gnat mistakenly allows
+begin
+   null;
+end Test_121;
+"""),))
+
+check_reports_an_error_but_should_not (
+    bug = 276227,
+    make = ("gnatmake", "test_124"),
+    regex = 'test_124\.ads:6:35: size for "T_arr_constrained" too small, minimum allowed is 256',
+    sources = (
+        ("test_124.ads", """package Test_124 is
+   type T is range 1 .. 32;
+   type T_arr_unconstrained is array (T range <>) of boolean;
+   type T_arr_constrained is new T_arr_unconstrained (T);
+   pragma pack (T_arr_unconstrained);
+   for T_arr_constrained'size use 32;
+end Test_124;
+"""),))
+
+check_reports_an_error_but_should_not (
+    bug = 278687,
+    make = ("gnatmake", "test_127"),
+    regex = 'test_127\.adb:1.:21: expected type "T2" defined at line .',
+    sources = (
+        ("test_127.ads", """-- The second parameter of T2'Class'Read is of type T2'Class,
+-- which should match an object of type T3, which is derived
+-- from T2.
+package test_127 is
+   pragma elaborate_body;
+end test_127;
+"""),
+        ("test_127.adb", """with ada.streams;
+package body test_127 is
+   type T1 is access all ada.streams.root_stream_type'class;
+   type T2 is tagged null record;
+   type T3 is new T2 with null record;
+
+   x: T1;
+   y: T3;
+begin
+   T2'class'read(x, y);
+end test_127;
+""")))
+
+check_compiles_but_should_not (
+    bug = 278831,
+    make = ("gnatmake", "test_128"),
+    sources = (
+        ("test_128.ads", """package Test_128 is
+   package inner is
+   private
+      type T1;
+   end inner;
+   type T1_ptr is access inner.T1; -- line  9 ERROR: gnat mistakenly accepts
+end Test_128;
+"""),
+        ("test_128.adb", """package body test_128 is
+   package body inner is
+      type T1 is new Integer;
+   end inner;
+end Test_128;
+""")))
+
+# Note that we also check the absence of the next inhibited message.
+check_reports_an_error_but_should_not (
+    bug = 279893,
+    make = ("gnatmake", "test_129"),
+    regex = """^gcc-[0-9.]+ -c test_129\.ads
+test_129\.ads:1.:49: designated type of actual does not match that of formal "T2"
+test_129\.ads:1.:49: instantiation abandoned
+gnatmake: "test_129\.ads" compilation error$""",
+    sources = (
+        ("pak1.ads", """-- legal instantiation rejected; illegal instantiation accepted
+-- adapted from John Woodruff c.l.a. post
+
+generic
+   type T1 is private;
+package pak1 is
+   subtype T3 is T1;
+end pak1;
+"""),
+        ("pak2.ads", """with pak1;
+generic
+   type T2 is private;
+package pak2 is
+   package the_pak1 is new pak1 (T1 => T2);
+end pak2;
+"""),
+        ("pak2-pak3.ads", """generic
+   type T2 is access the_pak1.T3;
+package pak2.pak3 is
+end pak2.pak3;
+"""),
+        ("test_129.ads", """with pak1;
+with pak2.pak3;
+package Test_129 is
+
+   type T4 is null record;
+   type T5 is null record;
+   subtype T3 is T5; -- line 9: triggers the bug at line 16
+
+   type T4_ptr is access T4;
+   type T5_ptr is access T5;
+
+   package new_pak2 is new pak2 (T2 => T4);
+   package new_pak3a is new new_pak2.pak3(T2 => T4_ptr);  -- line 15: Legal
+   package new_pak3b is new new_pak2.pak3(T2 => T5_ptr);  -- line 16: Illegal
+end Test_129;
+""")))
+
+print ("# Please ignore the gnatlink message.")
+check_reports_an_error_but_should_not (
+    bug = 280939,
+    make = ("gnatmake", "test_130"),
+    regex = "test_130\.adb:\(\.text\+0x5\): undefined reference to \`p2\'",
+    sources = (
+        ("pak1.ads", """--  RM 10.1.5(4) "the pragma shall have an argument that is a name
+--  denoting that declaration."
+--  RM 8.1(16) "The children of a parent library unit are inside the
+--  parent's declarative region."
+
+package pak1 is
+   pragma Pure;
+end pak1;
+"""),
+        ("pak1-p2.ads", """procedure pak1.p2;
+pragma Pure (p2);          -- ERROR: need expanded name
+pragma Import (ada, p2);   -- ERROR: need expanded name
+pragma Inline (p2);        -- ERROR: need expanded name
+"""),
+        ("test_130.adb", """with Pak1.P2;
+procedure Test_130 is
+begin
+   Pak1.P2;
+end Test_130;
+""")))
+
+check_compiles_but_should_not (
+    bug = 283833,
+    make = ("gnatmake", "test_132"),
+    sources = (
+        ("pak1.ads", """-- RM 8.5.4(5)  the convention of the renamed subprogram shall not
+-- be Intrinsic, if the renaming-as-body completes that declaration
+-- after the subprogram it declares is frozen.
+
+-- RM 13.14(3)  the end of the declaration of a library package
+-- causes freezing of each entity declared within it.
+
+-- RM 6.3.1(7)  the default calling convention is Intrinsic for
+-- any other implicitly declared subprogram unless it is a
+-- dispatching operation of a tagged type.
+
+package pak1 is
+   type T1 is null record;
+   procedure p1 (x1: T1);
+   type T2 is new T1;
+end pak1;
+"""),
+        ("pak1.adb", """package body Pak1 is
+   procedure P1 (X1 : T1) is begin null; end P1;
+end Pak1;
+"""),
+        ("test_132.ads", """with pak1;
+package Test_132 is
+   procedure p2 (x2: pak1.T2);
+end Test_132;
+"""),
+        ("test_132.adb", """package body Test_132 is
+   procedure p2 (x2: pak1.T2) renames pak1.p1; --ERROR: can't rename intrinsic
+end Test_132;
+""")))
+
+check_compiles_but_should_not (
+    bug = 283835,
+    make = ("gnatmake", "test_133"),
+    sources = (
+        ("test_133.ads", """package Test_133 is
+   package pak1 is
+      type T1 is null record;
+   end pak1;
+
+   package pak2 is
+      subtype boolean is standard.boolean;
+      function "=" (x, y: pak1.T1) return boolean;
+   end pak2;
+
+   use pak1, pak2;
+
+   x1: pak1.T1;
+   b1: boolean := x1 /= x1;  -- ERROR: ambigous  (gnat misses)
+   --  b2: boolean := x1 = x1;   -- ERROR: ambigous
+end Test_133;
+"""),
+        ("test_133.adb", """package body test_133 is
+   package body pak2 is
+      function "=" (x, y: pak1.T1) return boolean is
+      begin
+         return true;
+      end "=";
+   end pak2;
+end test_133;
+""")))
+
+check_compiles_but_should_not (
+    bug = 416979,
+    make = ("gnatmake", "pak1"),
+    sources = (
+        ("pak1.ads", """package pak1 is
+   -- RM 7.3(13), 4.9.1(1)
+   -- check that discriminants statically match
+   type T1(x1: integer) is tagged null record;
+   x2: integer := 2;
+   x3: constant integer := x2;
+   type T2 is new T1 (x2) with private;
+   type T3 is new T1 (x3) with private;
+private
+   type T2 is new T1 (x2) with null record;  --ERROR: nonstatic discriminant
+   type T3 is new T1 (x3) with null record;  --ERROR: nonstatic discriminant
+end pak1;
+"""),))
+
+# Once the bug box disappears, check the executable.
+# check_produces_a_faulty_executable (
+check_reports_an_error_but_should_not (
+    bug = 427108,
+    make = ("gnatmake", "test1"),
+#     regex = "FAILED",
+    regex = "Program_Error exp_disp.adb:7842 explicit raise",
+    sources = (
+        ("test1.adb", """-- "For the execution of a call on an inherited subprogram,
+-- a call on the corresponding primitive subprogram of the
+-- parent or progenitor type is performed; the normal conversion
+-- of each actual parameter to the subtype of the corresponding
+-- formal parameter (see 6.4.1) performs any necessary type
+-- conversion as well."
+
+with Text_IO; use Text_IO;
+procedure Test1 is
+   package Pak1 is
+      type T1 is tagged null record;
+      function Eq(X, Y: T1) return Boolean renames "=";
+   end Pak1;
+
+   package Pak2 is
+      type T2 is new Pak1.T1 with record
+         F1: Integer;
+      end record;
+   end Pak2;
+
+   Z1: Pak2.T2 := (F1 => 1);
+   Z2: Pak2.T2 := (F1 => 2);
+begin
+   if Pak2.Eq(Z1, Z2) = Pak1.Eq(Pak1.T1(Z1), Pak1.T1(Z2))
+      then Put_Line("PASSED");
+      else Put_Line("FAILED");
+   end if;
+end Test1;
+"""),))
+
+check_reports_an_error_but_should_not (
+    bug = 660698,
+    make = ("gnatmake", "proc.adb"),
+    regex = 'proc\.adb:17:28: there is no applicable operator "And" for type "Standard\.Integer"',
+    sources = (
+        ("proc.adb", """procedure Proc is
+   package P1 is
+      type T is new Integer;
+      function "and" (L, R : in Integer) return T;
+   end P1;
+   package body P1 is
+      function "and" (L, R : in Integer) return T is
+         pragma Unreferenced (L, R);
+      begin
+         return 0;
+      end "and";
+   end P1;
+   use type P1.T;
+   package P2 is
+      use P1;
+   end P2;
+   G : P1.T := Integer'(1) and Integer'(2);
+begin
+   null;
+end Proc;
+"""), ))
+
+check_produces_a_faulty_executable (
+    bug = 737225,
+    make = ("gnatmake", "round_decimal"),
+    trigger = "round_decimal",
+    regex = "Bug reproduced.",
+    sources = (
+        ("round_decimal.adb", """with Ada.Text_IO;
+
+procedure Round_Decimal is
+
+   --  OJBECTIVE:
+   --    Check that 'Round of a decimal fixed point type does round
+   --    away from zero if the operand is of a decimal fixed point
+   --    type with a smaller delta.
+
+   Unexpected_Compiler_Bug : exception;
+
+   type Milli is delta 0.001 digits 9;
+   type Centi is delta 0.01 digits 9;
+
+   function Rounded (Value : Milli) return Centi;
+   --  Value, rounded using Centi'Round
+
+   function Rounded (Value : Milli) return Centi is
+   begin
+      return Centi'Round (Value);
+   end Rounded;
+
+begin
+   --  Operands used directly:
+   if not (Milli'Round (0.999) = Milli'(0.999)
+             and
+           Centi'Round (0.999) = Centi'(1.0)
+             and
+           Centi'Round (Milli'(0.999)) = Centi'(1.0))
+   then
+      raise Unexpected_Compiler_Bug;
+   end if;
+   if Rounded (Milli'(0.999)) /= Centi'(1.0) then
+      Ada.Text_IO.Put_Line ("Bug reproduced.");
+   end if;
+end Round_Decimal;
+"""),))
+
+# Even if an error is reported, the problem with the atomic variable
+# should be checked.
+check_reports_an_error_but_should_not (
+    bug = 643663,
+    make = ("gnatmake", "test"),
+    regex = 'test\.adb:4:25: no value supplied for component "Reserved"',
+    sources = (
+        ("pkg.ads", """package Pkg is
+   type Byte is mod 2**8;
+   type Reserved_24 is mod 2**24;
+
+   type Data_Record is
+      record
+         Data : Byte;
+         Reserved : Reserved_24;
+      end record;
+
+   for Data_Record use
+      record
+         Data at 0 range 0 .. 7;
+         Reserved at 0 range 8 .. 31;
+      end record;
+
+   for Data_Record'Size use 32;
+   for Data_Record'Alignment use 4;
+
+   Data_Register : Data_Record;
+   pragma Atomic (Data_Register);
+end Pkg;
+"""), ("test.adb", """with Pkg;
+procedure Test is
+begin
+   Pkg.Data_Register := (
+      Data => 255,
+      others => <> -- expected error: no value supplied for component "Reserved"
+   );
+end Test;
+""")))
+
+try:
+    os.rmdir (workspace)
+except:
+    print ("Some unconfirmed, not removing directory {}.".format (workspace))
--- gcc-6-6.4.0.orig/debian/ada/debian_packaging.mk
+++ gcc-6-6.4.0/debian/ada/debian_packaging.mk
@@ -0,0 +1,91 @@
+# Common settings for Ada Debian packaging.
+#
+#  Copyright (C) 2012-2014 Nicolas Boulenguez <nicolas@debian.org>
+#
+#  This program is free software: you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation, either version 3 of the
+#  License, or (at your option) any later version.
+#  This program is distributed in the hope that it will be useful, but
+#  WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+#  General Public License for more details.
+#  You should have received a copy of the GNU General Public License
+#  along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+# dpkg-dev (>= 1.16.1) provides /usr/share/dpkg/default.mk (or the
+# more specific buildflags.mk) to set standard variables like
+# DEB_HOST_MULTIARCH, CFLAGS, LDFLAGS...) according to the build
+# environment (DEB_BUILD_OPTIONS...) and the policy (hardening
+# flags...).
+# You must include it before this file.
+ifeq (,$(findstring /usr/share/dpkg/buildflags.mk,$(MAKEFILE_LIST)))
+  $(error Please include /usr/share/dpkg/default.mk (or the more specific \
+          buildflags.mk) before $(lastword $(MAKEFILE_LIST)))
+endif
+
+# Ada is not in dpkg-dev flag list. We add a sensible default here.
+
+# Format checking is meaningless for Ada sources.
+ADAFLAGS := $(filter-out -Wformat -Werror=format-security, $(CFLAGS))
+
+ifdef DPKG_EXPORT_BUILDFLAGS
+  export ADAFLAGS
+endif
+
+# Avoid dpkg-shlibdeps warning about depending on a library from which
+# no symbol is used, see http://wiki.debian.org/ToolChain/DSOLinking.
+# Gnatmake users must upgrade to >= 4.6.4-1 to circumvent #680292.
+LDFLAGS += -Wl,--as-needed
+
+# Warn during build time if undefined symbols.
+LDFLAGS += -Wl,-z,defs
+
+ifdef DPKG_EXPORT_BUILDFLAGS
+  export LDFLAGS
+endif
+
+######################################################################
+# C compiler version
+
+# GCC binaries must be compatible with GNAT at the binary level, use
+# the same version. This setting is mandatory for every upstream C
+# compilation ("export CC" is enough for dh_auto_configure with a
+# normal ./configure).
+
+CC := gnatgcc
+
+######################################################################
+# Options for gprbuild/gnatmake.
+
+# Let Make delegate parallelism to gnatmake/gprbuild.
+.NOTPARALLEL:
+
+# Use all processors unless parallel=n is set in DEB_BUILD_OPTIONS.
+# http://www.debian.org/doc/debian-policy/ch-source.html#s-debianrules-options
+BUILDER_JOBS := $(filter parallel=%,$(DEB_BUILD_OPTIONS))
+ifneq (,$(BUILDER_JOBS))
+  BUILDER_JOBS := $(subst parallel=,,$(BUILDER_JOBS))
+else
+  BUILDER_JOBS := $(shell getconf _NPROCESSORS_ONLN)
+endif
+BUILDER_OPTIONS += -j$(BUILDER_JOBS)
+
+BUILDER_OPTIONS += -R
+# Avoid lintian warning about setting an explicit library runpath.
+# http://wiki.debian.org/RpathIssue
+
+BUILDER_OPTIONS += -v
+# Make exact command lines available for automatic log checkers.
+
+BUILDER_OPTIONS += -eS
+# Tell gnatmake to echo commands to stdout instead of stderr, avoiding
+# buildds thinking it is inactive and killing it.
+# -eS is the default on gprbuild.
+
+# You may be interested in
+# -s  recompile if compilation switches have changed
+#     (bad default because of interactions between -amxs and standard library)
+# -we handle warnings as errors
+# -vP2 verbose when parsing projects.
--- gcc-6-6.4.0.orig/debian/bin-wrapper.in
+++ gcc-6-6.4.0/debian/bin-wrapper.in
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+# some build tools are linked with a new libstdc++ and fail to run
+# when building libstdc++.
+
+if [ -n "$LD_LIBRARY_PATH" ]; then
+  ma=$(dpkg-architecture -qDEB_BUILD_MULTIARCH)
+  export LD_LIBRARY_PATH="/lib/$ma:/usr/lib/$ma:/lib:/usr/lib:$LD_LIBRARY_PATH"
+fi
+
+exec /usr/bin/$(basename $0) "$@"
--- gcc-6-6.4.0.orig/debian/changelog
+++ gcc-6-6.4.0/debian/changelog
@@ -0,0 +1,3202 @@
+gcc-6 (6.4.0-13ubuntu1) bionic; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 12 Mar 2018 16:55:32 +0100
+
+gcc-6 (6.4.0-13) unstable; urgency=medium
+
+  * Update to SVN 20180312 (r258446) from the gcc-6-branch.
+    - S/390: Disable branch prediction.
+    - Fix PR libstdc++/84671, PR libstdc++/81797, PR libstdc++/83833,
+      PR target/PR84295 (S390), PR c/84310, PR target/79747, PR other/80589,
+      PR gcov-profile/84137, PR gcov-profile/83879, PR rtl-optimization/82675,
+      PR c/84229, PR ipa/81360, PR target/83790 (NVPTX), PR target/82096,
+      PR target/84154 (PPC), PR target/83758 (PPC), PR target/84089 (PA),
+      PR bootstrap/84017, PR target/83370 (AArch64), PR tree-optimization/82726,
+      PR tree-optimization/70754, PR bootstrap/80867, PR target/84033 (PPC),
+      PR target/83399 (PPC), PR target/83862 (PPC), PR c++/84686, PR c++/84489,
+      PR c++/71784, PR c++/84441, PR c++/84520, PR c++/84151, PR fortran/56667,
+      PR fortran/71085, PR fortran/78990, PR fortran/83633, PR fortran/30792,
+      PR fortran/84506, PR fortran/84511, PR fortran/84346, PR fortran/68560,
+      PR fortran/35299, PR fortran/54223, PR fortran/84276, PR fortran/82994,
+      PR fortran/82049, PR lto/81440, PR ipa/81360, PR lto/81004,
+      PR lto/83954, PR lto/83954, PR target/83984 (PA), PR debug/77844,
+      PR ipa/82352, PR gcov-profile/82633, PR gcov-profile/82457, PR c++/84785,
+      PR fortran/84734, PR fortran/64124, PR fortran/70409.
+
+  [ Aurelien Jarno ]
+  * Configure s390x build with --with-arch=z196 on Debian.
+
+  [ Matthias Klose ]
+  * Fix cross-building libgnat on armel, when not building the common libraries.
+
+  [ Moritz Muehlenhoff ]
+  * Backport of retpoline support by H.J. Lu.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 12 Mar 2018 16:52:57 +0100
+
+gcc-6 (6.4.0-12ubuntu1) bionic; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 23 Jan 2018 22:58:25 +0100
+
+gcc-6 (6.4.0-12) unstable; urgency=medium
+
+  * Update to SVN 20180223 (r256971) from the gcc-6-branch.
+    - Fix PR c/81875, PR libstdc++/83834, PR libstdc++/83626,
+      PR libstdc++/83600, PR libstdc++/83598, PR libstdc++/83279,
+      PR libstdc++/79283, PR libstdc++/59568, PR target/81485 (SH),
+      PR target/80870 (SH), PR rtl-optimization/83424, PR target/83677 (PPC),
+      PR target/82975 (ARM), PR target/66488, PR target/80210 (PPC),
+      PR c++/83301, PR c++/78692, PR fortran/83900, PR fortran/83900,
+      PR fortran/80768, PR fortran/83874, PR fortran/78814, PR fortran/82367,
+      PR fortran/83093, PR fortran/82841, PR fortran/83679, PR fortran/83650,
+      PR libgfortran/83649, PR libgfortran/81937.
+  * Move the .gox files into the gccgo packages. Addresses: #883136.
+  * Fix shlibs search path for mips64 cross targets. Addresses: #883988.
+  * libffi: mips/n32.S: disable .set mips4 on mips r6 (YunQiang Su).
+  * debian/rules2: Fix typo for N32 conditions (YunQiang Su).
+    Addresses: #886316.
+  * Install the msa.h header for mips targets (YunQiang Su). Addresses: #887066.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 23 Jan 2018 13:41:09 +0100
+
+gcc-6 (6.4.0-11ubuntu1) bionic; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 13 Nov 2017 10:36:43 +0100
+
+gcc-6 (6.4.0-11) unstable; urgency=medium
+
+  * Update to SVN 20171206 (r255440) from the gcc-6-branch.
+    - Fix PR target/82941 (x86), PR target/82942 (x86), PR target/82990 (x86),
+      PR 81288/target (PPC), PR rtl-optimization/82621, PR fortran/82934,
+      PR fortran/78619.
+  * Update the Linaro support to the 6.4-2017.11 snapshot.
+  * Fix mipsr6 typos. Closes: #881621.
+  * Don't build mips r6 packages on old releases (YunQiang Su). Closes: #881610.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 06 Dec 2017 10:23:53 +0100
+
+gcc-6 (6.4.0-10ubuntu1) bionic; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 13 Nov 2017 10:36:43 +0100
+
+gcc-6 (6.4.0-10) unstable; urgency=medium
+
+  * Update to SVN 20171112 (r254663) from the gcc-6-branch.
+    - Fix PR target/82772 (alpha), PR rtl-optimization/64682,
+      PR rtl-optimization/69567, PR rtl-optimization/69737,
+      PR rtl-optimization/82683, PR fortran/78641, PR fortran/69739,
+      PR fortran/82796, PR fortran/81735, PR fortran/78293,
+      PR fortran/80554.
+  * Bump libunwind (build-)dependency for ia64. Addresses: #879959.
+  * gcj-6: Depend on gcc-6. Addresses: #855640.
+  * Add support for a plethora of mips r6 architectures (YunQiang Su).
+    Closes: #881575.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 13 Nov 2017 10:08:07 +0100
+
+gcc-6 (6.4.0-9ubuntu1) bionic; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 26 Oct 2017 11:25:24 +0200
+
+gcc-6 (6.4.0-9) unstable; urgency=medium
+
+  * Update to SVN 20171026 (r254099) from the gcc-6-branch.
+    - Fix PR target/82274 (x86), PR rtl-optimization/82602,
+      PR rtl-optimization/82549, PR libstdc++/81395, PR target/82445 (ARM),
+      PR fortran/79795, PR fortran/79402, PR fortran/81048, PR libfortran/82233.
+  * Update the Linaro support to the 6.4-2017.10 snapshot.
+  * Do the extra/optional dance ...
+  * Override hardening-no-pie flags for compiler executables.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 26 Oct 2017 11:19:43 +0200
+
+gcc-6 (6.4.0-8ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 10 Oct 2017 14:29:12 +0200
+
+gcc-6 (6.4.0-8) unstable; urgency=medium
+
+  * Update to SVN 20171010 (r253582) from the gcc-6-branch.
+    - Fix PR libstdc++/60936, PR tree-optimization/82337,
+      PR target/81996 (PPC), PR target/71951 (AArch64).
+  * Fix builds without hppa64 cross compiler and new debhelper. See: #877589.
+  * Fix build dependency on realpath. Closes: #877818.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 10 Oct 2017 13:59:13 +0200
+
+gcc-6 (6.4.0-7ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 20 Sep 2017 13:46:18 +0200
+
+gcc-6 (6.4.0-7) unstable; urgency=medium
+
+  * Update to SVN 20170920 (r253004) from the gcc-6-branch.
+    - Fix PR c++/81314, PR c/81687, PR c/45784, PR libquadmath/65757,
+      PR libstdc++/60936, PR target/82112 (PPC), PR c++/81355 (x86),
+      PR tree-optimization/81977, PR tree-optimization/82084,
+      PR middle-end/81505, PR middle-end/81768, PR c/81687,
+      PR middle-end/81766, PR target/81621 (S390), PR middle-end/81052,
+      PR middle-end/79499, PR target/81225 (x86), PR tree-opt/79987,
+      PR sanitizer/81224.
+  * Fix fortran cross compiler build with debhelper 10.9. See: #876246.
+  * Bump binutils dependency to 2.29.1 for sid/buster.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 20 Sep 2017 11:34:45 +0200
+
+gcc-6 (6.4.0-6ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 15 Sep 2017 12:33:23 +0200
+
+gcc-6 (6.4.0-6) unstable; urgency=medium
+
+  * Update to SVN 20170915 (r252799) from the gcc-6-branch.
+    - Fix PR target/81833 (PPC), PR target/82181 (xtensa),
+      PR tree-optimization/81987, PR other/39851, PR ipa/81128,
+      PR inline-asm/82001, PR c++/81355, PR tree-opt/81696, PR ipa/81128.
+  * Fix PR sanitizer/81066, taken from the gcc-7-branch.
+  * Fix libjava build failure with glibc-2.26.
+  * Update the Linaro support to the 6.4-2017.09 snapshot.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 15 Sep 2017 12:30:51 +0200
+
+gcc-6 (6.4.0-5ubuntu3) artful; urgency=medium
+
+  * Fix PR sanitizer/81066, taken from the gcc-7-branch.
+  * Fix libjava build failure with glibc-2.26.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 06 Sep 2017 18:10:47 +0200
+
+gcc-6 (6.4.0-5ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 06 Sep 2017 11:25:30 +0200
+
+gcc-6 (6.4.0-5) unstable; urgency=medium
+
+  * Update to SVN 20170906 (r251754) from the gcc-6-branch.
+    - Fix PR libstdc++/79820, PR libstdc++/81751, PR libstdc++/53984,
+      PR libstdc++/81017, PR c++/82039, PR libstdc++/81891, PR libstdc++/81599,
+      PR libstdc++/81338, PR target/81593 (PPC), PR target/81170 (PPC),
+      PR target/81295 (PPC), PR target/81170, PR target/81295, PR driver/81523,
+      PR c++/80287, PR target/80210 (PPC), PR target/81910 (AVR),
+      PR fortran/81770, PR tree-optimization/81503.
+  * Update the Linaro support to the 6.4-2017.08 snapshot.
+  * Default to PIE on powerpc again, now that PR target/81170 and
+    PR target/81295 are fixed. Closes: #856224.
+  * Bump standards version.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 06 Sep 2017 11:12:57 +0200
+
+gcc-6 (6.4.0-4ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 20 Aug 2017 17:27:57 +0200
+
+gcc-6 (6.4.0-4) unstable; urgency=medium
+
+  * Update to SVN 20170820 (r251205) from the gcc-6-branch.
+    - Fix PR target/81894 (x86), PR target/81861 (x86),
+      PR tree-optimization/81354, PR c++/71570.
+  * Don't build the gc enabled libobjc for cross compilers. Closes: #872301.
+  * Fix hangs w/ asan binaries on arm64 (Dann Frazier). LP: #1709727.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 20 Aug 2017 17:23:10 +0200
+
+gcc-6 (6.4.0-3ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 05 Aug 2017 10:49:52 -0400
+
+gcc-6 (6.4.0-3) unstable; urgency=medium
+
+  * Update to SVN 20170805 (r250889) from the gcc-6-branch.
+    - Fix PR lto/81487, PR target/81641 (x86), PR sanitizer/81604,
+      PR target/81414 (AArch64), PR tree-optimization/81555,
+      PR tree-optimization/81556, PR target/79883 (AVR), PR target/67353 (AVR),
+      PR target/81305 (AVR), PR target/81407 (AVR), PR lto/81487,
+      PR tree-optimization/81162, PR rtl-optimization/75964,
+      PR target/80569 (x86).
+  * Don't run the testsuite on the kfreebsd and hurd buildds, hangs.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 05 Aug 2017 10:26:43 -0400
+
+gcc-6 (6.4.0-2ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 24 Jul 2017 15:31:51 +0200
+
+gcc-6 (6.4.0-2) unstable; urgency=medium
+
+  * Update to SVN 20170724 (r250470) from the gcc-6-branch.
+    - Fix PR libstdc++/80316, PR target/80929 (AVR), PR target/80103 (PPC),
+      PR target/80101 (PPC), PR target/81375 (x86), PR target/81300 (x86),
+      PR tree-optimization/81192, PR target/81471 (x86).
+  * Don't configure powerpc with --enable-default-pie, fails to build.
+    See #856224, PR target/81295.
+  * Update the Linaro support to the 6.3-2017.07 snapshot.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 24 Jul 2017 10:37:10 +0200
+
+gcc-6 (6.4.0-1ubuntu2) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 04 Jul 2017 17:03:56 +0200
+
+gcc-6 (6.4.0-1) unstable; urgency=medium
+
+  * GCC 6.4.0 release.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 04 Jul 2017 16:59:17 +0200
+
+gcc-6 (6.3.0-21ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 28 Jun 2017 19:43:19 +0200
+
+gcc-6 (6.3.0-21) unstable; urgency=medium
+
+  * Fix Replaces attribute for the liblto_plugin move from cpp to gcc.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 28 Jun 2017 19:34:28 +0200
+
+gcc-6 (6.3.0-20) unstable; urgency=medium
+
+  * Update to SVN 20170628 (r249732) from the gcc-6-branch (6.4.0 RC).
+    - Fix PR c++/81130, PR libgomp/80822, PR middle-end/80809,
+      PR middle-end/80809, PR middle-end/80853, PR rtl-optimization/73650,
+      PR target/61729 (PPC), PR target/77850 (PPC), PR rtl-optimization/60818,
+      PR target/80382 (PPC), PR rtl-optimization/80429, PR middle-end/80692,
+      PR target/80618 (PPC), PR target/80966 (PPC), PR middle-end/80902,
+      PR tree-optimization/79552, PR tree-optimization/43434, PR target/79155,
+      PR other/80909, PR ipa/80663, PR ipa/79849, PR ipa/79850, PR driver/31468,
+      PR other/80589, PR gcov-profile/53915, PR driver/56469, PR lto/69953,
+      PR lto/78049, PR middle-end/80809, PR middle-end/80809,
+      PR middle-end/80853, PR tree-optimization/80453, PR middle-end/80341,
+  * 
+
+ -- Matthias Klose <doko@x1>  Wed, 06 Dec 2017 14:56:25 +0100
+
+gcc-6 (6.4.0-10ubuntu1) bionic; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 13 Nov 2017 10:36:43 +0100
+
+gcc-6 (6.4.0-10) unstable; urgency=medium
+
+  * Update to SVN 20171112 (r254663) from the gcc-6-branch.
+    - Fix PR target/82772 (alpha), PR rtl-optimization/64682,
+      PR rtl-optimization/69567, PR rtl-optimization/69737,
+      PR rtl-optimization/82683, PR fortran/78641, PR fortran/69739,
+      PR fortran/82796, PR fortran/81735, PR fortran/78293,
+      PR fortran/80554.
+  * Bump libunwind (build-)dependency for ia64. Addresses: #879959.
+  * gcj-6: Depend on gcc-6. Addresses: #855640.
+  * Add support for a plethora of mips r6 architectures (YunQiang Su).
+    Closes: #881575.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 13 Nov 2017 10:08:07 +0100
+
+gcc-6 (6.4.0-9ubuntu1) bionic; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 26 Oct 2017 11:25:24 +0200
+
+gcc-6 (6.4.0-9) unstable; urgency=medium
+
+  * Update to SVN 20171026 (r254099) from the gcc-6-branch.
+    - Fix PR target/82274 (x86), PR rtl-optimization/82602,
+      PR rtl-optimization/82549, PR libstdc++/81395, PR target/82445 (ARM),
+      PR fortran/79795, PR fortran/79402, PR fortran/81048, PR libfortran/82233.
+  * Update the Linaro support to the 6.4-2017.10 snapshot.
+  * Do the extra/optional dance ...
+  * Override hardening-no-pie flags for compiler executables.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 26 Oct 2017 11:19:43 +0200
+
+gcc-6 (6.4.0-8ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 10 Oct 2017 14:29:12 +0200
+
+gcc-6 (6.4.0-8) unstable; urgency=medium
+
+  * Update to SVN 20171010 (r253582) from the gcc-6-branch.
+    - Fix PR libstdc++/60936, PR tree-optimization/82337,
+      PR target/81996 (PPC), PR target/71951 (AArch64).
+  * Fix builds without hppa64 cross compiler and new debhelper. See: #877589.
+  * Fix build dependency on realpath. Closes: #877818.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 10 Oct 2017 13:59:13 +0200
+
+gcc-6 (6.4.0-7ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 20 Sep 2017 13:46:18 +0200
+
+gcc-6 (6.4.0-7) unstable; urgency=medium
+
+  * Update to SVN 20170920 (r253004) from the gcc-6-branch.
+    - Fix PR c++/81314, PR c/81687, PR c/45784, PR libquadmath/65757,
+      PR libstdc++/60936, PR target/82112 (PPC), PR c++/81355 (x86),
+      PR tree-optimization/81977, PR tree-optimization/82084,
+      PR middle-end/81505, PR middle-end/81768, PR c/81687,
+      PR middle-end/81766, PR target/81621 (S390), PR middle-end/81052,
+      PR middle-end/79499, PR target/81225 (x86), PR tree-opt/79987,
+      PR sanitizer/81224.
+  * Fix fortran cross compiler build with debhelper 10.9. See: #876246.
+  * Bump binutils dependency to 2.29.1 for sid/buster.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 20 Sep 2017 11:34:45 +0200
+
+gcc-6 (6.4.0-6ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 15 Sep 2017 12:33:23 +0200
+
+gcc-6 (6.4.0-6) unstable; urgency=medium
+
+  * Update to SVN 20170915 (r252799) from the gcc-6-branch.
+    - Fix PR target/81833 (PPC), PR target/82181 (xtensa),
+      PR tree-optimization/81987, PR other/39851, PR ipa/81128,
+      PR inline-asm/82001, PR c++/81355, PR tree-opt/81696, PR ipa/81128.
+  * Fix PR sanitizer/81066, taken from the gcc-7-branch.
+  * Fix libjava build failure with glibc-2.26.
+  * Update the Linaro support to the 6.4-2017.09 snapshot.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 15 Sep 2017 12:30:51 +0200
+
+gcc-6 (6.4.0-5ubuntu3) artful; urgency=medium
+
+  * Fix PR sanitizer/81066, taken from the gcc-7-branch.
+  * Fix libjava build failure with glibc-2.26.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 06 Sep 2017 18:10:47 +0200
+
+gcc-6 (6.4.0-5ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 06 Sep 2017 11:25:30 +0200
+
+gcc-6 (6.4.0-5) unstable; urgency=medium
+
+  * Update to SVN 20170906 (r251754) from the gcc-6-branch.
+    - Fix PR libstdc++/79820, PR libstdc++/81751, PR libstdc++/53984,
+      PR libstdc++/81017, PR c++/82039, PR libstdc++/81891, PR libstdc++/81599,
+      PR libstdc++/81338, PR target/81593 (PPC), PR target/81170 (PPC),
+      PR target/81295 (PPC), PR target/81170, PR target/81295, PR driver/81523,
+      PR c++/80287, PR target/80210 (PPC), PR target/81910 (AVR),
+      PR fortran/81770, PR tree-optimization/81503.
+  * Update the Linaro support to the 6.4-2017.08 snapshot.
+  * Default to PIE on powerpc again, now that PR target/81170 and
+    PR target/81295 are fixed. Closes: #856224.
+  * Bump standards version.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 06 Sep 2017 11:12:57 +0200
+
+gcc-6 (6.4.0-4ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 20 Aug 2017 17:27:57 +0200
+
+gcc-6 (6.4.0-4) unstable; urgency=medium
+
+  * Update to SVN 20170820 (r251205) from the gcc-6-branch.
+    - Fix PR target/81894 (x86), PR target/81861 (x86),
+      PR tree-optimization/81354, PR c++/71570.
+  * Don't build the gc enabled libobjc for cross compilers. Closes: #872301.
+  * Fix hangs w/ asan binaries on arm64 (Dann Frazier). LP: #1709727.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 20 Aug 2017 17:23:10 +0200
+
+gcc-6 (6.4.0-3ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 05 Aug 2017 10:49:52 -0400
+
+gcc-6 (6.4.0-3) unstable; urgency=medium
+
+  * Update to SVN 20170805 (r250889) from the gcc-6-branch.
+    - Fix PR lto/81487, PR target/81641 (x86), PR sanitizer/81604,
+      PR target/81414 (AArch64), PR tree-optimization/81555,
+      PR tree-optimization/81556, PR target/79883 (AVR), PR target/67353 (AVR),
+      PR target/81305 (AVR), PR target/81407 (AVR), PR lto/81487,
+      PR tree-optimization/81162, PR rtl-optimization/75964,
+      PR target/80569 (x86).
+  * Don't run the testsuite on the kfreebsd and hurd buildds, hangs.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 05 Aug 2017 10:26:43 -0400
+
+gcc-6 (6.4.0-2ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 24 Jul 2017 15:31:51 +0200
+
+gcc-6 (6.4.0-2) unstable; urgency=medium
+
+  * Update to SVN 20170724 (r250470) from the gcc-6-branch.
+    - Fix PR libstdc++/80316, PR target/80929 (AVR), PR target/80103 (PPC),
+      PR target/80101 (PPC), PR target/81375 (x86), PR target/81300 (x86),
+      PR tree-optimization/81192, PR target/81471 (x86).
+  * Don't configure powerpc with --enable-default-pie, fails to build.
+    See #856224, PR target/81295.
+  * Update the Linaro support to the 6.3-2017.07 snapshot.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 24 Jul 2017 10:37:10 +0200
+
+gcc-6 (6.4.0-1ubuntu2) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 04 Jul 2017 17:03:56 +0200
+
+gcc-6 (6.4.0-1) unstable; urgency=medium
+
+  * GCC 6.4.0 release.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 04 Jul 2017 16:59:17 +0200
+
+gcc-6 (6.3.0-21ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 28 Jun 2017 19:43:19 +0200
+
+gcc-6 (6.3.0-21) unstable; urgency=medium
+
+  * Fix Replaces attribute for the liblto_plugin move from cpp to gcc.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 28 Jun 2017 19:34:28 +0200
+
+gcc-6 (6.3.0-20) unstable; urgency=medium
+
+  * Update to SVN 20170628 (r249732) from the gcc-6-branch (6.4.0 RC).
+    - Fix PR c++/81130, PR libgomp/80822, PR middle-end/80809,
+      PR middle-end/80809, PR middle-end/80853, PR rtl-optimization/73650,
+      PR target/61729 (PPC), PR target/77850 (PPC), PR rtl-optimization/60818,
+      PR target/80382 (PPC), PR rtl-optimization/80429, PR middle-end/80692,
+      PR target/80618 (PPC), PR target/80966 (PPC), PR middle-end/80902,
+      PR tree-optimization/79552, PR tree-optimization/43434, PR target/79155,
+      PR other/80909, PR ipa/80663, PR ipa/79849, PR ipa/79850, PR driver/31468,
+      PR other/80589, PR gcov-profile/53915, PR driver/56469, PR lto/69953,
+      PR lto/78049, PR middle-end/80809, PR middle-end/80809,
+      PR middle-end/80853, PR tree-optimization/80453, PR middle-end/80341,
+      PR middle-end/80281, PR tree-optimization/79256,
+      PR tree-optimization/69264, PR tree-optimization/69823, PR target/80718,
+      PR target/80510, PR target/68163, PR target/71778, PR c++/80241,
+      PR c++/80244, PR sanitizer/80348, PR sanitizer/80348, PR c++/81154,
+      PR c++/80973, PR c++/80984, PR c++/70844, PR fortran/80918.
+  * Fix PR target/79041, aarch64 backend emitting R_AARCH64_ADR_PREL_PG_HI21
+    relocation despite -mpc-relative-literal-loads option being used.
+  * Move the liblto_plugin from the cpp to the gcc package.
+  * libstdc++6: Add more Breaks to smoothen upgrades from jessie to stretch.
+    Closes: #863845, #863745.
+  * Don't provide libobjc_gc symlinks for the libobjc multilib packages.
+    Closes: #866150.
+  * Configure with --enable-default-pie on ppc64 (Adrian Glaubitz) and
+    powerpc (Mathieu Malaterre).  Closes: #856224.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 28 Jun 2017 13:53:40 +0200
+
+gcc-6 (6.3.0-19ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 20 Jun 2017 15:59:28 +0200
+
+gcc-6 (6.3.0-19) unstable; urgency=medium
+
+  * Update to SVN 20170618 (r249347) from the gcc-6-branch.
+    - Fix PR libstdc++/80504, PR libstdc++/80493, PR libstdc++/80448,
+      PR libstdc++/80137, PR libstdc++/67440, PR libstdc++/69699,
+      PR libstdc++/71444, PR libstdc++/78236, PR target/80799 (x86),
+      PR sanitizer/80166, PR libgcc/80037, PR gcov-profile/78783,
+      PR sanitizer/80350, PR middle-end/79931, PR ipa/65972, PR lto/50345,
+      PR gcov-profile/78783, PR gcov-profile/80413, PR ipa/80212,
+      PR sanitizer/70878, PR gcov-profile/80224, PR ipa/80205, PR ipa/80104,
+      PR c++/80179, PR c++/80267, PR c++/60992, PR c++/80294,
+      PR libstdc++/81002, PR c/81006, PR rtl-optimization/80474,
+      PR target/80968, PR c++/81011, PR fortran/70601, PR fortran/65542,
+      PR fortran/80904, PR ada/80921.
+  * Update the Linaro support to the 6.3-2017.05 snapshot.
+  * Fix libmpx dependency generation for cross builds.
+  * Stop building packages now built by gcc-7.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 18 Jun 2017 16:21:31 +0200
+
+gcc-6 (6.3.0-18ubuntu2) artful; urgency=medium
+
+  * Update to SVN 20170519 (r248302) from the gcc-6-branch.
+    - Fix PR libstdc++/80504, PR libstdc++/80493, PR libstdc++/80448,
+      PR libstdc++/80137, PR libstdc++/67440, PR libstdc++/69699,
+      PR libstdc++/71444, PR libstdc++/78236, PR target/80799 (x86).
+  * Update the Linaro support to the 6.3-2017.05 snapshot.
+  * Starting with 17.10, enable PIE on armhf, arm64 and i386.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 19 May 2017 12:22:57 -0700
+
+gcc-6 (6.3.0-18ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+  * Update the Linaro support to the 6.3-2017.05 snapshot.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 16 May 2017 11:56:34 -0700
+
+gcc-6 (6.3.0-18) unstable; urgency=medium
+
+  * Update to SVN 20170516 (r248076) from the gcc-6-branch.
+    - Revert fix for PR middle-end/80222.
+    - Fix PR target/80090 (PA), PR target/79027 (PA), PR go/64238,
+      PR fortran/80752.
+  * Install crtfastmath.o and re-add unwind support on kfreebsd-amd64 (James
+    Clarke). Closes: #833829.
+  * Work around #814977 (gnat calling gcc-6-6) by providing a gcc-6-6
+    symlink.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 16 May 2017 08:59:32 -0700
+
+gcc-6 (6.3.0-17ubuntu1) artful; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 10 May 2017 15:56:32 +0200
+
+gcc-6 (6.3.0-17) unstable; urgency=medium
+
+  * Update to SVN 20170510 (r247831) from the gcc-6-branch.
+    - Fix PR target/77728 (ARM), PR target/68491 (x86), PR fortran/80392,
+      PR libgomp/80394, PR c/79940, PR c++/79572, PR c++/79641, PR c/80097,
+      PR c++/79512, PR rtl-optimization/80501, PR sanitizer/80349,
+      PR rtl-optimization/80385, PR libgomp/80394, PR c++/80297, PR debug/80321,
+      PR target/80286 (x86), PR debug/79255, PR debug/80025, PR sanitizer/80168,
+      PR rtl-optimization/80112, PR c++/80129, PR sanitizer/79944,
+      PR target/79932 (x86), PR target/79932 (x86), PR c/79940,
+      PR rtl-optimization/79901, PR target/79807 (x86), PR c++/79681,
+      PR target/79729 (x86), PR middle-end/79396, PR target/79570,
+      PR target/79494 (x86), PR target/79568 (x86), PR target/79559 (x86),
+      PR c++/80363, PR c++/80176, PR c++/79572, PR c++/80141, PR c++/79896,
+      PR c++/79664, PR c++/79639, PR c++/79512, PR middle-end/80075,
+      PR plugin/80094, PR tree-optimization/80113, PR tree-optimization/80122,
+      PR tree-optimization/80167, PR tree-optimization/80170,
+      PR middle-end/80171, PR middle-end/80222, PR tree-optimization/80262,
+      PR tree-optimization/80275, PR tree-optimization/80334,
+      PR middle-end/80362, PR tree-optimization/80492, PR middle-end/80539,
+      PR middle-end/71310, PR bootstrap/71510.
+  * Fix dependency on gcc-base package for rtlibs stage build (Helmut Grohne).
+  * Remove libquadmath/gdtoa license from debian/copyright (files removed).
+  * Build libgo when not building common libs.
+  * Fix PR rtl-optimization/60818, taken from the trunk (Adrian Glaubitz).
+    Closes: #861945.
+  * Fix building libgfortran, libgphobos and libmpx when building without
+    common libs.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 10 May 2017 13:13:01 +0200
+
+gcc-6 (6.3.0-16ubuntu6) artful; urgency=medium
+
+  * Update to SVN 20170506 (r247720) from the gcc-6-branch.
+    - Fix PR target/77728 (ARM), PR target/68491 (x86), PR fortran/80392,
+      PR libgomp/80394, PR c/79940, PR c++/79572, PR c++/79641, PR c/80097,
+      PR c++/79512, PR rtl-optimization/80501, PR sanitizer/80349,
+      PR rtl-optimization/80385, PR libgomp/80394, PR c++/80297, PR debug/80321,
+      PR target/80286 (x86), PR debug/79255, PR debug/80025, PR sanitizer/80168,
+      PR rtl-optimization/80112, PR c++/80129, PR sanitizer/79944,
+      PR target/79932 (x86), PR target/79932 (x86), PR c/79940,
+      PR rtl-optimization/79901, PR target/79807 (x86), PR c++/79681,
+      PR target/79729 (x86), PR middle-end/79396, PR target/79570,
+      PR target/79494 (x86), PR target/79568 (x86), PR target/79559 (x86),
+      PR c++/80363, PR c++/80176, PR c++/79572, PR c++/80141, PR c++/79896,
+      PR c++/79664, PR c++/79639, PR c++/79512.
+  * Fix dependency on gcc-base package for rtlibs stage build (Helmut Grohne).
+  * Remove libquadmath/gdtoa license from debian/copyright (files removed).
+  * Stop building packages now built by the gcc-7 source.
+  * Fix PR rtl-optimization/60818, taken from the trunk (Adrian Glaubitz).
+    Closes: #861945.
+  * Fix building libgfortran, libgphobos and libmpx when building without
+    common libs.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 07 May 2017 09:21:42 +0200
+
+gcc-6 (6.3.0-16) unstable; urgency=medium
+
+  * Update to SVN 20170425 (r247223) from the gcc-6-branch.
+    - Fix PR tree-optimization/80426, PR target/80462 (AVR),
+      PR target/79453 (AVR), PR fortran/80361.
+  * libstdc++6: add Breaks: libsigc++-2.0-0c2a (<= 2.4.1-1+b1). Closes: #861060.
+  * Fix PR middle-end/80533 (wrong code), taken from the trunk. LP: #1685385.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 30 Apr 2017 15:47:47 +0700
+
+gcc-6 (6.3.0-14ubuntu3) artful; urgency=medium
+
+  * debian/rules.patch: Disable ignore-pie-specs-when-not-enabled on Ubuntu.
+
+ -- Adam Conrad <adconrad@ubuntu.com>  Tue, 25 Apr 2017 13:55:59 -0600
+
+gcc-6 (6.3.0-14ubuntu2) artful; urgency=medium
+
+  * debian/rules.conf: Update rules to make artful behave like zesty.
+
+ -- Adam Conrad <adconrad@ubuntu.com>  Thu, 20 Apr 2017 18:40:26 -0600
+
+gcc-6 (6.3.0-14ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 18 Apr 2017 08:47:36 +0630
+
+gcc-6 (6.3.0-14) unstable; urgency=medium
+
+  * Re-upload as -14 to undo the reproducible builds upload.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 17 Apr 2017 20:19:55 +0630
+
+gcc-6 (6.3.0-13) unstable; urgency=medium
+
+  * Update to SVN 20170415 (r246940) from the gcc-6-branch.
+    - Fix PR target/45053 (PPC), PR target/80376 (PPC), PR target/80315 (PPC),
+      PR ipa/77333, PR target/78002 (AArch64), PR target/79733 (x86),
+      PR target/80298 (x86), PR c++/80150, PR c++/77563, PR c++/79519,
+      PR c++/79640, PR c++/80043, PR c++/78282, PR c++/79607, PR c++/79566,
+      PR c++/79580, PR c++/79508, PR c++/79050, PR c++/79461.
+  * Fix PR go/77857, gccgo vendoring. Taken from the trunk. Closes: #839598.
+  * libstdc++6: add Breaks: libopencv-core2.4. Closes: #859914.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 15 Apr 2017 23:34:35 +0200
+
+gcc-6 (6.3.0-12ubuntu2) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 07 Apr 2017 14:21:56 +0200
+
+gcc-6 (6.3.0-12) unstable; urgency=medium
+
+  * Update to SVN 20170406 (r246741) from the gcc-6-branch.
+    - Fix PR libstdc++/79141, PR libstdc++/80137, PR libstdc++/62045,
+      PR c++/79548, PR target/80082 (ARM), PR target/79947 (PPC),
+      PR tree-optimization/80218, PR target/80246 (PPC), PR target/80123 (PPC),
+      PR target/71294 (PPC), PR tree-optimization/78644,
+      PR tree-optimization/80181, PR sanitizer/80067, PR target/78543 (PPC),
+      PR target/80180 (x86), PR lto/66295, PR lto/79587, PR lto/66295,
+      PR target/79906 (PPC), PR gcov-profile/80081, PR middle-end/79753,
+      PR ipa/79769, PR c/79770, PR middle-end/79831, PR target/79892,
+      PR middle-end/78339, PR target/65705 (x86), PR target/69804 (x86,
+      closes: #812255), PR tree-optimization/79631, PR ipa/79761, PR lto/79760,
+      PR tree-optimization/79803, PR rtl-optimization/79574,
+      PR rtl-optimization/79574, PR rtl-optimization/79577, PR sanitizer/71458,
+      PR target/79951 (PPC), PR c++/80091, PR ada/80117, PR fortran/71838,
+      PR fortran/79676, PR fortran/79434.
+  * Re-add the fix for PR c++/72813, taken from the trunk, and accidentally
+    removed when updating the branch. Closes: #837162.
+  * Fix PR demangler/70909, libiberty demangler segfaults. CVE-2016-4491.
+  * Bump binutils version requirement.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 06 Apr 2017 23:49:46 +0200
+
+gcc-6 (6.3.0-11) unstable; urgency=medium
+
+  * Fix PR target/78543 (PPC), taken from the gcc-6-branch. Closes: #856809.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 29 Mar 2017 00:17:25 +0200
+
+gcc-6 (6.3.0-10ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 21 Mar 2017 16:30:53 +0100
+
+gcc-6 (6.3.0-10) unstable; urgency=medium
+
+  * Update to SVN 20170321 (r246313) from the gcc-6-branch.
+    - Fix PR libstdc++/79980, PR libstdc++/80041, PR libstdc++/79980,
+      PR libstdc++/79511, PR target/71017 (x86).
+
+  [ Matthias Klose ]
+  * Update the Linaro support to the 6.3-2017.03 snapshot.
+  * Address PR c++/80091, reverting r246134. Closes: #858261.
+
+  [ Nicolas Boulenguez ]
+  * Reactive the ada-gcc-name patch, calling the versioned gcc.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 21 Mar 2017 16:29:17 +0100
+
+gcc-6 (6.3.0-9ubuntu2) zesty; urgency=medium
+
+  * Update the Linaro support to the 6.3-2017.03 snapshot.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 17 Mar 2017 18:49:54 +0100
+
+gcc-6 (6.3.0-9ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 16 Mar 2017 14:59:50 +0100
+
+gcc-6 (6.3.0-9) unstable; urgency=medium
+
+  * Update to SVN 20170316 (r246188) from the gcc-6-branch.
+    - Fix PR target/79261 (PPC), PR fortran/78474, PR libstdc++/79789,
+      PR target/79514 (x86), PR target/79544 (PPC), PR lto/79579,
+      PR target/79749 (sparc), PR target/79261 (PPC), PR fortran/78474,
+      PR fortran/78331, PR target/77850 (PA), PR target/79439 (PPC),
+      PR c++/79796, PR ada/79903, PR ada/79945, PR libstdc++/80034,
+      PR c++/79962, PR c++/79984, PR c/79756, PR tree-optimization/79732,
+      PR target/80019 (x86), PR target/79752 (PPC), PR middle-end/80004,
+      PR target/49244 (x86), PR tree-optimization/79977, PR middle-end/79971,
+      PR tree-optimization/79666, PR middle-end/79576, PR c++/72775,
+      PR c++/79900, PR c++/79687, PR c++/79264, PR c++/61636, PR fortran/79894.
+  * gcj-6: Fix ecj1 symlink on i386. Closes: #856903.
+  * Fix libcc1.so symlink for cross compilers. Addresses: #856875.
+  * dpkg-buildflags stopped fiddling around with spec files; remove
+    the code removing and warning about dpkg's specs.
+  * libstdc++6: Add break for libopenmpi1.6. Closes: #854881.
+  * Fix symlinks to man pages in the hppa64 package. Closes: #857583.
+  * Don't ship the gnatgcc manpage symlink when building GFDL packages.
+    Closes: #857384.
+  * Install the gcov-dump utility.
+  * Allow to use lld with -fuse-ld=ld.lld.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 16 Mar 2017 14:25:48 +0100
+
+gcc-6 (6.3.0-8ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 21 Feb 2017 15:05:42 +0100
+
+gcc-6 (6.3.0-8) unstable; urgency=medium
+
+  * Update to SVN 20170221 (r245621) from the gcc-6-branch.
+    - Fix ICEs PR middle-end/79537, PR sanitizer/79558, PR middle-end/79536.
+  * Fix ecj1 symlink for gcj cross compiler packages. Addresses: #855640.
+  * Bump binutils version requirement.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 21 Feb 2017 14:54:53 +0100
+
+gcc-6 (6.3.0-7) unstable; urgency=medium
+
+  * Update to SVN 20170218 (r245414) from the gcc-6-branch.
+    - Fix PR target/78945 (ARM), PR translation/79397,
+      PR tree-optimization/71824, PR tree-optimization/71824,
+      PR tree-optimization/77318, PR target/71017 (x86), PR c++/78897,
+      PR c++/78908, PR c++/79296 (closes: #854692), PR sanitizer/79562,
+      PR libstdc++/79114, PR libstdc++/59170, PR libstdc++/59161,
+      PR libstdc++/72792, PR libstdc++/72792, PR libstdc++/72793,
+      PR libstdc++/69321, PR libstdc++/69301, PR libstdc++/79114,
+      PR libstdc++/78702, PR libstdc++/78134, PR libstdc++/78273,
+      PR c/79431, PR target 79545 (PPC), PR target/76731 (x86), PR c/79428,
+      PR tree-optimization/79411, PR c/79431, PR middle-end/79399,
+      PR tree-optimization/79338, PR target/79197 (PPC), PR target/79079,
+      PR tree-optimization/79267, PR target/79495 (x86), PR c/79471,
+      PR c++/79429, PR c/79431, PR c++/79377.
+  * Update the Linaro support to the 6.3-2017.02 snapshot.
+  * Fix target architecture for sparc non-multilib builds (Adrian Glaubitz).
+    Closes: #855197.
+  * Bump binutils version requirement.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 18 Feb 2017 10:00:36 +0100
+
+gcc-6 (6.3.0-6ubuntu2) zesty; urgency=medium
+
+  * Update to SVN 20170211 (r245353) from the gcc-6-branch.
+    - Fix PR target/78945 (ARM), PR translation/79397,
+      PR tree-optimization/71824, PR tree-optimization/71824,
+      PR tree-optimization/77318, PR target/71017 (x86), PR c++/78897.
+  * Update the Linaro support to the 6.3-2017.02 snapshot.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 11 Feb 2017 02:13:55 +0100
+
+gcc-6 (6.3.0-6) unstable; urgency=medium
+
+  * Update to SVN 20170205 (r245197) from the gcc-6-branch.
+    - Fix PR libstdc++/78346, PR libstdc++/79195, PR libstdc++/79254,
+      PR target/78478, PR target/79268 (PPC, LP: #1661051), PR c++/79176,
+      PR middle-end/78742, PR target/77439 (ARM32), PR tree-optimization/79034,
+      PR fortran/70697, PR fortran/70696, PR fortran/79305, PR go/79037,
+      PR go/79281 (closes: #853223), PR target/78862 (tilegx), PR lto/79061,
+      PR target/65484 (PPC).
+
+  [ Aurelien Jarno ]
+  * Don't use disable madd4 on MIPS big-endian.
+  * Disable lxc1/sxc1 instruction on mips and mipsel.
+
+  [ Matthias Klose ]
+  * Configure with --enable-default-pie on sparc and sparc64 (James Clark).
+    Closes: #854090.
+  * Configure with --enable-default-pie on kfreebsd-* (Steven Chamberlain).
+  * Configure staged builds with --disable-libmpx (Helmut Grohne).
+    Closes: #854159.
+  * Fix suffix'd gnat binary names (Svante Signell). Closes: #814978.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 05 Feb 2017 21:16:42 +0100
+
+gcc-6 (6.3.0-5ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 24 Jan 2017 18:17:14 +0100
+
+gcc-6 (6.3.0-5) unstable; urgency=medium
+
+  * Update to SVN 20170124 (r244868) from the gcc-6-branch.
+    - Fix PR lto/69188, PR go/78763, PR target/78478 (RTEMS).
+  * Fix removing the RUNPATH from the asan, tsan, ubsan, cilkrts, gfortran
+    and gphobos runtime libraries.
+  * Let the gnatgcc symlinks point to the versioned names. Closes: #839209.
+  * Backport patches to disable madd4 instructions on mips* targets and
+    disable these by default (YunQiang Su). Closes. #852153.
+  * Update multiarch builds for a new sh3 target. Closes: #851869.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 24 Jan 2017 14:48:12 +0100
+
+gcc-6 (6.3.0-4ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 21 Jan 2017 21:35:25 +0100
+
+gcc-6 (6.3.0-4) unstable; urgency=medium
+
+  * Update to SVN 20170121 (r244748) from the gcc-6-branch.
+    - Fix PR target/77455 (AArch64), PR rtl-optimization/79121, PR ipa/79043,
+      PR ipa/71207, PR tree-optimization/72488, PR c++/77545, PR c++/77284.
+  * Fix gdc cross build.
+  * Fix symlinks to unprefixed man pages. Closes: #851886.
+  * Fix PR go/79037, proposed golang patch (John Paul Adrian Glaubitz).
+    Closes: #852091.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 21 Jan 2017 18:51:03 +0100
+
+gcc-6 (6.3.0-3ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 18 Jan 2017 22:18:31 +0100
+
+gcc-6 (6.3.0-3) unstable; urgency=medium
+
+  * Update to SVN 20170118 (r244586) from the gcc-6-branch.
+    - Fix PR tree-optimization/71055 (closes: #849032), PR driver/78863,
+      PR translation/78745, PR tree-optimization/78886,
+      PR tree-optimization/78428, PR libstdc++/78956, PR libstdc++/78991,
+      PR rtl-optimization/78255, PR target/78041 (ARM), PR pch/78970,
+      PR lto/79042, PR target/78900 (PPC), PR tree-optimization/78024,
+      PR sanitizer/65479 (PPC), PR c++/77812, PR libstdc++/78389,
+      PR libstdc++/78389, PR debug/78839, PR rtl-optimization/78617,
+      PR target/78253 (ARM), PR target/79044 (PPC), PR c++/78341, PR c++/78949,
+      PR c++/78693, PR c++/71182, PR fortran/78866, PR middle-end/50199.
+  * Always configure sparc builds --with-cpu-32=ultrasparc (James Clark).
+    Closes: #850250.
+  * Enable gccgo on m68k (John Paul Adrian Glaubitz). Closes: #850749.
+  * Reapply the fix for PR target/55947, and fix PR c++/72813, taken from
+    the trunk.
+  * Fix PR target/79044 (PPC), ICE (Bill Schmidt). Closes: #850777.
+  * Don't add the configured prefix to libcc1's compiler name.
+    Closes: #851146.
+  * Update the Linaro support to the 6.3-2017.01 snapshot.
+  * Apply the header changes for PR libstdc++/64735 on armel as well,
+    conditionalized to keep the headers unchanged for other architectures.
+    Closes: #851273.
+  * Install the unprefixed man pages for gcc-ar, -nm and ranlib.
+    Closes: #851698.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 18 Jan 2017 20:02:20 +0100
+
+gcc-6 (6.3.0-2ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 31 Dec 2016 06:18:31 +0100
+
+gcc-6 (6.3.0-2) unstable; urgency=medium
+
+  * Update gdc-driver-nophobos patch.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 31 Dec 2016 06:10:49 +0100
+
+gcc-6 (6.3.0-1) unstable; urgency=medium
+
+  * GCC 6.3.0 release.
+  * Update to SVN 20161229 (r243959) from the gcc-6-branch.
+    - Fix PR c/77767, PR ipa/77905, PR translation/78922, PR fortran/78239.
+
+  [ Matthias Klose ]
+  * Backport proposed patch for PR libstdc++/64735. Closes: #727621.
+  * Configure --with-cpu-32=ultrasparc on sparc. Closes: #845461.
+  * Update gdc to the GCC-6 branch (20161222).
+  * Don't mark libphobos multilib packages as M-A: same.
+  * Configure libphobos builds with --with-target-system-zlib.
+  * Stop applying PR c++/77379.
+  * Fix ignoring dpkg's pie specs when pie is not enabled (James Clarke).
+    Closes: #849542.
+  * Apply proposed patch for PR rtl-optimization/65618. Addresses: #781457.
+  * Bump requirement on binutils to 2.27.90 (gold now implementing -z bndplt).
+
+  [ Samuel Thibault ]
+  * libgo fixup for program invocation name.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 31 Dec 2016 04:46:10 +0100
+
+gcc-6 (6.2.1-7ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 15 Dec 2016 22:50:24 +0100
+
+gcc-6 (6.2.1-7) unstable; urgency=medium
+
+  * GCC 6.3.0 release candidate.
+  * Update to SVN 20161215 (r243686, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/78465, PR c++/78761, PR c++/78252, PR target/59874,
+      PR target/78796, PR tree-optimization/77673, PR target/72717 (PPC),
+      PR rtl-optimization/71496, PR c++/78701.
+  * Drop build dependency on g++-5.
+  * Fix PR c++/78774, proposed for the gcc-6-branch.
+  * Apply patches for zlib security issues CVE-2016-9840, CVE-2016-9841,
+    CVE-2016-9842, CVE-2016-9843.
+  * Ignore dpkg's pie specs when pie is not enabled. Addresses: #848129.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 15 Dec 2016 22:43:42 +0100
+
+gcc-6 (6.2.1-6ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 12 Dec 2016 17:17:23 +0100
+
+gcc-6 (6.2.1-6) unstable; urgency=high
+
+  * Update to SVN 20161212 (r243558, 6.2.1) from the gcc-6-branch.
+    - Fix PR target/78426 (SH), PR fortran/78500, PR target/78101 (PPC),
+      PR target/48863 (ARM32), PR inline-asm/70184, PR libstdc++/71856,
+      PR libstdc++/77459, PR libstdc++/78326, PR libstdc++/51960,
+      PR target/57438 (x86), PR target/77933 (ARM), PR c++/78550,
+      PR tree-optimization/78542, PR tree-optimization/78482, PR c++/71848,
+      PR middle-end/71762, PR tree-optimization/71575, PR bootstrap/78188,
+      PR tree-optimization/78224, PR tree-optimization/77646, PR target/77957,
+      PR middle-end/78540, PR rtl-optimization/78546, PR fortran/78298,
+      PR middle-end/69183, PR middle-end/78416, PR middle-end/67335,
+      PR middle-end/78419, PR rtl-optimization/78378, PR fortran/78299,
+      PR target/77834, PR target/78227, PR target/77834,
+      PR rtl-optimization/77919, PR rtl-optimization/77919, PR middle-end/78025,
+      PR fortran/77973, PR sanitizer/66343, PR fortran/77665,
+      PR middle-end/77624, PR target/77587, PR tree-optimization/78646,
+      PR target/72827, PR c++/78551, PR c++/78649, PR c++/72808, PR c++/77591,
+      PR c++/77739, PR c++/77285, PR c++/78089, PR c++/77467, PR c++/77722,
+      PR c++/77638, PR c++/77637, PR c++/77482, PR c++/77375, PR c++/71274,
+      PR c++/71515, PR c++/77907, PR c++/57728, PR fortran/78593,
+      PR fortran/77666, PR fortran/78443, PR libstdc++/70975,
+      PR libstdc++/71337, PR libstdc++/78111, PR rtl-optimization/77309,
+      PR target/77904 (ARM32).
+
+  [ Matthias Klose ]
+  * Fix dependency generation for libgphobos multilib builds.
+  * Install missing vecintrin.h header on s390x.
+  * Fix PR target/77267 (x86), taken from the trunk.
+  * Use --push-state/--pop-state for gold as well when linking libtsan.
+  * Fix the configure check for compressed debug section support in as and ld.
+    Enables the -gz option again. Taken from the trunk.
+  * In GCC ICE dumps, prefix each line with the PID of the driver.
+  * Stop ignoring the bootstrap comparison failures on mips targets now that
+    these are release architectures.
+
+  [ Svante Signell ]
+  * GNU/Hurd port for gccgo.
+
+  [ Iain Buclaw ]
+  * Use needsCodegen rather than isRoot for determining the static/extern of a
+    template symbol. Closes: #845377.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 12 Dec 2016 16:53:57 +0100
+
+gcc-6 (6.2.1-5ubuntu2) zesty; urgency=medium
+
+  * Update to SVN 20161202 (r243204, 6.2.1) from the gcc-6-branch.
+    - Fix PR target/78426 (SH), PR fortran/78500, PR target/78101 (PPC),
+      PR target/48863 (ARM32), PR inline-asm/70184.
+  * Fix dependency generation for libgphobos multilib builds.
+  * Install missing vecintrin.h header on s390x.
+  * Fix PR target/77267 (x86), taken from the trunk. LP: #1623418.
+  * Use --push-state/--pop-state for gold as well when linking libtsan.
+  * Fix the configure check for compressed debug section support in as and ld.
+    Enables the -gz option again. Taken from the trunk.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 02 Dec 2016 23:22:52 +0100
+
+gcc-6 (6.2.1-5ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 24 Nov 2016 13:36:19 +0100
+
+gcc-6 (6.2.1-5) unstable; urgency=medium
+
+  * Update to SVN 20161124 (r242827, 6.2.1) from the gcc-6-branch.
+    - Fix PR target/77822 (AArch64), PR fortran/58001, PR fortran/69741,
+      PR libstdc++/78490, PR lto/78472, PR middle-end/78305, PR ipa/78309,
+      PR middle-end/78333, PR tree-optimization/78228, PR middle-end/78185,
+      PR tree-optimization/77855, PR fortran/66227, PR fortran/78297,
+      PR middle-end/78429.
+  * Don't apply the ada patches for stage builds.
+  * Add pkg-config to the build dependencies.
+  * Drop the work around for PR libstdc++/65913.
+  * gdc: Link with the shared libgphobos runtime by default. Closes: #845377.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 24 Nov 2016 12:41:33 +0100
+
+gcc-6 (6.2.1-4ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 19 Nov 2016 12:39:00 +0100
+
+gcc-6 (6.2.1-4) unstable; urgency=medium
+
+  * Update to SVN 20161119 (r242621, 6.2.1) from the gcc-6-branch.
+    - Fix PR c++/67631.
+  * Build the GC enabled libobjc using the system libgc when available
+  * Always apply *all* the gnat patches whether or not gnat is built.
+  * Bump debhelper compat level to 9.
+  * Mark libgphobos symbols changing with the file location (sic!) as optional.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 19 Nov 2016 15:52:25 +0100
+
+gcc-6 (6.2.1-3) unstable; urgency=medium
+
+  * Build-depend on binutils (>= 2.27.51.20161118), required for sparc64.
+  * Always apply the gnat patches whether or not gnat is built.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 18 Nov 2016 16:34:00 +0100
+
+gcc-6 (6.2.1-2ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 18 Nov 2016 14:03:09 +0100
+
+gcc-6 (6.2.1-2) unstable; urgency=medium
+
+  * Update to SVN 20161118 (r242586, 6.2.1) from the gcc-6-branch.
+    - Fix PR c++/68377.
+  * Add Replaces for renamed lib*gphobos-dev packages.
+  * libphobos: Fix ARM32 multilib detection for system zlib.
+  * Update libgphobos symbols files for ARM32 targets.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 18 Nov 2016 13:32:28 +0100
+
+gcc-6 (6.2.1-1ubuntu2) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 17 Nov 2016 13:26:20 +0100
+
+gcc-6 (6.2.1-1) unstable; urgency=medium
+
+  * Update to SVN 20161116 (r241998, 6.2.1) from the gcc-6-branch.
+    - Fix PR sanitizer/78294, PR target/78310 (x86), PR target/77822 (s390x),
+      PR target/78262 (x86).
+  * Update gdc to the GCC-6 branch (20161116).
+  * Update libasan symbol files.
+  * Build libgfortran libraries when building without common libs.
+  * Avoid warning for libgcc symbols files.
+  * Add symbols for libobjc_gc library.
+  * Build shared phobos runtime libraries (not yet enabled by default).
+
+ -- Matthias Klose <doko@debian.org>  Thu, 17 Nov 2016 12:42:56 +0100
+
+gcc-6 (6.2.0-13ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 09 Nov 2016 21:04:13 +0100
+
+gcc-6 (6.2.0-13) unstable; urgency=medium
+
+  * Update to SVN 20161109 (r241998, 6.2.1) from the gcc-6-branch.
+    - Fix PR c/71115, PR target/78229 (closes: #843379),
+      PR tree-optimization/77768, PR c++/78039 (closes: #841316),
+      PR libgcc/78064, PR driver/78206.
+  * Fix using the gcc-6-source package (Stephen Kitt). Closes: #843476.
+  * Fix PR target/77822 (AArch64), taken from the trunk. Closes: #839249.
+  * Fix PR target/77822 (s390x), proposed patch.
+  * Update libiberty to the trunk 20161108. Addresses security issues:
+    CVE-2016-6131, CVE-2016-4493, CVE-2016-4492, CVE-2016-4490,
+    CVE-2016-4489, CVE-2016-4488, CVE-2016-4487, CVE-2016-2226.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 09 Nov 2016 20:42:53 +0100
+
+gcc-6 (6.2.0-11ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 03 Nov 2016 15:27:16 +0100
+
+gcc-6 (6.2.0-11) unstable; urgency=medium
+
+  * Update to SVN 20161103 (r241817, 6.2.1) from the gcc-6-branch.
+    - Fix PR debug/77773, PR middle-end/72747, PR tree-optimization/78047,
+      PR tree-optimization/77879, PR tree-optimization/77839,
+      PR tree-optimization/77745, PR tree-optimization/77648,
+      PR target/78166 (PA), PR rtl-optimization/78038, PR middle-end/78128,
+      PR middle-end/71002, PR fortran/69544, PR fortran/78178,
+      PR fortran/71902, PR fortran/67219, PR fortran/71891, PR lto/78129,
+      PR libgfortran/78123.
+  * Fix symlinks for gcj manual pages. Closes: #842407.
+  * Fix ICE in tree_to_shwi, Linaro issue #2575.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 03 Nov 2016 14:10:24 +0100
+
+gcc-6 (6.2.0-10ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 27 Oct 2016 22:12:20 +0200
+
+gcc-6 (6.2.0-10) unstable; urgency=medium
+
+  * Update to SVN 20161027 (r241619, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/77288, PR libstdc++/77727, PR libstdc++/78052,
+      PR tree-optimization/77550, PR tree-optimization/77916,
+      PR fortran/71895, PR fortran/77763, PR fortran/61420, PR fortran/78013,
+      PR fortran/78021, PR fortran/72832, PR fortran/78092, PR fortran/78108,
+      PR target/78057 (x86), PR target/78037 (x86).
+  * Include go-relocation-test-gcc620-sparc64.obj.uue to fix libgo's
+    debug/elf TestDWARFRelocations test case (James Clark).
+  * Reapply fix for PR c++/71912, apply proposed fix for PR c++/78039.
+    Closes: #841292.
+  * Don't install alternatives for go and gofmt. The preferred way to do that
+    is to install the golang-any package.
+  * For Debian builds, don't enable bind now by default when linking with pie
+    by default.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 27 Oct 2016 15:27:07 +0200
+
+gcc-6 (6.2.0-9) unstable; urgency=medium
+
+  * Regenerate the control file.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 20 Oct 2016 10:46:44 +0200
+
+gcc-6 (6.2.0-8ubuntu1) zesty; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 19 Oct 2016 18:47:57 +0200
+
+gcc-6 (6.2.0-8) unstable; urgency=medium
+
+  * Update to SVN 20161019 (r241346, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/77990, PR target/77991 (x86).
+  * Install arm_fp16.h header on arm* architectures for Linaro builds.
+  * Backport upstream revisions from trunk (James Clark). Closes: #840574.
+    - r240457 (add getrandom for MIPS/SPARC)
+    - r241051 (fix getrandom on sparc64 and clone on sparc*)
+    - r241072 (make rawClone no_split_stack)
+    - r241084 (don't use pt_regs; unnecessary, and seemingly not defined by
+               the included headers on arm64)
+    - r241171 (sparc64 relocations, e1fc2925 in go master, now also in
+               gofrontend/gccgo)
+  * Revert fix for PR c++/71912, causing PR c++/78039. Addresses: #841292.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 19 Oct 2016 08:57:23 +0200
+
+gcc-6 (6.2.0-7ubuntu11) zesty; urgency=medium
+
+  * Build using the Linaro branch on armhf and arm64.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 18 Oct 2016 09:09:47 +0200
+
+gcc-6 (6.2.0-7) unstable; urgency=medium
+
+  * Update to SVN 20161018 (r241301, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/77987, PR libstdc++/77322, PR libstdc++/72820,
+      PR libstdc++/77994, PR tree-optimization/77937, PR c++/71912,
+      PR tree-optimization/77937, PR tree-optimization/77943,
+      PR bootstrap/77995, PR fortran/77978, PR fortran/77915, PR fortran/77942.
+
+  [ Matthias Klose ]
+  * Backport Mips go closure support, taken from libffi. Closes: #839132.
+  * Configure with --enable-default-pie and pass -z now when pie is enabled;
+    on amd64 arm64 armel armhf i386 mips mipsel mips64el ppc64el s390x.
+    Closes: #835148.
+  * Update the Linaro support to the 6-2016.10 snapshot.
+
+  [ Aurelien Jarno ]
+  * Enable logwatch on mips64el.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 18 Oct 2016 13:53:00 +0200
+
+gcc-6 (6.2.0-6) unstable; urgency=medium
+
+  * Update to SVN 20161010 (r240906, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/68323, PR libstdc++/77794, PR libstdc++/77795,
+      PR libstdc++/77801, PR libgcc/77519, PR target/77756 (x86),
+      PR target/77670 (PPC), PR rtl-optimization/71709, PR c++/77804,
+      PR fortran/41922, PR fortran/60774, PR fortran/61318, PR fortran/68566,
+      PR fortran/69514, PR fortran/69867, PR fortran/69962, PR fortran/70006,
+      PR fortran/71067, PR fortran/71730, PR fortran/71799, PR fortran/71859,
+      PR fortran/71862, PR fortran/77260, PR fortran/77351, PR fortran/77372,
+      PR fortran/77380, PR fortran/77391, PR fortran/77420, PR fortran/77429,
+      PR fortran/77460, PR fortran/77506, PR fortran/77507, PR fortran/77612,
+      PR fortran/77694, PR libgfortran/77707, PR libstdc++/70101,
+      PR libstdc++/77864, PR libstdc++/70564, PR target/77874 (x86),
+      PR target/77759 (sparc), PR fortran/77406, PR fortran/58991,
+      PR fortran/58992.
+  * Really fix gij installation on hppa. Closes: #838111.
+  * Install alternatives for go and gofmt. Closes: #840190.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 10 Oct 2016 05:20:07 +0200
+
+gcc-6 (6.2.0-5ubuntu12) yakkety; urgency=medium
+
+  * Update to SVN 20161005 (r240765, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/68323, PR libstdc++/77794, PR libstdc++/77795,
+      PR libstdc++/77801, PR libgcc/77519, PR target/77756 (x86),
+      PR target/77670 (PPC), PR rtl-optimization/71709, PR c++/77804,
+      PR fortran/41922, PR fortran/60774, PR fortran/61318, PR fortran/68566,
+      PR fortran/69514, PR fortran/69867, PR fortran/69962, PR fortran/70006,
+      PR fortran/71067, PR fortran/71730, PR fortran/71799, PR fortran/71859,
+      PR fortran/71862, PR fortran/77260, PR fortran/77351, PR fortran/77372,
+      PR fortran/77380, PR fortran/77391, PR fortran/77420, PR fortran/77429,
+      PR fortran/77460, PR fortran/77506, PR fortran/77507, PR fortran/77612,
+      PR fortran/77694, PR libgfortran/77707.
+  * Really fix gij installation on hppa. Closes: #838111.
+  * Strip again the compiler binaries.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 05 Oct 2016 09:01:56 +0200
+
+gcc-6 (6.2.0-5ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 28 Sep 2016 15:58:48 +0200
+
+gcc-6 (6.2.0-5) unstable; urgency=medium
+
+  * Update to SVN 20160927 (r240553, 6.2.1) from the gcc-6-branch.
+    - Fix PR sanitizer/77396, PR libstdc++/77645, PR libstdc++/77645,
+      PR target/77326 (AVR), PR target/77349 (PPC), PR middle-end/77594,
+      PR sanitizer/68260, PR fortran/77516, PR target/69255 (x86),
+      PR c++/77553, PR c++/77539, PR fortran/77500, PR c/77450,
+      PR middle-end/77436, PR tree-optimization/77514, PR middle-end/77544,
+      PR tree-optimization/77514, PR middle-end/77605, PR middle-end/77679,
+      PR tree-optimization/77621, PR target/77621 (x86), PR c++/71979.
+  * Fix gij installation on hppa. Closes: #838111.
+  * Fix PR rtl-optimization/71709, taken from the trunk. LP: #1628207.
+  * Apply workaround for PR libstdc++/77686. Addresses: #838438.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 28 Sep 2016 15:53:28 +0200
+
+gcc-6 (6.2.0-4) unstable; urgency=medium
+
+  * Update to SVN 20160914 (r240133, 6.2.1) from the gcc-6-branch.
+    - Fix PR rtl-optimization/77452, PR c++/77427.
+  * gcj: Depend on the ecj1 standalone binary.
+  * Configure native builds using --with-program-prefix.
+  * Fix ICE in gdc symbol mangling (Iain Buclaw). LP: #1620681.
+  * Backport from libffi trunk (Stefan Bühler):
+    - Always check for PaX MPROTECT on linux, make EMUTRAMP experimental.
+    - dlmmap_locked always needs locking as it always modifies execsize.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 15 Sep 2016 19:22:35 +0200
+
+gcc-6 (6.2.0-3ubuntu15) yakkety; urgency=medium
+
+  * Update to SVN 20160914 (r240133, 6.2.1) from the gcc-6-branch.
+    - PR c++/77427.
+  * Fix updating gcj-6-jdk. LP: #1623337.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 14 Sep 2016 13:33:20 +0200
+
+gcc-6 (6.2.0-3ubuntu14) yakkety; urgency=medium
+
+  * Update to SVN 20160910 (r240069, 6.2.1) from the gcc-6-branch.
+    - Fix PR rtl-optimization/77452.
+  * gcj: Depend on the ecj1 standalone binary.
+  * Configure native builds using --with-program-prefix.
+  * Fix ICE in gdc symbol mangling (Iain Buclaw). LP: #1620681.
+  * Restore the AArch64 vulcan support for non Linaro builds.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 11 Sep 2016 12:50:59 +0200
+
+gcc-6 (6.2.0-3ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 04 Sep 2016 13:28:31 +0200
+
+gcc-6 (6.2.0-3) unstable; urgency=medium
+
+  * Update to SVN 20160901 (r239944, 6.2.1) from the gcc-6-branch.
+    - Fix PR fortran/71014, PR libstdc++/77395, PR tree-optimization/72866,
+      PR debug/77363, PR middle-end/77377, PR middle-end/77259,
+      PR target/71910 (cygwin), PR target/77281 (ARM),
+      PR tree-optimization/71077, PR tree-optimization/68542, PR fortran/77352,
+      PR fortran/77374, PR fortran/71014, PR fortran/69281.
+  * Fix setting the stage1 C++ compiler.
+  * gdc: Always link with -ldl when linking with -lgphobos.
+    Closes: #835255, #835757.
+  * Fix building D code with external C++ references.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 04 Sep 2016 12:38:47 +0200
+
+gcc-6 (6.2.0-2ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 31 Aug 2016 12:38:54 +0200
+
+gcc-6 (6.2.0-2) unstable; urgency=medium
+
+  * Update to SVN 20160830 (r239868, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/77334, PR tree-optimization/76783,
+      PR tree-optimization/72851, PR target/72867 (x86), PR middle-end/71700,
+      PR target/77403 (x86), PR target/77270 (x86), PR target/77270 (x86),
+      PR lto/70955, PR target/72863 (PPC), PR tree-optimization/76490,
+      PR fortran/77358.
+  * Call default_file_start from s390_asm_file_start, taken from the trunk.
+  * Update multiarch patches for mips* r6 (YunQiang Su).
+  * Fix install location of D header files for cross builds (YunQiang Su).
+    Closes: #835847.
+  * Fix PR c++/77379, taken from the trunk.
+  * Update the Linaro support to the 6-2016.08 snapshot.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 31 Aug 2016 12:28:38 +0200
+
+gcc-6 (6.2.0-1ubuntu12) yakkety; urgency=medium
+
+  * Update to SVN 20160824 (r239726, 6.2.1) from the gcc-6-branch.
+    - Fix PR libstdc++/77334, PR tree-optimization/76783,
+      PR tree-optimization/72851, PR target/72867 (x86), PR middle-end/71700,
+  * Call default_file_start from s390_asm_file_start, taken from the trunk.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 24 Aug 2016 08:12:10 +0200
+
+gcc-6 (6.2.0-1ubuntu11) yakkety; urgency=medium
+
+  * GCC 6.2 release.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 22 Aug 2016 15:23:46 +0200
+
+gcc-6 (6.2.0-1) unstable; urgency=medium
+
+  * GCC 6.2 release.
+  * Update gdc to the gdc-6 branch 20160822.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 22 Aug 2016 14:15:21 +0200
+
+gcc-6 (6.1.1-12ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 15 Aug 2016 17:56:19 +0200
+
+gcc-6 (6.1.1-12) unstable; urgency=medium
+
+  * GCC 6.2 release candidate 1.
+  * Update to SVN 20160815 (r239482, 6.1.1) from the gcc-6-branch.
+    Fix PR target/71869 (PPC), PR target/72805 (x86), PR target/70677 (AVR),
+    PR c++/72415, PR sanitizer/71042, PR libstdc++/71964, PR libstdc++/70940,
+    PR c/67410, PR c/72816, PR driver/72765, PR debug/71906,
+    PR tree-optimization/73434, PR tree-optimization/72824, PR target/76342,
+    PR target/72843, PR c/71512, PR tree-optimization/71083, PR target/72819,
+    PR target/72853, PR tree-optimization/72824, PR ipa/71981, PR ipa/68273,
+    PR tree-optimization/71881, PR target/72802, PR target/72802,
+    PR rtl-optimization/71976, PR c++/71972, PR c++/72868, PR c++/73456,
+    PR c++/72800, PR c++/68724, PR debug/71906, PR fortran/71936,
+    PR fortran/72698, PR fortran/70524, PR fortran/71795, PR libgfortran/71123,
+    PR libgfortran/73142.
+
+  [ Matthias Klose ]
+  * Fix running the libjava testsuite.
+  * Revert fix for PR target/55947, causing PR libstdc++/72813. LP: #1610220.
+  * Update the Linaro support to the 6-2016.07 snapshot.
+
+  [ Aurelien Jarno ]
+  * Replace proposed fix for PR ipa/68273 by the corresponding patch taken
+    from trunk.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 15 Aug 2016 17:51:10 +0200
+
+gcc-6 (6.1.1-11ubuntu12) yakkety; urgency=medium
+
+  * Update to SVN 20160805 (r239167, 6.1.1) from the gcc-6-branch.
+    Fix PR target/71869 (PPC), PR target/72805 (x86), PR target/70677 (AVR),
+    PR c++/72415.
+
+  * Fix running the libjava testsuite.
+  * Revert fix for PR target/55947, causing PR libstdc++/72813. LP: #1610220.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 05 Aug 2016 15:09:39 +0200
+
+gcc-6 (6.1.1-11ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 03 Aug 2016 21:55:46 +0200
+
+gcc-6 (6.1.1-11) unstable; urgency=medium
+
+  * Update to SVN 20160802 (r238981, 6.1.1) from the gcc-6-branch.
+    - Fix PR target/72767 (AVR), PR target/71151 (AVR), PR c/7652,
+      PR target/71216 (PPC), PR target/72103 (PPC), PR c++/72457, PR c++/71576,
+      PR c++/71833, PR fortran/71883.
+
+  [ Nicolas Boulenguez ]
+  * debian/ada/confirm_debian_bugs.py: Update for GCC 6. Closes: #832799.
+
+  [ Matthias Klose ]
+  * Backport AArch64 Vulcan cost models (Dann Frazier). LP: #1603587.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 03 Aug 2016 21:53:37 +0200
+
+gcc-6 (6.1.1-10ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 24 Jul 2016 20:28:46 +0200
+
+gcc-6 (6.1.1-10) unstable; urgency=medium
+
+  * Update to SVN 20160724 (r238695, 6.1.1) from the gcc-6-branch.
+    - Fix PR libstdc++/71856, PR libstdc++/71320, PR c++/71214,
+      PR sanitizer/71953, PR fortran/71688, PR rtl-optimization/71916,
+      PR debug/71855, PR middle-end/71874, PR target/71493 (PPC),
+      PR rtl-optimization/71634, PR target/71733 (PPC), PR ipa/71624,
+      PR target/71805 (PPC), PR target/70098 (PPC), PR target/71763 (PPC),
+      PR middle-end/71758, PR tree-optimization/71823, PR middle-end/71606,
+      PR tree-optimization/71518, PR target/71806 (PPC), PR target/71720 (PPC),
+      PR middle-end/64516, PR tree-optimization/71264, PR middle-end/71423,
+      PR tree-optimization/71521, PR tree-optimization/71452, PR target/50739,
+      PR tree-optimization/71522, PR c++/55922, PR c++/63151, PR c++/70709,
+      PR c++/70778, PR c++/71738, PR c++/71350, PR c++/71748, PR c++/52746,
+      PR c++/69223, PR c++/71630, PR c++/71913, PR c++/71728, PR c++/71941,
+      PR c++/70822, PR c++/70106, PR c++/67565, PR c++/67579, PR c++/71843,
+      PR c++/70781, PR c++/71896, PR c++/71092, PR c++/71117, PR c++/71495,
+      PR c++/71511, PR c++/71513, PR c++/71604, PR c++/54430, PR c++/71711,
+      PR c++/71814, PR c++/71718, PR c++/70824, PR c++/71909, PR c++/71835,
+      PR c++/71828, PR c++/71822, PR c++/71871, PR c++/70869, PR c++/71054,
+      PR fortran/71807, PR fortran/70842, PR fortran/71764, PR fortran/71623,
+      PR fortran/71783.
+
+  [ Matthias Klose ]
+  * Build-depend on gnat-6 instead of gnat-5 on development distros.
+
+  [ Aurelien Jarno ]
+  * Replace libjava-mips64el-proposed.diff by the corresponding patch
+    taken from trunk.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 24 Jul 2016 19:42:10 +0200
+
+gcc-6 (6.1.1-9ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 05 Jul 2016 15:15:56 +0200
+
+gcc-6 (6.1.1-9) unstable; urgency=medium
+
+  * Update to SVN 20160705 (r237999, 6.1.1) from the gcc-6-branch.
+    - Fix PR fortran/71717, PR libstdc++/71313, PR c/71685, PR c++/71739,
+      PR target/71670 (PPC), PR middle-end/71626, PR target/71559 (x86),
+      PR target/71656 (PPC), PR target/71698 (PPC), PR driver/71651,
+      PR fortran/71687, PR fortran/71704, PR fortran/71705.
+  * Mark cross compilers as M-A: foreign. Addresses: #827136.
+  * On sparc64, configure with --with-cpu-32=ultrasparc, drop the
+    sparc-force-cpu patch. Closes: #809509.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 05 Jul 2016 11:19:50 +0200
+
+gcc-6 (6.1.1-8ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 30 Jun 2016 15:41:06 +0200
+
+gcc-6 (6.1.1-8) unstable; urgency=medium
+
+  * Update to SVN 20160630 (r237878, 6.1.1) from the gcc-6-branch.
+    - Fix PR tree-optimization/71647, PR target/30417 (AVR),
+      PR target/71103 (AVR), PR tree-optimization/71588, PR middle-end/71581,
+      PR c++/71528, PR fortran/70673, PR middle-end/71693.
+
+  [ Aurelien Jarno ]
+  * Apply proposed patch from Matthew Fortune to fix libjava on mips64el.
+
+  [ Matthias Klose ]
+  * Add AArch64 Vulcan cpu support (Dann Frazier). LP: #1594452.
+  * gfortran: Suggest libcoarrays-dev. Closes: #827995.
+  * cpp: Breaks libmagics++-dev (<< 2.28.0-4). Closes: #825278.
+  * Optimize for mips32r2 for o32 (YunQiang Su). Closes: #827801.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 30 Jun 2016 14:12:55 +0200
+
+gcc-6 (6.1.1-7ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 20 Jun 2016 20:27:58 +0200
+
+gcc-6 (6.1.1-7) unstable; urgency=medium
+
+  * Update to SVN 20160620 (r237590, 6.1.1) from the gcc-6-branch.
+    - Fix PR middle-end/71373, PR c/71381, PR libstdc++/71545, PR c/68657,
+      PR sanitizer/71498, PR middle-end/71529, PR target/71103 (AVR),
+      PR target/71554 (x86), PR middle-end/71494, PR c++/71448,
+      PR tree-optimization/71405, PR tree-optimization/71505,
+      PR target/71379 (s390), PR target/71186 (PPC), PR target/70915 (PPC),
+      PR c++/70572, PR c++/71516, PR c/71381.
+  * Fix libgnatprj build to avoid undefined symbols (YunQiang Su).
+    Closes: #826503.
+  * Add build support for tilegx (Helmut Grohne). Closes: #827578.
+  * Drop support for loongson 2f (YunQiang Su). Closes: #827554.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 20 Jun 2016 13:41:44 +0200
+
+gcc-6 (6.1.1-6ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 09 Jun 2016 19:27:27 +0200
+
+gcc-6 (6.1.1-6) unstable; urgency=medium
+
+  * Update to SVN 20160609 (r237267, 6.1.1) from the gcc-6-branch.
+    - Fix PR target/71389 (x86), PR tree-optimization/71259,
+      PR target/70830 (ARM), PR target/67310 (x86), PR c++/71442,
+      PR c++/70847, PR c++/71330, PR c++/71393, PR fortran/69659.
+  * gdc: Fix linking the runtime library. Addresses: #826645.
+  * Fix building libgnatprj on powerpc, and on PIE enabled builds (YunQiang Su).
+    Closes: #826365.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 09 Jun 2016 18:19:42 +0200
+
+gcc-6 (6.1.1-5ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 03 Jun 2016 19:46:59 +0200
+
+gcc-6 (6.1.1-5) unstable; urgency=medium
+
+  * Update to SVN 20160603 (r237075, 6.1.1) from the gcc-6-branch.
+    - Fix PR libstdc++/70762, PR libstdc++/69703, PR libstdc++/69703,
+      PR libstdc++/71038, PR libstdc++/71036, PR libstdc++/71037,
+      PR libstdc++/71005, PR libstdc++/71004, PR libstdc++/70609, PR c/71171,
+      PR middle-end/71279, PR c++/71147, PR c++/71257,
+      PR tree-optimization/70884, PR c++/71210, PR tree-optimization/71031,
+      PR c++/69872, PR c++/71257, PR c++/70344, PR c++/71184, PR fortran/66461,
+      PR fortran/71204, PR libffi/65567, PR c++/71349, PR target/71201,
+      PR middle-end/71371, PR debug/71057, PR target/71056 (ARM32),
+      PR tree-optimization/69068, PR middle-end/71002, PR bootstrap/71071,
+      PR c++/71372, PR c++/70972, PR c++/71166, PR c++/71227, PR c++/60095,
+      PR c++/69515, PR c++/69009, PR c++/71173, PR c++/70522, PR c++/70584,
+      PR c++/70735, PR c++/71306, PR c++/71349, PR c++/71105, PR c++/71147,
+      PR ada/71358, PR ada/71317, PR fortran/71156, PR middle-end/71387.
+  * Fix cross building libgnatprj on i386 targeting 64bit archs (YunQiang Su).
+    Closes: #823126.
+  * Detect hard float for non-linux or non-glibc arm-*-*eabihf builds (Helmut
+    Grohne). Closes: #823894.
+  * Update embedded timestamp setting patch, backported from the trunk.
+  * gccgo: Combine combine gccgo's ld() and ldShared() methods
+    in cmd/go (Michael Hudson-Doyle). LP: #1586872.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 03 Jun 2016 18:58:40 +0200
+
+gcc-6 (6.1.1-4ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 19 May 2016 17:24:36 +0200
+
+gcc-6 (6.1.1-4) unstable; urgency=medium
+
+  * Update to SVN 20160519 (r236478, 6.1.1) from the gcc-6-branch.
+    - Fix PR sanitizer/71160, PR c++/70498, PR target/71161 (x86),
+      PR fortran/70856, PR c++/71100, PR target/71145 (alpha), PR c++/70466,
+      PR target/70860 (nvptx), PR target/70809 (AArch64), PR hsa/70857,
+      PR driver/68463, PR target/70947 (PPC), PR ipa/70760, PR middle-end/70931,
+      PR middle-end/70941, PR tree-optimization/71006, PR target/70830 (ARM),
+      PR fortran/69603, PR fortran/71047, PR fortran/56226, PR ipa/70646.
+  * libgnat{prj,svn}-dev: Don't recommend gnat when building cross compiler
+    packages.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 19 May 2016 18:40:49 +0200
+
+gcc-6 (6.1.1-3ubuntu11) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 12 May 2016 02:33:19 +0200
+
+gcc-6 (6.1.1-3) unstable; urgency=medium
+
+  * Update to SVN 20160511 (r236071, 6.1.1) from the gcc-6-branch.
+    - Fix PR libstdc++/71049, PR middle-end/70877, PR tree-optimization/70876,
+      PR target/70963, PR tree-optimization/70916, PR debug/70935.
+  * Enable gdc for sh4.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 11 May 2016 22:35:33 +0200
+
+gcc-6 (6.1.1-2ubuntu12) yakkety; urgency=medium
+
+  * Fix package replacements with gccgo-6 packages. LP: #1578247, #1578250.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 10 May 2016 14:31:52 +0200
+
+gcc-6 (6.1.1-2) unstable; urgency=medium
+
+  * Update to SVN 20160510 (r236071, 6.1.1) from the gcc-6-branch.
+    - Fix PR tree-optimization/70956, PR sanitizer/70875, PR sanitizer/70342,
+      PR ada/70969, PR ada/70900.
+
+  [ Matthias Klose ]
+  * Call dh_makeshlibs with the --noscripts option when building a
+    cross compiler.
+  * Fix building cross gnat libs when not building the common libs.
+  * Fix building cross mips* multilibs when not building the common libs.
+  * Re-enable gnat build on some architectures for snapshot builds.
+  * Don't build gnat cross compilers on 32bit archs targeting 64bit targets.
+    Addresses: #823126.
+  * Avoid empty architecture lists in build dependencies. Closes: #823280.
+  * Tighten debhelper build dependency for cross build dependencies.
+  * Allow build dependencies for musl configurations (Helmut Grohne).
+    Closes: #823769.
+  * Fix dependency resolution for libraries not built anymore from
+    this source package.
+
+  [ Samuel Thibault ]
+  * patches/ada-hurd.diff: Fix Get_Page_Size type.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 10 May 2016 13:34:49 +0200
+
+gcc-6 (6.1.1-1) unstable; urgency=medium
+
+  * GCC 6.1.0 release.
+    - Fix PR bootstrap/70704, PR tree-optimization/70780, PR libgfortran/70684,
+      PR middle-end/70626, PR java/70839, PR target/70858, PR ada/70759,
+      PR ada/70786, PR c++/70540, PR middle-end/70626.
+  * Update to SVN 20160430 (r235678, 6.1.1) from the gcc-6-branch.
+    - Fix PR middle-end/70680, PR target/70750 (x86), PR ipa/70785,
+      PR sanitizer/70712, PR target/70728 (x86).
+    - Don't encode the minor version in the gcj abi version.
+
+  [ Aurelien Jarno ]
+  * Apply proposed patch for PR target/68273 (Wrong code on mips/mipsel due to
+    (invalid?) peeking at alignments in function_arg) on mips and mipsel.
+
+  [ Matthias Klose ]
+  * Always configure with --enable-targets=powerpcle-linux on ppc64el.
+  * Stop building libcc1 and libgccjit0, when not building common libs.
+  * Rename libgccjit-5-dbg to libgccjit0-dbg.
+  * Fix libjava testsuite with dejagnu 1.6, taken from the trunk.
+  * Allow embedded timestamps by C/C++ macros to be set externally (Eduard
+    Sanou).
+  * Add missing libstdc++ symbol to symbols file.
+  * libstdc++-doc: Ignore warnings about formulas and long identifiers in
+    man pages.
+  * Default the 32bit x86 architectures to i686, keep i585 symlinks.
+    See https://lists.debian.org/debian-devel/2015/09/msg00589.html
+  * Build-depend on debhelper (>= 9) and dpkg-dev (>= 1.17.14).
+  * Update gdc to the gdc-6 branch 20160430.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 30 Apr 2016 13:31:12 +0200
+
+gcc-6 (6.1.1-0ubuntu12) yakkety; urgency=medium
+
+  * GCC 6.1.0 release.
+    - Fix PR bootstrap/70704, PR tree-optimization/70780, PR libgfortran/70684.
+  * Update to SVN 20160428 (r235548, 6.1.1) from the gcc-6-branch.
+    - Fix PR middle-end/70680, PR target/70750 (x86), PR ipa/70785,
+      PR sanitizer/70712, PR target/70728 (x86).
+    - Don't encode the minor version in the gcj abi version.
+  * Always configure with --enable-targets=powerpcle-linux on ppc64el.
+  * Stop building libcc1 and libgccjit0, when not building common libs.
+  * Rename libgccjit-5-dbg to libgccjit0-dbg.
+  * Fix libjava testsuite with dejagnu 1.6, taken from the trunk.
+  * Re-enable running the tests.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 28 Apr 2016 10:33:38 +0200
+
+gcc-6 (6.0.1-2ubuntu12) yakkety; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 23 Apr 2016 18:24:49 +0200
+
+gcc-6 (6.0.1-2) unstable; urgency=medium
+
+  * GCC 6.1 release candidate 2.
+  * Update gdc to the trunk 20160423.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 23 Apr 2016 17:56:52 +0200
+
+gcc-6 (6.0.1-1ubuntu11) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 15 Apr 2016 18:38:06 +0200
+
+gcc-6 (6.0.1-1) experimental; urgency=medium
+
+  * GCC 6 release candidate 1.
+
+  [ Michael Hudson-Doyle ]
+  * cmd/go: deduplicate gccgo afiles by package path, not *Package. LP: #1566552.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 15 Apr 2016 18:32:25 +0200
+
+gcc-6 (6-20160405-0ubuntu1) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160405.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 05 Apr 2016 17:10:35 +0200
+
+gcc-6 (6-20160319-0ubuntu11) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160319.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 19 Mar 2016 12:17:24 +0100
+
+gcc-6 (6-20160313-0ubuntu11) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160313.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 13 Mar 2016 10:19:12 +0100
+
+gcc-6 (6-20160227-0ubuntu11) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160227.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 27 Feb 2016 11:02:40 +0100
+
+gcc-6 (6-20160225-0ubuntu11) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160225.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 25 Feb 2016 02:09:51 +0100
+
+gcc-6 (6-20160225-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160225.
+  * Update gdc to the trunk 20160224.
+  * Install missing architecture specific plugin header files.
+  * Fix PR target/69885, bootstrap error on m68k.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 25 Feb 2016 02:00:57 +0100
+
+gcc-6 (6-20160220-0ubuntu11) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160220.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 20 Feb 2016 04:38:26 +0100
+
+gcc-6 (6-20160206-0ubuntu11) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160206.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 06 Feb 2016 12:07:51 +0100
+
+gcc-6 (6-20160205-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160205.
+    - Fix PR tree-optimization/69320. Closes: #811921.
+    - Fix PR c++/68782. Closes: #812287.
+    - Fix PR tree-optimization/69328. Closes: #812247.
+    - Fix PR target/69421. Closes: #812246.
+    - Fix PR c++/69379. Closes: #812068.
+    - Fix PR lto/69393. Closes: #812062.
+    - Fix PR tree-optimization/69166. Closes: #812061.
+  * Update gdc to the trunk 20160205.
+    - Fix data corruption bug when passing around longdoubles.
+      Closes: #812080.
+  * Add more conflicts to GCC 5's debug and doc packages. Closes: #813081.
+  * Fix dependency generation for armel/armhf multilib cross targets.
+  * Fix libc dependency generation for multilib cross targets.
+  * Build libitm on alpha, s390x, sh4, sparc64.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 05 Feb 2016 18:08:37 +0100
+
+gcc-6 (6-20160122-1) experimental; urgency=medium
+
+  * Fix gnat build failure on KFreeBSD (Steven Chamberlain). Closes: #811372.
+  * Fix dependencies on target libraries which are not built anymore
+    from this source.
+  * Bump libmpx soname. Closes: #812084.
+  * Apply proposed patch for PR target/69129. Closes: #810081.
+  * Apply proposed patch for PR go/66904, pass linker flags from
+    "#cgo pkg-config:" directives (Michael Hudson).
+  * Configure with --enable-fix-cortex-a53-843419 on AArch64.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 22 Jan 2016 13:33:19 +0100
+
+gcc-6 (6-20160117-1ubuntu1) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160117.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 17 Jan 2016 12:34:33 +0100
+
+gcc-6 (6-20160117-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160117.
+  * Update gdc to the trunk 20160115.
+  * Update libgnatvsn/libgnatprj conflicts. Closes: #810809.
+  * Fix gnat build failures on the Hurd and KFreeBSD (Svante Signell).
+    Closes: #811063.
+  * Build libstdc++-6-doc with a fixed doxygen. Closes: #810717.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 17 Jan 2016 12:14:39 +0100
+
+gcc-6 (6-20160109-1ubuntu1) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160109.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 09 Jan 2016 12:03:28 +0100
+
+gcc-6 (6-20160109-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160109.
+  * Install new header file pkuintrin.h. Closes: #809807.
+  * Fix libcc1-0 dependency for cross compilers.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 09 Jan 2016 11:49:50 +0100
+
+gcc-6 (6-20160105-0ubuntu1) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160105.
+  * Install new header file pkuintrin.h. Closes: #809807.
+  * Fix libgcc1-0 dependency for cross compilers.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 02 Jan 2016 15:55:27 +0100
+
+gcc-6 (6-20160103-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160101.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 03 Jan 2016 12:47:13 +0100
+
+gcc-6 (6-20160101-0ubuntu2) xenial; urgency=medium
+
+  * Bump the libgcj version.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 02 Jan 2016 15:55:27 +0100
+
+gcc-6 (6-20160101-0ubuntu1) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20160101.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 01 Jan 2016 21:40:43 +0100
+
+gcc-6 (6-20151221-0ubuntu1) xenial; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20151220.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 21 Dec 2015 15:56:05 +0100
+
+gcc-6 (6-20151220-1ubuntu1) xenial; urgency=medium
+
+  * Test build for xenial.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 20 Dec 2015 14:11:14 +0100
+
+gcc-6 (6-20151220-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20151220.
+  * Update libstdc++-dbg conflicts. Closes: #807885.
+  * Set target tools and build dependencies for cross builds.
+  * Relax gcj-6-{jre,jre-headless,jdk} dependencies on libgcj16.
+  * Fix cross build issues.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 20 Dec 2015 13:46:12 +0100
+
+gcc-6 (6-20151219-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20151219.
+  * Update libstdc++-dbg conflicts. Closes: #807885.
+  * Set target tools and build dependencies for cross builds.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 19 Dec 2015 10:17:25 +0100
+
+gcc-6 (6-20151213-1ubuntu2) xenial; urgency=medium
+
+  * Test build for xenial.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 13 Dec 2015 15:04:49 +0100
+
+gcc-6 (6-20151213-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20151213.
+  * Update the ada-kfreebsd and ada-m68k patches.
+  * Fix cross-building without having the common cross libraries installed.
+  * Allow unstripped, non-optimized debug builds with setting DEB_BUILD_OPTIONS
+    including gccdebug.
+  * Remove obsolete libgccmath packaging support.
+  * Define SONAME macros whether the libraries are built or not.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 13 Dec 2015 13:24:55 +0100
+
+gcc-6 (6-20151211-1ubuntu3) xenial; urgency=medium
+
+  * Test build for xenial.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 11 Dec 2015 17:42:35 +0100
+
+gcc-6 (6-20151211-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from the trunk 20151211.
+  * Update gnat and gdc patches, re-enable gnat and gdc.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 11 Dec 2015 12:35:03 +0100
+
+gcc-6 (6-20151210-1) experimental; urgency=medium
+
+  * GCC 6 snapshot build, taken from 20151210.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 10 Dec 2015 22:09:13 +0100
+
+gcc-5 (5.3.1-3ubuntu1) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+    - Build using GCC Linaro on armhf and arm64.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 08 Dec 2015 02:21:55 +0100
+
+gcc-5 (5.3.1-3)  unstable; urgency=medium
+
+  * Update to SVN 20151207 (r231361, 5.3.1) from the gcc-5-branch.
+  * Remove upstreamed chunks from the ada-kfreebsd patch.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 08 Dec 2015 02:10:51 +0100
+
+gcc-5 (5.3.1-2ubuntu2) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+    - Build using GCC Linaro on armhf and arm64.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 07 Dec 2015 00:00:19 +0100
+
+gcc-5 (5.3.1-2) unstable; urgency=medium
+
+  * Update to SVN 20151206 (r231339, 5.3.1) from the gcc-5-branch.
+  * Re-enable building gdc/libphobos, fixing the profiled build.
+  * Fix PR sanitizer/67899, build failure on sparc/sparc64.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 06 Dec 2015 19:15:46 +0100
+
+gcc-5 (5.3.1-1ubuntu1) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+    - Build using GCC Linaro on armhf and arm64.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 05 Dec 2015 11:40:27 +0100
+
+gcc-5 (5.3.1-1) unstable; urgency=medium
+
+  * Update to SVN 20151205 (r231314, 5.3.1) from the gcc-5-branch.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 05 Dec 2015 11:36:26 +0100
+
+gcc-5 (5.3.1-0ubuntu2) xenial; urgency=medium
+
+  * Update libgcc symbols file.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 04 Dec 2015 18:52:20 +0100
+
+gcc-5 (5.3.1-0ubuntu1) xenial; urgency=medium
+
+  * Update to SVN 20151204 (r231267, 5.3.1) from the gcc-5-branch.
+  * Build using GCC Linaro on armhf and arm64.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 04 Dec 2015 15:04:01 +0100
+
+gcc-5 (5.3.0-3) unstable; urgency=medium
+
+  * Update libgcc symbols file.
+  * Restore libgcc.symbols.aebi.
+  * Disabled profiled bootstraps for backports.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 05 Dec 2015 07:50:48 +0100
+
+gcc-5 (5.3.0-1) experimental; urgency=medium
+
+  * GCC 5.3 release.
+    - Fix PR libstdc++/65142 (CVE-2015-5276).
+  * Update gdc to the gcc-5 branch 20151130.
+  * Enable the profiled bootstrap on amd64, arm64, armel armhf, i386, powerpc,
+    ppc64, ppc64el, s390x, x32 (excluding builds from the Linaro branch).
+  * Move test summary into the gcc-test-results package.
+  * Simplify libatomic, libcilkrts, libgcc, libgfortran, libgomp, libitm,
+    libmpx, libquadmath symbols files using versioned symbol references.
+    Closes: #806784.
+  * Only build the hppa64 cross compiler when either building the native compiler,
+    or when cross building the native compiler. Closes: #806479.
+  * Configure staged build with --enable-linker-build-id.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 04 Dec 2015 12:01:04 +0100
+
+gcc-5 (5.2.1-27ubuntu1) xenial; urgency=medium
+
+  * Configure with --enable-default-pie on s390x.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 30 Nov 2015 00:49:40 +0100
+
+gcc-5 (5.2.1-27) unstable; urgency=medium
+
+  * Update to SVN 20151129 (r231053, 5.2.1) from the gcc-5-branch.
+  * Don't strip cc1plus when shipping with unstripped frontends.
+  * Relax libgnatvsn5-dev-*-cross and libgnatprj5-dev-*-cross dependencies
+    on gnat-5-*-linux-gnu.
+  * Fix setting the explicit libc dependency for cross builds.
+  * Don't build m4-nofpu multilibs on sh4, install the default multilib
+    into the standard location.
+  * Stop building gnat on mips64, see https://gcc.gnu.org/PR65337 (#806370).
+  * Update the patch for PR go/67508 and re-enable Go on sparc and sparc64.
+  * Fix gnat sparc/sparc64 architecture detection.
+  * Update libgcc and libstdc++ symbols files.
+  * Don't ship the gcov tools in the gcc-hppa64-linux-gnu package.
+  * Run the autoconf generation in parallel.
+  * Add --enable-default-pie option to GCC configure, taken from the trunk.
+  * Enable gnat for m68k cross builds.
+  * Link gnat tools, gnat libs and libgccjit with the defaults LDFLAGS.
+  * Skip non-default multilib and libstdc++-v3 debug builds in bootstrap builds.
+  * Ship an empty debian/rules.parameters in the gcc-5-source package.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 29 Nov 2015 23:48:58 +0100
+
+gcc-5 (5.2.1-26ubuntu1) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 25 Nov 2015 17:29:15 +0100
+
+gcc-5 (5.2.1-26) unstable; urgency=medium
+
+  * Update to SVN 20151125 (r230897, 5.2.1) from the gcc-5-branch.
+  * Fix the rtlibs stage build. Closes: #806186.
+  * Fix packaging the cross libphobos package.
+  * Build the hppa64 cross compiler on x86 architectures.
+  * gcc-5-hppa64-linux-gnu: Stop providing unversioned tools using
+    alternatives. Build a gcc-hppa64-linux-gnu package instead.
+  * Split out a gcc-5-test-results package from g++-5, allowing a post
+    build analysis, and reducing the size of the g++-5 package.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 25 Nov 2015 20:33:08 +0100
+
+gcc-5 (5.2.1-25ubuntu1) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 23 Nov 2015 06:06:11 +0100
+
+gcc-5 (5.2.1-25) unstable; urgency=medium
+
+  * Update to SVN 20151123 (r230734, 5.2.1) from the gcc-5-branch.
+  * Fix libgcc4-dbg dependency on libgcc4. Closes: #805839.
+  * Fix building epoch prefixed cross packages.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 23 Nov 2015 05:48:00 +0100
+
+gcc-5 (5.2.1-24ubuntu3) xenial; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 21 Nov 2015 12:21:06 +0100
+
+gcc-5 (5.2.1-24) unstable; urgency=medium
+
+  * Update to SVN 20151121 (r230703, 5.2.1) from the gcc-5-branch.
+  * Fix PR libstdc++/56158, taken from the trunk. Closes: #804521. LP: #1514309.
+  * Don't try to build a gnat cross compiler when there is no gnat compiler
+    for the build architecture.
+  * Update gnat build dependencies for backports.
+  * Parallelize building documentation and parallelize the packaging step.
+  * Update the Linaro support to the 5-2015.11 snapshot.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 21 Nov 2015 11:22:16 +0100
+
+gcc-5 (5.2.1-23ubuntu1) xenial; urgency=medium
+
+  * Again, configure with --enable-targets=powerpcle-linux on ppc64el.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 28 Oct 2015 12:18:49 +0100
+
+gcc-5 (5.2.1-23) unstable; urgency=medium
+
+  * Update to SVN 20151028 (r229478, 5.2.1) from the gcc-5-branch.
+
+  [ Matthias Klose ]
+  * Update the Linaro support to the 5-2015.10 snapshot.
+  * gcj: On ppc64el, use the same jvm archdir name as for openjdk (ppc64le).
+  * gcj: Fix priority of java alternatives. Closes: #803055.
+  * gnat-5: Reintroduce the unversioned gnatgcc name. Closes: #802838.
+
+  [ Aurelien Jarno ]
+  * Replace proposed patch for PR rtl-optimization/67736 by the one
+    committed on trunk.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 28 Oct 2015 10:36:54 +0100
+
+gcc-5 (5.2.1-22ubuntu5) xenial; urgency=medium
+
+  * Revert the fix for PR ipa/67056, causing an ICE.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 23 Oct 2015 19:13:51 +0200
+
+gcc-5 (5.2.1-22ubuntu4) xenial; urgency=medium
+
+  * Update to SVN 20151022 (r229176, 5.2.1) from the gcc-5-branch.
+  * Fix PR ipa/67056, taken from the trunk. Closes: #788299.
+  * Target POWER8 on ppc64el.
+  * Again, don't strip the compiler binaries for more verbose ICEs.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 22 Oct 2015 17:32:47 +0200
+
+gcc-5 (5.2.1-22ubuntu2) wily; urgency=medium
+
+  * Strip the compiler binaries for the release.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 16 Oct 2015 12:17:17 +0200
+
+gcc-5 (5.2.1-22ubuntu1) wily; urgency=medium
+
+  * gcj: On ppc64el, use the same jvm archdir name as for openjdk (ppc64le).
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 11 Oct 2015 10:13:52 +0200
+
+gcc-5 (5.2.1-22) unstable; urgency=medium
+
+  * Update to SVN 20151010 (r228681, 5.2.1) from the gcc-5-branch.
+    - Fix PR libstdc++/65913, PR libstdc++/67173, PR libstdc++/67747,
+      PR c/67730, PR middle-end/67563, PR lto/67699, PR tree-optimization/67821,
+      PR debug/58315.
+
+  [ Matthias Klose ]
+  * Restore the work around for PR libstdc++/65913, still needed at least
+    for powerpc.
+  * Rename gcc-5-hppa64 to gcc-5-hppa64-linux-gnu, update (build) dependency
+    on binutils. Closes: #800563.
+  * Adjust setting DH_COMPAT for dh_movefiles with updated debhelper supporting
+    globbing of arguments. Closes: #800250.
+  * Build-depend on gnat-5 instead of gnat-4.9.
+
+  [ Aurelien Jarno ]
+  * Do not Use --with-mips-plt on mips and mipsel. Closes: #799811.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 10 Oct 2015 22:17:09 +0200
+
+gcc-5 (5.2.1-21ubuntu2) wily; urgency=medium
+
+  * Restore the work around for PR libstdc++/65913, still needed at least
+    for powerpc.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 04 Oct 2015 02:21:30 +0200
+
+gcc-5 (5.2.1-21ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 03 Oct 2015 21:30:44 +0200
+
+gcc-5 (5.2.1-21) unstable; urgency=medium
+
+  * Update to SVN 20151003 (r228449, 5.2.1) from the gcc-5-branch.
+  * Fix building gnat. Closes: #800781.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 03 Oct 2015 17:28:45 +0200
+
+gcc-5 (5.2.1-20ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 02 Oct 2015 11:35:22 +0200
+
+gcc-5 (5.2.1-20) unstable; urgency=medium
+
+  * Update to SVN 20151002 (r228373, 5.2.1) from the gcc-5-branch.
+  * Fix packaging the ada cross library packages.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 02 Oct 2015 10:24:38 +0200
+
+gcc-5 (5.2.1-19ubuntu1) wily; urgency=medium
+
+  * Configure --with-arch=zEC12 on s390x Ubuntu.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 30 Sep 2015 22:55:14 +0200
+
+gcc-5 (5.2.1-19) unstable; urgency=medium
+
+  * Update to SVN 20150930 (r228302, 5.2.1) from the gcc-5-branch.
+    - Fix PR ipa/66424. Closes: #800318.
+
+  [ Matthias Klose ]
+  * Update the Linaro support to the 5-2015.09 snapshot.
+  * Fix PR libstdc++/67707, taken from the trunk. LP: #1499564.
+  * Ship libgcj.spec in gcj-5 instead of gcj-5-jdk. Closes: #800010.
+  * gcj-5: Suggest gcj-5-jdk.
+  * Fix base dependency for ada cross library packages.
+  * Add ${shlibs:Depends} for libgnatvsn and libgnatprj.
+  * Link lrealpath.o into libgnatprj. Closes: #800045.
+  * libgnat{svn,prj}-dev: For cross builds, move adainclude and adalib files
+    into the gcc libdir.
+  * Default to POWER8 on ppc64el.
+  * armv8: Fix slt lda missing conditional code (taken from the trunk).
+  * Fix lintian pre-depends-directly-on-multiarch-support warnings.
+
+  [ Aurelien Jarno ]
+  * Apply proposed patch for PR rtl-optimization/67736 when building for
+    mips64 or mips64el. Closes: #800321.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 30 Sep 2015 20:36:50 +0200
+
+gcc-5 (5.2.1-18ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 23 Sep 2015 03:10:37 +0200
+
+gcc-5 (5.2.1-18) unstable; urgency=medium
+
+  * Update to SVN 20150922 (r228023, 5.2.1) from the gcc-5-branch.
+
+  [ Matthias Klose ]
+  * gcc-5-plugin-dev: Depend on libmpc-dev. Closes: #798997.
+  * Fix PR libstdc++/65913, taken from the trunk. Closes: #797577.
+
+  [ YunQiang Su ]
+  * Build again the gnat-5-sjlj package. Closes: #798782.
+  * Fix gnat cross builds, and cross building gnat.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 22 Sep 2015 23:15:17 +0200
+
+gcc-5 (5.2.1-17ubuntu5) wily; urgency=medium
+
+  * Don't assume --push-state/--pop-state being available for every linker.
+    LP: #1496743.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 22 Sep 2015 20:54:29 +0200
+
+gcc-5 (5.2.1-17ubuntu4) wily; urgency=medium
+
+  * gcc-5-plugin-dev: Depend on libmpc-dev. Closes: #798997.
+  * Work around PR c++/65913, link with -latomic when linking with -lstdc++.
+    Closes: #797577.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 15 Sep 2015 17:57:31 +0200
+
+gcc-5 (5.2.1-17ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 11 Sep 2015 03:24:48 +0200
+
+gcc-5 (5.2.1-17) unstable; urgency=medium
+
+  * Update to SVN 20150911 (r227671, 5.2.1) from the gcc-5-branch.
+    - Fix PR c++/67369, ICE on valid code. LP: #1489173.
+
+  [ Matthias Klose ]
+  * Build-depend on linux-libc-dev [m68k] for gcc and gcc-snapshot builds.
+    Closes: #796906.
+  * Don't ignore anymore bootstrap comparison failures on sh4. Closes: #796939.
+  * Fix stage1 cross build for KFreeBSD. Closes: #796901.
+  * libgo: Fix PR go/67508, rewrite lfstack packing/unpacking to look more
+    like that in Go (Michael Hudson). LP: #1472650.
+  * Fix PR target/67143 (AArch64), ICE on valid code. LP: #1481333.
+
+  [ Aurelien Jarno ]
+  * Use --with-mips-plt on mips*.
+  * Build for R2 ISA on mips, mips64 and mips64el.
+  * Optimize for R2 ISA on mipsel.
+  * Only apply mips-fix-loongson2f-nop on mipsel.
+
+  [ YunQiang Su ]
+  * Fix running the acats tests. Closes: #798531.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 11 Sep 2015 03:17:20 +0200
+
+gcc-5 (5.2.1-16ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 03 Sep 2015 16:00:26 +0200
+
+gcc-5 (5.2.1-16) unstable; urgency=medium
+
+  * Update to SVN 20150903 (r227431, 5.2.1) from the gcc-5-branch.
+    - Backport the filesystem TS library.
+  * libstdc++-dev: Install libstdc++fs.a.
+  * Again, configure with --enable-targets=powerpcle-linux on ppc64el.
+  * Apply proposed patch for PR target/67211 (ppc64el).
+  * libgo-dev: Install libgolibbegin.a.
+  * Apply proposed patch for PR target/67280 (ARM). LP: #1482320.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 03 Sep 2015 12:16:15 +0200
+
+gcc-5 (5.2.1-15ubuntu5) wily; urgency=medium
+
+  * Fix libstdc++-breaks (add version for the clustalx breaks).
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 25 Aug 2015 17:56:26 +0200
+
+gcc-5 (5.2.1-15ubuntu3) wily; urgency=medium
+
+  * Update to SVN 20150825 (r227166, 5.2.1) from the gcc-5-branch.
+    - Backport the filesystem TS library.
+  * libstdc++-dev: Install libstdc++fs.a.
+  * Again, configure with --enable-targets=powerpcle-linux on ppc64el.
+  * Apply proposed patch for PR target/67211 (ppc64el).
+  * libgo-dev: Install libgolibbegin.a.
+  * Add the PR libstdc++/66145 breaks for wily.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 25 Aug 2015 15:56:11 +0200
+
+gcc-5 (5.2.1-15ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 09 Aug 2015 13:20:15 +0200
+
+gcc-5 (5.2.1-15) unstable; urgency=medium
+
+  * Update to SVN 20150808 (r226731, 5.2.1) from the gcc-5-branch.
+  * Adjust libstdc++-breaks: Break libantlr-dev instead of antlr;
+    adjust libreoffice version (closes: #794203), drop xxsd break (see
+    #793289), remove cython breaks (closes: #794511), add breaks for
+    packages built using cython (chemps2, fiona, guiqwt, htseq, imposm,
+    pysph, pytaglib, python-scipy, python-sfml, rasterio).
+  * Ignore missing libstdc++ symbols on sparc64 (work around #792204).
+
+ -- Matthias Klose <doko@debian.org>  Sat, 08 Aug 2015 11:18:24 +0200
+
+gcc-5 (5.2.1-14) unstable; urgency=high
+
+  * Fix libstdc++6 breaks.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 31 Jul 2015 04:12:08 +0200
+
+gcc-5 (5.2.1-13) unstable; urgency=high
+
+  * Upload to unstable (https://wiki.debian.org/GCC5). See also
+    https://lists.debian.org/debian-devel-announce/2015/07/msg00000.html
+  * Update to SVN 20150730 (r226411, 5.2.1) from the gcc-5-branch.
+    - Fix PR libstdc++/67015. Closes: #793784.
+  * Fix version macros in the plugin-header.h header. Closes: #793478.
+  * libstdc++6: Add breaks for issues tagged with gcc-pr66145.
+  * Add libcpprest2.4 to libstdc++6 breaks. Closes: #784655.
+  * Fix PR c++/66857, taken from the trunk.
+  * Ignore differences in gcc/real.o in the bootstrap build for
+    sh*-*linux-gnu targets.  According to PR 67002, "A rare indeterminacy
+    of the register choice.  Both codes are valid.  It seems very hard to
+    find where has this indeterminacy come from". Suggested by Adrian
+    Glaubitz.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 30 Jul 2015 21:51:25 +0200
+
+gcc-5 (5.2.1-12ubuntu2) wily; urgency=medium
+
+  * Update to SVN 20150729 (r226354, 5.2.1) from the gcc-5-branch.
+    - Fix PR libstdc++/67015. Closes: #793784.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 29 Jul 2015 17:59:18 +0200
+
+gcc-5 (5.2.1-12ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 22 Jul 2015 21:17:54 +0200
+
+gcc-5 (5.2.1-12) experimental; urgency=medium
+
+  * Update to SVN 20150723 (r226105, 5.2.1) from the gcc-5-branch.
+  * Fix PR libstdc++/66145, std::ios_base::failure objects thrown from
+    libstdc++.so using the gcc4-compatible ABI.
+    Just build src/c++11/functexcept.cc using the new ABI. It will break
+    code, which will be handled in the archive by adding Breaks for the
+    affected packages.  Third party code using such code will need a rebuild.
+  * Remove the work around to build with -O1 on sh4.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 23 Jul 2015 14:18:44 +0200
+
+gcc-5 (5.2.1-11ubuntu1) wily; urgency=medium
+
+  * Configure without --disable-libstdcxx-dual-abi.
+  * Configure with --with-default-libstdcxx-abi=new.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 17 Jul 2015 08:14:56 +0200
+
+gcc-5 (5.2.1-1ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 16 Jul 2015 16:58:50 +0200
+
+gcc-5 (5.2.1-1) experimental; urgency=medium
+
+  * GCC 5.2 release.
+  * Update to SVN 20150716 (r225880, 5.2.1) from the gcc-5-branch.
+  * Require version 5.2 for the libstdc++6 cxx symbols.
+  * Ignore missing libstdc++ symbols on sparc64 (work around #792204).
+  * Go escape analysis: analyze multiple result type assertions (taken
+    from the trunk).
+
+ -- Matthias Klose <doko@debian.org>  Thu, 16 Jul 2015 15:35:44 +0200
+
+gcc-5 (5.1.1-14ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 11 Jul 2015 13:00:26 +0200
+
+gcc-5 (5.1.1-14) unstable; urgency=medium
+
+  * Update to SVN 20150711 (r225710, 5.1.1) from the gcc-5-branch.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 11 Jul 2015 11:57:19 +0200
+
+gcc-5 (5.1.1-13ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 07 Jul 2015 14:29:11 +0200
+
+gcc-5 (5.1.1-13) unstable; urgency=medium
+
+  * Update to SVN 20150706 (r225471, 5.1.1) from the gcc-5-branch.
+  * Update libasan symbol files.
+  * Configure --with-fp-32=xx on all mips targets, setting MIPS O32 default
+    to FPXX (YunQiang Su). Closes: #789612.
+  * Update libgccjit symbol file.
+  * Add x32 symbols files for libgcc1 and libstdc++6.
+  * libgccjit0: Add breaks for python-gccjit and python3-gccjit.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 06 Jul 2015 19:55:08 +0200
+
+gcc-5 (5.1.1-12ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 23 Jun 2015 12:53:45 +0200
+
+gcc-5 (5.1.1-12) unstable; urgency=medium
+
+  * Update to SVN 20150622 (r224724, 5.1.1) from the gcc-5-branch.
+  * Update symbols files for mips64 libatomic and libstdc++ (YunQiang Su).
+    Closes: #788990.
+  * Fix "empty-binary-package" lintian warnings.
+
+ -- Matthias Klose <doko@debian.org>  Mon, 22 Jun 2015 14:37:49 +0200
+
+gcc-5 (5.1.1-11ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 17 Jun 2015 14:38:38 +0200
+
+gcc-5 (5.1.1-11) unstable; urgency=medium
+
+  * Update to SVN 20150616 (r224519, 5.1.1) from the gcc-5-branch.
+  * gccgo: escape: Analyze binary expressions (taken from the trunk).
+  * Explicitly build with -Wl,--no-relax on alpha again.
+  * Build with -O1 on sh4 (try to work around PR target/66358).
+
+ -- Matthias Klose <doko@debian.org>  Tue, 16 Jun 2015 16:11:59 +0200
+
+gcc-5 (5.1.1-10) unstable; urgency=medium
+
+  * Update to SVN 20150613 (r224454, 5.1.1) from the gcc-5-branch.
+  * Make removal of byte-compiled libstdc++ pretty printer files more
+    robust. Closes: #787630.
+  * Fix mips 32bit (o32) multilib builds (YunQiang Su).
+  * Build target libraries with -Wl,-z,relro.
+  * Build libstdc++6 when building the common libraries.
+  * Fix a bunch of lintian warnings.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 13 Jun 2015 12:59:17 +0200
+
+gcc-5 (5.1.1-9ubuntu2) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 03 Jun 2015 01:02:23 +0200
+
+gcc-5 (5.1.1-9) unstable; urgency=medium
+
+  * Update to SVN 20150602 (r224029, 5.1.1) from the gcc-5-branch.
+  * Remove byte-compiled libstdc++ pretty printer files on upgrade.
+    Closes: #785939.
+  * Fix dangling libgccjit.so symlink.
+  * Fix base dependency for rtlibs stage builds.
+  * Fix build failure of the hppa64 cross compiler, introduced by the
+    gnat cross patches. Closes: #786692.
+  * Update README.source (Michael Vogt).
+  * libgo: syscall.Sendfile(): Apply proposed patch for PR go/66378.
+    (Michael Vogt). LP: #1460530.
+  * Set CC and CXX matching the same GCC version for the stage1 build.
+  * Work around PR go/66368, build libgo with -fno-stack-protector.
+    LP: #1454183.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 03 Jun 2015 00:49:41 +0200
+
+gcc-5 (5.1.1-8ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 28 May 2015 12:51:48 +0200
+
+gcc-5 (5.1.1-8) unstable; urgency=medium
+
+  * Update to SVN 20150528 (r223816, 5.1.1) from the gcc-5-branch.
+  * Set the priorities of the *-dev-*-cross packages to extra.
+  * Prepare to change the base dependency for *-cross packages.
+  * Fix dependencies for stage1 and stage2 builds.
+  * Relax dependencies on binary indep *-dev-*-cross packages.
+  * Disable building gdc on sh4 (bootstrap comparison failure).
+
+ -- Matthias Klose <doko@debian.org>  Thu, 28 May 2015 15:51:00 +0200
+
+gcc-5 (5.1.1-7) unstable; urgency=medium
+
+  * Update to SVN 20150522 (r223579, 5.1.1) from the gcc-5-branch.
+  * Add description for the ada-gnattools-cross patch (YunQiang Su).
+  * Provide a rtlibs stage to build a subset of target library packages.
+  * Make symbols file symlinking for cross builds more robust.
+  * Prefer gnatgcc-5 over gnatgcc when building native packages.
+  * Various fixes to build a gnat cross compiler:
+    - Fix dependencies of packages.
+    - Fix building libgnatprj and libgnatvsn (still needed to figure
+      out if these are target or host libraries).
+  * Fix building cross compilers with dpkg 1.18.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 22 May 2015 18:20:01 +0200
+
+gcc-5 (5.1.1-6ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+  * Fix dependencies for stage1 and stage2 builds.
+  * Disable building gdc on sh4.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 19 May 2015 18:29:02 +0200
+
+gcc-5 (5.1.1-6) unstable; urgency=medium
+
+  * Update to SVN 20150519 (r223346, 5.1.1) from the gcc-5-branch.
+  * Don't build gdc-multilib on armel.
+  * Remove old CFLAGS/LDFLAGS settings to build gdc.
+  * Remove reference to .ico file in NEWS.html.
+  * Fix gcc's dependency on libcc1-0 for native builds.
+  * Fix stripping the rpath when cross-building cross compilers.
+  * Remove work arounds to build 64bit multilibs on 32bit targets,
+    now properly fixed upstream.
+  * Partially apply patches to build a gnat cross compiler (submitted
+    by YunQiang Su).
+    - gnatmake: Call the versioned gnatbind and gnatlink commands.
+      Closes: #782257.
+    - Allow libgnatprj and libgnatvsn to cross build. Addresses: #783372.
+    - New patch ada-gnattools-cross.diff (no documentation).
+  * Backport patch for gccgo:
+    - gccgo: If unary & does not escape, the var does not escape.
+  * Apply the backported patches for the go escape analysis. Need to
+    be enabled with -fgo-optimize-alloc (this option may go away again).
+  * Re-enable running the tests.
+
+ -- Matthias Klose <doko@debian.org>  Tue, 19 May 2015 10:33:40 +0200
+
+gcc-5 (5.1.1-5ubuntu4) wily; urgency=medium
+
+  * Update to SVN 20150513 (r223155, 5.1.1) from the gcc-5-branch.
+  * Don't build gdc-multilib on armel.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 13 May 2015 14:36:20 +0200
+
+gcc-5 (5.1.1-5ubuntu3) wily; urgency=medium
+
+  * Fix gnat build dependencies.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 10 May 2015 02:46:32 +0200
+
+gcc-5 (5.1.1-5ubuntu2) wily; urgency=medium
+
+  * Update to SVN 20150509 (r222970, 5.1.1) from the gcc-5-branch.
+  * Fix gotools configury.
+  * Configure with
+      --disable-libstdcxx-dual-abi --with-default-libstdcxx-abi=c++98
+    While libstdc++ provides a dual ABI to support both the c++98 and c++11
+    ABI, there is no committment on compatibility of the old experimental
+    c++11 ABI from GCC 4.9 and the stable c++11 ABI in GCC 5.
+    Closes: #784655.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 09 May 2015 19:24:57 +0200
+
+gcc-5 (5.1.1-5ubuntu1) wily; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 05 May 2015 17:52:14 +0200
+
+gcc-5 (5.1.1-5) unstable; urgency=medium
+
+  * Update to SVN 20150507 (r222873, 5.1.1) from the gcc-5-branch.
+  * Fix 32bit libstdc++ symbols files for kfreebsd-amd64.
+  * libx32phobos-dev: Don't depend on libx32z-dev, when not available.
+  * Fix gotools configury.
+  * Configure with
+      --disable-libstdcxx-dual-abi --with-default-libstdcxx-abi=c++98
+    While libstdc++ provides a dual ABI to support both the c++98 and c++11
+    ABI, there is no committment on compatibility of the old experimental
+    c++11 ABI from GCC 4.9 and the stable c++11 ABI in GCC 5.
+    Closes: #784655.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 08 May 2015 18:48:49 +0200
+
+gcc-5 (5.1.1-4) unstable; urgency=medium
+
+  * Update to SVN 20150503 (r222751, 5.1.1) from the gcc-5-branch.
+    - Fix build failure on alpha.
+  * Fix applying the cross-biarch patch for stage1 builds.
+  * Fix libstdc++ symbols files for kfreebsd-amd64.
+  * Remove libn32phobos-5-dev from the control file.
+  * Really disable gnat on x32.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 02 May 2015 19:18:57 +0200
+
+gcc-5 (5.1.1-3) unstable; urgency=high
+
+  * Update to SVN 20150430 (r222660, 5.1.1) from the gcc-5-branch.
+  * Fix libstdc++ symbols files for kfreebsd-i386.
+  * PR libstdc++/62258, fix for std::uncaught_exception, taken from the trunk.
+    LP: #1439451.
+  * Backport patches for gccgo (not yet applied):
+    - Consider multi-result calls in escape analysis.
+    - Propagate escape info from closures to enclosed variables.
+    - Analyze function values and conversions.
+    - Use backend interface for stack allocation.
+  * More libstdc++ symbols updates for the Hurd and KFreeBSD.
+  * config-ml.in: Add D support.
+  * Update cross-biarch.diff to support D and Go.
+  * Apply the cross-biarch patch for every cross build.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 30 Apr 2015 15:42:05 +0200
+
+gcc-5 (5.1.1-2) unstable; urgency=medium
+
+  * Update to SVN 20150428 (r222550, 5.1.1) from the gcc-5-branch.
+  * Fix the gnat build dependency.
+  * Don't build go and gofmt for cross compilers.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 28 Apr 2015 23:57:14 +0200
+
+gcc-5 (5.1.1-1) unstable; urgency=medium
+
+  * GCC 5.1.0 release.
+  * Update to SVN 20150424 (r222416, 5.1.1) from the gcc-5-branch.
+  * Update NEWS files.
+  * Apply the ada-bootstrap-compare patch for snapshot builds as well.
+  * Update libasan, libgomp and libstdc++ symbols files.
+  * Don't ignore errors in dh_makeshlibs and dh_shlibdeps anymore, symbols
+    files should be uptodate now.
+  * Split out the sjlj build related things from the ada-acats patch into
+    a new ada-acats-sjlj patch.
+  * Don't build libx32phobos-5-dev when not building x32 multilibs.
+  * Fix standard C++ include directory for cross builds. Closes: #783241.
+  * Ignore bootstrap comparison failure on ia64. Filed upstream as
+    PR middle-end/65874.
+  * gccgo: Add (don't yet apply) a patch to implement escape analysis (taken
+    from the trunk). Turned off by default, enable with -fgo-optimize-alloc.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 24 Apr 2015 18:42:39 +0200
+
+gcc-5 (5.1.0-0ubuntu11) vivid; urgency=medium
+
+  * GCC 5.1.0 release.
+  * Update NEWS files.
+  * gccgo: Implement escape analysis (taken from the trunk). Turned off
+    by default, enable with -fgo-optimize-alloc.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 22 Apr 2015 14:54:11 +0200
+
+gcc-5 (5.1~rc2-0ubuntu12) vivid; urgency=medium
+
+  * Fix libasan symbols.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 22 Apr 2015 00:12:03 +0200
+
+gcc-5 (5.1~rc2-0ubuntu11) vivid; urgency=medium
+
+  * GCC 5.1 release candidate 2.
+  * Update to SVN 20150421 (r222253) from the gcc-5-branch.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 21 Apr 2015 18:53:06 +0200
+
+gcc-5 (5.1~rc1-0ubuntu12) vivid; urgency=medium
+
+  * Update to SVN 20150419 (r222218) from the gcc-5-branch.
+  * Apply the ada-bootstrap-compare patch for snapshot builds as well.
+  * Update libasan, libgomp and libstdc++ symbols files.
+  * Don't ignore errors in dh_makeshlibs and dh_shlibdeps anymore, symbols
+    files should be uptodate now.
+  * Split out the sjlj build related things from the ada-acats patch into
+    a new ada-acats-sjlj patch.
+  * Ignore bootstrap comparison failure on ia64. Filed upstream as
+    PR middle-end/65874.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 19 Apr 2015 15:57:49 +0200
+
+gcc-5 (5.1~rc1-0ubuntu11) vivid; urgency=medium
+
+  * GCC 5.1 release candidate 1.
+  * Update to SVN 20150414 (r222066) from the gcc-5-branch.
+  * Update GDC to the gcc-5 branch, 20140414.
+  * Don't build libobjc, when not building the common libraries.
+  * Don't run the gccjit tests on KFreeBSD. Works around #782444:.
+  * Fix not building libs built by the next GCC version.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 14 Apr 2015 03:01:02 +0200
+
+gcc-5 (5-20150410-0ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150410.
+  * Fix /usr/include/c++/5.0.0 symlink.
+  * Re-enable building the D frontend. Closes: #782254.
+  * gccgo: Install libnetgo.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 11 Apr 2015 02:21:24 +0200
+
+gcc-5 (5-20150404-0ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150404.
+  * Don't explicitly configure --with-gxx-include-dir and an absolute path,
+    so the toolchain remains relocatible. Instead, canonicalize the include
+    path names at runtime.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 04 Apr 2015 23:34:58 +0200
+
+gcc-5 (5-20150401-0ubuntu12) vivid; urgency=medium
+
+  * Update to SVN 20150401.
+  * Don't link libgnatprj using --no-allow-shlib-undefined on older releases.
+  * Don't build libmpx on older releases.
+  * Remove the work around to build libgccjit on arm64.
+  * Fix the libgccjit build using the just built compiler.
+  * Don't break other gcc, gcj, gnat -base packages for backports, only
+    needed for dist-upgrades.
+  * Don't add -gtoggle to STAGE3_CFLAGS (disabling the bootstrap comparison).
+    Instead, ignore the one differing file (gcc/ada/a-except.o) for now.
+    See #781457, PR ada/65618.
+  * Update libasan, libtsan, libgfortran and libstdc++ symbols files.
+  * Add symbols files for libmpx, libgccjit and libcc1.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 01 Apr 2015 11:27:39 +0200
+
+gcc-5 (5-20150329-1ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150329.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sun, 29 Mar 2015 19:13:54 +0200
+
+gcc-5 (5-20150329-1) experimental; urgency=medium
+
+  * Update to SVN 20150329.
+  * Fix building the gnat-5-doc package.
+  * Fix gnat build dependencies.
+  * Fix installation of the gnat upstream ChangeLog. Closes: #781451.
+  * Restore the bootstrap-debug.mk patch to the ada-mips patch
+    for debugging purposes. See #781457.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 29 Mar 2015 18:53:29 +0200
+
+gcc-5 (5-20150328-0ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150328.
+  * Fix building the gnat-5-doc package.
+  * Fix installation of the gnat upstream ChangeLog. Closes: #781451.
+  * Restore the bootstrap-debug.mk patch to the ada-mips patch
+    for debugging purposes. See #781457.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 28 Mar 2015 15:08:55 +0100
+
+gcc-5 (5-20150327-1) experimental; urgency=medium
+
+  * Update to SVN 20150327.
+  * Update libcc1 build support.
+  * Fix syntax in libstdc++ symbols file. Closes: #780991.
+  * Fix PR go/65417: Add support for PPC32 relocs to debug/elf. LP: #1431388.
+  * Fix PR go/65462: Fix go get dependencies. LP: #1432497.
+  * Limit the omp.h multilib fix to Linux. Closes: #778440.
+  * For ICEs, dump the preprocessed source file to stderr when in a
+    distro build environment.
+  * Remove the bootstrap-debug.mk patch from the ada-mips patch.
+  * gnat related work (partly based on #780640):
+    - Update patches for GCC 5.
+    - Build the gnat packages from the gcc-5 source package.
+    - Don't build a gnat-base package from the gcc-5 source.
+    - Stop building the gnat-5-sjlj package for now, patch needs an update.
+    - Fix the packaging when not building the gnat-5-sjlj package.
+    - Don't apply the ada-symbolic-tracebacks, patch needs an update.
+    - Fix the libgnatprj build, build with -DIN_GCC.
+  * Replace cloog/ppl build bits with isl build bits.
+
+ -- Matthias Klose <doko@debian.org>  Fri, 27 Mar 2015 21:05:16 +0100
+
+gcc-5 (5-20150321-1ubuntu12) vivid; urgency=medium
+
+  * Update to SVN 20150321.
+  * Move the libcc1plugin from the gcc-5-plugin-dev package into the
+    gcc-5 package.
+  * Configure with --enable-checking=yes (instead of =release).
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 21 Mar 2015 15:28:30 +0100
+
+gcc-5 (5-20150316-1ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150316.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 16 Mar 2015 11:56:03 +0100
+
+gcc-5 (5-20150314-1ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150314.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 14 Mar 2015 14:29:28 +0100
+
+gcc-5 (5-20150312-1ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150312.
+    - PR go/65404, enable cgo on arm64 and powerpc. LP: #1431032.
+  * Fix libmpx multilib builds.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 12 Mar 2015 23:11:21 +0100
+
+gcc-5 (5-20150311-1ubuntu12) vivid; urgency=medium
+
+  * Update to SVN 20150311.
+    - libgo: Add arm64 to the pointer size map (Michael Hudson).
+    - libgo: Add ppc to the pointer size map.
+  * Enable libmpx builds on amd64 and i386.
+  * Update the gcc-multiarch patch for mips64 (YunQiang Su).
+    Closes: #776402, #780271.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 11 Mar 2015 19:56:38 +0100
+
+gcc-5 (5-20150307-1ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150307.
+    - Update gccgo to Go 1.4.2.
+  * Enable libsanitizer for AArch64 and POWERPC LE (asan, ubsan).
+  * Remove the support to build empty libsanitizer packages on powerpc
+    and ppc64; libsanitizer should be stable on these architectures.
+  * Fix libcc1.so symlink. Closes: #779341.
+  * Revert the fix for PR65150 on armel and armhf to restore bootstrap.
+  * Don't strip the libgo library, or some things won't work as documented,
+    like runtime.Callers. Still keep the -dbg packages and check if some
+    debug information can be stripped.
+  * gccgo-5: Install alternatives for go and gofmt.
+
+ -- Matthias Klose <doko@ubuntu.com>  Sat, 07 Mar 2015 12:36:40 +0100
+
+gcc-5 (5-20150226-1) experimental; urgency=medium
+
+  * Update to SVN 20150226.
+    - Fix PR c/65040 (closes: #778514), PR tree-optimization/65053
+      (closes: #778070, #778071), PR c++/64898 (closes: #778472).
+  * Allow not to strip the compiler executables to be able to print backtraces
+    for ICEs.
+  * Fix gnat build on mips64el (James Cowgill). Addresses: #779191.
+  * Fix the hppa64 cross build (John David Anglin). Closes: #778658.
+  * Fix libstdc++ pretty printers for Python3. Closes: #778436.
+
+ -- Matthias Klose <doko@debian.org>  Thu, 26 Feb 2015 08:18:23 +0100
+
+gcc-5 (5-20150205-0ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150205.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 05 Feb 2015 01:57:43 +0100
+
+gcc-5 (5-20150203-0ubuntu12) vivid; urgency=medium
+
+  * Don't disable bootstrap mode for the jit build on arm64, gets
+    miscompiled.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 03 Feb 2015 13:39:02 +0100
+
+gcc-5 (5-20150203-0ubuntu11) vivid; urgency=medium
+
+  * Update to SVN 20150203.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 03 Feb 2015 13:39:02 +0100
+
+gcc-5 (5-20150129-0ubuntu2) vivid; urgency=medium
+
+  * Fix the libstdc++ build.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 29 Jan 2015 19:09:16 +0100
+
+gcc-5 (5-20150129-0ubuntu1) vivid; urgency=medium
+
+  * Update to SVN 20150129.
+  * Configure --with-default-libstdcxx-abi=c++11 for development,
+    --with-default-libstdcxx-abi=c++98 for backports.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 29 Jan 2015 17:47:03 +0100
+
+gcc-5 (5-20150128-0ubuntu1) vivid; urgency=medium
+
+  * Update to SVN 20150128.
+  * Update GDC for GCC 5.
+  * Build GDC multilib packages.
+  * Update cross-install-location.diff for gcc-5. Closes: #776100.
+  * Re-enable libgccjit on AArch64.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 28 Jan 2015 23:30:09 +0100
+
+gcc-5 (5-20150127-0ubuntu2) vivid; urgency=medium
+
+  * Disable libgccjit on AArch64, compiler issue
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 27 Jan 2015 18:05:12 +0100
+
+gcc-5 (5-20150127-0ubuntu1) vivid; urgency=medium
+
+  * Update to SVN 20150127.
+  * Disable libgccjit on AArch64.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 27 Jan 2015 14:39:03 +0100
+
+gcc-5 (5-20150126-0ubuntu3) vivid; urgency=medium
+
+  * Update to SVN 20150126.
+  * More symbol file updates.
+  * Fix libbacktrace and libsanitizer multilib builds.
+  * Fix libssp builds on 64bit architectures.
+
+ -- Matthias Klose <doko@ubuntu.com>  Mon, 26 Jan 2015 18:22:53 +0100
+
+gcc-5 (5-20150121-0ubuntu2) vivid; urgency=medium
+
+  * GCC 5.
+  * Build new binary packages libcc1-0, libgccjit0, libgccjit-5-dev,
+    libgccjit-5-dbg, libgccjit-5-doc.
+  * Update symbols files (still incomplete).
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 20 Jan 2015 12:45:13 +0100
+
+gcc-4.9 (4.9.2-10ubuntu2) vivid; urgency=medium
+
+  * Update to SVN 20150116 (r219730) from the gcc-4_9-branch.
+    - Fix PR libstdc++/64476, PR libstdc++/60966, PR libstdc++/64239,
+      PR middle-end/63704 (ice on valid), PR target/64513 (x86),
+      PR rtl-optimization/64286 (wrong code), PR tree-optimization/64563 (ice),
+      PR middle-end/64391 (ice on valid), PR c++/54442 (ice on valid),
+      PR target/64358 (rs6000, wrong code), PR target/63424 (AArch64, ice on
+      valid), PR target/64479 (SH), PR rtl-optimization/64536, PR target/64505
+      (rs6000), PR target/61413 (ARM, wrong code), PR target/64507 (SH),
+      PR target/64409 (x32, ice on valid), PR c++/64487 (ice on valid),
+      PR c++/64352, PR c++/64251 (rejects valid), PR c++/64297 (ice on valid),
+      PR c++/64029 (ice on valid), PR c++/63657 (diagnostic), PR c++/38958
+      (diagnostic), PR c++/63658 (rejects valid), PR ada/64492 (build),
+      PR fortran/64528 (ice on valid), PR fortran/63733 (wrong code),
+      PR fortran/56867 (wrong code), PR fortran/64244 (ice on valid).
+  * Update the Linaro support to the 4.9-2015.01 release.
+
+ -- Matthias Klose <doko@ubuntu.com>  Fri, 16 Jan 2015 14:28:09 +0100
+
+gcc-4.9 (4.9.2-10ubuntu1) vivid; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 31 Dec 2014 04:54:06 +0100
+
+gcc-4.9 (4.9.2-10) unstable; urgency=medium
+
+  * Really add x32 multilib packages for i386 cross builds to the control file.
+    Closes: #773265.
+  * Use the final binutils 2.25 release.
+  * Tighten the gcc-4.9 dependency on libgcc-4.9-dev (YunQiang Su).
+
+ -- Matthias Klose <doko@debian.org>  Thu, 25 Dec 2014 18:10:51 +0100
+
+gcc-4.9 (4.9.2-9) unstable; urgency=medium
+
+  * Update to SVN 20141220 (r218987) from the gcc-4_9-branch.
+    - Fix PR libstdc++/64302, PR libstdc++/64303, PR c++/60955,
+      PR rtl-optimization/64010 (wrong code), PR sanitizer/64265 (wrong code).
+  * Add x32 multilib packages for i386 cross builds to the control file.
+    Closes: #773265.
+  * Fix mips64el multilib cross builds. Closes: #772665.
+  * libphobos-4.x-dev: Stop providing libphobos-dev, now a real package.
+
+ -- Matthias Klose <doko@debian.org>  Sat, 20 Dec 2014 07:47:15 +0100
+
+gcc-4.9 (4.9.2-8) unstable; urgency=medium
+
+  * Update to SVN 20141214 (r218721) from the gcc-4_9-branch.
+    - Fix PR tree-optimization/62021 (ice), PR middle-end/64225 (missed
+      optimization), PR libstdc++/64239, PR rtl-optimization/64037 (wrong
+      code), PR target/64200 (x86, ice), PR tree-optimization/64269 (ice).
+  * Don't build libphobos multilibs, there is no gdc-multilib build.
+  * Really disable the sanitizer libs on powerpc, ppc64 and ppc64el.
+  * Paste config.log files to stdout in case of build errors.
+
+ -- Matthias Klose <doko@debian.org>  Sun, 14 Dec 2014 18:43:49 +0100
+
+gcc-4.9 (4.9.2-7ubuntu3) vivid; urgency=medium
+
+  * Fix the powerpc build.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 11 Dec 2014 15:52:15 +0100
+
+gcc-4.9 (4.9.2-7ubuntu2) vivid; urgency=medium
+
+  * Update to SVN 20141211 (r218620) from the gcc-4_9-branch.
+    - Fix PR tree-optimization/62021 (ice), PR middle-end/64225 (missed
+      optimization).
+  * Don't build libphobos multilibs, there is no gdc-multilib built.
+  * Really disable the sanitizer libs on powerpc, ppc64 and ppc64el.
+  * Paste config.log files to stdout in case of build errors.
+
+ -- Matthias Klose <doko@ubuntu.com>  Thu, 11 Dec 2014 12:04:13 +0100
+
+gcc-4.9 (4.9.2-7ubuntu1) vivid; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Wed, 10 Dec 2014 15:27:33 +0100
+
+gcc-4.9 (4.9.2-7) unstable; urgency=medium
+
+  * Update to SVN 20141210 (r218575) from the gcc-4_9-branch.
+    - Fix PR libstdc++/64203, PR target/55351 (SH), PR tree-optimization/61686,
+      PR bootstrap/64213.
+    - libgcc hppa backports.
+  * Fix cross builds with dpkg-architecture unconditionally exporting
+    target variables. For now specify the target architecture
+    in debian/target. This still needs to work with older dpkg versions,
+    so don't "simplify" the packaging. Closes: #768167.
+
+ -- Matthias Klose <doko@debian.org>  Wed, 10 Dec 2014 13:32:42 +0100
+
+gcc-4.9 (4.9.2-6ubuntu1) vivid; urgency=medium
+
+  * Merge with Debian; remaining changes:
+    - Build from upstream sources.
+
+ -- Matthias Klose <doko@ubuntu.com>  Tue, 09 Dec 2014 13:47:24 +0100
+
+# For older changelog entries, run 'apt-get changelog gcc-4.9-base'
--- gcc-6-6.4.0.orig/debian/compat
+++ gcc-6-6.4.0/debian/compat
@@ -0,0 +1 @@
+9
--- gcc-6-6.4.0.orig/debian/control
+++ gcc-6-6.4.0/debian/control
@@ -0,0 +1,1873 @@
+Source: gcc-6
+Section: devel
+Priority: optional
+Maintainer: Ubuntu Core developers <ubuntu-devel-discuss@lists.ubuntu.com>
+XSBC-Original-Maintainer: Debian GCC Maintainers <debian-gcc@lists.debian.org>
+Uploaders: Matthias Klose <doko@debian.org>
+Standards-Version: 4.1.3
+Build-Depends: debhelper (>= 9.20141010), dpkg-dev (>= 1.17.14), 
+  g++-multilib [amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mips64r6 mips64r6el mipsel mipsn32 mipsn32el mipsn32r6 mipsn32r6el mipsr6 mipsr6el powerpc ppc64 s390 s390x sparc sparc64 x32] <!cross>, g++-6 [arm64] <!cross>, 
+  libc6.1-dev (>= 2.13-0ubuntu6) [alpha ia64] | libc0.3-dev (>= 2.13-0ubuntu6) [hurd-i386] | libc0.1-dev (>= 2.13-0ubuntu6) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= 2.13-0ubuntu6), libc6-dev (>= 2.13-31) [armel armhf], libc6-dev-amd64 [i386 x32], libc6-dev-sparc64 [sparc], libc6-dev-sparc [sparc64], libc6-dev-s390 [s390x], libc6-dev-s390x [s390], libc6-dev-i386 [amd64 x32], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el s390x sparc64 x32], libn32gcc1 [mips mipsel mips64 mips64el mipsr6 mipsr6el mips64r6 mips64r6el], lib64gcc1 [i386 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el powerpc sparc s390 x32], libc6-dev-mips64 [mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el], libc6-dev-mipsn32 [mips mipsel mips64 mips64el mipsr6 mipsr6el mips64r6 mips64r6el], libc6-dev-mips32 [mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el], libc6-dev-x32 [amd64 i386], libx32gcc1 [amd64 i386], libc6-dev-armhf [armel], libhfgcc1 [armel], libc6-dev-armel [armhf], libsfgcc1 [armhf], libc6.1-dbg [alpha ia64] | libc0.3-dbg [hurd-i386] | libc0.1-dbg [kfreebsd-i386 kfreebsd-amd64] | libc6-dbg, 
+  kfreebsd-kernel-headers (>= 0.84) [kfreebsd-any], linux-libc-dev [m68k], 
+  m4, libtool, autoconf2.64, gcc-7-base, 
+  libunwind8-dev [ia64], libatomic-ops-dev [ia64], 
+  autogen, gawk, lzma, xz-utils, patchutils, 
+  zlib1g-dev, systemtap-sdt-dev [linux-any kfreebsd-any hurd-any], 
+  binutils:native (>= 2.30) | binutils-multiarch:native (>= 2.30), binutils-hppa64-linux-gnu:native (>= 2.30) [hppa amd64 i386 x32], 
+  gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext, 
+  gdb:native, 
+  texinfo (>= 4.3), locales, sharutils, 
+  procps, zlib1g-dev, libantlr-java, python:native, libffi-dev, fastjar, libmagic-dev, libecj-java (>= 3.3.0-2), zip, libasound2-dev [ !hurd-any !kfreebsd-any], libxtst-dev, libxt-dev, libgtk2.0-dev (>= 2.4.4-2), libart-2.0-dev, libcairo2-dev, gnat-6:native [!m32r !sh3 !sh3eb !sh4eb !powerpcspe !m68k !mips64 !x32], g++-6:native, netbase, 
+  libisl-dev, libmpc-dev (>= 1.1), libmpfr-dev (>= 3.0.0-9~), libgmp-dev (>= 2:5.0.1~), lib32z1-dev [amd64 kfreebsd-amd64], lib64z1-dev [i386], libx32z1-dev [amd64 kfreebsd-amd64 i386], 
+  dejagnu [!m68k !hurd-amd64 !hurd-i386 !hurd-alpha !kfreebsd-amd64 !kfreebsd-i386 !kfreebsd-alpha], coreutils (>= 2.26) | realpath (>= 1.9.12), chrpath, lsb-release, quilt, 
+  pkg-config, libgc-dev, 
+   g++-6-alpha-linux-gnu [alpha] <cross>, gobjc-6-alpha-linux-gnu [alpha] <cross>, gfortran-6-alpha-linux-gnu [alpha] <cross>, gcj-6-alpha-linux-gnu [alpha] <cross>, gdc-6-alpha-linux-gnu [alpha] <cross>, gccgo-6-alpha-linux-gnu [alpha] <cross>, gnat-6-alpha-linux-gnu [alpha] <cross>, g++-6-x86-64-linux-gnu [amd64] <cross>, gobjc-6-x86-64-linux-gnu [amd64] <cross>, gfortran-6-x86-64-linux-gnu [amd64] <cross>, gcj-6-x86-64-linux-gnu [amd64] <cross>, gdc-6-x86-64-linux-gnu [amd64] <cross>, gccgo-6-x86-64-linux-gnu [amd64] <cross>, gnat-6-x86-64-linux-gnu [amd64] <cross>, g++-6-arm-linux-gnueabi [armel] <cross>, gobjc-6-arm-linux-gnueabi [armel] <cross>, gfortran-6-arm-linux-gnueabi [armel] <cross>, gcj-6-arm-linux-gnueabi [armel] <cross>, gdc-6-arm-linux-gnueabi [armel] <cross>, gccgo-6-arm-linux-gnueabi [armel] <cross>, gnat-6-arm-linux-gnueabi [armel] <cross>, g++-6-arm-linux-gnueabihf [armhf] <cross>, gobjc-6-arm-linux-gnueabihf [armhf] <cross>, gfortran-6-arm-linux-gnueabihf [armhf] <cross>, gcj-6-arm-linux-gnueabihf [armhf] <cross>, gdc-6-arm-linux-gnueabihf [armhf] <cross>, gccgo-6-arm-linux-gnueabihf [armhf] <cross>, gnat-6-arm-linux-gnueabihf [armhf] <cross>, g++-6-aarch64-linux-gnu [arm64] <cross>, gobjc-6-aarch64-linux-gnu [arm64] <cross>, gfortran-6-aarch64-linux-gnu [arm64] <cross>, gcj-6-aarch64-linux-gnu [arm64] <cross>, gdc-6-aarch64-linux-gnu [arm64] <cross>, gccgo-6-aarch64-linux-gnu [arm64] <cross>, gnat-6-aarch64-linux-gnu [arm64] <cross>, g++-6-i686-linux-gnu [i386] <cross>, gobjc-6-i686-linux-gnu [i386] <cross>, gfortran-6-i686-linux-gnu [i386] <cross>, gcj-6-i686-linux-gnu [i386] <cross>, gdc-6-i686-linux-gnu [i386] <cross>, gccgo-6-i686-linux-gnu [i386] <cross>, gnat-6-i686-linux-gnu [i386] <cross>, g++-6-mips-linux-gnu [mips] <cross>, gobjc-6-mips-linux-gnu [mips] <cross>, gfortran-6-mips-linux-gnu [mips] <cross>, gcj-6-mips-linux-gnu [mips] <cross>, gdc-6-mips-linux-gnu [mips] <cross>, gccgo-6-mips-linux-gnu [mips] <cross>, gnat-6-mips-linux-gnu [mips] <cross>, g++-6-mipsel-linux-gnu [mipsel] <cross>, gobjc-6-mipsel-linux-gnu [mipsel] <cross>, gfortran-6-mipsel-linux-gnu [mipsel] <cross>, gcj-6-mipsel-linux-gnu [mipsel] <cross>, gdc-6-mipsel-linux-gnu [mipsel] <cross>, gccgo-6-mipsel-linux-gnu [mipsel] <cross>, gnat-6-mipsel-linux-gnu [mipsel] <cross>, g++-6-mips64-linux-gnuabi64 [mips64] <cross>, gobjc-6-mips64-linux-gnuabi64 [mips64] <cross>, gfortran-6-mips64-linux-gnuabi64 [mips64] <cross>, gcj-6-mips64-linux-gnuabi64 [mips64] <cross>, gdc-6-mips64-linux-gnuabi64 [mips64] <cross>, gccgo-6-mips64-linux-gnuabi64 [mips64] <cross>, g++-6-mips64el-linux-gnuabi64 [mips64el] <cross>, gobjc-6-mips64el-linux-gnuabi64 [mips64el] <cross>, gfortran-6-mips64el-linux-gnuabi64 [mips64el] <cross>, gcj-6-mips64el-linux-gnuabi64 [mips64el] <cross>, gdc-6-mips64el-linux-gnuabi64 [mips64el] <cross>, gccgo-6-mips64el-linux-gnuabi64 [mips64el] <cross>, gnat-6-mips64el-linux-gnuabi64 [mips64el] <cross>, g++-6-mips64-linux-gnuabin32 [mipsn32] <cross>, gobjc-6-mips64-linux-gnuabin32 [mipsn32] <cross>, gfortran-6-mips64-linux-gnuabin32 [mipsn32] <cross>, gcj-6-mips64-linux-gnuabin32 [mipsn32] <cross>, gdc-6-mips64-linux-gnuabin32 [mipsn32] <cross>, gccgo-6-mips64-linux-gnuabin32 [mipsn32] <cross>, gnat-6-mips64-linux-gnuabin32 [mipsn32] <cross>, g++-6-powerpc-linux-gnu [powerpc] <cross>, gobjc-6-powerpc-linux-gnu [powerpc] <cross>, gfortran-6-powerpc-linux-gnu [powerpc] <cross>, gcj-6-powerpc-linux-gnu [powerpc] <cross>, gdc-6-powerpc-linux-gnu [powerpc] <cross>, gccgo-6-powerpc-linux-gnu [powerpc] <cross>, gnat-6-powerpc-linux-gnu [powerpc] <cross>, g++-6-powerpc64-linux-gnu [ppc64] <cross>, gobjc-6-powerpc64-linux-gnu [ppc64] <cross>, gfortran-6-powerpc64-linux-gnu [ppc64] <cross>, gcj-6-powerpc64-linux-gnu [ppc64] <cross>, gdc-6-powerpc64-linux-gnu [ppc64] <cross>, gccgo-6-powerpc64-linux-gnu [ppc64] <cross>, gnat-6-powerpc64-linux-gnu [ppc64] <cross>, g++-6-powerpc64le-linux-gnu [ppc64el] <cross>, gobjc-6-powerpc64le-linux-gnu [ppc64el] <cross>, gfortran-6-powerpc64le-linux-gnu [ppc64el] <cross>, gcj-6-powerpc64le-linux-gnu [ppc64el] <cross>, gdc-6-powerpc64le-linux-gnu [ppc64el] <cross>, gccgo-6-powerpc64le-linux-gnu [ppc64el] <cross>, gnat-6-powerpc64le-linux-gnu [ppc64el] <cross>, g++-6-m68k-linux-gnu [m68k] <cross>, gobjc-6-m68k-linux-gnu [m68k] <cross>, gfortran-6-m68k-linux-gnu [m68k] <cross>, gcj-6-m68k-linux-gnu [m68k] <cross>, gdc-6-m68k-linux-gnu [m68k] <cross>, g++-6-sh4-linux-gnu [sh4] <cross>, gobjc-6-sh4-linux-gnu [sh4] <cross>, gfortran-6-sh4-linux-gnu [sh4] <cross>, gcj-6-sh4-linux-gnu [sh4] <cross>, g++-6-sparc64-linux-gnu [sparc64] <cross>, gobjc-6-sparc64-linux-gnu [sparc64] <cross>, gfortran-6-sparc64-linux-gnu [sparc64] <cross>, gcj-6-sparc64-linux-gnu [sparc64] <cross>, gdc-6-sparc64-linux-gnu [sparc64] <cross>, gccgo-6-sparc64-linux-gnu [sparc64] <cross>, g++-6-s390x-linux-gnu [s390x] <cross>, gobjc-6-s390x-linux-gnu [s390x] <cross>, gfortran-6-s390x-linux-gnu [s390x] <cross>, gcj-6-s390x-linux-gnu [s390x] <cross>, gdc-6-s390x-linux-gnu [s390x] <cross>, gccgo-6-s390x-linux-gnu [s390x] <cross>, gnat-6-s390x-linux-gnu [s390x] <cross>, g++-6-x86-64-linux-gnux32 [x32] <cross>, gobjc-6-x86-64-linux-gnux32 [x32] <cross>, gfortran-6-x86-64-linux-gnux32 [x32] <cross>, gcj-6-x86-64-linux-gnux32 [x32] <cross>, gdc-6-x86-64-linux-gnux32 [x32] <cross>, gccgo-6-x86-64-linux-gnux32 [x32] <cross>, g++-6-mips64el-linux-gnuabin32 [mipsn32el] <cross>, gobjc-6-mips64el-linux-gnuabin32 [mipsn32el] <cross>, gfortran-6-mips64el-linux-gnuabin32 [mipsn32el] <cross>, gcj-6-mips64el-linux-gnuabin32 [mipsn32el] <cross>, gdc-6-mips64el-linux-gnuabin32 [mipsn32el] <cross>, gccgo-6-mips64el-linux-gnuabin32 [mipsn32el] <cross>, gnat-6-mips64el-linux-gnuabin32 [mipsn32el] <cross>, g++-6-mipsisa32r6-linux-gnu [mipsr6] <cross>, gobjc-6-mipsisa32r6-linux-gnu [mipsr6] <cross>, gfortran-6-mipsisa32r6-linux-gnu [mipsr6] <cross>, gcj-6-mipsisa32r6-linux-gnu [mipsr6] <cross>, gdc-6-mipsisa32r6-linux-gnu [mipsr6] <cross>, gccgo-6-mipsisa32r6-linux-gnu [mipsr6] <cross>, gnat-6-mipsisa32r6-linux-gnu [mipsr6] <cross>, g++-6-mipsisa32r6el-linux-gnu [mipsr6el] <cross>, gobjc-6-mipsisa32r6el-linux-gnu [mipsr6el] <cross>, gfortran-6-mipsisa32r6el-linux-gnu [mipsr6el] <cross>, gcj-6-mipsisa32r6el-linux-gnu [mipsr6el] <cross>, gdc-6-mipsisa32r6el-linux-gnu [mipsr6el] <cross>, gccgo-6-mipsisa32r6el-linux-gnu [mipsr6el] <cross>, gnat-6-mipsisa32r6el-linux-gnu [mipsr6el] <cross>, g++-6-mipsisa64r6-linux-gnuabi64 [mips64r6] <cross>, gobjc-6-mipsisa64r6-linux-gnuabi64 [mips64r6] <cross>, gfortran-6-mipsisa64r6-linux-gnuabi64 [mips64r6] <cross>, gcj-6-mipsisa64r6-linux-gnuabi64 [mips64r6] <cross>, gdc-6-mipsisa64r6-linux-gnuabi64 [mips64r6] <cross>, gccgo-6-mipsisa64r6-linux-gnuabi64 [mips64r6] <cross>, gnat-6-mipsisa64r6-linux-gnuabi64 [mips64r6] <cross>, g++-6-mipsisa64r6el-linux-gnuabi64 [mips64r6el] <cross>, gobjc-6-mipsisa64r6el-linux-gnuabi64 [mips64r6el] <cross>, gfortran-6-mipsisa64r6el-linux-gnuabi64 [mips64r6el] <cross>, gcj-6-mipsisa64r6el-linux-gnuabi64 [mips64r6el] <cross>, gdc-6-mipsisa64r6el-linux-gnuabi64 [mips64r6el] <cross>, gccgo-6-mipsisa64r6el-linux-gnuabi64 [mips64r6el] <cross>, gnat-6-mipsisa64r6el-linux-gnuabi64 [mips64r6el] <cross>, g++-6-mipsisa64r6-linux-gnuabin32 [mipsn32r6] <cross>, gobjc-6-mipsisa64r6-linux-gnuabin32 [mipsn32r6] <cross>, gfortran-6-mipsisa64r6-linux-gnuabin32 [mipsn32r6] <cross>, gcj-6-mipsisa64r6-linux-gnuabin32 [mipsn32r6] <cross>, gdc-6-mipsisa64r6-linux-gnuabin32 [mipsn32r6] <cross>, gccgo-6-mipsisa64r6-linux-gnuabin32 [mipsn32r6] <cross>, gnat-6-mipsisa64r6-linux-gnuabin32 [mipsn32r6] <cross>, g++-6-mipsisa64r6el-linux-gnuabin32 [mipsn32r6el] <cross>, gobjc-6-mipsisa64r6el-linux-gnuabin32 [mipsn32r6el] <cross>, gfortran-6-mipsisa64r6el-linux-gnuabin32 [mipsn32r6el] <cross>, gcj-6-mipsisa64r6el-linux-gnuabin32 [mipsn32r6el] <cross>, gdc-6-mipsisa64r6el-linux-gnuabin32 [mipsn32r6el] <cross>, gccgo-6-mipsisa64r6el-linux-gnuabin32 [mipsn32r6el] <cross>, gnat-6-mipsisa64r6el-linux-gnuabin32 [mipsn32r6el] <cross>, 
+Build-Depends-Indep: doxygen (>= 1.7.2), graphviz (>= 2.2), ghostscript, texlive-latex-base, xsltproc, libxml2-utils, docbook-xsl-ns, 
+Homepage: http://gcc.gnu.org/
+Vcs-Browser: http://svn.debian.org/viewsvn/gcccvs/branches/sid/gcc-6/
+Vcs-Svn: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-6
+
+Package: gcc-6-base
+Architecture: any
+Multi-Arch: same
+Section: libs
+Priority: required
+Depends: ${misc:Depends}
+Replaces: ${base:Replaces}
+Breaks: ${base:Breaks}
+Description: GCC, the GNU Compiler Collection (base package)
+ This package contains files common to all languages and libraries
+ contained in the GNU Compiler Collection (GCC).
+
+Package: libgcc-6-dev
+Architecture: any
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libitm},
+ ${dep:libatomic}, ${dep:libbtrace}, ${dep:libasan}, ${dep:liblsan},
+ ${dep:libtsan}, ${dep:libubsan}, ${dep:libcilkrts}, ${dep:libvtv},
+ ${dep:libmpx},
+ ${dep:libqmath}, ${dep:libunwinddev}, ${shlibs:Depends}, ${misc:Depends}
+Multi-Arch: same
+Replaces: gccgo-6 (<< ${gcc:Version})
+Description: GCC support library (development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: libgcc4
+Architecture: hppa
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+Section: libs
+Priority: required
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: GCC support library
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+
+Package: libgcc4-dbg
+Architecture: hppa
+Multi-Arch: same
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgcc4 (= ${gcc:EpochVersion}), ${misc:Depends}
+Description: GCC support library (debug symbols)
+ Debug symbols for the GCC support library.
+
+Package: lib64gcc-6-dev
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+Description: GCC support library (64bit development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: lib32gcc-6-dev
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+Description: GCC support library (32 bit development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: libhfgcc-6-dev
+Architecture: armel
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+Description: GCC support library (hard float ABI development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: libsfgcc-6-dev
+Architecture: armhf
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+Description: GCC support library (soft float ABI development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: libn32gcc-6-dev
+Architecture: mips mipsel mips64 mips64el mipsr6 mipsr6el mips64r6 mips64r6el
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+Description: GCC support library (n32 development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: libx32gcc-6-dev
+Architecture: amd64 i386
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+Description: GCC support library (x32 development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+
+Package: gcc-6
+Architecture: any
+Section: devel
+Priority: optional
+Depends: cpp-6 (= ${gcc:Version}), gcc-6-base (= ${gcc:Version}),
+    ${dep:libcc1}, 
+  binutils (>= ${binutils:Version}), 
+  ${dep:libgccdev}, ${shlibs:Depends}, ${misc:Depends}
+Recommends: ${dep:libcdev}
+Replaces: gccgo-6 (<< ${gcc:Version}), cpp-6 (<< 6.3.0-21)
+Suggests: ${gcc:multilib}, gcc-6-doc (>= ${gcc:SoftVersion}),
+ gcc-6-locales (>= ${gcc:SoftVersion}),
+ libgcc1-dbg (>= ${libgcc:Version}),
+ libgomp1-dbg (>= ${gcc:Version}),
+ libitm1-dbg (>= ${gcc:Version}),
+ libatomic1-dbg (>= ${gcc:Version}),
+ libasan3-dbg (>= ${gcc:Version}),
+ liblsan0-dbg (>= ${gcc:Version}),
+ libtsan0-dbg (>= ${gcc:Version}),
+ libubsan0-dbg (>= ${gcc:Version}),
+ libcilkrts5-dbg (>= ${gcc:Version}),
+ libmpx2-dbg (>= ${gcc:Version}),
+ libquadmath0-dbg (>= ${gcc:Version})
+Provides: c-compiler
+Description: GNU C compiler
+ This is the GNU C compiler, a fairly portable optimizing compiler for C.
+
+Package: gcc-6-multilib
+Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mips64r6 mips64r6el mipsel mipsn32 mipsn32el mipsn32r6 mipsn32r6el mipsr6 mipsr6el powerpc ppc64 s390 s390x sparc sparc64 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Description: GNU C compiler (multilib support)
+ This is the GNU C compiler, a fairly portable optimizing compiler for C.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: gcc-6-test-results
+Architecture: any
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${misc:Depends}
+Replaces: g++-5 (<< 5.2.1-28)
+Description: Test results for the GCC test suite
+ This package contains the test results for running the GCC test suite
+ for a post build analysis.
+
+Package: gcc-6-plugin-dev
+Architecture: any
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), libgmp-dev (>= 2:5.0.1~), libmpc-dev (>= 1.1), ${shlibs:Depends}, ${misc:Depends}
+Description: Files for GNU GCC plugin development.
+ This package contains (header) files for GNU GCC plugin development. It
+ is only used for the development of GCC plugins, but not needed to run
+ plugins.
+
+Package: gcc-6-hppa64-linux-gnu
+Architecture: hppa amd64 i386 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}),
+  binutils-hppa64-linux-gnu | binutils-hppa64, 
+  ${shlibs:Depends}, ${misc:Depends}
+Description: GNU C compiler (cross compiler for hppa64)
+ This is the GNU C compiler, a fairly portable optimizing compiler for C.
+
+Package: cpp-6
+Architecture: any
+Section: interpreters
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Suggests: gcc-6-locales (>= ${gcc:SoftVersion})
+Replaces: gccgo-6 (<< ${gcc:Version})
+Breaks: libmagics++-dev (<< 2.28.0-4), hardening-wrapper (<< 2.8+nmu3)
+Description: GNU C preprocessor
+ A macro processor that is used automatically by the GNU C compiler
+ to transform programs before actual compilation.
+ .
+ This package has been separated from gcc for the benefit of those who
+ require the preprocessor but not the compiler.
+
+Package: cpp-6-doc
+Architecture: all
+Section: doc
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Description: Documentation for the GNU C preprocessor (cpp)
+ Documentation for the GNU C preprocessor in info format.
+
+Package: gcc-6-locales
+Architecture: all
+Section: devel
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), cpp-6 (>= ${gcc:SoftVersion}), ${misc:Depends}
+Recommends: gcc-6 (>= ${gcc:SoftVersion})
+Description: GCC, the GNU compiler collection (native language support files)
+ Native language support for GCC. Lets GCC speak your language,
+ if translations are available.
+ .
+ Please do NOT submit bug reports in other languages than "C".
+ Always reset your language settings to use the "C" locales.
+
+Package: g++-6
+Architecture: any
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), libstdc++-6-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Provides: c++-compiler, c++abi2-dev
+Suggests: ${gxx:multilib}, gcc-6-doc (>= ${gcc:SoftVersion}), libstdc++6-6-dbg (>= ${gcc:Version})
+Description: GNU C++ compiler
+ This is the GNU C++ compiler, a fairly portable optimizing compiler for C++.
+
+Package: g++-6-multilib
+Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mips64r6 mips64r6el mipsel mipsn32 mipsn32el mipsn32r6 mipsn32r6el mipsr6 mipsr6el powerpc ppc64 s390 s390x sparc sparc64 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), g++-6 (= ${gcc:Version}), gcc-6-multilib (= ${gcc:Version}), ${dep:libcxxbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: ${dep:libcxxbiarchdbg}
+Description: GNU C++ compiler (multilib support)
+ This is the GNU C++ compiler, a fairly portable optimizing compiler for C++.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: libasan3
+Section: libs
+Architecture: any
+Provides: libasan3-armel [armel], libasan3-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libasan3-dbg
+Architecture: any
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libasan3 (= ${gcc:Version}), ${misc:Depends}
+Provides: libasan3-dbg-armel [armel], libasan3-dbg-armhf [armhf]
+Multi-Arch: same
+Description: AddressSanitizer -- a fast memory error detector (debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib32asan3
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: AddressSanitizer -- a fast memory error detector (32bit)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib32asan3-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32asan3 (= ${gcc:Version}), ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (32 bit debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib64asan3
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (64bit)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib64asan3-dbg
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64asan3 (= ${gcc:Version}), ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (64bit debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+#Package: libn32asan`'ASAN_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: optional
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: AddressSanitizer -- a fast memory error detector (n32)
+# AddressSanitizer (ASan) is a fast memory error detector.  It finds
+# use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+#Package: libn32asan`'ASAN_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: optional
+#Depends: BASELDEP, libdep(asan`'ASAN_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: AddressSanitizer -- a fast memory error detector (n32 debug symbols)
+# AddressSanitizer (ASan) is a fast memory error detector.  It finds
+# use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libx32asan3
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (x32)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libx32asan3-dbg
+Architecture: amd64 i386
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32asan3 (= ${gcc:Version}), ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (x32 debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libhfasan3
+Section: libs
+Architecture: armel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libasan3-armhf [armel]
+Description: AddressSanitizer -- a fast memory error detector (hard float ABI)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libhfasan3-dbg
+Architecture: armel
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libhfasan3 (= ${gcc:Version}), ${misc:Depends}
+Conflicts: libasan3-armel [armhf]
+Description: AddressSanitizer -- a fast memory error detector (hard float ABI debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libsfasan3
+Section: libs
+Architecture: armhf
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (soft float ABI)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libsfasan3-dbg
+Architecture: armhf
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libsfasan3 (= ${gcc:Version}), ${misc:Depends}
+Description: AddressSanitizer -- a fast memory error detector (soft float ABI debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libmpx2
+Section: libs
+Architecture: any
+Provides: libmpx2-armel [armel], libmpx2-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Replaces: libmpx0 (<< 6-20160120-1)
+Description: Intel memory protection extensions (runtime)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libmpx2-dbg
+Architecture: any
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libmpx2 (= ${gcc:Version}), ${misc:Depends}
+Provides: libmpx2-dbg-armel [armel], libmpx2-dbg-armhf [armhf]
+Multi-Arch: same
+Description: Intel memory protection extensions (debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: lib32mpx2
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Replaces: lib32mpx0 (<< 6-20160120-1)
+Description: Intel memory protection extensions (32bit)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: lib32mpx2-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32mpx2 (= ${gcc:Version}), ${misc:Depends}
+Description: Intel memory protection extensions (32 bit debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: lib64mpx2
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib64mpx0 (<< 6-20160120-1)
+Description: Intel memory protection extensions (64bit)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: lib64mpx2-dbg
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64mpx2 (= ${gcc:Version}), ${misc:Depends}
+Description: Intel memory protection extensions (64bit debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libgccjit-6-doc
+Section: doc
+Architecture: all
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${misc:Depends}
+Conflicts: libgccjit-5-doc
+Description: GCC just-in-time compilation (documentation)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit-6-dev
+Section: libdevel
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgccjit0 (>= ${gcc:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+Suggests: libgccjit-6-dbg
+Description: GCC just-in-time compilation (development files)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: gobjc++-6
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gobjc-6 (= ${gcc:Version}), g++-6 (= ${gcc:Version}), ${shlibs:Depends}, libobjc-6-dev (= ${gcc:Version}), ${misc:Depends}
+Suggests: ${gobjcxx:multilib}, gcc-6-doc (>= ${gcc:SoftVersion})
+Provides: objc++-compiler
+Description: GNU Objective-C++ compiler
+ This is the GNU Objective-C++ compiler, which compiles
+ Objective-C++ on platforms supported by the gcc compiler. It uses the
+ gcc backend to generate optimized code.
+
+Package: gobjc++-6-multilib
+Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mips64r6 mips64r6el mipsel mipsn32 mipsn32el mipsn32r6 mipsn32r6el mipsr6 mipsr6el powerpc ppc64 s390 s390x sparc sparc64 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gobjc++-6 (= ${gcc:Version}), g++-6-multilib (= ${gcc:Version}), gobjc-6-multilib (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Objective-C++ compiler (multilib support)
+ This is the GNU Objective-C++ compiler, which compiles Objective-C++ on
+ platforms supported by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: gobjc-6
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libobjc-6-dev (= ${gcc:Version}), ${misc:Depends}
+Suggests: ${gobjc:multilib}, gcc-6-doc (>= ${gcc:SoftVersion}), libobjc4-dbg (>= ${gcc:Version})
+Provides: objc-compiler
+Description: GNU Objective-C compiler
+ This is the GNU Objective-C compiler, which compiles
+ Objective-C on platforms supported by the gcc compiler. It uses the
+ gcc backend to generate optimized code.
+
+Package: gobjc-6-multilib
+Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mips64r6 mips64r6el mipsel mipsn32 mipsn32el mipsn32r6 mipsn32r6el mipsr6 mipsr6el powerpc ppc64 s390 s390x sparc sparc64 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gobjc-6 (= ${gcc:Version}), gcc-6-multilib (= ${gcc:Version}), ${dep:libobjcbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Objective-C compiler (multilib support)
+ This is the GNU Objective-C compiler, which compiles Objective-C on platforms
+ supported by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: libobjc-6-dev
+Architecture: any
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgcc-6-dev (= ${gcc:Version}), libobjc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Multi-Arch: same
+Description: Runtime library for GNU Objective-C applications (development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: lib64objc-6-dev
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64gcc-6-dev (= ${gcc:Version}), lib64objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (64bit development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: lib32objc-6-dev
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32gcc-6-dev (= ${gcc:Version}), lib32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (32bit development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: libn32objc-6-dev
+Architecture: mips mipsel mips64 mips64el mipsr6 mipsr6el mips64r6 mips64r6el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libn32gcc-6-dev (= ${gcc:Version}), libn32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (n32 development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: libx32objc-6-dev
+Architecture: amd64 i386
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32gcc-6-dev (= ${gcc:Version}), libx32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (x32 development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: libhfobjc-6-dev
+Architecture: armel
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libhfgcc-6-dev (= ${gcc:Version}), libhfobjc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (hard float ABI development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: libsfobjc-6-dev
+Architecture: armhf
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libsfgcc-6-dev (= ${gcc:Version}), libsfobjc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Objective-C applications (soft float development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: gfortran-6
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), libgfortran-6-dev (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Provides: fortran95-compiler, ${fortran:mod-version}
+Suggests: ${gfortran:multilib}, gfortran-6-doc,
+ libgfortran3-dbg (>= ${gcc:Version}),
+ libcoarrays-dev
+Description: GNU Fortran compiler
+ This is the GNU Fortran compiler, which compiles
+ Fortran on platforms supported by the gcc compiler. It uses the
+ gcc backend to generate optimized code.
+
+Package: gfortran-6-multilib
+Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mips64r6 mips64r6el mipsel mipsn32 mipsn32el mipsn32r6 mipsn32r6el mipsr6 mipsr6el powerpc ppc64 s390 s390x sparc sparc64 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gfortran-6 (= ${gcc:Version}), gcc-6-multilib (= ${gcc:Version}), ${dep:libgfortranbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Fortran compiler (multilib support)
+ This is the GNU Fortran compiler, which compiles Fortran on platforms
+ supported by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: gfortran-6-doc
+Architecture: all
+Section: doc
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Description: Documentation for the GNU Fortran compiler (gfortran)
+ Documentation for the GNU Fortran compiler in info format.
+
+Package: libgfortran-6-dev
+Architecture: any
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgcc-6-dev (= ${gcc:Version}), libgfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Multi-Arch: same
+Description: Runtime library for GNU Fortran applications (development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: lib64gfortran-6-dev
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64gcc-6-dev (= ${gcc:Version}), lib64gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (64bit development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: lib32gfortran-6-dev
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32gcc-6-dev (= ${gcc:Version}), lib32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (32bit development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: libn32gfortran-6-dev
+Architecture: mips mipsel mips64 mips64el mipsr6 mipsr6el mips64r6 mips64r6el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libn32gcc-6-dev (= ${gcc:Version}), libn32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (n32 development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: libx32gfortran-6-dev
+Architecture: amd64 i386
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32gcc-6-dev (= ${gcc:Version}), libx32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (x32 development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: libhfgfortran-6-dev
+Architecture: armel
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libhfgcc-6-dev (= ${gcc:Version}), libhfgfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (hard float ABI development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: libsfgfortran-6-dev
+Architecture: armhf
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libsfgcc-6-dev (= ${gcc:Version}), libsfgfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (soft float ABI development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: libgfortran3
+Section: libs
+Architecture: any
+Provides: libgfortran3-armel [armel], libgfortran3-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libgfortran3-dbg
+Section: debug
+Architecture: any
+Provides: libgfortran3-dbg-armel [armel], libgfortran3-dbg-armhf [armhf]
+Multi-Arch: same
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgfortran3 (= ${gcc:Version}), libgcc1-dbg (>= ${libgcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: lib64gfortran3
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (64bit)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: lib64gfortran3-dbg
+Section: debug
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64gfortran3 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (64bit debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: lib32gfortran3
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Description: Runtime library for GNU Fortran applications (32bit)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: lib32gfortran3-dbg
+Section: debug
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32gfortran3 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (32 bit debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libn32gfortran3
+Section: libs
+Architecture: mips mipsel mips64 mips64el mipsr6 mipsr6el mips64r6 mips64r6el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (n32)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libn32gfortran3-dbg
+Section: debug
+Architecture: mips mipsel mips64 mips64el mipsr6 mipsr6el mips64r6 mips64r6el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libn32gfortran3 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (n32 debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libx32gfortran3
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (x32)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libx32gfortran3-dbg
+Section: debug
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32gfortran3 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Fortran applications (x32 debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libhfgfortran3
+Section: libs
+Architecture: armel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libgfortran3-armhf [armel]
+Description: Runtime library for GNU Fortran applications (hard float ABI)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libhfgfortran3-dbg
+Section: debug
+Architecture: armel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libhfgfortran3 (= ${gcc:Version}), ${misc:Depends}
+Conflicts: libgfortran3-dbg-armhf [armel]
+Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libsfgfortran3
+Section: libs
+Architecture: armhf
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libgfortran3-armel [armhf]
+Description: Runtime library for GNU Fortran applications (soft float ABI)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libsfgfortran3-dbg
+Section: debug
+Architecture: armhf
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libsfgfortran3 (= ${gcc:Version}), ${misc:Depends}
+Conflicts: libgfortran3-dbg-armel [armhf]
+Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: gccgo-6
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), libgo9 (>= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Provides: go-compiler
+Suggests: ${go:multilib}, gccgo-6-doc, libgo9-dbg (>= ${gcc:Version})
+Conflicts: ${golang:Conflicts}
+Breaks: libgo9 (<< 6.4.0-12)
+Replaces: libgo9 (<< 6.4.0-12)
+Description: GNU Go compiler
+ This is the GNU Go compiler, which compiles Go on platforms supported
+ by the gcc compiler. It uses the gcc backend to generate optimized code.
+
+Package: gccgo-6-multilib
+Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mips64r6 mips64r6el mipsel mipsn32 mipsn32el mipsn32r6 mipsn32r6el mipsr6 mipsr6el powerpc ppc64 s390 s390x sparc sparc64 x32
+Section: devel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gccgo-6 (= ${gcc:Version}), gcc-6-multilib (= ${gcc:Version}), ${dep:libgobiarch}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: ${dep:libgobiarchdbg}
+Breaks: lib32go9 (<< 6.4.0-12),
+  libn32go9 (<< 6.4.0-12), 
+  libx32go9 (<< 6.4.0-12), 
+  lib64go9 (<< 6.4.0-12)
+Replaces: lib32go9 (<< 6.4.0-12),
+  libn32go9 (<< 6.4.0-12), 
+  libx32go9 (<< 6.4.0-12), 
+  lib64go9 (<< 6.4.0-12)
+Description: GNU Go compiler (multilib support)
+ This is the GNU Go compiler, which compiles Go on platforms supported
+ by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: gccgo-6-doc
+Architecture: all
+Section: doc
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Description: Documentation for the GNU Go compiler (gccgo)
+ Documentation for the GNU Go compiler in info format.
+
+Package: libgo9
+Section: libs
+Architecture: any
+Provides: libgo9-armel [armel], libgo9-armhf [armhf]
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Replaces: libgo3, libgo8
+Description: Runtime library for GNU Go applications
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: libgo9-dbg
+Section: debug
+Architecture: any
+Provides: libgo9-dbg-armel [armel], libgo9-dbg-armhf [armhf]
+Multi-Arch: same
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgo9 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Go applications (debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+
+Package: lib64go9
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib64go3, lib64go8
+Description: Runtime library for GNU Go applications (64bit)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: lib64go9-dbg
+Section: debug
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64go9 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Go applications (64bit debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+
+Package: lib32go9
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Replaces: lib32go3, lib32go8
+Description: Runtime library for GNU Go applications (32bit)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: lib32go9-dbg
+Section: debug
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32go9 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Go applications (32 bit debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+
+Package: libn32go9
+Section: libs
+Architecture: mips mipsel mips64 mips64el mipsr6 mipsr6el mips64r6 mips64r6el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libn32go3, libn32go8
+Description: Runtime library for GNU Go applications (n32)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: libn32go9-dbg
+Section: debug
+Architecture: mips mipsel mips64 mips64el mipsr6 mipsr6el mips64r6 mips64r6el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libn32go9 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Go applications (n32 debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+
+Package: libx32go9
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libx32go3, libx32go8
+Description: Runtime library for GNU Go applications (x32)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: libx32go9-dbg
+Section: debug
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32go9 (= ${gcc:Version}), ${misc:Depends}
+Description: Runtime library for GNU Go applications (x32 debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+
+Package: gcj-6
+Section: java
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (= ${gcc:Version}), ${dep:gcj}, ${dep:gcjcross}, ${dep:libcdev}, ${dep:ecj}, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Recommends: libecj-java-gcj
+Replaces: gcj-5-jdk (<< 5.2.1-19)
+Suggests: gcj-6-jdk
+Description: GCJ byte code and native compiler for Java(TM)
+ GCJ is a front end to the GCC compiler which can natively compile both
+ Java(tm) source and bytecode files. The compiler can also generate class
+ files.
+ .
+ Install the gcj-6-jdk package for a more complete SDK environment.
+
+Package: gcj-6-jdk
+Section: java
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${dep:gcj}, ${dep:libcdev}, gcj-6 (= ${gcj:Version}), gcj-6-jre (= ${gcj:Version}), libgcj17-dev (>= ${gcj:Version}), fastjar, libgcj-bc, java-common, libantlr-java, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Recommends: libecj-java-gcj
+Suggests: gcj-6-source (>= ${gcj:SoftVersion}), libgcj17-dbg (>= ${gcc:Version})
+Provides: java-compiler, java-sdk, java2-sdk, java5-sdk
+Conflicts: gcj-4.4, cpp-4.1 (<< 4.1.1), gcc-4.1 (<< 4.1.1)
+Replaces: libgcj11 (<< 4.5-20100101-1)
+Description: GCJ and Classpath development tools for Java(TM)
+ GCJ is a front end to the GCC compiler which can natively compile both
+ Java(tm) source and bytecode files. The compiler can also generate class
+ files. Other java development tools from classpath are included in this
+ package.
+ .
+ The package contains as well a collection of wrapper scripts and symlinks.
+ It is meant to provide a Java-SDK-like interface to the GCJ tool set.
+
+Package: gcj-6-jre-headless
+Priority: optional
+Section: java
+Architecture: any
+Depends: gcc-6-base (= ${gcc:Version}), gcj-6-jre-lib (>= ${gcj:SoftVersion}), libgcj17 (>= ${gcj:Version}), ${dep:prctl}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: fastjar, gcj-6-jdk (= ${gcj:Version}), libgcj17-awt (>= ${gcj:Version})
+Provides: java5-runtime-headless, java2-runtime-headless, java1-runtime-headless, java-runtime-headless
+Description: Java runtime environment using GIJ/Classpath (headless version)
+ GIJ is a Java bytecode interpreter, not limited to interpreting bytecode.
+ It includes a class loader which can dynamically load shared objects, so
+ it is possible to give it the name of a class which has been compiled and
+ put into a shared library on the class path.
+ .
+ The package contains as well a collection of wrapper scripts and symlinks.
+ It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set,
+ limited to the headless tools and libraries.
+
+Package: gcj-6-jre
+Section: java
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gcj-6-jre-headless (= ${gcj:Version}), libgcj17-awt (>= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+Provides: java5-runtime, java2-runtime, java1-runtime, java-runtime
+Description: Java runtime environment using GIJ/Classpath
+ GIJ is a Java bytecode interpreter, not limited to interpreting bytecode.
+ It includes a class loader which can dynamically load shared objects, so
+ it is possible to give it the name of a class which has been compiled and
+ put into a shared library on the class path.
+ .
+ The package contains as well a collection of wrapper scripts and symlinks.
+ It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set.
+
+Package: libgcj17
+Section: libs
+Architecture: any
+Priority: optional
+Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), libgcj-common (>= 1:4.1.1-21), ${shlibs:Depends}, ${misc:Depends}
+Recommends: gcj-6-jre-lib (>= ${gcj:SoftVersion})
+Suggests: libgcj17-dbg (>= ${gcc:Version}), libgcj17-awt (= ${gcj:Version})
+Description: Java runtime library for use with gcj
+ This is the runtime that goes along with the gcj front end to
+ gcc. libgcj includes parts of the Java Class Libraries, plus glue to
+ connect the libraries to the compiler and the underlying OS.
+ .
+ To show file names and line numbers in stack traces, the packages
+ libgcj17-dbg and binutils are required.
+
+Package: gcj-6-jre-lib
+Section: java
+Architecture: all
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), libgcj17 (>= ${gcj:SoftVersion}), ${misc:Depends}
+Description: Java runtime library for use with gcj (jar files)
+ This is the jar file that goes along with the gcj front end to gcc.
+
+Package: libgcj17-awt
+Section: libs
+Architecture: any
+Priority: optional
+Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), libgcj17 (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+Suggests: ${pkg:gcjqt}
+Description: AWT peer runtime libraries for use with gcj
+ These are runtime libraries holding the AWT peer implementations
+ for libgcj (currently the GTK+ based peer library is required, the
+ QT bases library is not built).
+
+Package: libgcj17-dev
+Section: libdevel
+Architecture: any
+Multi-Arch: same
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgcj17-awt (= ${gcj:Version}), libgcj-bc, ${pkg:gcjgtk}, ${pkg:gcjqt}, zlib1g-dev, ${shlibs:Depends}, ${misc:Depends}
+Suggests: libgcj-doc
+Description: Java development headers for use with gcj
+ These are the development headers that go along with the gcj front end
+ to gcc. libgcj includes parts of the Java Class Libraries, plus glue
+ to connect the libraries to the compiler and the underlying OS.
+
+Package: libgcj17-dbg
+Section: debug
+Architecture: any
+Priority: optional
+Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+Depends: gcc-6-base (= ${gcc:Version}), libgcj17 (= ${gcj:Version}), ${misc:Depends}
+Recommends: binutils, libc6-dbg | libc-dbg
+Description: Debugging symbols for libraries provided in libgcj17-dev
+ The package provides debugging symbols for the libraries provided
+ in libgcj17-dev.
+ .
+ binutils is required to show file names and line numbers in stack traces.
+
+Package: gcj-6-source
+Section: java
+Architecture: all
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), gcj-6-jdk (>= ${gcj:SoftVersion}), ${misc:Depends}
+Description: GCJ java sources for use in IDEs like eclipse and netbeans
+ These are the java source files packaged as a zip file for use in development
+ environments like eclipse and netbeans.
+
+Package: libgcj-doc
+Section: doc
+Architecture: all
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), ${misc:Depends}
+Enhances: libgcj17-dev
+Provides: classpath-doc
+Description: libgcj API documentation and example programs
+ Autogenerated documentation describing the API of the libgcj library.
+ Sources and precompiled example programs from the Classpath library.
+
+Package: libstdc++-6-dev
+Architecture: any
+Multi-Arch: same
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgcc-6-dev (= ${gcc:Version}),
+ libstdc++6 (>= ${gcc:Version}), ${dep:libcdev}, ${misc:Depends}
+Conflicts: libg++27-dev, libg++272-dev (<< 2.7.2.8-1), libstdc++2.8-dev,
+ libg++2.8-dev, libstdc++2.9-dev, libstdc++2.9-glibc2.1-dev,
+ libstdc++2.10-dev (<< 1:2.95.3-2), libstdc++3.0-dev
+Suggests: libstdc++-6-doc
+Provides: libstdc++-dev
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libstdc++-6-pic
+Architecture: any
+Multi-Arch: same
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (shared library subset kit)
+ This is used to develop subsets of the libstdc++ shared libraries for
+ use on custom installation floppies and in embedded systems.
+ .
+ Unless you are making one of those, you will not need this package.
+
+Package: libstdc++6-6-dbg
+Architecture: any
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libstdc++6 (>= ${gcc:Version}),
+ libgcc1-dbg (>= ${libgcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Provides: libstdc++6-6-dbg-armel [armel], libstdc++6-6-dbg-armhf [armhf]
+Multi-Arch: same
+Recommends: libstdc++-6-dev (= ${gcc:Version})
+Conflicts: libstdc++5-dbg, libstdc++5-3.3-dbg, libstdc++6-dbg,
+ libstdc++6-4.0-dbg, libstdc++6-4.1-dbg, libstdc++6-4.2-dbg,
+ libstdc++6-4.3-dbg, libstdc++6-4.4-dbg, libstdc++6-4.5-dbg,
+ libstdc++6-4.6-dbg, libstdc++6-4.7-dbg, libstdc++6-4.8-dbg,
+ libstdc++6-4.9-dbg, libstdc++6-5-dbg
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: lib32stdc++-6-dev
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32gcc-6-dev (= ${gcc:Version}),
+ lib32stdc++6 (>= ${gcc:Version}), libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: lib32stdc++6-6-dbg
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32stdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), lib32gcc1-dbg (>= ${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+Conflicts: lib32stdc++6-dbg, lib32stdc++6-4.0-dbg,
+ lib32stdc++6-4.1-dbg, lib32stdc++6-4.2-dbg, lib32stdc++6-4.3-dbg,
+ lib32stdc++6-4.4-dbg, lib32stdc++6-4.5-dbg, lib32stdc++6-4.6-dbg,
+ lib32stdc++6-4.7-dbg, lib32stdc++6-4.8-dbg, lib32stdc++6-4.9-dbg,
+ lib32stdc++6-5-dbg
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: lib64stdc++-6-dev
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64gcc-6-dev (= ${gcc:Version}),
+ lib64stdc++6 (>= ${gcc:Version}), libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: lib64stdc++6-6-dbg
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64stdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), lib64gcc1-dbg (>= ${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+Conflicts: lib64stdc++6-dbg, lib64stdc++6-4.0-dbg,
+ lib64stdc++6-4.1-dbg, lib64stdc++6-4.2-dbg, lib64stdc++6-4.3-dbg,
+ lib64stdc++6-4.4-dbg, lib64stdc++6-4.5-dbg, lib64stdc++6-4.6-dbg,
+ lib64stdc++6-4.7-dbg, lib64stdc++6-4.8-dbg, lib64stdc++6-4.9-dbg,
+ lib64stdc++6-5-dbg
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: libn32stdc++-6-dev
+Architecture: mips mipsel mips64 mips64el mipsr6 mipsr6el mips64r6 mips64r6el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libn32gcc-6-dev (= ${gcc:Version}),
+ libn32stdc++6 (>= ${gcc:Version}), libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libn32stdc++6-6-dbg
+Architecture: mips mipsel mips64 mips64el mipsr6 mipsr6el mips64r6 mips64r6el
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libn32stdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), libn32gcc1-dbg (>= ${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libn32stdc++6-dbg, libn32stdc++6-4.0-dbg,
+ libn32stdc++6-4.1-dbg, libn32stdc++6-4.2-dbg, libn32stdc++6-4.3-dbg,
+ libn32stdc++6-4.4-dbg, libn32stdc++6-4.5-dbg, libn32stdc++6-4.6-dbg,
+ libn32stdc++6-4.7-dbg, libn32stdc++6-4.8-dbg, libn32stdc++6-4.9-dbg,
+ libn32stdc++6-5-dbg
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: libx32stdc++-6-dev
+Architecture: amd64 i386
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32gcc-6-dev (= ${gcc:Version}), libx32stdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libx32stdc++6-6-dbg
+Architecture: amd64 i386
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32stdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), libx32gcc1-dbg (>= ${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libx32stdc++6-dbg, libx32stdc++6-4.6-dbg,
+ libx32stdc++6-4.7-dbg, libx32stdc++6-4.8-dbg, libx32stdc++6-4.9-dbg,
+ libx32stdc++6-5-dbg
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: libhfstdc++-6-dev
+Architecture: armel
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libhfgcc-6-dev (= ${gcc:Version}),
+ libhfstdc++6 (>= ${gcc:Version}), libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libhfstdc++6-6-dbg
+Architecture: armel
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libhfstdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), libhfgcc1-dbg (>= ${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libhfstdc++6-dbg, libhfstdc++6-4.3-dbg, libhfstdc++6-4.4-dbg, libhfstdc++6-4.5-dbg, libhfstdc++6-4.6-dbg, libhfstdc++6-4.7-dbg, libhfstdc++6-4.8-dbg, libhfstdc++6-4.9-dbg, libhfstdc++6-5-dbg, libstdc++6-armhf [armel]
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: libsfstdc++-6-dev
+Architecture: armhf
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libsfgcc-6-dev (= ${gcc:Version}),
+ libsfstdc++6 (>= ${gcc:Version}), libstdc++-6-dev (= ${gcc:Version}), ${misc:Depends}
+Description: GNU Standard C++ Library v3 (development files)
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+
+Package: libsfstdc++6-6-dbg
+Architecture: armhf
+Section: debug
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libsfstdc++6 (>= ${gcc:Version}),
+ libstdc++-6-dev (= ${gcc:Version}), libsfgcc1-dbg (>= ${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+Conflicts: libsfstdc++6-dbg, libsfstdc++6-4.3-dbg, libsfstdc++6-4.4-dbg, libsfstdc++6-4.5-dbg, libsfstdc++6-4.6-dbg, libsfstdc++6-4.7-dbg, libsfstdc++6-4.8-dbg, libsfstdc++6-4.9-dbg, libsfstdc++6-5-dbg, libstdc++6-armel [armhf]
+Description: GNU Standard C++ Library v3 (debugging files)
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+
+Package: libstdc++-6-doc
+Architecture: all
+Section: doc
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), ${misc:Depends}
+Conflicts: libstdc++5-doc, libstdc++5-3.3-doc, libstdc++6-doc,
+ libstdc++6-4.0-doc, libstdc++6-4.1-doc, libstdc++6-4.2-doc, libstdc++6-4.3-doc,
+ libstdc++6-4.4-doc, libstdc++6-4.5-doc, libstdc++6-4.6-doc, libstdc++6-4.7-doc,
+ libstdc++-4.8-doc, libstdc++-4.9-doc, libstdc++-5-doc
+Description: GNU Standard C++ Library v3 (documentation files)
+ This package contains documentation files for the GNU stdc++ library.
+ .
+ One set is the distribution documentation, the other set is the
+ source documentation including a namespace list, class hierarchy,
+ alphabetical list, compound list, file list, namespace members,
+ compound members and file members.
+
+Package: gnat-6
+Architecture: any
+Priority: optional
+Pre-Depends: ${misc:Pre-Depends}
+Depends: gcc-6-base (= ${gcc:Version}), gcc-6 (>= ${gcc:SoftVersion}), ${dep:libgnat}, ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: gnat-6-doc, ada-reference-manual-2012, gnat-6-sjlj
+Breaks:   gnat (<< 4.6.1), dh-ada-library (<< 6.0), gnat-4.6-base (= 4.6.4-2),
+ gnat-4.9-base (= 4.9-20140330-1)
+Replaces: gnat (<< 4.6.1), dh-ada-library (<< 6.0), gnat-4.6-base (= 4.6.4-2),
+ gnat-4.9-base (= 4.9-20140330-1)
+# Takes over symlink from gnat (<< 4.6.1): /usr/bin/gnatgcc.
+# Takes over file from dh-ada-library (<< 6.0): debian_packaging.mk.
+# g-base 4.6.4-2, 4.9-20140330-1 contain debian_packaging.mk by mistake.
+# Newer versions of gnat and dh-ada-library will not provide these files.
+Conflicts: gnat (<< 4.1), gnat-3.1, gnat-3.2, gnat-3.3, gnat-3.4, gnat-3.5,
+ gnat-4.0, gnat-4.1, gnat-4.2, gnat-4.3, gnat-4.4, gnat-4.6, gnat-4.7, gnat-4.8,
+ gnat-4.9, gnat-5
+# These other packages will continue to provide /usr/bin/gnatmake and
+# other files.
+Description: GNU Ada compiler
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ This package provides the compiler, tools and runtime library that handles
+ exceptions using the default zero-cost mechanism.
+
+Package: gnat-6-sjlj
+Architecture: any
+Priority: optional
+Pre-Depends: ${misc:Pre-Depends}
+Depends: gcc-6-base (= ${gcc:Version}), gnat-6 (= ${gnat:Version}), ${misc:Depends}
+Description: GNU Ada compiler (setjump/longjump runtime library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ This package provides an alternative runtime library that handles
+ exceptions using the setjump/longjump mechanism (as a static library
+ only).  You can install it to supplement the normal compiler.
+
+Package: libgnat-6
+Section: libs
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: runtime for applications compiled with GNAT (shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the runtime shared library.
+
+Package: libgnat-6-dbg
+Section: debug
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgnat-6 (= ${gnat:Version}), ${misc:Depends}
+Description: runtime for applications compiled with GNAT (debugging symbols)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the debugging symbols.
+
+Package: libgnatvsn6-dev
+Section: libdevel
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gnat-6 (= ${gnat:Version}),
+ libgnatvsn6 (= ${gnat:Version}), ${misc:Depends}
+Conflicts: libgnatvsn-dev (<< 6),
+ libgnatvsn4.1-dev, libgnatvsn4.3-dev, libgnatvsn4.4-dev,
+ libgnatvsn4.5-dev, libgnatvsn4.6-dev, libgnatvsn4.9-dev,
+ libgnatvsn5-dev,
+Description: GNU Ada compiler selected components (development files)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnatvsn library exports selected GNAT components for use in other
+ packages, most notably ASIS tools. It is licensed under the GNAT-Modified
+ GPL, allowing to link proprietary programs with it.
+ .
+ This package contains the development files and static library.
+
+Package: libgnatvsn6
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Section: libs
+Depends: gcc-6-base (= ${gcc:Version}), libgnat-6 (= ${gnat:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Ada compiler selected components (shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnatvsn library exports selected GNAT components for use in other
+ packages, most notably ASIS tools. It is licensed under the GNAT-Modified
+ GPL, allowing to link proprietary programs with it.
+ .
+ This package contains the runtime shared library.
+
+Package: libgnatvsn6-dbg
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Section: debug
+Depends: gcc-6-base (= ${gcc:Version}), libgnatvsn6 (= ${gnat:Version}), ${misc:Depends}
+Suggests: gnat
+Description: GNU Ada compiler selected components (debugging symbols)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnatvsn library exports selected GNAT components for use in other
+ packages, most notably ASIS tools. It is licensed under the GNAT-Modified
+ GPL, allowing to link proprietary programs with it.
+ .
+ This package contains the debugging symbols.
+
+Package: libgnatprj6-dev
+Section: libdevel
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), gnat-6 (= ${gnat:Version}),
+ libgnatprj6 (= ${gnat:Version}),
+ libgnatvsn6-dev (= ${gnat:Version}), ${misc:Depends}
+Conflicts: libgnatprj-dev (<< 6),
+ libgnatprj4.1-dev, libgnatprj4.3-dev, libgnatprj4.4-dev,
+ libgnatprj4.5-dev, libgnatprj4.6-dev, libgnatprj4.9-dev,
+ libgnatprj5-dev,
+Description: GNU Ada compiler Project Manager (development files)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ GNAT uses project files to organise source and object files in large-scale
+ development efforts. The libgnatprj library exports GNAT project files
+ management for use in other packages, most notably ASIS tools (package
+ asis-programs) and GNAT Programming Studio (package gnat-gps). It is
+ licensed under the pure GPL; all programs that use it must also be
+ distributed under the GPL, or not distributed at all.
+ .
+ This package contains the development files and static library.
+
+Package: libgnatprj6
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Section: libs
+Depends: gcc-6-base (= ${gcc:Version}), libgnat-6 (= ${gnat:Version}),
+ libgnatvsn6 (= ${gnat:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+Description: GNU Ada compiler Project Manager (shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ GNAT uses project files to organise source and object files in large-scale
+ development efforts. The libgnatprj library exports GNAT project files
+ management for use in other packages, most notably ASIS tools (package
+ asis-programs) and GNAT Programming Studio (package gnat-gps). It is
+ licensed under the pure GPL; all programs that use it must also be
+ distributed under the GPL, or not distributed at all.
+ .
+ This package contains the runtime shared library.
+
+Package: libgnatprj6-dbg
+Architecture: any
+Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Priority: optional
+Section: debug
+Depends: gcc-6-base (= ${gcc:Version}), libgnatprj6 (= ${gnat:Version}), ${misc:Depends}
+Suggests: gnat
+Description: GNU Ada compiler Project Manager (debugging symbols)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ GNAT uses project files to organise source and object files in large-scale
+ development efforts. The libgnatprj library exports GNAT project files
+ management for use in other packages, most notably ASIS tools (package
+ asis-programs) and GNAT Programming Studio (package gnat-gps). It is
+ licensed under the pure GPL; all programs that use it must also be
+ distributed under the GPL, or not distributed at all.
+ .
+ This package contains the debugging symbols.
+
+Package: gnat-6-doc
+Architecture: all
+Section: doc
+Priority: optional
+Depends: dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Suggests: gnat-6
+Conflicts: gnat-4.1-doc, gnat-4.2-doc,
+  gnat-4.3-doc, gnat-4.4-doc, 
+  gnat-4.6-doc, gnat-4.9-doc, 
+  gnat-5-doc, 
+Description: GNU Ada compiler (documentation)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the documentation in info format.
+
+Package: gdc-6
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), g++-6 (>= ${gcc:SoftVersion}), ${dep:gdccross}, ${dep:phobosdev}, ${shlibs:Depends}, ${misc:Depends}
+Provides: gdc, d-compiler, d-v2-compiler
+Replaces: gdc (<< 4.4.6-5)
+Description: GNU D compiler (version 2)
+ This is the GNU D compiler, which compiles D on platforms supported by gcc.
+ It uses the gcc backend to generate optimised code.
+ .
+ This compiler supports D language version 2.
+
+Package: gdc-6-multilib
+Architecture: any
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), gdc-6 (= ${gcc:Version}), gcc-6-multilib (= ${gcc:Version}), ${dep:libphobosbiarchdev}${shlibs:Depends}, ${misc:Depends}
+Description: GNU D compiler (version 2, multilib support)
+ This is the GNU D compiler, which compiles D on platforms supported by gcc.
+ It uses the gcc backend to generate optimised code.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+
+Package: libgphobos-6-dev
+Architecture: amd64 armel armhf i386 x32 kfreebsd-amd64 kfreebsd-i386
+Multi-Arch: same
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgphobos68 (>= ${gdc:Version}),
+  zlib1g-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libphobos-6-dev
+Description: Phobos D standard library
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libgphobos68
+Section: libs
+Architecture: amd64 armel armhf i386 x32 kfreebsd-amd64 kfreebsd-i386
+Multi-Arch: same
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libgphobos68-dbg
+Section: debug
+Architecture: amd64 armel armhf i386 x32 kfreebsd-amd64 kfreebsd-i386
+Multi-Arch: same
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libgphobos68 (= ${gdc:Version}), ${misc:Depends}
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib64gphobos-6-dev
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64gphobos68 (>= ${gdc:Version}),
+  lib64gcc-6-dev (= ${gcc:Version}), lib64z1-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib64phobos-6-dev
+Description: Phobos D standard library (64bit development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib64gphobos68
+Section: libs
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib64gphobos68-dbg
+Section: debug
+Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el x32
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib64gphobos68 (= ${gdc:Version}), ${misc:Depends}
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib32gphobos-6-dev
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32gphobos68 (>= ${gdc:Version}),
+  lib32gcc-6-dev (= ${gcc:Version}), lib32z1-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib32phobos-6-dev
+Description: Phobos D standard library (32bit development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib32gphobos68
+Section: libs
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib32gphobos68-dbg
+Section: debug
+Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), lib32gphobos68 (= ${gdc:Version}), ${misc:Depends}
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libx32gphobos-6-dev
+Architecture: amd64 i386
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32gphobos68 (>= ${gdc:Version}),
+  libx32gcc-6-dev (= ${gcc:Version}), ${dep:libx32z}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libx32gphobos-6-dev
+Description: Phobos D standard library (x32 development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libx32gphobos68
+Section: libs
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libx32gphobos68-dbg
+Section: debug
+Architecture: amd64 i386
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libx32gphobos68 (= ${gdc:Version}), ${misc:Depends}
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libhfgphobos-6-dev
+Architecture: armel
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libhfgphobos68 (>= ${gdc:Version}),
+  libhfgcc-6-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Replaces: libhfphobos-6-dev
+Description: Phobos D standard library (hard float ABI development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libhfgphobos68
+Section: libs
+Architecture: armel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libhfgphobos68-dbg
+Section: debug
+Architecture: armel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libhfgphobos68 (= ${gdc:Version}), ${misc:Depends}
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libsfgphobos-6-dev
+Architecture: armhf
+Section: libdevel
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libsfgphobos68 (>= ${gdc:Version}),
+  libsfgcc-6-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Replaces: libsfphobos-6-dev
+Description: Phobos D standard library (soft float ABI development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libsfgphobos68
+Section: libs
+Architecture: armhf
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libsfgphobos68-dbg
+Section: debug
+Architecture: armhf
+Priority: optional
+Depends: gcc-6-base (= ${gcc:Version}), libsfgphobos68 (= ${gdc:Version}), ${misc:Depends}
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+#Package: gcc`'PV-soft-float
+#Architecture: arm armel armhf
+#Priority: PRI(optional)
+#Depends: BASEDEP, depifenabled(`cdev',`gcc`'PV (= ${gcc:Version}),') ${shlibs:Depends}, ${misc:Depends}
+#Conflicts: gcc-4.4-soft-float, gcc-4.5-soft-float, gcc-4.6-soft-float
+#BUILT_USING`'dnl
+#Description: GCC soft-floating-point gcc libraries (ARM)
+# These are versions of basic static libraries such as libgcc.a compiled
+# with the -msoft-float option, for CPUs without a floating-point unit.
+
+Package: gcc-6-doc
+Architecture: all
+Section: doc
+Priority: optional
+Depends: gcc-6-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Conflicts: gcc-docs (<< 2.95.2)
+Replaces: gcc (<=2.7.2.3-4.3), gcc-docs (<< 2.95.2)
+Description: Documentation for the GNU compilers (gcc, gobjc, g++)
+ Documentation for the GNU compilers in info format.
+
+Package: gcc-6-source
+Architecture: all
+Priority: optional
+Depends: make, autoconf2.64, quilt, patchutils, sharutils, gawk, ${misc:Depends}
+Description: Source of the GNU Compiler Collection
+ This package contains the sources and patches which are needed to
+ build the GNU Compiler Collection (GCC).
--- gcc-6-6.4.0.orig/debian/control.m4
+++ gcc-6-6.4.0/debian/control.m4
@@ -0,0 +1,5488 @@
+divert(-1)
+
+define(`checkdef',`ifdef($1, , `errprint(`error: undefined macro $1
+')m4exit(1)')')
+define(`errexit',`errprint(`error: undefined macro `$1'
+')m4exit(1)')
+
+dnl The following macros must be defined, when called:
+dnl ifdef(`SRCNAME',	, errexit(`SRCNAME'))
+dnl ifdef(`PV',		, errexit(`PV'))
+dnl ifdef(`ARCH',		, errexit(`ARCH'))
+
+dnl The architecture will also be defined (-D__i386__, -D__powerpc__, etc.)
+
+define(`PN', `$1')
+ifdef(`PRI', `', `
+    define(`PRI', `$1')
+')
+define(`MAINTAINER', `Debian GCC Maintainers <debian-gcc@lists.debian.org>')
+
+define(`depifenabled', `ifelse(index(enabled_languages, `$1'), -1, `', `$2')')
+define(`ifenabled', `ifelse(index(enabled_languages, `$1'), -1, `dnl', `$2')')
+
+ifdef(`TARGET',`ifdef(`CROSS_ARCH',`',`undefine(`MULTIARCH')')')
+define(`CROSS_ARCH', ifdef(`CROSS_ARCH', CROSS_ARCH, `all'))
+define(`libdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`>=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))')
+define(`libdevdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))')
+define(`libidevdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))')
+ifdef(`TARGET',`ifelse(CROSS_ARCH,`all',`
+define(`libidevdep', `lib$2$1`'LS`'AQ (>= ifelse(`$4',`',`${gcc:SoftVersion}',`$4'))')
+')')
+define(`libdbgdep', `lib$2$1`'LS`'AQ (ifelse(`$3',`',`>=',`$3') ifelse(`$4',`',`${gcc:Version}',`$4'))')
+
+define(`BUILT_USING', ifelse(add_built_using,yes,`Built-Using: ${Built-Using}
+'))
+
+divert`'dnl
+dnl --------------------------------------------------------------------------
+Source: SRCNAME
+Section: devel
+Priority: PRI(optional)
+ifelse(DIST,`Ubuntu',`dnl
+ifelse(regexp(SRCNAME, `gnat\|gdc-'),0,`dnl
+Maintainer: Ubuntu MOTU Developers <ubuntu-motu@lists.ubuntu.com>
+', `dnl
+Maintainer: Ubuntu Core developers <ubuntu-devel-discuss@lists.ubuntu.com>
+')dnl SRCNAME
+XSBC-Original-Maintainer: MAINTAINER
+', `dnl
+Maintainer: MAINTAINER
+')dnl DIST
+ifelse(regexp(SRCNAME, `gnat'),0,`dnl
+Uploaders: Ludovic Brenta <lbrenta@debian.org>
+', regexp(SRCNAME, `gdc'),0,`dnl
+Uploaders: Iain Buclaw <ibuclaw@ubuntu.com>, Matthias Klose <doko@debian.org>
+', `dnl
+Uploaders: Matthias Klose <doko@debian.org>
+')dnl SRCNAME
+Standards-Version: 4.1.3
+ifdef(`TARGET',`dnl cross
+Build-Depends: DEBHELPER_BUILD_DEP DPKG_BUILD_DEP
+  LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP
+  kfreebsd-kernel-headers (>= 0.84) [kfreebsd-any], linux-libc-dev [m68k],
+  LIBUNWIND_BUILD_DEP LIBATOMIC_OPS_BUILD_DEP AUTO_BUILD_DEP
+  SOURCE_BUILD_DEP CROSS_BUILD_DEP
+  ISL_BUILD_DEP MPC_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP
+  autogen, zlib1g-dev, gawk, lzma, xz-utils, patchutils,
+  pkg-config, libgc-dev,
+  zlib1g-dev, SDT_BUILD_DEP
+  bison (>= 1:2.3), flex, coreutils (>= 2.26) | realpath (>= 1.9.12), lsb-release, quilt
+',`dnl native
+Build-Depends: DEBHELPER_BUILD_DEP DPKG_BUILD_DEP
+  GCC_MULTILIB_BUILD_DEP
+  LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP LIBC_DBG_DEP
+  kfreebsd-kernel-headers (>= 0.84) [kfreebsd-any], linux-libc-dev [m68k],
+  AUTO_BUILD_DEP BASE_BUILD_DEP
+  libunwind8-dev [ia64], libatomic-ops-dev [ia64],
+  autogen, gawk, lzma, xz-utils, patchutils,
+  zlib1g-dev, SDT_BUILD_DEP
+  BINUTILS_BUILD_DEP,
+  gperf (>= 3.0.1), bison (>= 1:2.3), flex, gettext,
+  gdb`'NT,
+  texinfo (>= 4.3), locales, sharutils,
+  procps, FORTRAN_BUILD_DEP JAVA_BUILD_DEP GNAT_BUILD_DEP GO_BUILD_DEP GDC_BUILD_DEP
+  ISL_BUILD_DEP MPC_BUILD_DEP MPFR_BUILD_DEP GMP_BUILD_DEP PHOBOS_BUILD_DEP
+  CHECK_BUILD_DEP coreutils (>= 2.26) | realpath (>= 1.9.12), chrpath, lsb-release, quilt,
+  pkg-config, libgc-dev,
+  TARGET_TOOL_BUILD_DEP
+Build-Depends-Indep: LIBSTDCXX_BUILD_INDEP JAVA_BUILD_INDEP
+')dnl
+ifelse(regexp(SRCNAME, `gnat'),0,`dnl
+Homepage: http://gcc.gnu.org/
+', regexp(SRCNAME, `gdc'),0,`dnl
+Homepage: http://gdcproject.org/
+', `dnl
+Homepage: http://gcc.gnu.org/
+')dnl SRCNAME
+Vcs-Browser: http://svn.debian.org/viewsvn/gcccvs/branches/sid/gcc`'PV/
+Vcs-Svn: svn://anonscm.debian.org/gcccvs/branches/sid/gcc`'PV
+
+ifelse(regexp(SRCNAME, `gcc-snapshot'),0,`dnl
+Package: gcc-snapshot`'TS
+Architecture: any
+Section: devel
+Priority: optional
+Depends: binutils`'TS (>= ${binutils:Version}), ${dep:libcbiarchdev}, ${dep:libcdev}, ${dep:libunwinddev}, ${snap:depends}, ${shlibs:Depends}, ${dep:ecj}, python, ${misc:Depends}
+Recommends: ${snap:recommends}
+Suggests: ${dep:gold}
+Provides: c++-compiler`'TS`'ifdef(`TARGET',`',`, c++abi2-dev')
+BUILT_USING`'dnl
+Description: SNAPSHOT of the GNU Compiler Collection
+ This package contains a recent development SNAPSHOT of all files
+ contained in the GNU Compiler Collection (GCC).
+ .
+ The source code for this package has been exported from SVN trunk.
+ .
+ DO NOT USE THIS SNAPSHOT FOR BUILDING DEBIAN PACKAGES!
+ .
+ This package will NEVER hit the testing distribution. It is used for
+ tracking gcc bugs submitted to the Debian BTS in recent development
+ versions of gcc.
+',`dnl gcc-X.Y
+
+dnl default base package dependencies
+define(`BASEDEP', `gcc`'PV`'TS-base (= ${gcc:Version})')
+define(`SOFTBASEDEP', `gcc`'PV`'TS-base (>= ${gcc:SoftVersion})')
+
+ifdef(`TARGET',`
+define(`BASELDEP', `gcc`'PV`'ifelse(CROSS_ARCH,`all',`-cross')-base`'GCC_PORTS_BUILD (= ${gcc:Version})')
+define(`SOFTBASELDEP', `gcc`'PV`'ifelse(CROSS_ARCH, `all',`-cross')-base`'GCC_PORTS_BUILD (>= ${gcc:SoftVersion})')
+',`dnl
+define(`BASELDEP', `BASEDEP')
+define(`SOFTBASELDEP', `SOFTBASEDEP')
+')
+
+dnl base, when building libgcc out of the gcj source; needed if new symbols
+dnl in libgcc are used in libgcj.
+ifelse(index(SRCNAME, `gcj'), 0, `
+define(`BASEDEP', `gcj`'PV-base (= ${gcj:Version})')
+define(`SOFTBASEDEP', `gcj`'PV-base (>= ${gcj:SoftVersion})')
+')
+
+ifelse(index(SRCNAME, `gnat'), 0, `
+define(`BASEDEP', `gnat`'PV-base (= ${gnat:Version})')
+define(`SOFTBASEDEP', `gnat`'PV-base (>= ${gnat:SoftVersion})')
+')
+
+ifenabled(`gccbase',`
+Package: gcc`'PV`'TS-base
+Architecture: any
+Multi-Arch: same
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`optional',`PRI(required)')
+Depends: ${misc:Depends}
+Replaces: ${base:Replaces}
+Breaks: ${base:Breaks}
+BUILT_USING`'dnl
+Description: GCC, the GNU Compiler Collection (base package)
+ This package contains files common to all languages and libraries
+ contained in the GNU Compiler Collection (GCC).
+ifdef(`BASE_ONLY', `dnl
+ .
+ This version of GCC is not yet available for this architecture.
+ Please use the compilers from the gcc-snapshot package for testing.
+')`'dnl
+')`'dnl gccbase
+
+ifenabled(`gcclbase',`
+Package: gcc`'PV-cross-base`'GCC_PORTS_BUILD
+Architecture: all
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`optional',`PRI(required)')
+Depends: ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC, the GNU Compiler Collection (library base package)
+ This empty package contains changelog and copyright files common to
+ all libraries contained in the GNU Compiler Collection (GCC).
+ifdef(`BASE_ONLY', `dnl
+ .
+ This version of GCC is not yet available for this architecture.
+ Please use the compilers from the gcc-snapshot package for testing.
+')`'dnl
+')`'dnl gcclbase
+
+ifenabled(`java',`
+ifdef(`TARGET', `', `
+ifenabled(`gcjbase',`
+Package: gcj`'PV-base
+Architecture: any
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Section: libs
+Priority: PRI(optional)
+Depends: ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC, the GNU Compiler Collection (gcj base package)
+ This package contains files common to all java related packages
+ built from the GNU Compiler Collection (GCC).
+')`'dnl gccbase
+')`'dnl native
+
+ifenabled(`gcjxbase',`
+dnl override default base package dependencies to cross version
+dnl This creates a toolchain that doesnt depend on the system -base packages
+define(`BASEDEP', `gcj`'`PV`'TS'-base (= ${gcc:Version})')
+define(`SOFTBASEDEP', `gcj`'`PV`'TS'-base (>= ${gcc:SoftVersion})')
+
+Package: gcj`'`PV`'TS'-base
+Architecture: any
+Section: devel
+Priority: PRI(optional)
+Depends: ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC, the GNU Compiler Collection (gcj base package)
+ This package contains files common to all java related packages
+ built from the GNU Compiler Collection (GCC).
+')`'dnl
+')`'dnl java
+
+ifenabled(`gnatbase',`
+Package: gnat`'PV-base`'TS
+Architecture: any
+# "all" causes build instabilities for "any" dependencies (see #748388).
+Section: libs
+Priority: PRI(optional)
+Depends: ${misc:Depends}
+Breaks: gcc-4.6 (<< 4.6.1-8~)
+BUILT_USING`'dnl
+Description: GNU Ada compiler (common files)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ This package contains files common to all GNAT related packages.
+')`'dnl gnatbase
+
+ifenabled(`libgcc',`
+Package: libgcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`optional',required)
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+Provides: ifdef(`TARGET',`libgcc1-TARGET-dcv1',`libgcc1-armel [armel], libgcc1-armhf [armhf]')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `')
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libgcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gcc1,,=,${gcc:EpochVersion}), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libgcc1-dbg-armel [armel], libgcc1-dbg-armhf [armhf]
+')dnl
+ifdef(`MULTIARCH',`Multi-Arch: same
+')dnl
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libgcc2`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`m68k')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`optional',required)
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libgcc2-TARGET-dcv1
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `')
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libgcc2-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`m68k')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gcc2,,=,${gcc:EpochVersion}), ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libgcc
+
+ifenabled(`cdev',`
+Package: libgcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgcc}, ${dep:libssp}, ${dep:libgomp}, ${dep:libitm},
+ ${dep:libatomic}, ${dep:libbtrace}, ${dep:libasan}, ${dep:liblsan},
+ ${dep:libtsan}, ${dep:libubsan}, ${dep:libcilkrts}, ${dep:libvtv},
+ ${dep:libmpx},
+ ${dep:libqmath}, ${dep:libunwinddev}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Replaces: gccgo-6 (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl libgcc
+
+Package: libgcc4`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`hppa')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+')`'dnl
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`optional',required)
+Depends: ifdef(`STANDALONEJAVA',`gcj`'PV-base (>= ${gcj:Version})',`BASELDEP'), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `')
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libgcc4-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`hppa')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gcc4,,=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+ifenabled(`lib64gcc',`
+Package: lib64gcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${misc:Depends}
+ifdef(`TARGET',`Provides: lib64gcc1-TARGET-dcv1
+',`')`'dnl
+Conflicts: libdep(gcc`'GCC_SO,,<=,1:3.3-0pre9)
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (64bit)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: lib64gcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gcc1,64,=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl lib64gcc
+
+ifenabled(`cdev',`
+Package: lib64gcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (64bit development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl cdev
+
+ifenabled(`lib32gcc',`
+Package: lib32gcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+ifdef(`TARGET',`Provides: lib32gcc1-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library (32 bit Version)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: lib32gcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gcc1,32,=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl lib32gcc1
+
+ifenabled(`cdev',`
+Package: lib32gcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (32 bit development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl cdev
+
+ifenabled(`libneongcc',`
+Package: libgcc1-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: optional
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library [neon optimized]
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneongcc1
+
+ifenabled(`libhfgcc',`
+Package: libhfgcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libhfgcc1-TARGET-dcv1
+',`Conflicts: libgcc1-armhf [biarchhf_archs]
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (hard float ABI)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libhfgcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gcc1,hf,=,${gcc:EpochVersion}), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgcc1-dbg-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libhfgcc
+
+ifenabled(`cdev',`
+ifenabled(`armml',`
+Package: libhfgcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (hard float ABI development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl armml
+')`'dnl cdev
+
+ifenabled(`libsfgcc',`
+Package: libsfgcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libsfgcc1-TARGET-dcv1
+',`Conflicts: libgcc1-armel [biarchsf_archs]
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (soft float ABI)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libsfgcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gcc1,sf,=,${gcc:EpochVersion}), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgcc1-dbg-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libsfgcc
+
+ifenabled(`cdev',`
+ifenabled(`armml',`
+Package: libsfgcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (soft float ABI development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl armml
+')`'dnl cdev
+
+ifenabled(`libn32gcc',`
+Package: libn32gcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${misc:Depends}
+Conflicts: libdep(gcc`'GCC_SO,,<=,1:3.3-0pre9)
+ifdef(`TARGET',`Provides: libn32gcc1-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (n32)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libn32gcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gcc1,n32,=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libn32gcc
+
+ifenabled(`cdev',`
+Package: libn32gcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (n32 development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl cdev
+
+ifenabled(`libx32gcc',`
+Package: libx32gcc1`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libx32gcc1-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GCC support library`'ifdef(`TARGET)',` (TARGET)', `') (x32)
+ Shared version of the support library, a library of internal subroutines
+ that GCC uses to overcome shortcomings of particular machines, or
+ special needs for some languages.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libx32gcc1-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gcc1,x32,=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC support library (debug symbols)`'ifdef(`TARGET)',` (TARGET)', `')
+ Debug symbols for the GCC support library.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libx32gcc
+
+ifenabled(`cdev',`
+ifenabled(`x32dev',`
+Package: libx32gcc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: libdevel
+Priority: optional
+Recommends: ${dep:libcdev}
+Depends: BASELDEP, ${dep:libgccbiarch}, ${dep:libsspbiarch},
+ ${dep:libgompbiarch}, ${dep:libitmbiarch}, ${dep:libatomicbiarch},
+ ${dep:libbtracebiarch}, ${dep:libasanbiarch}, ${dep:liblsanbiarch},
+ ${dep:libtsanbiarch}, ${dep:libubsanbiarch},
+ ${dep:libvtvbiarch}, ${dep:libcilkrtsbiarch}, ${dep:libmpxbiarch},
+ ${dep:libqmathbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: gccgo-6-multilib (<< ${gcc:Version})
+BUILT_USING`'dnl
+Description: GCC support library (x32 development files)
+ This package contains the headers and static library files necessary for
+ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm.
+')`'dnl x32dev
+')`'dnl cdev
+
+ifenabled(`cdev',`
+Package: gcc`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: optional
+Depends: cpp`'PV`'TS (= ${gcc:Version}),ifenabled(`gccbase',` BASEDEP,')
+  ifenabled(`gccxbase',` BASEDEP,')
+  ${dep:libcc1},
+  binutils`'TS (>= ${binutils:Version}),
+  ${dep:libgccdev}, ${shlibs:Depends}, ${misc:Depends}
+Recommends: ${dep:libcdev}
+Replaces: gccgo-6 (<< ${gcc:Version}), cpp`'PV`'TS (<< 6.3.0-21)
+Suggests: ${gcc:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}),
+ gcc`'PV-locales (>= ${gcc:SoftVersion}),
+ libdbgdep(gcc`'GCC_SO-dbg,,>=,${libgcc:Version}),
+ libdbgdep(gomp`'GOMP_SO-dbg,),
+ libdbgdep(itm`'ITM_SO-dbg,),
+ libdbgdep(atomic`'ATOMIC_SO-dbg,),
+ libdbgdep(asan`'ASAN_SO-dbg,),
+ libdbgdep(lsan`'LSAN_SO-dbg,),
+ libdbgdep(tsan`'TSAN_SO-dbg,),
+ libdbgdep(ubsan`'UBSAN_SO-dbg,),
+ifenabled(`libvtv',`',`
+ libdbgdep(vtv`'VTV_SO-dbg,),
+')`'dnl
+ libdbgdep(cilkrts`'CILKRTS_SO-dbg,),
+ libdbgdep(mpx`'MPX_SO-dbg,),
+ libdbgdep(quadmath`'QMATH_SO-dbg,)
+Provides: c-compiler`'TS
+ifdef(`TARGET',`Conflicts: gcc-multilib
+')`'dnl
+BUILT_USING`'dnl
+Description: GNU C compiler`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU C compiler, a fairly portable optimizing compiler for C.
+ifdef(`TARGET', `dnl
+ .
+ This package contains C cross-compiler for TARGET architecture.
+')`'dnl
+
+ifenabled(`multilib',`
+Package: gcc`'PV-multilib`'TS
+Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: optional
+Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU C compiler (multilib support)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU C compiler, a fairly portable optimizing compiler for C.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+
+ifenabled(`testresults',`
+Package: gcc`'PV-test-results
+Architecture: any
+Section: devel
+Priority: optional
+Depends: BASEDEP, ${misc:Depends}
+Replaces: g++-5 (<< 5.2.1-28)
+BUILT_USING`'dnl
+Description: Test results for the GCC test suite
+ This package contains the test results for running the GCC test suite
+ for a post build analysis.
+')`'dnl testresults
+
+ifenabled(`plugindev',`
+Package: gcc`'PV-plugin-dev`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: optional
+Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), GMP_BUILD_DEP MPC_BUILD_DEP ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Files for GNU GCC plugin development.
+ This package contains (header) files for GNU GCC plugin development. It
+ is only used for the development of GCC plugins, but not needed to run
+ plugins.
+')`'dnl plugindev
+')`'dnl cdev
+
+ifenabled(`cdev',`
+Package: gcc`'PV-hppa64-linux-gnu
+Architecture: ifdef(`TARGET',`any',hppa amd64 i386 x32)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: PRI(optional)
+Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}),
+  binutils-hppa64-linux-gnu | binutils-hppa64,
+  ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU C compiler (cross compiler for hppa64)
+ This is the GNU C compiler, a fairly portable optimizing compiler for C.
+')`'dnl cdev
+
+ifenabled(`cdev',`
+Package: cpp`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: ifdef(`TARGET',`devel',`interpreters')
+Priority: optional
+Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends}
+Suggests: gcc`'PV-locales (>= ${gcc:SoftVersion})
+Replaces: gccgo-6 (<< ${gcc:Version})
+Breaks: libmagics++-dev (<< 2.28.0-4)ifdef(`TARGET',`',`, hardening-wrapper (<< 2.8+nmu3)')
+BUILT_USING`'dnl
+Description: GNU C preprocessor
+ A macro processor that is used automatically by the GNU C compiler
+ to transform programs before actual compilation.
+ .
+ This package has been separated from gcc for the benefit of those who
+ require the preprocessor but not the compiler.
+ifdef(`TARGET', `dnl
+ .
+ This package contains preprocessor configured for TARGET architecture.
+')`'dnl
+
+ifdef(`TARGET', `', `
+ifenabled(`gfdldoc',`
+Package: cpp`'PV-doc
+Architecture: all
+Section: doc
+Priority: PRI(optional)
+Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Description: Documentation for the GNU C preprocessor (cpp)
+ Documentation for the GNU C preprocessor in info `format'.
+')`'dnl gfdldoc
+')`'dnl native
+
+ifdef(`TARGET', `', `
+Package: gcc`'PV-locales
+Architecture: all
+Section: devel
+Priority: PRI(optional)
+Depends: SOFTBASEDEP, cpp`'PV (>= ${gcc:SoftVersion}), ${misc:Depends}
+Recommends: gcc`'PV (>= ${gcc:SoftVersion})
+Description: GCC, the GNU compiler collection (native language support files)
+ Native language support for GCC. Lets GCC speak your language,
+ if translations are available.
+ .
+ Please do NOT submit bug reports in other languages than "C".
+ Always reset your language settings to use the "C" locales.
+')`'dnl native
+')`'dnl cdev
+
+ifenabled(`c++',`
+ifenabled(`c++dev',`
+Package: g++`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: optional
+Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libidevdep(stdc++`'PV-dev,,=), ${shlibs:Depends}, ${misc:Depends}
+Provides: c++-compiler`'TS`'ifdef(`TARGET)',`',`, c++abi2-dev')
+Suggests: ${gxx:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libdbgdep(stdc++CXX_SO`'PV-dbg,)
+BUILT_USING`'dnl
+Description: GNU C++ compiler`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU C++ compiler, a fairly portable optimizing compiler for C++.
+ifdef(`TARGET', `dnl
+ .
+ This package contains C++ cross-compiler for TARGET architecture.
+')`'dnl
+
+ifenabled(`multilib',`
+Package: g++`'PV-multilib`'TS
+Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: optional
+Depends: BASEDEP, g++`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libcxxbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: ${dep:libcxxbiarchdbg}
+BUILT_USING`'dnl
+Description: GNU C++ compiler (multilib support)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU C++ compiler, a fairly portable optimizing compiler for C++.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+')`'dnl c++dev
+')`'dnl c++
+
+ifdef(`TARGET', `', `
+ifenabled(`ssp',`
+Package: libssp`'SSP_SO`'LS
+Architecture: any
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+
+Package: lib32ssp`'SSP_SO`'LS
+Architecture: biarch32_archs
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libssp0 (<< 4.1)
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library (32bit)
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+
+Package: lib64ssp`'SSP_SO`'LS
+Architecture: biarch64_archs
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libssp0 (<< 4.1)
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library (64bit)
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+
+Package: libn32ssp`'SSP_SO`'LS
+Architecture: biarchn32_archs
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libssp0 (<< 4.1)
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library (n32)
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+
+Package: libx32ssp`'SSP_SO`'LS
+Architecture: biarchx32_archs
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libssp0 (<< 4.1)
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library (x32)
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+
+Package: libhfssp`'SSP_SO`'LS
+Architecture: biarchhf_archs
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library (hard float ABI)
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+
+Package: libsfssp`'SSP_SO`'LS
+Architecture: biarchsf_archs
+Section: libs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC stack smashing protection library (soft float ABI)
+ GCC can now emit code for protecting applications from stack-smashing attacks.
+ The protection is realized by buffer overflow detection and reordering of
+ stack variables to avoid pointer corruption.
+')`'dnl
+')`'dnl native
+
+ifenabled(`libgomp',`
+Package: libgomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libgomp'GOMP_SO`-armel [armel], libgomp'GOMP_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libgomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libgomp'GOMP_SO`-dbg-armel [armel], libgomp'GOMP_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: lib32gomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (32bit)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: lib32gomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (32 bit debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: lib64gomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (64bit)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: lib64gomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (64bit debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libn32gomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (n32)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libn32gomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (n32 debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+
+ifenabled(`libx32gomp',`
+Package: libx32gomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (x32)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libx32gomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (x32 debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+')`'dnl libx32gomp
+
+ifenabled(`libhfgomp',`
+Package: libhfgomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (hard float ABI)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libhfgomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-dbg-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (hard float ABI debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+')`'dnl libhfgomp
+
+ifenabled(`libsfgomp',`
+Package: libsfgomp`'GOMP_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (soft float ABI)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+
+Package: libsfgomp`'GOMP_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(gomp`'GOMP_SO,sf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgomp'GOMP_SO`-dbg-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library (soft float ABI debug symbols)
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+')`'dnl libsfgomp
+
+ifenabled(`libneongomp',`
+Package: libgomp`'GOMP_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: optional
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC OpenMP (GOMP) support library [neon optimized]
+ GOMP is an implementation of OpenMP for the C, C++, and Fortran compilers
+ in the GNU Compiler Collection.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneongomp
+')`'dnl libgomp
+
+ifenabled(`libitm',`
+Package: libitm`'ITM_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libitm'ITM_SO`-armel [armel], libitm'ITM_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: libitm`'ITM_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(itm`'ITM_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libitm'ITM_SO`-dbg-armel [armel], libitm'ITM_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: lib32itm`'ITM_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (32bit)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: lib32itm`'ITM_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(itm`'ITM_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (32 bit debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: lib64itm`'ITM_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (64bit)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: lib64itm`'ITM_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(itm`'ITM_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (64bit debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+#Package: libn32itm`'ITM_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: optional
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: GNU Transactional Memory Library (n32)
+# GNU Transactional Memory Library (libitm) provides transaction support for
+# accesses to the memory of a process, enabling easy-to-use synchronization of
+# accesses to shared memory by several threads.
+
+#Package: libn32itm`'ITM_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: optional
+#Depends: BASELDEP, libdep(itm`'ITM_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: GNU Transactional Memory Library (n32 debug symbols)
+# GNU Transactional Memory Library (libitm) provides transaction support for
+# accesses to the memory of a process, enabling easy-to-use synchronization of
+# accesses to shared memory by several threads.
+
+ifenabled(`libx32itm',`
+Package: libx32itm`'ITM_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (x32)
+ This manual documents the usage and internals of libitm. It provides
+ transaction support for accesses to the memory of a process, enabling
+ easy-to-use synchronization of accesses to shared memory by several threads.
+
+Package: libx32itm`'ITM_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(itm`'ITM_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (x32 debug symbols)
+ This manual documents the usage and internals of libitm. It provides
+ transaction support for accesses to the memory of a process, enabling
+ easy-to-use synchronization of accesses to shared memory by several threads.
+')`'dnl libx32itm
+
+ifenabled(`libhfitm',`
+Package: libhfitm`'ITM_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libitm'ITM_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (hard float ABI)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: libhfitm`'ITM_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(itm`'ITM_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libitm'ITM_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (hard float ABI debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+')`'dnl libhfitm
+
+ifenabled(`libsfitm',`
+Package: libsfitm`'ITM_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (soft float ABI)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+
+Package: libsfitm`'ITM_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(itm`'ITM_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library (soft float ABI debug symbols)
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+')`'dnl libsfitm
+
+ifenabled(`libneonitm',`
+Package: libitm`'ITM_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: optional
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Transactional Memory Library [neon optimized]
+ GNU Transactional Memory Library (libitm) provides transaction support for
+ accesses to the memory of a process, enabling easy-to-use synchronization of
+ accesses to shared memory by several threads.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonitm
+')`'dnl libitm
+
+ifenabled(`libatomic',`
+Package: libatomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libatomic'ATOMIC_SO`-armel [armel], libatomic'ATOMIC_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libatomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libatomic'ATOMIC_SO`-dbg-armel [armel], libatomic'ATOMIC_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: lib32atomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (32bit)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: lib32atomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (32 bit debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: lib64atomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (64bit)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: lib64atomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (64bit debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libn32atomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (n32)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libn32atomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (n32 debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+ifenabled(`libx32atomic',`
+Package: libx32atomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (x32)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libx32atomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (x32 debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+')`'dnl libx32atomic
+
+ifenabled(`libhfatomic',`
+Package: libhfatomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libatomic'ATOMIC_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (hard float ABI)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libhfatomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libatomic'ATOMIC_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (hard float ABI debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+')`'dnl libhfatomic
+
+ifenabled(`libsfatomic',`
+Package: libsfatomic`'ATOMIC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (soft float ABI)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+
+Package: libsfatomic`'ATOMIC_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(atomic`'ATOMIC_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions (soft float ABI debug symbols)
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+')`'dnl libsfatomic
+
+ifenabled(`libneonatomic',`
+Package: libatomic`'ATOMIC_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: optional
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: support library providing __atomic built-in functions [neon optimized]
+ library providing __atomic built-in functions. When an atomic call cannot
+ be turned into lock-free instructions, GCC will make calls into this library.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonatomic
+')`'dnl libatomic
+
+ifenabled(`libasan',`
+Package: libasan`'ASAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libasan'ASAN_SO`-armel [armel], libasan'ASAN_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libasan`'ASAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(asan`'ASAN_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libasan'ASAN_SO`-dbg-armel [armel], libasan'ASAN_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib32asan`'ASAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (32bit)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib32asan`'ASAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(asan`'ASAN_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (32 bit debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib64asan`'ASAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (64bit)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: lib64asan`'ASAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(asan`'ASAN_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (64bit debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+#Package: libn32asan`'ASAN_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: optional
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: AddressSanitizer -- a fast memory error detector (n32)
+# AddressSanitizer (ASan) is a fast memory error detector.  It finds
+# use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+#Package: libn32asan`'ASAN_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: optional
+#Depends: BASELDEP, libdep(asan`'ASAN_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: AddressSanitizer -- a fast memory error detector (n32 debug symbols)
+# AddressSanitizer (ASan) is a fast memory error detector.  It finds
+# use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+ifenabled(`libx32asan',`
+Package: libx32asan`'ASAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (x32)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libx32asan`'ASAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(asan`'ASAN_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (x32 debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+')`'dnl libx32asan
+
+ifenabled(`libhfasan',`
+Package: libhfasan`'ASAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libasan'ASAN_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (hard float ABI)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libhfasan`'ASAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(asan`'ASAN_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libasan'ASAN_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (hard float ABI debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+')`'dnl libhfasan
+
+ifenabled(`libsfasan',`
+Package: libsfasan`'ASAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (soft float ABI)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+
+Package: libsfasan`'ASAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(asan`'ASAN_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector (soft float ABI debug symbols)
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+')`'dnl libsfasan
+
+ifenabled(`libneonasan',`
+Package: libasan`'ASAN_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: optional
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AddressSanitizer -- a fast memory error detector [neon optimized]
+ AddressSanitizer (ASan) is a fast memory error detector.  It finds
+ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonasan
+')`'dnl libasan
+
+ifenabled(`liblsan',`
+Package: liblsan`'LSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (runtime)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+
+Package: liblsan`'LSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(lsan`'LSAN_SO,,=), ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (debug symbols)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+
+ifenabled(`lib32lsan',`
+Package: lib32lsan`'LSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (32bit)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer (empty package).
+
+Package: lib32lsan`'LSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(lsan`'LSAN_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (32 bit debug symbols)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer (empty package).
+')`'dnl lib32lsan
+
+ifenabled(`lib64lsan',`
+#Package: lib64lsan`'LSAN_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+#Priority: optional
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: LeakSanitizer -- a memory leak detector (64bit)
+# LeakSanitizer (Lsan) is a memory leak detector which is integrated
+# into AddressSanitizer.
+
+#Package: lib64lsan`'LSAN_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+#Section: debug
+#Priority: optional
+#Depends: BASELDEP, libdep(lsan`'LSAN_SO,64,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: LeakSanitizer -- a memory leak detector (64bit debug symbols)
+# LeakSanitizer (Lsan) is a memory leak detector which is integrated
+# into AddressSanitizer.
+')`'dnl lib64lsan
+
+ifenabled(`libn32lsan',`
+#Package: libn32lsan`'LSAN_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: optional
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: LeakSanitizer -- a memory leak detector (n32)
+# LeakSanitizer (Lsan) is a memory leak detector which is integrated
+# into AddressSanitizer.
+
+#Package: libn32lsan`'LSAN_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: optional
+#Depends: BASELDEP, libdep(lsan`'LSAN_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: LeakSanitizer -- a memory leak detector (n32 debug symbols)
+# LeakSanitizer (Lsan) is a memory leak detector which is integrated
+# into AddressSanitizer.
+')`'dnl libn32lsan
+
+ifenabled(`libx32lsan',`
+Package: libx32lsan`'LSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (x32)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer (empty package).
+
+Package: libx32lsan`'LSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(lsan`'LSAN_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (x32 debug symbols)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer (empty package).
+')`'dnl libx32lsan
+
+ifenabled(`libhflsan',`
+Package: libhflsan`'LSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: liblsan'LSAN_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (hard float ABI)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+
+Package: libhflsan`'LSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(lsan`'LSAN_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: liblsan'LSAN_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (hard float ABI debug symbols)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+')`'dnl libhflsan
+
+ifenabled(`libsflsan',`
+Package: libsflsan`'LSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (soft float ABI)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+
+Package: libsflsan`'LSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(lsan`'LSAN_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector (soft float ABI debug symbols)
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+')`'dnl libsflsan
+
+ifenabled(`libneonlsan',`
+Package: liblsan`'LSAN_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: optional
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: LeakSanitizer -- a memory leak detector [neon optimized]
+ LeakSanitizer (Lsan) is a memory leak detector which is integrated
+ into AddressSanitizer.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonlsan
+')`'dnl liblsan
+
+ifenabled(`libtsan',`
+Package: libtsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libtsan'TSAN_SO`-armel [armel], libtsan'TSAN_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (runtime)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: libtsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libtsan'TSAN_SO`-dbg-armel [armel], libtsan'TSAN_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (debug symbols)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+ifenabled(`lib32tsan',`
+Package: lib32tsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (32bit)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: lib32tsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (32 bit debug symbols)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+')`'dnl lib32tsan
+
+ifenabled(`lib64tsan',`
+Package: lib64tsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (64bit)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: lib64tsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (64bit debug symbols)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+')`'dnl lib64tsan
+
+ifenabled(`libn32tsan',`
+Package: libn32tsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (n32)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: libn32tsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (n32 debug symbols)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+')`'dnl libn32tsan
+
+ifenabled(`libx32tsan',`
+Package: libx32tsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (x32)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: libx32tsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (x32 debug symbols)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+')`'dnl libx32tsan
+
+ifenabled(`libhftsan',`
+Package: libhftsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libtsan'TSAN_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (hard float ABI)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: libhftsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libtsan'TSAN_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (hard float ABI debug symbols)
+')`'dnl libhftsan
+
+ifenabled(`libsftsan',`
+Package: libsftsan`'TSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (soft float ABI)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+
+Package: libsftsan`'TSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(tsan`'TSAN_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races (soft float ABI debug symbols)
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+')`'dnl libsftsan
+
+ifenabled(`libneontsan',`
+Package: libtsan`'TSAN_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: optional
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: ThreadSanitizer -- a Valgrind-based detector of data races [neon optimized]
+ ThreadSanitizer (Tsan) is a data race detector for C/C++ programs. 
+ The Linux and Mac versions are based on Valgrind. 
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneontsan
+')`'dnl libtsan
+
+ifenabled(`libubsan',`
+Package: libubsan`'UBSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libubsan'UBSAN_SO`-armel [armel], libubsan'UBSAN_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (runtime)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libubsan`'UBSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libubsan'UBSAN_SO`-dbg-armel [armel], libubsan'UBSAN_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+ifenabled(`lib32ubsan',`
+Package: lib32ubsan`'UBSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (32bit)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: lib32ubsan`'UBSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (32 bit debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+')`'dnl lib32ubsan
+
+ifenabled(`lib64ubsan',`
+Package: lib64ubsan`'UBSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (64bit)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: lib64ubsan`'UBSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (64bit debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+')`'dnl lib64ubsan
+
+ifenabled(`libn32ubsan',`
+#Package: libn32ubsan`'UBSAN_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: optional
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: UBSan -- undefined behaviour sanitizer (n32)
+# UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+# Various computations will be instrumented to detect undefined behavior
+# at runtime. Available for C and C++.
+
+#Package: libn32ubsan`'UBSAN_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: optional
+#Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: UBSan -- undefined behaviour sanitizer (n32 debug symbols)
+# UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+# Various computations will be instrumented to detect undefined behavior
+# at runtime. Available for C and C++.
+')`'dnl libn32ubsan
+
+ifenabled(`libx32ubsan',`
+Package: libx32ubsan`'UBSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (x32)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libx32ubsan`'UBSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (x32 debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+')`'dnl libx32ubsan
+
+ifenabled(`libhfubsan',`
+Package: libhfubsan`'UBSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libubsan'UBSAN_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (hard float ABI)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libhfubsan`'UBSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libubsan'UBSAN_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (hard float ABI debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+')`'dnl libhfubsan
+
+ifenabled(`libsfubsan',`
+Package: libsfubsan`'UBSAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (soft float ABI)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+
+Package: libsfubsan`'UBSAN_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(ubsan`'UBSAN_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer (soft float ABI debug symbols)
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+')`'dnl libsfubsan
+
+ifenabled(`libneonubsan',`
+Package: libubsan`'UBSAN_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: optional
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: UBSan -- undefined behaviour sanitizer [neon optimized]
+ UndefinedBehaviorSanitizer can be enabled via -fsanitize=undefined.
+ Various computations will be instrumented to detect undefined behavior
+ at runtime. Available for C and C++.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonubsan
+')`'dnl libubsan
+
+ifenabled(`libvtv',`
+Package: libvtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (runtime)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: libvtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(vtv`'VTV_SO,,=), ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: GNU vtable verification library (debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+ifenabled(`lib32vtv',`
+Package: lib32vtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (32bit)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: lib32vtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(vtv`'VTV_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (32 bit debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+')`'dnl lib32vtv
+
+ifenabled(`lib64vtv',`
+Package: lib64vtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (64bit)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: lib64vtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(vtv`'VTV_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (64bit debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+')`'dnl lib64vtv
+
+ifenabled(`libn32vtv',`
+Package: libn32vtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (n32)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: libn32vtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(vtv`'VTV_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (n32 debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+')`'dnl libn32vtv
+
+ifenabled(`libx32vtv',`
+Package: libx32vtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (x32)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: libx32vtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(vtv`'VTV_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (x32 debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+')`'dnl libx32vtv
+
+ifenabled(`libhfvtv',`
+Package: libhfvtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libvtv'VTV_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GNU vtable verification library (hard float ABI)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: libhfvtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(vtv`'VTV_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libvtv'VTV_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GNU vtable verification library (hard float ABI debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+')`'dnl libhfvtv
+
+ifenabled(`libsfvtv',`
+Package: libsfvtv`'VTV_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (soft float ABI)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+
+Package: libsfvtv`'VTV_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(vtv`'VTV_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library (soft float ABI debug symbols)
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+')`'dnl libsfvtv
+
+ifenabled(`libneonvtv',`
+Package: libvtv`'VTV_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: optional
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU vtable verification library [neon optimized]
+ Vtable verification is a new security hardening feature for GCC that
+ is designed to detect and handle (during program execution) when a
+ vtable pointer that is about to be used for a virtual function call is
+ not a valid vtable pointer for that call.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonvtv
+')`'dnl libvtv
+
+ifenabled(`libcilkrts',`
+Package: libcilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libcilkrts'CILKRTS_SO`-armel [armel], libcilkrts'CILKRTS_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (runtime)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libcilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libcilkrts'CILKRTS_SO`-dbg-armel [armel], libcilkrts'CILKRTS_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+ifenabled(`lib32cilkrts',`
+Package: lib32cilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (32bit)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: lib32cilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (32 bit debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+')`'dnl lib32cilkrts
+
+ifenabled(`lib64cilkrts',`
+Package: lib64cilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (64bit)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: lib64cilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (64bit debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+')`'dnl lib64cilkrts
+
+ifenabled(`libn32cilkrts',`
+Package: libn32cilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (n32)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libn32cilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (n32 debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+')`'dnl libn32cilkrts
+
+ifenabled(`libx32cilkrts',`
+Package: libx32cilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (x32)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libx32cilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (x32 debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+')`'dnl libx32cilkrts
+
+ifenabled(`libhfcilkrts',`
+Package: libhfcilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libcilkrts'CILKRTS_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (hard float ABI)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libhfcilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libcilkrts'CILKRTS_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (hard float ABI debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+')`'dnl libhfcilkrts
+
+ifenabled(`libsfcilkrts',`
+Package: libsfcilkrts`'CILKRTS_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (soft float ABI)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+
+Package: libsfcilkrts`'CILKRTS_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(cilkrts`'CILKRTS_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions (soft float ABI debug symbols)
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+')`'dnl libsfcilkrts
+
+ifenabled(`libneoncilkrts',`
+Package: libcilkrts`'CILKRTS_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: optional
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel Cilk Plus language extensions [neon optimized]
+ Intel Cilk Plus is an extension to the C and C++ languages to support
+ data and task parallelism.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneoncilkrts
+')`'dnl libcilkrts
+
+ifenabled(`libmpx',`
+Package: libmpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libmpx'MPX_SO`-armel [armel], libmpx'MPX_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libmpx0 (<< 6-20160120-1)
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (runtime)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libmpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(mpx`'MPX_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libmpx'MPX_SO`-dbg-armel [armel], libmpx'MPX_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+ifenabled(`lib32mpx',`
+Package: lib32mpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Replaces: lib32mpx0 (<< 6-20160120-1)
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (32bit)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: lib32mpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(mpx`'MPX_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (32 bit debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+')`'dnl lib32mpx
+
+ifenabled(`lib64mpx',`
+Package: lib64mpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib64mpx0 (<< 6-20160120-1)
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (64bit)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: lib64mpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(mpx`'MPX_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (64bit debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+')`'dnl lib64mpx
+
+ifenabled(`libn32mpx',`
+Package: libn32mpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (n32)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libn32mpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(mpx`'MPX_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (n32 debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+')`'dnl libn32mpx
+
+ifenabled(`libx32mpx',`
+Package: libx32mpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (x32)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libx32mpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(mpx`'MPX_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (x32 debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+')`'dnl libx32mpx
+
+ifenabled(`libhfmpx',`
+Package: libhfmpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libmpx'MPX_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (hard float ABI)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libhfmpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(mpx`'MPX_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libmpx'MPX_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (hard float ABI debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+')`'dnl libhfmpx
+
+ifenabled(`libsfmpx',`
+Package: libsfmpx`'MPX_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (soft float ABI)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+
+Package: libsfmpx`'MPX_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(mpx`'MPX_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Intel memory protection extensions (soft float ABI debug symbols)
+ Intel MPX is a set of processor features which, with compiler,
+ runtime library and OS support, brings increased robustness to
+ software by checking pointer references whose compile time normal
+ intentions are usurped at runtime due to buffer overflow.
+')`'dnl libsfmpx
+')`'dnl libmpx
+
+ifenabled(`libbacktrace',`
+Package: libbacktrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libbacktrace'BTRACE_SO`-armel [armel], libbacktrace'BTRACE_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: libbacktrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,,=), ${misc:Depends}
+ifdef(`TARGET',`',`Provides: libbacktrace'BTRACE_SO`-dbg-armel [armel], libbacktrace'BTRACE_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: stack backtrace library (debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: lib32backtrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: stack backtrace library (32bit)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: lib32backtrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (32 bit debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: lib64backtrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (64bit)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: lib64backtrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (64bit debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: libn32backtrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (n32)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: libn32backtrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (n32 debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+ifenabled(`libx32backtrace',`
+Package: libx32backtrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (x32)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: libx32backtrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (x32 debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+')`'dnl libx32backtrace
+
+ifenabled(`libhfbacktrace',`
+Package: libhfbacktrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libbacktrace'BTRACE_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: stack backtrace library (hard float ABI)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: libhfbacktrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,hf,=), ${misc:Depends}
+wifdef(`TARGET',`dnl',`Conflicts: libbacktrace'BTRACE_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: stack backtrace library (hard float ABI debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+')`'dnl libhfbacktrace
+
+ifenabled(`libsfbacktrace',`
+Package: libsfbacktrace`'BTRACE_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (soft float ABI)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+
+Package: libsfbacktrace`'BTRACE_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(backtrace`'BTRACE_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library (soft float ABI debug symbols)
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+')`'dnl libsfbacktrace
+
+ifenabled(`libneonbacktrace',`
+Package: libbacktrace`'BTRACE_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: optional
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: stack backtrace library [neon optimized]
+ libbacktrace uses the GCC unwind interface to collect a stack trace,
+ and parses DWARF debug info to get file/line/function information.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonbacktrace
+')`'dnl libbacktrace
+
+
+ifenabled(`libqmath',`
+Package: libquadmath`'QMATH_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: libquadmath`'QMATH_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(quadmath`'QMATH_SO,,=), ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+
+Package: lib32quadmath`'QMATH_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (32bit)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: lib32quadmath`'QMATH_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(quadmath`'QMATH_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (32 bit debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+
+Package: lib64quadmath`'QMATH_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library  (64bit)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: lib64quadmath`'QMATH_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(quadmath`'QMATH_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library  (64bit debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+
+#Package: libn32quadmath`'QMATH_SO`'LS
+#Section: ifdef(`TARGET',`devel',`libs')
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Priority: optional
+#Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: GCC Quad-Precision Math Library (n32)
+# A library, which provides quad-precision mathematical functions on targets
+# supporting the __float128 datatype. The library is used to provide on such
+# targets the REAL(16) type in the GNU Fortran compiler.
+
+#Package: libn32quadmath`'QMATH_SO-dbg`'LS
+#Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+#Section: debug
+#Priority: optional
+#Depends: BASELDEP, libdep(quadmath`'QMATH_SO,n32,=), ${misc:Depends}
+#BUILT_USING`'dnl
+#Description: GCC Quad-Precision Math Library (n32 debug symbols)
+# A library, which provides quad-precision mathematical functions on targets
+# supporting the __float128 datatype.
+
+ifenabled(`libx32qmath',`
+Package: libx32quadmath`'QMATH_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (x32)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: libx32quadmath`'QMATH_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(quadmath`'QMATH_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (x32 debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+')`'dnl libx32qmath
+
+ifenabled(`libhfqmath',`
+Package: libhfquadmath`'QMATH_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (hard float ABI)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: libhfquadmath`'QMATH_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(quadmath`'QMATH_SO,hf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (hard float ABI debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+')`'dnl libhfqmath
+
+ifenabled(`libsfqmath',`
+Package: libsfquadmath`'QMATH_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (soft float ABI)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype. The library is used to provide on such
+ targets the REAL(16) type in the GNU Fortran compiler.
+
+Package: libsfquadmath`'QMATH_SO-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(quadmath`'QMATH_SO,sf,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC Quad-Precision Math Library (hard float ABI debug symbols)
+ A library, which provides quad-precision mathematical functions on targets
+ supporting the __float128 datatype.
+')`'dnl libsfqmath
+')`'dnl libqmath
+
+ifenabled(`libcc1',`
+Package: libcc1-`'CC1_SO
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCC cc1 plugin for GDB
+ libcc1 is a plugin for GDB.
+')`'dnl libcc1
+
+ifenabled(`libjit',`
+Package: libgccjit`'GCCJIT_SO
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASEDEP, ${shlibs:Depends}, ${misc:Depends}
+Breaks: python-gccjit (<< 0.4-4), python3-gccjit (<< 0.4-4)
+BUILT_USING`'dnl
+Description: GCC just-in-time compilation (shared library)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit`'GCCJIT_SO-dbg
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASEDEP, libgccjit`'GCCJIT_SO (= ${gcc:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+Breaks: libgccjit-5-dbg, libgccjit-6-dbg
+Replaces: libgccjit-5-dbg, libgccjit-6-dbg
+BUILT_USING`'dnl
+Description: GCC just-in-time compilation (debug information)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+')`'dnl libjit
+
+ifenabled(`jit',`
+Package: libgccjit`'PV-doc
+Section: doc
+Architecture: all
+Priority: optional
+Depends: BASEDEP, ${misc:Depends}
+Conflicts: libgccjit-5-doc
+Description: GCC just-in-time compilation (documentation)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+
+Package: libgccjit`'PV-dev
+Section: ifdef(`TARGET',`devel',`libdevel')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASEDEP, libgccjit`'GCCJIT_SO (>= ${gcc:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Suggests: libgccjit`'PV-dbg
+Description: GCC just-in-time compilation (development files)
+ libgccjit provides an embeddable shared library with an API for adding
+ compilation to existing programs using GCC.
+')`'dnl jit
+
+ifenabled(`objpp',`
+ifenabled(`objppdev',`
+Package: gobjc++`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: optional
+Depends: BASEDEP, gobjc`'PV`'TS (= ${gcc:Version}), g++`'PV`'TS (= ${gcc:Version}), ${shlibs:Depends}, libidevdep(objc`'PV-dev,,=), ${misc:Depends}
+Suggests: ${gobjcxx:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion})
+Provides: objc++-compiler`'TS
+BUILT_USING`'dnl
+Description: GNU Objective-C++ compiler
+ This is the GNU Objective-C++ compiler, which compiles
+ Objective-C++ on platforms supported by the gcc compiler. It uses the
+ gcc backend to generate optimized code.
+')`'dnl obcppdev
+
+ifenabled(`multilib',`
+Package: gobjc++`'PV-multilib`'TS
+Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: optional
+Depends: BASEDEP, gobjc++`'PV`'TS (= ${gcc:Version}), g++`'PV-multilib`'TS (= ${gcc:Version}), gobjc`'PV-multilib`'TS (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Objective-C++ compiler (multilib support)
+ This is the GNU Objective-C++ compiler, which compiles Objective-C++ on
+ platforms supported by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+')`'dnl obcpp
+
+ifenabled(`objc',`
+ifenabled(`objcdev',`
+Package: gobjc`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: optional
+Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:libcdev}, ${shlibs:Depends}, libidevdep(objc`'PV-dev,,=), ${misc:Depends}
+Suggests: ${gobjc:multilib}, gcc`'PV-doc (>= ${gcc:SoftVersion}), libdbgdep(objc`'OBJC_SO-dbg,)
+Provides: objc-compiler`'TS
+ifdef(`__sparc__',`Conflicts: gcc`'PV-sparc64', `dnl')
+BUILT_USING`'dnl
+Description: GNU Objective-C compiler
+ This is the GNU Objective-C compiler, which compiles
+ Objective-C on platforms supported by the gcc compiler. It uses the
+ gcc backend to generate optimized code.
+
+ifenabled(`multilib',`
+Package: gobjc`'PV-multilib`'TS
+Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: optional
+Depends: BASEDEP, gobjc`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libobjcbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Objective-C compiler (multilib support)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU Objective-C compiler, which compiles Objective-C on platforms
+ supported by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+
+Package: libobjc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,), libdep(objc`'OBJC_SO,), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: lib64objc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,64), libdep(objc`'OBJC_SO,64), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (64bit development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: lib32objc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,32), libdep(objc`'OBJC_SO,32), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (32bit development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+Package: libn32objc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,n32), libdep(objc`'OBJC_SO,n32), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (n32 development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+
+ifenabled(`x32dev',`
+Package: libx32objc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,x32), libdep(objc`'OBJC_SO,x32), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (x32 development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+')`'dnl libx32objc
+
+ifenabled(`armml',`
+Package: libhfobjc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,hf), libdep(objc`'OBJC_SO,hf), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (hard float ABI development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+')`'dnl armml
+
+ifenabled(`armml',`
+Package: libsfobjc`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,sf), libdep(objc`'OBJC_SO,sf), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (soft float development files)
+ This package contains the headers and static library files needed to build
+ GNU ObjC applications.
+')`'dnl armml
+')`'dnl objcdev
+
+ifenabled(`libobjc',`
+Package: libobjc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libobjc'OBJC_SO`-armel [armel], libobjc'OBJC_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+ifelse(OBJC_SO,`2',`Breaks: ${multiarch:breaks}
+',`')')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libobjc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libobjc'OBJC_SO`-dbg-armel [armel], libobjc'OBJC_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Priority: optional
+Depends: BASELDEP, libdep(objc`'OBJC_SO,,=), libdbgdep(gcc`'GCC_SO-dbg,,>=,${libgcc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl libobjc
+
+ifenabled(`lib64objc',`
+Package: lib64objc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (64bit)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: lib64objc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, libdep(objc`'OBJC_SO,64,=), libdbgdep(gcc`'GCC_SO-dbg,64,>=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (64 bit debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl lib64objc
+
+ifenabled(`lib32objc',`
+Package: lib32objc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (32bit)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: lib32objc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, libdep(objc`'OBJC_SO,32,=), libdbgdep(gcc`'GCC_SO-dbg,32,>=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (32 bit debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl lib32objc
+
+ifenabled(`libn32objc',`
+Package: libn32objc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (n32)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libn32objc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, libdep(objc`'OBJC_SO,n32,=), libdbgdep(gcc`'GCC_SO-dbg,n32,>=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (n32 debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl libn32objc
+
+ifenabled(`libx32objc',`
+Package: libx32objc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (x32)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libx32objc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, libdep(objc`'OBJC_SO,x32,=), libdbgdep(gcc`'GCC_SO-dbg,x32,>=,${gcc:EpochVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (x32 debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl libx32objc
+
+ifenabled(`libhfobjc',`
+Package: libhfobjc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (hard float ABI)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libhfobjc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, libdep(objc`'OBJC_SO,hf,=), libdbgdep(gcc`'GCC_SO-dbg,hf,>=,${gcc:EpochVersion}), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-dbg-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (hard float ABI debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl libhfobjc
+
+ifenabled(`libsfobjc',`
+Package: libsfobjc`'OBJC_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (soft float ABI)
+ Library needed for GNU ObjC applications linked against the shared library.
+
+Package: libsfobjc`'OBJC_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, libdep(objc`'OBJC_SO,sf,=), libdbgdep(gcc`'GCC_SO-dbg,sf,>=,${gcc:EpochVersion}), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libobjc'OBJC_SO`-dbg-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications (soft float ABI debug symbols)
+ Library needed for GNU ObjC applications linked against the shared library.
+')`'dnl libsfobjc
+
+ifenabled(`libneonobjc',`
+Package: libobjc`'OBJC_SO-neon`'LS
+Section: libs
+Architecture: NEON_ARCHS
+Priority: PRI(optional)
+Depends: BASELDEP, libc6-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Objective-C applications  [NEON version]
+ Library needed for GNU ObjC applications linked against the shared library.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneonobjc
+')`'dnl objc
+
+ifenabled(`fortran',`
+ifenabled(`fdev',`
+Package: gfortran`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: optional
+Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), libidevdep(gfortran`'PV-dev,,=), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Provides: fortran95-compiler, ${fortran:mod-version}
+Suggests: ${gfortran:multilib}, gfortran`'PV-doc,
+ libdbgdep(gfortran`'FORTRAN_SO-dbg,),
+ libcoarrays-dev
+BUILT_USING`'dnl
+Description: GNU Fortran compiler
+ This is the GNU Fortran compiler, which compiles
+ Fortran on platforms supported by the gcc compiler. It uses the
+ gcc backend to generate optimized code.
+
+ifenabled(`multilib',`
+Package: gfortran`'PV-multilib`'TS
+Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: optional
+Depends: BASEDEP, gfortran`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libgfortranbiarchdev}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Fortran compiler (multilib support)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU Fortran compiler, which compiles Fortran on platforms
+ supported by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+
+ifenabled(`gfdldoc',`
+Package: gfortran`'PV-doc
+Architecture: all
+Section: doc
+Priority: PRI(optional)
+Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Description: Documentation for the GNU Fortran compiler (gfortran)
+ Documentation for the GNU Fortran compiler in info `format'.
+')`'dnl gfdldoc
+
+Package: libgfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',), libdep(gfortran`'FORTRAN_SO,), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: lib64gfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',64), libdep(gfortran`'FORTRAN_SO,64), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (64bit development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: lib32gfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',32), libdep(gfortran`'FORTRAN_SO,32), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (32bit development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+Package: libn32gfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',n32), libdep(gfortran`'FORTRAN_SO,n32), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (n32 development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+
+ifenabled(`x32dev',`
+Package: libx32gfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',x32), libdep(gfortran`'FORTRAN_SO,x32), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (x32 development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+')`'dnl libx32gfortran
+
+ifenabled(`armml',`
+Package: libhfgfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',hf), libdep(gfortran`'FORTRAN_SO,hf), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (hard float ABI development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+')`'dnl armml
+
+ifenabled(`armml',`
+Package: libsfgfortran`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev`',sf), libdep(gfortran`'FORTRAN_SO,sf), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (soft float ABI development files)
+ This package contains the headers and static library files needed to build
+ GNU Fortran applications.
+')`'dnl armml
+')`'dnl fdev
+
+ifenabled(`libgfortran',`
+Package: libgfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libgfortran'FORTRAN_SO`-armel [armel], libgfortran'FORTRAN_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libgfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libgfortran'FORTRAN_SO`-dbg-armel [armel], libgfortran'FORTRAN_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Priority: optional
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,,=), libdbgdep(gcc`'GCC_SO-dbg,,>=,${libgcc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl libgfortran
+
+ifenabled(`lib64gfortran',`
+Package: lib64gfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (64bit)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: lib64gfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (64bit debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl lib64gfortran
+
+ifenabled(`lib32gfortran',`
+Package: lib32gfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (32bit)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: lib32gfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (32 bit debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl lib32gfortran
+
+ifenabled(`libn32gfortran',`
+Package: libn32gfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (n32)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libn32gfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (n32 debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl libn32gfortran
+
+ifenabled(`libx32gfortran',`
+Package: libx32gfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (x32)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libx32gfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (x32 debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl libx32gfortran
+
+ifenabled(`libhfgfortran',`
+Package: libhfgfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (hard float ABI)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libhfgfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,hf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-dbg-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl libhfgfortran
+
+ifenabled(`libsfgfortran',`
+Package: libsfgfortran`'FORTRAN_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (soft float ABI)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+
+Package: libsfgfortran`'FORTRAN_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, libdep(gfortran`'FORTRAN_SO,sf,=), ${misc:Depends}
+ifdef(`TARGET',`dnl',`Conflicts: libgfortran'FORTRAN_SO`-dbg-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications (hard float ABI debug symbols)
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+')`'dnl libsfgfortran
+
+ifenabled(`libneongfortran',`
+Package: libgfortran`'FORTRAN_SO-neon`'LS
+Section: libs
+Architecture: NEON_ARCHS
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, libgcc1-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Fortran applications [NEON version]
+ Library needed for GNU Fortran applications linked against the
+ shared library.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl libneongfortran
+')`'dnl fortran
+
+ifenabled(`ggo',`
+ifenabled(`godev',`
+Package: gccgo`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: optional
+Depends: BASEDEP, ifdef(`STANDALONEGO',`${dep:libcc1}, ',`gcc`'PV`'TS (= ${gcc:Version}), ')libidevdep(go`'GO_SO,,>=), ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Provides: go-compiler
+Suggests: ${go:multilib}, gccgo`'PV-doc, libdbgdep(go`'GO_SO-dbg,)
+Conflicts: ${golang:Conflicts}
+Breaks: libgo`'GO_SO`'LS (<< 6.4.0-12)
+Replaces: libgo`'GO_SO`'LS (<< 6.4.0-12)
+BUILT_USING`'dnl
+Description: GNU Go compiler
+ This is the GNU Go compiler, which compiles Go on platforms supported
+ by the gcc compiler. It uses the gcc backend to generate optimized code.
+
+ifenabled(`multilib',`
+Package: gccgo`'PV-multilib`'TS
+Architecture: ifdef(`TARGET',`any',MULTILIB_ARCHS)
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Section: devel
+Priority: optional
+Depends: BASEDEP, gccgo`'PV`'TS (= ${gcc:Version}), ifdef(`STANDALONEGO',,`gcc`'PV-multilib`'TS (= ${gcc:Version}), ')${dep:libgobiarch}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: ${dep:libgobiarchdbg}
+Breaks: lib32go`'GO_SO`'LS (<< 6.4.0-12),
+  libn32go`'GO_SO`'LS (<< 6.4.0-12),
+  libx32go`'GO_SO`'LS (<< 6.4.0-12),
+  lib64go`'GO_SO`'LS (<< 6.4.0-12)
+Replaces: lib32go`'GO_SO`'LS (<< 6.4.0-12),
+  libn32go`'GO_SO`'LS (<< 6.4.0-12),
+  libx32go`'GO_SO`'LS (<< 6.4.0-12),
+  lib64go`'GO_SO`'LS (<< 6.4.0-12)
+BUILT_USING`'dnl
+Description: GNU Go compiler (multilib support)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU Go compiler, which compiles Go on platforms supported
+ by the gcc compiler.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+
+ifenabled(`gfdldoc',`
+Package: gccgo`'PV-doc
+Architecture: all
+Section: doc
+Priority: PRI(optional)
+Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Documentation for the GNU Go compiler (gccgo)
+ Documentation for the GNU Go compiler in info `format'.
+')`'dnl gfdldoc
+')`'dnl fdev
+
+ifenabled(`libggo',`
+Package: libgo`'GO_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libgo'GO_SO`-armel [armel], libgo'GO_SO`-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libgo3`'LS, libgo8`'LS
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: libgo`'GO_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`TARGET',`',`Provides: libgo'GO_SO`-dbg-armel [armel], libgo'GO_SO`-dbg-armhf [armhf]
+')`'dnl
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Priority: optional
+Depends: BASELDEP, libdep(go`'GO_SO,,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+')`'dnl libgo
+
+ifenabled(`lib64ggo',`
+Package: lib64go`'GO_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib64go3`'LS, lib64go8`'LS
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (64bit)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: lib64go`'GO_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, libdep(go`'GO_SO,64,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (64bit debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+')`'dnl lib64go
+
+ifenabled(`lib32ggo',`
+Package: lib32go`'GO_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+Replaces: lib32go3`'LS, lib32go8`'LS
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (32bit)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: lib32go`'GO_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, libdep(go`'GO_SO,32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (32 bit debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+')`'dnl lib32go
+
+ifenabled(`libn32ggo',`
+Package: libn32go`'GO_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libn32go3`'LS, libn32go8`'LS
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (n32)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: libn32go`'GO_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, libdep(go`'GO_SO,n32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (n32 debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+')`'dnl libn32go
+
+ifenabled(`libx32ggo',`
+Package: libx32go`'GO_SO`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libx32go3`'LS, libx32go8`'LS
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (x32)
+ Library needed for GNU Go applications linked against the
+ shared library.
+
+Package: libx32go`'GO_SO-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, libdep(go`'GO_SO,x32,=), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Runtime library for GNU Go applications (x32 debug symbols)
+ Library needed for GNU Go applications linked against the
+ shared library. This currently is an empty package, because the
+ library is completely unstripped.
+')`'dnl libx32go
+')`'dnl ggo
+
+ifenabled(`java',`
+ifenabled(`gcj',`
+Package: gcj`'PV`'TS
+Section: java
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: optional
+Depends: BASEDEP, gcc`'PV`'TS (= ${gcc:Version}), ${dep:gcj}, ${dep:gcjcross}, ${dep:libcdev}, ${dep:ecj}, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Recommends: libecj-java-gcj
+Replaces: gcj-5-jdk (<< 5.2.1-19)
+Suggests: gcj`'PV-jdk
+BUILT_USING`'dnl
+Description: GCJ byte code and native compiler for Java(TM)
+ GCJ is a front end to the GCC compiler which can natively compile both
+ Java(tm) source and bytecode files. The compiler can also generate class
+ files.
+ .
+ifdef(`TARGET',`'dnl
+,` Install the gcj`'PV`'TS-jdk package for a more complete SDK environment.
+')`'dnl
+')`'dnl gcj
+
+ifenabled(`libgcj',`
+ifenabled(`libgcjcommon',`
+Package: libgcj-common
+Section: java
+Architecture: all
+Priority: PRI(optional)
+Depends: BASEDEP, ${misc:Depends}
+Conflicts: classpath (<= 0.04-4)
+Replaces: java-gcj-compat (<< 1.0.65-3), java-gcj-compat-dev (<< 1.0.65-3)
+BUILT_USING`'dnl
+Description: Java runtime library (common files)
+ This package contains files shared by Classpath and libgcj libraries.
+')`'dnl libgcjcommon
+
+
+Package: gcj`'PV-jdk`'TS
+Section: java
+Architecture: any
+Priority: optional
+Depends: BASEDEP, ${dep:gcj}, ${dep:libcdev}, gcj`'PV`'TS (= ${gcj:Version}), gcj`'PV-jre`'TS (= ${gcj:Version}), libidevdep(gcj`'GCJ_SO-dev,,>=,${gcj:Version}), fastjar, libgcj-bc`'LS, java-common, libantlr-java, ${shlibs:Depends}, dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Recommends: libecj-java-gcj
+Suggests: gcj`'PV-source (>= ${gcj:SoftVersion}), libdbgdep(gcj`'GCJ_SO-dbg,)
+Provides: java-compiler, java-sdk, java2-sdk, java5-sdk
+Conflicts: gcj-4.4, cpp-4.1 (<< 4.1.1), gcc-4.1 (<< 4.1.1)
+Replaces: libgcj11 (<< 4.5-20100101-1)
+BUILT_USING`'dnl
+Description: GCJ and Classpath development tools for Java(TM)
+ GCJ is a front end to the GCC compiler which can natively compile both
+ Java(tm) source and bytecode files. The compiler can also generate class
+ files. Other java development tools from classpath are included in this
+ package.
+ .
+ The package contains as well a collection of wrapper scripts and symlinks.
+ It is meant to provide a Java-SDK-like interface to the GCJ tool set.
+
+Package: gcj`'PV-jre-headless`'TS
+Priority: optional
+Section: java
+Architecture: any
+Depends: BASEDEP, gcj`'PV-jre-lib`'TS (>= ${gcj:SoftVersion}), libdep(gcj`'LIBGCJ_EXT,,>=,${gcj:Version}), ${dep:prctl}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: fastjar, gcj`'PV-jdk`'TS (= ${gcj:Version}), libdep(gcj`'LIBGCJ_EXT-awt,,>=,${gcj:Version})
+Provides: java5-runtime-headless, java2-runtime-headless, java1-runtime-headless, java-runtime-headless
+BUILT_USING`'dnl
+Description: Java runtime environment using GIJ/Classpath (headless version)
+ GIJ is a Java bytecode interpreter, not limited to interpreting bytecode.
+ It includes a class loader which can dynamically load shared objects, so
+ it is possible to give it the name of a class which has been compiled and
+ put into a shared library on the class path.
+ .
+ The package contains as well a collection of wrapper scripts and symlinks.
+ It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set,
+ limited to the headless tools and libraries.
+
+Package: gcj`'PV-jre`'TS
+Section: java
+Architecture: any
+Priority: optional
+Depends: BASEDEP, gcj`'PV-jre-headless`'TS (= ${gcj:Version}), libdep(gcj`'LIBGCJ_EXT-awt,,>=,${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+Provides: java5-runtime, java2-runtime, java1-runtime, java-runtime
+BUILT_USING`'dnl
+Description: Java runtime environment using GIJ/Classpath
+ GIJ is a Java bytecode interpreter, not limited to interpreting bytecode.
+ It includes a class loader which can dynamically load shared objects, so
+ it is possible to give it the name of a class which has been compiled and
+ put into a shared library on the class path.
+ .
+ The package contains as well a collection of wrapper scripts and symlinks.
+ It is meant to provide a Java-RTE-like interface to the GIJ/GCJ tool set.
+
+Package: libgcj`'LIBGCJ_EXT`'LS
+Section: libs
+Architecture: any
+Priority: PRI(optional)
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+')`'dnl
+Depends: SOFTBASEDEP, libgcj-common (>= 1:4.1.1-21), ${shlibs:Depends}, ${misc:Depends}
+Recommends: gcj`'PV-jre-lib`'TS (>= ${gcj:SoftVersion})
+Suggests: libdbgdep(gcj`'GCJ_SO-dbg,), libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version})
+BUILT_USING`'dnl
+Description: Java runtime library for use with gcj
+ This is the runtime that goes along with the gcj front end to
+ gcc. libgcj includes parts of the Java Class Libraries, plus glue to
+ connect the libraries to the compiler and the underlying OS.
+ .
+ To show file names and line numbers in stack traces, the packages
+ libgcj`'GCJ_SO-dbg and binutils are required.
+
+Package: gcj`'PV-jre-lib`'TS
+Section: java
+Architecture: all
+Priority: PRI(optional)
+Depends: SOFTBASEDEP, libdep(gcj`'LIBGCJ_EXT,,>=,${gcj:SoftVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Java runtime library for use with gcj (jar files)
+ This is the jar file that goes along with the gcj front end to gcc.
+
+ifenabled(`gcjbc',`
+Package: libgcj-bc
+Section: java
+Architecture: any
+Priority: PRI(optional)
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+')`'dnl
+Depends: BASEDEP, libdep(gcj`'LIBGCJ_EXT,,>=,${gcj:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Link time only library for use with gcj
+ A fake library that is used at link time only.  It ensures that
+ binaries built with the BC-ABI link against a constant SONAME.
+ This way, BC-ABI binaries continue to work if the SONAME underlying
+ libgcj.so changes.
+')`'dnl gcjbc
+
+Package: libgcj`'LIBGCJ_EXT-awt`'LS
+Section: libs
+Architecture: any
+Priority: PRI(optional)
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+')`'dnl
+Depends: SOFTBASEDEP, libdep(gcj`'LIBGCJ_EXT,,=,${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+Suggests: ${pkg:gcjqt}
+BUILT_USING`'dnl
+Description: AWT peer runtime libraries for use with gcj
+ These are runtime libraries holding the AWT peer implementations
+ for libgcj (currently the GTK+ based peer library is required, the
+ QT bases library is not built).
+
+ifenabled(`gtkpeer',`
+Package: libgcj`'GCJ_SO-awt-gtk`'LS
+Section: libs
+Architecture: any
+Priority: PRI(optional)
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+')`'dnl
+Depends: SOFTBASEDEP, libgcj`'LIBGCJ_EXT-awt`'LS (= ${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AWT GTK+ peer runtime library for use with libgcj
+ This is the runtime library holding the GTK+ based AWT peer
+ implementation for libgcj.
+')`'dnl gtkpeer
+
+ifenabled(`qtpeer',`
+Package: libgcj`'GCJ_SO-awt-qt`'LS
+Section: libs
+Architecture: any
+Priority: PRI(optional)
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+')`'dnl
+Depends: SOFTBASEDEP, libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: AWT QT peer runtime library for use with libgcj
+ This is the runtime library holding the QT based AWT peer
+ implementation for libgcj.
+')`'dnl qtpeer
+')`'dnl libgcj
+
+ifenabled(`libgcjdev',`
+Package: libgcj`'GCJ_SO-dev`'LS
+Section: libdevel
+Architecture: any
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Priority: PRI(optional)
+Depends: BASEDEP, libdep(gcj`'LIBGCJ_EXT-awt,,=,${gcj:Version}), libgcj-bc`'LS, ${pkg:gcjgtk}, ${pkg:gcjqt}, zlib1g-dev, ${shlibs:Depends}, ${misc:Depends}
+Suggests: libgcj-doc
+BUILT_USING`'dnl
+Description: Java development headers for use with gcj
+ These are the development headers that go along with the gcj front end
+ to gcc. libgcj includes parts of the Java Class Libraries, plus glue
+ to connect the libraries to the compiler and the underlying OS.
+
+Package: libgcj`'GCJ_SO-dbg`'LS
+Section: debug
+Architecture: any
+Priority: optional
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+Multi-Arch: same
+')`'dnl
+Depends: BASEDEP, libdep(gcj`'LIBGCJ_EXT,,=,${gcj:Version}), ${misc:Depends}
+Recommends: binutils, libc6-dbg | libc-dbg
+BUILT_USING`'dnl
+Description: Debugging symbols for libraries provided in libgcj`'GCJ_SO-dev
+ The package provides debugging symbols for the libraries provided
+ in libgcj`'GCJ_SO-dev.
+ .
+ binutils is required to show file names and line numbers in stack traces.
+
+ifenabled(`gcjsrc',`
+Package: gcj`'PV-source
+Section: java
+Architecture: all
+Priority: PRI(optional)
+Depends: SOFTBASEDEP, gcj`'PV-jdk (>= ${gcj:SoftVersion}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GCJ java sources for use in IDEs like eclipse and netbeans
+ These are the java source files packaged as a zip file for use in development
+ environments like eclipse and netbeans.
+')`'dnl
+
+ifenabled(`gcjdoc',`
+Package: libgcj-doc
+Section: doc
+Architecture: all
+Priority: PRI(optional)
+Depends: SOFTBASEDEP, ${misc:Depends}
+Enhances: libgcj`'GCJ_SO-dev
+Provides: classpath-doc
+BUILT_USING`'dnl
+Description: libgcj API documentation and example programs
+ Autogenerated documentation describing the API of the libgcj library.
+ Sources and precompiled example programs from the Classpath library.
+')`'dnl gcjdoc
+')`'dnl libgcjdev
+')`'dnl java
+
+ifenabled(`c++',`
+ifenabled(`libcxx',`
+Package: libstdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: ifdef(`TARGET',`optional',PRI(important))
+Depends: BASELDEP, ${dep:libc}, ${shlibs:Depends}, ${misc:Depends}
+Provides: ifdef(`TARGET',`libstdc++CXX_SO-TARGET-dcv1',`libstdc++'CXX_SO`-armel [armel], libstdc++'CXX_SO`-armhf [armhf]')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+Breaks: ${multiarch:breaks}, PR66145BREAKS
+')`'dnl
+Conflicts: scim (<< 1.4.2-1)
+Replaces: libstdc++CXX_SO`'PV-dbg`'LS (<< 4.9.0-3)
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libcxx
+
+ifenabled(`lib32cxx',`
+Package: lib32stdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: optional
+Depends: BASELDEP, libdep(gcc1,32), ${shlibs:Depends}, ${misc:Depends}
+Conflicts: ${confl:lib32}
+ifdef(`TARGET',`Provides: lib32stdc++CXX_SO-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (32 bit Version)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl lib32cxx
+
+ifenabled(`lib64cxx',`
+Package: lib64stdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: optional
+Depends: BASELDEP, libdep(gcc1,64), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: lib64stdc++CXX_SO-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (64bit)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl lib64cxx
+
+ifenabled(`libn32cxx',`
+Package: libn32stdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: optional
+Depends: BASELDEP, libdep(gcc1,n32), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libn32stdc++CXX_SO-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (n32)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libn32cxx
+
+ifenabled(`libx32cxx',`
+Package: libx32stdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: optional
+Depends: BASELDEP, libdep(gcc1,x32), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libx32stdc++CXX_SO-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (x32)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libx32cxx
+
+ifenabled(`libhfcxx',`
+Package: libhfstdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: optional
+Depends: BASELDEP, libdep(gcc1,hf), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libhfstdc++CXX_SO-TARGET-dcv1
+',`')`'dnl
+ifdef(`TARGET',`dnl',`Conflicts: libstdc++'CXX_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (hard float ABI)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libhfcxx
+
+ifenabled(`libsfcxx',`
+Package: libsfstdc++CXX_SO`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: ifdef(`TARGET',`devel',`libs')
+Priority: optional
+Depends: BASELDEP, libdep(gcc1,sf), ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libsfstdc++CXX_SO-TARGET-dcv1
+',`')`'dnl
+ifdef(`TARGET',`dnl',`Conflicts: libstdc++'CXX_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3`'ifdef(`TARGET)',` (TARGET)', `') (soft float ABI)
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libsfcxx
+
+ifenabled(`libneoncxx',`
+Package: libstdc++CXX_SO-neon`'LS
+Architecture: NEON_ARCHS
+Section: libs
+Priority: optional
+Depends: BASELDEP, libc6-neon`'LS, libgcc1-neon`'LS, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 [NEON version]
+ This package contains an additional runtime library for C++ programs
+ built with the GNU compiler.
+ .
+ This set of libraries is optimized to use a NEON coprocessor, and will
+ be selected instead when running under systems which have one.
+')`'dnl
+
+ifenabled(`c++dev',`
+Package: libstdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,,=),
+ libdep(stdc++CXX_SO,,>=), ${dep:libcdev}, ${misc:Depends}
+ifdef(`TARGET',`',`dnl native
+Conflicts: libg++27-dev, libg++272-dev (<< 2.7.2.8-1), libstdc++2.8-dev,
+ libg++2.8-dev, libstdc++2.9-dev, libstdc++2.9-glibc2.1-dev,
+ libstdc++2.10-dev (<< 1:2.95.3-2), libstdc++3.0-dev
+Suggests: libstdc++`'PV-doc
+')`'dnl native
+Provides: libstdc++-dev`'LS`'ifdef(`TARGET',`, libstdc++-dev-TARGET-dcv1')
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libstdc++`'PV-pic`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: optional
+Depends: BASELDEP, libdep(stdc++CXX_SO,),
+ libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+ifdef(`TARGET',`Provides: libstdc++-pic-TARGET-dcv1
+',`')`'dnl
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (shared library subset kit)`'ifdef(`TARGET)',` (TARGET)', `')
+ This is used to develop subsets of the libstdc++ shared libraries for
+ use on custom installation floppies and in embedded systems.
+ .
+ Unless you are making one of those, you will not need this package.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libstdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(stdc++CXX_SO,),
+ libdbgdep(gcc`'GCC_SO-dbg,,>=,${libgcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+Provides: ifdef(`TARGET',`libstdc++CXX_SO-dbg-TARGET-dcv1',`libstdc++'CXX_SO`'PV`-dbg-armel [armel], libstdc++'CXX_SO`'PV`-dbg-armhf [armhf]')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Recommends: libdevdep(stdc++`'PV-dev,)
+Conflicts: libstdc++5-dbg`'LS, libstdc++5-3.3-dbg`'LS, libstdc++6-dbg`'LS,
+ libstdc++6-4.0-dbg`'LS, libstdc++6-4.1-dbg`'LS, libstdc++6-4.2-dbg`'LS,
+ libstdc++6-4.3-dbg`'LS, libstdc++6-4.4-dbg`'LS, libstdc++6-4.5-dbg`'LS,
+ libstdc++6-4.6-dbg`'LS, libstdc++6-4.7-dbg`'LS, libstdc++6-4.8-dbg`'LS,
+ libstdc++6-4.9-dbg`'LS, libstdc++6-5-dbg`'LS
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: lib32stdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,32),
+ libdep(stdc++CXX_SO,32), libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: lib32stdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(stdc++CXX_SO,32),
+ libdevdep(stdc++`'PV-dev,), libdbgdep(gcc`'GCC_SO-dbg,32,>=,${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: lib32stdc++CXX_SO-dbg-TARGET-dcv1
+',`')`'dnl
+Conflicts: lib32stdc++6-dbg`'LS, lib32stdc++6-4.0-dbg`'LS,
+ lib32stdc++6-4.1-dbg`'LS, lib32stdc++6-4.2-dbg`'LS, lib32stdc++6-4.3-dbg`'LS,
+ lib32stdc++6-4.4-dbg`'LS, lib32stdc++6-4.5-dbg`'LS, lib32stdc++6-4.6-dbg`'LS,
+ lib32stdc++6-4.7-dbg`'LS, lib32stdc++6-4.8-dbg`'LS, lib32stdc++6-4.9-dbg`'LS,
+ lib32stdc++6-5-dbg`'LS
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: lib64stdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,64),
+ libdep(stdc++CXX_SO,64), libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: lib64stdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(stdc++CXX_SO,64),
+ libdevdep(stdc++`'PV-dev,), libdbgdep(gcc`'GCC_SO-dbg,64,>=,${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: lib64stdc++CXX_SO-dbg-TARGET-dcv1
+',`')`'dnl
+Conflicts: lib64stdc++6-dbg`'LS, lib64stdc++6-4.0-dbg`'LS,
+ lib64stdc++6-4.1-dbg`'LS, lib64stdc++6-4.2-dbg`'LS, lib64stdc++6-4.3-dbg`'LS,
+ lib64stdc++6-4.4-dbg`'LS, lib64stdc++6-4.5-dbg`'LS, lib64stdc++6-4.6-dbg`'LS,
+ lib64stdc++6-4.7-dbg`'LS, lib64stdc++6-4.8-dbg`'LS, lib64stdc++6-4.9-dbg`'LS,
+ lib64stdc++6-5-dbg`'LS
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libn32stdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,n32),
+ libdep(stdc++CXX_SO,n32), libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libn32stdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(stdc++CXX_SO,n32),
+ libdevdep(stdc++`'PV-dev,), libdbgdep(gcc`'GCC_SO-dbg,n32,>=,${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libn32stdc++CXX_SO-dbg-TARGET-dcv1
+',`')`'dnl
+Conflicts: libn32stdc++6-dbg`'LS, libn32stdc++6-4.0-dbg`'LS,
+ libn32stdc++6-4.1-dbg`'LS, libn32stdc++6-4.2-dbg`'LS, libn32stdc++6-4.3-dbg`'LS,
+ libn32stdc++6-4.4-dbg`'LS, libn32stdc++6-4.5-dbg`'LS, libn32stdc++6-4.6-dbg`'LS,
+ libn32stdc++6-4.7-dbg`'LS, libn32stdc++6-4.8-dbg`'LS, libn32stdc++6-4.9-dbg`'LS,
+ libn32stdc++6-5-dbg`'LS
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+ifenabled(`x32dev',`
+Package: libx32stdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,x32), libdep(stdc++CXX_SO,x32),
+ libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl x32dev
+
+ifenabled(`libx32dbgcxx',`
+Package: libx32stdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(stdc++CXX_SO,x32),
+ libdevdep(stdc++`'PV-dev,), libdbgdep(gcc`'GCC_SO-dbg,x32,>=,${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libx32stdc++CXX_SO-dbg-TARGET-dcv1
+',`')`'dnl
+Conflicts: libx32stdc++6-dbg`'LS, libx32stdc++6-4.6-dbg`'LS,
+ libx32stdc++6-4.7-dbg`'LS, libx32stdc++6-4.8-dbg`'LS, libx32stdc++6-4.9-dbg`'LS,
+ libx32stdc++6-5-dbg`'LS
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libx32dbgcxx
+
+ifenabled(`libhfdbgcxx',`
+Package: libhfstdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,hf),
+ libdep(stdc++CXX_SO,hf), libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libhfstdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(stdc++CXX_SO,hf),
+ libdevdep(stdc++`'PV-dev,), libdbgdep(gcc`'GCC_SO-dbg,hf,>=,${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libhfstdc++CXX_SO-dbg-TARGET-dcv1
+',`')`'dnl
+ifdef(`TARGET',`dnl',`Conflicts: libhfstdc++6-dbg`'LS, libhfstdc++6-4.3-dbg`'LS, libhfstdc++6-4.4-dbg`'LS, libhfstdc++6-4.5-dbg`'LS, libhfstdc++6-4.6-dbg`'LS, libhfstdc++6-4.7-dbg`'LS, libhfstdc++6-4.8-dbg`'LS, libhfstdc++6-4.9-dbg`'LS, libhfstdc++6-5-dbg`'LS, libstdc++'CXX_SO`-armhf [biarchhf_archs]')
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libhfdbgcxx
+
+ifenabled(`libsfdbgcxx',`
+Package: libsfstdc++`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: ifdef(`TARGET',`devel',`libdevel')
+Priority: optional
+Depends: BASELDEP, libdevdep(gcc`'PV-dev,sf),
+ libdep(stdc++CXX_SO,sf), libdevdep(stdc++`'PV-dev,), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (development files)`'ifdef(`TARGET',` (TARGET)', `')
+ This package contains the headers and static library files necessary for
+ building C++ programs which use libstdc++.
+ .
+ libstdc++-v3 is a complete rewrite from the previous libstdc++-v2, which
+ was included up to g++-2.95. The first version of libstdc++-v3 appeared
+ in g++-3.0.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+
+Package: libsfstdc++CXX_SO`'PV-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: debug
+Priority: optional
+Depends: BASELDEP, libdep(stdc++CXX_SO,sf),
+ libdevdep(stdc++`'PV-dev,), libdbgdep(gcc`'GCC_SO-dbg,sf,>=,${gcc:EpochVersion}),
+ ${shlibs:Depends}, ${misc:Depends}
+ifdef(`TARGET',`Provides: libsfstdc++CXX_SO-dbg-TARGET-dcv1
+',`')`'dnl
+ifdef(`TARGET',`dnl',`Conflicts: libsfstdc++6-dbg`'LS, libsfstdc++6-4.3-dbg`'LS, libsfstdc++6-4.4-dbg`'LS, libsfstdc++6-4.5-dbg`'LS, libsfstdc++6-4.6-dbg`'LS, libsfstdc++6-4.7-dbg`'LS, libsfstdc++6-4.8-dbg`'LS, libsfstdc++6-4.9-dbg`'LS, libsfstdc++6-5-dbg`'LS, libstdc++'CXX_SO`-armel [biarchsf_archs]')
+BUILT_USING`'dnl
+Description: GNU Standard C++ Library v3 (debugging files)`'ifdef(`TARGET)',` (TARGET)', `')
+ This package contains the shared library of libstdc++ compiled with
+ debugging symbols.
+ifdef(`TARGET', `dnl
+ .
+ This package contains files for TARGET architecture, for use in cross-compile
+ environment.
+')`'dnl
+')`'dnl libsfdbgcxx
+
+ifdef(`TARGET', `', `
+Package: libstdc++`'PV-doc
+Architecture: all
+Section: doc
+Priority: PRI(optional)
+Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), ${misc:Depends}
+Conflicts: libstdc++5-doc, libstdc++5-3.3-doc, libstdc++6-doc,
+ libstdc++6-4.0-doc, libstdc++6-4.1-doc, libstdc++6-4.2-doc, libstdc++6-4.3-doc,
+ libstdc++6-4.4-doc, libstdc++6-4.5-doc, libstdc++6-4.6-doc, libstdc++6-4.7-doc,
+ libstdc++-4.8-doc, libstdc++-4.9-doc, libstdc++-5-doc
+Description: GNU Standard C++ Library v3 (documentation files)
+ This package contains documentation files for the GNU stdc++ library.
+ .
+ One set is the distribution documentation, the other set is the
+ source documentation including a namespace list, class hierarchy,
+ alphabetical list, compound list, file list, namespace members,
+ compound members and file members.
+')`'dnl native
+')`'dnl c++dev
+')`'dnl c++
+
+ifenabled(`ada',`
+Package: gnat`'-GNAT_V`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: optional
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Depends: BASEDEP, gcc`'PV`'TS (>= ${gcc:SoftVersion}), ${dep:libgnat}, ${dep:libcdev}, ${shlibs:Depends}, ${misc:Depends}
+Suggests: gnat`'PV-doc, ada-reference-manual-2012, gnat`'-GNAT_V-sjlj
+Breaks:   gnat (<< 4.6.1), dh-ada-library (<< 6.0), gnat-4.6-base (= 4.6.4-2),
+ gnat-4.9-base (= 4.9-20140330-1)
+Replaces: gnat (<< 4.6.1), dh-ada-library (<< 6.0), gnat-4.6-base (= 4.6.4-2),
+ gnat-4.9-base (= 4.9-20140330-1)
+# Takes over symlink from gnat (<< 4.6.1): /usr/bin/gnatgcc.
+# Takes over file from dh-ada-library (<< 6.0): debian_packaging.mk.
+# g-base 4.6.4-2, 4.9-20140330-1 contain debian_packaging.mk by mistake.
+# Newer versions of gnat and dh-ada-library will not provide these files.
+Conflicts: gnat (<< 4.1), gnat-3.1, gnat-3.2, gnat-3.3, gnat-3.4, gnat-3.5,
+ gnat-4.0, gnat-4.1, gnat-4.2, gnat-4.3, gnat-4.4, gnat-4.6, gnat-4.7, gnat-4.8,
+ gnat-4.9, gnat-5`'TS
+# These other packages will continue to provide /usr/bin/gnatmake and
+# other files.
+BUILT_USING`'dnl
+Description: GNU Ada compiler
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ This package provides the compiler, tools and runtime library that handles
+ exceptions using the default zero-cost mechanism.
+
+ifenabled(`adasjlj',`
+Package: gnat`'-GNAT_V-sjlj`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: optional
+ifdef(`MULTIARCH', `Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Depends: BASEDEP, gnat`'-GNAT_V`'TS (= ${gnat:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Ada compiler (setjump/longjump runtime library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ This package provides an alternative runtime library that handles
+ exceptions using the setjump/longjump mechanism (as a static library
+ only).  You can install it to supplement the normal compiler.
+')`'dnl adasjlj
+
+ifenabled(`libgnat',`
+Package: libgnat`'-GNAT_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: runtime for applications compiled with GNAT (shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the runtime shared library.
+
+Package: libgnat`'-GNAT_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Depends: BASELDEP, libgnat`'-GNAT_V`'LS (= ${gnat:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: runtime for applications compiled with GNAT (debugging symbols)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the debugging symbols.
+
+Package: libgnatvsn`'GNAT_V-dev`'LS
+Section: libdevel
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Priority: optional
+Depends: BASELDEP, ifdef(`TARGET',`',`gnat`'PV`'TS (ifdef(`TARGET',`>= ${gnat:SoftVersion}',`= ${gnat:Version}')),')
+ libgnatvsn`'GNAT_V`'LS (= ${gnat:Version}), ${misc:Depends}
+ifdef(`TARGET',`Recommends: gnat`'PV`'TS (>= ${gnat:SoftVersion})
+')`'dnl
+Conflicts: libgnatvsn-dev (<< `'GNAT_V),
+ libgnatvsn4.1-dev, libgnatvsn4.3-dev, libgnatvsn4.4-dev,
+ libgnatvsn4.5-dev, libgnatvsn4.6-dev, libgnatvsn4.9-dev,
+ libgnatvsn5-dev`'LS,
+BUILT_USING`'dnl
+Description: GNU Ada compiler selected components (development files)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnatvsn library exports selected GNAT components for use in other
+ packages, most notably ASIS tools. It is licensed under the GNAT-Modified
+ GPL, allowing to link proprietary programs with it.
+ .
+ This package contains the development files and static library.
+
+Package: libgnatvsn`'GNAT_V`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Section: ifdef(`TARGET',`devel',`libs')
+Depends: BASELDEP, libgnat`'-GNAT_V`'LS (= ${gnat:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Ada compiler selected components (shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnatvsn library exports selected GNAT components for use in other
+ packages, most notably ASIS tools. It is licensed under the GNAT-Modified
+ GPL, allowing to link proprietary programs with it.
+ .
+ This package contains the runtime shared library.
+
+Package: libgnatvsn`'GNAT_V-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Section: debug
+Depends: BASELDEP, libgnatvsn`'GNAT_V`'LS (= ${gnat:Version}), ${misc:Depends}
+Suggests: gnat
+BUILT_USING`'dnl
+Description: GNU Ada compiler selected components (debugging symbols)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnatvsn library exports selected GNAT components for use in other
+ packages, most notably ASIS tools. It is licensed under the GNAT-Modified
+ GPL, allowing to link proprietary programs with it.
+ .
+ This package contains the debugging symbols.
+
+Package: libgnatprj`'GNAT_V-dev`'LS
+Section: libdevel
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+Priority: optional
+Depends: BASELDEP, ifdef(`TARGET',`',`gnat`'PV`'TS (ifdef(`TARGET',`>= ${gnat:SoftVersion}',`= ${gnat:Version}')),')
+ libgnatprj`'GNAT_V`'LS (= ${gnat:Version}),
+ libgnatvsn`'GNAT_V-dev`'LS (= ${gnat:Version}), ${misc:Depends}
+ifdef(`TARGET',`Recommends: gnat`'PV`'TS (>= ${gnat:SoftVersion})
+')`'dnl
+Conflicts: libgnatprj-dev (<< `'GNAT_V),
+ libgnatprj4.1-dev, libgnatprj4.3-dev, libgnatprj4.4-dev,
+ libgnatprj4.5-dev, libgnatprj4.6-dev, libgnatprj4.9-dev,
+ libgnatprj5-dev`'LS,
+BUILT_USING`'dnl
+Description: GNU Ada compiler Project Manager (development files)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ GNAT uses project files to organise source and object files in large-scale
+ development efforts. The libgnatprj library exports GNAT project files
+ management for use in other packages, most notably ASIS tools (package
+ asis-programs) and GNAT Programming Studio (package gnat-gps). It is
+ licensed under the pure GPL; all programs that use it must also be
+ distributed under the GPL, or not distributed at all.
+ .
+ This package contains the development files and static library.
+
+Package: libgnatprj`'GNAT_V`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Section: ifdef(`TARGET',`devel',`libs')
+Depends: BASELDEP, libgnat`'-GNAT_V`'LS (= ${gnat:Version}),
+ libgnatvsn`'GNAT_V`'LS (= ${gnat:Version}),
+ ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU Ada compiler Project Manager (shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ GNAT uses project files to organise source and object files in large-scale
+ development efforts. The libgnatprj library exports GNAT project files
+ management for use in other packages, most notably ASIS tools (package
+ asis-programs) and GNAT Programming Studio (package gnat-gps). It is
+ licensed under the pure GPL; all programs that use it must also be
+ distributed under the GPL, or not distributed at all.
+ .
+ This package contains the runtime shared library.
+
+Package: libgnatprj`'GNAT_V-dbg`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`any')
+ifdef(`MULTIARCH', `Multi-Arch: same
+Pre-Depends: ${misc:Pre-Depends}
+')`'dnl
+Priority: optional
+Section: debug
+Depends: BASELDEP, libgnatprj`'GNAT_V`'LS (= ${gnat:Version}), ${misc:Depends}
+Suggests: gnat
+BUILT_USING`'dnl
+Description: GNU Ada compiler Project Manager (debugging symbols)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ GNAT uses project files to organise source and object files in large-scale
+ development efforts. The libgnatprj library exports GNAT project files
+ management for use in other packages, most notably ASIS tools (package
+ asis-programs) and GNAT Programming Studio (package gnat-gps). It is
+ licensed under the pure GPL; all programs that use it must also be
+ distributed under the GPL, or not distributed at all.
+ .
+ This package contains the debugging symbols.
+')`'dnl libgnat
+
+ifenabled(`lib64gnat',`
+Package: lib64gnat`'-GNAT_V
+Section: libs
+Architecture: biarch64_archs
+Priority: PRI(optional)
+Depends: BASELDEP, ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: runtime for applications compiled with GNAT (64 bits shared library)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the runtime shared library for 64 bits architectures.
+')`'dnl libgnat
+
+ifenabled(`gfdldoc',`
+Package: gnat`'PV-doc
+Architecture: all
+Section: doc
+Priority: PRI(optional)
+Depends: dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Suggests: gnat`'PV
+Conflicts: gnat-4.1-doc, gnat-4.2-doc,
+  gnat-4.3-doc, gnat-4.4-doc,
+  gnat-4.6-doc, gnat-4.9-doc,
+  gnat-5-doc,
+BUILT_USING`'dnl
+Description: GNU Ada compiler (documentation)
+ GNAT is a compiler for the Ada programming language. It produces optimized
+ code on platforms supported by the GNU Compiler Collection (GCC).
+ .
+ The libgnat library provides runtime components needed by most
+ applications produced with GNAT.
+ .
+ This package contains the documentation in info `format'.
+')`'dnl gfdldoc
+')`'dnl ada
+
+ifenabled(`d ',`
+Package: gdc`'PV`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: optional
+Depends: SOFTBASEDEP, g++`'PV`'TS (>= ${gcc:SoftVersion}), ${dep:gdccross}, ${dep:phobosdev}, ${shlibs:Depends}, ${misc:Depends}
+Provides: gdc, d-compiler, d-v2-compiler
+Replaces: gdc (<< 4.4.6-5)
+BUILT_USING`'dnl
+Description: GNU D compiler (version 2)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU D compiler, which compiles D on platforms supported by gcc.
+ It uses the gcc backend to generate optimised code.
+ .
+ This compiler supports D language version 2.
+
+ifenabled(`multilib',`
+Package: gdc`'PV-multilib`'TS
+Architecture: any
+ifdef(`TARGET',`Multi-Arch: foreign
+')dnl
+Priority: optional
+Depends: SOFTBASEDEP, gdc`'PV`'TS (= ${gcc:Version}), gcc`'PV-multilib`'TS (= ${gcc:Version}), ${dep:libphobosbiarchdev}${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: GNU D compiler (version 2, multilib support)`'ifdef(`TARGET)',` (cross compiler for TARGET architecture)', `')
+ This is the GNU D compiler, which compiles D on platforms supported by gcc.
+ It uses the gcc backend to generate optimised code.
+ .
+ This is a dependency package, depending on development packages
+ for the non-default multilib architecture(s).
+')`'dnl multilib
+
+ifenabled(`libphobos',`
+Package: libgphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`libphobos_archs')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libgphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  zlib1g-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libphobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libgphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`libphobos_archs')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libgphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`libphobos_archs')
+ifdef(`MULTIARCH', `Multi-Arch: same
+')`'dnl
+Priority: optional
+Depends: BASELDEP, libgphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib64gphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, lib64gphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  libdevdep(gcc`'PV-dev,64), lib64z1-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib64phobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library (64bit development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib64gphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib64gphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch64_archs')
+Priority: optional
+Depends: BASELDEP, lib64gphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib32gphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, lib32gphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  libdevdep(gcc`'PV-dev,32), lib32z1-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: lib32phobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library (32bit development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib32gphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: lib32gphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarch32_archs')
+Priority: optional
+Depends: BASELDEP, lib32gphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+ifenabled(`libn32phobos',`
+Package: libn32gphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libn32gphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  libdevdep(gcc`'PV-dev,n32), libn32z1-dev, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libn32phobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library (n32 development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libn32gphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libn32gphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchn32_archs')
+Priority: optional
+Depends: BASELDEP, libn32gphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+')`'dnl libn32phobos
+
+ifenabled(`libx32phobos',`
+Package: libx32gphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libx32gphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  libdevdep(gcc`'PV-dev,x32), ${dep:libx32z}, ${shlibs:Depends}, ${misc:Depends}
+Replaces: libx32gphobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library (x32 development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libx32gphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libx32gphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchx32_archs')
+Priority: optional
+Depends: BASELDEP, libx32gphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+')`'dnl libx32phobos
+
+ifenabled(`armml',`
+Package: libhfgphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libhfgphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  libdevdep(gcc`'PV-dev,hf), ${shlibs:Depends}, ${misc:Depends}
+Replaces: libhfphobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library (hard float ABI development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libhfgphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libhfgphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchhf_archs')
+Priority: optional
+Depends: BASELDEP, libhfgphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libsfgphobos`'PV-dev`'LS
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Section: libdevel
+Priority: optional
+Depends: BASELDEP, libsfgphobos`'PHOBOS_V`'LS (>= ${gdc:Version}),
+  libdevdep(gcc`'PV-dev,sf), ${shlibs:Depends}, ${misc:Depends}
+Replaces: libsfphobos`'PV-dev`'LS
+BUILT_USING`'dnl
+Description: Phobos D standard library (soft float ABI development files)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libsfgphobos`'PHOBOS_V`'LS
+Section: ifdef(`TARGET',`devel',`libs')
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (runtime library)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+
+Package: libsfgphobos`'PHOBOS_V-dbg`'LS
+Section: debug
+Architecture: ifdef(`TARGET',`CROSS_ARCH',`biarchsf_archs')
+Priority: optional
+Depends: BASELDEP, libsfgphobos`'PHOBOS_V`'LS (= ${gdc:Version}), ${misc:Depends}
+BUILT_USING`'dnl
+Description: Phobos D standard library (debug symbols)
+ This is the Phobos standard library that comes with the D2 compiler.
+ .
+ For more information check http://www.dlang.org/phobos/
+')`'dnl armml
+')`'dnl libphobos
+')`'dnl d
+
+ifdef(`TARGET',`',`dnl
+ifenabled(`libs',`
+#Package: gcc`'PV-soft-float
+#Architecture: arm armel armhf
+#Priority: PRI(optional)
+#Depends: BASEDEP, depifenabled(`cdev',`gcc`'PV (= ${gcc:Version}),') ${shlibs:Depends}, ${misc:Depends}
+#Conflicts: gcc-4.4-soft-float, gcc-4.5-soft-float, gcc-4.6-soft-float
+#BUILT_USING`'dnl
+#Description: GCC soft-floating-point gcc libraries (ARM)
+# These are versions of basic static libraries such as libgcc.a compiled
+# with the -msoft-float option, for CPUs without a floating-point unit.
+')`'dnl commonlibs
+')`'dnl
+
+ifenabled(`fixincl',`
+Package: fixincludes
+Architecture: any
+Priority: PRI(optional)
+Depends: BASEDEP, gcc`'PV (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends}
+BUILT_USING`'dnl
+Description: Fix non-ANSI header files
+ FixIncludes was created to fix non-ANSI system header files. Many
+ system manufacturers supply proprietary headers that are not ANSI compliant.
+ The GNU compilers cannot compile non-ANSI headers. Consequently, the
+ FixIncludes shell script was written to fix the header files.
+ .
+ Not all packages with header files are installed on the system, when the
+ package is built, so we make fixincludes available at build time of other
+ packages, such that checking tools like lintian can make use of it.
+')`'dnl fixincl
+
+ifenabled(`cdev',`
+ifdef(`TARGET', `', `
+ifenabled(`gfdldoc',`
+Package: gcc`'PV-doc
+Architecture: all
+Section: doc
+Priority: PRI(optional)
+Depends: gcc`'PV-base (>= ${gcc:SoftVersion}), dpkg (>= 1.15.4) | install-info, ${misc:Depends}
+Conflicts: gcc-docs (<< 2.95.2)
+Replaces: gcc (<=2.7.2.3-4.3), gcc-docs (<< 2.95.2)
+Description: Documentation for the GNU compilers (gcc, gobjc, g++)
+ Documentation for the GNU compilers in info `format'.
+')`'dnl gfdldoc
+')`'dnl native
+')`'dnl cdev
+
+ifdef(`TARGET',`',`dnl
+ifenabled(`libnof',`
+#Package: gcc`'PV-nof
+#Architecture: powerpc
+#Priority: PRI(optional)
+#Depends: BASEDEP, ${shlibs:Depends}ifenabled(`cdev',`, gcc`'PV (= ${gcc:Version})'), ${misc:Depends}
+#Conflicts: gcc-3.2-nof
+#BUILT_USING`'dnl
+#Description: GCC no-floating-point gcc libraries (powerpc)
+# These are versions of basic static libraries such as libgcc.a compiled
+# with the -msoft-float option, for CPUs without a floating-point unit.
+')`'dnl libnof
+')`'dnl
+
+ifenabled(`source',`
+Package: gcc`'PV-source
+Architecture: all
+Priority: PRI(optional)
+Depends: make, autoconf2.64, quilt, patchutils, sharutils, gawk, ${misc:Depends}
+Description: Source of the GNU Compiler Collection
+ This package contains the sources and patches which are needed to
+ build the GNU Compiler Collection (GCC).
+')`'dnl source
+dnl
+')`'dnl gcc-X.Y
+dnl last line in file
--- gcc-6-6.4.0.orig/debian/copyright
+++ gcc-6-6.4.0/debian/copyright
@@ -0,0 +1,666 @@
+This is the Debian GNU/Linux prepackaged version of the GNU compiler
+collection, containing Ada, C, C++, Fortran 95, Java, Objective-C,
+Objective-C++, and Treelang compilers, documentation, and support
+libraries.  In addition, Debian provides the gdc compiler, either in
+the same source package, or built from a separate same source package.
+Packaging is done by the Debian GCC Maintainers
+<debian-gcc@lists.debian.org>, with sources obtained from:
+
+  ftp://gcc.gnu.org/pub/gcc/releases/  (for full releases)
+  svn://gcc.gnu.org/svn/gcc/           (for prereleases)
+  http://bitbucket.org/goshawk/gdc     (for D)
+
+The current gcc-6 source package is taken from the SVN gcc-6-branch.
+
+Changes: See changelog.Debian.gz
+
+Debian splits the GNU Compiler Collection into packages for each language,
+library, and documentation as follows:
+
+Language       Compiler package  Library package    Documentation
+---------------------------------------------------------------------------
+Ada            gnat-6          libgnat-6        gnat-6-doc
+C              gcc-6                              gcc-6-doc
+C++            g++-6           libstdc++6         libstdc++6-6-doc
+D              gdc-6
+Fortran 95     gfortran-6      libgfortran3       gfortran-6-doc
+Go             gccgo-6         libgo0
+Java           gcj-6           libgcj10           libgcj-doc
+Objective C    gobjc-6         libobjc2
+Objective C++  gobjc++-6
+
+For some language run-time libraries, Debian provides source files,
+development files, debugging symbols and libraries containing position-
+independent code in separate packages:
+
+Language  Sources      Development   Debugging            Position-Independent
+------------------------------------------------------------------------------
+C++                                  libstdc++6-6-dbg  libstdc++6-6-pic
+D         libphobos-6-dev
+Java      libgcj10-src libgcj10-dev  libgcj10-dbg
+
+Additional packages include:
+
+All languages:
+libgcc1, libgcc2, libgcc4       GCC intrinsics (platform-dependent)
+gcc-6-base                    Base files common to all compilers
+gcc-6-soft-float              Software floating point (ARM only)
+gcc-6-source                  The sources with patches
+
+Ada:
+libgnatvsn-dev, libgnatvsn6   GNAT version library
+libgnatprj-dev, libgnatprj6   GNAT Project Manager library
+
+C:
+cpp-6, cpp-6-doc            GNU C Preprocessor
+libssp0-dev, libssp0            GCC stack smashing protection library
+libquadmath0                    Math routines for the __float128 type
+fixincludes                     Fix non-ANSI header files
+
+Java:
+gij                             The Java bytecode interpreter and VM
+libgcj-common                   Common files for the Java run-time
+libgcj10-awt                    The Abstract Windowing Toolkit
+libgcj10-jar                    Java ARchive for the Java run-time
+
+C, C++ and Fortran 95:
+libgomp1-dev, libgomp1		GCC OpenMP (GOMP) support library
+libitm1-dev, libitm1		GNU Transactional Memory Library
+
+Biarch support: On some 64-bit platforms which can also run 32-bit code,
+Debian provides additional packages containing 32-bit versions of some
+libraries.  These packages have names beginning with 'lib32' instead of
+'lib', for example lib32stdc++6.  Similarly, on some 32-bit platforms which
+can also run 64-bit code, Debian provides additional packages with names
+beginning with 'lib64' instead of 'lib'.  These packages contain 64-bit
+versions of the libraries.  (At this time, not all platforms and not all
+libraries support biarch.)  The license terms for these lib32 or lib64
+packages are identical to the ones for the lib packages.
+
+
+COPYRIGHT STATEMENTS AND LICENSING TERMS
+
+
+GCC is Copyright (C) 1986, 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994,
+1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
+2008, 2009, 2010, 2011, 2012, 2013, 2014 Free Software Foundation, Inc.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Files that have exception clauses are licensed under the terms of the
+GNU General Public License; either version 3, or (at your option) any
+later version.
+
+On Debian GNU/Linux systems, the complete text of the GNU General
+Public License is in `/usr/share/common-licenses/GPL', version 3 of this
+license in `/usr/share/common-licenses/GPL-3'.
+
+The following runtime libraries are licensed under the terms of the
+GNU General Public License (v3 or later) with version 3.1 of the GCC
+Runtime Library Exception (included in this file):
+
+ - libgcc (libgcc/, gcc/libgcc2.[ch], gcc/unwind*, gcc/gthr*,
+   gcc/coretypes.h, gcc/crtstuff.c, gcc/defaults.h, gcc/dwarf2.h,
+   gcc/emults.c, gcc/gbl-ctors.h, gcc/gcov-io.h, gcc/libgcov.c,
+   gcc/tsystem.h, gcc/typeclass.h).
+ - libatomic
+ - libdecnumber
+ - libgomp
+ - libitm
+ - libssp
+ - libstdc++-v3
+ - libobjc
+ - libgfortran
+ - The libgnat-6 Ada support library and libgnatvsn library.
+ - Various config files in gcc/config/ used in runtime libraries.
+ - libvtv
+
+In contrast, libgnatprj is licensed under the terms of the pure GNU
+General Public License.
+
+The libbacktrace library is licensed under the following terms:
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+    (1) Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer. 
+
+    (2) Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in
+    the documentation and/or other materials provided with the
+    distribution.  
+    
+    (3) The name of the author may not be used to
+    endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+
+The libsanitizer libraries (libasan, liblsan, libtsan, libubsan) are
+licensed under the following terms:
+
+Copyright (c) 2009-2014 by the LLVM contributors.
+
+All rights reserved.
+
+Developed by:
+
+    LLVM Team
+
+    University of Illinois at Urbana-Champaign
+
+    http://llvm.org
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal with
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimers.
+
+    * Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimers in the
+      documentation and/or other materials provided with the distribution.
+
+    * Neither the names of the LLVM Team, University of Illinois at
+      Urbana-Champaign, nor the names of its contributors may be used to
+      endorse or promote products derived from this Software without specific
+      prior written permission.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+SOFTWARE.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+
+The libgcj library is licensed under the terms of the GNU General
+Public License, with a special exception:
+
+    Linking this library statically or dynamically with other modules
+    is making a combined work based on this library.  Thus, the terms
+    and conditions of the GNU General Public License cover the whole
+    combination.
+
+    As a special exception, the copyright holders of this library give
+    you permission to link this library with independent modules to
+    produce an executable, regardless of the license terms of these
+    independent modules, and to copy and distribute the resulting
+    executable under terms of your choice, provided that you also
+    meet, for each linked independent module, the terms and conditions
+    of the license of that module.  An independent module is a module
+    which is not derived from or based on this library.  If you modify
+    this library, you may extend this exception to your version of the
+    library, but you are not obligated to do so.  If you do not wish
+    to do so, delete this exception statement from your version.
+
+The libffi library is licensed under the following terms:
+
+    libffi - Copyright (c) 1996-2003  Red Hat, Inc.
+
+    Permission is hereby granted, free of charge, to any person obtaining
+    a copy of this software and associated documentation files (the
+    ``Software''), to deal in the Software without restriction, including
+    without limitation the rights to use, copy, modify, merge, publish,
+    distribute, sublicense, and/or sell copies of the Software, and to
+    permit persons to whom the Software is furnished to do so, subject to
+    the following conditions:
+
+    The above copyright notice and this permission notice shall be included
+    in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
+    OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+    IN NO EVENT SHALL CYGNUS SOLUTIONS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+    OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+    ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+    OTHER DEALINGS IN THE SOFTWARE.
+
+
+The documentation is licensed under the GNU Free Documentation License (v1.2).
+On Debian GNU/Linux systems, the complete text of this license is in
+`/usr/share/common-licenses/GFDL-1.2'.
+
+
+GCC RUNTIME LIBRARY EXCEPTION
+
+Version 3.1, 31 March 2009
+
+Copyright (C) 2009 Free Software Foundation, Inc. <http://fsf.org/>
+
+Everyone is permitted to copy and distribute verbatim copies of this
+license document, but changing it is not allowed.
+
+This GCC Runtime Library Exception ("Exception") is an additional
+permission under section 7 of the GNU General Public License, version
+3 ("GPLv3"). It applies to a given file (the "Runtime Library") that
+bears a notice placed by the copyright holder of the file stating that
+the file is governed by GPLv3 along with this Exception.
+
+When you use GCC to compile a program, GCC may combine portions of
+certain GCC header files and runtime libraries with the compiled
+program. The purpose of this Exception is to allow compilation of
+non-GPL (including proprietary) programs to use, in this way, the
+header files and runtime libraries covered by this Exception.
+
+0. Definitions.
+
+A file is an "Independent Module" if it either requires the Runtime
+Library for execution after a Compilation Process, or makes use of an
+interface provided by the Runtime Library, but is not otherwise based
+on the Runtime Library.
+
+"GCC" means a version of the GNU Compiler Collection, with or without
+modifications, governed by version 3 (or a specified later version) of
+the GNU General Public License (GPL) with the option of using any
+subsequent versions published by the FSF.
+
+"GPL-compatible Software" is software whose conditions of propagation,
+modification and use would permit combination with GCC in accord with
+the license of GCC.
+
+"Target Code" refers to output from any compiler for a real or virtual
+target processor architecture, in executable form or suitable for
+input to an assembler, loader, linker and/or execution
+phase. Notwithstanding that, Target Code does not include data in any
+format that is used as a compiler intermediate representation, or used
+for producing a compiler intermediate representation.
+
+The "Compilation Process" transforms code entirely represented in
+non-intermediate languages designed for human-written code, and/or in
+Java Virtual Machine byte code, into Target Code. Thus, for example,
+use of source code generators and preprocessors need not be considered
+part of the Compilation Process, since the Compilation Process can be
+understood as starting with the output of the generators or
+preprocessors.
+
+A Compilation Process is "Eligible" if it is done using GCC, alone or
+with other GPL-compatible software, or if it is done without using any
+work based on GCC. For example, using non-GPL-compatible Software to
+optimize any GCC intermediate representations would not qualify as an
+Eligible Compilation Process.
+
+1. Grant of Additional Permission.
+
+You have permission to propagate a work of Target Code formed by
+combining the Runtime Library with Independent Modules, even if such
+propagation would otherwise violate the terms of GPLv3, provided that
+all Target Code was generated by Eligible Compilation Processes. You
+may then convey such a combination under terms of your choice,
+consistent with the licensing of the Independent Modules.
+
+2. No Weakening of GCC Copyleft.
+
+The availability of this Exception does not imply any general
+presumption that third-party software is unaffected by the copyleft
+requirements of the license of GCC.
+
+
+libquadmath/*.[hc]:
+
+   Copyright (C) 2010 Free Software Foundation, Inc.
+   Written by Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+   Written by Tobias Burnus  <burnus@net-b.de>
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+Library General Public License for more details.
+
+libquadmath/math:
+
+atanq.c, expm1q.c, j0q.c, j1q.c, log1pq.c, logq.c:
+    Copyright 2001 by Stephen L. Moshier <moshier@na-net.ornl.gov> 
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+coshq.c, erfq.c, jnq.c, lgammaq.c, powq.c, roundq.c:
+   Changes for 128-bit __float128 are
+   Copyright (C) 2001 Stephen L. Moshier <moshier@na-net.ornl.gov>
+   and are incorporated herein by permission of the author.  The author 
+   reserves the right to distribute this material elsewhere under different
+   copying permissions.  These modifications are distributed here under 
+   the following terms:
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+ldexpq.c:
+   * Conversion to long double by Ulrich Drepper,
+   * Cygnus Support, drepper@cygnus.com.
+
+cosq_kernel.c, expq.c, sincos_table.c, sincosq.c, sincosq_kernel.c,
+sinq_kernel.c, truncq.c:
+   Copyright (C) 1997, 1999 Free Software Foundation, Inc.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+isinfq.c:
+ * Written by J.T. Conklin <jtc@netbsd.org>.
+ * Change for long double by Jakub Jelinek <jj@ultra.linux.cz>
+ * Public domain.
+
+llroundq.c, lroundq.c, tgammaq.c:
+   Copyright (C) 1997, 1999, 2002, 2004 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997 and
+                  Jakub Jelinek <jj@ultra.linux.cz>, 1999.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+log10q.c:
+   Cephes Math Library Release 2.2:  January, 1991
+   Copyright 1984, 1991 by Stephen L. Moshier
+   Adapted for glibc November, 2001
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+remaining files:
+
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+
+
+libjava/classpath/resource/gnu/java/locale/*
+
+They are copyrighted and covered by the terms of use:
+http://www.unicode.org/copyright.html
+
+EXHIBIT 1
+UNICODE, INC. LICENSE AGREEMENT - DATA FILES AND SOFTWARE
+
+ Unicode Data Files include all data files under the directories 
+http://www.unicode.org/Public/ and http://www.unicode.org/reports/. 
+Unicode Software includes any source code published in the Unicode Standard or 
+under the directories http://www.unicode.org/Public/ and 
+http://www.unicode.org/reports/.
+
+NOTICE TO USER: Carefully read the following legal agreement. BY DOWNLOADING, 
+INSTALLING, COPYING OR OTHERWISE USING UNICODE INC.'S DATA FILES ("DATA FILES"), 
+AND/OR SOFTWARE ("SOFTWARE"), YOU UNEQUIVOCALLY ACCEPT, AND AGREE TO BE BOUND BY, 
+ALL OF THE TERMS AND CONDITIONS OF THIS AGREEMENT. IF YOU DO NOT AGREE, 
+DO NOT DOWNLOAD, INSTALL, COPY, DISTRIBUTE OR USE THE DATA FILES OR SOFTWARE.
+
+	    COPYRIGHT AND PERMISSION NOTICE
+
+Copyrigh (c) 1991-2011 Unicode, Inc. All rights reserved. 
+Distributed under the Terms of Use in http://www.unicode.org/copyright.html.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy 
+of the Unicode data files and any associated documentation (the "Data Files") 
+or Unicode software and any associated documentation (the "Software") to deal 
+in the Data Files or Software without restriction, including without limitation 
+the rights to use, copy, modify, merge, publish, distribute, and/or sell copies
+ of the Data Files or Software, and to permit persons to whom the Data Files 
+or Software are furnished to do so, provided that (a) the above copyright notice(s) 
+and this permission notice appear with all copies of the Data Files or Software, 
+(b) both the above copyright notice(s) and this permission notice appear 
+in associated documentation, and (c) there is clear notice in each modified 
+Data File or in the Software as well as in the documentation associated with 
+the Data File(s) or Software that the data or software has been modified.
+
+THE DATA FILES AND SOFTWARE ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR HOLDERS INCLUDED IN THIS NOTICE BE LIABLE
+ FOR ANY CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES 
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF 
+CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 
+WITH THE USE OR PERFORMANCE OF THE DATA FILES OR SOFTWARE.
+
+Except as contained in this notice, the name of a copyright holder shall not be used
+ in advertising or otherwise to promote the sale, use or other dealings in these 
+Data Files or Software without prior written authorization of the copyright holder.
+
+Unicode and the Unicode logo are trademarks of Unicode, Inc., and may be registered
+ in some jurisdictions. All other trademarks and registered trademarks mentioned 
+herein are the property of their respective owners.
+
+
+gcc/go/gofrontend, libgo:
+
+Copyright (c) 2009 The Go Authors. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+   * Redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above
+copyright notice, this list of conditions and the following disclaimer
+in the documentation and/or other materials provided with the
+distribution.
+   * Neither the name of Google Inc. nor the names of its
+contributors may be used to endorse or promote products derived from
+this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+libcilkrts, libmpx:
+ Copyright (C) 2009-2014, Intel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+   * Neither the name of Intel Corporation nor the names of its
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
+ WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
+
+D:
+gdc-6                         GNU D Compiler
+libphobos-6-dev               D standard runtime library
+
+The D source package is made up of the following components.
+
+The D front-end for GCC:
+ - d/*
+
+Copyright (C) 2004-2007 David Friedman
+Modified by Vincenzo Ampolo, Michael Parrot, Iain Buclaw, (C) 2009, 2010
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+On Debian GNU/Linux systems, the complete text of the GNU General
+Public License is in `/usr/share/common-licenses/GPL', version 2 of this
+license in `/usr/share/common-licenses/GPL-2'.
+
+
+The DMD Compiler implementation of the D programming language:
+ - d/dmd/*
+
+Copyright (c) 1999-2010 by Digital Mars
+All Rights Reserved
+written by Walter Bright
+http://www.digitalmars.com
+License for redistribution is by either the Artistic License or
+the GNU General Public License (v1).
+
+On Debian GNU/Linux systems, the complete text of the GNU General
+Public License is in `/usr/share/common-licenses/GPL', the Artistic
+license in `/usr/share/common-licenses/Artistic'.
+
+
+The Zlib data compression library:
+ - d/phobos/etc/c/zlib/*
+
+ (C) 1995-2004 Jean-loup Gailly and Mark Adler
+
+  This software is provided 'as-is', without any express or implied
+  warranty.  In no event will the authors be held liable for any damages
+  arising from the use of this software.
+
+  Permission is granted to anyone to use this software for any purpose,
+  including commercial applications, and to alter it and redistribute it
+  freely, subject to the following restrictions:
+
+  1. The origin of this software must not be misrepresented; you must not
+     claim that you wrote the original software. If you use this software
+     in a product, an acknowledgment in the product documentation would be
+     appreciated but is not required.
+  2. Altered source versions must be plainly marked as such, and must not be
+     misrepresented as being the original software.
+  3. This notice may not be removed or altered from any source distribution.
+
+
+The Phobos standard runtime library:
+ - d/phobos/*
+
+Unless otherwise marked within the file, each file in the source
+is under the following licenses:
+
+Copyright (C) 2004-2005 by Digital Mars, www.digitalmars.com
+Written by Walter Bright
+
+This software is provided 'as-is', without any express or implied
+warranty. In no event will the authors be held liable for any damages
+arising from the use of this software.
+
+Permission is granted to anyone to use this software for any purpose,
+including commercial applications, and to alter it and redistribute it
+freely, in both source and binary form, subject to the following
+restrictions:
+
+ o  The origin of this software must not be misrepresented; you must not
+    claim that you wrote the original software. If you use this software
+    in a product, an acknowledgment in the product documentation would be
+    appreciated but is not required.
+ o  Altered source versions must be plainly marked as such, and must not
+    be misrepresented as being the original software.
+ o  This notice may not be removed or altered from any source
+    distribution.
+
+By plainly marking modifications, something along the lines of adding to each
+file that has been changed a "Modified by Foo Bar" line
+underneath the "Written by" line would be adequate.
+
--- gcc-6-6.4.0.orig/debian/copyright.in
+++ gcc-6-6.4.0/debian/copyright.in
@@ -0,0 +1,666 @@
+This is the Debian GNU/Linux prepackaged version of the GNU compiler
+collection, containing Ada, C, C++, Fortran 95, Java, Objective-C,
+Objective-C++, and Treelang compilers, documentation, and support
+libraries.  In addition, Debian provides the gdc compiler, either in
+the same source package, or built from a separate same source package.
+Packaging is done by the Debian GCC Maintainers
+<debian-gcc@lists.debian.org>, with sources obtained from:
+
+  ftp://gcc.gnu.org/pub/gcc/releases/  (for full releases)
+  svn://gcc.gnu.org/svn/gcc/           (for prereleases)
+  http://bitbucket.org/goshawk/gdc     (for D)
+
+The current gcc-@BV@ source package is taken from the SVN @SVN_BRANCH@.
+
+Changes: See changelog.Debian.gz
+
+Debian splits the GNU Compiler Collection into packages for each language,
+library, and documentation as follows:
+
+Language       Compiler package  Library package    Documentation
+---------------------------------------------------------------------------
+Ada            gnat-@BV@          libgnat-@BV@        gnat-@BV@-doc
+C              gcc-@BV@                              gcc-@BV@-doc
+C++            g++-@BV@           libstdc++6         libstdc++6-@BV@-doc
+D              gdc-@BV@
+Fortran 95     gfortran-@BV@      libgfortran3       gfortran-@BV@-doc
+Go             gccgo-@BV@         libgo0
+Java           gcj-@BV@           libgcj10           libgcj-doc
+Objective C    gobjc-@BV@         libobjc2
+Objective C++  gobjc++-@BV@
+
+For some language run-time libraries, Debian provides source files,
+development files, debugging symbols and libraries containing position-
+independent code in separate packages:
+
+Language  Sources      Development   Debugging            Position-Independent
+------------------------------------------------------------------------------
+C++                                  libstdc++6-@BV@-dbg  libstdc++6-@BV@-pic
+D         libphobos-@BV@-dev
+Java      libgcj10-src libgcj10-dev  libgcj10-dbg
+
+Additional packages include:
+
+All languages:
+libgcc1, libgcc2, libgcc4       GCC intrinsics (platform-dependent)
+gcc-@BV@-base                    Base files common to all compilers
+gcc-@BV@-soft-float              Software floating point (ARM only)
+gcc-@BV@-source                  The sources with patches
+
+Ada:
+libgnatvsn-dev, libgnatvsn@BV@   GNAT version library
+libgnatprj-dev, libgnatprj@BV@   GNAT Project Manager library
+
+C:
+cpp-@BV@, cpp-@BV@-doc            GNU C Preprocessor
+libssp0-dev, libssp0            GCC stack smashing protection library
+libquadmath0                    Math routines for the __float128 type
+fixincludes                     Fix non-ANSI header files
+
+Java:
+gij                             The Java bytecode interpreter and VM
+libgcj-common                   Common files for the Java run-time
+libgcj10-awt                    The Abstract Windowing Toolkit
+libgcj10-jar                    Java ARchive for the Java run-time
+
+C, C++ and Fortran 95:
+libgomp1-dev, libgomp1		GCC OpenMP (GOMP) support library
+libitm1-dev, libitm1		GNU Transactional Memory Library
+
+Biarch support: On some 64-bit platforms which can also run 32-bit code,
+Debian provides additional packages containing 32-bit versions of some
+libraries.  These packages have names beginning with 'lib32' instead of
+'lib', for example lib32stdc++6.  Similarly, on some 32-bit platforms which
+can also run 64-bit code, Debian provides additional packages with names
+beginning with 'lib64' instead of 'lib'.  These packages contain 64-bit
+versions of the libraries.  (At this time, not all platforms and not all
+libraries support biarch.)  The license terms for these lib32 or lib64
+packages are identical to the ones for the lib packages.
+
+
+COPYRIGHT STATEMENTS AND LICENSING TERMS
+
+
+GCC is Copyright (C) 1986, 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994,
+1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
+2008, 2009, 2010, 2011, 2012, 2013, 2014 Free Software Foundation, Inc.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Files that have exception clauses are licensed under the terms of the
+GNU General Public License; either version 3, or (at your option) any
+later version.
+
+On Debian GNU/Linux systems, the complete text of the GNU General
+Public License is in `/usr/share/common-licenses/GPL', version 3 of this
+license in `/usr/share/common-licenses/GPL-3'.
+
+The following runtime libraries are licensed under the terms of the
+GNU General Public License (v3 or later) with version 3.1 of the GCC
+Runtime Library Exception (included in this file):
+
+ - libgcc (libgcc/, gcc/libgcc2.[ch], gcc/unwind*, gcc/gthr*,
+   gcc/coretypes.h, gcc/crtstuff.c, gcc/defaults.h, gcc/dwarf2.h,
+   gcc/emults.c, gcc/gbl-ctors.h, gcc/gcov-io.h, gcc/libgcov.c,
+   gcc/tsystem.h, gcc/typeclass.h).
+ - libatomic
+ - libdecnumber
+ - libgomp
+ - libitm
+ - libssp
+ - libstdc++-v3
+ - libobjc
+ - libgfortran
+ - The libgnat-@BV@ Ada support library and libgnatvsn library.
+ - Various config files in gcc/config/ used in runtime libraries.
+ - libvtv
+
+In contrast, libgnatprj is licensed under the terms of the pure GNU
+General Public License.
+
+The libbacktrace library is licensed under the following terms:
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+    (1) Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer. 
+
+    (2) Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in
+    the documentation and/or other materials provided with the
+    distribution.  
+    
+    (3) The name of the author may not be used to
+    endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+
+The libsanitizer libraries (libasan, liblsan, libtsan, libubsan) are
+licensed under the following terms:
+
+Copyright (c) 2009-2014 by the LLVM contributors.
+
+All rights reserved.
+
+Developed by:
+
+    LLVM Team
+
+    University of Illinois at Urbana-Champaign
+
+    http://llvm.org
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal with
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimers.
+
+    * Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimers in the
+      documentation and/or other materials provided with the distribution.
+
+    * Neither the names of the LLVM Team, University of Illinois at
+      Urbana-Champaign, nor the names of its contributors may be used to
+      endorse or promote products derived from this Software without specific
+      prior written permission.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+SOFTWARE.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+
+The libgcj library is licensed under the terms of the GNU General
+Public License, with a special exception:
+
+    Linking this library statically or dynamically with other modules
+    is making a combined work based on this library.  Thus, the terms
+    and conditions of the GNU General Public License cover the whole
+    combination.
+
+    As a special exception, the copyright holders of this library give
+    you permission to link this library with independent modules to
+    produce an executable, regardless of the license terms of these
+    independent modules, and to copy and distribute the resulting
+    executable under terms of your choice, provided that you also
+    meet, for each linked independent module, the terms and conditions
+    of the license of that module.  An independent module is a module
+    which is not derived from or based on this library.  If you modify
+    this library, you may extend this exception to your version of the
+    library, but you are not obligated to do so.  If you do not wish
+    to do so, delete this exception statement from your version.
+
+The libffi library is licensed under the following terms:
+
+    libffi - Copyright (c) 1996-2003  Red Hat, Inc.
+
+    Permission is hereby granted, free of charge, to any person obtaining
+    a copy of this software and associated documentation files (the
+    ``Software''), to deal in the Software without restriction, including
+    without limitation the rights to use, copy, modify, merge, publish,
+    distribute, sublicense, and/or sell copies of the Software, and to
+    permit persons to whom the Software is furnished to do so, subject to
+    the following conditions:
+
+    The above copyright notice and this permission notice shall be included
+    in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
+    OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+    IN NO EVENT SHALL CYGNUS SOLUTIONS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+    OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+    ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+    OTHER DEALINGS IN THE SOFTWARE.
+
+
+The documentation is licensed under the GNU Free Documentation License (v1.2).
+On Debian GNU/Linux systems, the complete text of this license is in
+`/usr/share/common-licenses/GFDL-1.2'.
+
+
+GCC RUNTIME LIBRARY EXCEPTION
+
+Version 3.1, 31 March 2009
+
+Copyright (C) 2009 Free Software Foundation, Inc. <http://fsf.org/>
+
+Everyone is permitted to copy and distribute verbatim copies of this
+license document, but changing it is not allowed.
+
+This GCC Runtime Library Exception ("Exception") is an additional
+permission under section 7 of the GNU General Public License, version
+3 ("GPLv3"). It applies to a given file (the "Runtime Library") that
+bears a notice placed by the copyright holder of the file stating that
+the file is governed by GPLv3 along with this Exception.
+
+When you use GCC to compile a program, GCC may combine portions of
+certain GCC header files and runtime libraries with the compiled
+program. The purpose of this Exception is to allow compilation of
+non-GPL (including proprietary) programs to use, in this way, the
+header files and runtime libraries covered by this Exception.
+
+0. Definitions.
+
+A file is an "Independent Module" if it either requires the Runtime
+Library for execution after a Compilation Process, or makes use of an
+interface provided by the Runtime Library, but is not otherwise based
+on the Runtime Library.
+
+"GCC" means a version of the GNU Compiler Collection, with or without
+modifications, governed by version 3 (or a specified later version) of
+the GNU General Public License (GPL) with the option of using any
+subsequent versions published by the FSF.
+
+"GPL-compatible Software" is software whose conditions of propagation,
+modification and use would permit combination with GCC in accord with
+the license of GCC.
+
+"Target Code" refers to output from any compiler for a real or virtual
+target processor architecture, in executable form or suitable for
+input to an assembler, loader, linker and/or execution
+phase. Notwithstanding that, Target Code does not include data in any
+format that is used as a compiler intermediate representation, or used
+for producing a compiler intermediate representation.
+
+The "Compilation Process" transforms code entirely represented in
+non-intermediate languages designed for human-written code, and/or in
+Java Virtual Machine byte code, into Target Code. Thus, for example,
+use of source code generators and preprocessors need not be considered
+part of the Compilation Process, since the Compilation Process can be
+understood as starting with the output of the generators or
+preprocessors.
+
+A Compilation Process is "Eligible" if it is done using GCC, alone or
+with other GPL-compatible software, or if it is done without using any
+work based on GCC. For example, using non-GPL-compatible Software to
+optimize any GCC intermediate representations would not qualify as an
+Eligible Compilation Process.
+
+1. Grant of Additional Permission.
+
+You have permission to propagate a work of Target Code formed by
+combining the Runtime Library with Independent Modules, even if such
+propagation would otherwise violate the terms of GPLv3, provided that
+all Target Code was generated by Eligible Compilation Processes. You
+may then convey such a combination under terms of your choice,
+consistent with the licensing of the Independent Modules.
+
+2. No Weakening of GCC Copyleft.
+
+The availability of this Exception does not imply any general
+presumption that third-party software is unaffected by the copyleft
+requirements of the license of GCC.
+
+
+libquadmath/*.[hc]:
+
+   Copyright (C) 2010 Free Software Foundation, Inc.
+   Written by Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+   Written by Tobias Burnus  <burnus@net-b.de>
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+Library General Public License for more details.
+
+libquadmath/math:
+
+atanq.c, expm1q.c, j0q.c, j1q.c, log1pq.c, logq.c:
+    Copyright 2001 by Stephen L. Moshier <moshier@na-net.ornl.gov> 
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+coshq.c, erfq.c, jnq.c, lgammaq.c, powq.c, roundq.c:
+   Changes for 128-bit __float128 are
+   Copyright (C) 2001 Stephen L. Moshier <moshier@na-net.ornl.gov>
+   and are incorporated herein by permission of the author.  The author 
+   reserves the right to distribute this material elsewhere under different
+   copying permissions.  These modifications are distributed here under 
+   the following terms:
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+ldexpq.c:
+   * Conversion to long double by Ulrich Drepper,
+   * Cygnus Support, drepper@cygnus.com.
+
+cosq_kernel.c, expq.c, sincos_table.c, sincosq.c, sincosq_kernel.c,
+sinq_kernel.c, truncq.c:
+   Copyright (C) 1997, 1999 Free Software Foundation, Inc.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+isinfq.c:
+ * Written by J.T. Conklin <jtc@netbsd.org>.
+ * Change for long double by Jakub Jelinek <jj@ultra.linux.cz>
+ * Public domain.
+
+llroundq.c, lroundq.c, tgammaq.c:
+   Copyright (C) 1997, 1999, 2002, 2004 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997 and
+                  Jakub Jelinek <jj@ultra.linux.cz>, 1999.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+log10q.c:
+   Cephes Math Library Release 2.2:  January, 1991
+   Copyright 1984, 1991 by Stephen L. Moshier
+   Adapted for glibc November, 2001
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+remaining files:
+
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+
+
+libjava/classpath/resource/gnu/java/locale/*
+
+They are copyrighted and covered by the terms of use:
+http://www.unicode.org/copyright.html
+
+EXHIBIT 1
+UNICODE, INC. LICENSE AGREEMENT - DATA FILES AND SOFTWARE
+
+ Unicode Data Files include all data files under the directories 
+http://www.unicode.org/Public/ and http://www.unicode.org/reports/. 
+Unicode Software includes any source code published in the Unicode Standard or 
+under the directories http://www.unicode.org/Public/ and 
+http://www.unicode.org/reports/.
+
+NOTICE TO USER: Carefully read the following legal agreement. BY DOWNLOADING, 
+INSTALLING, COPYING OR OTHERWISE USING UNICODE INC.'S DATA FILES ("DATA FILES"), 
+AND/OR SOFTWARE ("SOFTWARE"), YOU UNEQUIVOCALLY ACCEPT, AND AGREE TO BE BOUND BY, 
+ALL OF THE TERMS AND CONDITIONS OF THIS AGREEMENT. IF YOU DO NOT AGREE, 
+DO NOT DOWNLOAD, INSTALL, COPY, DISTRIBUTE OR USE THE DATA FILES OR SOFTWARE.
+
+	    COPYRIGHT AND PERMISSION NOTICE
+
+Copyrigh (c) 1991-2011 Unicode, Inc. All rights reserved. 
+Distributed under the Terms of Use in http://www.unicode.org/copyright.html.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy 
+of the Unicode data files and any associated documentation (the "Data Files") 
+or Unicode software and any associated documentation (the "Software") to deal 
+in the Data Files or Software without restriction, including without limitation 
+the rights to use, copy, modify, merge, publish, distribute, and/or sell copies
+ of the Data Files or Software, and to permit persons to whom the Data Files 
+or Software are furnished to do so, provided that (a) the above copyright notice(s) 
+and this permission notice appear with all copies of the Data Files or Software, 
+(b) both the above copyright notice(s) and this permission notice appear 
+in associated documentation, and (c) there is clear notice in each modified 
+Data File or in the Software as well as in the documentation associated with 
+the Data File(s) or Software that the data or software has been modified.
+
+THE DATA FILES AND SOFTWARE ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR HOLDERS INCLUDED IN THIS NOTICE BE LIABLE
+ FOR ANY CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES 
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF 
+CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 
+WITH THE USE OR PERFORMANCE OF THE DATA FILES OR SOFTWARE.
+
+Except as contained in this notice, the name of a copyright holder shall not be used
+ in advertising or otherwise to promote the sale, use or other dealings in these 
+Data Files or Software without prior written authorization of the copyright holder.
+
+Unicode and the Unicode logo are trademarks of Unicode, Inc., and may be registered
+ in some jurisdictions. All other trademarks and registered trademarks mentioned 
+herein are the property of their respective owners.
+
+
+gcc/go/gofrontend, libgo:
+
+Copyright (c) 2009 The Go Authors. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+   * Redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above
+copyright notice, this list of conditions and the following disclaimer
+in the documentation and/or other materials provided with the
+distribution.
+   * Neither the name of Google Inc. nor the names of its
+contributors may be used to endorse or promote products derived from
+this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+libcilkrts, libmpx:
+ Copyright (C) 2009-2014, Intel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+   * Neither the name of Intel Corporation nor the names of its
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
+ WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
+
+D:
+gdc-@BV@                         GNU D Compiler
+libphobos-@BV@-dev               D standard runtime library
+
+The D source package is made up of the following components.
+
+The D front-end for GCC:
+ - d/*
+
+Copyright (C) 2004-2007 David Friedman
+Modified by Vincenzo Ampolo, Michael Parrot, Iain Buclaw, (C) 2009, 2010
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+On Debian GNU/Linux systems, the complete text of the GNU General
+Public License is in `/usr/share/common-licenses/GPL', version 2 of this
+license in `/usr/share/common-licenses/GPL-2'.
+
+
+The DMD Compiler implementation of the D programming language:
+ - d/dmd/*
+
+Copyright (c) 1999-2010 by Digital Mars
+All Rights Reserved
+written by Walter Bright
+http://www.digitalmars.com
+License for redistribution is by either the Artistic License or
+the GNU General Public License (v1).
+
+On Debian GNU/Linux systems, the complete text of the GNU General
+Public License is in `/usr/share/common-licenses/GPL', the Artistic
+license in `/usr/share/common-licenses/Artistic'.
+
+
+The Zlib data compression library:
+ - d/phobos/etc/c/zlib/*
+
+ (C) 1995-2004 Jean-loup Gailly and Mark Adler
+
+  This software is provided 'as-is', without any express or implied
+  warranty.  In no event will the authors be held liable for any damages
+  arising from the use of this software.
+
+  Permission is granted to anyone to use this software for any purpose,
+  including commercial applications, and to alter it and redistribute it
+  freely, subject to the following restrictions:
+
+  1. The origin of this software must not be misrepresented; you must not
+     claim that you wrote the original software. If you use this software
+     in a product, an acknowledgment in the product documentation would be
+     appreciated but is not required.
+  2. Altered source versions must be plainly marked as such, and must not be
+     misrepresented as being the original software.
+  3. This notice may not be removed or altered from any source distribution.
+
+
+The Phobos standard runtime library:
+ - d/phobos/*
+
+Unless otherwise marked within the file, each file in the source
+is under the following licenses:
+
+Copyright (C) 2004-2005 by Digital Mars, www.digitalmars.com
+Written by Walter Bright
+
+This software is provided 'as-is', without any express or implied
+warranty. In no event will the authors be held liable for any damages
+arising from the use of this software.
+
+Permission is granted to anyone to use this software for any purpose,
+including commercial applications, and to alter it and redistribute it
+freely, in both source and binary form, subject to the following
+restrictions:
+
+ o  The origin of this software must not be misrepresented; you must not
+    claim that you wrote the original software. If you use this software
+    in a product, an acknowledgment in the product documentation would be
+    appreciated but is not required.
+ o  Altered source versions must be plainly marked as such, and must not
+    be misrepresented as being the original software.
+ o  This notice may not be removed or altered from any source
+    distribution.
+
+By plainly marking modifications, something along the lines of adding to each
+file that has been changed a "Modified by Foo Bar" line
+underneath the "Written by" line would be adequate.
+
--- gcc-6-6.4.0.orig/debian/cpp-BV-CRB.preinst.in
+++ gcc-6-6.4.0/debian/cpp-BV-CRB.preinst.in
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+set -e
+
+if [ "$1" = "upgrade" ] || [ "$1" = "configure" ]; then
+    update-alternatives --quiet --remove @TARGET@-cpp /usr/bin/@TARGET@-cpp-@BV@
+fi
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.4.0.orig/debian/cpp-BV-doc.doc-base.cpp
+++ gcc-6-6.4.0/debian/cpp-BV-doc.doc-base.cpp
@@ -0,0 +1,16 @@
+Document: cpp-@BV@
+Title: The GNU C preprocessor
+Author: Various
+Abstract: The C preprocessor is a "macro processor" that is used automatically
+ by the C compiler to transform your program before actual compilation.
+ It is called a macro processor because it allows you to define "macros",
+ which are brief abbreviations for longer constructs.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/cpp.html
+Files: /usr/share/doc/gcc-@BV@-base/cpp.html
+
+Format: info
+Index: /usr/share/info/cpp-@BV@.info.gz
+Files: /usr/share/info/cpp-@BV@*
--- gcc-6-6.4.0.orig/debian/cpp-BV-doc.doc-base.cppint
+++ gcc-6-6.4.0/debian/cpp-BV-doc.doc-base.cppint
@@ -0,0 +1,17 @@
+Document: cppinternals-@BV@
+Title: The GNU C preprocessor (internals)
+Author: Various
+Abstract: This brief manual documents the internals of cpplib, and
+ explains some of the tricky issues.  It is intended that, along with
+ the comments in the source code, a reasonably competent C programmer
+ should be able to figure out what the code is doing, and why things
+ have been implemented the way they have.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/cppinternals.html
+Files: /usr/share/doc/gcc-@BV@-base/cppinternals.html
+
+Format: info
+Index: /usr/share/info/cppinternals-@BV@.info.gz
+Files: /usr/share/info/cppinternals-@BV@*
--- gcc-6-6.4.0.orig/debian/dh_doclink
+++ gcc-6-6.4.0/debian/dh_doclink
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+pkg=`echo $1 | sed 's/^-p//'`
+target=$2
+
+[ -d debian/$pkg/usr/share/doc ] || mkdir -p debian/$pkg/usr/share/doc
+if [ -d debian/$pkg/usr/share/doc/$p -a ! -h debian/$pkg/usr/share/doc/$p ]
+then
+    echo "WARNING: removing doc directory  $pkg"
+    rm -rf debian/$pkg/usr/share/doc/$pkg
+fi
+ln -sf $target debian/$pkg/usr/share/doc/$pkg
--- gcc-6-6.4.0.orig/debian/dh_rmemptydirs
+++ gcc-6-6.4.0/debian/dh_rmemptydirs
@@ -0,0 +1,10 @@
+#! /bin/sh -e
+
+pkg=`echo $1 | sed 's/^-p//'`
+
+: # remove empty directories, when all components are in place
+for d in `find debian/$pkg -depth -type d -empty 2> /dev/null`; do \
+    while rmdir $d 2> /dev/null; do d=`dirname $d`; done; \
+done
+
+exit 0
--- gcc-6-6.4.0.orig/debian/dummy-man.1
+++ gcc-6-6.4.0/debian/dummy-man.1
@@ -0,0 +1,29 @@
+.TH @NAME@ 1 "May 24, 2003" @name@ "Debian Free Documentation"
+.SH NAME
+@name@ \- A program with a man page covered by the GFDL with invariant sections
+.SH SYNOPSIS
+@name@ [\fB\s-1OPTION\s0\fR] ... [\fI\s-1ARGS\s0\fR...]
+
+.SH DESCRIPTION
+
+\fB@name@\fR is documented by a man page, which is covered by the "GNU
+Free Documentation License" (GFDL) containing invariant sections.
+.P
+In November 2002, version 1.2 of the GNU Free Documentation License (GNU
+FDL) was released by the Free Software Foundation after a long period
+of consultation. Unfortunately, some concerns raised by members of the
+Debian Project were not addressed, and as such the GNU FDL can apply
+to works that do not pass the Debian Free Software Guidelines (DFSG),
+and may thus only be included in the non-free component of the Debian
+archive, not the Debian distribution itself.
+
+.SH "SEE ALSO"
+.BR http://gcc.gnu.org/onlinedocs/
+for the complete documentation,
+.BR http://lists.debian.org/debian-legal/2003/debian-legal-200304/msg00307.html
+for a proposed statement of Debian with respect to the GFDL,
+.BR gfdl(7)
+
+.SH AUTHOR
+This manual page was written by the Debian GCC maintainers,
+for the Debian GNU/Linux system.
--- gcc-6-6.4.0.orig/debian/dummy.texi
+++ gcc-6-6.4.0/debian/dummy.texi
@@ -0,0 +1 @@
+@c This file is empty because the original one has a non DFSG free license (GFDL)
--- gcc-6-6.4.0.orig/debian/fixincludes.in
+++ gcc-6-6.4.0/debian/fixincludes.in
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+PATH="/@LIBEXECDIR@/install-tools:$PATH"
+
+TARGET_MACHINE=`dpkg-architecture -qDEB_HOST_GNU_TYPE`
+export TARGET_MACHINE
+
+exec fixinc.sh "$@"
--- gcc-6-6.4.0.orig/debian/g++-BV-CRB.preinst.in
+++ gcc-6-6.4.0/debian/g++-BV-CRB.preinst.in
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+set -e
+
+if [ "$1" = "upgrade" ] || [ "$1" = "configure" ]; then
+    update-alternatives --quiet --remove @TARGET@-g++ /usr/bin/@TARGET@-g++-@BV@
+fi
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.4.0.orig/debian/gcc-BV-CRB.preinst.in
+++ gcc-6-6.4.0/debian/gcc-BV-CRB.preinst.in
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+set -e
+
+if [ "$1" = "upgrade" ] || [ "$1" = "configure" ]; then
+    update-alternatives --quiet --remove @TARGET@-gcc /usr/bin/@TARGET@-gcc-@BV@
+    update-alternatives --quiet --remove @TARGET@-gcov /usr/bin/@TARGET@-gcov-@BV@
+fi
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.4.0.orig/debian/gcc-BV-doc.doc-base.gcc
+++ gcc-6-6.4.0/debian/gcc-BV-doc.doc-base.gcc
@@ -0,0 +1,14 @@
+Document: gcc-@BV@
+Title: The GNU C and C++ compiler
+Author: Various
+Abstract: This manual documents how to run, install and port the GNU compiler,
+ as well as its new features and incompatibilities, and how to report bugs.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/gcc.html
+Files: /usr/share/doc/gcc-@BV@-base/gcc.html
+
+Format: info
+Index: /usr/share/info/gcc-@BV@.info.gz
+Files: /usr/share/info/gcc-@BV@*
--- gcc-6-6.4.0.orig/debian/gcc-BV-doc.doc-base.gccint
+++ gcc-6-6.4.0/debian/gcc-BV-doc.doc-base.gccint
@@ -0,0 +1,17 @@
+Document: gccint-@BV@
+Title: Internals of the GNU C and C++ compiler
+Author: Various
+Abstract: This manual documents the internals of the GNU compilers,
+ including how to port them to new targets and some information about
+ how to write front ends for new languages.  It corresponds to GCC
+ version @BV@.x.  The use of the GNU compilers is documented in a
+ separate manual.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/gccint.html
+Files: /usr/share/doc/gcc-@BV@-base/gccint.html
+
+Format: info
+Index: /usr/share/info/gccint-@BV@.info.gz
+Files: /usr/share/info/gccint-@BV@*
--- gcc-6-6.4.0.orig/debian/gcc-BV-doc.doc-base.gomp
+++ gcc-6-6.4.0/debian/gcc-BV-doc.doc-base.gomp
@@ -0,0 +1,15 @@
+Document: gcc-@BV@-gomp
+Title: The GNU OpenMP Implementation (for GCC @BV@)
+Author: Various
+Abstract: This manual documents the usage of libgomp, the GNU implementation
+ of the OpenMP Application Programming Interface (API) for multi-platform
+ shared-memory parallel programming in C/C++ and Fortran.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/libgomp.html
+Files: /usr/share/doc/gcc-@BV@-base/libgomp.html
+
+Format: info
+Index: /usr/share/info/libgomp-@BV@.info.gz
+Files: /usr/share/info/libgomp-@BV@*
--- gcc-6-6.4.0.orig/debian/gcc-BV-doc.doc-base.itm
+++ gcc-6-6.4.0/debian/gcc-BV-doc.doc-base.itm
@@ -0,0 +1,16 @@
+Document: gcc-@BV@-itm
+Title: The GNU Transactional Memory Library (for GCC @BV@)
+Author: Various
+Abstract: This manual documents the usage and internals of libitm,
+ the GNU Transactional Memory Library. It provides transaction support
+ for accesses to a process' memory, enabling easy-to-use synchronization
+ of accesses to shared memory by several threads.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/libitm.html
+Files: /usr/share/doc/gcc-@BV@-base/libitm.html
+
+Format: info
+Index: /usr/share/info/libitm-@BV@.info.gz
+Files: /usr/share/info/libitm-@BV@*
--- gcc-6-6.4.0.orig/debian/gcc-BV-doc.doc-base.qmath
+++ gcc-6-6.4.0/debian/gcc-BV-doc.doc-base.qmath
@@ -0,0 +1,14 @@
+Document: gcc-@BV@-qmath
+Title: The GCC Quad-Precision Math Library (for GCC @BV@)
+Author: Various
+Abstract: This manual documents the usage of libquadmath, the GCC
+ Quad-Precision Math Library Application Programming Interface (API).
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/libquadmath.html
+Files: /usr/share/doc/gcc-@BV@-base/libquadmath.html
+
+Format: info
+Index: /usr/share/info/libquadmath-@BV@.info.gz
+Files: /usr/share/info/libquadmath-@BV@*
--- gcc-6-6.4.0.orig/debian/gcc-BV-hppa64-linux-gnu.overrides
+++ gcc-6-6.4.0/debian/gcc-BV-hppa64-linux-gnu.overrides
@@ -0,0 +1,3 @@
+gcc-@BV@-hppa64-linux-gnu binary: binary-from-other-architecture
+gcc-@BV@-hppa64-linux-gnu binary: binary-without-manpage
+gcc-@BV@-hppa64-linux-gnu binary: hardening-no-pie
--- gcc-6-6.4.0.orig/debian/gcc-BV-multilib.overrides
+++ gcc-6-6.4.0/debian/gcc-BV-multilib.overrides
@@ -0,0 +1 @@
+gcc-@BV@-multilib binary: binary-from-other-architecture
--- gcc-6-6.4.0.orig/debian/gcc-BV-source.overrides
+++ gcc-6-6.4.0/debian/gcc-BV-source.overrides
@@ -0,0 +1,5 @@
+gcc-@BV@-source: changelog-file-not-compressed
+
+# these are patches taken over unmodified from 4.3
+gcc-@BV@-source: script-not-executable
+gcc-@BV@-source: shell-script-fails-syntax-check
--- gcc-6-6.4.0.orig/debian/gcc-XX-BV.1
+++ gcc-6-6.4.0/debian/gcc-XX-BV.1
@@ -0,0 +1,17 @@
+.TH GCC-@TOOL@-@BV@ 1 "May 8, 2012" gcc-@TOOL@-@BV@ ""
+.SH NAME
+gcc-@TOOL@ \- a wrapper around @TOOL@ adding the --plugin option
+
+.SH SYNOPSIS
+gcc-@TOOL@ [\fB\s-1OPTION\s0\fR] ... [\fI\s-1ARGS\s0\fR...]
+
+.SH DESCRIPTION
+
+\fBgcc-@TOOL@\fR is a wrapper around @TOOL@(1) adding the appropriate
+\fB\-\-plugin\fR option for the GCC @BV@ compiler.
+
+.SH OPTIONS
+See @TOOL@(1) for a list of options that @TOOL@ understands.
+
+.SH "SEE ALSO"
+.BR @TOOL@(1)
--- gcc-6-6.4.0.orig/debian/gcc-dummy.texi
+++ gcc-6-6.4.0/debian/gcc-dummy.texi
@@ -0,0 +1,41 @@
+\input texinfo  @c -*-texinfo-*-
+@c %**start of header
+
+@settitle The GNU Compiler Collection (GCC)
+
+@c Create a separate index for command line options.
+@defcodeindex op
+@c Merge the standard indexes into a single one.
+@syncodeindex fn cp
+@syncodeindex vr cp
+@syncodeindex ky cp
+@syncodeindex pg cp
+@syncodeindex tp cp
+
+@paragraphindent 1
+
+@c %**end of header
+
+@copying
+The current documentation is licensed under the same terms as the Debian packaging.
+@end copying
+@ifnottex
+@dircategory Programming
+@direntry
+* @name@: (@name@).                  The GNU Compiler Collection (@name@).
+@end direntry
+@sp 1
+@end ifnottex
+
+@summarycontents
+@contents
+@page
+
+@node Top
+@top Introduction
+@cindex introduction
+The official GNU compilers' documentation is released under the terms
+of the GNU Free Documentation License with cover texts. This has been
+considered non free by the Debian Project. Thus you will find it in the
+non-free section of the Debian archive.
+@bye
--- gcc-6-6.4.0.orig/debian/gcc-snapshot.overrides
+++ gcc-6-6.4.0/debian/gcc-snapshot.overrides
@@ -0,0 +1,10 @@
+gcc-snapshot binary: bad-permissions-for-ali-file
+
+# keep patched ltdl copy
+gcc-snapshot binary: embedded-library
+
+gcc-snapshot binary: binary-from-other-architecture
+gcc-snapshot binary: extra-license-file
+gcc-snapshot binary: jar-not-in-usr-share
+gcc-snapshot binary: triplet-dir-and-architecture-mismatch
+gcc-snapshot binary: unstripped-binary-or-object
--- gcc-6-6.4.0.orig/debian/gcc-snapshot.prerm
+++ gcc-6-6.4.0/debian/gcc-snapshot.prerm
@@ -0,0 +1,5 @@
+#! /bin/sh -e
+
+rm -f /usr/lib/gcc-snapshot/share/python/*.py[co]
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/gccgo-BV-doc.doc-base
+++ gcc-6-6.4.0/debian/gccgo-BV-doc.doc-base
@@ -0,0 +1,17 @@
+Document: gccgo-@BV@
+Title: The GNU Go compiler (version @BV@)
+Author: Various
+Abstract: This manual describes how to use gccgo, the GNU compiler for
+ the Go programming language.  This manual is specifically about
+ gccgo.  For more information about the Go programming
+ language in general, including language specifications and standard
+ package documentation, see http://golang.org/.
+Section: Programming
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/gccgo.html
+Files: /usr/share/doc/gcc-@BV@-base/gccgo.html
+
+Format: info
+Index: /usr/share/info/gccgo-@BV@.info.gz
+Files: /usr/share/info/gccgo-@BV@*
--- gcc-6-6.4.0.orig/debian/gcj-BV-jdk.doc-base
+++ gcc-6-6.4.0/debian/gcj-BV-jdk.doc-base
@@ -0,0 +1,15 @@
+Document: gcj-@BV@
+Title: The GNU Ahead-of-time Compiler for the Java Language
+Author: Various
+Abstract: This manual describes how to use gcj, the GNU compiler for
+ the Java programming language.  gcj can generate both .class files and
+ object files, and it can read both Java source code and .class files.
+Section: Programming/Java
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/java/gcj.html
+Files: /usr/share/doc/gcc-@BV@-base/java/gcj.html
+
+Format: info
+Index: /usr/share/info/gcj-@BV@.info.gz
+Files: /usr/share/info/gcj-@BV@*
--- gcc-6-6.4.0.orig/debian/gcj-BV-jdk.overrides
+++ gcc-6-6.4.0/debian/gcj-BV-jdk.overrides
@@ -0,0 +1 @@
+gcj-@BV@-jdk binary: wrong-name-for-upstream-changelog
--- gcc-6-6.4.0.orig/debian/gcj-BV-jdk.postinst
+++ gcc-6-6.4.0/debian/gcj-BV-jdk.postinst
@@ -0,0 +1,45 @@
+#! /bin/sh -e
+
+if [ -d /usr/share/doc/gcc-@BV@-base/java ] && [ ! -h /usr/share/doc/gcc-@BV@-base/java ]; then
+    rm -rf /usr/share/doc/gcc-@BV@-base/java
+    ln -s ../gcj-@BV@-base /usr/share/doc/gcc-@BV@-base/java
+fi
+
+prio=@java_priority@
+update-alternatives --quiet \
+    --install /usr/bin/javac javac /usr/bin/gcj-wrapper-@BV@ $prio \
+    @GFDL@--slave /usr/share/man/man1/javac.1.gz javac.1.gz /usr/share/man/man1/gcj-wrapper-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/jar jar /usr/bin/gjar-@BV@ $prio \
+    --slave /usr/share/man/man1/jar.1.gz jar.1.gz /usr/share/man/man1/gjar-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/jarsigner jarsigner /usr/bin/gjarsigner-@BV@ $prio \
+    --slave /usr/share/man/man1/jarsigner.1.gz jarsigner.1.gz /usr/share/man/man1/gjarsigner-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/javah javah /usr/bin/gjavah-@BV@ $prio \
+    --slave /usr/share/man/man1/javah.1.gz javah.1.gz /usr/share/man/man1/gjavah-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/javadoc javadoc /usr/bin/gjdoc-@BV@ $prio \
+    --slave /usr/share/man/man1/javadoc.1.gz javadoc.1.gz /usr/share/man/man1/gjdoc-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/native2ascii native2ascii /usr/bin/gnative2ascii-@BV@ $prio \
+    --slave /usr/share/man/man1/native2ascii.1.gz native2ascii.1.gz /usr/share/man/man1/gnative2ascii-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/rmic rmic /usr/bin/grmic-@BV@ $prio \
+    @GFDL@--slave /usr/share/man/man1/rmic.1.gz rmic.1.gz /usr/share/man/man1/grmic-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/serialver serialver /usr/bin/gserialver-@BV@ $prio \
+    --slave /usr/share/man/man1/serialver.1.gz serialver.1.gz /usr/share/man/man1/gserialver-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/tnameserv tnameserv /usr/bin/gtnameserv-@BV@ $prio \
+    --slave /usr/share/man/man1/tnameserv.1.gz tnameserv.1.gz /usr/share/man/man1/gtnameserv-@BV@.1.gz
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/gcj-BV-jdk.prerm
+++ gcc-6-6.4.0/debian/gcj-BV-jdk.prerm
@@ -0,0 +1,15 @@
+#! /bin/sh -e
+
+if [ "$1" = "remove" ] || [ "$1" = "deconfigure" ]; then
+    update-alternatives --quiet --remove javac /usr/bin/gcj-wrapper-@BV@
+    update-alternatives --quiet --remove jar /usr/bin/gjar-@BV@
+    update-alternatives --quiet --remove jarsigner /usr/bin/gjarsigner-@BV@
+    update-alternatives --quiet --remove javah /usr/bin/gjavah-@BV@
+    update-alternatives --quiet --remove javadoc /usr/bin/gjdoc-@BV@
+    update-alternatives --quiet --remove native2ascii /usr/bin/gnative2ascii-@BV@
+    update-alternatives --quiet --remove rmic /usr/bin/grmic-@BV@
+    update-alternatives --quiet --remove serialver /usr/bin/gserialver-@BV@
+    update-alternatives --quiet --remove tnameserv /usr/bin/gtnameserv-@BV@
+fi
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/gcj-BV-jre-headless.overrides
+++ gcc-6-6.4.0/debian/gcj-BV-jre-headless.overrides
@@ -0,0 +1,5 @@
+# pick up the exact version, in case another gcj version is installed
+gcj-@BV@-jre-headless binary: binary-or-shlib-defines-rpath
+
+# don't strip the binaries, keep the libgcj13-dbg package Multi-Arch: same
+gcj-@BV@-jre-headless binary: unstripped-binary-or-object
--- gcc-6-6.4.0.orig/debian/gcj-BV-jre-headless.postinst
+++ gcc-6-6.4.0/debian/gcj-BV-jre-headless.postinst
@@ -0,0 +1,48 @@
+#! /bin/sh -e
+
+prio=@java_priority@
+
+update-alternatives --quiet \
+    --install /usr/bin/java java /usr/bin/gij-@BV@ $prio \
+    @GFDL@--slave /usr/share/man/man1/java.1.gz java.1.gz /usr/share/man/man1/gij-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/rmiregistry rmiregistry /usr/bin/grmiregistry-@BV@ $prio \
+    --slave /usr/share/man/man1/rmiregistry.1.gz rmiregistry.1.gz /usr/share/man/man1/grmiregistry-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/keytool keytool /usr/bin/gkeytool-@BV@ $prio \
+    --slave /usr/share/man/man1/keytool.1.gz keytool.1.gz /usr/share/man/man1/gkeytool-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/orbd orbd /usr/bin/gorbd-@BV@ $prio \
+    --slave /usr/share/man/man1/orbd.1.gz orbd.1.gz /usr/share/man/man1/gorbd-@BV@.1.gz
+
+update-alternatives --quiet \
+    --install /usr/bin/rmid rmid /usr/bin/grmid-@BV@ $prio \
+    --slave /usr/share/man/man1/rmid.1.gz rmid.1.gz /usr/share/man/man1/grmid-@BV@.1.gz
+
+case "$1" in
+configure)
+    if [ ! -f /var/lib/gcj-@BV@/classmap.db ]; then
+	uname=$(uname -m)
+	mkdir -p /var/lib/gcj-@BV@
+	if gcj-dbtool-@BV@ -n /var/lib/gcj-@BV@/classmap.db; then
+	    case "$uname" in arm*|m68k|parisc*)
+	        echo >&2 "gcj-dbtool succeeded unexpectedly"
+	    esac
+	else
+	    case "$uname" in
+	    arm*|m68k|parisc*)
+	        echo >&2 "ERROR: gcj-dbtool did fail; known problem on $uname";;
+	    *)
+		exit 2
+	    esac
+	    touch /var/lib/gcj-@BV@/classmap.db
+	fi
+    fi
+esac
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.4.0.orig/debian/gcj-BV-jre-headless.postrm
+++ gcc-6-6.4.0/debian/gcj-BV-jre-headless.postrm
@@ -0,0 +1,10 @@
+#! /bin/sh -e
+
+case "$1" in
+    purge)
+	rm -f /var/lib/gcj-@BV@/classmap.db
+esac
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.4.0.orig/debian/gcj-BV-jre-headless.prerm
+++ gcc-6-6.4.0/debian/gcj-BV-jre-headless.prerm
@@ -0,0 +1,13 @@
+#! /bin/sh -e
+
+if [ "$1" = "remove" ] || [ "$1" = "deconfigure" ]; then
+    update-alternatives --quiet --remove java /usr/bin/gij-@BV@
+    update-alternatives --quiet --remove rmiregistry /usr/bin/grmiregistry-@BV@
+    update-alternatives --quiet --remove keytool /usr/bin/gkeytool-@BV@
+    update-alternatives --quiet --remove orbd /usr/bin/gorbd-@BV@
+    update-alternatives --quiet --remove rmid /usr/bin/grmid-@BV@
+fi
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.4.0.orig/debian/gcj-wrapper-BV
+++ gcc-6-6.4.0/debian/gcj-wrapper-BV
@@ -0,0 +1,91 @@
+#!/usr/bin/perl -w
+#
+# Starts the GNU Java compiler.
+#
+# Command-line arguments should be in the style of Sun's Java compiler;
+# these will be converted to gcj arguments before being passed to the
+# gcj itself.
+#
+# Copyright (C) 2002-2003 by Ben Burton <bab@debian.org>
+# Based on the original gcj-wrapper-3.2 shell script.
+
+use strict;
+
+# The real Java compiler:
+my $javaCompiler = '/usr/bin/gcj-@BV@';
+
+# The command-line arguments to pass to the real Java compiler:
+my @commandLine;
+
+# The warning flags to pass to the GNU Java compiler:
+my $warnings = '-Wall';
+
+# Build the command-line from the arguments given.
+my $parsingOptions = 1;
+my $copyNextArg = 0;
+my $ignoreNextArg = 0;
+my $appendNextArg = '';
+foreach my $arg (@ARGV) {
+    # See if we already know what to do with this argument.
+    if ($ignoreNextArg) {
+        # Throw it away.
+        $ignoreNextArg = 0;
+        next;
+    } elsif ($copyNextArg or not $parsingOptions) {
+        # Copy it directly.
+        push @commandLine, $arg;
+        $copyNextArg = 0;
+        next;
+    } elsif ($appendNextArg) {
+        # Append it to $appendNextArg and then copy directly.
+        push @commandLine, ($appendNextArg . $arg);
+        $appendNextArg = '';
+        next;
+    }
+
+    # Try to interpret Sun-style options.
+    if ($arg eq '-version') {
+        push @commandLine, '--version';
+    } elsif ($arg eq '-h' or $arg eq '-help') {
+        push @commandLine, '--help';
+    } elsif ($arg eq '-classpath' or $arg eq '--classpath' or $arg eq '--cp') {
+        $appendNextArg = '--classpath=';
+    } elsif ($arg eq '-encoding' or $arg eq '-bootclasspath' or
+             $arg eq '-extdirs') {
+        $appendNextArg = '-' . $arg . '=';
+    } elsif ($arg eq '-d') {
+        push @commandLine, '-d';
+        $copyNextArg = 1;
+    } elsif ($arg eq '-nowarn') {
+        $warnings = '';
+    } elsif ($arg =~ /^-g/) {
+        # Some kind of debugging option - just switch debugging on.
+        push @commandLine, '-g' if ($arg ne '-g:none');
+    } elsif ($arg eq '-O') {
+        push @commandLine, '-O2';
+    } elsif ($arg eq '-Xss') {
+        push @commandLine, $arg;
+    } elsif ($arg =~ /^-X/) {
+        # An extended Sun option (which we don't support).
+        push @commandLine, '--help' if ($arg eq '-X');
+    } elsif ($arg eq '-source' or $arg eq '-sourcepath' or $arg eq '-target') {
+        # An unsupported option with a following argument.
+        $ignoreNextArg = 1;
+    } elsif ($arg =~ /^-/) {
+        # An unsupported standalone option.
+    } else {
+        # Some non-option argument has been given.
+        # Stop parsing options at this point.
+        push @commandLine, $arg;
+        $parsingOptions = 0;
+    }
+}
+
+# Was there a partial argument that was never completed?
+push @commandLine, $appendNextArg if ($appendNextArg);
+
+# Call the real Java compiler.
+my @fullCommandLine = ( $javaCompiler, '-C' );
+push @fullCommandLine, $warnings if ($warnings);
+push @fullCommandLine, @commandLine;
+exec @fullCommandLine or exit(1);
--- gcc-6-6.4.0.orig/debian/gcj-wrapper-BV.1
+++ gcc-6-6.4.0/debian/gcj-wrapper-BV.1
@@ -0,0 +1,20 @@
+.TH GCJ-WRAPPER 1 "June 6, 2002" gcj-wrapper "Java User's Manual"
+.SH NAME
+gcj-wrapper \- a wrapper around gcj
+
+.SH SYNOPSIS
+gcj-wrapper [\fB\s-1OPTION\s0\fR] ... [\fI\s-1ARGS\s0\fR...]
+
+.SH DESCRIPTION
+
+\fBgcj-wrapper\fR is a wrapper around gcj(1) to be called as the java
+compiler. Options different for javac(1) and gcj(1) are translated,
+options unknown to gcj(1) are silently ignored.
+
+.SH OPTIONS
+See gcj-@BV@(1) for a list of options that gcj understands.
+
+.SH "SEE ALSO"
+.BR gcj-@BV@(1)
+,
+.BR javac(1)
--- gcc-6-6.4.0.orig/debian/gcjh-wrapper-BV
+++ gcc-6-6.4.0/debian/gcjh-wrapper-BV
@@ -0,0 +1,86 @@
+#!/usr/bin/perl -w
+#
+# Starts the GNU Java header generator.
+#
+# Command-line arguments should be in the style of Sun's javah command;
+# these will be converted to gcjh arguments before being passed to the
+# gcjh itself.
+#
+# Copyright (C) 2003 by Peter Hawkins <peterh@debian.org>
+# Haphazardly hacked up based on the gcj-wrapper perl script.
+# Copyright (C) 2002-2003 by Ben Burton <bab@debian.org>
+# Based on the original gcj-wrapper-3.2 shell script.
+
+use strict;
+
+# The real Java header generator:
+my $javaHeaderGen = '/usr/bin/gcjh-@BV@';
+
+# The command-line arguments to pass to the real Java compiler:
+my @commandLine;
+
+# Build the command-line from the arguments given.
+my $parsingOptions = 1;
+my $copyNextArg = 0;
+my $ignoreNextArg = 0;
+my $appendNextArg = '';
+foreach my $arg (@ARGV) {
+    # See if we already know what to do with this argument.
+    if ($ignoreNextArg) {
+        # Throw it away.
+        $ignoreNextArg = 0;
+        next;
+    } elsif ($copyNextArg or not $parsingOptions) {
+        # Copy it directly.
+        push @commandLine, $arg;
+        $copyNextArg = 0;
+        next;
+    } elsif ($appendNextArg) {
+        # Append it to $appendNextArg and then copy directly.
+        push @commandLine, ($appendNextArg . $arg);
+        $appendNextArg = '';
+        next;
+    }
+
+    # Try to interpret Sun-style options.
+    if ($arg eq '-version') {
+        push @commandLine, '--version';
+    } elsif ($arg eq '-h' or $arg eq '-help') {
+        push @commandLine, '--help';
+    } elsif ($arg eq '-verbose') {
+        push @commandLine, '--verbose';
+    } elsif ($arg eq '-classpath' or $arg eq '--classpath' or $arg eq '--cp') {
+        $appendNextArg = '--classpath=';
+    } elsif ($arg eq '-encoding' or $arg eq '-bootclasspath' or
+             $arg eq '-extdirs') {
+        $appendNextArg = "-".$arg . '=';
+    } elsif ($arg eq '-d') {
+        push @commandLine, '-d';
+        $copyNextArg = 1;
+    } elsif ($arg eq '-o') {
+        push @commandLine, '-o';
+        $copyNextArg = 1;
+    } elsif ($arg eq '-stubs') {
+        push @commandLine, '-stubs';
+    } elsif ($arg eq '-jni') {
+        push @commandLine, '-jni';
+    } elsif ($arg =~ /^-old/) {
+        # An extended Sun option (which we don't support).
+        push @commandLine, '--help' if ($arg eq '-old');
+    } elsif ($arg =~ /^-/) {
+        # An unsupported standalone option.
+    } else {
+        # Some non-option argument has been given.
+        # Stop parsing options at this point.
+        push @commandLine, $arg;
+        $parsingOptions = 0;
+    }
+}
+
+# Was there a partial argument that was never completed?
+push @commandLine, $appendNextArg if ($appendNextArg);
+
+# Call the real Java header generator.
+my @fullCommandLine = ( $javaHeaderGen );
+push @fullCommandLine, @commandLine;
+exec @fullCommandLine or exit(1);
--- gcc-6-6.4.0.orig/debian/gcjh-wrapper-BV.1
+++ gcc-6-6.4.0/debian/gcjh-wrapper-BV.1
@@ -0,0 +1,20 @@
+.TH GCJH-WRAPPER 1 "June 6, 2002" gcjh-wrapper "Java User's Manual"
+.SH NAME
+gcjh-wrapper \- a wrapper around gcjh
+
+.SH SYNOPSIS
+gcjh-wrapper [\fB\s-1OPTION\s0\fR] ... [\fI\s-1ARGS\s0\fR...]
+
+.SH DESCRIPTION
+
+\fBgcjh-wrapper\fR is a wrapper around gcjh(1) to be called as the java header
+compiler. Options different for javah(1) and gcjh(1) are translated,
+options unknown to gcjh(1) are silently ignored.
+
+.SH OPTIONS
+See gcjh-@BV@(1) for a list of options that gcj understands.
+
+.SH "SEE ALSO"
+.BR gcjh-@BV@(1)
+,
+.BR javah(1)
--- gcc-6-6.4.0.orig/debian/gen-libstdc-breaks.sh
+++ gcc-6-6.4.0/debian/gen-libstdc-breaks.sh
@@ -0,0 +1,178 @@
+#! /bin/sh
+
+# https://bugs.debian.org/cgi-bin/pkgreport.cgi?tag=gcc-pr66145;users=debian-gcc@lists.debian.org
+
+vendor=Debian
+if dpkg-vendor --derives-from Ubuntu; then
+    vendor=Ubuntu
+fi
+
+if [ "$vendor" = Debian ]; then
+    :
+    pkgs=$(echo '
+antlr
+libaqsis1
+libassimp3
+blockattack
+boo
+libboost-date-time1.54.0
+libboost-date-time1.55.0
+libcpprest2.4
+printer-driver-brlaser
+c++-annotations
+clustalx
+libdavix0
+libdballe6
+dff
+libdiet-sed2.8
+libdiet-client2.8
+libdiet-admin2.8
+digikam-private-libs
+emscripten
+ergo
+fceux
+flush
+libfreefem++
+freeorion
+fslview
+fwbuilder
+libgazebo5
+libgetfem4++
+libgmsh2
+gnote
+gnudatalanguage
+python-healpy
+innoextract
+libinsighttoolkit4.7
+libdap17
+libdapclient6
+libdapserver7
+libkolabxml1
+libpqxx-4.0
+libreoffice-core
+librime1
+libwibble-dev
+lightspark
+libmarisa0
+mira-assembler
+mongodb
+mongodb-server
+ncbi-blast+
+libogre-1.8.0
+libogre-1.9.0
+openscad
+libopenwalnut1
+passepartout
+pdf2djvu
+photoprint
+plastimatch
+plee-the-bear
+povray
+powertop
+psi4
+python3-taglib
+realtimebattle
+ruby-passenger
+libapache2-mod-passenger
+schroot
+sqlitebrowser
+tecnoballz
+wesnoth-1.12-core
+widelands
+libwreport2
+xflr5
+libxmltooling6')
+else
+    pkgs=$(echo '
+antlr
+libaqsis1
+libassimp3
+blockattack
+boo
+libboost-date-time1.55.0
+libcpprest2.2
+printer-driver-brlaser
+c++-annotations
+chromium-browser
+clustalx
+libdavix0
+libdballe6
+dff
+libdiet-sed2.8
+libdiet-client2.8
+libdiet-admin2.8
+libkgeomap2
+libmediawiki1
+libkvkontakte1
+emscripten
+ergo
+fceux
+flush
+libfreefem++
+freeorion
+fslview
+fwbuilder
+libgazebo5
+libgetfem4++
+libgmsh2
+gnote
+gnudatalanguage
+python-healpy
+innoextract
+libinsighttoolkit4.6
+libdap17
+libdapclient6
+libdapserver7
+libkolabxml1
+libpqxx-4.0
+libreoffice-core
+librime1
+libwibble-dev
+lightspark
+libmarisa0
+mira-assembler
+mongodb
+mongodb-server
+ncbi-blast+
+libogre-1.8.0
+libogre-1.9.0
+openscad
+libopenwalnut1
+passepartout
+pdf2djvu
+photoprint
+plastimatch
+plee-the-bear
+povray
+powertop
+psi4
+python3-taglib
+realtimebattle
+ruby-passenger
+libapache2-mod-passenger
+sqlitebrowser
+tecnoballz
+wesnoth-1.12-core
+widelands
+libwreport2
+xflr5
+libxmltooling6')
+fi
+
+fn=debian/libstdc++-breaks.$vendor
+rm -f $fn
+echo $pkgs
+for p in $pkgs; do
+    #echo $p
+    if ! apt-cache show --no-all-versions $p >/dev/null; then
+	echo "not found: $p"
+    fi
+    v=$(apt-cache show --no-all-versions $p | awk '/^Version/ {print $2}')
+    case "$p" in
+    libboost-date-time*)
+      echo "$p," >> $fn
+      ;;
+    *)
+      echo "$p (<= $v)," >> $fn
+    esac
+done
--- gcc-6-6.4.0.orig/debian/gfortran-BV-CRB.preinst.in
+++ gcc-6-6.4.0/debian/gfortran-BV-CRB.preinst.in
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+set -e
+
+if [ "$1" = "upgrade" ] || [ "$1" = "configure" ]; then
+    update-alternatives --quiet --remove @TARGET@-gfortran /usr/bin/@TARGET@-gfortran-@BV@
+fi
+
+#DEBHELPER#
+
+exit 0
--- gcc-6-6.4.0.orig/debian/gfortran-BV-doc.doc-base
+++ gcc-6-6.4.0/debian/gfortran-BV-doc.doc-base
@@ -0,0 +1,14 @@
+Document: gfortran-@BV@
+Title: The GNU Fortran Compiler 
+Author: Various
+Abstract: This manual documents how to run, install and port `gfortran',
+ as well as its new features and incompatibilities, and how to report bugs.
+Section: Programming/Fortran
+
+Format: html
+Index: /usr/share/doc/gcc-@BV@-base/fortran/gfortran.html
+Files: /usr/share/doc/gcc-@BV@-base/fortran/gfortran.html
+
+Format: info
+Index: /usr/share/info/gfortran-@BV@.info.gz
+Files: /usr/share/info/gfortran-@BV@*
--- gcc-6-6.4.0.orig/debian/gij-hppa
+++ gcc-6-6.4.0/debian/gij-hppa
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+prctl=
+
+case "$(prctl --unaligned=)" in *signal)
+    echo >&2 "$(basename $0): ignore unaligned memory accesses"
+    prctl="prctl --unaligned=default"
+esac
+
+exec $prctl /usr/bin/gij-6.bin "$@"
--- gcc-6-6.4.0.orig/debian/gij-wrapper-BV
+++ gcc-6-6.4.0/debian/gij-wrapper-BV
@@ -0,0 +1,98 @@
+#!/usr/bin/perl -w
+#
+# Starts the GNU Java interpreter.
+#
+# Command-line arguments should be in the style of Sun's Java runtime;
+# these will be converted to gij arguments before being passed to the
+# gij itself.
+#
+# The Debian JNI module directory and any other specified JNI
+# directories will be included on the JNI search path.
+#
+# Copyright (C) 2002-2003 by Ben Burton <bab@debian.org>
+# Based on the original gij-wrapper-3.2 shell script.
+
+use strict;
+
+# The real Java runtime:
+my $javaRuntime = '/usr/bin/gij-@BV@';
+
+# The debian JNI module directory:
+my $debianJNIDir = '/usr/lib/jni';
+
+# The command-line arguments to pass to the real Java runtime:
+my @commandLine;
+
+# The full JNI search path to use:
+my $JNIPath = '';
+
+# Build the command-line from the arguments given.
+my $parsingOptions = 1;
+
+# Flag used to copy argument to -classpath or -cp.
+my $copyNext = 0;
+foreach my $arg (@ARGV) {
+  if (not $parsingOptions) {
+    # We're done parsing options; just copy all remaining arguments directly.
+    push @commandLine, $arg;
+    next;
+  }
+  if ($copyNext) {
+    push @commandLine, $arg;
+    $copyNext = 0;
+    next;
+  }
+
+  # Try to interpret Sun-style options.
+  if ($arg eq '-version') {
+    push @commandLine, '--version';
+  } elsif ($arg eq '-h' or $arg eq '-help') {
+    push @commandLine, '--help';
+  } elsif ($arg eq '-cp' or $arg eq '--cp') {
+    push @commandLine, '-cp';
+    $copyNext = 1;
+  } elsif ($arg eq '-classpath' or $arg eq '--classpath') {
+    push @commandLine, '-classpath';
+    $copyNext = 1;
+  } elsif ($arg =~ /^-Djava.library.path=(.+)$/) {
+    # A component of the JNI search path has been given.
+    if ($JNIPath) {
+      $JNIPath = $JNIPath . ':' . $1;
+    } else {
+      $JNIPath = $1;
+    }
+  } elsif ($arg eq '-jar' or $arg =~ /^-D/) {
+    # Copy the argument directly.
+    push @commandLine, $arg;
+  } elsif ($arg =~ /^-/) {
+    # An unrecognised option has been passed - just drop it.
+  } else {
+    # Some non-option argument has been given.
+    # Stop parsing options at this point.
+    push @commandLine, $arg;
+    $parsingOptions = 0;
+  }
+}
+
+# Add the debian JNI module directory to the JNI search path if it's not
+# already there.
+if ($JNIPath !~ /(^|:)$debianJNIDir($|:)/) {
+  if ($JNIPath) {
+    $JNIPath = $JNIPath . ':' . $debianJNIDir;
+  } else {
+    $JNIPath = $debianJNIDir;
+  }
+}
+
+# Use environment variable $LTDL_LIBRARY_PATH to store the JNI path,
+# since gij uses libltdl to dlopen JNI modules.
+if ($ENV{LTDL_LIBRARY_PATH}) {
+    $ENV{LTDL_LIBRARY_PATH} = $ENV{LTDL_LIBRARY_PATH} . ':' . $JNIPath;
+} else {
+    $ENV{LTDL_LIBRARY_PATH} = $JNIPath;
+}
+
+# Call the real Java runtime.
+my @fullCommandLine = ( $javaRuntime );
+push @fullCommandLine, @commandLine;
+exec @fullCommandLine or exit(1);
--- gcc-6-6.4.0.orig/debian/gij-wrapper-BV.1
+++ gcc-6-6.4.0/debian/gij-wrapper-BV.1
@@ -0,0 +1,22 @@
+.TH GIJ-WRAPPER 1 "August 11, 2001" gij-wrapper "Java User's Manual"
+.SH NAME
+gij-wrapper \- a wrapper around gij
+
+.SH SYNOPSIS
+gij-wrapper [\fB\s-1OPTION\s0\fR] ... \fI\s-1JARFILE\s0\fR [\fI\s-1ARGS\s0\fR...]
+.PP
+gij-wrapper [\fB\-jar\fR] [\fB\s-1OPTION\s0\fR] ... \fI\s-1CLASS\s0\fR [\fI\s-1ARGS\s0\fR...]
+
+.SH DESCRIPTION
+
+\fBgij-wrapper\fR is a wrapper around gij(1) to be called as the java
+interpreter. Options different for java(1) and gij(1) are translated,
+options unknown to gij(1) are silently ignored.
+
+.SH OPTIONS
+See gij-@BV@(1) for a list of options that gij understands.
+
+.SH "SEE ALSO"
+.BR gij-@BV@(1)
+,
+.BR java(1)
--- gcc-6-6.4.0.orig/debian/gnat-BV-doc.doc-base.rm
+++ gcc-6-6.4.0/debian/gnat-BV-doc.doc-base.rm
@@ -0,0 +1,16 @@
+Document: gnat-rm-@BV@
+Title: GNAT (GNU Ada) Reference Manual
+Author: Various
+Abstract: This manual contains useful information in writing programs
+ using the GNAT compiler.  It includes information on implementation
+ dependent characteristics of GNAT, including all the information
+ required by Annex M of the standard.
+Section: Programming/Ada
+
+Format: html
+Index: /usr/share/doc/gnat-@BV@-doc/gnat_rm.html
+Files: /usr/share/doc/gnat-@BV@-doc/gnat_rm.html
+
+Format: info
+Index: /usr/share/info/gnat_rm-@BV@.info.gz
+Files: /usr/share/info/gnat_rm-@BV@*
--- gcc-6-6.4.0.orig/debian/gnat-BV-doc.doc-base.style
+++ gcc-6-6.4.0/debian/gnat-BV-doc.doc-base.style
@@ -0,0 +1,16 @@
+Document: gnat-style-@BV@
+Title: GNAT Coding Style
+Author: Various
+Abstract: Most of GNAT is written in Ada using a consistent style to
+ ensure readability of the code.  This document has been written to
+ help maintain this consistent style, while having a large group of
+ developers work on the compiler.
+Section: Programming/Ada
+
+Format: html
+Index: /usr/share/doc/gnat-@BV@-doc/gnat-style.html
+Files: /usr/share/doc/gnat-@BV@-doc/gnat-style.html
+
+Format: info
+Index: /usr/share/info/gnat-style-@BV@.info.gz
+Files: /usr/share/info/gnat-style-@BV@*
--- gcc-6-6.4.0.orig/debian/gnat-BV-doc.doc-base.ug
+++ gcc-6-6.4.0/debian/gnat-BV-doc.doc-base.ug
@@ -0,0 +1,16 @@
+Document: gnat-ugn-@BV@
+Title: GNAT User's Guide for Unix Platforms
+Author: Various
+Abstract: This guide describes the use of GNAT, a compiler and
+ software development toolset for the full Ada 95 programming language.
+ It describes the features of the compiler and tools, and details how
+ to use them to build Ada 95 applications.
+Section: Programming/Ada
+
+Format: html
+Index: /usr/share/doc/gnat-@BV@-doc/gnat_ugn.html
+Files: /usr/share/doc/gnat-@BV@-doc/gnat_ugn.html
+
+Format: info
+Index: /usr/share/info/gnat_ugn-@BV@.info.gz
+Files: /usr/share/info/gnat_ugn-@BV@*
--- gcc-6-6.4.0.orig/debian/gnat-BV.overrides
+++ gcc-6-6.4.0/debian/gnat-BV.overrides
@@ -0,0 +1 @@
+gnat-@BV@ binary: quilt-build-dep-but-no-series-file
--- gcc-6-6.4.0.orig/debian/gnat.1
+++ gcc-6-6.4.0/debian/gnat.1
@@ -0,0 +1,43 @@
+.\" Hey, Emacs!  This is an -*- nroff -*- source file.
+.\"
+.\" Copyright (C) 1996 Erick Branderhorst <branderh@debian.org>
+.\" Copyright (C) 2011 Nicolas Boulenguez <nicolas.boulenguez@free.fr>
+.\"
+.\" This is free software; you can redistribute it and/or modify it under
+.\" the terms of the GNU General Public License as published by the Free
+.\" Software Foundation; either version 2, or (at your option) any later
+.\" version.
+.\"
+.\" This is distributed in the hope that it will be useful, but WITHOUT
+.\" ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+.\" FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+.\" for more details.
+.\"
+.\" You should have received a copy of the GNU General Public License with
+.\" your Debian GNU/Linux system, in /usr/doc/copyright/GPL, or with the
+.\" dpkg source package as the file COPYING.  If not, write to the Free
+.\" Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+.\"
+.\"
+.TH "GNAT TOOLBOX" 1 "Jun 2002" "Debian Project" "Debian Linux"
+.SH NAME
+gnat, gnatbind, gnatbl, gnatchop, gnatfind, gnathtml, gnatkr, gnatlink,
+gnatls, gnatmake, gnatprep, gnatpsta, gnatpsys, gnatxref \-
+GNAT toolbox
+.SH DESCRIPTION
+Those programs are part of GNU GNAT, a freely available Ada 95 compiler.
+.PP
+For accessing the full GNAT manuals, use
+.B info gnat-ug-4.8
+and
+.B info gnat-rm-4.8
+for the sections related to the reference manual.
+If those sections cannot be found, you will have to install the
+gnat-4.4-doc package as well (since these manuals contain invariant parts,
+the package is located in the non-free part of the Debian archive).
+You may also browse
+.B http://gcc.gnu.org/onlinedocs
+which provides the GCC online documentation.
+.SH AUTHOR
+This manpage has been written by Samuel Tardieu <sam@debian.org>, for the
+Debian GNU/Linux project.
--- gcc-6-6.4.0.orig/debian/gnatprj.gpr
+++ gcc-6-6.4.0/debian/gnatprj.gpr
@@ -0,0 +1,32 @@
+--  Project file for use with GNAT
+--  Copyright (c) 2005, 2008 Ludovic Brenta <ludovic@ludovic-brenta.org>
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  This project file is designed to help build applications that use
+--  GNAT project files.  Here is an example of how to use this project file:
+--
+--  with "gnatprj";
+--  project Example is
+--     for Object_Dir use "obj";
+--     for Exec_Dir use ".";
+--     for Main use ("example");
+--  end Example;
+
+with "gnatvsn.gpr";
+project Gnatprj is
+   for Library_Name use "gnatprj";
+   for Library_Dir use "/usr/lib";
+   for Library_Kind use "dynamic";
+   for Source_Dirs use ("/usr/share/ada/adainclude/gnatprj");
+   for Library_ALI_Dir use "/usr/lib/ada/adalib/gnatprj";
+   for Externally_Built use "true";
+end Gnatprj;
--- gcc-6-6.4.0.orig/debian/gnatvsn.gpr
+++ gcc-6-6.4.0/debian/gnatvsn.gpr
@@ -0,0 +1,31 @@
+--  Project file for use with GNAT
+--  Copyright (c) 2005, 2008 Ludovic Brenta <ludovic@ludovic-brenta.org>
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  This project file is designed to help build applications that use
+--  GNAT project files.  Here is an example of how to use this project file:
+--
+--  with "gnatvsn";
+--  project Example is
+--     for Object_Dir use "obj";
+--     for Exec_Dir use ".";
+--     for Main use ("example");
+--  end Example;
+
+project Gnatvsn is
+   for Library_Name use "gnatvsn";
+   for Library_Dir use "/usr/lib";
+   for Library_Kind use "dynamic";
+   for Source_Dirs use ("/usr/share/ada/adainclude/gnatvsn");
+   for Library_ALI_Dir use "/usr/lib/ada/adalib/gnatvsn";
+   for Externally_Built use "true";
+end Gnatvsn;
--- gcc-6-6.4.0.orig/debian/go-relocation-test-gcc620-sparc64.obj.uue
+++ gcc-6-6.4.0/debian/go-relocation-test-gcc620-sparc64.obj.uue
@@ -0,0 +1,136 @@
+begin 644 src/libgo/go/debug/elf/testdata/go-relocation-test-gcc620-sparc64.obj
+M?T5,1@("`0`````````````!`"L````!````````````````````````````
+M`!(``````@!```````!``!4`$IWCOU""$``8\G>HA\(GJ'\#````D!!@`$``
+M```!`````0```('/X`@!`````````&AE;&QO+"!W;W)L9`````-"``0`````
+M"`$`````#```````````````````````````````+``````"``````+8````
+M.`,(!P`````#`0@``````P('``````,$!P`````#`08``````P(%``````0$
+M!6EN=``#"`4``````@`````#@P```&D"``````.$````:0,(!P`````%"`8(
+M````E0,!!@`````'````E0@`````V`3Q```"'@D`````!/(```!B``D`````
+M!/<```"/"`D`````!/@```"/$`D`````!/D```"/&`D`````!/H```"/(`D`
+M````!/L```"/*`D`````!/P```"/,`D`````!/T```"/.`D`````!/X```"/
+M0`H`````!`$`````CT@*``````0!`0```(]0"@`````$`0(```"/6`H`````
+M!`$$```"5F`*``````0!!@```EQH"@`````$`0@```!B<`H`````!`$,````
+M8G0*``````0!#@```'!X"@`````$`1(```!&@`H`````!`$3````5((*````
+M``0!%````F*#"@`````$`1@```)RB`H`````!`$A````>Y`*``````0!*0``
+M`(V8"@`````$`2H```"-H`H`````!`$K````C:@*``````0!+````(VP"@``
+M```$`2X````MN`H`````!`$O````8L`*``````0!,0```GC$``L`````!)8(
+M`````!@$G````E8)``````2=```"5@`)``````2>```"7`@)``````2B````
+M8A``!@@```(E!@@```"A#````)4```)R#0```(8```8(```"'@P```"5```"
+MB`T```"&$P`.``````\`````!`$[```"B`\`````!`$\```"B`\`````!`$]
+M```"B`8(````G`<```*Q$``````%J@```EP0``````6K```"7!``````!:P`
+M``)<$``````&&@```&(,```"MP```O,1``<```+H$``````&&P```O,2````
+M``$$````````````````````+`&<```#/Q,``````00```!B`Y&``1,`````
+M`00```,_`Y&(`0`&"````(\``1$!)0X3"P,.&PX1`1('$!<```(6``,..@L[
+M"TD3```#)``+"SX+`PX```0D``L+/@L#"```!0\`"PL```8/``L+21,```<F
+M`$D3```($P$##@L+.@L["P$3```)#0`##CH+.PM)$S@+```*#0`##CH+.P5)
+M$S@+```+%@`##CH+.PL```P!`4D3`1,```TA`$D3+PL```X3``,./!D```\T
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+,`````0``````````
+`
+end
--- gcc-6-6.4.0.orig/debian/jdb.sh
+++ gcc-6-6.4.0/debian/jdb.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+# Placeholder script to fake a
+# JDK compatible JAVA_HOME directory.
+
+echo >&2 "This script is only a placeholder."
+echo >&2 "Some programs need a JDK rather than only a JRE to work."
+echo >&2 "They test for this tool to detect a JDK installation, but"
+echo >&2 "don't really need its functionality to work correctly."
--- gcc-6-6.4.0.orig/debian/lib32asan3.overrides
+++ gcc-6-6.4.0/debian/lib32asan3.overrides
@@ -0,0 +1,2 @@
+# automake gets it wrong for the multilib build
+lib32asan3 binary: binary-or-shlib-defines-rpath
--- gcc-6-6.4.0.orig/debian/lib32asan3.symbols
+++ gcc-6-6.4.0/debian/lib32asan3.symbols
@@ -0,0 +1,3 @@
+libasan.so.3 lib32asan3 #MINVER#
+#include "libasan.symbols.common"
+#include "libasan.symbols.32"
--- gcc-6-6.4.0.orig/debian/lib32gccLC.postinst
+++ gcc-6-6.4.0/debian/lib32gccLC.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/lib32gcc@LC@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcc-@BV@-base $docdir
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/lib32gphobos68.lintian-overrides
+++ gcc-6-6.4.0/debian/lib32gphobos68.lintian-overrides
@@ -0,0 +1,2 @@
+# no usable zconf.h header in lib32z1-dev
+lib32gphobos68 binary: embedded-library
--- gcc-6-6.4.0.orig/debian/lib32stdc++6.symbols.amd64
+++ gcc-6-6.4.0/debian/lib32stdc++6.symbols.amd64
@@ -0,0 +1,14 @@
+libstdc++.so.6 lib32stdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+#(optional)_Z16__VLTRegisterSetPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z17__VLTRegisterPairPPvPKvjS2_@CXXABI_1.3.8 4.9.0
+#(optional)_Z21__VLTRegisterSetDebugPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z22__VLTRegisterPairDebugPPvPKvjS2_PKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)_Z24__VLTVerifyVtablePointerPPvPKv@CXXABI_1.3.8 4.9.0
+#(optional)_Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)__VLTChangePermission@CXXABI_1.3.8 4.9.0
--- gcc-6-6.4.0.orig/debian/lib32stdc++6.symbols.kfreebsd-amd64
+++ gcc-6-6.4.0/debian/lib32stdc++6.symbols.kfreebsd-amd64
@@ -0,0 +1,7 @@
+libstdc++.so.6 lib32stdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.4.0.orig/debian/lib32stdc++6.symbols.ppc64
+++ gcc-6-6.4.0/debian/lib32stdc++6.symbols.ppc64
@@ -0,0 +1,9 @@
+libstdc++.so.6 lib32stdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.4.0.orig/debian/lib32stdc++6.symbols.s390x
+++ gcc-6-6.4.0/debian/lib32stdc++6.symbols.s390x
@@ -0,0 +1,558 @@
+libstdc++.so.6 lib32stdc++6 #MINVER#
+#include "libstdc++6.symbols.common"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.f128"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEm@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEm@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx9free_list6_M_getEm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNK10__cxxabiv117__class_type_info12__do_dyncastEiNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__class_type_info20__do_find_public_srcEiPKvPKS0_S2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4copyEPwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE6substrEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmRKS2_@GLIBCXX_3.4 4.1.1
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+ _ZNSi7getlineEPcic@GLIBCXX_3.4 4.1.1
+ _ZNSi8readsomeEPci@GLIBCXX_3.4 4.1.1
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+ _ZNSs7_M_copyEPcPKcm@GLIBCXX_3.4 4.1.1
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+ _ZNSt10istrstreamC2EPKci@GLIBCXX_3.4 4.1.1
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+ _ZNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4 4.1.1
+ _ZNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4 4.1.1
+ _ZSt11_Hash_bytesPKvmm@CXXABI_1.3.5 4.6
+ _ZSt15_Fnv_hash_bytesPKvmm@CXXABI_1.3.5 4.6
+ _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_i@GLIBCXX_3.4.9 4.2.1
+ _ZSt16__ostream_insertIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKS3_i@GLIBCXX_3.4.9 4.2.1
+ _ZSt17__copy_streambufsIcSt11char_traitsIcEEiPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.6 4.1.1
+ _ZSt17__copy_streambufsIwSt11char_traitsIwEEiPSt15basic_streambufIT_T0_ES6_@GLIBCXX_3.4.6 4.1.1
+ _ZSt17__verify_groupingPKcmRKSs@GLIBCXX_3.4.10 4.3
+ _ZSt21__copy_streambufs_eofIcSt11char_traitsIcEEiPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
+ _ZSt21__copy_streambufs_eofIwSt11char_traitsIwEEiPSt15basic_streambufIT_T0_ES6_Rb@GLIBCXX_3.4.9 4.2.1
+ _ZThn8_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSiD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSiD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSoD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSoD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10istrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10istrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10ostrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10ostrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _Znam@GLIBCXX_3.4 4.1.1
+ _ZnamRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _Znwm@GLIBCXX_3.4 4.1.1
+ _ZnwmRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit.s390"
+ _ZNSt12__basic_fileIcEC1EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcEC2EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
--- gcc-6-6.4.0.orig/debian/lib32stdc++6.symbols.sparc64
+++ gcc-6-6.4.0/debian/lib32stdc++6.symbols.sparc64
@@ -0,0 +1,9 @@
+libstdc++.so.6 lib32stdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.4.0.orig/debian/lib32stdc++CXX.postinst
+++ gcc-6-6.4.0/debian/lib32stdc++CXX.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/lib32stdc++@CXX@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcc-@BV@-base $docdir
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/lib64asan3.overrides
+++ gcc-6-6.4.0/debian/lib64asan3.overrides
@@ -0,0 +1,2 @@
+# automake gets it wrong for the multilib build
+lib64asan3 binary: binary-or-shlib-defines-rpath
--- gcc-6-6.4.0.orig/debian/lib64asan3.symbols
+++ gcc-6-6.4.0/debian/lib64asan3.symbols
@@ -0,0 +1,3 @@
+libasan.so.3 lib64asan3 #MINVER#
+#include "libasan.symbols.common"
+#include "libasan.symbols.64"
--- gcc-6-6.4.0.orig/debian/lib64gccLC.postinst
+++ gcc-6-6.4.0/debian/lib64gccLC.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/lib64gcc@LC@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcc-@BV@-base $docdir
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/lib64gphobos68.lintian-overrides
+++ gcc-6-6.4.0/debian/lib64gphobos68.lintian-overrides
@@ -0,0 +1,2 @@
+# no usable zconf.h header in lib64z1-dev
+lib64gphobos68 binary: embedded-library
--- gcc-6-6.4.0.orig/debian/lib64stdc++6.symbols.i386
+++ gcc-6-6.4.0/debian/lib64stdc++6.symbols.i386
@@ -0,0 +1,40 @@
+libstdc++.so.6 lib64stdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# acosl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# asinl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# atan2l@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# atanl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# ceill@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# coshl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# cosl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# expl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# floorl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# fmodl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# frexpl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# hypotl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# ldexpf@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# ldexpl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# log10l@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# logl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# modfl@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# powf@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# powl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# sinhl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# sinl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# sqrtl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# tanhl@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# tanl@GLIBCXX_3.4 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+#(optional)_Z16__VLTRegisterSetPPvPKvmmS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z17__VLTRegisterPairPPvPKvmS2_@CXXABI_1.3.8 4.9.0
+#(optional)_Z21__VLTRegisterSetDebugPPvPKvmmS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z22__VLTRegisterPairDebugPPvPKvmS2_PKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)_Z24__VLTVerifyVtablePointerPPvPKv@CXXABI_1.3.8 4.9.0
+#(optional)_Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)__VLTChangePermission@CXXABI_1.3.8 4.9.0
--- gcc-6-6.4.0.orig/debian/lib64stdc++6.symbols.powerpc
+++ gcc-6-6.4.0/debian/lib64stdc++6.symbols.powerpc
@@ -0,0 +1,11 @@
+libstdc++.so.6 lib64stdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.f128"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.64bit"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.4.0.orig/debian/lib64stdc++6.symbols.s390
+++ gcc-6-6.4.0/debian/lib64stdc++6.symbols.s390
@@ -0,0 +1,12 @@
+libstdc++.so.6 lib64stdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# ldexpf@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# powf@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.64bit"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.4.0.orig/debian/lib64stdc++6.symbols.sparc
+++ gcc-6-6.4.0/debian/lib64stdc++6.symbols.sparc
@@ -0,0 +1,11 @@
+libstdc++.so.6 lib64stdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVli@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVli@GLIBCXX_3.4 4.1.1
+# FIXME: Currently no ldbl symbols in the 64bit libstdc++ on sparc.
+# #include "libstdc++6.symbols.ldbl.64bit"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.4.0.orig/debian/lib64stdc++CXX.postinst
+++ gcc-6-6.4.0/debian/lib64stdc++CXX.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/lib64stdc++@CXX@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcc-@BV@-base $docdir
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/libasan.symbols.16
+++ gcc-6-6.4.0/debian/libasan.symbols.16
@@ -0,0 +1,38 @@
+ __sanitizer_syscall_post_impl_chown16@Base 5
+ __sanitizer_syscall_post_impl_fchown16@Base 5
+ __sanitizer_syscall_post_impl_getegid16@Base 5
+ __sanitizer_syscall_post_impl_geteuid16@Base 5
+ __sanitizer_syscall_post_impl_getgid16@Base 5
+ __sanitizer_syscall_post_impl_getgroups16@Base 5
+ __sanitizer_syscall_post_impl_getresgid16@Base 5
+ __sanitizer_syscall_post_impl_getresuid16@Base 5
+ __sanitizer_syscall_post_impl_getuid16@Base 5
+ __sanitizer_syscall_post_impl_lchown16@Base 5
+ __sanitizer_syscall_post_impl_setfsgid16@Base 5
+ __sanitizer_syscall_post_impl_setfsuid16@Base 5
+ __sanitizer_syscall_post_impl_setgid16@Base 5
+ __sanitizer_syscall_post_impl_setgroups16@Base 5
+ __sanitizer_syscall_post_impl_setregid16@Base 5
+ __sanitizer_syscall_post_impl_setresgid16@Base 5
+ __sanitizer_syscall_post_impl_setresuid16@Base 5
+ __sanitizer_syscall_post_impl_setreuid16@Base 5
+ __sanitizer_syscall_post_impl_setuid16@Base 5
+ __sanitizer_syscall_pre_impl_chown16@Base 5
+ __sanitizer_syscall_pre_impl_fchown16@Base 5
+ __sanitizer_syscall_pre_impl_getegid16@Base 5
+ __sanitizer_syscall_pre_impl_geteuid16@Base 5
+ __sanitizer_syscall_pre_impl_getgid16@Base 5
+ __sanitizer_syscall_pre_impl_getgroups16@Base 5
+ __sanitizer_syscall_pre_impl_getresgid16@Base 5
+ __sanitizer_syscall_pre_impl_getresuid16@Base 5
+ __sanitizer_syscall_pre_impl_getuid16@Base 5
+ __sanitizer_syscall_pre_impl_lchown16@Base 5
+ __sanitizer_syscall_pre_impl_setfsgid16@Base 5
+ __sanitizer_syscall_pre_impl_setfsuid16@Base 5
+ __sanitizer_syscall_pre_impl_setgid16@Base 5
+ __sanitizer_syscall_pre_impl_setgroups16@Base 5
+ __sanitizer_syscall_pre_impl_setregid16@Base 5
+ __sanitizer_syscall_pre_impl_setresgid16@Base 5
+ __sanitizer_syscall_pre_impl_setresuid16@Base 5
+ __sanitizer_syscall_pre_impl_setreuid16@Base 5
+ __sanitizer_syscall_pre_impl_setuid16@Base 5
--- gcc-6-6.4.0.orig/debian/libasan.symbols.32
+++ gcc-6-6.4.0/debian/libasan.symbols.32
@@ -0,0 +1,6 @@
+ _ZdaPvj@Base 5
+ _ZdlPvj@Base 5
+ _Znaj@Base 4.8
+ _ZnajRKSt9nothrow_t@Base 4.8
+ _Znwj@Base 4.8
+ _ZnwjRKSt9nothrow_t@Base 4.8
--- gcc-6-6.4.0.orig/debian/libasan.symbols.64
+++ gcc-6-6.4.0/debian/libasan.symbols.64
@@ -0,0 +1,8 @@
+ __interceptor_shmctl@Base 4.9
+ _ZdaPvm@Base 5
+ _ZdlPvm@Base 5
+ _Znam@Base 4.8
+ _ZnamRKSt9nothrow_t@Base 4.8
+ _Znwm@Base 4.8
+ _ZnwmRKSt9nothrow_t@Base 4.8
+ shmctl@Base 4.9
--- gcc-6-6.4.0.orig/debian/libasan.symbols.common
+++ gcc-6-6.4.0/debian/libasan.symbols.common
@@ -0,0 +1,1600 @@
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+ _ZdaPv@Base 4.8
+ _ZdaPvRKSt9nothrow_t@Base 4.8
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+ __sanitizer_syscall_post_impl_unshare@Base 4.9
+ __sanitizer_syscall_post_impl_uselib@Base 4.9
+ __sanitizer_syscall_post_impl_ustat@Base 4.9
+ __sanitizer_syscall_post_impl_utime@Base 4.9
+ __sanitizer_syscall_post_impl_utimensat@Base 4.9
+ __sanitizer_syscall_post_impl_utimes@Base 4.9
+ __sanitizer_syscall_post_impl_vfork@Base 4.9
+ __sanitizer_syscall_post_impl_vhangup@Base 4.9
+ __sanitizer_syscall_post_impl_vmsplice@Base 4.9
+ __sanitizer_syscall_post_impl_wait4@Base 4.9
+ __sanitizer_syscall_post_impl_waitid@Base 4.9
+ __sanitizer_syscall_post_impl_waitpid@Base 4.9
+ __sanitizer_syscall_post_impl_write@Base 4.9
+ __sanitizer_syscall_post_impl_writev@Base 4.9
+ __sanitizer_syscall_pre_impl_accept4@Base 4.9
+ __sanitizer_syscall_pre_impl_accept@Base 4.9
+ __sanitizer_syscall_pre_impl_access@Base 4.9
+ __sanitizer_syscall_pre_impl_acct@Base 4.9
+ __sanitizer_syscall_pre_impl_add_key@Base 4.9
+ __sanitizer_syscall_pre_impl_adjtimex@Base 4.9
+ __sanitizer_syscall_pre_impl_alarm@Base 4.9
+ __sanitizer_syscall_pre_impl_bdflush@Base 4.9
+ __sanitizer_syscall_pre_impl_bind@Base 4.9
+ __sanitizer_syscall_pre_impl_brk@Base 4.9
+ __sanitizer_syscall_pre_impl_capget@Base 4.9
+ __sanitizer_syscall_pre_impl_capset@Base 4.9
+ __sanitizer_syscall_pre_impl_chdir@Base 4.9
+ __sanitizer_syscall_pre_impl_chmod@Base 4.9
+ __sanitizer_syscall_pre_impl_chown@Base 4.9
+ __sanitizer_syscall_pre_impl_chroot@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_adjtime@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_getres@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_gettime@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_nanosleep@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_settime@Base 4.9
+ __sanitizer_syscall_pre_impl_close@Base 4.9
+ __sanitizer_syscall_pre_impl_connect@Base 4.9
+ __sanitizer_syscall_pre_impl_creat@Base 4.9
+ __sanitizer_syscall_pre_impl_delete_module@Base 4.9
+ __sanitizer_syscall_pre_impl_dup2@Base 4.9
+ __sanitizer_syscall_pre_impl_dup3@Base 4.9
+ __sanitizer_syscall_pre_impl_dup@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_create1@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_create@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_ctl@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_pwait@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_wait@Base 4.9
+ __sanitizer_syscall_pre_impl_eventfd2@Base 4.9
+ __sanitizer_syscall_pre_impl_eventfd@Base 4.9
+ __sanitizer_syscall_pre_impl_exit@Base 4.9
+ __sanitizer_syscall_pre_impl_exit_group@Base 4.9
+ __sanitizer_syscall_pre_impl_faccessat@Base 4.9
+ __sanitizer_syscall_pre_impl_fchdir@Base 4.9
+ __sanitizer_syscall_pre_impl_fchmod@Base 4.9
+ __sanitizer_syscall_pre_impl_fchmodat@Base 4.9
+ __sanitizer_syscall_pre_impl_fchown@Base 4.9
+ __sanitizer_syscall_pre_impl_fchownat@Base 4.9
+ __sanitizer_syscall_pre_impl_fcntl64@Base 4.9
+ __sanitizer_syscall_pre_impl_fcntl@Base 4.9
+ __sanitizer_syscall_pre_impl_fdatasync@Base 4.9
+ __sanitizer_syscall_pre_impl_fgetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_flistxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_flock@Base 4.9
+ __sanitizer_syscall_pre_impl_fork@Base 4.9
+ __sanitizer_syscall_pre_impl_fremovexattr@Base 4.9
+ __sanitizer_syscall_pre_impl_fsetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_fstat64@Base 4.9
+ __sanitizer_syscall_pre_impl_fstat@Base 4.9
+ __sanitizer_syscall_pre_impl_fstatat64@Base 4.9
+ __sanitizer_syscall_pre_impl_fstatfs64@Base 4.9
+ __sanitizer_syscall_pre_impl_fstatfs@Base 4.9
+ __sanitizer_syscall_pre_impl_fsync@Base 4.9
+ __sanitizer_syscall_pre_impl_ftruncate@Base 4.9
+ __sanitizer_syscall_pre_impl_futimesat@Base 4.9
+ __sanitizer_syscall_pre_impl_get_mempolicy@Base 4.9
+ __sanitizer_syscall_pre_impl_get_robust_list@Base 4.9
+ __sanitizer_syscall_pre_impl_getcpu@Base 4.9
+ __sanitizer_syscall_pre_impl_getcwd@Base 4.9
+ __sanitizer_syscall_pre_impl_getdents64@Base 4.9
+ __sanitizer_syscall_pre_impl_getdents@Base 4.9
+ __sanitizer_syscall_pre_impl_getegid@Base 4.9
+ __sanitizer_syscall_pre_impl_geteuid@Base 4.9
+ __sanitizer_syscall_pre_impl_getgid@Base 4.9
+ __sanitizer_syscall_pre_impl_getgroups@Base 4.9
+ __sanitizer_syscall_pre_impl_gethostname@Base 4.9
+ __sanitizer_syscall_pre_impl_getitimer@Base 4.9
+ __sanitizer_syscall_pre_impl_getpeername@Base 4.9
+ __sanitizer_syscall_pre_impl_getpgid@Base 4.9
+ __sanitizer_syscall_pre_impl_getpgrp@Base 4.9
+ __sanitizer_syscall_pre_impl_getpid@Base 4.9
+ __sanitizer_syscall_pre_impl_getppid@Base 4.9
+ __sanitizer_syscall_pre_impl_getpriority@Base 4.9
+ __sanitizer_syscall_pre_impl_getresgid@Base 4.9
+ __sanitizer_syscall_pre_impl_getresuid@Base 4.9
+ __sanitizer_syscall_pre_impl_getrlimit@Base 4.9
+ __sanitizer_syscall_pre_impl_getrusage@Base 4.9
+ __sanitizer_syscall_pre_impl_getsid@Base 4.9
+ __sanitizer_syscall_pre_impl_getsockname@Base 4.9
+ __sanitizer_syscall_pre_impl_getsockopt@Base 4.9
+ __sanitizer_syscall_pre_impl_gettid@Base 4.9
+ __sanitizer_syscall_pre_impl_gettimeofday@Base 4.9
+ __sanitizer_syscall_pre_impl_getuid@Base 4.9
+ __sanitizer_syscall_pre_impl_getxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_init_module@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_add_watch@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_init1@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_init@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_rm_watch@Base 4.9
+ __sanitizer_syscall_pre_impl_io_cancel@Base 4.9
+ __sanitizer_syscall_pre_impl_io_destroy@Base 4.9
+ __sanitizer_syscall_pre_impl_io_getevents@Base 4.9
+ __sanitizer_syscall_pre_impl_io_setup@Base 4.9
+ __sanitizer_syscall_pre_impl_io_submit@Base 4.9
+ __sanitizer_syscall_pre_impl_ioctl@Base 4.9
+ __sanitizer_syscall_pre_impl_ioperm@Base 4.9
+ __sanitizer_syscall_pre_impl_ioprio_get@Base 4.9
+ __sanitizer_syscall_pre_impl_ioprio_set@Base 4.9
+ __sanitizer_syscall_pre_impl_ipc@Base 4.9
+ __sanitizer_syscall_pre_impl_kexec_load@Base 4.9
+ __sanitizer_syscall_pre_impl_keyctl@Base 4.9
+ __sanitizer_syscall_pre_impl_kill@Base 4.9
+ __sanitizer_syscall_pre_impl_lchown@Base 4.9
+ __sanitizer_syscall_pre_impl_lgetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_link@Base 4.9
+ __sanitizer_syscall_pre_impl_linkat@Base 4.9
+ __sanitizer_syscall_pre_impl_listen@Base 4.9
+ __sanitizer_syscall_pre_impl_listxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_llistxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_llseek@Base 4.9
+ __sanitizer_syscall_pre_impl_lookup_dcookie@Base 4.9
+ __sanitizer_syscall_pre_impl_lremovexattr@Base 4.9
+ __sanitizer_syscall_pre_impl_lseek@Base 4.9
+ __sanitizer_syscall_pre_impl_lsetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_lstat64@Base 4.9
+ __sanitizer_syscall_pre_impl_lstat@Base 4.9
+ __sanitizer_syscall_pre_impl_madvise@Base 4.9
+ __sanitizer_syscall_pre_impl_mbind@Base 4.9
+ __sanitizer_syscall_pre_impl_migrate_pages@Base 4.9
+ __sanitizer_syscall_pre_impl_mincore@Base 4.9
+ __sanitizer_syscall_pre_impl_mkdir@Base 4.9
+ __sanitizer_syscall_pre_impl_mkdirat@Base 4.9
+ __sanitizer_syscall_pre_impl_mknod@Base 4.9
+ __sanitizer_syscall_pre_impl_mknodat@Base 4.9
+ __sanitizer_syscall_pre_impl_mlock@Base 4.9
+ __sanitizer_syscall_pre_impl_mlockall@Base 4.9
+ __sanitizer_syscall_pre_impl_mmap_pgoff@Base 4.9
+ __sanitizer_syscall_pre_impl_mount@Base 4.9
+ __sanitizer_syscall_pre_impl_move_pages@Base 4.9
+ __sanitizer_syscall_pre_impl_mprotect@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_getsetattr@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_notify@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_open@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_timedreceive@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_timedsend@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_unlink@Base 4.9
+ __sanitizer_syscall_pre_impl_mremap@Base 4.9
+ __sanitizer_syscall_pre_impl_msgctl@Base 4.9
+ __sanitizer_syscall_pre_impl_msgget@Base 4.9
+ __sanitizer_syscall_pre_impl_msgrcv@Base 4.9
+ __sanitizer_syscall_pre_impl_msgsnd@Base 4.9
+ __sanitizer_syscall_pre_impl_msync@Base 4.9
+ __sanitizer_syscall_pre_impl_munlock@Base 4.9
+ __sanitizer_syscall_pre_impl_munlockall@Base 4.9
+ __sanitizer_syscall_pre_impl_munmap@Base 4.9
+ __sanitizer_syscall_pre_impl_name_to_handle_at@Base 4.9
+ __sanitizer_syscall_pre_impl_nanosleep@Base 4.9
+ __sanitizer_syscall_pre_impl_newfstat@Base 4.9
+ __sanitizer_syscall_pre_impl_newfstatat@Base 4.9
+ __sanitizer_syscall_pre_impl_newlstat@Base 4.9
+ __sanitizer_syscall_pre_impl_newstat@Base 4.9
+ __sanitizer_syscall_pre_impl_newuname@Base 4.9
+ __sanitizer_syscall_pre_impl_ni_syscall@Base 4.9
+ __sanitizer_syscall_pre_impl_nice@Base 4.9
+ __sanitizer_syscall_pre_impl_old_getrlimit@Base 4.9
+ __sanitizer_syscall_pre_impl_old_mmap@Base 4.9
+ __sanitizer_syscall_pre_impl_old_readdir@Base 4.9
+ __sanitizer_syscall_pre_impl_old_select@Base 4.9
+ __sanitizer_syscall_pre_impl_oldumount@Base 4.9
+ __sanitizer_syscall_pre_impl_olduname@Base 4.9
+ __sanitizer_syscall_pre_impl_open@Base 4.9
+ __sanitizer_syscall_pre_impl_open_by_handle_at@Base 4.9
+ __sanitizer_syscall_pre_impl_openat@Base 4.9
+ __sanitizer_syscall_pre_impl_pause@Base 4.9
+ __sanitizer_syscall_pre_impl_pciconfig_iobase@Base 4.9
+ __sanitizer_syscall_pre_impl_pciconfig_read@Base 4.9
+ __sanitizer_syscall_pre_impl_pciconfig_write@Base 4.9
+ __sanitizer_syscall_pre_impl_perf_event_open@Base 4.9
+ __sanitizer_syscall_pre_impl_personality@Base 4.9
+ __sanitizer_syscall_pre_impl_pipe2@Base 4.9
+ __sanitizer_syscall_pre_impl_pipe@Base 4.9
+ __sanitizer_syscall_pre_impl_pivot_root@Base 4.9
+ __sanitizer_syscall_pre_impl_poll@Base 4.9
+ __sanitizer_syscall_pre_impl_ppoll@Base 4.9
+ __sanitizer_syscall_pre_impl_pread64@Base 4.9
+ __sanitizer_syscall_pre_impl_preadv@Base 4.9
+ __sanitizer_syscall_pre_impl_prlimit64@Base 4.9
+ __sanitizer_syscall_pre_impl_process_vm_readv@Base 4.9
+ __sanitizer_syscall_pre_impl_process_vm_writev@Base 4.9
+ __sanitizer_syscall_pre_impl_pselect6@Base 4.9
+ __sanitizer_syscall_pre_impl_ptrace@Base 4.9
+ __sanitizer_syscall_pre_impl_pwrite64@Base 4.9
+ __sanitizer_syscall_pre_impl_pwritev@Base 4.9
+ __sanitizer_syscall_pre_impl_quotactl@Base 4.9
+ __sanitizer_syscall_pre_impl_read@Base 4.9
+ __sanitizer_syscall_pre_impl_readlink@Base 4.9
+ __sanitizer_syscall_pre_impl_readlinkat@Base 4.9
+ __sanitizer_syscall_pre_impl_readv@Base 4.9
+ __sanitizer_syscall_pre_impl_reboot@Base 4.9
+ __sanitizer_syscall_pre_impl_recv@Base 4.9
+ __sanitizer_syscall_pre_impl_recvfrom@Base 4.9
+ __sanitizer_syscall_pre_impl_recvmmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_recvmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_remap_file_pages@Base 4.9
+ __sanitizer_syscall_pre_impl_removexattr@Base 4.9
+ __sanitizer_syscall_pre_impl_rename@Base 4.9
+ __sanitizer_syscall_pre_impl_renameat@Base 4.9
+ __sanitizer_syscall_pre_impl_request_key@Base 4.9
+ __sanitizer_syscall_pre_impl_restart_syscall@Base 4.9
+ __sanitizer_syscall_pre_impl_rmdir@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigpending@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigprocmask@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigqueueinfo@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigtimedwait@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_tgsigqueueinfo@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_get_priority_max@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_get_priority_min@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_getaffinity@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_getparam@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_getscheduler@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_rr_get_interval@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_setaffinity@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_setparam@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_setscheduler@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_yield@Base 4.9
+ __sanitizer_syscall_pre_impl_select@Base 4.9
+ __sanitizer_syscall_pre_impl_semctl@Base 4.9
+ __sanitizer_syscall_pre_impl_semget@Base 4.9
+ __sanitizer_syscall_pre_impl_semop@Base 4.9
+ __sanitizer_syscall_pre_impl_semtimedop@Base 4.9
+ __sanitizer_syscall_pre_impl_send@Base 4.9
+ __sanitizer_syscall_pre_impl_sendfile64@Base 4.9
+ __sanitizer_syscall_pre_impl_sendfile@Base 4.9
+ __sanitizer_syscall_pre_impl_sendmmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_sendmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_sendto@Base 4.9
+ __sanitizer_syscall_pre_impl_set_mempolicy@Base 4.9
+ __sanitizer_syscall_pre_impl_set_robust_list@Base 4.9
+ __sanitizer_syscall_pre_impl_set_tid_address@Base 4.9
+ __sanitizer_syscall_pre_impl_setdomainname@Base 4.9
+ __sanitizer_syscall_pre_impl_setfsgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setfsuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setgroups@Base 4.9
+ __sanitizer_syscall_pre_impl_sethostname@Base 4.9
+ __sanitizer_syscall_pre_impl_setitimer@Base 4.9
+ __sanitizer_syscall_pre_impl_setns@Base 4.9
+ __sanitizer_syscall_pre_impl_setpgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setpriority@Base 4.9
+ __sanitizer_syscall_pre_impl_setregid@Base 4.9
+ __sanitizer_syscall_pre_impl_setresgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setresuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setreuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setrlimit@Base 4.9
+ __sanitizer_syscall_pre_impl_setsid@Base 4.9
+ __sanitizer_syscall_pre_impl_setsockopt@Base 4.9
+ __sanitizer_syscall_pre_impl_settimeofday@Base 4.9
+ __sanitizer_syscall_pre_impl_setuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_sgetmask@Base 4.9
+ __sanitizer_syscall_pre_impl_shmat@Base 4.9
+ __sanitizer_syscall_pre_impl_shmctl@Base 4.9
+ __sanitizer_syscall_pre_impl_shmdt@Base 4.9
+ __sanitizer_syscall_pre_impl_shmget@Base 4.9
+ __sanitizer_syscall_pre_impl_shutdown@Base 4.9
+ __sanitizer_syscall_pre_impl_signal@Base 4.9
+ __sanitizer_syscall_pre_impl_signalfd4@Base 4.9
+ __sanitizer_syscall_pre_impl_signalfd@Base 4.9
+ __sanitizer_syscall_pre_impl_sigpending@Base 4.9
+ __sanitizer_syscall_pre_impl_sigprocmask@Base 4.9
+ __sanitizer_syscall_pre_impl_socket@Base 4.9
+ __sanitizer_syscall_pre_impl_socketcall@Base 4.9
+ __sanitizer_syscall_pre_impl_socketpair@Base 4.9
+ __sanitizer_syscall_pre_impl_splice@Base 4.9
+ __sanitizer_syscall_pre_impl_spu_create@Base 4.9
+ __sanitizer_syscall_pre_impl_spu_run@Base 4.9
+ __sanitizer_syscall_pre_impl_ssetmask@Base 4.9
+ __sanitizer_syscall_pre_impl_stat64@Base 4.9
+ __sanitizer_syscall_pre_impl_stat@Base 4.9
+ __sanitizer_syscall_pre_impl_statfs64@Base 4.9
+ __sanitizer_syscall_pre_impl_statfs@Base 4.9
+ __sanitizer_syscall_pre_impl_stime@Base 4.9
+ __sanitizer_syscall_pre_impl_swapoff@Base 4.9
+ __sanitizer_syscall_pre_impl_swapon@Base 4.9
+ __sanitizer_syscall_pre_impl_symlink@Base 4.9
+ __sanitizer_syscall_pre_impl_symlinkat@Base 4.9
+ __sanitizer_syscall_pre_impl_sync@Base 4.9
+ __sanitizer_syscall_pre_impl_syncfs@Base 4.9
+ __sanitizer_syscall_pre_impl_sysctl@Base 4.9
+ __sanitizer_syscall_pre_impl_sysfs@Base 4.9
+ __sanitizer_syscall_pre_impl_sysinfo@Base 4.9
+ __sanitizer_syscall_pre_impl_syslog@Base 4.9
+ __sanitizer_syscall_pre_impl_tee@Base 4.9
+ __sanitizer_syscall_pre_impl_tgkill@Base 4.9
+ __sanitizer_syscall_pre_impl_time@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_create@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_delete@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_getoverrun@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_gettime@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_settime@Base 4.9
+ __sanitizer_syscall_pre_impl_timerfd_create@Base 4.9
+ __sanitizer_syscall_pre_impl_timerfd_gettime@Base 4.9
+ __sanitizer_syscall_pre_impl_timerfd_settime@Base 4.9
+ __sanitizer_syscall_pre_impl_times@Base 4.9
+ __sanitizer_syscall_pre_impl_tkill@Base 4.9
+ __sanitizer_syscall_pre_impl_truncate@Base 4.9
+ __sanitizer_syscall_pre_impl_umask@Base 4.9
+ __sanitizer_syscall_pre_impl_umount@Base 4.9
+ __sanitizer_syscall_pre_impl_uname@Base 4.9
+ __sanitizer_syscall_pre_impl_unlink@Base 4.9
+ __sanitizer_syscall_pre_impl_unlinkat@Base 4.9
+ __sanitizer_syscall_pre_impl_unshare@Base 4.9
+ __sanitizer_syscall_pre_impl_uselib@Base 4.9
+ __sanitizer_syscall_pre_impl_ustat@Base 4.9
+ __sanitizer_syscall_pre_impl_utime@Base 4.9
+ __sanitizer_syscall_pre_impl_utimensat@Base 4.9
+ __sanitizer_syscall_pre_impl_utimes@Base 4.9
+ __sanitizer_syscall_pre_impl_vfork@Base 4.9
+ __sanitizer_syscall_pre_impl_vhangup@Base 4.9
+ __sanitizer_syscall_pre_impl_vmsplice@Base 4.9
+ __sanitizer_syscall_pre_impl_wait4@Base 4.9
+ __sanitizer_syscall_pre_impl_waitid@Base 4.9
+ __sanitizer_syscall_pre_impl_waitpid@Base 4.9
+ __sanitizer_syscall_pre_impl_write@Base 4.9
+ __sanitizer_syscall_pre_impl_writev@Base 4.9
+ __sanitizer_unaligned_load16@Base 4.9
+ __sanitizer_unaligned_load32@Base 4.9
+ __sanitizer_unaligned_load64@Base 4.9
+ __sanitizer_unaligned_store16@Base 4.9
+ __sanitizer_unaligned_store32@Base 4.9
+ __sanitizer_unaligned_store64@Base 4.9
+ __sanitizer_update_counter_bitset_and_clear_counters@Base 6.2
+ __sanitizer_verify_contiguous_container@Base 5
+ __tls_get_addr@Base 5
+ __uflow@Base 5
+ __underflow@Base 5
+ __woverflow@Base 5
+ __wuflow@Base 5
+ __wunderflow@Base 5
+ __xpg_strerror_r@Base 4.9
+ _exit@Base 4.9
+ _longjmp@Base 4.8
+ _obstack_begin@Base 5
+ _obstack_begin_1@Base 5
+ _obstack_newchunk@Base 5
+ accept4@Base 4.9
+ accept@Base 4.9
+ aligned_alloc@Base 5
+ asctime@Base 4.8
+ asctime_r@Base 4.8
+ asprintf@Base 5
+ atoi@Base 4.8
+ atol@Base 4.8
+ atoll@Base 4.8
+ backtrace@Base 4.9
+ backtrace_symbols@Base 4.9
+ calloc@Base 4.8
+ canonicalize_file_name@Base 4.9
+ capget@Base 5
+ capset@Base 5
+ cfree@Base 4.8
+ clock_getres@Base 4.9
+ clock_gettime@Base 4.9
+ clock_settime@Base 4.9
+ confstr@Base 4.9
+ ctime@Base 4.8
+ ctime_r@Base 4.8
+ dlclose@Base 5
+ dlopen@Base 5
+ drand48_r@Base 4.9
+ endgrent@Base 5
+ endpwent@Base 5
+ ether_aton@Base 4.9
+ ether_aton_r@Base 4.9
+ ether_hostton@Base 4.9
+ ether_line@Base 4.9
+ ether_ntoa@Base 4.9
+ ether_ntoa_r@Base 4.9
+ ether_ntohost@Base 4.9
+ fclose@Base 5
+ fdopen@Base 5
+ fflush@Base 5
+ fgetgrent@Base 5
+ fgetgrent_r@Base 5
+ fgetpwent@Base 5
+ fgetpwent_r@Base 5
+ fgetxattr@Base 5
+ flistxattr@Base 5
+ fmemopen@Base 5
+ fopen64@Base 5
+ fopen@Base 5
+ fopencookie@Base 6.2
+ fork@Base 5
+ fprintf@Base 5
+ free@Base 4.8
+ freopen64@Base 5
+ freopen@Base 5
+ frexp@Base 4.9
+ frexpf@Base 4.9
+ frexpl@Base 4.9
+ fscanf@Base 4.8
+ fstatfs64@Base 4.9
+ fstatfs@Base 4.9
+ fstatvfs64@Base 4.9
+ fstatvfs@Base 4.9
+ ftime@Base 5
+ get_current_dir_name@Base 4.9
+ getaddrinfo@Base 4.9
+ getcwd@Base 4.9
+ getdelim@Base 4.9
+ getgrent@Base 5
+ getgrent_r@Base 5
+ getgrgid@Base 4.9
+ getgrgid_r@Base 4.9
+ getgrnam@Base 4.9
+ getgrnam_r@Base 4.9
+ getgroups@Base 4.9
+ gethostbyaddr@Base 4.9
+ gethostbyaddr_r@Base 4.9
+ gethostbyname2@Base 4.9
+ gethostbyname2_r@Base 4.9
+ gethostbyname@Base 4.9
+ gethostbyname_r@Base 4.9
+ gethostent@Base 4.9
+ gethostent_r@Base 4.9
+ getifaddrs@Base 5
+ getitimer@Base 4.9
+ getline@Base 4.9
+ getmntent@Base 4.9
+ getmntent_r@Base 4.9
+ getnameinfo@Base 4.9
+ getpass@Base 5
+ getpeername@Base 4.9
+ getpwent@Base 5
+ getpwent_r@Base 5
+ getpwnam@Base 4.9
+ getpwnam_r@Base 4.9
+ getpwuid@Base 4.9
+ getpwuid_r@Base 4.9
+ getresgid@Base 5
+ getresuid@Base 5
+ getsockname@Base 4.9
+ getsockopt@Base 4.9
+ getxattr@Base 5
+ glob64@Base 4.9
+ glob@Base 4.9
+ gmtime@Base 4.8
+ gmtime_r@Base 4.8
+ iconv@Base 4.9
+ if_indextoname@Base 5
+ if_nametoindex@Base 5
+ index@Base 4.8
+ inet_aton@Base 4.9
+ inet_ntop@Base 4.9
+ inet_pton@Base 4.9
+ initgroups@Base 4.9
+ ioctl@Base 4.9
+ lgamma@Base 4.9
+ lgamma_r@Base 4.9
+ lgammaf@Base 4.9
+ lgammaf_r@Base 4.9
+ lgammal@Base 4.9
+ lgammal_r@Base 4.9
+ lgetxattr@Base 5
+ listxattr@Base 5
+ llistxattr@Base 5
+ localtime@Base 4.8
+ localtime_r@Base 4.8
+ longjmp@Base 4.8
+ lrand48_r@Base 4.9
+ mallinfo@Base 4.8
+ malloc@Base 4.8
+ malloc_stats@Base 4.8
+ malloc_usable_size@Base 4.8
+ mallopt@Base 4.8
+ mbsnrtowcs@Base 4.9
+ mbsrtowcs@Base 4.9
+ mbstowcs@Base 4.9
+ memalign@Base 4.8
+ memchr@Base 5
+ memcmp@Base 4.8
+ memcpy@Base 4.8
+ memmove@Base 4.8
+ memrchr@Base 5
+ memset@Base 4.8
+ mincore@Base 6.2
+ mktime@Base 5
+ mlock@Base 4.8
+ mlockall@Base 4.8
+ modf@Base 4.9
+ modff@Base 4.9
+ modfl@Base 4.9
+ munlock@Base 4.8
+ munlockall@Base 4.8
+ open_memstream@Base 5
+ open_wmemstream@Base 5
+ opendir@Base 6.2
+ poll@Base 4.9
+ posix_memalign@Base 4.8
+ ppoll@Base 4.9
+ prctl@Base 4.8
+ pread64@Base 4.8
+ pread@Base 4.8
+ preadv64@Base 4.9
+ preadv@Base 4.9
+ printf@Base 5
+ process_vm_readv@Base 6.2
+ process_vm_writev@Base 6.2
+ pthread_attr_getaffinity_np@Base 4.9
+ pthread_attr_getdetachstate@Base 4.9
+ pthread_attr_getguardsize@Base 4.9
+ pthread_attr_getinheritsched@Base 4.9
+ pthread_attr_getschedparam@Base 4.9
+ pthread_attr_getschedpolicy@Base 4.9
+ pthread_attr_getscope@Base 4.9
+ pthread_attr_getstack@Base 4.9
+ pthread_attr_getstacksize@Base 4.9
+ pthread_barrierattr_getpshared@Base 5
+ pthread_condattr_getclock@Base 5
+ pthread_condattr_getpshared@Base 5
+ pthread_create@Base 4.8
+ pthread_getschedparam@Base 4.9
+ pthread_join@Base 6.2
+ pthread_mutex_lock@Base 4.9
+ pthread_mutex_unlock@Base 4.9
+ pthread_mutexattr_getprioceiling@Base 5
+ pthread_mutexattr_getprotocol@Base 5
+ pthread_mutexattr_getpshared@Base 5
+ pthread_mutexattr_getrobust@Base 5
+ pthread_mutexattr_getrobust_np@Base 5
+ pthread_mutexattr_gettype@Base 5
+ pthread_rwlockattr_getkind_np@Base 5
+ pthread_rwlockattr_getpshared@Base 5
+ pthread_setcancelstate@Base 6.2
+ pthread_setcanceltype@Base 6.2
+ pthread_setname_np@Base 4.9
+ pvalloc@Base 4.8
+ pwrite64@Base 4.8
+ pwrite@Base 4.8
+ pwritev64@Base 4.9
+ pwritev@Base 4.9
+ rand_r@Base 5
+ random_r@Base 4.9
+ read@Base 4.8
+ readdir64@Base 4.9
+ readdir64_r@Base 4.9
+ readdir@Base 4.9
+ readdir_r@Base 4.9
+ readv@Base 4.9
+ realloc@Base 4.8
+ realpath@Base 4.9
+ recvmsg@Base 4.9
+ remquo@Base 4.9
+ remquof@Base 4.9
+ remquol@Base 4.9
+ scandir64@Base 4.9
+ scandir@Base 4.9
+ scanf@Base 4.8
+ sched_getaffinity@Base 4.9
+ sched_getparam@Base 6.2
+ sem_destroy@Base 6.2
+ sem_getvalue@Base 6.2
+ sem_init@Base 6.2
+ sem_post@Base 6.2
+ sem_timedwait@Base 6.2
+ sem_trywait@Base 6.2
+ sem_wait@Base 6.2
+ setgrent@Base 5
+ setitimer@Base 4.9
+ setlocale@Base 4.9
+ setpwent@Base 5
+ sigaction@Base 4.8
+ sigemptyset@Base 4.9
+ sigfillset@Base 4.9
+ siglongjmp@Base 4.8
+ signal@Base 4.8
+ sigpending@Base 4.9
+ sigprocmask@Base 4.9
+ sigtimedwait@Base 4.9
+ sigwait@Base 4.9
+ sigwaitinfo@Base 4.9
+ sincos@Base 4.9
+ sincosf@Base 4.9
+ sincosl@Base 4.9
+ snprintf@Base 5
+ sprintf@Base 5
+ sscanf@Base 4.8
+ statfs64@Base 4.9
+ statfs@Base 4.9
+ statvfs64@Base 4.9
+ statvfs@Base 4.9
+ strcasecmp@Base 4.8
+ strcasestr@Base 6.2
+ strcat@Base 4.8
+ strchr@Base 4.8
+ strcmp@Base 4.8
+ strcpy@Base 4.8
+ strcspn@Base 6.2
+ strdup@Base 4.8
+ strerror@Base 4.9
+ strerror_r@Base 4.9
+ strlen@Base 4.8
+ strncasecmp@Base 4.8
+ strncat@Base 4.8
+ strncmp@Base 4.8
+ strncpy@Base 4.8
+ strnlen@Base 4.8
+ strpbrk@Base 6.2
+ strptime@Base 4.9
+ strspn@Base 6.2
+ strstr@Base 6.2
+ strtoimax@Base 4.9
+ strtol@Base 4.8
+ strtoll@Base 4.8
+ strtoumax@Base 4.9
+ swapcontext@Base 4.8
+ sysinfo@Base 4.9
+ tcgetattr@Base 4.9
+ tempnam@Base 4.9
+ textdomain@Base 4.9
+ time@Base 4.9
+ timerfd_gettime@Base 5
+ timerfd_settime@Base 5
+ times@Base 4.9
+ tmpnam@Base 4.9
+ tmpnam_r@Base 4.9
+ tsearch@Base 5
+ valloc@Base 4.8
+ vasprintf@Base 5
+ vfprintf@Base 5
+ vfscanf@Base 4.8
+ vprintf@Base 5
+ vscanf@Base 4.8
+ vsnprintf@Base 5
+ vsprintf@Base 5
+ vsscanf@Base 4.8
+ wait3@Base 4.9
+ wait4@Base 4.9
+ wait@Base 4.9
+ waitid@Base 4.9
+ waitpid@Base 4.9
+ wcrtomb@Base 6.2
+ wcslen@Base 4.9
+ wcsnrtombs@Base 4.9
+ wcsrtombs@Base 4.9
+ wcstombs@Base 4.9
+ wordexp@Base 4.9
+ write@Base 4.8
+ writev@Base 4.9
+ xdr_bool@Base 5
+ xdr_bytes@Base 5
+ xdr_char@Base 5
+ xdr_double@Base 5
+ xdr_enum@Base 5
+ xdr_float@Base 5
+ xdr_hyper@Base 5
+ xdr_int16_t@Base 5
+ xdr_int32_t@Base 5
+ xdr_int64_t@Base 5
+ xdr_int8_t@Base 5
+ xdr_int@Base 5
+ xdr_long@Base 5
+ xdr_longlong_t@Base 5
+ xdr_quad_t@Base 5
+ xdr_short@Base 5
+ xdr_string@Base 5
+ xdr_u_char@Base 5
+ xdr_u_hyper@Base 5
+ xdr_u_int@Base 5
+ xdr_u_long@Base 5
+ xdr_u_longlong_t@Base 5
+ xdr_u_quad_t@Base 5
+ xdr_u_short@Base 5
+ xdr_uint16_t@Base 5
+ xdr_uint32_t@Base 5
+ xdr_uint64_t@Base 5
+ xdr_uint8_t@Base 5
+ xdrmem_create@Base 5
+ xdrstdio_create@Base 5
--- gcc-6-6.4.0.orig/debian/libasan3.symbols
+++ gcc-6-6.4.0/debian/libasan3.symbols
@@ -0,0 +1,20 @@
+libasan.so.3 libasan3 #MINVER#
+#include "libasan.symbols.common"
+(arch=!arm64 !alpha !amd64 !ia64 !ppc64 !ppc64el !s390x !sparc64 !kfreebsd-amd64)#include "libasan.symbols.32"
+(arch=arm64 alpha amd64 ia64 ppc64 ppc64el s390x sparc64 kfreebsd-amd64)#include "libasan.symbols.64"
+(arch=armel armhf sparc64 x32)#include "libasan.symbols.16"
+# these are missing on some archs ...
+ (arch=!arm64 !armel !armhf !i386 !powerpc !ppc64 !ppc64el !sparc !sparc64)__interceptor_ptrace@Base 4.9
+ (arch=!arm64 !armel !armhf !i386 !powerpc !ppc64 !ppc64el !sparc !sparc64)ptrace@Base 4.9
+ (arch=armel armhf)__interceptor___aeabi_memclr4@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memclr8@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memclr@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memcpy4@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memcpy8@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memcpy@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memmove4@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memmove8@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memmove@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memset4@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memset8@Base 5
+ (arch=armel armhf)__interceptor___aeabi_memset@Base 5
--- gcc-6-6.4.0.orig/debian/libatomic.symbols
+++ gcc-6-6.4.0/debian/libatomic.symbols
@@ -0,0 +1,4 @@
+libatomic.so.1 #PACKAGE# #MINVER#
+ (symver)LIBATOMIC_1.0 4.8
+ (symver)LIBATOMIC_1.1 4.9
+ (symver)LIBATOMIC_1.2 6
--- gcc-6-6.4.0.orig/debian/libcc1-0.symbols
+++ gcc-6-6.4.0/debian/libcc1-0.symbols
@@ -0,0 +1,61 @@
+libcc1.so.0 libcc1-0 #MINVER#
+ (optional=abi_c++98)_ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag@Base 5
+ (optional=abi_c++98)_ZNSt6vectorISsSaISsEE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPSsS1_EERKSs@Base 5
+ (optional=abi_c++11)_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12emplace_backIJS5_EEEvDpOT_@Base 6
+ (optional=abi_c++11)_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS5_S7_EERKS5_@Base 5
+ (optional=abi_c++11)_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE19_M_emplace_back_auxIJRKS5_EEEvDpOT_@Base 6
+ (optional=abi_c++11)_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE19_M_emplace_back_auxIJS5_EEEvDpOT_@Base 6
+ _xexit_cleanup@Base 5
+ concat@Base 5
+ concat_copy2@Base 5
+ concat_copy@Base 5
+ concat_length@Base 5
+ gcc_c_fe_context@Base 5
+ htab_clear_slot@Base 5
+ htab_collisions@Base 5
+ htab_create@Base 5
+ htab_create_alloc@Base 5
+ htab_create_alloc_ex@Base 5
+ htab_create_typed_alloc@Base 5
+ htab_delete@Base 5
+ htab_elements@Base 5
+ htab_empty@Base 5
+ htab_eq_pointer@Base 5
+ htab_find@Base 5
+ htab_find_slot@Base 5
+ htab_find_slot_with_hash@Base 5
+ htab_find_with_hash@Base 5
+ htab_hash_pointer@Base 5
+ htab_hash_string@Base 5
+ htab_remove_elt@Base 5
+ htab_remove_elt_with_hash@Base 5
+ htab_set_functions_ex@Base 5
+ htab_size@Base 5
+ htab_traverse@Base 5
+ htab_traverse_noresize@Base 5
+ htab_try_create@Base 5
+ iterative_hash@Base 5
+ libiberty_concat_ptr@Base 5
+ reconcat@Base 5
+ xcalloc@Base 5
+ xexit@Base 5
+ xmalloc@Base 5
+ xmalloc_failed@Base 5
+ xmalloc_set_program_name@Base 5
+ xre_comp@Base 5
+ xre_compile_fastmap@Base 5
+ xre_compile_pattern@Base 5
+ xre_exec@Base 5
+ xre_match@Base 5
+ xre_match_2@Base 5
+ xre_max_failures@Base 5
+ xre_search@Base 5
+ xre_search_2@Base 5
+ xre_set_registers@Base 5
+ xre_set_syntax@Base 5
+ xre_syntax_options@Base 5
+ xrealloc@Base 5
+ xregcomp@Base 5
+ xregerror@Base 5
+ xregexec@Base 5
+ xregfree@Base 5
--- gcc-6-6.4.0.orig/debian/libcilkrts.symbols
+++ gcc-6-6.4.0/debian/libcilkrts.symbols
@@ -0,0 +1,4 @@
+libcilkrts.so.5 #PACKAGE# #MINVER#
+ (symver)CILKABI0 4.9
+ (symver)CILKABI1 4.9
+ (symver)CILKLIB1.02 4.9
--- gcc-6-6.4.0.orig/debian/libgcc.symbols
+++ gcc-6-6.4.0/debian/libgcc.symbols
@@ -0,0 +1,25 @@
+libgcc_s.so.1 #PACKAGE# #MINVER#
+ (symver)GCC_3.0 1:3.0
+ (symver)GCC_3.3 1:3.3
+ (symver)GCC_3.3.1 1:3.3.1
+# __gcc_personality_sj0, __gcc_personality_v0
+#(symver|optional)GCC_3.3.2 1:3.3.2
+ (symver|arch=armel armhf mips mipsel mips64el powerpc powerpcspe sh4)GCC_3.3.4 1:3.3.4
+ (symver)GCC_3.4 1:3.4
+ (symver)GCC_3.4.2 1:3.4.2
+#(symver|arch-bits=32)GCC_3.4.4 1:3.4.4
+ (symver|arch=!armel !armhf !any-i386 !mips !mipsel !powerpc !powerpcspe !s390 !sh4 !sparc)GCC_3.4.4 1:3.4.4
+ (symver|arch=armel armhf|ignore-blacklist)GCC_3.5 1:3.5
+ (symver)GCC_4.0.0 1:4.0
+ (symver|arch=powerpc)GCC_4.1.0 1:4.1
+ (symver)GCC_4.2.0 1:4.2
+ (symver)GCC_4.3.0 1:4.3
+ (symver|arch=any-i386 mips mipsel mips64el)GCC_4.4.0 1:4.4
+ (symver|arch=arm64 any-i386 mips64el)GCC_4.5.0 1:4.5
+#(symver|optional)GCC_4.6.0 1:4.6
+ (symver)GCC_4.7.0 1:4.7
+ (symver|arch=any-amd64 any-i386 x32)GCC_4.8.0 1:4.8
+ (symver|arch=!any-amd64 !x32)GLIBC_2.0 1:4.2
+ (symver|arch=s390x sh4 sparc64)GLIBC_2.2 1:4.2
+ (symver|arch=sparc)GCC_LDBL_3.0@GCC_LDBL_3.0 1:3.0
+ (symver|arch=alpha sparc)GCC_LDBL_4.0.0@GCC_LDBL_4.0.0 1:4.0
--- gcc-6-6.4.0.orig/debian/libgcc.symbols.aeabi
+++ gcc-6-6.4.0/debian/libgcc.symbols.aeabi
@@ -0,0 +1,69 @@
+ __aeabi_cdcmpeq@GCC_3.5 1:3.5
+ __aeabi_cdcmple@GCC_3.5 1:3.5
+ __aeabi_cdrcmple@GCC_3.5 1:3.5
+ __aeabi_cfcmpeq@GCC_3.5 1:3.5
+ __aeabi_cfcmple@GCC_3.5 1:3.5
+ __aeabi_cfrcmple@GCC_3.5 1:3.5
+ __aeabi_d2f@GCC_3.5 1:3.5
+ __aeabi_d2iz@GCC_3.5 1:3.5
+ __aeabi_d2lz@GCC_3.5 1:3.5
+ __aeabi_d2uiz@GCC_3.5 1:3.5
+ __aeabi_d2ulz@GCC_3.5 1:3.5
+ __aeabi_dadd@GCC_3.5 1:3.5
+ __aeabi_dcmpeq@GCC_3.5 1:3.5
+ __aeabi_dcmpge@GCC_3.5 1:3.5
+ __aeabi_dcmpgt@GCC_3.5 1:3.5
+ __aeabi_dcmple@GCC_3.5 1:3.5
+ __aeabi_dcmplt@GCC_3.5 1:3.5
+ __aeabi_dcmpun@GCC_3.5 1:3.5
+ __aeabi_ddiv@GCC_3.5 1:3.5
+ __aeabi_dmul@GCC_3.5 1:3.5
+ __aeabi_dneg@GCC_3.5 1:3.5
+ __aeabi_drsub@GCC_3.5 1:3.5
+ __aeabi_dsub@GCC_3.5 1:3.5
+ __aeabi_f2d@GCC_3.5 1:3.5
+ __aeabi_f2iz@GCC_3.5 1:3.5
+ __aeabi_f2lz@GCC_3.5 1:3.5
+ __aeabi_f2uiz@GCC_3.5 1:3.5
+ __aeabi_f2ulz@GCC_3.5 1:3.5
+ __aeabi_fadd@GCC_3.5 1:3.5
+ __aeabi_fcmpeq@GCC_3.5 1:3.5
+ __aeabi_fcmpge@GCC_3.5 1:3.5
+ __aeabi_fcmpgt@GCC_3.5 1:3.5
+ __aeabi_fcmple@GCC_3.5 1:3.5
+ __aeabi_fcmplt@GCC_3.5 1:3.5
+ __aeabi_fcmpun@GCC_3.5 1:3.5
+ __aeabi_fdiv@GCC_3.5 1:3.5
+ __aeabi_fmul@GCC_3.5 1:3.5
+ __aeabi_fneg@GCC_3.5 1:3.5
+ __aeabi_frsub@GCC_3.5 1:3.5
+ __aeabi_fsub@GCC_3.5 1:3.5
+ __aeabi_i2d@GCC_3.5 1:3.5
+ __aeabi_i2f@GCC_3.5 1:3.5
+ __aeabi_idiv@GCC_3.5 1:3.5
+ __aeabi_idiv0@GCC_3.5 1:4.5.0
+ __aeabi_idivmod@GCC_3.5 1:3.5
+ __aeabi_l2d@GCC_3.5 1:3.5
+ __aeabi_l2f@GCC_3.5 1:3.5
+ __aeabi_lasr@GCC_3.5 1:3.5
+ __aeabi_lcmp@GCC_3.5 1:3.5
+ __aeabi_ldivmod@GCC_3.5 1:3.5
+ __aeabi_ldiv0@GCC_3.5 1:4.5.0
+ __aeabi_llsl@GCC_3.5 1:3.5
+ __aeabi_llsr@GCC_3.5 1:3.5
+ __aeabi_lmul@GCC_3.5 1:3.5
+ __aeabi_ui2d@GCC_3.5 1:3.5
+ __aeabi_ui2f@GCC_3.5 1:3.5
+ __aeabi_uidiv@GCC_3.5 1:3.5
+ __aeabi_uidivmod@GCC_3.5 1:3.5
+ __aeabi_ul2d@GCC_3.5 1:3.5
+ __aeabi_ul2f@GCC_3.5 1:3.5
+ __aeabi_ulcmp@GCC_3.5 1:3.5
+ __aeabi_uldivmod@GCC_3.5 1:3.5
+ __aeabi_unwind_cpp_pr0@GCC_3.5 1:3.5
+ __aeabi_unwind_cpp_pr1@GCC_3.5 1:3.5
+ __aeabi_unwind_cpp_pr2@GCC_3.5 1:3.5
+ __aeabi_uread4@GCC_3.5 1:3.5
+ __aeabi_uread8@GCC_3.5 1:3.5
+ __aeabi_uwrite4@GCC_3.5 1:3.5
+ __aeabi_uwrite8@GCC_3.5 1:3.5
--- gcc-6-6.4.0.orig/debian/libgcc2.symbols.m68k
+++ gcc-6-6.4.0/debian/libgcc2.symbols.m68k
@@ -0,0 +1,162 @@
+libgcc_s.so.2 libgcc2 #MINVER#
+ GCC_3.0@GCC_3.0 4.2.1
+ GCC_3.3.1@GCC_3.3.1 4.2.1
+ GCC_3.3.4@GCC_3.3.4 4.4.5
+ GCC_3.3@GCC_3.3 4.2.1
+ GCC_3.4.2@GCC_3.4.2 4.2.1
+ GCC_3.4@GCC_3.4 4.2.1
+ GCC_4.0.0@GCC_4.0.0 4.2.1
+ GCC_4.2.0@GCC_4.2.0 4.2.1
+ GCC_4.3.0@GCC_4.3.0 4.3.0
+ GCC_4.5.0@GCC_4.5.0 4.5
+ GCC_4.7.0@GCC_4.7.0 4.7
+ GLIBC_2.0@GLIBC_2.0 4.2.1
+ _Unwind_Backtrace@GCC_3.3 4.2.1
+ _Unwind_DeleteException@GCC_3.0 4.2.1
+ _Unwind_FindEnclosingFunction@GCC_3.3 4.2.1
+ _Unwind_Find_FDE@GCC_3.0 4.2.1
+ _Unwind_ForcedUnwind@GCC_3.0 4.2.1
+ _Unwind_GetCFA@GCC_3.3 4.2.1
+ _Unwind_GetDataRelBase@GCC_3.0 4.2.1
+ _Unwind_GetGR@GCC_3.0 4.2.1
+ _Unwind_GetIP@GCC_3.0 4.2.1
+ _Unwind_GetIPInfo@GCC_4.2.0 4.2.1
+ _Unwind_GetLanguageSpecificData@GCC_3.0 4.2.1
+ _Unwind_GetRegionStart@GCC_3.0 4.2.1
+ _Unwind_GetTextRelBase@GCC_3.0 4.2.1
+ _Unwind_RaiseException@GCC_3.0 4.2.1
+ _Unwind_Resume@GCC_3.0 4.2.1
+ _Unwind_Resume_or_Rethrow@GCC_3.3 4.2.1
+ _Unwind_SetGR@GCC_3.0 4.2.1
+ _Unwind_SetIP@GCC_3.0 4.2.1
+ __absvdi2@GCC_3.0 4.2.1
+ __absvsi2@GCC_3.0 4.2.1
+ __adddf3@GCC_3.0 4.4.5
+ __addsf3@GCC_3.0 4.4.5
+ __addvdi3@GCC_3.0 4.2.1
+ __addvsi3@GCC_3.0 4.2.1
+ __addxf3@GCC_3.0 4.4.5
+ __ashldi3@GCC_3.0 4.2.1
+ __ashrdi3@GCC_3.0 4.2.1
+ __bswapdi2@GCC_4.3.0 4.3.0
+ __bswapsi2@GCC_4.3.0 4.3.0
+ __clear_cache@GCC_3.0 4.2.1
+  __clrsbdi2@GCC_4.7.0 4.7
+  __clrsbsi2@GCC_4.7.0 4.7
+ __clzdi2@GCC_3.4 4.2.1
+ __clzsi2@GCC_3.4 4.2.1
+ __cmpdi2@GCC_3.0 4.2.1
+ __ctzdi2@GCC_3.4 4.2.1
+ __ctzsi2@GCC_3.4 4.2.1
+ __deregister_frame@GLIBC_2.0 4.2.1
+ __deregister_frame_info@GLIBC_2.0 4.2.1
+ __deregister_frame_info_bases@GCC_3.0 4.2.1
+ __divdc3@GCC_4.0.0 4.2.1
+ __divdf3@GCC_3.0 4.4.5
+ __divdi3@GLIBC_2.0 4.2.1
+ __divsc3@GCC_4.0.0 4.2.1
+ __divsf3@GCC_3.0 4.4.5
+ __divsi3@GCC_3.0 4.4.5
+ __divxc3@GCC_4.0.0 4.2.1
+ __divxf3@GCC_3.0 4.4.5
+ __emutls_get_address@GCC_4.3.0 4.3.0
+ __emutls_register_common@GCC_4.3.0 4.3.0
+ __enable_execute_stack@GCC_3.4.2 4.2.1
+ __eqdf2@GCC_3.0 4.4.5
+ __eqsf2@GCC_3.0 4.4.5
+ __eqxf2@GCC_3.0 4.4.5
+ __extenddfxf2@GCC_3.0 4.4.5
+ __extendsfdf2@GCC_3.0 4.4.5
+ __extendsfxf2@GCC_3.0 4.4.5
+ __ffsdi2@GCC_3.0 4.2.1
+ __ffssi2@GCC_4.3.0 4.3.0
+ __fixdfdi@GCC_3.0 4.2.1
+ __fixdfsi@GCC_3.0 4.4.5
+ __fixsfdi@GCC_3.0 4.2.1
+ __fixsfsi@GCC_3.0 4.4.5
+ __fixunsdfdi@GCC_3.0 4.2.1
+ __fixunsdfsi@GCC_3.0 4.2.1
+ __fixunssfdi@GCC_3.0 4.2.1
+ __fixunssfsi@GCC_3.0 4.2.1
+ __fixunsxfdi@GCC_3.0 4.2.1
+ __fixunsxfsi@GCC_3.0 4.2.1
+ __fixxfdi@GCC_3.0 4.2.1
+ __fixxfsi@GCC_3.0 4.4.5
+ __floatdidf@GCC_3.0 4.2.1
+ __floatdisf@GCC_3.0 4.2.1
+ __floatdixf@GCC_3.0 4.2.1
+ __floatsidf@GCC_3.0 4.4.5
+ __floatsisf@GCC_3.0 4.4.5
+ __floatsixf@GCC_3.0 4.4.5
+ __floatundidf@GCC_4.2.0 4.2.1
+ __floatundisf@GCC_4.2.0 4.2.1
+ __floatundixf@GCC_4.2.0 4.2.1
+ __floatunsidf@GCC_4.2.0 4.4.5
+ __floatunsisf@GCC_4.2.0 4.4.5
+ __floatunsixf@GCC_4.2.0 4.4.5
+ __frame_state_for@GLIBC_2.0 4.2.1
+ __gcc_personality_v0@GCC_3.3.1 4.2.1
+ __gedf2@GCC_3.0 4.4.5
+ __gesf2@GCC_3.0 4.4.5
+ __gexf2@GCC_3.0 4.4.5
+ __gtdf2@GCC_3.0 4.4.5
+ __gtsf2@GCC_3.0 4.4.5
+ __gtxf2@GCC_3.0 4.4.5
+ __ledf2@GCC_3.0 4.4.5
+ __lesf2@GCC_3.0 4.4.5
+ __lexf2@GCC_3.0 4.4.5
+ __lshrdi3@GCC_3.0 4.2.1
+ __ltdf2@GCC_3.0 4.4.5
+ __ltsf2@GCC_3.0 4.4.5
+ __ltxf2@GCC_3.0 4.4.5
+ __moddi3@GLIBC_2.0 4.2.1
+ __modsi3@GCC_3.0 4.4.5
+ __muldc3@GCC_4.0.0 4.2.1
+ __muldf3@GCC_3.0 4.4.5
+ __muldi3@GCC_3.0 4.2.1
+ __mulsc3@GCC_4.0.0 4.2.1
+ __mulsf3@GCC_3.0 4.4.5
+ __mulsi3@GCC_3.0 4.4.5
+ __mulvdi3@GCC_3.0 4.2.1
+ __mulvsi3@GCC_3.0 4.2.1
+ __mulxc3@GCC_4.0.0 4.2.1
+ __mulxf3@GCC_3.0 4.4.5
+ __nedf2@GCC_3.0 4.4.5
+ __negdf2@GCC_3.0 4.4.5
+ __negdi2@GCC_3.0 4.2.1
+ __negsf2@GCC_3.0 4.4.5
+ __negvdi2@GCC_3.0 4.2.1
+ __negvsi2@GCC_3.0 4.2.1
+ __negxf2@GCC_3.0 4.4.5
+ __nesf2@GCC_3.0 4.4.5
+ __nexf2@GCC_3.0 4.4.5
+ __paritydi2@GCC_3.4 4.2.1
+ __paritysi2@GCC_3.4 4.2.1
+ __popcountdi2@GCC_3.4 4.2.1
+ __popcountsi2@GCC_3.4 4.2.1
+ __powidf2@GCC_4.0.0 4.2.1
+ __powisf2@GCC_4.0.0 4.2.1
+ __powixf2@GCC_4.0.0 4.2.1
+ __register_frame@GLIBC_2.0 4.2.1
+ __register_frame_info@GLIBC_2.0 4.2.1
+ __register_frame_info_bases@GCC_3.0 4.2.1
+ __register_frame_info_table@GLIBC_2.0 4.2.1
+ __register_frame_info_table_bases@GCC_3.0 4.2.1
+ __register_frame_table@GLIBC_2.0 4.2.1
+ __subdf3@GCC_3.0 4.4.5
+ __subsf3@GCC_3.0 4.4.5
+ __subvdi3@GCC_3.0 4.2.1
+ __subvsi3@GCC_3.0 4.2.1
+ __subxf3@GCC_3.0 4.4.5
+ __truncdfsf2@GCC_3.0 4.4.5
+ __truncxfdf2@GCC_3.0 4.4.5
+ __truncxfsf2@GCC_3.0 4.4.5
+ __ucmpdi2@GCC_3.0 4.2.1
+ __udivdi3@GLIBC_2.0 4.2.1
+ __udivmoddi4@GCC_3.0 4.2.1
+ __udivsi3@GCC_3.0 4.4.5
+ __umoddi3@GLIBC_2.0 4.2.1
+ __umodsi3@GCC_3.0 4.4.5
+ __unorddf2@GCC_3.3.4 4.4.5
+ __unordsf2@GCC_3.3.4 4.4.5
+ __unordxf2@GCC_4.5.0 4.7
--- gcc-6-6.4.0.orig/debian/libgcc4.symbols.hppa
+++ gcc-6-6.4.0/debian/libgcc4.symbols.hppa
@@ -0,0 +1,96 @@
+libgcc_s.so.4 libgcc4 #MINVER#
+ GCC_3.0@GCC_3.0 4.1.1
+ GCC_3.3.1@GCC_3.3.1 4.1.1
+ GCC_3.3@GCC_3.3 4.1.1
+ GCC_3.4.2@GCC_3.4.2 4.1.1
+ GCC_3.4@GCC_3.4 4.1.1
+ GCC_4.0.0@GCC_4.0.0 4.1.1
+ GCC_4.2.0@GCC_4.2.0 4.1.1
+ GCC_4.3.0@GCC_4.3.0 4.3
+ GCC_4.7.0@GCC_4.7.0 1:4.7
+ GLIBC_2.0@GLIBC_2.0 4.1.1
+ _Unwind_Backtrace@GCC_3.3 4.1.1
+ _Unwind_DeleteException@GCC_3.0 4.1.1
+ _Unwind_FindEnclosingFunction@GCC_3.3 4.1.1
+ _Unwind_Find_FDE@GCC_3.0 4.1.1
+ _Unwind_ForcedUnwind@GCC_3.0 4.1.1
+ _Unwind_GetCFA@GCC_3.3 4.1.1
+ _Unwind_GetDataRelBase@GCC_3.0 4.1.1
+ _Unwind_GetGR@GCC_3.0 4.1.1
+ _Unwind_GetIP@GCC_3.0 4.1.1
+ _Unwind_GetIPInfo@GCC_4.2.0 4.1.1
+ _Unwind_GetLanguageSpecificData@GCC_3.0 4.1.1
+ _Unwind_GetRegionStart@GCC_3.0 4.1.1
+ _Unwind_GetTextRelBase@GCC_3.0 4.1.1
+ _Unwind_RaiseException@GCC_3.0 4.1.1
+ _Unwind_Resume@GCC_3.0 4.1.1
+ _Unwind_Resume_or_Rethrow@GCC_3.3 4.1.1
+ _Unwind_SetGR@GCC_3.0 4.1.1
+ _Unwind_SetIP@GCC_3.0 4.1.1
+ __absvdi2@GCC_3.0 4.1.1
+ __absvsi2@GCC_3.0 4.1.1
+ __addvdi3@GCC_3.0 4.1.1
+ __addvsi3@GCC_3.0 4.1.1
+ __ashldi3@GCC_3.0 4.1.1
+ __ashrdi3@GCC_3.0 4.1.1
+ __bswapdi2@GCC_4.3.0 4.3
+ __bswapsi2@GCC_4.3.0 4.3
+ __clear_cache@GCC_3.0 4.1.1
+ __clrsbdi2@GCC_4.7.0 4.7
+ __clrsbsi2@GCC_4.7.0 4.7
+ __clzdi2@GCC_3.4 4.1.1
+ __clzsi2@GCC_3.4 4.1.1
+ __cmpdi2@GCC_3.0 4.1.1
+ __ctzdi2@GCC_3.4 4.1.1
+ __ctzsi2@GCC_3.4 4.1.1
+ __deregister_frame@GLIBC_2.0 4.1.1
+ __deregister_frame_info@GLIBC_2.0 4.1.1
+ __deregister_frame_info_bases@GCC_3.0 4.1.1
+ __divdc3@GCC_4.0.0 4.1.1
+ __divdi3@GLIBC_2.0 4.1.1
+ __divsc3@GCC_4.0.0 4.1.1
+ __emutls_get_address@GCC_4.3.0 4.3
+ __emutls_register_common@GCC_4.3.0 4.3
+ __enable_execute_stack@GCC_3.4.2 4.1.1
+ __ffsdi2@GCC_3.0 4.1.1
+ __ffssi2@GCC_4.3.0 4.3
+ __fixdfdi@GCC_3.0 4.1.1
+ __fixsfdi@GCC_3.0 4.1.1
+ __fixunsdfdi@GCC_3.0 4.1.1
+ __fixunsdfsi@GCC_3.0 4.1.1
+ __fixunssfdi@GCC_3.0 4.1.1
+ __fixunssfsi@GCC_3.0 4.1.1
+ __floatdidf@GCC_3.0 4.1.1
+ __floatdisf@GCC_3.0 4.1.1
+ __floatundidf@GCC_4.2.0 4.2.1
+ __floatundisf@GCC_4.2.0 4.2.1
+ __frame_state_for@GLIBC_2.0 4.1.1
+ __gcc_personality_v0@GCC_3.3.1 4.1.1
+ __lshrdi3@GCC_3.0 4.1.1
+ __moddi3@GLIBC_2.0 4.1.1
+ __muldc3@GCC_4.0.0 4.1.1
+ __muldi3@GCC_3.0 4.1.1
+ __mulsc3@GCC_4.0.0 4.1.1
+ __mulvdi3@GCC_3.0 4.1.1
+ __mulvsi3@GCC_3.0 4.1.1
+ __negdi2@GCC_3.0 4.1.1
+ __negvdi2@GCC_3.0 4.1.1
+ __negvsi2@GCC_3.0 4.1.1
+ __paritydi2@GCC_3.4 4.1.1
+ __paritysi2@GCC_3.4 4.1.1
+ __popcountdi2@GCC_3.4 4.1.1
+ __popcountsi2@GCC_3.4 4.1.1
+ __powidf2@GCC_4.0.0 4.1.1
+ __powisf2@GCC_4.0.0 4.1.1
+ __register_frame@GLIBC_2.0 4.1.1
+ __register_frame_info@GLIBC_2.0 4.1.1
+ __register_frame_info_bases@GCC_3.0 4.1.1
+ __register_frame_info_table@GLIBC_2.0 4.1.1
+ __register_frame_info_table_bases@GCC_3.0 4.1.1
+ __register_frame_table@GLIBC_2.0 4.1.1
+ __subvdi3@GCC_3.0 4.1.1
+ __subvsi3@GCC_3.0 4.1.1
+ __ucmpdi2@GCC_3.0 4.1.1
+ __udivdi3@GLIBC_2.0 4.1.1
+ __udivmoddi4@GCC_3.0 4.1.1
+ __umoddi3@GLIBC_2.0 4.1.1
--- gcc-6-6.4.0.orig/debian/libgccLC.postinst
+++ gcc-6-6.4.0/debian/libgccLC.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/libgcc@LC@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcc-@BV@-base $docdir
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/libgccjit0.symbols
+++ gcc-6-6.4.0/debian/libgccjit0.symbols
@@ -0,0 +1,7 @@
+libgccjit.so.0 #PACKAGE# #MINVER#
+ (symver)LIBGCCJIT_ABI_0 5.1
+ (symver)LIBGCCJIT_ABI_1 5.1
+ (symver)LIBGCCJIT_ABI_2 5.1
+ (symver)LIBGCCJIT_ABI_3 5.1
+ (symver)LIBGCCJIT_ABI_4 6
+ (symver)LIBGCCJIT_ABI_5 6
--- gcc-6-6.4.0.orig/debian/libgcj-common.postinst
+++ gcc-6-6.4.0/debian/libgcj-common.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/libgcj-common
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcj-@BV@-base $docdir
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/libgcj-common.preinst
+++ gcc-6-6.4.0/debian/libgcj-common.preinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    upgrade|install)
+	if [ -n "$2" ] && [ -h /usr/share/doc/libgcj-common ] \
+	   && dpkg --compare-versions "$2" lt 1:4.0.2-10
+	then
+	    rm -f /usr/share/doc/libgcj-common
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/libgcj-doc.doc-base
+++ gcc-6-6.4.0/debian/libgcj-doc.doc-base
@@ -0,0 +1,10 @@
+Document: libgcj-doc
+Title: The GNU LibGCJ Classpath library
+Author: Various
+Abstract: Autogenerated documentation describing the libgcj
+ library (GCC 5), based on the classpath library.
+Section: Programming/Java
+
+Format: html
+Index: /usr/share/doc/gcc-6-base/api/index.html
+Files: /usr/share/doc/gcc-6-base/api/*.html
--- gcc-6-6.4.0.orig/debian/libgcjGCJ-awt.overrides
+++ gcc-6-6.4.0/debian/libgcjGCJ-awt.overrides
@@ -0,0 +1,2 @@
+# pick up the exact version, in case another gcj version is installed
+libgcj@GCJ@-awt binary: binary-or-shlib-defines-rpath
--- gcc-6-6.4.0.orig/debian/libgcjGCJ-dev.overrides
+++ gcc-6-6.4.0/debian/libgcjGCJ-dev.overrides
@@ -0,0 +1 @@
+libgcj@GCJ@-dev binary: library-not-linked-against-libc
--- gcc-6-6.4.0.orig/debian/libgcjGCJ.overrides
+++ gcc-6-6.4.0/debian/libgcjGCJ.overrides
@@ -0,0 +1,9 @@
+# pick up the exact version, in case another gcj version is installed
+libgcj@GCJ@ binary: binary-or-shlib-defines-rpath
+
+# intended
+libgcj@GCJ@ binary: unused-shlib-entry-in-control-file
+libgcj@GCJ@ binary: shlibs-declares-dependency-on-other-package
+
+# keep patched ltdl copy
+libgcj@GCJ@ binary: embedded-library
--- gcc-6-6.4.0.orig/debian/libgcjLGCJ.postinst
+++ gcc-6-6.4.0/debian/libgcjLGCJ.postinst
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/libgcj@GCJ@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	  rm -rf /usr/share/doc/libgcj@GCJ@
+	  ln -s gcj-@BV@-base /usr/share/doc/libgcj@GCJ@
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/libgcjLGCJ.postrm
+++ gcc-6-6.4.0/debian/libgcjLGCJ.postrm
@@ -0,0 +1,12 @@
+#! /bin/sh -e
+
+case "$1" in
+    remove|purge)
+        # only purge if no other library is installed.
+        if [ -z "$(ls /usr/lib/libgcj.so.@GCJ@* 2>/dev/null)" ]; then
+	    rm -f /var/lib/gcj-@BV@/classmap.db
+	    rmdir --ignore-fail-on-non-empty /var/lib/gcj-@BV@ 2>/dev/null || true
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/libgfortran.symbols
+++ gcc-6-6.4.0/debian/libgfortran.symbols
@@ -0,0 +1,12 @@
+libgfortran.so.3 #PACKAGE# #MINVER#
+ (symver)F2C_1.0 4.3
+ (symver)GFORTRAN_C99_1.0 4.3
+ (symver)GFORTRAN_C99_1.1 4.5
+ (symver)GFORTRAN_1.0 4.3
+ (symver)GFORTRAN_1.1 4.4
+ (symver)GFORTRAN_1.2 4.5
+ (symver)GFORTRAN_1.3 4.6
+ (symver)GFORTRAN_1.4 4.6
+ (symver)GFORTRAN_1.5 4.8
+ (symver)GFORTRAN_1.6 5
+ (symver)GFORTRAN_1.7 6
--- gcc-6-6.4.0.orig/debian/libgnat-BV.overrides
+++ gcc-6-6.4.0/debian/libgnat-BV.overrides
@@ -0,0 +1 @@
+libgnat-@BV@ binary: package-name-doesnt-match-sonames
--- gcc-6-6.4.0.orig/debian/libgnatprjBV.overrides
+++ gcc-6-6.4.0/debian/libgnatprjBV.overrides
@@ -0,0 +1 @@
+libgnatprj@BV@ binary: missing-dependency-on-libc
--- gcc-6-6.4.0.orig/debian/libgnatvsnBV.overrides
+++ gcc-6-6.4.0/debian/libgnatvsnBV.overrides
@@ -0,0 +1 @@
+libgnatvsn@BV@ binary: missing-dependency-on-libc
--- gcc-6-6.4.0.orig/debian/libgomp.symbols
+++ gcc-6-6.4.0/debian/libgomp.symbols
@@ -0,0 +1,18 @@
+libgomp.so.1 #PACKAGE# #MINVER#
+ (symver)GOACC_2.0 5
+ (symver)GOACC_2.0.1 6
+ (symver)GOMP_1.0 4.2.1
+ (symver)GOMP_2.0 4.4
+ (symver)GOMP_3.0 4.7
+ (symver)GOMP_4.0 4.9
+ (symver)GOMP_4.0.1 5
+ (symver)GOMP_4.5 6
+ (symver)GOMP_PLUGIN_1.0 5
+ (symver)GOMP_PLUGIN_1.1 6
+ (symver)OACC_2.0 5
+ (symver)OMP_1.0 4.2.1
+ (symver)OMP_2.0 4.2.1
+ (symver)OMP_3.0 4.4
+ (symver)OMP_3.1 4.7
+ (symver)OMP_4.0 4.9
+ (symver)OMP_4.5 6
--- gcc-6-6.4.0.orig/debian/libgphobos.symbols
+++ gcc-6-6.4.0/debian/libgphobos.symbols
@@ -0,0 +1,12 @@
+libgdruntime.so.68 #PACKAGE# #MINVER#
+#(arch-bits=32)#include "libgphobos.symbols.rt32"
+#(arch-bits=64)#include "libgphobos.symbols.rt64"
+(arch=i386 x32 kfreebsd-i386)#include "libgphobos.symbols.rt32"
+(arch=amd64 kfreebsd-amd64)#include "libgphobos.symbols.rt64"
+(arch=armel armhf)#include "libgphobos.symbols.rtarm32"
+libgphobos.so.68 #PACKAGE# #MINVER#
+#(arch-bits=32)#include "libgphobos.symbols.32"
+#(arch-bits=64)#include "libgphobos.symbols.64"
+(arch=i386 x32 kfreebsd-i386)#include "libgphobos.symbols.32"
+(arch=amd64 kfreebsd-amd64)#include "libgphobos.symbols.64"
+(arch=armel armhf)#include "libgphobos.symbols.arm32"
--- gcc-6-6.4.0.orig/debian/libgphobos.symbols.32
+++ gcc-6-6.4.0/debian/libgphobos.symbols.32
@@ -0,0 +1,10380 @@
+ ZLIB_VERNUM@Base 6
+ ZLIB_VERSION@Base 6
+ Z_NULL@Base 6
+ _D100TypeInfo_S3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z13PackedPtrImpl6__initZ@Base 6
+ _D100TypeInfo_S3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D100TypeInfo_S3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D100TypeInfo_S3std9algorithm9iteration40__T8splitterVAyaa6_61203d3d2062TAyaTAyaZ8splitterFAyaAyaZ6Result6__initZ@Base 6
+ _D101TypeInfo_S3std5regex67__T10RegexMatchTAaS453std5regex8internal8thompson15ThompsonMatcherZ10RegexMatch6__initZ@Base 6
+ _D102TypeInfo_S3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9Intervals6__initZ@Base 6
+ _D102TypeInfo_S3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
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+ _D3std3uni22toLowerSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toTitleSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toTitleSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toUpperSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toUpperSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni23__T13copyBackwardsTkTkZ13copyBackwardsFNaNbNiNfAkAkZv@Base 6
+ _D3std3uni23__T15packedArrayViewThZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni23__T15packedArrayViewTtZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni23genUnrolledSwitchSearchFkZAya@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZb@Base 6
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+ _D3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits6__initZ@Base 6
+ _D3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits6__initZ@Base 6
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+ _D3std3uni24__T9sliceBitsVki14Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVki14Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZh@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl11simpleWriteMFNaNbNiNehkZv@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNehkZv@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZh@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii4Vii9Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii5Vii8Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii6Vii7Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieThVii8Vii7Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryZxS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTtVii8Vii7Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryZxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTtVii8Vii8Vii5Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryZxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZt@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNetkZv@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNetkZv@Base 6
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+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZt@Base 6
+ _D3std3uni26__T16propertyNameLessTaTaZ16propertyNameLessFNaNfAxaAxaZb@Base 6
+ _D3std3uni27__T13replicateBitsVki4Vki8Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T13replicateBitsVki1Vki32Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T13replicateBitsVki2Vki16Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T13replicateBitsVki32Vki1Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T20isPrettyPropertyNameTaZ20isPrettyPropertyNameFNaNfxAaZb@Base 6
+ _D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZb@Base 6
+ _D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZi@Base 6
+ _D3std3uni29__T6asTrieTbVii7Vii4Vii4Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryZxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni31__T16codepointSetTrieVii13Vii8Z87__T16codepointSetTrieTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ16codepointSetTrieFNaNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplKxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNehkZv@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNehkkZv@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl77__T8opEqualsTS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZb@Base 6
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+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl6__initZ@Base 6
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+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl78__T8opEqualsTS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZb@Base 6
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+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZt@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T8CowArrayTS3std3uni8GcPolicyZ8CowArray10__postblitMFNaNbNiNeZv@Base 6
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+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki8Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki11Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki12Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki13Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki14Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki16Z9BitPackedkZv@Base 6
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+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
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+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVki1Z9BitPackedkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNebkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVki1Z9BitPackedkkZv@Base 6
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+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
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+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTbVki1Z9BitPacked@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl118__T8opEqualsTxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki7Z9BitPackedkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki7Z9BitPackedkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl118__T8opEqualsTxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkkZv@Base 6
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+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxuZ10decodeImplFNaKAxuKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxwZ10decodeImplFNaKAxwKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ10decodeImplFKAyaKkZ18__T9exceptionTAyaZ9exceptionFNaNfAyaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ10decodeImplFNaKAyaKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ10decodeImplFKxAaKkZ18__T9exceptionTAxaZ9exceptionFNaNfAxaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ10decodeImplFNaKxAaKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAuZ10decodeImplFNaKxAuKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAwZ10decodeImplFNaKxAwKkZw@Base 6
+ _D3std3utf10strideImplFNaNeakZk@Base 6
+ _D3std3utf12UTFException11setSequenceMFNaNbNiNfAkXC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__ctorMFNaNfAyakAyakC6object9ThrowableZC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__initZ@Base 6
+ _D3std3utf12UTFException6__vtblZ@Base 6
+ _D3std3utf12UTFException7__ClassZ@Base 6
+ _D3std3utf12UTFException8toStringMFZAya@Base 6
+ _D3std3utf12__ModuleInfoZ@Base 6
+ _D3std3utf12isValidDcharFNaNbNiNfwZb@Base 6
+ _D3std3utf14__T6byCharTAaZ6byCharFNaNbNiNfAaZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf14__T6strideTAaZ6strideFNaNfAaZk@Base 6
+ _D3std3utf14__T6toUTFzTPaZ15__T6toUTFzTAyaZ6toUTFzFNaNbNfAyaZPa@Base 6
+ _D3std3utf15__T6byCharTAxaZ6byCharFNaNbNiNfAxaZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf15__T6byCharTAyaZ6byCharFNaNbNiNfAyaZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf15__T6strideTAxaZ6strideFNaNfAxakZk@Base 6
+ _D3std3utf15__T6strideTAxaZ6strideFNaNfKAxakZk@Base 6
+ _D3std3utf15__T6strideTAyaZ6strideFNaNfKAyakZk@Base 6
+ _D3std3utf16__T7byDcharTAyaZ7byDcharFNaNbNiNfAyaZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf17__T8validateTAxaZ8validateFNaNfxAaZv@Base 6
+ _D3std3utf17__T8validateTAxuZ8validateFNaNfxAuZv@Base 6
+ _D3std3utf17__T8validateTAxwZ8validateFNaNfxAwZv@Base 6
+ _D3std3utf18__T10codeLengthTaZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10codeLengthTuZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10codeLengthTwZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10toUCSindexTaZ10toUCSindexFNaNfAxakZk@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfkZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfkkZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZk@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFNaNbNiNfAaZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10codeLengthTyaZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfkZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfkkZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFNaNbNiNfAxaZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfkZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfkkZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFNaNbNiNfAyaZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10strideBackTAxaZ10strideBackFNaNfKAxakZk@Base 6
+ _D3std3utf20__T10strideBackTAyaZ10strideBackFNaNfKAyakZk@Base 6
+ _D3std3utf23__T10toUTFzImplTPaTAxaZ10toUTFzImplFNaNbNfAxaZPa@Base 6
+ _D3std3utf23__T10toUTFzImplTPaTAyaZ10toUTFzImplFNaNbNfAyaZPa@Base 6
+ _D3std3utf28__T20canSearchInCodeUnitsTaZ20canSearchInCodeUnitsFNaNbNiNfwZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNaNbNiNfS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl11__xopEqualsFKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImplKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImplZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl4saveMFNaNbNdNiNfZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl@Base 6
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+ _D3std4conv16__T5parseThTAxaZ5parseFNaNfKAxakZh@Base 6
+ _D3std4conv16__T5parseTiTAxaZ5parseFNaNfKAxaZi@Base 6
+ _D3std4conv16__T5parseTkTAxaZ5parseFNaNfKAxaZk@Base 6
+ _D3std4conv16__T5parseTtTAxaZ5parseFNaNfKAxaZt@Base 6
+ _D3std4conv16__T5toStrTAyaTaZ5toStrFNaNfaZAya@Base 6
+ _D3std4conv16__T5toStrTAyaTbZ5toStrFNaNbNiNfbZAya@Base 6
+ _D3std4conv16__T5toStrTAyaTwZ5toStrFNaNfwZAya@Base 6
+ _D3std4conv16__T6toImplThTxkZ6toImplFNaNfxkZh@Base 6
+ _D3std4conv16__T6toImplThTxkZ6toImplFxkZ17__T9__lambda2TxkZ9__lambda2FNaNbNiNeKxkZh@Base 6
+ _D3std4conv16__T6toImplTiTxhZ6toImplFNaNbNiNfxhZi@Base 6
+ _D3std4conv16__T6toImplTiTxkZ6toImplFNaNfxkZi@Base 6
+ _D3std4conv16__T6toImplTiTxsZ6toImplFNaNbNiNfxsZi@Base 6
+ _D3std4conv16__T6toImplTiTykZ6toImplFNaNfykZi@Base 6
+ _D3std4conv16__T8unsignedTxkZ8unsignedFNaNbNiNfxkZk@Base 6
+ _D3std4conv16__T8unsignedTxlZ8unsignedFNaNbNiNfxlZm@Base 6
+ _D3std4conv16__T8unsignedTxmZ8unsignedFNaNbNiNfxmZm@Base 6
+ _D3std4conv16__T8unsignedTyhZ8unsignedFNaNbNiNfyhZh@Base 6
+ _D3std4conv16testEmplaceChunkFNaNbNiAvkkAyaZv@Base 6
+ _D3std4conv174__T11emplaceImplTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ174__T11emplaceImplTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ11emplaceImplFNaNbNcNiNfKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv174__T11emplaceImplTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ69__T11emplaceImplTAyaTAxaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ11emplaceImplFNaNbNcNiNfKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKAyaKAxaKS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv17__T4textTAyaTAxaZ4textFNaNbNfAyaAxaZAya@Base 6
+ _D3std4conv17__T4textTAyaTAyaZ4textFNaNbNfAyaAyaZAya@Base 6
+ _D3std4conv17__T5toStrTAyaTPvZ5toStrFNaNfPvZAya@Base 6
+ _D3std4conv17__T5toStrTAyaTxaZ5toStrFNaNfxaZAya@Base 6
+ _D3std4conv17__T5toStrTAyaTxdZ5toStrFNfxdZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTaZ6toImplFNaNfaZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTbZ6toImplFNaNbNiNfbZAya@Base 6
+ _D3std4conv17__T6toImplTAyaThZ6toImplFNaNbNehkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaThZ6toImplFNaNbNfhZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTiZ6toImplFNaNbNeikE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTiZ6toImplFNaNbNfiZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTkZ6toImplFNaNbNekkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTkZ6toImplFNaNbNfkZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTtZ6toImplFNaNbNetkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTtZ6toImplFNaNbNftZAya@Base 6
+ _D3std4conv17__T6toImplTAyaTwZ6toImplFNaNfwZAya@Base 6
+ _D3std4conv17__T6toImplTtTAxaZ6toImplFNaNfAxaZt@Base 6
+ _D3std4conv181__T18emplaceInitializerTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ18emplaceInitializerFNaNbNcNiNeKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv18__T5toStrTAyaTAyhZ5toStrFNaNfAyhZAya@Base 6
+ _D3std4conv18__T5toStrTAyaTPxhZ5toStrFNaNfPxhZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTAaZ6toImplFNaNbNfAaZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTPaZ6toImplFNaNbPaZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTPvZ6toImplFNaNfPvZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxaZ6toImplFNaNfxaZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxdZ6toImplFNfxdZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxlZ6toImplFNaNbNexlkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxlZ6toImplFNaNbNfxlZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxmZ6toImplFNaNbNexmkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTxmZ6toImplFNaNbNfxmZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTyhZ6toImplFNaNbNeyhkE3std5ascii10LetterCaseZAya@Base 6
+ _D3std4conv18__T6toImplTAyaTyhZ6toImplFNaNbNfyhZAya@Base 6
+ _D3std4conv19__T11emplaceImplTaZ19__T11emplaceImplTaZ11emplaceImplFNaNbNcNiNfKaKaZa@Base 6
+ _D3std4conv19__T11emplaceImplThZ19__T11emplaceImplThZ11emplaceImplFNaNbNcNiNfKhKhZh@Base 6
+ _D3std4conv19__T11emplaceImplTwZ19__T11emplaceImplTwZ11emplaceImplFNaNbNcNiNfKwKwZw@Base 6
+ _D3std4conv19__T4textTAyaTAyaTkZ4textFNaNbNfAyaAyakZAya@Base 6
+ _D3std4conv19__T4textTAyaTkTAyaZ4textFNaNbNfAyakAyaZAya@Base 6
+ _D3std4conv19__T4textTAyaTwTAyaZ4textFNaNfAyawAyaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTAxaZ6toImplFNaNbNfAxaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTAyaZ6toImplFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTAyhZ6toImplFNaNfAyhZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTPxaZ6toImplFNaNbPxaZAya@Base 6
+ _D3std4conv19__T6toImplTAyaTPxhZ6toImplFNaNfPxhZAya@Base 6
+ _D3std4conv20__T10emplaceRefTaTaZ10emplaceRefFNaNbNcNiNfKaKaZa@Base 6
+ _D3std4conv20__T10emplaceRefTaTaZ10emplaceRefFNaNbNcNiNfKaaZa@Base 6
+ _D3std4conv20__T10emplaceRefThThZ10emplaceRefFNaNbNcNiNfKhKhZh@Base 6
+ _D3std4conv20__T10emplaceRefTwTwZ10emplaceRefFNaNbNcNiNfKwKwZw@Base 6
+ _D3std4conv20__T11emplaceImplTxaZ20__T11emplaceImplTxaZ11emplaceImplFNaNbNcNiNfKaKxaZa@Base 6
+ _D3std4conv20__T4textTAyaTxaTAyaZ4textFNaNfAyaxaAyaZAya@Base 6
+ _D3std4conv20__T9convErrorTAxaThZ9convErrorFNaNfAxaiAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv20__T9convErrorTAxaTiZ9convErrorFNaNfAxaAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv20__T9convErrorTAxaTkZ9convErrorFNaNfAxaAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv20__T9convErrorTAxaTtZ9convErrorFNaNfAxaAyakZC3std4conv13ConvException@Base 6
+ _D3std4conv20isOctalLiteralStringFAyaZb@Base 6
+ _D3std4conv20strippedOctalLiteralFAyaZAya@Base 6
+ _D3std4conv21ConvOverflowException6__ctorMFNaNbNfAyaAyakZC3std4conv21ConvOverflowException@Base 6
+ _D3std4conv21ConvOverflowException6__initZ@Base 6
+ _D3std4conv21ConvOverflowException6__vtblZ@Base 6
+ _D3std4conv21ConvOverflowException7__ClassZ@Base 6
+ _D3std4conv21__T11emplaceImplTAxaZ21__T11emplaceImplTAxaZ11emplaceImplFNaNbNcNiNfKAxaKAxaZAxa@Base 6
+ _D3std4conv21__T11emplaceImplTAyaZ21__T11emplaceImplTAyaZ11emplaceImplFNaNbNcNiNfKAyaKAyaZAya@Base 6
+ _D3std4conv21__T4textTAxaTAyaTAxaZ4textFNaNbNfAxaAyaAxaZAya@Base 6
+ _D3std4conv21__T4textTAyaTAxaTAyaZ4textFNaNbNfAyaAxaAyaZAya@Base 6
+ _D3std4conv21__T4textTAyaTAyaTAyaZ4textFNaNbNfAyaAyaAyaZAya@Base 6
+ _D3std4conv21__T4textTAyaTkTAyaTkZ4textFNaNbNfAyakAyakZAya@Base 6
+ _D3std4conv21__T4textTPxhTAyaTPxhZ4textFNaNfPxhAyaPxhZAya@Base 6
+ _D3std4conv21__T8textImplTAyaTAyaZ8textImplFNaNbNiNfAyaZAya@Base 6
+ _D3std4conv221__T7emplaceTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueTAyaTAxaTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ7emplaceFNaNbNiNfPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKAyaKAxaS3std5regex8internal2ir12__T5RegexTaZ5RegexZPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv23__T8textImplTAyaTAyaTaZ8textImplFNaNfAyaaZAya@Base 6
+ _D3std4conv24__T10emplaceRefTAyaTAyaZ10emplaceRefFNaNbNcNiNfKAyaKAyaZAya@Base 6
+ _D3std4conv24__T10emplaceRefTxaTaTxaZ10emplaceRefFNaNbNcNiNfKaKxaZa@Base 6
+ _D3std4conv24__T8textImplTAyaTAyaTxaZ8textImplFNaNfAyaxaZAya@Base 6
+ _D3std4conv25__T4textTAyaTkTAyaTkTAyaZ4textFNaNbNfAyakAyakAyaZAya@Base 6
+ _D3std4conv25__T5octalTiVAyaa3_363630Z5octalFNaNbNdNiNfZi@Base 6
+ _D3std4conv25__T5octalTiVAyaa3_363636Z5octalFNaNbNdNiNfZi@Base 6
+ _D3std4conv25__T5octalTiVAyaa3_373737Z5octalFNaNbNdNiNfZi@Base 6
+ _D3std4conv25__T8textImplTAyaTAyaTAxaZ8textImplFNaNbNfAyaAxaZAya@Base 6
+ _D3std4conv25__T8textImplTAyaTAyaTAyaZ8textImplFNaNbNfAyaAyaZAya@Base 6
+ _D3std4conv27__T4textTAyaTAyaTAyaTiTAyaZ4textFNaNbNfAyaAyaAyaiAyaZAya@Base 6
+ _D3std4conv27__T8textImplTAyaTAyaTAyaTkZ8textImplFNaNbNfAyaAyakZAya@Base 6
+ _D3std4conv27__T8textImplTAyaTAyaTkTAyaZ8textImplFNaNbNfAyakAyaZAya@Base 6
+ _D3std4conv27__T8textImplTAyaTAyaTwTAyaZ8textImplFNaNfAyawAyaZAya@Base 6
+ _D3std4conv28__T8textImplTAyaTAyaTxaTAyaZ8textImplFNaNfAyaxaAyaZAya@Base 6
+ _D3std4conv29__T4textTAyaTAyaTAyaTAxaTAyaZ4textFNaNbNfAyaAyaAyaAxaAyaZAya@Base 6
+ _D3std4conv29__T4textTAyaTAyaTiTAyaTiTAyaZ4textFNaNbNfAyaAyaiAyaiAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAxaTAyaTAxaZ8textImplFNaNbNfAxaAyaAxaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTAxaTAyaZ8textImplFNaNbNfAyaAxaAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTAyaTAyaZ8textImplFNaNbNfAyaAyaAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTkTAyaTkZ8textImplFNaNbNfAyakAyakZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTPxhTAyaTPxhZ8textImplFNaNfPxhAyaPxhZAya@Base 6
+ _D3std4conv30__T20convError_unexpectedTAxaZ20convError_unexpectedFNaNfAxaZAya@Base 6
+ _D3std4conv326__T7emplaceTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ7emplaceFNaNbNiNfPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv33__T8textImplTAyaTAyaTkTAyaTkTAyaZ8textImplFNaNbNfAyakAyakAyaZAya@Base 6
+ _D3std4conv34__T6toImplTiTE3std8datetime5MonthZ6toImplFNaNbNiNfE3std8datetime5MonthZi@Base 6
+ _D3std4conv35__T6toImplTiTxE3std8datetime5MonthZ6toImplFNaNbNiNfxE3std8datetime5MonthZi@Base 6
+ _D3std4conv35__T8textImplTAyaTAyaTAyaTAyaTiTAyaZ8textImplFNaNbNfAyaAyaAyaiAyaZAya@Base 6
+ _D3std4conv36__T4textTE3std5regex8internal2ir2IRZ4textFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv36__T7emplaceTS3std3net4curl3FTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl3FTP4ImplZPS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv37__T11emplaceImplTS3std4file8DirEntryZ37__T11emplaceImplTS3std4file8DirEntryZ11emplaceImplFNaNbNcNiNfKS3std4file8DirEntryKS3std4file8DirEntryZS3std4file8DirEntry@Base 6
+ _D3std4conv37__T5toStrTAyaTS3std11concurrency3TidZ5toStrFS3std11concurrency3TidZAya@Base 6
+ _D3std4conv37__T7emplaceTS3std3net4curl4HTTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl4HTTP4ImplZPS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv37__T7emplaceTS3std3net4curl4SMTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl4SMTP4ImplZPS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv37__T8textImplTAyaTAyaTAyaTAyaTAxaTAyaZ8textImplFNaNbNfAyaAyaAyaAxaAyaZAya@Base 6
+ _D3std4conv37__T8textImplTAyaTAyaTAyaTiTAyaTiTAyaZ8textImplFNaNbNfAyaAyaiAyaiAyaZAya@Base 6
+ _D3std4conv38__T6toImplTAyaTS3std11concurrency3TidZ6toImplFS3std11concurrency3TidZAya@Base 6
+ _D3std4conv40__T7emplaceTS3std4file15DirIteratorImplZ7emplaceFNaNbNiNfPS3std4file15DirIteratorImplZPS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv41__T11emplaceImplTS3std3net4curl3FTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv41__T5toStrTyAaTE3std5regex8internal2ir2IRZ5toStrFNaNfE3std5regex8internal2ir2IRZyAa@Base 6
+ _D3std4conv41__T5toStrTyAaTE3std6socket12SocketOptionZ5toStrFNaNfE3std6socket12SocketOptionZyAa@Base 6
+ _D3std4conv42__T11emplaceImplTS3std3net4curl4HTTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl4HTTP4ImplZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv42__T11emplaceImplTS3std3net4curl4SMTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv42__T6toImplTAyaTE3std5regex8internal2ir2IRZ6toImplFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv42__T6toImplTAyaTE3std6socket12SocketOptionZ6toImplFNaNfE3std6socket12SocketOptionZAya@Base 6
+ _D3std4conv43__T11emplaceImplTS3std6socket11AddressInfoZ43__T11emplaceImplTS3std6socket11AddressInfoZ11emplaceImplFNaNbNcNiNfKS3std6socket11AddressInfoKS3std6socket11AddressInfoZS3std6socket11AddressInfo@Base 6
+ _D3std4conv44__T8textImplTAyaTE3std5regex8internal2ir2IRZ8textImplFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv45__T11emplaceImplTS3std4file15DirIteratorImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv45__T11emplaceImplTS3std4file15DirIteratorImplZ43__T11emplaceImplTAyaTE3std4file8SpanModeTbZ11emplaceImplFNcKS3std4file15DirIteratorImplKAyaKE3std4file8SpanModeKbZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv46__T11emplaceImplTS3std3uni17CodepointIntervalZ46__T11emplaceImplTS3std3uni17CodepointIntervalZ11emplaceImplFNaNbNcNiNfKS3std3uni17CodepointIntervalKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std4conv48__T18emplaceInitializerTS3std3net4curl3FTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl3FTP4ImplZ4inityS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv48__T18emplaceInitializerTS3std3net4curl3FTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv48__T5toStrTAyaTPS3std11parallelism12AbstractTaskZ5toStrFNaNfPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv48__T6toImplTiTE3std3net7isemail15EmailStatusCodeZ6toImplFNaNbNiNfE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4HTTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl4HTTP4ImplZ4inityS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4HTTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl4HTTP4ImplZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4SMTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl4SMTP4ImplZ4inityS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4SMTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv49__T5toStrTAyaTC3std11concurrency14LinkTerminatedZ5toStrFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv49__T6toImplTAyaTPS3std11parallelism12AbstractTaskZ6toImplFNaNfPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv50__T11emplaceImplTS3std5regex8internal2ir8BytecodeZ50__T11emplaceImplTS3std5regex8internal2ir8BytecodeZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir8BytecodeKS3std5regex8internal2ir8BytecodeZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std4conv50__T5toStrTAyaTC3std11concurrency15OwnerTerminatedZ5toStrFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv50__T6toImplTAyaTC3std11concurrency14LinkTerminatedZ6toImplFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv51__T6toImplTAyaTC3std11concurrency15OwnerTerminatedZ6toImplFC3std11concurrency15OwnerTerminatedZAya@Base 6
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+ _D3std4conv52__T18emplaceInitializerTS3std4file15DirIteratorImplZ18emplaceInitializerFNaNbNcNiNeKS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
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+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6finishMFNaNbNiNeZG28h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6finishMFNaNbNiNeZG32h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6finishMFNaNbNiNeZG48h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6finishMFNaNbNiNeZG64h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9constantsyG80m@Base 6
+ _D3std6digest6digest12__ModuleInfoZ@Base 6
+ _D3std6digest6digest18__T7asArrayVki4ThZ7asArrayFNaNbNcNiKAhAyaZG4h@Base 6
+ _D3std6digest6digest19__T7asArrayVki16ThZ7asArrayFNaNbNcNiKAhAyaZG16h@Base 6
+ _D3std6digest6digest19__T7asArrayVki20ThZ7asArrayFNaNbNcNiKAhAyaZG20h@Base 6
+ _D3std6digest6digest19__T7asArrayVki28ThZ7asArrayFNaNbNcNiKAhAyaZG28h@Base 6
+ _D3std6digest6digest19__T7asArrayVki32ThZ7asArrayFNaNbNcNiKAhAyaZG32h@Base 6
+ _D3std6digest6digest19__T7asArrayVki48ThZ7asArrayFNaNbNcNiKAhAyaZG48h@Base 6
+ _D3std6digest6digest19__T7asArrayVki64ThZ7asArrayFNaNbNcNiKAhAyaZG64h@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest4peekMxFNaNbNeMAhZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest4peekMxFNaNbNeZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest42__T13WrapperDigestTS3std6digest3crc5CRC32Z13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest49__T13WrapperDigestTS3std6digest6ripemd9RIPEMD160Z13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii160Z3SHAZ13WrapperDigest7__ClassZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest62__T13WrapperDigestTS3std6digest3sha20__T3SHAVii512Vii224Z3SHAZ13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
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+ _D3std6format15__T6formatTaTkZ6formatFNaNfxAakZAya@Base 6
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+ _D3std8internal4math12biguintnoasm15multibyteSquareFNaNbNiNfAkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm18multibyteDivAssignFNaNbNiNfAkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteAddSubVai43Z15multibyteAddSubFNaNbNiNfAkAxkAxkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteAddSubVai45Z15multibyteAddSubFNaNbNiNfAkAxkAxkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteMulAddVai43Z15multibyteMulAddFNaNbNiNfAkAxkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm26__T15multibyteMulAddVai45Z15multibyteMulAddFNaNbNiNfAkAxkkkZk@Base 6
+ _D3std8internal4math12biguintnoasm27multibyteAddDiagonalSquaresFNaNbNiNfAkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm27multibyteMultiplyAccumulateFNaNbNiNfAkAxkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm27multibyteTriangleAccumulateFNaNbNiNfAkAxkZv@Base 6
+ _D3std8internal4math12biguintnoasm35__T24multibyteIncrementAssignVai43Z24multibyteIncrementAssignFNaNbNiNfAkkZk@Base 6
+ _D3std8internal4math12biguintnoasm35__T24multibyteIncrementAssignVai45Z24multibyteIncrementAssignFNaNbNiNfAkkZk@Base 6
+ _D3std8internal4math13errorfunction12__ModuleInfoZ@Base 6
+ _D3std8internal4math13errorfunction1PyG10e@Base 6
+ _D3std8internal4math13errorfunction1QyG11e@Base 6
+ _D3std8internal4math13errorfunction1RyG5e@Base 6
+ _D3std8internal4math13errorfunction1SyG6e@Base 6
+ _D3std8internal4math13errorfunction1TyG7e@Base 6
+ _D3std8internal4math13errorfunction1UyG7e@Base 6
+ _D3std8internal4math13errorfunction20__T12rationalPolyTeZ12rationalPolyFNaNbNiNfeAxeAxeZe@Base 6
+ _D3std8internal4math13errorfunction22normalDistributionImplFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P0yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P1yG10e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P2yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2P3yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q0yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q1yG10e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q2yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZ2Q3yG8e@Base 6
+ _D3std8internal4math13errorfunction25normalDistributionInvImplFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction3erfFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction4erfcFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction5EXP_2ye@Base 6
+ _D3std8internal4math13errorfunction5erfceFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13errorfunction5expx2FNaNbNiNfeiZe@Base 6
+ _D3std8internal4math13gammafunction10EULERGAMMAye@Base 6
+ _D3std8internal4math13gammafunction11logmdigammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction12__ModuleInfoZ@Base 6
+ _D3std8internal4math13gammafunction13gammaStirlingFNaNbNiNfeZ19LargeStirlingCoeffsyG7e@Base 6
+ _D3std8internal4math13gammafunction13gammaStirlingFNaNbNiNfeZ19SmallStirlingCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction13gammaStirlingFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction14betaIncompleteFNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction15gammaIncompleteFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction16GammaSmallCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction16igammaTemmeLargeFNaNbNiNfeeZ4coefyG13Ae@Base 6
+ _D3std8internal4math13gammafunction16igammaTemmeLargeFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction17betaIncompleteInvFNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction17logGammaNumeratoryG7e@Base 6
+ _D3std8internal4math13gammafunction18betaDistExpansion1FNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction18betaDistExpansion2FNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction18logmdigammaInverseFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction19GammaSmallNegCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction19betaDistPowerSeriesFNaNbNiNfeeeZe@Base 6
+ _D3std8internal4math13gammafunction19logGammaDenominatoryG8e@Base 6
+ _D3std8internal4math13gammafunction20GammaNumeratorCoeffsyG8e@Base 6
+ _D3std8internal4math13gammafunction20gammaIncompleteComplFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction22GammaDenominatorCoeffsyG9e@Base 6
+ _D3std8internal4math13gammafunction22logGammaStirlingCoeffsyG7e@Base 6
+ _D3std8internal4math13gammafunction23gammaIncompleteComplInvFNaNbNiNfeeZe@Base 6
+ _D3std8internal4math13gammafunction4Bn_nyG7e@Base 6
+ _D3std8internal4math13gammafunction5gammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction7digammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4math13gammafunction8logGammaFNaNbNiNfeZe@Base 6
+ _D3std8internal4test10dummyrange12__ModuleInfoZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange13opIndexAssignMFNaNbNiNfkkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opIndexMNgFNaNbNcNiNfkZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opSliceMFNaNbNiNfkkZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
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+ _D3std9exception14RangePrimitive6__initZ@Base 6
+ _D3std9exception14__T7enforceTbZ7enforceFNaNfbLC6object9ThrowableZb@Base 6
+ _D3std9exception150__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa44_2e2e2f2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1588Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ (optional)_D3std9exception166__T12errnoEnforceTbVAyaa71_2f686f6d652f7061636b616765732f6763632f372f6763632d372d372d32303136313131362f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vki557Z12errnoEnforceFNfbLAyaZb@Base 6
+ (optional)_D3std9exception166__T12errnoEnforceTiVAyaa71_2f686f6d652f7061636b616765732f6763632f372f6763632d372d372d32303136313131362f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vki557Z12errnoEnforceFNfiLAyaZi@Base 6
+ (optional)_D3std9exception203__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa71_2f686f6d652f7061636b616765732f6763632f372f6763632d372d372d32303136313131362f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vki557Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception207__T11doesPointToTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception20__T12assumeUniqueTaZ12assumeUniqueFNaNbNiAaZAya@Base 6
+ _D3std9exception20__T12assumeUniqueTaZ12assumeUniqueFNaNbNiKAaZAya@Base 6
+ _D3std9exception20__T12assumeUniqueTkZ12assumeUniqueFNaNbNiKAkZAyk@Base 6
+ _D3std9exception25__T11doesPointToTAkTAkTvZ11doesPointToFNaNbNiNeKxAkKxAkZb@Base 6
+ _D3std9exception25__T7bailOutHTC9ExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTiZ7enforceFNaNfiLAxaAyakZi@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTkZ7enforceFNaNfkLAxaAyakZk@Base 6
+ _D3std9exception289__T11doesPointToTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception28__T7enforceHTC9ExceptionTPvZ7enforceFNaNfPvLAxaAyakZPv@Base 6
+ _D3std9exception291__T11doesPointToTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception291__T11doesPointToTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception297__T11doesPointToTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception29__T11doesPointToTAAyaTAAyaTvZ11doesPointToFNaNbNiNeKxAAyaKxAAyaZb@Base 6
+ _D3std9exception37__T16collectExceptionHTC9ExceptionTmZ16collectExceptionFNaNbNfLmZC9Exception@Base 6
+ _D3std9exception39__T7bailOutHTC3std4json13JSONExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception40__T11doesPointToTAyaTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxAyaKxS3std5stdio4FileZb@Base 6
+ _D3std9exception40__T7bailOutHTC4core4time13TimeExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception41__T18isUnionAliasedImplTS3std5stdio4FileZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception41__T7enforceHTC3std4json13JSONExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception41__T9enforceExHTC3std4json13JSONExceptionZ16__T9enforceExTbZ9enforceExFNaNfbLAyaAyakZb@Base 6
+ _D3std9exception42__T7enforceHTC4core4time13TimeExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception43__T7bailOutHTC3std3net4curl13CurlExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception44__T18isUnionAliasedImplTS3std3net4curl4CurlZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception44__T18isUnionAliasedImplTS3std4file8DirEntryZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception44__T7enforceTPS4core3sys5posix5netdb7hostentZ7enforceFNaNfPS4core3sys5posix5netdb7hostentLC6object9ThrowableZPS4core3sys5posix5netdb7hostent@Base 6
+ _D3std9exception45__T11doesPointToTbTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception45__T7enforceHTC3std3net4curl13CurlExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception45__T9enforceExHTC3std6format15FormatExceptionZ16__T9enforceExTbZ9enforceExFNaNfbLAyaAyakZb@Base 6
+ _D3std9exception45__T9enforceExHTC3std6format15FormatExceptionZ16__T9enforceExTkZ9enforceExFNaNfkLAyaAyakZk@Base 6
+ _D3std9exception46__T11doesPointToTbTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception46__T11doesPointToTbTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception46__T11doesPointToTtTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxtKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception46__T7enforceHTC3std3net4curl13CurlExceptionTPvZ7enforceFNaNfPvLAxaAyakZPv@Base 6
+ _D3std9exception47__T11doesPointToTAyaTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception47__T11doesPointToTPxvTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTAyaTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTPxvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTPxvTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception48__T18isUnionAliasedImplTS3std3net4curl3FTP4ImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception49__T11doesPointToTbTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxbKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToThTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxhKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTiTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxiKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTkTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxkKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTlTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxlKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTmTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxmKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTtTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxtKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T18isUnionAliasedImplTS3std3net4curl4HTTP4ImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception49__T18isUnionAliasedImplTS3std3net4curl4SMTP4ImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception50__T11doesPointToTDFAhZkTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZkKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception50__T11doesPointToTDFAvZkTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZkKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception50__T7bailOutHTC3std3net4curl20CurlTimeoutExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception51__T11doesPointToTAyaTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAhZkTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZkKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAhZkTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZkKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAvZkTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZkKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAvZkTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZkKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFxAaZvTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFkkkkZiTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFkkkkZiKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFxAaZvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFxAaZvTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTwTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxwKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception52__T18isUnionAliasedImplTS3std4file15DirIteratorImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception52__T7enforceHTC3std3net4curl20CurlTimeoutExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception53__T11doesPointToTDFkkkkZiTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFkkkkZiKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception53__T11doesPointToTDFkkkkZiTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFkkkkZiKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception53__T11doesPointToTHAyaxAyaTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxHAyaAyaKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception53__T11doesPointToTS3std5stdio4FileTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxS3std5stdio4FileKxS3std5stdio4FileZb@Base 6
+ _D3std9exception53__T7bailOutHTC3std11concurrency19TidMissingExceptionZ7bailOutFAyakxAaZv@Base 6
+ _D3std9exception54__T11doesPointToTAyaTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxAyaKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception54__T7enforceHTC9ExceptionTPOS4core4stdc5stdio8_IO_FILEZ7enforceFNaNfPOS4core4stdc5stdio8_IO_FILELAxaAyakZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception55__T18isUnionAliasedImplTS3std5stdio17LockingTextReaderZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception55__T7enforceHTC3std11concurrency19TidMissingExceptionTbZ7enforceFbLAxaAyakZb@Base 6
+ _D3std9exception56__T18isUnionAliasedImplTS3std3net4curl4HTTP10StatusLineZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception57__T18isUnionAliasedImplTS4core3sys5posix3sys4stat6stat_tZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception60__T11doesPointToTPxS3std5stdio4File4ImplTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxPS3std5stdio4File4ImplKxS3std5stdio4FileZb@Base 6
+ _D3std9exception63__T11doesPointToTS3std3net4curl4CurlTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4CurlKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception63__T7enforceHTC3std4json13JSONExceptionTPNgS3std4json9JSONValueZ7enforceFNaNfPNgS3std4json9JSONValueLAxaAyakZPNgS3std4json9JSONValue@Base 6
+ _D3std9exception64__T11doesPointToTS3std3net4curl4CurlTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4CurlKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception64__T11doesPointToTS3std3net4curl4CurlTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4CurlKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception67__T11doesPointToTE3std4file8SpanModeTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxE3std4file8SpanModeKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception67__T11doesPointToTS3std3net4curl3FTP4ImplTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl3FTP4ImplKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception67__T11doesPointToTS3std4file8DirEntryTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS3std4file8DirEntryKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception67__T11doesPointToTS3std5stdio4FileTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxS3std5stdio4FileKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception67__T11doesPointToTlTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxlKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception69__T11doesPointToTS3std3net4curl4HTTP4ImplTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4HTTP4ImplKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception69__T11doesPointToTS3std3net4curl4SMTP4ImplTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4SMTP4ImplKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception70__T11doesPointToTPxS3etc1c4curl10curl_slistTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxPS3etc1c4curl10curl_slistKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception70__T18isUnionAliasedImplTS3std8datetime13PosixTimeZone14TempTransitionZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception71__T11doesPointToTE3std3net4curl4HTTP6MethodTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxE3std3net4curl4HTTP6MethodKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception71__T11doesPointToTPxS3etc1c4curl10curl_slistTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxPS3etc1c4curl10curl_slistKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception74__T11doesPointToTPxS3std5stdio4File4ImplTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxPS3std5stdio4File4ImplKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception75__T11doesPointToTS3std4file15DirIteratorImplTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNeKxS3std4file15DirIteratorImplKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception76__T11doesPointToTS3std3net4curl4HTTP10StatusLineTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxS3std3net4curl4HTTP10StatusLineKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception80__T11doesPointToTDFS3std3net4curl4HTTP10StatusLineZvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFS3std3net4curl4HTTP10StatusLineZvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception80__T11doesPointToTS4core3sys5posix3sys4stat6stat_tTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS4core3sys5posix3sys4stat6stat_tKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception81__T11doesPointToTS3std5stdio17LockingTextReaderTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxS3std5stdio17LockingTextReaderKxS3std5stdio17LockingTextReaderZb@Base 6
+ _D3std9exception81__T18isUnionAliasedImplTS3std5array34__T8AppenderTAS3std4file8DirEntryZ8AppenderZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception93__T11doesPointToTAS3std5regex8internal2ir10NamedGroupTAS3std5regex8internal2ir10NamedGroupTvZ11doesPointToFNaNbNiNeKxAS3std5regex8internal2ir10NamedGroupKxAS3std5regex8internal2ir10NamedGroupZb@Base 6
+ _D3std9exception93__T7enforceHTC9ExceptionTPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeZ7enforceFNaNfPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4NodeLAxaAyakZPS3std11concurrency36__T4ListTS3std11concurrency7MessageZ4List4Node@Base 6
+ _D3std9exception94__T11doesPointToTDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception95__T11doesPointToTDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFE3std6socket8socket_tE3etc1c4curl12CurlSockTypeZiKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception95__T11doesPointToTDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFlE3etc1c4curl11CurlSeekPosZE3etc1c4curl8CurlSeekKxS3std3net4curl4HTTP4ImplZb@Base 6
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+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedVmi1Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVmi1Z9BitPackedmZv@Base 6
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+ _D3std3uni8Grapheme13__T6__ctorTwZ6__ctorMFNcNexAwXS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme13opIndexAssignMFNaNbNiNewmZv@Base 6
+ _D3std3uni8Grapheme25__T10opOpAssignVAyaa1_7eZ10opOpAssignMFNcNewZS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme29__T10opOpAssignVAyaa1_7eTAxiZ10opOpAssignMFNcNeAxiZS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme29__T10opOpAssignVAyaa1_7eTAxwZ10opOpAssignMFNcNeAxwZS3std3uni8Grapheme@Base 6
+ _D3std3uni8Grapheme5isBigMxFNaNbNdNiNeZh@Base 6
+ _D3std3uni8Grapheme6__dtorMFNeZv@Base 6
+ _D3std3uni8Grapheme6__initZ@Base 6
+ _D3std3uni8Grapheme6lengthMxFNaNbNdNiNeZm@Base 6
+ _D3std3uni8Grapheme6setBigMFNaNbNiNeZv@Base 6
+ _D3std3uni8Grapheme7opIndexMxFNaNbNiNemZw@Base 6
+ _D3std3uni8Grapheme7opSliceMFNaNbNiZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni8Grapheme7opSliceMFNaNbNimmZS3std3uni41__T16SliceOverIndexedTS3std3uni8GraphemeZ16SliceOverIndexed@Base 6
+ _D3std3uni8Grapheme8opAssignMFNcNjNeS3std3uni8GraphemeZS3std3uni8Grapheme@Base 6
+ _D3std3uni8encodeToFNaNbNiNeAamwZm@Base 6
+ _D3std3uni8encodeToFNaNbNiNeAwmwZm@Base 6
+ _D3std3uni8encodeToFNaNeAumwZm@Base 6
+ _D3std3uni8isFormatFNaNbNiNfwZb@Base 6
+ _D3std3uni8isNumberFNaNbNiNfwZb@Base 6
+ _D3std3uni8isSymbolFNaNbNiNfwZb@Base 6
+ _D3std3uni8markTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni8markTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni8midlow_8FNaNbNiNfkZk@Base 6
+ _D3std3uni94__T5forceTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedTS3std3uni20__T9BitPackedTkVmi7Z9BitPackedZ5forceFNaNbNiNfS3std3uni20__T9BitPackedTkVmi7Z9BitPackedZS3std3uni20__T9BitPackedTkVmi7Z9BitPacked@Base 6
+ _D3std3uni94__T5forceTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedTS3std3uni20__T9BitPackedTkVmi8Z9BitPackedZ5forceFNaNbNiNfS3std3uni20__T9BitPackedTkVmi8Z9BitPackedZS3std3uni20__T9BitPackedTkVmi8Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedTS3std3uni21__T9BitPackedTkVmi11Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVmi11Z9BitPackedZS3std3uni21__T9BitPackedTkVmi11Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedTS3std3uni21__T9BitPackedTkVmi12Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVmi12Z9BitPackedZS3std3uni21__T9BitPackedTkVmi12Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedTS3std3uni21__T9BitPackedTkVmi13Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVmi13Z9BitPackedZS3std3uni21__T9BitPackedTkVmi13Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedTS3std3uni21__T9BitPackedTkVmi14Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVmi14Z9BitPackedZS3std3uni21__T9BitPackedTkVmi14Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedTS3std3uni21__T9BitPackedTkVmi15Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVmi15Z9BitPackedZS3std3uni21__T9BitPackedTkVmi15Z9BitPacked@Base 6
+ _D3std3uni96__T5forceTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedTS3std3uni21__T9BitPackedTkVmi16Z9BitPackedZ5forceFNaNbNiNfS3std3uni21__T9BitPackedTkVmi16Z9BitPackedZS3std3uni21__T9BitPackedTkVmi16Z9BitPacked@Base 6
+ _D3std3uni97__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTAaZ6toCaseFNaNeAaZAa@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTAxaZ6toCaseFNaNeAxaZAxa@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTAyaZ6toCaseFNaNeAyaZAya@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTAyuZ6toCaseFNaNeAyuZAyu@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toLowerIndexFNaNbNiNewZtVii1043S34_D3std3uni10toLowerTabFNaNbNiNemZwTAywZ6toCaseFNaNbNeAywZAyw@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNemZwTAyaZ6toCaseFNaNeAyaZAya@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNemZwTAyuZ6toCaseFNaNeAyuZAyu@Base 6
+ _D3std3uni98__T6toCaseS36_D3std3uni12toUpperIndexFNaNbNiNewZtVii1051S34_D3std3uni10toUpperTabFNaNbNiNemZwTAywZ6toCaseFNaNbNeAywZAyw@Base 6
+ _D3std3uni9alphaTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9alphaTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9isControlFNaNbNiNfwZb@Base 6
+ _D3std3uni9nfcQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9nfcQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9nfdQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9nfdQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVmi1Z9BitPackedTwVmi1114112TS3std3uni24__T9sliceBitsVmi13Vmi21Z9sliceBitsTS3std3uni23__T9sliceBitsVmi8Vmi13Z9sliceBitsTS3std3uni22__T9sliceBitsVmi0Vmi8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9recomposeFNaNbNemAwAhZm@Base 6
+ _D3std3uri10URI_EncodeFAywkZAya@Base 6
+ _D3std3uri12URIException6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC3std3uri12URIException@Base 6
+ _D3std3uri12URIException6__initZ@Base 6
+ _D3std3uri12URIException6__vtblZ@Base 6
+ _D3std3uri12URIException7__ClassZ@Base 6
+ _D3std3uri12__ModuleInfoZ@Base 6
+ _D3std3uri18_sharedStaticCtor1FZ6helperFyAakZv@Base 6
+ _D3std3uri18_sharedStaticCtor1FZv@Base 6
+ _D3std3uri9ascii2hexFwZk@Base 6
+ _D3std3uri9hex2asciiyG16a@Base 6
+ _D3std3uri9uri_flagsG128h@Base 6
+ _D3std3utf100__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ11decodeFrontFNaNeKAyaJmZw@Base 6
+ _D3std3utf100__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ11decodeFrontFNaNfKAyaZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ10decodeImplFKAaKmZ17__T9exceptionTAaZ9exceptionFNaNfAaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ10decodeImplFNaKAaKmZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAuZ10decodeImplFNaKAuKmZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAwZ10decodeImplFNaKAwKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ10decodeImplFKAxaKmZ18__T9exceptionTAxaZ9exceptionFNaNfAxaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ10decodeImplFNaKAxaKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxuZ10decodeImplFNaKAxuKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxwZ10decodeImplFNaKAxwKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ10decodeImplFKAyaKmZ18__T9exceptionTAyaZ9exceptionFNaNfAyaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ10decodeImplFNaKAyaKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ10decodeImplFKxAaKmZ18__T9exceptionTAxaZ9exceptionFNaNfAxaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ10decodeImplFNaKxAaKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAuZ10decodeImplFNaKxAuKmZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAwZ10decodeImplFNaKxAwKmZw@Base 6
+ _D3std3utf10strideImplFNaNeamZk@Base 6
+ _D3std3utf12UTFException11setSequenceMFNaNbNiNfAkXC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__ctorMFNaNbNfAyaAyamC6object9ThrowableZC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__ctorMFNaNfAyamAyamC6object9ThrowableZC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__initZ@Base 6
+ _D3std3utf12UTFException6__vtblZ@Base 6
+ _D3std3utf12UTFException7__ClassZ@Base 6
+ _D3std3utf12UTFException8toStringMFZAya@Base 6
+ _D3std3utf12__ModuleInfoZ@Base 6
+ _D3std3utf12isValidDcharFNaNbNiNfwZb@Base 6
+ _D3std3utf14__T6byCharTAaZ6byCharFNaNbNiNfAaZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf14__T6strideTAaZ6strideFNaNfAaZk@Base 6
+ _D3std3utf14__T6toUTFzTPaZ15__T6toUTFzTAyaZ6toUTFzFNaNbNfAyaZPa@Base 6
+ _D3std3utf15__T6byCharTAxaZ6byCharFNaNbNiNfAxaZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf15__T6byCharTAyaZ6byCharFNaNbNiNfAyaZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf15__T6strideTAxaZ6strideFNaNfAxamZk@Base 6
+ _D3std3utf15__T6strideTAxaZ6strideFNaNfKAxamZk@Base 6
+ _D3std3utf15__T6strideTAyaZ6strideFNaNfKAyamZk@Base 6
+ _D3std3utf16__T7byDcharTAyaZ7byDcharFNaNbNiNfAyaZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf17__T8validateTAxaZ8validateFNaNfxAaZv@Base 6
+ _D3std3utf17__T8validateTAxuZ8validateFNaNfxAuZv@Base 6
+ _D3std3utf17__T8validateTAxwZ8validateFNaNfxAwZv@Base 6
+ _D3std3utf18__T10codeLengthTaZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10codeLengthTuZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10codeLengthTwZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10toUCSindexTaZ10toUCSindexFNaNfAxamZm@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfmZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfmmZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZm@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFNaNbNiNfAaZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10codeLengthTyaZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfmZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfmmZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZm@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFNaNbNiNfAxaZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfmZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfmmZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZm@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFNaNbNiNfAyaZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10strideBackTAxaZ10strideBackFNaNfKAxamZk@Base 6
+ _D3std3utf20__T10strideBackTAyaZ10strideBackFNaNfKAyamZk@Base 6
+ _D3std3utf23__T10toUTFzImplTPaTAxaZ10toUTFzImplFNaNbNfAxaZPa@Base 6
+ _D3std3utf23__T10toUTFzImplTPaTAyaZ10toUTFzImplFNaNbNfAyaZPa@Base 6
+ _D3std3utf28__T20canSearchInCodeUnitsTaZ20canSearchInCodeUnitsFNaNbNiNfwZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNaNbNiNfS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl11__xopEqualsFKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImplKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImplZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl4saveMFNaNbNdNiNfZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl5frontMFNaNbNdNiNfZa@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl6__ctorMFNaNbNcNiNfKS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl6__initZ@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImpl9__xtoHashFNbNeKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplmwZ6ResultZ10byCharImplZm@Base 6
+ _D3std3utf6encodeFNaNfKAawZv@Base 6
+ _D3std3utf6encodeFNaNfKAuwZv@Base 6
+ _D3std3utf6encodeFNaNfKAwwZv@Base 6
+ _D3std3utf6encodeFNaNfKG2uwZm@Base 6
+ _D3std3utf6encodeFNaNfKG4awZm@Base 6
+ _D3std3utf6toUTF8FNaNbNiNfNkJG4awZAa@Base 6
+ _D3std3utf6toUTF8FNaNfxAaZAya@Base 6
+ _D3std3utf6toUTF8FNaNfxAuZAya@Base 6
+ _D3std3utf6toUTF8FNaNfxAwZAya@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl11__xopEqualsFKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZb@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl4saveMFNaNbNdNiNfZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl5frontMFNaNbNdNiNfZw@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__ctorMFNaNbNcNiNfKS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__initZ@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl9__xtoHashFNbNeKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZm@Base 6
+ _D3std3utf7toUTF16FNaNbNiNfNkKG2uwZAu@Base 6
+ _D3std3utf7toUTF16FNaNfxAaZAyu@Base 6
+ _D3std3utf7toUTF16FNaNfxAuZAyu@Base 6
+ _D3std3utf7toUTF16FNaNfxAwZAyu@Base 6
+ _D3std3utf7toUTF32FNaNfxAaZAyw@Base 6
+ _D3std3utf7toUTF32FNaNfxAuZAyw@Base 6
+ _D3std3utf7toUTF32FNaNfxAwZAyw@Base 6
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+ _D3std4conv29__T4textTAyaTAyaTiTAyaTiTAyaZ4textFNaNbNfAyaAyaiAyaiAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAxaTAyaTAxaZ8textImplFNaNbNfAxaAyaAxaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTAxaTAyaZ8textImplFNaNbNfAyaAxaAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTAyaTAyaZ8textImplFNaNbNfAyaAyaAyaZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTkTAyaTkZ8textImplFNaNbNfAyakAyakZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTAyaTmTAyaTmZ8textImplFNaNbNfAyamAyamZAya@Base 6
+ _D3std4conv29__T8textImplTAyaTPxhTAyaTPxhZ8textImplFNaNfPxhAyaPxhZAya@Base 6
+ _D3std4conv30__T20convError_unexpectedTAxaZ20convError_unexpectedFNaNfAxaZAya@Base 6
+ _D3std4conv326__T7emplaceTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueTS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZ7emplaceFNaNbNiNfPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueKS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5ValueZPS3std10functional114__T7memoizeS95_D3std5regex18__T9regexImplTAyaZ9regexImplFNfAyaAxaZS3std5regex8internal2ir12__T5RegexTaZ5RegexVii8Z7memoizeFAyaAxaZ5Value@Base 6
+ _D3std4conv33__T8textImplTAyaTAyaTkTAyaTmTAyaZ8textImplFNaNbNfAyakAyamAyaZAya@Base 6
+ _D3std4conv34__T6toImplTiTE3std8datetime5MonthZ6toImplFNaNbNiNfE3std8datetime5MonthZi@Base 6
+ _D3std4conv35__T6toImplTiTxE3std8datetime5MonthZ6toImplFNaNbNiNfxE3std8datetime5MonthZi@Base 6
+ _D3std4conv35__T8textImplTAyaTAyaTAyaTAyaTiTAyaZ8textImplFNaNbNfAyaAyaAyaiAyaZAya@Base 6
+ _D3std4conv36__T4textTE3std5regex8internal2ir2IRZ4textFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv36__T7emplaceTS3std3net4curl3FTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl3FTP4ImplZPS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv37__T11emplaceImplTS3std4file8DirEntryZ37__T11emplaceImplTS3std4file8DirEntryZ11emplaceImplFNaNbNcNiNfKS3std4file8DirEntryKS3std4file8DirEntryZS3std4file8DirEntry@Base 6
+ _D3std4conv37__T5toStrTAyaTS3std11concurrency3TidZ5toStrFS3std11concurrency3TidZAya@Base 6
+ _D3std4conv37__T7emplaceTS3std3net4curl4HTTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl4HTTP4ImplZPS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv37__T7emplaceTS3std3net4curl4SMTP4ImplZ7emplaceFNaNbNiNfPS3std3net4curl4SMTP4ImplZPS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv37__T8textImplTAyaTAyaTAyaTAyaTAxaTAyaZ8textImplFNaNbNfAyaAyaAyaAxaAyaZAya@Base 6
+ _D3std4conv37__T8textImplTAyaTAyaTAyaTiTAyaTiTAyaZ8textImplFNaNbNfAyaAyaiAyaiAyaZAya@Base 6
+ _D3std4conv38__T6toImplTAyaTS3std11concurrency3TidZ6toImplFS3std11concurrency3TidZAya@Base 6
+ _D3std4conv40__T7emplaceTS3std4file15DirIteratorImplZ7emplaceFNaNbNiNfPS3std4file15DirIteratorImplZPS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv41__T11emplaceImplTS3std3net4curl3FTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv41__T5toStrTyAaTE3std5regex8internal2ir2IRZ5toStrFNaNfE3std5regex8internal2ir2IRZyAa@Base 6
+ _D3std4conv41__T5toStrTyAaTE3std6socket12SocketOptionZ5toStrFNaNfE3std6socket12SocketOptionZyAa@Base 6
+ _D3std4conv42__T11emplaceImplTS3std3net4curl4HTTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl4HTTP4ImplZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv42__T11emplaceImplTS3std3net4curl4SMTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv42__T6toImplTAyaTE3std5regex8internal2ir2IRZ6toImplFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv42__T6toImplTAyaTE3std6socket12SocketOptionZ6toImplFNaNfE3std6socket12SocketOptionZAya@Base 6
+ _D3std4conv43__T11emplaceImplTS3std6socket11AddressInfoZ43__T11emplaceImplTS3std6socket11AddressInfoZ11emplaceImplFNaNbNcNiNfKS3std6socket11AddressInfoKS3std6socket11AddressInfoZS3std6socket11AddressInfo@Base 6
+ _D3std4conv44__T8textImplTAyaTE3std5regex8internal2ir2IRZ8textImplFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv45__T11emplaceImplTS3std4file15DirIteratorImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv45__T11emplaceImplTS3std4file15DirIteratorImplZ43__T11emplaceImplTAyaTE3std4file8SpanModeTbZ11emplaceImplFNcKS3std4file15DirIteratorImplKAyaKE3std4file8SpanModeKbZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv46__T11emplaceImplTS3std3uni17CodepointIntervalZ46__T11emplaceImplTS3std3uni17CodepointIntervalZ11emplaceImplFNaNbNcNiNfKS3std3uni17CodepointIntervalKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std4conv48__T18emplaceInitializerTS3std3net4curl3FTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl3FTP4ImplZ4inityS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv48__T18emplaceInitializerTS3std3net4curl3FTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
+ _D3std4conv48__T5toStrTAyaTPS3std11parallelism12AbstractTaskZ5toStrFNaNfPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv48__T6toImplTiTE3std3net7isemail15EmailStatusCodeZ6toImplFNaNbNiNfE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4HTTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl4HTTP4ImplZ4inityS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4HTTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl4HTTP4ImplZS3std3net4curl4HTTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4SMTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl4SMTP4ImplZ4inityS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4SMTP4ImplZ18emplaceInitializerFNaNbNcNiNeKS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv49__T5toStrTAyaTC3std11concurrency14LinkTerminatedZ5toStrFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv49__T6toImplTAyaTPS3std11parallelism12AbstractTaskZ6toImplFNaNfPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv50__T11emplaceImplTS3std5regex8internal2ir8BytecodeZ50__T11emplaceImplTS3std5regex8internal2ir8BytecodeZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir8BytecodeKS3std5regex8internal2ir8BytecodeZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std4conv50__T5toStrTAyaTC3std11concurrency15OwnerTerminatedZ5toStrFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv50__T6toImplTAyaTC3std11concurrency14LinkTerminatedZ6toImplFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv51__T6toImplTAyaTC3std11concurrency15OwnerTerminatedZ6toImplFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv52__T18emplaceInitializerTS3std4file15DirIteratorImplZ18emplaceInitializerFNaNbNcNeKS3std4file15DirIteratorImplZ4inityS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv52__T18emplaceInitializerTS3std4file15DirIteratorImplZ18emplaceInitializerFNaNbNcNiNeKS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv53__T11emplaceImplTS3std5regex8internal2ir10NamedGroupZ53__T11emplaceImplTS3std5regex8internal2ir10NamedGroupZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir10NamedGroupKS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std4conv55__T11emplaceImplTS3std4file15DirIteratorImpl9DirHandleZ55__T11emplaceImplTS3std4file15DirIteratorImpl9DirHandleZ11emplaceImplFNaNbNcNiNfKS3std4file15DirIteratorImpl9DirHandleKS3std4file15DirIteratorImpl9DirHandleZS3std4file15DirIteratorImpl9DirHandle@Base 6
+ _D3std4conv56__T10emplaceRefTS3std4file8DirEntryTS3std4file8DirEntryZ10emplaceRefFNaNbNcNiNfKS3std4file8DirEntryKS3std4file8DirEntryZS3std4file8DirEntry@Base 6
+ _D3std4conv61__T11emplaceImplTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ61__T11emplaceImplTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir12__T5RegexTaZ5RegexKS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std4conv65__T6toImplTiTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ6toImplFNaNbNiNfE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std4conv66__T7emplaceTS3std4file15DirIteratorImplTAyaTE3std4file8SpanModeTbZ7emplaceFPS3std4file15DirIteratorImplKAyaKE3std4file8SpanModeKbZPS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv68__T10emplaceRefTS3std6socket11AddressInfoTS3std6socket11AddressInfoZ10emplaceRefFNaNbNcNiNfKS3std6socket11AddressInfoKS3std6socket11AddressInfoZS3std6socket11AddressInfo@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni1Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni2Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni3Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni4Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni5Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni6Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni7Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni8Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni9Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni10Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni13Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni16Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni17Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni18Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni19Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni20Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni21Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni26Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni30Z7enumRepyAa@Base 6
+ _D3std4conv74__T10emplaceRefTS3std3uni17CodepointIntervalTS3std3uni17CodepointIntervalZ10emplaceRefFNaNbNcNiNfKS3std3uni17CodepointIntervalKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi128Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi129Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi130Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi132Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi133Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi134Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi136Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi137Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi138Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi140Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi141Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi142Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi144Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi145Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi146Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi148Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi149Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi150Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi152Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi153Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi154Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi156Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi157Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi158Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi160Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi161Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi162Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi164Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi168Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi172Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi176Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi180Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi184Z7enumRepyAa@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi188Z7enumRepyAa@Base 6
+ _D3std4conv79__T4textTPS3std11parallelism12AbstractTaskTaTPS3std11parallelism12AbstractTaskZ4textFNaNfPS3std11parallelism12AbstractTaskaPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv82__T10emplaceRefTS3std5regex8internal2ir8BytecodeTS3std5regex8internal2ir8BytecodeZ10emplaceRefFNaNbNcNiNfKS3std5regex8internal2ir8BytecodeKS3std5regex8internal2ir8BytecodeZS3std5regex8internal2ir8Bytecode@Base 6
+ _D3std4conv87__T8textImplTAyaTPS3std11parallelism12AbstractTaskTaTPS3std11parallelism12AbstractTaskZ8textImplFNaNfPS3std11parallelism12AbstractTaskaPS3std11parallelism12AbstractTaskZAya@Base 6
+ _D3std4conv88__T10emplaceRefTS3std5regex8internal2ir10NamedGroupTS3std5regex8internal2ir10NamedGroupZ10emplaceRefFNaNbNcNiNfKS3std5regex8internal2ir10NamedGroupKS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std4conv92__T10emplaceRefTS3std4file15DirIteratorImpl9DirHandleTS3std4file15DirIteratorImpl9DirHandleZ10emplaceRefFNaNbNcNiNfKS3std4file15DirIteratorImpl9DirHandleKS3std4file15DirIteratorImpl9DirHandleZS3std4file15DirIteratorImpl9DirHandle@Base 6
+ _D3std4conv96__T4textTAyaTPvTAyaTiTAyaTiTAyaTaTAyaThTAyaThTAyaTbTAyaTbTAyaTbTAyaTbTAyaTbTAyaTAxaTAyaTAxaTAyaZ4textFNaNfAyaPvAyaiAyaiAyaaAyahAyahAyabAyabAyabAyabAyabAyaAxaAyaAxaAyaZAya@Base 6
+ _D3std4conv9__T2toThZ10__T2toTxkZ2toFNaNfxkZh@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxhZ2toFNaNbNiNfxhZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxkZ2toFNaNfxkZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxmZ2toFNaNfxmZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTxsZ2toFNaNbNiNfxsZi@Base 6
+ _D3std4conv9__T2toTiZ10__T2toTykZ2toFNaNfykZi@Base 6
+ _D3std4conv9__T2toTiZ28__T2toTE3std8datetime5MonthZ2toFNaNbNiNfE3std8datetime5MonthZi@Base 6
+ _D3std4conv9__T2toTiZ29__T2toTxE3std8datetime5MonthZ2toFNaNbNiNfxE3std8datetime5MonthZi@Base 6
+ _D3std4conv9__T2toTiZ42__T2toTE3std3net7isemail15EmailStatusCodeZ2toFNaNbNiNfE3std3net7isemail15EmailStatusCodeZi@Base 6
+ _D3std4conv9__T2toTiZ59__T2toTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ2toFNaNbNiNfE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toThZ2toFNaNbNiNfhZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTiZ2toFNaNbNiNfiZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTkZ2toFNaNfkZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTmZ2toFNaNfmZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTsZ2toFNaNbNiNfsZi@Base 6
+ _D3std4conv9__T2toTiZ9__T2toTtZ2toFNaNbNiNftZi@Base 6
+ _D3std4conv9__T2toTkZ9__T2toTkZ2toFNaNbNiNfkZk@Base 6
+ _D3std4conv9__T2toTkZ9__T2toTmZ2toFNaNfmZk@Base 6
+ _D3std4conv9__T2toTlZ9__T2toTlZ2toFNaNbNiNflZl@Base 6
+ _D3std4conv9__T2toTlZ9__T2toTmZ2toFNaNfmZl@Base 6
+ _D3std4conv9__T2toTmZ9__T2toTkZ2toFNaNbNiNfkZm@Base 6
+ _D3std4conv9__T2toTmZ9__T2toTmZ2toFNaNbNiNfmZm@Base 6
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+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA19__T11T_SHA2_0_15TkZ11T_SHA2_0_15FNaNbNiiPxG64hKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA20__T12T_SHA2_16_79TkZ12T_SHA2_16_79FNaNbNiNfiKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA21__T13transformSHA2TkZ13transformSHA2FNaNbNiPG8kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6__initZ@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6finishMFNaNbNiNeZG28h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA19__T11T_SHA2_0_15TkZ11T_SHA2_0_15FNaNbNiiPxG64hKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA20__T12T_SHA2_16_79TkZ12T_SHA2_16_79FNaNbNiNfiKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA21__T13transformSHA2TkZ13transformSHA2FNaNbNiPG8kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6__initZ@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6finishMFNaNbNiNeZG32h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6finishMFNaNbNiNeZG28h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6finishMFNaNbNiNeZG32h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6finishMFNaNbNiNeZG48h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6finishMFNaNbNiNeZG64h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9constantsyG80m@Base 6
+ _D3std6digest6digest12__ModuleInfoZ@Base 6
+ _D3std6digest6digest18__T7asArrayVmi4ThZ7asArrayFNaNbNcNiKAhAyaZG4h@Base 6
+ _D3std6digest6digest19__T7asArrayVmi16ThZ7asArrayFNaNbNcNiKAhAyaZG16h@Base 6
+ _D3std6digest6digest19__T7asArrayVmi20ThZ7asArrayFNaNbNcNiKAhAyaZG20h@Base 6
+ _D3std6digest6digest19__T7asArrayVmi28ThZ7asArrayFNaNbNcNiKAhAyaZG28h@Base 6
+ _D3std6digest6digest19__T7asArrayVmi32ThZ7asArrayFNaNbNcNiKAhAyaZG32h@Base 6
+ _D3std6digest6digest19__T7asArrayVmi48ThZ7asArrayFNaNbNcNiKAhAyaZG48h@Base 6
+ _D3std6digest6digest19__T7asArrayVmi64ThZ7asArrayFNaNbNcNiKAhAyaZG64h@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6lengthMxFNaNbNdNeZm@Base 6
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+ _D3std6digest6digest6Digest6digestMFNbNeMAxAvXAh@Base 6
+ _D3std6digest6digest71__T11toHexStringVE3std6digest6digest5Orderi1VE3std5ascii10LetterCasei0Z11toHexStringFNaNbxAhZAya@Base 6
+ _D3std6digest6digest76__T11toHexStringVE3std6digest6digest5Orderi1Vmi16VE3std5ascii10LetterCasei0Z11toHexStringFNaNbNiNfxG16hZG32a@Base 6
+ _D3std6digest6ripemd10rotateLeftFNaNbNiNfkkZk@Base 6
+ _D3std6digest6ripemd12__ModuleInfoZ@Base 6
+ _D3std6digest6ripemd9RIPEMD1601FFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601GFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601HFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601IFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601JFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1602FFFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602GGFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602HHFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602IIFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602JJFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603FFFFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603GGGFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603HHHFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603IIIFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603JJJFNaNbNiNfKkkKkkkkkZv@Base 6
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+ _D3std6digest6ripemd9RIPEMD1605startMFNaNbNiNfZv@Base 6
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+ _D3std6format101__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpecmbAyaAyaE3std3net7isemail15EmailStatusCodeZ16__T7gencodeVmi4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZk@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda13FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda15FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
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+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange13opIndexAssignMFNaNbNiNfkmZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opIndexMNgFNaNbNcNiNfmZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opSliceMFNaNbNiNfmmZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6lengthMxFNaNbNdNiNfZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZm@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
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+ _D3std9container5dlist6DRange6__ctorMFNaNbNcNfPS3std9container5dlist8BaseNodeZS3std9container5dlist6DRange@Base 6
+ _D3std9container5dlist6DRange6__initZ@Base 6
+ _D3std9container5dlist6DRange7popBackMFNaNbNfZv@Base 6
+ _D3std9container5dlist6DRange8popFrontMFNaNbNfZv@Base 6
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+ _D3std9container5dlist8BaseNode7connectFNaNbNfPS3std9container5dlist8BaseNodePS3std9container5dlist8BaseNodeZv@Base 6
+ _D3std9container5slist12__ModuleInfoZ@Base 6
+ _D3std9container6rbtree12__ModuleInfoZ@Base 6
+ _D3std9exception104__T11doesPointToTPyS3std8datetime13PosixTimeZone6TTInfoTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxPyS3std8datetime13PosixTimeZone6TTInfoKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception104__T11doesPointToTS3std5array34__T8AppenderTAS3std4file8DirEntryZ8AppenderTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8AppenderKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception105__T11doesPointToTAS3std8datetime13PosixTimeZone10LeapSecondTAS3std8datetime13PosixTimeZone10LeapSecondTvZ11doesPointToFNaNbNiNeKxAS3std8datetime13PosixTimeZone10LeapSecondKxAS3std8datetime13PosixTimeZone10LeapSecondZb@Base 6
+ _D3std9exception111__T11doesPointToTPxS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxPS3std5array34__T8AppenderTAS3std4file8DirEntryZ8Appender4DataKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception111__T11doesPointToTS3std8datetime13PosixTimeZone14TempTransitionTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxS3std8datetime13PosixTimeZone14TempTransitionKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception113__T11doesPointToTAS3std8datetime13PosixTimeZone14TempTransitionTAS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxAS3std8datetime13PosixTimeZone14TempTransitionKxAS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception113__T11doesPointToTPxS3std8datetime13PosixTimeZone14TransitionTypeTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxPS3std8datetime13PosixTimeZone14TransitionTypeKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception115__T11doesPointToTmTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxmKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi674Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi676Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi681Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi749Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi891Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi949Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi994Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception117__T11doesPointToTAxkTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxAkKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi1010Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi1088Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi1124Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi1155Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi146Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi308Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi315Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi341Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi372Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi397Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vmi482Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception118__T18isUnionAliasedImplTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception121__T12errnoEnforceTbVAyaa43_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f70726f636573732e64Vmi2907Z12errnoEnforceFNfbLAyaZb@Base 6
+ _D3std9exception122__T11doesPointToTS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8AppenderTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8AppenderKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception129__T11doesPointToTPxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxPS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception12__ModuleInfoZ@Base 6
+ _D3std9exception143__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi385Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception143__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi455Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception144__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vmi1588Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception14ErrnoException5errnoMFNdZk@Base 6
+ _D3std9exception14ErrnoException6__ctorMFNeAyaAyamZC3std9exception14ErrnoException@Base 6
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+ _D3std9exception14ErrnoException6__vtblZ@Base 6
+ _D3std9exception14ErrnoException7__ClassZ@Base 6
+ _D3std9exception14RangePrimitive6__initZ@Base 6
+ _D3std9exception14__T7enforceTbZ7enforceFNaNfbLC6object9ThrowableZb@Base 6
+ (optional)_D3std9exception166__T12errnoEnforceTbVAyaa71_2f686f6d652f7061636b616765732f6763632f372f6763632d372d372d32303136313131362f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vmi557Z12errnoEnforceFNfbLAyaZb@Base 6
+ (optional)_D3std9exception166__T12errnoEnforceTiVAyaa71_2f686f6d652f7061636b616765732f6763632f372f6763632d372d372d32303136313131362f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vmi557Z12errnoEnforceFNfiLAyaZi@Base 6
+ (optional)_D3std9exception203__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa71_2f686f6d652f7061636b616765732f6763632f372f6763632d372d372d32303136313131362f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vmi557Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6
+ _D3std9exception207__T11doesPointToTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception20__T12assumeUniqueTaZ12assumeUniqueFNaNbNiAaZAya@Base 6
+ _D3std9exception20__T12assumeUniqueTaZ12assumeUniqueFNaNbNiKAaZAya@Base 6
+ _D3std9exception20__T12assumeUniqueTkZ12assumeUniqueFNaNbNiKAkZAyk@Base 6
+ _D3std9exception25__T11doesPointToTAkTAkTvZ11doesPointToFNaNbNiNeKxAkKxAkZb@Base 6
+ _D3std9exception25__T7bailOutHTC9ExceptionZ7bailOutFNaNfAyamxAaZv@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTbZ7enforceFNaNfbLAxaAyamZb@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTiZ7enforceFNaNfiLAxaAyamZi@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTkZ7enforceFNaNfkLAxaAyamZk@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTmZ7enforceFNaNfmLAxaAyamZm@Base 6
+ _D3std9exception289__T11doesPointToTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception28__T7enforceHTC9ExceptionTPvZ7enforceFNaNfPvLAxaAyamZPv@Base 6
+ _D3std9exception291__T11doesPointToTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception291__T11doesPointToTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception297__T11doesPointToTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception29__T11doesPointToTAAyaTAAyaTvZ11doesPointToFNaNbNiNeKxAAyaKxAAyaZb@Base 6
+ _D3std9exception37__T16collectExceptionHTC9ExceptionTmZ16collectExceptionFNaNbNfLmZC9Exception@Base 6
+ _D3std9exception39__T7bailOutHTC3std4json13JSONExceptionZ7bailOutFNaNfAyamxAaZv@Base 6
+ _D3std9exception40__T11doesPointToTAyaTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxAyaKxS3std5stdio4FileZb@Base 6
+ _D3std9exception40__T7bailOutHTC4core4time13TimeExceptionZ7bailOutFNaNfAyamxAaZv@Base 6
+ _D3std9exception41__T18isUnionAliasedImplTS3std5stdio4FileZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception41__T7enforceHTC3std4json13JSONExceptionTbZ7enforceFNaNfbLAxaAyamZb@Base 6
+ _D3std9exception41__T9enforceExHTC3std4json13JSONExceptionZ16__T9enforceExTbZ9enforceExFNaNfbLAyaAyamZb@Base 6
+ _D3std9exception42__T7enforceHTC4core4time13TimeExceptionTbZ7enforceFNaNfbLAxaAyamZb@Base 6
+ _D3std9exception43__T7bailOutHTC3std3net4curl13CurlExceptionZ7bailOutFNaNfAyamxAaZv@Base 6
+ _D3std9exception44__T18isUnionAliasedImplTS3std3net4curl4CurlZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception44__T18isUnionAliasedImplTS3std4file8DirEntryZ18isUnionAliasedImplFNaNbNiNfmZb@Base 6
+ _D3std9exception44__T7enforceTPS4core3sys5posix5netdb7hostentZ7enforceFNaNfPS4core3sys5posix5netdb7hostentLC6object9ThrowableZPS4core3sys5posix5netdb7hostent@Base 6
+ _D3std9exception45__T11doesPointToTbTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception45__T7enforceHTC3std3net4curl13CurlExceptionTbZ7enforceFNaNfbLAxaAyamZb@Base 6
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+ _D3std9exception46__T11doesPointToTbTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception46__T11doesPointToTtTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxtKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception46__T7enforceHTC3std3net4curl13CurlExceptionTPvZ7enforceFNaNfPvLAxaAyamZPv@Base 6
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+ _D3std9exception48__T11doesPointToTAyaTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTPxvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl4HTTP4ImplZb@Base 6
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+ _D3std3uni17CodepointInterval11__xopEqualsFKxS3std3uni17CodepointIntervalKxS3std3uni17CodepointIntervalZb@Base 6
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+ _D3std3uni17CodepointInterval6__ctorMFNaNbNcNiNfkkZS3std3uni17CodepointInterval@Base 6
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+ _D3std3uni17__T8spaceForVki8Z8spaceForFNaNbNiNfkZk@Base 6
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+ _D3std3uni22__T6asTrieTtVii12Vii9Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables25__T9TrieEntryTtVii12Vii9Z9TrieEntryZxS3std3uni112__T4TrieTtTwVki1114112TS3std3uni23__T9sliceBitsVki9Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki5Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki5Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki5Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki6Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki6Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki6Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki7Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki7Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki7Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki8Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki8Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki8Z9sliceBits6__initZ@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki9Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki9Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni22__T9sliceBitsVki0Vki9Z9sliceBits6__initZ@Base 6
+ _D3std3uni22toLowerSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toLowerSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toTitleSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toTitleSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toUpperSimpleIndexTrieFNaNbNdNiNfZ3resyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni22toUpperSimpleIndexTrieFNaNbNdNiNfZyS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni23__T13copyBackwardsTkTkZ13copyBackwardsFNaNbNiNfAkAkZv@Base 6
+ _D3std3uni23__T15packedArrayViewThZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni23__T15packedArrayViewTtZ15packedArrayViewFNaNbNiNePNgkkZNgS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl@Base 6
+ _D3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki5Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki10Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki6Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki7Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki8Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki13Z9sliceBits6__initZ@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni23__T9sliceBitsVki9Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni23genUnrolledSwitchSearchFkZAya@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMFNaNbNcNiNeS3std3uni186__T10MultiArrayTS3std3uni20__T9BitPackedTkVki7Z9BitPackedTS3std3uni21__T9BitPackedTkVki11Z9BitPackedTS3std3uni21__T9BitPackedTkVki15Z9BitPackedTS3std3uni20__T9BitPackedTbVki1Z9BitPackedZ10MultiArrayZS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__T6__ctorZ6__ctorMxFNaNbNcNiNeAxkAxkAxkZxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie11__xopEqualsFKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZb@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie12__T7opIndexZ7opIndexMxFNaNbNiNewZb@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie6__initZ@Base 6
+ _D3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie9__xtoHashFNbNeKxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4TrieZk@Base 6
+ _D3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVki10Vki14Z9sliceBits6__initZ@Base 6
+ _D3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVki13Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni24__T9sliceBitsVki14Vki21Z9sliceBits13__T6opCallTiZ6opCallFNaNbNiNfiZi@Base 6
+ _D3std3uni24__T9sliceBitsVki14Vki21Z9sliceBits13__T6opCallTwZ6opCallFNaNbNiNfwZk@Base 6
+ _D3std3uni24__T9sliceBitsVki14Vki21Z9sliceBits6__initZ@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZh@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl11simpleWriteMFNaNbNiNehkZv@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNehkZv@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni25__T13PackedPtrImplThVki8Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZh@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii4Vii9Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii4Vii9Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki9Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki9Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii5Vii8Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii5Vii8Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTbVii8Vii6Vii7Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTbVii8Vii6Vii7Z9TrieEntryZxS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki7Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki7Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieThVii8Vii7Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryThVii8Vii7Vii6Z9TrieEntryZxS3std3uni158__T4TrieThTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTtVii8Vii7Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii7Vii6Z9TrieEntryZxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni25__T6asTrieTtVii8Vii8Vii5Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables28__T9TrieEntryTtVii8Vii8Vii5Z9TrieEntryZxS3std3uni158__T4TrieTtTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki5Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki5Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZt@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNetkZv@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNetkZv@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni26__T13PackedPtrImplTtVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZt@Base 6
+ _D3std3uni26__T16propertyNameLessTaTaZ16propertyNameLessFNaNfAxaAxaZb@Base 6
+ _D3std3uni27__T13replicateBitsVki4Vki8Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T13replicateBitsVki1Vki32Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T13replicateBitsVki2Vki16Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T13replicateBitsVki32Vki1Z13replicateBitsFNaNbNiNfkZk@Base 6
+ _D3std3uni28__T20isPrettyPropertyNameTaZ20isPrettyPropertyNameFNaNfxAaZb@Base 6
+ _D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZ4predFNaNbNiNfwZb@Base 6
+ _D3std3uni29__T19comparePropertyNameTaTaZ19comparePropertyNameFNaNfAxaAxaZi@Base 6
+ _D3std3uni29__T6asTrieTbVii7Vii4Vii4Vii6Z6asTrieFNaNbNiNfxS3std8internal14unicode_tables32__T9TrieEntryTbVii7Vii4Vii4Vii6Z9TrieEntryZxS3std3uni244__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki14Vki21Z9sliceBitsTS3std3uni24__T9sliceBitsVki10Vki14Z9sliceBitsTS3std3uni23__T9sliceBitsVki6Vki10Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki6Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni31__T16codepointSetTrieVii13Vii8Z87__T16codepointSetTrieTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZ16codepointSetTrieFNaNfS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionListZS3std3uni152__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni23__T9sliceBitsVki8Vki21Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplKxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNehkZv@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNehkkZv@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl77__T8opEqualsTS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl78__T8opEqualsTxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZh@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni31__T19PackedArrayViewImplThVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplKxS3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni32__T19PackedArrayViewImplTtVki16Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNetkZv@Base 6
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+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki7Z9BitPackedkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki8Z9BitPacked@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki8Z9BitPackedkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni65__T13PackedPtrImplTS3std3uni20__T9BitPackedTkVki8Z9BitPackedVki8Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki8Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki11Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki11Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki11Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki12Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki12Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki12Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki13Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki13Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki13Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki14Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki14Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki14Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki15Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki15Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki15Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl11simpleIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl11simpleWriteMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNeS3std3uni21__T9BitPackedTkVki16Z9BitPackedkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl6__ctorMNgFNaNbNcNiNfPNgkZNgS3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl6__initZ@Base 6
+ _D3std3uni67__T13PackedPtrImplTS3std3uni21__T9BitPackedTkVki16Z9BitPackedVki16Z13PackedPtrImpl7opIndexMNgFNaNbNiNekZS3std3uni21__T9BitPackedTkVki16Z9BitPacked@Base 6
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+ _D3std3uni6isMarkFNaNbNiNfwZb@Base 6
+ _D3std3uni6mcTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
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+ _D3std3uni6read24FNaNbNiNfxPhkZk@Base 6
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+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl118__T8opEqualsTxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVki1Z9BitPackedkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNebkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTbVki1Z9BitPackedkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNebkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTbVki1Z9BitPacked@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl7opSliceMFNaNbNiNeZS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl7opSliceMNgFNaNbNiNekkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTbVki1Z9BitPackedVki1Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl118__T8opEqualsTxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZ8opEqualsMxFNaNbNiNeKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl11__xopEqualsFKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplKxS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImplZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl12__T7roundUpZ7roundUpMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki7Z9BitPackedkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opIndexAssignMFNaNbNiNekkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNeS3std3uni20__T9BitPackedTkVki7Z9BitPackedkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl13opSliceAssignMFNaNbNiNekkkZv@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl14__T9roundDownZ9roundDownMFNaNbNiNekZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl5zerosMFNaNbNiNekkZb@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6__ctorMNgFNaNbNcNiNePNgkkkZNgS3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6__initZ@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl6lengthMxFNaNbNdNiNeZk@Base 6
+ _D3std3uni71__T19PackedArrayViewImplTS3std3uni20__T9BitPackedTkVki7Z9BitPackedVki8Z19PackedArrayViewImpl7opIndexMNgFNaNbNiNekZS3std3uni20__T9BitPackedTkVki7Z9BitPacked@Base 6
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+ _D3std3uni9nfdQCTrieFNaNbNdNiNfZ3resyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9nfdQCTrieFNaNbNdNiNfZyS3std3uni198__T4TrieTS3std3uni20__T9BitPackedTbVki1Z9BitPackedTwVki1114112TS3std3uni24__T9sliceBitsVki13Vki21Z9sliceBitsTS3std3uni23__T9sliceBitsVki8Vki13Z9sliceBitsTS3std3uni22__T9sliceBitsVki0Vki8Z9sliceBitsZ4Trie@Base 6
+ _D3std3uni9recomposeFNaNbNekAwAhZk@Base 6
+ _D3std3uri10URI_EncodeFAywkZAya@Base 6
+ _D3std3uri12URIException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std3uri12URIException@Base 6
+ _D3std3uri12URIException6__initZ@Base 6
+ _D3std3uri12URIException6__vtblZ@Base 6
+ _D3std3uri12URIException7__ClassZ@Base 6
+ _D3std3uri12__ModuleInfoZ@Base 6
+ _D3std3uri18_sharedStaticCtor1FZ6helperFyAakZv@Base 6
+ _D3std3uri18_sharedStaticCtor1FZv@Base 6
+ _D3std3uri9ascii2hexFwZk@Base 6
+ _D3std3uri9hex2asciiyG16a@Base 6
+ _D3std3uri9uri_flagsG128h@Base 6
+ _D3std3utf100__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ11decodeFrontFNaNeKAyaJkZw@Base 6
+ _D3std3utf100__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ11decodeFrontFNaNfKAyaZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ10decodeImplFKAaKkZ17__T9exceptionTAaZ9exceptionFNaNfAaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ10decodeImplFNaKAaKkZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAuZ10decodeImplFNaKAuKkZw@Base 6
+ _D3std3utf102__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAwZ10decodeImplFNaKAwKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ10decodeImplFKAxaKkZ18__T9exceptionTAxaZ9exceptionFNaNfAxaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ10decodeImplFNaKAxaKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxuZ10decodeImplFNaKAxuKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxwZ10decodeImplFNaKAxwKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ10decodeImplFKAyaKkZ18__T9exceptionTAyaZ9exceptionFNaNfAyaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ10decodeImplFNaKAyaKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ10decodeImplFKxAaKkZ18__T9exceptionTAxaZ9exceptionFNaNfAxaAyaZC3std3utf12UTFException@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ10decodeImplFNaKxAaKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAuZ10decodeImplFNaKxAuKkZw@Base 6
+ _D3std3utf103__T10decodeImplVbi1VE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAwZ10decodeImplFNaKxAwKkZw@Base 6
+ _D3std3utf10strideImplFNaNeakZk@Base 6
+ _D3std3utf12UTFException11setSequenceMFNaNbNiNfAkXC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__ctorMFNaNbNfAyaAyakC6object9ThrowableZC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__ctorMFNaNfAyakAyakC6object9ThrowableZC3std3utf12UTFException@Base 6
+ _D3std3utf12UTFException6__initZ@Base 6
+ _D3std3utf12UTFException6__vtblZ@Base 6
+ _D3std3utf12UTFException7__ClassZ@Base 6
+ _D3std3utf12UTFException8toStringMFZAya@Base 6
+ _D3std3utf12__ModuleInfoZ@Base 6
+ _D3std3utf12isValidDcharFNaNbNiNfwZb@Base 6
+ _D3std3utf14__T6byCharTAaZ6byCharFNaNbNiNfAaZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf14__T6strideTAaZ6strideFNaNfAaZk@Base 6
+ _D3std3utf14__T6toUTFzTPaZ15__T6toUTFzTAyaZ6toUTFzFNaNbNfAyaZPa@Base 6
+ _D3std3utf15__T6byCharTAxaZ6byCharFNaNbNiNfAxaZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf15__T6byCharTAyaZ6byCharFNaNbNiNfAyaZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf15__T6strideTAxaZ6strideFNaNfAxakZk@Base 6
+ _D3std3utf15__T6strideTAxaZ6strideFNaNfKAxakZk@Base 6
+ _D3std3utf15__T6strideTAyaZ6strideFNaNfKAyakZk@Base 6
+ _D3std3utf16__T7byDcharTAyaZ7byDcharFNaNbNiNfAyaZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf17__T8validateTAxaZ8validateFNaNfxAaZv@Base 6
+ _D3std3utf17__T8validateTAxuZ8validateFNaNfxAuZv@Base 6
+ _D3std3utf17__T8validateTAxwZ8validateFNaNfxAwZv@Base 6
+ _D3std3utf18__T10codeLengthTaZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10codeLengthTuZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10codeLengthTwZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf18__T10toUCSindexTaZ10toUCSindexFNaNfAxakZk@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfkZNga@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfkkZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImplZk@Base 6
+ _D3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFNaNbNiNfAaZS3std3utf19__T10byCodeUnitTAaZ10byCodeUnitFAaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf19__T10codeLengthTyaZ10codeLengthFNaNbNiNfwZh@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfkZNgxa@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfkkZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImplZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFNaNbNiNfAxaZS3std3utf20__T10byCodeUnitTAxaZ10byCodeUnitFAxaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl11__xopEqualsFKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl4backMNgFNaNbNcNdNiNfZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl4saveMFNaNbNdNiNfZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl5frontMNgFNaNbNcNdNiNfZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6__initZ@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7opIndexMNgFNaNbNcNiNfkZya@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7opSliceMFNaNbNiNfkkZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl7popBackMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl9__xtoHashFNbNeKxS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZk@Base 6
+ _D3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFNaNbNiNfAyaZS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImpl@Base 6
+ _D3std3utf20__T10strideBackTAxaZ10strideBackFNaNfKAxakZk@Base 6
+ _D3std3utf20__T10strideBackTAyaZ10strideBackFNaNfKAyakZk@Base 6
+ _D3std3utf23__T10toUTFzImplTPaTAxaZ10toUTFzImplFNaNbNfAxaZPa@Base 6
+ _D3std3utf23__T10toUTFzImplTPaTAyaZ10toUTFzImplFNaNbNfAyaZPa@Base 6
+ _D3std3utf28__T20canSearchInCodeUnitsTaZ20canSearchInCodeUnitsFNaNbNiNfwZb@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNaNbNiNfS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl@Base 6
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+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImpl9__xtoHashFNbNeKxS3std3utf429__T6byCharTS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ6byCharFNcS3std6string198__T14rightJustifierTS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZ14rightJustifierFS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplkwZ6ResultZ10byCharImplZk@Base 6
+ _D3std3utf6encodeFNaNfKAawZv@Base 6
+ _D3std3utf6encodeFNaNfKAuwZv@Base 6
+ _D3std3utf6encodeFNaNfKAwwZv@Base 6
+ _D3std3utf6encodeFNaNfKG2uwZk@Base 6
+ _D3std3utf6encodeFNaNfKG4awZk@Base 6
+ _D3std3utf6toUTF8FNaNbNiNfNkJG4awZAa@Base 6
+ _D3std3utf6toUTF8FNaNfxAaZAya@Base 6
+ _D3std3utf6toUTF8FNaNfxAuZAya@Base 6
+ _D3std3utf6toUTF8FNaNfxAwZAya@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNaNbNiNfS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl11__xopEqualsFKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZb@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl4saveMFNaNbNdNiNfZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl5emptyMFNaNbNdNiNfZb@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl5frontMFNaNbNdNiNfZw@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__ctorMFNaNbNcNiNfKS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl6__initZ@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl8popFrontMFNaNbNiNfZv@Base 6
+ _D3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImpl9__xtoHashFNbNeKxS3std3utf77__T7byDcharTS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ7byDcharFNcS3std3utf20__T10byCodeUnitTAyaZ10byCodeUnitFAyaZ14ByCodeUnitImplZ11byDcharImplZk@Base 6
+ _D3std3utf7toUTF16FNaNbNiNfNkKG2uwZAu@Base 6
+ _D3std3utf7toUTF16FNaNfxAaZAyu@Base 6
+ _D3std3utf7toUTF16FNaNfxAuZAyu@Base 6
+ _D3std3utf7toUTF16FNaNfxAwZAyu@Base 6
+ _D3std3utf7toUTF32FNaNfxAaZAyw@Base 6
+ _D3std3utf7toUTF32FNaNfxAuZAyw@Base 6
+ _D3std3utf7toUTF32FNaNfxAwZAyw@Base 6
+ _D3std3utf93__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ6decodeFNaNeKAaKkZw@Base 6
+ _D3std3utf93__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAuZ6decodeFNaNeKAuKkZw@Base 6
+ _D3std3utf93__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAwZ6decodeFNaNeKAwKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxaZ6decodeFNaNeKAxaKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxuZ6decodeFNaNeKAxuKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAxwZ6decodeFNaNeKAxwKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAyaZ6decodeFNaNeKAyaKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAaZ6decodeFNaNeKxAaKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAuZ6decodeFNaNeKxAuKkZw@Base 6
+ _D3std3utf94__T6decodeVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TxAwZ6decodeFNaNeKxAwKkZw@Base 6
+ _D3std3utf99__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ11decodeFrontFNaNeKAaJkZw@Base 6
+ _D3std3utf99__T11decodeFrontVE3std8typecons55__T4FlagVAyaa19_7573655265706c6163656d656e744463686172Z4Flagi0TAaZ11decodeFrontFNaNfKAaZw@Base 6
+ _D3std3xml10DigitTableyAi@Base 6
+ _D3std3xml10checkCharsFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml10checkCharsFKAyaZv@Base 6
+ _D3std3xml10checkSpaceFKAyaZ8__mixin24failMFC3std3xml14CheckExceptionZv@Base 6
+ _D3std3xml10checkSpaceFKAyaZv@Base 6
+ _D3std3xml10isBaseCharFwZb@Base 6
+ _D3std3xml10isExtenderFwZb@Base 6
+ _D3std3xml111__T4starS99_D3std3xml76__T3seqS29_D3std3xml10checkSpaceFKAyaZvS33_D3std3xml14checkAttributeFKAyaZvZ3seqFKAyaZvZ4starFKAyaZv@Base 6
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+ _D3std4conv40__T7emplaceTS3std4file15DirIteratorImplZ7emplaceFNaNbNiNfPS3std4file15DirIteratorImplZPS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv41__T11emplaceImplTS3std3net4curl3FTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl3FTP4ImplZS3std3net4curl3FTP4Impl@Base 6
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+ _D3std4conv41__T5toStrTyAaTE3std6socket12SocketOptionZ5toStrFNaNfE3std6socket12SocketOptionZyAa@Base 6
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+ _D3std4conv42__T11emplaceImplTS3std3net4curl4SMTP4ImplZ17__T11emplaceImplZ11emplaceImplFNaNbNcNiNfKS3std3net4curl4SMTP4ImplZS3std3net4curl4SMTP4Impl@Base 6
+ _D3std4conv42__T6toImplTAyaTE3std5regex8internal2ir2IRZ6toImplFNaNfE3std5regex8internal2ir2IRZAya@Base 6
+ _D3std4conv42__T6toImplTAyaTE3std6socket12SocketOptionZ6toImplFNaNfE3std6socket12SocketOptionZAya@Base 6
+ _D3std4conv43__T11emplaceImplTS3std6socket11AddressInfoZ43__T11emplaceImplTS3std6socket11AddressInfoZ11emplaceImplFNaNbNcNiNfKS3std6socket11AddressInfoKS3std6socket11AddressInfoZS3std6socket11AddressInfo@Base 6
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+ _D3std4conv45__T11emplaceImplTS3std4file15DirIteratorImplZ43__T11emplaceImplTAyaTE3std4file8SpanModeTbZ11emplaceImplFNcKS3std4file15DirIteratorImplKAyaKE3std4file8SpanModeKbZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv46__T11emplaceImplTS3std3uni17CodepointIntervalZ46__T11emplaceImplTS3std3uni17CodepointIntervalZ11emplaceImplFNaNbNcNiNfKS3std3uni17CodepointIntervalKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std4conv48__T18emplaceInitializerTS3std3net4curl3FTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl3FTP4ImplZ4inityS3std3net4curl3FTP4Impl@Base 6
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+ _D3std4conv48__T6toImplTiTE3std3net7isemail15EmailStatusCodeZ6toImplFNaNbNiNfE3std3net7isemail15EmailStatusCodeZi@Base 6
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+ _D3std4conv49__T18emplaceInitializerTS3std3net4curl4SMTP4ImplZ18emplaceInitializerFNaNbNcNeKS3std3net4curl4SMTP4ImplZ4inityS3std3net4curl4SMTP4Impl@Base 6
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+ _D3std4conv49__T5toStrTAyaTC3std11concurrency14LinkTerminatedZ5toStrFC3std11concurrency14LinkTerminatedZAya@Base 6
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+ _D3std4conv50__T5toStrTAyaTC3std11concurrency15OwnerTerminatedZ5toStrFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv50__T6toImplTAyaTC3std11concurrency14LinkTerminatedZ6toImplFC3std11concurrency14LinkTerminatedZAya@Base 6
+ _D3std4conv51__T6toImplTAyaTC3std11concurrency15OwnerTerminatedZ6toImplFC3std11concurrency15OwnerTerminatedZAya@Base 6
+ _D3std4conv52__T18emplaceInitializerTS3std4file15DirIteratorImplZ18emplaceInitializerFNaNbNcNeKS3std4file15DirIteratorImplZ4inityS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv52__T18emplaceInitializerTS3std4file15DirIteratorImplZ18emplaceInitializerFNaNbNcNiNeKS3std4file15DirIteratorImplZS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv53__T11emplaceImplTS3std5regex8internal2ir10NamedGroupZ53__T11emplaceImplTS3std5regex8internal2ir10NamedGroupZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir10NamedGroupKS3std5regex8internal2ir10NamedGroupZS3std5regex8internal2ir10NamedGroup@Base 6
+ _D3std4conv55__T11emplaceImplTS3std4file15DirIteratorImpl9DirHandleZ55__T11emplaceImplTS3std4file15DirIteratorImpl9DirHandleZ11emplaceImplFNaNbNcNiNfKS3std4file15DirIteratorImpl9DirHandleKS3std4file15DirIteratorImpl9DirHandleZS3std4file15DirIteratorImpl9DirHandle@Base 6
+ _D3std4conv56__T10emplaceRefTS3std4file8DirEntryTS3std4file8DirEntryZ10emplaceRefFNaNbNcNiNfKS3std4file8DirEntryKS3std4file8DirEntryZS3std4file8DirEntry@Base 6
+ _D3std4conv61__T11emplaceImplTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ61__T11emplaceImplTS3std5regex8internal2ir12__T5RegexTaZ5RegexZ11emplaceImplFNaNbNcNiNfKS3std5regex8internal2ir12__T5RegexTaZ5RegexKS3std5regex8internal2ir12__T5RegexTaZ5RegexZS3std5regex8internal2ir12__T5RegexTaZ5Regex@Base 6
+ _D3std4conv65__T6toImplTiTE3std3net4curl20AsyncChunkInputRange8__mixin55StateZ6toImplFNaNbNiNfE3std3net4curl20AsyncChunkInputRange8__mixin55StateZi@Base 6
+ _D3std4conv66__T7emplaceTS3std4file15DirIteratorImplTAyaTE3std4file8SpanModeTbZ7emplaceFPS3std4file15DirIteratorImplKAyaKE3std4file8SpanModeKbZPS3std4file15DirIteratorImpl@Base 6
+ _D3std4conv68__T10emplaceRefTS3std6socket11AddressInfoTS3std6socket11AddressInfoZ10emplaceRefFNaNbNcNiNfKS3std6socket11AddressInfoKS3std6socket11AddressInfoZS3std6socket11AddressInfo@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni1Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni2Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni3Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni4Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni5Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni6Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni7Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni8Z7enumRepyAa@Base 6
+ _D3std4conv72__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni9Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni10Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni13Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni16Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni17Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni18Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni19Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni20Z7enumRepyAa@Base 6
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+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni26Z7enumRepyAa@Base 6
+ _D3std4conv73__T7enumRepTyAaTE3std6socket12SocketOptionVE3std6socket12SocketOptioni30Z7enumRepyAa@Base 6
+ _D3std4conv74__T10emplaceRefTS3std3uni17CodepointIntervalTS3std3uni17CodepointIntervalZ10emplaceRefFNaNbNcNiNfKS3std3uni17CodepointIntervalKS3std3uni17CodepointIntervalZS3std3uni17CodepointInterval@Base 6
+ _D3std4conv74__T7enumRepTyAaTE3std5regex8internal2ir2IRVE3std5regex8internal2ir2IRi128Z7enumRepyAa@Base 6
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+ _D3std4conv9__T2toTiZ28__T2toTE3std8datetime5MonthZ2toFNaNbNiNfE3std8datetime5MonthZi@Base 6
+ _D3std4conv9__T2toTiZ29__T2toTxE3std8datetime5MonthZ2toFNaNbNiNfxE3std8datetime5MonthZi@Base 6
+ _D3std4conv9__T2toTiZ42__T2toTE3std3net7isemail15EmailStatusCodeZ2toFNaNbNiNfE3std3net7isemail15EmailStatusCodeZi@Base 6
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+ _D3std5ascii13fullHexDigitsyAa@Base 6
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+ _D3std5ascii14__T7toLowerTwZ7toLowerFNaNbNiNfwZw@Base 6
+ _D3std5ascii14lowerHexDigitsyAa@Base 6
+ _D3std5ascii15__T7toLowerTxaZ7toLowerFNaNbNiNfxaZa@Base 6
+ _D3std5ascii15__T7toLowerTxwZ7toLowerFNaNbNiNfxwZw@Base 6
+ _D3std5ascii15__T7toLowerTyaZ7toLowerFNaNbNiNfyaZa@Base 6
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+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA19__T11T_SHA2_0_15TkZ11T_SHA2_0_15FNaNbNiiPxG64hKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA20__T12T_SHA2_16_79TkZ12T_SHA2_16_79FNaNbNiNfiKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA21__T13transformSHA2TkZ13transformSHA2FNaNbNiPG8kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6__initZ@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA6finishMFNaNbNiNeZG28h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii224Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA19__T11T_SHA2_0_15TkZ11T_SHA2_0_15FNaNbNiiPxG64hKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA20__T12T_SHA2_16_79TkZ12T_SHA2_16_79FNaNbNiNfiKG16kkkkKkkkkKkkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA21__T13transformSHA2TkZ13transformSHA2FNaNbNiPG8kPxG64hZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6__initZ@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA6finishMFNaNbNiNeZG32h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha20__T3SHAVii512Vii256Z3SHA9constantsyG64k@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA6finishMFNaNbNiNeZG28h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii224Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA6finishMFNaNbNiNeZG32h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii256Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA6finishMFNaNbNiNeZG48h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii384Z3SHA9constantsyG80m@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA10__T3MajTkZ3MajFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA10__T3MajTmZ3MajFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA12transformX86FNaNbNiPG5kPxG64hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA19__T11T_SHA2_0_15TmZ11T_SHA2_0_15FNaNbNiiPxG128hKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA20__T12T_SHA2_16_79TmZ12T_SHA2_16_79FNaNbNiNfiKG16mmmmKmmmmKmmZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA21__T13transformSHA2TmZ13transformSHA2FNaNbNiPG8mPxG128hZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA3putMFNaNbNiNeMAxhXv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA5startMFNaNbNiNfZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6ParityFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6T_0_15FNaNbNiiPxG64hKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6__initZ@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA6finishMFNaNbNiNeZG64h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_16_19FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_20_39FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_40_59FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7T_60_79FNaNbNiNfiKG16kkKkkkkKkZv@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA7paddingyG128h@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA8SmSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma0FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma0FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma1FNaNbNiNfkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9BigSigma1FNaNbNiNfmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9__T2ChTkZ2ChFNaNbNiNfkkkZk@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9__T2ChTmZ2ChFNaNbNiNfmmmZm@Base 6
+ _D3std6digest3sha21__T3SHAVii1024Vii512Z3SHA9constantsyG80m@Base 6
+ _D3std6digest6digest12__ModuleInfoZ@Base 6
+ _D3std6digest6digest18__T7asArrayVki4ThZ7asArrayFNaNbNcNiKAhAyaZG4h@Base 6
+ _D3std6digest6digest19__T7asArrayVki16ThZ7asArrayFNaNbNcNiKAhAyaZG16h@Base 6
+ _D3std6digest6digest19__T7asArrayVki20ThZ7asArrayFNaNbNcNiKAhAyaZG20h@Base 6
+ _D3std6digest6digest19__T7asArrayVki28ThZ7asArrayFNaNbNcNiKAhAyaZG28h@Base 6
+ _D3std6digest6digest19__T7asArrayVki32ThZ7asArrayFNaNbNcNiKAhAyaZG32h@Base 6
+ _D3std6digest6digest19__T7asArrayVki48ThZ7asArrayFNaNbNcNiKAhAyaZG48h@Base 6
+ _D3std6digest6digest19__T7asArrayVki64ThZ7asArrayFNaNbNcNiKAhAyaZG64h@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest3putMFNbNeMAxhXv@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest5resetMFNbNeZv@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__ctorMFNaNbNiNfZC3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__initZ@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6__vtblZ@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbMAhZAh@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6finishMFNbNeZAh@Base 6
+ _D3std6digest6digest39__T13WrapperDigestTS3std6digest2md3MD5Z13WrapperDigest6lengthMxFNaNbNdNeZk@Base 6
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+ _D3std6digest6digest6Digest6digestMFNbNeMAxAvXAh@Base 6
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+ _D3std6digest6ripemd9RIPEMD1601GFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601HFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601IFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1601JFNaNbNiNfkkkZk@Base 6
+ _D3std6digest6ripemd9RIPEMD1602FFFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602GGFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602HHFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602IIFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1602JJFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603FFFFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603GGGFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603HHHFNaNbNiNfKkkKkkkkkZv@Base 6
+ _D3std6digest6ripemd9RIPEMD1603IIIFNaNbNiNfKkkKkkkkkZv@Base 6
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+ _D3std6format101__T9formatNthTS3std5array17__T8AppenderTAyaZ8AppenderTaTbTAyaTAyaTE3std3net7isemail15EmailStatusCodeZ9formatNthFS3std5array17__T8AppenderTAyaZ8AppenderKS3std6format18__T10FormatSpecTaZ10FormatSpeckbAyaAyaE3std3net7isemail15EmailStatusCodeZ16__T7gencodeVki4Z7gencodeFNaNbNfZAya@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFNaNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZk@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda11FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
+ _D3std6format102__T14formattedWriteTS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkTaTykTykTkTkTkZ14formattedWriteFS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkxAaykykkkkZ10__lambda13FNaNbNiNeZPFNaNbNfS3std6format26__T7sformatTaTykTykTkTkTkZ7sformatFAaxAaykykkkkZ4SinkPxvKS3std6format18__T10FormatSpecTaZ10FormatSpecZv@Base 6
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+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opIndexMNgFNaNbNcNiNfkZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opSliceMFNaNbNiNfkkZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMFNaNbNdNiNfkZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMNgFNaNbNcNdNiNfZNgk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi0VE3std8internal4test10dummyrange6Lengthi1VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei0Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei1Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4backMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange7popBackMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange8popFrontMFNaNbNiNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRange9__xtoHashFNbNeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei2Z10DummyRangeZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange11__xopEqualsFKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeKxS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRangeZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4backMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange4saveMFNaNbNdNiNfZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5emptyMxFNaNbNdNiNfZb@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange5frontMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6__initZ@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6lengthMxFNaNbNdNiNfZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange6reinitMFNaNbNfZv@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opIndexMxFNaNbNiNfkZk@Base 6
+ _D3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange7opSliceMFNaNbNiNfkkZS3std8internal4test10dummyrange144__T10DummyRangeVE3std8internal4test10dummyrange8ReturnByi1VE3std8internal4test10dummyrange6Lengthi0VE3std8internal4test10dummyrange9RangeTypei3Z10DummyRange@Base 6
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+ _D3std9exception113__T11doesPointToTPxS3std8datetime13PosixTimeZone14TransitionTypeTS3std8datetime13PosixTimeZone14TempTransitionTvZ11doesPointToFNaNbNiNeKxPS3std8datetime13PosixTimeZone14TransitionTypeKxS3std8datetime13PosixTimeZone14TempTransitionZb@Base 6
+ _D3std9exception115__T11doesPointToTkTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxkKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki674Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki676Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki681Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki749Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki891Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki949Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception116__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki994Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception117__T11doesPointToTAxkTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxAkKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1010Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1088Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1124Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception117__T12errnoEnforceTbVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1155Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki146Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki308Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki315Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki341Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki372Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki397Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T12errnoEnforceTbVAyaa42_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f6d6d66696c652e64Vki482Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception118__T18isUnionAliasedImplTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception121__T12errnoEnforceTbVAyaa43_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f70726f636573732e64Vki2907Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ _D3std9exception122__T11doesPointToTS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8AppenderTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8AppenderKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception129__T11doesPointToTPxS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxPS3std5array52__T8AppenderTAS3std4file15DirIteratorImpl9DirHandleZ8Appender4DataKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception12__ModuleInfoZ@Base 6
+ _D3std9exception143__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki385Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6.2.1-1ubuntu2
+ _D3std9exception143__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki455Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6.2.1-1ubuntu2
+ _D3std9exception144__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa41_2e2e2f2e2e2f2e2e2f2e2e2f7372632f6c696270686f626f732f7372632f7374642f737464696f2e64Vki1588Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6.2.1-1ubuntu2
+ _D3std9exception14ErrnoException5errnoMFNdZk@Base 6
+ _D3std9exception14ErrnoException6__ctorMFNeAyaAyakZC3std9exception14ErrnoException@Base 6
+ _D3std9exception14ErrnoException6__initZ@Base 6
+ _D3std9exception14ErrnoException6__vtblZ@Base 6
+ _D3std9exception14ErrnoException7__ClassZ@Base 6
+ _D3std9exception14RangePrimitive6__initZ@Base 6
+ _D3std9exception14__T7enforceTbZ7enforceFNaNfbLC6object9ThrowableZb@Base 6
+ (optional)_D3std9exception158__T12errnoEnforceTbVAyaa62_2f686f6d652f7562756e74752f6763632f6763632d362d362e322e312f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vki557Z12errnoEnforceFNfbLAyaZb@Base 6.2.1-1ubuntu2
+ (optional)_D3std9exception158__T12errnoEnforceTiVAyaa62_2f686f6d652f7562756e74752f6763632f6763632d362d362e322e312f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vki557Z12errnoEnforceFNfiLAyaZi@Base 6.2.1-1ubuntu2
+ (optional)_D3std9exception185__T12errnoEnforceTPOS4core4stdc5stdio8_IO_FILEVAyaa62_2f686f6d652f7562756e74752f6763632f6763632d362d362e322e312f7372632f6c696270686f626f732f7372632f7374642f657863657074696f6e2e64Vki557Z12errnoEnforceFNfPOS4core4stdc5stdio8_IO_FILELAyaZPOS4core4stdc5stdio8_IO_FILE@Base 6.2.1-1ubuntu2
+ _D3std9exception207__T11doesPointToTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsTvZ11doesPointToFNaNbNiNeKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsKxS3std3uni38__T13InversionListTS3std3uni8GcPolicyZ13InversionList17__T9IntervalsTAkZ9IntervalsZb@Base 6
+ _D3std9exception20__T12assumeUniqueTaZ12assumeUniqueFNaNbNiAaZAya@Base 6
+ _D3std9exception20__T12assumeUniqueTaZ12assumeUniqueFNaNbNiKAaZAya@Base 6
+ _D3std9exception20__T12assumeUniqueTkZ12assumeUniqueFNaNbNiKAkZAyk@Base 6
+ _D3std9exception25__T11doesPointToTAkTAkTvZ11doesPointToFNaNbNiNeKxAkKxAkZb@Base 6
+ _D3std9exception25__T7bailOutHTC9ExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTiZ7enforceFNaNfiLAxaAyakZi@Base 6
+ _D3std9exception27__T7enforceHTC9ExceptionTkZ7enforceFNaNfkLAxaAyakZk@Base 6
+ _D3std9exception289__T11doesPointToTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons83__T10RefCountedTS3std3net4curl3FTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception28__T7enforceHTC9ExceptionTPvZ7enforceFNaNfPvLAxaAyakZPv@Base 6
+ _D3std9exception291__T11doesPointToTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons84__T10RefCountedTS3std3net4curl4HTTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception291__T11doesPointToTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons84__T10RefCountedTS3std3net4curl4SMTP4ImplVE3std8typecons24RefCountedAutoInitializei1Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception297__T11doesPointToTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplTPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplTvZ11doesPointToFNaNbNiNeKxPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplKxPS3std8typecons87__T10RefCountedTS3std4file15DirIteratorImplVE3std8typecons24RefCountedAutoInitializei0Z10RefCounted15RefCountedStore4ImplZb@Base 6
+ _D3std9exception29__T11doesPointToTAAyaTAAyaTvZ11doesPointToFNaNbNiNeKxAAyaKxAAyaZb@Base 6
+ _D3std9exception37__T16collectExceptionHTC9ExceptionTmZ16collectExceptionFNaNbNfLmZC9Exception@Base 6
+ _D3std9exception39__T7bailOutHTC3std4json13JSONExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception40__T11doesPointToTAyaTS3std5stdio4FileTvZ11doesPointToFNaNbNiNeKxAyaKxS3std5stdio4FileZb@Base 6
+ _D3std9exception40__T7bailOutHTC4core4time13TimeExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception41__T18isUnionAliasedImplTS3std5stdio4FileZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception41__T7enforceHTC3std4json13JSONExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception41__T9enforceExHTC3std4json13JSONExceptionZ16__T9enforceExTbZ9enforceExFNaNfbLAyaAyakZb@Base 6
+ _D3std9exception42__T7enforceHTC4core4time13TimeExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception43__T7bailOutHTC3std3net4curl13CurlExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception44__T18isUnionAliasedImplTS3std3net4curl4CurlZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception44__T18isUnionAliasedImplTS3std4file8DirEntryZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception44__T7enforceTPS4core3sys5posix5netdb7hostentZ7enforceFNaNfPS4core3sys5posix5netdb7hostentLC6object9ThrowableZPS4core3sys5posix5netdb7hostent@Base 6
+ _D3std9exception45__T11doesPointToTbTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception45__T7enforceHTC3std3net4curl13CurlExceptionTbZ7enforceFNaNfbLAxaAyakZb@Base 6
+ _D3std9exception45__T9enforceExHTC3std6format15FormatExceptionZ16__T9enforceExTbZ9enforceExFNaNfbLAyaAyakZb@Base 6
+ _D3std9exception45__T9enforceExHTC3std6format15FormatExceptionZ16__T9enforceExTkZ9enforceExFNaNfkLAyaAyakZk@Base 6
+ _D3std9exception46__T11doesPointToTbTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception46__T11doesPointToTbTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxbKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception46__T11doesPointToTtTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxtKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception46__T7enforceHTC3std3net4curl13CurlExceptionTPvZ7enforceFNaNfPvLAxaAyakZPv@Base 6
+ _D3std9exception47__T11doesPointToTAyaTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception47__T11doesPointToTPxvTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTAyaTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTPxvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception48__T11doesPointToTPxvTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxPvKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception48__T18isUnionAliasedImplTS3std3net4curl3FTP4ImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception49__T11doesPointToTbTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxbKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToThTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxhKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTiTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxiKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTkTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxkKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTlTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxlKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTmTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxmKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T11doesPointToTtTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxtKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception49__T18isUnionAliasedImplTS3std3net4curl4HTTP4ImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception49__T18isUnionAliasedImplTS3std3net4curl4SMTP4ImplZ18isUnionAliasedImplFNaNbNiNfkZb@Base 6
+ _D3std9exception50__T11doesPointToTDFAhZkTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZkKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception50__T11doesPointToTDFAvZkTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZkKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception50__T7bailOutHTC3std3net4curl20CurlTimeoutExceptionZ7bailOutFNaNfAyakxAaZv@Base 6
+ _D3std9exception51__T11doesPointToTAyaTS3std4file15DirIteratorImplTvZ11doesPointToFNaNbNiNeKxAyaKxS3std4file15DirIteratorImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAhZkTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZkKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAhZkTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAhZkKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAvZkTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZkKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFAvZkTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFAvZkKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception51__T11doesPointToTDFxAaZvTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFkkkkZiTS3std3net4curl3FTP4ImplTvZ11doesPointToFNaNbNiNeKxDFkkkkZiKxS3std3net4curl3FTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFxAaZvTS3std3net4curl4HTTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl4HTTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTDFxAaZvTS3std3net4curl4SMTP4ImplTvZ11doesPointToFNaNbNiNeKxDFxAaZvKxS3std3net4curl4SMTP4ImplZb@Base 6
+ _D3std9exception52__T11doesPointToTwTS3std5stdio17LockingTextReaderTvZ11doesPointToFNaNbNiNeKxwKxS3std5stdio17LockingTextReaderZb@Base 6
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--- gcc-6-6.4.0.orig/debian/libgphobos.symbols.rt64
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+ __asan_cplus_demangle_v3_callback@Base 4.9
+ __asan_internal_memcmp@Base 4.9
+ __asan_internal_memcpy@Base 4.9
+ __asan_internal_memset@Base 4.9
+ __asan_internal_strcmp@Base 4.9
+ __asan_internal_strlen@Base 4.9
+ __asan_internal_strncmp@Base 4.9
+ __asan_internal_strnlen@Base 4.9
+ __asan_is_gnu_v3_mangled_ctor@Base 4.9
+ __asan_is_gnu_v3_mangled_dtor@Base 4.9
+ __asan_java_demangle_v3@Base 4.9
+ __asan_java_demangle_v3_callback@Base 4.9
+ __interceptor___libc_memalign@Base 4.9
+ __interceptor_aligned_alloc@Base 5
+ __interceptor_calloc@Base 4.9
+ __interceptor_cfree@Base 4.9
+ __interceptor_free@Base 4.9
+ __interceptor_mallinfo@Base 4.9
+ __interceptor_malloc@Base 4.9
+ __interceptor_malloc_usable_size@Base 4.9
+ __interceptor_mallopt@Base 4.9
+ __interceptor_memalign@Base 4.9
+ __interceptor_posix_memalign@Base 4.9
+ __interceptor_pthread_create@Base 4.9
+ __interceptor_pthread_join@Base 4.9
+ __interceptor_pvalloc@Base 4.9
+ __interceptor_realloc@Base 4.9
+ __interceptor_valloc@Base 4.9
+ __libc_memalign@Base 4.9
+ __lsan_disable@Base 4.9
+ __lsan_do_leak_check@Base 4.9
+ __lsan_do_recoverable_leak_check@Base 6
+ __lsan_enable@Base 4.9
+ __lsan_ignore_object@Base 4.9
+ __lsan_register_root_region@Base 5
+ __lsan_unregister_root_region@Base 5
+ __sanitizer_cov@Base 4.9
+ __sanitizer_cov_dump@Base 4.9
+ __sanitizer_cov_indir_call16@Base 5
+ __sanitizer_cov_init@Base 5
+ __sanitizer_cov_module_init@Base 5
+ __sanitizer_cov_trace_basic_block@Base 6
+ __sanitizer_cov_trace_cmp@Base 6
+ __sanitizer_cov_trace_func_enter@Base 6
+ __sanitizer_cov_trace_switch@Base 6
+ __sanitizer_cov_with_check@Base 6
+ __sanitizer_get_allocated_size@Base 5
+ __sanitizer_get_coverage_guards@Base 6
+ __sanitizer_get_current_allocated_bytes@Base 5
+ __sanitizer_get_estimated_allocated_size@Base 5
+ __sanitizer_get_free_bytes@Base 5
+ __sanitizer_get_heap_size@Base 5
+ __sanitizer_get_number_of_counters@Base 6
+ __sanitizer_get_ownership@Base 5
+ __sanitizer_get_total_unique_caller_callee_pairs@Base 6
+ __sanitizer_get_total_unique_coverage@Base 6
+ __sanitizer_get_unmapped_bytes@Base 5
+ __sanitizer_maybe_open_cov_file@Base 5
+ __sanitizer_print_stack_trace@Base 5
+ __sanitizer_report_error_summary@Base 4.9
+ __sanitizer_reset_coverage@Base 6
+ __sanitizer_sandbox_on_notify@Base 4.9
+ __sanitizer_set_death_callback@Base 6
+ __sanitizer_set_report_path@Base 4.9
+ __sanitizer_update_counter_bitset_and_clear_counters@Base 6
+ aligned_alloc@Base 5
+ calloc@Base 4.9
+ cfree@Base 4.9
+ free@Base 4.9
+ mallinfo@Base 4.9
+ malloc@Base 4.9
+ malloc_usable_size@Base 4.9
+ mallopt@Base 4.9
+ memalign@Base 4.9
+ posix_memalign@Base 4.9
+ pthread_create@Base 4.9
+ pthread_join@Base 4.9
+ pvalloc@Base 4.9
+ realloc@Base 4.9
+ valloc@Base 4.9
--- gcc-6-6.4.0.orig/debian/libmpx.symbols
+++ gcc-6-6.4.0/debian/libmpx.symbols
@@ -0,0 +1,5 @@
+libmpx.so.2 #PACKAGE# #MINVER#
+ (symver)LIBMPX_1.0 5
+ (symver)LIBMPX_2.0 6
+libmpxwrappers.so.2 #PACKAGE# #MINVER#
+ (symver)LIBMPXWRAPPERS_1.0 5
--- gcc-6-6.4.0.orig/debian/libobjc.symbols
+++ gcc-6-6.4.0/debian/libobjc.symbols
@@ -0,0 +1,9 @@
+libobjc.so.4 #PACKAGE# #MINVER#
+#include "libobjc.symbols.common"
+ __gnu_objc_personality_v0@Base 4.2.1
+ (arch=armel armhf)__objc_exception_class@Base 4.3.0
+libobjc_gc.so.4 #PACKAGE# #MINVER#
+#include "libobjc.symbols.common"
+#include "libobjc.symbols.gc"
+ __gnu_objc_personality_v0@Base 4.2.1
+ (arch=armel armhf)__objc_exception_class@Base 4.3.0
--- gcc-6-6.4.0.orig/debian/libobjc.symbols.common
+++ gcc-6-6.4.0/debian/libobjc.symbols.common
@@ -0,0 +1,205 @@
+ __objc_accessors_init@Base 4.6
+ __objc_add_class_to_hash@Base 4.2.1
+ __objc_class_links_resolved@Base 4.2.1
+ __objc_class_name_NXConstantString@Base 4.2.1
+ __objc_class_name_Object@Base 4.2.1
+ __objc_class_name_Protocol@Base 4.2.1
+ __objc_dangling_categories@Base 4.2.1
+ __objc_exec_class@Base 4.2.1
+ __objc_force_linking@Base 4.2.1
+ __objc_generate_gc_type_description@Base 4.2.1
+ __objc_get_forward_imp@Base 4.2.1
+ __objc_init_class@Base 4.6
+ __objc_init_class_tables@Base 4.2.1
+ __objc_init_dispatch_tables@Base 4.2.1
+ __objc_init_selector_tables@Base 4.2.1
+ __objc_init_thread_system@Base 4.2.1
+ __objc_install_premature_dtable@Base 4.2.1
+ __objc_is_multi_threaded@Base 4.2.1
+ __objc_linking@Base 4.2.1
+ __objc_msg_forward@Base 4.2.1
+ __objc_msg_forward2@Base 4.3
+ __objc_print_dtable_stats@Base 4.2.1
+ __objc_protocols_add_protocol@Base 4.6
+ __objc_protocols_init@Base 4.6
+ __objc_register_instance_methods_to_class@Base 4.2.1
+ __objc_register_selectors_from_class@Base 4.2.1
+ __objc_register_selectors_from_description_list@Base 4.6
+ __objc_register_selectors_from_list@Base 4.2.1
+ __objc_register_selectors_from_module@Base 4.6
+ __objc_resolve_class_links@Base 4.2.1
+ __objc_responds_to@Base 4.2.1
+ __objc_runtime_mutex@Base 4.2.1
+ __objc_runtime_threads_alive@Base 4.2.1
+ __objc_selector_max_index@Base 4.2.1
+ __objc_sparse2_id@Base 4.2.1
+ __objc_sync_init@Base 4.6
+ __objc_thread_exit_status@Base 4.2.1
+ __objc_uninstalled_dtable@Base 4.2.1
+ __objc_update_classes_with_methods@Base 4.6
+ __objc_update_dispatch_table_for_class@Base 4.2.1
+ _objc_abort@Base 4.6
+ _objc_became_multi_threaded@Base 4.2.1
+ _objc_load_callback@Base 4.2.1
+ _objc_lookup_class@Base 4.6
+ class_addIvar@Base 4.6
+ class_addMethod@Base 4.6
+ class_addProtocol@Base 4.6
+ class_add_method_list@Base 4.2.1
+ class_conformsToProtocol@Base 4.6
+ class_copyIvarList@Base 4.6
+ class_copyMethodList@Base 4.6
+ class_copyPropertyList@Base 4.6
+ class_copyProtocolList@Base 4.6
+ class_createInstance@Base 4.6
+ class_getClassMethod@Base 4.6
+ class_getClassVariable@Base 4.6
+ class_getInstanceMethod@Base 4.6
+ class_getInstanceSize@Base 4.6
+ class_getInstanceVariable@Base 4.6
+ class_getIvarLayout@Base 4.6
+ class_getMethodImplementation@Base 4.6
+ class_getName@Base 4.6
+ class_getProperty@Base 4.6
+ class_getSuperclass@Base 4.6
+ class_getVersion@Base 4.6
+ class_getWeakIvarLayout@Base 4.6
+ class_isMetaClass@Base 4.6
+ class_ivar_set_gcinvisible@Base 4.2.1
+ class_replaceMethod@Base 4.6
+ class_respondsToSelector@Base 4.6
+ class_setIvarLayout@Base 4.6
+ class_setVersion@Base 4.6
+ class_setWeakIvarLayout@Base 4.6
+ get_imp@Base 4.2.1
+ idxsize@Base 4.2.1
+ ivar_getName@Base 4.6
+ ivar_getOffset@Base 4.6
+ ivar_getTypeEncoding@Base 4.6
+ method_copyArgumentType@Base 4.6
+ method_copyReturnType@Base 4.6
+ method_exchangeImplementations@Base 4.6
+ method_getArgumentType@Base 4.6
+ method_getDescription@Base 4.6
+ method_getImplementation@Base 4.6
+ method_getName@Base 4.6
+ method_getNumberOfArguments@Base 4.6
+ method_getReturnType@Base 4.6
+ method_getTypeEncoding@Base 4.6
+ method_get_imp@Base 4.6
+ method_setImplementation@Base 4.6
+ narrays@Base 4.2.1
+ nbuckets@Base 4.2.1
+ nil_method@Base 4.2.1
+ nindices@Base 4.2.1
+ objc_aligned_size@Base 4.2.1
+ objc_alignof_type@Base 4.2.1
+ objc_allocateClassPair@Base 4.6
+ objc_atomic_malloc@Base 4.2.1
+ objc_calloc@Base 4.2.1
+ objc_condition_allocate@Base 4.2.1
+ objc_condition_broadcast@Base 4.2.1
+ objc_condition_deallocate@Base 4.2.1
+ objc_condition_signal@Base 4.2.1
+ objc_condition_wait@Base 4.2.1
+ objc_copyProtocolList@Base 4.6
+ objc_copyStruct@Base 4.6
+ objc_disposeClassPair@Base 4.6
+ objc_enumerationMutation@Base 4.6
+ objc_exception_throw@Base 4.2.1
+ objc_free@Base 4.2.1
+ objc_getClass@Base 4.6
+ objc_getClassList@Base 4.6
+ objc_getMetaClass@Base 4.6
+ objc_getProperty@Base 4.6
+ objc_getPropertyStruct@Base 4.6
+ objc_getProtocol@Base 4.6
+ objc_getRequiredClass@Base 4.6
+ objc_get_class@Base 4.2.1
+ objc_get_meta_class@Base 4.2.1
+ objc_get_type_qualifiers@Base 4.2.1
+ objc_hash_add@Base 4.2.1
+ objc_hash_delete@Base 4.2.1
+ objc_hash_is_key_in_hash@Base 4.2.1
+ objc_hash_new@Base 4.2.1
+ objc_hash_next@Base 4.2.1
+ objc_hash_remove@Base 4.2.1
+ objc_hash_value_for_key@Base 4.2.1
+ objc_layout_finish_structure@Base 4.2.1
+ objc_layout_structure@Base 4.2.1
+ objc_layout_structure_get_info@Base 4.2.1
+ objc_layout_structure_next_member@Base 4.2.1
+ objc_lookUpClass@Base 4.6
+ objc_lookup_class@Base 4.2.1
+ objc_malloc@Base 4.2.1
+ objc_msg_lookup@Base 4.2.1
+ objc_msg_lookup_super@Base 4.2.1
+ objc_mutex_allocate@Base 4.2.1
+ objc_mutex_deallocate@Base 4.2.1
+ objc_mutex_lock@Base 4.2.1
+ objc_mutex_trylock@Base 4.2.1
+ objc_mutex_unlock@Base 4.2.1
+ objc_promoted_size@Base 4.2.1
+ objc_realloc@Base 4.2.1
+ objc_registerClassPair@Base 4.6
+ objc_setEnumerationMutationHandler@Base 4.6
+ objc_setExceptionMatcher@Base 4.6
+ objc_setGetUnknownClassHandler@Base 4.6
+ objc_setProperty@Base 4.6
+ objc_setPropertyStruct@Base 4.6
+ objc_setUncaughtExceptionHandler@Base 4.6
+ objc_set_thread_callback@Base 4.2.1
+ objc_sizeof_type@Base 4.2.1
+ objc_skip_argspec@Base 4.2.1
+ objc_skip_offset@Base 4.2.1
+ objc_skip_type_qualifiers@Base 4.2.1
+ objc_skip_typespec@Base 4.2.1
+ objc_sync_enter@Base 4.6
+ objc_sync_exit@Base 4.6
+ objc_thread_add@Base 4.2.1
+ objc_thread_detach@Base 4.2.1
+ objc_thread_exit@Base 4.2.1
+ objc_thread_get_data@Base 4.2.1
+ objc_thread_get_priority@Base 4.2.1
+ objc_thread_id@Base 4.2.1
+ objc_thread_remove@Base 4.2.1
+ objc_thread_set_data@Base 4.2.1
+ objc_thread_set_priority@Base 4.2.1
+ objc_thread_yield@Base 4.2.1
+ object_copy@Base 4.2.1
+ object_dispose@Base 4.2.1
+ object_getClassName@Base 4.6
+ object_getIndexedIvars@Base 4.6
+ object_getInstanceVariable@Base 4.6
+ object_getIvar@Base 4.6
+ object_setClass@Base 4.6
+ object_setInstanceVariable@Base 4.6
+ object_setIvar@Base 4.6
+ property_getAttributes@Base 4.6
+ property_getName@Base 4.6
+ protocol_conformsToProtocol@Base 4.6
+ protocol_copyMethodDescriptionList@Base 4.6
+ protocol_copyPropertyList@Base 4.6
+ protocol_copyProtocolList@Base 4.6
+ protocol_getMethodDescription@Base 4.6
+ protocol_getName@Base 4.6
+ protocol_getProperty@Base 4.6
+ protocol_isEqual@Base 4.6
+ sarray_at_put@Base 4.2.1
+ sarray_at_put_safe@Base 4.2.1
+ sarray_free@Base 4.2.1
+ sarray_lazy_copy@Base 4.2.1
+ sarray_new@Base 4.2.1
+ sarray_realloc@Base 4.2.1
+ sarray_remove_garbage@Base 4.2.1
+ search_for_method_in_list@Base 4.2.1
+ sel_copyTypedSelectorList@Base 4.6
+ sel_getName@Base 4.6
+ sel_getTypeEncoding@Base 4.6
+ sel_getTypedSelector@Base 4.6
+ sel_getUid@Base 4.6 
+ sel_get_any_uid@Base 4.2.1
+ sel_isEqual@Base 4.6
+ sel_is_mapped@Base 4.2.1
+ sel_registerName@Base 4.6
+ sel_registerTypedName@Base 4.6
--- gcc-6-6.4.0.orig/debian/libobjc.symbols.gc
+++ gcc-6-6.4.0/debian/libobjc.symbols.gc
@@ -0,0 +1,522 @@
+ async_set_pht_entry_from_index@Base 4.2.1
+ free_list_index_of@Base 4.2.1
+ suspend_self@Base 4.2.1
+ GC_abort@Base 6
+ GC_acquire_mark_lock@Base 6
+ GC_add_ext_descriptor@Base 6
+ GC_add_leaked@Base 6
+ GC_add_map_entry@Base 6
+ GC_add_roots@Base 6
+ GC_add_roots_inner@Base 6
+ GC_add_smashed@Base 6
+ GC_add_to_black_list_normal@Base 6
+ GC_add_to_black_list_stack@Base 6
+ GC_add_to_fl@Base 6
+ GC_add_to_heap@Base 6
+ GC_adj_words_allocd@Base 6
+ GC_all_bottom_indices@Base 6
+ GC_all_bottom_indices_end@Base 6
+ GC_all_interior_pointers@Base 6
+ GC_alloc_large@Base 6
+ GC_alloc_large_and_clear@Base 6
+ GC_alloc_reclaim_list@Base 6
+ GC_allocate_ml@Base 6
+ GC_allochblk@Base 6
+ GC_allochblk_nth@Base 6
+ GC_allocobj@Base 6
+ GC_aobjfreelist_ptr@Base 6
+ GC_apply_to_all_blocks@Base 6
+ GC_apply_to_maps@Base 6
+ GC_approx_sp@Base 6
+ GC_arobjfreelist@Base 6
+ GC_array_kind@Base 6
+ GC_array_mark_proc@Base 6
+ GC_array_mark_proc_index@Base 6
+ GC_arrays@Base 6
+ GC_auobjfreelist_ptr@Base 6
+ GC_avail_descr@Base 6
+ GC_base@Base 6
+ GC_begin_syscall@Base 6
+ GC_bl_init@Base 6
+ GC_black_list_spacing@Base 6
+ GC_block_count@Base 6
+ GC_block_empty@Base 6
+ GC_block_nearly_full1@Base 6
+ GC_block_nearly_full3@Base 6
+ GC_block_nearly_full@Base 6
+ GC_block_was_dirty@Base 6
+ GC_bm_table@Base 6
+ GC_brief_async_signal_safe_sleep@Base 6
+ GC_build_fl1@Base 6
+ GC_build_fl2@Base 6
+ GC_build_fl4@Base 6
+ GC_build_fl@Base 6
+ GC_build_fl_clear2@Base 6
+ GC_build_fl_clear3@Base 6
+ GC_build_fl_clear4@Base 6
+ GC_call_with_alloc_lock@Base 6
+ GC_calloc_explicitly_typed@Base 6
+ GC_change_stubborn@Base 6
+ GC_check_annotated_obj@Base 6
+ GC_check_heap@Base 6
+ GC_check_heap_block@Base 6
+ GC_check_heap_proc@Base 6
+ GC_clear_a_few_frames@Base 6
+ GC_clear_bl@Base 6
+ GC_clear_fl_links@Base 6
+ GC_clear_fl_marks@Base 6
+ GC_clear_hdr_marks@Base 6
+ GC_clear_mark_bit@Base 6
+ GC_clear_marks@Base 6
+ GC_clear_roots@Base 6
+ GC_clear_stack@Base 6
+ GC_clear_stack_inner@Base 6
+ GC_collect_a_little@Base 6
+ GC_collect_a_little_inner@Base 6
+ GC_collect_or_expand@Base 6
+ GC_collecting@Base 6
+ GC_collection_in_progress@Base 6
+ GC_cond_register_dynamic_libraries@Base 6
+ GC_continue_reclaim@Base 6
+ GC_copy_bl@Base 6
+ GC_copyright@Base 6
+ GC_current_warn_proc@Base 6
+ GC_data_start@Base 6
+ GC_debug_change_stubborn@Base 6
+ GC_debug_end_stubborn_change@Base 6
+ GC_debug_free@Base 6
+ GC_debug_free_inner@Base 6
+ GC_debug_gcj_fast_malloc@Base 6
+ GC_debug_gcj_malloc@Base 6
+ GC_debug_header_size@Base 6
+ GC_debug_invoke_finalizer@Base 6
+ GC_debug_malloc@Base 6
+ GC_debug_malloc_atomic@Base 6
+ GC_debug_malloc_atomic_ignore_off_page@Base 6
+ GC_debug_malloc_atomic_uncollectable@Base 6
+ GC_debug_malloc_ignore_off_page@Base 6
+ GC_debug_malloc_replacement@Base 6
+ GC_debug_malloc_stubborn@Base 6
+ GC_debug_malloc_uncollectable@Base 6
+ GC_debug_print_heap_obj_proc@Base 6
+ GC_debug_realloc@Base 6
+ GC_debug_realloc_replacement@Base 6
+ GC_debug_register_displacement@Base 6
+ GC_debug_register_finalizer@Base 6
+ GC_debug_register_finalizer_ignore_self@Base 6
+ GC_debug_register_finalizer_no_order@Base 6
+ GC_debug_register_finalizer_unreachable@Base 6
+ GC_debugging_started@Base 6
+ GC_default_is_valid_displacement_print_proc@Base 6
+ GC_default_is_visible_print_proc@Base 6
+ GC_default_oom_fn@Base 6
+ GC_default_print_heap_obj_proc@Base 6
+ GC_default_push_other_roots@Base 6
+ GC_default_same_obj_print_proc@Base 6
+ GC_default_warn_proc@Base 6
+ GC_deficit@Base 6
+ GC_delete_gc_thread@Base 6
+ GC_delete_thread@Base 6
+ GC_descr_obj_size@Base 6
+ GC_destroy_thread_local@Base 6
+ GC_dirty_init@Base 6
+ GC_dirty_maintained@Base 6
+ GC_disable@Base 6
+ GC_disable_signals@Base 6
+ GC_dl_entries@Base 6
+ GC_dlopen@Base 6
+ GC_do_nothing@Base 6
+ GC_dont_expand@Base 6
+ GC_dont_gc@Base 6
+ GC_dont_precollect@Base 6
+ GC_double_descr@Base 6
+ GC_dump@Base 6
+ GC_dump_finalization@Base 6
+ GC_dump_regions@Base 6
+ GC_dump_regularly@Base 6
+ GC_ed_size@Base 6
+ GC_enable@Base 6
+ GC_enable_incremental@Base 6
+ GC_enable_signals@Base 6
+ GC_end_blocking@Base 6
+ GC_end_stubborn_change@Base 6
+ GC_end_syscall@Base 6
+ GC_enqueue_all_finalizers@Base 6
+ GC_eobjfreelist@Base 6
+ GC_err_printf@Base 6
+ GC_err_puts@Base 6
+ GC_err_write@Base 6
+ GC_excl_table_entries@Base 6
+ GC_exclude_static_roots@Base 6
+ GC_exit_check@Base 6
+ GC_expand_hp@Base 6
+ GC_expand_hp_inner@Base 6
+ GC_explicit_kind@Base 6
+ GC_explicit_typing_initialized@Base 6
+ GC_ext_descriptors@Base 6
+ GC_extend_size_map@Base 6
+ GC_fail_count@Base 6
+ GC_fault_handler@Base 6
+ GC_finalization_failures@Base 6
+ GC_finalize@Base 6
+ GC_finalize_all@Base 6
+ GC_finalize_now@Base 6
+ GC_finalize_on_demand@Base 6
+ GC_finalizer_notifier@Base 6
+ GC_find_header@Base 6
+ GC_find_leak@Base 6
+ GC_find_limit@Base 6
+ GC_find_start@Base 6
+ GC_finish_collection@Base 6
+ GC_fl_builder_count@Base 6
+ GC_fo_entries@Base 6
+ GC_free@Base 6
+ GC_free_block_ending_at@Base 6
+ GC_free_bytes@Base 6
+ GC_free_inner@Base 6
+ GC_free_space_divisor@Base 6
+ GC_freehblk@Base 6
+ GC_freehblk_ptr@Base 6
+ GC_full_freq@Base 6
+ GC_gc_no@Base 6
+ GC_gcj_debug_kind@Base 6
+ GC_gcj_fast_malloc@Base 6
+ GC_gcj_kind@Base 6
+ GC_gcj_malloc@Base 6
+ GC_gcj_malloc_ignore_off_page@Base 6
+ GC_gcj_malloc_initialized@Base 6
+ GC_gcjdebugobjfreelist@Base 6
+ GC_gcjobjfreelist@Base 6
+ GC_gcollect@Base 6
+ GC_general_register_disappearing_link@Base 6
+ GC_generic_lock@Base 6
+ GC_generic_malloc@Base 6
+ GC_generic_malloc_ignore_off_page@Base 6
+ GC_generic_malloc_inner@Base 6
+ GC_generic_malloc_inner_ignore_off_page@Base 6
+ GC_generic_malloc_many@Base 6
+ GC_generic_malloc_words_small@Base 6
+ GC_generic_malloc_words_small_inner@Base 6
+ GC_generic_or_special_malloc@Base 6
+ GC_generic_push_regs@Base 6
+ GC_get_bytes_since_gc@Base 6
+ GC_get_first_part@Base 6
+ GC_get_free_bytes@Base 6
+ GC_get_heap_size@Base 6
+ GC_get_nprocs@Base 6
+ GC_get_stack_base@Base 6
+ GC_get_thread_stack_base@Base 6
+ GC_get_total_bytes@Base 6
+ GC_greatest_plausible_heap_addr@Base 6
+ GC_grow_table@Base 6
+ GC_has_other_debug_info@Base 6
+ GC_have_errors@Base 6
+ GC_hblk_fl_from_blocks@Base 6
+ GC_hblkfreelist@Base 6
+ GC_hdr_cache_hits@Base 6
+ GC_hdr_cache_misses@Base 6
+ GC_high_water@Base 6
+ GC_ignore_self_finalize_mark_proc@Base 6
+ GC_in_thread_creation@Base 6
+ GC_incomplete_normal_bl@Base 6
+ GC_incomplete_stack_bl@Base 6
+ GC_incr_mem_freed@Base 6
+ GC_incr_words_allocd@Base 6
+ GC_incremental@Base 6
+ GC_incremental_protection_needs@Base 6
+ GC_init@Base 6
+ GC_init_explicit_typing@Base 6
+ GC_init_gcj_malloc@Base 6
+ GC_init_headers@Base 6
+ GC_init_inner@Base 6
+ GC_init_linux_data_start@Base 6
+ GC_init_parallel@Base 6
+ GC_init_size_map@Base 6
+ GC_init_thread_local@Base 6
+ GC_initiate_gc@Base 6
+ GC_install_counts@Base 6
+ GC_install_header@Base 6
+ GC_invalid_header@Base 6
+ GC_invalid_map@Base 6
+ GC_invalidate_map@Base 6
+ GC_invalidate_mark_state@Base 6
+ GC_invoke_finalizers@Base 6
+ GC_is_black_listed@Base 6
+ GC_is_fresh@Base 6
+ GC_is_full_gc@Base 6
+ GC_is_initialized@Base 6
+ GC_is_marked@Base 6
+ GC_is_static_root@Base 6
+ GC_is_thread_suspended@Base 6
+ GC_is_valid_displacement@Base 6
+ GC_is_valid_displacement_print_proc@Base 6
+ GC_is_visible@Base 6
+ GC_is_visible_print_proc@Base 6
+ GC_java_finalization@Base 6
+ GC_jmp_buf@Base 6
+ GC_key_create@Base 6
+ GC_large_alloc_warn_interval@Base 6
+ GC_large_alloc_warn_suppressed@Base 6
+ GC_leaked@Base 6
+ GC_least_plausible_heap_addr@Base 6
+ GC_linux_stack_base@Base 6
+ GC_local_gcj_malloc@Base 6
+ GC_local_malloc@Base 6
+ GC_local_malloc_atomic@Base 6
+ GC_lock@Base 6
+ GC_lock_holder@Base 6
+ GC_lookup_thread@Base 6
+ GC_make_array_descriptor@Base 6
+ GC_make_closure@Base 6
+ GC_make_descriptor@Base 6
+ GC_make_sequence_descriptor@Base 6
+ GC_malloc@Base 6
+ GC_malloc_atomic@Base 6
+ GC_malloc_atomic_ignore_off_page@Base 6
+ GC_malloc_atomic_uncollectable@Base 6
+ GC_malloc_explicitly_typed@Base 6
+ GC_malloc_explicitly_typed_ignore_off_page@Base 6
+ GC_malloc_ignore_off_page@Base 6
+ GC_malloc_many@Base 6
+ GC_malloc_stubborn@Base 6
+ GC_malloc_uncollectable@Base 6
+ GC_mark_and_push@Base 6
+ GC_mark_and_push_stack@Base 6
+ GC_mark_from@Base 6
+ GC_mark_init@Base 6
+ GC_mark_some@Base 6
+ GC_mark_stack@Base 6
+ GC_mark_stack_empty@Base 6
+ GC_mark_stack_limit@Base 6
+ GC_mark_stack_size@Base 6
+ GC_mark_stack_too_small@Base 6
+ GC_mark_stack_top@Base 6
+ GC_mark_state@Base 6
+ GC_mark_thread_local_free_lists@Base 6
+ GC_max@Base 6
+ GC_max_retries@Base 6
+ GC_maybe_gc@Base 6
+ GC_mem_found@Base 6
+ GC_memalign@Base 6
+ GC_min@Base 6
+ GC_min_sp@Base 6
+ GC_n_attempts@Base 6
+ GC_n_heap_sects@Base 6
+ GC_n_kinds@Base 6
+ GC_n_leaked@Base 6
+ GC_n_mark_procs@Base 6
+ GC_n_rescuing_pages@Base 6
+ GC_n_set_marks@Base 6
+ GC_n_smashed@Base 6
+ GC_need_full_gc@Base 6
+ GC_never_stop_func@Base 6
+ GC_new_free_list@Base 6
+ GC_new_free_list_inner@Base 6
+ GC_new_hblk@Base 6
+ GC_new_kind@Base 6
+ GC_new_kind_inner@Base 6
+ GC_new_proc@Base 6
+ GC_new_proc_inner@Base 6
+ GC_new_thread@Base 6
+ GC_next_exclusion@Base 6
+ GC_next_used_block@Base 6
+ GC_no_dls@Base 6
+ GC_non_gc_bytes@Base 6
+ GC_noop1@Base 6
+ GC_noop@Base 6
+ GC_normal_finalize_mark_proc@Base 6
+ GC_notify_all_builder@Base 6
+ GC_notify_full_gc@Base 6
+ GC_notify_or_invoke_finalizers@Base 6
+ GC_nprocs@Base 6
+ GC_null_finalize_mark_proc@Base 6
+ GC_number_stack_black_listed@Base 6
+ GC_obj_kinds@Base 6
+ GC_objects_are_marked@Base 6
+ GC_objfreelist_ptr@Base 6
+ GC_old_bus_handler@Base 6
+ GC_old_normal_bl@Base 6
+ GC_old_segv_handler@Base 6
+ GC_old_stack_bl@Base 6
+ GC_on_stack@Base 6
+ GC_oom_fn@Base 6
+ GC_page_size@Base 6
+ GC_page_was_dirty@Base 6
+ GC_page_was_ever_dirty@Base 6
+ GC_parallel@Base 6
+ GC_pause@Base 6
+ GC_post_incr@Base 6
+ GC_pre_incr@Base 6
+ GC_prev_block@Base 6
+ GC_print_address_map@Base 6
+ GC_print_all_errors@Base 6
+ GC_print_all_smashed@Base 6
+ GC_print_all_smashed_proc@Base 6
+ GC_print_back_height@Base 6
+ GC_print_block_descr@Base 6
+ GC_print_block_list@Base 6
+ GC_print_finalization_stats@Base 6
+ GC_print_hblkfreelist@Base 6
+ GC_print_heap_obj@Base 6
+ GC_print_heap_sects@Base 6
+ GC_print_obj@Base 6
+ GC_print_smashed_obj@Base 6
+ GC_print_source_ptr@Base 6
+ GC_print_static_roots@Base 6
+ GC_print_stats@Base 6
+ GC_print_type@Base 6
+ GC_printf@Base 6
+ GC_project2@Base 6
+ GC_promote_black_lists@Base 6
+ GC_protect_heap@Base 6
+ GC_pthread_create@Base 6
+ GC_pthread_detach@Base 6
+ GC_pthread_join@Base 6
+ GC_pthread_sigmask@Base 6
+ GC_push_all@Base 6
+ GC_push_all_eager@Base 6
+ GC_push_all_stack@Base 6
+ GC_push_all_stacks@Base 6
+ GC_push_complex_descriptor@Base 6
+ GC_push_conditional@Base 6
+ GC_push_conditional_with_exclusions@Base 6
+ GC_push_current_stack@Base 6
+ GC_push_finalizer_structures@Base 6
+ GC_push_gc_structures@Base 6
+ GC_push_marked1@Base 6
+ GC_push_marked2@Base 6
+ GC_push_marked4@Base 6
+ GC_push_marked@Base 6
+ GC_push_next_marked@Base 6
+ GC_push_next_marked_dirty@Base 6
+ GC_push_next_marked_uncollectable@Base 6
+ GC_push_one@Base 6
+ GC_push_other_roots@Base 6
+ GC_push_roots@Base 6
+ GC_push_selected@Base 6
+ GC_push_stubborn_structures@Base 6
+ GC_push_thread_structures@Base 6
+ GC_quiet@Base 6
+ GC_read_dirty@Base 6
+ GC_realloc@Base 6
+ GC_reclaim1@Base 6
+ GC_reclaim_all@Base 6
+ GC_reclaim_block@Base 6
+ GC_reclaim_check@Base 6
+ GC_reclaim_clear2@Base 6
+ GC_reclaim_clear4@Base 6
+ GC_reclaim_clear@Base 6
+ GC_reclaim_generic@Base 6
+ GC_reclaim_small_nonempty_block@Base 6
+ GC_reclaim_uninit2@Base 6
+ GC_reclaim_uninit4@Base 6
+ GC_reclaim_uninit@Base 6
+ GC_register_data_segments@Base 6
+ GC_register_describe_type_fn@Base 6
+ GC_register_disappearing_link@Base 6
+ GC_register_displacement@Base 6
+ GC_register_displacement_inner@Base 6
+ GC_register_dynamic_libraries@Base 6
+ GC_register_dynamic_libraries_dl_iterate_phdr@Base 6
+ GC_register_finalizer@Base 6
+ GC_register_finalizer_ignore_self@Base 6
+ GC_register_finalizer_inner@Base 6
+ GC_register_finalizer_no_order@Base 6
+ GC_register_finalizer_unreachable@Base 6
+ GC_register_has_static_roots_callback@Base 6
+ GC_register_main_static_data@Base 6
+ GC_register_my_thread@Base 6
+ GC_release_mark_lock@Base 6
+ GC_remove_allowed_signals@Base 6
+ GC_remove_counts@Base 6
+ GC_remove_from_fl@Base 6
+ GC_remove_header@Base 6
+ GC_remove_protection@Base 6
+ GC_remove_roots@Base 6
+ GC_remove_roots_inner@Base 6
+ GC_remove_specific@Base 6
+ GC_remove_tmp_roots@Base 6
+ GC_repeat_read@Base 6
+ GC_reset_fault_handler@Base 6
+ GC_restart_handler@Base 6
+ GC_resume_thread@Base 6
+ GC_retry_signals@Base 6
+ GC_root_size@Base 6
+ GC_roots_present@Base 6
+ GC_same_obj@Base 6
+ GC_same_obj_print_proc@Base 6
+ GC_scratch_alloc@Base 6
+ GC_set_and_save_fault_handler@Base 6
+ GC_set_fl_marks@Base 6
+ GC_set_free_space_divisor@Base 6
+ GC_set_hdr_marks@Base 6
+ GC_set_mark_bit@Base 6
+ GC_set_max_heap_size@Base 6
+ GC_set_warn_proc@Base 6
+ GC_setpagesize@Base 6
+ GC_setspecific@Base 6
+ GC_setup_temporary_fault_handler@Base 6
+ GC_should_collect@Base 6
+ GC_should_invoke_finalizers@Base 6
+ GC_signal_mark_stack_overflow@Base 6
+ GC_size@Base 6
+ GC_sleep@Base 6
+ GC_slow_getspecific@Base 6
+ GC_smashed@Base 6
+ GC_spin_count@Base 6
+ GC_split_block@Base 6
+ GC_stack_last_cleared@Base 6
+ GC_stackbottom@Base 6
+ GC_start_blocking@Base 6
+ GC_start_call_back@Base 6
+ GC_start_debugging@Base 6
+ GC_start_reclaim@Base 6
+ GC_start_routine@Base 6
+ GC_start_time@Base 6
+ GC_start_world@Base 6
+ GC_stderr@Base 6
+ GC_stdout@Base 6
+ GC_stop_count@Base 6
+ GC_stop_init@Base 6
+ GC_stop_world@Base 6
+ GC_stopped_mark@Base 6
+ GC_stopping_pid@Base 6
+ GC_stopping_thread@Base 6
+ GC_store_debug_info@Base 6
+ GC_suspend_ack_sem@Base 6
+ GC_suspend_all@Base 6
+ GC_suspend_handler@Base 6
+ GC_suspend_handler_inner@Base 6
+ GC_suspend_thread@Base 6
+ GC_thr_init@Base 6
+ GC_thr_initialized@Base 6
+ GC_thread_exit_proc@Base 6
+ GC_thread_key@Base 6
+ GC_threads@Base 6
+ GC_time_limit@Base 6
+ GC_timeout_stop_func@Base 6
+ GC_total_stack_black_listed@Base 6
+ GC_try_to_collect@Base 6
+ GC_try_to_collect_inner@Base 6
+ GC_typed_mark_proc@Base 6
+ GC_typed_mark_proc_index@Base 6
+ GC_unix_get_mem@Base 6
+ GC_unlocked_count@Base 6
+ GC_unpromote_black_lists@Base 6
+ GC_unprotect_range@Base 6
+ GC_unreachable_finalize_mark_proc@Base 6
+ GC_unregister_disappearing_link@Base 6
+ GC_unregister_my_thread@Base 6
+ GC_uobjfreelist_ptr@Base 6
+ GC_use_entire_heap@Base 6
+ GC_used_heap_size_after_full@Base 6
+ GC_version@Base 6
+ GC_wait_builder@Base 6
+ GC_wait_for_gc_completion@Base 6
+ GC_wait_for_reclaim@Base 6
+ GC_with_callee_saves_pushed@Base 6
+ GC_words_allocd_at_reset@Base 6
+ GC_world_is_stopped@Base 6
+ GC_world_stopped@Base 6
+ GC_write@Base 6
+ GC_write_fault_handler@Base 6
--- gcc-6-6.4.0.orig/debian/libquadmath.symbols
+++ gcc-6-6.4.0/debian/libquadmath.symbols
@@ -0,0 +1,3 @@
+libquadmath.so.0 #PACKAGE# #MINVER#
+ (symver)QUADMATH_1.0 4.6
+ (symver)QUADMATH_1.1 6
--- gcc-6-6.4.0.orig/debian/libstdc++-BV-doc.doc-base
+++ gcc-6-6.4.0/debian/libstdc++-BV-doc.doc-base
@@ -0,0 +1,13 @@
+Document: libstdc++-@BV@-doc
+Title: The GNU Standard C++ Library v3 (gcc-@BV@)
+Author: Various
+Abstract: This package contains documentation files for the GNU stdc++ library.
+ One set is the distribution documentation, the other set is the
+ source documentation including a namespace list, class hierarchy,
+ alphabetical list, compound list, file list, namespace members,
+ compound members and file members.
+Section: Programming/C++
+
+Format: html
+Index: /usr/share/doc/libstdc++-@BV@-doc/libstdc++/index.html
+Files: /usr/share/doc/libstdc++-@BV@-doc/libstdc++/*
--- gcc-6-6.4.0.orig/debian/libstdc++-BV-doc.overrides
+++ gcc-6-6.4.0/debian/libstdc++-BV-doc.overrides
@@ -0,0 +1,11 @@
+libstdc++-@BV@-doc binary: hyphen-used-as-minus-sign
+libstdc++-@BV@-doc binary: manpage-has-bad-whatis-entry
+
+# 3xx used by intent to avoid conficts
+libstdc++-@BV@-doc binary: manpage-section-mismatch
+
+# some very long identifiers
+libstdc++-@BV@-doc binary: manpage-has-errors-from-man.*can't break line
+
+# doxygen accepts formulas in man pages ...
+libstdc++-@BV@-doc binary: manpage-has-errors-from-man.*a space character is not allowed in an escape name
--- gcc-6-6.4.0.orig/debian/libstdc++-breaks.Debian
+++ gcc-6-6.4.0/debian/libstdc++-breaks.Debian
@@ -0,0 +1,94 @@
+libantlr-dev (<= 2.7.7+dfsg-6),
+libaqsis1 (<= 1.8.2-1),
+libassimp3 (<= 3.0~dfsg-4),
+blockattack (<= 1.4.1+ds1-2.1+b2),
+boo (<= 0.9.5~git20110729.r1.202a430-2),
+libboost-date-time1.54.0,
+libboost-date-time1.55.0,
+libcpprest2.4 (<= 2.4.0-2),
+printer-driver-brlaser (<= 3-3),
+c++-annotations (<= 10.2.0-1),
+clustalx (<= 2.1+lgpl-3),
+libdavix0 (<= 0.4.0-1+b1),
+libdballe6 (<= 6.8-1),
+dff (<= 1.3.0+dfsg.1-4.1+b3),
+libdiet-sed2.8 (<= 2.8.0-1+b3),
+libdiet-client2.8 (<= 2.8.0-1+b3),
+libdiet-admin2.8 (<= 2.8.0-1+b3),
+digikam-private-libs (<= 4:4.4.0-1.1+b2),
+emscripten (<= 1.22.1-1),
+ergo (<= 3.4.0-1),
+fceux (<= 2.2.2+dfsg0-1),
+flush (<= 0.9.12-3.1),
+libfreefem++ (<= 3.37.1-1),
+freeorion (<= 0.4.4+git20150327-2),
+fslview (<= 4.0.1-4),
+fwbuilder (<= 5.1.0-4),
+libgazebo5 (<= 5.0.1+dfsg-2.1),
+libgetfem4++ (<= 4.2.1~beta1~svn4635~dfsg-3+b1),
+libgmsh2 (<= 2.9.3+dfsg1-1),
+gnote (<= 3.16.2-1),
+gnudatalanguage (<= 0.9.5-2+b2),
+python-healpy (<= 1.8.1-1+b1),
+innoextract (<= 1.4-1+b1),
+libinsighttoolkit4.7 (<= 4.7.2-2),
+libdap17 (<= 3.14.0-2),
+libdapclient6 (<= 3.14.0-2),
+libdapserver7 (<= 3.14.0-2),
+libkolabxml1 (<= 1.1.0-3),
+libpqxx-4.0 (<= 4.0.1+dfsg-3),
+libreoffice-core (<= 1:4.4.5-2),
+librime1 (<= 1.2+dfsg-2),
+libwibble-dev (<= 1.1-1),
+lightspark (<= 0.7.2+git20150512-2+b1),
+libmarisa0 (<= 0.2.4-8),
+mira-assembler (<= 4.9.5-1),
+mongodb (<= 1:2.4.14-2),
+mongodb-server (<= 1:2.4.14-2),
+ncbi-blast+ (<= 2.2.30-4),
+libogre-1.8.0 (<= 1.8.0+dfsg1-7+b1),
+libogre-1.9.0 (<= 1.9.0+dfsg1-4),
+openscad (<= 2014.03+dfsg-1+b1),
+libopenwalnut1 (<= 1.4.0~rc1+hg3a3147463ee2-1+b1),
+passepartout (<= 0.7.1-1.1),
+pdf2djvu (<= 0.7.21-2),
+photoprint (<= 0.4.2~pre2-2.3+b2),
+plastimatch (<= 1.6.2+dfsg-1),
+plee-the-bear (<= 0.6.0-3.1),
+povray (<= 1:3.7.0.0-8),
+powertop (<= 2.6.1-1),
+psi4 (<= 4.0~beta5+dfsg-2+b1),
+python3-taglib (<= 0.3.6+dfsg-2+b2),
+realtimebattle (<= 1.0.8-14),
+ruby-passenger (<= 5.0.7-1),
+libapache2-mod-passenger (<= 5.0.7-1),
+schroot (<= 1.6.10-1+b1),
+sqlitebrowser (<= 3.5.1-3),
+tecnoballz (<= 0.93.1-6),
+wesnoth-1.12-core (<= 1:1.12.4-1),
+widelands (<= 1:18-3+b1),
+libwreport2 (<= 2.14-1),
+xflr5 (<= 6.09.06-2),
+libxmltooling6 (<= 1.5.3-2.1),
+libchemps2-1 (<= 1.5-1),
+python-fiona (<= 1.5.1-2),
+python3-fiona (<= 1.5.1-2),
+fiona (<= 1.5.1-2),
+python-guiqwt (<= 2.3.1-1),
+python-htseq (<= 0.5.4p3-2),
+python-imposm (<= 2.5.0-3+b2),
+python-pysph (<= 0~20150606.gitfa26de9-5),
+python3-taglib (<= 0.3.6+dfsg-2+b2),
+python-scipy (<= 0.14.1-1),
+python3-scipy (<= 0.14.1-1),
+python-sfml (<= 2.2~git20150611.196c88+dfsg-1+b1),
+python3-sfml (<= 2.2~git20150611.196c88+dfsg-1+b1),
+python-rasterio (<= 0.24.0-1),
+libopenmpi1.6,
+libopencv-core2.4,
+libsigc++-2.0-0c2a (<= 2.4.1-1+b1),
+libktoblzcheck1c2a,
+libaqbanking34-plugins,
+liblhapdf0,
+libpythia8,
+libxapian30 (<= 1.4.1-1~bpo8+1),
--- gcc-6-6.4.0.orig/debian/libstdc++-breaks.Ubuntu
+++ gcc-6-6.4.0/debian/libstdc++-breaks.Ubuntu
@@ -0,0 +1,73 @@
+libantlr-dev (<= 2.7.7+dfsg-6),
+libaqsis1 (<= 1.8.2-1),
+libassimp3 (<= 3.0~dfsg-4),
+blockattack (<= 1.4.1+ds1-2.1build2),
+boo (<= 0.9.5~git20110729.r1.202a430-2),
+libboost-date-time1.55.0,
+libcpprest2.2 (<= 2.2.0-1),
+printer-driver-brlaser (<= 3-3),
+c++-annotations (<= 10.2.0-1),
+chromium-browser (<= 43.0.2357.130-0ubuntu2),
+clustalx (<= 2.1+lgpl-2),
+libdavix0 (<= 0.4.0-1build1),
+libdballe6 (<= 6.8-1),
+dff (<= 1.3.0+dfsg.1-4.1build2),
+libdiet-sed2.8 (<= 2.8.0-1build3),
+libdiet-client2.8 (<= 2.8.0-1build3),
+libdiet-admin2.8 (<= 2.8.0-1build3),
+libkgeomap2 (<= 4:15.04.2-0ubuntu1),
+libmediawiki1 (<= 1.0~digikam4.10.0-0ubuntu2),
+libkvkontakte1 (<= 1.0~digikam4.10.0-0ubuntu2),
+emscripten (<= 1.22.1-1),
+ergo (<= 3.4.0-1),
+fceux (<= 2.2.2+dfsg0-1),
+flush (<= 0.9.12-3.1ubuntu1),
+libfreefem++ (<= 3.37.1-1),
+freeorion (<= 0.4.4+git20150327-2),
+fslview (<= 4.0.1-4),
+fwbuilder (<= 5.1.0-4),
+libgazebo5 (<= 5.0.1+dfsg-2.1),
+libgetfem4++ (<= 4.2.1~beta1~svn4482~dfsg-3ubuntu3),
+libgmsh2 (<= 2.8.5+dfsg-1.1ubuntu1),
+gnote (<= 3.16.2-1),
+gnudatalanguage (<= 0.9.5-2build1),
+python-healpy (<= 1.8.1-1),
+innoextract (<= 1.4-1build1),
+libinsighttoolkit4.6 (<= 4.6.0-3ubuntu3),
+libdap17 (<= 3.14.0-2),
+libdapclient6 (<= 3.14.0-2),
+libdapserver7 (<= 3.14.0-2),
+libkolabxml1 (<= 1.1.0-3),
+libpqxx-4.0 (<= 4.0.1+dfsg-3ubuntu1),
+libreoffice-core (<= 1:4.4.4~rc3-0ubuntu1),
+librime1 (<= 1.2+dfsg-2),
+libwibble-dev (<= 1.1-1),
+lightspark (<= 0.7.2+git20150512-2),
+libmarisa0 (<= 0.2.4-8build1),
+mira-assembler (<= 4.9.5-1),
+mongodb (<= 1:2.6.3-0ubuntu7),
+mongodb-server (<= 1:2.6.3-0ubuntu7),
+ncbi-blast+ (<= 2.2.30-4),
+libogre-1.8.0 (<= 1.8.1+dfsg-0ubuntu5),
+libogre-1.9.0 (<= 1.9.0+dfsg1-4),
+openscad (<= 2014.03+dfsg-1build1),
+libopenwalnut1 (<= 1.4.0~rc1+hg3a3147463ee2-1ubuntu2),
+passepartout (<= 0.7.1-1.1),
+pdf2djvu (<= 0.7.19-1ubuntu2),
+photoprint (<= 0.4.2~pre2-2.3),
+plastimatch (<= 1.6.2+dfsg-1),
+plee-the-bear (<= 0.6.0-3.1),
+povray (<= 1:3.7.0.0-8),
+powertop (<= 2.6.1-1),
+psi4 (<= 4.0~beta5+dfsg-2build1),
+python3-taglib (<= 0.3.6+dfsg-2build2),
+realtimebattle (<= 1.0.8-14),
+ruby-passenger (<= 4.0.53-1),
+libapache2-mod-passenger (<= 4.0.53-1),
+sqlitebrowser (<= 3.5.1-3),
+tecnoballz (<= 0.93.1-6),
+wesnoth-1.12-core (<= 1:1.12.4-1),
+widelands (<= 1:18-3build1),
+libwreport2 (<= 2.14-1),
+xflr5 (<= 6.09.06-2),
+libxmltooling6 (<= 1.5.3-2.1),
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.128bit
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.128bit
@@ -0,0 +1,46 @@
+ _ZNSt14numeric_limitsInE10has_denormE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE10is_boundedE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE10is_integerE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE11round_styleE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE12has_infinityE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE12max_digits10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE12max_exponentE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE12min_exponentE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE13has_quiet_NaNE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE14is_specializedE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE14max_exponent10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE14min_exponent10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE15has_denorm_lossE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE15tinyness_beforeE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE17has_signaling_NaNE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE5radixE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE5trapsE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE6digitsE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE8digits10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE8is_exactE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE9is_iec559E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE9is_moduloE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsInE9is_signedE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE10has_denormE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE10is_boundedE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE10is_integerE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE11round_styleE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE12has_infinityE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE12max_digits10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE12max_exponentE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE12min_exponentE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE13has_quiet_NaNE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE14is_specializedE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE14max_exponent10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE14min_exponent10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE15has_denorm_lossE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE15tinyness_beforeE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE17has_signaling_NaNE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE5radixE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE5trapsE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE6digitsE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE8digits10E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE8is_exactE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE9is_iec559E@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE9is_moduloE@GLIBCXX_3.4.17 4.7
+ _ZNSt14numeric_limitsIoE9is_signedE@GLIBCXX_3.4.17 4.7
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.32bit
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.32bit
@@ -0,0 +1,601 @@
+#include "libstdc++6.symbols.common"
+#include "libstdc++6.symbols.32bit.cxx11"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEj@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEj@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reclaim_blockEPcj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reserve_blockEjj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reclaim_blockEPcj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reserve_blockEjj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx9free_list6_M_getEj@GLIBCXX_3.4.4 4.1.1
+ _ZNK10__cxxabiv117__class_type_info12__do_dyncastEiNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__class_type_info20__do_find_public_srcEiPKvPKS0_S2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEjjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEjjPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE2atEj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4copyEPwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE6substrEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjRKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_checkEjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_limitEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEEixEj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEjjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEjjPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSs16find_last_not_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs2atEj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4copyEPcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs6substrEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEjjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEjjPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEjjRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEjjRKSsjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_checkEjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_limitEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSsixEj@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE6_M_putEPcjPKcPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE6_M_putEPwjPKwPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt19__codecvt_utf8_baseIDiE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE9do_lengthER11__mbstate_tPKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIcc11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE9do_lengthERS0_PKcS4_j@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE12_M_transformEPcPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE12_M_transformEPwPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE12_M_group_intEPKcjcRSt8ios_basePcS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE14_M_group_floatEPKcjcS6_PcS7_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6_M_padEciRSt8ios_basePcPKcRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE12_M_group_intEPKcjwRSt8ios_basePwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE14_M_group_floatEPKcjwPKwPwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6_M_padEwiRSt8ios_basePwPKwRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt8__detail20_Prime_rehash_policy11_M_next_bktEj@GLIBCXX_3.4.18 4.8
+ _ZNKSt8__detail20_Prime_rehash_policy14_M_need_rehashEjjj@GLIBCXX_3.4.18 4.8
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES3_S3_RiiijRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES3_S3_RiPPKcjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE24_M_extract_wday_or_monthES3_S3_RiPPKcjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.14 4.5
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_numES3_S3_RiiijRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE15_M_extract_nameES3_S3_RiPPKwjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE24_M_extract_wday_or_monthES3_S3_RiPPKwjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.14 4.5
+ _ZNKSt8valarrayIjE4sizeEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE10_S_compareEjj@GLIBCXX_3.4.16 4.6.0
+ _ZNSbIwSt11char_traitsIwESaIwEE12_S_constructEjwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE14_M_replace_auxEjjjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE18_S_construct_aux_2EjwRKS1_@GLIBCXX_3.4.14 4.5
+ _ZNSbIwSt11char_traitsIwESaIwEE15_M_replace_safeEjjPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE2atEj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep26_M_set_length_and_sharableEj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep26_M_set_length_and_sharableEj@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep8_M_cloneERKS1_j@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep9_S_createEjjRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE5eraseEjj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendERKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6appendEjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignERKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6assignEjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEN9__gnu_cxx17__normal_iteratorIPwS2_EEjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjPKw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjRKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6insertEjjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6resizeEj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE6resizeEjw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_copyEPwPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_copyEPwPKwj@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_moveEPwPKwj@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7_M_moveEPwPKwj@GLIBCXX_3.4.5 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE7replaceEN9__gnu_cxx17__normal_iteratorIPwS2_EES6_PKwj@GLIBCXX_3.4 4.1.1
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+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZdaPvj@CXXABI_1.3.9 5
+ _ZdlPvj@CXXABI_1.3.9 5
+ _Znaj@GLIBCXX_3.4 4.1.1
+ _ZnajRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _Znwj@GLIBCXX_3.4 4.1.1
+ _ZnwjRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcEC1EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcEC2EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.32bit.cxx11
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.32bit.cxx11
@@ -0,0 +1,329 @@
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEPKcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEPKcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEjjPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEPKcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEPKcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE2atEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4copyEPcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEPKcjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6substrEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEjjPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEjjPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEjjRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEjjRKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_checkEjPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_limitEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEixEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEPKwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEPKwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE15_M_check_lengthEjjPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE2atEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4copyEPwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEPKwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEPKwjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindERKS4_j@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6substrEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEjjPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEjjPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEjjRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEjjRKS4_jj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_checkEjPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_limitEjj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEixEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE12_M_transformEPcPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE12_M_transformEPwPKwj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES4_S4_RiiijRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES4_S4_RiPPKcjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE24_M_extract_wday_or_monthES4_S4_RiPPKcjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_numES4_S4_RiiijRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE15_M_extract_nameES4_S4_RiPPKwjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE24_M_extract_wday_or_monthES4_S4_RiPPKwjRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIcEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIcEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIwEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIwEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIcc11__mbstate_tEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIcc11__mbstate_tEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIwc11__mbstate_tEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIwc11__mbstate_tEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1ERKNSt7__cxx1112basic_stringIcS2_SaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2ERKNSt7__cxx1112basic_stringIcS2_SaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC1EPSt18__moneypunct_cacheIcLb0EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC2EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC2EPSt18__moneypunct_cacheIcLb0EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC1EPSt18__moneypunct_cacheIcLb1EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC2EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC2EPSt18__moneypunct_cacheIcLb1EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb1EEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC1EPSt18__moneypunct_cacheIwLb0EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC2EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC2EPSt18__moneypunct_cacheIwLb0EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb0EEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC1EPSt18__moneypunct_cacheIwLb1EEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC1Ej@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIwLb1EEC2EPSt18__moneypunct_cacheIwLb1EEj@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1ERKNS_12basic_stringIcS3_SaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2ERKNS_12basic_stringIcS3_SaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1ERKNS_12basic_stringIcS2_IcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2ERKNS_12basic_stringIcS2_IcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC1EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC2EPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC1EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC2EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC1EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC2EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC2EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC1EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC2EP15__locale_structPKcj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC1EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC1EPSt16__numpunct_cacheIcEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC2EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC2EPSt16__numpunct_cacheIcEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC1EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC1EPSt16__numpunct_cacheIwEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC2EP15__locale_structj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC2EPSt16__numpunct_cacheIwEj@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Ej@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt17__verify_groupingPKcjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn8_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn8_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn8_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn8_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n12_NSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.32bit.hurd
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.32bit.hurd
@@ -0,0 +1,536 @@
+#include "libstdc++6.symbols.common"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEj@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEj@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reclaim_blockEPcj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reserve_blockEjj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reclaim_blockEPcj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reserve_blockEjj@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx9free_list6_M_getEj@GLIBCXX_3.4.4 4.1.1
+ _ZNK10__cxxabiv117__class_type_info12__do_dyncastEiNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__class_type_info20__do_find_public_srcEiPKvPKS0_S2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEjjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEjjPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE2atEj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4copyEPwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindERKS2_j@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE6substrEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjPKwj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEjjRKS2_jj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_checkEjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_limitEjj@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEEixEj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofERKSsj@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEjjPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEjjPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSs16find_last_not_ofEPKcj@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEPKcjj@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofERKSsj@GLIBCXX_3.4 4.1.1
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+ _ZThn8_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn8_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSiD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSiD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSoD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSoD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10istrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10istrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10ostrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt10ostrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _Znaj@GLIBCXX_3.4 4.1.1
+ _ZnajRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _Znwj@GLIBCXX_3.4 4.1.1
+ _ZnwjRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcEC1EP15__pthread_mutex@GLIBCXX_3.4 4.3.0
+ _ZNSt12__basic_fileIcEC2EP15__pthread_mutex@GLIBCXX_3.4 4.3.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.64bit
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.64bit
@@ -0,0 +1,614 @@
+#include "libstdc++6.symbols.common"
+#include "libstdc++6.symbols.64bit.cxx11"
+ _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEm@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEm@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPcl@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKcl@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsgetnEPwl@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsputnEPKwl@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx9free_list6_M_getEm@GLIBCXX_3.4.4 4.1.1
+ _ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__class_type_info20__do_find_public_srcElPKvPKS0_S2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4copyEPwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE6substrEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmRKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_checkEmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_limitEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEEixEm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEmmPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSs16find_last_not_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs2atEm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4copyEPcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs6substrEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmRKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_checkEmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_limitEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSsixEm@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE6_M_putEPcmPKcPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE6_M_putEPwmPKwPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt19__codecvt_utf8_baseIDiE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDsE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIwE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDiE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIDsE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt20__codecvt_utf16_baseIwE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDiE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIDsE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt25__codecvt_utf8_utf16_baseIwE9do_lengthER11__mbstate_tPKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDic11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIDsc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4.21 5
+ _ZNKSt7codecvtIcc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE12_M_transformEPcPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE12_M_transformEPwPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE12_M_group_intEPKcmcRSt8ios_basePcS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE14_M_group_floatEPKcmcS6_PcS7_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6_M_padEclRSt8ios_basePcPKcRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE12_M_group_intEPKcmwRSt8ios_basePwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE14_M_group_floatEPKcmwPKwPwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6_M_padEwlRSt8ios_basePwPKwRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt8__detail20_Prime_rehash_policy11_M_next_bktEm@GLIBCXX_3.4.18 4.8
+ _ZNKSt8__detail20_Prime_rehash_policy14_M_need_rehashEmmm@GLIBCXX_3.4.18 4.8
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES3_S3_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES3_S3_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE24_M_extract_wday_or_monthES3_S3_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.14 4.5
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_numES3_S3_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE15_M_extract_nameES3_S3_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE24_M_extract_wday_or_monthES3_S3_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.14 4.5
+ _ZNKSt8valarrayImE4sizeEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE10_S_compareEmm@GLIBCXX_3.4.16 4.6.0
+ _ZNSbIwSt11char_traitsIwESaIwEE12_S_constructEmwRKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE14_M_replace_auxEmmmw@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE15_M_replace_safeEmmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE18_S_construct_aux_2EmwRKS1_@GLIBCXX_3.4.14 4.5
+ _ZNSbIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep26_M_set_length_and_sharableEm@GLIBCXX_3.4 4.1.1
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+ _ZThn16_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZThn16_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSdD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSdD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSiD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSiD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSoD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSoD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt10istrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt10istrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt10ostrstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt10ostrstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_fstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_fstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_fstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_istreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_istreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_ostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt13basic_ostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ifstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ifstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ifstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ofstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ofstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt14basic_ofstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n24_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _ZdaPvm@CXXABI_1.3.9 5
+ _ZdlPvm@CXXABI_1.3.9 5
+ _Znam@GLIBCXX_3.4 4.1.1
+ _ZnamRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _Znwm@GLIBCXX_3.4 4.1.1
+ _ZnwmRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNSt12__basic_fileIcEC1EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcEC2EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.64bit.cxx11
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.64bit.cxx11
@@ -0,0 +1,329 @@
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEPKcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12find_last_ofEcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEPKcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13find_first_ofEcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEPKcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16find_last_not_ofEcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEPKcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17find_first_not_ofEcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE2atEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4copyEPcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEPKcmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5rfindEcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6substrEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEmmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEmmPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEmmRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7compareEmmRKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_checkEmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_limitEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEixEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEPKwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12find_last_ofEwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEPKwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13find_first_ofEwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16find_last_not_ofEwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17find_first_not_ofEwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4copyEPwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEPKwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4findEwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEPKwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindERKS4_m@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5rfindEwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6substrEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEmmPKw@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEmmPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEmmRKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareEmmRKS4_mm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_checkEmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8_M_limitEmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEixEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE12_M_transformEPcPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE12_M_transformEPwPKwm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES4_S4_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES4_S4_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE24_M_extract_wday_or_monthES4_S4_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_numES4_S4_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE15_M_extract_nameES4_S4_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE24_M_extract_wday_or_monthES4_S4_RiPPKwmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIcEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIcEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIwEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt12ctype_bynameIwEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIcc11__mbstate_tEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIcc11__mbstate_tEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIwc11__mbstate_tEC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt14codecvt_bynameIwc11__mbstate_tEC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1ERKNSt7__cxx1112basic_stringIcS2_SaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2ERKNSt7__cxx1112basic_stringIcS2_SaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1110moneypunctIcLb0EEC1EPSt18__moneypunct_cacheIcLb0EEm@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE6setbufEPcl@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE8_M_pbumpEPcS5_l@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE6setbufEPwl@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE7_M_syncEPwmm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE7seekoffElSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE8_M_pbumpEPwS5_l@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIcEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115messages_bynameIwEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIcEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115numpunct_bynameIwEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1ERKNS_12basic_stringIcS3_SaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2ERKNS_12basic_stringIcS3_SaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1ERKNS_12basic_stringIcS2_IcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2ERKNS_12basic_stringIcS2_IcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb0EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIcLb1EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb0EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC1EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC1ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC2EPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx1117moneypunct_bynameIwLb1EEC2ERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC1EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC2EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIcEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC1EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC2EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx117collateIwEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC2EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIcEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC1EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC2EP15__locale_structPKcm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118messagesIwEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC1EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC1EPSt16__numpunct_cacheIcEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC2EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC2EPSt16__numpunct_cacheIcEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIcEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC1EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC1EPSt16__numpunct_cacheIwEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC2EP15__locale_structm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC2EPSt16__numpunct_cacheIwEm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118numpunctIwEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZSt17__verify_groupingPKcmRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn16_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn16_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn16_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZThn16_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTv0_n24_NSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4.21 5.2
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.alpha
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.alpha
@@ -0,0 +1,56 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.64bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNSt14numeric_limitsInE10has_denormE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE10is_boundedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE10is_integerE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE11round_styleE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12has_infinityE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12max_digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12max_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12min_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE13has_quiet_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE14is_specializedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE14max_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE14min_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE15has_denorm_lossE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE15tinyness_beforeE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE17has_signaling_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE5radixE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE5trapsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE6digitsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE8digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE8is_exactE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE9is_iec559E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE9is_moduloE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE9is_signedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE10has_denormE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE10is_boundedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE10is_integerE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE11round_styleE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12has_infinityE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12max_digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12max_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12min_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE13has_quiet_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE14is_specializedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE14max_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE14min_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE15has_denorm_lossE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE15tinyness_beforeE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE17has_signaling_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE5radixE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE5trapsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE6digitsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE8digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE8is_exactE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE9is_iec559E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE9is_moduloE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE9is_signedE@GLIBCXX_3.4.17 4.8
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.amd64
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.amd64
@@ -0,0 +1,16 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+#(optional)_Z16__VLTRegisterSetPPvPKvmmS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z17__VLTRegisterPairPPvPKvmS2_@CXXABI_1.3.8 4.9.0
+#(optional)_Z21__VLTRegisterSetDebugPPvPKvmmS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z22__VLTRegisterPairDebugPPvPKvmS2_PKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)_Z24__VLTVerifyVtablePointerPPvPKv@CXXABI_1.3.8 4.9.0
+#(optional)_Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)__VLTChangePermission@CXXABI_1.3.8 4.9.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.arm
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.arm
@@ -0,0 +1,6 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+ __gxx_personality_sj0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.arm64
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.arm64
@@ -0,0 +1,10 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.armel
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.armel
@@ -0,0 +1,13 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+ CXXABI_ARM_1.3.3@CXXABI_ARM_1.3.3 4.4.0
+ _ZNKSt9type_info6beforeERKS_@GLIBCXX_3.4 4.3.0
+ _ZNKSt9type_infoeqERKS_@GLIBCXX_3.4 4.3.0
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ __cxa_begin_cleanup@CXXABI_1.3 4.3.0
+ __cxa_end_cleanup@CXXABI_1.3 4.3.0
+ __cxa_type_match@CXXABI_1.3 4.3.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.armhf
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.armhf
@@ -0,0 +1,13 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+ CXXABI_ARM_1.3.3@CXXABI_ARM_1.3.3 4.4.0
+ _ZNKSt9type_info6beforeERKS_@GLIBCXX_3.4 4.3.0
+ _ZNKSt9type_infoeqERKS_@GLIBCXX_3.4 4.3.0
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ __cxa_begin_cleanup@CXXABI_1.3 4.3.0
+ __cxa_end_cleanup@CXXABI_1.3 4.3.0
+ __cxa_type_match@CXXABI_1.3 4.3.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.common
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.common
@@ -0,0 +1,3462 @@
+ CXXABI_1.3.1@CXXABI_1.3.1 4.1.1
+ CXXABI_1.3.2@CXXABI_1.3.2 4.3
+ CXXABI_1.3.3@CXXABI_1.3.3 4.4.0
+ CXXABI_1.3.4@CXXABI_1.3.4 4.5
+ CXXABI_1.3.5@CXXABI_1.3.5 4.6
+ CXXABI_1.3.6@CXXABI_1.3.6 4.7
+ CXXABI_1.3.7@CXXABI_1.3.7 4.8
+ CXXABI_1.3.8@CXXABI_1.3.8 4.9
+ CXXABI_1.3.9@CXXABI_1.3.9 5
+ CXXABI_1.3.10@CXXABI_1.3.10 6
+ CXXABI_1.3@CXXABI_1.3 4.1.1
+ CXXABI_TM_1@CXXABI_TM_1 4.7
+ GLIBCXX_3.4.10@GLIBCXX_3.4.10 4.3
+ GLIBCXX_3.4.11@GLIBCXX_3.4.11 4.4.0
+ GLIBCXX_3.4.12@GLIBCXX_3.4.12 4.4.0
+ GLIBCXX_3.4.13@GLIBCXX_3.4.13 4.4.2
+ GLIBCXX_3.4.14@GLIBCXX_3.4.14 4.5
+ GLIBCXX_3.4.15@GLIBCXX_3.4.15 4.6
+ GLIBCXX_3.4.16@GLIBCXX_3.4.16 4.6.0
+ GLIBCXX_3.4.17@GLIBCXX_3.4.17 4.7
+ GLIBCXX_3.4.18@GLIBCXX_3.4.18 4.8
+ GLIBCXX_3.4.19@GLIBCXX_3.4.19 4.8
+ GLIBCXX_3.4.1@GLIBCXX_3.4.1 4.1.1
+ GLIBCXX_3.4.20@GLIBCXX_3.4.20 4.9
+ GLIBCXX_3.4.21@GLIBCXX_3.4.21 5
+ GLIBCXX_3.4.22@GLIBCXX_3.4.22 6
+ GLIBCXX_3.4.2@GLIBCXX_3.4.2 4.1.1
+ GLIBCXX_3.4.3@GLIBCXX_3.4.3 4.1.1
+ GLIBCXX_3.4.4@GLIBCXX_3.4.4 4.1.1
+ GLIBCXX_3.4.5@GLIBCXX_3.4.5 4.1.1
+ GLIBCXX_3.4.6@GLIBCXX_3.4.6 4.1.1
+ GLIBCXX_3.4.7@GLIBCXX_3.4.7 4.1.1
+ GLIBCXX_3.4.8@GLIBCXX_3.4.8 4.1.1
+ GLIBCXX_3.4.9@GLIBCXX_3.4.9 4.2.1
+ GLIBCXX_3.4@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.common.cxx11"
+(arch=amd64 i386 x32 kfreebsd-amd64 kfreebsd-i386)#include "libstdc++6.symbols.float128"
+(arch=!armel)#include "libstdc++6.symbols.not-armel"
+ (arch=!armel !hurd-i386 !kfreebsd-amd64 !kfreebsd-i386)_ZNSt28__atomic_futex_unsigned_base19_M_futex_notify_allEPj@GLIBCXX_3.4.21 5
+ _ZGTtNKSt11logic_error4whatEv@GLIBCXX_3.4.22 6
+ _ZGTtNKSt13bad_exception4whatEv@CXXABI_1.3.10 6
+ _ZGTtNKSt13bad_exceptionD1Ev@CXXABI_1.3.10 6
+ _ZGTtNKSt13runtime_error4whatEv@GLIBCXX_3.4.22 6
+ _ZGTtNKSt9exception4whatEv@CXXABI_1.3.10 6
+ _ZGTtNKSt9exceptionD1Ev@CXXABI_1.3.10 6
+ _ZGTtNSt11logic_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt11logic_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt11logic_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt11logic_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt11logic_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt11logic_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt11logic_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt11range_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt11range_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt11range_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt11range_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt11range_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt11range_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt11range_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12domain_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt12domain_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt12domain_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt12domain_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt12domain_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12domain_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12domain_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12length_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt12length_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt12length_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt12length_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt12length_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12length_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12length_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12out_of_rangeC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt12out_of_rangeC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt12out_of_rangeC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt12out_of_rangeC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt12out_of_rangeD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12out_of_rangeD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt12out_of_rangeD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt13runtime_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt13runtime_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt13runtime_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt13runtime_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt13runtime_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt13runtime_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt13runtime_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt14overflow_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt14overflow_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt14overflow_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt14overflow_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt14overflow_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt14overflow_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt14overflow_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt15underflow_errorC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt15underflow_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt15underflow_errorC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt15underflow_errorC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt15underflow_errorD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt15underflow_errorD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt15underflow_errorD2Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt16invalid_argumentC1EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt16invalid_argumentC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt16invalid_argumentC2EPKc@GLIBCXX_3.4.22 6
+ (optional=abi_c++11)_ZGTtNSt16invalid_argumentC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.22 6
+ _ZGTtNSt16invalid_argumentD0Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt16invalid_argumentD1Ev@GLIBCXX_3.4.22 6
+ _ZGTtNSt16invalid_argumentD2Ev@GLIBCXX_3.4.22 6
+ _ZGVNSt10moneypunctIcLb0EE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt10moneypunctIcLb1EE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt10moneypunctIwLb0EE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt10moneypunctIwLb1EE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt11__timepunctIcE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt11__timepunctIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt7collateIcE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt7collateIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8messagesIcE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8messagesIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8numpunctIcE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8numpunctIwE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZGVNSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4 4.1.1
+ _ZN10__cxxabiv116__enum_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv116__enum_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv116__enum_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__array_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__array_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__array_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__class_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__class_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__class_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__pbase_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__pbase_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv117__pbase_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv119__pointer_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv119__pointer_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv119__pointer_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv120__function_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv120__function_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv120__function_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv120__si_class_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv120__si_class_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv120__si_class_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv121__vmi_class_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv121__vmi_class_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv121__vmi_class_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv123__fundamental_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv123__fundamental_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv123__fundamental_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv129__pointer_to_member_type_infoD0Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv129__pointer_to_member_type_infoD1Ev@CXXABI_1.3 4.1.1
+ _ZN10__cxxabiv129__pointer_to_member_type_infoD2Ev@CXXABI_1.3 4.1.1
+ _ZN10__gnu_norm15_List_node_base4hookEPS0_@GLIBCXX_3.4 4.1.1
+ _ZN10__gnu_norm15_List_node_base4swapERS0_S1_@GLIBCXX_3.4 4.1.1
+ _ZN10__gnu_norm15_List_node_base6unhookEv@GLIBCXX_3.4 4.1.1
+ _ZN10__gnu_norm15_List_node_base7reverseEv@GLIBCXX_3.4 4.1.1
+ _ZN10__gnu_norm15_List_node_base8transferEPS0_S1_@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug19_Safe_iterator_base12_M_get_mutexEv@GLIBCXX_3.4.9 4.2.1
+ _ZN11__gnu_debug19_Safe_iterator_base16_M_attach_singleEPNS_19_Safe_sequence_baseEb@GLIBCXX_3.4.9 4.2.1
+ _ZN11__gnu_debug19_Safe_iterator_base16_M_detach_singleEv@GLIBCXX_3.4.9 4.2.1
+ _ZN11__gnu_debug19_Safe_iterator_base9_M_attachEPNS_19_Safe_sequence_baseEb@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug19_Safe_iterator_base9_M_detachEv@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug19_Safe_sequence_base12_M_get_mutexEv@GLIBCXX_3.4.9 4.2.1
+ _ZN11__gnu_debug19_Safe_sequence_base13_M_detach_allEv@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug19_Safe_sequence_base18_M_detach_singularEv@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug19_Safe_sequence_base22_M_revalidate_singularEv@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug19_Safe_sequence_base7_M_swapERS0_@GLIBCXX_3.4 4.1.1
+ _ZN11__gnu_debug25_Safe_local_iterator_base9_M_attachEPNS_19_Safe_sequence_baseEb@GLIBCXX_3.4.17 4.7
+ _ZN11__gnu_debug25_Safe_local_iterator_base9_M_detachEv@GLIBCXX_3.4.17 4.7
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+ _ZNKSt13basic_fstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4.5 4.1.1
+ _ZNKSt13basic_fstreamIwSt11char_traitsIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt13basic_fstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt13basic_fstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4.5 4.1.1
+ _ZNKSt13basic_istreamIwSt11char_traitsIwEE6gcountEv@GLIBCXX_3.4 4.1.1
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+ _ZNKSt13runtime_error4whatEv@GLIBCXX_3.4 4.1.1
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+ _ZNKSt14basic_ifstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ifstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4.5 4.1.1
+ _ZNKSt14basic_ifstreamIwSt11char_traitsIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ifstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ifstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4.5 4.1.1
+ _ZNKSt14basic_ofstreamIcSt11char_traitsIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ofstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ofstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4.5 4.1.1
+ _ZNKSt14basic_ofstreamIwSt11char_traitsIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ofstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt14basic_ofstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4.5 4.1.1
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+ _ZNKSt15basic_streambufIcSt11char_traitsIcEE4pptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIcSt11char_traitsIcEE5ebackEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIcSt11char_traitsIcEE5egptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIcSt11char_traitsIcEE5epptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIcSt11char_traitsIcEE5pbaseEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIcSt11char_traitsIcEE6getlocEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE4gptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE4pptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE5ebackEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE5egptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE5epptrEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE5pbaseEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_streambufIwSt11char_traitsIwEE6getlocEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_stringbufIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt15basic_stringbufIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt16bad_array_length4whatEv@CXXABI_1.3.8 4.9
+ _ZNKSt17bad_function_call4whatEv@GLIBCXX_3.4.18 4.8
+ _ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt18basic_stringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt18basic_stringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
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+ _ZNKSt19__codecvt_utf8_baseIDiE16do_always_noconvEv@GLIBCXX_3.4.21 5
+ _ZNKSt19__codecvt_utf8_baseIDiE5do_inER11__mbstate_tPKcS4_RS4_PDiS6_RS6_@GLIBCXX_3.4.21 5
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+ _ZNKSt19basic_istringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_istringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_istringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_istringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
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+ _ZNKSt5ctypeIcE10do_tolowerEc@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIcE10do_toupperEPcPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt5ctypeIcE10do_toupperEc@GLIBCXX_3.4 4.1.1
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+ _ZNKSt8numpunctIcE11do_truenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE12do_falsenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE13decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE13thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE16do_decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE16do_thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE8groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE8truenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIcE9falsenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE11do_groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE11do_truenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE12do_falsenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE13decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE13thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE16do_decimal_pointEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE16do_thousands_sepEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE8groupingEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE8truenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8numpunctIwE9falsenameEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10date_orderEv@GLIBCXX_3.4 4.1.1
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+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11get_weekdayES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE13do_date_orderEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE13get_monthnameES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14do_get_weekdayES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE16do_get_monthnameES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmPKcSC_@GLIBCXX_3.4.21 5
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE21_M_extract_via_formatES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_dateES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_timeES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_yearES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10date_orderEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_dateES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_timeES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_yearES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
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+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE13do_date_orderEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE13get_monthnameES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
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+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE16do_get_monthnameES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE21_M_extract_via_formatES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmPKwSC_@GLIBCXX_3.4.21 5
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_dateES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE8get_timeES3_S3_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4 4.1.1
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+ _ZNKSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_RSt8ios_basecPK2tmPKcSB_@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_RSt8ios_basecPK2tmcc@GLIBCXX_3.4 4.1.1
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+ _ZNKSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewPK2tmcc@GLIBCXX_3.4 4.1.1
+ _ZNKSt9bad_alloc4whatEv@GLIBCXX_3.4.9 4.2.1
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+ _ZNKSt9basic_iosIcSt11char_traitsIcEE3badEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEE3eofEv@GLIBCXX_3.4 4.1.1
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+ _ZNKSt9basic_iosIcSt11char_traitsIcEE4failEv@GLIBCXX_3.4 4.1.1
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+ _ZNKSt9basic_iosIcSt11char_traitsIcEE6narrowEcc@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIcSt11char_traitsIcEE7rdstateEv@GLIBCXX_3.4 4.1.1
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+ _ZNKSt9basic_iosIcSt11char_traitsIcEEcvbEv@GLIBCXX_3.4.21 5
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+ _ZNKSt9basic_iosIwSt11char_traitsIwEE3badEv@GLIBCXX_3.4 4.1.1
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+ _ZNKSt9basic_iosIwSt11char_traitsIwEE4fillEv@GLIBCXX_3.4 4.1.1
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+ _ZNKSt9basic_iosIwSt11char_traitsIwEE5rdbufEv@GLIBCXX_3.4 4.1.1
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+ _ZNKSt9basic_iosIwSt11char_traitsIwEE6narrowEwc@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEE7rdstateEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEEcvPvEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9basic_iosIwSt11char_traitsIwEEcvbEv@GLIBCXX_3.4.21 5
+ _ZNKSt9basic_iosIwSt11char_traitsIwEEntEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9exception4whatEv@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb0EEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10_M_extractILb1EEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb0EEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10_M_extractILb1EEES3_S3_S3_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRSbIwS2_SaIwEE@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES3_S3_bRSt8ios_baseRSt12_Ios_IostateRSbIwS2_SaIwEE@GLIBCXX_3.4 4.1.1
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+ _ZNKSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_bRSt8ios_basecRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES3_bRSt8ios_basece@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES3_bRSt8ios_basecRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES3_bRSt8ios_basece@GLIBCXX_3.4 4.1.1
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+ _ZNKSt9strstream5rdbufEv@GLIBCXX_3.4 4.1.1
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+ _ZNSbIwSt11char_traitsIwESaIwEE13_S_copy_charsEPwPKwS5_@GLIBCXX_3.4 4.1.1
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+ _ZNSbIwSt11char_traitsIwESaIwEE13shrink_to_fitEv@GLIBCXX_3.4.14 4.5
+ _ZNSbIwSt11char_traitsIwESaIwEE3endEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep10_M_destroyERKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep10_M_disposeERKS1_@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep10_M_refcopyEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep10_M_refdataEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep11_S_max_sizeE@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep11_S_terminalE@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep12_S_empty_repEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep13_M_set_leakedEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep15_M_set_sharableEv@GLIBCXX_3.4 4.1.1
+ _ZNSbIwSt11char_traitsIwESaIwEE4_Rep20_S_empty_rep_storageE@GLIBCXX_3.4 4.1.1
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+ _ZNSt13basic_fstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_fstreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
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+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIdEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIeEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIfEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIjEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIlEERS2_RT_@GLIBCXX_3.4.9 4.2.1
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+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractItEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIxEERS2_RT_@GLIBCXX_3.4.9 4.2.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE10_M_extractIyEERS2_RT_@GLIBCXX_3.4.9 4.2.1
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+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getERSt15basic_streambufIwS1_Ew@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getERw@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE3getEv@GLIBCXX_3.4 4.1.1
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+ _ZNSt13basic_istreamIwSt11char_traitsIwEE4swapERS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE4syncEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE5seekgESt4fposI11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE5tellgEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE5ungetEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6ignoreEv@GLIBCXX_3.4.5 4.1.1
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+ _ZNSt13basic_istreamIwSt11char_traitsIwEE6sentryC2ERS2_b@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEE7putbackEw@GLIBCXX_3.4 4.1.1
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+ _ZNSt13basic_istreamIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
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+ _ZNSt13basic_istreamIwSt11char_traitsIwEEC2EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_istreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
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+ _ZNSt13basic_istreamIwSt11char_traitsIwEErsEPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
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+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE5tellpEv@GLIBCXX_3.4 4.1.1
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+ _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertIyEERS2_T_@GLIBCXX_3.4.9 4.2.1
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+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC1EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
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+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
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+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC2EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC2ERSt14basic_iostreamIwS1_E@GLIBCXX_3.4.21 5
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEEaSEOS2_@GLIBCXX_3.4.21 5
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEPFRS2_S3_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEPFRSt8ios_baseS4_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEPFRSt9basic_iosIwS1_ES5_E@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEPKv@GLIBCXX_3.4 4.1.1
+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
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+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEs@GLIBCXX_3.4 4.1.1
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+ _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEy@GLIBCXX_3.4 4.1.1
+ _ZNSt13random_device14_M_init_pretr1ERKSs@GLIBCXX_3.4.18 4.8
+ _ZNSt13random_device16_M_getval_pretr1Ev@GLIBCXX_3.4.18 4.8
+ _ZNSt13random_device7_M_finiEv@GLIBCXX_3.4.18 4.8
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+ _ZNSt13random_device9_M_getvalEv@GLIBCXX_3.4.18 4.8
+ _ZNSt13runtime_errorC1ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt13runtime_errorC2ERKSs@GLIBCXX_3.4 4.1.1
+ _ZNSt13runtime_errorD0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13runtime_errorD1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt13runtime_errorD2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC2EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEE4openERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEE5closeEv@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEE7is_openEv@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC1EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC1ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC2EPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC2ERKSsSt13_Ios_Openmode@GLIBCXX_3.4.13 4.4.2
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ifstreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEC1EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEC1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEC2EPSt15basic_streambufIwS1_E@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEEC2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_iostreamIwSt11char_traitsIwEED2Ev@GLIBCXX_3.4 4.1.1
+ _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
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+ _ZTSSt13basic_filebufIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
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+ _ZTSSt14basic_ofstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
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+ _ZTSSt14codecvt_bynameIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTSSt14collate_bynameIcE@GLIBCXX_3.4 4.1.1
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+ _ZTSSt15basic_stringbufIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15messages_bynameIcE@GLIBCXX_3.4 4.1.1
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+ _ZTSSt15numpunct_bynameIcE@GLIBCXX_3.4 4.1.1
+ _ZTSSt15numpunct_bynameIwE@GLIBCXX_3.4 4.1.1
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+ _ZTSSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
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+ _ZTSSt15underflow_error@GLIBCXX_3.4 4.1.1
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+ _ZTSSt17moneypunct_bynameIcLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTSSt17moneypunct_bynameIcLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTSSt17moneypunct_bynameIwLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTSSt17moneypunct_bynameIwLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTSSt18basic_stringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
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+ _ZTSSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTSSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
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+ _ZTSSt9strstream@GLIBCXX_3.4 4.1.1
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+ _ZTTSt14basic_ofstreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
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+ _ZTTSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
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+ _ZTVSt10moneypunctIcLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt10moneypunctIwLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt10moneypunctIwLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt10ostrstream@GLIBCXX_3.4 4.1.1
+ _ZTVSt11__timepunctIcE@GLIBCXX_3.4 4.1.1
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+ _ZTVSt11logic_error@GLIBCXX_3.4 4.1.1
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+ _ZTVSt13basic_ostreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt13runtime_error@GLIBCXX_3.4 4.1.1
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+ _ZTVSt14basic_iostreamIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
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+ _ZTVSt14codecvt_bynameIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
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+ _ZTVSt14collate_bynameIcE@GLIBCXX_3.4 4.1.1
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+ _ZTVSt14error_category@GLIBCXX_3.4.11 4.4.0
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+ _ZTVSt15basic_stringbufIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
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+ _ZTVSt15messages_bynameIcE@GLIBCXX_3.4 4.1.1
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+ _ZTVSt15numpunct_bynameIcE@GLIBCXX_3.4 4.1.1
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+ _ZTVSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt15underflow_error@GLIBCXX_3.4 4.1.1
+ _ZTVSt16bad_array_length@CXXABI_1.3.8 4.9
+ _ZTVSt16invalid_argument@GLIBCXX_3.4 4.1.1
+ _ZTVSt17bad_function_call@GLIBCXX_3.4.15 4.6
+ _ZTVSt17moneypunct_bynameIcLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt17moneypunct_bynameIcLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt17moneypunct_bynameIwLb0EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt17moneypunct_bynameIwLb1EE@GLIBCXX_3.4 4.1.1
+ _ZTVSt18basic_stringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt18basic_stringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt19__codecvt_utf8_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTVSt19__codecvt_utf8_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTVSt19__codecvt_utf8_baseIwE@GLIBCXX_3.4.21 5
+ _ZTVSt19basic_istringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt19basic_istringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt19basic_ostringstreamIwSt11char_traitsIwESaIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt20__codecvt_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTVSt20__codecvt_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTVSt20__codecvt_utf16_baseIwE@GLIBCXX_3.4.21 5
+ _ZTVSt20bad_array_new_length@CXXABI_1.3.8 4.9
+ _ZTVSt21__ctype_abstract_baseIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt21__ctype_abstract_baseIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt23__codecvt_abstract_baseIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTVSt23__codecvt_abstract_baseIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTVSt25__codecvt_utf8_utf16_baseIDiE@GLIBCXX_3.4.21 5
+ _ZTVSt25__codecvt_utf8_utf16_baseIDsE@GLIBCXX_3.4.21 5
+ _ZTVSt25__codecvt_utf8_utf16_baseIwE@GLIBCXX_3.4.21 5
+ _ZTVSt5ctypeIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt5ctypeIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7codecvtIDic11__mbstate_tE@GLIBCXX_3.4.21 5
+ _ZTVSt7codecvtIDsc11__mbstate_tE@GLIBCXX_3.4.21 5
+ _ZTVSt7codecvtIcc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7codecvtIwc11__mbstate_tE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7collateIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7collateIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8bad_cast@GLIBCXX_3.4 4.1.1
+ _ZTVSt8ios_base@GLIBCXX_3.4 4.1.1
+ _ZTVSt8messagesIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8messagesIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8numpunctIcE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8numpunctIwE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8time_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt8time_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9bad_alloc@GLIBCXX_3.4 4.1.1
+ _ZTVSt9basic_iosIcSt11char_traitsIcEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9basic_iosIwSt11char_traitsIwEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9exception@GLIBCXX_3.4 4.1.1
+ _ZTVSt9money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE@GLIBCXX_3.4 4.1.1
+ _ZTVSt9strstream@GLIBCXX_3.4 4.1.1
+ _ZTVSt9type_info@GLIBCXX_3.4 4.1.1
+ _ZdaPv@GLIBCXX_3.4 4.1.1
+ _ZdaPvRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _ZdlPv@GLIBCXX_3.4 4.1.1
+ _ZdlPvRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ __atomic_flag_for_address@GLIBCXX_3.4.11 4.4.0
+ __atomic_flag_wait_explicit@GLIBCXX_3.4.11 4.4.0
+ __cxa_allocate_dependent_exception@CXXABI_1.3.6 4.7
+ __cxa_allocate_exception@CXXABI_1.3 4.1.1
+ __cxa_bad_cast@CXXABI_1.3 4.1.1
+ __cxa_bad_typeid@CXXABI_1.3 4.1.1
+ __cxa_begin_catch@CXXABI_1.3 4.1.1
+ __cxa_call_unexpected@CXXABI_1.3 4.1.1
+ __cxa_current_exception_type@CXXABI_1.3 4.1.1
+ __cxa_deleted_virtual@CXXABI_1.3.6 4.7
+ __cxa_demangle@CXXABI_1.3 4.1.1
+ __cxa_end_catch@CXXABI_1.3 4.1.1
+ __cxa_free_dependent_exception@CXXABI_1.3.6 4.7
+ __cxa_free_exception@CXXABI_1.3 4.1.1
+ __cxa_get_exception_ptr@CXXABI_1.3.1 4.1.1
+ __cxa_get_globals@CXXABI_1.3 4.1.1
+ __cxa_get_globals_fast@CXXABI_1.3 4.1.1
+ __cxa_guard_abort@CXXABI_1.3 4.1.1
+ __cxa_guard_acquire@CXXABI_1.3 4.1.1
+ __cxa_guard_release@CXXABI_1.3 4.1.1
+ __cxa_pure_virtual@CXXABI_1.3 4.1.1
+ __cxa_rethrow@CXXABI_1.3 4.1.1
+ __cxa_thread_atexit@CXXABI_1.3.7 4.8
+ __cxa_throw@CXXABI_1.3 4.1.1
+ __cxa_throw_bad_array_length@CXXABI_1.3.8 4.9
+ __cxa_throw_bad_array_new_length@CXXABI_1.3.8 4.9
+ __cxa_tm_cleanup@CXXABI_TM_1 4.7
+ __cxa_vec_cctor@CXXABI_1.3 4.1.1
+ __cxa_vec_cleanup@CXXABI_1.3 4.1.1
+ __cxa_vec_ctor@CXXABI_1.3 4.1.1
+ __cxa_vec_delete2@CXXABI_1.3 4.1.1
+ __cxa_vec_delete3@CXXABI_1.3 4.1.1
+ __cxa_vec_delete@CXXABI_1.3 4.1.1
+ __cxa_vec_dtor@CXXABI_1.3 4.1.1
+ __cxa_vec_new2@CXXABI_1.3 4.1.1
+ __cxa_vec_new3@CXXABI_1.3 4.1.1
+ __cxa_vec_new@CXXABI_1.3 4.1.1
+ __dynamic_cast@CXXABI_1.3 4.1.1
+ __once_proxy@GLIBCXX_3.4.11 4.4.0
+ atomic_flag_clear_explicit@GLIBCXX_3.4.11 4.4.0
+ atomic_flag_test_and_set_explicit@GLIBCXX_3.4.11 4.4.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.common.cxx11
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.common.cxx11
@@ -0,0 +1,880 @@
+ (optional=abi_c++11)_ZGVNSt7__cxx1110moneypunctIcLb0EE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx1110moneypunctIcLb1EE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx1110moneypunctIwLb0EE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx1110moneypunctIwLb1EE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx117collateIcE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx117collateIwE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx118messagesIcE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx118messagesIwE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx118numpunctIcE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx118numpunctIwE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZGVNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt3_V214error_category10_M_messageB5cxx11Ei@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt3tr14hashINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEEclES6_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt3tr14hashINSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEEEclES6_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt6locale4nameB5cxx11Ev@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE10neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE10pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE11curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE11do_groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE11frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE13decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE13do_neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE13do_pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE13negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE13positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE13thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE14do_curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE14do_frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE16do_decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE16do_negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE16do_positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE16do_thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb0EE8groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE10neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE10pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE11curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE11do_groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE11frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE13decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE13do_neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE13do_pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE13negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE13positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE13thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE14do_curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE14do_frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE16do_decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE16do_negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE16do_positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE16do_thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIcLb1EE8groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE10neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE10pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE11curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE11do_groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE11frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE13decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE13do_neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE13do_pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE13negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE13positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE13thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE14do_curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE14do_frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE16do_decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE16do_negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE16do_positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE16do_thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb0EE8groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE10neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE10pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE11curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE11do_groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE11frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE13decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE13do_neg_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE13do_pos_formatEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE13negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE13positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE13thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE14do_curr_symbolEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE14do_frac_digitsEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE16do_decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE16do_negative_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE16do_positive_signEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE16do_thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1110moneypunctIwLb1EE8groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_disjunctEPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_M_local_dataEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13get_allocatorEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16_M_get_allocatorEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE3endEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4backEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4cendEv@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5c_strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5crendEv@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6cbeginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6lengthEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6rbeginEv@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7crbeginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8max_sizeEv@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE11_M_is_localEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13_M_local_dataEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE13get_allocatorEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE16_M_get_allocatorEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE3endEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4backEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4cendEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4dataEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4rendEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE4sizeEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5beginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5c_strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5crendEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5emptyEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE5frontEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6cbeginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6lengthEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6rbeginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7_M_dataEv@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7compareERKS4_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE7crbeginEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8capacityEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE8max_sizeEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEE3strEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEE5rdbufEv@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE10do_compareEPKcS3_S3_S3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE12do_transformEPKcS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE4hashEPKcS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE7compareEPKcS3_S3_S3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE7do_hashEPKcS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIcE9transformEPKcS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE10_M_compareEPKwS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE10do_compareEPKwS3_S3_S3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE12do_transformEPKwS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE4hashEPKwS3_@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE7do_hashEPKwS3_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx117collateIwE9transformEPKwS3_@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE20_M_convert_from_charEPc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE3getEiiiRKNS_12basic_stringIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE4openERKNS_12basic_stringIcSt11char_traitsIcESaIcEEERKSt6locale@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE5closeEi@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIcE8do_closeEi@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIwE20_M_convert_from_charEPc@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNKSt7__cxx118messagesIwE5closeEi@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE11do_groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE11do_truenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE12do_falsenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE13decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE13thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE16do_decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE16do_thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE8groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE8truenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIcE9falsenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE11do_groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE11do_truenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE12do_falsenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE13decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE13thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE16do_decimal_pointEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE16do_thousands_sepEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE8groupingEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE8truenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118numpunctIwE9falsenameEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE10date_orderEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11do_get_dateES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11do_get_timeES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11do_get_yearES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE11get_weekdayES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE13do_date_orderEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE13get_monthnameES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14do_get_weekdayES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE16do_get_monthnameES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE21_M_extract_via_formatES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmPKc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmPKcSD_@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tmcc@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_dateES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_timeES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8get_yearES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE10date_orderEv@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_dateES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_timeES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11do_get_yearES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE11get_weekdayES4_S4_RSt8ios_baseRSt12_Ios_IostateP2tm@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZTINSt7__cxx1115messages_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1115messages_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1115numpunct_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1115numpunct_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1117moneypunct_bynameIcLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1117moneypunct_bynameIcLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1117moneypunct_bynameIwLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1117moneypunct_bynameIwLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx117collateIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx117collateIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx118messagesIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx118messagesIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx118numpunctIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx118numpunctIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTINSt8ios_base7failureB5cxx11E@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1110moneypunctIcLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1110moneypunctIcLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1110moneypunctIwLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1110moneypunctIwLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1114collate_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1114collate_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115messages_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115messages_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115numpunct_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115numpunct_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1115time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1117moneypunct_bynameIcLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1117moneypunct_bynameIcLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1117moneypunct_bynameIwLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1117moneypunct_bynameIwLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx117collateIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx117collateIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx118messagesIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx118messagesIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx118numpunctIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx118numpunctIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx118time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTSNSt8ios_base7failureB5cxx11E@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTTNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTTNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTTNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTTNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1110moneypunctIcLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1110moneypunctIcLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1110moneypunctIwLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1110moneypunctIwLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1114collate_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1114collate_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115messages_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115messages_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115numpunct_bynameIcEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115numpunct_bynameIwEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1115time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZTVNSt7__cxx1117moneypunct_bynameIcLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1117moneypunct_bynameIwLb0EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1117moneypunct_bynameIwLb1EEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1118basic_stringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1119basic_istringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1119basic_ostringstreamIcSt11char_traitsIcESaIcEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx1119basic_ostringstreamIwSt11char_traitsIwESaIwEEE@GLIBCXX_3.4.21 5.2
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+ (optional=abi_c++11)_ZTVNSt7__cxx118time_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZTVNSt8ios_base7failureB5cxx11E@GLIBCXX_3.4.21 5.2
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.excprop
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.excprop
@@ -0,0 +1,17 @@
+ _ZNKSt15__exception_ptr13exception_ptr20__cxa_exception_typeEv@CXXABI_1.3.3 4.4.0
+ _ZNKSt15__exception_ptr13exception_ptrcvMS0_FvvEEv@CXXABI_1.3.3 4.4.0
+ _ZNKSt15__exception_ptr13exception_ptrntEv@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptr4swapERS0_@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrC1ERKS0_@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrC1Ev@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrC2EMS0_FvvE@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrC2ERKS0_@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrC2Ev@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrD1Ev@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptrD2Ev@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptr13exception_ptraSERKS0_@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptreqERKNS_13exception_ptrES2_@CXXABI_1.3.3 4.4.0
+ _ZNSt15__exception_ptrneERKNS_13exception_ptrES2_@CXXABI_1.3.3 4.4.0
+ _ZSt17current_exceptionv@CXXABI_1.3.3 4.4.0
+ _ZSt17rethrow_exceptionNSt15__exception_ptr13exception_ptrE@CXXABI_1.3.3 4.4.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.float128
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.float128
@@ -0,0 +1,7 @@
+ CXXABI_FLOAT128@CXXABI_FLOAT128 5
+ _ZTIPKg@CXXABI_FLOAT128 5
+ _ZTIPg@CXXABI_FLOAT128 5
+ _ZTIg@CXXABI_FLOAT128 5
+ _ZTSPKg@CXXABI_FLOAT128 5
+ _ZTSPg@CXXABI_FLOAT128 5
+ _ZTSg@CXXABI_FLOAT128 5
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.glibcxxmath
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.glibcxxmath
@@ -0,0 +1,22 @@
+ acosl@GLIBCXX_3.4.3 4.1.1
+ asinl@GLIBCXX_3.4.3 4.1.1
+ atan2l@GLIBCXX_3.4 4.1.1
+ atanl@GLIBCXX_3.4.3 4.1.1
+ ceill@GLIBCXX_3.4.3 4.1.1
+ coshl@GLIBCXX_3.4 4.1.1
+ cosl@GLIBCXX_3.4 4.1.1
+ expl@GLIBCXX_3.4 4.1.1
+ floorl@GLIBCXX_3.4.3 4.1.1
+ fmodl@GLIBCXX_3.4.3 4.1.1
+ frexpl@GLIBCXX_3.4.3 4.1.1
+ hypotl@GLIBCXX_3.4 4.1.1
+ ldexpl@GLIBCXX_3.4.3 4.1.1
+ log10l@GLIBCXX_3.4 4.1.1
+ logl@GLIBCXX_3.4 4.1.1
+ modfl@GLIBCXX_3.4.3 4.1.1
+ powl@GLIBCXX_3.4 4.1.1
+ sinhl@GLIBCXX_3.4 4.1.1
+ sinl@GLIBCXX_3.4 4.1.1
+ sqrtl@GLIBCXX_3.4 4.1.1
+ tanhl@GLIBCXX_3.4 4.1.1
+ tanl@GLIBCXX_3.4 4.1.1
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.hppa
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.hppa
@@ -0,0 +1,9 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.excprop"
+# removed, see PR libstdc++/39491 __signbitl@GLIBCXX_3.4 4.2.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.hurd-i386
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.hurd-i386
@@ -0,0 +1,6 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit.hurd"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.i386
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.i386
@@ -0,0 +1,14 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+#(optional)_Z16__VLTRegisterSetPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z17__VLTRegisterPairPPvPKvjS2_@CXXABI_1.3.8 4.9.0
+#(optional)_Z21__VLTRegisterSetDebugPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z22__VLTRegisterPairDebugPPvPKvjS2_PKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)_Z24__VLTVerifyVtablePointerPPvPKv@CXXABI_1.3.8 4.9.0
+#(optional)_Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)__VLTChangePermission@CXXABI_1.3.8 4.9.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.ia64
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.ia64
@@ -0,0 +1,53 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNSt14numeric_limitsInE10has_denormE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE10is_boundedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE10is_integerE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE11round_styleE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12has_infinityE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12max_digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12max_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE12min_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE13has_quiet_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE14is_specializedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE14max_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE14min_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE15has_denorm_lossE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE15tinyness_beforeE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE17has_signaling_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE5radixE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE5trapsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE6digitsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE8digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE8is_exactE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE9is_iec559E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE9is_moduloE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsInE9is_signedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE10has_denormE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE10is_boundedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE10is_integerE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE11round_styleE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12has_infinityE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12max_digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12max_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE12min_exponentE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE13has_quiet_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE14is_specializedE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE14max_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE14min_exponent10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE15has_denorm_lossE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE15tinyness_beforeE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE17has_signaling_NaNE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE5radixE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE5trapsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE6digitsE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE8digits10E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE8is_exactE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE9is_iec559E@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE9is_moduloE@GLIBCXX_3.4.17 4.8
+ _ZNSt14numeric_limitsIoE9is_signedE@GLIBCXX_3.4.17 4.8
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.kfreebsd-amd64
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.kfreebsd-amd64
@@ -0,0 +1,9 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.kfreebsd-i386
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.kfreebsd-i386
@@ -0,0 +1,7 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.ldbl.32bit
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.ldbl.32bit
@@ -0,0 +1,284 @@
+ CXXABI_LDBL_1.3@CXXABI_LDBL_1.3 4.2.1
+ GLIBCXX_LDBL_3.4.10@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ GLIBCXX_LDBL_3.4.7@GLIBCXX_LDBL_3.4.7 4.2.1
+ GLIBCXX_LDBL_3.4@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt3tr14hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ _ZGVNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIjEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIlEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intImEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intItEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIxEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIyEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE16_M_extract_floatES4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRj@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRl@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRm@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRt@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRx@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRy@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE8__do_getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIjEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIlEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intImEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intItEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIxEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE14_M_extract_intIyEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE16_M_extract_floatES4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRb@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRd@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRf@GLIBCXX_LDBL_3.4 4.2.1
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--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.ldbl.32bit.s390
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.ldbl.32bit.s390
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+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
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+ _ZStlsIgwSt11char_traitsIwEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStrsIgcSt11char_traitsIcEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStrsIgwSt11char_traitsIwEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
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+ _ZTINSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTIPKg@CXXABI_LDBL_1.3 4.2.1
+ _ZTIPg@CXXABI_LDBL_1.3 4.2.1
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+ _ZTSNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSPKg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSPg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSg@CXXABI_LDBL_1.3 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.ldbl.64bit
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.ldbl.64bit
@@ -0,0 +1,284 @@
+ CXXABI_LDBL_1.3@CXXABI_LDBL_1.3 4.2.1
+ GLIBCXX_LDBL_3.4.10@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ GLIBCXX_LDBL_3.4.7@GLIBCXX_LDBL_3.4.7 4.2.1
+ GLIBCXX_LDBL_3.4@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt3tr14hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIgEclEg@GLIBCXX_LDBL_3.4.10 4.3.0~rc2
+ _ZGVNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZGVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
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+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIlEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intImEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
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+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_intIyEES4_S4_S4_RSt8ios_baseRSt12_Ios_IostateRT_@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE16_M_extract_floatES4_S4_RSt8ios_baseRSt12_Ios_IostateRSs@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNKSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_RSt8ios_baseRSt12_Ios_IostateRPv@GLIBCXX_LDBL_3.4 4.2.1
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+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE2idE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2Em@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED0Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED1Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEED2Ev@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt14__convert_to_vIgEvPKcRT_RSt12_Ios_IostateRKP15__locale_struct@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9has_facetINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEEbRKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZSt9use_facetINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEEERKT_RKSt6locale@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStlsIgcSt11char_traitsIcEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStlsIgwSt11char_traitsIwEERSt13basic_ostreamIT0_T1_ES6_RKSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStrsIgcSt11char_traitsIcEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZStrsIgwSt11char_traitsIwEERSt13basic_istreamIT0_T1_ES6_RSt7complexIT_E@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTINSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTIPKg@CXXABI_LDBL_1.3 4.2.1
+ _ZTIPg@CXXABI_LDBL_1.3 4.2.1
+ _ZTIg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTSPKg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSPg@CXXABI_LDBL_1.3 4.2.1
+ _ZTSg@CXXABI_LDBL_1.3 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1287num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEE@GLIBCXX_LDBL_3.4 4.2.1
+ _ZTVNSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEE@GLIBCXX_LDBL_3.4 4.2.1
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.m68k
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.m68k
@@ -0,0 +1,6 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.mips
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.mips
@@ -0,0 +1,7 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.glibcxxmath"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.mips64
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.mips64
@@ -0,0 +1,7 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.mips64el
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.mips64el
@@ -0,0 +1,10 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.9.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.9.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.mips64r6
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.mips64r6
@@ -0,0 +1,7 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.mips64r6el
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.mips64r6el
@@ -0,0 +1,10 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.9
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.9
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.mipsel
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.mipsel
@@ -0,0 +1,8 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.mipsr6
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.mipsr6
@@ -0,0 +1,7 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+ __gxx_personality_v0@CXXABI_1.3 4.1
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.glibcxxmath"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.mipsr6el
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.mipsr6el
@@ -0,0 +1,8 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+ __gxx_personality_v0@CXXABI_1.3 4.1
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.money.f128
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.money.f128
@@ -0,0 +1,10 @@
+  GLIBCXX_LDBL_3.4.21@GLIBCXX_LDBL_3.4.21 5
+# cxx11 symbols only
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_bRSt8ios_basecg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_bRSt8ios_basecg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_bRSt8ios_basewg@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_bRSt8ios_basewg@GLIBCXX_3.4.21 5.2
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.money.ldbl
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.money.ldbl
@@ -0,0 +1,9 @@
+# cxx11 symbols only
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE3getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_getIwSt19istreambuf_iteratorIwSt11char_traitsIwEEE6do_getES4_S4_bRSt8ios_baseRSt12_Ios_IostateRe@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE3putES4_bRSt8ios_basece@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6do_putES4_bRSt8ios_basece@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE3putES4_bRSt8ios_basewe@GLIBCXX_3.4.21 5.2
+ (optional=abi_c++11)_ZNKSt7__cxx119money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES4_bRSt8ios_basewe@GLIBCXX_3.4.21 5.2
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.not-armel
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.not-armel
@@ -0,0 +1,24 @@
+ _ZNSt13__future_base11_State_baseD0Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base11_State_baseD1Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base11_State_baseD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base12_Result_baseC1Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base12_Result_baseC2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base12_Result_baseD0Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base12_Result_baseD1Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base12_Result_baseD2Ev@GLIBCXX_3.4.15 4.6
+ _ZNSt13__future_base13_State_baseV211_Make_ready6_M_setEv@GLIBCXX_3.4.21 5
+ _ZNSt13__future_base19_Async_state_commonD0Ev@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZNSt13__future_base19_Async_state_commonD1Ev@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZNSt13__future_base19_Async_state_commonD2Ev@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZNSt16nested_exceptionD0Ev@CXXABI_1.3.5 4.6
+ _ZNSt16nested_exceptionD1Ev@CXXABI_1.3.5 4.6
+ _ZNSt16nested_exceptionD2Ev@CXXABI_1.3.5 4.6
+ _ZTINSt13__future_base11_State_baseE@GLIBCXX_3.4.15 4.6
+ _ZTINSt13__future_base12_Result_baseE@GLIBCXX_3.4.15 4.6
+ _ZTINSt13__future_base19_Async_state_commonE@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZTISt16nested_exception@CXXABI_1.3.5 4.6
+ _ZTSNSt13__future_base19_Async_state_commonE@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZTVNSt13__future_base11_State_baseE@GLIBCXX_3.4.15 4.6
+ _ZTVNSt13__future_base12_Result_baseE@GLIBCXX_3.4.15 4.6
+ _ZTVNSt13__future_base19_Async_state_commonE@GLIBCXX_3.4.17 4.7.0~rc1
+ _ZTVSt16nested_exception@CXXABI_1.3.5 4.6
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.powerpc
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.powerpc
@@ -0,0 +1,9 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.powerpcspe
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.powerpcspe
@@ -0,0 +1,8 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.ppc64
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.ppc64
@@ -0,0 +1,11 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.64bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.ppc64el
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.ppc64el
@@ -0,0 +1,11 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.64bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.s390
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.s390
@@ -0,0 +1,558 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.common"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base16_M_get_free_listEm@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx17__pool_alloc_base9_M_refillEm@GLIBCXX_3.4.2 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb0EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reclaim_blockEPcm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx6__poolILb1EE16_M_reserve_blockEmm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx9free_list6_M_getEm@GLIBCXX_3.4.4 4.1.1
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsgetnEPci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE6xsputnEPKci@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIcSt11char_traitsIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsgetnEPwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE6xsputnEPKwi@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZN9__gnu_cxx18stdio_sync_filebufIwSt11char_traitsIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNK10__cxxabiv117__class_type_info12__do_dyncastEiNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv117__class_type_info20__do_find_public_srcEiPKvPKS0_S2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info12__do_dyncastEiNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE@CXXABI_1.3 4.1.1
+ _ZNK10__cxxabiv121__vmi_class_type_info20__do_find_public_srcEiPKvPKNS_17__class_type_infoES2_@CXXABI_1.3 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE12find_last_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE13find_first_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE15_M_check_lengthEmmPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE16find_last_not_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE17find_first_not_ofEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE2atEm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4copyEPwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE4findEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEPKwmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindERKS2_m@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE5rfindEwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE6substrEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKw@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmRKS2_@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE7compareEmmRKS2_mm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_checkEmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEE8_M_limitEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSbIwSt11char_traitsIwESaIwEEixEm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs12find_last_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs13find_first_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs15_M_check_lengthEmmPKc@GLIBCXX_3.4.5 4.1.1
+ _ZNKSs16find_last_not_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs16find_last_not_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs17find_first_not_ofEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs2atEm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4copyEPcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs4findEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEPKcmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindERKSsm@GLIBCXX_3.4 4.1.1
+ _ZNKSs5rfindEcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs6substrEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmRKSs@GLIBCXX_3.4 4.1.1
+ _ZNKSs7compareEmmRKSsmm@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_checkEmPKc@GLIBCXX_3.4 4.1.1
+ _ZNKSs8_M_limitEmm@GLIBCXX_3.4 4.1.1
+ _ZNKSsixEm@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIcE6_M_putEPcmPKcPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt11__timepunctIwE6_M_putEPwmPKwPK2tm@GLIBCXX_3.4 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt7codecvtIcc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1
+ _ZNKSt7codecvtIwc11__mbstate_tE9do_lengthERS0_PKcS4_m@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIcE12_M_transformEPcPKcm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7collateIwE12_M_transformEPwPKwm@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE12_M_group_intEPKcmcRSt8ios_basePcS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE14_M_group_floatEPKcmcS6_PcS7_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE6_M_padEciRSt8ios_basePcPKcRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE12_M_group_intEPKcmwRSt8ios_basePwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE14_M_group_floatEPKcmwPKwPwS9_Ri@GLIBCXX_3.4 4.1.1
+ _ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6_M_padEwiRSt8ios_basePwPKwRi@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE14_M_extract_numES3_S3_RiiimRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
+ _ZNKSt8time_getIcSt19istreambuf_iteratorIcSt11char_traitsIcEEE15_M_extract_nameES3_S3_RiPPKcmRSt8ios_baseRSt12_Ios_Iostate@GLIBCXX_3.4 4.1.1
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+ _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
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+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE7seekoffExSt12_Ios_SeekdirSt13_Ios_Openmode@GLIBCXX_3.4 4.1.1
+ _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEE8_M_pbumpEPwS4_x@GLIBCXX_3.4.16 4.7
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+ _ZNSt15numpunct_bynameIwEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIcSt19istreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_get_bynameIwSt19istreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcm@GLIBCXX_3.4 4.1.1
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+ _ZNSt15time_put_bynameIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEEC2EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC1EPKcm@GLIBCXX_3.4 4.1.1
+ _ZNSt15time_put_bynameIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEEC2EPKcm@GLIBCXX_3.4 4.1.1
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+ _ZNSt17moneypunct_bynameIcLb0EEC1EPKcm@GLIBCXX_3.4 4.1.1
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+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_istreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt13basic_ostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ifstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_iostreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt14basic_ofstreamIwSt11char_traitsIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt18basic_stringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_istringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIcSt11char_traitsIcESaIcEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt19basic_ostringstreamIwSt11char_traitsIwESaIwEED1Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD0Ev@GLIBCXX_3.4 4.1.1
+ _ZTv0_n12_NSt9strstreamD1Ev@GLIBCXX_3.4 4.1.1
+ _Znam@GLIBCXX_3.4 4.1.1
+ _ZnamRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ _Znwm@GLIBCXX_3.4 4.1.1
+ _ZnwmRKSt9nothrow_t@GLIBCXX_3.4 4.1.1
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit.s390"
+ _ZNSt12__basic_fileIcEC1EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
+ _ZNSt12__basic_fileIcEC2EP15pthread_mutex_t@GLIBCXX_3.4 4.1.1
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.s390x
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.s390x
@@ -0,0 +1,13 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+ _ZN9__gnu_cxx12__atomic_addEPVii@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVii@GLIBCXX_3.4 4.1.1
+#DEPRECATED: 4.2.2-4# ldexpf@GLIBCXX_3.4.3 4.1.1
+#DEPRECATED: 4.2.2-4# powf@GLIBCXX_3.4 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.64bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.sh4
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.sh4
@@ -0,0 +1,8 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.sparc
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.sparc
@@ -0,0 +1,9 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.excprop"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+#include "libstdc++6.symbols.glibcxxmath"
+#include "libstdc++6.symbols.ldbl.32bit"
+#include "libstdc++6.symbols.money.f128"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3.0~rc2
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.sparc64
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.sparc64
@@ -0,0 +1,11 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.64bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.money.ldbl"
+ _ZN9__gnu_cxx12__atomic_addEPVli@GLIBCXX_3.4 4.1.1
+ _ZN9__gnu_cxx18__exchange_and_addEPVli@GLIBCXX_3.4 4.1.1
+# FIXME: Currently no ldbl symbols in the 64bit libstdc++ on sparc.
+# #include "libstdc++6.symbols.ldbl.64bit"
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
--- gcc-6-6.4.0.orig/debian/libstdc++6.symbols.x32
+++ gcc-6-6.4.0/debian/libstdc++6.symbols.x32
@@ -0,0 +1,27 @@
+libstdc++.so.6 libstdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+#(optional)_Z16__VLTRegisterSetPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z17__VLTRegisterPairPPvPKvjS2_@CXXABI_1.3.8 4.9.0
+#(optional)_Z21__VLTRegisterSetDebugPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z22__VLTRegisterPairDebugPPvPKvjS2_PKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)_Z24__VLTVerifyVtablePointerPPvPKv@CXXABI_1.3.8 4.9.0
+#(optional)_Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)__VLTChangePermission@CXXABI_1.3.8 4.9.0
+ _ZTIPKn@CXXABI_1.3.5 4.9.0
+ _ZTIPKo@CXXABI_1.3.5 4.9.0
+ _ZTIPn@CXXABI_1.3.5 4.9.0
+ _ZTIPo@CXXABI_1.3.5 4.9.0
+ _ZTIn@CXXABI_1.3.5 4.9.0
+ _ZTIo@CXXABI_1.3.5 4.9.0
+ _ZTSPKn@CXXABI_1.3.9 4.9.0
+ _ZTSPKo@CXXABI_1.3.9 4.9.0
+ _ZTSPn@CXXABI_1.3.9 4.9.0
+ _ZTSPo@CXXABI_1.3.9 4.9.0
+ _ZTSn@CXXABI_1.3.9 4.9.0
+ _ZTSo@CXXABI_1.3.9 4.9.0
--- gcc-6-6.4.0.orig/debian/libstdc++CXX.postinst
+++ gcc-6-6.4.0/debian/libstdc++CXX.postinst
@@ -0,0 +1,18 @@
+#! /bin/sh -e
+
+case "$1" in
+    configure)
+	docdir=/usr/share/doc/libstdc++@CXX@
+	if [ -d $docdir ] && [ ! -h $docdir ]; then
+	    rm -rf $docdir
+	    ln -s gcc-@BV@-base $docdir
+	fi
+
+	if [ -n "$2" ] && [ -d /usr/share/gcc-4.9 ] && dpkg --compare-versions "$2" lt 5.1.1-10; then
+	    find /usr/share/gcc-4.9/python -name __pycache__ -type d -print0 | xargs -r0 rm -rf
+	    find /usr/share/gcc-4.9/python -name '*.py[co]' -type f -print0 | xargs -r0 rm -f
+	    find /usr/share/gcc-4.9 -empty -delete 2>/dev/null || true
+	fi
+esac
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/libstdc++CXX.prerm
+++ gcc-6-6.4.0/debian/libstdc++CXX.prerm
@@ -0,0 +1,13 @@
+#! /bin/sh
+
+set -e
+
+case "$1" in
+    remove|upgrade)
+	files=$(dpkg -L libstdc++@CXX@@TARGET_QUAL@ | awk -F/ 'BEGIN {OFS="/"} /\.py$/ {$NF=sprintf("__pycache__/%s.*.py[co]", substr($NF,1,length($NF)-3)); print}')
+	rm -f $files
+	dirs=$(dpkg -L libstdc++@CXX@@TARGET_QUAL@ | awk -F/ 'BEGIN {OFS="/"} /\.py$/ {NF--; print}' | sort -u)
+	find $dirs -mindepth 1 -maxdepth 1 -name __pycache__ -type d -empty | xargs -r rmdir
+esac
+
+#DEBHELPER#
--- gcc-6-6.4.0.orig/debian/libtsan0.symbols
+++ gcc-6-6.4.0/debian/libtsan0.symbols
@@ -0,0 +1,1758 @@
+libtsan.so.0 libtsan0 #MINVER#
+ AnnotateBenignRace@Base 4.9
+ AnnotateBenignRaceSized@Base 4.9
+ AnnotateCondVarSignal@Base 4.9
+ AnnotateCondVarSignalAll@Base 4.9
+ AnnotateCondVarWait@Base 4.9
+ AnnotateEnableRaceDetection@Base 4.9
+ AnnotateExpectRace@Base 4.9
+ AnnotateFlushExpectedRaces@Base 4.9
+ AnnotateFlushState@Base 4.9
+ AnnotateHappensAfter@Base 4.9
+ AnnotateHappensBefore@Base 4.9
+ AnnotateIgnoreReadsBegin@Base 4.9
+ AnnotateIgnoreReadsEnd@Base 4.9
+ AnnotateIgnoreSyncBegin@Base 4.9
+ AnnotateIgnoreSyncEnd@Base 4.9
+ AnnotateIgnoreWritesBegin@Base 4.9
+ AnnotateIgnoreWritesEnd@Base 4.9
+ AnnotateMemoryIsInitialized@Base 4.9
+ AnnotateMemoryIsUninitialized@Base 5
+ AnnotateMutexIsNotPHB@Base 4.9
+ AnnotateMutexIsUsedAsCondVar@Base 4.9
+ AnnotateNewMemory@Base 4.9
+ AnnotateNoOp@Base 4.9
+ AnnotatePCQCreate@Base 4.9
+ AnnotatePCQDestroy@Base 4.9
+ AnnotatePCQGet@Base 4.9
+ AnnotatePCQPut@Base 4.9
+ AnnotatePublishMemoryRange@Base 4.9
+ AnnotateRWLockAcquired@Base 4.9
+ AnnotateRWLockCreate@Base 4.9
+ AnnotateRWLockCreateStatic@Base 4.9
+ AnnotateRWLockDestroy@Base 4.9
+ AnnotateRWLockReleased@Base 4.9
+ AnnotateThreadName@Base 4.9
+ AnnotateTraceMemory@Base 4.9
+ AnnotateUnpublishMemoryRange@Base 4.9
+ RunningOnValgrind@Base 4.9
+ ThreadSanitizerQuery@Base 4.9
+ ValgrindSlowdown@Base 4.9
+ WTFAnnotateBenignRaceSized@Base 4.9
+ WTFAnnotateHappensAfter@Base 4.9
+ WTFAnnotateHappensBefore@Base 4.9
+ _ZN11__sanitizer11CheckFailedEPKciS1_yy@Base 4.9
+ _ZN11__sanitizer7OnPrintEPKc@Base 4.9
+ _ZN6__tsan10OnFinalizeEb@Base 4.9
+ _ZN6__tsan12OnInitializeEv@Base 5
+ _ZN6__tsan8OnReportEPKNS_10ReportDescEb@Base 4.9
+ _ZdaPv@Base 4.9
+ _ZdaPvRKSt9nothrow_t@Base 4.9
+ _ZdlPv@Base 4.9
+ _ZdlPvRKSt9nothrow_t@Base 4.9
+ _Znam@Base 4.9
+ _ZnamRKSt9nothrow_t@Base 4.9
+ _Znwm@Base 4.9
+ _ZnwmRKSt9nothrow_t@Base 4.9
+ __asan_backtrace_alloc@Base 4.9
+ __asan_backtrace_close@Base 4.9
+ __asan_backtrace_create_state@Base 4.9
+ __asan_backtrace_dwarf_add@Base 4.9
+ __asan_backtrace_free@Base 4.9
+ __asan_backtrace_get_view@Base 4.9
+ __asan_backtrace_initialize@Base 4.9
+ __asan_backtrace_open@Base 4.9
+ __asan_backtrace_pcinfo@Base 4.9
+ __asan_backtrace_qsort@Base 4.9
+ __asan_backtrace_release_view@Base 4.9
+ __asan_backtrace_syminfo@Base 4.9
+ __asan_backtrace_vector_finish@Base 4.9
+ __asan_backtrace_vector_grow@Base 4.9
+ __asan_backtrace_vector_release@Base 4.9
+ __asan_cplus_demangle_builtin_types@Base 4.9
+ __asan_cplus_demangle_fill_ctor@Base 4.9
+ __asan_cplus_demangle_fill_dtor@Base 4.9
+ __asan_cplus_demangle_fill_extended_operator@Base 4.9
+ __asan_cplus_demangle_fill_name@Base 4.9
+ __asan_cplus_demangle_init_info@Base 4.9
+ __asan_cplus_demangle_mangled_name@Base 4.9
+ __asan_cplus_demangle_operators@Base 4.9
+ __asan_cplus_demangle_print@Base 4.9
+ __asan_cplus_demangle_print_callback@Base 4.9
+ __asan_cplus_demangle_type@Base 4.9
+ __asan_cplus_demangle_v3@Base 4.9
+ __asan_cplus_demangle_v3_callback@Base 4.9
+ __asan_internal_memcmp@Base 4.9
+ __asan_internal_memcpy@Base 4.9
+ __asan_internal_memset@Base 4.9
+ __asan_internal_strcmp@Base 4.9
+ __asan_internal_strlen@Base 4.9
+ __asan_internal_strncmp@Base 4.9
+ __asan_internal_strnlen@Base 4.9
+ __asan_is_gnu_v3_mangled_ctor@Base 4.9
+ __asan_is_gnu_v3_mangled_dtor@Base 4.9
+ __asan_java_demangle_v3@Base 4.9
+ __asan_java_demangle_v3_callback@Base 4.9
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+ __sanitizer_syscall_post_impl_mprotect@Base 4.9
+ __sanitizer_syscall_post_impl_mq_getsetattr@Base 4.9
+ __sanitizer_syscall_post_impl_mq_notify@Base 4.9
+ __sanitizer_syscall_post_impl_mq_open@Base 4.9
+ __sanitizer_syscall_post_impl_mq_timedreceive@Base 4.9
+ __sanitizer_syscall_post_impl_mq_timedsend@Base 4.9
+ __sanitizer_syscall_post_impl_mq_unlink@Base 4.9
+ __sanitizer_syscall_post_impl_mremap@Base 4.9
+ __sanitizer_syscall_post_impl_msgctl@Base 4.9
+ __sanitizer_syscall_post_impl_msgget@Base 4.9
+ __sanitizer_syscall_post_impl_msgrcv@Base 4.9
+ __sanitizer_syscall_post_impl_msgsnd@Base 4.9
+ __sanitizer_syscall_post_impl_msync@Base 4.9
+ __sanitizer_syscall_post_impl_munlock@Base 4.9
+ __sanitizer_syscall_post_impl_munlockall@Base 4.9
+ __sanitizer_syscall_post_impl_munmap@Base 4.9
+ __sanitizer_syscall_post_impl_name_to_handle_at@Base 4.9
+ __sanitizer_syscall_post_impl_nanosleep@Base 4.9
+ __sanitizer_syscall_post_impl_newfstat@Base 4.9
+ __sanitizer_syscall_post_impl_newfstatat@Base 4.9
+ __sanitizer_syscall_post_impl_newlstat@Base 4.9
+ __sanitizer_syscall_post_impl_newstat@Base 4.9
+ __sanitizer_syscall_post_impl_newuname@Base 4.9
+ __sanitizer_syscall_post_impl_ni_syscall@Base 4.9
+ __sanitizer_syscall_post_impl_nice@Base 4.9
+ __sanitizer_syscall_post_impl_old_getrlimit@Base 4.9
+ __sanitizer_syscall_post_impl_old_mmap@Base 4.9
+ __sanitizer_syscall_post_impl_old_readdir@Base 4.9
+ __sanitizer_syscall_post_impl_old_select@Base 4.9
+ __sanitizer_syscall_post_impl_oldumount@Base 4.9
+ __sanitizer_syscall_post_impl_olduname@Base 4.9
+ __sanitizer_syscall_post_impl_open@Base 4.9
+ __sanitizer_syscall_post_impl_open_by_handle_at@Base 4.9
+ __sanitizer_syscall_post_impl_openat@Base 4.9
+ __sanitizer_syscall_post_impl_pause@Base 4.9
+ __sanitizer_syscall_post_impl_pciconfig_iobase@Base 4.9
+ __sanitizer_syscall_post_impl_pciconfig_read@Base 4.9
+ __sanitizer_syscall_post_impl_pciconfig_write@Base 4.9
+ __sanitizer_syscall_post_impl_perf_event_open@Base 4.9
+ __sanitizer_syscall_post_impl_personality@Base 4.9
+ __sanitizer_syscall_post_impl_pipe2@Base 4.9
+ __sanitizer_syscall_post_impl_pipe@Base 4.9
+ __sanitizer_syscall_post_impl_pivot_root@Base 4.9
+ __sanitizer_syscall_post_impl_poll@Base 4.9
+ __sanitizer_syscall_post_impl_ppoll@Base 4.9
+ __sanitizer_syscall_post_impl_pread64@Base 4.9
+ __sanitizer_syscall_post_impl_preadv@Base 4.9
+ __sanitizer_syscall_post_impl_prlimit64@Base 4.9
+ __sanitizer_syscall_post_impl_process_vm_readv@Base 4.9
+ __sanitizer_syscall_post_impl_process_vm_writev@Base 4.9
+ __sanitizer_syscall_post_impl_pselect6@Base 4.9
+ __sanitizer_syscall_post_impl_ptrace@Base 4.9
+ __sanitizer_syscall_post_impl_pwrite64@Base 4.9
+ __sanitizer_syscall_post_impl_pwritev@Base 4.9
+ __sanitizer_syscall_post_impl_quotactl@Base 4.9
+ __sanitizer_syscall_post_impl_read@Base 4.9
+ __sanitizer_syscall_post_impl_readlink@Base 4.9
+ __sanitizer_syscall_post_impl_readlinkat@Base 4.9
+ __sanitizer_syscall_post_impl_readv@Base 4.9
+ __sanitizer_syscall_post_impl_reboot@Base 4.9
+ __sanitizer_syscall_post_impl_recv@Base 4.9
+ __sanitizer_syscall_post_impl_recvfrom@Base 4.9
+ __sanitizer_syscall_post_impl_recvmmsg@Base 4.9
+ __sanitizer_syscall_post_impl_recvmsg@Base 4.9
+ __sanitizer_syscall_post_impl_remap_file_pages@Base 4.9
+ __sanitizer_syscall_post_impl_removexattr@Base 4.9
+ __sanitizer_syscall_post_impl_rename@Base 4.9
+ __sanitizer_syscall_post_impl_renameat@Base 4.9
+ __sanitizer_syscall_post_impl_request_key@Base 4.9
+ __sanitizer_syscall_post_impl_restart_syscall@Base 4.9
+ __sanitizer_syscall_post_impl_rmdir@Base 4.9
+ __sanitizer_syscall_post_impl_rt_sigpending@Base 4.9
+ __sanitizer_syscall_post_impl_rt_sigprocmask@Base 4.9
+ __sanitizer_syscall_post_impl_rt_sigqueueinfo@Base 4.9
+ __sanitizer_syscall_post_impl_rt_sigtimedwait@Base 4.9
+ __sanitizer_syscall_post_impl_rt_tgsigqueueinfo@Base 4.9
+ __sanitizer_syscall_post_impl_sched_get_priority_max@Base 4.9
+ __sanitizer_syscall_post_impl_sched_get_priority_min@Base 4.9
+ __sanitizer_syscall_post_impl_sched_getaffinity@Base 4.9
+ __sanitizer_syscall_post_impl_sched_getparam@Base 4.9
+ __sanitizer_syscall_post_impl_sched_getscheduler@Base 4.9
+ __sanitizer_syscall_post_impl_sched_rr_get_interval@Base 4.9
+ __sanitizer_syscall_post_impl_sched_setaffinity@Base 4.9
+ __sanitizer_syscall_post_impl_sched_setparam@Base 4.9
+ __sanitizer_syscall_post_impl_sched_setscheduler@Base 4.9
+ __sanitizer_syscall_post_impl_sched_yield@Base 4.9
+ __sanitizer_syscall_post_impl_select@Base 4.9
+ __sanitizer_syscall_post_impl_semctl@Base 4.9
+ __sanitizer_syscall_post_impl_semget@Base 4.9
+ __sanitizer_syscall_post_impl_semop@Base 4.9
+ __sanitizer_syscall_post_impl_semtimedop@Base 4.9
+ __sanitizer_syscall_post_impl_send@Base 4.9
+ __sanitizer_syscall_post_impl_sendfile64@Base 4.9
+ __sanitizer_syscall_post_impl_sendfile@Base 4.9
+ __sanitizer_syscall_post_impl_sendmmsg@Base 4.9
+ __sanitizer_syscall_post_impl_sendmsg@Base 4.9
+ __sanitizer_syscall_post_impl_sendto@Base 4.9
+ __sanitizer_syscall_post_impl_set_mempolicy@Base 4.9
+ __sanitizer_syscall_post_impl_set_robust_list@Base 4.9
+ __sanitizer_syscall_post_impl_set_tid_address@Base 4.9
+ __sanitizer_syscall_post_impl_setdomainname@Base 4.9
+ __sanitizer_syscall_post_impl_setfsgid@Base 4.9
+ __sanitizer_syscall_post_impl_setfsuid@Base 4.9
+ __sanitizer_syscall_post_impl_setgid@Base 4.9
+ __sanitizer_syscall_post_impl_setgroups@Base 4.9
+ __sanitizer_syscall_post_impl_sethostname@Base 4.9
+ __sanitizer_syscall_post_impl_setitimer@Base 4.9
+ __sanitizer_syscall_post_impl_setns@Base 4.9
+ __sanitizer_syscall_post_impl_setpgid@Base 4.9
+ __sanitizer_syscall_post_impl_setpriority@Base 4.9
+ __sanitizer_syscall_post_impl_setregid@Base 4.9
+ __sanitizer_syscall_post_impl_setresgid@Base 4.9
+ __sanitizer_syscall_post_impl_setresuid@Base 4.9
+ __sanitizer_syscall_post_impl_setreuid@Base 4.9
+ __sanitizer_syscall_post_impl_setrlimit@Base 4.9
+ __sanitizer_syscall_post_impl_setsid@Base 4.9
+ __sanitizer_syscall_post_impl_setsockopt@Base 4.9
+ __sanitizer_syscall_post_impl_settimeofday@Base 4.9
+ __sanitizer_syscall_post_impl_setuid@Base 4.9
+ __sanitizer_syscall_post_impl_setxattr@Base 4.9
+ __sanitizer_syscall_post_impl_sgetmask@Base 4.9
+ __sanitizer_syscall_post_impl_shmat@Base 4.9
+ __sanitizer_syscall_post_impl_shmctl@Base 4.9
+ __sanitizer_syscall_post_impl_shmdt@Base 4.9
+ __sanitizer_syscall_post_impl_shmget@Base 4.9
+ __sanitizer_syscall_post_impl_shutdown@Base 4.9
+ __sanitizer_syscall_post_impl_signal@Base 4.9
+ __sanitizer_syscall_post_impl_signalfd4@Base 4.9
+ __sanitizer_syscall_post_impl_signalfd@Base 4.9
+ __sanitizer_syscall_post_impl_sigpending@Base 4.9
+ __sanitizer_syscall_post_impl_sigprocmask@Base 4.9
+ __sanitizer_syscall_post_impl_socket@Base 4.9
+ __sanitizer_syscall_post_impl_socketcall@Base 4.9
+ __sanitizer_syscall_post_impl_socketpair@Base 4.9
+ __sanitizer_syscall_post_impl_splice@Base 4.9
+ __sanitizer_syscall_post_impl_spu_create@Base 4.9
+ __sanitizer_syscall_post_impl_spu_run@Base 4.9
+ __sanitizer_syscall_post_impl_ssetmask@Base 4.9
+ __sanitizer_syscall_post_impl_stat64@Base 4.9
+ __sanitizer_syscall_post_impl_stat@Base 4.9
+ __sanitizer_syscall_post_impl_statfs64@Base 4.9
+ __sanitizer_syscall_post_impl_statfs@Base 4.9
+ __sanitizer_syscall_post_impl_stime@Base 4.9
+ __sanitizer_syscall_post_impl_swapoff@Base 4.9
+ __sanitizer_syscall_post_impl_swapon@Base 4.9
+ __sanitizer_syscall_post_impl_symlink@Base 4.9
+ __sanitizer_syscall_post_impl_symlinkat@Base 4.9
+ __sanitizer_syscall_post_impl_sync@Base 4.9
+ __sanitizer_syscall_post_impl_syncfs@Base 4.9
+ __sanitizer_syscall_post_impl_sysctl@Base 4.9
+ __sanitizer_syscall_post_impl_sysfs@Base 4.9
+ __sanitizer_syscall_post_impl_sysinfo@Base 4.9
+ __sanitizer_syscall_post_impl_syslog@Base 4.9
+ __sanitizer_syscall_post_impl_tee@Base 4.9
+ __sanitizer_syscall_post_impl_tgkill@Base 4.9
+ __sanitizer_syscall_post_impl_time@Base 4.9
+ __sanitizer_syscall_post_impl_timer_create@Base 4.9
+ __sanitizer_syscall_post_impl_timer_delete@Base 4.9
+ __sanitizer_syscall_post_impl_timer_getoverrun@Base 4.9
+ __sanitizer_syscall_post_impl_timer_gettime@Base 4.9
+ __sanitizer_syscall_post_impl_timer_settime@Base 4.9
+ __sanitizer_syscall_post_impl_timerfd_create@Base 4.9
+ __sanitizer_syscall_post_impl_timerfd_gettime@Base 4.9
+ __sanitizer_syscall_post_impl_timerfd_settime@Base 4.9
+ __sanitizer_syscall_post_impl_times@Base 4.9
+ __sanitizer_syscall_post_impl_tkill@Base 4.9
+ __sanitizer_syscall_post_impl_truncate@Base 4.9
+ __sanitizer_syscall_post_impl_umask@Base 4.9
+ __sanitizer_syscall_post_impl_umount@Base 4.9
+ __sanitizer_syscall_post_impl_uname@Base 4.9
+ __sanitizer_syscall_post_impl_unlink@Base 4.9
+ __sanitizer_syscall_post_impl_unlinkat@Base 4.9
+ __sanitizer_syscall_post_impl_unshare@Base 4.9
+ __sanitizer_syscall_post_impl_uselib@Base 4.9
+ __sanitizer_syscall_post_impl_ustat@Base 4.9
+ __sanitizer_syscall_post_impl_utime@Base 4.9
+ __sanitizer_syscall_post_impl_utimensat@Base 4.9
+ __sanitizer_syscall_post_impl_utimes@Base 4.9
+ __sanitizer_syscall_post_impl_vfork@Base 4.9
+ __sanitizer_syscall_post_impl_vhangup@Base 4.9
+ __sanitizer_syscall_post_impl_vmsplice@Base 4.9
+ __sanitizer_syscall_post_impl_wait4@Base 4.9
+ __sanitizer_syscall_post_impl_waitid@Base 4.9
+ __sanitizer_syscall_post_impl_waitpid@Base 4.9
+ __sanitizer_syscall_post_impl_write@Base 4.9
+ __sanitizer_syscall_post_impl_writev@Base 4.9
+ __sanitizer_syscall_pre_impl_accept4@Base 4.9
+ __sanitizer_syscall_pre_impl_accept@Base 4.9
+ __sanitizer_syscall_pre_impl_access@Base 4.9
+ __sanitizer_syscall_pre_impl_acct@Base 4.9
+ __sanitizer_syscall_pre_impl_add_key@Base 4.9
+ __sanitizer_syscall_pre_impl_adjtimex@Base 4.9
+ __sanitizer_syscall_pre_impl_alarm@Base 4.9
+ __sanitizer_syscall_pre_impl_bdflush@Base 4.9
+ __sanitizer_syscall_pre_impl_bind@Base 4.9
+ __sanitizer_syscall_pre_impl_brk@Base 4.9
+ __sanitizer_syscall_pre_impl_capget@Base 4.9
+ __sanitizer_syscall_pre_impl_capset@Base 4.9
+ __sanitizer_syscall_pre_impl_chdir@Base 4.9
+ __sanitizer_syscall_pre_impl_chmod@Base 4.9
+ __sanitizer_syscall_pre_impl_chown@Base 4.9
+ __sanitizer_syscall_pre_impl_chroot@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_adjtime@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_getres@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_gettime@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_nanosleep@Base 4.9
+ __sanitizer_syscall_pre_impl_clock_settime@Base 4.9
+ __sanitizer_syscall_pre_impl_close@Base 4.9
+ __sanitizer_syscall_pre_impl_connect@Base 4.9
+ __sanitizer_syscall_pre_impl_creat@Base 4.9
+ __sanitizer_syscall_pre_impl_delete_module@Base 4.9
+ __sanitizer_syscall_pre_impl_dup2@Base 4.9
+ __sanitizer_syscall_pre_impl_dup3@Base 4.9
+ __sanitizer_syscall_pre_impl_dup@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_create1@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_create@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_ctl@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_pwait@Base 4.9
+ __sanitizer_syscall_pre_impl_epoll_wait@Base 4.9
+ __sanitizer_syscall_pre_impl_eventfd2@Base 4.9
+ __sanitizer_syscall_pre_impl_eventfd@Base 4.9
+ __sanitizer_syscall_pre_impl_exit@Base 4.9
+ __sanitizer_syscall_pre_impl_exit_group@Base 4.9
+ __sanitizer_syscall_pre_impl_faccessat@Base 4.9
+ __sanitizer_syscall_pre_impl_fchdir@Base 4.9
+ __sanitizer_syscall_pre_impl_fchmod@Base 4.9
+ __sanitizer_syscall_pre_impl_fchmodat@Base 4.9
+ __sanitizer_syscall_pre_impl_fchown@Base 4.9
+ __sanitizer_syscall_pre_impl_fchownat@Base 4.9
+ __sanitizer_syscall_pre_impl_fcntl64@Base 4.9
+ __sanitizer_syscall_pre_impl_fcntl@Base 4.9
+ __sanitizer_syscall_pre_impl_fdatasync@Base 4.9
+ __sanitizer_syscall_pre_impl_fgetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_flistxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_flock@Base 4.9
+ __sanitizer_syscall_pre_impl_fork@Base 4.9
+ __sanitizer_syscall_pre_impl_fremovexattr@Base 4.9
+ __sanitizer_syscall_pre_impl_fsetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_fstat64@Base 4.9
+ __sanitizer_syscall_pre_impl_fstat@Base 4.9
+ __sanitizer_syscall_pre_impl_fstatat64@Base 4.9
+ __sanitizer_syscall_pre_impl_fstatfs64@Base 4.9
+ __sanitizer_syscall_pre_impl_fstatfs@Base 4.9
+ __sanitizer_syscall_pre_impl_fsync@Base 4.9
+ __sanitizer_syscall_pre_impl_ftruncate@Base 4.9
+ __sanitizer_syscall_pre_impl_futimesat@Base 4.9
+ __sanitizer_syscall_pre_impl_get_mempolicy@Base 4.9
+ __sanitizer_syscall_pre_impl_get_robust_list@Base 4.9
+ __sanitizer_syscall_pre_impl_getcpu@Base 4.9
+ __sanitizer_syscall_pre_impl_getcwd@Base 4.9
+ __sanitizer_syscall_pre_impl_getdents64@Base 4.9
+ __sanitizer_syscall_pre_impl_getdents@Base 4.9
+ __sanitizer_syscall_pre_impl_getegid@Base 4.9
+ __sanitizer_syscall_pre_impl_geteuid@Base 4.9
+ __sanitizer_syscall_pre_impl_getgid@Base 4.9
+ __sanitizer_syscall_pre_impl_getgroups@Base 4.9
+ __sanitizer_syscall_pre_impl_gethostname@Base 4.9
+ __sanitizer_syscall_pre_impl_getitimer@Base 4.9
+ __sanitizer_syscall_pre_impl_getpeername@Base 4.9
+ __sanitizer_syscall_pre_impl_getpgid@Base 4.9
+ __sanitizer_syscall_pre_impl_getpgrp@Base 4.9
+ __sanitizer_syscall_pre_impl_getpid@Base 4.9
+ __sanitizer_syscall_pre_impl_getppid@Base 4.9
+ __sanitizer_syscall_pre_impl_getpriority@Base 4.9
+ __sanitizer_syscall_pre_impl_getresgid@Base 4.9
+ __sanitizer_syscall_pre_impl_getresuid@Base 4.9
+ __sanitizer_syscall_pre_impl_getrlimit@Base 4.9
+ __sanitizer_syscall_pre_impl_getrusage@Base 4.9
+ __sanitizer_syscall_pre_impl_getsid@Base 4.9
+ __sanitizer_syscall_pre_impl_getsockname@Base 4.9
+ __sanitizer_syscall_pre_impl_getsockopt@Base 4.9
+ __sanitizer_syscall_pre_impl_gettid@Base 4.9
+ __sanitizer_syscall_pre_impl_gettimeofday@Base 4.9
+ __sanitizer_syscall_pre_impl_getuid@Base 4.9
+ __sanitizer_syscall_pre_impl_getxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_init_module@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_add_watch@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_init1@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_init@Base 4.9
+ __sanitizer_syscall_pre_impl_inotify_rm_watch@Base 4.9
+ __sanitizer_syscall_pre_impl_io_cancel@Base 4.9
+ __sanitizer_syscall_pre_impl_io_destroy@Base 4.9
+ __sanitizer_syscall_pre_impl_io_getevents@Base 4.9
+ __sanitizer_syscall_pre_impl_io_setup@Base 4.9
+ __sanitizer_syscall_pre_impl_io_submit@Base 4.9
+ __sanitizer_syscall_pre_impl_ioctl@Base 4.9
+ __sanitizer_syscall_pre_impl_ioperm@Base 4.9
+ __sanitizer_syscall_pre_impl_ioprio_get@Base 4.9
+ __sanitizer_syscall_pre_impl_ioprio_set@Base 4.9
+ __sanitizer_syscall_pre_impl_ipc@Base 4.9
+ __sanitizer_syscall_pre_impl_kexec_load@Base 4.9
+ __sanitizer_syscall_pre_impl_keyctl@Base 4.9
+ __sanitizer_syscall_pre_impl_kill@Base 4.9
+ __sanitizer_syscall_pre_impl_lchown@Base 4.9
+ __sanitizer_syscall_pre_impl_lgetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_link@Base 4.9
+ __sanitizer_syscall_pre_impl_linkat@Base 4.9
+ __sanitizer_syscall_pre_impl_listen@Base 4.9
+ __sanitizer_syscall_pre_impl_listxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_llistxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_llseek@Base 4.9
+ __sanitizer_syscall_pre_impl_lookup_dcookie@Base 4.9
+ __sanitizer_syscall_pre_impl_lremovexattr@Base 4.9
+ __sanitizer_syscall_pre_impl_lseek@Base 4.9
+ __sanitizer_syscall_pre_impl_lsetxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_lstat64@Base 4.9
+ __sanitizer_syscall_pre_impl_lstat@Base 4.9
+ __sanitizer_syscall_pre_impl_madvise@Base 4.9
+ __sanitizer_syscall_pre_impl_mbind@Base 4.9
+ __sanitizer_syscall_pre_impl_migrate_pages@Base 4.9
+ __sanitizer_syscall_pre_impl_mincore@Base 4.9
+ __sanitizer_syscall_pre_impl_mkdir@Base 4.9
+ __sanitizer_syscall_pre_impl_mkdirat@Base 4.9
+ __sanitizer_syscall_pre_impl_mknod@Base 4.9
+ __sanitizer_syscall_pre_impl_mknodat@Base 4.9
+ __sanitizer_syscall_pre_impl_mlock@Base 4.9
+ __sanitizer_syscall_pre_impl_mlockall@Base 4.9
+ __sanitizer_syscall_pre_impl_mmap_pgoff@Base 4.9
+ __sanitizer_syscall_pre_impl_mount@Base 4.9
+ __sanitizer_syscall_pre_impl_move_pages@Base 4.9
+ __sanitizer_syscall_pre_impl_mprotect@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_getsetattr@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_notify@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_open@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_timedreceive@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_timedsend@Base 4.9
+ __sanitizer_syscall_pre_impl_mq_unlink@Base 4.9
+ __sanitizer_syscall_pre_impl_mremap@Base 4.9
+ __sanitizer_syscall_pre_impl_msgctl@Base 4.9
+ __sanitizer_syscall_pre_impl_msgget@Base 4.9
+ __sanitizer_syscall_pre_impl_msgrcv@Base 4.9
+ __sanitizer_syscall_pre_impl_msgsnd@Base 4.9
+ __sanitizer_syscall_pre_impl_msync@Base 4.9
+ __sanitizer_syscall_pre_impl_munlock@Base 4.9
+ __sanitizer_syscall_pre_impl_munlockall@Base 4.9
+ __sanitizer_syscall_pre_impl_munmap@Base 4.9
+ __sanitizer_syscall_pre_impl_name_to_handle_at@Base 4.9
+ __sanitizer_syscall_pre_impl_nanosleep@Base 4.9
+ __sanitizer_syscall_pre_impl_newfstat@Base 4.9
+ __sanitizer_syscall_pre_impl_newfstatat@Base 4.9
+ __sanitizer_syscall_pre_impl_newlstat@Base 4.9
+ __sanitizer_syscall_pre_impl_newstat@Base 4.9
+ __sanitizer_syscall_pre_impl_newuname@Base 4.9
+ __sanitizer_syscall_pre_impl_ni_syscall@Base 4.9
+ __sanitizer_syscall_pre_impl_nice@Base 4.9
+ __sanitizer_syscall_pre_impl_old_getrlimit@Base 4.9
+ __sanitizer_syscall_pre_impl_old_mmap@Base 4.9
+ __sanitizer_syscall_pre_impl_old_readdir@Base 4.9
+ __sanitizer_syscall_pre_impl_old_select@Base 4.9
+ __sanitizer_syscall_pre_impl_oldumount@Base 4.9
+ __sanitizer_syscall_pre_impl_olduname@Base 4.9
+ __sanitizer_syscall_pre_impl_open@Base 4.9
+ __sanitizer_syscall_pre_impl_open_by_handle_at@Base 4.9
+ __sanitizer_syscall_pre_impl_openat@Base 4.9
+ __sanitizer_syscall_pre_impl_pause@Base 4.9
+ __sanitizer_syscall_pre_impl_pciconfig_iobase@Base 4.9
+ __sanitizer_syscall_pre_impl_pciconfig_read@Base 4.9
+ __sanitizer_syscall_pre_impl_pciconfig_write@Base 4.9
+ __sanitizer_syscall_pre_impl_perf_event_open@Base 4.9
+ __sanitizer_syscall_pre_impl_personality@Base 4.9
+ __sanitizer_syscall_pre_impl_pipe2@Base 4.9
+ __sanitizer_syscall_pre_impl_pipe@Base 4.9
+ __sanitizer_syscall_pre_impl_pivot_root@Base 4.9
+ __sanitizer_syscall_pre_impl_poll@Base 4.9
+ __sanitizer_syscall_pre_impl_ppoll@Base 4.9
+ __sanitizer_syscall_pre_impl_pread64@Base 4.9
+ __sanitizer_syscall_pre_impl_preadv@Base 4.9
+ __sanitizer_syscall_pre_impl_prlimit64@Base 4.9
+ __sanitizer_syscall_pre_impl_process_vm_readv@Base 4.9
+ __sanitizer_syscall_pre_impl_process_vm_writev@Base 4.9
+ __sanitizer_syscall_pre_impl_pselect6@Base 4.9
+ __sanitizer_syscall_pre_impl_ptrace@Base 4.9
+ __sanitizer_syscall_pre_impl_pwrite64@Base 4.9
+ __sanitizer_syscall_pre_impl_pwritev@Base 4.9
+ __sanitizer_syscall_pre_impl_quotactl@Base 4.9
+ __sanitizer_syscall_pre_impl_read@Base 4.9
+ __sanitizer_syscall_pre_impl_readlink@Base 4.9
+ __sanitizer_syscall_pre_impl_readlinkat@Base 4.9
+ __sanitizer_syscall_pre_impl_readv@Base 4.9
+ __sanitizer_syscall_pre_impl_reboot@Base 4.9
+ __sanitizer_syscall_pre_impl_recv@Base 4.9
+ __sanitizer_syscall_pre_impl_recvfrom@Base 4.9
+ __sanitizer_syscall_pre_impl_recvmmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_recvmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_remap_file_pages@Base 4.9
+ __sanitizer_syscall_pre_impl_removexattr@Base 4.9
+ __sanitizer_syscall_pre_impl_rename@Base 4.9
+ __sanitizer_syscall_pre_impl_renameat@Base 4.9
+ __sanitizer_syscall_pre_impl_request_key@Base 4.9
+ __sanitizer_syscall_pre_impl_restart_syscall@Base 4.9
+ __sanitizer_syscall_pre_impl_rmdir@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigpending@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigprocmask@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigqueueinfo@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_sigtimedwait@Base 4.9
+ __sanitizer_syscall_pre_impl_rt_tgsigqueueinfo@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_get_priority_max@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_get_priority_min@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_getaffinity@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_getparam@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_getscheduler@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_rr_get_interval@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_setaffinity@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_setparam@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_setscheduler@Base 4.9
+ __sanitizer_syscall_pre_impl_sched_yield@Base 4.9
+ __sanitizer_syscall_pre_impl_select@Base 4.9
+ __sanitizer_syscall_pre_impl_semctl@Base 4.9
+ __sanitizer_syscall_pre_impl_semget@Base 4.9
+ __sanitizer_syscall_pre_impl_semop@Base 4.9
+ __sanitizer_syscall_pre_impl_semtimedop@Base 4.9
+ __sanitizer_syscall_pre_impl_send@Base 4.9
+ __sanitizer_syscall_pre_impl_sendfile64@Base 4.9
+ __sanitizer_syscall_pre_impl_sendfile@Base 4.9
+ __sanitizer_syscall_pre_impl_sendmmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_sendmsg@Base 4.9
+ __sanitizer_syscall_pre_impl_sendto@Base 4.9
+ __sanitizer_syscall_pre_impl_set_mempolicy@Base 4.9
+ __sanitizer_syscall_pre_impl_set_robust_list@Base 4.9
+ __sanitizer_syscall_pre_impl_set_tid_address@Base 4.9
+ __sanitizer_syscall_pre_impl_setdomainname@Base 4.9
+ __sanitizer_syscall_pre_impl_setfsgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setfsuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setgroups@Base 4.9
+ __sanitizer_syscall_pre_impl_sethostname@Base 4.9
+ __sanitizer_syscall_pre_impl_setitimer@Base 4.9
+ __sanitizer_syscall_pre_impl_setns@Base 4.9
+ __sanitizer_syscall_pre_impl_setpgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setpriority@Base 4.9
+ __sanitizer_syscall_pre_impl_setregid@Base 4.9
+ __sanitizer_syscall_pre_impl_setresgid@Base 4.9
+ __sanitizer_syscall_pre_impl_setresuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setreuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setrlimit@Base 4.9
+ __sanitizer_syscall_pre_impl_setsid@Base 4.9
+ __sanitizer_syscall_pre_impl_setsockopt@Base 4.9
+ __sanitizer_syscall_pre_impl_settimeofday@Base 4.9
+ __sanitizer_syscall_pre_impl_setuid@Base 4.9
+ __sanitizer_syscall_pre_impl_setxattr@Base 4.9
+ __sanitizer_syscall_pre_impl_sgetmask@Base 4.9
+ __sanitizer_syscall_pre_impl_shmat@Base 4.9
+ __sanitizer_syscall_pre_impl_shmctl@Base 4.9
+ __sanitizer_syscall_pre_impl_shmdt@Base 4.9
+ __sanitizer_syscall_pre_impl_shmget@Base 4.9
+ __sanitizer_syscall_pre_impl_shutdown@Base 4.9
+ __sanitizer_syscall_pre_impl_signal@Base 4.9
+ __sanitizer_syscall_pre_impl_signalfd4@Base 4.9
+ __sanitizer_syscall_pre_impl_signalfd@Base 4.9
+ __sanitizer_syscall_pre_impl_sigpending@Base 4.9
+ __sanitizer_syscall_pre_impl_sigprocmask@Base 4.9
+ __sanitizer_syscall_pre_impl_socket@Base 4.9
+ __sanitizer_syscall_pre_impl_socketcall@Base 4.9
+ __sanitizer_syscall_pre_impl_socketpair@Base 4.9
+ __sanitizer_syscall_pre_impl_splice@Base 4.9
+ __sanitizer_syscall_pre_impl_spu_create@Base 4.9
+ __sanitizer_syscall_pre_impl_spu_run@Base 4.9
+ __sanitizer_syscall_pre_impl_ssetmask@Base 4.9
+ __sanitizer_syscall_pre_impl_stat64@Base 4.9
+ __sanitizer_syscall_pre_impl_stat@Base 4.9
+ __sanitizer_syscall_pre_impl_statfs64@Base 4.9
+ __sanitizer_syscall_pre_impl_statfs@Base 4.9
+ __sanitizer_syscall_pre_impl_stime@Base 4.9
+ __sanitizer_syscall_pre_impl_swapoff@Base 4.9
+ __sanitizer_syscall_pre_impl_swapon@Base 4.9
+ __sanitizer_syscall_pre_impl_symlink@Base 4.9
+ __sanitizer_syscall_pre_impl_symlinkat@Base 4.9
+ __sanitizer_syscall_pre_impl_sync@Base 4.9
+ __sanitizer_syscall_pre_impl_syncfs@Base 4.9
+ __sanitizer_syscall_pre_impl_sysctl@Base 4.9
+ __sanitizer_syscall_pre_impl_sysfs@Base 4.9
+ __sanitizer_syscall_pre_impl_sysinfo@Base 4.9
+ __sanitizer_syscall_pre_impl_syslog@Base 4.9
+ __sanitizer_syscall_pre_impl_tee@Base 4.9
+ __sanitizer_syscall_pre_impl_tgkill@Base 4.9
+ __sanitizer_syscall_pre_impl_time@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_create@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_delete@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_getoverrun@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_gettime@Base 4.9
+ __sanitizer_syscall_pre_impl_timer_settime@Base 4.9
+ __sanitizer_syscall_pre_impl_timerfd_create@Base 4.9
+ __sanitizer_syscall_pre_impl_timerfd_gettime@Base 4.9
+ __sanitizer_syscall_pre_impl_timerfd_settime@Base 4.9
+ __sanitizer_syscall_pre_impl_times@Base 4.9
+ __sanitizer_syscall_pre_impl_tkill@Base 4.9
+ __sanitizer_syscall_pre_impl_truncate@Base 4.9
+ __sanitizer_syscall_pre_impl_umask@Base 4.9
+ __sanitizer_syscall_pre_impl_umount@Base 4.9
+ __sanitizer_syscall_pre_impl_uname@Base 4.9
+ __sanitizer_syscall_pre_impl_unlink@Base 4.9
+ __sanitizer_syscall_pre_impl_unlinkat@Base 4.9
+ __sanitizer_syscall_pre_impl_unshare@Base 4.9
+ __sanitizer_syscall_pre_impl_uselib@Base 4.9
+ __sanitizer_syscall_pre_impl_ustat@Base 4.9
+ __sanitizer_syscall_pre_impl_utime@Base 4.9
+ __sanitizer_syscall_pre_impl_utimensat@Base 4.9
+ __sanitizer_syscall_pre_impl_utimes@Base 4.9
+ __sanitizer_syscall_pre_impl_vfork@Base 4.9
+ __sanitizer_syscall_pre_impl_vhangup@Base 4.9
+ __sanitizer_syscall_pre_impl_vmsplice@Base 4.9
+ __sanitizer_syscall_pre_impl_wait4@Base 4.9
+ __sanitizer_syscall_pre_impl_waitid@Base 4.9
+ __sanitizer_syscall_pre_impl_waitpid@Base 4.9
+ __sanitizer_syscall_pre_impl_write@Base 4.9
+ __sanitizer_syscall_pre_impl_writev@Base 4.9
+ __sanitizer_unaligned_load16@Base 4.9
+ __sanitizer_unaligned_load32@Base 4.9
+ __sanitizer_unaligned_load64@Base 4.9
+ __sanitizer_unaligned_store16@Base 4.9
+ __sanitizer_unaligned_store32@Base 4.9
+ __sanitizer_unaligned_store64@Base 4.9
+ __sanitizer_update_counter_bitset_and_clear_counters@Base 6
+ __sigsetjmp@Base 4.9
+ __tls_get_addr@Base 6
+ __tsan_acquire@Base 4.9
+ __tsan_atomic128_compare_exchange_strong@Base 4.9
+ __tsan_atomic128_compare_exchange_val@Base 4.9
+ __tsan_atomic128_compare_exchange_weak@Base 4.9
+ __tsan_atomic128_exchange@Base 4.9
+ __tsan_atomic128_fetch_add@Base 4.9
+ __tsan_atomic128_fetch_and@Base 4.9
+ __tsan_atomic128_fetch_nand@Base 4.9
+ __tsan_atomic128_fetch_or@Base 4.9
+ __tsan_atomic128_fetch_sub@Base 4.9
+ __tsan_atomic128_fetch_xor@Base 4.9
+ __tsan_atomic128_load@Base 4.9
+ __tsan_atomic128_store@Base 4.9
+ __tsan_atomic16_compare_exchange_strong@Base 4.9
+ __tsan_atomic16_compare_exchange_val@Base 4.9
+ __tsan_atomic16_compare_exchange_weak@Base 4.9
+ __tsan_atomic16_exchange@Base 4.9
+ __tsan_atomic16_fetch_add@Base 4.9
+ __tsan_atomic16_fetch_and@Base 4.9
+ __tsan_atomic16_fetch_nand@Base 4.9
+ __tsan_atomic16_fetch_or@Base 4.9
+ __tsan_atomic16_fetch_sub@Base 4.9
+ __tsan_atomic16_fetch_xor@Base 4.9
+ __tsan_atomic16_load@Base 4.9
+ __tsan_atomic16_store@Base 4.9
+ __tsan_atomic32_compare_exchange_strong@Base 4.9
+ __tsan_atomic32_compare_exchange_val@Base 4.9
+ __tsan_atomic32_compare_exchange_weak@Base 4.9
+ __tsan_atomic32_exchange@Base 4.9
+ __tsan_atomic32_fetch_add@Base 4.9
+ __tsan_atomic32_fetch_and@Base 4.9
+ __tsan_atomic32_fetch_nand@Base 4.9
+ __tsan_atomic32_fetch_or@Base 4.9
+ __tsan_atomic32_fetch_sub@Base 4.9
+ __tsan_atomic32_fetch_xor@Base 4.9
+ __tsan_atomic32_load@Base 4.9
+ __tsan_atomic32_store@Base 4.9
+ __tsan_atomic64_compare_exchange_strong@Base 4.9
+ __tsan_atomic64_compare_exchange_val@Base 4.9
+ __tsan_atomic64_compare_exchange_weak@Base 4.9
+ __tsan_atomic64_exchange@Base 4.9
+ __tsan_atomic64_fetch_add@Base 4.9
+ __tsan_atomic64_fetch_and@Base 4.9
+ __tsan_atomic64_fetch_nand@Base 4.9
+ __tsan_atomic64_fetch_or@Base 4.9
+ __tsan_atomic64_fetch_sub@Base 4.9
+ __tsan_atomic64_fetch_xor@Base 4.9
+ __tsan_atomic64_load@Base 4.9
+ __tsan_atomic64_store@Base 4.9
+ __tsan_atomic8_compare_exchange_strong@Base 4.9
+ __tsan_atomic8_compare_exchange_val@Base 4.9
+ __tsan_atomic8_compare_exchange_weak@Base 4.9
+ __tsan_atomic8_exchange@Base 4.9
+ __tsan_atomic8_fetch_add@Base 4.9
+ __tsan_atomic8_fetch_and@Base 4.9
+ __tsan_atomic8_fetch_nand@Base 4.9
+ __tsan_atomic8_fetch_or@Base 4.9
+ __tsan_atomic8_fetch_sub@Base 4.9
+ __tsan_atomic8_fetch_xor@Base 4.9
+ __tsan_atomic8_load@Base 4.9
+ __tsan_atomic8_store@Base 4.9
+ __tsan_atomic_signal_fence@Base 4.9
+ __tsan_atomic_thread_fence@Base 4.9
+ __tsan_default_options@Base 4.9
+ __tsan_func_entry@Base 4.9
+ __tsan_func_exit@Base 4.9
+ __tsan_init@Base 4.9
+ __tsan_java_acquire@Base 6
+ __tsan_java_alloc@Base 4.9
+ __tsan_java_finalize@Base 5
+ __tsan_java_fini@Base 4.9
+ __tsan_java_free@Base 4.9
+ __tsan_java_init@Base 4.9
+ __tsan_java_move@Base 4.9
+ __tsan_java_mutex_lock@Base 4.9
+ __tsan_java_mutex_lock_rec@Base 4.9
+ __tsan_java_mutex_read_lock@Base 4.9
+ __tsan_java_mutex_read_unlock@Base 4.9
+ __tsan_java_mutex_unlock@Base 4.9
+ __tsan_java_mutex_unlock_rec@Base 4.9
+ __tsan_java_release@Base 6
+ __tsan_java_release_store@Base 6
+ __tsan_read16@Base 4.9
+ __tsan_read16_pc@Base 6
+ __tsan_read1@Base 4.9
+ __tsan_read1_pc@Base 6
+ __tsan_read2@Base 4.9
+ __tsan_read2_pc@Base 6
+ __tsan_read4@Base 4.9
+ __tsan_read4_pc@Base 6
+ __tsan_read8@Base 4.9
+ __tsan_read8_pc@Base 6
+ __tsan_read_range@Base 4.9
+ __tsan_release@Base 4.9
+ __tsan_unaligned_read16@Base 6
+ __tsan_unaligned_read2@Base 4.9
+ __tsan_unaligned_read4@Base 4.9
+ __tsan_unaligned_read8@Base 4.9
+ __tsan_unaligned_write16@Base 6
+ __tsan_unaligned_write2@Base 4.9
+ __tsan_unaligned_write4@Base 4.9
+ __tsan_unaligned_write8@Base 4.9
+ __tsan_vptr_read@Base 4.9
+ __tsan_vptr_update@Base 4.9
+ __tsan_write16@Base 4.9
+ __tsan_write16_pc@Base 6
+ __tsan_write1@Base 4.9
+ __tsan_write1_pc@Base 6
+ __tsan_write2@Base 4.9
+ __tsan_write2_pc@Base 6
+ __tsan_write4@Base 4.9
+ __tsan_write4_pc@Base 6
+ __tsan_write8@Base 4.9
+ __tsan_write8_pc@Base 6
+ __tsan_write_range@Base 4.9
+ __uflow@Base 5
+ __underflow@Base 5
+ __woverflow@Base 5
+ __wuflow@Base 5
+ __wunderflow@Base 5
+ __xpg_strerror_r@Base 4.9
+ __xstat64@Base 4.9
+ __xstat@Base 4.9
+ _exit@Base 4.9
+ _obstack_begin@Base 5
+ _obstack_begin_1@Base 5
+ _obstack_newchunk@Base 5
+ _setjmp@Base 4.9
+ abort@Base 4.9
+ accept4@Base 4.9
+ accept@Base 4.9
+ aligned_alloc@Base 5
+ asctime@Base 4.9
+ asctime_r@Base 4.9
+ asprintf@Base 5
+ atexit@Base 4.9
+ backtrace@Base 4.9
+ backtrace_symbols@Base 4.9
+ bind@Base 4.9
+ calloc@Base 4.9
+ canonicalize_file_name@Base 4.9
+ capget@Base 5
+ capset@Base 5
+ cfree@Base 4.9
+ clock_getres@Base 4.9
+ clock_gettime@Base 4.9
+ clock_settime@Base 4.9
+ close@Base 4.9
+ closedir@Base 6
+ confstr@Base 4.9
+ connect@Base 4.9
+ creat64@Base 4.9
+ creat@Base 4.9
+ ctime@Base 4.9
+ ctime_r@Base 4.9
+ dl_iterate_phdr@Base 6
+ dlclose@Base 4.9
+ dlopen@Base 4.9
+ drand48_r@Base 4.9
+ dup2@Base 4.9
+ dup3@Base 4.9
+ dup@Base 4.9
+ endgrent@Base 5
+ endpwent@Base 5
+ epoll_create1@Base 4.9
+ epoll_create@Base 4.9
+ epoll_ctl@Base 4.9
+ epoll_wait@Base 4.9
+ ether_aton@Base 4.9
+ ether_aton_r@Base 4.9
+ ether_hostton@Base 4.9
+ ether_line@Base 4.9
+ ether_ntoa@Base 4.9
+ ether_ntoa_r@Base 4.9
+ ether_ntohost@Base 4.9
+ eventfd@Base 4.9
+ fclose@Base 4.9
+ fdopen@Base 5
+ fflush@Base 4.9
+ fgetxattr@Base 5
+ flistxattr@Base 5
+ fmemopen@Base 5
+ fopen64@Base 5
+ fopen@Base 4.9
+ fopencookie@Base 6
+ fork@Base 4.9
+ fprintf@Base 5
+ fread@Base 4.9
+ free@Base 4.9
+ freopen64@Base 5
+ freopen@Base 4.9
+ frexp@Base 4.9
+ frexpf@Base 4.9
+ frexpl@Base 4.9
+ fscanf@Base 4.9
+ fstat64@Base 4.9
+ fstat@Base 4.9
+ fstatfs64@Base 4.9
+ fstatfs@Base 4.9
+ fstatvfs64@Base 4.9
+ fstatvfs@Base 4.9
+ ftime@Base 5
+ fwrite@Base 4.9
+ get_current_dir_name@Base 4.9
+ getaddrinfo@Base 4.9
+ getcwd@Base 4.9
+ getdelim@Base 4.9
+ getgroups@Base 4.9
+ gethostbyaddr@Base 4.9
+ gethostbyaddr_r@Base 4.9
+ gethostbyname2@Base 4.9
+ gethostbyname2_r@Base 4.9
+ gethostbyname@Base 4.9
+ gethostbyname_r@Base 4.9
+ gethostent@Base 4.9
+ gethostent_r@Base 4.9
+ getifaddrs@Base 5
+ getitimer@Base 4.9
+ getline@Base 4.9
+ getmntent@Base 4.9
+ getmntent_r@Base 4.9
+ getnameinfo@Base 5
+ getpass@Base 5
+ getpeername@Base 4.9
+ getresgid@Base 5
+ getresuid@Base 5
+ getsockname@Base 4.9
+ getsockopt@Base 4.9
+ gettimeofday@Base 4.9
+ getxattr@Base 5
+ glob64@Base 5
+ glob@Base 5
+ gmtime@Base 4.9
+ gmtime_r@Base 4.9
+ iconv@Base 4.9
+ if_indextoname@Base 5
+ if_nametoindex@Base 5
+ inet_aton@Base 4.9
+ inet_ntop@Base 4.9
+ inet_pton@Base 4.9
+ initgroups@Base 4.9
+ inotify_init1@Base 4.9
+ inotify_init@Base 4.9
+ ioctl@Base 4.9
+ kill@Base 4.9
+ lgamma@Base 4.9
+ lgamma_r@Base 4.9
+ lgammaf@Base 4.9
+ lgammaf_r@Base 4.9
+ lgammal@Base 4.9
+ lgammal_r@Base 4.9
+ lgetxattr@Base 5
+ listen@Base 4.9
+ listxattr@Base 5
+ llistxattr@Base 5
+ localtime@Base 4.9
+ localtime_r@Base 4.9
+ longjmp@Base 4.9
+ lrand48_r@Base 4.9
+ lstat64@Base 4.9
+ lstat@Base 4.9
+ malloc@Base 4.9
+ malloc_usable_size@Base 4.9
+ mbsnrtowcs@Base 4.9
+ mbsrtowcs@Base 4.9
+ mbstowcs@Base 4.9
+ memalign@Base 4.9
+ memchr@Base 4.9
+ memcmp@Base 4.9
+ memcpy@Base 4.9
+ memmove@Base 4.9
+ memrchr@Base 4.9
+ memset@Base 4.9
+ mincore@Base 6
+ mktime@Base 5
+ mlock@Base 4.9
+ mlockall@Base 4.9
+ mmap64@Base 4.9
+ mmap@Base 4.9
+ modf@Base 4.9
+ modff@Base 4.9
+ modfl@Base 4.9
+ munlock@Base 4.9
+ munlockall@Base 4.9
+ munmap@Base 4.9
+ nanosleep@Base 4.9
+ on_exit@Base 4.9
+ open64@Base 4.9
+ open@Base 4.9
+ open_memstream@Base 5
+ open_wmemstream@Base 5
+ opendir@Base 4.9
+ pipe2@Base 4.9
+ pipe@Base 4.9
+ poll@Base 4.9
+ posix_memalign@Base 4.9
+ ppoll@Base 4.9
+ prctl@Base 4.9
+ pread64@Base 4.9
+ pread@Base 4.9
+ preadv64@Base 4.9
+ preadv@Base 4.9
+ printf@Base 5
+ process_vm_readv@Base 6
+ process_vm_writev@Base 6
+ pthread_attr_getaffinity_np@Base 4.9
+ pthread_attr_getdetachstate@Base 4.9
+ pthread_attr_getguardsize@Base 4.9
+ pthread_attr_getinheritsched@Base 4.9
+ pthread_attr_getschedparam@Base 4.9
+ pthread_attr_getschedpolicy@Base 4.9
+ pthread_attr_getscope@Base 4.9
+ pthread_attr_getstack@Base 4.9
+ pthread_attr_getstacksize@Base 4.9
+ pthread_barrier_destroy@Base 4.9
+ pthread_barrier_init@Base 4.9
+ pthread_barrier_wait@Base 4.9
+ pthread_barrierattr_getpshared@Base 5
+ pthread_cond_broadcast@Base 4.9
+ pthread_cond_destroy@Base 4.9
+ pthread_cond_init@Base 4.9
+ pthread_cond_signal@Base 4.9
+ pthread_cond_timedwait@Base 4.9
+ pthread_cond_wait@Base 4.9
+ pthread_condattr_getclock@Base 5
+ pthread_condattr_getpshared@Base 5
+ pthread_create@Base 4.9
+ pthread_detach@Base 4.9
+ pthread_getschedparam@Base 4.9
+ pthread_join@Base 4.9
+ pthread_kill@Base 4.9
+ pthread_mutex_destroy@Base 4.9
+ pthread_mutex_init@Base 4.9
+ pthread_mutex_lock@Base 4.9
+ pthread_mutex_timedlock@Base 4.9
+ pthread_mutex_trylock@Base 4.9
+ pthread_mutex_unlock@Base 4.9
+ pthread_mutexattr_getprioceiling@Base 5
+ pthread_mutexattr_getprotocol@Base 5
+ pthread_mutexattr_getpshared@Base 5
+ pthread_mutexattr_getrobust@Base 5
+ pthread_mutexattr_getrobust_np@Base 5
+ pthread_mutexattr_gettype@Base 5
+ pthread_once@Base 4.9
+ pthread_rwlock_destroy@Base 4.9
+ pthread_rwlock_init@Base 4.9
+ pthread_rwlock_rdlock@Base 4.9
+ pthread_rwlock_timedrdlock@Base 4.9
+ pthread_rwlock_timedwrlock@Base 4.9
+ pthread_rwlock_tryrdlock@Base 4.9
+ pthread_rwlock_trywrlock@Base 4.9
+ pthread_rwlock_unlock@Base 4.9
+ pthread_rwlock_wrlock@Base 4.9
+ pthread_rwlockattr_getkind_np@Base 5
+ pthread_rwlockattr_getpshared@Base 5
+ pthread_setcancelstate@Base 6
+ pthread_setcanceltype@Base 6
+ pthread_setname_np@Base 4.9
+ pthread_spin_destroy@Base 4.9
+ pthread_spin_init@Base 4.9
+ pthread_spin_lock@Base 4.9
+ pthread_spin_trylock@Base 4.9
+ pthread_spin_unlock@Base 4.9
+ ptrace@Base 4.9
+ puts@Base 4.9
+ pvalloc@Base 4.9
+ pwrite64@Base 4.9
+ pwrite@Base 4.9
+ pwritev64@Base 4.9
+ pwritev@Base 4.9
+ raise@Base 4.9
+ rand_r@Base 5
+ random_r@Base 4.9
+ read@Base 4.9
+ readdir64@Base 4.9
+ readdir64_r@Base 4.9
+ readdir@Base 4.9
+ readdir_r@Base 4.9
+ readv@Base 4.9
+ realloc@Base 4.9
+ realpath@Base 4.9
+ recv@Base 4.9
+ recvmsg@Base 4.9
+ remquo@Base 4.9
+ remquof@Base 4.9
+ remquol@Base 4.9
+ rmdir@Base 4.9
+ scandir64@Base 4.9
+ scandir@Base 4.9
+ scanf@Base 4.9
+ sched_getaffinity@Base 4.9
+ sched_getparam@Base 6
+ sem_destroy@Base 4.9
+ sem_getvalue@Base 4.9
+ sem_init@Base 4.9
+ sem_post@Base 4.9
+ sem_timedwait@Base 4.9
+ sem_trywait@Base 4.9
+ sem_wait@Base 4.9
+ send@Base 4.9
+ sendmsg@Base 4.9
+ setgrent@Base 5
+ setitimer@Base 4.9
+ setjmp@Base 4.9
+ setlocale@Base 4.9
+ setpwent@Base 5
+ shmctl@Base 4.9
+ sigaction@Base 4.9
+ sigemptyset@Base 4.9
+ sigfillset@Base 4.9
+ siglongjmp@Base 4.9
+ signal@Base 4.9
+ signalfd@Base 4.9
+ sigpending@Base 4.9
+ sigprocmask@Base 4.9
+ sigsetjmp@Base 4.9
+ sigsuspend@Base 4.9
+ sigtimedwait@Base 4.9
+ sigwait@Base 4.9
+ sigwaitinfo@Base 4.9
+ sincos@Base 4.9
+ sincosf@Base 4.9
+ sincosl@Base 4.9
+ sleep@Base 4.9
+ snprintf@Base 5
+ socket@Base 4.9
+ socketpair@Base 4.9
+ sprintf@Base 5
+ sscanf@Base 4.9
+ stat64@Base 4.9
+ stat@Base 4.9
+ statfs64@Base 4.9
+ statfs@Base 4.9
+ statvfs64@Base 4.9
+ statvfs@Base 4.9
+ strcasecmp@Base 4.9
+ strcasestr@Base 6
+ strchr@Base 4.9
+ strchrnul@Base 4.9
+ strcmp@Base 4.9
+ strcpy@Base 4.9
+ strcspn@Base 6
+ strdup@Base 4.9
+ strerror@Base 4.9
+ strerror_r@Base 4.9
+ strlen@Base 4.9
+ strncasecmp@Base 4.9
+ strncmp@Base 4.9
+ strncpy@Base 4.9
+ strpbrk@Base 6
+ strptime@Base 4.9
+ strrchr@Base 4.9
+ strspn@Base 6
+ strstr@Base 4.9
+ strtoimax@Base 4.9
+ strtoumax@Base 4.9
+ sysinfo@Base 4.9
+ tcgetattr@Base 4.9
+ tempnam@Base 4.9
+ textdomain@Base 4.9
+ time@Base 4.9
+ timerfd_gettime@Base 5
+ timerfd_settime@Base 5
+ times@Base 4.9
+ tmpfile64@Base 5
+ tmpfile@Base 5
+ tmpnam@Base 4.9
+ tmpnam_r@Base 4.9
+ tsearch@Base 5
+ unlink@Base 4.9
+ usleep@Base 4.9
+ valloc@Base 4.9
+ vasprintf@Base 5
+ vfork@Base 5
+ vfprintf@Base 5
+ vfscanf@Base 4.9
+ vprintf@Base 5
+ vscanf@Base 4.9
+ vsnprintf@Base 5
+ vsprintf@Base 5
+ vsscanf@Base 4.9
+ wait3@Base 4.9
+ wait4@Base 4.9
+ wait@Base 4.9
+ waitid@Base 4.9
+ waitpid@Base 4.9
+ wcrtomb@Base 6
+ wcsnrtombs@Base 4.9
+ wcsrtombs@Base 4.9
+ wcstombs@Base 4.9
+ wordexp@Base 4.9
+ write@Base 4.9
+ writev@Base 4.9
+ xdr_bool@Base 5
+ xdr_bytes@Base 5
+ xdr_char@Base 5
+ xdr_double@Base 5
+ xdr_enum@Base 5
+ xdr_float@Base 5
+ xdr_hyper@Base 5
+ xdr_int16_t@Base 5
+ xdr_int32_t@Base 5
+ xdr_int64_t@Base 5
+ xdr_int8_t@Base 5
+ xdr_int@Base 5
+ xdr_long@Base 5
+ xdr_longlong_t@Base 5
+ xdr_quad_t@Base 5
+ xdr_short@Base 5
+ xdr_string@Base 5
+ xdr_u_char@Base 5
+ xdr_u_hyper@Base 5
+ xdr_u_int@Base 5
+ xdr_u_long@Base 5
+ xdr_u_longlong_t@Base 5
+ xdr_u_quad_t@Base 5
+ xdr_u_short@Base 5
+ xdr_uint16_t@Base 5
+ xdr_uint32_t@Base 5
+ xdr_uint64_t@Base 5
+ xdr_uint8_t@Base 5
+ xdrmem_create@Base 5
+ xdrstdio_create@Base 5
--- gcc-6-6.4.0.orig/debian/libubsan0.symbols
+++ gcc-6-6.4.0/debian/libubsan0.symbols
@@ -0,0 +1,100 @@
+libubsan.so.0 libubsan0 #MINVER#
+ _ZN11__sanitizer11CheckFailedEPKciS1_yy@Base 4.9
+ _ZN11__sanitizer7OnPrintEPKc@Base 4.9
+ __asan_backtrace_alloc@Base 4.9
+ __asan_backtrace_close@Base 4.9
+ __asan_backtrace_create_state@Base 4.9
+ __asan_backtrace_dwarf_add@Base 4.9
+ __asan_backtrace_free@Base 4.9
+ __asan_backtrace_get_view@Base 4.9
+ __asan_backtrace_initialize@Base 4.9
+ __asan_backtrace_open@Base 4.9
+ __asan_backtrace_pcinfo@Base 4.9
+ __asan_backtrace_qsort@Base 4.9
+ __asan_backtrace_release_view@Base 4.9
+ __asan_backtrace_syminfo@Base 4.9
+ __asan_backtrace_vector_finish@Base 4.9
+ __asan_backtrace_vector_grow@Base 4.9
+ __asan_backtrace_vector_release@Base 4.9
+ __asan_cplus_demangle_builtin_types@Base 4.9
+ __asan_cplus_demangle_fill_ctor@Base 4.9
+ __asan_cplus_demangle_fill_dtor@Base 4.9
+ __asan_cplus_demangle_fill_extended_operator@Base 4.9
+ __asan_cplus_demangle_fill_name@Base 4.9
+ __asan_cplus_demangle_init_info@Base 4.9
+ __asan_cplus_demangle_mangled_name@Base 4.9
+ __asan_cplus_demangle_operators@Base 4.9
+ __asan_cplus_demangle_print@Base 4.9
+ __asan_cplus_demangle_print_callback@Base 4.9
+ __asan_cplus_demangle_type@Base 4.9
+ __asan_cplus_demangle_v3@Base 4.9
+ __asan_cplus_demangle_v3_callback@Base 4.9
+ __asan_internal_memcmp@Base 4.9
+ __asan_internal_memcpy@Base 4.9
+ __asan_internal_memset@Base 4.9
+ __asan_internal_strcmp@Base 4.9
+ __asan_internal_strlen@Base 4.9
+ __asan_internal_strncmp@Base 4.9
+ __asan_internal_strnlen@Base 4.9
+ __asan_is_gnu_v3_mangled_ctor@Base 4.9
+ __asan_is_gnu_v3_mangled_dtor@Base 4.9
+ __asan_java_demangle_v3@Base 4.9
+ __asan_java_demangle_v3_callback@Base 4.9
+ __sanitizer_cov@Base 4.9
+ __sanitizer_cov_dump@Base 4.9
+ __sanitizer_cov_indir_call16@Base 5
+ __sanitizer_cov_init@Base 5
+ __sanitizer_cov_module_init@Base 5
+ __sanitizer_cov_trace_basic_block@Base 6
+ __sanitizer_cov_trace_cmp@Base 6
+ __sanitizer_cov_trace_func_enter@Base 6
+ __sanitizer_cov_trace_switch@Base 6
+ __sanitizer_cov_with_check@Base 6
+ __sanitizer_get_coverage_guards@Base 6
+ __sanitizer_get_number_of_counters@Base 6
+ __sanitizer_get_total_unique_caller_callee_pairs@Base 6
+ __sanitizer_get_total_unique_coverage@Base 6
+ __sanitizer_maybe_open_cov_file@Base 5
+ __sanitizer_report_error_summary@Base 4.9
+ __sanitizer_reset_coverage@Base 6
+ __sanitizer_sandbox_on_notify@Base 4.9
+ __sanitizer_set_death_callback@Base 6
+ __sanitizer_set_report_path@Base 4.9
+ __sanitizer_update_counter_bitset_and_clear_counters@Base 6
+ __ubsan_handle_add_overflow@Base 4.9
+ __ubsan_handle_add_overflow_abort@Base 4.9
+ __ubsan_handle_builtin_unreachable@Base 4.9
+ __ubsan_handle_cfi_bad_icall@Base 6
+ __ubsan_handle_cfi_bad_icall_abort@Base 6
+ __ubsan_handle_cfi_bad_type@Base 6
+ __ubsan_handle_cfi_bad_type_abort@Base 6
+ __ubsan_handle_divrem_overflow@Base 4.9
+ __ubsan_handle_divrem_overflow_abort@Base 4.9
+ __ubsan_handle_dynamic_type_cache_miss@Base 4.9
+ __ubsan_handle_dynamic_type_cache_miss_abort@Base 4.9
+ __ubsan_handle_float_cast_overflow@Base 4.9
+ __ubsan_handle_float_cast_overflow_abort@Base 4.9
+ __ubsan_handle_function_type_mismatch@Base 4.9
+ __ubsan_handle_function_type_mismatch_abort@Base 4.9
+ __ubsan_handle_load_invalid_value@Base 4.9
+ __ubsan_handle_load_invalid_value_abort@Base 4.9
+ __ubsan_handle_missing_return@Base 4.9
+ __ubsan_handle_mul_overflow@Base 4.9
+ __ubsan_handle_mul_overflow_abort@Base 4.9
+ __ubsan_handle_negate_overflow@Base 4.9
+ __ubsan_handle_negate_overflow_abort@Base 4.9
+ __ubsan_handle_nonnull_arg@Base 5
+ __ubsan_handle_nonnull_arg_abort@Base 5
+ __ubsan_handle_nonnull_return@Base 5
+ __ubsan_handle_nonnull_return_abort@Base 5
+ __ubsan_handle_out_of_bounds@Base 4.9
+ __ubsan_handle_out_of_bounds_abort@Base 4.9
+ __ubsan_handle_shift_out_of_bounds@Base 4.9
+ __ubsan_handle_shift_out_of_bounds_abort@Base 4.9
+ __ubsan_handle_sub_overflow@Base 4.9
+ __ubsan_handle_sub_overflow_abort@Base 4.9
+ __ubsan_handle_type_mismatch@Base 4.9
+ __ubsan_handle_type_mismatch_abort@Base 4.9
+ __ubsan_handle_vla_bound_not_positive@Base 4.9
+ __ubsan_handle_vla_bound_not_positive_abort@Base 4.9
+ __ubsan_vptr_type_cache@Base 4.9
--- gcc-6-6.4.0.orig/debian/libvtv0.symbols
+++ gcc-6-6.4.0/debian/libvtv0.symbols
@@ -0,0 +1,68 @@
+libvtv.so.0 libvtv0 #MINVER#
+ _Z10__vtv_freePv@Base 4.9.0
+ (arch=amd64)_Z12__vtv_mallocm@Base 4.9.0
+ (arch=i386)_Z12__vtv_mallocj@Base 4.9.0
+ _Z14__VLTDumpStatsv@Base 4.9.0
+ _Z14__vtv_open_logPKc@Base 4.9.0
+ (arch=amd64)_Z16__VLTRegisterSetPPvPKvmmS0_@Base 4.9.0
+ (arch=i386)_Z16__VLTRegisterSetPPvPKvjjS0_@Base 4.9.0
+ _Z16__vtv_add_to_logiPKcz@Base 4.9.0
+ (arch=amd64)_Z17__VLTRegisterPairPPvPKvmS2_@Base 4.9.0
+ (arch=i386)_Z17__VLTRegisterPairPPvPKvjS2_@Base 4.9.0
+ _Z17__vtv_malloc_initv@Base 4.9.0
+ _Z17__vtv_really_failPKc@Base 4.9.0
+ _Z17__vtv_verify_failPPvPKv@Base 4.9.0
+ _Z18__vtv_malloc_statsv@Base 4.9.0
+ _Z20__vtv_malloc_protectv@Base 4.9.0
+ (arch=amd64)_Z21__VLTRegisterSetDebugPPvPKvmmS0_@Base 4.9.0
+ (arch=i386)_Z21__VLTRegisterSetDebugPPvPKvjjS0_@Base 4.9.0
+ (arch=amd64)_Z22__VLTRegisterPairDebugPPvPKvmS2_PKcS4_@Base 4.9.0
+ (arch=i386)_Z22__VLTRegisterPairDebugPPvPKvjS2_PKcS4_@Base 4.9.0
+ _Z22__vtv_malloc_unprotectv@Base 4.9.0
+ _Z23__vtv_malloc_dump_statsv@Base 4.9.0
+ _Z23__vtv_verify_fail_debugPPvPKvPKc@Base 4.9.0
+ (arch=amd64)_Z23search_cached_file_datam@Base 4.9.0
+ (arch=i386)_Z23search_cached_file_dataj@Base 4.9.0
+ _Z24__VLTVerifyVtablePointerPPvPKv@Base 4.9.0
+ _Z25__vtv_count_mmapped_pagesv@Base 4.9.0
+ _Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@Base 4.9.0
+ _Z30__vtv_log_verification_failurePKcb@Base 4.9.0
+ (arch=amd64)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE12put_internalEPKNS8_8key_typeERKS6_b@Base 4.9.0
+ (arch=amd64)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE15find_or_add_keyEPKNS8_8key_typeEPPS6_@Base 4.9.0
+ (arch=amd64)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE16destructive_copyEv@Base 4.9.0
+ (arch=amd64)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE3putEPKNS8_8key_typeERKS6_@Base 4.9.0
+ (arch=amd64)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE6createEm@Base 4.9.0
+ (arch=amd64)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE7destroyEPS8_@Base 4.9.0
+ (arch=amd64)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE11is_too_fullEm@Base 4.9.0
+ (arch=amd64)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE12bucket_countEv@Base 4.9.0
+ (arch=amd64)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE3getEPKNS8_8key_typeE@Base 4.9.0
+ (arch=amd64)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE4sizeEv@Base 4.9.0
+ (arch=amd64)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE5emptyEv@Base 4.9.0
+ (arch=amd64)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIm9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE8key_type6equalsEPKS9_@Base 4.9.0
+ (arch=i386)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE12put_internalEPKNS8_8key_typeERKS6_b@Base 4.9.0
+ (arch=i386)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE15find_or_add_keyEPKNS8_8key_typeEPPS6_@Base 4.9.0
+ (arch=i386)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE16destructive_copyEv@Base 4.9.0
+ (arch=i386)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE3putEPKNS8_8key_typeERKS6_@Base 4.9.0
+ (arch=i386)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE6createEj@Base 4.9.0
+ (arch=i386)_ZN20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE7destroyEPS8_@Base 4.9.0
+ (arch=i386)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE11is_too_fullEj@Base 4.9.0
+ (arch=i386)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE12bucket_countEv@Base 4.9.0
+ (arch=i386)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE3getEPKNS8_8key_typeE@Base 4.9.0
+ (arch=i386)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE4sizeEv@Base 4.9.0
+ (arch=i386)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE5emptyEv@Base 4.9.0
+ (arch=i386)_ZNK20insert_only_hash_mapIPPN21insert_only_hash_setsIj9vptr_hash14vptr_set_allocE20insert_only_hash_setE30insert_only_hash_map_allocatorE8key_type6equalsEPKS9_@Base 4.9.0
+ __VLTChangePermission@Base 4.9.0
+ __VLTprotect@Base 4.9.0
+ __VLTunprotect@Base 4.9.0
+ _vtable_map_vars_end@Base 4.9.0
+ _vtable_map_vars_start@Base 4.9.0
+ mprotect_cycles@Base 4.9.0
+ num_cache_entries@Base 4.9.0
+ num_calls_to_mprotect@Base 4.9.0
+ num_calls_to_regpair@Base 4.9.0
+ num_calls_to_regset@Base 4.9.0
+ num_calls_to_verify_vtable@Base 4.9.0
+ num_pages_protected@Base 4.9.0
+ regpair_cycles@Base 4.9.0
+ regset_cycles@Base 4.9.0
+ verify_vtable_cycles@Base 4.9.0
--- gcc-6-6.4.0.orig/debian/libx32asan3.overrides
+++ gcc-6-6.4.0/debian/libx32asan3.overrides
@@ -0,0 +1,2 @@
+# automake gets it wrong for the multilib build
+libx32asan3 binary: binary-or-shlib-defines-rpath
--- gcc-6-6.4.0.orig/debian/libx32asan3.symbols
+++ gcc-6-6.4.0/debian/libx32asan3.symbols
@@ -0,0 +1,4 @@
+libasan.so.3 libx32asan3 #MINVER#
+#include "libasan.symbols.common"
+#include "libasan.symbols.32"
+#include "libasan.symbols.16"
--- gcc-6-6.4.0.orig/debian/libx32gphobos68.lintian-overrides
+++ gcc-6-6.4.0/debian/libx32gphobos68.lintian-overrides
@@ -0,0 +1,2 @@
+# no multilib zlib for x32
+libx32gphobos68 binary: embedded-library
--- gcc-6-6.4.0.orig/debian/libx32stdc++6.symbols
+++ gcc-6-6.4.0/debian/libx32stdc++6.symbols
@@ -0,0 +1,27 @@
+libstdc++.so.6 libx32stdc++6 #MINVER#
+#include "libstdc++6.symbols.32bit"
+#include "libstdc++6.symbols.128bit"
+#include "libstdc++6.symbols.excprop"
+#include "libstdc++6.symbols.money.ldbl"
+ __gxx_personality_v0@CXXABI_1.3 4.1.1
+ _ZNKSt3tr14hashIeEclEe@GLIBCXX_3.4.10 4.3
+ _ZNKSt4hashIeEclEe@GLIBCXX_3.4.10 4.3
+#(optional)_Z16__VLTRegisterSetPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z17__VLTRegisterPairPPvPKvjS2_@CXXABI_1.3.8 4.9.0
+#(optional)_Z21__VLTRegisterSetDebugPPvPKvjjS0_@CXXABI_1.3.8 4.9.0
+#(optional)_Z22__VLTRegisterPairDebugPPvPKvjS2_PKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)_Z24__VLTVerifyVtablePointerPPvPKv@CXXABI_1.3.8 4.9.0
+#(optional)_Z29__VLTVerifyVtablePointerDebugPPvPKvPKcS4_@CXXABI_1.3.8 4.9.0
+#(optional)__VLTChangePermission@CXXABI_1.3.8 4.9.0
+ _ZTIPKn@CXXABI_1.3.5 4.9.0
+ _ZTIPKo@CXXABI_1.3.5 4.9.0
+ _ZTIPn@CXXABI_1.3.5 4.9.0
+ _ZTIPo@CXXABI_1.3.5 4.9.0
+ _ZTIn@CXXABI_1.3.5 4.9.0
+ _ZTIo@CXXABI_1.3.5 4.9.0
+ _ZTSPKn@CXXABI_1.3.9 4.9.0
+ _ZTSPKo@CXXABI_1.3.9 4.9.0
+ _ZTSPn@CXXABI_1.3.9 4.9.0
+ _ZTSPo@CXXABI_1.3.9 4.9.0
+ _ZTSn@CXXABI_1.3.9 4.9.0
+ _ZTSo@CXXABI_1.3.9 4.9.0
--- gcc-6-6.4.0.orig/debian/locale-gen
+++ gcc-6-6.4.0/debian/locale-gen
@@ -0,0 +1,50 @@
+#!/bin/sh
+
+# generate locales that the libstdc++ testsuite depends on
+
+LOCPATH=`pwd`/locales
+export LOCPATH
+
+[ -d $LOCPATH ] || mkdir -p $LOCPATH
+
+[ -n "$USE_CPUS" ] || USE_CPUS=1
+
+umask 022
+
+echo "Generating locales..."
+xargs -L 1 -P $USE_CPUS -I{} \
+    sh -c '
+	set {}; locale=$1; charset=$2
+	case $locale in \#*) exit;; esac
+	[ -n "$locale" -a -n "$charset" ] || exit
+	echo "  `echo $locale | sed \"s/\([^.\@]*\).*/\1/\"`.$charset`echo $locale | sed \"s/\([^\@]*\)\(\@.*\)*/\2/\"`..."
+        if [ -f $LOCPATH/$locale ]; then
+	    input=$locale
+	else
+            input=`echo $locale | sed "s/\([^.]*\)[^@]*\(.*\)/\1\2/"`
+	fi
+	localedef -i $input -c -f $charset $LOCPATH/$locale #-A /etc/locale.alias
+    ' <<EOF
+de_DE			ISO-8859-1
+de_DE@euro		ISO-8859-15
+en_HK			ISO-8859-1
+en_PH			ISO-8859-1
+en_US			ISO-8859-1
+en_US.ISO-8859-1	ISO-8859-1
+en_US.ISO-8859-15	ISO-8859-15
+en_US.UTF-8		UTF-8
+es_ES			ISO-8859-1
+es_MX			ISO-8859-1
+fr_FR			ISO-8859-1
+fr_FR@euro		ISO-8859-15
+is_IS			ISO-8859-1
+is_IS.UTF-8		UTF-8
+it_IT			ISO-8859-1
+ja_JP.eucjp		EUC-JP
+se_NO.UTF-8		UTF-8
+ta_IN			UTF-8
+zh_TW			BIG5
+zh_TW			UTF-8
+EOF
+
+echo "Generation complete."
--- gcc-6-6.4.0.orig/debian/logwatch.sh
+++ gcc-6-6.4.0/debian/logwatch.sh
@@ -0,0 +1,104 @@
+#! /bin/sh
+
+# script to trick the build daemons and output something, if there is
+# still test/build activity
+
+# $1: primary file to watch. if there is activity on this file, we do nothing
+# $2+: files to watch to look for activity despite no output in $1
+#      if the files are modified or are newly created, then the message
+#      is printed on stdout.
+#      if nothing is modified, don't output anything (so the buildd timeout
+#      hits).
+
+pidfile=logwatch.pid
+timeout=3600
+message='\nlogwatch still running\n'
+
+usage()
+{
+    echo >&2 "usage: `basename $0` [-p <pidfile>] [-t <timeout>] [-m <message>]"
+    echo >&2 "           <logfile> [<logfile> ...]"
+    exit 1
+}
+
+while [ $# -gt 0 ]; do
+    case $1 in
+    -p)
+	pidfile=$2
+	shift
+	shift
+	;;
+    -t)
+	timeout=$2
+	shift
+	shift
+	;;
+    -m)
+	message="$2"
+	shift
+	shift
+	;;
+    -*)
+	usage
+	;;
+    *)
+	break
+    esac
+done
+
+[ $# -gt 0 ] || usage
+
+logfile="$1"
+shift
+otherlogs="$@"
+
+cleanup()
+{
+    rm -f $pidfile
+    exit 0
+}
+
+#trap cleanup 0 1 3 15
+
+echo $$ > $pidfile
+
+update()
+{
+    _logvar=$1
+    _othervar=$2
+
+    # logfile may not exist yet
+    if [ -r $logfile ]; then
+	_logtail="`tail -10 $logfile | md5sum` $f"
+    else
+	_logtail="does not exist: $logfile"
+    fi
+    eval $_logvar="'$_logtail'"
+
+    _othertails=''
+    for f in $otherlogs; do
+	if [ -r $f ]; then
+	    _othertails="$_othertails `tail -10 $f | md5sum` $f"
+	else
+	    _othertails="$_othertails does not exist: $f"
+	fi
+    done
+    eval $_othervar="'$_othertails'"
+}
+
+update logtail othertails
+while true; do
+    sleep $timeout
+    update newlogtail newothertails
+    if [ "$logtail" != "$newlogtail" ]; then
+	# there is still action in the primary logfile. do nothing.
+	logtail="$newlogtail"
+    elif [ "$othertails" != "$newothertails" ]; then
+	# there is still action in the other log files, so print the message
+	/bin/echo -e $message
+	othertails="$newothertails"
+    else
+	# nothing changed in the other log files. maybe a timeout ...
+	:
+    fi
+done
--- gcc-6-6.4.0.orig/debian/patches/0001-i386-Move-struct-ix86_frame-to-machine_function.diff
+++ gcc-6-6.4.0/debian/patches/0001-i386-Move-struct-ix86_frame-to-machine_function.diff
@@ -0,0 +1,241 @@
+From bc4dce5559f2a8cc319b2c44f893d00c67b7842e Mon Sep 17 00:00:00 2001
+From: hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Mon, 15 Jan 2018 11:27:24 +0000
+Subject: [PATCH] i386: Move struct ix86_frame to machine_function
+
+Make ix86_frame available to i386 code generation.  This is needed to
+backport the patch set of -mindirect-branch= to mitigate variant #2 of
+the speculative execution vulnerabilities on x86 processors identified
+by CVE-2017-5715, aka Spectre.
+
+	Backport from mainline
+	2017-06-01  Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	* config/i386/i386.c (ix86_frame): Moved to ...
+	* config/i386/i386.h (ix86_frame): Here.
+	(machine_function): Add frame.
+	* config/i386/i386.c (ix86_compute_frame_layout): Repace the
+	frame argument with &cfun->machine->frame.
+	(ix86_can_use_return_insn_p): Don't pass &frame to
+	ix86_compute_frame_layout.  Copy frame from cfun->machine->frame.
+	(ix86_can_eliminate): Likewise.
+	(ix86_expand_prologue): Likewise.
+	(ix86_expand_epilogue): Likewise.
+	(ix86_expand_split_stack_prologue): Likewise.
+---
+ gcc/config/i386/i386.c | 68 ++++++++++----------------------------------------
+ gcc/config/i386/i386.h | 53 ++++++++++++++++++++++++++++++++++++++-
+ 2 files changed, 65 insertions(+), 56 deletions(-)
+
+diff --git a/src/gcc/config/i386/i386.c b/src/gcc/config/i386/i386.c
+index 8b5faac51..a1ff32b64 100644
+--- a/src/gcc/config/i386/i386.c
++++ b/src/gcc/config/i386/i386.c
+@@ -2434,53 +2434,6 @@ struct GTY(()) stack_local_entry {
+   struct stack_local_entry *next;
+ };
+ 
+-/* Structure describing stack frame layout.
+-   Stack grows downward:
+-
+-   [arguments]
+-					<- ARG_POINTER
+-   saved pc
+-
+-   saved static chain			if ix86_static_chain_on_stack
+-
+-   saved frame pointer			if frame_pointer_needed
+-					<- HARD_FRAME_POINTER
+-   [saved regs]
+-					<- regs_save_offset
+-   [padding0]
+-
+-   [saved SSE regs]
+-					<- sse_regs_save_offset
+-   [padding1]          |
+-		       |		<- FRAME_POINTER
+-   [va_arg registers]  |
+-		       |
+-   [frame]	       |
+-		       |
+-   [padding2]	       | = to_allocate
+-					<- STACK_POINTER
+-  */
+-struct ix86_frame
+-{
+-  int nsseregs;
+-  int nregs;
+-  int va_arg_size;
+-  int red_zone_size;
+-  int outgoing_arguments_size;
+-
+-  /* The offsets relative to ARG_POINTER.  */
+-  HOST_WIDE_INT frame_pointer_offset;
+-  HOST_WIDE_INT hard_frame_pointer_offset;
+-  HOST_WIDE_INT stack_pointer_offset;
+-  HOST_WIDE_INT hfp_save_offset;
+-  HOST_WIDE_INT reg_save_offset;
+-  HOST_WIDE_INT sse_reg_save_offset;
+-
+-  /* When save_regs_using_mov is set, emit prologue using
+-     move instead of push instructions.  */
+-  bool save_regs_using_mov;
+-};
+-
+ /* Which cpu are we scheduling for.  */
+ enum attr_cpu ix86_schedule;
+ 
+@@ -2572,7 +2525,7 @@ static unsigned int ix86_function_arg_boundary (machine_mode,
+ 						const_tree);
+ static rtx ix86_static_chain (const_tree, bool);
+ static int ix86_function_regparm (const_tree, const_tree);
+-static void ix86_compute_frame_layout (struct ix86_frame *);
++static void ix86_compute_frame_layout (void);
+ static bool ix86_expand_vector_init_one_nonzero (bool, machine_mode,
+ 						 rtx, rtx, int);
+ static void ix86_add_new_builtins (HOST_WIDE_INT);
+@@ -10944,7 +10897,8 @@ ix86_can_use_return_insn_p (void)
+   if (crtl->args.pops_args && crtl->args.size >= 32768)
+     return 0;
+ 
+-  ix86_compute_frame_layout (&frame);
++  ix86_compute_frame_layout ();
++  frame = cfun->machine->frame;
+   return (frame.stack_pointer_offset == UNITS_PER_WORD
+ 	  && (frame.nregs + frame.nsseregs) == 0);
+ }
+@@ -11355,8 +11309,8 @@ ix86_can_eliminate (const int from, const int to)
+ HOST_WIDE_INT
+ ix86_initial_elimination_offset (int from, int to)
+ {
+-  struct ix86_frame frame;
+-  ix86_compute_frame_layout (&frame);
++  ix86_compute_frame_layout ();
++  struct ix86_frame frame = cfun->machine->frame;
+ 
+   if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
+     return frame.hard_frame_pointer_offset;
+@@ -11395,8 +11349,9 @@ ix86_builtin_setjmp_frame_value (void)
+ /* Fill structure ix86_frame about frame of currently computed function.  */
+ 
+ static void
+-ix86_compute_frame_layout (struct ix86_frame *frame)
++ix86_compute_frame_layout (void)
+ {
++  struct ix86_frame *frame = &cfun->machine->frame;
+   unsigned HOST_WIDE_INT stack_alignment_needed;
+   HOST_WIDE_INT offset;
+   unsigned HOST_WIDE_INT preferred_alignment;
+@@ -12702,7 +12657,8 @@ ix86_expand_prologue (void)
+   m->fs.sp_offset = INCOMING_FRAME_SP_OFFSET;
+   m->fs.sp_valid = true;
+ 
+-  ix86_compute_frame_layout (&frame);
++  ix86_compute_frame_layout ();
++  frame = m->frame;
+ 
+   if (!TARGET_64BIT && ix86_function_ms_hook_prologue (current_function_decl))
+     {
+@@ -13379,7 +13335,8 @@ ix86_expand_epilogue (int style)
+   bool using_drap;
+ 
+   ix86_finalize_stack_realign_flags ();
+-  ix86_compute_frame_layout (&frame);
++  ix86_compute_frame_layout ();
++  frame = m->frame;
+ 
+   m->fs.sp_valid = (!frame_pointer_needed
+ 		    || (crtl->sp_is_unchanging
+@@ -13876,7 +13833,8 @@ ix86_expand_split_stack_prologue (void)
+   gcc_assert (flag_split_stack && reload_completed);
+ 
+   ix86_finalize_stack_realign_flags ();
+-  ix86_compute_frame_layout (&frame);
++  ix86_compute_frame_layout ();
++  frame = cfun->machine->frame;
+   allocate = frame.stack_pointer_offset - INCOMING_FRAME_SP_OFFSET;
+ 
+   /* This is the label we will branch to if we have enough stack
+diff --git a/src/gcc/config/i386/i386.h b/src/gcc/config/i386/i386.h
+index 8113f83c7..541441661 100644
+--- a/src/gcc/config/i386/i386.h
++++ b/src/gcc/config/i386/i386.h
+@@ -2427,9 +2427,56 @@ enum avx_u128_state
+ 
+ #define FASTCALL_PREFIX '@'
+ 
++#ifndef USED_FOR_TARGET
++/* Structure describing stack frame layout.
++   Stack grows downward:
++
++   [arguments]
++					<- ARG_POINTER
++   saved pc
++
++   saved static chain			if ix86_static_chain_on_stack
++
++   saved frame pointer			if frame_pointer_needed
++					<- HARD_FRAME_POINTER
++   [saved regs]
++					<- regs_save_offset
++   [padding0]
++
++   [saved SSE regs]
++					<- sse_regs_save_offset
++   [padding1]          |
++		       |		<- FRAME_POINTER
++   [va_arg registers]  |
++		       |
++   [frame]	       |
++		       |
++   [padding2]	       | = to_allocate
++					<- STACK_POINTER
++  */
++struct GTY(()) ix86_frame
++{
++  int nsseregs;
++  int nregs;
++  int va_arg_size;
++  int red_zone_size;
++  int outgoing_arguments_size;
++
++  /* The offsets relative to ARG_POINTER.  */
++  HOST_WIDE_INT frame_pointer_offset;
++  HOST_WIDE_INT hard_frame_pointer_offset;
++  HOST_WIDE_INT stack_pointer_offset;
++  HOST_WIDE_INT hfp_save_offset;
++  HOST_WIDE_INT reg_save_offset;
++  HOST_WIDE_INT sse_reg_save_offset;
++
++  /* When save_regs_using_mov is set, emit prologue using
++     move instead of push instructions.  */
++  bool save_regs_using_mov;
++};
++
+ /* Machine specific frame tracking during prologue/epilogue generation.  */
+ 
+-#ifndef USED_FOR_TARGET
+ struct GTY(()) machine_frame_state
+ {
+   /* This pair tracks the currently active CFA as reg+offset.  When reg
+@@ -2475,6 +2522,9 @@ struct GTY(()) machine_function {
+   int varargs_fpr_size;
+   int optimize_mode_switching[MAX_386_ENTITIES];
+ 
++  /* Cached initial frame layout for the current function.  */
++  struct ix86_frame frame;
++
+   /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE
+      has been computed for.  */
+   int use_fast_prologue_epilogue_nregs;
+@@ -2554,6 +2604,7 @@ struct GTY(()) machine_function {
+ #define ix86_current_function_calls_tls_descriptor \
+   (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
+ #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
++#define ix86_red_zone_size (cfun->machine->frame.red_zone_size)
+ 
+ /* Control behavior of x86_file_start.  */
+ #define X86_FILE_START_VERSION_DIRECTIVE false
+-- 
+2.16.1
+
--- gcc-6-6.4.0.orig/debian/patches/0002-i386-Use-reference-of-struct-ix86_frame-to-avoid-copy.diff
+++ gcc-6-6.4.0/debian/patches/0002-i386-Use-reference-of-struct-ix86_frame-to-avoid-copy.diff
@@ -0,0 +1,69 @@
+From 4ba8249ec4d94a57870f56be36d2dc88f43d9ec7 Mon Sep 17 00:00:00 2001
+From: hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Mon, 15 Jan 2018 11:28:44 +0000
+Subject: [PATCH] i386: Use reference of struct ix86_frame to avoid copy
+
+When there is no need to make a copy of ix86_frame, we can use reference
+of struct ix86_frame to avoid copy.
+
+	Backport from mainline
+	2017-11-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/i386.c (ix86_can_use_return_insn_p): Use reference
+	of struct ix86_frame.
+	(ix86_initial_elimination_offset): Likewise.
+	(ix86_expand_split_stack_prologue): Likewise.
+---
+ gcc/config/i386/i386.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/src/gcc/config/i386/i386.c b/src/gcc/config/i386/i386.c
+index a1ff32b64..13ebf107e 100644
+--- a/src/gcc/config/i386/i386.c
++++ b/src/gcc/config/i386/i386.c
+@@ -10887,7 +10887,6 @@ symbolic_reference_mentioned_p (rtx op)
+ bool
+ ix86_can_use_return_insn_p (void)
+ {
+-  struct ix86_frame frame;
+ 
+   if (! reload_completed || frame_pointer_needed)
+     return 0;
+@@ -10898,7 +10897,7 @@ ix86_can_use_return_insn_p (void)
+     return 0;
+ 
+   ix86_compute_frame_layout ();
+-  frame = cfun->machine->frame;
++  struct ix86_frame &frame = cfun->machine->frame;
+   return (frame.stack_pointer_offset == UNITS_PER_WORD
+ 	  && (frame.nregs + frame.nsseregs) == 0);
+ }
+@@ -11310,7 +11309,7 @@ HOST_WIDE_INT
+ ix86_initial_elimination_offset (int from, int to)
+ {
+   ix86_compute_frame_layout ();
+-  struct ix86_frame frame = cfun->machine->frame;
++  struct ix86_frame &frame = cfun->machine->frame;
+ 
+   if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
+     return frame.hard_frame_pointer_offset;
+@@ -13821,7 +13820,6 @@ static GTY(()) rtx split_stack_fn_large;
+ void
+ ix86_expand_split_stack_prologue (void)
+ {
+-  struct ix86_frame frame;
+   HOST_WIDE_INT allocate;
+   unsigned HOST_WIDE_INT args_size;
+   rtx_code_label *label;
+@@ -13834,7 +13832,7 @@ ix86_expand_split_stack_prologue (void)
+ 
+   ix86_finalize_stack_realign_flags ();
+   ix86_compute_frame_layout ();
+-  frame = cfun->machine->frame;
++  struct ix86_frame &frame = cfun->machine->frame;
+   allocate = frame.stack_pointer_offset - INCOMING_FRAME_SP_OFFSET;
+ 
+   /* This is the label we will branch to if we have enough stack
+-- 
+2.16.1
+
--- gcc-6-6.4.0.orig/debian/patches/0003-i386-Use-const-reference-of-struct-ix86_frame-to-avoi.diff
+++ gcc-6-6.4.0/debian/patches/0003-i386-Use-const-reference-of-struct-ix86_frame-to-avoi.diff
@@ -0,0 +1,125 @@
+From 198a682bc589496613fb13519f10f9fff11888d3 Mon Sep 17 00:00:00 2001
+From: hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Sat, 27 Jan 2018 13:10:24 +0000
+Subject: [PATCH] i386: Use const reference of struct ix86_frame to avoid copy
+
+We can use const reference of struct ix86_frame to avoid making a local
+copy of ix86_frame.  ix86_expand_epilogue makes a local copy of struct
+ix86_frame and uses the reg_save_offset field as a local variable.  This
+patch uses a separate local variable for reg_save_offset.
+
+Tested on x86-64 with ada.
+
+	Backport from mainline
+	PR target/83905
+	* config/i386/i386.c (ix86_expand_prologue): Use cost reference
+	of struct ix86_frame.
+	(ix86_expand_epilogue): Likewise.  Add a local variable for
+	the reg_save_offset field in struct ix86_frame.
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-7-branch@257123 138bc75d-0d04-0410-961f-82ee72b054a4
+---
+ gcc/config/i386/i386.c | 24 ++++++++++++------------
+ 1 file changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/src/gcc/config/i386/i386.c b/src/gcc/config/i386/i386.c
+index 13ebf107e..6c98f7581 100644
+--- a/src/gcc/config/i386/i386.c
++++ b/src/gcc/config/i386/i386.c
+@@ -12633,7 +12633,6 @@ ix86_expand_prologue (void)
+ {
+   struct machine_function *m = cfun->machine;
+   rtx insn, t;
+-  struct ix86_frame frame;
+   HOST_WIDE_INT allocate;
+   bool int_registers_saved;
+   bool sse_registers_saved;
+@@ -12657,7 +12656,7 @@ ix86_expand_prologue (void)
+   m->fs.sp_valid = true;
+ 
+   ix86_compute_frame_layout ();
+-  frame = m->frame;
++  const struct ix86_frame &frame = cfun->machine->frame;
+ 
+   if (!TARGET_64BIT && ix86_function_ms_hook_prologue (current_function_decl))
+     {
+@@ -13329,13 +13328,12 @@ ix86_expand_epilogue (int style)
+ {
+   struct machine_function *m = cfun->machine;
+   struct machine_frame_state frame_state_save = m->fs;
+-  struct ix86_frame frame;
+   bool restore_regs_via_mov;
+   bool using_drap;
+ 
+   ix86_finalize_stack_realign_flags ();
+   ix86_compute_frame_layout ();
+-  frame = m->frame;
++  const struct ix86_frame &frame = cfun->machine->frame;
+ 
+   m->fs.sp_valid = (!frame_pointer_needed
+ 		    || (crtl->sp_is_unchanging
+@@ -13377,11 +13375,13 @@ ix86_expand_epilogue (int style)
+ 				  + UNITS_PER_WORD);
+     }
+ 
++  HOST_WIDE_INT reg_save_offset = frame.reg_save_offset;
++
+   /* Special care must be taken for the normal return case of a function
+      using eh_return: the eax and edx registers are marked as saved, but
+      not restored along this path.  Adjust the save location to match.  */
+   if (crtl->calls_eh_return && style != 2)
+-    frame.reg_save_offset -= 2 * UNITS_PER_WORD;
++    reg_save_offset -= 2 * UNITS_PER_WORD;
+ 
+   /* EH_RETURN requires the use of moves to function properly.  */
+   if (crtl->calls_eh_return)
+@@ -13397,11 +13397,11 @@ ix86_expand_epilogue (int style)
+   else if (TARGET_EPILOGUE_USING_MOVE
+ 	   && cfun->machine->use_fast_prologue_epilogue
+ 	   && (frame.nregs > 1
+-	       || m->fs.sp_offset != frame.reg_save_offset))
++	       || m->fs.sp_offset != reg_save_offset))
+     restore_regs_via_mov = true;
+   else if (frame_pointer_needed
+ 	   && !frame.nregs
+-	   && m->fs.sp_offset != frame.reg_save_offset)
++	   && m->fs.sp_offset != reg_save_offset)
+     restore_regs_via_mov = true;
+   else if (frame_pointer_needed
+ 	   && TARGET_USE_LEAVE
+@@ -13439,7 +13439,7 @@ ix86_expand_epilogue (int style)
+       rtx t;
+ 
+       if (frame.nregs)
+-	ix86_emit_restore_regs_using_mov (frame.reg_save_offset, style == 2);
++	ix86_emit_restore_regs_using_mov (reg_save_offset, style == 2);
+ 
+       /* eh_return epilogues need %ecx added to the stack pointer.  */
+       if (style == 2)
+@@ -13529,19 +13529,19 @@ ix86_expand_epilogue (int style)
+ 	 epilogues.  */
+       if (!m->fs.sp_valid
+  	  || (TARGET_SEH
+-	      && (m->fs.sp_offset - frame.reg_save_offset
++	      && (m->fs.sp_offset - reg_save_offset
+ 		  >= SEH_MAX_FRAME_SIZE)))
+ 	{
+ 	  pro_epilogue_adjust_stack (stack_pointer_rtx, hard_frame_pointer_rtx,
+ 				     GEN_INT (m->fs.fp_offset
+-					      - frame.reg_save_offset),
++					      - reg_save_offset),
+ 				     style, false);
+ 	}
+-      else if (m->fs.sp_offset != frame.reg_save_offset)
++      else if (m->fs.sp_offset != reg_save_offset)
+ 	{
+ 	  pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
+ 				     GEN_INT (m->fs.sp_offset
+-					      - frame.reg_save_offset),
++					      - reg_save_offset),
+ 				     style,
+ 				     m->fs.cfa_reg == stack_pointer_rtx);
+ 	}
+-- 
+2.16.1
+
--- gcc-6-6.4.0.orig/debian/patches/0004-x86-Add-mindirect-branch.diff
+++ gcc-6-6.4.0/debian/patches/0004-x86-Add-mindirect-branch.diff
@@ -0,0 +1,2093 @@
+From 4d22193f5780c6ae47bc879f28fa0ec5081ea748 Mon Sep 17 00:00:00 2001
+From: "H.J. Lu" <hjl.tools@gmail.com>
+Date: Sat, 6 Jan 2018 22:29:55 -0800
+Subject: [PATCH] x86: Add -mindirect-branch=
+
+Add -mindirect-branch= option to convert indirect call and jump to call
+and return thunks.  The default is 'keep', which keeps indirect call and
+jump unmodified.  'thunk' converts indirect call and jump to call and
+return thunk.  'thunk-inline' converts indirect call and jump to inlined
+call and return thunk.  'thunk-extern' converts indirect call and jump to
+external call and return thunk provided in a separate object file.  You
+can control this behavior for a specific function by using the function
+attribute indirect_branch.
+
+2 kinds of thunks are geneated.  Memory thunk where the function address
+is at the top of the stack:
+
+__x86_indirect_thunk:
+	call L2
+L1:
+	pause
+	lfence
+	jmp L1
+L2:
+	lea 8(%rsp), %rsp|lea 4(%esp), %esp
+	ret
+
+Indirect jmp via memory, "jmp mem", is converted to
+
+	push memory
+	jmp __x86_indirect_thunk
+
+Indirect call via memory, "call mem", is converted to
+
+	jmp L2
+L1:
+	push [mem]
+	jmp __x86_indirect_thunk
+L2:
+	call L1
+
+Register thunk where the function address is in a register, reg:
+
+__x86_indirect_thunk_reg:
+	call	L2
+L1:
+	pause
+	lfence
+	jmp	L1
+L2:
+	movq	%reg, (%rsp)|movl    %reg, (%esp)
+	ret
+
+where reg is one of (r|e)ax, (r|e)dx, (r|e)cx, (r|e)bx, (r|e)si, (r|e)di,
+(r|e)bp, r8, r9, r10, r11, r12, r13, r14 and r15.
+
+Indirect jmp via register, "jmp reg", is converted to
+
+	jmp __x86_indirect_thunk_reg
+
+Indirect call via register, "call reg", is converted to
+
+	call __x86_indirect_thunk_reg
+
+gcc/
+
+	Backport from mainline
+	2018-01-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/i386-opts.h (indirect_branch): New.
+	* config/i386/i386-protos.h (ix86_output_indirect_jmp): Likewise.
+	* config/i386/i386.c (ix86_using_red_zone): Disallow red-zone
+	with local indirect jump when converting indirect call and jump.
+	(ix86_set_indirect_branch_type): New.
+	(ix86_set_current_function): Call ix86_set_indirect_branch_type.
+	(indirectlabelno): New.
+	(indirect_thunk_needed): Likewise.
+	(indirect_thunk_bnd_needed): Likewise.
+	(indirect_thunks_used): Likewise.
+	(indirect_thunks_bnd_used): Likewise.
+	(INDIRECT_LABEL): Likewise.
+	(indirect_thunk_name): Likewise.
+	(output_indirect_thunk): Likewise.
+	(output_indirect_thunk_function): Likewise.
+	(ix86_output_indirect_branch_via_reg): Likewise.
+	(ix86_output_indirect_branch_via_push): Likewise.
+	(ix86_output_indirect_branch): Likewise.
+	(ix86_output_indirect_jmp): Likewise.
+	(ix86_code_end): Call output_indirect_thunk_function if needed.
+	(ix86_output_call_insn): Call ix86_output_indirect_branch if
+	needed.
+	(ix86_handle_fndecl_attribute): Handle indirect_branch.
+	(ix86_attribute_table): Add indirect_branch.
+	* config/i386/i386.h (machine_function): Add indirect_branch_type
+	and has_local_indirect_jump.
+	* config/i386/i386.md (indirect_jump): Set has_local_indirect_jump
+	to true.
+	(tablejump): Likewise.
+	(*indirect_jump): Use ix86_output_indirect_jmp.
+	(*tablejump_1): Likewise.
+	(simple_return_indirect_internal): Likewise.
+	* config/i386/i386.opt (mindirect-branch=): New option.
+	(indirect_branch): New.
+	(keep): Likewise.
+	(thunk): Likewise.
+	(thunk-inline): Likewise.
+	(thunk-extern): Likewise.
+
+gcc/testsuite/
+
+	Backport from mainline
+	2018-01-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gcc.target/i386/indirect-thunk-1.c: New test.
+	* gcc.target/i386/indirect-thunk-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-5.c: Likewise.
+	* gcc.target/i386/indirect-thunk-6.c: Likewise.
+	* gcc.target/i386/indirect-thunk-7.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-5.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-6.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-7.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-8.c: Likewise.
+	* gcc.target/i386/indirect-thunk-bnd-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-bnd-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-bnd-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-bnd-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-5.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-6.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-7.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-5.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-6.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-7.c: Likewise.
+---
+ gcc/config/i386/i386-opts.h                        |  13 +
+ gcc/config/i386/i386-protos.h                      |   1 +
+ gcc/config/i386/i386.c                             | 639 ++++++++++++++++++++-
+ gcc/config/i386/i386.h                             |   7 +
+ gcc/config/i386/i386.md                            |  26 +-
+ gcc/config/i386/i386.opt                           |  20 +
+ gcc/testsuite/gcc.target/i386/indirect-thunk-1.c   |  20 +
+ gcc/testsuite/gcc.target/i386/indirect-thunk-2.c   |  20 +
+ gcc/testsuite/gcc.target/i386/indirect-thunk-3.c   |  21 +
+ gcc/testsuite/gcc.target/i386/indirect-thunk-4.c   |  21 +
+ gcc/testsuite/gcc.target/i386/indirect-thunk-5.c   |  17 +
+ gcc/testsuite/gcc.target/i386/indirect-thunk-6.c   |  18 +
+ gcc/testsuite/gcc.target/i386/indirect-thunk-7.c   |  44 ++
+ .../gcc.target/i386/indirect-thunk-attr-1.c        |  23 +
+ .../gcc.target/i386/indirect-thunk-attr-2.c        |  21 +
+ .../gcc.target/i386/indirect-thunk-attr-3.c        |  23 +
+ .../gcc.target/i386/indirect-thunk-attr-4.c        |  22 +
+ .../gcc.target/i386/indirect-thunk-attr-5.c        |  22 +
+ .../gcc.target/i386/indirect-thunk-attr-6.c        |  21 +
+ .../gcc.target/i386/indirect-thunk-attr-7.c        |  44 ++
+ .../gcc.target/i386/indirect-thunk-attr-8.c        |  42 ++
+ .../gcc.target/i386/indirect-thunk-bnd-1.c         |  20 +
+ .../gcc.target/i386/indirect-thunk-bnd-2.c         |  21 +
+ .../gcc.target/i386/indirect-thunk-bnd-3.c         |  19 +
+ .../gcc.target/i386/indirect-thunk-bnd-4.c         |  20 +
+ .../gcc.target/i386/indirect-thunk-extern-1.c      |  19 +
+ .../gcc.target/i386/indirect-thunk-extern-2.c      |  19 +
+ .../gcc.target/i386/indirect-thunk-extern-3.c      |  20 +
+ .../gcc.target/i386/indirect-thunk-extern-4.c      |  20 +
+ .../gcc.target/i386/indirect-thunk-extern-5.c      |  16 +
+ .../gcc.target/i386/indirect-thunk-extern-6.c      |  17 +
+ .../gcc.target/i386/indirect-thunk-extern-7.c      |  43 ++
+ .../gcc.target/i386/indirect-thunk-inline-1.c      |  20 +
+ .../gcc.target/i386/indirect-thunk-inline-2.c      |  20 +
+ .../gcc.target/i386/indirect-thunk-inline-3.c      |  21 +
+ .../gcc.target/i386/indirect-thunk-inline-4.c      |  21 +
+ .../gcc.target/i386/indirect-thunk-inline-5.c      |  17 +
+ .../gcc.target/i386/indirect-thunk-inline-6.c      |  18 +
+ .../gcc.target/i386/indirect-thunk-inline-7.c      |  44 ++
+ 41 files changed, 1486 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-1.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-2.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-3.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-4.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-5.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-6.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-7.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-attr-8.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-1.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-2.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-3.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-4.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-extern-5.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-extern-6.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-inline-5.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-inline-6.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-inline-7.c
+
+diff --git a/src/gcc/config/i386/i386-opts.h b/src/gcc/config/i386/i386-opts.h
+index b7f92e3be..cc2115287 100644
+--- a/src/gcc/config/i386/i386-opts.h
++++ b/src/gcc/config/i386/i386-opts.h
+@@ -99,4 +99,17 @@ enum stack_protector_guard {
+   SSP_GLOBAL    /* global canary */
+ };
+ 
++/* This is used to mitigate variant #2 of the speculative execution
++   vulnerabilities on x86 processors identified by CVE-2017-5715, aka
++   Spectre.  They convert indirect branches and function returns to
++   call and return thunks to avoid speculative execution via indirect
++   call, jmp and ret.  */
++enum indirect_branch {
++  indirect_branch_unset = 0,
++  indirect_branch_keep,
++  indirect_branch_thunk,
++  indirect_branch_thunk_inline,
++  indirect_branch_thunk_extern
++};
++
+ #endif
+diff --git a/src/gcc/config/i386/i386-protos.h b/src/gcc/config/i386/i386-protos.h
+index ff47bc156..eca4cbf07 100644
+--- a/src/gcc/config/i386/i386-protos.h
++++ b/src/gcc/config/i386/i386-protos.h
+@@ -311,6 +311,7 @@ extern enum attr_cpu ix86_schedule;
+ #endif
+ 
+ extern const char * ix86_output_call_insn (rtx_insn *insn, rtx call_op);
++extern const char * ix86_output_indirect_jmp (rtx call_op, bool ret_p);
+ extern bool ix86_operands_ok_for_move_multiple (rtx *operands, bool load,
+ 						enum machine_mode mode);
+ 
+diff --git a/src/gcc/config/i386/i386.c b/src/gcc/config/i386/i386.c
+index 6c98f7581..0b9fc4d30 100644
+--- a/src/gcc/config/i386/i386.c
++++ b/src/gcc/config/i386/i386.c
+@@ -3662,12 +3662,23 @@ make_pass_stv (gcc::context *ctxt)
+   return new pass_stv (ctxt);
+ }
+ 
+-/* Return true if a red-zone is in use.  */
++/* Return true if a red-zone is in use.  We can't use red-zone when
++   there are local indirect jumps, like "indirect_jump" or "tablejump",
++   which jumps to another place in the function, since "call" in the
++   indirect thunk pushes the return address onto stack, destroying
++   red-zone.
++
++   TODO: If we can reserve the first 2 WORDs, for PUSH and, another
++   for CALL, in red-zone, we can allow local indirect jumps with
++   indirect thunk.  */
+ 
+ bool
+ ix86_using_red_zone (void)
+ {
+-  return TARGET_RED_ZONE && !TARGET_64BIT_MS_ABI;
++  return (TARGET_RED_ZONE
++	  && !TARGET_64BIT_MS_ABI
++	  && (!cfun->machine->has_local_indirect_jump
++	      || cfun->machine->indirect_branch_type == indirect_branch_keep));
+ }
+ 
+ /* Return a string that documents the current -m options.  The caller is
+@@ -6350,6 +6361,37 @@ ix86_reset_previous_fndecl (void)
+   ix86_previous_fndecl = NULL_TREE;
+ }
+ 
++/* Set the indirect_branch_type field from the function FNDECL.  */
++
++static void
++ix86_set_indirect_branch_type (tree fndecl)
++{
++  if (cfun->machine->indirect_branch_type == indirect_branch_unset)
++    {
++      tree attr = lookup_attribute ("indirect_branch",
++				    DECL_ATTRIBUTES (fndecl));
++      if (attr != NULL)
++	{
++	  tree args = TREE_VALUE (attr);
++	  if (args == NULL)
++	    gcc_unreachable ();
++	  tree cst = TREE_VALUE (args);
++	  if (strcmp (TREE_STRING_POINTER (cst), "keep") == 0)
++	    cfun->machine->indirect_branch_type = indirect_branch_keep;
++	  else if (strcmp (TREE_STRING_POINTER (cst), "thunk") == 0)
++	    cfun->machine->indirect_branch_type = indirect_branch_thunk;
++	  else if (strcmp (TREE_STRING_POINTER (cst), "thunk-inline") == 0)
++	    cfun->machine->indirect_branch_type = indirect_branch_thunk_inline;
++	  else if (strcmp (TREE_STRING_POINTER (cst), "thunk-extern") == 0)
++	    cfun->machine->indirect_branch_type = indirect_branch_thunk_extern;
++	  else
++	    gcc_unreachable ();
++	}
++      else
++	cfun->machine->indirect_branch_type = ix86_indirect_branch;
++    }
++}
++
+ /* Establish appropriate back-end context for processing the function
+    FNDECL.  The argument might be NULL to indicate processing at top
+    level, outside of any function scope.  */
+@@ -6360,7 +6402,13 @@ ix86_set_current_function (tree fndecl)
+      several times in the course of compiling a function, and we don't want to
+      slow things down too much or call target_reinit when it isn't safe.  */
+   if (fndecl == ix86_previous_fndecl)
+-    return;
++    {
++      /* There may be 2 function bodies for the same function FNDECL,
++	 one is extern inline and one isn't.  */
++      if (fndecl != NULL_TREE)
++	ix86_set_indirect_branch_type (fndecl);
++      return;
++    }
+ 
+   tree old_tree;
+   if (ix86_previous_fndecl == NULL_TREE)
+@@ -6377,6 +6425,8 @@ ix86_set_current_function (tree fndecl)
+       return;
+     }
+ 
++  ix86_set_indirect_branch_type (fndecl);
++
+   tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
+   if (new_tree == NULL_TREE)
+     new_tree = target_option_default_node;
+@@ -10962,6 +11012,220 @@ ix86_setup_frame_addresses (void)
+ # endif
+ #endif
+ 
++/* Label count for call and return thunks.  It is used to make unique
++   labels in call and return thunks.  */
++static int indirectlabelno;
++
++/* True if call and return thunk functions are needed.  */
++static bool indirect_thunk_needed = false;
++/* True if call and return thunk functions with the BND prefix are
++   needed.  */
++static bool indirect_thunk_bnd_needed = false;
++
++/* Bit masks of integer registers, which contain branch target, used
++   by call and return thunks functions.  */
++static int indirect_thunks_used;
++/* Bit masks of integer registers, which contain branch target, used
++   by call and return thunks functions with the BND prefix.  */
++static int indirect_thunks_bnd_used;
++
++#ifndef INDIRECT_LABEL
++# define INDIRECT_LABEL "LIND"
++#endif
++
++/* Fills in the label name that should be used for the indirect thunk.  */
++
++static void
++indirect_thunk_name (char name[32], int regno, bool need_bnd_p)
++{
++  if (USE_HIDDEN_LINKONCE)
++    {
++      const char *bnd = need_bnd_p ? "_bnd" : "";
++      if (regno >= 0)
++	{
++	  const char *reg_prefix;
++	  if (LEGACY_INT_REGNO_P (regno))
++	    reg_prefix = TARGET_64BIT ? "r" : "e";
++	  else
++	    reg_prefix = "";
++	  sprintf (name, "__x86_indirect_thunk%s_%s%s",
++		   bnd, reg_prefix, reg_names[regno]);
++	}
++      else
++	sprintf (name, "__x86_indirect_thunk%s", bnd);
++    }
++  else
++    {
++      if (regno >= 0)
++	{
++	  if (need_bnd_p)
++	    ASM_GENERATE_INTERNAL_LABEL (name, "LITBR", regno);
++	  else
++	    ASM_GENERATE_INTERNAL_LABEL (name, "LITR", regno);
++	}
++      else
++	{
++	  if (need_bnd_p)
++	    ASM_GENERATE_INTERNAL_LABEL (name, "LITB", 0);
++	  else
++	    ASM_GENERATE_INTERNAL_LABEL (name, "LIT", 0);
++	}
++    }
++}
++
++/* Output a call and return thunk for indirect branch.  If BND_P is
++   true, the BND prefix is needed.   If REGNO != -1,  the function
++   address is in REGNO and the call and return thunk looks like:
++
++	call	L2
++   L1:
++	pause
++	jmp	L1
++   L2:
++	mov	%REG, (%sp)
++	ret
++
++   Otherwise, the function address is on the top of stack and the
++   call and return thunk looks like:
++
++	call L2
++  L1:
++	pause
++	jmp L1
++  L2:
++	lea WORD_SIZE(%sp), %sp
++	ret
++ */
++
++static void
++output_indirect_thunk (bool need_bnd_p, int regno)
++{
++  char indirectlabel1[32];
++  char indirectlabel2[32];
++
++  ASM_GENERATE_INTERNAL_LABEL (indirectlabel1, INDIRECT_LABEL,
++			       indirectlabelno++);
++  ASM_GENERATE_INTERNAL_LABEL (indirectlabel2, INDIRECT_LABEL,
++			       indirectlabelno++);
++
++  /* Call */
++  if (need_bnd_p)
++    fputs ("\tbnd call\t", asm_out_file);
++  else
++    fputs ("\tcall\t", asm_out_file);
++  assemble_name_raw (asm_out_file, indirectlabel2);
++  fputc ('\n', asm_out_file);
++
++  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, indirectlabel1);
++
++  /* Pause + lfence.  */
++  fprintf (asm_out_file, "\tpause\n\tlfence\n");
++
++  /* Jump.  */
++  fputs ("\tjmp\t", asm_out_file);
++  assemble_name_raw (asm_out_file, indirectlabel1);
++  fputc ('\n', asm_out_file);
++
++  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, indirectlabel2);
++
++  if (regno >= 0)
++    {
++      /* MOV.  */
++      rtx xops[2];
++      xops[0] = gen_rtx_MEM (word_mode, stack_pointer_rtx);
++      xops[1] = gen_rtx_REG (word_mode, regno);
++      output_asm_insn ("mov\t{%1, %0|%0, %1}", xops);
++    }
++  else
++    {
++      /* LEA.  */
++      rtx xops[2];
++      xops[0] = stack_pointer_rtx;
++      xops[1] = plus_constant (Pmode, stack_pointer_rtx, UNITS_PER_WORD);
++      output_asm_insn ("lea\t{%E1, %0|%0, %E1}", xops);
++    }
++
++  if (need_bnd_p)
++    fputs ("\tbnd ret\n", asm_out_file);
++  else
++    fputs ("\tret\n", asm_out_file);
++}
++
++/* Output a funtion with a call and return thunk for indirect branch.
++   If BND_P is true, the BND prefix is needed.   If REGNO != -1,  the
++   function address is in REGNO.  Otherwise, the function address is
++   on the top of stack.  */
++
++static void
++output_indirect_thunk_function (bool need_bnd_p, int regno)
++{
++  char name[32];
++  tree decl;
++
++  /* Create __x86_indirect_thunk/__x86_indirect_thunk_bnd.  */
++  indirect_thunk_name (name, regno, need_bnd_p);
++  decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
++		     get_identifier (name),
++		     build_function_type_list (void_type_node, NULL_TREE));
++  DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
++				   NULL_TREE, void_type_node);
++  TREE_PUBLIC (decl) = 1;
++  TREE_STATIC (decl) = 1;
++  DECL_IGNORED_P (decl) = 1;
++
++#if TARGET_MACHO
++  if (TARGET_MACHO)
++    {
++      switch_to_section (darwin_sections[picbase_thunk_section]);
++      fputs ("\t.weak_definition\t", asm_out_file);
++      assemble_name (asm_out_file, name);
++      fputs ("\n\t.private_extern\t", asm_out_file);
++      assemble_name (asm_out_file, name);
++      putc ('\n', asm_out_file);
++      ASM_OUTPUT_LABEL (asm_out_file, name);
++      DECL_WEAK (decl) = 1;
++    }
++  else
++#endif
++    if (USE_HIDDEN_LINKONCE)
++      {
++	cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
++
++	targetm.asm_out.unique_section (decl, 0);
++	switch_to_section (get_named_section (decl, NULL, 0));
++
++	targetm.asm_out.globalize_label (asm_out_file, name);
++	fputs ("\t.hidden\t", asm_out_file);
++	assemble_name (asm_out_file, name);
++	putc ('\n', asm_out_file);
++	ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
++      }
++    else
++      {
++	switch_to_section (text_section);
++	ASM_OUTPUT_LABEL (asm_out_file, name);
++      }
++
++  DECL_INITIAL (decl) = make_node (BLOCK);
++  current_function_decl = decl;
++  allocate_struct_function (decl, false);
++  init_function_start (decl);
++  /* We're about to hide the function body from callees of final_* by
++     emitting it directly; tell them we're a thunk, if they care.  */
++  cfun->is_thunk = true;
++  first_function_block_is_cold = false;
++  /* Make sure unwind info is emitted for the thunk if needed.  */
++  final_start_function (emit_barrier (), asm_out_file, 1);
++
++  output_indirect_thunk (need_bnd_p, regno);
++
++  final_end_function ();
++  init_insn_lengths ();
++  free_after_compilation (cfun);
++  set_cfun (NULL);
++  current_function_decl = NULL;
++}
++
+ static int pic_labels_used;
+ 
+ /* Fills in the label name that should be used for a pc thunk for
+@@ -10988,11 +11252,32 @@ ix86_code_end (void)
+   rtx xops[2];
+   int regno;
+ 
++  if (indirect_thunk_needed)
++    output_indirect_thunk_function (false, -1);
++  if (indirect_thunk_bnd_needed)
++    output_indirect_thunk_function (true, -1);
++
++  for (regno = FIRST_REX_INT_REG; regno <= LAST_REX_INT_REG; regno++)
++    {
++      int i = regno - FIRST_REX_INT_REG + LAST_INT_REG + 1;
++      if ((indirect_thunks_used & (1 << i)))
++	output_indirect_thunk_function (false, regno);
++
++      if ((indirect_thunks_bnd_used & (1 << i)))
++	output_indirect_thunk_function (true, regno);
++    }
++
+   for (regno = AX_REG; regno <= SP_REG; regno++)
+     {
+       char name[32];
+       tree decl;
+ 
++      if ((indirect_thunks_used & (1 << regno)))
++	output_indirect_thunk_function (false, regno);
++
++      if ((indirect_thunks_bnd_used & (1 << regno)))
++	output_indirect_thunk_function (true, regno);
++
+       if (!(pic_labels_used & (1 << regno)))
+ 	continue;
+ 
+@@ -27369,12 +27654,292 @@ ix86_nopic_noplt_attribute_p (rtx call_op)
+   return false;
+ }
+ 
++/* Output indirect branch via a call and return thunk.  CALL_OP is a
++   register which contains the branch target.  XASM is the assembly
++   template for CALL_OP.  Branch is a tail call if SIBCALL_P is true.
++   A normal call is converted to:
++
++	call __x86_indirect_thunk_reg
++
++   and a tail call is converted to:
++
++	jmp __x86_indirect_thunk_reg
++ */
++
++static void
++ix86_output_indirect_branch_via_reg (rtx call_op, bool sibcall_p)
++{
++  char thunk_name_buf[32];
++  char *thunk_name;
++  bool need_bnd_p = ix86_bnd_prefixed_insn_p (current_output_insn);
++  int regno = REGNO (call_op);
++
++  if (cfun->machine->indirect_branch_type
++      != indirect_branch_thunk_inline)
++    {
++      if (cfun->machine->indirect_branch_type == indirect_branch_thunk)
++	{
++	  int i = regno;
++	  if (i >= FIRST_REX_INT_REG)
++	    i -= (FIRST_REX_INT_REG - LAST_INT_REG - 1);
++	  if (need_bnd_p)
++	    indirect_thunks_bnd_used |= 1 << i;
++	  else
++	    indirect_thunks_used |= 1 << i;
++	}
++      indirect_thunk_name (thunk_name_buf, regno, need_bnd_p);
++      thunk_name = thunk_name_buf;
++    }
++  else
++    thunk_name = NULL;
++
++  if (sibcall_p)
++    {
++      if (thunk_name != NULL)
++	{
++	  if (need_bnd_p)
++	    fprintf (asm_out_file, "\tbnd jmp\t%s\n", thunk_name);
++	  else
++	    fprintf (asm_out_file, "\tjmp\t%s\n", thunk_name);
++	}
++      else
++	output_indirect_thunk (need_bnd_p, regno);
++    }
++  else
++    {
++      if (thunk_name != NULL)
++	{
++	  if (need_bnd_p)
++	    fprintf (asm_out_file, "\tbnd call\t%s\n", thunk_name);
++	  else
++	    fprintf (asm_out_file, "\tcall\t%s\n", thunk_name);
++	  return;
++	}
++
++      char indirectlabel1[32];
++      char indirectlabel2[32];
++
++      ASM_GENERATE_INTERNAL_LABEL (indirectlabel1,
++				   INDIRECT_LABEL,
++				   indirectlabelno++);
++      ASM_GENERATE_INTERNAL_LABEL (indirectlabel2,
++				   INDIRECT_LABEL,
++				   indirectlabelno++);
++
++      /* Jump.  */
++      if (need_bnd_p)
++	fputs ("\tbnd jmp\t", asm_out_file);
++      else
++	fputs ("\tjmp\t", asm_out_file);
++      assemble_name_raw (asm_out_file, indirectlabel2);
++      fputc ('\n', asm_out_file);
++
++      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, indirectlabel1);
++
++      if (thunk_name != NULL)
++	{
++	  if (need_bnd_p)
++	    fprintf (asm_out_file, "\tbnd jmp\t%s\n", thunk_name);
++	  else
++	    fprintf (asm_out_file, "\tjmp\t%s\n", thunk_name);
++	}
++      else
++	output_indirect_thunk (need_bnd_p, regno);
++
++      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, indirectlabel2);
++
++      /* Call.  */
++      if (need_bnd_p)
++	fputs ("\tbnd call\t", asm_out_file);
++      else
++	fputs ("\tcall\t", asm_out_file);
++      assemble_name_raw (asm_out_file, indirectlabel1);
++      fputc ('\n', asm_out_file);
++    }
++}
++
++/* Output indirect branch via a call and return thunk.  CALL_OP is
++   the branch target.  XASM is the assembly template for CALL_OP.
++   Branch is a tail call if SIBCALL_P is true.  A normal call is
++   converted to:
++
++	jmp L2
++   L1:
++	push CALL_OP
++	jmp __x86_indirect_thunk
++   L2:
++	call L1
++
++   and a tail call is converted to:
++
++	push CALL_OP
++	jmp __x86_indirect_thunk
++ */
++
++static void
++ix86_output_indirect_branch_via_push (rtx call_op, const char *xasm,
++				      bool sibcall_p)
++{
++  char thunk_name_buf[32];
++  char *thunk_name;
++  char push_buf[64];
++  bool need_bnd_p = ix86_bnd_prefixed_insn_p (current_output_insn);
++  int regno = -1;
++
++  if (cfun->machine->indirect_branch_type
++      != indirect_branch_thunk_inline)
++    {
++      if (cfun->machine->indirect_branch_type == indirect_branch_thunk)
++	{
++	  if (need_bnd_p)
++	    indirect_thunk_bnd_needed = true;
++	  else
++	    indirect_thunk_needed = true;
++	}
++      indirect_thunk_name (thunk_name_buf, regno, need_bnd_p);
++      thunk_name = thunk_name_buf;
++    }
++  else
++    thunk_name = NULL;
++
++  snprintf (push_buf, sizeof (push_buf), "push{%c}\t%s",
++	    TARGET_64BIT ? 'q' : 'l', xasm);
++
++  if (sibcall_p)
++    {
++      output_asm_insn (push_buf, &call_op);
++      if (thunk_name != NULL)
++	{
++	  if (need_bnd_p)
++	    fprintf (asm_out_file, "\tbnd jmp\t%s\n", thunk_name);
++	  else
++	    fprintf (asm_out_file, "\tjmp\t%s\n", thunk_name);
++	}
++      else
++	output_indirect_thunk (need_bnd_p, regno);
++    }
++  else
++    {
++      char indirectlabel1[32];
++      char indirectlabel2[32];
++
++      ASM_GENERATE_INTERNAL_LABEL (indirectlabel1,
++				   INDIRECT_LABEL,
++				   indirectlabelno++);
++      ASM_GENERATE_INTERNAL_LABEL (indirectlabel2,
++				   INDIRECT_LABEL,
++				   indirectlabelno++);
++
++      /* Jump.  */
++      if (need_bnd_p)
++	fputs ("\tbnd jmp\t", asm_out_file);
++      else
++	fputs ("\tjmp\t", asm_out_file);
++      assemble_name_raw (asm_out_file, indirectlabel2);
++      fputc ('\n', asm_out_file);
++
++      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, indirectlabel1);
++
++      /* An external function may be called via GOT, instead of PLT.  */
++      if (MEM_P (call_op))
++	{
++	  struct ix86_address parts;
++	  rtx addr = XEXP (call_op, 0);
++	  if (ix86_decompose_address (addr, &parts)
++	      && parts.base == stack_pointer_rtx)
++	    {
++	      /* Since call will adjust stack by -UNITS_PER_WORD,
++		 we must convert "disp(stack, index, scale)" to
++		 "disp+UNITS_PER_WORD(stack, index, scale)".  */
++	      if (parts.index)
++		{
++		  addr = gen_rtx_MULT (Pmode, parts.index,
++				       GEN_INT (parts.scale));
++		  addr = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
++				       addr);
++		}
++	      else
++		addr = stack_pointer_rtx;
++
++	      rtx disp;
++	      if (parts.disp != NULL_RTX)
++		disp = plus_constant (Pmode, parts.disp,
++				      UNITS_PER_WORD);
++	      else
++		disp = GEN_INT (UNITS_PER_WORD);
++
++	      addr = gen_rtx_PLUS (Pmode, addr, disp);
++	      call_op = gen_rtx_MEM (GET_MODE (call_op), addr);
++	    }
++	}
++
++      output_asm_insn (push_buf, &call_op);
++
++      if (thunk_name != NULL)
++	{
++	  if (need_bnd_p)
++	    fprintf (asm_out_file, "\tbnd jmp\t%s\n", thunk_name);
++	  else
++	    fprintf (asm_out_file, "\tjmp\t%s\n", thunk_name);
++	}
++      else
++	output_indirect_thunk (need_bnd_p, regno);
++
++      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, indirectlabel2);
++
++      /* Call.  */
++      if (need_bnd_p)
++	fputs ("\tbnd call\t", asm_out_file);
++      else
++	fputs ("\tcall\t", asm_out_file);
++      assemble_name_raw (asm_out_file, indirectlabel1);
++      fputc ('\n', asm_out_file);
++    }
++}
++
++/* Output indirect branch via a call and return thunk.  CALL_OP is
++   the branch target.  XASM is the assembly template for CALL_OP.
++   Branch is a tail call if SIBCALL_P is true.   */
++
++static void
++ix86_output_indirect_branch (rtx call_op, const char *xasm,
++			     bool sibcall_p)
++{
++  if (REG_P (call_op))
++    ix86_output_indirect_branch_via_reg (call_op, sibcall_p);
++  else
++    ix86_output_indirect_branch_via_push (call_op, xasm, sibcall_p);
++}
++/* Output indirect jump.  CALL_OP is the jump target.  Jump is a
++   function return if RET_P is true.  */
++
++const char *
++ix86_output_indirect_jmp (rtx call_op, bool ret_p)
++{
++  if (cfun->machine->indirect_branch_type != indirect_branch_keep)
++    {
++      /* We can't have red-zone if this isn't a function return since
++	 "call" in the indirect thunk pushes the return address onto
++	 stack, destroying red-zone.  */
++      if (!ret_p && ix86_red_zone_size != 0)
++	gcc_unreachable ();
++
++      ix86_output_indirect_branch (call_op, "%0", true);
++      return "";
++    }
++  else
++    return "%!jmp\t%A0";
++}
++
+ /* Output the assembly for a call instruction.  */
+ 
+ const char *
+ ix86_output_call_insn (rtx_insn *insn, rtx call_op)
+ {
+   bool direct_p = constant_call_address_operand (call_op, VOIDmode);
++  bool output_indirect_p
++    = (!TARGET_SEH
++       && cfun->machine->indirect_branch_type != indirect_branch_keep);
+   bool seh_nop_p = false;
+   const char *xasm;
+ 
+@@ -27383,7 +27948,13 @@ ix86_output_call_insn (rtx_insn *insn, rtx call_op)
+       if (direct_p)
+ 	{
+ 	  if (ix86_nopic_noplt_attribute_p (call_op))
+-	    xasm = "%!jmp\t{*%p0@GOTPCREL(%%rip)|[QWORD PTR %p0@GOTPCREL[rip]]}";
++	    {
++	      direct_p = false;
++	      if (output_indirect_p)
++		xasm = "{%p0@GOTPCREL(%%rip)|[QWORD PTR %p0@GOTPCREL[rip]]}";
++	      else
++		xasm = "%!jmp\t{*%p0@GOTPCREL(%%rip)|[QWORD PTR %p0@GOTPCREL[rip]]}";
++	    }
+ 	  else
+ 	    xasm = "%!jmp\t%P0";
+ 	}
+@@ -27392,9 +27963,17 @@ ix86_output_call_insn (rtx_insn *insn, rtx call_op)
+       else if (TARGET_SEH)
+ 	xasm = "%!rex.W jmp\t%A0";
+       else
+-	xasm = "%!jmp\t%A0";
++	{
++	  if (output_indirect_p)
++	    xasm = "%0";
++	  else
++	    xasm = "%!jmp\t%A0";
++	}
+ 
+-      output_asm_insn (xasm, &call_op);
++      if (output_indirect_p && !direct_p)
++	ix86_output_indirect_branch (call_op, xasm, true);
++      else
++	output_asm_insn (xasm, &call_op);
+       return "";
+     }
+ 
+@@ -27431,14 +28010,28 @@ ix86_output_call_insn (rtx_insn *insn, rtx call_op)
+   if (direct_p)
+     {
+       if (ix86_nopic_noplt_attribute_p (call_op))
+-	xasm = "%!call\t{*%p0@GOTPCREL(%%rip)|[QWORD PTR %p0@GOTPCREL[rip]]}";
++	{
++	  direct_p = false;
++	  if (output_indirect_p)
++	    xasm = "{%p0@GOTPCREL(%%rip)|[QWORD PTR %p0@GOTPCREL[rip]]}";
++	  else
++	    xasm = "%!call\t{*%p0@GOTPCREL(%%rip)|[QWORD PTR %p0@GOTPCREL[rip]]}";
++	}
+       else
+ 	xasm = "%!call\t%P0";
+     }
+   else
+-    xasm = "%!call\t%A0";
++    {
++      if (output_indirect_p)
++	xasm = "%0";
++      else
++	xasm = "%!call\t%A0";
++    }
+ 
+-  output_asm_insn (xasm, &call_op);
++  if (output_indirect_p && !direct_p)
++    ix86_output_indirect_branch (call_op, xasm, false);
++  else
++    output_asm_insn (xasm, &call_op);
+ 
+   if (seh_nop_p)
+     return "nop";
+@@ -44836,7 +45429,7 @@ ix86_handle_struct_attribute (tree *node, tree name, tree, int,
+ }
+ 
+ static tree
+-ix86_handle_fndecl_attribute (tree *node, tree name, tree, int,
++ix86_handle_fndecl_attribute (tree *node, tree name, tree args, int,
+ 			      bool *no_add_attrs)
+ {
+   if (TREE_CODE (*node) != FUNCTION_DECL)
+@@ -44845,6 +45438,29 @@ ix86_handle_fndecl_attribute (tree *node, tree name, tree, int,
+                name);
+       *no_add_attrs = true;
+     }
++
++  if (is_attribute_p ("indirect_branch", name))
++    {
++      tree cst = TREE_VALUE (args);
++      if (TREE_CODE (cst) != STRING_CST)
++	{
++	  warning (OPT_Wattributes,
++		   "%qE attribute requires a string constant argument",
++		   name);
++	  *no_add_attrs = true;
++	}
++      else if (strcmp (TREE_STRING_POINTER (cst), "keep") != 0
++	       && strcmp (TREE_STRING_POINTER (cst), "thunk") != 0
++	       && strcmp (TREE_STRING_POINTER (cst), "thunk-inline") != 0
++	       && strcmp (TREE_STRING_POINTER (cst), "thunk-extern") != 0)
++	{
++	  warning (OPT_Wattributes,
++		   "argument to %qE attribute is not "
++		   "(keep|thunk|thunk-inline|thunk-extern)", name);
++	  *no_add_attrs = true;
++	}
++    }
++
+   return NULL_TREE;
+ }
+ 
+@@ -49072,6 +49688,9 @@ static const struct attribute_spec ix86_attribute_table[] =
+     false },
+   { "callee_pop_aggregate_return", 1, 1, false, true, true,
+     ix86_handle_callee_pop_aggregate_return, true },
++  { "indirect_branch", 1, 1, true, false, false,
++    ix86_handle_fndecl_attribute, false },
++
+   /* End element.  */
+   { NULL,        0, 0, false, false, false, NULL, false }
+ };
+diff --git a/src/gcc/config/i386/i386.h b/src/gcc/config/i386/i386.h
+index 541441661..9dccdb035 100644
+--- a/src/gcc/config/i386/i386.h
++++ b/src/gcc/config/i386/i386.h
+@@ -2572,6 +2572,13 @@ struct GTY(()) machine_function {
+   /* If true, it is safe to not save/restore DRAP register.  */
+   BOOL_BITFIELD no_drap_save_restore : 1;
+ 
++  /* How to generate indirec branch.  */
++  ENUM_BITFIELD(indirect_branch) indirect_branch_type : 3;
++
++  /* If true, the current function has local indirect jumps, like
++     "indirect_jump" or "tablejump".  */
++  BOOL_BITFIELD has_local_indirect_jump : 1;
++
+   /* If true, there is register available for argument passing.  This
+      is used only in ix86_function_ok_for_sibcall by 32-bit to determine
+      if there is scratch register available for indirect sibcall.  In
+diff --git a/src/gcc/config/i386/i386.md b/src/gcc/config/i386/i386.md
+index d2bfe314f..153e1622b 100644
+--- a/src/gcc/config/i386/i386.md
++++ b/src/gcc/config/i386/i386.md
+@@ -11807,13 +11807,18 @@
+ {
+   if (TARGET_X32)
+     operands[0] = convert_memory_address (word_mode, operands[0]);
++  cfun->machine->has_local_indirect_jump = true;
+ })
+ 
+ (define_insn "*indirect_jump"
+   [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rBw"))]
+   ""
+-  "%!jmp\t%A0"
+-  [(set_attr "type" "ibr")
++  "* return ix86_output_indirect_jmp (operands[0], false);"
++  [(set (attr "type")
++     (if_then_else (match_test "(cfun->machine->indirect_branch_type
++				 != indirect_branch_keep)")
++	(const_string "multi")
++	(const_string "ibr")))
+    (set_attr "length_immediate" "0")
+    (set_attr "maybe_prefix_bnd" "1")])
+ 
+@@ -11856,14 +11861,19 @@
+ 
+   if (TARGET_X32)
+     operands[0] = convert_memory_address (word_mode, operands[0]);
++  cfun->machine->has_local_indirect_jump = true;
+ })
+ 
+ (define_insn "*tablejump_1"
+   [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rBw"))
+    (use (label_ref (match_operand 1)))]
+   ""
+-  "%!jmp\t%A0"
+-  [(set_attr "type" "ibr")
++  "* return ix86_output_indirect_jmp (operands[0], false);"
++  [(set (attr "type")
++     (if_then_else (match_test "(cfun->machine->indirect_branch_type
++				 != indirect_branch_keep)")
++	(const_string "multi")
++	(const_string "ibr")))
+    (set_attr "length_immediate" "0")
+    (set_attr "maybe_prefix_bnd" "1")])
+ 
+@@ -12520,8 +12530,12 @@
+   [(simple_return)
+    (use (match_operand:SI 0 "register_operand" "r"))]
+   "reload_completed"
+-  "%!jmp\t%A0"
+-  [(set_attr "type" "ibr")
++  "* return ix86_output_indirect_jmp (operands[0], true);"
++  [(set (attr "type")
++     (if_then_else (match_test "(cfun->machine->indirect_branch_type
++				 != indirect_branch_keep)")
++	(const_string "multi")
++	(const_string "ibr")))
+    (set_attr "length_immediate" "0")
+    (set_attr "maybe_prefix_bnd" "1")])
+ 
+diff --git a/src/gcc/config/i386/i386.opt b/src/gcc/config/i386/i386.opt
+index f304b621e..5ffa3349a 100644
+--- a/src/gcc/config/i386/i386.opt
++++ b/src/gcc/config/i386/i386.opt
+@@ -897,3 +897,23 @@ Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
+ mmitigate-rop
+ Target Var(flag_mitigate_rop) Init(0)
+ Attempt to avoid generating instruction sequences containing ret bytes.
++
++mindirect-branch=
++Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep)
++Convert indirect call and jump to call and return thunks.
++
++Enum
++Name(indirect_branch) Type(enum indirect_branch)
++Known indirect branch choices (for use with the -mindirect-branch= option):
++
++EnumValue
++Enum(indirect_branch) String(keep) Value(indirect_branch_keep)
++
++EnumValue
++Enum(indirect_branch) String(thunk) Value(indirect_branch_thunk)
++
++EnumValue
++Enum(indirect_branch) String(thunk-inline) Value(indirect_branch_thunk_inline)
++
++EnumValue
++Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern)
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c
+new file mode 100644
+index 000000000..d983e1c3e
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch;
++
++void
++male_indirect_jump (long offset)
++{
++  dispatch(offset);
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c
+new file mode 100644
+index 000000000..58f09b42d
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch[256];
++
++void
++male_indirect_jump (long offset)
++{
++  dispatch[offset](offset);
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c
+new file mode 100644
+index 000000000..f20d35c19
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch;
++
++int
++male_indirect_jump (long offset)
++{
++  dispatch(offset);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c
+new file mode 100644
+index 000000000..0eff8fb65
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch[256];
++
++int
++male_indirect_jump (long offset)
++{
++  dispatch[offset](offset);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-5.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-5.c
+new file mode 100644
+index 000000000..a25b20dd8
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-5.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile { target *-*-linux* } } */
++/* { dg-options "-O2 -fpic -fno-plt -mindirect-branch=thunk" } */
++
++extern void bar (void);
++
++void
++foo (void)
++{
++  bar ();
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*bar@GOT" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-6.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-6.c
+new file mode 100644
+index 000000000..cff114a6c
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-6.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile { target *-*-linux* } } */
++/* { dg-options "-O2 -fpic -fno-plt -mindirect-branch=thunk" } */
++
++extern void bar (void);
++
++int
++foo (void)
++{
++  bar ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*bar@GOT" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 2 } } */
++/* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 2 } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-7.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-7.c
+new file mode 100644
+index 000000000..afdb60079
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-7.c
+@@ -0,0 +1,44 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk -fno-pic" } */
++
++void func0 (void);
++void func1 (void);
++void func2 (void);
++void func3 (void);
++void func4 (void);
++void func4 (void);
++void func5 (void);
++
++void
++bar (int i)
++{
++  switch (i)
++    {
++    default:
++      func0 ();
++      break;
++    case 1:
++      func1 ();
++      break;
++    case 2:
++      func2 ();
++      break;
++    case 3:
++      func3 ();
++      break;
++    case 4:
++      func4 ();
++      break;
++    case 5:
++      func5 ();
++      break;
++    }
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*\.L\[0-9\]+\\(,%" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c
+new file mode 100644
+index 000000000..d64d978b6
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c
+@@ -0,0 +1,23 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch;
++
++extern void male_indirect_jump (long)
++  __attribute__ ((indirect_branch("thunk")));
++
++void
++male_indirect_jump (long offset)
++{
++  dispatch(offset);
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c
+new file mode 100644
+index 000000000..93067454d
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch[256];
++
++__attribute__ ((indirect_branch("thunk")))
++void
++male_indirect_jump (long offset)
++{
++  dispatch[offset](offset);
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c
+new file mode 100644
+index 000000000..97744d657
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c
+@@ -0,0 +1,23 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch;
++extern int male_indirect_jump (long)
++  __attribute__ ((indirect_branch("thunk-inline")));
++
++int
++male_indirect_jump (long offset)
++{
++  dispatch(offset);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 2 } } */
++/* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 2 } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c
+new file mode 100644
+index 000000000..bfce3ea5c
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c
+@@ -0,0 +1,22 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch[256];
++
++__attribute__ ((indirect_branch("thunk-inline")))
++int
++male_indirect_jump (long offset)
++{
++  dispatch[offset](offset);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 2 } } */
++/* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 2 } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c
+new file mode 100644
+index 000000000..083360604
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c
+@@ -0,0 +1,22 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch;
++extern int male_indirect_jump (long)
++  __attribute__ ((indirect_branch("thunk-extern")));
++
++int
++male_indirect_jump (long offset)
++{
++  dispatch(offset);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c
+new file mode 100644
+index 000000000..2eba0fbd9
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch[256];
++
++__attribute__ ((indirect_branch("thunk-extern")))
++int
++male_indirect_jump (long offset)
++{
++  dispatch[offset](offset);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c
+new file mode 100644
+index 000000000..f58427eae
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c
+@@ -0,0 +1,44 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fno-pic" } */
++
++void func0 (void);
++void func1 (void);
++void func2 (void);
++void func3 (void);
++void func4 (void);
++void func4 (void);
++void func5 (void);
++
++__attribute__ ((indirect_branch("thunk-extern")))
++void
++bar (int i)
++{
++  switch (i)
++    {
++    default:
++      func0 ();
++      break;
++    case 1:
++      func1 ();
++      break;
++    case 2:
++      func2 ();
++      break;
++    case 3:
++      func3 ();
++      break;
++    case 4:
++      func4 ();
++      break;
++    case 5:
++      func5 ();
++      break;
++    }
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*\.L\[0-9\]+\\(,%" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-not "call\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-8.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-8.c
+new file mode 100644
+index 000000000..564ed3954
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-8.c
+@@ -0,0 +1,42 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk -fno-pic" } */
++
++void func0 (void);
++void func1 (void);
++void func2 (void);
++void func3 (void);
++void func4 (void);
++void func4 (void);
++void func5 (void);
++
++__attribute__ ((indirect_branch("keep")))
++void
++bar (int i)
++{
++  switch (i)
++    {
++    default:
++      func0 ();
++      break;
++    case 1:
++      func1 ();
++      break;
++    case 2:
++      func2 ();
++      break;
++    case 3:
++      func3 ();
++      break;
++    case 4:
++      func4 ();
++      break;
++    case 5:
++      func5 ();
++      break;
++    }
++}
++
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-not "call\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-1.c
+new file mode 100644
+index 000000000..50fbee20a
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-1.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile { target { ! x32 } } } */
++/* { dg-options "-O2 -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fno-pic" } */
++
++void (*dispatch) (char *);
++char buf[10];
++
++void
++foo (void)
++{
++  dispatch (buf);
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "pushq\[ \t\]%rax" { target x32 } } } */
++/* { dg-final { scan-assembler "bnd jmp\[ \t\]*__x86_indirect_thunk_bnd" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "bnd call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "bnd ret" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-2.c
+new file mode 100644
+index 000000000..2976e67ad
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-2.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile { target { ! x32 } } } */
++/* { dg-options "-O2 -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fno-pic" } */
++
++void (*dispatch) (char *);
++char buf[10];
++
++int
++foo (void)
++{
++  dispatch (buf);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "pushq\[ \t\]%rax" { target x32 } } } */
++/* { dg-final { scan-assembler "bnd jmp\[ \t\]*__x86_indirect_thunk_bnd" } } */
++/* { dg-final { scan-assembler "bnd jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "bnd call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "bnd ret" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-3.c
+new file mode 100644
+index 000000000..da4bc98ef
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-3.c
+@@ -0,0 +1,19 @@
++/* { dg-do compile { target { *-*-linux* && { ! x32 } } } } */
++/* { dg-options "-O2 -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fpic -fno-plt" } */
++
++void bar (char *);
++char buf[10];
++
++void
++foo (void)
++{
++  bar (buf);
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*bar@GOT" } } */
++/* { dg-final { scan-assembler "bnd jmp\[ \t\]*__x86_indirect_thunk_bnd" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "bnd call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "bnd ret" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-4.c
+new file mode 100644
+index 000000000..c64d12ef9
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-4.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile { target { *-*-linux* && { ! x32 } } } } */
++/* { dg-options "-O2 -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fpic -fno-plt" } */
++
++void bar (char *);
++char buf[10];
++
++int
++foo (void)
++{
++  bar (buf);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*bar@GOT" } } */
++/* { dg-final { scan-assembler "bnd jmp\[ \t\]*__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler "bnd jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-times "bnd call\[ \t\]*\.LIND" 2 } } */
++/* { dg-final { scan-assembler "bnd ret" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c
+new file mode 100644
+index 000000000..49f27b494
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c
+@@ -0,0 +1,19 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk-extern -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch;
++
++void
++male_indirect_jump (long offset)
++{
++  dispatch(offset);
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-not "call\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c
+new file mode 100644
+index 000000000..a1e3eb6fc
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c
+@@ -0,0 +1,19 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk-extern -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch[256];
++
++void
++male_indirect_jump (long offset)
++{
++  dispatch[offset](offset);
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-not "call\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c
+new file mode 100644
+index 000000000..395634e7e
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk-extern -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch;
++
++int
++male_indirect_jump (long offset)
++{
++  dispatch(offset);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c
+new file mode 100644
+index 000000000..fd3f63379
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk-extern -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch[256];
++
++int
++male_indirect_jump (long offset)
++{
++  dispatch[offset](offset);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-5.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-5.c
+new file mode 100644
+index 000000000..ba2f92b6f
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-5.c
+@@ -0,0 +1,16 @@
++/* { dg-do compile { target *-*-linux* } } */
++/* { dg-options "-O2 -fpic -fno-plt -mindirect-branch=thunk-extern" } */
++
++extern void bar (void);
++
++void
++foo (void)
++{
++  bar ();
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*bar@GOT" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-not "call\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-6.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-6.c
+new file mode 100644
+index 000000000..0c5a2d472
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-6.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile { target *-*-linux* } } */
++/* { dg-options "-O2 -fpic -fno-plt -mindirect-branch=thunk-extern" } */
++
++extern void bar (void);
++
++int
++foo (void)
++{
++  bar ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*bar@GOT" } } */
++/* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 1 } } */
++/* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 1 } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c
+new file mode 100644
+index 000000000..665252327
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c
+@@ -0,0 +1,43 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk-extern -fno-pic" } */
++
++void func0 (void);
++void func1 (void);
++void func2 (void);
++void func3 (void);
++void func4 (void);
++void func4 (void);
++void func5 (void);
++
++void
++bar (int i)
++{
++  switch (i)
++    {
++    default:
++      func0 ();
++      break;
++    case 1:
++      func1 ();
++      break;
++    case 2:
++      func2 ();
++      break;
++    case 3:
++      func3 ();
++      break;
++    case 4:
++      func4 ();
++      break;
++    case 5:
++      func5 ();
++      break;
++    }
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*\.L\[0-9\]+\\(,%" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-not "call\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c
+new file mode 100644
+index 000000000..68c0ff713
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk-inline -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch;
++
++void
++male_indirect_jump (long offset)
++{
++  dispatch(offset);
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c
+new file mode 100644
+index 000000000..e2da1fcb6
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk-inline -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch[256];
++
++void
++male_indirect_jump (long offset)
++{
++  dispatch[offset](offset);
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c
+new file mode 100644
+index 000000000..244fec708
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk-inline -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch;
++
++int
++male_indirect_jump (long offset)
++{
++  dispatch(offset);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 2 } } */
++/* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 2 } } */
++/* { dg-final { scan-assembler-times {\tpause} 1 } } */
++/* { dg-final { scan-assembler-times {\tlfence} 1 } } */
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c
+new file mode 100644
+index 000000000..107ebe32f
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk-inline -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch[256];
++
++int
++male_indirect_jump (long offset)
++{
++  dispatch[offset](offset);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 2 } } */
++/* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 2 } } */
++/* { dg-final { scan-assembler-times {\tpause} 1 } } */
++/* { dg-final { scan-assembler-times {\tlfence} 1 } } */
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-5.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-5.c
+new file mode 100644
+index 000000000..17b04ef22
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-5.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile { target *-*-linux* } } */
++/* { dg-options "-O2 -fpic -fno-plt -mindirect-branch=thunk-inline" } */
++
++extern void bar (void);
++
++void
++foo (void)
++{
++  bar ();
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*bar@GOT" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-6.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-6.c
+new file mode 100644
+index 000000000..d9eb11285
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-6.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile { target *-*-linux* } } */
++/* { dg-options "-O2 -fpic -fno-plt -mindirect-branch=thunk-inline" } */
++
++extern void bar (void);
++
++int
++foo (void)
++{
++  bar ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*bar@GOT" } } */
++/* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 2 } } */
++/* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 2 } } */
++/* { dg-final { scan-assembler-times {\tpause} 1 } } */
++/* { dg-final { scan-assembler-times {\tlfence} 1 } } */
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-7.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-7.c
+new file mode 100644
+index 000000000..d02b1dcb1
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-7.c
+@@ -0,0 +1,44 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk-inline -fno-pic" } */
++
++void func0 (void);
++void func1 (void);
++void func2 (void);
++void func3 (void);
++void func4 (void);
++void func4 (void);
++void func5 (void);
++
++void
++bar (int i)
++{
++  switch (i)
++    {
++    default:
++      func0 ();
++      break;
++    case 1:
++      func1 ();
++      break;
++    case 2:
++      func2 ();
++      break;
++    case 3:
++      func3 ();
++      break;
++    case 4:
++      func4 ();
++      break;
++    case 5:
++      func5 ();
++      break;
++    }
++}
++
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*\.L\[0-9\]+\\(,%" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk" } } */
+-- 
+2.16.1
+
--- gcc-6-6.4.0.orig/debian/patches/0005-x86-Add-mfunction-return.diff
+++ gcc-6-6.4.0/debian/patches/0005-x86-Add-mfunction-return.diff
@@ -0,0 +1,1509 @@
+From 4fdfda0044443095df739f808021baca24c10fdd Mon Sep 17 00:00:00 2001
+From: "H.J. Lu" <hjl.tools@gmail.com>
+Date: Sat, 6 Jan 2018 22:29:56 -0800
+Subject: [PATCH] x86: Add -mfunction-return=
+
+Add -mfunction-return= option to convert function return to call and
+return thunks.  The default is 'keep', which keeps function return
+unmodified.  'thunk' converts function return to call and return thunk.
+'thunk-inline' converts function return to inlined call and return thunk.
+'thunk-extern' converts function return to external call and return
+thunk provided in a separate object file.  You can control this behavior
+for a specific function by using the function attribute function_return.
+
+Function return thunk is the same as memory thunk for -mindirect-branch=
+where the return address is at the top of the stack:
+
+__x86_return_thunk:
+	call L2
+L1:
+	pause
+	lfence
+	jmp L1
+L2:
+	lea 8(%rsp), %rsp|lea 4(%esp), %esp
+	ret
+
+and function return becomes
+
+	jmp __x86_return_thunk
+
+-mindirect-branch= tests are updated with -mfunction-return=keep to
+avoid false test failures when -mfunction-return=thunk is added to
+RUNTESTFLAGS for "make check".
+
+gcc/
+
+	Backport from mainline
+	2018-01-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/i386-protos.h (ix86_output_function_return): New.
+	* config/i386/i386.c (ix86_set_indirect_branch_type): Also
+	set function_return_type.
+	(indirect_thunk_name): Add ret_p to indicate thunk for function
+	return.
+	(output_indirect_thunk_function): Pass false to
+	indirect_thunk_name.
+	(ix86_output_indirect_branch_via_reg): Likewise.
+	(ix86_output_indirect_branch_via_push): Likewise.
+	(output_indirect_thunk_function): Create alias for function
+	return thunk if regno < 0.
+	(ix86_output_function_return): New function.
+	(ix86_handle_fndecl_attribute): Handle function_return.
+	(ix86_attribute_table): Add function_return.
+	* config/i386/i386.h (machine_function): Add
+	function_return_type.
+	* config/i386/i386.md (simple_return_internal): Use
+	ix86_output_function_return.
+	(simple_return_internal_long): Likewise.
+	* config/i386/i386.opt (mfunction-return=): New option.
+	(indirect_branch): Mention -mfunction-return=.
+
+gcc/testsuite/
+
+	Backport from mainline
+	2018-01-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gcc.target/i386/indirect-thunk-1.c (dg-options): Add
+	-mfunction-return=keep.
+	* gcc.target/i386/indirect-thunk-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-5.c: Likewise.
+	* gcc.target/i386/indirect-thunk-6.c: Likewise.
+	* gcc.target/i386/indirect-thunk-7.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-5.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-6.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-7.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-8.c: Likewise.
+	* gcc.target/i386/indirect-thunk-bnd-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-bnd-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-bnd-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-bnd-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-5.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-6.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-7.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-5.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-6.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-7.c: Likewise.
+	* gcc.target/i386/ret-thunk-1.c: New test.
+	* gcc.target/i386/ret-thunk-10.c: Likewise.
+	* gcc.target/i386/ret-thunk-11.c: Likewise.
+	* gcc.target/i386/ret-thunk-12.c: Likewise.
+	* gcc.target/i386/ret-thunk-13.c: Likewise.
+	* gcc.target/i386/ret-thunk-14.c: Likewise.
+	* gcc.target/i386/ret-thunk-15.c: Likewise.
+	* gcc.target/i386/ret-thunk-16.c: Likewise.
+	* gcc.target/i386/ret-thunk-2.c: Likewise.
+	* gcc.target/i386/ret-thunk-3.c: Likewise.
+	* gcc.target/i386/ret-thunk-4.c: Likewise.
+	* gcc.target/i386/ret-thunk-5.c: Likewise.
+	* gcc.target/i386/ret-thunk-6.c: Likewise.
+	* gcc.target/i386/ret-thunk-7.c: Likewise.
+	* gcc.target/i386/ret-thunk-8.c: Likewise.
+	* gcc.target/i386/ret-thunk-9.c: Likewise.
+
+i386: Don't use ASM_OUTPUT_DEF for TARGET_MACHO
+
+ASM_OUTPUT_DEF isn't defined for TARGET_MACHO.  Use ASM_OUTPUT_LABEL to
+generate the __x86_return_thunk label, instead of the set directive.
+Update testcase to remove the __x86_return_thunk label check.  Since
+-fno-pic is ignored on Darwin, update testcases to sscan or "push"
+only on Linux.
+
+gcc/
+
+	Backport from mainline
+	2018-01-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/83839
+	* config/i386/i386.c (output_indirect_thunk_function): Use
+	ASM_OUTPUT_LABEL, instead of ASM_OUTPUT_DEF, for TARGET_MACHO
+	for  __x86.return_thunk.
+
+gcc/testsuite/
+
+	Backport from mainline
+	2018-01-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/83839
+	* gcc.target/i386/indirect-thunk-1.c: Scan for "push" only on
+	Linux.
+	* gcc.target/i386/indirect-thunk-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-7.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-5.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-6.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-7.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-7.c: Likewise.
+	* gcc.target/i386/indirect-thunk-register-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-register-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-register-4.c: Likewise.
+	* gcc.target/i386/ret-thunk-10.c: Likewise.
+	* gcc.target/i386/ret-thunk-11.c: Likewise.
+	* gcc.target/i386/ret-thunk-12.c: Likewise.
+	* gcc.target/i386/ret-thunk-13.c: Likewise.
+	* gcc.target/i386/ret-thunk-14.c: Likewise.
+	* gcc.target/i386/ret-thunk-15.c: Likewise.
+	* gcc.target/i386/ret-thunk-9.c: Don't check the
+	__x86_return_thunk label.
+	Scan for "push" only for Linux.
+---
+ gcc/config/i386/i386-protos.h                      |   1 +
+ gcc/config/i386/i386.c                             | 152 +++++++++++++++++++--
+ gcc/config/i386/i386.h                             |   3 +
+ gcc/config/i386/i386.md                            |   9 +-
+ gcc/config/i386/i386.opt                           |   6 +-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-1.c   |   4 +-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-2.c   |   4 +-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-3.c   |   4 +-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-4.c   |   4 +-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-5.c   |   2 +-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-6.c   |   2 +-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-7.c   |   4 +-
+ .../gcc.target/i386/indirect-thunk-attr-1.c        |   4 +-
+ .../gcc.target/i386/indirect-thunk-attr-2.c        |   4 +-
+ .../gcc.target/i386/indirect-thunk-attr-3.c        |   4 +-
+ .../gcc.target/i386/indirect-thunk-attr-4.c        |   4 +-
+ .../gcc.target/i386/indirect-thunk-attr-5.c        |   4 +-
+ .../gcc.target/i386/indirect-thunk-attr-6.c        |   4 +-
+ .../gcc.target/i386/indirect-thunk-attr-7.c        |   4 +-
+ .../gcc.target/i386/indirect-thunk-attr-8.c        |   2 +-
+ .../gcc.target/i386/indirect-thunk-bnd-1.c         |   4 +-
+ .../gcc.target/i386/indirect-thunk-bnd-2.c         |   4 +-
+ .../gcc.target/i386/indirect-thunk-bnd-3.c         |   2 +-
+ .../gcc.target/i386/indirect-thunk-bnd-4.c         |   2 +-
+ .../gcc.target/i386/indirect-thunk-extern-1.c      |   4 +-
+ .../gcc.target/i386/indirect-thunk-extern-2.c      |   4 +-
+ .../gcc.target/i386/indirect-thunk-extern-3.c      |   4 +-
+ .../gcc.target/i386/indirect-thunk-extern-4.c      |   4 +-
+ .../gcc.target/i386/indirect-thunk-extern-5.c      |   2 +-
+ .../gcc.target/i386/indirect-thunk-extern-6.c      |   2 +-
+ .../gcc.target/i386/indirect-thunk-extern-7.c      |   4 +-
+ .../gcc.target/i386/indirect-thunk-inline-1.c      |   4 +-
+ .../gcc.target/i386/indirect-thunk-inline-2.c      |   4 +-
+ .../gcc.target/i386/indirect-thunk-inline-3.c      |   4 +-
+ .../gcc.target/i386/indirect-thunk-inline-4.c      |   4 +-
+ .../gcc.target/i386/indirect-thunk-inline-5.c      |   2 +-
+ .../gcc.target/i386/indirect-thunk-inline-6.c      |   2 +-
+ .../gcc.target/i386/indirect-thunk-inline-7.c      |   4 +-
+ gcc/testsuite/gcc.target/i386/ret-thunk-1.c        |  13 ++
+ gcc/testsuite/gcc.target/i386/ret-thunk-10.c       |  23 ++++
+ gcc/testsuite/gcc.target/i386/ret-thunk-11.c       |  23 ++++
+ gcc/testsuite/gcc.target/i386/ret-thunk-12.c       |  22 +++
+ gcc/testsuite/gcc.target/i386/ret-thunk-13.c       |  22 +++
+ gcc/testsuite/gcc.target/i386/ret-thunk-14.c       |  22 +++
+ gcc/testsuite/gcc.target/i386/ret-thunk-15.c       |  22 +++
+ gcc/testsuite/gcc.target/i386/ret-thunk-16.c       |  18 +++
+ gcc/testsuite/gcc.target/i386/ret-thunk-2.c        |  13 ++
+ gcc/testsuite/gcc.target/i386/ret-thunk-3.c        |  12 ++
+ gcc/testsuite/gcc.target/i386/ret-thunk-4.c        |  12 ++
+ gcc/testsuite/gcc.target/i386/ret-thunk-5.c        |  15 ++
+ gcc/testsuite/gcc.target/i386/ret-thunk-6.c        |  14 ++
+ gcc/testsuite/gcc.target/i386/ret-thunk-7.c        |  13 ++
+ gcc/testsuite/gcc.target/i386/ret-thunk-8.c        |  14 ++
+ gcc/testsuite/gcc.target/i386/ret-thunk-9.c        |  24 ++++
+ 56 files changed, 516 insertions(+), 74 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-1.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-10.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-11.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-12.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-13.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-14.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-15.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-16.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-2.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-3.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-4.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-5.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-6.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-7.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-8.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-9.c
+
+diff --git a/src/gcc/config/i386/i386-protos.h b/src/gcc/config/i386/i386-protos.h
+index eca4cbf07..620d70ef9 100644
+--- a/src/gcc/config/i386/i386-protos.h
++++ b/src/gcc/config/i386/i386-protos.h
+@@ -312,6 +312,7 @@ extern enum attr_cpu ix86_schedule;
+ 
+ extern const char * ix86_output_call_insn (rtx_insn *insn, rtx call_op);
+ extern const char * ix86_output_indirect_jmp (rtx call_op, bool ret_p);
++extern const char * ix86_output_function_return (bool long_p);
+ extern bool ix86_operands_ok_for_move_multiple (rtx *operands, bool load,
+ 						enum machine_mode mode);
+ 
+diff --git a/src/gcc/config/i386/i386.c b/src/gcc/config/i386/i386.c
+index 0b9fc4d30..34e26a3a3 100644
+--- a/src/gcc/config/i386/i386.c
++++ b/src/gcc/config/i386/i386.c
+@@ -6390,6 +6390,31 @@ ix86_set_indirect_branch_type (tree fndecl)
+       else
+ 	cfun->machine->indirect_branch_type = ix86_indirect_branch;
+     }
++
++  if (cfun->machine->function_return_type == indirect_branch_unset)
++    {
++      tree attr = lookup_attribute ("function_return",
++				    DECL_ATTRIBUTES (fndecl));
++      if (attr != NULL)
++	{
++	  tree args = TREE_VALUE (attr);
++	  if (args == NULL)
++	    gcc_unreachable ();
++	  tree cst = TREE_VALUE (args);
++	  if (strcmp (TREE_STRING_POINTER (cst), "keep") == 0)
++	    cfun->machine->function_return_type = indirect_branch_keep;
++	  else if (strcmp (TREE_STRING_POINTER (cst), "thunk") == 0)
++	    cfun->machine->function_return_type = indirect_branch_thunk;
++	  else if (strcmp (TREE_STRING_POINTER (cst), "thunk-inline") == 0)
++	    cfun->machine->function_return_type = indirect_branch_thunk_inline;
++	  else if (strcmp (TREE_STRING_POINTER (cst), "thunk-extern") == 0)
++	    cfun->machine->function_return_type = indirect_branch_thunk_extern;
++	  else
++	    gcc_unreachable ();
++	}
++      else
++	cfun->machine->function_return_type = ix86_function_return;
++    }
+ }
+ 
+ /* Establish appropriate back-end context for processing the function
+@@ -11036,8 +11061,12 @@ static int indirect_thunks_bnd_used;
+ /* Fills in the label name that should be used for the indirect thunk.  */
+ 
+ static void
+-indirect_thunk_name (char name[32], int regno, bool need_bnd_p)
++indirect_thunk_name (char name[32], int regno, bool need_bnd_p,
++		     bool ret_p)
+ {
++  if (regno >= 0 && ret_p)
++    gcc_unreachable ();
++
+   if (USE_HIDDEN_LINKONCE)
+     {
+       const char *bnd = need_bnd_p ? "_bnd" : "";
+@@ -11052,7 +11081,10 @@ indirect_thunk_name (char name[32], int regno, bool need_bnd_p)
+ 		   bnd, reg_prefix, reg_names[regno]);
+ 	}
+       else
+-	sprintf (name, "__x86_indirect_thunk%s", bnd);
++	{
++	  const char *ret = ret_p ? "return" : "indirect";
++	  sprintf (name, "__x86_%s_thunk%s", ret, bnd);
++	}
+     }
+   else
+     {
+@@ -11065,10 +11097,20 @@ indirect_thunk_name (char name[32], int regno, bool need_bnd_p)
+ 	}
+       else
+ 	{
+-	  if (need_bnd_p)
+-	    ASM_GENERATE_INTERNAL_LABEL (name, "LITB", 0);
++	  if (ret_p)
++	    {
++	      if (need_bnd_p)
++		ASM_GENERATE_INTERNAL_LABEL (name, "LRTB", 0);
++	      else
++		ASM_GENERATE_INTERNAL_LABEL (name, "LRT", 0);
++	    }
+ 	  else
+-	    ASM_GENERATE_INTERNAL_LABEL (name, "LIT", 0);
++	    {
++	      if (need_bnd_p)
++		ASM_GENERATE_INTERNAL_LABEL (name, "LITB", 0);
++	      else
++		ASM_GENERATE_INTERNAL_LABEL (name, "LIT", 0);
++	    }
+ 	}
+     }
+ }
+@@ -11163,7 +11205,7 @@ output_indirect_thunk_function (bool need_bnd_p, int regno)
+   tree decl;
+ 
+   /* Create __x86_indirect_thunk/__x86_indirect_thunk_bnd.  */
+-  indirect_thunk_name (name, regno, need_bnd_p);
++  indirect_thunk_name (name, regno, need_bnd_p, false);
+   decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
+ 		     get_identifier (name),
+ 		     build_function_type_list (void_type_node, NULL_TREE));
+@@ -11206,6 +11248,36 @@ output_indirect_thunk_function (bool need_bnd_p, int regno)
+ 	ASM_OUTPUT_LABEL (asm_out_file, name);
+       }
+ 
++  if (regno < 0)
++    {
++      /* Create alias for __x86.return_thunk/__x86.return_thunk_bnd.  */
++      char alias[32];
++
++      indirect_thunk_name (alias, regno, need_bnd_p, true);
++#if TARGET_MACHO
++      if (TARGET_MACHO)
++	{
++	  fputs ("\t.weak_definition\t", asm_out_file);
++	  assemble_name (asm_out_file, alias);
++	  fputs ("\n\t.private_extern\t", asm_out_file);
++	  assemble_name (asm_out_file, alias);
++	  putc ('\n', asm_out_file);
++	  ASM_OUTPUT_LABEL (asm_out_file, alias);
++	}
++#else
++      ASM_OUTPUT_DEF (asm_out_file, alias, name);
++      if (USE_HIDDEN_LINKONCE)
++	{
++	  fputs ("\t.globl\t", asm_out_file);
++	  assemble_name (asm_out_file, alias);
++	  putc ('\n', asm_out_file);
++	  fputs ("\t.hidden\t", asm_out_file);
++	  assemble_name (asm_out_file, alias);
++	  putc ('\n', asm_out_file);
++	}
++#endif
++    }
++
+   DECL_INITIAL (decl) = make_node (BLOCK);
+   current_function_decl = decl;
+   allocate_struct_function (decl, false);
+@@ -27687,7 +27759,7 @@ ix86_output_indirect_branch_via_reg (rtx call_op, bool sibcall_p)
+ 	  else
+ 	    indirect_thunks_used |= 1 << i;
+ 	}
+-      indirect_thunk_name (thunk_name_buf, regno, need_bnd_p);
++      indirect_thunk_name (thunk_name_buf, regno, need_bnd_p, false);
+       thunk_name = thunk_name_buf;
+     }
+   else
+@@ -27796,7 +27868,7 @@ ix86_output_indirect_branch_via_push (rtx call_op, const char *xasm,
+ 	  else
+ 	    indirect_thunk_needed = true;
+ 	}
+-      indirect_thunk_name (thunk_name_buf, regno, need_bnd_p);
++      indirect_thunk_name (thunk_name_buf, regno, need_bnd_p, false);
+       thunk_name = thunk_name_buf;
+     }
+   else
+@@ -27931,6 +28003,46 @@ ix86_output_indirect_jmp (rtx call_op, bool ret_p)
+     return "%!jmp\t%A0";
+ }
+ 
++/* Output function return.  CALL_OP is the jump target.  Add a REP
++   prefix to RET if LONG_P is true and function return is kept.  */
++
++const char *
++ix86_output_function_return (bool long_p)
++{
++  if (cfun->machine->function_return_type != indirect_branch_keep)
++    {
++      char thunk_name[32];
++      bool need_bnd_p = ix86_bnd_prefixed_insn_p (current_output_insn);
++
++      if (cfun->machine->function_return_type
++	  != indirect_branch_thunk_inline)
++	{
++	  bool need_thunk = (cfun->machine->function_return_type
++			     == indirect_branch_thunk);
++	  indirect_thunk_name (thunk_name, -1, need_bnd_p, true);
++	  if (need_bnd_p)
++	    {
++	      indirect_thunk_bnd_needed |= need_thunk;
++	      fprintf (asm_out_file, "\tbnd jmp\t%s\n", thunk_name);
++	    }
++	  else
++	    {
++	      indirect_thunk_needed |= need_thunk;
++	      fprintf (asm_out_file, "\tjmp\t%s\n", thunk_name);
++	    }
++	}
++      else
++	output_indirect_thunk (need_bnd_p, -1);
++
++      return "";
++    }
++
++  if (!long_p || ix86_bnd_prefixed_insn_p (current_output_insn))
++    return "%!ret";
++
++  return "rep%; ret";
++}
++
+ /* Output the assembly for a call instruction.  */
+ 
+ const char *
+@@ -45461,6 +45573,28 @@ ix86_handle_fndecl_attribute (tree *node, tree name, tree args, int,
+ 	}
+     }
+ 
++  if (is_attribute_p ("function_return", name))
++    {
++      tree cst = TREE_VALUE (args);
++      if (TREE_CODE (cst) != STRING_CST)
++	{
++	  warning (OPT_Wattributes,
++		   "%qE attribute requires a string constant argument",
++		   name);
++	  *no_add_attrs = true;
++	}
++      else if (strcmp (TREE_STRING_POINTER (cst), "keep") != 0
++	       && strcmp (TREE_STRING_POINTER (cst), "thunk") != 0
++	       && strcmp (TREE_STRING_POINTER (cst), "thunk-inline") != 0
++	       && strcmp (TREE_STRING_POINTER (cst), "thunk-extern") != 0)
++	{
++	  warning (OPT_Wattributes,
++		   "argument to %qE attribute is not "
++		   "(keep|thunk|thunk-inline|thunk-extern)", name);
++	  *no_add_attrs = true;
++	}
++    }
++
+   return NULL_TREE;
+ }
+ 
+@@ -49690,6 +49824,8 @@ static const struct attribute_spec ix86_attribute_table[] =
+     ix86_handle_callee_pop_aggregate_return, true },
+   { "indirect_branch", 1, 1, true, false, false,
+     ix86_handle_fndecl_attribute, false },
++  { "function_return", 1, 1, true, false, false,
++    ix86_handle_fndecl_attribute, false },
+ 
+   /* End element.  */
+   { NULL,        0, 0, false, false, false, NULL, false }
+diff --git a/src/gcc/config/i386/i386.h b/src/gcc/config/i386/i386.h
+index 9dccdb035..b34bc117c 100644
+--- a/src/gcc/config/i386/i386.h
++++ b/src/gcc/config/i386/i386.h
+@@ -2579,6 +2579,9 @@ struct GTY(()) machine_function {
+      "indirect_jump" or "tablejump".  */
+   BOOL_BITFIELD has_local_indirect_jump : 1;
+ 
++  /* How to generate function return.  */
++  ENUM_BITFIELD(indirect_branch) function_return_type : 3;
++
+   /* If true, there is register available for argument passing.  This
+      is used only in ix86_function_ok_for_sibcall by 32-bit to determine
+      if there is scratch register available for indirect sibcall.  In
+diff --git a/src/gcc/config/i386/i386.md b/src/gcc/config/i386/i386.md
+index 153e1622b..2da671e9f 100644
+--- a/src/gcc/config/i386/i386.md
++++ b/src/gcc/config/i386/i386.md
+@@ -12489,7 +12489,7 @@
+ (define_insn "simple_return_internal"
+   [(simple_return)]
+   "reload_completed"
+-  "%!ret"
++  "* return ix86_output_function_return (false);"
+   [(set_attr "length" "1")
+    (set_attr "atom_unit" "jeu")
+    (set_attr "length_immediate" "0")
+@@ -12503,12 +12503,7 @@
+   [(simple_return)
+    (unspec [(const_int 0)] UNSPEC_REP)]
+   "reload_completed"
+-{
+-  if (ix86_bnd_prefixed_insn_p (insn))
+-    return "%!ret";
+-
+-  return "rep%; ret";
+-}
++  "* return ix86_output_function_return (true);"
+   [(set_attr "length" "2")
+    (set_attr "atom_unit" "jeu")
+    (set_attr "length_immediate" "0")
+diff --git a/src/gcc/config/i386/i386.opt b/src/gcc/config/i386/i386.opt
+index 5ffa3349a..ad5916fb6 100644
+--- a/src/gcc/config/i386/i386.opt
++++ b/src/gcc/config/i386/i386.opt
+@@ -902,9 +902,13 @@ mindirect-branch=
+ Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep)
+ Convert indirect call and jump to call and return thunks.
+ 
++mfunction-return=
++Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep)
++Convert function return to call and return thunk.
++
+ Enum
+ Name(indirect_branch) Type(enum indirect_branch)
+-Known indirect branch choices (for use with the -mindirect-branch= option):
++Known indirect branch choices (for use with the -mindirect-branch=/-mfunction-return= options):
+ 
+ EnumValue
+ Enum(indirect_branch) String(keep) Value(indirect_branch_keep)
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c
+index d983e1c3e..e365ef569 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -11,7 +11,7 @@ male_indirect_jump (long offset)
+   dispatch(offset);
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c
+index 58f09b42d..05a51ad91 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -11,7 +11,7 @@ male_indirect_jump (long offset)
+   dispatch[offset](offset);
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c
+index f20d35c19..3c0d4c39f 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -12,7 +12,7 @@ male_indirect_jump (long offset)
+   return 0;
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c
+index 0eff8fb65..14d4ef6dd 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -12,7 +12,7 @@ male_indirect_jump (long offset)
+   return 0;
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-5.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-5.c
+index a25b20dd8..b4836c38d 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-5.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-5.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target *-*-linux* } } */
+-/* { dg-options "-O2 -fpic -fno-plt -mindirect-branch=thunk" } */
++/* { dg-options "-O2 -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk" } */
+ 
+ extern void bar (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-6.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-6.c
+index cff114a6c..1f06bd1af 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-6.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-6.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target *-*-linux* } } */
+-/* { dg-options "-O2 -fpic -fno-plt -mindirect-branch=thunk" } */
++/* { dg-options "-O2 -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk" } */
+ 
+ extern void bar (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-7.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-7.c
+index afdb60079..bc6b47a63 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-7.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-7.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
+ 
+ void func0 (void);
+ void func1 (void);
+@@ -35,7 +35,7 @@ bar (int i)
+     }
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*\.L\[0-9\]+\\(,%" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*\.L\[0-9\]+\\(,%" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c
+index d64d978b6..2257be3af 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -14,7 +14,7 @@ male_indirect_jump (long offset)
+   dispatch(offset);
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c
+index 93067454d..e9cfdc587 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -12,7 +12,7 @@ male_indirect_jump (long offset)
+   dispatch[offset](offset);
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c
+index 97744d657..f938db050 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -14,7 +14,7 @@ male_indirect_jump (long offset)
+   return 0;
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 2 } } */
+ /* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 2 } } */
+ /* { dg-final { scan-assembler {\tpause} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c
+index bfce3ea5c..4e5859969 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -13,7 +13,7 @@ male_indirect_jump (long offset)
+   return 0;
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 2 } } */
+ /* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 2 } } */
+ /* { dg-final { scan-assembler {\tpause} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c
+index 083360604..b8d50249d 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -14,7 +14,7 @@ male_indirect_jump (long offset)
+   return 0;
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c
+index 2eba0fbd9..455adabfe 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -13,7 +13,7 @@ male_indirect_jump (long offset)
+   return 0;
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c
+index f58427eae..4595b841e 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
+ 
+ void func0 (void);
+ void func1 (void);
+@@ -36,7 +36,7 @@ bar (int i)
+     }
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*\.L\[0-9\]+\\(,%" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*\.L\[0-9\]+\\(,%" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" } } */
+ /* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-8.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-8.c
+index 564ed3954..d730d31bd 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-8.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-8.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
+ 
+ void func0 (void);
+ void func1 (void);
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-1.c
+index 50fbee20a..5e3e118e9 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-1.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target { ! x32 } } } */
+-/* { dg-options "-O2 -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fno-pic" } */
+ 
+ void (*dispatch) (char *);
+ char buf[10];
+@@ -10,7 +10,7 @@ foo (void)
+   dispatch (buf);
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "pushq\[ \t\]%rax" { target x32 } } } */
+ /* { dg-final { scan-assembler "bnd jmp\[ \t\]*__x86_indirect_thunk_bnd" } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-2.c
+index 2976e67ad..2801aa419 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-2.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target { ! x32 } } } */
+-/* { dg-options "-O2 -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fno-pic" } */
+ 
+ void (*dispatch) (char *);
+ char buf[10];
+@@ -11,7 +11,7 @@ foo (void)
+   return 0;
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "pushq\[ \t\]%rax" { target x32 } } } */
+ /* { dg-final { scan-assembler "bnd jmp\[ \t\]*__x86_indirect_thunk_bnd" } } */
+ /* { dg-final { scan-assembler "bnd jmp\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-3.c
+index da4bc98ef..70b4fb36e 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-3.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-3.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target { *-*-linux* && { ! x32 } } } } */
+-/* { dg-options "-O2 -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fpic -fno-plt" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fpic -fno-plt" } */
+ 
+ void bar (char *);
+ char buf[10];
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-4.c
+index c64d12ef9..3baf03ee7 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-4.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-4.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target { *-*-linux* && { ! x32 } } } } */
+-/* { dg-options "-O2 -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fpic -fno-plt" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fpic -fno-plt" } */
+ 
+ void bar (char *);
+ char buf[10];
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c
+index 49f27b494..edeb26421 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk-extern -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -11,7 +11,7 @@ male_indirect_jump (long offset)
+   dispatch(offset);
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
+ /* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c
+index a1e3eb6fc..1d00413a7 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk-extern -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -11,7 +11,7 @@ male_indirect_jump (long offset)
+   dispatch[offset](offset);
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
+ /* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c
+index 395634e7e..06ebf1c90 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk-extern -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -12,7 +12,7 @@ male_indirect_jump (long offset)
+   return 0;
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c
+index fd3f63379..1c8f94466 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk-extern -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -12,7 +12,7 @@ male_indirect_jump (long offset)
+   return 0;
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 1 { target { ! x32 } } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-5.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-5.c
+index ba2f92b6f..21740ac5b 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-5.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-5.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target *-*-linux* } } */
+-/* { dg-options "-O2 -fpic -fno-plt -mindirect-branch=thunk-extern" } */
++/* { dg-options "-O2 -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk-extern" } */
+ 
+ extern void bar (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-6.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-6.c
+index 0c5a2d472..a77c1f470 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-6.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-6.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target *-*-linux* } } */
+-/* { dg-options "-O2 -fpic -fno-plt -mindirect-branch=thunk-extern" } */
++/* { dg-options "-O2 -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk-extern" } */
+ 
+ extern void bar (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c
+index 665252327..86e9fd1f1 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk-extern -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
+ 
+ void func0 (void);
+ void func1 (void);
+@@ -35,7 +35,7 @@ bar (int i)
+     }
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*\.L\[0-9\]+\\(,%" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*\.L\[0-9\]+\\(,%" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
+ /* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c
+index 68c0ff713..3ecde8788 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk-inline -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -11,7 +11,7 @@ male_indirect_jump (long offset)
+   dispatch(offset);
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
+ /* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
+ /* { dg-final { scan-assembler {\tpause} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c
+index e2da1fcb6..df32a19a2 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk-inline -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -11,7 +11,7 @@ male_indirect_jump (long offset)
+   dispatch[offset](offset);
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
+ /* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
+ /* { dg-final { scan-assembler {\tpause} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c
+index 244fec708..9540996de 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk-inline -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -12,7 +12,7 @@ male_indirect_jump (long offset)
+   return 0;
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 2 } } */
+ /* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 2 } } */
+ /* { dg-final { scan-assembler-times {\tpause} 1 } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c
+index 107ebe32f..f3db6e244 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk-inline -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+@@ -12,7 +12,7 @@ male_indirect_jump (long offset)
+   return 0;
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?dispatch" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 2 } } */
+ /* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 2 } } */
+ /* { dg-final { scan-assembler-times {\tpause} 1 } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-5.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-5.c
+index 17b04ef22..0f687c3b0 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-5.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-5.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target *-*-linux* } } */
+-/* { dg-options "-O2 -fpic -fno-plt -mindirect-branch=thunk-inline" } */
++/* { dg-options "-O2 -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk-inline" } */
+ 
+ extern void bar (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-6.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-6.c
+index d9eb11285..b27c6fc96 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-6.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-6.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target *-*-linux* } } */
+-/* { dg-options "-O2 -fpic -fno-plt -mindirect-branch=thunk-inline" } */
++/* { dg-options "-O2 -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk-inline" } */
+ 
+ extern void bar (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-7.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-7.c
+index d02b1dcb1..764a375fc 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-7.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-7.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mindirect-branch=thunk-inline -fno-pic" } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
+ 
+ void func0 (void);
+ void func1 (void);
+@@ -35,7 +35,7 @@ bar (int i)
+     }
+ }
+ 
+-/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*\.L\[0-9\]+\\(,%" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*\.L\[0-9\]+\\(,%" { target { { ! x32 } && *-*-linux* } } } } */
+ /* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+ /* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
+ /* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-1.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-1.c
+new file mode 100644
+index 000000000..7223f67ba
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-1.c
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=thunk" } */
++
++void
++foo (void)
++{
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_return_thunk" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-10.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-10.c
+new file mode 100644
+index 000000000..3a6727b5c
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-10.c
+@@ -0,0 +1,23 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=thunk-inline -mindirect-branch=thunk -fno-pic" } */
++
++extern void (*bar) (void);
++
++int
++foo (void)
++{
++  bar ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*__x86_return_thunk" } } */
++/* { dg-final { scan-assembler-times {\tpause} 2 } } */
++/* { dg-final { scan-assembler-times {\tlfence} 2 } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?bar" { target { { ! x32 } && *-*-linux* } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } }  } } */
++/* { dg-final { scan-assembler "__x86_indirect_thunk:" { target { ! x32 } }  } } */
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target { x32 } }  } } */
++/* { dg-final { scan-assembler "__x86_indirect_thunk_(r|e)ax:" { target { x32 } }  } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-11.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-11.c
+new file mode 100644
+index 000000000..b8f681883
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-11.c
+@@ -0,0 +1,23 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=thunk-extern -mindirect-branch=thunk -fno-pic" } */
++
++extern void (*bar) (void);
++
++int
++foo (void)
++{
++  bar ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_return_thunk" } } */
++/* { dg-final { scan-assembler-times {\tpause} 1 } } */
++/* { dg-final { scan-assembler-times {\tlfence} 1 } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?bar" { target { { ! x32 } && *-*-linux* } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "__x86_indirect_thunk:" { target { ! x32 } }  } } */
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target { x32 } }  } } */
++/* { dg-final { scan-assembler "__x86_indirect_thunk_(r|e)ax:" { target { x32 } }  } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-12.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-12.c
+new file mode 100644
+index 000000000..01b0a02f8
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-12.c
+@@ -0,0 +1,22 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
++
++extern void (*bar) (void);
++
++int
++foo (void)
++{
++  bar ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*__x86_return_thunk" } } */
++/* { dg-final { scan-assembler-times {\tpause} 1 } } */
++/* { dg-final { scan-assembler-times {\tlfence} 1 } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "__x86_indirect_thunk:" { target { ! x32 } }  } } */
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target { x32 } }  } } */
++/* { dg-final { scan-assembler "__x86_indirect_thunk_(r|e)ax:" { target { x32 } }  } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-13.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-13.c
+new file mode 100644
+index 000000000..4b497b5f8
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-13.c
+@@ -0,0 +1,22 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
++
++extern void (*bar) (void);
++extern int foo (void) __attribute__ ((function_return("thunk")));
++
++int
++foo (void)
++{
++  bar ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_return_thunk" } } */
++/* { dg-final { scan-assembler-times {\tpause} 2 } } */
++/* { dg-final { scan-assembler-times {\tlfence} 2 } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?bar" { target { { ! x32 } && *-*-linux* } } } } */
++/* { dg-final { scan-assembler-times "jmp\[ \t\]*\.LIND" 3 } } */
++/* { dg-final { scan-assembler-times "call\[ \t\]*\.LIND" 3 } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler-not "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target { x32 } }  } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-14.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-14.c
+new file mode 100644
+index 000000000..4ae4c44a3
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-14.c
+@@ -0,0 +1,22 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
++
++extern void (*bar) (void);
++
++__attribute__ ((function_return("thunk-inline")))
++int
++foo (void)
++{
++  bar ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler-times {\tpause} 1 } } */
++/* { dg-final { scan-assembler-times {\tlfence} 1 } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*__x86_return_thunk" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?bar" { target { { ! x32 } && *-*-linux* } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target { x32 } }  } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-15.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-15.c
+new file mode 100644
+index 000000000..5b5bc765a
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-15.c
+@@ -0,0 +1,22 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=keep -fno-pic" } */
++
++extern void (*bar) (void);
++
++__attribute__ ((function_return("thunk-extern"), indirect_branch("thunk")))
++int
++foo (void)
++{
++  bar ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_return_thunk" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-times {\tpause} 1 } } */
++/* { dg-final { scan-assembler-times {\tlfence} 1 } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?bar" { target { { ! x32 } && *-*-linux* } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target x32 } } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-16.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-16.c
+new file mode 100644
+index 000000000..a16cad16a
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-16.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=thunk-inline -mindirect-branch=thunk-extern -fno-pic" } */
++
++extern void (*bar) (void);
++
++__attribute__ ((function_return("keep"), indirect_branch("keep")))
++int
++foo (void)
++{
++  bar ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk" } } */
++/* { dg-final { scan-assembler-not "__x86_return_thunk" } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-not "call\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-2.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-2.c
+new file mode 100644
+index 000000000..c6659e3ad
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-2.c
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=thunk-inline" } */
++
++void
++foo (void)
++{
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*__x86_return_thunk" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-3.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-3.c
+new file mode 100644
+index 000000000..0f7f388f4
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-3.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=thunk-extern" } */
++
++void
++foo (void)
++{
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_return_thunk" } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-not "call\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-4.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-4.c
+new file mode 100644
+index 000000000..9ae37e835
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-4.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=keep" } */
++
++void
++foo (void)
++{
++}
++
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*__x86_return_thunk" } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-not "call\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-5.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-5.c
+new file mode 100644
+index 000000000..4bd0d2a27
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-5.c
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=keep" } */
++
++extern void foo (void) __attribute__ ((function_return("thunk")));
++
++void
++foo (void)
++{
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_return_thunk" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-6.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-6.c
+new file mode 100644
+index 000000000..053841f6f
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-6.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=keep" } */
++
++__attribute__ ((function_return("thunk-inline")))
++void
++foo (void)
++{
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler {\tlfence} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*__x86_return_thunk" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-7.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-7.c
+new file mode 100644
+index 000000000..262e67801
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-7.c
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=keep" } */
++
++__attribute__ ((function_return("thunk-extern")))
++void
++foo (void)
++{
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_return_thunk" } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-not "call\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-8.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-8.c
+new file mode 100644
+index 000000000..c1658e966
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-8.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=thunk-inline" } */
++
++extern void foo (void) __attribute__ ((function_return("keep")));
++
++void
++foo (void)
++{
++}
++
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*__x86_return_thunk" } } */
++/* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-not "call\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-9.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-9.c
+new file mode 100644
+index 000000000..fa24a1f73
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-9.c
+@@ -0,0 +1,24 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mfunction-return=thunk -mindirect-branch=thunk -fno-pic" } */
++
++extern void (*bar) (void);
++
++int
++foo (void)
++{
++  bar ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_return_thunk" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "__x86_indirect_thunk:" } } */
++/* { dg-final { scan-assembler-times {\tpause} 1 { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times {\tlfence} 1 { target { ! x32 } } } } */
++/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?bar" { target { { ! x32 } && *-*-linux* } } } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" { target { ! x32 } } } } */
++/* { dg-final { scan-assembler-times {\tpause} 2 { target { x32 } } } } */
++/* { dg-final { scan-assembler-times {\tlfence} 2 { target { x32 } } } } */
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_(r|e)ax" { target { x32 } } } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" { target x32 } } } */
+-- 
+2.16.1
+
--- gcc-6-6.4.0.orig/debian/patches/0006-x86-Add-mindirect-branch-register.diff
+++ gcc-6-6.4.0/debian/patches/0006-x86-Add-mindirect-branch-register.diff
@@ -0,0 +1,915 @@
+From b5869f4417ad2e689eab4f61015fe36b834707b3 Mon Sep 17 00:00:00 2001
+From: "H.J. Lu" <hjl.tools@gmail.com>
+Date: Sat, 6 Jan 2018 22:29:56 -0800
+Subject: [PATCH] x86: Add -mindirect-branch-register
+
+Add -mindirect-branch-register to force indirect branch via register.
+This is implemented by disabling patterns of indirect branch via memory,
+similar to TARGET_X32.
+
+-mindirect-branch= and -mfunction-return= tests are updated with
+-mno-indirect-branch-register to avoid false test failures when
+-mindirect-branch-register is added to RUNTESTFLAGS for "make check".
+
+gcc/
+
+	Backport from mainline
+	2018-01-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/constraints.md (Bs): Disallow memory operand for
+	-mindirect-branch-register.
+	(Bw): Likewise.
+	* config/i386/predicates.md (indirect_branch_operand): Likewise.
+	(GOT_memory_operand): Likewise.
+	(call_insn_operand): Likewise.
+	(sibcall_insn_operand): Likewise.
+	(GOT32_symbol_operand): Likewise.
+	* config/i386/i386.md (indirect_jump): Call convert_memory_address
+	for -mindirect-branch-register.
+	(tablejump): Likewise.
+	(*sibcall_memory): Likewise.
+	(*sibcall_value_memory): Likewise.
+	Disallow peepholes of indirect call and jump via memory for
+	-mindirect-branch-register.
+	(*call_pop): Replace m with Bw.
+	(*call_value_pop): Likewise.
+	(*sibcall_pop_memory): Replace m with Bs.
+	* config/i386/i386.opt (mindirect-branch-register): New option.
+
+gcc/testsuite/
+
+	Backport from mainline
+	2018-01-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gcc.target/i386/indirect-thunk-1.c (dg-options): Add
+	-mno-indirect-branch-register.
+	* gcc.target/i386/indirect-thunk-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-5.c: Likewise.
+	* gcc.target/i386/indirect-thunk-6.c: Likewise.
+	* gcc.target/i386/indirect-thunk-7.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-5.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-6.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-7.c: Likewise.
+	* gcc.target/i386/indirect-thunk-bnd-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-bnd-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-bnd-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-bnd-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-5.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-6.c: Likewise.
+	* gcc.target/i386/indirect-thunk-extern-7.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-1.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-3.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-4.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-5.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-6.c: Likewise.
+	* gcc.target/i386/indirect-thunk-inline-7.c: Likewise.
+	* gcc.target/i386/ret-thunk-10.c: Likewise.
+	* gcc.target/i386/ret-thunk-11.c: Likewise.
+	* gcc.target/i386/ret-thunk-12.c: Likewise.
+	* gcc.target/i386/ret-thunk-13.c: Likewise.
+	* gcc.target/i386/ret-thunk-14.c: Likewise.
+	* gcc.target/i386/ret-thunk-15.c: Likewise.
+	* gcc.target/i386/ret-thunk-9.c: Likewise.
+	* gcc.target/i386/indirect-thunk-register-1.c: New test.
+	* gcc.target/i386/indirect-thunk-register-2.c: Likewise.
+	* gcc.target/i386/indirect-thunk-register-3.c: Likewise.
+
+i386: Rename to ix86_indirect_branch_register
+
+Rename the variable for -mindirect-branch-register to
+ix86_indirect_branch_register to match the command-line option name.
+
+	Backport from mainline
+	2018-01-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/constraints.md (Bs): Replace
+	ix86_indirect_branch_thunk_register with
+	ix86_indirect_branch_register.
+	(Bw): Likewise.
+	* config/i386/i386.md (indirect_jump): Likewise.
+	(tablejump): Likewise.
+	(*sibcall_memory): Likewise.
+	(*sibcall_value_memory): Likewise.
+	Peepholes of indirect call and jump via memory: Likewise.
+	* config/i386/i386.opt: Likewise.
+	* config/i386/predicates.md (indirect_branch_operand): Likewise.
+	(GOT_memory_operand): Likewise.
+	(call_insn_operand): Likewise.
+	(sibcall_insn_operand): Likewise.
+	(GOT32_symbol_operand): Likewise.
+
+x86: Rewrite ix86_indirect_branch_register logic
+
+Rewrite ix86_indirect_branch_register logic with
+
+(and (not (match_test "ix86_indirect_branch_register"))
+     (original condition before r256662))
+
+	Backport from mainline
+	2018-01-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/predicates.md (constant_call_address_operand):
+	Rewrite ix86_indirect_branch_register logic.
+	(sibcall_insn_operand): Likewise.
+
+Don't check ix86_indirect_branch_register for GOT operand
+
+Since GOT_memory_operand and GOT32_symbol_operand are simple pattern
+matches, don't check ix86_indirect_branch_register here.  If needed,
+-mindirect-branch= will convert indirect branch via GOT slot to a call
+and return thunk.
+
+	Backport from mainline
+	2018-01-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/constraints.md (Bs): Update
+	ix86_indirect_branch_register check.  Don't check
+	ix86_indirect_branch_register with GOT_memory_operand.
+	(Bw): Likewise.
+	* config/i386/predicates.md (GOT_memory_operand): Don't check
+	ix86_indirect_branch_register here.
+	(GOT32_symbol_operand): Likewise.
+
+i386: Rewrite indirect_branch_operand logic
+
+	Backport from mainline
+	2018-01-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/predicates.md (indirect_branch_operand): Rewrite
+	ix86_indirect_branch_register logic.
+---
+ gcc/config/i386/constraints.md                     |  6 ++--
+ gcc/config/i386/i386.md                            | 34 ++++++++++++++--------
+ gcc/config/i386/i386.opt                           |  4 +++
+ gcc/config/i386/predicates.md                      | 21 +++++++------
+ gcc/testsuite/gcc.target/i386/indirect-thunk-1.c   |  2 +-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-2.c   |  2 +-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-3.c   |  2 +-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-4.c   |  2 +-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-5.c   |  2 +-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-6.c   |  2 +-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-7.c   |  2 +-
+ .../gcc.target/i386/indirect-thunk-attr-1.c        |  2 +-
+ .../gcc.target/i386/indirect-thunk-attr-2.c        |  2 +-
+ .../gcc.target/i386/indirect-thunk-attr-3.c        |  2 +-
+ .../gcc.target/i386/indirect-thunk-attr-4.c        |  2 +-
+ .../gcc.target/i386/indirect-thunk-attr-5.c        |  2 +-
+ .../gcc.target/i386/indirect-thunk-attr-6.c        |  2 +-
+ .../gcc.target/i386/indirect-thunk-attr-7.c        |  2 +-
+ .../gcc.target/i386/indirect-thunk-bnd-1.c         |  2 +-
+ .../gcc.target/i386/indirect-thunk-bnd-2.c         |  2 +-
+ .../gcc.target/i386/indirect-thunk-bnd-3.c         |  2 +-
+ .../gcc.target/i386/indirect-thunk-bnd-4.c         |  2 +-
+ .../gcc.target/i386/indirect-thunk-extern-1.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-extern-2.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-extern-3.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-extern-4.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-extern-5.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-extern-6.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-extern-7.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-inline-1.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-inline-2.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-inline-3.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-inline-4.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-inline-5.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-inline-6.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-inline-7.c      |  2 +-
+ .../gcc.target/i386/indirect-thunk-register-1.c    | 22 ++++++++++++++
+ .../gcc.target/i386/indirect-thunk-register-2.c    | 20 +++++++++++++
+ .../gcc.target/i386/indirect-thunk-register-3.c    | 19 ++++++++++++
+ gcc/testsuite/gcc.target/i386/ret-thunk-10.c       |  2 +-
+ gcc/testsuite/gcc.target/i386/ret-thunk-11.c       |  2 +-
+ gcc/testsuite/gcc.target/i386/ret-thunk-12.c       |  2 +-
+ gcc/testsuite/gcc.target/i386/ret-thunk-13.c       |  2 +-
+ gcc/testsuite/gcc.target/i386/ret-thunk-14.c       |  2 +-
+ gcc/testsuite/gcc.target/i386/ret-thunk-15.c       |  2 +-
+ gcc/testsuite/gcc.target/i386/ret-thunk-9.c        |  2 +-
+ 47 files changed, 147 insertions(+), 63 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-register-1.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-register-2.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-register-3.c
+
+diff --git a/src/gcc/config/i386/constraints.md b/src/gcc/config/i386/constraints.md
+index 1a4c701ad..9204c8e84 100644
+--- a/src/gcc/config/i386/constraints.md
++++ b/src/gcc/config/i386/constraints.md
+@@ -172,14 +172,16 @@
+ 
+ (define_constraint "Bs"
+   "@internal Sibcall memory operand."
+-  (ior (and (not (match_test "TARGET_X32"))
++  (ior (and (not (match_test "ix86_indirect_branch_register"))
++	    (not (match_test "TARGET_X32"))
+ 	    (match_operand 0 "sibcall_memory_operand"))
+        (and (match_test "TARGET_X32 && Pmode == DImode")
+ 	    (match_operand 0 "GOT_memory_operand"))))
+ 
+ (define_constraint "Bw"
+   "@internal Call memory operand."
+-  (ior (and (not (match_test "TARGET_X32"))
++  (ior (and (not (match_test "ix86_indirect_branch_register"))
++	    (not (match_test "TARGET_X32"))
+ 	    (match_operand 0 "memory_operand"))
+        (and (match_test "TARGET_X32 && Pmode == DImode")
+ 	    (match_operand 0 "GOT_memory_operand"))))
+diff --git a/src/gcc/config/i386/i386.md b/src/gcc/config/i386/i386.md
+index 2da671e9f..05a88fff3 100644
+--- a/src/gcc/config/i386/i386.md
++++ b/src/gcc/config/i386/i386.md
+@@ -11805,7 +11805,7 @@
+   [(set (pc) (match_operand 0 "indirect_branch_operand"))]
+   ""
+ {
+-  if (TARGET_X32)
++  if (TARGET_X32 || ix86_indirect_branch_register)
+     operands[0] = convert_memory_address (word_mode, operands[0]);
+   cfun->machine->has_local_indirect_jump = true;
+ })
+@@ -11859,7 +11859,7 @@
+ 					 OPTAB_DIRECT);
+     }
+ 
+-  if (TARGET_X32)
++  if (TARGET_X32 || ix86_indirect_branch_register)
+     operands[0] = convert_memory_address (word_mode, operands[0]);
+   cfun->machine->has_local_indirect_jump = true;
+ })
+@@ -12048,7 +12048,7 @@
+   [(call (mem:QI (match_operand:W 0 "memory_operand" "m"))
+ 	 (match_operand 1))
+    (unspec [(const_int 0)] UNSPEC_PEEPSIB)]
+-  "!TARGET_X32"
++  "!TARGET_X32 && !ix86_indirect_branch_register"
+   "* return ix86_output_call_insn (insn, operands[0]);"
+   [(set_attr "type" "call")])
+ 
+@@ -12057,7 +12057,9 @@
+ 	(match_operand:W 1 "memory_operand"))
+    (call (mem:QI (match_dup 0))
+ 	 (match_operand 3))]
+-  "!TARGET_X32 && SIBLING_CALL_P (peep2_next_insn (1))
++  "!TARGET_X32
++   && !ix86_indirect_branch_register
++   && SIBLING_CALL_P (peep2_next_insn (1))
+    && !reg_mentioned_p (operands[0],
+ 			CALL_INSN_FUNCTION_USAGE (peep2_next_insn (1)))"
+   [(parallel [(call (mem:QI (match_dup 1))
+@@ -12070,7 +12072,9 @@
+    (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+    (call (mem:QI (match_dup 0))
+ 	 (match_operand 3))]
+-  "!TARGET_X32 && SIBLING_CALL_P (peep2_next_insn (2))
++  "!TARGET_X32
++   && !ix86_indirect_branch_register
++   && SIBLING_CALL_P (peep2_next_insn (2))
+    && !reg_mentioned_p (operands[0],
+ 			CALL_INSN_FUNCTION_USAGE (peep2_next_insn (2)))"
+   [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+@@ -12092,7 +12096,7 @@
+ })
+ 
+ (define_insn "*call_pop"
+-  [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lmBz"))
++  [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lBwBz"))
+ 	 (match_operand 1))
+    (set (reg:SI SP_REG)
+ 	(plus:SI (reg:SI SP_REG)
+@@ -12112,7 +12116,7 @@
+   [(set_attr "type" "call")])
+ 
+ (define_insn "*sibcall_pop_memory"
+-  [(call (mem:QI (match_operand:SI 0 "memory_operand" "m"))
++  [(call (mem:QI (match_operand:SI 0 "memory_operand" "Bs"))
+ 	 (match_operand 1))
+    (set (reg:SI SP_REG)
+ 	(plus:SI (reg:SI SP_REG)
+@@ -12166,7 +12170,9 @@
+   [(set (match_operand:W 0 "register_operand")
+         (match_operand:W 1 "memory_operand"))
+    (set (pc) (match_dup 0))]
+-  "!TARGET_X32 && peep2_reg_dead_p (2, operands[0])"
++  "!TARGET_X32
++   && !ix86_indirect_branch_register
++   && peep2_reg_dead_p (2, operands[0])"
+   [(set (pc) (match_dup 1))])
+ 
+ ;; Call subroutine, returning value in operand 0
+@@ -12244,7 +12250,7 @@
+  	(call (mem:QI (match_operand:W 1 "memory_operand" "m"))
+ 	      (match_operand 2)))
+    (unspec [(const_int 0)] UNSPEC_PEEPSIB)]
+-  "!TARGET_X32"
++  "!TARGET_X32 && !ix86_indirect_branch_register"
+   "* return ix86_output_call_insn (insn, operands[1]);"
+   [(set_attr "type" "callv")])
+ 
+@@ -12254,7 +12260,9 @@
+    (set (match_operand 2)
+    (call (mem:QI (match_dup 0))
+ 		 (match_operand 3)))]
+-  "!TARGET_X32 && SIBLING_CALL_P (peep2_next_insn (1))
++  "!TARGET_X32
++   && !ix86_indirect_branch_register
++   && SIBLING_CALL_P (peep2_next_insn (1))
+    && !reg_mentioned_p (operands[0],
+ 			CALL_INSN_FUNCTION_USAGE (peep2_next_insn (1)))"
+   [(parallel [(set (match_dup 2)
+@@ -12269,7 +12277,9 @@
+    (set (match_operand 2)
+ 	(call (mem:QI (match_dup 0))
+ 	      (match_operand 3)))]
+-  "!TARGET_X32 && SIBLING_CALL_P (peep2_next_insn (2))
++  "!TARGET_X32
++   && !ix86_indirect_branch_register
++   && SIBLING_CALL_P (peep2_next_insn (2))
+    && !reg_mentioned_p (operands[0],
+ 			CALL_INSN_FUNCTION_USAGE (peep2_next_insn (2)))"
+   [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+@@ -12294,7 +12304,7 @@
+ 
+ (define_insn "*call_value_pop"
+   [(set (match_operand 0)
+-	(call (mem:QI (match_operand:SI 1 "call_insn_operand" "lmBz"))
++	(call (mem:QI (match_operand:SI 1 "call_insn_operand" "lBwBz"))
+ 	      (match_operand 2)))
+    (set (reg:SI SP_REG)
+ 	(plus:SI (reg:SI SP_REG)
+diff --git a/src/gcc/config/i386/i386.opt b/src/gcc/config/i386/i386.opt
+index ad5916fb6..a97f84f68 100644
+--- a/src/gcc/config/i386/i386.opt
++++ b/src/gcc/config/i386/i386.opt
+@@ -921,3 +921,7 @@ Enum(indirect_branch) String(thunk-inline) Value(indirect_branch_thunk_inline)
+ 
+ EnumValue
+ Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern)
++
++mindirect-branch-register
++Target Report Var(ix86_indirect_branch_register) Init(0)
++Force indirect call and jump via register.
+diff --git a/src/gcc/config/i386/predicates.md b/src/gcc/config/i386/predicates.md
+index 93dda7bb0..d1f0a7dbf 100644
+--- a/src/gcc/config/i386/predicates.md
++++ b/src/gcc/config/i386/predicates.md
+@@ -593,7 +593,8 @@
+ ;; Test for a valid operand for indirect branch.
+ (define_predicate "indirect_branch_operand"
+   (ior (match_operand 0 "register_operand")
+-       (and (not (match_test "TARGET_X32"))
++       (and (not (match_test "ix86_indirect_branch_register"))
++	    (not (match_test "TARGET_X32"))
+ 	    (match_operand 0 "memory_operand"))))
+ 
+ ;; Return true if OP is a memory operands that can be used in sibcalls.
+@@ -636,20 +637,22 @@
+   (ior (match_test "constant_call_address_operand
+ 		     (op, mode == VOIDmode ? mode : Pmode)")
+        (match_operand 0 "call_register_no_elim_operand")
+-       (ior (and (not (match_test "TARGET_X32"))
+-		 (match_operand 0 "memory_operand"))
+-	    (and (match_test "TARGET_X32 && Pmode == DImode")
+-		 (match_operand 0 "GOT_memory_operand")))))
++       (and (not (match_test "ix86_indirect_branch_register"))
++	    (ior (and (not (match_test "TARGET_X32"))
++		      (match_operand 0 "memory_operand"))
++		 (and (match_test "TARGET_X32 && Pmode == DImode")
++		      (match_operand 0 "GOT_memory_operand"))))))
+ 
+ ;; Similarly, but for tail calls, in which we cannot allow memory references.
+ (define_special_predicate "sibcall_insn_operand"
+   (ior (match_test "constant_call_address_operand
+ 		     (op, mode == VOIDmode ? mode : Pmode)")
+        (match_operand 0 "register_no_elim_operand")
+-       (ior (and (not (match_test "TARGET_X32"))
+-		 (match_operand 0 "sibcall_memory_operand"))
+-	    (and (match_test "TARGET_X32 && Pmode == DImode")
+-		 (match_operand 0 "GOT_memory_operand")))))
++       (and (not (match_test "ix86_indirect_branch_register"))
++	    (ior (and (not (match_test "TARGET_X32"))
++		      (match_operand 0 "sibcall_memory_operand"))
++		 (and (match_test "TARGET_X32 && Pmode == DImode")
++		      (match_operand 0 "GOT_memory_operand"))))))
+ 
+ ;; Return true if OP is a 32-bit GOT symbol operand.
+ (define_predicate "GOT32_symbol_operand"
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c
+index e365ef569..60d09881a 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c
+index 05a51ad91..aac751637 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c
+index 3c0d4c39f..9e24a3853 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mno-indirect-branch-register -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c
+index 14d4ef6dd..127b5d945 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mno-indirect-branch-register -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-5.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-5.c
+index b4836c38d..fcaa18d10 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-5.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-5.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target *-*-linux* } } */
+-/* { dg-options "-O2 -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk" } */
+ 
+ extern void bar (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-6.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-6.c
+index 1f06bd1af..e4649283d 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-6.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-6.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target *-*-linux* } } */
+-/* { dg-options "-O2 -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mno-indirect-branch-register -mno-indirect-branch-register -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk" } */
+ 
+ extern void bar (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-7.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-7.c
+index bc6b47a63..17c2d0faf 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-7.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-7.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
+ 
+ void func0 (void);
+ void func1 (void);
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c
+index 2257be3af..9194ccf3c 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c
+index e9cfdc587..e51f261a6 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c
+index f938db050..4aeec1833 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c
+index 4e5859969..ac0e5999f 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c
+index b8d50249d..573cf1ef0 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c
+index 455adabfe..b2b37fc6e 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c
+index 4595b841e..4a43e1999 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-7.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fno-pic" } */
+ 
+ void func0 (void);
+ void func1 (void);
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-1.c
+index 5e3e118e9..ac84ab623 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-1.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target { ! x32 } } } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fno-pic" } */
+ 
+ void (*dispatch) (char *);
+ char buf[10];
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-2.c
+index 2801aa419..ce655e8be 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-2.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target { ! x32 } } } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fno-pic" } */
+ 
+ void (*dispatch) (char *);
+ char buf[10];
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-3.c
+index 70b4fb36e..d34485a00 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-3.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-3.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target { *-*-linux* && { ! x32 } } } } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fpic -fno-plt" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fpic -fno-plt" } */
+ 
+ void bar (char *);
+ char buf[10];
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-4.c
+index 3baf03ee7..0e19830de 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-4.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-bnd-4.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target { *-*-linux* && { ! x32 } } } } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fpic -fno-plt" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk -fcheck-pointer-bounds -mmpx -fpic -fno-plt" } */
+ 
+ void bar (char *);
+ char buf[10];
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c
+index edeb26421..579441f25 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c
+index 1d00413a7..c92e6f2b0 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c
+index 06ebf1c90..d9964c25b 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c
+index 1c8f94466..d4dca4dc5 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-5.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-5.c
+index 21740ac5b..5c07e02df 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-5.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-5.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target *-*-linux* } } */
+-/* { dg-options "-O2 -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk-extern" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk-extern" } */
+ 
+ extern void bar (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-6.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-6.c
+index a77c1f470..3eb440693 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-6.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-6.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target *-*-linux* } } */
+-/* { dg-options "-O2 -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk-extern" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk-extern" } */
+ 
+ extern void bar (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c
+index 86e9fd1f1..aece93836 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-7.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
+ 
+ void func0 (void);
+ void func1 (void);
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c
+index 3ecde8788..3aba5e8c8 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c
+index df32a19a2..0f0181d66 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c
+index 9540996de..2eef6f35a 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c
+index f3db6e244..e825a10f1 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
+ 
+ typedef void (*dispatch_t)(long offset);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-5.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-5.c
+index 0f687c3b0..c6d77e103 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-5.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-5.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target *-*-linux* } } */
+-/* { dg-options "-O2 -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk-inline" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk-inline" } */
+ 
+ extern void bar (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-6.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-6.c
+index b27c6fc96..6454827b7 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-6.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-6.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target *-*-linux* } } */
+-/* { dg-options "-O2 -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk-inline" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -fpic -fno-plt -mindirect-branch=thunk-inline" } */
+ 
+ extern void bar (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-7.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-7.c
+index 764a375fc..c67066cf1 100644
+--- a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-7.c
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-7.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
+ 
+ void func0 (void);
+ void func1 (void);
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-register-1.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-register-1.c
+new file mode 100644
+index 000000000..7d396a319
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-register-1.c
+@@ -0,0 +1,22 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk -mindirect-branch-register -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch;
++
++void
++male_indirect_jump (long offset)
++{
++  dispatch(offset);
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" } } */
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "mov\[ \t\](%eax|%rax), \\((%esp|%rsp)\\)" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler-not "push(?:l|q)\[ \t\]*_?dispatch"  } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" } } */
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk\n" } } */
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk_bnd\n" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-register-2.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-register-2.c
+new file mode 100644
+index 000000000..e7e616bb2
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-register-2.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk-inline -mindirect-branch-register -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch;
++
++void
++male_indirect_jump (long offset)
++{
++  dispatch(offset);
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "call\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler "mov\[ \t\](%eax|%rax), \\((%esp|%rsp)\\)" } } */
++/* { dg-final { scan-assembler {\tpause} } } */
++/* { dg-final { scan-assembler-not "push(?:l|q)\[ \t\]*_?dispatch"  } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" } } */
++/* { dg-final { scan-assembler-not "__x86_indirect_thunk" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-register-3.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-register-3.c
+new file mode 100644
+index 000000000..5320e923b
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-register-3.c
+@@ -0,0 +1,19 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=thunk-extern -mindirect-branch-register -fno-pic" } */
++
++typedef void (*dispatch_t)(long offset);
++
++dispatch_t dispatch;
++
++void
++male_indirect_jump (long offset)
++{
++  dispatch(offset);
++}
++
++/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk_(r|e)ax" } } */
++/* { dg-final { scan-assembler-not "push(?:l|q)\[ \t\]*_?dispatch"  } } */
++/* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" } } */
++/* { dg-final { scan-assembler-not {\t(pause|pause|nop)} } } */
++/* { dg-final { scan-assembler-not "jmp\[ \t\]*\.LIND" } } */
++/* { dg-final { scan-assembler-not "call\[ \t\]*\.LIND" } } */
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-10.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-10.c
+index 3a6727b5c..e6fea84a4 100644
+--- a/src/gcc/testsuite/gcc.target/i386/ret-thunk-10.c
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-10.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=thunk-inline -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mno-indirect-branch-register -mfunction-return=thunk-inline -mindirect-branch=thunk -fno-pic" } */
+ 
+ extern void (*bar) (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-11.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-11.c
+index b8f681883..e239ec454 100644
+--- a/src/gcc/testsuite/gcc.target/i386/ret-thunk-11.c
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-11.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=thunk-extern -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mno-indirect-branch-register -mno-indirect-branch-register -mno-indirect-branch-register -mfunction-return=thunk-extern -mindirect-branch=thunk -fno-pic" } */
+ 
+ extern void (*bar) (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-12.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-12.c
+index 01b0a02f8..fa3181303 100644
+--- a/src/gcc/testsuite/gcc.target/i386/ret-thunk-12.c
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-12.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mno-indirect-branch-register -mno-indirect-branch-register -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk -fno-pic" } */
+ 
+ extern void (*bar) (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-13.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-13.c
+index 4b497b5f8..fd5b41fdd 100644
+--- a/src/gcc/testsuite/gcc.target/i386/ret-thunk-13.c
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-13.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-inline -fno-pic" } */
+ 
+ extern void (*bar) (void);
+ extern int foo (void) __attribute__ ((function_return("thunk")));
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-14.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-14.c
+index 4ae4c44a3..d606373ea 100644
+--- a/src/gcc/testsuite/gcc.target/i386/ret-thunk-14.c
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-14.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=thunk-extern -fno-pic" } */
+ 
+ extern void (*bar) (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-15.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-15.c
+index 5b5bc765a..75e45e226 100644
+--- a/src/gcc/testsuite/gcc.target/i386/ret-thunk-15.c
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-15.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=keep -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mno-indirect-branch-register -mno-indirect-branch-register -mno-indirect-branch-register -mfunction-return=keep -mindirect-branch=keep -fno-pic" } */
+ 
+ extern void (*bar) (void);
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-9.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-9.c
+index fa24a1f73..d1db41cc1 100644
+--- a/src/gcc/testsuite/gcc.target/i386/ret-thunk-9.c
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-9.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mfunction-return=thunk -mindirect-branch=thunk -fno-pic" } */
++/* { dg-options "-O2 -mno-indirect-branch-register -mno-indirect-branch-register -mfunction-return=thunk -mindirect-branch=thunk -fno-pic" } */
+ 
+ extern void (*bar) (void);
+ 
+-- 
+2.16.1
+
--- gcc-6-6.4.0.orig/debian/patches/0007-x86-Add-V-register-operand-modifier.diff
+++ gcc-6-6.4.0/debian/patches/0007-x86-Add-V-register-operand-modifier.diff
@@ -0,0 +1,118 @@
+From 3fdf3ef78715a58a01a9f4ccd1836e5ceca636c5 Mon Sep 17 00:00:00 2001
+From: "H.J. Lu" <hjl.tools@gmail.com>
+Date: Sat, 6 Jan 2018 22:29:56 -0800
+Subject: [PATCH] x86: Add 'V' register operand modifier
+
+Add 'V', a special modifier which prints the name of the full integer
+register without '%'.  For
+
+extern void (*func_p) (void);
+
+void
+foo (void)
+{
+  asm ("call __x86_indirect_thunk_%V0" : : "a" (func_p));
+}
+
+it generates:
+
+foo:
+	movq	func_p(%rip), %rax
+	call	__x86_indirect_thunk_rax
+	ret
+
+gcc/
+
+	Backport from mainline
+	2018-01-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/i386.c (print_reg): Print the name of the full
+	integer register without '%'.
+	(ix86_print_operand): Handle 'V'.
+
+gcc/testsuite/
+
+	Backport from mainline
+	2018-01-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gcc.target/i386/indirect-thunk-register-4.c: New test.
+---
+ gcc/config/i386/i386.c                                    | 13 ++++++++++++-
+ gcc/testsuite/gcc.target/i386/indirect-thunk-register-4.c | 13 +++++++++++++
+ 3 files changed, 28 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-register-4.c
+
+diff --git a/src/gcc/config/i386/i386.c b/src/gcc/config/i386/i386.c
+index 34e26a3a3..eeca7e5e4 100644
+--- a/src/gcc/config/i386/i386.c
++++ b/src/gcc/config/i386/i386.c
+@@ -16869,6 +16869,7 @@ put_condition_code (enum rtx_code code, machine_mode mode, bool reverse,
+    If CODE is 'h', pretend the reg is the 'high' byte register.
+    If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
+    If CODE is 'd', duplicate the operand for AVX instruction.
++   If CODE is 'V', print naked full integer register name without %.
+  */
+ 
+ void
+@@ -16879,7 +16880,7 @@ print_reg (rtx x, int code, FILE *file)
+   unsigned int regno;
+   bool duplicated;
+ 
+-  if (ASSEMBLER_DIALECT == ASM_ATT)
++  if (ASSEMBLER_DIALECT == ASM_ATT && code != 'V')
+     putc ('%', file);
+ 
+   if (x == pc_rtx)
+@@ -16922,6 +16923,14 @@ print_reg (rtx x, int code, FILE *file)
+ 	      && regno != FPSR_REG
+ 	      && regno != FPCR_REG);
+ 
++  if (code == 'V')
++    {
++      if (GENERAL_REGNO_P (regno))
++	msize = GET_MODE_SIZE (word_mode);
++      else
++	error ("'V' modifier on non-integer register");
++    }
++
+   duplicated = code == 'd' && TARGET_AVX;
+ 
+   switch (msize)
+@@ -17035,6 +17044,7 @@ print_reg (rtx x, int code, FILE *file)
+    & -- print some in-use local-dynamic symbol name.
+    H -- print a memory address offset by 8; used for sse high-parts
+    Y -- print condition for XOP pcom* instruction.
++   V -- print naked full integer register name without %.
+    + -- print a branch hint as 'cs' or 'ds' prefix
+    ; -- print a semicolon (after prefixes due to bug in older gas).
+    ~ -- print "i" if TARGET_AVX2, "f" otherwise.
+@@ -17259,6 +17269,7 @@ ix86_print_operand (FILE *file, rtx x, int code)
+ 	case 'X':
+ 	case 'P':
+ 	case 'p':
++	case 'V':
+ 	  break;
+ 
+ 	case 's':
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-register-4.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-register-4.c
+new file mode 100644
+index 000000000..f0cd9b75b
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-register-4.c
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mindirect-branch=keep -fno-pic" } */
++
++extern void (*func_p) (void);
++
++void
++foo (void)
++{
++  asm("call __x86_indirect_thunk_%V0" : : "a" (func_p));
++}
++
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_eax" { target ia32 } } } */
++/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_rax" { target { ! ia32 } } } } */
+-- 
+2.16.1
+
--- gcc-6-6.4.0.orig/debian/patches/0008-x86-Disallow-mindirect-branch-mfunction-return-with-m.diff
+++ gcc-6-6.4.0/debian/patches/0008-x86-Disallow-mindirect-branch-mfunction-return-with-m.diff
@@ -0,0 +1,266 @@
+From c12509757e2b390cb7ae3eb7b150e40654c1f770 Mon Sep 17 00:00:00 2001
+From: "H.J. Lu" <hjl.tools@gmail.com>
+Date: Sat, 13 Jan 2018 18:01:54 -0800
+Subject: [PATCH] x86: Disallow -mindirect-branch=/-mfunction-return= with
+ -mcmodel=large
+
+Since the thunk function may not be reachable in large code model,
+-mcmodel=large is incompatible with -mindirect-branch=thunk,
+-mindirect-branch=thunk-extern, -mfunction-return=thunk and
+-mfunction-return=thunk-extern.  Issue an error when they are used with
+-mcmodel=large.
+
+gcc/
+
+	Backport from mainline
+	2018-01-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/i386.c (ix86_set_indirect_branch_type): Disallow
+	-mcmodel=large with -mindirect-branch=thunk,
+	-mindirect-branch=thunk-extern, -mfunction-return=thunk and
+	-mfunction-return=thunk-extern.
+
+gcc/testsuite/
+
+	Backport from mainline
+	2018-01-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gcc.target/i386/indirect-thunk-10.c: New test.
+	* gcc.target/i386/indirect-thunk-8.c: Likewise.
+	* gcc.target/i386/indirect-thunk-9.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-10.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-11.c: Likewise.
+	* gcc.target/i386/indirect-thunk-attr-9.c: Likewise.
+	* gcc.target/i386/ret-thunk-17.c: Likewise.
+	* gcc.target/i386/ret-thunk-18.c: Likewise.
+	* gcc.target/i386/ret-thunk-19.c: Likewise.
+	* gcc.target/i386/ret-thunk-20.c: Likewise.
+	* gcc.target/i386/ret-thunk-21.c: Likewise.
+---
+ gcc/config/i386/i386.c                             | 26 ++++++++++++++++++++++
+ gcc/testsuite/gcc.target/i386/indirect-thunk-10.c  |  7 ++++++
+ gcc/testsuite/gcc.target/i386/indirect-thunk-8.c   |  7 ++++++
+ gcc/testsuite/gcc.target/i386/indirect-thunk-9.c   |  7 ++++++
+ .../gcc.target/i386/indirect-thunk-attr-10.c       |  9 ++++++++
+ .../gcc.target/i386/indirect-thunk-attr-11.c       |  9 ++++++++
+ .../gcc.target/i386/indirect-thunk-attr-9.c        |  9 ++++++++
+ gcc/testsuite/gcc.target/i386/ret-thunk-17.c       |  7 ++++++
+ gcc/testsuite/gcc.target/i386/ret-thunk-18.c       |  8 +++++++
+ gcc/testsuite/gcc.target/i386/ret-thunk-19.c       |  8 +++++++
+ gcc/testsuite/gcc.target/i386/ret-thunk-20.c       |  9 ++++++++
+ gcc/testsuite/gcc.target/i386/ret-thunk-21.c       |  9 ++++++++
+ 13 files changed, 126 insertions(+)
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-10.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-8.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-9.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-attr-10.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-attr-11.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-attr-9.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-17.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-18.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-19.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-20.c
+ create mode 100644 gcc/testsuite/gcc.target/i386/ret-thunk-21.c
+
+diff --git a/src/gcc/config/i386/i386.c b/src/gcc/config/i386/i386.c
+index eeca7e5e4..9c038bee0 100644
+--- a/src/gcc/config/i386/i386.c
++++ b/src/gcc/config/i386/i386.c
+@@ -6389,6 +6389,19 @@ ix86_set_indirect_branch_type (tree fndecl)
+ 	}
+       else
+ 	cfun->machine->indirect_branch_type = ix86_indirect_branch;
++
++      /* -mcmodel=large is not compatible with -mindirect-branch=thunk
++	 nor -mindirect-branch=thunk-extern.  */
++      if ((ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
++	  && ((cfun->machine->indirect_branch_type
++	       == indirect_branch_thunk_extern)
++	      || (cfun->machine->indirect_branch_type
++		  == indirect_branch_thunk)))
++	error ("%<-mindirect-branch=%s%> and %<-mcmodel=large%> are not "
++	       "compatible",
++	       ((cfun->machine->indirect_branch_type
++		 == indirect_branch_thunk_extern)
++		? "thunk-extern" : "thunk"));
+     }
+ 
+   if (cfun->machine->function_return_type == indirect_branch_unset)
+@@ -6414,6 +6427,19 @@ ix86_set_indirect_branch_type (tree fndecl)
+ 	}
+       else
+ 	cfun->machine->function_return_type = ix86_function_return;
++
++      /* -mcmodel=large is not compatible with -mfunction-return=thunk
++	 nor -mfunction-return=thunk-extern.  */
++      if ((ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
++	  && ((cfun->machine->function_return_type
++	       == indirect_branch_thunk_extern)
++	      || (cfun->machine->function_return_type
++		  == indirect_branch_thunk)))
++	error ("%<-mfunction-return=%s%> and %<-mcmodel=large%> are not "
++	       "compatible",
++	       ((cfun->machine->function_return_type
++		 == indirect_branch_thunk_extern)
++		? "thunk-extern" : "thunk"));
+     }
+ }
+ 
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-10.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-10.c
+new file mode 100644
+index 000000000..a0674bd23
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-10.c
+@@ -0,0 +1,7 @@
++/* { dg-do compile { target { lp64 } } } */
++/* { dg-options "-O2 -mindirect-branch=thunk-inline -mfunction-return=keep -mcmodel=large" } */
++
++void
++bar (void)
++{
++}
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-8.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-8.c
+new file mode 100644
+index 000000000..7a80a8986
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-8.c
+@@ -0,0 +1,7 @@
++/* { dg-do compile { target { lp64 } } } */
++/* { dg-options "-O2 -mindirect-branch=thunk -mfunction-return=keep -mcmodel=large" } */
++
++void
++bar (void)
++{ /* { dg-error "'-mindirect-branch=thunk' and '-mcmodel=large' are not compatible" } */
++}
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-9.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-9.c
+new file mode 100644
+index 000000000..d4d45c511
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-9.c
+@@ -0,0 +1,7 @@
++/* { dg-do compile { target { lp64 } } } */
++/* { dg-options "-O2 -mindirect-branch=thunk-extern -mfunction-return=keep -mcmodel=large" } */
++
++void
++bar (void)
++{ /* { dg-error "'-mindirect-branch=thunk-extern' and '-mcmodel=large' are not compatible" } */
++}
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-10.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-10.c
+new file mode 100644
+index 000000000..3a2aeaddb
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-10.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile { target { lp64 } } } */
++/* { dg-options "-O2 -mindirect-branch=keep -mfunction-return=keep -mcmodel=large" } */
++/* { dg-additional-options "-fPIC" { target fpic } } */
++
++__attribute__ ((indirect_branch("thunk-extern")))
++void
++bar (void)
++{ /* { dg-error "'-mindirect-branch=thunk-extern' and '-mcmodel=large' are not compatible" } */
++}
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-11.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-11.c
+new file mode 100644
+index 000000000..8e52f032b
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-11.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile { target { lp64 } } } */
++/* { dg-options "-O2 -mindirect-branch=keep -mfunction-return=keep -mcmodel=large" } */
++/* { dg-additional-options "-fPIC" { target fpic } } */
++
++__attribute__ ((indirect_branch("thunk-inline")))
++void
++bar (void)
++{
++}
+diff --git a/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-9.c b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-9.c
+new file mode 100644
+index 000000000..bdaa4f691
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-9.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile { target { lp64 } } } */
++/* { dg-options "-O2 -mindirect-branch=keep -mfunction-return=keep -mcmodel=large" } */
++/* { dg-additional-options "-fPIC" { target fpic } } */
++
++__attribute__ ((indirect_branch("thunk")))
++void
++bar (void)
++{ /* { dg-error "'-mindirect-branch=thunk' and '-mcmodel=large' are not compatible" } */
++}
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-17.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-17.c
+new file mode 100644
+index 000000000..0605e2c65
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-17.c
+@@ -0,0 +1,7 @@
++/* { dg-do compile { target { lp64 } } } */
++/* { dg-options "-O2 -mfunction-return=thunk -mindirect-branch=keep -mcmodel=large" } */
++
++void
++bar (void)
++{ /* { dg-error "'-mfunction-return=thunk' and '-mcmodel=large' are not compatible" } */
++}
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-18.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-18.c
+new file mode 100644
+index 000000000..307019dc2
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-18.c
+@@ -0,0 +1,8 @@
++/* { dg-do compile { target { lp64 } } } */
++/* { dg-options "-O2 -mfunction-return=thunk-extern -mindirect-branch=keep -mcmodel=large" } */
++/* { dg-additional-options "-fPIC" { target fpic } } */
++
++void
++bar (void)
++{ /* { dg-error "'-mfunction-return=thunk-extern' and '-mcmodel=large' are not compatible" } */
++}
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-19.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-19.c
+new file mode 100644
+index 000000000..772617f40
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-19.c
+@@ -0,0 +1,8 @@
++/* { dg-do compile { target { lp64 } } } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=keep -mcmodel=large" } */
++
++__attribute__ ((function_return("thunk")))
++void
++bar (void)
++{ /* { dg-error "'-mfunction-return=thunk' and '-mcmodel=large' are not compatible" } */
++}
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-20.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-20.c
+new file mode 100644
+index 000000000..1e9f9bd5a
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-20.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile { target { lp64 } } } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=keep -mcmodel=large" } */
++/* { dg-additional-options "-fPIC" { target fpic } } */
++
++__attribute__ ((function_return("thunk-extern")))
++void
++bar (void)
++{ /* { dg-error "'-mfunction-return=thunk-extern' and '-mcmodel=large' are not compatible" } */
++}
+diff --git a/src/gcc/testsuite/gcc.target/i386/ret-thunk-21.c b/src/gcc/testsuite/gcc.target/i386/ret-thunk-21.c
+new file mode 100644
+index 000000000..eea07f7ab
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/i386/ret-thunk-21.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile { target { lp64 } } } */
++/* { dg-options "-O2 -mfunction-return=keep -mindirect-branch=keep -mcmodel=large" } */
++/* { dg-additional-options "-fPIC" { target fpic } } */
++
++__attribute__ ((function_return("thunk-inline")))
++void
++bar (void)
++{
++}
+-- 
+2.16.1
+
--- gcc-6-6.4.0.orig/debian/patches/0009-Use-INVALID_REGNUM-in-indirect-thunk-processing.diff
+++ gcc-6-6.4.0/debian/patches/0009-Use-INVALID_REGNUM-in-indirect-thunk-processing.diff
@@ -0,0 +1,121 @@
+From ec9350eeb3d5975e5fe269b6facee3e7b917cc6a Mon Sep 17 00:00:00 2001
+From: uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Thu, 25 Jan 2018 19:39:01 +0000
+Subject: [PATCH] Use INVALID_REGNUM in indirect thunk processing
+
+	Backport from mainline
+	2018-01-17  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.c (indirect_thunk_name): Declare regno
+	as unsigned int.  Compare regno with INVALID_REGNUM.
+	(output_indirect_thunk): Ditto.
+	(output_indirect_thunk_function): Ditto.
+	(ix86_code_end): Declare regno as unsigned int.  Use INVALID_REGNUM
+	in the call to output_indirect_thunk_function.
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-7-branch@257067 138bc75d-0d04-0410-961f-82ee72b054a4
+---
+ gcc/config/i386/i386.c | 30 +++++++++++++++---------------
+ 1 file changed, 15 insertions(+), 15 deletions(-)
+
+diff --git a/src/gcc/config/i386/i386.c b/src/gcc/config/i386/i386.c
+index 9c038bee0..40126579c 100644
+--- a/src/gcc/config/i386/i386.c
++++ b/src/gcc/config/i386/i386.c
+@@ -11087,16 +11087,16 @@ static int indirect_thunks_bnd_used;
+ /* Fills in the label name that should be used for the indirect thunk.  */
+ 
+ static void
+-indirect_thunk_name (char name[32], int regno, bool need_bnd_p,
+-		     bool ret_p)
++indirect_thunk_name (char name[32], unsigned int regno,
++		     bool need_bnd_p, bool ret_p)
+ {
+-  if (regno >= 0 && ret_p)
++  if (regno != INVALID_REGNUM && ret_p)
+     gcc_unreachable ();
+ 
+   if (USE_HIDDEN_LINKONCE)
+     {
+       const char *bnd = need_bnd_p ? "_bnd" : "";
+-      if (regno >= 0)
++      if (regno != INVALID_REGNUM)
+ 	{
+ 	  const char *reg_prefix;
+ 	  if (LEGACY_INT_REGNO_P (regno))
+@@ -11114,7 +11114,7 @@ indirect_thunk_name (char name[32], int regno, bool need_bnd_p,
+     }
+   else
+     {
+-      if (regno >= 0)
++      if (regno != INVALID_REGNUM)
+ 	{
+ 	  if (need_bnd_p)
+ 	    ASM_GENERATE_INTERNAL_LABEL (name, "LITBR", regno);
+@@ -11166,7 +11166,7 @@ indirect_thunk_name (char name[32], int regno, bool need_bnd_p,
+  */
+ 
+ static void
+-output_indirect_thunk (bool need_bnd_p, int regno)
++output_indirect_thunk (bool need_bnd_p, unsigned int regno)
+ {
+   char indirectlabel1[32];
+   char indirectlabel2[32];
+@@ -11196,7 +11196,7 @@ output_indirect_thunk (bool need_bnd_p, int regno)
+ 
+   ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, indirectlabel2);
+ 
+-  if (regno >= 0)
++  if (regno != INVALID_REGNUM)
+     {
+       /* MOV.  */
+       rtx xops[2];
+@@ -11220,12 +11220,12 @@ output_indirect_thunk (bool need_bnd_p, int regno)
+ }
+ 
+ /* Output a funtion with a call and return thunk for indirect branch.
+-   If BND_P is true, the BND prefix is needed.   If REGNO != -1,  the
+-   function address is in REGNO.  Otherwise, the function address is
++   If BND_P is true, the BND prefix is needed.  If REGNO != INVALID_REGNUM,
++   the function address is in REGNO.  Otherwise, the function address is
+    on the top of stack.  */
+ 
+ static void
+-output_indirect_thunk_function (bool need_bnd_p, int regno)
++output_indirect_thunk_function (bool need_bnd_p, unsigned int regno)
+ {
+   char name[32];
+   tree decl;
+@@ -11274,7 +11274,7 @@ output_indirect_thunk_function (bool need_bnd_p, int regno)
+ 	ASM_OUTPUT_LABEL (asm_out_file, name);
+       }
+ 
+-  if (regno < 0)
++  if (regno == INVALID_REGNUM)
+     {
+       /* Create alias for __x86.return_thunk/__x86.return_thunk_bnd.  */
+       char alias[32];
+@@ -11348,16 +11348,16 @@ static void
+ ix86_code_end (void)
+ {
+   rtx xops[2];
+-  int regno;
++  unsigned int regno;
+ 
+   if (indirect_thunk_needed)
+-    output_indirect_thunk_function (false, -1);
++    output_indirect_thunk_function (false, INVALID_REGNUM);
+   if (indirect_thunk_bnd_needed)
+-    output_indirect_thunk_function (true, -1);
++    output_indirect_thunk_function (true, INVALID_REGNUM);
+ 
+   for (regno = FIRST_REX_INT_REG; regno <= LAST_REX_INT_REG; regno++)
+     {
+-      int i = regno - FIRST_REX_INT_REG + LAST_INT_REG + 1;
++      unsigned int i = regno - FIRST_REX_INT_REG + LAST_INT_REG + 1;
+       if ((indirect_thunks_used & (1 << i)))
+ 	output_indirect_thunk_function (false, regno);
+ 
+-- 
+2.16.1
+
--- gcc-6-6.4.0.orig/debian/patches/CVE-2016-9840.diff
+++ gcc-6-6.4.0/debian/patches/CVE-2016-9840.diff
@@ -0,0 +1,69 @@
+commit 6a043145ca6e9c55184013841a67b2fef87e44c0
+Author: Mark Adler <madler@alumni.caltech.edu>
+Date:   Wed Sep 21 23:35:50 2016 -0700
+
+    Remove offset pointer optimization in inftrees.c.
+    
+    inftrees.c was subtracting an offset from a pointer to an array,
+    in order to provide a pointer that allowed indexing starting at
+    the offset. This is not compliant with the C standard, for which
+    the behavior of a pointer decremented before its allocated memory
+    is undefined. Per the recommendation of a security audit of the
+    zlib code by Trail of Bits and TrustInSoft, in support of the
+    Mozilla Foundation, this tiny optimization was removed, in order
+    to avoid the possibility of undefined behavior.
+
+diff --git a/inftrees.c b/inftrees.c
+index 22fcd66..0d2670d 100644
+--- a/src/zlib/inftrees.c
++++ b/src/zlib/inftrees.c
+@@ -54,7 +54,7 @@ unsigned short FAR *work;
+     code FAR *next;             /* next available space in table */
+     const unsigned short FAR *base;     /* base value table to use */
+     const unsigned short FAR *extra;    /* extra bits table to use */
+-    int end;                    /* use base and extra for symbol > end */
++    unsigned match;             /* use base and extra for symbol >= match */
+     unsigned short count[MAXBITS+1];    /* number of codes of each length */
+     unsigned short offs[MAXBITS+1];     /* offsets in table for each length */
+     static const unsigned short lbase[31] = { /* Length codes 257..285 base */
+@@ -181,19 +181,17 @@ unsigned short FAR *work;
+     switch (type) {
+     case CODES:
+         base = extra = work;    /* dummy value--not used */
+-        end = 19;
++        match = 20;
+         break;
+     case LENS:
+         base = lbase;
+-        base -= 257;
+         extra = lext;
+-        extra -= 257;
+-        end = 256;
++        match = 257;
+         break;
+     default:            /* DISTS */
+         base = dbase;
+         extra = dext;
+-        end = -1;
++        match = 0;
+     }
+ 
+     /* initialize state for loop */
+@@ -216,13 +214,13 @@ unsigned short FAR *work;
+     for (;;) {
+         /* create table entry */
+         here.bits = (unsigned char)(len - drop);
+-        if ((int)(work[sym]) < end) {
++        if (work[sym] + 1 < match) {
+             here.op = (unsigned char)0;
+             here.val = work[sym];
+         }
+-        else if ((int)(work[sym]) > end) {
+-            here.op = (unsigned char)(extra[work[sym]]);
+-            here.val = base[work[sym]];
++        else if (work[sym] >= match) {
++            here.op = (unsigned char)(extra[work[sym] - match]);
++            here.val = base[work[sym] - match];
+         }
+         else {
+             here.op = (unsigned char)(32 + 64);         /* end of block */
--- gcc-6-6.4.0.orig/debian/patches/CVE-2016-9841.diff
+++ gcc-6-6.4.0/debian/patches/CVE-2016-9841.diff
@@ -0,0 +1,222 @@
+commit 9aaec95e82117c1cb0f9624264c3618fc380cecb
+Author: Mark Adler <madler@alumni.caltech.edu>
+Date:   Wed Sep 21 22:25:21 2016 -0700
+
+    Use post-increment only in inffast.c.
+    
+    An old inffast.c optimization turns out to not be optimal anymore
+    with modern compilers, and furthermore was not compliant with the
+    C standard, for which decrementing a pointer before its allocated
+    memory is undefined. Per the recommendation of a security audit of
+    the zlib code by Trail of Bits and TrustInSoft, in support of the
+    Mozilla Foundation, this "optimization" was removed, in order to
+    avoid the possibility of undefined behavior.
+
+diff --git a/inffast.c b/inffast.c
+index bda59ce..f0d163d 100644
+--- a/src/zlib/inffast.c
++++ b/src/zlib/inffast.c
+@@ -10,25 +10,6 @@
+ 
+ #ifndef ASMINF
+ 
+-/* Allow machine dependent optimization for post-increment or pre-increment.
+-   Based on testing to date,
+-   Pre-increment preferred for:
+-   - PowerPC G3 (Adler)
+-   - MIPS R5000 (Randers-Pehrson)
+-   Post-increment preferred for:
+-   - none
+-   No measurable difference:
+-   - Pentium III (Anderson)
+-   - M68060 (Nikl)
+- */
+-#ifdef POSTINC
+-#  define OFF 0
+-#  define PUP(a) *(a)++
+-#else
+-#  define OFF 1
+-#  define PUP(a) *++(a)
+-#endif
+-
+ /*
+    Decode literal, length, and distance codes and write out the resulting
+    literal and match bytes until either not enough input or output is
+@@ -96,9 +77,9 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+ 
+     /* copy state to local variables */
+     state = (struct inflate_state FAR *)strm->state;
+-    in = strm->next_in - OFF;
++    in = strm->next_in;
+     last = in + (strm->avail_in - 5);
+-    out = strm->next_out - OFF;
++    out = strm->next_out;
+     beg = out - (start - strm->avail_out);
+     end = out + (strm->avail_out - 257);
+ #ifdef INFLATE_STRICT
+@@ -119,9 +100,9 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+        input data or output space */
+     do {
+         if (bits < 15) {
+-            hold += (unsigned long)(PUP(in)) << bits;
++            hold += (unsigned long)(*in++) << bits;
+             bits += 8;
+-            hold += (unsigned long)(PUP(in)) << bits;
++            hold += (unsigned long)(*in++) << bits;
+             bits += 8;
+         }
+         here = lcode[hold & lmask];
+@@ -134,14 +115,14 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+             Tracevv((stderr, here.val >= 0x20 && here.val < 0x7f ?
+                     "inflate:         literal '%c'\n" :
+                     "inflate:         literal 0x%02x\n", here.val));
+-            PUP(out) = (unsigned char)(here.val);
++            *out++ = (unsigned char)(here.val);
+         }
+         else if (op & 16) {                     /* length base */
+             len = (unsigned)(here.val);
+             op &= 15;                           /* number of extra bits */
+             if (op) {
+                 if (bits < op) {
+-                    hold += (unsigned long)(PUP(in)) << bits;
++                    hold += (unsigned long)(*in++) << bits;
+                     bits += 8;
+                 }
+                 len += (unsigned)hold & ((1U << op) - 1);
+@@ -150,9 +131,9 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+             }
+             Tracevv((stderr, "inflate:         length %u\n", len));
+             if (bits < 15) {
+-                hold += (unsigned long)(PUP(in)) << bits;
++                hold += (unsigned long)(*in++) << bits;
+                 bits += 8;
+-                hold += (unsigned long)(PUP(in)) << bits;
++                hold += (unsigned long)(*in++) << bits;
+                 bits += 8;
+             }
+             here = dcode[hold & dmask];
+@@ -165,10 +146,10 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+                 dist = (unsigned)(here.val);
+                 op &= 15;                       /* number of extra bits */
+                 if (bits < op) {
+-                    hold += (unsigned long)(PUP(in)) << bits;
++                    hold += (unsigned long)(*in++) << bits;
+                     bits += 8;
+                     if (bits < op) {
+-                        hold += (unsigned long)(PUP(in)) << bits;
++                        hold += (unsigned long)(*in++) << bits;
+                         bits += 8;
+                     }
+                 }
+@@ -196,30 +177,30 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+ #ifdef INFLATE_ALLOW_INVALID_DISTANCE_TOOFAR_ARRR
+                         if (len <= op - whave) {
+                             do {
+-                                PUP(out) = 0;
++                                *out++ = 0;
+                             } while (--len);
+                             continue;
+                         }
+                         len -= op - whave;
+                         do {
+-                            PUP(out) = 0;
++                            *out++ = 0;
+                         } while (--op > whave);
+                         if (op == 0) {
+                             from = out - dist;
+                             do {
+-                                PUP(out) = PUP(from);
++                                *out++ = *from++;
+                             } while (--len);
+                             continue;
+                         }
+ #endif
+                     }
+-                    from = window - OFF;
++                    from = window;
+                     if (wnext == 0) {           /* very common case */
+                         from += wsize - op;
+                         if (op < len) {         /* some from window */
+                             len -= op;
+                             do {
+-                                PUP(out) = PUP(from);
++                                *out++ = *from++;
+                             } while (--op);
+                             from = out - dist;  /* rest from output */
+                         }
+@@ -230,14 +211,14 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+                         if (op < len) {         /* some from end of window */
+                             len -= op;
+                             do {
+-                                PUP(out) = PUP(from);
++                                *out++ = *from++;
+                             } while (--op);
+-                            from = window - OFF;
++                            from = window;
+                             if (wnext < len) {  /* some from start of window */
+                                 op = wnext;
+                                 len -= op;
+                                 do {
+-                                    PUP(out) = PUP(from);
++                                    *out++ = *from++;
+                                 } while (--op);
+                                 from = out - dist;      /* rest from output */
+                             }
+@@ -248,35 +229,35 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+                         if (op < len) {         /* some from window */
+                             len -= op;
+                             do {
+-                                PUP(out) = PUP(from);
++                                *out++ = *from++;
+                             } while (--op);
+                             from = out - dist;  /* rest from output */
+                         }
+                     }
+                     while (len > 2) {
+-                        PUP(out) = PUP(from);
+-                        PUP(out) = PUP(from);
+-                        PUP(out) = PUP(from);
++                        *out++ = *from++;
++                        *out++ = *from++;
++                        *out++ = *from++;
+                         len -= 3;
+                     }
+                     if (len) {
+-                        PUP(out) = PUP(from);
++                        *out++ = *from++;
+                         if (len > 1)
+-                            PUP(out) = PUP(from);
++                            *out++ = *from++;
+                     }
+                 }
+                 else {
+                     from = out - dist;          /* copy direct from output */
+                     do {                        /* minimum length is three */
+-                        PUP(out) = PUP(from);
+-                        PUP(out) = PUP(from);
+-                        PUP(out) = PUP(from);
++                        *out++ = *from++;
++                        *out++ = *from++;
++                        *out++ = *from++;
+                         len -= 3;
+                     } while (len > 2);
+                     if (len) {
+-                        PUP(out) = PUP(from);
++                        *out++ = *from++;
+                         if (len > 1)
+-                            PUP(out) = PUP(from);
++                            *out++ = *from++;
+                     }
+                 }
+             }
+@@ -313,8 +294,8 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */
+     hold &= (1U << bits) - 1;
+ 
+     /* update state and return */
+-    strm->next_in = in + OFF;
+-    strm->next_out = out + OFF;
++    strm->next_in = in;
++    strm->next_out = out;
+     strm->avail_in = (unsigned)(in < last ? 5 + (last - in) : 5 - (in - last));
+     strm->avail_out = (unsigned)(out < end ?
+                                  257 + (end - out) : 257 - (out - end));
--- gcc-6-6.4.0.orig/debian/patches/CVE-2016-9842.diff
+++ gcc-6-6.4.0/debian/patches/CVE-2016-9842.diff
@@ -0,0 +1,27 @@
+commit e54e1299404101a5a9d0cf5e45512b543967f958
+Author: Mark Adler <madler@alumni.caltech.edu>
+Date:   Sat Sep 5 17:45:55 2015 -0700
+
+    Avoid shifts of negative values inflateMark().
+    
+    The C standard says that bit shifts of negative integers is
+    undefined.  This casts to unsigned values to assure a known
+    result.
+
+Index: b/src/zlib/inflate.c
+===================================================================
+--- a/src/zlib/inflate.c
++++ b/src/zlib/inflate.c
+@@ -1504,9 +1504,10 @@ z_streamp strm;
+ {
+     struct inflate_state FAR *state;
+ 
+-    if (strm == Z_NULL || strm->state == Z_NULL) return -1L << 16;
++    if (strm == Z_NULL || strm->state == Z_NULL)
++        return (long)(((unsigned long)0 - 1) << 16);
+     state = (struct inflate_state FAR *)strm->state;
+-    return ((long)(state->back) << 16) +
++    return (long)(((unsigned long)((long)state->back)) << 16) +
+         (state->mode == COPY ? state->length :
+             (state->mode == MATCH ? state->was - state->length : 0));
+ }
--- gcc-6-6.4.0.orig/debian/patches/CVE-2016-9843.diff
+++ gcc-6-6.4.0/debian/patches/CVE-2016-9843.diff
@@ -0,0 +1,47 @@
+commit d1d577490c15a0c6862473d7576352a9f18ef811
+Author: Mark Adler <madler@alumni.caltech.edu>
+Date:   Wed Sep 28 20:20:25 2016 -0700
+
+    Avoid pre-decrement of pointer in big-endian CRC calculation.
+    
+    There was a small optimization for PowerPCs to pre-increment a
+    pointer when accessing a word, instead of post-incrementing. This
+    required prefacing the loop with a decrement of the pointer,
+    possibly pointing before the object passed. This is not compliant
+    with the C standard, for which decrementing a pointer before its
+    allocated memory is undefined. When tested on a modern PowerPC
+    with a modern compiler, the optimization no longer has any effect.
+    Due to all that, and per the recommendation of a security audit of
+    the zlib code by Trail of Bits and TrustInSoft, in support of the
+    Mozilla Foundation, this "optimization" was removed, in order to
+    avoid the possibility of undefined behavior.
+
+diff --git a/crc32.c b/crc32.c
+index 979a719..05733f4 100644
+--- a/src/zlib/crc32.c
++++ b/src/zlib/crc32.c
+@@ -278,7 +278,7 @@ local unsigned long crc32_little(crc, buf, len)
+ }
+ 
+ /* ========================================================================= */
+-#define DOBIG4 c ^= *++buf4; \
++#define DOBIG4 c ^= *buf4++; \
+         c = crc_table[4][c & 0xff] ^ crc_table[5][(c >> 8) & 0xff] ^ \
+             crc_table[6][(c >> 16) & 0xff] ^ crc_table[7][c >> 24]
+ #define DOBIG32 DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4
+@@ -300,7 +300,6 @@ local unsigned long crc32_big(crc, buf, len)
+     }
+ 
+     buf4 = (const z_crc_t FAR *)(const void FAR *)buf;
+-    buf4--;
+     while (len >= 32) {
+         DOBIG32;
+         len -= 32;
+@@ -309,7 +308,6 @@ local unsigned long crc32_big(crc, buf, len)
+         DOBIG4;
+         len -= 4;
+     }
+-    buf4++;
+     buf = (const unsigned char FAR *)buf4;
+ 
+     if (len) do {
--- gcc-6-6.4.0.orig/debian/patches/ada-749574.diff
+++ gcc-6-6.4.0/debian/patches/ada-749574.diff
@@ -0,0 +1,34 @@
+From: Ludovic Brenta <lbrenta@debian.org>
+Forwarded: no
+Bug-Debian: http://bugs.debian.org/749574
+Description: Constraint_Error, range check failed at gnatlink.adb:2195, when called from gnatmake with -D option
+ The procedure gnatlink assumes that the Linker_Options.Table contains access
+ values to strings whose 'First index is always 1.  This assumption is wrong
+ for the string returned by function Base_Name.
+.
+ Instead of fixing the assumption in many places, this patch changes the
+ function Base_Name always to return a string with 'First=1.
+.
+ This looks like an upstream bug but strangely the reporter of this bug
+ says it does not happen on GCC built from upstream sources.  Further
+ investigation is required to determine whether or not to forward this
+ bug and patch upstream.
+
+Index: b/src/gcc/ada/gnatlink.adb
+===================================================================
+--- a/src/gcc/ada/gnatlink.adb
++++ b/src/gcc/ada/gnatlink.adb
+@@ -267,7 +267,12 @@ procedure Gnatlink is
+          Findex2 := File_Name'Last + 1;
+       end if;
+ 
+-      return File_Name (Findex1 .. Findex2 - 1);
++      declare
++         Result : String (1 .. Findex2 - Findex1);
++      begin
++         Result (1 .. Findex2 - Findex1) := File_Name (Findex1 .. Findex2 - 1);
++         return Result;
++      end;
+    end Base_Name;
+ 
+    -------------------------------
--- gcc-6-6.4.0.orig/debian/patches/ada-acats.diff
+++ gcc-6-6.4.0/debian/patches/ada-acats.diff
@@ -0,0 +1,206 @@
+# DP: - When running the ACATS, look for the gnat tools in their new
+# DP:   directory (build/gnattools), and for the shared libraries in
+# DP:   build/gcc/ada/rts, build/libgnatvsn and build/libgnatprj.
+
+Index: b/src/gcc/testsuite/ada/acats/run_acats
+===================================================================
+--- a/src/gcc/testsuite/ada/acats/run_acats
++++ b/src/gcc/testsuite/ada/acats/run_acats
+@@ -20,52 +20,30 @@ which () {
+     return 1
+ }
+ 
++echo '#!/bin/sh' > host_gnatchop
++echo exec /usr/bin/gnatchop --GCC=gcc-6 '$*' >> host_gnatchop
++
++chmod +x host_gnatchop
++
++echo '#!/bin/sh' > host_gnatmake
++echo echo '$PATH' '$*' >> host_gnatmake
++echo exec /usr/bin/gnatmake '$*' >> host_gnatmake
++
++chmod +x host_gnatmake
++
+ # Set up environment to use the Ada compiler from the object tree
+ 
+-host_gnatchop=`which gnatchop`
+-host_gnatmake=`which gnatmake`
+ ROOT=`${PWDCMD-pwd}`
+ BASE=`cd $ROOT/../../..; ${PWDCMD-pwd}`
+-
+ PATH=$BASE:$ROOT:$PATH
+-ADA_INCLUDE_PATH=$BASE/ada/rts
+-LD_LIBRARY_PATH=$ADA_INCLUDE_PATH:$BASE:$LD_LIBRARY_PATH
+-ADA_OBJECTS_PATH=$ADA_INCLUDE_PATH
+-
+-if [ ! -d $ADA_INCLUDE_PATH ]; then
+-   echo gnatlib missing, exiting.
+-   exit 1
+-fi
+-
+-if [ ! -f $BASE/gnatchop ]; then
+-   echo gnattools missing, exiting.
+-   exit 1
+-fi
+-
+-if [ ! -f $BASE/gnatmake ]; then
+-   echo gnattools missing, exiting.
+-   exit 1
+-fi
+-
+ GCC_DRIVER="$BASE/xgcc"
++TARGET=`${GCC_DRIVER} -v  2>&1 |grep '^Target:' | cut -d' ' -f2`
++GNATTOOLS=`cd $BASE/../gnattools; ${PWDCMD-pwd}`
++LIBGNATVSN=`cd $BASE/../${TARGET}/libgnatvsn; ${PWDCMD-pwd}`
++LIBGNATPRJ=`cd $BASE/../${TARGET}/libgnatprj; ${PWDCMD-pwd}`
+ GCC="$BASE/xgcc -B$BASE/"
+ export PATH ADA_INCLUDE_PATH ADA_OBJECTS_PATH GCC_DRIVER GCC LD_LIBRARY_PATH
+-
+-echo '#!/bin/sh' > host_gnatchop
+-echo PATH=`dirname $host_gnatchop`:'$PATH' >> host_gnatchop
+-echo unset ADA_INCLUDE_PATH ADA_OBJECTS_PATH GCC_EXEC_PREFIX >> host_gnatchop
+-echo export PATH >> host_gnatchop
+-echo exec gnatchop '"$@"' >> host_gnatchop
+-
+-chmod +x host_gnatchop
+-
+-echo '#!/bin/sh' > host_gnatmake
+-echo PATH=`dirname $host_gnatmake`:'$PATH' >> host_gnatmake
+-echo unset ADA_INCLUDE_PATH ADA_OBJECTS_PATH GCC_EXEC_PREFIX >> host_gnatmake
+-echo export PATH >> host_gnatmake
+-echo exec gnatmake '"$@"' >> host_gnatmake
+-
+-chmod +x host_gnatmake
++export GNATTOOLS LIBGNATVSN LIBGNATPRJ
+ 
+ # Limit the stack to 16MB for stack checking
+ ulimit -s 16384
+Index: b/src/gcc/testsuite/ada/acats/run_all.sh
+===================================================================
+--- a/src/gcc/testsuite/ada/acats/run_all.sh
++++ b/src/gcc/testsuite/ada/acats/run_all.sh
+@@ -1,4 +1,5 @@
+ #!/bin/sh
++
+ # Run ACATS with the GNU Ada compiler
+ 
+ # The following functions are to be customized if you run in cross
+@@ -12,6 +13,10 @@
+ gccflags="-O2"
+ gnatflags="-gnatws"
+ 
++RTS=`cd $GNATTOOLS/../gcc/ada/rts; ${PWDCMD-pwd}`
++LD_LIBRARY_PATH=$RTS:$LIBGNATVSN:$LIBGNATPRJ
++export LD_LIBRARY_PATH
++
+ target_run () {
+   eval $EXPECT -f $testdir/run_test.exp $*
+ }
+@@ -63,12 +68,15 @@ if [ "$dir" = "$testdir" ]; then
+ fi
+ 
+ target_gnatchop () {
+-  gnatchop --GCC="$GCC_DRIVER" $*
++  ADA_INCLUDE_PATH=$GNATTOOLS/../../src/gcc/ada $GNATTOOLS/gnatchop --GCC="$GCC_DRIVER" $*
+ }
+ 
+ target_gnatmake () {
+-  echo gnatmake --GCC=\"$GCC\" $gnatflags $gccflags $* -largs $EXTERNAL_OBJECTS --GCC=\"$GCC\"
+-  gnatmake --GCC="$GCC" $gnatflags $gccflags $* -largs $EXTERNAL_OBJECTS --GCC="$GCC"
++  EXTERNAL_OBJECTS="$EXTERNAL_OBJECTS $RTS/adaint.o $RTS/sysdep.o $RTS/init.o $RTS/raise-gcc.o"
++  $GNATTOOLS/gnatmake -I- -I$RTS -I. \
++      --GCC="$GCC" --GNATBIND="$GNATTOOLS/gnatbind" \
++      --GNATLINK="$GNATTOOLS/gnatlink" $gnatflags $gccflags $* \
++      -bargs -static -largs $EXTERNAL_OBJECTS --GCC="$GCC -I- -I$RTS -I."
+ }
+ 
+ target_gcc () {
+@@ -101,8 +109,8 @@ display target gcc is $GCC
+ display `$GCC -v 2>&1`
+ display host=`gcc -dumpmachine`
+ display target=$target
+-display `type gnatmake`
+-gnatls -v >> $dir/acats.log
++display `type $GNATTOOLS/gnatmake`
++$GNATTOOLS/gnatls -I- -I$RTS -v >> $dir/acats.log
+ display ""
+ 
+ if [ -n "$GCC_RUNTEST_PARALLELIZE_DIR" ]; then
+@@ -129,7 +137,7 @@ cp $testdir/support/*.ada $testdir/suppo
+ # Find out the size in bit of an address on the target
+ target_gnatmake $testdir/support/impbit.adb >> $dir/acats.log 2>&1
+ target_run $dir/support/impbit > $dir/support/impbit.out 2>&1
+-target_bit=`cat $dir/support/impbit.out`
++target_bit=`cat $dir/support/impbit.out | sed -e 's/ //g' -e 's/\r//g'`
+ echo target_bit="$target_bit" >> $dir/acats.log
+ 
+ # Find out a suitable asm statement
+Index: b/src/gcc/testsuite/lib/gnat.exp
+===================================================================
+--- a/src/gcc/testsuite/lib/gnat.exp
++++ b/src/gcc/testsuite/lib/gnat.exp
+@@ -88,18 +88,25 @@ proc gnat_init { args } {
+     global GNAT_UNDER_TEST
+     global TOOL_EXECUTABLE
+     global gnat_target_current
++    global ld_library_path
+ 
+     set gnat_target_current ""
+ 
+     if { $gnat_initialized == 1 } { return }
+ 
+-    if ![info exists GNAT_UNDER_TEST] then {
+-	if [info exists TOOL_EXECUTABLE] {
+-	    set GNAT_UNDER_TEST "$TOOL_EXECUTABLE"
+-	} else {
+-	    set GNAT_UNDER_TEST "[local_find_gnatmake]"
+-	}
+-    }
++    set target [target_info name]
++    set GNAT_UNDER_TEST "$rootme/../gnattools/gnatmake -I$rootme/ada/rts --GCC=$rootme/xgcc --GNATBIND=$rootme/../gnattools/gnatbind --GNATLINK=$rootme/../gnattools/gnatlink -cargs -B$rootme -largs --GCC=$rootme/xgcc -B$rootme -margs"
++    append ld_library_path ":$rootme/ada/rts"
++    append ld_library_path ":$rootme/../$target/libgnatvsn"
++    append ld_library_path ":$rootme/../$target/libgnatprj"
++    set_ld_library_path_env_vars
++
++    # gnatlink looks for system.ads itself and has no --RTS option, so
++    # specify via environment
++    verbose -log "ADA_INCLUDE_PATH=$rootme/ada/rts"
++    verbose -log "ADA_OBJECTS_PATH=$rootme/ada/rts"
++    setenv ADA_INCLUDE_PATH "$rootme/ada/rts"
++    setenv ADA_OBJECTS_PATH "$rootme/ada/rts"
+ 
+     if ![info exists tmpdir] then {
+ 	set tmpdir /tmp
+@@ -121,31 +128,6 @@ proc gnat_target_compile { source dest t
+ 	return [gcc_target_compile $source $dest $type $options]
+     }
+ 
+-    # If we detect a change of target, we need to recompute both
+-    # GNAT_UNDER_TEST and the appropriate RTS.
+-    if { $gnat_target_current!="[current_target_name]" } {
+-	set gnat_target_current "[current_target_name]"
+-	if [info exists TOOL_OPTIONS] {
+-	    set rtsdir "[get_multilibs ${TOOL_OPTIONS}]/libada"
+-	} else {
+-	    set rtsdir "[get_multilibs]/libada"
+-	}
+-	if [info exists TOOL_EXECUTABLE] {
+-	    set GNAT_UNDER_TEST "$TOOL_EXECUTABLE"
+-	} else {
+-	    set GNAT_UNDER_TEST "[local_find_gnatmake]"
+-	}
+-        set GNAT_UNDER_TEST "$GNAT_UNDER_TEST --RTS=$rtsdir"
+-
+-	# gnatlink looks for system.ads itself and has no --RTS option, so
+-	# specify via environment
+-	setenv ADA_INCLUDE_PATH "$rtsdir/adainclude"
+-	setenv ADA_OBJECTS_PATH "$rtsdir/adainclude"
+-	# Always log so compilations can be repeated manually.
+-	verbose -log "ADA_INCLUDE_PATH=$rtsdir/adainclude"
+-	verbose -log "ADA_OBJECTS_PATH=$rtsdir/adainclude"
+-    }
+-
+     lappend options "compiler=$GNAT_UNDER_TEST -q -f"
+     lappend options "timeout=[timeout_value]"
+ 
--- gcc-6-6.4.0.orig/debian/patches/ada-arm.diff
+++ gcc-6-6.4.0/debian/patches/ada-arm.diff
@@ -0,0 +1,18 @@
+DP: Improve support for ZCX on arm.
+
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -1992,7 +1992,10 @@ ifeq ($(strip $(filter-out arm% linux-gn
+     LIBGNAT_TARGET_PAIRS += \
+     system.ads<system-linux-armeb.ads
+   else
+-    EH_MECHANISM=-arm
++    # Special case; the GCC exception mechanism is supported under
++    # another name and with different files than for other
++    # target_cpus.
++    override EH_MECHANISM=-arm
+     LIBGNAT_TARGET_PAIRS += \
+     system.ads<system-linux-armel.ads \
+     a-exexpr.adb<a-exexpr-gcc.adb \
--- gcc-6-6.4.0.orig/debian/patches/ada-default-project-path.diff
+++ gcc-6-6.4.0/debian/patches/ada-default-project-path.diff
@@ -0,0 +1,134 @@
+# DP: - Change the default search path for project files to the one specified
+# DP:   by the Debian Policy for Ada: /usr/share/ada/adainclude.
+
+Index: b/src/gcc/ada/Make-generated.in
+===================================================================
+--- a/src/gcc/ada/Make-generated.in
++++ b/src/gcc/ada/Make-generated.in
+@@ -76,6 +76,7 @@ $(ADA_GEN_SUBDIR)/stamp-sdefault : $(src
+ 	$(ECHO) "   S2 : constant String := \"$(ADA_RTL_OBJ_DIR)/\";" >>tmp-sdefault.adb
+ 	$(ECHO) "   S3 : constant String := \"$(target_noncanonical)/\";" >>tmp-sdefault.adb
+ 	$(ECHO) "   S4 : constant String := \"$(libsubdir)/\";" >>tmp-sdefault.adb
++	$(ECHO) "   S5 : constant String := \"/usr/share/ada/adainclude/\";" >>tmp-sdefault.adb
+ 	$(ECHO) "   function Include_Dir_Default_Name return String_Ptr is" >>tmp-sdefault.adb
+ 	$(ECHO) "   begin" >>tmp-sdefault.adb
+ 	$(ECHO) "      return Relocate_Path (S0, S1);" >>tmp-sdefault.adb
+@@ -92,6 +93,10 @@ $(ADA_GEN_SUBDIR)/stamp-sdefault : $(src
+ 	$(ECHO) "   begin" >>tmp-sdefault.adb
+ 	$(ECHO) "      return Relocate_Path (S0, S4);" >>tmp-sdefault.adb
+ 	$(ECHO) "   end Search_Dir_Prefix;" >>tmp-sdefault.adb
++	$(ECHO) "   function Project_Dir_Prefix return String_Ptr is" >>tmp-sdefault.adb
++	$(ECHO) "   begin" >>tmp-sdefault.adb
++	$(ECHO) "      return Relocate_Path (S0, S5);" >>tmp-sdefault.adb
++	$(ECHO) "   end Project_Dir_Prefix;" >>tmp-sdefault.adb
+ 	$(ECHO) "end Sdefault;" >> tmp-sdefault.adb
+ 	$(MOVE_IF_CHANGE) tmp-sdefault.adb $(ADA_GEN_SUBDIR)/sdefault.adb
+ 	touch $(ADA_GEN_SUBDIR)/stamp-sdefault
+Index: b/src/gcc/ada/prj-env.adb
+===================================================================
+--- a/src/gcc/ada/prj-env.adb
++++ b/src/gcc/ada/prj-env.adb
+@@ -1877,6 +1877,7 @@ package body Prj.Env is
+       Target_Name  : String;
+       Runtime_Name : String := "")
+    is
++      pragma Unreferenced (Target_Name);
+       Add_Default_Dir : Boolean := Target_Name /= "-";
+       First           : Positive;
+       Last            : Positive;
+@@ -2075,82 +2076,9 @@ package body Prj.Env is
+ 
+       --  Set the initial value of Current_Project_Path
+ 
+-      if Add_Default_Dir then
+-         if Sdefault.Search_Dir_Prefix = null then
+-
+-            --  gprbuild case
+-
+-            Prefix := new String'(Executable_Prefix_Path);
+-
+-         else
+-            Prefix := new String'(Sdefault.Search_Dir_Prefix.all
+-                                  & ".." & Dir_Separator
+-                                  & ".." & Dir_Separator
+-                                  & ".." & Dir_Separator
+-                                  & ".." & Dir_Separator);
+-         end if;
+-
+-         if Prefix.all /= "" then
+-            if Target_Name /= "" then
+-
+-               if Runtime_Name /= "" then
+-                  if Base_Name (Runtime_Name) = Runtime_Name then
+-
+-                     --  $prefix/$target/$runtime/lib/gnat
+-                     Add_Target;
+-                     Add_Str_To_Name_Buffer
+-                       (Runtime_Name & Directory_Separator &
+-                          "lib" & Directory_Separator & "gnat");
+-
+-                     --  $prefix/$target/$runtime/share/gpr
+-                     Add_Target;
+-                     Add_Str_To_Name_Buffer
+-                       (Runtime_Name & Directory_Separator &
+-                          "share" & Directory_Separator & "gpr");
+-
+-                  else
+-                     Runtime :=
+-                       new String'(Normalize_Pathname (Runtime_Name));
+-
+-                     --  $runtime_dir/lib/gnat
+-                     Add_Str_To_Name_Buffer
+-                       (Path_Separator & Runtime.all & Directory_Separator &
+-                        "lib" & Directory_Separator & "gnat");
+-
+-                     --  $runtime_dir/share/gpr
+-                     Add_Str_To_Name_Buffer
+-                       (Path_Separator & Runtime.all & Directory_Separator &
+-                        "share" & Directory_Separator & "gpr");
+-                  end if;
+-               end if;
+-
+-               --  $prefix/$target/lib/gnat
+-
+-               Add_Target;
+-               Add_Str_To_Name_Buffer
+-                 ("lib" & Directory_Separator & "gnat");
+-
+-               --  $prefix/$target/share/gpr
+-
+-               Add_Target;
+-               Add_Str_To_Name_Buffer
+-                 ("share" & Directory_Separator & "gpr");
+-            end if;
+-
+-            --  $prefix/share/gpr
+-
+-            Add_Str_To_Name_Buffer
+-              (Path_Separator & Prefix.all & "share"
+-               & Directory_Separator & "gpr");
+-
+-            --  $prefix/lib/gnat
+-
+-            Add_Str_To_Name_Buffer
+-              (Path_Separator & Prefix.all & "lib"
+-               & Directory_Separator & "gnat");
+-         end if;
+-
+-         Free (Prefix);
++      if Add_Default_Dir and Sdefault.Project_Dir_Prefix /= null then
++         Add_Str_To_Name_Buffer (Path_Separator
++                                 & Sdefault.Project_Dir_Prefix.all);
+       end if;
+ 
+       Self.Path := new String'(Name_Buffer (1 .. Name_Len));
+Index: b/src/gcc/ada/sdefault.ads
+===================================================================
+--- a/src/gcc/ada/sdefault.ads
++++ b/src/gcc/ada/sdefault.ads
+@@ -35,4 +35,5 @@ package Sdefault is
+    function Object_Dir_Default_Name  return String_Ptr;
+    function Target_Name              return String_Ptr;
+    function Search_Dir_Prefix        return String_Ptr;
++   function Project_Dir_Prefix       return String_Ptr;
+ end Sdefault;
--- gcc-6-6.4.0.orig/debian/patches/ada-driver-check.diff
+++ gcc-6-6.4.0/debian/patches/ada-driver-check.diff
@@ -0,0 +1,29 @@
+# DP: Simplify Ada driver check (we always build using the required
+# DP: Ada version. Needed for warnings on alpha.
+
+Index: b/src/config/acx.m4
+===================================================================
+--- a/src/config/acx.m4
++++ b/src/config/acx.m4
+@@ -381,7 +381,7 @@ acx_cv_cc_gcc_supports_ada=no
+ # Other compilers, like HP Tru64 UNIX cc, exit successfully when
+ # given a .adb file, but produce no object file.  So we must check
+ # if an object file was really produced to guard against this.
+-errors=`(${CC} $1[]m4_ifval([$1], [ ])-c conftest.adb) 2>&1 || echo failure`
++errors=`(${CC} $1[]m4_ifval([$1], [ ])-c conftest.adb) 2>/dev/null || echo failure`
+ if test x"$errors" = x && test -f conftest.$ac_objext; then
+   acx_cv_cc_gcc_supports_ada=yes
+ fi
+Index: b/src/configure
+===================================================================
+--- a/src/configure
++++ b/src/configure
+@@ -5358,7 +5358,7 @@ acx_cv_cc_gcc_supports_ada=no
+ # Other compilers, like HP Tru64 UNIX cc, exit successfully when
+ # given a .adb file, but produce no object file.  So we must check
+ # if an object file was really produced to guard against this.
+-errors=`(${CC} -c conftest.adb) 2>&1 || echo failure`
++errors=`(${CC} -c conftest.adb) 2>/dev/null || echo failure`
+ if test x"$errors" = x && test -f conftest.$ac_objext; then
+   acx_cv_cc_gcc_supports_ada=yes
+ fi
--- gcc-6-6.4.0.orig/debian/patches/ada-gcc-name.diff
+++ gcc-6-6.4.0/debian/patches/ada-gcc-name.diff
@@ -0,0 +1,128 @@
+# DP: use gcc-7 instead of gcc as the command name.
+
+--- a/src/gcc/ada/gnatlink.adb
++++ b/src/gcc/ada/gnatlink.adb
+@@ -136,7 +136,8 @@
+    --  This table collects the arguments to be passed to compile the binder
+    --  generated file.
+ 
+-   Gcc : String_Access := Program_Name ("gcc", "gnatlink");
++   Gcc : String_Access
++     := Program_Name ("gcc-" & Gnatvsn.Library_Version, "gnatlink");
+ 
+    Read_Mode : constant String := "r" & ASCII.NUL;
+ 
+@@ -1412,7 +1413,8 @@
+       end if;
+ 
+       Write_Line ("  --GCC=comp Use comp as the compiler");
+-      Write_Line ("  --LINK=nam Use 'nam' for the linking rather than 'gcc'");
++      Write_Line ("  --LINK=nam Use 'nam' for the linking rather than 'gcc-"
++		 & Gnatvsn.Library_Version & "'");
+       Write_Eol;
+       Write_Line ("  [non-Ada-objects]  list of non Ada object files");
+       Write_Line ("  [linker-options]   other options for the linker");
+--- a/src/gcc/ada/make.adb
++++ b/src/gcc/ada/make.adb
+@@ -667,9 +667,12 @@
+    -- Compiler, Binder & Linker Data and Subprograms --
+    ----------------------------------------------------
+ 
+-   Gcc      : String_Access := Program_Name ("gcc", "gnatmake");
+-   Gnatbind : String_Access := Program_Name ("gnatbind", "gnatmake");
+-   Gnatlink : String_Access := Program_Name ("gnatlink", "gnatmake");
++   Gcc      : String_Access := Program_Name
++     ("gcc-" & Gnatvsn.Library_Version, "gnatmake");
++   Gnatbind : String_Access := Program_Name
++     ("gnatbind-" & Gnatvsn.Library_Version, "gnatmake");
++   Gnatlink : String_Access := Program_Name
++     ("gnatlink-" & Gnatvsn.Library_Version, "gnatmake");
+    --  Default compiler, binder, linker programs
+ 
+    Globalizer : constant String := "codepeer_globalizer";
+--- a/src/gcc/ada/gnatchop.adb
++++ b/src/gcc/ada/gnatchop.adb
+@@ -36,6 +36,7 @@
+ with GNAT.Heap_Sort_G;
+ with GNAT.Table;
+ 
++with Gnatvsn;
+ with Switch;                     use Switch;
+ with Types;
+ 
+@@ -44,7 +45,7 @@
+    Config_File_Name : constant String_Access := new String'("gnat.adc");
+    --  The name of the file holding the GNAT configuration pragmas
+ 
+-   Gcc : String_Access := new String'("gcc");
++   Gcc : String_Access := new String'("gcc-" & Gnatvsn.Library_Version);
+    --  May be modified by switch --GCC=
+ 
+    Gcc_Set : Boolean := False;
+--- a/src/gcc/ada/mdll-utl.adb
++++ b/src/gcc/ada/mdll-utl.adb
+@@ -29,6 +29,7 @@
+ with Ada.Exceptions;
+ 
+ with GNAT.Directory_Operations;
++with Gnatvsn;
+ with Osint;
+ 
+ package body MDLL.Utl is
+@@ -39,7 +40,7 @@
+    Dlltool_Name  : constant String := "dlltool";
+    Dlltool_Exec  : OS_Lib.String_Access;
+ 
+-   Gcc_Name      : constant String := "gcc";
++   Gcc_Name      : constant String := "gcc-" & Gnatvsn.Library_Version;
+    Gcc_Exec      : OS_Lib.String_Access;
+ 
+    Gnatbind_Name : constant String := "gnatbind";
+@@ -212,7 +213,7 @@
+          end;
+       end if;
+ 
+-      Print_Command ("gcc", Arguments (1 .. A));
++      Print_Command (Gcc_Name, Arguments (1 .. A));
+ 
+       OS_Lib.Spawn (Gcc_Exec.all, Arguments (1 .. A), Success);
+ 
+--- a/src/gcc/ada/mlib-utl.adb
++++ b/src/gcc/ada/mlib-utl.adb
+@@ -23,6 +23,7 @@
+ --                                                                          --
+ ------------------------------------------------------------------------------
+ 
++with Gnatvsn;
+ with MLib.Fil; use MLib.Fil;
+ with MLib.Tgt; use MLib.Tgt;
+ with Opt;
+@@ -446,7 +447,8 @@
+       if Driver_Name = No_Name then
+          if Gcc_Exec = null then
+             if Gcc_Name = null then
+-               Gcc_Name := Osint.Program_Name ("gcc", "gnatmake");
++               Gcc_Name := Osint.Program_Name
++		 ("gcc-" & Gnatvsn.Library_Version, "gnatmake");
+             end if;
+ 
+             Gcc_Exec := Locate_Exec_On_Path (Gcc_Name.all);
+--- a/src/gcc/ada/prj-makr.adb
++++ b/src/gcc/ada/prj-makr.adb
+@@ -24,6 +24,7 @@
+ ------------------------------------------------------------------------------
+ 
+ with Csets;
++with Gnatvsn;
+ with Makeutl;  use Makeutl;
+ with Opt;
+ with Output;
+@@ -115,7 +116,7 @@
+ 
+    procedure Dup2 (Old_Fd, New_Fd : File_Descriptor);
+ 
+-   Gcc      : constant String := "gcc";
++   Gcc      : constant String := "gcc-" & Gnatvsn.Library_Version;
+    Gcc_Path : String_Access := null;
+ 
+    Non_Empty_Node : constant Project_Node_Id := 1;
--- gcc-6-6.4.0.orig/debian/patches/ada-gnattools-cross.diff
+++ gcc-6-6.4.0/debian/patches/ada-gnattools-cross.diff
@@ -0,0 +1,761 @@
+# DP: - When building the native gnat, link the gnat tools against
+# DP:   the build tree (build/$(host_alias)/{libgnatvsn,libgnatprj}.)
+# DP: - When building a cross gnat, link against the libgnatvsn-6-dev
+# DP:   and libgnatprj-6-dev packages.
+# DP:   This link will be done by /usr/bin/$(host_alias)-gnat*, thus
+# DP:   the native gnat with the same major version will be required.
+
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -102,7 +102,7 @@ INSTALL_DATA_DATE = cp -p
+ MAKEINFO = makeinfo
+ TEXI2DVI = texi2dvi
+ TEXI2PDF = texi2pdf
+-GNATBIND_FLAGS = -static -x
++GNATBIND_FLAGS = -shared -x
+ ADA_CFLAGS =
+ ADAFLAGS = -W -Wall -gnatpg -gnata
+ FORCE_DEBUG_ADAFLAGS = -g
+@@ -141,6 +141,8 @@ target=@target@
+ target_cpu=@target_cpu@
+ target_vendor=@target_vendor@
+ target_os=@target_os@
++host_alias=@host_alias@
++host=@host@
+ host_cpu=@host_cpu@
+ host_vendor=@host_vendor@
+ host_os=@host_os@
+@@ -235,7 +237,7 @@ ALL_CPPFLAGS = $(CPPFLAGS)
+ ALL_COMPILERFLAGS = $(ALL_CFLAGS)
+ 
+ # This is where we get libiberty.a from.
+-LIBIBERTY = ../../libiberty/libiberty.a
++LIBIBERTY = ../../libiberty/pic/libiberty.a
+ 
+ # We need to link against libbacktrace because diagnostic.c in
+ # libcommon.a uses it.
+@@ -247,9 +249,15 @@ LIBS = $(LIBINTL) $(LIBICONV) $(LIBBACKT
+ LIBDEPS = $(LIBINTL_DEP) $(LIBICONV_DEP) $(LIBBACKTRACE) $(LIBIBERTY)
+ # Default is no TGT_LIB; one might be passed down or something
+ TGT_LIB =
+-TOOLS_LIBS = ../link.o ../targext.o ../../ggc-none.o ../../libcommon-target.a \
+-  ../../libcommon.a ../../../libcpp/libcpp.a $(LIBGNAT) $(LIBINTL) $(LIBICONV) \
+-  ../$(LIBBACKTRACE) ../$(LIBIBERTY) $(SYSLIBS) $(TGT_LIB)
++
++TOOLS_LIBS = ../link.o ../targext.o ../../ggc-none.o ../../version.o ../../../libiberty/pic/lrealpath.o \
++      ../../libbackend.a ../../libcommon-target.a ../../libcommon.a ../../../libcpp/libcpp.a ../$(LIBBACKTRACE) ../$(LIBIBERTY) -lstdc++
++
++ifeq ($(host),$(target))
++  TOOLS_LIBS +=  -L../$(RTSDIR) -lgnat-6 \
++		-L../../../$(target_alias)/libgnatvsn -lgnatvsn \
++                -L../../../$(target_alias)/libgnatprj -lgnatprj
++endif
+ 
+ # Add -no-pie to TOOLS_LIBS since some of them are compiled with -fno-PIE.
+ TOOLS_LIBS += @NO_PIE_FLAG@
+@@ -261,7 +269,12 @@ TOOLS_LIBS += @NO_PIE_FLAG@
+ INCLUDES = -iquote . -iquote .. -iquote $(srcdir)/ada -iquote $(srcdir) \
+ 	   -I $(ftop_srcdir)/include $(GMPINC)
+ 
+-ADA_INCLUDES = -I- -I. -I$(srcdir)/ada
++ifeq ($(host),$(target))
++  ADA_INCLUDES = -I../rts \
++		-I../../../$(target_alias)/libgnatvsn \
++		-I../../../$(target_alias)/libgnatprj
++endif
++ADA_INCLUDES += -I- -I. -I$(srcdir)/ada
+ 
+ # Likewise, but valid for subdirectories of the current dir.
+ # FIXME: for VxWorks, we cannot add $(fsrcdir) because the regs.h file in
+@@ -309,30 +322,50 @@ Makefile: ../config.status $(srcdir)/ada
+ # defined in this file into the environment.
+ .NOEXPORT:
+ 
+-# Lists of files for various purposes.
+ 
+-GNATLINK_OBJS = gnatlink.o \
+- a-except.o ali.o alloc.o butil.o casing.o csets.o debug.o fmap.o fname.o \
+- gnatvsn.o hostparm.o indepsw.o interfac.o i-c.o i-cstrin.o namet.o opt.o \
+- osint.o output.o rident.o s-exctab.o s-secsta.o s-stalib.o s-stoele.o \
+- sdefault.o snames.o stylesw.o switch.o system.o table.o targparm.o tree_io.o \
+- types.o validsw.o widechar.o
+-
+-GNATMAKE_OBJS = a-except.o ali.o ali-util.o aspects.o s-casuti.o alloc.o \
+- atree.o binderr.o butil.o casing.o csets.o debug.o elists.o einfo.o errout.o \
+- erroutc.o errutil.o err_vars.o fmap.o fname.o fname-uf.o fname-sf.o \
+- gnatmake.o gnatvsn.o hostparm.o interfac.o i-c.o i-cstrin.o krunch.o lib.o \
+- make.o makeusg.o makeutl.o mlib.o mlib-fil.o mlib-prj.o mlib-tgt.o \
+- mlib-tgt-specific.o mlib-utl.o namet.o nlists.o opt.o osint.o osint-m.o \
+- output.o prj.o prj-attr.o prj-attr-pm.o prj-com.o prj-dect.o prj-env.o \
+- prj-conf.o prj-pp.o prj-err.o prj-ext.o prj-nmsc.o prj-pars.o prj-part.o \
+- prj-proc.o prj-strt.o prj-tree.o prj-util.o restrict.o rident.o s-exctab.o \
+- s-secsta.o s-stalib.o s-stoele.o scans.o scng.o sdefault.o sfn_scan.o \
+- s-purexc.o s-htable.o scil_ll.o sem_aux.o sinfo.o sinput.o sinput-c.o \
+- sinput-p.o snames.o stand.o stringt.o styleg.o stylesw.o system.o validsw.o \
+- switch.o switch-m.o table.o targparm.o tempdir.o tree_io.o types.o uintp.o \
+- uname.o urealp.o usage.o widechar.o \
+- $(EXTRA_GNATMAKE_OBJS)
++# Since we don't have gnatmake, we must specify the full list of
++# object files necessary to build gnatmake and gnatlink.
++GNATLINK_OBJS = \
++gnatlink.o \
++indepsw.o \
++validsw.o
++
++GNATMAKE_OBJS = \
++aspects.o \
++errout.o \
++fname-sf.o \
++gnatmake.o \
++make.o \
++makeusg.o \
++mlib-prj.o \
++osint-m.o \
++restrict.o \
++sem_aux.o \
++usage.o \
++validsw.o \
++$(EXTRA_GNATMAKE_OBJS)
++
++EXTRA_TOOLS_OBJS = \
++bcheck.o \
++binde.o \
++bindgen.o \
++bindusg.o \
++clean.o \
++gprep.o \
++makegpr.o \
++osint-b.o \
++osint-l.o \
++prep.o \
++prj-makr.o \
++prj-pp.o \
++switch-b.o \
++vms_cmds.o \
++vms_conv.o \
++vms_data.o \
++xr_tabls.o \
++xref_lib.o
++
++OBJECTS = $(GNATLINK_OBJS) $(GNATMAKE_OBJS) $(EXTRA_TOOLS_OBJS)
+ 
+ # Make arch match the current multilib so that the RTS selection code
+ # picks up the right files. For a given target this must be coherent
+@@ -1640,6 +1673,11 @@ ifeq ($(strip $(filter-out s390% linux%,
+   LIBRARY_VERSION := $(LIB_VERSION)
+ endif
+ 
++ifeq ($(strip $(filter-out hppa% unknown linux gnu,$(targ))),)
++  GNATLIB_SHARED = gnatlib-shared-dual
++  LIBRARY_VERSION := $(LIB_VERSION)
++endif
++
+ # HP/PA HP-UX 10
+ ifeq ($(strip $(filter-out hppa% hp hpux10%,$(target_cpu) $(target_vendor) $(target_os))),)
+   LIBGNAT_TARGET_PAIRS = \
+@@ -2541,153 +2579,6 @@ ADA_EXCLUDE_FILES=$(filter-out \
+   $(patsubst %$(objext),%.adb,$(GNATRTL_OBJS)), \
+   $(ADA_EXCLUDE_SRCS))
+ 
+-LIBGNAT=../$(RTSDIR)/libgnat.a
+-
+-TOOLS_FLAGS_TO_PASS=		\
+-	"CC=$(CC)" 		\
+-	"CFLAGS=$(CFLAGS)"	\
+-	"LDFLAGS=$(LDFLAGS)"	\
+-	"ADAFLAGS=$(ADAFLAGS)"	\
+-	"INCLUDES=$(INCLUDES_FOR_SUBDIR)"\
+-	"ADA_INCLUDES=$(ADA_INCLUDES) $(ADA_INCLUDES_FOR_SUBDIR)"\
+-	"libsubdir=$(libsubdir)"	\
+-	"exeext=$(exeext)"	\
+-	"fsrcdir=$(fsrcdir)"	\
+-	"srcdir=$(fsrcdir)"	\
+-	"TOOLS_LIBS=$(TOOLS_LIBS) $(TGT_LIB)"	\
+-	"GNATMAKE=$(GNATMAKE)"	\
+-	"GNATLINK=$(GNATLINK)"	\
+-	"GNATBIND=$(GNATBIND)"
+-
+-GCC_LINK=$(CXX) $(GCC_LINK_FLAGS) $(ADA_INCLUDES) $(LDFLAGS)
+-
+-# Build directory for the tools. Let's copy the target-dependent
+-# sources using the same mechanism as for gnatlib. The other sources are
+-# accessed using the vpath directive below
+-
+-../stamp-tools:
+-	-$(RM) tools/*
+-	-$(RMDIR) tools
+-	-$(MKDIR) tools
+-	-(cd tools; $(LN_S) ../sdefault.adb ../snames.ads ../snames.adb .)
+-	-$(foreach PAIR,$(TOOLS_TARGET_PAIRS), \
+-	          $(RM) tools/$(word 1,$(subst <, ,$(PAIR)));\
+-	          $(LN_S) $(fsrcpfx)ada/$(word 2,$(subst <, ,$(PAIR))) \
+-	                tools/$(word 1,$(subst <, ,$(PAIR)));)
+-	touch ../stamp-tools
+-
+-# when compiling the tools, the runtime has to be first on the path so that
+-# it hides the runtime files lying with the rest of the sources
+-ifeq ($(TOOLSCASE),native)
+-  vpath %.ads ../$(RTSDIR) ../
+-  vpath %.adb ../$(RTSDIR) ../
+-  vpath %.c   ../$(RTSDIR) ../
+-  vpath %.h   ../$(RTSDIR) ../
+-endif
+-
+-# in the cross tools case, everything is compiled with the native
+-# gnatmake/link. Therefore only -I needs to be modified in ADA_INCLUDES
+-ifeq ($(TOOLSCASE),cross)
+-  vpath %.ads ../
+-  vpath %.adb ../
+-  vpath %.c   ../
+-  vpath %.h   ../
+-endif
+-
+-# gnatmake/link tools cannot always be built with gnatmake/link for bootstrap
+-# reasons: gnatmake should be built with a recent compiler, a recent compiler
+-# may not generate ALI files compatible with an old gnatmake so it is important
+-# to be able to build gnatmake without a version of gnatmake around. Once
+-# everything has been compiled once, gnatmake can be recompiled with itself
+-# (see target gnattools1-re)
+-gnattools1: ../stamp-tools ../stamp-gnatlib-$(RTSDIR)
+-	$(MAKE) -C tools -f ../Makefile $(TOOLS_FLAGS_TO_PASS) \
+-	  TOOLSCASE=native \
+-	  ../../gnatmake$(exeext) ../../gnatlink$(exeext)
+-
+-# gnatmake/link can be built with recent gnatmake/link if they are available.
+-# This is especially convenient for building cross tools or for rebuilding
+-# the tools when the original bootstrap has already be done.
+-gnattools1-re: ../stamp-tools
+-	$(MAKE) -C tools -f ../Makefile $(TOOLS_FLAGS_TO_PASS) \
+-	  TOOLSCASE=cross INCLUDES="" gnatmake-re gnatlink-re
+-
+-# these tools are built with gnatmake & are common to native and cross
+-gnattools2: ../stamp-tools
+-	$(MAKE) -C tools -f ../Makefile $(TOOLS_FLAGS_TO_PASS) \
+-	  TOOLSCASE=native common-tools $(EXTRA_GNATTOOLS)
+-
+-# those tools are only built for the cross version
+-gnattools4: ../stamp-tools
+-ifeq ($(ENABLE_VXADDR2LINE),true)
+-	$(MAKE) -C tools -f ../Makefile $(TOOLS_FLAGS_TO_PASS) \
+-	  TOOLSCASE=cross top_buildir=../../.. \
+-	  ../../vxaddr2line$(exeext)
+-endif
+-
+-common-tools: ../stamp-tools
+-	$(GNATMAKE) -j0 -c -b $(ADA_INCLUDES) \
+-	  --GNATBIND="$(GNATBIND)" --GCC="$(CC) $(ALL_ADAFLAGS)" \
+-	  gnatchop gnatcmd gnatkr gnatls gnatprep gnatxref gnatfind gnatname \
+-	  gnatclean -bargs $(ADA_INCLUDES) $(GNATBIND_FLAGS)
+-	$(GNATLINK) -v gnatcmd -o ../../gnat$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatchop -o ../../gnatchop$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatkr -o ../../gnatkr$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatls -o ../../gnatls$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatprep -o ../../gnatprep$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatxref -o ../../gnatxref$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatfind -o ../../gnatfind$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatname -o ../../gnatname$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-	$(GNATLINK) -v gnatclean -o ../../gnatclean$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+-
+-../../gnatdll$(exeext): ../stamp-tools
+-	$(GNATMAKE) -c $(ADA_INCLUDES) gnatdll --GCC="$(CC) $(ALL_ADAFLAGS)"
+-	$(GNATBIND) $(ADA_INCLUDES) $(GNATBIND_FLAGS) gnatdll
+-	$(GNATLINK) -v gnatdll -o $@ --GCC="$(GCC_LINK)" $(TOOLS_LIBS)
+-
+-../../vxaddr2line$(exeext): ../stamp-tools
+-	$(GNATMAKE) -c  $(ADA_INCLUDES) vxaddr2line --GCC="$(CC) $(ALL_ADAFLAGS)"
+-	$(GNATBIND) $(ADA_INCLUDES) $(GNATBIND_FLAGS) vxaddr2line
+-	$(GNATLINK) -v vxaddr2line -o $@ --GCC="$(GCC_LINK)" ../targext.o $(CLIB)
+-
+-gnatmake-re: ../stamp-tools
+-	$(GNATMAKE) -j0 $(ADA_INCLUDES) -u sdefault --GCC="$(CC) $(MOST_ADA_FLAGS)"
+-	$(GNATMAKE) -j0 -c $(ADA_INCLUDES) gnatmake --GCC="$(CC) $(ALL_ADAFLAGS)"
+-	$(GNATBIND) $(ADA_INCLUDES) $(GNATBIND_FLAGS) gnatmake
+-	$(GNATLINK) -v gnatmake -o ../../gnatmake$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
+-
+-# Note the use of the "mv" command in order to allow gnatlink to be linked with
+-# with the former version of gnatlink itself which cannot override itself.
+-# gnatlink-re cannot be run at the same time as gnatmake-re, hence the
+-# dependency
+-gnatlink-re: ../stamp-tools gnatmake-re
+-	$(GNATMAKE) -j0 -c $(ADA_INCLUDES) gnatlink --GCC="$(CC) $(ALL_ADAFLAGS)"
+-	$(GNATBIND) $(ADA_INCLUDES) $(GNATBIND_FLAGS) gnatlink
+-	$(GNATLINK) -v gnatlink -o ../../gnatlinknew$(exeext) \
+-		    --GCC="$(GCC_LINK)" $(TOOLS_LIBS)
+-	$(MV)  ../../gnatlinknew$(exeext)  ../../gnatlink$(exeext)
+-
+-# Needs to be built with CC=gcc
+-# Since the RTL should be built with the latest compiler, remove the
+-#  stamp target in the parent directory whenever gnat1 is rebuilt
+-
+-# Likewise for the tools
+-../../gnatmake$(exeext): $(P) b_gnatm.o $(GNATMAKE_OBJS)
+-	+$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) $(TOOLS_LIBS) $(TOOLS1_LIBS)
+-
+-../../gnatlink$(exeext): $(P) b_gnatl.o $(GNATLINK_OBJS)
+-	+$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) $(TOOLS_LIBS) $(TOOLS1_LIBS)
+-
+ ../stamp-gnatlib-$(RTSDIR):
+ 	@if [ ! -f stamp-gnatlib-$(RTSDIR) ] ; \
+ 	then \
+@@ -2726,14 +2617,10 @@ install-gnatlib: ../stamp-gnatlib-$(RTSD
+ #     Also install the .dSYM directories if they exist (these directories
+ #     contain the debug information for the shared libraries on darwin)
+ 	for file in gnat gnarl; do \
+-	   if [ -f $(RTSDIR)/lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext) ]; then \
+-	      $(INSTALL) $(RTSDIR)/lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext) \
++	   if [ -f $(RTSDIR)/lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext).1 ]; then \
++	      $(INSTALL) $(RTSDIR)/lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext).1 \
+ 			 $(DESTDIR)$(ADA_RTL_OBJ_DIR); \
+ 	   fi; \
+-	   if [ -f $(RTSDIR)/lib$${file}$(soext) ]; then \
+-	      $(LN_S) lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext) \
+-	      $(DESTDIR)$(ADA_RTL_OBJ_DIR)/lib$${file}$(soext); \
+-	   fi; \
+ 	   if [ -d $(RTSDIR)/lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext).dSYM ]; then \
+ 	      $(CP) -r $(RTSDIR)/lib$${file}$(hyphen)$(LIBRARY_VERSION)$(soext).dSYM \
+ 	        $(DESTDIR)$(ADA_RTL_OBJ_DIR); \
+@@ -2746,19 +2633,7 @@ install-gnatlib: ../stamp-gnatlib-$(RTSD
+ 	cd $(DESTDIR)$(ADA_INCLUDE_DIR); $(CHMOD) a-wx *.adb
+ 	cd $(DESTDIR)$(ADA_INCLUDE_DIR); $(CHMOD) a-wx *.ads
+ 
+-../stamp-gnatlib2-$(RTSDIR):
+-	$(RM) $(RTSDIR)/s-*.ali
+-	$(RM) $(RTSDIR)/s-*$(objext)
+-	$(RM) $(RTSDIR)/a-*.ali
+-	$(RM) $(RTSDIR)/a-*$(objext)
+-	$(RM) $(RTSDIR)/*.ali
+-	$(RM) $(RTSDIR)/*$(objext)
+-	$(RM) $(RTSDIR)/*$(arext)
+-	$(RM) $(RTSDIR)/*$(soext)
+-	touch ../stamp-gnatlib2-$(RTSDIR)
+-	$(RM) ../stamp-gnatlib-$(RTSDIR)
+-
+-../stamp-gnatlib1-$(RTSDIR): Makefile ../stamp-gnatlib2-$(RTSDIR)
++../stamp-gnatlib1-$(RTSDIR): Makefile
+ 	$(RMDIR) $(RTSDIR)
+ 	$(MKDIR) $(RTSDIR)
+ 	$(CHMOD) u+w $(RTSDIR)
+@@ -2823,7 +2698,7 @@ $(RTSDIR)/s-oscons.ads: ../stamp-gnatlib
+ 	    $(OSCONS_EXTRACT) ; \
+ 	    ../bldtools/oscons/xoscons s-oscons)
+ 
+-gnatlib: ../stamp-gnatlib1-$(RTSDIR) ../stamp-gnatlib2-$(RTSDIR) $(RTSDIR)/s-oscons.ads
++gnatlib: ../stamp-gnatlib1-$(RTSDIR) $(RTSDIR)/s-oscons.ads
+ 	test -f $(RTSDIR)/s-oscons.ads || exit 1
+ # C files
+ 	$(MAKE) -C $(RTSDIR) \
+@@ -2861,32 +2736,44 @@ gnatlib: ../stamp-gnatlib1-$(RTSDIR) ../
+ 
+ # Warning: this target assumes that LIBRARY_VERSION has been set correctly.
+ gnatlib-shared-default:
+-	$(MAKE) $(FLAGS_TO_PASS) \
+-             GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+-	     GNATLIBCFLAGS="$(GNATLIBCFLAGS) $(PICFLAG_FOR_TARGET)" \
+-	     GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C) $(PICFLAG_FOR_TARGET)" \
+-	     MULTISUBDIR="$(MULTISUBDIR)" \
+-	     THREAD_KIND="$(THREAD_KIND)" \
+-             gnatlib
+-	$(RM) $(RTSDIR)/libgna*$(soext)
++	$(MAKE) -C $(RTSDIR) \
++		CC="`echo \"$(GCC_FOR_TARGET)\" \
++		| sed -e 's,\./xgcc,../../xgcc,' -e 's,-B\./,-B../../,'`" \
++	        INCLUDES="$(INCLUDES_FOR_SUBDIR) -I./../.." \
++                CFLAGS="$(GNATLIBCFLAGS_FOR_C) $(PICFLAG_FOR_TARGET)" \
++	        FORCE_DEBUG_ADAFLAGS="$(FORCE_DEBUG_ADAFLAGS)" \
++		srcdir=$(fsrcdir) \
++	        -f ../Makefile $(LIBGNAT_OBJS)
++	$(MAKE) -C $(RTSDIR) \
++		CC="`echo \"$(GCC_FOR_TARGET)\" \
++		| sed -e 's,\./xgcc,../../xgcc,' -e 's,-B\./,-B../../,'`" \
++	        ADA_INCLUDES="" \
++                CFLAGS="$(GNATLIBCFLAGS) $(PICFLAG_FOR_TARGET)" \
++	        ADAFLAGS="$(GNATLIBFLAGS) $(PICFLAG_FOR_TARGET)" \
++	        FORCE_DEBUG_ADAFLAGS="$(FORCE_DEBUG_ADAFLAGS)" \
++		srcdir=$(fsrcdir) \
++	        -f ../Makefile \
++	        $(GNATRTL_OBJS)
++	$(RM) $(RTSDIR)/libgna*$(soext) $(RTSDIR)/libgna*$(soext).1
+ 	cd $(RTSDIR); `echo "$(GCC_FOR_TARGET)" \
+                 | sed -e 's,\./xgcc,../../xgcc,' -e 's,-B\./,-B../../,'` -shared $(GNATLIBCFLAGS) \
+ 		$(PICFLAG_FOR_TARGET) \
+-		-o libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
++		-o libgnat$(hyphen)$(LIBRARY_VERSION)$(soext).1 \
+ 		$(GNATRTL_NONTASKING_OBJS) $(LIBGNAT_OBJS) \
+-		$(SO_OPTS)libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
++		$(SO_OPTS)libgnat$(hyphen)$(LIBRARY_VERSION)$(soext).1 \
+ 		$(MISCLIB) -lm $(GNATLIBLDFLAGS)
+ 	cd $(RTSDIR); `echo "$(GCC_FOR_TARGET)" \
+                 | sed -e 's,\./xgcc,../../xgcc,' -e 's,-B\./,-B../../,'` -shared $(GNATLIBCFLAGS) \
+ 		$(PICFLAG_FOR_TARGET) \
+-		-o libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext) \
++		-o libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext).1 \
+ 		$(GNATRTL_TASKING_OBJS) \
+-		$(SO_OPTS)libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext) \
++		$(SO_OPTS)libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext).1 \
+ 		$(THREADSLIB) $(GNATLIBLDFLAGS)
+-	cd $(RTSDIR); $(LN_S) libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
+-		libgnat$(soext)
+-	cd $(RTSDIR); $(LN_S) libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext) \
+-		libgnarl$(soext)
++	cd $(RTSDIR); for lib in gnat gnarl; do \
++		l=lib$${lib}$(hyphen)$(LIBRARY_VERSION)$(soext); \
++		$(LN_S) $$l.1 $$l; \
++	done
++	$(CHMOD) a-wx $(RTSDIR)/*.ali
+ 
+ gnatlib-shared-dual:
+ 	$(MAKE) $(FLAGS_TO_PASS) \
+@@ -2896,9 +2783,8 @@ gnatlib-shared-dual:
+              GNATLIBLDFLAGS="$(GNATLIBLDFLAGS)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+-             gnatlib-shared-default
+-	$(MV) $(RTSDIR)/libgna*$(soext) .
+-	$(RM) ../stamp-gnatlib2-$(RTSDIR)
++	     gnatlib
++	$(RM) $(RTSDIR)/*.o $(RTSDIR)/*.ali
+ 	$(MAKE) $(FLAGS_TO_PASS) \
+              GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+@@ -2906,8 +2792,7 @@ gnatlib-shared-dual:
+              GNATLIBLDFLAGS="$(GNATLIBLDFLAGS)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+-             gnatlib
+-	$(MV) libgna*$(soext) $(RTSDIR)
++	     gnatlib-shared-default
+ 
+ gnatlib-shared-dual-win32:
+ 	$(MAKE) $(FLAGS_TO_PASS) \
+@@ -2917,17 +2802,15 @@ gnatlib-shared-dual-win32:
+ 	     PICFLAG_FOR_TARGET="$(PICFLAG_FOR_TARGET)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+-             gnatlib-shared-win32
+-	$(MV) $(RTSDIR)/libgna*$(soext) .
+-	$(RM) ../stamp-gnatlib2-$(RTSDIR)
++             gnatlib
++	$(RM) $(RTSDIR)/*.o $(RTSDIR)/*.ali
+ 	$(MAKE) $(FLAGS_TO_PASS) \
+              GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+ 	     GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+-             gnatlib
+-	$(MV) libgna*$(soext) $(RTSDIR)
++             gnatlib-shared-win32
+ 
+ # ??? we need to add the option to support auto-import of arrays/records to
+ # the GNATLIBFLAGS when this will be supported by GNAT. At this point we will
+@@ -3177,6 +3060,68 @@ targext.o : targext.c
+ 		$(ALL_CPPFLAGS) $(INCLUDES_FOR_SUBDIR) \
+ 		$< $(OUTPUT_OPTION)
+ 
++GCC_LINK=$(CXX) $(GCC_LINK_FLAGS) $(ADA_INCLUDES) $(LDFLAGS)
++
++../stamp-tools:
++	-$(RM) tools/*
++	-$(RMDIR) tools
++	-$(MKDIR) tools
++	-(cd tools; $(LN_S) ../sdefault.adb ../snames.ads ../snames.adb .)
++	-$(foreach PAIR,$(TOOLS_TARGET_PAIRS), \
++	          $(RM) tools/$(word 1,$(subst <, ,$(PAIR)));\
++	          $(LN_S) $(fsrcpfx)ada/$(word 2,$(subst <, ,$(PAIR))) \
++	                tools/$(word 1,$(subst <, ,$(PAIR)));)
++	touch ../stamp-tools
++
++gnatmake-re: ../stamp-tools
++	$(GNATMAKE) -j0 $(ADA_INCLUDES) -u sdefault --GCC="$(CC) $(MOST_ADA_FLAGS)"
++	$(GNATMAKE) -j0 -c $(ADA_INCLUDES) gnatmake --GCC="$(CC) $(ALL_ADAFLAGS)"
++	$(GNATBIND) $(ADA_INCLUDES) $(GNATBIND_FLAGS) gnatmake
++	$(GNATLINK) -v gnatmake -o ../../gnatmake$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++
++# Note the use of the "mv" command in order to allow gnatlink to be linked with
++# with the former version of gnatlink itself which cannot override itself.
++# gnatlink-re cannot be run at the same time as gnatmake-re, hence the
++# dependency
++gnatlink-re: ../stamp-tools gnatmake-re
++	$(GNATMAKE) -j0 -c $(ADA_INCLUDES) gnatlink --GCC="$(CC) $(ALL_ADAFLAGS)"
++	$(GNATBIND) $(ADA_INCLUDES) $(GNATBIND_FLAGS) gnatlink
++	$(GNATLINK) -v gnatlink -o ../../gnatlinknew$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(MV)  ../../gnatlinknew$(exeext)  ../../gnatlink$(exeext)
++
++# Likewise for the tools
++../../gnatmake$(exeext): $(P) b_gnatm.o $(GNATMAKE_OBJS)
++	+$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatm.o $(GNATMAKE_OBJS) $(TOOLS_LIBS)
++
++../../gnatlink$(exeext): $(P) b_gnatl.o $(GNATLINK_OBJS)
++	+$(GCC_LINK) $(ALL_CFLAGS) -o $@ b_gnatl.o $(GNATLINK_OBJS) $(TOOLS_LIBS)
++
++common-tools: ../stamp-tools
++	$(GNATMAKE) -j0 -c -b $(ADA_INCLUDES) \
++	  --GNATBIND="$(GNATBIND)" --GCC="$(CC) $(ALL_ADAFLAGS)" \
++	  gnatchop gnatcmd gnatkr gnatls gnatprep gnatxref gnatfind gnatname \
++	  gnatclean -bargs $(ADA_INCLUDES) $(GNATBIND_FLAGS)
++	$(GNATLINK) -v gnatcmd -o ../../gnat$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatchop -o ../../gnatchop$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatkr -o ../../gnatkr$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatls -o ../../gnatls$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatprep -o ../../gnatprep$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatxref -o ../../gnatxref$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatfind -o ../../gnatfind$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatname -o ../../gnatname$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++	$(GNATLINK) -v gnatclean -o ../../gnatclean$(exeext) \
++		$(TOOLS_LIBS) $(LDFLAGS)
++
+ # In GNU Make, ignore whether `stage*' exists.
+ .PHONY: stage1 stage2 stage3 stage4 clean realclean TAGS bootstrap
+ .PHONY: risky-stage1 risky-stage2 risky-stage3 risky-stage4
+Index: b/src/gnattools/Makefile.in
+===================================================================
+--- a/src/gnattools/Makefile.in
++++ b/src/gnattools/Makefile.in
+@@ -52,7 +52,7 @@ WARN_CFLAGS = @warn_cflags@
+ ADA_CFLAGS=@ADA_CFLAGS@
+ 
+ # Variables for gnattools.
+-ADAFLAGS= -gnatpg -gnata
++ADAFLAGS= -gnatn
+ 
+ # For finding the GCC build dir, which is used far too much
+ GCC_DIR=../gcc
+@@ -70,28 +70,168 @@ INCLUDES_FOR_SUBDIR = -iquote . -iquote
+ ADA_INCLUDES_FOR_SUBDIR = -I. -I$(fsrcdir)/ada
+ 
+ CXX_LFLAGS = \
+- -B../../../$(target_noncanonical)/libstdc++-v3/src/.libs \
+- -B../../../$(target_noncanonical)/libstdc++-v3/libsupc++/.libs \
+- -L../../../$(target_noncanonical)/libstdc++-v3/src/.libs \
+- -L../../../$(target_noncanonical)/libstdc++-v3/libsupc++/.libs
++ -B../$(target_noncanonical)/libstdc++-v3/src/.libs \
++ -B../$(target_noncanonical)/libstdc++-v3/libsupc++/.libs \
++ -L../$(target_noncanonical)/libstdc++-v3/src/.libs \
++ -L../$(target_noncanonical)/libstdc++-v3/libsupc++/.libs \
++ -L../$(target_noncanonical)/libatomic/.libs
++
++CFLAGS=-O2 -Wall
++ADA_CFLAGS=-O2 -gnatn
++ADA_INCLUDES=-nostdinc -I- -I. -I../gcc/ada/rts \
++     -I../$(target_noncanonical)/libgnatvsn -I../$(target_noncanonical)/libgnatprj
++LIB_VERSION=$(strip $(shell grep ' Library_Version :' \
++              ../$(target_noncanonical)/libgnatvsn/gnatvsn.ads | sed -e 's/.*"\(.*\)".*/\1/'))
++SHARED_ADA_LIBS := -L../gcc/ada/rts -lgnat-$(LIB_VERSION)
++SHARED_ADA_LIBS += -L../$(target_noncanonical)/libgnatvsn -lgnatvsn
++SHARED_ADA_LIBS += -L../$(target_noncanonical)/libgnatprj -lgnatprj
++STATIC_ADA_LIBS := ../gcc/ada/rts/libgnat.a
++STATIC_GCC_LIBS := ../gcc/libcommon-target.a ../gcc/libcommon.a ../libcpp/libcpp.a \
++../libbacktrace/.libs/libbacktrace.a ../libiberty/libiberty.a
++
++# We will use the just-built compiler to compile and link everything.
++GCC=../gcc/xgcc -B../gcc/ -no-pie
++GXX=../gcc/xg++ -B../gcc/ -no-pie
++
++# File lists
++# ----------
++
++# File associations set by configure
++EXTRA_GNATTOOLS = @EXTRA_GNATTOOLS@
++TOOLS_TARGET_PAIRS = @TOOLS_TARGET_PAIRS@
++
++# Stage 1 builds xgcc and gnatbind; we can use them to build
++# gnatmake-static and gnatlink-static, then use gnatmake-static and
++# gnatlink-static to build the other tools.  The reason we first build
++# statically-linked versions of gnatmake and gnatlink is so we can run
++# them with confidence on all build platforms, without LD_LIBRARY_PATH
++# or some such variable.
++
++# The tools we will build using gnatmake-static and gnatlink-static.
++TOOLS := gnat gnatbind gnatchop gnatclean gnatfind gnatkr gnatls gnatlink
++TOOLS += gnatmake gnatname gnatprep gnatxref
++
++# Since we don't have gnatmake, we must specify the full list of
++# object files necessary to build gnatmake and gnatlink.
++GNATLINK_OBJS = \
++gnatlink.o \
++indepsw.o \
++validsw.o \
++link.o
++
++GNATMAKE_OBJS = \
++aspects.o \
++errout.o \
++fname-sf.o \
++gnatmake.o \
++make.o \
++makeusg.o \
++mlib-prj.o \
++osint-m.o \
++restrict.o \
++sem_aux.o \
++usage.o \
++validsw.o \
++link.o \
++$(EXTRA_GNATMAKE_OBJS)
++
++EXTRA_TOOLS_OBJS = \
++bcheck.o \
++binde.o \
++bindgen.o \
++bindusg.o \
++clean.o \
++gprep.o \
++makegpr.o \
++osint-b.o \
++osint-l.o \
++prep.o \
++prj-makr.o \
++prj-pp.o \
++switch-b.o \
++vms_cmds.o \
++vms_conv.o \
++vms_data.o \
++xr_tabls.o \
++xref_lib.o
++
++OBJECTS = $(GNATLINK_OBJS) $(GNATMAKE_OBJS) $(EXTRA_TOOLS_OBJS)
++
++# Makefile targets
++# ----------------
++
++.PHONY: gnattools gnattools-native gnattools-cross regnattools
++gnattools: @default_gnattools_target@
++
++BODIES := $(foreach f,$(OBJECTS),$(wildcard $(patsubst %.o,@srcdir@/../gcc/ada/%.adb,$(f))))
++SPECS  := $(foreach f,$(OBJECTS),$(wildcard $(patsubst %.o,@srcdir@/../gcc/ada/%.ads,$(f))))
++
++$(notdir $(SPECS) $(BODIES)): stamp-gnattools-sources
++
++stamp-gnattools-sources:
++	for file in $(BODIES) $(SPECS); do \
++	   $(LN_S) -f $$file .; \
++	done
++	rm -f sdefault.adb; $(LN_S) ../gcc/ada/sdefault.adb .
++	$(foreach PAIR,$(TOOLS_TARGET_PAIRS), \
++	          rm -f $(word 1,$(subst <, ,$(PAIR)));\
++	          $(LN_S) @srcdir@/../gcc/ada/$(word 2,$(subst <, ,$(PAIR))) \
++	                  $(word 1,$(subst <, ,$(PAIR)));)
++	touch $@
++
++gnattools-native: ../gcc/ada/rts/libgnat-$(LIB_VERSION).so
++gnattools-native: ../$(target_noncanonical)/libgnatvsn/libgnatvsn.so
++gnattools-native: stamp-gnattools-sources
++gnattools-native: $(TOOLS)
++	cp -lpf $(TOOLS) ../gcc
++
++$(TOOLS) gnatcmd: | gnatmake-static gnatlink-static
++
++vpath %.c @srcdir@/../gcc/ada:@srcdir@/../gcc
++vpath %.h @srcdir@/../gcc/ada
++
++# gnatlink
++
++gnatlink-static: $(GNATLINK_OBJS) b_gnatl.o
++	$(GXX) -o $@ $^ \
++	  ../$(target_noncanonical)/libgnatprj/libgnatprj.a \
++	  ../$(target_noncanonical)/libgnatvsn/libgnatvsn.a \
++	  ../gcc/ada/rts/libgnat.a $(STATIC_GCC_LIBS) $(CXX_LFLAGS) $(LDFLAGS)
++
++gnatlink: $(GNATLINK_OBJS) b_gnatl.o
++	$(GXX) -o $@ $^ $(SHARED_ADA_LIBS) $(STATIC_GCC_LIBS) $(CXX_LFLAGS) $(LDFLAGS)
++
++b_gnatl.adb: $(GNATLINK_OBJS)
++	../gcc/gnatbind -o $@ $(ADA_INCLUDES) gnatlink.ali
++
++# gnatmake
++
++gnatmake-static: $(GNATMAKE_OBJS) b_gnatm.o
++	$(GXX) -o $@ $(ADA_CFLAGS) $^ \
++	  ../$(target_noncanonical)/libgnatprj/libgnatprj.a \
++	  ../$(target_noncanonical)/libgnatvsn/libgnatvsn.a \
++	  $(STATIC_ADA_LIBS) $(STATIC_GCC_LIBS) $(CXX_LFLAGS) $(LDFLAGS)
++
++gnatmake: $(GNATMAKE_OBJS) b_gnatm.o
++	$(GXX) -o $@ $(ADA_CFLAGS) $^ $(SHARED_ADA_LIBS) $(STATIC_GCC_LIBS) $(CXX_LFLAGS) $(LDFLAGS)
++
++b_gnatm.adb: $(GNATMAKE_OBJS)
++	../gcc/gnatbind -o $@ $(ADA_INCLUDES) gnatmake.ali
++
++# Other tools
++gnat: gnatcmd
++	cp -lp $< $@
++
++gnatbind gnatchop gnatclean gnatcmd gnatfind gnatkr gnatls gnatname gnatprep \
++gnatxref: link.o
++	if [ ! -f $@.adb ] ; then $(LN_S) ../../src/gcc/ada/$@.ad[bs] .; fi
++	./gnatmake-static -c -b $@ $(ADA_CFLAGS) $(ADA_INCLUDES) \
++	   --GCC="$(GCC)" \
++	   --GNATBIND=../gcc/gnatbind
++	./gnatlink-static -o $@ $@.ali $^ \
++	   $(ADA_INCLUDES) $(SHARED_ADA_LIBS) $(STATIC_GCC_LIBS) $(CXX_LFLAGS) $(LDFLAGS) \
++	   --GCC="$(GXX) $(ADA_INCLUDES)"
+ 
+-# Variables for gnattools, native
+-TOOLS_FLAGS_TO_PASS_NATIVE= \
+-	"CC=../../xgcc -B../../" \
+-	"CXX=../../xg++ -B../../ $(CXX_LFLAGS)" \
+-	"CFLAGS=$(CFLAGS) $(WARN_CFLAGS)" \
+-	"LDFLAGS=$(LDFLAGS)" \
+-	"ADAFLAGS=$(ADAFLAGS)" \
+-	"ADA_CFLAGS=$(ADA_CFLAGS)" \
+-	"INCLUDES=$(INCLUDES_FOR_SUBDIR)" \
+-	"ADA_INCLUDES=-I- -I../rts $(ADA_INCLUDES_FOR_SUBDIR)"\
+-	"exeext=$(exeext)" \
+-	"fsrcdir=$(fsrcdir)" \
+-	"srcdir=$(fsrcdir)" \
+-	"GNATMAKE=../../gnatmake" \
+-	"GNATLINK=../../gnatlink" \
+-	"GNATBIND=../../gnatbind" \
+-	"TOOLSCASE=native"
+ 
+ # Variables for regnattools
+ TOOLS_FLAGS_TO_PASS_RE= \
+@@ -184,20 +324,12 @@ $(GCC_DIR)/stamp-tools:
+ 	                $(GCC_DIR)/ada/tools/$(word 1,$(subst <, ,$(PAIR)));)
+ 	touch $(GCC_DIR)/stamp-tools
+ 
+-# gnatmake/link tools cannot always be built with gnatmake/link for bootstrap 
+-# reasons: gnatmake should be built with a recent compiler, a recent compiler
+-# may not generate ALI files compatible with an old gnatmake so it is important
+-# to be able to build gnatmake without a version of gnatmake around. Once 
+-# everything has been compiled once, gnatmake can be recompiled with itself 
+-# (see target regnattools) 
+-gnattools-native: $(GCC_DIR)/stamp-tools $(GCC_DIR)/stamp-gnatlib-rts
+-	# gnattools1
+-	$(MAKE) -C $(GCC_DIR)/ada/tools -f ../Makefile \
+-	  $(TOOLS_FLAGS_TO_PASS_NATIVE) \
+-	  ../../gnatmake$(exeext) ../../gnatlink$(exeext)
+-	# gnattools2
+-	$(MAKE) -C $(GCC_DIR)/ada/tools -f ../Makefile \
+-	  $(TOOLS_FLAGS_TO_PASS_NATIVE) common-tools
++%.o: %.adb
++	$(GCC) -c -o $@ $< $(ADA_CFLAGS) $(ADA_INCLUDES)
++
++%.o: %.ads
++	$(GCC) -c -o $@ $< $(ADA_CFLAGS) $(ADA_INCLUDES)
++
+ 
+ # gnatmake/link can be built with recent gnatmake/link if they are available.
+ # This is especially convenient for building cross tools or for rebuilding
--- gcc-6-6.4.0.orig/debian/patches/ada-gnattools-ldflags.diff
+++ gcc-6-6.4.0/debian/patches/ada-gnattools-ldflags.diff
@@ -0,0 +1,96 @@
+# DP: Link gnat tools with the defaults LDFLAGS
+
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -111,6 +111,7 @@ NO_SIBLING_ADAFLAGS = -fno-optimize-sibl
+ NO_REORDER_ADAFLAGS = -fno-toplevel-reorder
+ GNATLIBFLAGS = -W -Wall -gnatpg -nostdinc
+ GNATLIBCFLAGS = -g -O2
++GNATLIBLDFLAGS = $(LDFLAGS)
+ # Pretend that _Unwind_GetIPInfo is available for the target by default.  This
+ # should be autodetected during the configuration of libada and passed down to
+ # here, but we need something for --disable-libada and hope for the best.
+@@ -2627,23 +2628,23 @@ common-tools: ../stamp-tools
+ 	  gnatchop gnatcmd gnatkr gnatls gnatprep gnatxref gnatfind gnatname \
+ 	  gnatclean -bargs $(ADA_INCLUDES) $(GNATBIND_FLAGS)
+ 	$(GNATLINK) -v gnatcmd -o ../../gnat$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatchop -o ../../gnatchop$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatkr -o ../../gnatkr$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatls -o ../../gnatls$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatprep -o ../../gnatprep$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatxref -o ../../gnatxref$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatfind -o ../../gnatfind$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatname -o ../../gnatname$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 	$(GNATLINK) -v gnatclean -o ../../gnatclean$(exeext) \
+-		--GCC="$(GCC_LINK)" $(TOOLS_LIBS)
++		--GCC="$(GCC_LINK)" $(TOOLS_LIBS) $(LDFLAGS)
+ 
+ ../../gnatdll$(exeext): ../stamp-tools
+ 	$(GNATMAKE) -c $(ADA_INCLUDES) gnatdll --GCC="$(CC) $(ALL_ADAFLAGS)"
+@@ -2871,14 +2872,14 @@ gnatlib-shared-default:
+ 		-o libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
+ 		$(GNATRTL_NONTASKING_OBJS) $(LIBGNAT_OBJS) \
+ 		$(SO_OPTS)libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
+-		$(MISCLIB) -lm
++		$(MISCLIB) -lm $(GNATLIBLDFLAGS)
+ 	cd $(RTSDIR); `echo "$(GCC_FOR_TARGET)" \
+                 | sed -e 's,\./xgcc,../../xgcc,' -e 's,-B\./,-B../../,'` -shared $(GNATLIBCFLAGS) \
+ 		$(PICFLAG_FOR_TARGET) \
+ 		-o libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext) \
+ 		$(GNATRTL_TASKING_OBJS) \
+ 		$(SO_OPTS)libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext) \
+-		$(THREADSLIB)
++		$(THREADSLIB) $(GNATLIBLDFLAGS)
+ 	cd $(RTSDIR); $(LN_S) libgnat$(hyphen)$(LIBRARY_VERSION)$(soext) \
+ 		libgnat$(soext)
+ 	cd $(RTSDIR); $(LN_S) libgnarl$(hyphen)$(LIBRARY_VERSION)$(soext) \
+@@ -2889,6 +2890,7 @@ gnatlib-shared-dual:
+              GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+ 	     GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C)" \
++             GNATLIBLDFLAGS="$(GNATLIBLDFLAGS)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+              gnatlib-shared-default
+@@ -2898,6 +2900,7 @@ gnatlib-shared-dual:
+              GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+ 	     GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C)" \
++             GNATLIBLDFLAGS="$(GNATLIBLDFLAGS)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+              gnatlib
+@@ -2985,6 +2988,7 @@ gnatlib-shared:
+              GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+ 	     GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C)" \
++             GNATLIBLDFLAGS="$(GNATLIBLDFLAGS)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
+ 	     PICFLAG_FOR_TARGET="$(PICFLAG_FOR_TARGET)" \
+@@ -3030,6 +3034,7 @@ gnatlib-zcx:
+ 	     GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+ 	     GNATLIBCFLAGS_FOR_C="$(GNATLIBCFLAGS_FOR_C)" \
++             GNATLIBLDFLAGS="$(GNATLIBLDFLAGS)" \
+ 	     FORCE_DEBUG_ADAFLAGS="$(FORCE_DEBUG_ADAFLAGS)" \
+ 	     MULTISUBDIR="$(MULTISUBDIR)" \
+ 	     THREAD_KIND="$(THREAD_KIND)" \
--- gcc-6-6.4.0.orig/debian/patches/ada-kfreebsd.diff
+++ gcc-6-6.4.0/debian/patches/ada-kfreebsd.diff
@@ -0,0 +1,306 @@
+# DP: add support for GNU/kFreeBSD.
+
+Index: b/src/gcc/ada/terminals.c
+===================================================================
+--- a/src/gcc/ada/terminals.c
++++ b/src/gcc/ada/terminals.c
+@@ -1071,7 +1071,8 @@ __gnat_setup_winsize (void *desc, int ro
+ /* On some system termio is either absent or including it will disable termios
+    (HP-UX) */
+ #if !defined (__hpux__) && !defined (BSD) && !defined (__APPLE__) \
+-  && !defined (__rtems__)
++  && ! defined (__FreeBSD_kernel__) && ! defined (__GNU__) \
++  && ! defined (__rtems__)
+ #   include <termio.h>
+ #endif
+ 
+Index: b/src/gcc/ada/s-osinte-kfreebsd-gnu.adb
+===================================================================
+--- /dev/null
++++ b/src/gcc/ada/s-osinte-kfreebsd-gnu.adb
+@@ -0,0 +1,158 @@
++------------------------------------------------------------------------------
++--                                                                          --
++--                 GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS                 --
++--                                                                          --
++--                   S Y S T E M . O S _ I N T E R F A C E                  --
++--                                                                          --
++--                                   B o d y                                --
++--                                                                          --
++--             Copyright (C) 1991-1994, Florida State University            --
++--                     Copyright (C) 1995-2006, AdaCore                     --
++--                                                                          --
++-- GNARL is free software; you can  redistribute it  and/or modify it under --
++-- terms of the  GNU General Public License as published  by the Free Soft- --
++-- ware  Foundation;  either version 2,  or (at your option) any later ver- --
++-- sion. GNARL is distributed in the hope that it will be useful, but WITH- --
++-- OUT ANY WARRANTY;  without even the  implied warranty of MERCHANTABILITY --
++-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License --
++-- for  more details.  You should have  received  a copy of the GNU General --
++-- Public License  distributed with GNARL; see file COPYING.  If not, write --
++-- to  the  Free Software Foundation,  51  Franklin  Street,  Fifth  Floor, --
++-- Boston, MA 02110-1301, USA.                                              --
++--                                                                          --
++-- As a special exception,  if other files  instantiate  generics from this --
++-- unit, or you link  this unit with other files  to produce an executable, --
++-- this  unit  does not  by itself cause  the resulting  executable  to  be --
++-- covered  by the  GNU  General  Public  License.  This exception does not --
++-- however invalidate  any other reasons why  the executable file  might be --
++-- covered by the  GNU Public License.                                      --
++--                                                                          --
++-- GNARL was developed by the GNARL team at Florida State University.       --
++-- Extensive contributions were provided by Ada Core Technologies, Inc.     --
++--                                                                          --
++------------------------------------------------------------------------------
++
++--  This is the GNU/kFreeBSD version of this package.
++
++pragma Polling (Off);
++--  Turn off polling, we do not want ATC polling to take place during
++--  tasking operations. It causes infinite loops and other problems.
++
++--  This package encapsulates all direct interfaces to OS services
++--  that are needed by children of System.
++
++package body System.OS_Interface is
++
++   --------------------
++   -- Get_Stack_Base --
++   --------------------
++
++   function Get_Stack_Base (thread : pthread_t) return Address is
++      pragma Warnings (Off, thread);
++
++   begin
++      return Null_Address;
++   end Get_Stack_Base;
++
++   ------------------
++   -- pthread_init --
++   ------------------
++
++   procedure pthread_init is
++   begin
++      null;
++   end pthread_init;
++
++   -----------------------------------
++   -- pthread_mutexattr_setprotocol --
++   -----------------------------------
++
++   function pthread_mutexattr_setprotocol
++     (attr     : access pthread_mutexattr_t;
++      protocol : int) return int is
++      pragma Unreferenced (attr, protocol);
++   begin
++      return 0;
++   end pthread_mutexattr_setprotocol;
++
++   -----------------------------------
++   -- pthread_mutexattr_getprotocol --
++   -----------------------------------
++
++   function pthread_mutexattr_getprotocol
++     (attr     : access pthread_mutexattr_t;
++      protocol : access int) return int is
++      pragma Unreferenced (attr, protocol);
++   begin
++      return 0;
++   end pthread_mutexattr_getprotocol;
++
++   --------------------------------------
++   -- pthread_mutexattr_setprioceiling --
++   --------------------------------------
++
++   function pthread_mutexattr_setprioceiling
++     (attr     : access pthread_mutexattr_t;
++      prioceiling : int) return int is
++      pragma Unreferenced (attr, prioceiling);
++   begin
++      return 0;
++   end pthread_mutexattr_setprioceiling;
++
++   --------------------------------------
++   -- pthread_mutexattr_getprioceiling --
++   --------------------------------------
++
++   function pthread_mutexattr_getprioceiling
++     (attr     : access pthread_mutexattr_t;
++      prioceiling : access int) return int is
++      pragma Unreferenced (attr, prioceiling);
++   begin
++      return 0;
++   end pthread_mutexattr_getprioceiling;
++
++   -----------------
++   -- To_Duration --
++   -----------------
++
++   function To_Duration (TS : timespec) return Duration is
++   begin
++      return Duration (TS.tv_sec) + Duration (TS.tv_nsec) / 10#1#E9;
++   end To_Duration;
++
++   ------------------------
++   -- To_Target_Priority --
++   ------------------------
++
++   function To_Target_Priority
++     (Prio : System.Any_Priority) return Interfaces.C.int
++   is
++   begin
++      return Interfaces.C.int (Prio);
++   end To_Target_Priority;
++
++   -----------------
++   -- To_Timespec --
++   -----------------
++
++   function To_Timespec (D : Duration) return timespec is
++      S : time_t;
++      F : Duration;
++
++   begin
++      S := time_t (Long_Long_Integer (D));
++      F := D - Duration (S);
++
++      --  If F has negative value due to a round-up, adjust for positive F
++      --  value.
++
++      if F < 0.0 then
++         S := S - 1;
++         F := F + 1.0;
++      end if;
++
++      return timespec'(tv_sec => S,
++                       tv_nsec => long (Long_Long_Integer (F * 10#1#E9)));
++   end To_Timespec;
++
++end System.OS_Interface;
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -1397,7 +1397,7 @@ ifeq ($(strip $(filter-out %86 kfreebsd%
+   a-intnam.ads<a-intnam-freebsd.ads \
+   s-inmaop.adb<s-inmaop-posix.adb \
+   s-intman.adb<s-intman-posix.adb \
+-  s-osinte.adb<s-osinte-posix.adb \
++  s-osinte.adb<s-osinte-kfreebsd-gnu.adb \
+   s-osinte.ads<s-osinte-kfreebsd-gnu.ads \
+   s-osprim.adb<s-osprim-posix.adb \
+   s-taprop.adb<s-taprop-posix.adb \
+@@ -1457,7 +1457,7 @@ ifeq ($(strip $(filter-out x86_64 kfreeb
+   a-numaux.ads<a-numaux-x86.ads \
+   s-inmaop.adb<s-inmaop-posix.adb \
+   s-intman.adb<s-intman-posix.adb \
+-  s-osinte.adb<s-osinte-posix.adb \
++  s-osinte.adb<s-osinte-kfreebsd-gnu.adb \
+   s-osinte.ads<s-osinte-kfreebsd-gnu.ads \
+   s-osprim.adb<s-osprim-posix.adb \
+   s-taprop.adb<s-taprop-posix.adb \
+Index: b/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
+===================================================================
+--- a/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
++++ b/src/gcc/ada/s-osinte-kfreebsd-gnu.ads
+@@ -45,6 +45,7 @@ package System.OS_Interface is
+    pragma Preelaborate;
+ 
+    pragma Linker_Options ("-lpthread");
++   pragma Linker_Options ("-lrt");
+ 
+    subtype int            is Interfaces.C.int;
+    subtype char           is Interfaces.C.char;
+@@ -206,9 +207,7 @@ package System.OS_Interface is
+    function nanosleep (rqtp, rmtp : access timespec) return int;
+    pragma Import (C, nanosleep, "nanosleep");
+ 
+-   type clockid_t is private;
+-
+-   CLOCK_REALTIME : constant clockid_t;
++   type clockid_t is new int;
+ 
+    function clock_gettime
+      (clock_id : clockid_t;
+@@ -441,31 +440,25 @@ package System.OS_Interface is
+    PTHREAD_PRIO_PROTECT : constant := 2;
+    PTHREAD_PRIO_INHERIT : constant := 1;
+ 
++   --  GNU/kFreeBSD does not support Thread Priority Protection or Thread
++   --  Priority Inheritance and lacks some pthread_mutexattr_* functions.
++   --  Replace them with dummy versions.
++
+    function pthread_mutexattr_setprotocol
+      (attr     : access pthread_mutexattr_t;
+       protocol : int) return int;
+-   pragma Import
+-      (C, pthread_mutexattr_setprotocol, "pthread_mutexattr_setprotocol");
+ 
+    function pthread_mutexattr_getprotocol
+      (attr     : access pthread_mutexattr_t;
+       protocol : access int) return int;
+-   pragma Import
+-     (C, pthread_mutexattr_getprotocol, "pthread_mutexattr_getprotocol");
+ 
+    function pthread_mutexattr_setprioceiling
+      (attr     : access pthread_mutexattr_t;
+       prioceiling : int) return int;
+-   pragma Import
+-     (C, pthread_mutexattr_setprioceiling,
+-      "pthread_mutexattr_setprioceiling");
+ 
+    function pthread_mutexattr_getprioceiling
+      (attr     : access pthread_mutexattr_t;
+       prioceiling : access int) return int;
+-   pragma Import
+-     (C, pthread_mutexattr_getprioceiling,
+-      "pthread_mutexattr_getprioceiling");
+ 
+    type struct_sched_param is record
+       sched_priority : int;  --  scheduling priority
+@@ -592,8 +585,8 @@ private
+    --  #define sa_handler __sigaction_u._handler
+    --  #define sa_sigaction __sigaction_u._sigaction
+ 
+-   --  Should we add a signal_context type here ?
+-   --  How could it be done independent of the CPU architecture ?
++   --  Should we add a signal_context type here ???
++   --  How could it be done independent of the CPU architecture ???
+    --  sigcontext type is opaque, so it is architecturally neutral.
+    --  It is always passed as an access type, so define it as an empty record
+    --  since the contents are not used anywhere.
+@@ -610,9 +603,6 @@ private
+    end record;
+    pragma Convention (C, timespec);
+ 
+-   type clockid_t is new int;
+-   CLOCK_REALTIME : constant clockid_t := 0;
+-
+    type pthread_attr_t is record
+       detachstate   : int;
+       schedpolicy   : int;
+Index: b/src/gcc/ada/gsocket.h
+===================================================================
+--- a/src/gcc/ada/gsocket.h
++++ b/src/gcc/ada/gsocket.h
+@@ -243,6 +243,7 @@
+ #endif
+ 
+ #if defined (__FreeBSD__) || defined (__vxworks) || defined(__rtems__) \
++ || defined (__FreeBSD_kernel__) || defined(__GNU__) \
+  || defined (__DragonFly__) || defined (__NetBSD__) || defined (__OpenBSD__)
+ # define Has_Sockaddr_Len 1
+ #else
+Index: b/src/gcc/ada/s-oscons-tmplt.c
+===================================================================
+--- a/src/gcc/ada/s-oscons-tmplt.c
++++ b/src/gcc/ada/s-oscons-tmplt.c
+@@ -1436,7 +1436,7 @@ CND(CLOCK_FASTEST, "Fastest clock")
+ CND(CLOCK_THREAD_CPUTIME_ID, "Thread CPU clock")
+ 
+ #if defined(__FreeBSD__) || (defined(_AIX) && defined(_AIXVERSION_530)) \
+- || defined(__DragonFly__)
++ || defined(__DragonFly__) || defined(__FreeBSD_kernel__)
+ /** On these platforms use system provided monotonic clock instead of
+  ** the default CLOCK_REALTIME. We then need to set up cond var attributes
+  ** appropriately (see thread.c).
--- gcc-6-6.4.0.orig/debian/patches/ada-libgnatprj.diff
+++ gcc-6-6.4.0/debian/patches/ada-libgnatprj.diff
@@ -0,0 +1,1991 @@
+t
+# DP: - Introduce a new shared library named libgnatprj, containing
+# DP:   the GNAT project file manager licensed under the pure GPL, for
+# DP:   use in GNAT tools, GLADE and GPS.  Link the GNAT tools against
+# DP:   this new library.
+
+# This patch seems large, but the hunks in Makefile.in are actually
+# generated from Makefile.def using autogen.
+
+# !!! Must be applied after ada-libgnatvsn.dpatch
+
+Index: b/src/gcc/ada/gcc-interface/config-lang.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/config-lang.in
++++ b/src/gcc/ada/gcc-interface/config-lang.in
+@@ -34,8 +34,8 @@ gtfiles="\$(srcdir)/ada/gcc-interface/ad
+ 
+ outputs="ada/gcc-interface/Makefile ada/Makefile"
+ 
+-target_libs="target-libada target-libgnatvsn"
+-lang_dirs="libada libgnatvsn gnattools"
++target_libs="target-libada target-libgnatvsn target-libgnatprj"
++lang_dirs="libada libgnatvsn libgnatprj gnattools"
+ 
+ # Ada is not enabled by default for the time being.
+ build_by_default=no
+Index: b/src/libgnatprj/Makefile.in
+===================================================================
+--- /dev/null
++++ b/src/libgnatprj/Makefile.in
+@@ -0,0 +1,180 @@
++# Makefile for libgnatprj.
++#   Copyright (c) 2006 Ludovic Brenta <ludovic@ludovic-brenta.org>
++#
++# This file is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++# 
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++# 
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++# Default target; must be first.
++all: libgnatprj
++
++.SUFFIXES:
++
++CPUS := $(shell getconf _NPROCESSORS_ONLN)
++LIB_VERSION := $(strip $(shell grep ' Library_Version :' \
++                 @srcdir@/../gcc/ada/gnatvsn.ads | \
++	         sed -e 's/.*"\(.*\)".*/\1/'))
++GCC=$(CC)
++GPP=$(CXX)
++LIBGNAT_JUST_BUILT := -nostdinc -I../../gcc/ada/rts
++LIBGNATVSN := -I../libgnatvsn
++CFLAGS := -g -O2
++ADAFLAGS := -g -O2 -gnatn
++BASEVER := $(shell cat @srcdir@/../gcc/BASE-VER)
++DEVPHASE := $(shell cat @srcdir@/../gcc/DEV-PHASE)
++DATESTAMP := $(shell cat @srcdir@/../gcc/DATESTAMP)
++TOOLS_TARGET_PAIRS := @TOOLS_TARGET_PAIRS@
++LN_S := @LN_S@
++
++ifneq (@build@,@host@)
++   CFLAGS += -b @host@
++endif
++
++.PHONY: libgnatprj install
++libgnatprj: libgnatprj.so.$(LIB_VERSION) libgnatprj.a
++
++# Here we list one file per Ada unit: the body file if the unit has a
++# body, the spec file otherwise.
++PRJ_SOURCES := ali.adb ali-util.adb butil.adb binderr.adb errout.adb \
++erroutc.adb errutil.adb err_vars.ads fname-uf.adb fmap.adb impunit.adb \
++lib-util.adb makeutl.adb mlib.adb mlib-fil.adb mlib-tgt.adb \
++mlib-tgt-specific.adb mlib-utl.adb osint.adb osint-c.adb prj.adb prj-attr.adb \
++prj-attr-pm.adb prj-com.ads prj-conf.adb prj-dect.adb prj-env.adb prj-err.adb \
++prj-ext.adb prj-makr.adb prj-nmsc.adb prj-pars.adb prj-part.adb prj-pp.adb \
++prj-proc.adb prj-strt.adb prj-tree.adb prj-util.adb restrict.adb rident.ads \
++scng.adb sfn_scan.adb sinfo-cn.adb sinput-c.adb sinput-p.adb style.adb \
++styleg.adb stylesw.adb switch.adb switch-m.adb targparm.adb tempdir.adb
++
++# Source files generated in build/gcc/ada, not src/gcc/ada.
++GENERATED_SOURCES := sdefault.adb
++
++SOURCES := $(PRJ_SOURCES) $(GENERATED_SOURCES)
++
++OBJECTS := $(patsubst %.ads,%.o,$(SOURCES:.adb=.o))
++
++# Add some object files compiled from C sources.  prefix.o requires
++# some objects from libiberty and from gcc.
++OBJECTS += link.o prefix.o
++
++# These object files have already been built, both PIC and non-PIC.
++# prefix.o depends on them.
++LIBIBERTY_OBJECTS := concat.o filename_cmp.o lrealpath.o safe-ctype.o xexit.o xmalloc.o xstrdup.o
++
++vpath %.c @srcdir@ @srcdir@/../gcc @srcdir@/../gcc/common @srcdir@/../gcc/ada
++
++libgnatprj.so.$(LIB_VERSION): $(addprefix obj-shared/,$(OBJECTS))
++	: # Make libgnatprj.so
++	$(GCC) -o $@ -shared -fPIC -Wl,--soname,$@ -Wl,--no-allow-shlib-undefined \
++	   $^ $(addprefix ../libiberty/pic/,$(LIBIBERTY_OBJECTS)) \
++	   -L../../gcc/ada/rts -lgnat-$(LIB_VERSION) \
++	   -L../libgnatvsn -lgnatvsn $(LDFLAGS)
++	$(LN_S) -f libgnatprj.so.$(LIB_VERSION) libgnatprj.so
++	chmod a=r obj-shared/*.ali
++# Make the .ali files, but not the .o files, visible to the gnat tools.
++	cp -lp obj-shared/*.ali .
++
++$(addprefix obj-shared/,$(OBJECTS)): | stamp-libgnatprj-sources obj-shared
++
++obj-shared/%.o: %.adb
++	$(GCC) -c -fPIC $(ADAFLAGS) $(LIBGNAT_JUST_BUILT) $(LIBGNATVSN) -DUSED_FOR_TARGET $< -o $@
++
++obj-shared/%.o: %.ads
++	$(GCC) -c -fPIC $(ADAFLAGS) $(LIBGNAT_JUST_BUILT) $(LIBGNATVSN) -DUSED_FOR_TARGET $< -o $@
++
++obj-shared/%.o: %.c
++	$(GPP) -c -fPIC $(CFLAGS) -DHAVE_CONFIG_H -pedantic \
++	   -I. -I@srcdir@/../gcc -I@srcdir@/../include -I@srcdir@/../libcpp/include -I../../gcc -DUSED_FOR_TARGET \
++	   $< -o $@
++
++obj-shared/prefix.o: @srcdir@/../gcc/prefix.c
++	$(GPP) -c -fPIC $(CFLAGS) -DPREFIX=\"@prefix@\" -DBASEVER=\"$(BASEVER)\" \
++	   -I. -I@srcdir@/../gcc -I@srcdir@/../include -I../../gcc -I@srcdir@/../libcpp/include -DUSED_FOR_TARGET \
++	   $< -o $@
++
++obj-shared:
++	-mkdir $@
++
++libgnatprj.a: $(addprefix obj-static/,$(OBJECTS))
++	: # Make libgnatprj.a
++	ar rc $@ $^ $(addprefix ../libiberty/,$(LIBIBERTY_OBJECTS))
++	ranlib $@
++
++$(addprefix obj-static/,$(OBJECTS)): | stamp-libgnatprj-sources obj-static
++
++obj-static/%.o: %.adb
++	$(GCC) -c $(ADAFLAGS) $(LIBGNAT_JUST_BUILT) $(LIBGNATVSN) -DUSED_FOR_TARGET $< -o $@
++
++obj-static/%.o: %.ads
++	$(GCC) -c $(ADAFLAGS) $(LIBGNAT_JUST_BUILT) $(LIBGNATVSN) -DUSED_FOR_TARGET $< -o $@
++
++obj-static/%.o: %.c
++	$(GPP) -c $(CFLAGS) -DHAVE_CONFIG_H -pedantic \
++	   -I. -I@srcdir@/../gcc -I@srcdir@/../include -I@srcdir@/../libcpp/include -I../../gcc -DUSED_FOR_TARGET \
++	   $< -o $@
++
++obj-static/prefix.o: @srcdir@/../gcc/prefix.c
++	$(GPP) -c $(CFLAGS) -DPREFIX=\"@prefix@\" -DBASEVER=\"$(BASEVER)\" \
++	   -I. -I@srcdir@/../gcc -I@srcdir@/../include -I../../gcc -I@srcdir@/../libcpp/include -DUSED_FOR_TARGET \
++	   $< -o $@
++
++obj-static:
++	-mkdir $@
++
++$(SOURCES): stamp-libgnatprj-sources
++
++stamp-libgnatprj-sources:
++	for file in $(PRJ_SOURCES); do \
++	   ads=$$(echo $$file | sed 's/\.adb/.ads/'); \
++	   if [ -f @srcdir@/../gcc/ada/$$file -a ! -L $$file ] ; then $(LN_S) @srcdir@/../gcc/ada/$$file .; fi; \
++	   if [ -f @srcdir@/../gcc/ada/$$ads -a ! -L $$ads ] ; then $(LN_S) @srcdir@/../gcc/ada/$$ads .; fi; \
++	done
++	for file in $(GENERATED_SOURCES); do \
++	   ads=$$(echo $$file | sed 's/\.adb/.ads/'); \
++	   if [ -f ../../gcc/ada/$$file -a ! -L $$file ] ; then $(LN_S) ../../gcc/ada/$$file .; fi; \
++	   if [ -f ../../gcc/ada/$$ads -a ! -L $$ads ] ; then $(LN_S) ../../gcc/ada/$$ads .; \
++	   else \
++	      if [ -f @srcdir@/../gcc/ada/$$ads -a ! -L $$ads ] ; then $(LN_S) @srcdir@/../gcc/ada/$$ads .; fi; \
++	   fi; \
++	done
++	$(foreach PAIR,$(TOOLS_TARGET_PAIRS), \
++	          rm -f $(word 1,$(subst <, ,$(PAIR)));\
++	          $(LN_S) @srcdir@/../gcc/ada/$(word 2,$(subst <, ,$(PAIR))) \
++	                  $(word 1,$(subst <, ,$(PAIR)));)
++	touch $@
++
++# Generate a list of source files (.ads and .adb) to install.  Almost
++# all of them are in src/gcc/ada, but some are generated during build
++# and are in build/gcc/ada.
++BODIES := $(filter %.adb,$(PRJ_SOURCES))
++SPECS := $(filter %.ads,$(PRJ_SOURCES)) $(patsubst %.adb,%.ads,$(BODIES) $(GENERATED_SOURCES))
++SOURCES_TO_INSTALL := \
++$(addprefix  @srcdir@/../gcc/ada/,$(SPECS) $(BODIES)) \
++$(addprefix ../../gcc/ada/,$(GENERATED_SOURCES))
++
++libdir = @libdir@
++
++install: libgnatprj
++	$(INSTALL_DATA) libgnatprj.a $(DESTDIR)$(libdir)
++	$(INSTALL_DATA) libgnatprj.so.$(LIB_VERSION) $(DESTDIR)$(libdir)
++	cd $(DESTDIR)$(libdir); ln -sf libgnatprj.so.$(LIB_VERSION) libgnatprj.so
++	mkdir -p $(DESTDIR)$(prefix)/share/ada/adainclude/gnatprj
++	$(INSTALL_DATA) $(SOURCES_TO_INSTALL) \
++	   $(DESTDIR)$(prefix)/share/ada/adainclude/gnatprj
++	mkdir -p $(DESTDIR)$(prefix)/lib/ada/adalib/gnatprj
++	$(INSTALL) -m 0444 obj-shared/*.ali \
++	   $(DESTDIR)$(prefix)/lib/ada/adalib/gnatprj
++	chmod a=r $(DESTDIR)$(prefix)/lib/ada/adalib/gnatprj/*.ali
++
++.PHONY: clean
++clean:
++	rm -rf *.ali obj-static obj-shared libgnatprj* *.adb *.ads stamp*
+Index: b/src/libgnatprj/targetm.c
+===================================================================
+--- /dev/null
++++ b/src/libgnatprj/targetm.c
+@@ -0,0 +1,7 @@
++#include "config.h"
++#include "system.h"
++#include "coretypes.h"
++#include "common/common-target.h"
++#include "common/common-target-def.h"
++
++struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
+Index: b/src/Makefile.def
+===================================================================
+--- a/src/Makefile.def
++++ b/src/Makefile.def
+@@ -190,6 +190,13 @@ target_modules = { module= libgnatvsn; n
+ 		   missing= TAGS;
+ 		   missing= install-info;
+ 		   missing= installcheck; };
++target_modules = { module= libgnatprj; no_check=true;
++		   missing= info;
++		   missing= dvi;
++		   missing= html;
++		   missing= TAGS;
++		   missing= install-info;
++		   missing= installcheck; };
+ target_modules = { module= libgomp; bootstrap= true; lib_path=.libs; };
+ target_modules = { module= libitm; lib_path=.libs; };
+ target_modules = { module= libatomic; lib_path=.libs; };
+@@ -389,8 +396,12 @@ dependencies = { module=all-fixincludes;
+ dependencies = { module=all-target-libada; on=all-gcc; };
+ dependencies = { module=all-gnattools; on=all-target-libada; };
+ dependencies = { module=all-gnattools; on=all-target-libgnatvsn; };
++dependencies = { module=all-gnattools; on=all-target-libgnatprj; };
+ dependencies = { module=all-target-libgnatvsn; on=all-target-libada; };
++dependencies = { module=all-target-libgnatprj; on=all-target-libgnatvsn; };
++dependencies = { module=all-target-libgnatprj; on=all-target-libiberty; };
+ dependencies = { module=all-gnattools; on=all-target-libstdc++-v3; };
++dependencies = { module=all-target-libgnatvsn; on=all-target-libstdc++-v3; };
+ 
+ // Depending on the specific configuration, the LTO plugin will either use the
+ // generic libiberty build or the specific build for linker plugins.
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -178,6 +178,7 @@ target_libraries="target-libgcc \
+ 		target-libada \
+ 		${target_libiberty} \
+ 		target-libgnatvsn \
++		target-libgnatprj \
+ 		target-libgo"
+ 
+ # these tools are built using the target libraries, and are intended to
+@@ -462,7 +463,7 @@ AC_ARG_ENABLE(libada,
+ ENABLE_LIBADA=$enableval,
+ ENABLE_LIBADA=yes)
+ if test "${ENABLE_LIBADA}" != "yes" ; then
+-  noconfigdirs="$noconfigdirs target-libgnatvsn gnattools"
++  noconfigdirs="$noconfigdirs target-libgnatvsn target-libgnatprj gnattools"
+ fi
+ 
+ AC_ARG_ENABLE(libssp,
+Index: b/src/libgnatprj/configure.ac
+===================================================================
+--- /dev/null
++++ b/src/libgnatprj/configure.ac
+@@ -0,0 +1,557 @@
++# Configure script for libada.
++#   Copyright 2003, 2004 Free Software Foundation, Inc.
++#
++# This file is free software; you can redistribute it and/or modify it
++# under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful, but
++# WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++# General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++
++AC_INIT
++AC_PREREQ([2.63])
++
++AC_CONFIG_SRCDIR([Makefile.in])
++
++# Start of actual configure tests
++
++AC_PROG_INSTALL
++
++AC_CANONICAL_BUILD
++AC_CANONICAL_HOST
++AC_CANONICAL_TARGET
++
++GCC_NO_EXECUTABLES
++AC_PROG_CC
++AC_GNU_SOURCE
++AC_PROG_CPP_WERROR
++
++AC_PROG_CC_C_O
++# autoconf is lame and doesn't give us any substitution variable for this.
++if eval "test \"`echo '$ac_cv_prog_cc_'${ac_cc}_c_o`\" = no"; then
++  NO_MINUS_C_MINUS_O=yes
++else
++  OUTPUT_OPTION='-o $@'
++fi
++AC_SUBST(NO_MINUS_C_MINUS_O)
++AC_SUBST(OUTPUT_OPTION)
++
++AC_C_CONST
++AC_C_INLINE
++AC_C_BIGENDIAN
++
++dnl When we start using libtool:
++dnl AM_PROG_LIBTOOL
++
++dnl When we start using automake:
++dnl AM_CONFIG_HEADER(config.h:config.in)
++AC_CONFIG_HEADER(config.h:config.in)
++
++sinclude(../config/acx.m4)
++ACX_NONCANONICAL_TARGET
++
++# Need to pass this down for now :-P
++AC_PROG_LN_S
++
++# It's OK to check for header files.  Although the compiler may not be
++# able to link anything, it had better be able to at least compile
++# something.
++AC_CHECK_HEADERS(sys/file.h sys/param.h limits.h stdlib.h malloc.h string.h unistd.h strings.h sys/time.h time.h sys/resource.h sys/stat.h sys/mman.h fcntl.h alloca.h sys/pstat.h sys/sysmp.h sys/sysinfo.h machine/hal_sysinfo.h sys/table.h sys/sysctl.h sys/systemcfg.h stdint.h stdio_ext.h process.h sys/prctl.h)
++AC_HEADER_SYS_WAIT
++AC_HEADER_TIME
++
++# Determine sizes of some types.
++AC_CHECK_SIZEOF([int])
++AC_CHECK_SIZEOF([long])
++AC_CHECK_SIZEOF([size_t])
++
++AC_TYPE_INTPTR_T
++AC_TYPE_UINTPTR_T
++AC_TYPE_SSIZE_T
++
++# Given the above check, we always have uintptr_t or a fallback
++# definition.  So define HAVE_UINTPTR_T in case any imported code
++# relies on it.
++AC_DEFINE(HAVE_UINTPTR_T, 1, [Define if you have the \`uintptr_t' type.])
++
++AC_TYPE_PID_T
++
++# This is the list of functions which libiberty will provide if they
++# are not available on the host.
++
++funcs="asprintf"
++funcs="$funcs atexit"
++funcs="$funcs basename"
++funcs="$funcs bcmp"
++funcs="$funcs bcopy"
++funcs="$funcs bsearch"
++funcs="$funcs bzero"
++funcs="$funcs calloc"
++funcs="$funcs clock"
++funcs="$funcs ffs"
++funcs="$funcs getcwd"
++funcs="$funcs getpagesize"
++funcs="$funcs gettimeofday"
++funcs="$funcs index"
++funcs="$funcs insque"
++funcs="$funcs memchr"
++funcs="$funcs memcmp"
++funcs="$funcs memcpy"
++funcs="$funcs memmem"
++funcs="$funcs memmove"
++funcs="$funcs mempcpy"
++funcs="$funcs memset"
++funcs="$funcs mkstemps"
++funcs="$funcs putenv"
++funcs="$funcs random"
++funcs="$funcs rename"
++funcs="$funcs rindex"
++funcs="$funcs setenv"
++funcs="$funcs snprintf"
++funcs="$funcs sigsetmask"
++funcs="$funcs stpcpy"
++funcs="$funcs stpncpy"
++funcs="$funcs strcasecmp"
++funcs="$funcs strchr"
++funcs="$funcs strdup"
++funcs="$funcs strncasecmp"
++funcs="$funcs strndup"
++funcs="$funcs strnlen"
++funcs="$funcs strrchr"
++funcs="$funcs strstr"
++funcs="$funcs strtod"
++funcs="$funcs strtol"
++funcs="$funcs strtoul"
++funcs="$funcs strtoll"
++funcs="$funcs strtoull"
++funcs="$funcs strverscmp"
++funcs="$funcs tmpnam"
++funcs="$funcs vasprintf"
++funcs="$funcs vfprintf"
++funcs="$funcs vprintf"
++funcs="$funcs vsnprintf"
++funcs="$funcs vsprintf"
++funcs="$funcs waitpid"
++funcs="$funcs setproctitle"
++
++# Also in the old function.def file: alloca, vfork, getopt.
++
++vars="sys_errlist sys_nerr sys_siglist"
++
++checkfuncs="__fsetlocking canonicalize_file_name dup3 getrlimit getrusage \
++ getsysinfo gettimeofday on_exit psignal pstat_getdynamic pstat_getstatic \
++ realpath setrlimit sbrk spawnve spawnvpe strerror strsignal sysconf sysctl \
++ sysmp table times wait3 wait4"
++
++# These are neither executed nor required, but they help keep
++# autoheader happy without adding a bunch of text to acconfig.h.
++if test "x" = "y"; then
++  AC_CHECK_FUNCS(asprintf atexit \
++    basename bcmp bcopy bsearch bzero \
++    calloc canonicalize_file_name clock \
++    dup3 \
++    ffs __fsetlocking \
++    getcwd getpagesize getrlimit getrusage getsysinfo gettimeofday \
++    index insque \
++    memchr memcmp memcpy memmem memmove memset mkstemps \
++    on_exit \
++    psignal pstat_getdynamic pstat_getstatic putenv \
++    random realpath rename rindex \
++    sbrk setenv setproctitle setrlimit sigsetmask snprintf spawnve spawnvpe \
++     stpcpy stpncpy strcasecmp strchr strdup \
++     strerror strncasecmp strndup strnlen strrchr strsignal strstr strtod \
++     strtol strtoul strtoll strtoull strverscmp sysconf sysctl sysmp \
++    table times tmpnam \
++    vasprintf vfprintf vprintf vsprintf \
++    wait3 wait4 waitpid)
++  AC_CHECK_DECLS([basename, ffs, asprintf, vasprintf, snprintf, vsnprintf, strtol, strtoul, strtoll, strtoull])
++  AC_DEFINE(HAVE_SYS_ERRLIST, 1, [Define if you have the sys_errlist variable.])
++  AC_DEFINE(HAVE_SYS_NERR,    1, [Define if you have the sys_nerr variable.])
++  AC_DEFINE(HAVE_SYS_SIGLIST, 1, [Define if you have the sys_siglist variable.])
++fi
++
++# For each of these functions, if the host does not provide the
++# function we want to put FN.o in LIBOBJS, and if the host does
++# provide the function, we want to define HAVE_FN in config.h.
++
++setobjs=
++CHECK=
++if test -n "${with_target_subdir}"; then
++
++  # We are being configured as a target library.  AC_REPLACE_FUNCS
++  # may not work correctly, because the compiler may not be able to
++  # link executables.  Note that we may still be being configured
++  # native.
++
++  # If we are being configured for newlib, we know which functions
++  # newlib provide and which ones we will be expected to provide.
++
++  if test "x${with_newlib}" = "xyes"; then
++    AC_LIBOBJ([asprintf])
++    AC_LIBOBJ([basename])
++    AC_LIBOBJ([insque])
++    AC_LIBOBJ([random])
++    AC_LIBOBJ([strdup])
++    AC_LIBOBJ([vasprintf])
++
++    for f in $funcs; do
++      case "$f" in
++	asprintf | basename | insque | random | strdup | vasprintf)
++	  ;;
++	*)
++	  n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
++	  AC_DEFINE_UNQUOTED($n)
++	  ;;
++      esac
++    done
++
++    # newlib doesnt provide any of the variables in $vars, so we
++    # dont have to check them here.
++
++    # Of the functions in $checkfuncs, newlib only has strerror.
++    AC_DEFINE(HAVE_STRERROR)
++
++    setobjs=yes
++
++  fi
++
++  # If we are being configured for Mingw, we know which functions
++  # Mingw provides and which ones we will be expected to provide.
++
++  case "${host}" in
++  *-*-mingw*)
++    AC_LIBOBJ([asprintf])
++    AC_LIBOBJ([basename])
++    AC_LIBOBJ([bcmp])
++    AC_LIBOBJ([bcopy])
++    AC_LIBOBJ([bzero])
++    AC_LIBOBJ([clock])
++    AC_LIBOBJ([ffs])
++    AC_LIBOBJ([getpagesize])
++    AC_LIBOBJ([index])
++    AC_LIBOBJ([insque])
++    AC_LIBOBJ([mempcpy])
++    AC_LIBOBJ([mkstemps])
++    AC_LIBOBJ([random])
++    AC_LIBOBJ([rindex])
++    AC_LIBOBJ([sigsetmask])
++    AC_LIBOBJ([stpcpy])
++    AC_LIBOBJ([stpncpy])
++    AC_LIBOBJ([strndup])
++    AC_LIBOBJ([strnlen])
++    AC_LIBOBJ([strverscmp])
++    AC_LIBOBJ([vasprintf])
++    AC_LIBOBJ([waitpid])
++
++    for f in $funcs; do
++      case "$f" in
++	asprintf | basename | bcmp | bcopy | bzero | clock | ffs | getpagesize | index | insque | mempcpy | mkstemps | random | rindex | sigsetmask | stpcpy | stpncpy | strdup | strndup | strnlen | strverscmp | vasprintf | waitpid)
++	  ;;
++	*)
++	  n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
++	  AC_DEFINE_UNQUOTED($n)
++	  ;;
++      esac
++    done
++
++    # Mingw doesnt provide any of the variables in $vars, so we
++    # dont have to check them here.
++
++    # Of the functions in $checkfuncs, Mingw only has strerror.
++    AC_DEFINE(HAVE_STRERROR)
++
++    setobjs=yes
++    ;;
++
++  *-*-msdosdjgpp)
++    AC_LIBOBJ([vasprintf])
++    AC_LIBOBJ([vsnprintf])
++    AC_LIBOBJ([snprintf])
++    AC_LIBOBJ([asprintf])
++
++    for f in atexit basename bcmp bcopy bsearch bzero calloc clock ffs \
++             getcwd getpagesize getrusage gettimeofday \
++             index insque memchr memcmp memcpy memmove memset psignal \
++             putenv random rename rindex sbrk setenv stpcpy strcasecmp \
++             strchr strdup strerror strncasecmp strrchr strstr strtod \
++             strtol strtoul sysconf times tmpnam vfprintf vprintf \
++             vsprintf waitpid
++    do
++      n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
++      AC_DEFINE_UNQUOTED($n)
++    done
++
++
++    setobjs=yes
++    ;;
++
++  esac
++
++else
++
++   # Not a target library, so we set things up to run the test suite.
++   CHECK=really-check
++
++fi
++
++AC_SUBST(CHECK)
++AC_SUBST(target_header_dir)
++
++case "${host}" in
++  *-*-cygwin* | *-*-mingw*)
++    AC_DEFINE(HAVE_SYS_ERRLIST)
++    AC_DEFINE(HAVE_SYS_NERR)
++    ;;
++esac
++
++if test -z "${setobjs}"; then
++  case "${host}" in
++
++  *-*-vxworks*)
++    # Handle VxWorks configuration specially, since on VxWorks the
++    # libraries are actually on the target board, not in the file
++    # system.
++    AC_LIBOBJ([basename])
++    AC_LIBOBJ([getpagesize])
++    AC_LIBOBJ([insque])
++    AC_LIBOBJ([random])
++    AC_LIBOBJ([strcasecmp])
++    AC_LIBOBJ([strncasecmp])
++    AC_LIBOBJ([strdup])
++    AC_LIBOBJ([vfork])
++    AC_LIBOBJ([waitpid])
++    AC_LIBOBJ([vasprintf])
++    for f in $funcs; do
++      case "$f" in
++	basename | getpagesize | insque | random | strcasecmp)
++	  ;;
++	strncasecmp | strdup | vfork | waitpid | vasprintf)
++	  ;;
++	*)
++	  n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
++	  AC_DEFINE_UNQUOTED($n)
++	  ;;
++      esac
++    done
++
++    # VxWorks doesn't provide any of the variables in $vars, so we
++    # don't have to check them here.
++
++    # Of the functions in $checkfuncs, VxWorks only has strerror.
++    AC_DEFINE(HAVE_STRERROR)
++
++    setobjs=yes
++    ;;
++
++  esac
++fi
++
++if test -z "${setobjs}"; then
++
++  case "${host}" in
++
++  *-*-android*)
++    # On android, getpagesize is defined in unistd.h as a static inline
++    # function, which AC_CHECK_FUNCS does not handle properly.
++    ac_cv_func_getpagesize=yes
++    ;;
++
++  *-*-mingw32*)
++    # Under mingw32, sys_nerr and sys_errlist exist, but they are
++    # macros, so the test below won't find them.
++    libgnatprj_cv_var_sys_nerr=yes
++    libgnatprj_cv_var_sys_errlist=yes
++    ;;
++
++  *-*-msdosdjgpp*)
++    # vfork and fork are stubs.
++    ac_cv_func_vfork_works=no
++    ;;
++
++  *-*-uwin*)
++    # Under some versions of uwin, vfork is notoriously buggy and the test 
++    # can hang configure; on other versions, vfork exists just as a stub.
++    # FIXME: This should be removed once vfork in uwin's runtime is fixed.
++    ac_cv_func_vfork_works=no
++    # Under uwin 2.0+, sys_nerr and sys_errlist exist, but they are
++    # macros (actually, these are imported from a DLL, but the end effect 
++    # is the same), so the test below won't find them.
++    libgnatprj_cv_var_sys_nerr=yes
++    libgnatprj_cv_var_sys_errlist=yes
++    ;;
++
++  *-*-*vms*)
++    # Under VMS, vfork works very different than on Unix. The standard test 
++    # won't work, and it isn't easily adaptable. It makes more sense to
++    # just force it.
++    ac_cv_func_vfork_works=yes
++    ;;
++
++  esac
++
++  # We haven't set the list of objects yet.  Use the standard autoconf
++  # tests.  This will only work if the compiler works.
++  AC_ISC_POSIX
++  AC_REPLACE_FUNCS($funcs)
++  AC_FUNC_FORK
++  if test $ac_cv_func_vfork_works = no; then
++    AC_LIBOBJ([vfork])
++  fi
++  # We only need _doprnt if we might use it to implement v*printf.
++  if test $ac_cv_func_vprintf != yes \
++     || test $ac_cv_func_vfprintf != yes \
++     || test $ac_cv_func_vsprintf != yes; then
++    AC_REPLACE_FUNCS(_doprnt)
++  else
++    AC_CHECK_FUNCS(_doprnt)
++  fi
++
++  for v in $vars; do
++    AC_MSG_CHECKING([for $v])
++    AC_CACHE_VAL(libgnatprj_cv_var_$v,
++      [AC_LINK_IFELSE([AC_LANG_PROGRAM([[int *p;]],[[extern int $v []; p = $v;]])],
++		      [eval "libgnatprj_cv_var_$v=yes"],
++		      [eval "libgnatprj_cv_var_$v=no"])])
++    if eval "test \"`echo '$libgnatprj_cv_var_'$v`\" = yes"; then
++      AC_MSG_RESULT(yes)
++      n=HAVE_`echo $v | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
++      AC_DEFINE_UNQUOTED($n)
++    else
++      AC_MSG_RESULT(no)
++    fi
++  done
++
++  # special check for _system_configuration because AIX <4.3.2 do not
++  # contain the `physmem' member.
++  AC_MSG_CHECKING([for external symbol _system_configuration])
++  AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[#include <sys/systemcfg.h>]],
++			[[double x = _system_configuration.physmem;]])],
++    [AC_MSG_RESULT([yes])
++    AC_DEFINE(HAVE__SYSTEM_CONFIGURATION, 1,
++	      [Define if you have the _system_configuration variable.])],
++    [AC_MSG_RESULT([no])])
++
++  AC_CHECK_FUNCS($checkfuncs)
++  AC_CHECK_DECLS([basename, ffs, asprintf, vasprintf, snprintf, vsnprintf])
++  AC_CHECK_DECLS([calloc, getenv, getopt, malloc, realloc, sbrk])
++  AC_CHECK_DECLS([strtol, strtoul, strtoll, strtoull])
++  AC_CHECK_DECLS([strverscmp])
++fi
++
++# Determine x_ada_cflags
++case $host in
++  hppa*) x_ada_cflags=-mdisable-indexing ;;
++  *) x_ada_cflags= ;;
++esac
++AC_SUBST([x_ada_cflags])
++
++# Determine what to build for 'gnattools'
++if test $build = $target ; then
++  # Note that build=target is almost certainly the wrong test; FIXME
++  default_gnattools_target="gnattools-native"
++else
++  default_gnattools_target="gnattools-cross"
++fi
++AC_SUBST([default_gnattools_target])
++
++# Target-specific stuff (defaults)
++TOOLS_TARGET_PAIRS=
++AC_SUBST(TOOLS_TARGET_PAIRS)
++
++# Per-target case statement
++# ---/----------------------
++case "${target}" in
++  alpha*-dec-vx*) # Unlike all other Vxworks
++    ;;
++  m68k*-wrs-vx* \
++  | powerpc*-wrs-vxworks \
++  | sparc*-wrs-vx* \
++  | *86-wrs-vxworks \
++  | xscale*-wrs-vx* \
++  | xscale*-wrs-coff \
++  | mips*-wrs-vx*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-vxworks.adb"
++    ;;
++  sparc-sun-solaris*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"
++    ;;
++  *86-*-solaris2*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-solaris.adb"
++    ;;
++  *86-*-linux* \
++  | aarch64*-*-linux* \
++  | arm*-*-linux* \
++  | powerpc*-*-linux* \
++  | *ia64-*-linux* \
++  | alpha*-*-linux* \
++  | sparc*-*-linux* \
++  | hppa*-*-linux* \
++  | mips*-*-linux* \
++  | m68k-*-linux \
++  | *x86_64-*-linux* \
++  | *86-*-kfreebsd*-gnu \
++  | *86-*-gnu \
++  | *x86_64-*-kfreebsd*-gnu )
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb"
++    ;;
++  s390*-*-linux*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb"
++    ;;
++  *86-*-freebsd*)
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb"
++    ;;
++  mips-sgi-irix*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-irix.adb"
++    ;;
++  hppa*-hp-hpux10*) # Unlike hpux11
++    ;;
++  hppa*-hp-hpux11*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-hpux.adb"
++    ;;
++  *-ibm-aix*)
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-specific-aix.adb"
++    ;;
++  alpha*-dec-osf*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-tru64.adb"
++    ;;
++  alpha*-dec-vms* | alpha*-dec-openvms* | alpha*-dec-vms* \
++  | alpha*-hp-vms* | alpha*-hp-openvms* | alpha*-hp-vms*)
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-specific-vms-alpha.adb \
++    symbols.adb<symbols-vms.adb \
++    symbols-processing.adb<symbols-processing-vms-alpha.adb"
++    ;;
++  ia64*-dec-vms* | ia64*-dec-openvms* | ia64*-dec-vms* \
++  | ia64*-hp-vms* | ia64*-hp-openvms* | ia64*-hp-vms*)
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-vms-ia64.adb \
++    symbols.adb<symbols-vms.adb \
++    symbols-processing.adb<symbols-processing-vms-ia64.adb"
++    ;;
++  *-*-cygwin32* | *-*-mingw32* | *-*-pe)
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-specific-mingw.adb"
++    ;;
++  powerpc-*-darwin*)
++    TOOLS_TARGET_PAIRS="mlib-tgt-specific.adb<mlib-tgt-specific-darwin.adb"
++    ;;
++  *-*-lynxos)
++    TOOLS_TARGET_PAIRS="\
++    mlib-tgt-specific.adb<mlib-tgt-specific-lynxos.adb"
++    ;;
++esac
++
++# Output: create a Makefile.
++AC_CONFIG_FILES([Makefile])
++
++AC_OUTPUT
+Index: b/src/Makefile.in
+===================================================================
+--- a/src/Makefile.in
++++ b/src/Makefile.in
+@@ -977,6 +977,7 @@ configure-target:  \
+     maybe-configure-target-rda \
+     maybe-configure-target-libada \
+     maybe-configure-target-libgnatvsn \
++    maybe-configure-target-libgnatprj \
+     maybe-configure-target-libgomp \
+     maybe-configure-target-libitm \
+     maybe-configure-target-libatomic
+@@ -1146,6 +1147,7 @@ all-target: maybe-all-target-boehm-gc
+ all-target: maybe-all-target-rda
+ all-target: maybe-all-target-libada
+ all-target: maybe-all-target-libgnatvsn
++all-target: maybe-all-target-libgnatprj
+ @if target-libgomp-no-bootstrap
+ all-target: maybe-all-target-libgomp
+ @endif target-libgomp-no-bootstrap
+@@ -1242,6 +1244,7 @@ info-target: maybe-info-target-boehm-gc
+ info-target: maybe-info-target-rda
+ info-target: maybe-info-target-libada
+ info-target: maybe-info-target-libgnatvsn
++info-target: maybe-info-target-libgnatprj
+ info-target: maybe-info-target-libgomp
+ info-target: maybe-info-target-libitm
+ info-target: maybe-info-target-libatomic
+@@ -1331,6 +1334,7 @@ dvi-target: maybe-dvi-target-boehm-gc
+ dvi-target: maybe-dvi-target-rda
+ dvi-target: maybe-dvi-target-libada
+ dvi-target: maybe-dvi-target-libgnatvsn
++dvi-target: maybe-dvi-target-libgnatprj
+ dvi-target: maybe-dvi-target-libgomp
+ dvi-target: maybe-dvi-target-libitm
+ dvi-target: maybe-dvi-target-libatomic
+@@ -1420,6 +1424,7 @@ pdf-target: maybe-pdf-target-boehm-gc
+ pdf-target: maybe-pdf-target-rda
+ pdf-target: maybe-pdf-target-libada
+ pdf-target: maybe-pdf-target-libgnatvsn
++pdf-target: maybe-pdf-target-libgnatprj
+ pdf-target: maybe-pdf-target-libgomp
+ pdf-target: maybe-pdf-target-libitm
+ pdf-target: maybe-pdf-target-libatomic
+@@ -1509,6 +1514,7 @@ html-target: maybe-html-target-boehm-gc
+ html-target: maybe-html-target-rda
+ html-target: maybe-html-target-libada
+ html-target: maybe-html-target-libgnatvsn
++html-target: maybe-html-target-libgnatprj
+ html-target: maybe-html-target-libgomp
+ html-target: maybe-html-target-libitm
+ html-target: maybe-html-target-libatomic
+@@ -1598,6 +1604,7 @@ TAGS-target: maybe-TAGS-target-boehm-gc
+ TAGS-target: maybe-TAGS-target-rda
+ TAGS-target: maybe-TAGS-target-libada
+ TAGS-target: maybe-TAGS-target-libgnatvsn
++TAGS-target: maybe-TAGS-target-libgnatprj
+ TAGS-target: maybe-TAGS-target-libgomp
+ TAGS-target: maybe-TAGS-target-libitm
+ TAGS-target: maybe-TAGS-target-libatomic
+@@ -1687,6 +1694,7 @@ install-info-target: maybe-install-info-
+ install-info-target: maybe-install-info-target-rda
+ install-info-target: maybe-install-info-target-libada
+ install-info-target: maybe-install-info-target-libgnatvsn
++install-info-target: maybe-install-info-target-libgnatprj
+ install-info-target: maybe-install-info-target-libgomp
+ install-info-target: maybe-install-info-target-libitm
+ install-info-target: maybe-install-info-target-libatomic
+@@ -1776,6 +1784,7 @@ install-pdf-target: maybe-install-pdf-ta
+ install-pdf-target: maybe-install-pdf-target-rda
+ install-pdf-target: maybe-install-pdf-target-libada
+ install-pdf-target: maybe-install-pdf-target-libgnatvsn
++install-pdf-target: maybe-install-pdf-target-libgnatprj
+ install-pdf-target: maybe-install-pdf-target-libgomp
+ install-pdf-target: maybe-install-pdf-target-libitm
+ install-pdf-target: maybe-install-pdf-target-libatomic
+@@ -1865,6 +1874,7 @@ install-html-target: maybe-install-html-
+ install-html-target: maybe-install-html-target-rda
+ install-html-target: maybe-install-html-target-libada
+ install-html-target: maybe-install-html-target-libgnatvsn
++install-html-target: maybe-install-html-target-libgnatprj
+ install-html-target: maybe-install-html-target-libgomp
+ install-html-target: maybe-install-html-target-libitm
+ install-html-target: maybe-install-html-target-libatomic
+@@ -1954,6 +1964,7 @@ installcheck-target: maybe-installcheck-
+ installcheck-target: maybe-installcheck-target-rda
+ installcheck-target: maybe-installcheck-target-libada
+ installcheck-target: maybe-installcheck-target-libgnatvsn
++installcheck-target: maybe-installcheck-target-libgnatprj
+ installcheck-target: maybe-installcheck-target-libgomp
+ installcheck-target: maybe-installcheck-target-libitm
+ installcheck-target: maybe-installcheck-target-libatomic
+@@ -2043,6 +2054,7 @@ mostlyclean-target: maybe-mostlyclean-ta
+ mostlyclean-target: maybe-mostlyclean-target-rda
+ mostlyclean-target: maybe-mostlyclean-target-libada
+ mostlyclean-target: maybe-mostlyclean-target-libgnatvsn
++mostlyclean-target: maybe-mostlyclean-target-libgnatprj
+ mostlyclean-target: maybe-mostlyclean-target-libgomp
+ mostlyclean-target: maybe-mostlyclean-target-libitm
+ mostlyclean-target: maybe-mostlyclean-target-libatomic
+@@ -2132,6 +2144,7 @@ clean-target: maybe-clean-target-boehm-g
+ clean-target: maybe-clean-target-rda
+ clean-target: maybe-clean-target-libada
+ clean-target: maybe-clean-target-libgnatvsn
++clean-target: maybe-clean-target-libgnatprj
+ clean-target: maybe-clean-target-libgomp
+ clean-target: maybe-clean-target-libitm
+ clean-target: maybe-clean-target-libatomic
+@@ -2221,6 +2234,7 @@ distclean-target: maybe-distclean-target
+ distclean-target: maybe-distclean-target-rda
+ distclean-target: maybe-distclean-target-libada
+ distclean-target: maybe-distclean-target-libgnatvsn
++distclean-target: maybe-distclean-target-libgnatprj
+ distclean-target: maybe-distclean-target-libgomp
+ distclean-target: maybe-distclean-target-libitm
+ distclean-target: maybe-distclean-target-libatomic
+@@ -2310,6 +2324,7 @@ maintainer-clean-target: maybe-maintaine
+ maintainer-clean-target: maybe-maintainer-clean-target-rda
+ maintainer-clean-target: maybe-maintainer-clean-target-libada
+ maintainer-clean-target: maybe-maintainer-clean-target-libgnatvsn
++maintainer-clean-target: maybe-maintainer-clean-target-libgnatprj
+ maintainer-clean-target: maybe-maintainer-clean-target-libgomp
+ maintainer-clean-target: maybe-maintainer-clean-target-libitm
+ maintainer-clean-target: maybe-maintainer-clean-target-libatomic
+@@ -2455,6 +2470,7 @@ check-target:  \
+     maybe-check-target-rda \
+     maybe-check-target-libada \
+     maybe-check-target-libgnatvsn \
++    maybe-check-target-libgnatprj \
+     maybe-check-target-libgomp \
+     maybe-check-target-libitm \
+     maybe-check-target-libatomic
+@@ -2640,6 +2656,7 @@ install-target:  \
+     maybe-install-target-rda \
+     maybe-install-target-libada \
+     maybe-install-target-libgnatvsn \
++    maybe-install-target-libgnatprj \
+     maybe-install-target-libgomp \
+     maybe-install-target-libitm \
+     maybe-install-target-libatomic
+@@ -2749,6 +2766,7 @@ install-strip-target:  \
+     maybe-install-strip-target-rda \
+     maybe-install-strip-target-libada \
+     maybe-install-strip-target-libgnatvsn \
++    maybe-install-strip-target-libgnatprj \
+     maybe-install-strip-target-libgomp \
+     maybe-install-strip-target-libitm \
+     maybe-install-strip-target-libatomic
+@@ -46415,6 +46433,362 @@ maintainer-clean-target-libgnatvsn:
+ 
+ 
+ 
++.PHONY: configure-target-libgnatprj maybe-configure-target-libgnatprj
++maybe-configure-target-libgnatprj:
++@if gcc-bootstrap
++configure-target-libgnatprj: stage_current
++@endif gcc-bootstrap
++@if target-libgnatprj
++maybe-configure-target-libgnatprj: configure-target-libgnatprj
++configure-target-libgnatprj: 
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	echo "Checking multilib configuration for libgnatprj..."; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatprj ; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libgnatprj/multilib.tmp 2> /dev/null ; \
++	if test -r $(TARGET_SUBDIR)/libgnatprj/multilib.out; then \
++	  if cmp -s $(TARGET_SUBDIR)/libgnatprj/multilib.tmp $(TARGET_SUBDIR)/libgnatprj/multilib.out; then \
++	    rm -f $(TARGET_SUBDIR)/libgnatprj/multilib.tmp; \
++	  else \
++	    rm -f $(TARGET_SUBDIR)/libgnatprj/Makefile; \
++	    mv $(TARGET_SUBDIR)/libgnatprj/multilib.tmp $(TARGET_SUBDIR)/libgnatprj/multilib.out; \
++	  fi; \
++	else \
++	  mv $(TARGET_SUBDIR)/libgnatprj/multilib.tmp $(TARGET_SUBDIR)/libgnatprj/multilib.out; \
++	fi; \
++	test ! -f $(TARGET_SUBDIR)/libgnatprj/Makefile || exit 0; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatprj ; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	echo Configuring in $(TARGET_SUBDIR)/libgnatprj; \
++	cd "$(TARGET_SUBDIR)/libgnatprj" || exit 1; \
++	case $(srcdir) in \
++	  /* | [A-Za-z]:[\\/]*) topdir=$(srcdir) ;; \
++	  *) topdir=`echo $(TARGET_SUBDIR)/libgnatprj/ | \
++		sed -e 's,\./,,g' -e 's,[^/]*/,../,g' `$(srcdir) ;; \
++	esac; \
++	module_srcdir=libgnatprj; \
++	rm -f no-such-file || : ; \
++	CONFIG_SITE=no-such-file $(SHELL) \
++	  $$s/$$module_srcdir/configure \
++	  --srcdir=$${topdir}/$$module_srcdir \
++	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
++	  --target=${target_alias}  \
++	  || exit 1
++@endif target-libgnatprj
++
++
++
++
++
++.PHONY: all-target-libgnatprj maybe-all-target-libgnatprj
++maybe-all-target-libgnatprj:
++@if gcc-bootstrap
++all-target-libgnatprj: stage_current
++@endif gcc-bootstrap
++@if target-libgnatprj
++TARGET-target-libgnatprj=all
++maybe-all-target-libgnatprj: all-target-libgnatprj
++all-target-libgnatprj: configure-target-libgnatprj
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) $(EXTRA_TARGET_FLAGS)   \
++		$(TARGET-target-libgnatprj))
++@endif target-libgnatprj
++
++
++
++
++
++.PHONY: check-target-libgnatprj maybe-check-target-libgnatprj
++maybe-check-target-libgnatprj:
++@if target-libgnatprj
++maybe-check-target-libgnatprj: check-target-libgnatprj
++
++# Dummy target for uncheckable module.
++check-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: install-target-libgnatprj maybe-install-target-libgnatprj
++maybe-install-target-libgnatprj:
++@if target-libgnatprj
++maybe-install-target-libgnatprj: install-target-libgnatprj
++
++install-target-libgnatprj: installdirs
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install)
++
++@endif target-libgnatprj
++
++.PHONY: install-strip-target-libgnatprj maybe-install-strip-target-libgnatprj
++maybe-install-strip-target-libgnatprj:
++@if target-libgnatprj
++maybe-install-strip-target-libgnatprj: install-strip-target-libgnatprj
++
++install-strip-target-libgnatprj: installdirs
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install-strip)
++
++@endif target-libgnatprj
++
++# Other targets (info, dvi, pdf, etc.)
++
++.PHONY: maybe-info-target-libgnatprj info-target-libgnatprj
++maybe-info-target-libgnatprj:
++@if target-libgnatprj
++maybe-info-target-libgnatprj: info-target-libgnatprj
++
++# libgnatprj doesn't support info.
++info-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: maybe-dvi-target-libgnatprj dvi-target-libgnatprj
++maybe-dvi-target-libgnatprj:
++@if target-libgnatprj
++maybe-dvi-target-libgnatprj: dvi-target-libgnatprj
++
++# libgnatprj doesn't support dvi.
++dvi-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: maybe-pdf-target-libgnatprj pdf-target-libgnatprj
++maybe-pdf-target-libgnatprj:
++@if target-libgnatprj
++maybe-pdf-target-libgnatprj: pdf-target-libgnatprj
++
++pdf-target-libgnatprj: \
++    configure-target-libgnatprj 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           pdf) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++.PHONY: maybe-html-target-libgnatprj html-target-libgnatprj
++maybe-html-target-libgnatprj:
++@if target-libgnatprj
++maybe-html-target-libgnatprj: html-target-libgnatprj
++
++# libgnatprj doesn't support html.
++html-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: maybe-TAGS-target-libgnatprj TAGS-target-libgnatprj
++maybe-TAGS-target-libgnatprj:
++@if target-libgnatprj
++maybe-TAGS-target-libgnatprj: TAGS-target-libgnatprj
++
++# libgnatprj doesn't support TAGS.
++TAGS-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: maybe-install-info-target-libgnatprj install-info-target-libgnatprj
++maybe-install-info-target-libgnatprj:
++@if target-libgnatprj
++maybe-install-info-target-libgnatprj: install-info-target-libgnatprj
++
++# libgnatprj doesn't support install-info.
++install-info-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: maybe-install-pdf-target-libgnatprj install-pdf-target-libgnatprj
++maybe-install-pdf-target-libgnatprj:
++@if target-libgnatprj
++maybe-install-pdf-target-libgnatprj: install-pdf-target-libgnatprj
++
++install-pdf-target-libgnatprj: \
++    configure-target-libgnatprj \
++    pdf-target-libgnatprj 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-pdf) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++.PHONY: maybe-install-html-target-libgnatprj install-html-target-libgnatprj
++maybe-install-html-target-libgnatprj:
++@if target-libgnatprj
++maybe-install-html-target-libgnatprj: install-html-target-libgnatprj
++
++install-html-target-libgnatprj: \
++    configure-target-libgnatprj \
++    html-target-libgnatprj 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-html) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++.PHONY: maybe-installcheck-target-libgnatprj installcheck-target-libgnatprj
++maybe-installcheck-target-libgnatprj:
++@if target-libgnatprj
++maybe-installcheck-target-libgnatprj: installcheck-target-libgnatprj
++
++# libgnatprj doesn't support installcheck.
++installcheck-target-libgnatprj:
++
++@endif target-libgnatprj
++
++.PHONY: maybe-mostlyclean-target-libgnatprj mostlyclean-target-libgnatprj
++maybe-mostlyclean-target-libgnatprj:
++@if target-libgnatprj
++maybe-mostlyclean-target-libgnatprj: mostlyclean-target-libgnatprj
++
++mostlyclean-target-libgnatprj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           mostlyclean) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++.PHONY: maybe-clean-target-libgnatprj clean-target-libgnatprj
++maybe-clean-target-libgnatprj:
++@if target-libgnatprj
++maybe-clean-target-libgnatprj: clean-target-libgnatprj
++
++clean-target-libgnatprj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing clean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           clean) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++.PHONY: maybe-distclean-target-libgnatprj distclean-target-libgnatprj
++maybe-distclean-target-libgnatprj:
++@if target-libgnatprj
++maybe-distclean-target-libgnatprj: distclean-target-libgnatprj
++
++distclean-target-libgnatprj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           distclean) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++.PHONY: maybe-maintainer-clean-target-libgnatprj maintainer-clean-target-libgnatprj
++maybe-maintainer-clean-target-libgnatprj:
++@if target-libgnatprj
++maybe-maintainer-clean-target-libgnatprj: maintainer-clean-target-libgnatprj
++
++maintainer-clean-target-libgnatprj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatprj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           maintainer-clean) \
++	  || exit 1
++
++@endif target-libgnatprj
++
++
++
++
++
+ .PHONY: configure-target-libgomp maybe-configure-target-libgomp
+ maybe-configure-target-libgomp:
+ @if gcc-bootstrap
+@@ -50620,6 +50994,7 @@ configure-target-boehm-gc: stage_last
+ configure-target-rda: stage_last
+ configure-target-libada: stage_last
+ configure-target-libgnatvsn: stage_last
++configure-target-libgnatprj: stage_last
+ configure-stage1-target-libgomp: maybe-all-stage1-gcc
+ configure-stage2-target-libgomp: maybe-all-stage2-gcc
+ configure-stage3-target-libgomp: maybe-all-stage3-gcc
+@@ -50656,6 +51031,7 @@ configure-target-boehm-gc: maybe-all-gcc
+ configure-target-rda: maybe-all-gcc
+ configure-target-libada: maybe-all-gcc
+ configure-target-libgnatvsn: maybe-all-gcc
++configure-target-libgnatprj: maybe-all-gcc
+ configure-target-libgomp: maybe-all-gcc
+ configure-target-libitm: maybe-all-gcc
+ configure-target-libatomic: maybe-all-gcc
+@@ -51030,8 +51406,12 @@ all-stagefeedback-fixincludes: maybe-all
+ all-target-libada: maybe-all-gcc
+ all-gnattools: maybe-all-target-libada
+ all-gnattools: maybe-all-target-libgnatvsn
++all-gnattools: maybe-all-target-libgnatprj
+ all-target-libgnatvsn: maybe-all-target-libada
++all-target-libgnatprj: maybe-all-target-libgnatvsn
++all-target-libgnatprj: maybe-all-target-libiberty
+ all-gnattools: maybe-all-target-libstdc++-v3
++all-target-libgnatvsn: maybe-all-target-libstdc++-v3
+ all-lto-plugin: maybe-all-libiberty
+ 
+ all-stage1-lto-plugin: maybe-all-stage1-libiberty
+@@ -51628,6 +52008,7 @@ configure-target-boehm-gc: maybe-all-tar
+ configure-target-rda: maybe-all-target-libgcc
+ configure-target-libada: maybe-all-target-libgcc
+ configure-target-libgnatvsn: maybe-all-target-libgcc
++configure-target-libgnatprj: maybe-all-target-libgcc
+ configure-target-libgomp: maybe-all-target-libgcc
+ configure-target-libitm: maybe-all-target-libgcc
+ configure-target-libatomic: maybe-all-target-libgcc
+@@ -51684,6 +52065,8 @@ configure-target-libada: maybe-all-targe
+ 
+ configure-target-libgnatvsn: maybe-all-target-newlib maybe-all-target-libgloss
+ 
++configure-target-libgnatprj: maybe-all-target-newlib maybe-all-target-libgloss
++
+ configure-target-libgomp: maybe-all-target-newlib maybe-all-target-libgloss
+ 
+ configure-target-libitm: maybe-all-target-newlib maybe-all-target-libgloss
+Index: b/src/libgnatprj/config.in
+===================================================================
+--- /dev/null
++++ b/src/libgnatprj/config.in
+@@ -0,0 +1,565 @@
++/* config.in.  Generated from configure.ac by autoheader.  */
++
++/* Define if building universal (internal helper macro) */
++#undef AC_APPLE_UNIVERSAL_BUILD
++
++/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
++   This function is required for alloca.c support on those systems. */
++#undef CRAY_STACKSEG_END
++
++/* Define to 1 if you have the <alloca.h> header file. */
++#undef HAVE_ALLOCA_H
++
++/* Define to 1 if you have the `asprintf' function. */
++#undef HAVE_ASPRINTF
++
++/* Define to 1 if you have the `atexit' function. */
++#undef HAVE_ATEXIT
++
++/* Define to 1 if you have the `basename' function. */
++#undef HAVE_BASENAME
++
++/* Define to 1 if you have the `bcmp' function. */
++#undef HAVE_BCMP
++
++/* Define to 1 if you have the `bcopy' function. */
++#undef HAVE_BCOPY
++
++/* Define to 1 if you have the `bsearch' function. */
++#undef HAVE_BSEARCH
++
++/* Define to 1 if you have the `bzero' function. */
++#undef HAVE_BZERO
++
++/* Define to 1 if you have the `calloc' function. */
++#undef HAVE_CALLOC
++
++/* Define to 1 if you have the `canonicalize_file_name' function. */
++#undef HAVE_CANONICALIZE_FILE_NAME
++
++/* Define to 1 if you have the `clock' function. */
++#undef HAVE_CLOCK
++
++/* Define to 1 if you have the declaration of `asprintf', and to 0 if you
++   don't. */
++#undef HAVE_DECL_ASPRINTF
++
++/* Define to 1 if you have the declaration of `basename(char *)', and to 0 if
++   you don't. */
++#undef HAVE_DECL_BASENAME
++
++/* Define to 1 if you have the declaration of `calloc', and to 0 if you don't.
++   */
++#undef HAVE_DECL_CALLOC
++
++/* Define to 1 if you have the declaration of `ffs', and to 0 if you don't. */
++#undef HAVE_DECL_FFS
++
++/* Define to 1 if you have the declaration of `getenv', and to 0 if you don't.
++   */
++#undef HAVE_DECL_GETENV
++
++/* Define to 1 if you have the declaration of `getopt', and to 0 if you don't.
++   */
++#undef HAVE_DECL_GETOPT
++
++/* Define to 1 if you have the declaration of `malloc', and to 0 if you don't.
++   */
++#undef HAVE_DECL_MALLOC
++
++/* Define to 1 if you have the declaration of `realloc', and to 0 if you
++   don't. */
++#undef HAVE_DECL_REALLOC
++
++/* Define to 1 if you have the declaration of `sbrk', and to 0 if you don't.
++   */
++#undef HAVE_DECL_SBRK
++
++/* Define to 1 if you have the declaration of `snprintf', and to 0 if you
++   don't. */
++#undef HAVE_DECL_SNPRINTF
++
++/* Define to 1 if you have the declaration of `strtol', and to 0 if you don't.
++   */
++#undef HAVE_DECL_STRTOL
++
++/* Define to 1 if you have the declaration of `strtoll', and to 0 if you
++   don't. */
++#undef HAVE_DECL_STRTOLL
++
++/* Define to 1 if you have the declaration of `strtoul', and to 0 if you
++   don't. */
++#undef HAVE_DECL_STRTOUL
++
++/* Define to 1 if you have the declaration of `strtoull', and to 0 if you
++   don't. */
++#undef HAVE_DECL_STRTOULL
++
++/* Define to 1 if you have the declaration of `strverscmp', and to 0 if you
++   don't. */
++#undef HAVE_DECL_STRVERSCMP
++
++/* Define to 1 if you have the declaration of `vasprintf', and to 0 if you
++   don't. */
++#undef HAVE_DECL_VASPRINTF
++
++/* Define to 1 if you have the declaration of `vsnprintf', and to 0 if you
++   don't. */
++#undef HAVE_DECL_VSNPRINTF
++
++/* Define to 1 if you have the `dup3' function. */
++#undef HAVE_DUP3
++
++/* Define to 1 if you have the <fcntl.h> header file. */
++#undef HAVE_FCNTL_H
++
++/* Define to 1 if you have the `ffs' function. */
++#undef HAVE_FFS
++
++/* Define to 1 if you have the `fork' function. */
++#undef HAVE_FORK
++
++/* Define to 1 if you have the `getcwd' function. */
++#undef HAVE_GETCWD
++
++/* Define to 1 if you have the `getpagesize' function. */
++#undef HAVE_GETPAGESIZE
++
++/* Define to 1 if you have the `getrlimit' function. */
++#undef HAVE_GETRLIMIT
++
++/* Define to 1 if you have the `getrusage' function. */
++#undef HAVE_GETRUSAGE
++
++/* Define to 1 if you have the `getsysinfo' function. */
++#undef HAVE_GETSYSINFO
++
++/* Define to 1 if you have the `gettimeofday' function. */
++#undef HAVE_GETTIMEOFDAY
++
++/* Define to 1 if you have the `index' function. */
++#undef HAVE_INDEX
++
++/* Define to 1 if you have the `insque' function. */
++#undef HAVE_INSQUE
++
++/* Define to 1 if the system has the type `intptr_t'. */
++#undef HAVE_INTPTR_T
++
++/* Define to 1 if you have the <inttypes.h> header file. */
++#undef HAVE_INTTYPES_H
++
++/* Define to 1 if you have the <limits.h> header file. */
++#undef HAVE_LIMITS_H
++
++/* Define if you have the `long long' type. */
++#undef HAVE_LONG_LONG
++
++/* Define to 1 if you have the <machine/hal_sysinfo.h> header file. */
++#undef HAVE_MACHINE_HAL_SYSINFO_H
++
++/* Define to 1 if you have the <malloc.h> header file. */
++#undef HAVE_MALLOC_H
++
++/* Define to 1 if you have the `memchr' function. */
++#undef HAVE_MEMCHR
++
++/* Define to 1 if you have the `memcmp' function. */
++#undef HAVE_MEMCMP
++
++/* Define to 1 if you have the `memcpy' function. */
++#undef HAVE_MEMCPY
++
++/* Define to 1 if you have the `memmem' function. */
++#undef HAVE_MEMMEM
++
++/* Define to 1 if you have the `memmove' function. */
++#undef HAVE_MEMMOVE
++
++/* Define to 1 if you have the <memory.h> header file. */
++#undef HAVE_MEMORY_H
++
++/* Define to 1 if you have the `memset' function. */
++#undef HAVE_MEMSET
++
++/* Define to 1 if you have the `mkstemps' function. */
++#undef HAVE_MKSTEMPS
++
++/* Define to 1 if you have a working `mmap' system call. */
++#undef HAVE_MMAP
++
++/* Define to 1 if you have the `on_exit' function. */
++#undef HAVE_ON_EXIT
++
++/* Define to 1 if you have the <process.h> header file. */
++#undef HAVE_PROCESS_H
++
++/* Define to 1 if you have the `psignal' function. */
++#undef HAVE_PSIGNAL
++
++/* Define to 1 if you have the `pstat_getdynamic' function. */
++#undef HAVE_PSTAT_GETDYNAMIC
++
++/* Define to 1 if you have the `pstat_getstatic' function. */
++#undef HAVE_PSTAT_GETSTATIC
++
++/* Define to 1 if you have the `putenv' function. */
++#undef HAVE_PUTENV
++
++/* Define to 1 if you have the `random' function. */
++#undef HAVE_RANDOM
++
++/* Define to 1 if you have the `realpath' function. */
++#undef HAVE_REALPATH
++
++/* Define to 1 if you have the `rename' function. */
++#undef HAVE_RENAME
++
++/* Define to 1 if you have the `rindex' function. */
++#undef HAVE_RINDEX
++
++/* Define to 1 if you have the `sbrk' function. */
++#undef HAVE_SBRK
++
++/* Define to 1 if you have the `setenv' function. */
++#undef HAVE_SETENV
++
++/* Define to 1 if you have the `setproctitle' function. */
++#undef HAVE_SETPROCTITLE
++
++/* Define to 1 if you have the `setrlimit' function. */
++#undef HAVE_SETRLIMIT
++
++/* Define to 1 if you have the `sigsetmask' function. */
++#undef HAVE_SIGSETMASK
++
++/* Define to 1 if you have the `snprintf' function. */
++#undef HAVE_SNPRINTF
++
++/* Define to 1 if you have the `spawnve' function. */
++#undef HAVE_SPAWNVE
++
++/* Define to 1 if you have the `spawnvpe' function. */
++#undef HAVE_SPAWNVPE
++
++/* Define to 1 if you have the <stdint.h> header file. */
++#undef HAVE_STDINT_H
++
++/* Define to 1 if you have the <stdio_ext.h> header file. */
++#undef HAVE_STDIO_EXT_H
++
++/* Define to 1 if you have the <stdlib.h> header file. */
++#undef HAVE_STDLIB_H
++
++/* Define to 1 if you have the `stpcpy' function. */
++#undef HAVE_STPCPY
++
++/* Define to 1 if you have the `stpncpy' function. */
++#undef HAVE_STPNCPY
++
++/* Define to 1 if you have the `strcasecmp' function. */
++#undef HAVE_STRCASECMP
++
++/* Define to 1 if you have the `strchr' function. */
++#undef HAVE_STRCHR
++
++/* Define to 1 if you have the `strdup' function. */
++#undef HAVE_STRDUP
++
++/* Define to 1 if you have the `strerror' function. */
++#undef HAVE_STRERROR
++
++/* Define to 1 if you have the <strings.h> header file. */
++#undef HAVE_STRINGS_H
++
++/* Define to 1 if you have the <string.h> header file. */
++#undef HAVE_STRING_H
++
++/* Define to 1 if you have the `strncasecmp' function. */
++#undef HAVE_STRNCASECMP
++
++/* Define to 1 if you have the `strndup' function. */
++#undef HAVE_STRNDUP
++
++/* Define to 1 if you have the `strnlen' function. */
++#undef HAVE_STRNLEN
++
++/* Define to 1 if you have the `strrchr' function. */
++#undef HAVE_STRRCHR
++
++/* Define to 1 if you have the `strsignal' function. */
++#undef HAVE_STRSIGNAL
++
++/* Define to 1 if you have the `strstr' function. */
++#undef HAVE_STRSTR
++
++/* Define to 1 if you have the `strtod' function. */
++#undef HAVE_STRTOD
++
++/* Define to 1 if you have the `strtol' function. */
++#undef HAVE_STRTOL
++
++/* Define to 1 if you have the `strtoll' function. */
++#undef HAVE_STRTOLL
++
++/* Define to 1 if you have the `strtoul' function. */
++#undef HAVE_STRTOUL
++
++/* Define to 1 if you have the `strtoull' function. */
++#undef HAVE_STRTOULL
++
++/* Define to 1 if you have the `strverscmp' function. */
++#undef HAVE_STRVERSCMP
++
++/* Define to 1 if you have the `sysconf' function. */
++#undef HAVE_SYSCONF
++
++/* Define to 1 if you have the `sysctl' function. */
++#undef HAVE_SYSCTL
++
++/* Define to 1 if you have the `sysmp' function. */
++#undef HAVE_SYSMP
++
++/* Define if you have the sys_errlist variable. */
++#undef HAVE_SYS_ERRLIST
++
++/* Define to 1 if you have the <sys/file.h> header file. */
++#undef HAVE_SYS_FILE_H
++
++/* Define to 1 if you have the <sys/mman.h> header file. */
++#undef HAVE_SYS_MMAN_H
++
++/* Define if you have the sys_nerr variable. */
++#undef HAVE_SYS_NERR
++
++/* Define to 1 if you have the <sys/param.h> header file. */
++#undef HAVE_SYS_PARAM_H
++
++/* Define to 1 if you have the <sys/prctl.h> header file. */
++#undef HAVE_SYS_PRCTL_H
++
++/* Define to 1 if you have the <sys/pstat.h> header file. */
++#undef HAVE_SYS_PSTAT_H
++
++/* Define to 1 if you have the <sys/resource.h> header file. */
++#undef HAVE_SYS_RESOURCE_H
++
++/* Define if you have the sys_siglist variable. */
++#undef HAVE_SYS_SIGLIST
++
++/* Define to 1 if you have the <sys/stat.h> header file. */
++#undef HAVE_SYS_STAT_H
++
++/* Define to 1 if you have the <sys/sysctl.h> header file. */
++#undef HAVE_SYS_SYSCTL_H
++
++/* Define to 1 if you have the <sys/sysinfo.h> header file. */
++#undef HAVE_SYS_SYSINFO_H
++
++/* Define to 1 if you have the <sys/sysmp.h> header file. */
++#undef HAVE_SYS_SYSMP_H
++
++/* Define to 1 if you have the <sys/systemcfg.h> header file. */
++#undef HAVE_SYS_SYSTEMCFG_H
++
++/* Define to 1 if you have the <sys/table.h> header file. */
++#undef HAVE_SYS_TABLE_H
++
++/* Define to 1 if you have the <sys/time.h> header file. */
++#undef HAVE_SYS_TIME_H
++
++/* Define to 1 if you have the <sys/types.h> header file. */
++#undef HAVE_SYS_TYPES_H
++
++/* Define to 1 if you have <sys/wait.h> that is POSIX.1 compatible. */
++#undef HAVE_SYS_WAIT_H
++
++/* Define to 1 if you have the `table' function. */
++#undef HAVE_TABLE
++
++/* Define to 1 if you have the `times' function. */
++#undef HAVE_TIMES
++
++/* Define to 1 if you have the <time.h> header file. */
++#undef HAVE_TIME_H
++
++/* Define to 1 if you have the `tmpnam' function. */
++#undef HAVE_TMPNAM
++
++/* Define if you have the \`uintptr_t' type. */
++#undef HAVE_UINTPTR_T
++
++/* Define to 1 if you have the <unistd.h> header file. */
++#undef HAVE_UNISTD_H
++
++/* Define to 1 if you have the `vasprintf' function. */
++#undef HAVE_VASPRINTF
++
++/* Define to 1 if you have the `vfork' function. */
++#undef HAVE_VFORK
++
++/* Define to 1 if you have the <vfork.h> header file. */
++#undef HAVE_VFORK_H
++
++/* Define to 1 if you have the `vfprintf' function. */
++#undef HAVE_VFPRINTF
++
++/* Define to 1 if you have the `vprintf' function. */
++#undef HAVE_VPRINTF
++
++/* Define to 1 if you have the `vsprintf' function. */
++#undef HAVE_VSPRINTF
++
++/* Define to 1 if you have the `wait3' function. */
++#undef HAVE_WAIT3
++
++/* Define to 1 if you have the `wait4' function. */
++#undef HAVE_WAIT4
++
++/* Define to 1 if you have the `waitpid' function. */
++#undef HAVE_WAITPID
++
++/* Define to 1 if `fork' works. */
++#undef HAVE_WORKING_FORK
++
++/* Define to 1 if `vfork' works. */
++#undef HAVE_WORKING_VFORK
++
++/* Define to 1 if you have the `_doprnt' function. */
++#undef HAVE__DOPRNT
++
++/* Define if you have the _system_configuration variable. */
++#undef HAVE__SYSTEM_CONFIGURATION
++
++/* Define to 1 if you have the `__fsetlocking' function. */
++#undef HAVE___FSETLOCKING
++
++/* Define if canonicalize_file_name is not declared in system header files. */
++#undef NEED_DECLARATION_CANONICALIZE_FILE_NAME
++
++/* Define if errno must be declared even when <errno.h> is included. */
++#undef NEED_DECLARATION_ERRNO
++
++/* Define to 1 if your C compiler doesn't accept -c and -o together. */
++#undef NO_MINUS_C_MINUS_O
++
++/* Define to the address where bug reports for this package should be sent. */
++#undef PACKAGE_BUGREPORT
++
++/* Define to the full name of this package. */
++#undef PACKAGE_NAME
++
++/* Define to the full name and version of this package. */
++#undef PACKAGE_STRING
++
++/* Define to the one symbol short name of this package. */
++#undef PACKAGE_TARNAME
++
++/* Define to the home page for this package. */
++#undef PACKAGE_URL
++
++/* Define to the version of this package. */
++#undef PACKAGE_VERSION
++
++/* The size of `int', as computed by sizeof. */
++#undef SIZEOF_INT
++
++/* The size of `long', as computed by sizeof. */
++#undef SIZEOF_LONG
++
++/* The size of `long long', as computed by sizeof. */
++#undef SIZEOF_LONG_LONG
++
++/* The size of `size_t', as computed by sizeof. */
++#undef SIZEOF_SIZE_T
++
++/* Define if you know the direction of stack growth for your system; otherwise
++   it will be automatically deduced at run-time. STACK_DIRECTION > 0 => grows
++   toward higher addresses STACK_DIRECTION < 0 => grows toward lower addresses
++   STACK_DIRECTION = 0 => direction of growth unknown */
++#undef STACK_DIRECTION
++
++/* Define to 1 if you have the ANSI C header files. */
++#undef STDC_HEADERS
++
++/* Define to 1 if you can safely include both <sys/time.h> and <time.h>. */
++#undef TIME_WITH_SYS_TIME
++
++/* Define to an unsigned 64-bit type available in the compiler. */
++#undef UNSIGNED_64BIT_TYPE
++
++/* Enable extensions on AIX 3, Interix.  */
++#ifndef _ALL_SOURCE
++# undef _ALL_SOURCE
++#endif
++/* Enable GNU extensions on systems that have them.  */
++#ifndef _GNU_SOURCE
++# undef _GNU_SOURCE
++#endif
++/* Enable threading extensions on Solaris.  */
++#ifndef _POSIX_PTHREAD_SEMANTICS
++# undef _POSIX_PTHREAD_SEMANTICS
++#endif
++/* Enable extensions on HP NonStop.  */
++#ifndef _TANDEM_SOURCE
++# undef _TANDEM_SOURCE
++#endif
++/* Enable general extensions on Solaris.  */
++#ifndef __EXTENSIONS__
++# undef __EXTENSIONS__
++#endif
++
++
++/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most
++   significant byte first (like Motorola and SPARC, unlike Intel). */
++#if defined AC_APPLE_UNIVERSAL_BUILD
++# if defined __BIG_ENDIAN__
++#  define WORDS_BIGENDIAN 1
++# endif
++#else
++# ifndef WORDS_BIGENDIAN
++#  undef WORDS_BIGENDIAN
++# endif
++#endif
++
++/* Number of bits in a file offset, on hosts where this is settable. */
++#undef _FILE_OFFSET_BITS
++
++/* Define for large files, on AIX-style hosts. */
++#undef _LARGE_FILES
++
++/* Define to 1 if on MINIX. */
++#undef _MINIX
++
++/* Define to 2 if the system does not provide POSIX.1 features except with
++   this defined. */
++#undef _POSIX_1_SOURCE
++
++/* Define to 1 if you need to in order for `stat' and other things to work. */
++#undef _POSIX_SOURCE
++
++/* Define to empty if `const' does not conform to ANSI C. */
++#undef const
++
++/* Define to `__inline__' or `__inline' if that's what the C compiler
++   calls it, or to nothing if 'inline' is not supported under any name.  */
++#ifndef __cplusplus
++#undef inline
++#endif
++
++/* Define to the type of a signed integer type wide enough to hold a pointer,
++   if such a type exists, and if the system does not define it. */
++#undef intptr_t
++
++/* Define to `int' if <sys/types.h> does not define. */
++#undef pid_t
++
++/* Define to `int' if <sys/types.h> does not define. */
++#undef ssize_t
++
++/* Define to the type of an unsigned integer type wide enough to hold a
++   pointer, if such a type exists, and if the system does not define it. */
++#undef uintptr_t
++
++/* Define as `fork' if `vfork' does not work. */
++#undef vfork
+Index: b/src/gcc/prefix.c
+===================================================================
+--- a/src/gcc/prefix.c
++++ b/src/gcc/prefix.c
+@@ -70,7 +70,10 @@ License along with GCC; see the file COP
+ #include <windows.h>
+ #endif
+ #include "prefix.h"
++
++#ifndef USED_FOR_TARGET
+ #include "common/common-target.h"
++#endif
+ 
+ static const char *std_prefix = PREFIX;
+ 
+@@ -284,7 +287,11 @@ update_path (const char *path, const cha
+ 	  && (p != result && IS_DIR_SEPARATOR (p[-1])))
+ 	{
+ 	  *p = 0;
++#ifndef USED_FOR_TARGET
+ 	  if (!targetm_common.always_strip_dotdot
++#else
++	  if (true
++#endif
+ 	      && access (result, X_OK) == 0)
+ 	    {
+ 	      *p = '.';
--- gcc-6-6.4.0.orig/debian/patches/ada-libgnatvsn.diff
+++ gcc-6-6.4.0/debian/patches/ada-libgnatvsn.diff
@@ -0,0 +1,836 @@
+# DP: - Introduce a new shared library named libgnatvsn, containing
+# DP:   common components of GNAT under the GNAT-Modified GPL, for
+# DP:   use in GNAT tools, ASIS, GLADE and GPS.   Link the gnat tools
+# DP:   against this new library.
+
+# This patch seems large, but the hunks in Makefile.in are actually
+# generated from Makefile.def using autogen.
+
+# !!! Must be applied after ada-link-lib.dpatch
+
+Index: b/src/libgnatvsn/configure
+===================================================================
+--- /dev/null
++++ b/src/libgnatvsn/configure
+@@ -0,0 +1,47 @@
++#!/bin/sh
++
++# Minimal configure script for libgnatvsn.  We're only interested in
++# a few parameters.
++
++for arg in $*; do
++    case ${arg} in
++	--build=*)
++	    build=`expr ${arg} : '--build=\(.\+\)'`;;
++	--host=*)
++	    host=`expr ${arg} : '--host=\(.\+\)'`;;
++	--target=*)
++	    target=`expr ${arg} : '--target=\(.\+\)'`;;
++	--prefix=*)
++	    prefix=`expr ${arg} : '--prefix=\(.\+\)'`;;
++	--srcdir=*)
++	    srcdir=`expr ${arg} : '--srcdir=\(.\+\)'`;;
++	--libdir=*)
++	    libdir=`expr ${arg} : '--libdir=\(.\+\)'`;;
++	--with-pkgversion=*)
++	    pkgversion=`expr ${arg} : '--with-pkgversion=\(.\+\)'`;;
++	--with-bugurl=*)
++	    bugurl=`expr ${arg} : '--with-bugurl=\(.\+\)'`;;
++	*)
++	    echo "Warning: ignoring option: ${arg}"
++    esac
++done
++
++echo "build: ${build}" | tee config.log
++echo "host: ${host}" | tee -a config.log
++echo "target: ${target}" | tee -a config.log
++echo "prefix: ${prefix}" | tee -a config.log
++echo "srcdir: ${srcdir}" | tee -a config.log
++echo "libdir: ${libdir}" | tee -a config.log
++echo "pkgversion: ${pkgversion}" | tee -a config.log
++echo "bugurl: ${bugurl}" | tee -a config.log
++
++echo "Creating Makefile..." | tee -a config.log
++sed -e "s,@build@,${build},g" \
++    -e "s,@host@,${host},g" \
++    -e "s,@target@,${target},g" \
++    -e "s,@prefix@,${prefix},g" \
++    -e "s,@srcdir@,${srcdir},g" \
++    -e "s,@libdir@,${libdir},g" \
++    -e "s,@PKGVERSION@,${pkgversion},g" \
++    -e "s,@REPORT_BUGS_TO@,${bugurl},g" \
++    < ${srcdir}/Makefile.in > Makefile
+Index: b/src/libgnatvsn/Makefile.in
+===================================================================
+--- /dev/null
++++ b/src/libgnatvsn/Makefile.in
+@@ -0,0 +1,153 @@
++# Makefile for libgnatvsn.
++#   Copyright (c) 2006 Ludovic Brenta <ludovic@ludovic-brenta.org>
++#
++# This file is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++# 
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++# 
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++# Default target; must be first.
++all: libgnatvsn
++
++.SUFFIXES:
++
++CPUS := $(shell getconf _NPROCESSORS_ONLN)
++LIB_VERSION := $(strip $(shell grep ' Library_Version :' \
++                 @srcdir@/../gcc/ada/gnatvsn.ads | \
++	         sed -e 's/.*"\(.*\)".*/\1/'))
++GCC:=$(CC)
++LIBGNAT_JUST_BUILT := -nostdinc -I../../gcc/ada/rts
++CFLAGS := -g -O2 -gnatn
++FULLVER := $(shell cat @srcdir@/../gcc/FULL-VER)
++DEVPHASE := $(shell cat @srcdir@/../gcc/DEV-PHASE)
++DATESTAMP := $(shell cat @srcdir@/../gcc/DATESTAMP)
++
++# For use in version.c - double quoted strings, with appropriate
++# surrounding punctuation and spaces, and with the datestamp and
++# development phase collapsed to the empty string in release mode
++# (i.e. if DEVPHASE_c is empty).  The space immediately after the
++# comma in the $(if ...) constructs is significant - do not remove it.
++FULLVER_s   := "\"$(FULLVER)\""
++DEVPHASE_s  := "\"$(if $(DEVPHASE), ($(DEVPHASE)))\""
++DATESTAMP_s := "\"$(if $(DEVPHASE), $(DATESTAMP))\""
++PKGVERSION_s:= "\"@PKGVERSION@\""
++BUGURL_s    := "\"@REPORT_BUGS_TO@\""
++
++.PHONY: libgnatvsn install
++libgnatvsn: libgnatvsn.so.$(LIB_VERSION) libgnatvsn.a
++
++VSN_SOURCES := alloc.ads aspects.adb atree.adb casing.adb csets.adb debug.adb einfo.adb \
++elists.adb fname.adb gnatvsn.adb hostparm.ads krunch.adb lib.adb namet.adb \
++nlists.adb opt.adb output.adb repinfo.adb scans.adb sinfo.adb sem_aux.adb \
++sinput.adb stand.adb stringt.adb table.adb tree_in.adb tree_io.adb types.adb \
++uintp.adb uname.adb urealp.adb widechar.adb
++
++VSN_SEPARATES := lib-list.adb lib-sort.adb
++
++VSN_GENERATED_SOURCES := snames.adb
++
++OBJECTS=$(patsubst %.ads,%.o,$(VSN_SOURCES:.adb=.o) $(VSN_GENERATED_SOURCES:.adb=.o)) version.o
++
++vpath %.c @srcdir@/../gcc
++
++libgnatvsn.so.$(LIB_VERSION): $(addprefix obj-shared/,$(OBJECTS))
++	: # Make libgnatvsn.so
++	$(GCC) -o $@ -shared -fPIC -Wl,--soname,$@ $^ \
++	   -L../../gcc/ada/rts -lgnat-$(LIB_VERSION) $(LDFLAGS)
++	ln -s libgnatvsn.so.$(LIB_VERSION) libgnatvsn.so
++	chmod a=r obj-shared/*.ali
++# Make the .ali files, but not the .o files, visible to the gnat tools.
++	cp -lp obj-shared/*.ali .
++
++$(addprefix obj-shared/,$(OBJECTS)): | stamp-libgnatvsn-sources obj-shared
++
++obj-shared/%.o: %.adb
++	$(GCC) -c -fPIC $(CFLAGS) $(LIBGNAT_JUST_BUILT) $< -o $@
++
++obj-shared/%.o: %.ads
++	$(GCC) -c -fPIC $(CFLAGS) $(LIBGNAT_JUST_BUILT) $< -o $@
++
++obj-shared/version.o: version.c
++	$(GCC) -c -fPIC -g -O2 \
++	   -DBASEVER=$(FULLVER_s) \
++	   -DDATESTAMP=$(DATESTAMP_s) \
++	   -DDEVPHASE=$(DEVPHASE_s) \
++	   -DPKGVERSION=$(PKGVERSION_s) \
++	   -DBUGURL=$(BUGURL_s) \
++	   -DREVISION= \
++	   $(realpath $<) -o $@
++
++obj-shared:
++	-mkdir $@
++
++libgnatvsn.a: $(addprefix obj-static/,$(OBJECTS))
++	: # Make libgnatvsn.a
++	ar rc $@ $^
++	ranlib $@
++
++$(addprefix obj-static/,$(OBJECTS)): | stamp-libgnatvsn-sources obj-static
++
++obj-static/%.o: %.adb
++	$(GCC) -c $(CFLAGS) $(LIBGNAT_JUST_BUILT) $< -o $@
++
++obj-static/%.o: %.ads
++	$(GCC) -c $(CFLAGS) $(LIBGNAT_JUST_BUILT) $< -o $@
++
++obj-static/version.o: version.c
++	$(GCC) -c -g -O2 \
++	   -DBASEVER=$(FULLVER_s) \
++	   -DDATESTAMP=$(DATESTAMP_s) \
++	   -DDEVPHASE=$(DEVPHASE_s) \
++	   -DPKGVERSION=$(PKGVERSION_s) \
++	   -DBUGURL=$(BUGURL_s) \
++	   -DREVISION= \
++	   $< -o $@
++
++obj-static:
++	-mkdir $@
++
++$(VSN_SOURCES) $(VSN_SEPARATES) $(VSN_GENERATED_SOURCES): stamp-libgnatvsn-sources
++
++stamp-libgnatvsn-sources:
++	for file in $(VSN_SOURCES) $(VSN_SEPARATES); do \
++	   ads=$$(echo $$file | sed 's/\.adb/.ads/'); \
++	   if [ -f @srcdir@/../gcc/ada/$$file -a ! -L $$file ] ; then ln -s @srcdir@/../gcc/ada/$$file .; fi; \
++	   if [ -f @srcdir@/../gcc/ada/$$ads -a ! -L $$ads ] ; then ln -s @srcdir@/../gcc/ada/$$ads .; fi; \
++	done
++	for file in $(VSN_GENERATED_SOURCES); do \
++	   ads=$$(echo $$file | sed 's/\.adb/.ads/'); \
++	   if [ -f ../../gcc/ada/$$file -a ! -L $$file ] ; then ln -s ../../gcc/ada/$$file .; fi; \
++	   if [ -f ../../gcc/ada/$$ads -a ! -L $$ads ] ; then ln -s ../../gcc/ada/$$ads .; fi; \
++	done
++	touch $@
++
++libdir = @libdir@
++
++install: libgnatvsn
++	$(INSTALL_DATA) libgnatvsn.a $(DESTDIR)$(libdir)
++	$(INSTALL_DATA) libgnatvsn.so.$(LIB_VERSION) $(DESTDIR)$(libdir)
++	cd $(DESTDIR)$(libdir); ln -sf libgnatvsn.so.$(LIB_VERSION) libgnatvsn.so
++	mkdir -p $(DESTDIR)$(prefix)/share/ada/adainclude/gnatvsn
++	$(INSTALL_DATA) \
++	   $(addprefix @srcdir@/../gcc/ada/,$(VSN_SOURCES) $(VSN_SEPARATES)) \
++	   $(addprefix @srcdir@/../gcc/ada/,$(patsubst %.adb,%.ads,$(filter %.adb,$(VSN_SOURCES)))) \
++	   $(addprefix ../../gcc/ada/,$(VSN_GENERATED_SOURCES)) \
++	   $(addprefix ../../gcc/ada/,$(patsubst %.adb,%.ads,$(VSN_GENERATED_SOURCES))) \
++	   $(DESTDIR)$(prefix)/share/ada/adainclude/gnatvsn
++	mkdir -p $(DESTDIR)$(prefix)/lib/ada/adalib/gnatvsn
++	$(INSTALL) -m 0444 obj-shared/*.ali \
++	   $(DESTDIR)$(prefix)/lib/ada/adalib/gnatvsn
++	chmod a=r $(DESTDIR)$(prefix)/lib/ada/adalib/gnatvsn/*.ali
++
++.PHONY: clean
++clean:
++	rm -rf *.ali obj-static obj-shared libgnatvsn* *.adb *.ads stamp*
+Index: b/src/Makefile.def
+===================================================================
+--- a/src/Makefile.def
++++ b/src/Makefile.def
+@@ -183,6 +183,13 @@ target_modules = { module= libada; no_in
+ 		   missing= TAGS;
+ 		   missing= install-info;
+ 		   missing= installcheck; };
++target_modules = { module= libgnatvsn; no_check=true;
++		   missing= info;
++		   missing= dvi;
++		   missing= html;
++		   missing= TAGS;
++		   missing= install-info;
++		   missing= installcheck; };
+ target_modules = { module= libgomp; bootstrap= true; lib_path=.libs; };
+ target_modules = { module= libitm; lib_path=.libs; };
+ target_modules = { module= libatomic; lib_path=.libs; };
+@@ -381,6 +388,8 @@ dependencies = { module=all-fixincludes;
+ 
+ dependencies = { module=all-target-libada; on=all-gcc; };
+ dependencies = { module=all-gnattools; on=all-target-libada; };
++dependencies = { module=all-gnattools; on=all-target-libgnatvsn; };
++dependencies = { module=all-target-libgnatvsn; on=all-target-libada; };
+ dependencies = { module=all-gnattools; on=all-target-libstdc++-v3; };
+ 
+ // Depending on the specific configuration, the LTO plugin will either use the
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -177,6 +177,7 @@ target_libraries="target-libgcc \
+ 		target-libobjc \
+ 		target-libada \
+ 		${target_libiberty} \
++		target-libgnatvsn \
+ 		target-libgo"
+ 
+ # these tools are built using the target libraries, and are intended to
+@@ -461,7 +462,7 @@ AC_ARG_ENABLE(libada,
+ ENABLE_LIBADA=$enableval,
+ ENABLE_LIBADA=yes)
+ if test "${ENABLE_LIBADA}" != "yes" ; then
+-  noconfigdirs="$noconfigdirs gnattools"
++  noconfigdirs="$noconfigdirs target-libgnatvsn gnattools"
+ fi
+ 
+ AC_ARG_ENABLE(libssp,
+Index: b/src/gcc/ada/gcc-interface/config-lang.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/config-lang.in
++++ b/src/gcc/ada/gcc-interface/config-lang.in
+@@ -34,8 +34,8 @@ gtfiles="\$(srcdir)/ada/gcc-interface/ad
+ 
+ outputs="ada/gcc-interface/Makefile ada/Makefile"
+ 
+-target_libs="target-libada"
+-lang_dirs="libada gnattools"
++target_libs="target-libada target-libgnatvsn"
++lang_dirs="libada libgnatvsn gnattools"
+ 
+ # Ada is not enabled by default for the time being.
+ build_by_default=no
+Index: b/src/Makefile.in
+===================================================================
+--- a/src/Makefile.in
++++ b/src/Makefile.in
+@@ -976,6 +976,7 @@ configure-target:  \
+     maybe-configure-target-boehm-gc \
+     maybe-configure-target-rda \
+     maybe-configure-target-libada \
++    maybe-configure-target-libgnatvsn \
+     maybe-configure-target-libgomp \
+     maybe-configure-target-libitm \
+     maybe-configure-target-libatomic
+@@ -1144,6 +1145,7 @@ all-target: maybe-all-target-zlib
+ all-target: maybe-all-target-boehm-gc
+ all-target: maybe-all-target-rda
+ all-target: maybe-all-target-libada
++all-target: maybe-all-target-libgnatvsn
+ @if target-libgomp-no-bootstrap
+ all-target: maybe-all-target-libgomp
+ @endif target-libgomp-no-bootstrap
+@@ -1239,6 +1241,7 @@ info-target: maybe-info-target-zlib
+ info-target: maybe-info-target-boehm-gc
+ info-target: maybe-info-target-rda
+ info-target: maybe-info-target-libada
++info-target: maybe-info-target-libgnatvsn
+ info-target: maybe-info-target-libgomp
+ info-target: maybe-info-target-libitm
+ info-target: maybe-info-target-libatomic
+@@ -1327,6 +1330,7 @@ dvi-target: maybe-dvi-target-zlib
+ dvi-target: maybe-dvi-target-boehm-gc
+ dvi-target: maybe-dvi-target-rda
+ dvi-target: maybe-dvi-target-libada
++dvi-target: maybe-dvi-target-libgnatvsn
+ dvi-target: maybe-dvi-target-libgomp
+ dvi-target: maybe-dvi-target-libitm
+ dvi-target: maybe-dvi-target-libatomic
+@@ -1415,6 +1419,7 @@ pdf-target: maybe-pdf-target-zlib
+ pdf-target: maybe-pdf-target-boehm-gc
+ pdf-target: maybe-pdf-target-rda
+ pdf-target: maybe-pdf-target-libada
++pdf-target: maybe-pdf-target-libgnatvsn
+ pdf-target: maybe-pdf-target-libgomp
+ pdf-target: maybe-pdf-target-libitm
+ pdf-target: maybe-pdf-target-libatomic
+@@ -1503,6 +1508,7 @@ html-target: maybe-html-target-zlib
+ html-target: maybe-html-target-boehm-gc
+ html-target: maybe-html-target-rda
+ html-target: maybe-html-target-libada
++html-target: maybe-html-target-libgnatvsn
+ html-target: maybe-html-target-libgomp
+ html-target: maybe-html-target-libitm
+ html-target: maybe-html-target-libatomic
+@@ -1591,6 +1597,7 @@ TAGS-target: maybe-TAGS-target-zlib
+ TAGS-target: maybe-TAGS-target-boehm-gc
+ TAGS-target: maybe-TAGS-target-rda
+ TAGS-target: maybe-TAGS-target-libada
++TAGS-target: maybe-TAGS-target-libgnatvsn
+ TAGS-target: maybe-TAGS-target-libgomp
+ TAGS-target: maybe-TAGS-target-libitm
+ TAGS-target: maybe-TAGS-target-libatomic
+@@ -1679,6 +1686,7 @@ install-info-target: maybe-install-info-
+ install-info-target: maybe-install-info-target-boehm-gc
+ install-info-target: maybe-install-info-target-rda
+ install-info-target: maybe-install-info-target-libada
++install-info-target: maybe-install-info-target-libgnatvsn
+ install-info-target: maybe-install-info-target-libgomp
+ install-info-target: maybe-install-info-target-libitm
+ install-info-target: maybe-install-info-target-libatomic
+@@ -1767,6 +1775,7 @@ install-pdf-target: maybe-install-pdf-ta
+ install-pdf-target: maybe-install-pdf-target-boehm-gc
+ install-pdf-target: maybe-install-pdf-target-rda
+ install-pdf-target: maybe-install-pdf-target-libada
++install-pdf-target: maybe-install-pdf-target-libgnatvsn
+ install-pdf-target: maybe-install-pdf-target-libgomp
+ install-pdf-target: maybe-install-pdf-target-libitm
+ install-pdf-target: maybe-install-pdf-target-libatomic
+@@ -1855,6 +1864,7 @@ install-html-target: maybe-install-html-
+ install-html-target: maybe-install-html-target-boehm-gc
+ install-html-target: maybe-install-html-target-rda
+ install-html-target: maybe-install-html-target-libada
++install-html-target: maybe-install-html-target-libgnatvsn
+ install-html-target: maybe-install-html-target-libgomp
+ install-html-target: maybe-install-html-target-libitm
+ install-html-target: maybe-install-html-target-libatomic
+@@ -1943,6 +1953,7 @@ installcheck-target: maybe-installcheck-
+ installcheck-target: maybe-installcheck-target-boehm-gc
+ installcheck-target: maybe-installcheck-target-rda
+ installcheck-target: maybe-installcheck-target-libada
++installcheck-target: maybe-installcheck-target-libgnatvsn
+ installcheck-target: maybe-installcheck-target-libgomp
+ installcheck-target: maybe-installcheck-target-libitm
+ installcheck-target: maybe-installcheck-target-libatomic
+@@ -2031,6 +2042,7 @@ mostlyclean-target: maybe-mostlyclean-ta
+ mostlyclean-target: maybe-mostlyclean-target-boehm-gc
+ mostlyclean-target: maybe-mostlyclean-target-rda
+ mostlyclean-target: maybe-mostlyclean-target-libada
++mostlyclean-target: maybe-mostlyclean-target-libgnatvsn
+ mostlyclean-target: maybe-mostlyclean-target-libgomp
+ mostlyclean-target: maybe-mostlyclean-target-libitm
+ mostlyclean-target: maybe-mostlyclean-target-libatomic
+@@ -2119,6 +2131,7 @@ clean-target: maybe-clean-target-zlib
+ clean-target: maybe-clean-target-boehm-gc
+ clean-target: maybe-clean-target-rda
+ clean-target: maybe-clean-target-libada
++clean-target: maybe-clean-target-libgnatvsn
+ clean-target: maybe-clean-target-libgomp
+ clean-target: maybe-clean-target-libitm
+ clean-target: maybe-clean-target-libatomic
+@@ -2207,6 +2220,7 @@ distclean-target: maybe-distclean-target
+ distclean-target: maybe-distclean-target-boehm-gc
+ distclean-target: maybe-distclean-target-rda
+ distclean-target: maybe-distclean-target-libada
++distclean-target: maybe-distclean-target-libgnatvsn
+ distclean-target: maybe-distclean-target-libgomp
+ distclean-target: maybe-distclean-target-libitm
+ distclean-target: maybe-distclean-target-libatomic
+@@ -2295,6 +2309,7 @@ maintainer-clean-target: maybe-maintaine
+ maintainer-clean-target: maybe-maintainer-clean-target-boehm-gc
+ maintainer-clean-target: maybe-maintainer-clean-target-rda
+ maintainer-clean-target: maybe-maintainer-clean-target-libada
++maintainer-clean-target: maybe-maintainer-clean-target-libgnatvsn
+ maintainer-clean-target: maybe-maintainer-clean-target-libgomp
+ maintainer-clean-target: maybe-maintainer-clean-target-libitm
+ maintainer-clean-target: maybe-maintainer-clean-target-libatomic
+@@ -2439,6 +2454,7 @@ check-target:  \
+     maybe-check-target-boehm-gc \
+     maybe-check-target-rda \
+     maybe-check-target-libada \
++    maybe-check-target-libgnatvsn \
+     maybe-check-target-libgomp \
+     maybe-check-target-libitm \
+     maybe-check-target-libatomic
+@@ -2623,6 +2639,7 @@ install-target:  \
+     maybe-install-target-boehm-gc \
+     maybe-install-target-rda \
+     maybe-install-target-libada \
++    maybe-install-target-libgnatvsn \
+     maybe-install-target-libgomp \
+     maybe-install-target-libitm \
+     maybe-install-target-libatomic
+@@ -2731,6 +2748,7 @@ install-strip-target:  \
+     maybe-install-strip-target-boehm-gc \
+     maybe-install-strip-target-rda \
+     maybe-install-strip-target-libada \
++    maybe-install-strip-target-libgnatvsn \
+     maybe-install-strip-target-libgomp \
+     maybe-install-strip-target-libitm \
+     maybe-install-strip-target-libatomic
+@@ -46041,6 +46059,362 @@ maintainer-clean-target-libada:
+ 
+ 
+ 
++.PHONY: configure-target-libgnatvsn maybe-configure-target-libgnatvsn
++maybe-configure-target-libgnatvsn:
++@if gcc-bootstrap
++configure-target-libgnatvsn: stage_current
++@endif gcc-bootstrap
++@if target-libgnatvsn
++maybe-configure-target-libgnatvsn: configure-target-libgnatvsn
++configure-target-libgnatvsn: 
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	echo "Checking multilib configuration for libgnatvsn..."; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatvsn ; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp 2> /dev/null ; \
++	if test -r $(TARGET_SUBDIR)/libgnatvsn/multilib.out; then \
++	  if cmp -s $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp $(TARGET_SUBDIR)/libgnatvsn/multilib.out; then \
++	    rm -f $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp; \
++	  else \
++	    rm -f $(TARGET_SUBDIR)/libgnatvsn/Makefile; \
++	    mv $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp $(TARGET_SUBDIR)/libgnatvsn/multilib.out; \
++	  fi; \
++	else \
++	  mv $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp $(TARGET_SUBDIR)/libgnatvsn/multilib.out; \
++	fi; \
++	test ! -f $(TARGET_SUBDIR)/libgnatvsn/Makefile || exit 0; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatvsn ; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	echo Configuring in $(TARGET_SUBDIR)/libgnatvsn; \
++	cd "$(TARGET_SUBDIR)/libgnatvsn" || exit 1; \
++	case $(srcdir) in \
++	  /* | [A-Za-z]:[\\/]*) topdir=$(srcdir) ;; \
++	  *) topdir=`echo $(TARGET_SUBDIR)/libgnatvsn/ | \
++		sed -e 's,\./,,g' -e 's,[^/]*/,../,g' `$(srcdir) ;; \
++	esac; \
++	module_srcdir=libgnatvsn; \
++	rm -f no-such-file || : ; \
++	CONFIG_SITE=no-such-file $(SHELL) \
++	  $$s/$$module_srcdir/configure \
++	  --srcdir=$${topdir}/$$module_srcdir \
++	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
++	  --target=${target_alias}  \
++	  || exit 1
++@endif target-libgnatvsn
++
++
++
++
++
++.PHONY: all-target-libgnatvsn maybe-all-target-libgnatvsn
++maybe-all-target-libgnatvsn:
++@if gcc-bootstrap
++all-target-libgnatvsn: stage_current
++@endif gcc-bootstrap
++@if target-libgnatvsn
++TARGET-target-libgnatvsn=all
++maybe-all-target-libgnatvsn: all-target-libgnatvsn
++all-target-libgnatvsn: configure-target-libgnatvsn
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) $(EXTRA_TARGET_FLAGS)   \
++		$(TARGET-target-libgnatvsn))
++@endif target-libgnatvsn
++
++
++
++
++
++.PHONY: check-target-libgnatvsn maybe-check-target-libgnatvsn
++maybe-check-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-check-target-libgnatvsn: check-target-libgnatvsn
++
++# Dummy target for uncheckable module.
++check-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: install-target-libgnatvsn maybe-install-target-libgnatvsn
++maybe-install-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-install-target-libgnatvsn: install-target-libgnatvsn
++
++install-target-libgnatvsn: installdirs
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install)
++
++@endif target-libgnatvsn
++
++.PHONY: install-strip-target-libgnatvsn maybe-install-strip-target-libgnatvsn
++maybe-install-strip-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-install-strip-target-libgnatvsn: install-strip-target-libgnatvsn
++
++install-strip-target-libgnatvsn: installdirs
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install-strip)
++
++@endif target-libgnatvsn
++
++# Other targets (info, dvi, pdf, etc.)
++
++.PHONY: maybe-info-target-libgnatvsn info-target-libgnatvsn
++maybe-info-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-info-target-libgnatvsn: info-target-libgnatvsn
++
++# libgnatvsn doesn't support info.
++info-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-dvi-target-libgnatvsn dvi-target-libgnatvsn
++maybe-dvi-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-dvi-target-libgnatvsn: dvi-target-libgnatvsn
++
++# libgnatvsn doesn't support dvi.
++dvi-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-pdf-target-libgnatvsn pdf-target-libgnatvsn
++maybe-pdf-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-pdf-target-libgnatvsn: pdf-target-libgnatvsn
++
++pdf-target-libgnatvsn: \
++    configure-target-libgnatvsn 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           pdf) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-html-target-libgnatvsn html-target-libgnatvsn
++maybe-html-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-html-target-libgnatvsn: html-target-libgnatvsn
++
++# libgnatvsn doesn't support html.
++html-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-TAGS-target-libgnatvsn TAGS-target-libgnatvsn
++maybe-TAGS-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-TAGS-target-libgnatvsn: TAGS-target-libgnatvsn
++
++# libgnatvsn doesn't support TAGS.
++TAGS-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-install-info-target-libgnatvsn install-info-target-libgnatvsn
++maybe-install-info-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-install-info-target-libgnatvsn: install-info-target-libgnatvsn
++
++# libgnatvsn doesn't support install-info.
++install-info-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-install-pdf-target-libgnatvsn install-pdf-target-libgnatvsn
++maybe-install-pdf-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-install-pdf-target-libgnatvsn: install-pdf-target-libgnatvsn
++
++install-pdf-target-libgnatvsn: \
++    configure-target-libgnatvsn \
++    pdf-target-libgnatvsn 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-pdf) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-install-html-target-libgnatvsn install-html-target-libgnatvsn
++maybe-install-html-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-install-html-target-libgnatvsn: install-html-target-libgnatvsn
++
++install-html-target-libgnatvsn: \
++    configure-target-libgnatvsn \
++    html-target-libgnatvsn 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-html) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-installcheck-target-libgnatvsn installcheck-target-libgnatvsn
++maybe-installcheck-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-installcheck-target-libgnatvsn: installcheck-target-libgnatvsn
++
++# libgnatvsn doesn't support installcheck.
++installcheck-target-libgnatvsn:
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-mostlyclean-target-libgnatvsn mostlyclean-target-libgnatvsn
++maybe-mostlyclean-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-mostlyclean-target-libgnatvsn: mostlyclean-target-libgnatvsn
++
++mostlyclean-target-libgnatvsn: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           mostlyclean) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-clean-target-libgnatvsn clean-target-libgnatvsn
++maybe-clean-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-clean-target-libgnatvsn: clean-target-libgnatvsn
++
++clean-target-libgnatvsn: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing clean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           clean) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-distclean-target-libgnatvsn distclean-target-libgnatvsn
++maybe-distclean-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-distclean-target-libgnatvsn: distclean-target-libgnatvsn
++
++distclean-target-libgnatvsn: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           distclean) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++.PHONY: maybe-maintainer-clean-target-libgnatvsn maintainer-clean-target-libgnatvsn
++maybe-maintainer-clean-target-libgnatvsn:
++@if target-libgnatvsn
++maybe-maintainer-clean-target-libgnatvsn: maintainer-clean-target-libgnatvsn
++
++maintainer-clean-target-libgnatvsn: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libgnatvsn && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           maintainer-clean) \
++	  || exit 1
++
++@endif target-libgnatvsn
++
++
++
++
++
+ .PHONY: configure-target-libgomp maybe-configure-target-libgomp
+ maybe-configure-target-libgomp:
+ @if gcc-bootstrap
+@@ -50245,6 +50619,7 @@ configure-target-zlib: stage_last
+ configure-target-boehm-gc: stage_last
+ configure-target-rda: stage_last
+ configure-target-libada: stage_last
++configure-target-libgnatvsn: stage_last
+ configure-stage1-target-libgomp: maybe-all-stage1-gcc
+ configure-stage2-target-libgomp: maybe-all-stage2-gcc
+ configure-stage3-target-libgomp: maybe-all-stage3-gcc
+@@ -50280,6 +50655,7 @@ configure-target-zlib: maybe-all-gcc
+ configure-target-boehm-gc: maybe-all-gcc
+ configure-target-rda: maybe-all-gcc
+ configure-target-libada: maybe-all-gcc
++configure-target-libgnatvsn: maybe-all-gcc
+ configure-target-libgomp: maybe-all-gcc
+ configure-target-libitm: maybe-all-gcc
+ configure-target-libatomic: maybe-all-gcc
+@@ -50653,6 +51029,8 @@ all-stageprofile-fixincludes: maybe-all-
+ all-stagefeedback-fixincludes: maybe-all-stagefeedback-libiberty
+ all-target-libada: maybe-all-gcc
+ all-gnattools: maybe-all-target-libada
++all-gnattools: maybe-all-target-libgnatvsn
++all-target-libgnatvsn: maybe-all-target-libada
+ all-gnattools: maybe-all-target-libstdc++-v3
+ all-lto-plugin: maybe-all-libiberty
+ 
+@@ -51249,6 +51627,7 @@ configure-target-zlib: maybe-all-target-
+ configure-target-boehm-gc: maybe-all-target-libgcc
+ configure-target-rda: maybe-all-target-libgcc
+ configure-target-libada: maybe-all-target-libgcc
++configure-target-libgnatvsn: maybe-all-target-libgcc
+ configure-target-libgomp: maybe-all-target-libgcc
+ configure-target-libitm: maybe-all-target-libgcc
+ configure-target-libatomic: maybe-all-target-libgcc
+@@ -51303,6 +51682,8 @@ configure-target-rda: maybe-all-target-n
+ 
+ configure-target-libada: maybe-all-target-newlib maybe-all-target-libgloss
+ 
++configure-target-libgnatvsn: maybe-all-target-newlib maybe-all-target-libgloss
++
+ configure-target-libgomp: maybe-all-target-newlib maybe-all-target-libgloss
+ 
+ configure-target-libitm: maybe-all-target-newlib maybe-all-target-libgloss
--- gcc-6-6.4.0.orig/debian/patches/ada-library-project-files-soname.diff
+++ gcc-6-6.4.0/debian/patches/ada-library-project-files-soname.diff
@@ -0,0 +1,81 @@
+# DP: - in project files, use the exact Library_Version provided, if any, as
+# DP:   the soname of libraries; do not strip minor version numbers
+# DP:   (PR ada/40025).
+
+Index: b/src/gcc/ada/mlib-tgt-specific-linux.adb
+===================================================================
+--- a/src/gcc/ada/mlib-tgt-specific-linux.adb
++++ b/src/gcc/ada/mlib-tgt-specific-linux.adb
+@@ -50,6 +50,8 @@ package body MLib.Tgt.Specific is
+ 
+    function Is_Archive_Ext (Ext : String) return Boolean;
+ 
++   function Library_Major_Minor_Id_Supported return Boolean;
++
+    ---------------------------
+    -- Build_Dynamic_Library --
+    ---------------------------
+@@ -142,7 +144,18 @@ package body MLib.Tgt.Specific is
+       return Ext = ".a" or else Ext = ".so";
+    end Is_Archive_Ext;
+ 
++   --------------------------------------
++   -- Library_Major_Minor_Id_Supported --
++   --------------------------------------
++
++   function Library_Major_Minor_Id_Supported return Boolean is
++   begin
++      return False;
++   end Library_Major_Minor_Id_Supported;
++
+ begin
+    Build_Dynamic_Library_Ptr := Build_Dynamic_Library'Access;
+    Is_Archive_Ext_Ptr := Is_Archive_Ext'Access;
++   Library_Major_Minor_Id_Supported_Ptr :=
++                                Library_Major_Minor_Id_Supported'Access;
+ end MLib.Tgt.Specific;
+Index: b/src/gcc/ada/mlib.adb
+===================================================================
+--- a/src/gcc/ada/mlib.adb
++++ b/src/gcc/ada/mlib.adb
+@@ -30,6 +30,7 @@ with System;
+ with Opt;
+ with Output; use Output;
+ 
++with MLib.Tgt;
+ with MLib.Utl; use MLib.Utl;
+ 
+ with Prj.Com;
+@@ -393,7 +394,11 @@ package body MLib is
+    -- Major_Id_Name --
+    -------------------
+ 
+-   function Major_Id_Name
++   function Major_Id_Name_If_Supported
++     (Lib_Filename : String;
++      Lib_Version  : String)
++      return String;
++   function Major_Id_Name_If_Supported
+      (Lib_Filename : String;
+       Lib_Version  : String)
+       return String
+@@ -447,6 +452,19 @@ package body MLib is
+       else
+          return "";
+       end if;
++   end Major_Id_Name_If_Supported;
++
++   function Major_Id_Name
++     (Lib_Filename : String;
++      Lib_Version  : String)
++      return String
++   is
++   begin
++      if MLib.Tgt.Library_Major_Minor_Id_Supported then
++         return Major_Id_Name_If_Supported (Lib_Filename, Lib_Version);
++      else
++         return "";
++      end if;
+    end Major_Id_Name;
+ 
+    -------------------------------
--- gcc-6-6.4.0.orig/debian/patches/ada-link-lib.diff
+++ gcc-6-6.4.0/debian/patches/ada-link-lib.diff
@@ -0,0 +1,1181 @@
+# DP: - Install the shared Ada libraries as '.so.1', not '.so' to conform
+# DP:   to the Debian policy.
+# DP: - Don't include a runtime link path (-rpath), when linking binaries.
+# DP: - Build the shared libraries on hppa-linux.
+# DP: - Instead of building libada as a target library only, build it as
+# DP:   both a host and, if different, target library.
+# DP: - Build the GNAT tools in their top-level directory; do not use
+# DP:   recursive makefiles.
+# DP: - Link the GNAT tools dynamically.
+
+# This patch seems large, but the hunks in Makefile.in are actually
+# generated from Makefile.def using autogen.
+
+Index: b/src/gcc/ada/gcc-interface/config-lang.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/config-lang.in
++++ b/src/gcc/ada/gcc-interface/config-lang.in
+@@ -35,7 +35,7 @@ gtfiles="\$(srcdir)/ada/gcc-interface/ad
+ outputs="ada/gcc-interface/Makefile ada/Makefile"
+ 
+ target_libs="target-libada"
+-lang_dirs="gnattools"
++lang_dirs="libada gnattools"
+ 
+ # Ada is not enabled by default for the time being.
+ build_by_default=no
+Index: b/src/gcc/ada/link.c
+===================================================================
+--- a/src/gcc/ada/link.c
++++ b/src/gcc/ada/link.c
+@@ -106,9 +106,9 @@ const char *__gnat_default_libgcc_subdir
+ #elif defined (__FreeBSD__) || defined (__DragonFly__) \
+    || defined (__NetBSD__) || defined (__OpenBSD__)
+ const char *__gnat_object_file_option = "-Wl,@";
+-const char *__gnat_run_path_option = "-Wl,-rpath,";
+-char __gnat_shared_libgnat_default = STATIC;
+-char __gnat_shared_libgcc_default = STATIC;
++const char *__gnat_run_path_option = "";
++char __gnat_shared_libgnat_default = SHARED;
++char __gnat_shared_libgcc_default = SHARED;
+ int __gnat_link_max = 8192;
+ unsigned char __gnat_objlist_file_supported = 1;
+ const char *__gnat_object_library_extension = ".a";
+@@ -128,9 +128,9 @@ const char *__gnat_default_libgcc_subdir
+ 
+ #elif defined (__linux__) || defined (__GLIBC__)
+ const char *__gnat_object_file_option = "-Wl,@";
+-const char *__gnat_run_path_option = "-Wl,-rpath,";
+-char __gnat_shared_libgnat_default = STATIC;
+-char __gnat_shared_libgcc_default = STATIC;
++const char *__gnat_run_path_option = "";
++char __gnat_shared_libgnat_default = SHARED;
++char __gnat_shared_libgcc_default = SHARED;
+ int __gnat_link_max = 8192;
+ unsigned char __gnat_objlist_file_supported = 1;
+ const char *__gnat_object_library_extension = ".a";
+Index: b/src/libada/Makefile.in
+===================================================================
+--- a/src/libada/Makefile.in
++++ b/src/libada/Makefile.in
+@@ -60,7 +60,7 @@ CFLAGS=-g
+ PICFLAG = @PICFLAG@
+ GNATLIBFLAGS= -W -Wall -gnatpg -nostdinc
+ GNATLIBCFLAGS= -g -O2
+-GNATLIBCFLAGS_FOR_C = -W -Wall $(GNATLIBCFLAGS) $(CFLAGS_FOR_TARGET) \
++GNATLIBCFLAGS_FOR_C = -W -Wall $(GNATLIBCFLAGS) \
+ 	-fexceptions -DIN_RTS @have_getipinfo@
+ 
+ host_subdir = @host_subdir@
+Index: b/src/Makefile.def
+===================================================================
+--- a/src/Makefile.def
++++ b/src/Makefile.def
+@@ -121,7 +121,13 @@ host_modules= { module= libtermcap; no_c
+                 missing=distclean;
+                 missing=maintainer-clean; };
+ host_modules= { module= utils; no_check=true; };
+-host_modules= { module= gnattools; };
++host_modules= { module= gnattools; no_check=true;
++		missing= info;
++		missing= dvi;
++		missing= html;
++		missing= TAGS;
++		missing= install-info;
++		missing= installcheck; };
+ host_modules= { module= lto-plugin; bootstrap=true;
+ 		extra_configure_flags='--enable-shared @extra_linker_plugin_flags@ @extra_linker_plugin_configure_flags@';
+ 		extra_make_flags='@extra_linker_plugin_flags@'; };
+@@ -164,12 +170,19 @@ target_modules = { module= libtermcap; n
+ target_modules = { module= winsup; };
+ target_modules = { module= libgloss; no_check=true; };
+ target_modules = { module= libffi; no_install=true; };
++target_modules = { module= libiberty; no_install=true; no_check=true; };
+ target_modules = { module= libjava; raw_cxx=true;
+                    extra_configure_flags="$(EXTRA_CONFIGARGS_LIBJAVA)"; };
+ target_modules = { module= zlib; };
+ target_modules = { module= boehm-gc; };
+ target_modules = { module= rda; };
+-target_modules = { module= libada; };
++target_modules = { module= libada; no_install=true; no_check=true;
++		   missing= info;
++		   missing= dvi;
++		   missing= html;
++		   missing= TAGS;
++		   missing= install-info;
++		   missing= installcheck; };
+ target_modules = { module= libgomp; bootstrap= true; lib_path=.libs; };
+ target_modules = { module= libitm; lib_path=.libs; };
+ target_modules = { module= libatomic; lib_path=.libs; };
+@@ -366,6 +379,7 @@ dependencies = { module=all-libcpp; on=a
+ 
+ dependencies = { module=all-fixincludes; on=all-libiberty; };
+ 
++dependencies = { module=all-target-libada; on=all-gcc; };
+ dependencies = { module=all-gnattools; on=all-target-libada; };
+ dependencies = { module=all-gnattools; on=all-target-libstdc++-v3; };
+ 
+Index: b/src/Makefile.in
+===================================================================
+--- a/src/Makefile.in
++++ b/src/Makefile.in
+@@ -970,6 +970,7 @@ configure-target:  \
+     maybe-configure-target-winsup \
+     maybe-configure-target-libgloss \
+     maybe-configure-target-libffi \
++    maybe-configure-target-libiberty \
+     maybe-configure-target-libjava \
+     maybe-configure-target-zlib \
+     maybe-configure-target-boehm-gc \
+@@ -1137,6 +1138,7 @@ all-target: maybe-all-target-libtermcap
+ all-target: maybe-all-target-winsup
+ all-target: maybe-all-target-libgloss
+ all-target: maybe-all-target-libffi
++all-target: maybe-all-target-libiberty
+ all-target: maybe-all-target-libjava
+ all-target: maybe-all-target-zlib
+ all-target: maybe-all-target-boehm-gc
+@@ -1231,6 +1233,7 @@ info-target: maybe-info-target-libtermca
+ info-target: maybe-info-target-winsup
+ info-target: maybe-info-target-libgloss
+ info-target: maybe-info-target-libffi
++info-target: maybe-info-target-libiberty
+ info-target: maybe-info-target-libjava
+ info-target: maybe-info-target-zlib
+ info-target: maybe-info-target-boehm-gc
+@@ -1318,6 +1321,7 @@ dvi-target: maybe-dvi-target-libtermcap
+ dvi-target: maybe-dvi-target-winsup
+ dvi-target: maybe-dvi-target-libgloss
+ dvi-target: maybe-dvi-target-libffi
++dvi-target: maybe-dvi-target-libiberty
+ dvi-target: maybe-dvi-target-libjava
+ dvi-target: maybe-dvi-target-zlib
+ dvi-target: maybe-dvi-target-boehm-gc
+@@ -1405,6 +1409,7 @@ pdf-target: maybe-pdf-target-libtermcap
+ pdf-target: maybe-pdf-target-winsup
+ pdf-target: maybe-pdf-target-libgloss
+ pdf-target: maybe-pdf-target-libffi
++pdf-target: maybe-pdf-target-libiberty
+ pdf-target: maybe-pdf-target-libjava
+ pdf-target: maybe-pdf-target-zlib
+ pdf-target: maybe-pdf-target-boehm-gc
+@@ -1492,6 +1497,7 @@ html-target: maybe-html-target-libtermca
+ html-target: maybe-html-target-winsup
+ html-target: maybe-html-target-libgloss
+ html-target: maybe-html-target-libffi
++html-target: maybe-html-target-libiberty
+ html-target: maybe-html-target-libjava
+ html-target: maybe-html-target-zlib
+ html-target: maybe-html-target-boehm-gc
+@@ -1579,6 +1585,7 @@ TAGS-target: maybe-TAGS-target-libtermca
+ TAGS-target: maybe-TAGS-target-winsup
+ TAGS-target: maybe-TAGS-target-libgloss
+ TAGS-target: maybe-TAGS-target-libffi
++TAGS-target: maybe-TAGS-target-libiberty
+ TAGS-target: maybe-TAGS-target-libjava
+ TAGS-target: maybe-TAGS-target-zlib
+ TAGS-target: maybe-TAGS-target-boehm-gc
+@@ -1666,6 +1673,7 @@ install-info-target: maybe-install-info-
+ install-info-target: maybe-install-info-target-winsup
+ install-info-target: maybe-install-info-target-libgloss
+ install-info-target: maybe-install-info-target-libffi
++install-info-target: maybe-install-info-target-libiberty
+ install-info-target: maybe-install-info-target-libjava
+ install-info-target: maybe-install-info-target-zlib
+ install-info-target: maybe-install-info-target-boehm-gc
+@@ -1753,6 +1761,7 @@ install-pdf-target: maybe-install-pdf-ta
+ install-pdf-target: maybe-install-pdf-target-winsup
+ install-pdf-target: maybe-install-pdf-target-libgloss
+ install-pdf-target: maybe-install-pdf-target-libffi
++install-pdf-target: maybe-install-pdf-target-libiberty
+ install-pdf-target: maybe-install-pdf-target-libjava
+ install-pdf-target: maybe-install-pdf-target-zlib
+ install-pdf-target: maybe-install-pdf-target-boehm-gc
+@@ -1840,6 +1849,7 @@ install-html-target: maybe-install-html-
+ install-html-target: maybe-install-html-target-winsup
+ install-html-target: maybe-install-html-target-libgloss
+ install-html-target: maybe-install-html-target-libffi
++install-html-target: maybe-install-html-target-libiberty
+ install-html-target: maybe-install-html-target-libjava
+ install-html-target: maybe-install-html-target-zlib
+ install-html-target: maybe-install-html-target-boehm-gc
+@@ -1927,6 +1937,7 @@ installcheck-target: maybe-installcheck-
+ installcheck-target: maybe-installcheck-target-winsup
+ installcheck-target: maybe-installcheck-target-libgloss
+ installcheck-target: maybe-installcheck-target-libffi
++installcheck-target: maybe-installcheck-target-libiberty
+ installcheck-target: maybe-installcheck-target-libjava
+ installcheck-target: maybe-installcheck-target-zlib
+ installcheck-target: maybe-installcheck-target-boehm-gc
+@@ -2014,6 +2025,7 @@ mostlyclean-target: maybe-mostlyclean-ta
+ mostlyclean-target: maybe-mostlyclean-target-winsup
+ mostlyclean-target: maybe-mostlyclean-target-libgloss
+ mostlyclean-target: maybe-mostlyclean-target-libffi
++mostlyclean-target: maybe-mostlyclean-target-libiberty
+ mostlyclean-target: maybe-mostlyclean-target-libjava
+ mostlyclean-target: maybe-mostlyclean-target-zlib
+ mostlyclean-target: maybe-mostlyclean-target-boehm-gc
+@@ -2101,6 +2113,7 @@ clean-target: maybe-clean-target-libterm
+ clean-target: maybe-clean-target-winsup
+ clean-target: maybe-clean-target-libgloss
+ clean-target: maybe-clean-target-libffi
++clean-target: maybe-clean-target-libiberty
+ clean-target: maybe-clean-target-libjava
+ clean-target: maybe-clean-target-zlib
+ clean-target: maybe-clean-target-boehm-gc
+@@ -2188,6 +2201,7 @@ distclean-target: maybe-distclean-target
+ distclean-target: maybe-distclean-target-winsup
+ distclean-target: maybe-distclean-target-libgloss
+ distclean-target: maybe-distclean-target-libffi
++distclean-target: maybe-distclean-target-libiberty
+ distclean-target: maybe-distclean-target-libjava
+ distclean-target: maybe-distclean-target-zlib
+ distclean-target: maybe-distclean-target-boehm-gc
+@@ -2275,6 +2289,7 @@ maintainer-clean-target: maybe-maintaine
+ maintainer-clean-target: maybe-maintainer-clean-target-winsup
+ maintainer-clean-target: maybe-maintainer-clean-target-libgloss
+ maintainer-clean-target: maybe-maintainer-clean-target-libffi
++maintainer-clean-target: maybe-maintainer-clean-target-libiberty
+ maintainer-clean-target: maybe-maintainer-clean-target-libjava
+ maintainer-clean-target: maybe-maintainer-clean-target-zlib
+ maintainer-clean-target: maybe-maintainer-clean-target-boehm-gc
+@@ -2418,6 +2433,7 @@ check-target:  \
+     maybe-check-target-winsup \
+     maybe-check-target-libgloss \
+     maybe-check-target-libffi \
++    maybe-check-target-libiberty \
+     maybe-check-target-libjava \
+     maybe-check-target-zlib \
+     maybe-check-target-boehm-gc \
+@@ -2601,6 +2617,7 @@ install-target:  \
+     maybe-install-target-winsup \
+     maybe-install-target-libgloss \
+     maybe-install-target-libffi \
++    maybe-install-target-libiberty \
+     maybe-install-target-libjava \
+     maybe-install-target-zlib \
+     maybe-install-target-boehm-gc \
+@@ -2708,6 +2725,7 @@ install-strip-target:  \
+     maybe-install-strip-target-winsup \
+     maybe-install-strip-target-libgloss \
+     maybe-install-strip-target-libffi \
++    maybe-install-strip-target-libiberty \
+     maybe-install-strip-target-libjava \
+     maybe-install-strip-target-zlib \
+     maybe-install-strip-target-boehm-gc \
+@@ -30607,12 +30625,6 @@ maybe-check-gnattools:
+ maybe-check-gnattools: check-gnattools
+ 
+ check-gnattools:
+-	@: $(MAKE); $(unstage)
+-	@r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS)  \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(FLAGS_TO_PASS)  check)
+ 
+ @endif gnattools
+ 
+@@ -30653,24 +30665,8 @@ maybe-info-gnattools:
+ @if gnattools
+ maybe-info-gnattools: info-gnattools
+ 
+-info-gnattools: \
+-    configure-gnattools 
+-	@: $(MAKE); $(unstage)
+-	@[ -f ./gnattools/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS) \
+-	for flag in $(EXTRA_HOST_FLAGS) ; do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	echo "Doing info in gnattools"; \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	          info) \
+-	  || exit 1
++# gnattools doesn't support info.
++info-gnattools:
+ 
+ @endif gnattools
+ 
+@@ -30679,24 +30675,8 @@ maybe-dvi-gnattools:
+ @if gnattools
+ maybe-dvi-gnattools: dvi-gnattools
+ 
+-dvi-gnattools: \
+-    configure-gnattools 
+-	@: $(MAKE); $(unstage)
+-	@[ -f ./gnattools/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS) \
+-	for flag in $(EXTRA_HOST_FLAGS) ; do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	echo "Doing dvi in gnattools"; \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	          dvi) \
+-	  || exit 1
++# gnattools doesn't support dvi.
++dvi-gnattools:
+ 
+ @endif gnattools
+ 
+@@ -30731,24 +30711,8 @@ maybe-html-gnattools:
+ @if gnattools
+ maybe-html-gnattools: html-gnattools
+ 
+-html-gnattools: \
+-    configure-gnattools 
+-	@: $(MAKE); $(unstage)
+-	@[ -f ./gnattools/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS) \
+-	for flag in $(EXTRA_HOST_FLAGS) ; do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	echo "Doing html in gnattools"; \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	          html) \
+-	  || exit 1
++# gnattools doesn't support html.
++html-gnattools:
+ 
+ @endif gnattools
+ 
+@@ -30757,24 +30721,8 @@ maybe-TAGS-gnattools:
+ @if gnattools
+ maybe-TAGS-gnattools: TAGS-gnattools
+ 
+-TAGS-gnattools: \
+-    configure-gnattools 
+-	@: $(MAKE); $(unstage)
+-	@[ -f ./gnattools/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS) \
+-	for flag in $(EXTRA_HOST_FLAGS) ; do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	echo "Doing TAGS in gnattools"; \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	          TAGS) \
+-	  || exit 1
++# gnattools doesn't support TAGS.
++TAGS-gnattools:
+ 
+ @endif gnattools
+ 
+@@ -30783,25 +30731,8 @@ maybe-install-info-gnattools:
+ @if gnattools
+ maybe-install-info-gnattools: install-info-gnattools
+ 
+-install-info-gnattools: \
+-    configure-gnattools \
+-    info-gnattools 
+-	@: $(MAKE); $(unstage)
+-	@[ -f ./gnattools/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS) \
+-	for flag in $(EXTRA_HOST_FLAGS) ; do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	echo "Doing install-info in gnattools"; \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	          install-info) \
+-	  || exit 1
++# gnattools doesn't support install-info.
++install-info-gnattools:
+ 
+ @endif gnattools
+ 
+@@ -30864,24 +30795,8 @@ maybe-installcheck-gnattools:
+ @if gnattools
+ maybe-installcheck-gnattools: installcheck-gnattools
+ 
+-installcheck-gnattools: \
+-    configure-gnattools 
+-	@: $(MAKE); $(unstage)
+-	@[ -f ./gnattools/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(HOST_EXPORTS) \
+-	for flag in $(EXTRA_HOST_FLAGS) ; do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	echo "Doing installcheck in gnattools"; \
+-	(cd $(HOST_SUBDIR)/gnattools && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	          installcheck) \
+-	  || exit 1
++# gnattools doesn't support installcheck.
++installcheck-gnattools:
+ 
+ @endif gnattools
+ 
+@@ -43505,6 +43420,449 @@ maintainer-clean-target-libffi:
+ 
+ 
+ 
++.PHONY: configure-target-libiberty maybe-configure-target-libiberty
++maybe-configure-target-libiberty:
++@if gcc-bootstrap
++configure-target-libiberty: stage_current
++@endif gcc-bootstrap
++@if target-libiberty
++maybe-configure-target-libiberty: configure-target-libiberty
++configure-target-libiberty: 
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	echo "Checking multilib configuration for libiberty..."; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libiberty; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libiberty/multilib.tmp 2> /dev/null; \
++	if test -r $(TARGET_SUBDIR)/libiberty/multilib.out; then \
++	  if cmp -s $(TARGET_SUBDIR)/libiberty/multilib.tmp $(TARGET_SUBDIR)/libiberty/multilib.out; then \
++	    rm -f $(TARGET_SUBDIR)/libiberty/multilib.tmp; \
++	  else \
++	    rm -f $(TARGET_SUBDIR)/libiberty/Makefile; \
++	    mv $(TARGET_SUBDIR)/libiberty/multilib.tmp $(TARGET_SUBDIR)/libiberty/multilib.out; \
++	  fi; \
++	else \
++	  mv $(TARGET_SUBDIR)/libiberty/multilib.tmp $(TARGET_SUBDIR)/libiberty/multilib.out; \
++	fi; \
++	test ! -f $(TARGET_SUBDIR)/libiberty/Makefile || exit 0; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libiberty; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	echo Configuring in $(TARGET_SUBDIR)/libiberty; \
++	cd "$(TARGET_SUBDIR)/libiberty" || exit 1; \
++	case $(srcdir) in \
++	  /* | [A-Za-z]:[\\/]*) topdir=$(srcdir) ;; \
++	  *) topdir=`echo $(TARGET_SUBDIR)/libiberty/ | \
++		sed -e 's,\./,,g' -e 's,[^/]*/,../,g' `$(srcdir) ;; \
++	esac; \
++	module_srcdir=libiberty; \
++	rm -f no-such-file || : ; \
++	CONFIG_SITE=no-such-file $(SHELL) \
++	  $$s/$$module_srcdir/configure \
++	  --srcdir=$${topdir}/$$module_srcdir \
++	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
++	  --target=${target_alias}  \
++	  || exit 1
++@endif target-libiberty
++
++
++
++
++
++.PHONY: all-target-libiberty maybe-all-target-libiberty
++maybe-all-target-libiberty:
++@if gcc-bootstrap
++all-target-libiberty: stage_current
++@endif gcc-bootstrap
++@if target-libiberty
++TARGET-target-libiberty=all
++maybe-all-target-libiberty: all-target-libiberty
++all-target-libiberty: configure-target-libiberty
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) $(EXTRA_TARGET_FLAGS)   \
++		$(TARGET-target-libiberty))
++@endif target-libiberty
++
++
++
++
++
++.PHONY: check-target-libiberty maybe-check-target-libiberty
++maybe-check-target-libiberty:
++@if target-libiberty
++maybe-check-target-libiberty: check-target-libiberty
++
++# Dummy target for uncheckable module.
++check-target-libiberty:
++
++@endif target-libiberty
++
++.PHONY: install-target-libiberty maybe-install-target-libiberty
++maybe-install-target-libiberty:
++@if target-libiberty
++maybe-install-target-libiberty: install-target-libiberty
++
++# Dummy target for uninstallable.
++install-target-libiberty:
++
++@endif target-libiberty
++
++.PHONY: install-strip-target-libiberty maybe-install-strip-target-libiberty
++maybe-install-strip-target-libiberty:
++@if target-libiberty
++maybe-install-strip-target-libiberty: install-strip-target-libiberty
++
++# Dummy target for uninstallable.
++install-strip-target-libiberty:
++
++@endif target-libiberty
++
++# Other targets (info, dvi, pdf, etc.)
++
++.PHONY: maybe-info-target-libiberty info-target-libiberty
++maybe-info-target-libiberty:
++@if target-libiberty
++maybe-info-target-libiberty: info-target-libiberty
++
++info-target-libiberty: \
++    configure-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing info in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           info) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-dvi-target-libiberty dvi-target-libiberty
++maybe-dvi-target-libiberty:
++@if target-libiberty
++maybe-dvi-target-libiberty: dvi-target-libiberty
++
++dvi-target-libiberty: \
++    configure-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing dvi in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           dvi) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-pdf-target-libiberty pdf-target-libiberty
++maybe-pdf-target-libiberty:
++@if target-libiberty
++maybe-pdf-target-libiberty: pdf-target-libiberty
++
++pdf-target-libiberty: \
++    configure-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           pdf) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-html-target-libiberty html-target-libiberty
++maybe-html-target-libiberty:
++@if target-libiberty
++maybe-html-target-libiberty: html-target-libiberty
++
++html-target-libiberty: \
++    configure-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing html in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           html) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-TAGS-target-libiberty TAGS-target-libiberty
++maybe-TAGS-target-libiberty:
++@if target-libiberty
++maybe-TAGS-target-libiberty: TAGS-target-libiberty
++
++TAGS-target-libiberty: \
++    configure-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing TAGS in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           TAGS) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-install-info-target-libiberty install-info-target-libiberty
++maybe-install-info-target-libiberty:
++@if target-libiberty
++maybe-install-info-target-libiberty: install-info-target-libiberty
++
++install-info-target-libiberty: \
++    configure-target-libiberty \
++    info-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-info in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-info) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-install-pdf-target-libiberty install-pdf-target-libiberty
++maybe-install-pdf-target-libiberty:
++@if target-libiberty
++maybe-install-pdf-target-libiberty: install-pdf-target-libiberty
++
++install-pdf-target-libiberty: \
++    configure-target-libiberty \
++    pdf-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-pdf) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-install-html-target-libiberty install-html-target-libiberty
++maybe-install-html-target-libiberty:
++@if target-libiberty
++maybe-install-html-target-libiberty: install-html-target-libiberty
++
++install-html-target-libiberty: \
++    configure-target-libiberty \
++    html-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-html) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-installcheck-target-libiberty installcheck-target-libiberty
++maybe-installcheck-target-libiberty:
++@if target-libiberty
++maybe-installcheck-target-libiberty: installcheck-target-libiberty
++
++installcheck-target-libiberty: \
++    configure-target-libiberty 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing installcheck in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           installcheck) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-mostlyclean-target-libiberty mostlyclean-target-libiberty
++maybe-mostlyclean-target-libiberty:
++@if target-libiberty
++maybe-mostlyclean-target-libiberty: mostlyclean-target-libiberty
++
++mostlyclean-target-libiberty: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           mostlyclean) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-clean-target-libiberty clean-target-libiberty
++maybe-clean-target-libiberty:
++@if target-libiberty
++maybe-clean-target-libiberty: clean-target-libiberty
++
++clean-target-libiberty: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing clean in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           clean) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-distclean-target-libiberty distclean-target-libiberty
++maybe-distclean-target-libiberty:
++@if target-libiberty
++maybe-distclean-target-libiberty: distclean-target-libiberty
++
++distclean-target-libiberty: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           distclean) \
++	  || exit 1
++
++@endif target-libiberty
++
++.PHONY: maybe-maintainer-clean-target-libiberty maintainer-clean-target-libiberty
++maybe-maintainer-clean-target-libiberty:
++@if target-libiberty
++maybe-maintainer-clean-target-libiberty: maintainer-clean-target-libiberty
++
++maintainer-clean-target-libiberty: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libiberty/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libiberty"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libiberty && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           maintainer-clean) \
++	  || exit 1
++
++@endif target-libiberty
++
++
++
++
++
+ .PHONY: configure-target-libjava maybe-configure-target-libjava
+ maybe-configure-target-libjava:
+ @if gcc-bootstrap
+@@ -45412,13 +45770,8 @@ maybe-check-target-libada:
+ @if target-libada
+ maybe-check-target-libada: check-target-libada
+ 
++# Dummy target for uncheckable module.
+ check-target-libada:
+-	@: $(MAKE); $(unstage)
+-	@r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(TARGET_FLAGS_TO_PASS)   check)
+ 
+ @endif target-libada
+ 
+@@ -45427,13 +45780,8 @@ maybe-install-target-libada:
+ @if target-libada
+ maybe-install-target-libada: install-target-libada
+ 
+-install-target-libada: installdirs
+-	@: $(MAKE); $(unstage)
+-	@r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install)
++# Dummy target for uninstallable.
++install-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45442,13 +45790,8 @@ maybe-install-strip-target-libada:
+ @if target-libada
+ maybe-install-strip-target-libada: install-strip-target-libada
+ 
+-install-strip-target-libada: installdirs
+-	@: $(MAKE); $(unstage)
+-	@r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install-strip)
++# Dummy target for uninstallable.
++install-strip-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45459,24 +45802,8 @@ maybe-info-target-libada:
+ @if target-libada
+ maybe-info-target-libada: info-target-libada
+ 
+-info-target-libada: \
+-    configure-target-libada 
+-	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing info in $(TARGET_SUBDIR)/libada"; \
+-	for flag in $(EXTRA_TARGET_FLAGS); do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	           info) \
+-	  || exit 1
++# libada doesn't support info.
++info-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45485,24 +45812,8 @@ maybe-dvi-target-libada:
+ @if target-libada
+ maybe-dvi-target-libada: dvi-target-libada
+ 
+-dvi-target-libada: \
+-    configure-target-libada 
+-	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing dvi in $(TARGET_SUBDIR)/libada"; \
+-	for flag in $(EXTRA_TARGET_FLAGS); do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	           dvi) \
+-	  || exit 1
++# libada doesn't support dvi.
++dvi-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45537,24 +45848,8 @@ maybe-html-target-libada:
+ @if target-libada
+ maybe-html-target-libada: html-target-libada
+ 
+-html-target-libada: \
+-    configure-target-libada 
+-	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing html in $(TARGET_SUBDIR)/libada"; \
+-	for flag in $(EXTRA_TARGET_FLAGS); do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	           html) \
+-	  || exit 1
++# libada doesn't support html.
++html-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45563,24 +45858,8 @@ maybe-TAGS-target-libada:
+ @if target-libada
+ maybe-TAGS-target-libada: TAGS-target-libada
+ 
+-TAGS-target-libada: \
+-    configure-target-libada 
+-	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing TAGS in $(TARGET_SUBDIR)/libada"; \
+-	for flag in $(EXTRA_TARGET_FLAGS); do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	           TAGS) \
+-	  || exit 1
++# libada doesn't support TAGS.
++TAGS-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45589,25 +45868,8 @@ maybe-install-info-target-libada:
+ @if target-libada
+ maybe-install-info-target-libada: install-info-target-libada
+ 
+-install-info-target-libada: \
+-    configure-target-libada \
+-    info-target-libada 
+-	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-info in $(TARGET_SUBDIR)/libada"; \
+-	for flag in $(EXTRA_TARGET_FLAGS); do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	           install-info) \
+-	  || exit 1
++# libada doesn't support install-info.
++install-info-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -45670,24 +45932,8 @@ maybe-installcheck-target-libada:
+ @if target-libada
+ maybe-installcheck-target-libada: installcheck-target-libada
+ 
+-installcheck-target-libada: \
+-    configure-target-libada 
+-	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada/Makefile ] || exit 0; \
+-	r=`${PWD_COMMAND}`; export r; \
+-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+-	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing installcheck in $(TARGET_SUBDIR)/libada"; \
+-	for flag in $(EXTRA_TARGET_FLAGS); do \
+-	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+-	done; \
+-	(cd $(TARGET_SUBDIR)/libada && \
+-	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
+-	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
+-	          "RANLIB=$${RANLIB}" \
+-	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
+-	           installcheck) \
+-	  || exit 1
++# libada doesn't support installcheck.
++installcheck-target-libada:
+ 
+ @endif target-libada
+ 
+@@ -49993,6 +50239,7 @@ configure-target-libtermcap: stage_last
+ configure-target-winsup: stage_last
+ configure-target-libgloss: stage_last
+ configure-target-libffi: stage_last
++configure-target-libiberty: stage_last
+ configure-target-libjava: stage_last
+ configure-target-zlib: stage_last
+ configure-target-boehm-gc: stage_last
+@@ -50027,6 +50274,7 @@ configure-target-libtermcap: maybe-all-g
+ configure-target-winsup: maybe-all-gcc
+ configure-target-libgloss: maybe-all-gcc
+ configure-target-libffi: maybe-all-gcc
++configure-target-libiberty: maybe-all-gcc
+ configure-target-libjava: maybe-all-gcc
+ configure-target-zlib: maybe-all-gcc
+ configure-target-boehm-gc: maybe-all-gcc
+@@ -50403,6 +50651,7 @@ all-stage3-fixincludes: maybe-all-stage3
+ all-stage4-fixincludes: maybe-all-stage4-libiberty
+ all-stageprofile-fixincludes: maybe-all-stageprofile-libiberty
+ all-stagefeedback-fixincludes: maybe-all-stagefeedback-libiberty
++all-target-libada: maybe-all-gcc
+ all-gnattools: maybe-all-target-libada
+ all-gnattools: maybe-all-target-libstdc++-v3
+ all-lto-plugin: maybe-all-libiberty
+@@ -50994,6 +51243,7 @@ configure-target-libtermcap: maybe-all-t
+ configure-target-winsup: maybe-all-target-libgcc
+ configure-target-libgloss: maybe-all-target-libgcc
+ configure-target-libffi: maybe-all-target-libgcc
++configure-target-libiberty: maybe-all-target-libgcc
+ configure-target-libjava: maybe-all-target-libgcc
+ configure-target-zlib: maybe-all-target-libgcc
+ configure-target-boehm-gc: maybe-all-target-libgcc
+@@ -51041,6 +51291,7 @@ configure-target-winsup: maybe-all-targe
+ configure-target-libffi: maybe-all-target-newlib maybe-all-target-libgloss
+ configure-target-libffi: maybe-all-target-libstdc++-v3
+ 
++
+ configure-target-libjava: maybe-all-target-newlib maybe-all-target-libgloss
+ configure-target-libjava: maybe-all-target-libstdc++-v3
+ 
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -148,6 +148,11 @@ libgcj="target-libffi \
+ 	target-zlib \
+ 	target-libjava"
+ 
++case "${target}" in
++  hppa64-*linux*) ;;
++  *) target_libiberty="target-libiberty";;
++esac
++
+ # these libraries are built for the target environment, and are built after
+ # the host libraries and the host tools (which may be a cross compiler)
+ # Note that libiberty is not a target library.
+@@ -171,6 +176,7 @@ target_libraries="target-libgcc \
+ 		${libgcj} \
+ 		target-libobjc \
+ 		target-libada \
++		${target_libiberty} \
+ 		target-libgo"
+ 
+ # these tools are built using the target libraries, and are intended to
+Index: b/src/gcc/ada/gcc-interface/Make-lang.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Make-lang.in
++++ b/src/gcc/ada/gcc-interface/Make-lang.in
+@@ -58,11 +58,7 @@ WARN_ADAFLAGS= -W -Wall
+ # need to be built by a recent/matching native so we might as well leave the
+ # checks fully active.
+ 
+-ifeq ($(CROSS),)
+ ADAFLAGS= $(COMMON_ADAFLAGS) -gnatwns
+-else
+-ADAFLAGS= $(COMMON_ADAFLAGS)
+-endif
+ 
+ ALL_ADAFLAGS = \
+   $(CFLAGS) $(ADA_CFLAGS) $(ADAFLAGS) $(CHECKING_ADAFLAGS) $(WARN_ADAFLAGS)
--- gcc-6-6.4.0.orig/debian/patches/ada-link-shlib.diff
+++ gcc-6-6.4.0/debian/patches/ada-link-shlib.diff
@@ -0,0 +1,89 @@
+# DP: In gnatlink, pass the options and libraries after objects to the
+# DP: linker to avoid link failures with --as-needed. Closes: #680292.
+
+Index: b/src/gcc/ada/mlib-tgt-specific-linux.adb
+===================================================================
+--- a/src/gcc/ada/mlib-tgt-specific-linux.adb
++++ b/src/gcc/ada/mlib-tgt-specific-linux.adb
+@@ -81,19 +81,54 @@ package body MLib.Tgt.Specific is
+       Version_Arg          : String_Access;
+       Symbolic_Link_Needed : Boolean := False;
+ 
++      N_Options    : Argument_List := Options;
++      Options_Last : Natural := N_Options'Last;
++      --  After moving -lxxx to Options_2, N_Options up to index Options_Last
++      --  will contain the Options to pass to MLib.Utl.Gcc.
++
++      Real_Options_2 : Argument_List (1 .. Options'Length);
++      Real_Options_2_Last : Natural := 0;
++      --  Real_Options_2 up to index Real_Options_2_Last will contain the
++      --  Options_2 to pass to MLib.Utl.Gcc.
++
+    begin
+       if Opt.Verbose_Mode then
+          Write_Str ("building relocatable shared library ");
+          Write_Line (Lib_Path);
+       end if;
+ 
++      --  Move all -lxxx to Options_2
++
++      declare
++         Index : Natural := N_Options'First;
++         Arg   : String_Access;
++
++      begin
++         while Index <= Options_Last loop
++            Arg := N_Options (Index);
++
++            if Arg'Length > 2
++              and then Arg (Arg'First .. Arg'First + 1) = "-l"
++            then
++               Real_Options_2_Last := Real_Options_2_Last + 1;
++               Real_Options_2 (Real_Options_2_Last) := Arg;
++               N_Options (Index .. Options_Last - 1) :=
++                 N_Options (Index + 1 .. Options_Last);
++               Options_Last := Options_Last - 1;
++
++            else
++               Index := Index + 1;
++            end if;
++         end loop;
++      end;
++
+       if Lib_Version = "" then
+          Utl.Gcc
+            (Output_File => Lib_Path,
+             Objects     => Ofiles,
+-            Options     => Options,
++            Options     => N_Options (N_Options'First .. Options_Last),
+             Driver_Name => Driver_Name,
+-            Options_2   => No_Argument_List);
++            Options_2   => Real_Options_2 (1 .. Real_Options_2_Last));
+ 
+       else
+          declare
+@@ -111,18 +146,20 @@ package body MLib.Tgt.Specific is
+                Utl.Gcc
+                  (Output_File => Lib_Version,
+                   Objects     => Ofiles,
+-                  Options     => Options & Version_Arg,
++                  Options     => N_Options (N_Options'First .. Options_Last)
++                                 & Version_Arg,
+                   Driver_Name => Driver_Name,
+-                  Options_2   => No_Argument_List);
++                  Options_2   => Real_Options_2 (1 .. Real_Options_2_Last));
+                Symbolic_Link_Needed := Lib_Version /= Lib_Path;
+ 
+             else
+                Utl.Gcc
+                  (Output_File => Lib_Dir & Directory_Separator & Lib_Version,
+                   Objects     => Ofiles,
+-                  Options     => Options & Version_Arg,
++                  Options     => N_Options (N_Options'First .. Options_Last)
++                                 & Version_Arg,
+                   Driver_Name => Driver_Name,
+-                  Options_2   => No_Argument_List);
++                  Options_2   => Real_Options_2 (1 .. Real_Options_2_Last));
+                Symbolic_Link_Needed :=
+                  Lib_Dir & Directory_Separator & Lib_Version /= Lib_Path;
+             end if;
--- gcc-6-6.4.0.orig/debian/patches/ada-m68k.diff
+++ gcc-6-6.4.0/debian/patches/ada-m68k.diff
@@ -0,0 +1,259 @@
+gcc/ada/
+
+2011-10-12  Mikael Pettersson  <mikpe@it.uu.se>
+
+	PR ada/48835
+	* gcc-interface/Makefile.in: Add support for m68k-linux.
+	* system-linux-m68k.ads: New file based on system-linux-ppc.ads
+	and system-vxworks-m68k.ads.
+	* s-memory.adb (Gnat_Malloc): New wrapper around Alloc, returning
+	the memory address as a pointer not an integer.
+	Add Gnat_Malloc -> __gnat_malloc export.
+	* s-memory.ads: Remove Alloc -> __gnat_malloc export.
+
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -2084,6 +2084,35 @@ ifeq ($(strip $(filter-out hppa% linux%,
+   LIBRARY_VERSION := $(LIB_VERSION)
+ endif
+ 
++# M68K Linux
++ifeq ($(strip $(filter-out m68k% linux%,$(arch) $(osys))),)
++  LIBGNAT_TARGET_PAIRS = \
++  a-intnam.ads<a-intnam-linux.ads \
++  s-inmaop.adb<s-inmaop-posix.adb \
++  s-intman.adb<s-intman-posix.adb \
++  s-linux.ads<s-linux.ads \
++  s-osinte.adb<s-osinte-posix.adb \
++  s-osinte.ads<s-osinte-linux.ads \
++  s-osprim.adb<s-osprim-posix.adb \
++  s-taprop.adb<s-taprop-linux.adb \
++  s-tasinf.ads<s-tasinf-linux.ads \
++  s-tasinf.adb<s-tasinf-linux.adb \
++  s-taspri.ads<s-taspri-posix.ads \
++  s-tpopsp.adb<s-tpopsp-posix-foreign.adb \
++  system.ads<system-linux-m68k.ads
++
++  TOOLS_TARGET_PAIRS =  \
++    mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \
++    indepsw.adb<indepsw-gnu.adb
++
++  EXTRA_GNATRTL_TASKING_OBJS=s-linux.o
++  EH_MECHANISM=-gcc
++  THREADSLIB = -lpthread
++  GNATLIB_SHARED = gnatlib-shared-dual
++  GMEM_LIB = gmemlib
++  LIBRARY_VERSION := $(LIB_VERSION)
++endif
++
+ # SH4 Linux
+ ifeq ($(strip $(filter-out sh4% linux%,$(target_cpu) $(target_os))),)
+   LIBGNAT_TARGET_PAIRS = \
+Index: b/src/gcc/ada/s-memory.adb
+===================================================================
+--- a/src/gcc/ada/s-memory.adb
++++ b/src/gcc/ada/s-memory.adb
+@@ -47,6 +47,7 @@ with Ada.Exceptions;
+ with System.Soft_Links;
+ with System.Parameters;
+ with System.CRTL;
++with Ada.Unchecked_Conversion;
+ 
+ package body System.Memory is
+ 
+@@ -100,6 +101,22 @@ package body System.Memory is
+       return Result;
+    end Alloc;
+ 
++   type Char_Ptr is access all Character;
++   pragma Convention (C, Char_Ptr);
++   pragma No_Strict_Aliasing (Char_Ptr);
++
++   function To_Char_Ptr is
++      new Ada.Unchecked_Conversion (System.Address, Char_Ptr);
++
++   --  The function exported as __gnat_malloc MUST return a pointer type.
++   function Gnat_Malloc (Size : size_t) return Char_Ptr;
++   pragma Export (C, Gnat_Malloc, "__gnat_malloc");
++
++   function Gnat_Malloc (Size : size_t) return Char_Ptr is
++   begin
++      return To_Char_Ptr (Alloc (Size));
++   end Gnat_Malloc;
++
+    ----------
+    -- Free --
+    ----------
+Index: b/src/gcc/ada/s-memory.ads
+===================================================================
+--- a/src/gcc/ada/s-memory.ads
++++ b/src/gcc/ada/s-memory.ads
+@@ -100,7 +100,6 @@ private
+ 
+    --  The following names are used from the generated compiler code
+ 
+-   pragma Export (C, Alloc,   "__gnat_malloc");
+    pragma Export (C, Free,    "__gnat_free");
+    pragma Export (C, Realloc, "__gnat_realloc");
+ 
+Index: b/src/gcc/ada/system-linux-m68k.ads
+===================================================================
+--- /dev/null
++++ b/src/gcc/ada/system-linux-m68k.ads
+@@ -0,0 +1,154 @@
++------------------------------------------------------------------------------
++--                                                                          --
++--                        GNAT RUN-TIME COMPONENTS                          --
++--                                                                          --
++--                               S Y S T E M                                --
++--                                                                          --
++--                                 S p e c                                  --
++--                         (GNU/Linux/m68k Version)                         --
++--                                                                          --
++--          Copyright (C) 2014, Free Software Foundation, Inc.              --
++--                                                                          --
++-- This specification is derived from the Ada Reference Manual for use with --
++-- GNAT. The copyright notice above, and the license provisions that follow --
++-- apply solely to the  contents of the part following the private keyword. --
++--                                                                          --
++-- GNAT is free software;  you can  redistribute it  and/or modify it under --
++-- terms of the  GNU General Public License as published  by the Free Soft- --
++-- ware  Foundation;  either version 3,  or (at your option) any later ver- --
++-- sion.  GNAT is distributed in the hope that it will be useful, but WITH- --
++-- OUT ANY WARRANTY;  without even the  implied warranty of MERCHANTABILITY --
++-- or FITNESS FOR A PARTICULAR PURPOSE.                                     --
++--                                                                          --
++-- As a special exception under Section 7 of GPL version 3, you are granted --
++-- additional permissions described in the GCC Runtime Library Exception,   --
++-- version 3.1, as published by the Free Software Foundation.               --
++--                                                                          --
++-- You should have received a copy of the GNU General Public License and    --
++-- a copy of the GCC Runtime Library Exception along with this program;     --
++-- see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see    --
++-- <http://www.gnu.org/licenses/>.                                          --
++--                                                                          --
++-- GNAT was originally developed  by the GNAT team at  New York University. --
++-- Extensive contributions were provided by Ada Core Technologies Inc.      --
++--                                                                          --
++------------------------------------------------------------------------------
++
++package System is
++   pragma Pure;
++   --  Note that we take advantage of the implementation permission to make
++   --  this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada
++   --  2005, this is Pure in any case (AI-362).
++
++   type Name is (SYSTEM_NAME_GNAT);
++   System_Name : constant Name := SYSTEM_NAME_GNAT;
++
++   --  System-Dependent Named Numbers
++
++   Min_Int               : constant := Long_Long_Integer'First;
++   Max_Int               : constant := Long_Long_Integer'Last;
++
++   Max_Binary_Modulus    : constant := 2 ** Long_Long_Integer'Size;
++   Max_Nonbinary_Modulus : constant := 2 ** Integer'Size - 1;
++
++   Max_Base_Digits       : constant := Long_Long_Float'Digits;
++   Max_Digits            : constant := Long_Long_Float'Digits;
++
++   Max_Mantissa          : constant := 63;
++   Fine_Delta            : constant := 2.0 ** (-Max_Mantissa);
++
++   Tick                  : constant := 0.000_001;
++
++   --  Storage-related Declarations
++
++   type Address is private;
++   pragma Preelaborable_Initialization (Address);
++   Null_Address : constant Address;
++
++   Storage_Unit : constant := 8;
++   Word_Size    : constant := 32;
++   Memory_Size  : constant := 2 ** 32;
++
++   --  Address comparison
++
++   function "<"  (Left, Right : Address) return Boolean;
++   function "<=" (Left, Right : Address) return Boolean;
++   function ">"  (Left, Right : Address) return Boolean;
++   function ">=" (Left, Right : Address) return Boolean;
++   function "="  (Left, Right : Address) return Boolean;
++
++   pragma Import (Intrinsic, "<");
++   pragma Import (Intrinsic, "<=");
++   pragma Import (Intrinsic, ">");
++   pragma Import (Intrinsic, ">=");
++   pragma Import (Intrinsic, "=");
++
++   --  Other System-Dependent Declarations
++
++   type Bit_Order is (High_Order_First, Low_Order_First);
++   Default_Bit_Order : constant Bit_Order := High_Order_First;
++   pragma Warnings (Off, Default_Bit_Order); -- kill constant condition warning
++
++   --  Priority-related Declarations (RM D.1)
++
++   --  Is the following actually true for GNU/Linux/m68k?
++   --
++   --  0 .. 98 corresponds to the system priority range 1 .. 99.
++   --
++   --  If the scheduling policy is SCHED_FIFO or SCHED_RR the runtime makes use
++   --  of the entire range provided by the system.
++   --
++   --  If the scheduling policy is SCHED_OTHER the only valid system priority
++   --  is 1 and other values are simply ignored.
++
++   Max_Priority           : constant Positive := 97;
++   Max_Interrupt_Priority : constant Positive := 98;
++
++   subtype Any_Priority       is Integer      range  0 .. 98;
++   subtype Priority           is Any_Priority range  0 .. 97;
++   subtype Interrupt_Priority is Any_Priority range 98 .. 98;
++
++   Default_Priority : constant Priority := 48;
++
++private
++
++   type Address is mod Memory_Size;
++   Null_Address : constant Address := 0;
++
++   --------------------------------------
++   -- System Implementation Parameters --
++   --------------------------------------
++
++   --  These parameters provide information about the target that is used
++   --  by the compiler. They are in the private part of System, where they
++   --  can be accessed using the special circuitry in the Targparm unit
++   --  whose source should be consulted for more detailed descriptions
++   --  of the individual switch values.
++
++   Backend_Divide_Checks     : constant Boolean := False;
++   Backend_Overflow_Checks   : constant Boolean := False;
++   Command_Line_Args         : constant Boolean := True;
++   Configurable_Run_Time     : constant Boolean := False;
++   Denorm                    : constant Boolean := True;
++   Duration_32_Bits          : constant Boolean := False;
++   Exit_Status_Supported     : constant Boolean := True;
++   Fractional_Fixed_Ops      : constant Boolean := False;
++   Frontend_Layout           : constant Boolean := False;
++   Machine_Overflows         : constant Boolean := False;
++   Machine_Rounds            : constant Boolean := True;
++   Preallocated_Stacks       : constant Boolean := False;
++   Signed_Zeros              : constant Boolean := True;
++   Stack_Check_Default       : constant Boolean := False;
++   Stack_Check_Probes        : constant Boolean := False;
++   Stack_Check_Limits        : constant Boolean := False;
++   Support_Aggregates        : constant Boolean := True;
++   Support_Atomic_Primitives : constant Boolean := True;
++   Support_Composite_Assign  : constant Boolean := True;
++   Support_Composite_Compare : constant Boolean := True;
++   Support_Long_Shifts       : constant Boolean := True;
++   Always_Compatible_Rep     : constant Boolean := False;
++   Suppress_Standard_Library : constant Boolean := False;
++   Use_Ada_Main_Program_Name : constant Boolean := False;
++   ZCX_By_Default            : constant Boolean := True;
++
++end System;
--- gcc-6-6.4.0.orig/debian/patches/ada-mips.diff
+++ gcc-6-6.4.0/debian/patches/ada-mips.diff
@@ -0,0 +1,23 @@
+# DP: Improve support for mips.
+
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -1906,10 +1906,15 @@ ifeq ($(strip $(filter-out mips linux%,$
+   s-taprop.adb<s-taprop-linux.adb \
+   s-tasinf.ads<s-tasinf-linux.ads \
+   s-tasinf.adb<s-tasinf-linux.adb \
+-  s-taspri.ads<s-taspri-posix.ads \
++  s-taspri.ads<s-taspri-posix-noaltstack.ads \
+   s-tpopsp.adb<s-tpopsp-posix-foreign.adb \
+   system.ads<system-linux-mips.ads
+ 
++  TOOLS_TARGET_PAIRS =  \
++    mlib-tgt-specific.adb<mlib-tgt-specific-linux.adb \
++    indepsw.adb<indepsw-gnu.adb
++
++  EXTRA_GNATRTL_TASKING_OBJS=s-linux.o
+   EH_MECHANISM=-gcc
+   THREADSLIB = -lpthread
+   GNATLIB_SHARED = gnatlib-shared-dual
--- gcc-6-6.4.0.orig/debian/patches/ada-nobiarch-check.diff
+++ gcc-6-6.4.0/debian/patches/ada-nobiarch-check.diff
@@ -0,0 +1,20 @@
+# DP: For biarch builds, disable the gnat testsuite for the non-default
+# architecture (no biarch support in gnat yet).
+
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -4510,7 +4510,11 @@
+ 	if [ -f $${rootme}/../expect/expect ] ; then  \
+ 	   TCL_LIBRARY=`cd .. ; cd $${srcdir}/../tcl/library ; ${PWD_COMMAND}` ; \
+ 	    export TCL_LIBRARY ; fi ; \
+-	$(RUNTEST) --tool $* $(RUNTESTFLAGS))
++	if [ "$*" = gnat ]; then \
++	  runtestflags="`echo '$(RUNTESTFLAGS)' | sed -r 's/,-m(32|64|x32)//g;s/,-mabi=(n32|64)//g'`"; \
++	  case "$$runtestflags" in *\\{\\}) runtestflags=; esac; \
++	fi; \
++	$(RUNTEST) --tool $* $$runtestflags)
+ 
+ $(patsubst %,%-subtargets,$(filter-out $(lang_checks_parallelized),$(lang_checks))): check-%-subtargets:
+ 	@echo check-$*
--- gcc-6-6.4.0.orig/debian/patches/ada-revert-pr63225.diff
+++ gcc-6-6.4.0/debian/patches/ada-revert-pr63225.diff
@@ -0,0 +1,97 @@
+# DP: Revert the changes made to allow bootstrapping with -fno-inline.
+# DP: We allow inlining during bootstrap and this change breaks aliversion compatibility
+# DP: with earlier uploads of libgnatvsn5.  This patch shall be removed in the next
+# DP: major version of GNAT.
+
+Index: b/src/gcc/ada/uintp.adb
+===================================================================
+--- a/src/gcc/ada/uintp.adb
++++ b/src/gcc/ada/uintp.adb
+@@ -171,6 +171,22 @@ package body Uintp is
+    --  If Discard_Quotient is True, Quotient is set to No_Uint
+    --  If Discard_Remainder is True, Remainder is set to No_Uint
+ 
++   function Vector_To_Uint
++     (In_Vec   : UI_Vector;
++      Negative : Boolean) return Uint;
++   --  Functions that calculate values in UI_Vectors, call this function to
++   --  create and return the Uint value. In_Vec contains the multiple precision
++   --  (Base) representation of a non-negative value. Leading zeroes are
++   --  permitted. Negative is set if the desired result is the negative of the
++   --  given value. The result will be either the appropriate directly
++   --  represented value, or a table entry in the proper canonical format is
++   --  created and returned.
++   --
++   --  Note that Init_Operand puts a signed value in the result vector, but
++   --  Vector_To_Uint is always presented with a non-negative value. The
++   --  processing of signs is something that is done by the caller before
++   --  calling Vector_To_Uint.
++
+    ------------
+    -- Direct --
+    ------------
+Index: b/src/gcc/ada/uintp.ads
+===================================================================
+--- a/src/gcc/ada/uintp.ads
++++ b/src/gcc/ada/uintp.ads
+@@ -90,18 +90,6 @@ package Uintp is
+    Uint_Minus_80  : constant Uint;
+    Uint_Minus_128 : constant Uint;
+ 
+-   type UI_Vector is array (Pos range <>) of Int;
+-   --  Vector containing the integer values of a Uint value
+-
+-   --  Note: An earlier version of this package used pointers of arrays of Ints
+-   --  (dynamically allocated) for the Uint type. The change leads to a few
+-   --  less natural idioms used throughout this code, but eliminates all uses
+-   --  of the heap except for the table package itself. For example, Uint
+-   --  parameters are often converted to UI_Vectors for internal manipulation.
+-   --  This is done by creating the local UI_Vector using the function N_Digits
+-   --  on the Uint to find the size needed for the vector, and then calling
+-   --  Init_Operand to copy the values out of the table into the vector.
+-
+    -----------------
+    -- Subprograms --
+    -----------------
+@@ -264,22 +252,6 @@ package Uintp is
+    --  function is used for capacity checks, and it can be one bit off
+    --  without affecting its usage.
+ 
+-   function Vector_To_Uint
+-     (In_Vec   : UI_Vector;
+-      Negative : Boolean) return Uint;
+-   --  Functions that calculate values in UI_Vectors, call this function to
+-   --  create and return the Uint value. In_Vec contains the multiple precision
+-   --  (Base) representation of a non-negative value. Leading zeroes are
+-   --  permitted. Negative is set if the desired result is the negative of the
+-   --  given value. The result will be either the appropriate directly
+-   --  represented value, or a table entry in the proper canonical format is
+-   --  created and returned.
+-   --
+-   --  Note that Init_Operand puts a signed value in the result vector, but
+-   --  Vector_To_Uint is always presented with a non-negative value. The
+-   --  processing of signs is something that is done by the caller before
+-   --  calling Vector_To_Uint.
+-
+    ---------------------
+    -- Output Routines --
+    ---------------------
+@@ -527,6 +499,18 @@ private
+    --  UI_Vector is defined for this purpose and some internal subprograms
+    --  used for converting from one to the other are defined.
+ 
++   type UI_Vector is array (Pos range <>) of Int;
++   --  Vector containing the integer values of a Uint value
++
++   --  Note: An earlier version of this package used pointers of arrays of Ints
++   --  (dynamically allocated) for the Uint type. The change leads to a few
++   --  less natural idioms used throughout this code, but eliminates all uses
++   --  of the heap except for the table package itself. For example, Uint
++   --  parameters are often converted to UI_Vectors for internal manipulation.
++   --  This is done by creating the local UI_Vector using the function N_Digits
++   --  on the Uint to find the size needed for the vector, and then calling
++   --  Init_Operand to copy the values out of the table into the vector.
++
+    type Uint_Entry is record
+       Length : Pos;
+       --  Length of entry in Udigits table in digits (i.e. in words)
--- gcc-6-6.4.0.orig/debian/patches/ada-s-osinte-gnu.ads.diff
+++ gcc-6-6.4.0/debian/patches/ada-s-osinte-gnu.ads.diff
@@ -0,0 +1,752 @@
+--- /dev/null	2012-01-30 20:41:15.189616186 +0100
++++ b/src/gcc/ada/s-osinte-gnu.ads	2012-04-11 19:34:45.000000000 +0200
+@@ -0,0 +1,749 @@
++------------------------------------------------------------------------------
++--                                                                          --
++--                GNU ADA RUN-TIME LIBRARY (GNARL) COMPONENTS               --
++--                                                                          --
++--                   S Y S T E M . O S _ I N T E R F A C E                  --
++--                                                                          --
++--                                  S p e c                                 --
++--                                                                          --
++--             Copyright (C) 1991-1994, Florida State University            --
++--          Copyright (C) 1995-2011, Free Software Foundation, Inc.         --
++--                                                                          --
++-- GNARL is free software; you can  redistribute it  and/or modify it under --
++-- terms of the  GNU General Public License as published  by the Free Soft- --
++-- ware  Foundation;  either version 2,  or (at your option) any later ver- --
++-- sion. GNARL is distributed in the hope that it will be useful, but WITH- --
++-- OUT ANY WARRANTY;  without even the  implied warranty of MERCHANTABILITY --
++-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License --
++-- for  more details.  You should have  received  a copy of the GNU General --
++-- Public License  distributed with GNARL; see file COPYING.  If not, write --
++-- to  the  Free Software Foundation,  51  Franklin  Street,  Fifth  Floor, --
++-- Boston, MA 02110-1301, USA.                                              --
++--                                                                          --
++-- As a special exception,  if other files  instantiate  generics from this --
++-- unit, or you link  this unit with other files  to produce an executable, --
++-- this  unit  does not  by itself cause  the resulting  executable  to  be --
++-- covered  by the  GNU  General  Public  License.  This exception does not --
++-- however invalidate  any other reasons why  the executable file  might be --
++-- covered by the  GNU Public License.                                      --
++--                                                                          --
++-- GNARL was developed by the GNARL team at Florida State University.       --
++-- Extensive contributions were provided by Ada Core Technologies, Inc.     --
++--                                                                          --
++------------------------------------------------------------------------------
++
++--  This is the GNU/Hurd version of this package
++
++--  This package encapsulates all direct interfaces to OS services
++--  that are needed by children of System.
++
++--  PLEASE DO NOT add any with-clauses to this package or remove the pragma
++--  Preelaborate. This package is designed to be a bottom-level (leaf) package
++
++with Interfaces.C;
++with Unchecked_Conversion;
++
++package System.OS_Interface is
++   pragma Preelaborate;
++
++   pragma Linker_Options ("-lpthread");
++   pragma Linker_Options ("-lrt");
++
++   subtype int            is Interfaces.C.int;
++   subtype char           is Interfaces.C.char;
++   subtype short          is Interfaces.C.short;
++   subtype long           is Interfaces.C.long;
++   subtype unsigned       is Interfaces.C.unsigned;
++   subtype unsigned_short is Interfaces.C.unsigned_short;
++   subtype unsigned_long  is Interfaces.C.unsigned_long;
++   subtype unsigned_char  is Interfaces.C.unsigned_char;
++   subtype plain_char     is Interfaces.C.plain_char;
++   subtype size_t         is Interfaces.C.size_t;
++
++   -----------
++   -- Errno --
++   -----------
++   --  From /usr/include/i386-gnu/bits/errno.h
++
++   function errno return int;
++   pragma Import (C, errno, "__get_errno");
++
++   EAGAIN   : constant := 1073741859;
++   EINTR    : constant := 1073741828;
++   EINVAL   : constant := 1073741846;
++   ENOMEM   : constant := 1073741836;
++   EPERM    : constant := 1073741825;
++   ETIMEDOUT    : constant := 1073741884;
++
++   -------------
++   -- Signals --
++   -------------
++   --  From /usr/include/i386-gnu/bits/signum.h
++
++   Max_Interrupt : constant := 32;
++   type Signal is new int range 0 .. Max_Interrupt;
++   for Signal'Size use int'Size;
++
++   SIGHUP     : constant := 1; --  hangup
++   SIGINT     : constant := 2; --  interrupt (rubout)
++   SIGQUIT    : constant := 3; --  quit (ASCD FS)
++   SIGILL     : constant := 4; --  illegal instruction (not reset)
++   SIGTRAP    : constant := 5; --  trace trap (not reset)
++   SIGIOT     : constant := 6; --  IOT instruction
++   SIGABRT    : constant := 6; --  used by abort, replace SIGIOT in the  future
++   SIGEMT     : constant := 7; --  EMT instruction
++   SIGFPE     : constant := 8; --  floating point exception
++   SIGKILL    : constant := 9; --  kill (cannot be caught or ignored)
++   SIGBUS     : constant := 10; --  bus error
++   SIGSEGV    : constant := 11; --  segmentation violation
++   SIGSYS     : constant := 12; --  bad argument to system call
++   SIGPIPE    : constant := 13; --  write on a pipe with no one to read it
++   SIGALRM    : constant := 14; --  alarm clock
++   SIGTERM    : constant := 15; --  software termination signal from kill
++   SIGURG     : constant := 16; --  urgent condition on IO channel
++   SIGSTOP    : constant := 17; --  stop (cannot be caught or ignored)
++   SIGTSTP    : constant := 18; --  user stop requested from tty
++   SIGCONT    : constant := 19; --  stopped process has been continued
++   SIGCLD     : constant := 20; --  alias for SIGCHLD
++   SIGCHLD    : constant := 20; --  child status change
++   SIGTTIN    : constant := 21; --  background tty read attempted
++   SIGTTOU    : constant := 22; --  background tty write attempted
++   SIGIO      : constant := 23; --  I/O possible (Solaris SIGPOLL alias)
++   SIGPOLL    : constant := 23; --  I/O possible (same as SIGIO?)
++   SIGXCPU    : constant := 24; --  CPU time limit exceeded
++   SIGXFSZ    : constant := 25; --  filesize limit exceeded
++   SIGVTALRM  : constant := 26; --  virtual timer expired
++   SIGPROF    : constant := 27; --  profiling timer expired
++   SIGWINCH   : constant := 28; --  window size change
++   SIGINFO    : constant := 29; --  information request (NetBSD/FreeBSD)
++   SIGUSR1    : constant := 30; --  user defined signal 1
++   SIGUSR2    : constant := 31; --  user defined signal 2
++   SIGLOST    : constant := 32; --  Resource lost (Sun); server died (GNU)
++--   SIGLTHRRES : constant := 32; --  GNU/LinuxThreads restart signal
++--   SIGLTHRCAN : constant := 33; --  GNU/LinuxThreads cancel signal
++--   SIGLTHRDBG : constant := 34; --  GNU/LinuxThreads debugger signal
++
++   SIGADAABORT : constant := SIGABRT;
++   --  Change this if you want to use another signal for task abort.
++   --  SIGTERM might be a good one.
++
++   type Signal_Set is array (Natural range <>) of Signal;
++
++   Unmasked    : constant Signal_Set := (
++      SIGTRAP,
++      --  To enable debugging on multithreaded applications, mark SIGTRAP to
++      --  be kept unmasked.
++
++      SIGBUS,
++
++      SIGTTIN, SIGTTOU, SIGTSTP,
++      --  Keep these three signals unmasked so that background processes
++      --  and IO behaves as normal "C" applications
++
++      SIGPROF,
++      --  To avoid confusing the profiler
++
++      SIGKILL, SIGSTOP);
++      --  These two signals actually cannot be masked;
++      --  POSIX simply won't allow it.
++
++   Reserved    : constant Signal_Set :=
++   --  I am not sure why the following signal is reserved.
++   --  I guess they are not supported by this version of GNU/Hurd.
++     (0 .. 0 => SIGVTALRM);
++
++   type sigset_t is private;
++
++   --  From /usr/include/signal.h /usr/include/i386-gnu/bits/sigset.h
++   function sigaddset (set : access sigset_t; sig : Signal) return int;
++   pragma Import (C, sigaddset, "sigaddset");
++
++   function sigdelset (set : access sigset_t; sig : Signal) return int;
++   pragma Import (C, sigdelset, "sigdelset");
++
++   function sigfillset (set : access sigset_t) return int;
++   pragma Import (C, sigfillset, "sigfillset");
++
++   function sigismember (set : access sigset_t; sig : Signal) return int;
++   pragma Import (C, sigismember, "sigismember");
++
++   function sigemptyset (set : access sigset_t) return int;
++   pragma Import (C, sigemptyset, "sigemptyset");
++
++   --  sigcontext is architecture dependent, so define it private
++   type struct_sigcontext is private;
++
++   --  From /usr/include/i386-gnu/bits/sigaction.h: Note: arg. order differs
++   type struct_sigaction is record
++      sa_handler : System.Address;
++      sa_mask    : sigset_t;
++      sa_flags   : int;
++   end record;
++   pragma Convention (C, struct_sigaction);
++
++   type struct_sigaction_ptr is access all struct_sigaction;
++
++   --  From /usr/include/i386-gnu/bits/sigaction.h
++   SIG_BLOCK   : constant := 1;
++   SIG_UNBLOCK : constant := 2;
++   SIG_SETMASK : constant := 3;
++
++   --  From /usr/include/i386-gnu/bits/signum.h
++   SIG_ERR  : constant := 1;
++   SIG_DFL  : constant := 0;
++   SIG_IGN  : constant := 1;
++   SIG_HOLD : constant := 2;
++
++   --  From /usr/include/i386-gnu/bits/sigaction.h
++   SA_SIGINFO : constant := 16#0040#;
++   SA_ONSTACK : constant := 16#0001#;
++
++   function sigaction
++     (sig  : Signal;
++      act  : struct_sigaction_ptr;
++      oact : struct_sigaction_ptr) return int;
++   pragma Import (C, sigaction, "sigaction");
++
++   ----------
++   -- Time --
++   ----------
++
++   Time_Slice_Supported : constant Boolean := True;
++   --  Indicates whether time slicing is supported (i.e SCHED_RR is supported)
++
++   type timespec is private;
++
++   function nanosleep (rqtp, rmtp : access timespec) return int;
++   pragma Import (C, nanosleep, "nanosleep");
++
++   type clockid_t is private;
++
++   CLOCK_REALTIME : constant clockid_t;
++
++   --  From: /usr/include/time.h
++   function clock_gettime
++     (clock_id : clockid_t;
++      tp       : access timespec)
++      return int;
++   pragma Import (C, clock_gettime, "clock_gettime");
++
++   function To_Duration (TS : timespec) return Duration;
++   pragma Inline (To_Duration);
++
++   function To_Timespec (D : Duration) return timespec;
++   pragma Inline (To_Timespec);
++
++   --  From: /usr/include/unistd.h
++   function sysconf (name : int) return long;
++   pragma Import (C, sysconf);
++
++   --  From /usr/include/i386-gnu/bits/confname.h
++   SC_CLK_TCK          : constant := 2;
++   SC_NPROCESSORS_ONLN : constant := 84;
++
++   -------------------------
++   -- Priority Scheduling --
++   -------------------------
++   --  From /usr/include/i386-gnu/bits/sched.h
++
++   SCHED_OTHER : constant := 0;
++   SCHED_FIFO  : constant := 1;
++   SCHED_RR    : constant := 2;
++
++   function To_Target_Priority
++     (Prio : System.Any_Priority) return Interfaces.C.int;
++   --  Maps System.Any_Priority to a POSIX priority.
++
++   -------------
++   -- Process --
++   -------------
++
++   type pid_t is private;
++
++   --  From: /usr/include/signal.h
++   function kill (pid : pid_t; sig : Signal) return int;
++   pragma Import (C, kill, "kill");
++
++   --  From: /usr/include/unistd.h
++   function getpid return pid_t;
++   pragma Import (C, getpid, "getpid");
++
++   ---------
++   -- LWP --
++   ---------
++
++   --  From: /usr/include/pthread/pthread.h
++   function lwp_self return System.Address;
++   --  lwp_self does not exist on this thread library, revert to pthread_self
++   --  which is the closest approximation (with getpid). This function is
++   --  needed to share 7staprop.adb across POSIX-like targets.
++   pragma Import (C, lwp_self, "pthread_self");
++
++   -------------
++   -- Threads --
++   -------------
++
++   type Thread_Body is access
++     function (arg : System.Address) return System.Address;
++   pragma Convention (C, Thread_Body);
++
++   function Thread_Body_Access is new
++     Unchecked_Conversion (System.Address, Thread_Body);
++
++   --  From: /usr/include/bits/pthread.h:typedef int __pthread_t;
++   --  /usr/include/pthread/pthreadtypes.h:typedef __pthread_t pthread_t;
++   type pthread_t is new unsigned_long;
++   subtype Thread_Id        is pthread_t;
++
++   function To_pthread_t is new Unchecked_Conversion
++     (unsigned_long, pthread_t);
++
++   type pthread_mutex_t     is limited private;
++   type pthread_cond_t      is limited private;
++   type pthread_attr_t      is limited private;
++   type pthread_mutexattr_t is limited private;
++   type pthread_condattr_t  is limited private;
++   type pthread_key_t       is private;
++
++   --  From /usr/include/pthread/pthreadtypes.h
++   PTHREAD_CREATE_DETACHED : constant := 1;
++   PTHREAD_CREATE_JOINABLE : constant := 0;
++
++   PTHREAD_SCOPE_PROCESS : constant := 1;
++   PTHREAD_SCOPE_SYSTEM  : constant := 0;
++
++   -----------
++   -- Stack --
++   -----------
++
++   --  From: /usr/include/i386-gnu/bits/sigstack.h
++   type stack_t is record
++      ss_sp    : System.Address;
++      ss_size  : size_t;
++      ss_flags : int;
++   end record;
++   pragma Convention (C, stack_t);
++
++   function sigaltstack
++     (ss  : not null access stack_t;
++      oss : access stack_t) return int;
++   pragma Import (C, sigaltstack, "sigaltstack");
++
++   Alternate_Stack : aliased System.Address;
++   --  This is a dummy definition, never used (Alternate_Stack_Size is null)
++
++   Alternate_Stack_Size : constant := 0;
++   --  No alternate signal stack is used on this platform
++
++   Stack_Base_Available : constant Boolean := False;
++   --  Indicates whether the stack base is available on this target
++
++   function Get_Stack_Base (thread : pthread_t) return Address;
++   pragma Inline (Get_Stack_Base);
++   --  returns the stack base of the specified thread. Only call this function
++   --  when Stack_Base_Available is True.
++
++   --  From: /usr/include/unistd.h __getpagesize or getpagesize??
++   function Get_Page_Size return int;
++   pragma Import (C, Get_Page_Size, "__getpagesize");
++   --  Returns the size of a page
++
++   --  From /usr/include/i386-gnu/bits/mman.h
++   PROT_NONE  : constant := 0;
++   PROT_READ  : constant := 4;
++   PROT_WRITE : constant := 2;
++   PROT_EXEC  : constant := 1;
++   PROT_ALL   : constant := PROT_READ + PROT_WRITE + PROT_EXEC;
++   PROT_ON    : constant := PROT_NONE;
++   PROT_OFF   : constant := PROT_ALL;
++
++   --  From /usr/include/i386-gnu/bits/mman.h
++   function mprotect (addr : Address; len : size_t; prot : int) return int;
++   pragma Import (C, mprotect);
++
++   ---------------------------------------
++   -- Nonstandard Thread Initialization --
++   ---------------------------------------
++
++   procedure pthread_init;
++   pragma Inline (pthread_init);
++   --  This is a dummy procedure to share some GNULLI files
++
++   -------------------------
++   -- POSIX.1c  Section 3 --
++   -------------------------
++
++   --  From: /usr/include/signal.h:
++   --  sigwait (__const sigset_t *__restrict __set, int *__restrict __sig)
++   function sigwait (set : access sigset_t; sig : access Signal) return int;
++   pragma Import (C, sigwait, "sigwait");
++
++   --  From: /usr/include/pthread/pthread.h:
++   --  extern int pthread_kill (pthread_t thread, int signo);
++   function pthread_kill (thread : pthread_t; sig : Signal) return int;
++   pragma Import (C, pthread_kill, "pthread_kill");
++
++   --  From: /usr/include/i386-gnu/bits/sigthread.h
++   --  extern int pthread_sigmask (int __how, __const __sigset_t *__newmask,
++   --  __sigset_t *__oldmask) __THROW;
++   function pthread_sigmask
++     (how  : int;
++      set  : access sigset_t;
++      oset : access sigset_t) return int;
++   pragma Import (C, pthread_sigmask, "pthread_sigmask");
++
++   --------------------------
++   -- POSIX.1c  Section 11 --
++   --------------------------
++
++   --  From: /usr/include/pthread/pthread.h and
++   --  /usr/include/pthread/pthreadtypes.h
++   function pthread_mutexattr_init
++     (attr : access pthread_mutexattr_t) return int;
++   pragma Import (C, pthread_mutexattr_init, "pthread_mutexattr_init");
++
++   function pthread_mutexattr_destroy
++     (attr : access pthread_mutexattr_t) return int;
++   pragma Import (C, pthread_mutexattr_destroy, "pthread_mutexattr_destroy");
++
++   function pthread_mutex_init
++     (mutex : access pthread_mutex_t;
++      attr  : access pthread_mutexattr_t) return int;
++   pragma Import (C, pthread_mutex_init, "pthread_mutex_init");
++
++   function pthread_mutex_destroy (mutex : access pthread_mutex_t) return int;
++   pragma Import (C, pthread_mutex_destroy, "pthread_mutex_destroy");
++
++   function pthread_mutex_lock (mutex : access pthread_mutex_t) return int;
++   pragma Import (C, pthread_mutex_lock, "pthread_mutex_lock");
++
++   function pthread_mutex_unlock (mutex : access pthread_mutex_t) return int;
++   pragma Import (C, pthread_mutex_unlock, "pthread_mutex_unlock");
++
++   function pthread_condattr_init
++     (attr : access pthread_condattr_t) return int;
++   pragma Import (C, pthread_condattr_init, "pthread_condattr_init");
++
++   function pthread_condattr_destroy
++     (attr : access pthread_condattr_t) return int;
++   pragma Import (C, pthread_condattr_destroy, "pthread_condattr_destroy");
++
++   function pthread_cond_init
++     (cond : access pthread_cond_t;
++      attr : access pthread_condattr_t) return int;
++   pragma Import (C, pthread_cond_init, "pthread_cond_init");
++
++   function pthread_cond_destroy (cond : access pthread_cond_t) return int;
++   pragma Import (C, pthread_cond_destroy, "pthread_cond_destroy");
++
++   function pthread_cond_signal (cond : access pthread_cond_t) return int;
++   pragma Import (C, pthread_cond_signal, "pthread_cond_signal");
++
++   function pthread_cond_wait
++     (cond  : access pthread_cond_t;
++      mutex : access pthread_mutex_t) return int;
++   pragma Import (C, pthread_cond_wait, "pthread_cond_wait");
++
++   function pthread_cond_timedwait
++     (cond    : access pthread_cond_t;
++      mutex   : access pthread_mutex_t;
++      abstime : access timespec) return int;
++   pragma Import (C, pthread_cond_timedwait, "pthread_cond_timedwait");
++
++   Relative_Timed_Wait : constant Boolean := False;
++   --  pthread_cond_timedwait requires an absolute delay time
++
++   --------------------------
++   -- POSIX.1c  Section 13 --
++   --------------------------
++   --  From /usr/include/pthread/pthreadtypes.h
++
++   PTHREAD_PRIO_NONE    : constant := 0;
++   PTHREAD_PRIO_PROTECT : constant := 2;
++   PTHREAD_PRIO_INHERIT : constant := 1;
++
++   --  From: /usr/include/pthread/pthread.h
++   function pthread_mutexattr_setprotocol
++     (attr     : access pthread_mutexattr_t;
++      protocol : int) return int;
++   pragma Import (C, pthread_mutexattr_setprotocol,
++     "pthread_mutexattr_setprotocol");
++
++   function pthread_mutexattr_getprotocol
++     (attr     : access pthread_mutexattr_t;
++      protocol : access int) return int;
++   pragma Import (C, pthread_mutexattr_getprotocol,
++     "pthread_mutexattr_getprotocol");
++
++   function pthread_mutexattr_setprioceiling
++     (attr     : access pthread_mutexattr_t;
++      prioceiling : int) return int;
++   pragma Import (C, pthread_mutexattr_setprioceiling,
++     "pthread_mutexattr_setprioceiling");
++
++   function pthread_mutexattr_getprioceiling
++     (attr     : access pthread_mutexattr_t;
++      prioceiling : access int) return int;
++   pragma Import (C, pthread_mutexattr_getprioceiling,
++     "pthread_mutexattr_getprioceiling");
++
++   type struct_sched_param is record
++      sched_priority : int;  --  scheduling priority
++   end record;
++   pragma Convention (C, struct_sched_param);
++
++   function pthread_setschedparam
++     (thread : pthread_t;
++      policy : int;
++      param  : access struct_sched_param) return int;
++   pragma Import (C, pthread_setschedparam, "pthread_setschedparam");
++
++   function pthread_attr_setscope
++     (attr            : access pthread_attr_t;
++      contentionscope : int) return int;
++   pragma Import (C, pthread_attr_setscope, "pthread_attr_setscope");
++
++   function pthread_attr_getscope
++     (attr            : access pthread_attr_t;
++      contentionscope : access int) return int;
++   pragma Import (C, pthread_attr_getscope, "pthread_attr_getscope");
++
++   function pthread_attr_setinheritsched
++     (attr            : access pthread_attr_t;
++      inheritsched : int) return int;
++   pragma Import (C, pthread_attr_setinheritsched,
++     "pthread_attr_setinheritsched");
++
++   function pthread_attr_getinheritsched
++     (attr         : access pthread_attr_t;
++      inheritsched : access int) return int;
++   pragma Import (C, pthread_attr_getinheritsched,
++     "pthread_attr_getinheritsched");
++
++   function pthread_attr_setschedpolicy
++     (attr   : access pthread_attr_t;
++      policy : int) return int;
++   pragma Import (C, pthread_attr_setschedpolicy, "pthread_setschedpolicy");
++
++   function sched_yield return int;
++   pragma Import (C, sched_yield, "sched_yield");
++
++   ---------------------------
++   -- P1003.1c - Section 16 --
++   ---------------------------
++
++   function pthread_attr_init
++     (attributes : access pthread_attr_t) return int;
++   pragma Import (C, pthread_attr_init, "pthread_attr_init");
++
++   function pthread_attr_destroy
++     (attributes : access pthread_attr_t) return int;
++   pragma Import (C, pthread_attr_destroy, "pthread_attr_destroy");
++
++   function pthread_attr_setdetachstate
++     (attr        : access pthread_attr_t;
++      detachstate : int) return int;
++   pragma Import
++     (C, pthread_attr_setdetachstate, "pthread_attr_setdetachstate");
++
++   function pthread_attr_setstacksize
++     (attr      : access pthread_attr_t;
++      stacksize : size_t) return int;
++   pragma Import (C, pthread_attr_setstacksize, "pthread_attr_setstacksize");
++
++   --  From: /usr/include/pthread/pthread.h
++   function pthread_create
++     (thread        : access pthread_t;
++      attributes    : access pthread_attr_t;
++      start_routine : Thread_Body;
++      arg           : System.Address) return int;
++   pragma Import (C, pthread_create, "pthread_create");
++
++   procedure pthread_exit (status : System.Address);
++   pragma Import (C, pthread_exit, "pthread_exit");
++
++   function pthread_self return pthread_t;
++   pragma Import (C, pthread_self, "pthread_self");
++
++   --------------------------
++   -- POSIX.1c  Section 17 --
++   --------------------------
++
++   function pthread_setspecific
++     (key   : pthread_key_t;
++      value : System.Address) return int;
++   pragma Import (C, pthread_setspecific, "pthread_setspecific");
++
++   function pthread_getspecific (key : pthread_key_t) return System.Address;
++   pragma Import (C, pthread_getspecific, "pthread_getspecific");
++
++   type destructor_pointer is access procedure (arg : System.Address);
++   pragma Convention (C, destructor_pointer);
++
++   function pthread_key_create
++     (key        : access pthread_key_t;
++      destructor : destructor_pointer) return int;
++   pragma Import (C, pthread_key_create, "pthread_key_create");
++
++   --  From /usr/include/i386-gnu/bits/sched.h
++   --  1_024 == 1024??
++   CPU_SETSIZE : constant := 1_024;
++
++   type bit_field is array (1 .. CPU_SETSIZE) of Boolean;
++   for bit_field'Size use CPU_SETSIZE;
++   pragma Pack (bit_field);
++   pragma Convention (C, bit_field);
++
++   type cpu_set_t is record
++      bits : bit_field;
++   end record;
++   pragma Convention (C, cpu_set_t);
++
++   --  function pthread_setaffinity_np
++   --  (thread     : pthread_t;
++   --   cpusetsize : size_t;
++   --   cpuset     : access cpu_set_t) return int;
++   --   pragma Import (C, pthread_setaffinity_np,
++   --   "__gnat_pthread_setaffinity_np");
++
++private
++
++   type sigset_t is array (1 .. 4) of unsigned;
++
++   --  FIXME:
++   --  In GNU/Hurd the component sa_handler turns out to
++   --  be one a union type, and the selector is a macro:
++   --  #define sa_handler __sigaction_handler.sa_handler
++   --  #define sa_sigaction __sigaction_handler.sa_sigaction
++
++   --  In FreeBSD the component sa_handler turns out to
++   --  be one a union type, and the selector is a macro:
++   --  #define sa_handler __sigaction_u._handler
++   --  #define sa_sigaction __sigaction_u._sigaction
++
++   --  Should we add a signal_context type here ?
++   --  How could it be done independent of the CPU architecture ?
++   --  sigcontext type is opaque, so it is architecturally neutral.
++   --  It is always passed as an access type, so define it as an empty record
++   --  since the contents are not used anywhere.
++   type struct_sigcontext is null record;
++   pragma Convention (C, struct_sigcontext);
++
++   type pid_t is new int;
++
++   type time_t is new long;
++
++   type timespec is record
++      tv_sec  : time_t;
++      tv_nsec : long;
++   end record;
++   pragma Convention (C, timespec);
++
++   type clockid_t is new int;
++   CLOCK_REALTIME : constant clockid_t := 0;
++
++   --  From: /usr/include/pthread/pthreadtypes.h:
++   --  typedef struct __pthread_attr pthread_attr_t;
++   --  /usr/include/bits/thread-attr.h: struct __pthread_attr...
++   --  /usr/include/pthread/pthreadtypes.h: enum __pthread_contentionscope
++   --   enum __pthread_detachstate detachstate;
++   --   enum __pthread_inheritsched inheritsched;
++   --   enum __pthread_contentionscope contentionscope;
++   --   Not used: schedpolicy   : int;
++   type pthread_attr_t is record
++      schedparam    : struct_sched_param;
++      stackaddr     : System.Address;
++      stacksize     : size_t;
++      guardsize     : size_t;
++      detachstate   : int;
++      inheritsched  : int;
++      contentionscope : int;
++      schedpolicy   : int;
++   end record;
++   pragma Convention (C, pthread_attr_t);
++
++   --  From: /usr/include/pthread/pthreadtypes.h:
++   --  typedef struct __pthread_condattr pthread_condattr_t;
++   --  From: /usr/include/bits/condition-attr.h:
++   --  struct __pthread_condattr {
++   --    enum __pthread_process_shared pshared;
++   --    __Clockid_T Clock;}
++   --  From: /usr/include/pthread/pthreadtypes.h:
++   --  enum __pthread_process_shared
++   type pthread_condattr_t is record
++      pshared : int;
++      clock   : clockid_t;
++   end record;
++   pragma Convention (C, pthread_condattr_t);
++
++   --  From: /usr/include/pthread/pthreadtypes.h:
++   --  typedef struct __pthread_mutexattr pthread_mutexattr_t; and
++   --  /usr/include/bits/mutex-attr.h
++   --  struct __pthread_mutexattr {
++   --  Int Prioceiling;
++   --  Enum __Pthread_Mutex_Protocol Protocol;
++   --  Enum __Pthread_Process_Shared Pshared;
++   --  Enum __Pthread_Mutex_Type Mutex_Type;};
++   type pthread_mutexattr_t is record
++      prioceiling : int;
++      protocol    : int;
++      pshared     : int;
++      mutex_type  : int;
++   end record;
++   pragma Convention (C, pthread_mutexattr_t);
++
++   --  From: /usr/include/pthread/pthreadtypes.h
++   --  typedef struct __pthread_mutex pthread_mutex_t; and
++   --  /usr/include/bits/mutex.h:
++   --  struct __pthread_mutex {
++   --  __pthread_spinlock_t __held;
++   --  __pthread_spinlock_t __lock;
++   --  /* in cthreads, mutex_init does not initialized the third
++   --    pointer, as such, we cannot rely on its value for anything.  */
++   --    char *cthreadscompat1;
++   --  struct __pthread *__queue;
++   --  struct __pthread_mutexattr *attr;
++   --  void *data;
++   --  /*  up to this point, we are completely compatible with cthreads
++   --    and what libc expects.  */
++   --    void *owner;
++   --  unsigned locks;
++   --  /* if null then the default attributes apply.  */
++   --    };
++   type pthread_mutex_t is record
++      held          : int;
++      lock          : int;
++      cthreadcompat : System.Address;
++      queue         : System.Address;
++      attr          : System.Address;
++      data          : System.Address;
++      owner         : System.Address;
++      locks         : unsigned;
++   end record;
++   pragma Convention (C, pthread_mutex_t);
++   --  pointer needed?
++   --  type pthread_mutex_t_ptr is access pthread_mutex_t;
++
++   --  From: /usr/include/pthread/pthreadtypes.h:
++   --  typedef struct __pthread_cond pthread_cond_t;
++   --  typedef struct __pthread_condattr pthread_condattr_t;
++   --  /usr/include/bits/condition.h:struct __pthread_cond{}
++   --  pthread_condattr_t: see above!
++   --  /usr/include/bits/condition.h:    struct __pthread_condimpl *__impl;
++
++   type pthread_cond_t is record
++      lock       : int;
++      queue      : System.Address;
++      condattr   : System.Address;
++      impl       : System.Address;
++      data       : System.Address;
++   end record;
++   pragma Convention (C, pthread_cond_t);
++
++   --  From: /usr/include/pthread/pthreadtypes.h:
++   --  typedef __pthread_key pthread_key_t; and
++   --  /usr/include/bits/thread-specific.h:
++   --  typedef int __pthread_key;
++   type pthread_key_t is new int;
++
++end System.OS_Interface;
--- gcc-6-6.4.0.orig/debian/patches/ada-sjlj.diff
+++ gcc-6-6.4.0/debian/patches/ada-sjlj.diff
@@ -0,0 +1,1034 @@
+Index: b/src/libada-sjlj/Makefile.in
+===================================================================
+--- /dev/null
++++ b/src/libada-sjlj/Makefile.in
+@@ -0,0 +1,201 @@
++# Makefile for libada.
++#   Copyright (C) 2003-2015 Free Software Foundation, Inc.
++#
++# This file is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3 of the License, or
++# (at your option) any later version.
++# 
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++# 
++# You should have received a copy of the GNU General Public License
++# along with this program; see the file COPYING3.  If not see
++# <http://www.gnu.org/licenses/>.
++
++# Default target; must be first.
++all: gnatlib
++	$(MULTIDO) $(AM_MAKEFLAGS) DO=all multi-do # $(MAKE)
++
++.PHONY: all
++
++## Multilib support variables.
++MULTISRCTOP =
++MULTIBUILDTOP =
++MULTIDIRS =
++MULTISUBDIR =
++MULTIDO = true
++MULTICLEAN = true
++
++# Standard autoconf-set variables.
++SHELL = @SHELL@
++srcdir = @srcdir@
++libdir = @libdir@
++build = @build@
++target = @target@
++prefix = @prefix@
++
++# Nonstandard autoconf-set variables.
++enable_shared = @enable_shared@
++
++LN_S=@LN_S@
++AWK=@AWK@
++
++ifeq (cp -p,$(LN_S))
++LN_S_RECURSIVE = cp -pR
++else
++LN_S_RECURSIVE = $(LN_S)
++endif
++
++# Variables for the user (or the top level) to override.
++objext=.o
++THREAD_KIND=native
++TRACE=no
++LDFLAGS=
++
++# The tedious process of getting CFLAGS right.
++CFLAGS=-g
++PICFLAG = @PICFLAG@
++GNATLIBFLAGS= -W -Wall -gnatpg -nostdinc
++GNATLIBCFLAGS= -g -O2
++GNATLIBCFLAGS_FOR_C = -W -Wall $(GNATLIBCFLAGS) \
++	-fexceptions -DIN_RTS @have_getipinfo@
++
++host_subdir = @host_subdir@
++GCC_DIR=$(MULTIBUILDTOP)../../$(host_subdir)/gcc
++
++target_noncanonical:=@target_noncanonical@
++version := $(shell cat $(srcdir)/../gcc/BASE-VER)
++libsubdir := $(libdir)/gcc/$(target_noncanonical)/$(version)$(MULTISUBDIR)
++ADA_RTS_DIR=$(GCC_DIR)/ada/rts$(subst /,_,$(MULTISUBDIR))
++ADA_RTS_SUBDIR=./rts$(subst /,_,$(MULTISUBDIR))
++
++# exeext should not be used because it's the *host* exeext.  We're building
++# a *target* library, aren't we?!?  Likewise for CC.  Still, provide bogus
++# definitions just in case something slips through the safety net provided
++# by recursive make invocations in gcc/ada/Makefile.in
++LIBADA_FLAGS_TO_PASS = \
++        "MAKEOVERRIDES=" \
++        "LDFLAGS=$(LDFLAGS)" \
++        "LN_S=$(LN_S)" \
++        "SHELL=$(SHELL)" \
++        "GNATLIBFLAGS=$(GNATLIBFLAGS) $(MULTIFLAGS)" \
++        "GNATLIBCFLAGS=$(GNATLIBCFLAGS) $(MULTIFLAGS)" \
++        "GNATLIBCFLAGS_FOR_C=$(GNATLIBCFLAGS_FOR_C) $(MULTIFLAGS)" \
++        "PICFLAG_FOR_TARGET=$(PICFLAG)" \
++        "THREAD_KIND=$(THREAD_KIND)" \
++        "TRACE=$(TRACE)" \
++        "MULTISUBDIR=$(MULTISUBDIR)" \
++        "libsubdir=$(libsubdir)" \
++        "objext=$(objext)" \
++        "prefix=$(prefix)" \
++        "exeext=.exeext.should.not.be.used " \
++	'CC=the.host.compiler.should.not.be.needed' \
++	"GCC_FOR_TARGET=$(CC)" \
++        "CFLAGS=$(CFLAGS)" \
++	"RTSDIR=rts-sjlj"
++
++# Rules to build gnatlib.
++.PHONY: gnatlib gnatlib-plain gnatlib-sjlj gnatlib-zcx gnatlib-shared osconstool
++gnatlib: gnatlib-sjlj
++
++gnatlib-plain: osconstool $(GCC_DIR)/ada/Makefile
++	test -f stamp-libada || \
++	$(MAKE) -C $(GCC_DIR)/ada $(LIBADA_FLAGS_TO_PASS) gnatlib \
++	&& touch stamp-libada
++	-rm -rf adainclude
++	-rm -rf adalib
++	$(LN_S_RECURSIVE) $(ADA_RTS_DIR) adainclude
++	$(LN_S_RECURSIVE) $(ADA_RTS_DIR) adalib
++
++gnatlib-sjlj gnatlib-zcx gnatlib-shared: osconstool $(GCC_DIR)/ada/Makefile
++	test -f stamp-libada || \
++	$(MAKE) -C $(GCC_DIR)/ada $(LIBADA_FLAGS_TO_PASS) $@ \
++	&& touch stamp-libada-sjlj
++	-rm -rf adainclude
++	-rm -rf adalib
++	$(LN_S_RECURSIVE) $(ADA_RTS_DIR) adainclude
++	$(LN_S_RECURSIVE) $(ADA_RTS_DIR) adalib
++
++osconstool:
++	$(MAKE) -C $(GCC_DIR)/ada $(LIBADA_FLAGS_TO_PASS) ./bldtools/oscons/xoscons
++
++install-gnatlib: $(GCC_DIR)/ada/Makefile
++	$(MAKE) -C $(GCC_DIR)/ada $(LIBADA_FLAGS_TO_PASS) install-gnatlib-sjlj
++
++# Check uninstalled version.
++check:
++
++# Check installed version.
++installcheck:
++
++# Build info (none here).
++info:
++
++# Build DVI (none here).
++dvi:
++
++# Build PDF (none here).
++pdf:
++
++# Build html (none here).
++html:
++
++# Build TAGS (none here).
++TAGS:
++
++.PHONY: check installcheck info dvi pdf html
++
++# Installation rules.
++install: install-gnatlib
++	$(MULTIDO) $(AM_MAKEFLAGS) DO=install multi-do # $(MAKE)
++
++install-strip: install
++
++install-info:
++
++install-pdf:
++
++install-html:
++
++.PHONY: install install-strip install-info install-pdf install-html
++
++# Cleaning rules.
++mostlyclean:
++	$(MULTICLEAN) $(AM_MAKEFLAGS) DO=mostlyclean multi-clean # $(MAKE)
++
++clean:
++	$(MULTICLEAN) $(AM_MAKEFLAGS) DO=clean multi-clean # $(MAKE)
++
++distclean:
++	$(MULTICLEAN) $(AM_MAKEFLAGS) DO=distclean multi-clean # $(MAKE)
++	$(RM) Makefile config.status config.log
++
++maintainer-clean:
++
++.PHONY: mostlyclean clean distclean maintainer-clean
++
++# Rules for rebuilding this Makefile.
++Makefile: $(srcdir)/Makefile.in config.status
++	CONFIG_FILES=$@ ; \
++	CONFIG_HEADERS= ; \
++	$(SHELL) ./config.status
++
++config.status: $(srcdir)/configure
++	$(SHELL) ./config.status --recheck
++
++AUTOCONF = autoconf
++configure_deps = \
++	$(srcdir)/configure.ac \
++	$(srcdir)/../config/acx.m4 \
++	$(srcdir)/../config/override.m4 \
++	$(srcdir)/../config/multi.m4
++
++$(srcdir)/configure: @MAINT@ $(configure_deps)
++	cd $(srcdir) && $(AUTOCONF)
++
++# Don't export variables to the environment, in order to not confuse
++# configure.
++.NOEXPORT:
+Index: b/src/libada-sjlj/configure.ac
+===================================================================
+--- /dev/null
++++ b/src/libada-sjlj/configure.ac
+@@ -0,0 +1,140 @@
++# Configure script for libada.
++#   Copyright (C) 2003-2015 Free Software Foundation, Inc.
++#
++# This file is free software; you can redistribute it and/or modify it
++# under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful, but
++# WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++# General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; see the file COPYING3.  If not see
++# <http://www.gnu.org/licenses/>.
++
++sinclude(../config/acx.m4)
++sinclude(../config/multi.m4)
++sinclude(../config/override.m4)
++sinclude(../config/picflag.m4)
++sinclude(../config/unwind_ipinfo.m4)
++
++AC_INIT
++AC_PREREQ([2.64])
++
++AC_CONFIG_SRCDIR([Makefile.in])
++
++# Determine the host, build, and target systems
++AC_CANONICAL_BUILD
++AC_CANONICAL_HOST
++AC_CANONICAL_TARGET
++target_alias=${target_alias-$host_alias}
++
++# Determine the noncanonical target name, for directory use.
++ACX_NONCANONICAL_TARGET
++
++# Determine the target- and build-specific subdirectories
++GCC_TOPLEV_SUBDIRS
++
++# Command-line options.
++# Very limited version of AC_MAINTAINER_MODE.
++AC_ARG_ENABLE([maintainer-mode],
++  [AC_HELP_STRING([--enable-maintainer-mode],
++                 [enable make rules and dependencies not useful (and
++                  sometimes confusing) to the casual installer])],
++  [case ${enable_maintainer_mode} in
++     yes) MAINT='' ;;
++     no) MAINT='#' ;;
++     *) AC_MSG_ERROR([--enable-maintainer-mode must be yes or no]) ;;
++   esac
++   maintainer_mode=${enableval}],
++  [MAINT='#'])
++AC_SUBST([MAINT])dnl
++
++AM_ENABLE_MULTILIB(, ..)
++# Calculate toolexeclibdir
++# Also toolexecdir, though it's only used in toolexeclibdir
++case ${enable_version_specific_runtime_libs} in
++  yes)
++    # Need the gcc compiler version to know where to install libraries
++    # and header files if --enable-version-specific-runtime-libs option
++    # is selected.
++    toolexecdir='$(libdir)/gcc/$(target_alias)'
++    toolexeclibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)'
++    ;;
++  no)
++    if test -n "$with_cross_host" &&
++       test x"$with_cross_host" != x"no"; then
++      # Install a library built with a cross compiler in tooldir, not libdir.
++      toolexecdir='$(exec_prefix)/$(target_alias)'
++      toolexeclibdir='$(toolexecdir)/lib'
++    else
++      toolexecdir='$(libdir)/gcc-lib/$(target_alias)'
++      toolexeclibdir='$(libdir)'
++    fi
++    multi_os_directory=`$CC -print-multi-os-directory`
++    case $multi_os_directory in
++      .) ;; # Avoid trailing /.
++      *) toolexeclibdir=$toolexeclibdir/$multi_os_directory ;;
++    esac
++    ;;
++esac
++AC_SUBST(toolexecdir)
++AC_SUBST(toolexeclibdir)
++#TODO: toolexeclibdir is currently disregarded
++
++# Check the compiler.
++# The same as in boehm-gc and libstdc++. Have to borrow it from there.
++# We must force CC to /not/ be precious variables; otherwise
++# the wrong, non-multilib-adjusted value will be used in multilibs.
++# As a side effect, we have to subst CFLAGS ourselves.
++
++m4_rename([_AC_ARG_VAR_PRECIOUS],[real_PRECIOUS])
++m4_define([_AC_ARG_VAR_PRECIOUS],[])
++AC_PROG_CC
++m4_rename_force([real_PRECIOUS],[_AC_ARG_VAR_PRECIOUS])
++
++AC_SUBST(CFLAGS)
++
++AC_ARG_ENABLE([shared],
++[AC_HELP_STRING([--disable-shared],
++                [don't provide a shared libgnat])],
++[
++case $enable_shared in
++  yes | no) ;;
++  *)
++    enable_shared=no
++    IFS="${IFS=         }"; ac_save_ifs="$IFS"; IFS="${IFS}:,"
++    for pkg in $enableval; do
++      case $pkg in
++        ada | libada)
++          enable_shared=yes ;;
++      esac
++    done
++    IFS="$ac_save_ifs"
++    ;;
++esac
++], [enable_shared=yes])
++AC_SUBST([enable_shared])
++
++GCC_PICFLAG
++AC_SUBST([PICFLAG])
++
++# These must be passed down, or are needed by gcc/libgcc.mvars
++AC_PROG_AWK
++AC_PROG_LN_S
++
++# Check for _Unwind_GetIPInfo
++GCC_CHECK_UNWIND_GETIPINFO
++have_getipinfo=
++if test x$have_unwind_getipinfo = xyes; then
++  have_getipinfo=-DHAVE_GETIPINFO
++fi
++AC_SUBST(have_getipinfo)
++
++# Output: create a Makefile.
++AC_CONFIG_FILES([Makefile])
++
++AC_OUTPUT
+Index: b/src/Makefile.def
+===================================================================
+--- a/src/Makefile.def
++++ b/src/Makefile.def
+@@ -183,6 +183,13 @@ target_modules = { module= libada; no_in
+ 		   missing= TAGS;
+ 		   missing= install-info;
+ 		   missing= installcheck; };
++target_modules = { module= libada-sjlj; no_install=true; no_check=true;
++		   missing= info;
++		   missing= dvi;
++		   missing= html;
++		   missing= TAGS;
++		   missing= install-info;
++		   missing= installcheck; };
+ target_modules = { module= libgnatvsn; no_check=true;
+ 		   missing= info;
+ 		   missing= dvi;
+@@ -394,6 +401,7 @@ dependencies = { module=all-libcpp; on=a
+ dependencies = { module=all-fixincludes; on=all-libiberty; };
+ 
+ dependencies = { module=all-target-libada; on=all-gcc; };
++dependencies = { module=all-target-libada-sjlj; on=all-target-libada; };
+ dependencies = { module=all-gnattools; on=all-target-libada; };
+ dependencies = { module=all-gnattools; on=all-target-libgnatvsn; };
+ dependencies = { module=all-gnattools; on=all-target-libgnatprj; };
+Index: b/src/Makefile.in
+===================================================================
+--- a/src/Makefile.in
++++ b/src/Makefile.in
+@@ -976,6 +976,7 @@ configure-target:  \
+     maybe-configure-target-boehm-gc \
+     maybe-configure-target-rda \
+     maybe-configure-target-libada \
++    maybe-configure-target-libada-sjlj \
+     maybe-configure-target-libgnatvsn \
+     maybe-configure-target-libgnatprj \
+     maybe-configure-target-libgomp \
+@@ -1146,6 +1147,7 @@ all-target: maybe-all-target-zlib
+ all-target: maybe-all-target-boehm-gc
+ all-target: maybe-all-target-rda
+ all-target: maybe-all-target-libada
++all-target: maybe-all-target-libada-sjlj
+ all-target: maybe-all-target-libgnatvsn
+ all-target: maybe-all-target-libgnatprj
+ @if target-libgomp-no-bootstrap
+@@ -1243,6 +1245,7 @@ info-target: maybe-info-target-zlib
+ info-target: maybe-info-target-boehm-gc
+ info-target: maybe-info-target-rda
+ info-target: maybe-info-target-libada
++info-target: maybe-info-target-libada-sjlj
+ info-target: maybe-info-target-libgnatvsn
+ info-target: maybe-info-target-libgnatprj
+ info-target: maybe-info-target-libgomp
+@@ -1333,6 +1336,7 @@ dvi-target: maybe-dvi-target-zlib
+ dvi-target: maybe-dvi-target-boehm-gc
+ dvi-target: maybe-dvi-target-rda
+ dvi-target: maybe-dvi-target-libada
++dvi-target: maybe-dvi-target-libada-sjlj
+ dvi-target: maybe-dvi-target-libgnatvsn
+ dvi-target: maybe-dvi-target-libgnatprj
+ dvi-target: maybe-dvi-target-libgomp
+@@ -1423,6 +1427,7 @@ pdf-target: maybe-pdf-target-zlib
+ pdf-target: maybe-pdf-target-boehm-gc
+ pdf-target: maybe-pdf-target-rda
+ pdf-target: maybe-pdf-target-libada
++pdf-target: maybe-pdf-target-libada-sjlj
+ pdf-target: maybe-pdf-target-libgnatvsn
+ pdf-target: maybe-pdf-target-libgnatprj
+ pdf-target: maybe-pdf-target-libgomp
+@@ -1513,6 +1518,7 @@ html-target: maybe-html-target-zlib
+ html-target: maybe-html-target-boehm-gc
+ html-target: maybe-html-target-rda
+ html-target: maybe-html-target-libada
++html-target: maybe-html-target-libada-sjlj
+ html-target: maybe-html-target-libgnatvsn
+ html-target: maybe-html-target-libgnatprj
+ html-target: maybe-html-target-libgomp
+@@ -1603,6 +1609,7 @@ TAGS-target: maybe-TAGS-target-zlib
+ TAGS-target: maybe-TAGS-target-boehm-gc
+ TAGS-target: maybe-TAGS-target-rda
+ TAGS-target: maybe-TAGS-target-libada
++TAGS-target: maybe-TAGS-target-libada-sjlj
+ TAGS-target: maybe-TAGS-target-libgnatvsn
+ TAGS-target: maybe-TAGS-target-libgnatprj
+ TAGS-target: maybe-TAGS-target-libgomp
+@@ -1693,6 +1700,7 @@ install-info-target: maybe-install-info-
+ install-info-target: maybe-install-info-target-boehm-gc
+ install-info-target: maybe-install-info-target-rda
+ install-info-target: maybe-install-info-target-libada
++install-info-target: maybe-install-info-target-libada-sjlj
+ install-info-target: maybe-install-info-target-libgnatvsn
+ install-info-target: maybe-install-info-target-libgnatprj
+ install-info-target: maybe-install-info-target-libgomp
+@@ -1783,6 +1791,7 @@ install-pdf-target: maybe-install-pdf-ta
+ install-pdf-target: maybe-install-pdf-target-boehm-gc
+ install-pdf-target: maybe-install-pdf-target-rda
+ install-pdf-target: maybe-install-pdf-target-libada
++install-pdf-target: maybe-install-pdf-target-libada-sjlj
+ install-pdf-target: maybe-install-pdf-target-libgnatvsn
+ install-pdf-target: maybe-install-pdf-target-libgnatprj
+ install-pdf-target: maybe-install-pdf-target-libgomp
+@@ -1873,6 +1882,7 @@ install-html-target: maybe-install-html-
+ install-html-target: maybe-install-html-target-boehm-gc
+ install-html-target: maybe-install-html-target-rda
+ install-html-target: maybe-install-html-target-libada
++install-html-target: maybe-install-html-target-libada-sjlj
+ install-html-target: maybe-install-html-target-libgnatvsn
+ install-html-target: maybe-install-html-target-libgnatprj
+ install-html-target: maybe-install-html-target-libgomp
+@@ -1963,6 +1973,7 @@ installcheck-target: maybe-installcheck-
+ installcheck-target: maybe-installcheck-target-boehm-gc
+ installcheck-target: maybe-installcheck-target-rda
+ installcheck-target: maybe-installcheck-target-libada
++installcheck-target: maybe-installcheck-target-libada-sjlj
+ installcheck-target: maybe-installcheck-target-libgnatvsn
+ installcheck-target: maybe-installcheck-target-libgnatprj
+ installcheck-target: maybe-installcheck-target-libgomp
+@@ -2053,6 +2064,7 @@ mostlyclean-target: maybe-mostlyclean-ta
+ mostlyclean-target: maybe-mostlyclean-target-boehm-gc
+ mostlyclean-target: maybe-mostlyclean-target-rda
+ mostlyclean-target: maybe-mostlyclean-target-libada
++mostlyclean-target: maybe-mostlyclean-target-libada-sjlj
+ mostlyclean-target: maybe-mostlyclean-target-libgnatvsn
+ mostlyclean-target: maybe-mostlyclean-target-libgnatprj
+ mostlyclean-target: maybe-mostlyclean-target-libgomp
+@@ -2143,6 +2155,7 @@ clean-target: maybe-clean-target-zlib
+ clean-target: maybe-clean-target-boehm-gc
+ clean-target: maybe-clean-target-rda
+ clean-target: maybe-clean-target-libada
++clean-target: maybe-clean-target-libada-sjlj
+ clean-target: maybe-clean-target-libgnatvsn
+ clean-target: maybe-clean-target-libgnatprj
+ clean-target: maybe-clean-target-libgomp
+@@ -2233,6 +2246,7 @@ distclean-target: maybe-distclean-target
+ distclean-target: maybe-distclean-target-boehm-gc
+ distclean-target: maybe-distclean-target-rda
+ distclean-target: maybe-distclean-target-libada
++distclean-target: maybe-distclean-target-libada-sjlj
+ distclean-target: maybe-distclean-target-libgnatvsn
+ distclean-target: maybe-distclean-target-libgnatprj
+ distclean-target: maybe-distclean-target-libgomp
+@@ -2323,6 +2337,7 @@ maintainer-clean-target: maybe-maintaine
+ maintainer-clean-target: maybe-maintainer-clean-target-boehm-gc
+ maintainer-clean-target: maybe-maintainer-clean-target-rda
+ maintainer-clean-target: maybe-maintainer-clean-target-libada
++maintainer-clean-target: maybe-maintainer-clean-target-libada-sjlj
+ maintainer-clean-target: maybe-maintainer-clean-target-libgnatvsn
+ maintainer-clean-target: maybe-maintainer-clean-target-libgnatprj
+ maintainer-clean-target: maybe-maintainer-clean-target-libgomp
+@@ -2469,6 +2484,7 @@ check-target:  \
+     maybe-check-target-boehm-gc \
+     maybe-check-target-rda \
+     maybe-check-target-libada \
++    maybe-check-target-libada-sjlj \
+     maybe-check-target-libgnatvsn \
+     maybe-check-target-libgnatprj \
+     maybe-check-target-libgomp \
+@@ -2655,6 +2671,7 @@ install-target:  \
+     maybe-install-target-boehm-gc \
+     maybe-install-target-rda \
+     maybe-install-target-libada \
++    maybe-install-target-libada-sjlj \
+     maybe-install-target-libgnatvsn \
+     maybe-install-target-libgnatprj \
+     maybe-install-target-libgomp \
+@@ -2765,6 +2782,7 @@ install-strip-target:  \
+     maybe-install-strip-target-boehm-gc \
+     maybe-install-strip-target-rda \
+     maybe-install-strip-target-libada \
++    maybe-install-strip-target-libada-sjlj \
+     maybe-install-strip-target-libgnatvsn \
+     maybe-install-strip-target-libgnatprj \
+     maybe-install-strip-target-libgomp \
+@@ -46077,6 +46095,352 @@ maintainer-clean-target-libada:
+ 
+ 
+ 
++.PHONY: configure-target-libada-sjlj maybe-configure-target-libada-sjlj
++maybe-configure-target-libada-sjlj:
++@if gcc-bootstrap
++configure-target-libada-sjlj: stage_current
++@endif gcc-bootstrap
++@if target-libada-sjlj
++maybe-configure-target-libada-sjlj: configure-target-libada-sjlj
++configure-target-libada-sjlj: 
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	echo "Checking multilib configuration for libada-sjlj..."; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libada-sjlj ; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp 2> /dev/null ; \
++	if test -r $(TARGET_SUBDIR)/libada-sjlj/multilib.out; then \
++	  if cmp -s $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp $(TARGET_SUBDIR)/libada-sjlj/multilib.out; then \
++	    rm -f $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp; \
++	  else \
++	    rm -f $(TARGET_SUBDIR)/libada-sjlj/Makefile; \
++	    mv $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp $(TARGET_SUBDIR)/libada-sjlj/multilib.out; \
++	  fi; \
++	else \
++	  mv $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp $(TARGET_SUBDIR)/libada-sjlj/multilib.out; \
++	fi; \
++	test ! -f $(TARGET_SUBDIR)/libada-sjlj/Makefile || exit 0; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libada-sjlj ; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	echo Configuring in $(TARGET_SUBDIR)/libada-sjlj; \
++	cd "$(TARGET_SUBDIR)/libada-sjlj" || exit 1; \
++	case $(srcdir) in \
++	  /* | [A-Za-z]:[\\/]*) topdir=$(srcdir) ;; \
++	  *) topdir=`echo $(TARGET_SUBDIR)/libada-sjlj/ | \
++		sed -e 's,\./,,g' -e 's,[^/]*/,../,g' `$(srcdir) ;; \
++	esac; \
++	module_srcdir=libada-sjlj; \
++	rm -f no-such-file || : ; \
++	CONFIG_SITE=no-such-file $(SHELL) \
++	  $$s/$$module_srcdir/configure \
++	  --srcdir=$${topdir}/$$module_srcdir \
++	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
++	  --target=${target_alias}  \
++	  || exit 1
++@endif target-libada-sjlj
++
++
++
++
++
++.PHONY: all-target-libada-sjlj maybe-all-target-libada-sjlj
++maybe-all-target-libada-sjlj:
++@if gcc-bootstrap
++all-target-libada-sjlj: stage_current
++@endif gcc-bootstrap
++@if target-libada-sjlj
++TARGET-target-libada-sjlj=all
++maybe-all-target-libada-sjlj: all-target-libada-sjlj
++all-target-libada-sjlj: configure-target-libada-sjlj
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) $(EXTRA_TARGET_FLAGS)   \
++		$(TARGET-target-libada-sjlj))
++@endif target-libada-sjlj
++
++
++
++
++
++.PHONY: check-target-libada-sjlj maybe-check-target-libada-sjlj
++maybe-check-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-check-target-libada-sjlj: check-target-libada-sjlj
++
++# Dummy target for uncheckable module.
++check-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: install-target-libada-sjlj maybe-install-target-libada-sjlj
++maybe-install-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-install-target-libada-sjlj: install-target-libada-sjlj
++
++# Dummy target for uninstallable.
++install-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: install-strip-target-libada-sjlj maybe-install-strip-target-libada-sjlj
++maybe-install-strip-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-install-strip-target-libada-sjlj: install-strip-target-libada-sjlj
++
++# Dummy target for uninstallable.
++install-strip-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++# Other targets (info, dvi, pdf, etc.)
++
++.PHONY: maybe-info-target-libada-sjlj info-target-libada-sjlj
++maybe-info-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-info-target-libada-sjlj: info-target-libada-sjlj
++
++# libada-sjlj doesn't support info.
++info-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-dvi-target-libada-sjlj dvi-target-libada-sjlj
++maybe-dvi-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-dvi-target-libada-sjlj: dvi-target-libada-sjlj
++
++# libada-sjlj doesn't support dvi.
++dvi-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-pdf-target-libada-sjlj pdf-target-libada-sjlj
++maybe-pdf-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-pdf-target-libada-sjlj: pdf-target-libada-sjlj
++
++pdf-target-libada-sjlj: \
++    configure-target-libada-sjlj 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           pdf) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-html-target-libada-sjlj html-target-libada-sjlj
++maybe-html-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-html-target-libada-sjlj: html-target-libada-sjlj
++
++# libada-sjlj doesn't support html.
++html-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-TAGS-target-libada-sjlj TAGS-target-libada-sjlj
++maybe-TAGS-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-TAGS-target-libada-sjlj: TAGS-target-libada-sjlj
++
++# libada-sjlj doesn't support TAGS.
++TAGS-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-install-info-target-libada-sjlj install-info-target-libada-sjlj
++maybe-install-info-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-install-info-target-libada-sjlj: install-info-target-libada-sjlj
++
++# libada-sjlj doesn't support install-info.
++install-info-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-install-pdf-target-libada-sjlj install-pdf-target-libada-sjlj
++maybe-install-pdf-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-install-pdf-target-libada-sjlj: install-pdf-target-libada-sjlj
++
++install-pdf-target-libada-sjlj: \
++    configure-target-libada-sjlj \
++    pdf-target-libada-sjlj 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-pdf) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-install-html-target-libada-sjlj install-html-target-libada-sjlj
++maybe-install-html-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-install-html-target-libada-sjlj: install-html-target-libada-sjlj
++
++install-html-target-libada-sjlj: \
++    configure-target-libada-sjlj \
++    html-target-libada-sjlj 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-html) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-installcheck-target-libada-sjlj installcheck-target-libada-sjlj
++maybe-installcheck-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-installcheck-target-libada-sjlj: installcheck-target-libada-sjlj
++
++# libada-sjlj doesn't support installcheck.
++installcheck-target-libada-sjlj:
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-mostlyclean-target-libada-sjlj mostlyclean-target-libada-sjlj
++maybe-mostlyclean-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-mostlyclean-target-libada-sjlj: mostlyclean-target-libada-sjlj
++
++mostlyclean-target-libada-sjlj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           mostlyclean) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-clean-target-libada-sjlj clean-target-libada-sjlj
++maybe-clean-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-clean-target-libada-sjlj: clean-target-libada-sjlj
++
++clean-target-libada-sjlj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing clean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           clean) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-distclean-target-libada-sjlj distclean-target-libada-sjlj
++maybe-distclean-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-distclean-target-libada-sjlj: distclean-target-libada-sjlj
++
++distclean-target-libada-sjlj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           distclean) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++.PHONY: maybe-maintainer-clean-target-libada-sjlj maintainer-clean-target-libada-sjlj
++maybe-maintainer-clean-target-libada-sjlj:
++@if target-libada-sjlj
++maybe-maintainer-clean-target-libada-sjlj: maintainer-clean-target-libada-sjlj
++
++maintainer-clean-target-libada-sjlj: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libada-sjlj && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           maintainer-clean) \
++	  || exit 1
++
++@endif target-libada-sjlj
++
++
++
++
++
+ .PHONY: configure-target-libgnatvsn maybe-configure-target-libgnatvsn
+ maybe-configure-target-libgnatvsn:
+ @if gcc-bootstrap
+@@ -50993,6 +51357,7 @@ configure-target-zlib: stage_last
+ configure-target-boehm-gc: stage_last
+ configure-target-rda: stage_last
+ configure-target-libada: stage_last
++configure-target-libada-sjlj: stage_last
+ configure-target-libgnatvsn: stage_last
+ configure-target-libgnatprj: stage_last
+ configure-stage1-target-libgomp: maybe-all-stage1-gcc
+@@ -51030,6 +51395,7 @@ configure-target-zlib: maybe-all-gcc
+ configure-target-boehm-gc: maybe-all-gcc
+ configure-target-rda: maybe-all-gcc
+ configure-target-libada: maybe-all-gcc
++configure-target-libada-sjlj: maybe-all-gcc
+ configure-target-libgnatvsn: maybe-all-gcc
+ configure-target-libgnatprj: maybe-all-gcc
+ configure-target-libgomp: maybe-all-gcc
+@@ -51404,6 +51770,7 @@ all-stage4-fixincludes: maybe-all-stage4
+ all-stageprofile-fixincludes: maybe-all-stageprofile-libiberty
+ all-stagefeedback-fixincludes: maybe-all-stagefeedback-libiberty
+ all-target-libada: maybe-all-gcc
++all-target-libada-sjlj: maybe-all-target-libada
+ all-gnattools: maybe-all-target-libada
+ all-gnattools: maybe-all-target-libgnatvsn
+ all-gnattools: maybe-all-target-libgnatprj
+@@ -52007,6 +52374,7 @@ configure-target-zlib: maybe-all-target-
+ configure-target-boehm-gc: maybe-all-target-libgcc
+ configure-target-rda: maybe-all-target-libgcc
+ configure-target-libada: maybe-all-target-libgcc
++configure-target-libada-sjlj: maybe-all-target-libgcc
+ configure-target-libgnatvsn: maybe-all-target-libgcc
+ configure-target-libgnatprj: maybe-all-target-libgcc
+ configure-target-libgomp: maybe-all-target-libgcc
+@@ -52063,6 +52431,8 @@ configure-target-rda: maybe-all-target-n
+ 
+ configure-target-libada: maybe-all-target-newlib maybe-all-target-libgloss
+ 
++configure-target-libada-sjlj: maybe-all-target-newlib maybe-all-target-libgloss
++
+ configure-target-libgnatvsn: maybe-all-target-newlib maybe-all-target-libgloss
+ 
+ configure-target-libgnatprj: maybe-all-target-newlib maybe-all-target-libgloss
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -176,6 +176,7 @@ target_libraries="target-libgcc \
+ 		${libgcj} \
+ 		target-libobjc \
+ 		target-libada \
++		target-libada-sjlj \
+ 		${target_libiberty} \
+ 		target-libgnatvsn \
+ 		target-libgnatprj \
+@@ -463,7 +464,7 @@ AC_ARG_ENABLE(libada,
+ ENABLE_LIBADA=$enableval,
+ ENABLE_LIBADA=yes)
+ if test "${ENABLE_LIBADA}" != "yes" ; then
+-  noconfigdirs="$noconfigdirs target-libgnatvsn target-libgnatprj gnattools"
++  noconfigdirs="$noconfigdirs target-libgnatvsn target-libgnatprj gnattools target-libada-sjlj"
+ fi
+ 
+ AC_ARG_ENABLE(libssp,
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -192,7 +192,7 @@ TOOLSCASE =
+ 
+ # Multilib handling
+ MULTISUBDIR =
+-RTSDIR = rts$(subst /,_,$(MULTISUBDIR))
++RTSDIR := rts$(subst /,_,$(MULTISUBDIR))
+ 
+ # Link flags used to build gnat tools.  By default we prefer to statically
+ # link with libgcc to avoid a dependency on shared libgcc (which is tricky
+@@ -2633,6 +2633,27 @@ install-gnatlib: ../stamp-gnatlib-$(RTSD
+ 	cd $(DESTDIR)$(ADA_INCLUDE_DIR); $(CHMOD) a-wx *.adb
+ 	cd $(DESTDIR)$(ADA_INCLUDE_DIR); $(CHMOD) a-wx *.ads
+ 
++install-gnatlib-sjlj: ../stamp-gnatlib-$(RTSDIR)
++#	Create the directory before deleting it, in case the directory is
++#	a list of directories (as it may be on VMS). This ensures we are
++#	deleting the right one.
++	-$(MKDIR) $(DESTDIR)$(ADA_RTL_OBJ_DIR_SJLJ)
++	-$(MKDIR) $(DESTDIR)$(ADA_INCLUDE_DIR_SJLJ)
++	$(RMDIR) $(DESTDIR)$(ADA_RTL_OBJ_DIR_SJLJ)
++	$(RMDIR) $(DESTDIR)$(ADA_INCLUDE_DIR_SJLJ)
++	-$(MKDIR) $(DESTDIR)$(ADA_RTL_OBJ_DIR_SJLJ)
++	-$(MKDIR) $(DESTDIR)$(ADA_INCLUDE_DIR_SJLJ)
++	for file in $(RTSDIR)/*.ali; do \
++	    $(INSTALL_DATA_DATE) $$file $(DESTDIR)$(ADA_RTL_OBJ_DIR_SJLJ); \
++	done
++	# This copy must be done preserving the date on the original file.
++	for file in $(RTSDIR)/*.ad?; do \
++	    $(INSTALL_DATA_DATE) $$file $(DESTDIR)$(ADA_INCLUDE_DIR_SJLJ); \
++	done
++	cd $(DESTDIR)$(ADA_INCLUDE_DIR_SJLJ); $(CHMOD) a-wx *.adb
++	cd $(DESTDIR)$(ADA_INCLUDE_DIR_SJLJ); $(CHMOD) a-wx *.ads
++
++
+ ../stamp-gnatlib1-$(RTSDIR): Makefile
+ 	$(RMDIR) $(RTSDIR)
+ 	$(MKDIR) $(RTSDIR)
+@@ -2889,7 +2910,7 @@ gnatlib-shared:
+ # in getting multiple blank lines, hence a style check error, as a
+ # result.
+ gnatlib-sjlj:
+-	$(MAKE) $(FLAGS_TO_PASS) EH_MECHANISM="" \
++	$(MAKE) $(FLAGS_TO_PASS) EH_MECHANISM="" RTSDIR="$(RTSDIR)" \
+ 	THREAD_KIND="$(THREAD_KIND)" ../stamp-gnatlib1-$(RTSDIR)
+ 	sed \
+ 	  -e 's/Frontend_Exceptions.*/Frontend_Exceptions       : constant Boolean := True;/' \
+@@ -2898,6 +2919,7 @@ gnatlib-sjlj:
+ 	  $(RTSDIR)/system.ads > $(RTSDIR)/s.ads
+ 	$(MV) $(RTSDIR)/s.ads $(RTSDIR)/system.ads
+ 	$(MAKE) $(FLAGS_TO_PASS) \
++	     RTSDIR="$(RTSDIR)" \
+ 	     EH_MECHANISM="" \
+ 	     GNATLIBFLAGS="$(GNATLIBFLAGS)" \
+ 	     GNATLIBCFLAGS="$(GNATLIBCFLAGS)" \
+@@ -2950,6 +2972,8 @@ b_gnatm.o : b_gnatm.adb
+ 
+ ADA_INCLUDE_DIR = $(libsubdir)/adainclude
+ ADA_RTL_OBJ_DIR = $(libsubdir)/adalib
++ADA_INCLUDE_DIR_SJLJ = $(libsubdir)/rts-sjlj/adainclude
++ADA_RTL_OBJ_DIR_SJLJ = $(libsubdir)/rts-sjlj/adalib
+ 
+ # Special flags
+ 
+Index: b/src/gcc/ada/gcc-interface/config-lang.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/config-lang.in
++++ b/src/gcc/ada/gcc-interface/config-lang.in
+@@ -34,8 +34,8 @@ gtfiles="\$(srcdir)/ada/gcc-interface/ad
+ 
+ outputs="ada/gcc-interface/Makefile ada/Makefile"
+ 
+-target_libs="target-libada target-libgnatvsn target-libgnatprj"
+-lang_dirs="libada libgnatvsn libgnatprj gnattools"
++target_libs="target-libada target-libgnatvsn target-libgnatprj target-libada-sjlj"
++lang_dirs="libada libgnatvsn libgnatprj gnattools libada-sjlj"
+ 
+ # Ada is not enabled by default for the time being.
+ build_by_default=no
+Index: b/src/gcc/ada/gcc-interface/Make-lang.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Make-lang.in
++++ b/src/gcc/ada/gcc-interface/Make-lang.in
+@@ -784,6 +784,7 @@ ada.install-common:
+ 
+ install-gnatlib:
+ 	$(MAKE) -C ada $(COMMON_FLAGS_TO_PASS) $(ADA_FLAGS_TO_PASS) install-gnatlib$(LIBGNAT_TARGET)
++	$(MAKE) -C ada $(COMMON_FLAGS_TO_PASS) $(ADA_FLAGS_TO_PASS) RTSDIR="rts-sjlj" install-gnatlib-sjlj$(LIBGNAT_TARGET)
+ 
+ install-gnatlib-obj:
+ 	$(MAKE) -C ada $(COMMON_FLAGS_TO_PASS) $(ADA_FLAGS_TO_PASS) install-gnatlib-obj
--- gcc-6-6.4.0.orig/debian/patches/ada-symbolic-tracebacks.diff
+++ gcc-6-6.4.0/debian/patches/ada-symbolic-tracebacks.diff
@@ -0,0 +1,401 @@
+# DP: - Enable support for symbolic tracebacks in exceptions (delete the dummy
+# DP:   convert_addresses from adaint.c, and provide a real one separately.)
+
+Ported Jürgen Pfeifer's patch to enable symbolic tracebacks on Debian
+GNU/Linux.
+
+The binary distribution of GNAT 3.15p comes with an old version of
+binutils that includes a library, libaddr2line.a.  This library does
+not exist in recent versions of binutils.  The patch works around this
+by calling /usr/bin/addr2line (still part of binutils) and parsing the
+output.  See debian/convert_addresses.c for the gory details.
+
+I have modified convert_addresses.c to not use a shell script anymore;
+Debian controls the version of binutils which is installed.  Also, I
+use execve instead of execle.
+
+-- 
+Ludovic Brenta.
+
+# ' make emacs highlighting happy
+
+Index: b/src/gcc/ada/gcc-interface/Makefile.in
+===================================================================
+--- a/src/gcc/ada/gcc-interface/Makefile.in
++++ b/src/gcc/ada/gcc-interface/Makefile.in
+@@ -270,7 +270,8 @@
+ # Both . and srcdir are used, in that order,
+ # so that tm.h and config.h will be found in the compilation
+ # subdirectory rather than in the source directory.
+-INCLUDES = -I- -I. -I.. -I$(srcdir)/ada -I$(srcdir) -I$(ftop_srcdir)/include $(GMPINC)
++INCLUDES = -iquote . -iquote .. -iquote $(srcdir)/ada -iquote $(srcdir) \
++ -iquote $(ftop_srcdir)/include $(GMPINC)
+ 
+ ADA_INCLUDES = -I- -I. -I$(srcdir)/ada
+ 
+@@ -2426,7 +2427,7 @@
+ # library.  LIBGNAT_OBJS is the list of object files for libgnat.
+ # thread.c is special as put into GNATRTL_TASKING_OBJS by Makefile.rtl
+ LIBGNAT_OBJS = adadecode.o adaint.o argv.o aux-io.o 			\
+-  cal.o cio.o cstreams.o ctrl_c.o					\
++  cal.o cio.o convert_addresses.o cstreams.o ctrl_c.o			\
+   env.o errno.o exit.o expect.o final.o 				\
+   init.o initialize.o locales.o mkdir.o					\
+   raise.o seh_init.o socket.o sysdep.o					\
+@@ -3104,6 +3105,7 @@
+ socket.o  : socket.c gsocket.h
+ sysdep.o  : sysdep.c
+ raise.o   : raise.c raise.h
++convert_addresses.o : convert_addresses.c
+ sigtramp-armdroid.o : sigtramp-armdroid.c sigtramp.h
+ sigtramp-armvxw.o : sigtramp-armvxw.c sigtramp.h
+ sigtramp-ppcvxw.o : sigtramp-ppcvxw.c sigtramp.h
+Index: b/src/gcc/ada/adaint.c
+===================================================================
+--- a/src/gcc/ada/adaint.c
++++ b/src/gcc/ada/adaint.c
+@@ -3608,35 +3608,6 @@
+ }
+ #endif
+ 
+-#if defined (IS_CROSS)  \
+-  || (! ((defined (sparc) || defined (i386)) && defined (sun) \
+-      && defined (__SVR4)) \
+-      && ! (defined (linux) && (defined (i386) || defined (__x86_64__))) \
+-      && ! (defined (linux) && defined (__ia64__)) \
+-      && ! (defined (linux) && defined (powerpc)) \
+-      && ! defined (__FreeBSD__) \
+-      && ! defined (__Lynx__) \
+-      && ! defined (__hpux__) \
+-      && ! defined (__APPLE__) \
+-      && ! defined (_AIX) \
+-      && ! defined (VMS) \
+-      && ! defined (__MINGW32__))
+-
+-/* Dummy function to satisfy g-trasym.o. See the preprocessor conditional
+-   just above for a list of native platforms that provide a non-dummy
+-   version of this procedure in libaddr2line.a.  */
+-
+-void
+-convert_addresses (const char *file_name ATTRIBUTE_UNUSED,
+-		   void *addrs ATTRIBUTE_UNUSED,
+-		   int n_addr ATTRIBUTE_UNUSED,
+-		   void *buf ATTRIBUTE_UNUSED,
+-		   int *len ATTRIBUTE_UNUSED)
+-{
+-  *len = 0;
+-}
+-#endif
+-
+ #if defined (_WIN32)
+ int __gnat_argument_needs_quote = 1;
+ #else
+Index: b/src/gcc/ada/convert_addresses.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/ada/convert_addresses.c
+@@ -0,0 +1,159 @@
++/*
++  Copyright (C) 1999 by Juergen Pfeifer <juergen.pfeifer@gmx.net>
++  Ada for Linux Team (ALT)
++
++  Permission is hereby granted, free of charge, to any person obtaining a
++  copy of this software and associated documentation files (the
++  "Software"), to deal in the Software without restriction, including
++  without limitation the rights to use, copy, modify, merge, publish,
++  distribute, distribute with modifications, sublicense, and/or sell
++  copies of the Software, and to permit persons to whom the Software is
++  furnished to do so, subject to the following conditions:
++
++  The above copyright notice and this permission notice shall be included
++  in all copies or substantial portions of the Software.
++
++  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++  OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
++  IN NO EVENT SHALL THE ABOVE COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
++  DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++  OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
++  THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++
++  Except as contained in this notice, the name(s) of the above copyright
++  holders shall not be used in advertising or otherwise to promote the
++  sale, use or other dealings in this Software without prior written
++  authorization.
++*/
++#include <sys/types.h>
++#include <stdlib.h>
++#include <stdio.h>
++#include <unistd.h>
++#include <string.h>
++#include <signal.h>
++
++#define STDIN_FILENO  0
++#define STDOUT_FILENO 1
++#define MAX_LINE      1024
++
++#define CLOSE1  close(fd1[0]); close(fd1[1])
++#define CLOSE2  close(fd2[0]); close(fd2[1])
++#define RESTSIG sigaction(SIGPIPE,&oact,NULL)
++
++void convert_addresses
++(const char const *file_name,
++  void* addrs[],
++  int   n_addr,
++  char* buf,
++  int*  len)
++{
++  int max_len = *len;
++  pid_t child;
++
++  struct sigaction act, oact;
++
++  int fd1[2], fd2[2];
++
++  if (!file_name) {
++    return;
++  }
++
++  *buf = 0; *len = 0;
++  act.sa_handler = SIG_IGN;
++  sigemptyset(&act.sa_mask);
++  act.sa_flags = 0;
++  if (sigaction(SIGPIPE,&act,&oact) < 0)
++    return;
++
++  if (pipe(fd1) >= 0) {
++    if (pipe(fd2)>=0) {
++      if ((child = fork()) < 0) {
++      CLOSE1; CLOSE2; RESTSIG;
++      return;
++      }
++      else {
++      if (0==child) {
++        close(fd1[1]);
++        close(fd2[0]);
++        if (fd1[0] != STDIN_FILENO) {
++          if (dup2(fd1[0],STDIN_FILENO) != STDIN_FILENO) {
++            CLOSE1; CLOSE2;
++          }
++          close(fd1[0]);
++        }
++        if (fd2[1] != STDOUT_FILENO) {
++          if (dup2(fd2[1],STDOUT_FILENO) != STDOUT_FILENO) {
++            CLOSE1; CLOSE2;
++          }
++          close(fd2[1]);
++        }
++        {
++          /* As pointed out by Florian Weimer to me, it is a
++             security threat to call the script with a user defined
++             environment and using the path. That would be Trojans
++             pleasure.  Therefore we use the absolute path to
++             addr2line and an empty environment. That should be
++             safe.
++          */
++          char *file_name_for_execve = strdup (file_name); /* non-const */
++          char *const argv[] = { "addr2line",
++                                 "-e",
++                                 file_name_for_execve,
++                                 "--demangle=gnat",
++                                 "--functions",
++                                 "--basenames",
++                                 NULL };
++          char *const envp[] = { NULL };
++          if (execve("/usr/bin/addr2line", argv, envp) < 0) {
++            CLOSE1; CLOSE2;
++          }
++	  if (file_name_for_execve) { free (file_name_for_execve); }
++        }
++      }
++      else {
++        int i, n;
++        char hex[16];
++        char line[MAX_LINE + 1];
++        char *p;
++        char *s = buf;
++
++        /* Parent context */
++        close(fd1[0]);
++        close(fd2[1]);
++
++        for(i=0; i < n_addr; i++) {
++          snprintf(hex,sizeof(hex),"%p\n",addrs[i]);
++          write(fd1[1],hex,strlen(hex));
++          n = read(fd2[0],line,MAX_LINE);
++          if (n<=0)
++            break;
++          line[n]=0;
++          /* We have approx. 16 additional chars for "%p in " clause.
++             We use this info to prevent a buffer overrun.
++          */
++          if (n + 16 + (*len) > max_len)
++            break;
++          p = strchr(line,'\n');
++          if (p) {
++            if (*(p+1)) {
++              *p = 0;
++              *len += snprintf(s, (max_len - (*len)), "%p in %s at %s",addrs[i], line, p+1);
++            }
++            else {
++              *len += snprintf(s, (max_len - (*len)), "%p at %s",addrs[i], line);
++            }
++            s = buf + (*len);
++          }
++        }
++        close(fd1[1]);
++        close(fd2[0]);
++      }
++      }
++    }
++    else {
++      CLOSE1;
++    }
++  }
++  RESTSIG;
++}
+Index: b/src/gcc/ada/g-trasym.adb
+===================================================================
+--- a/src/gcc/ada/g-trasym.adb
++++ b/src/gcc/ada/g-trasym.adb
+@@ -33,40 +33,110 @@
+ --  is not supported. It returns tracebacks as lists of LF separated strings of
+ --  the form "0x..." corresponding to the addresses.
+ 
++with System.Soft_Links;
+ with Ada.Exceptions.Traceback; use Ada.Exceptions.Traceback;
+-with System.Address_Image;
+ 
+ package body GNAT.Traceback.Symbolic is
+ 
++   package TSL renames System.Soft_Links;
++
++   --  To perform the raw addresses to symbolic form translation we rely on a
++   --  libaddr2line symbolizer which examines debug info from a provided
++   --  executable file name, and an absolute path is needed to ensure the file
++   --  is always found. This is "__gnat_locate_exec_on_path (gnat_argv [0])"
++   --  for our executable file, a fairly heavy operation so we cache the
++   --  result.
++
++   Exename : System.Address;
++   --  Pointer to the name of the executable file to be used on all
++   --  invocations of the libaddr2line symbolization service.
++
++   Exename_Resolved : Boolean := False;
++   --  Flag to indicate whether we have performed the executable file name
++   --  resolution already. Relying on a not null Exename for this purpose
++   --  would be potentially inefficient as this is what we will get if the
++   --  resolution attempt fails.
++
+    ------------------------
+    -- Symbolic_Traceback --
+    ------------------------
+ 
+    function Symbolic_Traceback (Traceback : Tracebacks_Array) return String is
++
++      procedure convert_addresses
++        (filename : System.Address;
++         addrs    : System.Address;
++         n_addrs  : Integer;
++         buf      : System.Address;
++         len      : System.Address);
++      pragma Import (C, convert_addresses, "convert_addresses");
++      --  This is the procedure version of the Ada-aware addr2line. It places
++      --  in BUF a string representing the symbolic translation of the N_ADDRS
++      --  raw addresses provided in ADDRS, looked up in debug information from
++      --  FILENAME. LEN points to an integer which contains the size of the
++      --  BUF buffer at input and the result length at output.
++      --
++      --  Note that this procedure is *not* thread-safe.
++
++      type Argv_Array is array (0 .. 0) of System.Address;
++      gnat_argv : access Argv_Array;
++      pragma Import (C, gnat_argv, "gnat_argv");
++
++      function locate_exec_on_path
++        (c_exename : System.Address) return System.Address;
++      pragma Import (C, locate_exec_on_path, "__gnat_locate_exec_on_path");
++
++      B_Size : constant Integer := 256 * Traceback'Length;
++      Len    : Integer := B_Size;
++      Res    : String (1 .. B_Size);
++
++      use type System.Address;
++
+    begin
++      --  The symbolic translation of an empty set of addresses is an empty
++      --  string.
++
+       if Traceback'Length = 0 then
+          return "";
++      end if;
+ 
+-      else
+-         declare
+-            Img : String := System.Address_Image (Traceback (Traceback'First));
++      --  If our input set of raw addresses is not empty, resort to the
++      --  libaddr2line service to symbolize it all.
+ 
+-            Result : String (1 .. (Img'Length + 3) * Traceback'Length);
+-            Last   : Natural := 0;
++      --  Compute, cache and provide the absolute path to our executable file
++      --  name as the binary file where the relevant debug information is to be
++      --  found. If the executable file name resolution fails, we have no
++      --  sensible basis to invoke the symbolizer at all.
++
++      --  Protect all this against concurrent accesses explicitly, as the
++      --  underlying services are potentially thread unsafe.
++
++      TSL.Lock_Task.all;
++
++      if not Exename_Resolved then
++         Exename := locate_exec_on_path (gnat_argv (0));
++         Exename_Resolved := True;
++      end if;
++
++      if Exename /= System.Null_Address then
++         Len := Res'Length;
++         convert_addresses
++           (Exename, Traceback'Address, Traceback'Length,
++            Res (1)'Address, Len'Address);
++      end if;
++
++      TSL.Unlock_Task.all;
+ 
+-         begin
+-            for J in Traceback'Range loop
+-               Img := System.Address_Image (Traceback (J));
+-               Result (Last + 1 .. Last + 2) := "0x";
+-               Last := Last + 2;
+-               Result (Last + 1 .. Last + Img'Length) := Img;
+-               Last := Last + Img'Length + 1;
+-               Result (Last) := ASCII.LF;
+-            end loop;
++      --  Return what the addr2line symbolizer has produced if we have called
++      --  it (the executable name resolution succeeded), or an empty string
++      --  otherwise.
+ 
+-            return Result (1 .. Last);
+-         end;
++      if Exename /= System.Null_Address then
++         return Res (1 .. Len);
++      else
++         return "";
+       end if;
++
+    end Symbolic_Traceback;
+ 
+    function Symbolic_Traceback (E : Exception_Occurrence) return String is
+Index: b/src/gcc/ada/tracebak.c
+===================================================================
+--- a/src/gcc/ada/tracebak.c
++++ b/src/gcc/ada/tracebak.c
+@@ -425,7 +425,7 @@
+ /* Starting with GCC 4.6, -fomit-frame-pointer is turned on by default for
+    32-bit x86/Linux as well and DWARF 2 unwind tables are emitted instead.
+    See the x86-64 case below for the drawbacks with this approach.  */
+-#if defined (linux) && (__GNUC__ * 10 + __GNUC_MINOR__ > 45)
++#if (defined (linux) || defined(__GNU__)) && (__GNUC__ * 10 + __GNUC_MINOR__ > 45)
+ #define USE_GCC_UNWINDER
+ #else
+ #define USE_GENERIC_UNWINDER
--- gcc-6-6.4.0.orig/debian/patches/add-gnu-to-libgo-headers.diff
+++ gcc-6-6.4.0/debian/patches/add-gnu-to-libgo-headers.diff
@@ -0,0 +1,793 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/archive/tar/stat_atim.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/archive/tar/stat_atim.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/archive/tar/stat_atim.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build linux dragonfly openbsd solaris
++// +build linux dragonfly openbsd solaris gnu
+ 
+ package tar
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_resnew.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/cgo_resnew.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_resnew.go
+@@ -3,7 +3,7 @@
+ // license that can be found in the LICENSE file.
+ 
+ // +build cgo,!netgo
+-// +build darwin linux,!android netbsd solaris
++// +build darwin linux,!android netbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_socknew.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/cgo_socknew.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_socknew.go
+@@ -3,7 +3,7 @@
+ // license that can be found in the LICENSE file.
+ 
+ // +build cgo,!netgo
+-// +build android linux solaris
++// +build android linux solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/hook_cloexec.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/hook_cloexec.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/hook_cloexec.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build freebsd linux
++// +build freebsd linux gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/main_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/main_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/main_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sock_cloexec.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/sock_cloexec.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sock_cloexec.go
+@@ -5,7 +5,7 @@
+ // This file implements sysSocket and accept for platforms that
+ // provide a fast path for setting SetNonblock and CloseOnExec.
+ 
+-// +build freebsd linux
++// +build freebsd linux gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sockoptip_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/sockoptip_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sockoptip_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd windows
++// +build darwin dragonfly freebsd linux netbsd openbsd windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/exec_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/exec_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/exec_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ // Fork, exec, wait, etc.
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/runtime/netpoll_select.c
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/runtime/netpoll_select.c
++++ gcc-6-6.2.1-4.1/src/libgo/runtime/netpoll_select.c
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build solaris
++// +build solaris gnu
+ 
+ #include "config.h"
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/exec/lp_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/exec/lp_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/exec/lp_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package exec
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/exec/lp_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/exec/lp_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/exec/lp_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package exec
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/os_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/os_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/os_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package os_test
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/signal/signal_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/signal/signal_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/signal/signal_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package signal
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/signal/signal_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/signal/signal_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/signal/signal_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package signal
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/runtime/crash_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/runtime/crash_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/runtime/crash_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package runtime_test
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/exec_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/exec_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/exec_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package syscall_test
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/error_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/error_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/error_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package os
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/file_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/file_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/file_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package os
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/path_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/path_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/path_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package os
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/sys_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/sys_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/sys_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build dragonfly linux netbsd openbsd solaris
++// +build dragonfly linux netbsd openbsd solaris gnu
+ 
+ package os
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/user/decls_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/user/decls_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/user/decls_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd
++// +build darwin dragonfly freebsd linux netbsd openbsd gnu
+ // +build cgo
+ 
+ package user
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/user/lookup_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/user/lookup_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/user/lookup_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd !android,linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd !android,linux netbsd openbsd solaris gnu
+ // +build cgo
+ 
+ package user
+Index: gcc-6-6.2.1-4.1/src/libgo/go/runtime/runtime_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/runtime/runtime_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/runtime/runtime_unix_test.go
+@@ -6,7 +6,7 @@
+ // We need a fast system call to provoke the race,
+ // and Close(-1) is nearly universally fast.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd plan9
++// +build darwin dragonfly freebsd linux netbsd openbsd plan9 gnu
+ 
+ package runtime_test
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/env_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/env_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/env_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ // Unix environment variables.
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/exec_bsd.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/exec_bsd.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/exec_bsd.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd netbsd openbsd
++// +build darwin dragonfly freebsd netbsd openbsd gnu
+ 
+ package syscall
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/export_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/export_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/export_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd
++// +build darwin dragonfly freebsd linux netbsd openbsd gnu
+ 
+ package syscall
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/mmap_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/mmap_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/mmap_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd
++// +build darwin dragonfly freebsd linux netbsd openbsd gnu
+ 
+ package syscall_test
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/sockcmsg_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/sockcmsg_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/sockcmsg_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ // Socket control messages
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/syscall_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/syscall_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/syscall_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package syscall
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/time/sys_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/time/sys_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/time/sys_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package time
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/time/zoneinfo_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/time/zoneinfo_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/time/zoneinfo_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin,386 darwin,amd64 dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin,386 darwin,amd64 dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ // Parse "zoneinfo" time zone file.
+ // This is a fairly standard file format used on OS X, Linux, BSD, Sun, and others.
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/addrselect.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/addrselect.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/addrselect.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ // Minimal RFC 6724 address selection.
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/addrselect_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/addrselect_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/addrselect_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/cgo_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_unix.go
+@@ -3,7 +3,7 @@
+ // license that can be found in the LICENSE file.
+ 
+ // +build cgo,!netgo
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/cgo_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/cgo_unix_test.go
+@@ -3,7 +3,7 @@
+ // license that can be found in the LICENSE file.
+ 
+ // +build cgo,!netgo
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/conf.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/conf.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/conf.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/conf_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/conf_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/conf_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/dnsclient_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/dnsclient_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/dnsclient_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ // DNS client: see RFC 1035.
+ // Has to be linked into package net for Dial.
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/dnsconfig_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/dnsconfig_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/dnsconfig_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ // Read system DNS config from /etc/resolv.conf
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/dnsconfig_unix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/dnsconfig_unix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/dnsconfig_unix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/fd_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/fd_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/fd_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/fd_posix_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/fd_posix_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/fd_posix_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/fd_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/fd_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/fd_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/file_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/file_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/file_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/hook_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/hook_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/hook_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/interface_stub.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/interface_stub.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/interface_stub.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build nacl plan9 solaris
++// +build nacl plan9 solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/iprawsock_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/iprawsock_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/iprawsock_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/ipsock_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/ipsock_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/ipsock_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ // Internet protocol family sockets for POSIX
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/lookup_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/lookup_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/lookup_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/nss.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/nss.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/nss.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/nss_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/nss_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/nss_test.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/port_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/port_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/port_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris gnu
+ 
+ // Read system port mappings from /etc/services
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sockopt_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/sockopt_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sockopt_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sock_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/sock_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sock_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/tcpsockopt_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/tcpsockopt_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/tcpsockopt_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/tcpsockopt_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/tcpsockopt_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/tcpsockopt_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build freebsd linux netbsd
++// +build freebsd linux netbsd gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/tcpsock_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/tcpsock_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/tcpsock_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/udpsock_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/udpsock_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/udpsock_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/unixsock_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/net/unixsock_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/unixsock_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package net
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/exec_posix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/exec_posix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/exec_posix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows gnu
+ 
+ package os
+ 
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/file_unix.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/file_unix.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/file_unix.go
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris
++// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris gnu
+ 
+ package os
+ 
--- gcc-6-6.4.0.orig/debian/patches/alpha-ieee-doc.diff
+++ gcc-6-6.4.0/debian/patches/alpha-ieee-doc.diff
@@ -0,0 +1,24 @@
+# DP: #212912
+# DP: on alpha-linux, make -mieee default and add -mieee-disable switch
+# DP: to turn default off (doc patch)
+
+---
+ gcc/doc/invoke.texi |    7 +++++++
+ 1 files changed, 7 insertions(+), 0 deletions(-)
+
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -9980,6 +9980,13 @@ able to correctly support denormalized numbers and exceptional IEEE
+ values such as not-a-number and plus/minus infinity.  Other Alpha
+ compilers call this option @option{-ieee_with_no_inexact}.
+ 
++DEBIAN SPECIFIC: This option is on by default for alpha-linux-gnu, unless
++@option{-ffinite-math-only} (which is part of the @option{-ffast-math}
++set) is specified, because the software functions in the GNU libc math
++libraries generate denormalized numbers, NaNs, and infs (all of which
++will cause a programs to SIGFPE when it attempts to use the results without
++@option{-mieee}).
++
+ @item -mieee-with-inexact
+ @opindex mieee-with-inexact
+ This is like @option{-mieee} except the generated code also maintains
--- gcc-6-6.4.0.orig/debian/patches/alpha-ieee.diff
+++ gcc-6-6.4.0/debian/patches/alpha-ieee.diff
@@ -0,0 +1,21 @@
+# DP: #212912
+# DP: on alpha-linux, make -mieee default and add -mieee-disable switch
+# DP: to turn default off
+
+---
+ gcc/config/alpha/alpha.c |    4 ++++
+ 1 files changed, 4 insertions(+), 0 deletions(-)
+
+--- a/src/gcc/config/alpha/alpha.c
++++ b/src/gcc/config/alpha/alpha.c
+@@ -259,6 +259,10 @@
+   int line_size = 0, l1_size = 0, l2_size = 0;
+   int i;
+ 
++  /* If not -ffinite-math-only, enable -mieee*/
++  if (!flag_finite_math_only)
++    target_flags |= MASK_IEEE|MASK_IEEE_CONFORMANT;
++
+ #ifdef SUBTARGET_OVERRIDE_OPTIONS
+   SUBTARGET_OVERRIDE_OPTIONS;
+ #endif
--- gcc-6-6.4.0.orig/debian/patches/alpha-no-ev4-directive.diff
+++ gcc-6-6.4.0/debian/patches/alpha-no-ev4-directive.diff
@@ -0,0 +1,32 @@
+# DP: never emit .ev4 directive.
+
+---
+ gcc/config/alpha/alpha.c |    7 +++----
+ 1 files changed, 3 insertions(+), 4 deletions(-)
+
+Index: b/src/gcc/config/alpha/alpha.c
+===================================================================
+--- a/src/gcc/config/alpha/alpha.c
++++ b/src/gcc/config/alpha/alpha.c
+@@ -9460,7 +9460,7 @@ alpha_file_start (void)
+     fputs ("\t.set nomacro\n", asm_out_file);
+   if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
+     {
+-      const char *arch;
++      const char *arch = NULL;
+ 
+       if (alpha_cpu == PROCESSOR_EV6 || TARGET_FIX || TARGET_CIX)
+ 	arch = "ev6";
+@@ -9470,10 +9470,9 @@ alpha_file_start (void)
+ 	arch = "ev56";
+       else if (alpha_cpu == PROCESSOR_EV5)
+ 	arch = "ev5";
+-      else
+-	arch = "ev4";
+ 
+-      fprintf (asm_out_file, "\t.arch %s\n", arch);
++      if (arch)
++        fprintf (asm_out_file, "\t.arch %s\n", arch);
+     }
+ }
+ 
--- gcc-6-6.4.0.orig/debian/patches/aotcompile.diff
+++ gcc-6-6.4.0/debian/patches/aotcompile.diff
@@ -0,0 +1,51 @@
+--- ./build/aot/aotcompile.py.orig	2010-04-08 13:38:27.621086079 +0000
++++ ./build/aot/aotcompile.py	2010-04-08 14:22:55.102335973 +0000
+@@ -31,12 +31,25 @@
+          "dbtool": "/usr/lib/gcc-snapshot/bin/gcj-dbtool"}
+ 
+ MAKEFLAGS = []
+-GCJFLAGS = ["-fPIC", "-findirect-dispatch", "-fjni"]
++GCJFLAGS = ["-O2 -fPIC", "-findirect-dispatch", "-fjni"]
+ LDFLAGS = ["-Wl,-Bsymbolic"]
+ 
+ MAX_CLASSES_PER_JAR = 1024
+ MAX_BYTES_PER_JAR = 1048576
+ 
++try:
++    for line in file('/proc/meminfo'):
++        if line.startswith('MemTotal:'):
++            memtotal = int(line.split()[1])
++        if memtotal < 270000:
++            MAX_CLASSES_PER_JAR = 512
++            MAX_BYTES_PER_JAR = 524288
++        if memtotal < 140000:
++            MAX_CLASSES_PER_JAR = 256
++            MAX_BYTES_PER_JAR = 262144
++except:
++    pass
++
+ MAKEFILE = "Makefile"
+ 
+ MAKEFILE_HEADER = '''\
+@@ -49,7 +62,7 @@
+ 	$(GCJ) -c $(GCJFLAGS) $< -o $@
+ 
+ TARGETS = \\
+-%(targets)s
++javac ecj1
+ 
+ all: $(TARGETS)'''
+ 
+@@ -63,6 +76,12 @@
+ %(dso)s: $(%(base)s_OBJECTS)
+ 	$(GCJ) -shared $(GCJFLAGS) $(LDFLAGS) $^ -o $@
+ 
++javac: $(%(base)s_OBJECTS) resources.o
++	$(GCJ) $(GCJFLAGS) $(RPATH) -Wl,-O1 --main=org.eclipse.jdt.internal.compiler.batch.Main $^ -o $@
++
++ecj1: $(%(base)s_OBJECTS) resources.o
++	$(GCJ) $(GCJFLAGS) $(RPATH) -Wl,-O1 --main=org.eclipse.jdt.internal.compiler.batch.GCCMain $^ -o $@
++
+ %(db)s: $(%(base)s_SOURCES)
+ 	$(DBTOOL) -n $@ 64
+ 	for jar in $^; do \\
--- gcc-6-6.4.0.orig/debian/patches/arm-multilib-defaults.diff
+++ gcc-6-6.4.0/debian/patches/arm-multilib-defaults.diff
@@ -0,0 +1,92 @@
+# DP: Set MULTILIB_DEFAULTS for ARM multilib builds
+
+Index: b/src/gcc/config.gcc
+===================================================================
+--- a/src/gcc/config.gcc
++++ b/src/gcc/config.gcc
+@@ -3743,10 +3743,18 @@ case "${target}" in
+ 		fi
+ 
+ 		case "$with_float" in
+-		"" \
+-		| soft | hard | softfp)
++		"")
+ 			# OK
+ 			;;
++		soft)
++			tm_defines="${tm_defines} TARGET_CONFIGURED_FLOAT_ABI=0"
++			;;
++		softfp)
++			tm_defines="${tm_defines} TARGET_CONFIGURED_FLOAT_ABI=1"
++			;;
++		hard)
++			tm_defines="${tm_defines} TARGET_CONFIGURED_FLOAT_ABI=2"
++			;;
+ 		*)
+ 			echo "Unknown floating point type used in --with-float=$with_float" 1>&2
+ 			exit 1
+@@ -3780,6 +3788,9 @@ case "${target}" in
+ 		"" \
+ 		| arm | thumb )
+ 			#OK
++			if test "$with_mode" = thumb; then
++				tm_defines="${tm_defines} TARGET_CONFIGURED_THUMB_MODE=1"
++			fi
+ 			;;
+ 		*)
+ 			echo "Unknown mode used in --with-mode=$with_mode"
+Index: b/src/gcc/config/arm/linux-eabi.h
+===================================================================
+--- a/src/gcc/config/arm/linux-eabi.h
++++ b/src/gcc/config/arm/linux-eabi.h
+@@ -43,7 +43,21 @@
+    target hardware.  If you override this to use the hard-float ABI then
+    change the setting of GLIBC_DYNAMIC_LINKER_DEFAULT as well.  */
+ #undef  TARGET_DEFAULT_FLOAT_ABI
++#ifdef TARGET_CONFIGURED_FLOAT_ABI
++#if TARGET_CONFIGURED_FLOAT_ABI == 2
++#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_HARD
++#define MULTILIB_DEFAULT_FLOAT_ABI "mfloat-abi=hard"
++#elif TARGET_CONFIGURED_FLOAT_ABI == 1
++#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFTFP
++#define MULTILIB_DEFAULT_FLOAT_ABI "mfloat-abi=softfp"
++#else
++#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
++#define MULTILIB_DEFAULT_FLOAT_ABI "mfloat-abi=soft"
++#endif
++#else
+ #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
++#define MULTILIB_DEFAULT_FLOAT_ABI "mfloat-abi=soft"
++#endif
+ 
+ /* We default to the "aapcs-linux" ABI so that enums are int-sized by
+    default.  */
+@@ -103,6 +117,28 @@
+ #define MUSL_DYNAMIC_LINKER \
+   "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}.so.1"
+ 
++/* Set the multilib defaults according the configuration, needed to
++   let gcc -print-multi-dir do the right thing.  */
++
++#if TARGET_BIG_ENDIAN_DEFAULT
++#define MULTILIB_DEFAULT_ENDIAN "mbig-endian"
++#else
++#define MULTILIB_DEFAULT_ENDIAN "mlittle-endian"
++#endif
++
++#ifndef TARGET_CONFIGURED_THUMB_MODE
++#define MULTILIB_DEFAULT_MODE "marm"
++#elif TARGET_CONFIGURED_THUMB_MODE == 1
++#define MULTILIB_DEFAULT_MODE "mthumb"
++#else
++#define MULTILIB_DEFAULT_MODE "marm"
++#endif
++
++#undef  MULTILIB_DEFAULTS
++#define MULTILIB_DEFAULTS \
++	{ MULTILIB_DEFAULT_MODE, MULTILIB_DEFAULT_ENDIAN, \
++	  MULTILIB_DEFAULT_FLOAT_ABI, "mno-thumb-interwork" }
++
+ /* At this point, bpabi.h will have clobbered LINK_SPEC.  We want to
+    use the GNU/Linux version, not the generic BPABI version.  */
+ #undef  LINK_SPEC
--- gcc-6-6.4.0.orig/debian/patches/arm-multilib-soft-cross.diff
+++ gcc-6-6.4.0/debian/patches/arm-multilib-soft-cross.diff
@@ -0,0 +1,27 @@
+# DP: ARM hard/soft float multilib support
+
+Index: b/src/gcc/config/arm/t-linux-eabi
+===================================================================
+--- a/src/gcc/config/arm/t-linux-eabi
++++ b/src/gcc/config/arm/t-linux-eabi
+@@ -21,6 +21,20 @@
+ MULTILIB_OPTIONS	=
+ MULTILIB_DIRNAMES	=
+ 
++ifeq ($(with_float),hard)
++MULTILIB_OPTIONS	= mfloat-abi=soft/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?soft=msoft-float mfloat-abi?soft=mfloat-abi?softfp
++MULTILIB_OSDIRNAMES	= ../libsf:arm-linux-gnueabi ../lib:arm-linux-gnueabihf
++else
++MULTILIB_OPTIONS	= mfloat-abi=soft/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?soft=msoft-float mfloat-abi?soft=mfloat-abi?softfp
++MULTILIB_OSDIRNAMES	= ../lib:arm-linux-gnueabi ../libhf:arm-linux-gnueabihf
++endif
++
+ #MULTILIB_OPTIONS     += mcpu=fa606te/mcpu=fa626te/mcpu=fmp626/mcpu=fa726te
+ #MULTILIB_DIRNAMES    += fa606te fa626te fmp626 fa726te
+ #MULTILIB_EXCEPTIONS  += *mthumb/*mcpu=fa606te *mthumb/*mcpu=fa626te *mthumb/*mcpu=fmp626 *mthumb/*mcpu=fa726te*
--- gcc-6-6.4.0.orig/debian/patches/arm-multilib-soft-float.diff
+++ gcc-6-6.4.0/debian/patches/arm-multilib-soft-float.diff
@@ -0,0 +1,26 @@
+--- a/src/gcc/config/arm/t-linux-eabi
++++ b/src/gcc/config/arm/t-linux-eabi
+@@ -24,6 +24,23 @@
+ MULTILIB_OPTIONS	=
+ MULTILIB_DIRNAMES	=
+ 
++ifneq (,$(findstring MULTIARCH_DEFAULTS,$(tm_defines)))
++ifneq (,$(findstring __arm_linux_gnueabi__,$(tm_defines)))
++  MULTILIB_OPTIONS	= mfloat-abi=softfp/mfloat-abi=hard/mfloat-abi=soft
++  MULTILIB_DIRNAMES	= . hf soft-float
++  MULTILIB_EXCEPTIONS	=
++  MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?soft=msoft-float
++  MULTILIB_OSDIRNAMES	= ../../lib/arm-linux-gnueabi ../../lib/arm-linux-gnueabihf soft-float
++endif
++ifneq (,$(findstring __arm_linux_gnueabihf__,$(tm_defines)))
++  MULTILIB_OPTIONS	= mfloat-abi=hard/mfloat-abi=softfp/mfloat-abi=soft
++  MULTILIB_DIRNAMES	= . sf soft-float
++  MULTILIB_EXCEPTIONS	=
++  MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?soft=msoft-float
++  MULTILIB_OSDIRNAMES	= ../../lib/arm-linux-gnueabihf ../../lib/arm-linux-gnueabi soft-float
++endif
++endif
++
+ #MULTILIB_OPTIONS     += mcpu=fa606te/mcpu=fa626te/mcpu=fmp626/mcpu=fa726te
+ #MULTILIB_DIRNAMES    += fa606te fa626te fmp626 fa726te
+ #MULTILIB_EXCEPTIONS  += *mthumb/*mcpu=fa606te *mthumb/*mcpu=fa626te *mthumb/*mcpu=fmp626 *mthumb/*mcpu=fa726te*
--- gcc-6-6.4.0.orig/debian/patches/arm-multilib-soft.diff
+++ gcc-6-6.4.0/debian/patches/arm-multilib-soft.diff
@@ -0,0 +1,27 @@
+# DP: ARM hard/soft float multilib support
+
+Index: b/src/gcc/config/arm/t-linux-eabi
+===================================================================
+--- a/src/gcc/config/arm/t-linux-eabi
++++ b/src/gcc/config/arm/t-linux-eabi
+@@ -23,6 +23,20 @@
+ MULTILIB_OPTIONS	=
+ MULTILIB_DIRNAMES	=
+ 
++ifeq ($(with_float),hard)
++MULTILIB_OPTIONS	= mfloat-abi=soft/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?soft=msoft-float mfloat-abi?soft=mfloat-abi?softfp
++MULTILIB_OSDIRNAMES	= arm-linux-gnueabi:arm-linux-gnueabi ../lib:arm-linux-gnueabihf
++else
++MULTILIB_OPTIONS	= mfloat-abi=soft/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?soft=msoft-float mfloat-abi?soft=mfloat-abi?softfp
++MULTILIB_OSDIRNAMES	= ../lib:arm-linux-gnueabi arm-linux-gnueabihf:arm-linux-gnueabihf
++endif
++
+ #MULTILIB_OPTIONS     += mcpu=fa606te/mcpu=fa626te/mcpu=fmp626/mcpu=fa726te
+ #MULTILIB_DIRNAMES    += fa606te fa626te fmp626 fa726te
+ #MULTILIB_EXCEPTIONS  += *mthumb/*mcpu=fa606te *mthumb/*mcpu=fa626te *mthumb/*mcpu=fmp626 *mthumb/*mcpu=fa726te*
--- gcc-6-6.4.0.orig/debian/patches/arm-multilib-softfp-cross.diff
+++ gcc-6-6.4.0/debian/patches/arm-multilib-softfp-cross.diff
@@ -0,0 +1,27 @@
+# DP: ARM hard/softfp float multilib support
+
+Index: b/src/gcc/config/arm/t-linux-eabi
+===================================================================
+--- a/src/gcc/config/arm/t-linux-eabi	2011-01-03 20:52:22.000000000 +0000
++++ b/src/gcc/config/arm/t-linux-eabi	2011-08-21 21:08:47.583351817 +0000
+@@ -24,6 +24,20 @@
+ MULTILIB_OPTIONS	=
+ MULTILIB_DIRNAMES	=
+ 
++ifeq ($(with_float),hard)
++MULTILIB_OPTIONS	= mfloat-abi=softfp/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?softfp=msoft-float mfloat-abi?softfp=mfloat-abi?soft
++MULTILIB_OSDIRNAMES	= ../libsf:arm-linux-gnueabi ../lib:arm-linux-gnueabihf
++else
++MULTILIB_OPTIONS	= mfloat-abi=softfp/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?softfp=msoft-float mfloat-abi?softfp=mfloat-abi?soft
++MULTILIB_OSDIRNAMES	= ../lib:arm-linux-gnueabi ../libhf:arm-linux-gnueabihf
++endif
++
+ #MULTILIB_OPTIONS     += mcpu=fa606te/mcpu=fa626te/mcpu=fmp626/mcpu=fa726te
+ #MULTILIB_DIRNAMES    += fa606te fa626te fmp626 fa726te
+ #MULTILIB_EXCEPTIONS  += *mthumb/*mcpu=fa606te *mthumb/*mcpu=fa626te *mthumb/*mcpu=fmp626 *mthumb/*mcpu=fa726te*
--- gcc-6-6.4.0.orig/debian/patches/arm-multilib-softfp.diff
+++ gcc-6-6.4.0/debian/patches/arm-multilib-softfp.diff
@@ -0,0 +1,27 @@
+# DP: ARM hard/softfp float multilib support
+
+Index: b/src/gcc/config/arm/t-linux-eabi
+===================================================================
+--- a/src/gcc/config/arm/t-linux-eabi	2011-01-03 20:52:22.000000000 +0000
++++ b/src/gcc/config/arm/t-linux-eabi	2011-08-21 21:08:47.583351817 +0000
+@@ -24,6 +24,20 @@
+ MULTILIB_OPTIONS	=
+ MULTILIB_DIRNAMES	=
+ 
++ifeq ($(with_float),hard)
++MULTILIB_OPTIONS	= mfloat-abi=softfp/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?softfp=msoft-float mfloat-abi?softfp=mfloat-abi?soft
++MULTILIB_OSDIRNAMES	= arm-linux-gnueabi:arm-linux-gnueabi ../lib:arm-linux-gnueabihf
++else
++MULTILIB_OPTIONS	= mfloat-abi=softfp/mfloat-abi=hard
++MULTILIB_DIRNAMES	= sf hf
++MULTILIB_EXCEPTIONS	=
++MULTILIB_MATCHES	= mfloat-abi?hard=mhard-float mfloat-abi?softfp=msoft-float mfloat-abi?softfp=mfloat-abi?soft
++MULTILIB_OSDIRNAMES	= ../lib:arm-linux-gnueabi arm-linux-gnueabihf:arm-linux-gnueabihf
++endif
++
+ #MULTILIB_OPTIONS     += mcpu=fa606te/mcpu=fa626te/mcpu=fmp626/mcpu=fa726te
+ #MULTILIB_DIRNAMES    += fa606te fa626te fmp626 fa726te
+ #MULTILIB_EXCEPTIONS  += *mthumb/*mcpu=fa606te *mthumb/*mcpu=fa626te *mthumb/*mcpu=fmp626 *mthumb/*mcpu=fa726te*
--- gcc-6-6.4.0.orig/debian/patches/asan-Enable-48-bit-VMA-support-on-aarch64.diff
+++ gcc-6-6.4.0/debian/patches/asan-Enable-48-bit-VMA-support-on-aarch64.diff
@@ -0,0 +1,27 @@
+Description: [asan] Enable 48-bit VMA support on aarch64
+ This patch adds 48-bits VMA support for asan on aarch64. The current
+ 47-bit mask is not suffice since on aarch64 kernel with 48-bit vma
+ (default on ubuntu 16.04) the process may use full VMA range as:
+ .
+ [...]
+ ffffa39a7000-ffffa39a8000 r--p 00000000 00:00 0 [vvar]
+ ffffa39a8000-ffffa39a9000 r-xp 00000000 00:00 0 [vdso]
+ ffffa39a9000-ffffa39aa000 r--p 0001c000 08:02 13631554 /lib/aarch64-linux-gnu/ld-2.23.so
+ ffffa39aa000-ffffa39ac000 rw-p 0001d000 08:02 13631554 /lib/aarch64-linux-gnu/ld-2.23.so
+ ffffc2227000-ffffc2248000 rw-p 00000000 00:00 0 [stack]
+Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
+Origin: http://llvm.org/svn/llvm-project/compiler-rt/trunk@275792
+Bug-Ubuntu: https://bugs.launchpad.net/bugs/1709727
+Applied-Upstream: svn://gcc.gnu.org/svn/gcc/trunk@241977
+
+--- a/src/libsanitizer/sanitizer_common/sanitizer_platform.h	2015-11-23 09:07:18.342543000 +0000
++++ b/src/libsanitizer/sanitizer_common/sanitizer_platform.h	2017-08-09 21:13:12.883595484 +0000
+@@ -107,6 +107,8 @@
+ // will still work but will consume more memory for TwoLevelByteMap.
+ #if defined(__mips__)
+ # define SANITIZER_MMAP_RANGE_SIZE FIRST_32_SECOND_64(1ULL << 32, 1ULL << 40)
++#elif defined(__aarch64__)
++# define SANITIZER_MMAP_RANGE_SIZE FIRST_32_SECOND_64(1ULL << 32, 1ULL << 48)
+ #else
+ # define SANITIZER_MMAP_RANGE_SIZE FIRST_32_SECOND_64(1ULL << 32, 1ULL << 47)
+ #endif
--- gcc-6-6.4.0.orig/debian/patches/bind_now_when_pie.diff
+++ gcc-6-6.4.0/debian/patches/bind_now_when_pie.diff
@@ -0,0 +1,20 @@
+Author: Steve Beattie <steve.beattie@canonical.com>
+Description: enable bind now by default when linking with pie by default
+
+---
+ src/gcc/gcc.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -930,7 +930,7 @@ proper position among the other output f
+ #ifndef LINK_PIE_SPEC
+ #ifdef HAVE_LD_PIE
+ #ifndef LD_PIE_SPEC
+-#define LD_PIE_SPEC "-pie"
++#define LD_PIE_SPEC "-pie -z now"
+ #endif
+ #else
+ #define LD_PIE_SPEC ""
--- gcc-6-6.4.0.orig/debian/patches/boehm-gc-getnprocs.diff
+++ gcc-6-6.4.0/debian/patches/boehm-gc-getnprocs.diff
@@ -0,0 +1,20 @@
+# DP: boehm-gc/pthread_support.c (GC_get_nprocs): Use sysconf as fallback.
+
+---
+ boehm-gc/pthread_support.c |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+Index: b/src/boehm-gc/pthread_support.c
+===================================================================
+--- a/src/boehm-gc/pthread_support.c
++++ b/src/boehm-gc/pthread_support.c
+@@ -724,7 +724,8 @@ int GC_get_nprocs()
+     f = open("/proc/stat", O_RDONLY);
+     if (f < 0 || (len = STAT_READ(f, stat_buf, STAT_BUF_SIZE)) < 100) {
+ 	WARN("Couldn't read /proc/stat\n", 0);
+-	return -1;
++	/* Fallback to sysconf after the warning */
++	return sysconf(_SC_NPROCESSORS_ONLN);
+     }
+     for (i = 0; i < len - 100; ++i) {
+         if (stat_buf[i] == '\n' && stat_buf[i+1] == 'c'
--- gcc-6-6.4.0.orig/debian/patches/boehm-gc-nocheck.diff
+++ gcc-6-6.4.0/debian/patches/boehm-gc-nocheck.diff
@@ -0,0 +1,18 @@
+# DP: Disable running the boehm-gc testsuite. Hangs the buildd at least on hppa.
+
+---
+ boehm-gc/Makefile.in |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+--- a/src/boehm-gc/Makefile.in
++++ b/src/boehm-gc/Makefile.in
+@@ -684,7 +684,8 @@ check-TESTS: $(TESTS)
+ 	  test "$$failed" -eq 0; \
+ 	else :; fi
+ check-am: $(check_PROGRAMS)
+-	$(MAKE) $(AM_MAKEFLAGS) check-TESTS
++	: # $(MAKE) $(AM_MAKEFLAGS) check-TESTS
++	@echo target $@ disabled for Debian build.
+ check: check-recursive
+ all-am: Makefile $(LTLIBRARIES) all-multi
+ installdirs: installdirs-recursive
--- gcc-6-6.4.0.orig/debian/patches/bootstrap-no-unneeded-libs.diff
+++ gcc-6-6.4.0/debian/patches/bootstrap-no-unneeded-libs.diff
@@ -0,0 +1,1422 @@
+# DP: For bootstrap builds, don't build unneeded libstdc++ things
+# DP: (debug library, PCH headers).
+
+Index: b/src/Makefile.tpl
+===================================================================
+--- a/src/Makefile.tpl
++++ b/src/Makefile.tpl
+@@ -1060,7 +1060,9 @@
+ 	  --target=[+target_alias+] $${srcdiroption} [+ IF prev +]\
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) [+ ENDIF prev +]\
+ 	  $(STAGE[+id+]_CONFIGURE_FLAGS)[+ IF extra_configure_flags +] \
+-	  [+extra_configure_flags+][+ ENDIF extra_configure_flags +]
++	  [+extra_configure_flags+][+ ENDIF extra_configure_flags +] \
++	  [+ IF bootstrap_configure_flags +][+bootstrap_configure_flags+] \
++	  [+ ENDIF bootstrap_configure_flags +]
+ @endif [+prefix+][+module+]-bootstrap
+ [+ ENDFOR bootstrap_stage +]
+ [+ ENDIF bootstrap +]
+Index: b/src/Makefile.def
+===================================================================
+--- a/src/Makefile.def
++++ b/src/Makefile.def
+@@ -117,7 +117,8 @@
+ target_modules = { module= libstdc++-v3;
+ 		   bootstrap=true;
+ 		   lib_path=src/.libs;
+-		   raw_cxx=true; };
++		   raw_cxx=true;
++		   bootstrap_configure_flags='--disable-libstdcxx-debug --disable-libstdcxx-pch'; };
+ target_modules = { module= libmudflap; lib_path=.libs; };
+ target_modules = { module= libsanitizer; lib_path=.libs; };
+ target_modules = { module= libssp; lib_path=.libs; };
+Index: b/src/Makefile.in
+===================================================================
+--- a/src/Makefile.in
++++ b/src/Makefile.in
+@@ -3007,7 +3007,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif bfd-bootstrap
+ 
+ .PHONY: configure-stage2-bfd maybe-configure-stage2-bfd
+@@ -3040,7 +3041,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif bfd-bootstrap
+ 
+ .PHONY: configure-stage3-bfd maybe-configure-stage3-bfd
+@@ -3073,7 +3075,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif bfd-bootstrap
+ 
+ .PHONY: configure-stage4-bfd maybe-configure-stage4-bfd
+@@ -3106,7 +3109,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif bfd-bootstrap
+ 
+ .PHONY: configure-stageprofile-bfd maybe-configure-stageprofile-bfd
+@@ -3139,7 +3143,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif bfd-bootstrap
+ 
+ .PHONY: configure-stagefeedback-bfd maybe-configure-stagefeedback-bfd
+@@ -3172,7 +3177,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif bfd-bootstrap
+ 
+ 
+@@ -3879,7 +3885,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif opcodes-bootstrap
+ 
+ .PHONY: configure-stage2-opcodes maybe-configure-stage2-opcodes
+@@ -3912,7 +3919,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif opcodes-bootstrap
+ 
+ .PHONY: configure-stage3-opcodes maybe-configure-stage3-opcodes
+@@ -3945,7 +3953,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif opcodes-bootstrap
+ 
+ .PHONY: configure-stage4-opcodes maybe-configure-stage4-opcodes
+@@ -3978,7 +3987,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif opcodes-bootstrap
+ 
+ .PHONY: configure-stageprofile-opcodes maybe-configure-stageprofile-opcodes
+@@ -4011,7 +4021,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif opcodes-bootstrap
+ 
+ .PHONY: configure-stagefeedback-opcodes maybe-configure-stagefeedback-opcodes
+@@ -4044,7 +4055,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif opcodes-bootstrap
+ 
+ 
+@@ -4751,7 +4763,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif binutils-bootstrap
+ 
+ .PHONY: configure-stage2-binutils maybe-configure-stage2-binutils
+@@ -4784,7 +4797,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif binutils-bootstrap
+ 
+ .PHONY: configure-stage3-binutils maybe-configure-stage3-binutils
+@@ -4817,7 +4831,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif binutils-bootstrap
+ 
+ .PHONY: configure-stage4-binutils maybe-configure-stage4-binutils
+@@ -4850,7 +4865,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif binutils-bootstrap
+ 
+ .PHONY: configure-stageprofile-binutils maybe-configure-stageprofile-binutils
+@@ -4883,7 +4899,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif binutils-bootstrap
+ 
+ .PHONY: configure-stagefeedback-binutils maybe-configure-stagefeedback-binutils
+@@ -4916,7 +4933,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif binutils-bootstrap
+ 
+ 
+@@ -8696,7 +8714,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif gas-bootstrap
+ 
+ .PHONY: configure-stage2-gas maybe-configure-stage2-gas
+@@ -8729,7 +8748,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif gas-bootstrap
+ 
+ .PHONY: configure-stage3-gas maybe-configure-stage3-gas
+@@ -8762,7 +8782,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif gas-bootstrap
+ 
+ .PHONY: configure-stage4-gas maybe-configure-stage4-gas
+@@ -8795,7 +8816,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif gas-bootstrap
+ 
+ .PHONY: configure-stageprofile-gas maybe-configure-stageprofile-gas
+@@ -8828,7 +8850,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif gas-bootstrap
+ 
+ .PHONY: configure-stagefeedback-gas maybe-configure-stagefeedback-gas
+@@ -8861,7 +8884,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif gas-bootstrap
+ 
+ 
+@@ -9568,7 +9592,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif gcc-bootstrap
+ 
+ .PHONY: configure-stage2-gcc maybe-configure-stage2-gcc
+@@ -9601,7 +9626,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif gcc-bootstrap
+ 
+ .PHONY: configure-stage3-gcc maybe-configure-stage3-gcc
+@@ -9634,7 +9660,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif gcc-bootstrap
+ 
+ .PHONY: configure-stage4-gcc maybe-configure-stage4-gcc
+@@ -9667,7 +9694,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif gcc-bootstrap
+ 
+ .PHONY: configure-stageprofile-gcc maybe-configure-stageprofile-gcc
+@@ -9700,7 +9728,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif gcc-bootstrap
+ 
+ .PHONY: configure-stagefeedback-gcc maybe-configure-stagefeedback-gcc
+@@ -9733,7 +9762,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif gcc-bootstrap
+ 
+ 
+@@ -10441,7 +10471,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=none-${host_vendor}-${host_os} \
+ 	  --target=none-${host_vendor}-${host_os} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif gmp-bootstrap
+ 
+ .PHONY: configure-stage2-gmp maybe-configure-stage2-gmp
+@@ -10475,7 +10506,8 @@
+ 	  --target=none-${host_vendor}-${host_os} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif gmp-bootstrap
+ 
+ .PHONY: configure-stage3-gmp maybe-configure-stage3-gmp
+@@ -10509,7 +10541,8 @@
+ 	  --target=none-${host_vendor}-${host_os} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif gmp-bootstrap
+ 
+ .PHONY: configure-stage4-gmp maybe-configure-stage4-gmp
+@@ -10543,7 +10576,8 @@
+ 	  --target=none-${host_vendor}-${host_os} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif gmp-bootstrap
+ 
+ .PHONY: configure-stageprofile-gmp maybe-configure-stageprofile-gmp
+@@ -10577,7 +10611,8 @@
+ 	  --target=none-${host_vendor}-${host_os} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif gmp-bootstrap
+ 
+ .PHONY: configure-stagefeedback-gmp maybe-configure-stagefeedback-gmp
+@@ -10611,7 +10646,8 @@
+ 	  --target=none-${host_vendor}-${host_os} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif gmp-bootstrap
+ 
+ 
+@@ -11307,7 +11343,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpfr_configure_flags@
++	  --disable-shared @extra_mpfr_configure_flags@ \
++	  
+ @endif mpfr-bootstrap
+ 
+ .PHONY: configure-stage2-mpfr maybe-configure-stage2-mpfr
+@@ -11341,7 +11378,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpfr_configure_flags@
++	  --disable-shared @extra_mpfr_configure_flags@ \
++	  
+ @endif mpfr-bootstrap
+ 
+ .PHONY: configure-stage3-mpfr maybe-configure-stage3-mpfr
+@@ -11375,7 +11413,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpfr_configure_flags@
++	  --disable-shared @extra_mpfr_configure_flags@ \
++	  
+ @endif mpfr-bootstrap
+ 
+ .PHONY: configure-stage4-mpfr maybe-configure-stage4-mpfr
+@@ -11409,7 +11448,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpfr_configure_flags@
++	  --disable-shared @extra_mpfr_configure_flags@ \
++	  
+ @endif mpfr-bootstrap
+ 
+ .PHONY: configure-stageprofile-mpfr maybe-configure-stageprofile-mpfr
+@@ -11443,7 +11483,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpfr_configure_flags@
++	  --disable-shared @extra_mpfr_configure_flags@ \
++	  
+ @endif mpfr-bootstrap
+ 
+ .PHONY: configure-stagefeedback-mpfr maybe-configure-stagefeedback-mpfr
+@@ -11477,7 +11518,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpfr_configure_flags@
++	  --disable-shared @extra_mpfr_configure_flags@ \
++	  
+ @endif mpfr-bootstrap
+ 
+ 
+@@ -12173,7 +12215,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@
++	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@ \
++	  
+ @endif mpc-bootstrap
+ 
+ .PHONY: configure-stage2-mpc maybe-configure-stage2-mpc
+@@ -12207,7 +12250,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@
++	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@ \
++	  
+ @endif mpc-bootstrap
+ 
+ .PHONY: configure-stage3-mpc maybe-configure-stage3-mpc
+@@ -12241,7 +12285,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@
++	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@ \
++	  
+ @endif mpc-bootstrap
+ 
+ .PHONY: configure-stage4-mpc maybe-configure-stage4-mpc
+@@ -12275,7 +12320,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@
++	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@ \
++	  
+ @endif mpc-bootstrap
+ 
+ .PHONY: configure-stageprofile-mpc maybe-configure-stageprofile-mpc
+@@ -12309,7 +12355,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@
++	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@ \
++	  
+ @endif mpc-bootstrap
+ 
+ .PHONY: configure-stagefeedback-mpc maybe-configure-stagefeedback-mpc
+@@ -12343,7 +12390,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@
++	  --disable-shared @extra_mpc_gmp_configure_flags@ @extra_mpc_mpfr_configure_flags@ \
++	  
+ @endif mpc-bootstrap
+ 
+ 
+@@ -13039,7 +13087,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_isl_gmp_configure_flags@
++	  --disable-shared @extra_isl_gmp_configure_flags@ \
++	  
+ @endif isl-bootstrap
+ 
+ .PHONY: configure-stage2-isl maybe-configure-stage2-isl
+@@ -13073,7 +13122,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_isl_gmp_configure_flags@
++	  --disable-shared @extra_isl_gmp_configure_flags@ \
++	  
+ @endif isl-bootstrap
+ 
+ .PHONY: configure-stage3-isl maybe-configure-stage3-isl
+@@ -13107,7 +13157,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_isl_gmp_configure_flags@
++	  --disable-shared @extra_isl_gmp_configure_flags@ \
++	  
+ @endif isl-bootstrap
+ 
+ .PHONY: configure-stage4-isl maybe-configure-stage4-isl
+@@ -13141,7 +13192,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_isl_gmp_configure_flags@
++	  --disable-shared @extra_isl_gmp_configure_flags@ \
++	  
+ @endif isl-bootstrap
+ 
+ .PHONY: configure-stageprofile-isl maybe-configure-stageprofile-isl
+@@ -13175,7 +13227,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_isl_gmp_configure_flags@
++	  --disable-shared @extra_isl_gmp_configure_flags@ \
++	  
+ @endif isl-bootstrap
+ 
+ .PHONY: configure-stagefeedback-isl maybe-configure-stagefeedback-isl
+@@ -13209,7 +13262,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --disable-shared @extra_isl_gmp_configure_flags@
++	  --disable-shared @extra_isl_gmp_configure_flags@ \
++	  
+ @endif isl-bootstrap
+ 
+ 
+@@ -13905,7 +13959,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system
++	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system \
++	  
+ @endif cloog-bootstrap
+ 
+ .PHONY: configure-stage2-cloog maybe-configure-stage2-cloog
+@@ -13939,7 +13994,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system
++	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system \
++	  
+ @endif cloog-bootstrap
+ 
+ .PHONY: configure-stage3-cloog maybe-configure-stage3-cloog
+@@ -13973,7 +14029,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system
++	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system \
++	  
+ @endif cloog-bootstrap
+ 
+ .PHONY: configure-stage4-cloog maybe-configure-stage4-cloog
+@@ -14007,7 +14064,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system
++	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system \
++	  
+ @endif cloog-bootstrap
+ 
+ .PHONY: configure-stageprofile-cloog maybe-configure-stageprofile-cloog
+@@ -14041,7 +14099,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system
++	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system \
++	  
+ @endif cloog-bootstrap
+ 
+ .PHONY: configure-stagefeedback-cloog maybe-configure-stagefeedback-cloog
+@@ -14075,7 +14134,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system
++	  --disable-shared --with-gmp=system --with-bits=gmp --with-isl=system \
++	  
+ @endif cloog-bootstrap
+ 
+ 
+@@ -14771,7 +14831,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif libelf-bootstrap
+ 
+ .PHONY: configure-stage2-libelf maybe-configure-stage2-libelf
+@@ -14805,7 +14866,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif libelf-bootstrap
+ 
+ .PHONY: configure-stage3-libelf maybe-configure-stage3-libelf
+@@ -14839,7 +14901,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif libelf-bootstrap
+ 
+ .PHONY: configure-stage4-libelf maybe-configure-stage4-libelf
+@@ -14873,7 +14936,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif libelf-bootstrap
+ 
+ .PHONY: configure-stageprofile-libelf maybe-configure-stageprofile-libelf
+@@ -14907,7 +14971,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif libelf-bootstrap
+ 
+ .PHONY: configure-stagefeedback-libelf maybe-configure-stagefeedback-libelf
+@@ -14941,7 +15006,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --disable-shared
++	  --disable-shared \
++	  
+ @endif libelf-bootstrap
+ 
+ 
+@@ -15636,7 +15702,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif gold-bootstrap
+ 
+ .PHONY: configure-stage2-gold maybe-configure-stage2-gold
+@@ -15669,7 +15736,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif gold-bootstrap
+ 
+ .PHONY: configure-stage3-gold maybe-configure-stage3-gold
+@@ -15702,7 +15770,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif gold-bootstrap
+ 
+ .PHONY: configure-stage4-gold maybe-configure-stage4-gold
+@@ -15735,7 +15804,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif gold-bootstrap
+ 
+ .PHONY: configure-stageprofile-gold maybe-configure-stageprofile-gold
+@@ -15768,7 +15838,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif gold-bootstrap
+ 
+ .PHONY: configure-stagefeedback-gold maybe-configure-stagefeedback-gold
+@@ -15801,7 +15872,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif gold-bootstrap
+ 
+ 
+@@ -16948,7 +17020,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif intl-bootstrap
+ 
+ .PHONY: configure-stage2-intl maybe-configure-stage2-intl
+@@ -16981,7 +17054,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif intl-bootstrap
+ 
+ .PHONY: configure-stage3-intl maybe-configure-stage3-intl
+@@ -17014,7 +17088,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif intl-bootstrap
+ 
+ .PHONY: configure-stage4-intl maybe-configure-stage4-intl
+@@ -17047,7 +17122,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif intl-bootstrap
+ 
+ .PHONY: configure-stageprofile-intl maybe-configure-stageprofile-intl
+@@ -17080,7 +17156,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif intl-bootstrap
+ 
+ .PHONY: configure-stagefeedback-intl maybe-configure-stagefeedback-intl
+@@ -17113,7 +17190,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif intl-bootstrap
+ 
+ 
+@@ -18685,7 +18763,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif ld-bootstrap
+ 
+ .PHONY: configure-stage2-ld maybe-configure-stage2-ld
+@@ -18718,7 +18797,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif ld-bootstrap
+ 
+ .PHONY: configure-stage3-ld maybe-configure-stage3-ld
+@@ -18751,7 +18831,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif ld-bootstrap
+ 
+ .PHONY: configure-stage4-ld maybe-configure-stage4-ld
+@@ -18784,7 +18865,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif ld-bootstrap
+ 
+ .PHONY: configure-stageprofile-ld maybe-configure-stageprofile-ld
+@@ -18817,7 +18899,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif ld-bootstrap
+ 
+ .PHONY: configure-stagefeedback-ld maybe-configure-stagefeedback-ld
+@@ -18850,7 +18933,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif ld-bootstrap
+ 
+ 
+@@ -19557,7 +19641,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif libbacktrace-bootstrap
+ 
+ .PHONY: configure-stage2-libbacktrace maybe-configure-stage2-libbacktrace
+@@ -19590,7 +19675,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif libbacktrace-bootstrap
+ 
+ .PHONY: configure-stage3-libbacktrace maybe-configure-stage3-libbacktrace
+@@ -19623,7 +19709,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif libbacktrace-bootstrap
+ 
+ .PHONY: configure-stage4-libbacktrace maybe-configure-stage4-libbacktrace
+@@ -19656,7 +19743,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif libbacktrace-bootstrap
+ 
+ .PHONY: configure-stageprofile-libbacktrace maybe-configure-stageprofile-libbacktrace
+@@ -19689,7 +19777,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif libbacktrace-bootstrap
+ 
+ .PHONY: configure-stagefeedback-libbacktrace maybe-configure-stagefeedback-libbacktrace
+@@ -19722,7 +19811,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif libbacktrace-bootstrap
+ 
+ 
+@@ -20429,7 +20519,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif libcpp-bootstrap
+ 
+ .PHONY: configure-stage2-libcpp maybe-configure-stage2-libcpp
+@@ -20462,7 +20553,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif libcpp-bootstrap
+ 
+ .PHONY: configure-stage3-libcpp maybe-configure-stage3-libcpp
+@@ -20495,7 +20587,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif libcpp-bootstrap
+ 
+ .PHONY: configure-stage4-libcpp maybe-configure-stage4-libcpp
+@@ -20528,7 +20621,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif libcpp-bootstrap
+ 
+ .PHONY: configure-stageprofile-libcpp maybe-configure-stageprofile-libcpp
+@@ -20561,7 +20655,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif libcpp-bootstrap
+ 
+ .PHONY: configure-stagefeedback-libcpp maybe-configure-stagefeedback-libcpp
+@@ -20594,7 +20689,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif libcpp-bootstrap
+ 
+ 
+@@ -21301,7 +21397,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif libdecnumber-bootstrap
+ 
+ .PHONY: configure-stage2-libdecnumber maybe-configure-stage2-libdecnumber
+@@ -21334,7 +21431,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif libdecnumber-bootstrap
+ 
+ .PHONY: configure-stage3-libdecnumber maybe-configure-stage3-libdecnumber
+@@ -21367,7 +21465,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif libdecnumber-bootstrap
+ 
+ .PHONY: configure-stage4-libdecnumber maybe-configure-stage4-libdecnumber
+@@ -21400,7 +21499,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif libdecnumber-bootstrap
+ 
+ .PHONY: configure-stageprofile-libdecnumber maybe-configure-stageprofile-libdecnumber
+@@ -21433,7 +21533,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif libdecnumber-bootstrap
+ 
+ .PHONY: configure-stagefeedback-libdecnumber maybe-configure-stagefeedback-libdecnumber
+@@ -21466,7 +21567,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif libdecnumber-bootstrap
+ 
+ 
+@@ -22614,7 +22716,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  @extra_host_libiberty_configure_flags@
++	  @extra_host_libiberty_configure_flags@ \
++	  
+ @endif libiberty-bootstrap
+ 
+ .PHONY: configure-stage2-libiberty maybe-configure-stage2-libiberty
+@@ -22648,7 +22751,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  @extra_host_libiberty_configure_flags@
++	  @extra_host_libiberty_configure_flags@ \
++	  
+ @endif libiberty-bootstrap
+ 
+ .PHONY: configure-stage3-libiberty maybe-configure-stage3-libiberty
+@@ -22682,7 +22786,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  @extra_host_libiberty_configure_flags@
++	  @extra_host_libiberty_configure_flags@ \
++	  
+ @endif libiberty-bootstrap
+ 
+ .PHONY: configure-stage4-libiberty maybe-configure-stage4-libiberty
+@@ -22716,7 +22821,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  @extra_host_libiberty_configure_flags@
++	  @extra_host_libiberty_configure_flags@ \
++	  
+ @endif libiberty-bootstrap
+ 
+ .PHONY: configure-stageprofile-libiberty maybe-configure-stageprofile-libiberty
+@@ -22750,7 +22856,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  @extra_host_libiberty_configure_flags@
++	  @extra_host_libiberty_configure_flags@ \
++	  
+ @endif libiberty-bootstrap
+ 
+ .PHONY: configure-stagefeedback-libiberty maybe-configure-stagefeedback-libiberty
+@@ -22784,7 +22891,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  @extra_host_libiberty_configure_flags@
++	  @extra_host_libiberty_configure_flags@ \
++	  
+ @endif libiberty-bootstrap
+ 
+ 
+@@ -26056,7 +26164,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif zlib-bootstrap
+ 
+ .PHONY: configure-stage2-zlib maybe-configure-stage2-zlib
+@@ -26089,7 +26198,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif zlib-bootstrap
+ 
+ .PHONY: configure-stage3-zlib maybe-configure-stage3-zlib
+@@ -26122,7 +26232,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif zlib-bootstrap
+ 
+ .PHONY: configure-stage4-zlib maybe-configure-stage4-zlib
+@@ -26155,7 +26266,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif zlib-bootstrap
+ 
+ .PHONY: configure-stageprofile-zlib maybe-configure-stageprofile-zlib
+@@ -26188,7 +26300,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif zlib-bootstrap
+ 
+ .PHONY: configure-stagefeedback-zlib maybe-configure-stagefeedback-zlib
+@@ -26221,7 +26334,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif zlib-bootstrap
+ 
+ 
+@@ -29919,7 +30033,8 @@
+ 	  $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  $(STAGE1_CONFIGURE_FLAGS) \
+-	  --enable-shared
++	  --enable-shared \
++	  
+ @endif lto-plugin-bootstrap
+ 
+ .PHONY: configure-stage2-lto-plugin maybe-configure-stage2-lto-plugin
+@@ -29953,7 +30068,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE2_CONFIGURE_FLAGS) \
+-	  --enable-shared
++	  --enable-shared \
++	  
+ @endif lto-plugin-bootstrap
+ 
+ .PHONY: configure-stage3-lto-plugin maybe-configure-stage3-lto-plugin
+@@ -29987,7 +30103,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE3_CONFIGURE_FLAGS) \
+-	  --enable-shared
++	  --enable-shared \
++	  
+ @endif lto-plugin-bootstrap
+ 
+ .PHONY: configure-stage4-lto-plugin maybe-configure-stage4-lto-plugin
+@@ -30021,7 +30138,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGE4_CONFIGURE_FLAGS) \
+-	  --enable-shared
++	  --enable-shared \
++	  
+ @endif lto-plugin-bootstrap
+ 
+ .PHONY: configure-stageprofile-lto-plugin maybe-configure-stageprofile-lto-plugin
+@@ -30055,7 +30173,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEprofile_CONFIGURE_FLAGS) \
+-	  --enable-shared
++	  --enable-shared \
++	  
+ @endif lto-plugin-bootstrap
+ 
+ .PHONY: configure-stagefeedback-lto-plugin maybe-configure-stagefeedback-lto-plugin
+@@ -30089,7 +30208,8 @@
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+ 	  $(STAGEfeedback_CONFIGURE_FLAGS) \
+-	  --enable-shared
++	  --enable-shared \
++	  
+ @endif lto-plugin-bootstrap
+ 
+ 
+@@ -30829,7 +30949,9 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  --disable-libstdcxx-debug --disable-libstdcxx-pch \
++	  
+ @endif target-libstdc++-v3-bootstrap
+ 
+ .PHONY: configure-stage2-target-libstdc++-v3 maybe-configure-stage2-target-libstdc++-v3
+@@ -30874,7 +30996,9 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  --disable-libstdcxx-debug --disable-libstdcxx-pch \
++	  
+ @endif target-libstdc++-v3-bootstrap
+ 
+ .PHONY: configure-stage3-target-libstdc++-v3 maybe-configure-stage3-target-libstdc++-v3
+@@ -30919,7 +31043,9 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  --disable-libstdcxx-debug --disable-libstdcxx-pch \
++	  
+ @endif target-libstdc++-v3-bootstrap
+ 
+ .PHONY: configure-stage4-target-libstdc++-v3 maybe-configure-stage4-target-libstdc++-v3
+@@ -30964,7 +31090,9 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  --disable-libstdcxx-debug --disable-libstdcxx-pch \
++	  
+ @endif target-libstdc++-v3-bootstrap
+ 
+ .PHONY: configure-stageprofile-target-libstdc++-v3 maybe-configure-stageprofile-target-libstdc++-v3
+@@ -31009,7 +31137,9 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  --disable-libstdcxx-debug --disable-libstdcxx-pch \
++	  
+ @endif target-libstdc++-v3-bootstrap
+ 
+ .PHONY: configure-stagefeedback-target-libstdc++-v3 maybe-configure-stagefeedback-target-libstdc++-v3
+@@ -31054,7 +31184,9 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  --disable-libstdcxx-debug --disable-libstdcxx-pch \
++	  
+ @endif target-libstdc++-v3-bootstrap
+ 
+ 
+@@ -33631,7 +33763,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgcc-bootstrap
+ 
+ .PHONY: configure-stage2-target-libgcc maybe-configure-stage2-target-libgcc
+@@ -33676,7 +33809,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgcc-bootstrap
+ 
+ .PHONY: configure-stage3-target-libgcc maybe-configure-stage3-target-libgcc
+@@ -33721,7 +33855,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgcc-bootstrap
+ 
+ .PHONY: configure-stage4-target-libgcc maybe-configure-stage4-target-libgcc
+@@ -33766,7 +33901,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgcc-bootstrap
+ 
+ .PHONY: configure-stageprofile-target-libgcc maybe-configure-stageprofile-target-libgcc
+@@ -33811,7 +33947,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgcc-bootstrap
+ 
+ .PHONY: configure-stagefeedback-target-libgcc maybe-configure-stagefeedback-target-libgcc
+@@ -33856,7 +33993,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgcc-bootstrap
+ 
+ 
+@@ -40928,7 +41066,8 @@
+ 	$(SHELL) $${libsrcdir}/configure \
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+-	  $(STAGE1_CONFIGURE_FLAGS)
++	  $(STAGE1_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgomp-bootstrap
+ 
+ .PHONY: configure-stage2-target-libgomp maybe-configure-stage2-target-libgomp
+@@ -40973,7 +41112,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE2_CONFIGURE_FLAGS)
++	  $(STAGE2_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgomp-bootstrap
+ 
+ .PHONY: configure-stage3-target-libgomp maybe-configure-stage3-target-libgomp
+@@ -41018,7 +41158,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE3_CONFIGURE_FLAGS)
++	  $(STAGE3_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgomp-bootstrap
+ 
+ .PHONY: configure-stage4-target-libgomp maybe-configure-stage4-target-libgomp
+@@ -41063,7 +41204,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGE4_CONFIGURE_FLAGS)
++	  $(STAGE4_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgomp-bootstrap
+ 
+ .PHONY: configure-stageprofile-target-libgomp maybe-configure-stageprofile-target-libgomp
+@@ -41108,7 +41250,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEprofile_CONFIGURE_FLAGS)
++	  $(STAGEprofile_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgomp-bootstrap
+ 
+ .PHONY: configure-stagefeedback-target-libgomp maybe-configure-stagefeedback-target-libgomp
+@@ -41153,7 +41296,8 @@
+ 	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
+ 	  --target=${target_alias} $${srcdiroption} \
+ 	  --with-build-libsubdir=$(HOST_SUBDIR) \
+-	  $(STAGEfeedback_CONFIGURE_FLAGS)
++	  $(STAGEfeedback_CONFIGURE_FLAGS) \
++	  
+ @endif target-libgomp-bootstrap
+ 
+ 
--- gcc-6-6.4.0.orig/debian/patches/canonical-cpppath.diff
+++ gcc-6-6.4.0/debian/patches/canonical-cpppath.diff
@@ -0,0 +1,36 @@
+# DP: Don't use any relative path names for the standard include paths.
+
+Index: b/src/gcc/incpath.c
+===================================================================
+--- a/src/gcc/incpath.c
++++ b/src/gcc/incpath.c
+@@ -171,6 +171,14 @@ add_standard_paths (const char *sysroot,
+ 			str = reconcat (str, str, dir_separator_str,
+ 					imultiarch, NULL);
+ 		    }
++		  {
++		    char *rp = lrealpath (str);
++		    if (rp)
++		      {
++			free (str);
++			str = rp;
++		      }
++		  }
+ 		  add_path (str, SYSTEM, p->cxx_aware, false);
+ 		}
+ 	    }
+@@ -245,6 +253,14 @@ add_standard_paths (const char *sysroot,
+ 	      else
+ 		str = reconcat (str, str, dir_separator_str, imultiarch, NULL);
+ 	    }
++	  {
++	    char *rp = lrealpath (str);
++	    if (rp)
++	      {
++		free (str);
++		str = rp;
++	      }
++	  }
+ 
+ 	  add_path (str, SYSTEM, p->cxx_aware, false);
+ 	}
--- gcc-6-6.4.0.orig/debian/patches/cmd-go-combine-gccgo-s-ld-and-ldShared-methods.diff
+++ gcc-6-6.4.0/debian/patches/cmd-go-combine-gccgo-s-ld-and-ldShared-methods.diff
@@ -0,0 +1,148 @@
+# DP: cmd/go: combine gccgo's ld() and ldShared() methods
+
+From 7fc382a2a201960826ed72413983685ac942c64c Mon Sep 17 00:00:00 2001
+From: Michael Hudson-Doyle <michael.hudson@canonical.com>
+Date: Tue, 31 May 2016 20:48:42 +1200
+Subject: [PATCH] cmd/go: combine gccgo's ld() and ldShared() methods
+
+This fixes handling of cgo flags and makes sure packages that are only
+implicitly included in the shared library are passed to the link.
+
+Fixes #15885
+
+Change-Id: I1e8a72b5314261973ca903c78834700fb113dde9
+---
+ src/cmd/go/build.go | 63 ++++++++++++++++++++++++-----------------------------
+ 1 file changed, 29 insertions(+), 34 deletions(-)
+
+Index: b/src/libgo/go/cmd/go/build.go
+===================================================================
+--- a/src/libgo/go/cmd/go/build.go
++++ b/src/libgo/go/cmd/go/build.go
+@@ -2629,7 +2629,7 @@ func (gccgoToolchain) pack(b *builder, p
+ 	return b.run(p.Dir, p.ImportPath, nil, "ar", "rc", mkAbs(objDir, afile), absOfiles)
+ }
+ 
+-func (tools gccgoToolchain) ld(b *builder, root *action, out string, allactions []*action, mainpkg string, ofiles []string) error {
++func (tools gccgoToolchain) link(b *builder, root *action, out string, allactions []*action, mainpkg string, ofiles []string, buildmode, desc string) error {
+ 	// gccgo needs explicit linking with all package dependencies,
+ 	// and all LDFLAGS from cgo dependencies.
+ 	apackagePathsSeen := make(map[string]bool)
+@@ -2638,8 +2638,12 @@ func (tools gccgoToolchain) ld(b *builde
+ 	ldflags := b.gccArchArgs()
+ 	cgoldflags := []string{}
+ 	usesCgo := false
+-	cxx := len(root.p.CXXFiles) > 0 || len(root.p.SwigCXXFiles) > 0
+-	objc := len(root.p.MFiles) > 0
++	cxx := false
++	objc := false
++	if root.p != nil {
++		cxx = len(root.p.CXXFiles) > 0 || len(root.p.SwigCXXFiles) > 0
++		objc = len(root.p.MFiles) > 0
++	}
+ 
+ 	readCgoFlags := func(flagsFile string) error {
+ 		flags, err := ioutil.ReadFile(flagsFile)
+@@ -2686,11 +2690,11 @@ func (tools gccgoToolchain) ld(b *builde
+ 		}
+ 
+ 		newarchive := newa.Name()
+-		err = b.run(b.work, root.p.ImportPath, nil, "ar", "x", newarchive, "_cgo_flags")
++		err = b.run(b.work, desc, nil, "ar", "x", newarchive, "_cgo_flags")
+ 		if err != nil {
+ 			return "", err
+ 		}
+-		err = b.run(".", root.p.ImportPath, nil, "ar", "d", newarchive, "_cgo_flags")
++		err = b.run(".", desc, nil, "ar", "d", newarchive, "_cgo_flags")
+ 		if err != nil {
+ 			return "", err
+ 		}
+@@ -2793,7 +2797,9 @@ func (tools gccgoToolchain) ld(b *builde
+ 
+ 	ldflags = append(ldflags, cgoldflags...)
+ 	ldflags = append(ldflags, envList("CGO_LDFLAGS", "")...)
+-	ldflags = append(ldflags, root.p.CgoLDFLAGS...)
++	if root.p != nil {
++		ldflags = append(ldflags, root.p.CgoLDFLAGS...)
++	}
+ 
+ 	ldflags = stringList("-Wl,-(", ldflags, "-Wl,-)")
+ 
+@@ -2808,7 +2814,7 @@ func (tools gccgoToolchain) ld(b *builde
+ 	}
+ 
+ 	var realOut string
+-	switch ldBuildmode {
++	switch buildmode {
+ 	case "exe":
+ 		if usesCgo && goos == "linux" {
+ 			ldflags = append(ldflags, "-Wl,-E")
+@@ -2843,12 +2849,14 @@ func (tools gccgoToolchain) ld(b *builde
+ 
+ 	case "c-shared":
+ 		ldflags = append(ldflags, "-shared", "-nostdlib", "-Wl,--whole-archive", "-lgolibbegin", "-Wl,--no-whole-archive", "-lgo", "-lgcc_s", "-lgcc", "-lc", "-lgcc")
++	case "shared":
++		ldflags = append(ldflags, "-zdefs", "-shared", "-nostdlib", "-lgo", "-lgcc_s", "-lgcc", "-lc")
+ 
+ 	default:
+-		fatalf("-buildmode=%s not supported for gccgo", ldBuildmode)
++		fatalf("-buildmode=%s not supported for gccgo", buildmode)
+ 	}
+ 
+-	switch ldBuildmode {
++	switch buildmode {
+ 	case "exe", "c-shared":
+ 		if cxx {
+ 			ldflags = append(ldflags, "-lstdc++")
+@@ -2858,41 +2866,27 @@ func (tools gccgoToolchain) ld(b *builde
+ 		}
+ 	}
+ 
+-	if err := b.run(".", root.p.ImportPath, nil, tools.linker(), "-o", out, ofiles, ldflags, buildGccgoflags); err != nil {
++	if err := b.run(".", desc, nil, tools.linker(), "-o", out, ofiles, ldflags, buildGccgoflags); err != nil {
+ 		return err
+ 	}
+ 
+-	switch ldBuildmode {
++	switch buildmode {
+ 	case "c-archive":
+-		if err := b.run(".", root.p.ImportPath, nil, "ar", "rc", realOut, out); err != nil {
++		if err := b.run(".", desc, nil, "ar", "rc", realOut, out); err != nil {
+ 			return err
+ 		}
+ 	}
+ 	return nil
+ }
+ 
++func (tools gccgoToolchain) ld(b *builder, root *action, out string, allactions []*action, mainpkg string, ofiles []string) error {
++	return tools.link(b, root, out, allactions, mainpkg, ofiles, ldBuildmode, root.p.ImportPath)
++}
++
+ func (tools gccgoToolchain) ldShared(b *builder, toplevelactions []*action, out string, allactions []*action) error {
+-	args := []string{"-o", out, "-shared", "-nostdlib", "-zdefs", "-Wl,--whole-archive"}
+-	for _, a := range toplevelactions {
+-		args = append(args, a.target)
+-	}
+-	args = append(args, "-Wl,--no-whole-archive", "-shared", "-nostdlib", "-lgo", "-lgcc_s", "-lgcc", "-lc")
+-	shlibs := []string{}
+-	for _, a := range allactions {
+-		if strings.HasSuffix(a.target, ".so") {
+-			shlibs = append(shlibs, a.target)
+-		}
+-	}
+-	for _, shlib := range shlibs {
+-		args = append(
+-			args,
+-			"-L"+filepath.Dir(shlib),
+-			"-Wl,-rpath="+filepath.Dir(shlib),
+-			"-l"+strings.TrimSuffix(
+-				strings.TrimPrefix(filepath.Base(shlib), "lib"),
+-				".so"))
+-	}
+-	return b.run(".", out, nil, tools.linker(), args, buildGccgoflags)
++	fakeRoot := &action{}
++	fakeRoot.deps = toplevelactions
++	return tools.link(b, fakeRoot, out, allactions, "", []string{}, "shared", out)
+ }
+ 
+ func (tools gccgoToolchain) cc(b *builder, p *Package, objdir, ofile, cfile string) error {
--- gcc-6-6.4.0.orig/debian/patches/compress-debug-check.diff
+++ gcc-6-6.4.0/debian/patches/compress-debug-check.diff
@@ -0,0 +1,88 @@
+gcc/
+
+2016-06-22  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	* configure.ac (gcc_cv_as_compress_debug): Remove
+	--compress-debug-sections as extra as switch.
+	Handle gas --compress-debug-sections=type.
+	(gcc_cv_ld_compess_debug): Remove bogus ld_date check.
+	Handle gld --compress-debug-sections=type.
+	* configure: Regenerate.
+
+ 
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -4729,12 +4729,21 @@
+ fi
+ 
+ gcc_GAS_CHECK_FEATURE([compressed debug sections],
+-  gcc_cv_as_compress_debug,,[--compress-debug-sections],,
++  gcc_cv_as_compress_debug,,,,
+   [# gas compiled without zlib cannot compress debug sections and warns
+    # about it, but still exits successfully.  So check for this, too.
+    if $gcc_cv_as --compress-debug-sections -o conftest.o conftest.s 2>&1 | grep -i warning > /dev/null
+    then
+      gcc_cv_as_compress_debug=0
++   # Since binutils 2.26, gas supports --compress-debug-sections=type,
++   # defaulting to the ELF gABI format.
++   elif $gcc_cv_as --compress-debug-sections=zlib-gnu -o conftest.o conftest.s > /dev/null 2>&1
++   then
++     gcc_cv_as_compress_debug=2
++     gcc_cv_as_compress_debug_option="--compress-debug-sections"
++     gcc_cv_as_no_compress_debug_option="--nocompress-debug-sections"
++   # Before binutils 2.26, gas only supported --compress-debug-options and
++   # emitted the traditional GNU format.
+    elif $gcc_cv_as --compress-debug-sections -o conftest.o conftest.s > /dev/null 2>&1
+    then
+      gcc_cv_as_compress_debug=1
+@@ -4742,8 +4751,6 @@
+      gcc_cv_as_no_compress_debug_option="--nocompress-debug-sections"
+    else
+      gcc_cv_as_compress_debug=0
+-   # FIXME: Future gas versions will support ELF gABI style via
+-   # --compress-debug-sections[=type].
+    fi])
+ AC_DEFINE_UNQUOTED(HAVE_AS_COMPRESS_DEBUG, $gcc_cv_as_compress_debug,
+ [Define to the level of your assembler's compressed debug section support.])
+@@ -5118,6 +5125,7 @@
+ 
+ AC_MSG_CHECKING(linker for compressed debug sections)
+ # gold/gld support compressed debug sections since binutils 2.19/2.21
++# In binutils 2.26, gld gained support for the ELF gABI format.
+ if test $in_tree_ld = yes ; then
+   gcc_cv_ld_compress_debug=0
+   if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 19 -o "$gcc_cv_gld_major_version" -gt 2 \
+@@ -5124,21 +5132,23 @@
+      && test $in_tree_ld_is_elf = yes && test $ld_is_gold = yes; then
+     gcc_cv_ld_compress_debug=2
+     gcc_cv_ld_compress_debug_option="--compress-debug-sections"
++  elif test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 26 -o "$gcc_cv_gld_major_version" -gt 2 \
++     && test $in_tree_ld_is_elf = yes && test $ld_is_gold = no; then
++    gcc_cv_ld_compress_debug=3
++    gcc_cv_ld_compress_debug_option="--compress-debug-sections"
+   elif test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 21 -o "$gcc_cv_gld_major_version" -gt 2 \
+      && test $in_tree_ld_is_elf = yes; then
+     gcc_cv_ld_compress_debug=1
+   fi
+ elif echo "$ld_ver" | grep GNU > /dev/null; then
+-  gcc_cv_ld_compress_debug=1
+-  if test 0"$ld_date" -lt 20050308; then
+-    if test -n "$ld_date"; then
+-      # If there was date string, but was earlier than 2005-03-08, fail
+-      gcc_cv_ld_compress_debug=0
+-    elif test "$ld_vers_major" -lt 2; then
+-      gcc_cv_ld_compress_debug=0
+-    elif test "$ld_vers_major" -eq 2 -a "$ld_vers_minor" -lt 21; then
+-      gcc_cv_ld_compress_debug=0
+-    fi
++  if test "$ld_vers_major" -lt 2 \
++     || test "$ld_vers_major" -eq 2 -a "$ld_vers_minor" -lt 21; then
++    gcc_cv_ld_compress_debug=0
++  elif test "$ld_vers_major" -eq 2 -a "$ld_vers_minor" -lt 26; then
++    gcc_cv_ld_compress_debug=1
++  else
++    gcc_cv_ld_compress_debug=3
++    gcc_cv_ld_compress_debug_option="--compress-debug-sections"
+   fi
+   if test $ld_is_gold = yes; then
+     gcc_cv_ld_compress_debug=2
--- gcc-6-6.4.0.orig/debian/patches/config-ml.diff
+++ gcc-6-6.4.0/debian/patches/config-ml.diff
@@ -0,0 +1,55 @@
+# DP: - Disable some biarch libraries for biarch builds.
+# DP: - Fix multilib builds on kernels which don't support all multilibs.
+
+Index: b/src/config-ml.in
+===================================================================
+--- a/src/config-ml.in
++++ b/src/config-ml.in
+@@ -475,6 +475,25 @@ powerpc*-*-* | rs6000*-*-*)
+ 	;;
+ esac
+ 
++if [ -z "$biarch_multidir_names" ]; then
++  biarch_multidir_names="libiberty libstdc++-v3 libgfortran libmudflap libssp libffi libobjc libgomp"
++  echo "WARNING: biarch_multidir_names is unset. Use default value:"
++  echo "  $biarch_multidir_names"
++fi
++ml_srcbase=`basename $ml_realsrcdir`
++old_multidirs="${multidirs}"
++multidirs=""
++for x in ${old_multidirs}; do
++    case " $x " in
++	" 32 "|" n32 "|" x32 "|" 64 "|" hf "|" sf "|" m4-nofpu ")
++	case "$biarch_multidir_names" in
++	    *"$ml_srcbase"*) multidirs="${multidirs} ${x}" ;;
++	esac
++	;;
++	*) multidirs="${multidirs} ${x}" ;;
++    esac
++done
++
+ # Remove extraneous blanks from multidirs.
+ # Tests like `if [ -n "$multidirs" ]' require it.
+ multidirs=`echo "$multidirs" | sed -e 's/^[ ][ ]*//' -e 's/[ ][ ]*$//' -e 's/[ ][ ]*/ /g'`
+@@ -891,9 +910,20 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	fi
+     fi
+ 
++    ml_configure_args=
++    for arg in ${ac_configure_args}
++    do
++      case $arg in
++      *CC=*)  ml_configure_args=${ml_config_env} ;;
++      *CXX=*) ml_configure_args=${ml_config_env} ;;
++      *GCJ=*) ml_configure_args=${ml_config_env} ;;
++      *) ;;
++      esac
++    done
++
+     if eval ${ml_config_env} ${ml_config_shell} ${ml_recprog} \
+ 	--with-multisubdir=${ml_dir} --with-multisrctop=${multisrctop} \
+-	"${ac_configure_args}" ${ml_config_env} ${ml_srcdiroption} ; then
++	"${ac_configure_args}" ${ml_configure_args} ${ml_config_env} ${ml_srcdiroption} ; then
+       true
+     else
+       exit 1
--- gcc-6-6.4.0.orig/debian/patches/cross-biarch.diff
+++ gcc-6-6.4.0/debian/patches/cross-biarch.diff
@@ -0,0 +1,91 @@
+# DP: Fix the location of target's libs in cross-build for biarch
+
+Index: b/src/config-ml.in
+===================================================================
+--- a/src/config-ml.in
++++ b/src/config-ml.in
+@@ -533,7 +533,13 @@ multi-do:
+ 	    else \
+ 	      if [ -d ../$${dir}/$${lib} ]; then \
+ 		flags=`echo $$i | sed -e 's/^[^;]*;//' -e 's/@/ -/g'`; \
+-		if (cd ../$${dir}/$${lib}; $(MAKE) $(FLAGS_TO_PASS) \
++		libsuffix_="$${dir}"; \
++		if [ "$${dir}" = "n32" ]; then libsuffix_=32; fi; \
++		if [ -n "$$($${compiler} -v 2>&1 |grep '^Target: mips')" ] && [ "$${dir}" = "32" ]; then libsuffix_=o32; fi; \
++		if (cd ../$${dir}/$${lib}; $(MAKE) $(subst \
++				-B$(build_tooldir)/lib/, \
++				-B$(build_tooldir)/lib$${libsuffix_}/, \
++				$(FLAGS_TO_PASS)) \
+ 				CFLAGS="$(CFLAGS) $${flags}" \
+ 				CCASFLAGS="$(CCASFLAGS) $${flags}" \
+ 				FCFLAGS="$(FCFLAGS) $${flags}" \
+@@ -786,6 +792,15 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	GFORTRAN_=$GFORTRAN' '
+ 	GOC_=$GOC' '
+     else
++	if [ "${ml_dir}" = "." ]; then
++		FILTER_="s!X\\(.*\\)!\\1!p"
++	elif [ "${ml_dir}" = "n32" ]; then # mips n32 -> lib32
++		FILTER_="s!X\\(.*\\)/!\\132/!p"
++	elif [ "${ml_dir}" = "32" ] && [ "$(echo ${host} |grep '^mips')" ]; then # mips o32 -> libo32
++		FILTER_="s!X\\(.*\\)/!\\1o32/!p"
++	else
++		FILTER_="s!X\\(.*\\)/!\\1${ml_dir}/!p"
++	fi
+ 	# Create a regular expression that matches any string as long
+ 	# as ML_POPDIR.
+ 	popdir_rx=`echo "${ML_POPDIR}" | sed 's,.,.,g'`
+@@ -794,6 +809,8 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    CC_="${CC_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\1/p"`' ' ;;
++	  -B*/lib/)
++	    CC_="${CC_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    CC_="${CC_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
+@@ -806,6 +823,8 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    CXX_="${CXX_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  -B*/lib/)
++	    CXX_="${CXX_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    CXX_="${CXX_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
+@@ -818,6 +837,8 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    F77_="${F77_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  -B*/lib/)
++	    F77_="${F77_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    F77_="${F77_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
+@@ -830,6 +851,8 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    GCJ_="${GCJ_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  -B*/lib/)
++	    GCJ_="${GCJ_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    GCJ_="${GCJ_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
+@@ -842,6 +865,8 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    GFORTRAN_="${GFORTRAN_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  -B*/lib/)
++	    GFORTRAN_="${GFORTRAN_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    GFORTRAN_="${GFORTRAN_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
+@@ -854,6 +879,8 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    GOC_="${GOC_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  -B*/lib/)
++	    GOC_="${GOC_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    GOC_="${GOC_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
--- gcc-6-6.4.0.orig/debian/patches/cross-fixes.diff
+++ gcc-6-6.4.0/debian/patches/cross-fixes.diff
@@ -0,0 +1,81 @@
+# DP: Fix the linker error when creating an xcc for ia64
+
+---
+ gcc/config/ia64/fde-glibc.c     |    3 +++
+ gcc/config/ia64/unwind-ia64.c   |    3 ++-
+ gcc/unwind-compat.c             |    2 ++
+ gcc/unwind-generic.h            |    2 ++
+ 6 files changed, 14 insertions(+), 1 deletions(-)
+
+Index: b/src/libgcc/config/ia64/fde-glibc.c
+===================================================================
+--- a/src/libgcc/config/ia64/fde-glibc.c
++++ b/src/libgcc/config/ia64/fde-glibc.c
+@@ -28,6 +28,7 @@
+ #ifndef _GNU_SOURCE
+ #define _GNU_SOURCE 1
+ #endif
++#ifndef inhibit_libc
+ #include "config.h"
+ #include <stddef.h>
+ #include <stdlib.h>
+@@ -159,3 +160,5 @@ _Unwind_FindTableEntry (void *pc, unw_wo
+ 
+   return data.ret;
+ }
++
++#endif
+Index: b/src/libgcc/config/ia64/unwind-ia64.c
+===================================================================
+--- a/src/libgcc/config/ia64/unwind-ia64.c
++++ b/src/libgcc/config/ia64/unwind-ia64.c
+@@ -26,6 +26,7 @@
+    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+    <http://www.gnu.org/licenses/>.  */
+ 
++#ifndef inhibit_libc
+ #include "tconfig.h"
+ #include "tsystem.h"
+ #include "coretypes.h"
+@@ -2466,3 +2467,4 @@ alias (_Unwind_SetIP);
+ #endif
+ 
+ #endif
++#endif
+Index: b/src/libgcc/unwind-compat.c
+===================================================================
+--- a/src/libgcc/unwind-compat.c
++++ b/src/libgcc/unwind-compat.c
+@@ -23,6 +23,7 @@
+    <http://www.gnu.org/licenses/>.  */
+ 
+ #if defined (USE_GAS_SYMVER) && defined (USE_LIBUNWIND_EXCEPTIONS)
++#ifndef inhibit_libc
+ #include "tconfig.h"
+ #include "tsystem.h"
+ #include "unwind.h"
+@@ -207,3 +208,4 @@ _Unwind_SetIP (struct _Unwind_Context *c
+ }
+ symver (_Unwind_SetIP, GCC_3.0);
+ #endif
++#endif
+Index: b/src/libgcc/unwind-generic.h
+===================================================================
+--- a/src/libgcc/unwind-generic.h
++++ b/src/libgcc/unwind-generic.h
+@@ -221,6 +221,7 @@ _Unwind_SjLj_Resume_or_Rethrow (struct _
+    compatible with the standard ABI for IA-64, we inline these.  */
+ 
+ #ifdef __ia64__
++#ifndef inhibit_libc
+ static inline _Unwind_Ptr
+ _Unwind_GetDataRelBase (struct _Unwind_Context *_C)
+ {
+@@ -237,6 +238,7 @@ _Unwind_GetTextRelBase (struct _Unwind_C
+ 
+ /* @@@ Retrieve the Backing Store Pointer of the given context.  */
+ extern _Unwind_Word _Unwind_GetBSP (struct _Unwind_Context *);
++#endif /* inhibit_libc */
+ #else
+ extern _Unwind_Ptr _Unwind_GetDataRelBase (struct _Unwind_Context *);
+ extern _Unwind_Ptr _Unwind_GetTextRelBase (struct _Unwind_Context *);
--- gcc-6-6.4.0.orig/debian/patches/cross-install-location.diff
+++ gcc-6-6.4.0/debian/patches/cross-install-location.diff
@@ -0,0 +1,409 @@
+Index: b/src/fixincludes/Makefile.in
+===================================================================
+--- a/src/fixincludes/Makefile.in
++++ b/src/fixincludes/Makefile.in
+@@ -52,9 +52,9 @@ target_noncanonical:=@target_noncanonica
+ gcc_version := $(shell cat $(srcdir)/../gcc/BASE-VER)
+ 
+ # Directory in which the compiler finds libraries etc.
+-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
+ # Directory in which the compiler finds executables
+-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
+ # Where our executable files go
+ itoolsdir = $(libexecsubdir)/install-tools
+ # Where our data files go
+Index: b/src/libgfortran/Makefile.in
+===================================================================
+--- a/src/libgfortran/Makefile.in
++++ b/src/libgfortran/Makefile.in
+@@ -604,12 +604,12 @@ libgfortran_la_LDFLAGS = -version-info `
+ 
+ libgfortran_la_DEPENDENCIES = $(version_dep) libgfortran.spec $(LIBQUADLIB_DEP)
+ cafexeclib_LTLIBRARIES = libcaf_single.la
+-cafexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR)
++cafexeclibdir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR)
+ libcaf_single_la_SOURCES = caf/single.c
+ libcaf_single_la_LDFLAGS = -static
+ libcaf_single_la_DEPENDENCIES = caf/libcaf.h
+ libcaf_single_la_LINK = $(LINK) $(libcaf_single_la_LDFLAGS)
+-@IEEE_SUPPORT_TRUE@fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR)/finclude
++@IEEE_SUPPORT_TRUE@fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR)/finclude
+ @IEEE_SUPPORT_TRUE@nodist_finclude_HEADERS = ieee_arithmetic.mod ieee_exceptions.mod ieee_features.mod
+ AM_CPPFLAGS = -iquote$(srcdir)/io -I$(srcdir)/$(MULTISRCTOP)../gcc \
+ 	      -I$(srcdir)/$(MULTISRCTOP)../gcc/config $(LIBQUADINCLUDE) \
+Index: b/src/libgfortran/Makefile.am
+===================================================================
+--- a/src/libgfortran/Makefile.am
++++ b/src/libgfortran/Makefile.am
+@@ -43,14 +43,14 @@ libgfortran_la_LDFLAGS = -version-info `
+ libgfortran_la_DEPENDENCIES = $(version_dep) libgfortran.spec $(LIBQUADLIB_DEP)
+ 
+ cafexeclib_LTLIBRARIES = libcaf_single.la
+-cafexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR)
++cafexeclibdir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR)
+ libcaf_single_la_SOURCES = caf/single.c
+ libcaf_single_la_LDFLAGS = -static
+ libcaf_single_la_DEPENDENCIES = caf/libcaf.h
+ libcaf_single_la_LINK = $(LINK) $(libcaf_single_la_LDFLAGS)
+ 
+ if IEEE_SUPPORT
+-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR)/finclude
++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)$(MULTISUBDIR)/finclude
+ nodist_finclude_HEADERS = ieee_arithmetic.mod ieee_exceptions.mod ieee_features.mod
+ endif
+ 
+Index: b/src/lto-plugin/Makefile.in
+===================================================================
+--- a/src/lto-plugin/Makefile.in
++++ b/src/lto-plugin/Makefile.in
+@@ -255,7 +255,7 @@ with_libiberty = @with_libiberty@
+ ACLOCAL_AMFLAGS = -I .. -I ../config
+ AUTOMAKE_OPTIONS = no-dependencies
+ gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER)
+-libexecsubdir := $(libexecdir)/gcc/$(real_target_noncanonical)/$(gcc_version)$(accel_dir_suffix)
++libexecsubdir := $(libexecdir)/gcc-cross/$(real_target_noncanonical)/$(gcc_version)$(accel_dir_suffix)
+ AM_CPPFLAGS = -I$(top_srcdir)/../include $(DEFS)
+ AM_CFLAGS = @ac_lto_plugin_warn_cflags@
+ AM_LDFLAGS = @ac_lto_plugin_ldflags@
+Index: b/src/lto-plugin/Makefile.am
+===================================================================
+--- a/src/lto-plugin/Makefile.am
++++ b/src/lto-plugin/Makefile.am
+@@ -5,7 +5,7 @@ AUTOMAKE_OPTIONS = no-dependencies
+ 
+ gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER)
+ target_noncanonical := @target_noncanonical@
+-libexecsubdir := $(libexecdir)/gcc/$(real_target_noncanonical)/$(gcc_version)$(accel_dir_suffix)
++libexecsubdir := $(libexecdir)/gcc-cross/$(real_target_noncanonical)/$(gcc_version)$(accel_dir_suffix)
+ 
+ AM_CPPFLAGS = -I$(top_srcdir)/../include $(DEFS)
+ AM_CFLAGS = @ac_lto_plugin_warn_cflags@
+Index: b/src/libitm/Makefile.in
+===================================================================
+--- a/src/libitm/Makefile.in
++++ b/src/libitm/Makefile.in
+@@ -334,8 +334,8 @@ SUBDIRS = testsuite
+ gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER)
+ abi_version = -fabi-version=4
+ search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir)
+-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude
+-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude
++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ AM_CPPFLAGS = $(addprefix -I, $(search_path))
+ AM_CFLAGS = $(XCFLAGS)
+ AM_CXXFLAGS = $(XCFLAGS) -std=gnu++0x -funwind-tables -fno-exceptions \
+Index: b/src/libitm/Makefile.am
+===================================================================
+--- a/src/libitm/Makefile.am
++++ b/src/libitm/Makefile.am
+@@ -11,8 +11,8 @@ abi_version = -fabi-version=4
+ config_path = @config_path@
+ search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir)
+ 
+-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude
+-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude
++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ 
+ vpath % $(strip $(search_path))
+ 
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -4179,7 +4179,7 @@ process_command (unsigned int decoded_op
+ 	 GCC_EXEC_PREFIX is typically a directory name with a trailing
+ 	 / (which is ignored by make_relative_prefix), so append a
+ 	 program name.  */
+-      char *tmp_prefix = concat (gcc_exec_prefix, "gcc", NULL);
++      char *tmp_prefix = concat (gcc_exec_prefix, "gcc-cross", NULL);
+       gcc_libexec_prefix = get_relative_prefix (tmp_prefix,
+ 						standard_exec_prefix,
+ 						standard_libexec_prefix);
+@@ -4205,15 +4205,15 @@ process_command (unsigned int decoded_op
+     {
+       int len = strlen (gcc_exec_prefix);
+ 
+-      if (len > (int) sizeof ("/lib/gcc/") - 1
++      if (len > (int) sizeof ("/lib/gcc-cross/") - 1
+ 	  && (IS_DIR_SEPARATOR (gcc_exec_prefix[len-1])))
+ 	{
+-	  temp = gcc_exec_prefix + len - sizeof ("/lib/gcc/") + 1;
++	  temp = gcc_exec_prefix + len - sizeof ("/lib/gcc-cross/") + 1;
+ 	  if (IS_DIR_SEPARATOR (*temp)
+ 	      && filename_ncmp (temp + 1, "lib", 3) == 0
+ 	      && IS_DIR_SEPARATOR (temp[4])
+-	      && filename_ncmp (temp + 5, "gcc", 3) == 0)
+-	    len -= sizeof ("/lib/gcc/") - 1;
++	      && filename_ncmp (temp + 5, "gcc-cross", 3) == 0)
++	    len -= sizeof ("/lib/gcc-cross/") - 1;
+ 	}
+ 
+       set_std_prefix (gcc_exec_prefix, len);
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -592,9 +592,9 @@ libexecdir = @libexecdir@
+ # --------
+ 
+ # Directory in which the compiler finds libraries etc.
+-libsubdir = $(libdir)/gcc/$(real_target_noncanonical)/$(version)$(accel_dir_suffix)
++libsubdir = $(libdir)/gcc-cross/$(real_target_noncanonical)/$(version)$(accel_dir_suffix)
+ # Directory in which the compiler finds executables
+-libexecsubdir = $(libexecdir)/gcc/$(real_target_noncanonical)/$(version)$(accel_dir_suffix)
++libexecsubdir = $(libexecdir)/gcc-cross/$(real_target_noncanonical)/$(version)$(accel_dir_suffix)
+ # Directory in which all plugin resources are installed
+ plugin_resourcesdir = $(libsubdir)/plugin
+  # Directory in which plugin headers are installed
+@@ -2017,8 +2017,8 @@ prefix.o: $(FULLVER)
+ 
+ DRIVER_DEFINES = \
+   -DSTANDARD_STARTFILE_PREFIX=\"$(unlibsubdir)/\" \
+-  -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
+-  -DSTANDARD_LIBEXEC_PREFIX=\"$(libexecdir)/gcc/\" \
++  -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc-cross/\" \
++  -DSTANDARD_LIBEXEC_PREFIX=\"$(libexecdir)/gcc-cross/\" \
+   -DDEFAULT_TARGET_VERSION=\"$(BASEVER_c)\" \
+   -DDEFAULT_TARGET_FULL_VERSION=\"$(FULLVER_c)\" \
+   -DDEFAULT_REAL_TARGET_MACHINE=\"$(real_target_noncanonical)\" \
+@@ -2671,7 +2671,7 @@ PREPROCESSOR_DEFINES = \
+   -DTOOL_INCLUDE_DIR=\"$(gcc_tooldir)/include\" \
+   -DNATIVE_SYSTEM_HEADER_DIR=\"$(NATIVE_SYSTEM_HEADER_DIR)\" \
+   -DPREFIX=\"$(prefix)/\" \
+-  -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
++  -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc-cross/\" \
+   @TARGET_SYSTEM_ROOT_DEFINE@
+ 
+ CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(FULLVER_s)
+Index: b/src/libssp/Makefile.in
+===================================================================
+--- a/src/libssp/Makefile.in
++++ b/src/libssp/Makefile.in
+@@ -287,7 +287,7 @@ gcc_version := $(shell cat $(top_srcdir)
+ @LIBSSP_USE_SYMVER_SUN_TRUE@@LIBSSP_USE_SYMVER_TRUE@version_dep = ssp.map-sun
+ AM_CFLAGS = -Wall
+ toolexeclib_LTLIBRARIES = libssp.la libssp_nonshared.la
+-libsubincludedir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include
++libsubincludedir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/include
+ nobase_libsubinclude_HEADERS = ssp/ssp.h ssp/string.h ssp/stdio.h ssp/unistd.h
+ libssp_la_SOURCES = \
+ 	ssp.c gets-chk.c memcpy-chk.c memmove-chk.c mempcpy-chk.c \
+Index: b/src/libssp/Makefile.am
+===================================================================
+--- a/src/libssp/Makefile.am
++++ b/src/libssp/Makefile.am
+@@ -39,7 +39,7 @@ AM_CFLAGS = -Wall
+ toolexeclib_LTLIBRARIES = libssp.la libssp_nonshared.la
+ 
+ target_noncanonical = @target_noncanonical@
+-libsubincludedir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include
++libsubincludedir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/include
+ nobase_libsubinclude_HEADERS = ssp/ssp.h ssp/string.h ssp/stdio.h ssp/unistd.h
+ 
+ libssp_la_SOURCES = \
+Index: b/src/libquadmath/Makefile.in
+===================================================================
+--- a/src/libquadmath/Makefile.in
++++ b/src/libquadmath/Makefile.in
+@@ -354,7 +354,7 @@ AUTOMAKE_OPTIONS = 1.8 foreign
+ 
+ @BUILD_LIBQUADMATH_TRUE@libquadmath_la_DEPENDENCIES = $(version_dep) $(libquadmath_la_LIBADD)
+ @BUILD_LIBQUADMATH_TRUE@nodist_libsubinclude_HEADERS = quadmath.h quadmath_weak.h
+-@BUILD_LIBQUADMATH_TRUE@libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++@BUILD_LIBQUADMATH_TRUE@libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ @BUILD_LIBQUADMATH_TRUE@libquadmath_la_SOURCES = \
+ @BUILD_LIBQUADMATH_TRUE@  math/x2y2m1q.c math/isinf_nsq.c math/acoshq.c math/fmodq.c \
+ @BUILD_LIBQUADMATH_TRUE@  math/acosq.c math/frexpq.c \
+Index: b/src/libquadmath/Makefile.am
+===================================================================
+--- a/src/libquadmath/Makefile.am
++++ b/src/libquadmath/Makefile.am
+@@ -41,7 +41,7 @@ libquadmath_la_LDFLAGS = -version-info `
+ libquadmath_la_DEPENDENCIES = $(version_dep) $(libquadmath_la_LIBADD)
+ 
+ nodist_libsubinclude_HEADERS = quadmath.h quadmath_weak.h
+-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ 
+ libquadmath_la_SOURCES = \
+   math/x2y2m1q.c math/isinf_nsq.c math/acoshq.c math/fmodq.c \
+Index: b/src/libobjc/Makefile.in
+===================================================================
+--- a/src/libobjc/Makefile.in
++++ b/src/libobjc/Makefile.in
+@@ -50,7 +50,7 @@ top_builddir = .
+ -include ../boehm-gc/threads.mk
+ 
+ libdir = $(exec_prefix)/lib
+-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
+ 
+ # Multilib support variables.
+ MULTISRCTOP =
+Index: b/src/libada/Makefile.in
+===================================================================
+--- a/src/libada/Makefile.in
++++ b/src/libada/Makefile.in
+@@ -68,7 +68,7 @@ GCC_DIR=$(MULTIBUILDTOP)../../$(host_sub
+ 
+ target_noncanonical:=@target_noncanonical@
+ version := $(shell cat $(srcdir)/../gcc/BASE-VER)
+-libsubdir := $(libdir)/gcc/$(target_noncanonical)/$(version)$(MULTISUBDIR)
++libsubdir := $(libdir)/gcc-cross/$(target_noncanonical)/$(version)$(MULTISUBDIR)
+ ADA_RTS_DIR=$(GCC_DIR)/ada/rts$(subst /,_,$(MULTISUBDIR))
+ ADA_RTS_SUBDIR=./rts$(subst /,_,$(MULTISUBDIR))
+ 
+Index: b/src/libgomp/Makefile.in
+===================================================================
+--- a/src/libgomp/Makefile.in
++++ b/src/libgomp/Makefile.in
+@@ -386,8 +386,8 @@ gcc_version := $(shell cat $(top_srcdir)
+ search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir) \
+ 	      $(top_srcdir)/../include
+ 
+-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude
+-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude
++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ AM_CPPFLAGS = $(addprefix -I, $(search_path))
+ AM_CFLAGS = $(XCFLAGS)
+ AM_LDFLAGS = $(XLDFLAGS) $(SECTION_LDFLAGS) $(OPT_LDFLAGS)
+Index: b/src/libgomp/Makefile.am
+===================================================================
+--- a/src/libgomp/Makefile.am
++++ b/src/libgomp/Makefile.am
+@@ -10,8 +10,8 @@ config_path = @config_path@
+ search_path = $(addprefix $(top_srcdir)/config/, $(config_path)) $(top_srcdir) \
+ 	      $(top_srcdir)/../include
+ 
+-fincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/finclude
+-libsubincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++fincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/finclude
++libsubincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ 
+ vpath % $(strip $(search_path))
+ 
+Index: b/src/libgcc/Makefile.in
+===================================================================
+--- a/src/libgcc/Makefile.in
++++ b/src/libgcc/Makefile.in
+@@ -186,7 +186,7 @@ STRIP = @STRIP@
+ STRIP_FOR_TARGET = $(STRIP)
+ 
+ # Directory in which the compiler finds libraries etc.
+-libsubdir = $(libdir)/gcc/$(real_host_noncanonical)/$(version)@accel_dir_suffix@
++libsubdir = $(libdir)/gcc-cross/$(real_host_noncanonical)/$(version)@accel_dir_suffix@
+ # Used to install the shared libgcc.
+ slibdir = @slibdir@
+ # Maybe used for DLLs on Windows targets.
+Index: b/src/libjava/Makefile.in
+===================================================================
+--- a/src/libjava/Makefile.in
++++ b/src/libjava/Makefile.in
+@@ -825,8 +825,8 @@ write_entries_to_file = $(shell rm -f $(
+ 
+ 
+ # This is required by TL_AC_GXX_INCLUDE_DIR.
+-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)
+-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
+ toolexeclib_LTLIBRARIES = libgcj.la libgij.la libgcj-tools.la \
+ 	$(am__append_2) $(am__append_3) $(am__append_4)
+ toolexecmainlib_DATA = libgcj.spec
+Index: b/src/libjava/Makefile.am
+===================================================================
+--- a/src/libjava/Makefile.am
++++ b/src/libjava/Makefile.am
+@@ -35,9 +35,9 @@ write_entries_to_file = $(shell rm -f $(
+ target_noncanonical = @target_noncanonical@
+ 
+ # This is required by TL_AC_GXX_INCLUDE_DIR.
+-libsubdir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libsubdir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
+ 
+-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libexecsubdir = $(libexecdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)
+ 
+ ##
+ ## What gets installed, and where.
+Index: b/src/libffi/include/Makefile.am
+===================================================================
+--- a/src/libffi/include/Makefile.am
++++ b/src/libffi/include/Makefile.am
+@@ -8,6 +8,6 @@ EXTRA_DIST=ffi.h.in
+ 
+ # Where generated headers like ffitarget.h get installed.
+ gcc_version   := $(shell cat $(top_srcdir)/../gcc/BASE-VER)
+-toollibffidir := $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++toollibffidir := $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ 
+ toollibffi_HEADERS = ffi.h ffitarget.h
+Index: b/src/libffi/include/Makefile.in
+===================================================================
+--- a/src/libffi/include/Makefile.in
++++ b/src/libffi/include/Makefile.in
+@@ -251,7 +251,7 @@ EXTRA_DIST = ffi.h.in
+ 
+ # Where generated headers like ffitarget.h get installed.
+ gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER)
+-toollibffidir := $(libdir)/gcc/$(target_alias)/$(gcc_version)/include
++toollibffidir := $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include
+ toollibffi_HEADERS = ffi.h ffitarget.h
+ all: all-am
+ 
+Index: b/src/libcc1/Makefile.am
+===================================================================
+--- a/src/libcc1/Makefile.am
++++ b/src/libcc1/Makefile.am
+@@ -35,7 +35,7 @@ libiberty = $(if $(wildcard $(libiberty_
+ 	    $(Wc)$(libiberty_normal)))
+ libiberty_dep = $(patsubst $(Wc)%,%,$(libiberty))
+ 
+-plugindir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/plugin
++plugindir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/plugin
+ cc1libdir = $(libdir)/$(libsuffix)
+ 
+ if ENABLE_PLUGIN
+Index: b/src/libcc1/Makefile.in
+===================================================================
+--- a/src/libcc1/Makefile.in
++++ b/src/libcc1/Makefile.in
+@@ -290,7 +290,7 @@ libiberty = $(if $(wildcard $(libiberty_
+ 	    $(Wc)$(libiberty_normal)))
+ 
+ libiberty_dep = $(patsubst $(Wc)%,%,$(libiberty))
+-plugindir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/plugin
++plugindir = $(libdir)/gcc-cross/$(target_noncanonical)/$(gcc_version)/plugin
+ cc1libdir = $(libdir)/$(libsuffix)
+ @ENABLE_PLUGIN_TRUE@plugin_LTLIBRARIES = libcc1plugin.la
+ @ENABLE_PLUGIN_TRUE@cc1lib_LTLIBRARIES = libcc1.la
+Index: b/src/libsanitizer/Makefile.am
+===================================================================
+--- a/src/libsanitizer/Makefile.am
++++ b/src/libsanitizer/Makefile.am
+@@ -1,6 +1,6 @@
+ ACLOCAL_AMFLAGS = -I .. -I ../config
+ 
+-sanincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include/sanitizer
++sanincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include/sanitizer
+ 
+ nodist_saninclude_HEADERS =
+ 
+Index: b/src/libsanitizer/Makefile.in
+===================================================================
+--- a/src/libsanitizer/Makefile.in
++++ b/src/libsanitizer/Makefile.in
+@@ -285,7 +285,7 @@ top_build_prefix = @top_build_prefix@
+ top_builddir = @top_builddir@
+ top_srcdir = @top_srcdir@
+ ACLOCAL_AMFLAGS = -I .. -I ../config
+-sanincludedir = $(libdir)/gcc/$(target_alias)/$(gcc_version)/include/sanitizer
++sanincludedir = $(libdir)/gcc-cross/$(target_alias)/$(gcc_version)/include/sanitizer
+ nodist_saninclude_HEADERS = $(am__append_1)
+ @SANITIZER_SUPPORTED_TRUE@SUBDIRS = sanitizer_common $(am__append_2) \
+ @SANITIZER_SUPPORTED_TRUE@	$(am__append_3) lsan asan ubsan \
--- gcc-6-6.4.0.orig/debian/patches/cross-no-locale-include.diff
+++ gcc-6-6.4.0/debian/patches/cross-no-locale-include.diff
@@ -0,0 +1,17 @@
+# DP: Don't add /usr/local/include for cross compilers. Assume that
+# DP: /usr/include is ready for multiarch, but not /usr/local/include.
+
+--- a/src/gcc/cppdefault.c
++++ b/src/gcc/cppdefault.c
+@@ -66,8 +66,11 @@
+ #ifdef LOCAL_INCLUDE_DIR
+     /* /usr/local/include comes before the fixincluded header files.  */
+     { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 },
++#if 0
++    /* Unsafe to assume that /usr/local/include is ready for multiarch.  */
+     { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 },
+ #endif
++#endif
+ #ifdef PREFIX_INCLUDE_DIR
+     { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0 },
+ #endif
--- gcc-6-6.4.0.orig/debian/patches/disable-gdc-tests.diff
+++ gcc-6-6.4.0/debian/patches/disable-gdc-tests.diff
@@ -0,0 +1,16 @@
+# DP: Disable D tests, hang on many buildds
+
+Index: b/src/gcc/d/Make-lang.in
+===================================================================
+--- a/src/gcc/d/Make-lang.in
++++ b/src/gcc/d/Make-lang.in
+@@ -284,6 +284,6 @@ d.stagefeedback: stagefeedback-start
+ # check targets.  However, our DejaGNU framework requires 'check-gdc' as its
+ # entry point.  We feed the former to the latter here.
+ check-d: check-gdc
+-lang_checks += check-gdc
+-lang_checks_parallelized += check-gdc
+-check_gdc_parallelize = 10
++#lang_checks += check-gdc
++#lang_checks_parallelized += check-gdc
++#check_gdc_parallelize = 10
--- gcc-6-6.4.0.orig/debian/patches/g++-multiarch-incdir.diff
+++ gcc-6-6.4.0/debian/patches/g++-multiarch-incdir.diff
@@ -0,0 +1,119 @@
+# DP: Use /usr/include/<multiarch>/c++/4.x as the include directory
+# DP: for host dependent c++ header files.
+
+Index: b/src/libstdc++-v3/include/Makefile.am
+===================================================================
+--- a/src/libstdc++-v3/include/Makefile.am
++++ b/src/libstdc++-v3/include/Makefile.am
+@@ -911,7 +911,7 @@ endif
+ 
+ host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR)
+ host_builddir = ./${host_alias}/bits
+-host_installdir = ${gxx_include_dir}/${host_alias}$(MULTISUBDIR)/bits
++host_installdir = $(if $(shell $(CC) -print-multiarch),/usr/include/$(shell $(filter-out -m%,$(CC)) -print-multiarch)/c++/$(notdir ${gxx_include_dir})$(MULTISUBDIR)/bits,${gxx_include_dir}/${default_host_alias}$(MULTISUBDIR)/bits)
+ host_headers = \
+ 	${host_srcdir}/ctype_base.h \
+ 	${host_srcdir}/ctype_inline.h \
+Index: b/src/libstdc++-v3/include/Makefile.in
+===================================================================
+--- a/src/libstdc++-v3/include/Makefile.in
++++ b/src/libstdc++-v3/include/Makefile.in
+@@ -1193,7 +1193,7 @@ profile_impl_headers = \
+ @GLIBCXX_C_HEADERS_COMPATIBILITY_TRUE@c_compatibility_headers_extra = ${c_compatibility_headers}
+ host_srcdir = ${glibcxx_srcdir}/$(OS_INC_SRCDIR)
+ host_builddir = ./${host_alias}/bits
+-host_installdir = ${gxx_include_dir}/${host_alias}$(MULTISUBDIR)/bits
++host_installdir = $(if $(shell $(CC) -print-multiarch),/usr/include/$(shell $(filter-out -m%,$(CC)) -print-multiarch)/c++/$(notdir ${gxx_include_dir})$(MULTISUBDIR)/bits,${gxx_include_dir}/${default_host_alias}$(MULTISUBDIR)/bits)
+ host_headers = \
+ 	${host_srcdir}/ctype_base.h \
+ 	${host_srcdir}/ctype_inline.h \
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -1140,6 +1140,7 @@ FLAGS_TO_PASS = \
+ 	"prefix=$(prefix)" \
+ 	"local_prefix=$(local_prefix)" \
+ 	"gxx_include_dir=$(gcc_gxx_include_dir)" \
++	"gxx_tool_include_dir=$(gcc_gxx_tool_include_dir)" \
+ 	"build_tooldir=$(build_tooldir)" \
+ 	"gcc_tooldir=$(gcc_tooldir)" \
+ 	"bindir=$(bindir)" \
+@@ -1637,6 +1638,14 @@ ifneq ($(xmake_file),)
+ include $(xmake_file)
+ endif
+ 
++# Directory in which the compiler finds target-dependent g++ includes.
++ifneq ($(call if_multiarch,non-empty),)
++  gcc_gxx_tool_include_dir = $(libsubdir)/$(libsubdir_to_prefix)include/$(MULTIARCH_DIRNAME)/c++/$(BASEVER_c)
++else
++  gcc_gxx_tool_include_dir = $(gcc_gxx_include_dir)/$(target_noncanonical)
++endif
++
++
+ # all-tree.def includes all the tree.def files.
+ all-tree.def: s-alltree; @true
+ s-alltree: Makefile
+@@ -2675,7 +2684,7 @@ PREPROCESSOR_DEFINES = \
+   -DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \
+   -DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \
+   -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \
+-  -DGPLUSPLUS_TOOL_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/$(target_noncanonical)\" \
++  -DGPLUSPLUS_TOOL_INCLUDE_DIR=\"$(gcc_gxx_tool_include_dir)\" \
+   -DGPLUSPLUS_BACKWARD_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/backward\" \
+   -DLOCAL_INCLUDE_DIR=\"$(local_includedir)\" \
+   -DCROSS_INCLUDE_DIR=\"$(CROSS_SYSTEM_HEADER_DIR)\" \
+Index: b/src/gcc/cppdefault.c
+===================================================================
+--- a/src/gcc/cppdefault.c
++++ b/src/gcc/cppdefault.c
+@@ -49,6 +49,8 @@ const struct default_include cpp_include
+     /* Pick up GNU C++ target-dependent include files.  */
+     { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1,
+       GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 },
++    { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1,
++      GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 2 },
+ #endif
+ #ifdef GPLUSPLUS_BACKWARD_INCLUDE_DIR
+     /* Pick up GNU C++ backward and deprecated include files.  */
+Index: b/src/gcc/incpath.c
+===================================================================
+--- a/src/gcc/incpath.c
++++ b/src/gcc/incpath.c
+@@ -158,6 +158,18 @@ add_standard_paths (const char *sysroot,
+ 			}
+ 		      str = reconcat (str, str, dir_separator_str,
+ 				      imultiarch, NULL);
++		      if (p->cplusplus && strstr (str, "/c++/"))
++			{
++			  char *suffix = strstr (str, "/c++/");
++			  *suffix++ = '\0';
++			  suffix = xstrdup (suffix);
++			  str = reconcat (str, str, dir_separator_str,
++					  imultiarch,
++					  dir_separator_str, suffix, NULL);
++			}
++		      else
++			str = reconcat (str, str, dir_separator_str,
++					imultiarch, NULL);
+ 		    }
+ 		  add_path (str, SYSTEM, p->cxx_aware, false);
+ 		}
+@@ -222,7 +234,16 @@ add_standard_paths (const char *sysroot,
+ 		  free (str);
+ 		  continue;
+ 		}
+-	      str = reconcat (str, str, dir_separator_str, imultiarch, NULL);
++	      if (p->cplusplus && strstr (str, "/c++/"))
++		{
++		  char *suffix = strstr (str, "/c++/");
++		  *suffix++ = '\0';
++		  suffix = xstrdup (suffix);
++		  str = reconcat (str, str, dir_separator_str, imultiarch,
++				  dir_separator_str, suffix, NULL);
++		}
++	      else
++		str = reconcat (str, str, dir_separator_str, imultiarch, NULL);
+ 	    }
+ 
+ 	  add_path (str, SYSTEM, p->cxx_aware, false);
--- gcc-6-6.4.0.orig/debian/patches/gcc-SOURCE_DATE_EPOCH-2-doc.diff
+++ gcc-6-6.4.0/debian/patches/gcc-SOURCE_DATE_EPOCH-2-doc.diff
@@ -0,0 +1,31 @@
+gcc/ChangeLog:
+
+2016-05-13  Eduard Sanou  <dhole@openmailbox.org>
+
+	* doc/cppenv.texi: Note that the `%s` in `date` is a non-standard
+	extension.
+
+diff --git a/gcc/doc/cppenv.texi b/gcc/doc/cppenv.texi
+index e958e93..8cefd52 100644
+--- a/src/gcc/doc/cppenv.texi
++++ b/src/gcc/doc/cppenv.texi
+@@ -81,7 +81,6 @@ main input file is omitted.
+ @end ifclear
+ 
+ @item SOURCE_DATE_EPOCH
+-
+ If this variable is set, its value specifies a UNIX timestamp to be
+ used in replacement of the current date and time in the @code{__DATE__}
+ and @code{__TIME__} macros, so that the embedded timestamps become
+@@ -89,8 +88,9 @@ reproducible.
+ 
+ The value of @env{SOURCE_DATE_EPOCH} must be a UNIX timestamp,
+ defined as the number of seconds (excluding leap seconds) since
+-01 Jan 1970 00:00:00 represented in ASCII, identical to the output of
+-@samp{@command{date +%s}}.
++01 Jan 1970 00:00:00 represented in ASCII; identical to the output of
++@samp{@command{date +%s}} on GNU/Linux and other systems that support the
++@code{%s} extension in the @code{date} command.
+ 
+ The value should be a known timestamp such as the last modification
+ time of the source or package and it should be set by the build
--- gcc-6-6.4.0.orig/debian/patches/gcc-SOURCE_DATE_EPOCH-2.diff
+++ gcc-6-6.4.0/debian/patches/gcc-SOURCE_DATE_EPOCH-2.diff
@@ -0,0 +1,378 @@
+gcc/c-family/ChangeLog:
+
+2016-05-13  Eduard Sanou  <dhole@openmailbox.org>
+
+	* c-common.c (get_source_date_epoch): Rename to
+	cb_get_source_date_epoch.
+	* c-common.c (cb_get_source_date_epoch): Use a single generic erorr
+	message when the parsing fails.  Use error_at instead of fatal_error.
+	* c-common.h (get_source_date_epoch): Rename to
+	cb_get_source_date_epoch.
+	* c-common.h (cb_get_source_date_epoch): Prototype.
+	* c-common.h (MAX_SOURCE_DATE_EPOCH): Define.
+	* c-common.h (c_omp_region_type): Remove trailing comma.
+	* c-lex.c (init_c_lex): Set cb->get_source_date_epoch callback.
+	* c-lex.c (c_lex_with_flags): Remove initialization of
+	pfile->source_date_epoch.
+
+gcc/ChangeLog:
+
+2016-05-13  Eduard Sanou  <dhole@openmailbox.org>
+
+	* doc/cppenv.texi: Note that the `%s` in `date` is a non-standard
+	extension.
+	* gcc.c (driver_handle_option): Call set_source_date_epoch_envvar.
+	* gcc.c (set_source_date_epoch_envvar): New function, sets
+	the SOURCE_DATE_EPOCH environment variable to the current time.
+
+gcc/testsuite/ChangeLog:
+
+2016-05-13  Eduard Sanou  <dhole@openmailbox.org>
+
+	* gcc.dg/cpp/source_date_epoch-1.c: New file, test the proper
+	behaviour of the macros __DATE__ and __TIME__ when SOURCE_DATE_EPOCH
+	env var is set.
+	* gcc.dg/cpp/source_date_epoch-2.c: New file, test the error output
+	when parsing the SOURCE_DATE_EPOCH env var, and make sure it is only
+	shown once.
+	* lib/gcc-dg.exp (dg-set-compiler-env-var): New function, set env vars
+	during compilation.
+	* lib/gcc-dg.exp (restore-compiler-env-var): New function, restore env
+	vars set by dg-set-compiler-env-var.
+
+libcpp/ChangeLog:
+
+2016-05-13  Eduard Sanou  <dhole@openmailbox.org>
+
+	* include/cpplib.h (cpp_callbacks): Add get_source_date_epoch
+	callback.
+	* include/cpplib.h (cpp_init_source_date_epoch): Remove prototype.
+	* init.c (cpp_init_source_date_epoch): Remove function.
+	* init.c (cpp_create_reader): Initialize pfile->source_date_epoch.
+	* internal.h (cpp_reader): Extend comment about source_date_epoch.
+	* macro.c (_cpp_builtin_macro_text): Use get_source_date_epoch
+	callback only once, read pfile->source_date_epoch on future passes.
+	Check that get_source_date_epoch callback is not NULL.
+
+Index: b/src/gcc/c-family/c-common.c
+===================================================================
+--- a/src/gcc/c-family/c-common.c
++++ b/src/gcc/c-family/c-common.c
+@@ -12753,8 +12753,9 @@ valid_array_size_p (location_t loc, tree
+ /* Read SOURCE_DATE_EPOCH from environment to have a deterministic
+    timestamp to replace embedded current dates to get reproducible
+    results.  Returns -1 if SOURCE_DATE_EPOCH is not defined.  */
++
+ time_t
+-get_source_date_epoch ()
++cb_get_source_date_epoch (cpp_reader *pfile ATTRIBUTE_UNUSED)
+ {
+   char *source_date_epoch;
+   long long epoch;
+@@ -12766,19 +12767,14 @@ get_source_date_epoch ()
+ 
+   errno = 0;
+   epoch = strtoll (source_date_epoch, &endptr, 10);
+-  if ((errno == ERANGE && (epoch == LLONG_MAX || epoch == LLONG_MIN))
+-      || (errno != 0 && epoch == 0))
+-    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
+-		 "strtoll: %s\n", xstrerror(errno));
+-  if (endptr == source_date_epoch)
+-    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
+-		 "no digits were found: %s\n", endptr);
+-  if (*endptr != '\0')
+-    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
+-		 "trailing garbage: %s\n", endptr);
+-  if (epoch < 0)
+-    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
+-		 "value must be nonnegative: %lld \n", epoch);
++  if (errno != 0 || endptr == source_date_epoch || *endptr != '\0'
++      || epoch < 0 || epoch > MAX_SOURCE_DATE_EPOCH)
++    {
++      error_at (input_location, "environment variable SOURCE_DATE_EPOCH must "
++	        "expand to a non-negative integer less than or equal to %wd",
++		MAX_SOURCE_DATE_EPOCH);
++      return (time_t) -1;
++    }
+ 
+   return (time_t) epoch;
+ }
+Index: b/src/gcc/c-family/c-common.h
+===================================================================
+--- a/src/gcc/c-family/c-common.h
++++ b/src/gcc/c-family/c-common.h
+@@ -1084,6 +1084,16 @@ extern vec<tree, va_gc> *make_tree_vecto
+    c_register_builtin_type.  */
+ extern GTY(()) tree registered_builtin_types;
+ 
++/* Read SOURCE_DATE_EPOCH from environment to have a deterministic
++   timestamp to replace embedded current dates to get reproducible
++   results.  Returns -1 if SOURCE_DATE_EPOCH is not defined.  */
++extern time_t cb_get_source_date_epoch (cpp_reader *pfile);
++
++/* The value (as a unix timestamp) corresponds to date
++   "Dec 31 9999 23:59:59 UTC", which is the latest date that __DATE__ and
++   __TIME__ can store.  */
++#define MAX_SOURCE_DATE_EPOCH HOST_WIDE_INT_C (253402300799)
++
+ /* In c-gimplify.c  */
+ extern void c_genericize (tree);
+ extern int c_gimplify_expr (tree *, gimple_seq *, gimple_seq *);
+@@ -1467,9 +1477,4 @@ extern bool reject_gcc_builtin (const_tr
+ extern void warn_duplicated_cond_add_or_warn (location_t, tree, vec<tree> **);
+ extern bool valid_array_size_p (location_t, tree, tree);
+ 
+-/* Read SOURCE_DATE_EPOCH from environment to have a deterministic
+-   timestamp to replace embedded current dates to get reproducible
+-   results.  Returns -1 if SOURCE_DATE_EPOCH is not defined.  */
+-extern time_t get_source_date_epoch (void);
+-
+ #endif /* ! GCC_C_COMMON_H */
+Index: b/src/gcc/c-family/c-lex.c
+===================================================================
+--- a/src/gcc/c-family/c-lex.c
++++ b/src/gcc/c-family/c-lex.c
+@@ -80,6 +80,7 @@ init_c_lex (void)
+   cb->valid_pch = c_common_valid_pch;
+   cb->read_pch = c_common_read_pch;
+   cb->has_attribute = c_common_has_attribute;
++  cb->get_source_date_epoch = cb_get_source_date_epoch;
+ 
+   /* Set the debug callbacks if we can use them.  */
+   if ((debug_info_level == DINFO_LEVEL_VERBOSE
+@@ -385,9 +386,6 @@ c_lex_with_flags (tree *value, location_
+   enum cpp_ttype type;
+   unsigned char add_flags = 0;
+   enum overflow_type overflow = OT_NONE;
+-  time_t source_date_epoch = get_source_date_epoch ();
+-
+-  cpp_init_source_date_epoch (parse_in, source_date_epoch);
+ 
+   timevar_push (TV_CPP);
+  retry:
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -3542,6 +3542,29 @@ save_switch (const char *opt, size_t n_a
+   n_switches++;
+ }
+ 
++/* Set the SOURCE_DATE_EPOCH environment variable to the current time if it is
++   not set already.  */
++
++static void
++set_source_date_epoch_envvar ()
++{
++  /* Array size is 21 = ceil(log_10(2^64)) + 1 to hold string representations
++     of 64 bit integers.  */
++  char source_date_epoch[21];
++  time_t tt;
++
++  errno = 0;
++  tt = time (NULL);
++  if (tt < (time_t) 0 || errno != 0)
++    tt = (time_t) 0;
++
++  snprintf (source_date_epoch, 21, "%llu", (unsigned long long) tt);
++  /* Using setenv instead of xputenv because we want the variable to remain
++     after finalizing so that it's still set in the second run when using
++     -fcompare-debug.  */
++  setenv ("SOURCE_DATE_EPOCH", source_date_epoch, 0);
++}
++
+ /* Handle an option DECODED that is unknown to the option-processing
+    machinery.  */
+ 
+@@ -3841,6 +3864,7 @@ driver_handle_option (struct gcc_options
+       else
+ 	compare_debug_opt = arg;
+       save_switch (compare_debug_replacement_opt, 0, NULL, validated, true);
++      set_source_date_epoch_envvar ();
+       return true;
+ 
+     case OPT_fdiagnostics_color_:
+Index: b/src/gcc/testsuite/gcc.dg/cpp/source_date_epoch-1.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/cpp/source_date_epoch-1.c
+@@ -0,0 +1,11 @@
++/* { dg-do run } */
++/* { dg-set-compiler-env-var SOURCE_DATE_EPOCH "630333296" } */
++
++int
++main()
++{
++  if (__builtin_strcmp (__DATE__, "Dec 22 1989") != 0
++      || __builtin_strcmp (__TIME__, "12:34:56") != 0)
++    __builtin_abort ();
++  return 0;
++}
+Index: b/src/gcc/testsuite/gcc.dg/cpp/source_date_epoch-2.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/cpp/source_date_epoch-2.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-set-compiler-env-var SOURCE_DATE_EPOCH "AAA" } */
++
++/* Make sure that SOURCE_DATE_EPOCH is only parsed once */
++
++int
++main(void)
++{
++  __builtin_printf ("%s %s\n", __DATE__, __TIME__); /* { dg-error "SOURCE_DATE_EPOCH must expand" } */
++  __builtin_printf ("%s %s\n", __DATE__, __TIME__);
++  return 0;
++}
+Index: b/src/gcc/testsuite/lib/gcc-dg.exp
+===================================================================
+--- a/src/gcc/testsuite/lib/gcc-dg.exp
++++ b/src/gcc/testsuite/lib/gcc-dg.exp
+@@ -450,6 +450,38 @@ proc restore-target-env-var { } {
+     }
+ }
+ 
++proc dg-set-compiler-env-var { args } {
++    global set_compiler_env_var
++    global saved_compiler_env_var
++    if { [llength $args] != 3 } {
++	error "dg-set-compiler-env-var: need two arguments"
++	return
++    }
++    set var [lindex $args 1]
++    set value [lindex $args 2]
++    if [info exists ::env($var)] {
++      lappend saved_compiler_env_var [list $var 1 $::env($var)]
++    } else {
++      lappend saved_compiler_env_var [list $var 0]
++    }
++    setenv $var $value
++    lappend set_compiler_env_var [list $var $value]
++}
++
++proc restore-compiler-env-var { } {
++    global saved_compiler_env_var
++    for { set env_vari [llength $saved_compiler_env_var] } {
++          [incr env_vari -1] >= 0 } {} {
++	set env_var [lindex $saved_compiler_env_var $env_vari]
++	set var [lindex $env_var 0]
++	if [lindex $env_var 1] {
++	    setenv $var [lindex $env_var 2]
++	} else {
++	    unsetenv $var
++	}
++    }
++}
++
+ # Utility routines.
+ 
+ #
+@@ -862,6 +894,8 @@ if { [info procs saved-dg-test] == [list
+ 	global shouldfail
+ 	global testname_with_flags
+ 	global set_target_env_var
++	global set_compiler_env_var
++	global saved_compiler_env_var
+ 	global keep_saved_temps_suffixes
+ 	global multiline_expected_outputs
+ 
+@@ -876,6 +910,11 @@ if { [info procs saved-dg-test] == [list
+ 	if [info exists keep_saved_temps_suffixes] {
+ 	    unset keep_saved_temps_suffixes
+ 	}
++	if [info exists set_compiler_env_var] {
++	    restore-compiler-env-var
++	    unset set_compiler_env_var
++	    unset saved_compiler_env_var
++	}
+ 	unset_timeout_vars
+ 	if [info exists compiler_conditional_xfail_data] {
+ 	    unset compiler_conditional_xfail_data
+Index: b/src/libcpp/include/cpplib.h
+===================================================================
+--- a/src/libcpp/include/cpplib.h
++++ b/src/libcpp/include/cpplib.h
+@@ -594,6 +594,9 @@ struct cpp_callbacks
+ 
+   /* Callback that can change a user builtin into normal macro.  */
+   bool (*user_builtin_macro) (cpp_reader *, cpp_hashnode *);
++
++  /* Callback to parse SOURCE_DATE_EPOCH from environment.  */
++  time_t (*get_source_date_epoch) (cpp_reader *);
+ };
+ 
+ #ifdef VMS
+@@ -784,9 +787,6 @@ extern void cpp_init_special_builtins (c
+ /* Set up built-ins like __FILE__.  */
+ extern void cpp_init_builtins (cpp_reader *, int);
+ 
+-/* Initialize the source_date_epoch value.  */
+-extern void cpp_init_source_date_epoch (cpp_reader *, time_t);
+-
+ /* This is called after options have been parsed, and partially
+    processed.  */
+ extern void cpp_post_options (cpp_reader *);
+Index: b/src/libcpp/init.c
+===================================================================
+--- a/src/libcpp/init.c
++++ b/src/libcpp/init.c
+@@ -257,6 +257,9 @@ cpp_create_reader (enum c_lang lang, cpp
+   /* Do not force token locations by default.  */
+   pfile->forced_token_location_p = NULL;
+ 
++  /* Initialize source_date_epoch to -2 (not yet set).  */
++  pfile->source_date_epoch = (time_t) -2;
++
+   /* The expression parser stack.  */
+   _cpp_expand_op_stack (pfile);
+ 
+@@ -533,13 +536,6 @@ cpp_init_builtins (cpp_reader *pfile, in
+     _cpp_define_builtin (pfile, "__OBJC__ 1");
+ }
+ 
+-/* Initialize the source_date_epoch value.  */
+-void
+-cpp_init_source_date_epoch (cpp_reader *pfile, time_t source_date_epoch)
+-{
+-  pfile->source_date_epoch = source_date_epoch; 
+-}
+-
+ /* Sanity-checks are dependent on command-line options, so it is
+    called as a subroutine of cpp_read_main_file.  */
+ #if CHECKING_P
+Index: b/src/libcpp/internal.h
+===================================================================
+--- a/src/libcpp/internal.h
++++ b/src/libcpp/internal.h
+@@ -503,7 +503,8 @@ struct cpp_reader
+   const unsigned char *time;
+ 
+   /* Externally set timestamp to replace current date and time useful for
+-     reproducibility.  */
++     reproducibility.  It should be initialized to -2 (not yet set) and
++     set to -1 to disable it or to a non-negative value to enable it.  */
+   time_t source_date_epoch;
+ 
+   /* EOF token, and a token forcing paste avoidance.  */
+Index: b/src/libcpp/macro.c
+===================================================================
+--- a/src/libcpp/macro.c
++++ b/src/libcpp/macro.c
+@@ -358,9 +358,13 @@ _cpp_builtin_macro_text (cpp_reader *pfi
+ 	  struct tm *tb = NULL;
+ 
+ 	  /* Set a reproducible timestamp for __DATE__ and __TIME__ macro
+-	     usage if SOURCE_DATE_EPOCH is defined.  */
+-	  if (pfile->source_date_epoch != (time_t) -1)
+-	     tb = gmtime (&pfile->source_date_epoch);
++	     if SOURCE_DATE_EPOCH is defined.  */
++	  if (pfile->source_date_epoch == (time_t) -2
++	      && pfile->cb.get_source_date_epoch != NULL)
++	    pfile->source_date_epoch = pfile->cb.get_source_date_epoch (pfile);
++
++	  if (pfile->source_date_epoch >= (time_t) 0)
++	    tb = gmtime (&pfile->source_date_epoch);
+ 	  else
+ 	    {
+ 	      /* (time_t) -1 is a legitimate value for "number of seconds
--- gcc-6-6.4.0.orig/debian/patches/gcc-SOURCE_DATE_EPOCH-doc.diff
+++ gcc-6-6.4.0/debian/patches/gcc-SOURCE_DATE_EPOCH-doc.diff
@@ -0,0 +1,33 @@
+# DP: Allow embedded timestamps by C/C++ macros to be set externally (docs)
+
+gcc/ChangeLog:
+
+2016-04-27  Eduard Sanou  <dhole@openmailbox.org>
+	    Matthias Klose  <doko@debian.org>
+
+	* doc/cppenv.texi: Document SOURCE_DATE_EPOCH environment variable.
+
+--- a/src/gcc/doc/cppenv.texi
++++ b/src/gcc/doc/cppenv.texi
+@@ -79,4 +79,21 @@
+ @ifclear cppmanual
+ @xref{Preprocessor Options}.
+ @end ifclear
++
++@item SOURCE_DATE_EPOCH
++
++If this variable is set, its value specifies a UNIX timestamp to be
++used in replacement of the current date and time in the @code{__DATE__}
++and @code{__TIME__} macros, so that the embedded timestamps become
++reproducible.
++
++The value of @env{SOURCE_DATE_EPOCH} must be a UNIX timestamp,
++defined as the number of seconds (excluding leap seconds) since
++01 Jan 1970 00:00:00 represented in ASCII, identical to the output of
++@samp{@command{date +%s}}.
++
++The value should be a known timestamp such as the last modification
++time of the source or package and it should be set by the build
++process.
++
+ @end vtable
--- gcc-6-6.4.0.orig/debian/patches/gcc-SOURCE_DATE_EPOCH.diff
+++ gcc-6-6.4.0/debian/patches/gcc-SOURCE_DATE_EPOCH.diff
@@ -0,0 +1,186 @@
+# DP: Allow embedded timestamps by C/C++ macros to be set externally
+
+gcc/c-family/ChangeLog:
+
+2016-04-27  Eduard Sanou  <dhole@openmailbox.org>
+	    Matthias Klose  <doko@debian.org>
+
+	* c-common.c (get_source_date_epoch): New function, gets the environment
+	variable SOURCE_DATE_EPOCH and parses it as long long with error 
+	handling.
+	* c-common.h (get_source_date_epoch): Prototype.
+	* c-lex.c (c_lex_with_flags): set parse_in->source_date_epoch.
+
+gcc/ChangeLog:
+
+2016-04-27  Eduard Sanou  <dhole@openmailbox.org>
+	    Matthias Klose  <doko@debian.org>
+
+	* doc/cppenv.texi: Document SOURCE_DATE_EPOCH environment variable.
+
+libcpp/ChangeLog:
+
+2016-04-27  Eduard Sanou  <dhole@openmailbox.org>
+	    Matthias Klose  <doko@debian.org>
+
+	* include/cpplib.h (cpp_init_source_date_epoch): Prototype.
+	* init.c (cpp_init_source_date_epoch): New function.
+	* internal.h: Added source_date_epoch variable to struct
+	cpp_reader to store a reproducible date.
+	* macro.c (_cpp_builtin_macro_text): Set pfile->date timestamp from 
+	pfile->source_date_epoch instead of localtime if source_date_epoch is 
+	set, to be used for __DATE__ and __TIME__ macros to help reproducible 
+	builds.
+
+Index: b/src/gcc/c-family/c-common.c
+===================================================================
+--- a/src/gcc/c-family/c-common.c
++++ b/src/gcc/c-family/c-common.c
+@@ -12750,4 +12750,37 @@ valid_array_size_p (location_t loc, tree
+   return true;
+ }
+ 
++/* Read SOURCE_DATE_EPOCH from environment to have a deterministic
++   timestamp to replace embedded current dates to get reproducible
++   results.  Returns -1 if SOURCE_DATE_EPOCH is not defined.  */
++time_t
++get_source_date_epoch ()
++{
++  char *source_date_epoch;
++  long long epoch;
++  char *endptr;
++
++  source_date_epoch = getenv ("SOURCE_DATE_EPOCH");
++  if (!source_date_epoch)
++    return (time_t) -1;
++
++  errno = 0;
++  epoch = strtoll (source_date_epoch, &endptr, 10);
++  if ((errno == ERANGE && (epoch == LLONG_MAX || epoch == LLONG_MIN))
++      || (errno != 0 && epoch == 0))
++    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
++		 "strtoll: %s\n", xstrerror(errno));
++  if (endptr == source_date_epoch)
++    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
++		 "no digits were found: %s\n", endptr);
++  if (*endptr != '\0')
++    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
++		 "trailing garbage: %s\n", endptr);
++  if (epoch < 0)
++    fatal_error (UNKNOWN_LOCATION, "environment variable $SOURCE_DATE_EPOCH: "
++		 "value must be nonnegative: %lld \n", epoch);
++
++  return (time_t) epoch;
++}
++
+ #include "gt-c-family-c-common.h"
+Index: b/src/gcc/c-family/c-common.h
+===================================================================
+--- a/src/gcc/c-family/c-common.h
++++ b/src/gcc/c-family/c-common.h
+@@ -1467,4 +1467,9 @@ extern bool reject_gcc_builtin (const_tr
+ extern void warn_duplicated_cond_add_or_warn (location_t, tree, vec<tree> **);
+ extern bool valid_array_size_p (location_t, tree, tree);
+ 
++/* Read SOURCE_DATE_EPOCH from environment to have a deterministic
++   timestamp to replace embedded current dates to get reproducible
++   results.  Returns -1 if SOURCE_DATE_EPOCH is not defined.  */
++extern time_t get_source_date_epoch (void);
++
+ #endif /* ! GCC_C_COMMON_H */
+Index: b/src/gcc/c-family/c-lex.c
+===================================================================
+--- a/src/gcc/c-family/c-lex.c
++++ b/src/gcc/c-family/c-lex.c
+@@ -385,6 +385,9 @@ c_lex_with_flags (tree *value, location_
+   enum cpp_ttype type;
+   unsigned char add_flags = 0;
+   enum overflow_type overflow = OT_NONE;
++  time_t source_date_epoch = get_source_date_epoch ();
++
++  cpp_init_source_date_epoch (parse_in, source_date_epoch);
+ 
+   timevar_push (TV_CPP);
+  retry:
+Index: b/src/libcpp/include/cpplib.h
+===================================================================
+--- a/src/libcpp/include/cpplib.h
++++ b/src/libcpp/include/cpplib.h
+@@ -784,6 +784,9 @@ extern void cpp_init_special_builtins (c
+ /* Set up built-ins like __FILE__.  */
+ extern void cpp_init_builtins (cpp_reader *, int);
+ 
++/* Initialize the source_date_epoch value.  */
++extern void cpp_init_source_date_epoch (cpp_reader *, time_t);
++
+ /* This is called after options have been parsed, and partially
+    processed.  */
+ extern void cpp_post_options (cpp_reader *);
+Index: b/src/libcpp/init.c
+===================================================================
+--- a/src/libcpp/init.c
++++ b/src/libcpp/init.c
+@@ -533,8 +533,15 @@ cpp_init_builtins (cpp_reader *pfile, in
+     _cpp_define_builtin (pfile, "__OBJC__ 1");
+ }
+ 
++/* Initialize the source_date_epoch value.  */
++void
++cpp_init_source_date_epoch (cpp_reader *pfile, time_t source_date_epoch)
++{
++  pfile->source_date_epoch = source_date_epoch; 
++}
++
+ /* Sanity-checks are dependent on command-line options, so it is
+-   called as a subroutine of cpp_read_main_file ().  */
++   called as a subroutine of cpp_read_main_file.  */
+ #if CHECKING_P
+ static void sanity_checks (cpp_reader *);
+ static void sanity_checks (cpp_reader *pfile)
+Index: b/src/libcpp/internal.h
+===================================================================
+--- a/src/libcpp/internal.h
++++ b/src/libcpp/internal.h
+@@ -502,6 +502,10 @@ struct cpp_reader
+   const unsigned char *date;
+   const unsigned char *time;
+ 
++  /* Externally set timestamp to replace current date and time useful for
++     reproducibility.  */
++  time_t source_date_epoch;
++
+   /* EOF token, and a token forcing paste avoidance.  */
+   cpp_token avoid_paste;
+   cpp_token eof;
+Index: b/src/libcpp/macro.c
+===================================================================
+--- a/src/libcpp/macro.c
++++ b/src/libcpp/macro.c
+@@ -357,13 +357,20 @@ _cpp_builtin_macro_text (cpp_reader *pfi
+ 	  time_t tt;
+ 	  struct tm *tb = NULL;
+ 
+-	  /* (time_t) -1 is a legitimate value for "number of seconds
+-	     since the Epoch", so we have to do a little dance to
+-	     distinguish that from a genuine error.  */
+-	  errno = 0;
+-	  tt = time(NULL);
+-	  if (tt != (time_t)-1 || errno == 0)
+-	    tb = localtime (&tt);
++	  /* Set a reproducible timestamp for __DATE__ and __TIME__ macro
++	     usage if SOURCE_DATE_EPOCH is defined.  */
++	  if (pfile->source_date_epoch != (time_t) -1)
++	     tb = gmtime (&pfile->source_date_epoch);
++	  else
++	    {
++	      /* (time_t) -1 is a legitimate value for "number of seconds
++		 since the Epoch", so we have to do a little dance to
++		 distinguish that from a genuine error.  */
++	      errno = 0;
++	      tt = time (NULL);
++	      if (tt != (time_t)-1 || errno == 0)
++		tb = localtime (&tt);
++	    }
+ 
+ 	  if (tb)
+ 	    {
--- gcc-6-6.4.0.orig/debian/patches/gcc-as-needed-gold.diff
+++ gcc-6-6.4.0/debian/patches/gcc-as-needed-gold.diff
@@ -0,0 +1,17 @@
+# DP: Use --push-state/--pop-state for gold as well when linking libtsan.
+
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -700,10 +700,10 @@
+ #define LIBTSAN_SPEC STATIC_LIBTSAN_LIBS
+ #elif defined(HAVE_LD_STATIC_DYNAMIC)
+ #define LIBTSAN_SPEC "%{static-libtsan:" LD_STATIC_OPTION "}" \
+-		     " %{!static-libtsan:%{!fuse-ld=gold:--push-state }--no-as-needed}" \
++		     " %{!static-libtsan:--push-state --no-as-needed}" \
+ 		     " -ltsan " \
+ 		     " %{static-libtsan:" LD_DYNAMIC_OPTION "}" \
+-		     " %{!static-libtsan:%{fuse-ld=gold:--as-needed;:--pop-state}}" \
++		     " %{!static-libtsan:--pop-state}" \
+ 		     STATIC_LIBTSAN_LIBS
+ #else
+ #define LIBTSAN_SPEC "-ltsan" STATIC_LIBTSAN_LIBS
--- gcc-6-6.4.0.orig/debian/patches/gcc-as-needed.diff
+++ gcc-6-6.4.0/debian/patches/gcc-as-needed.diff
@@ -0,0 +1,209 @@
+# DP: On linux targets pass --as-needed by default to the linker, but always
+# DP: link the sanitizer libraries with --no-as-needed.
+
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -568,8 +568,11 @@ proper position among the other output f
+ #ifdef LIBTSAN_EARLY_SPEC
+ #define LIBTSAN_SPEC STATIC_LIBTSAN_LIBS
+ #elif defined(HAVE_LD_STATIC_DYNAMIC)
+-#define LIBTSAN_SPEC "%{static-libtsan:" LD_STATIC_OPTION \
+-		     "} -ltsan %{static-libtsan:" LD_DYNAMIC_OPTION "}" \
++#define LIBTSAN_SPEC "%{static-libtsan:" LD_STATIC_OPTION "}" \
++		     " %{!static-libtsan:%{!fuse-ld=gold:--push-state }--no-as-needed}" \
++		     " -ltsan " \
++		     " %{static-libtsan:" LD_DYNAMIC_OPTION "}" \
++		     " %{!static-libtsan:%{fuse-ld=gold:--as-needed;:--pop-state}}" \
+ 		     STATIC_LIBTSAN_LIBS
+ #else
+ #define LIBTSAN_SPEC "-ltsan" STATIC_LIBTSAN_LIBS
+--- a/src/gcc/config/gnu-user.h
++++ b/src/gcc/config/gnu-user.h
+@@ -124,13 +124,13 @@
+ #define LIBASAN_EARLY_SPEC "%{!shared:libasan_preinit%O%s} " \
+   "%{static-libasan:%{!shared:" \
+   LD_STATIC_OPTION " --whole-archive -lasan --no-whole-archive " \
+-  LD_DYNAMIC_OPTION "}}%{!static-libasan:-lasan}"
++  LD_DYNAMIC_OPTION "}}%{!static-libasan:%{!fuse-ld=gold:--push-state} --no-as-needed -lasan %{fuse-ld=gold:--as-needed;:--pop-state}}"
+ #undef LIBTSAN_EARLY_SPEC
+ #define LIBTSAN_EARLY_SPEC "%{static-libtsan:%{!shared:" \
+   LD_STATIC_OPTION " --whole-archive -ltsan --no-whole-archive " \
+-  LD_DYNAMIC_OPTION "}}%{!static-libtsan:-ltsan}"
++  LD_DYNAMIC_OPTION "}}%{!static-libtsan:%{!fuse-ld=gold:--push-state} --no-as-needed -ltsan %{fuse-ld=gold:--as-needed;:--pop-state}}"
+ #undef LIBLSAN_EARLY_SPEC
+ #define LIBLSAN_EARLY_SPEC "%{static-liblsan:%{!shared:" \
+   LD_STATIC_OPTION " --whole-archive -llsan --no-whole-archive " \
+-  LD_DYNAMIC_OPTION "}}%{!static-liblsan:-llsan}"
++  LD_DYNAMIC_OPTION "}}%{!static-liblsan:%{!fuse-ld=gold:--push-state} --no-as-needed -llsan %{fuse-ld=gold:--as-needed;:--pop-state}}"
+ #endif
+Index: b/src/gcc/config/aarch64/aarch64-linux.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64-linux.h
++++ b/src/gcc/config/aarch64/aarch64-linux.h
+@@ -36,6 +36,7 @@
+ 
+ #define LINUX_TARGET_LINK_SPEC  "%{h*}		\
+    --hash-style=gnu				\
++   --as-needed					\
+    %{static:-Bstatic}				\
+    %{shared:-shared}				\
+    %{symbolic:-Bsymbolic}			\
+Index: b/src/gcc/config/ia64/linux.h
+===================================================================
+--- a/src/gcc/config/ia64/linux.h
++++ b/src/gcc/config/ia64/linux.h
+@@ -58,7 +58,7 @@ do {						\
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
+ 
+ #undef LINK_SPEC
+-#define LINK_SPEC " --hash-style=gnu \
++#define LINK_SPEC " --hash-style=gnu --as-needed \
+   %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/sparc/linux.h
+===================================================================
+--- a/src/gcc/config/sparc/linux.h
++++ b/src/gcc/config/sparc/linux.h
+@@ -86,7 +86,7 @@ extern const char *host_detect_local_cpu
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+ 
+ #undef  LINK_SPEC
+-#define LINK_SPEC "-m elf32_sparc --hash-style=gnu %{shared:-shared} \
++#define LINK_SPEC "-m elf32_sparc --hash-style=gnu --as-needed %{shared:-shared} \
+   %{!mno-relax:%{!r:-relax}} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/s390/linux.h
+===================================================================
+--- a/src/gcc/config/s390/linux.h
++++ b/src/gcc/config/s390/linux.h
+@@ -65,7 +65,7 @@ along with GCC; see the file COPYING3.
+ 
+ #undef  LINK_SPEC
+ #define LINK_SPEC \
+-  "%{m31:-m elf_s390}%{m64:-m elf64_s390} --hash-style=gnu \
++  "%{m31:-m elf_s390}%{m64:-m elf64_s390} --hash-style=gnu --as-needed \
+    %{shared:-shared} \
+    %{!shared: \
+       %{static:-static} \
+Index: b/src/gcc/config/rs6000/linux64.h
+===================================================================
+--- a/src/gcc/config/rs6000/linux64.h
++++ b/src/gcc/config/rs6000/linux64.h
+@@ -466,12 +466,12 @@ extern int dot_symbols;
+ 					   " -m elf64ppc")
+ #endif
+ 
+-#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " --hash-style=gnu %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " --hash-style=gnu --as-needed %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}} \
+   %(link_os_extra_spec32)"
+ 
+-#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " --hash-style=gnu %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " --hash-style=gnu --as-needed %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "}} \
+   %(link_os_extra_spec64)"
+Index: b/src/gcc/config/rs6000/sysv4.h
+===================================================================
+--- a/src/gcc/config/rs6000/sysv4.h
++++ b/src/gcc/config/rs6000/sysv4.h
+@@ -784,7 +784,7 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEF
+   CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, \
+ 			 MUSL_DYNAMIC_LINKER)
+ 
+-#define LINK_OS_LINUX_SPEC "-m elf32ppclinux --hash-style=gnu %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC "-m elf32ppclinux --hash-style=gnu --as-needed %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}"
+ 
+Index: b/src/gcc/config/i386/gnu-user64.h
+===================================================================
+--- a/src/gcc/config/i386/gnu-user64.h
++++ b/src/gcc/config/i386/gnu-user64.h
+@@ -57,6 +57,7 @@ see the files COPYING3 and COPYING.RUNTI
+                    %{" SPEC_32 ":-m " GNU_USER_LINK_EMULATION32 "} \
+                    %{" SPEC_X32 ":-m " GNU_USER_LINK_EMULATIONX32 "} \
+   --hash-style=gnu \
++  --as-needed \
+   %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/i386/gnu-user.h
+===================================================================
+--- a/src/gcc/config/i386/gnu-user.h
++++ b/src/gcc/config/i386/gnu-user.h
+@@ -74,7 +74,7 @@ along with GCC; see the file COPYING3.
+   { "link_emulation", GNU_USER_LINK_EMULATION },\
+   { "dynamic_linker", GNU_USER_DYNAMIC_LINKER }
+ 
+-#define GNU_USER_TARGET_LINK_SPEC "-m %(link_emulation) --hash-style=gnu %{shared:-shared} \
++#define GNU_USER_TARGET_LINK_SPEC "-m %(link_emulation) --hash-style=gnu --as-needed %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+       %{rdynamic:-export-dynamic} \
+Index: b/src/gcc/config/alpha/linux-elf.h
+===================================================================
+--- a/src/gcc/config/alpha/linux-elf.h
++++ b/src/gcc/config/alpha/linux-elf.h
+@@ -37,7 +37,7 @@ along with GCC; see the file COPYING3.
+ 
+ #define ELF_DYNAMIC_LINKER	GNU_USER_DYNAMIC_LINKER
+ 
+-#define LINK_SPEC "-m elf64alpha --hash-style=gnu %{G*} %{relax:-relax}	\
++#define LINK_SPEC "-m elf64alpha --hash-style=gnu --as-needed %{G*} %{relax:-relax}	\
+   %{O*:-O3} %{!O*:-O1}						\
+   %{shared:-shared}						\
+   %{!shared:							\
+Index: b/src/gcc/config/arm/linux-elf.h
+===================================================================
+--- a/src/gcc/config/arm/linux-elf.h
++++ b/src/gcc/config/arm/linux-elf.h
+@@ -73,6 +73,7 @@
+      %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} \
+    -X \
+    --hash-style=gnu \
++   --as-needed \
+    %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
+    SUBTARGET_EXTRA_LINK_SPEC
+ 
+Index: b/src/gcc/config/mips/gnu-user.h
+===================================================================
+--- a/src/gcc/config/mips/gnu-user.h
++++ b/src/gcc/config/mips/gnu-user.h
+@@ -55,6 +55,7 @@ along with GCC; see the file COPYING3.
+ #undef GNU_USER_TARGET_LINK_SPEC
+ #define GNU_USER_TARGET_LINK_SPEC "\
+   %{G*} %{EB} %{EL} %{mips*} %{shared} \
++ -as-needed \
+   %{!shared: \
+     %{!static: \
+       %{rdynamic:-export-dynamic} \
+Index: b/src/libjava/Makefile.am
+===================================================================
+--- a/src/libjava/Makefile.am
++++ b/src/libjava/Makefile.am
+@@ -628,7 +628,7 @@ libgcj_bc.la: $(libgcj_bc_la_OBJECTS) $(
+ 	rm .libs/libgcj_bc.so; \
+ 	mv .libs/libgcj_bc.so.1.0.0 .libs/libgcj_bc.so; \
+ 	$(libgcj_bc_dummy_LINK) -xc /dev/null -Wl,-soname,libgcj_bc.so.1 \
+-	-o .libs/libgcj_bc.so.1.0.0 -lgcj || exit; \
++	-o .libs/libgcj_bc.so.1.0.0 -Wl,--no-as-needed -lgcj || exit; \
+ 	rm .libs/libgcj_bc.so.1; \
+ 	$(LN_S) libgcj_bc.so.1.0.0 .libs/libgcj_bc.so.1
+ 
+Index: b/src/libjava/Makefile.in
+===================================================================
+--- a/src/libjava/Makefile.in
++++ b/src/libjava/Makefile.in
+@@ -10646,7 +10646,7 @@ libgcj_bc.la: $(libgcj_bc_la_OBJECTS) $(
+ 	rm .libs/libgcj_bc.so; \
+ 	mv .libs/libgcj_bc.so.1.0.0 .libs/libgcj_bc.so; \
+ 	$(libgcj_bc_dummy_LINK) -xc /dev/null -Wl,-soname,libgcj_bc.so.1 \
+-	-o .libs/libgcj_bc.so.1.0.0 -lgcj || exit; \
++	-o .libs/libgcj_bc.so.1.0.0 -Wl,--no-as-needed -lgcj || exit; \
+ 	rm .libs/libgcj_bc.so.1; \
+ 	$(LN_S) libgcj_bc.so.1.0.0 .libs/libgcj_bc.so.1
+ 
--- gcc-6-6.4.0.orig/debian/patches/gcc-auto-build.diff
+++ gcc-6-6.4.0/debian/patches/gcc-auto-build.diff
@@ -0,0 +1,15 @@
+# DP: Fix cross building a native compiler.
+
+Index: b/src/gcc/configure.ac
+===================================================================
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -1686,7 +1686,7 @@ else
+ 	# Clearing GMPINC is necessary to prevent host headers being
+ 	# used by the build compiler.  Defining GENERATOR_FILE stops
+ 	# system.h from including gmp.h.
+-	CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
++	CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD} -DGENERATOR_FILE" \
+ 	CXX="${CXX_FOR_BUILD}" CXXFLAGS="${CXXFLAGS_FOR_BUILD}" \
+ 	LD="${LD_FOR_BUILD}" LDFLAGS="${LDFLAGS_FOR_BUILD}" \
+ 	GMPINC="" CPPFLAGS="${CPPFLAGS} -DGENERATOR_FILE" \
--- gcc-6-6.4.0.orig/debian/patches/gcc-base-version.diff
+++ gcc-6-6.4.0/debian/patches/gcc-base-version.diff
@@ -0,0 +1,228 @@
+# DP: Set base version to 5, introduce full version 5.x.y.
+
+Index: b/src/gcc/BASE-VER
+===================================================================
+--- a/src/gcc/BASE-VER
++++ b/src/gcc/BASE-VER
+@@ -1 +1 @@
+-6.4.0
++6
+Index: b/src/gcc/FULL-VER
+===================================================================
+--- /dev/null
++++ b/src/gcc/FULL-VER
+@@ -0,0 +1 @@
++6.4.0
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -829,11 +829,13 @@ GTM_H     = tm.h      $(tm_file_list) in
+ TM_H      = $(GTM_H) insn-flags.h $(OPTIONS_H)
+ 
+ # Variables for version information.
+-BASEVER     := $(srcdir)/BASE-VER  # 4.x.y
++FULLVER     := $(srcdir)/FULL-VER  # 6.x.y
++BASEVER     := $(srcdir)/BASE-VER  # 6.x
+ DEVPHASE    := $(srcdir)/DEV-PHASE # experimental, prerelease, ""
+ DATESTAMP   := $(srcdir)/DATESTAMP # YYYYMMDD or empty
+ REVISION    := $(srcdir)/REVISION  # [BRANCH revision XXXXXX]
+ 
++FULLVER_c   := $(shell cat $(FULLVER))
+ BASEVER_c   := $(shell cat $(BASEVER))
+ DEVPHASE_c  := $(shell cat $(DEVPHASE))
+ DATESTAMP_c := $(shell cat $(DATESTAMP))
+@@ -858,6 +860,7 @@ PATCHLEVEL_c := \
+ # immediately after the comma in the $(if ...) constructs is
+ # significant - do not remove it.
+ BASEVER_s   := "\"$(BASEVER_c)\""
++FULLVER_s   := "\"$(FULLVER_c)\""
+ DEVPHASE_s  := "\"$(if $(DEVPHASE_c), ($(DEVPHASE_c)))\""
+ DATESTAMP_s := \
+   "\"$(if $(DEVPHASE_c)$(filter-out 0,$(PATCHLEVEL_c)), $(DATESTAMP_c))\""
+@@ -2016,8 +2019,8 @@ default-c.o: config/default-c.c
+ 
+ # Files used by all variants of C and some other languages.
+ 
+-CFLAGS-prefix.o += -DPREFIX=\"$(prefix)\" -DBASEVER=$(BASEVER_s)
+-prefix.o: $(BASEVER)
++CFLAGS-prefix.o += -DPREFIX=\"$(prefix)\" -DBASEVER=$(FULLVER_s)
++prefix.o: $(FULLVER)
+ 
+ # Language-independent files.
+ 
+@@ -2025,7 +2028,8 @@ DRIVER_DEFINES = \
+   -DSTANDARD_STARTFILE_PREFIX=\"$(unlibsubdir)/\" \
+   -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
+   -DSTANDARD_LIBEXEC_PREFIX=\"$(libexecdir)/gcc/\" \
+-  -DDEFAULT_TARGET_VERSION=\"$(version)\" \
++  -DDEFAULT_TARGET_VERSION=\"$(BASEVER_c)\" \
++  -DDEFAULT_TARGET_FULL_VERSION=\"$(FULLVER_c)\" \
+   -DDEFAULT_REAL_TARGET_MACHINE=\"$(real_target_noncanonical)\" \
+   -DDEFAULT_TARGET_MACHINE=\"$(target_noncanonical)\" \
+   -DSTANDARD_BINDIR_PREFIX=\"$(bindir)/\" \
+@@ -2076,20 +2080,20 @@ s-options-h: optionlist $(srcdir)/opt-fu
+ 
+ dumpvers: dumpvers.c
+ 
+-CFLAGS-version.o += -DBASEVER=$(BASEVER_s) -DDATESTAMP=$(DATESTAMP_s) \
++CFLAGS-version.o += -DBASEVER=$(FULLVER_s) -DDATESTAMP=$(DATESTAMP_s) \
+ 	-DREVISION=$(REVISION_s) \
+ 	-DDEVPHASE=$(DEVPHASE_s) -DPKGVERSION=$(PKGVERSION_s) \
+ 	-DBUGURL=$(BUGURL_s)
+-version.o: $(REVISION) $(DATESTAMP) $(BASEVER) $(DEVPHASE)
++version.o: $(REVISION) $(DATESTAMP) $(FULLVER) $(DEVPHASE)
+ 
+ # lto-compress.o needs $(ZLIBINC) added to the include flags.
+ CFLAGS-lto-compress.o += $(ZLIBINC)
+ 
+ bversion.h: s-bversion; @true
+-s-bversion: BASE-VER
+-	echo "#define BUILDING_GCC_MAJOR `echo $(BASEVER_c) | sed -e 's/^\([0-9]*\).*$$/\1/'`" > bversion.h
+-	echo "#define BUILDING_GCC_MINOR `echo $(BASEVER_c) | sed -e 's/^[0-9]*\.\([0-9]*\).*$$/\1/'`" >> bversion.h
+-	echo "#define BUILDING_GCC_PATCHLEVEL `echo $(BASEVER_c) | sed -e 's/^[0-9]*\.[0-9]*\.\([0-9]*\)$$/\1/'`" >> bversion.h
++s-bversion: FULL-VER
++	echo "#define BUILDING_GCC_MAJOR `echo $(FULLVER_c) | sed -e 's/^\([0-9]*\).*$$/\1/'`" > bversion.h
++	echo "#define BUILDING_GCC_MINOR `echo $(FULLVER_c) | sed -e 's/^[0-9]*\.\([0-9]*\).*$$/\1/'`" >> bversion.h
++	echo "#define BUILDING_GCC_PATCHLEVEL `echo $(FULLVER_c) | sed -e 's/^[0-9]*\.[0-9]*\.\([0-9]*\)$$/\1/'`" >> bversion.h
+ 	echo "#define BUILDING_GCC_VERSION (BUILDING_GCC_MAJOR * 1000 + BUILDING_GCC_MINOR)" >> bversion.h
+ 	$(STAMP) s-bversion
+ 
+@@ -2456,9 +2460,9 @@ build/%.o :  # dependencies provided by
+ ## build/version.o is compiled by the $(COMPILER_FOR_BUILD) but needs
+ ## several C macro definitions, just like version.o
+ build/version.o:  version.c version.h \
+-                  $(REVISION) $(DATESTAMP) $(BASEVER) $(DEVPHASE)
++                  $(REVISION) $(DATESTAMP) $(FULLVER) $(DEVPHASE)
+ 	$(COMPILER_FOR_BUILD) -c $(BUILD_COMPILERFLAGS) $(BUILD_CPPFLAGS) \
+-	-DBASEVER=$(BASEVER_s) -DDATESTAMP=$(DATESTAMP_s) \
++	-DBASEVER=$(FULLVER_s) -DDATESTAMP=$(DATESTAMP_s) \
+ 	-DREVISION=$(REVISION_s) \
+ 	-DDEVPHASE=$(DEVPHASE_s) -DPKGVERSION=$(PKGVERSION_s) \
+ 	-DBUGURL=$(BUGURL_s) -o $@ $<
+@@ -2681,8 +2685,8 @@ PREPROCESSOR_DEFINES = \
+   -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
+   @TARGET_SYSTEM_ROOT_DEFINE@
+ 
+-CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(BASEVER_s)
+-cppbuiltin.o: $(BASEVER)
++CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(FULLVER_s)
++cppbuiltin.o: $(FULLVER)
+ 
+ CFLAGS-cppdefault.o += $(PREPROCESSOR_DEFINES)
+ 
+@@ -2698,8 +2702,8 @@ build/gcov-iov$(build_exeext): build/gco
+ 		build/gcov-iov.o -o $@
+ 
+ gcov-iov.h: s-iov; @true
+-s-iov: build/gcov-iov$(build_exeext) $(BASEVER) $(DEVPHASE)
+-	build/gcov-iov$(build_exeext) '$(BASEVER_c)' '$(DEVPHASE_c)' \
++s-iov: build/gcov-iov$(build_exeext) $(FULLVER) $(DEVPHASE)
++	build/gcov-iov$(build_exeext) '$(FULLVER_c)' '$(DEVPHASE_c)' \
+ 	    > tmp-gcov-iov.h
+ 	$(SHELL) $(srcdir)/../move-if-change tmp-gcov-iov.h gcov-iov.h
+ 	$(STAMP) s-iov
+@@ -2978,8 +2982,8 @@ TEXI_GCCINSTALL_FILES = install.texi ins
+ TEXI_CPPINT_FILES = cppinternals.texi gcc-common.texi gcc-vers.texi
+ 
+ # gcc-vers.texi is generated from the version files.
+-gcc-vers.texi: $(BASEVER) $(DEVPHASE)
+-	(echo "@set version-GCC $(BASEVER_c)"; \
++gcc-vers.texi: $(FULLVER) $(DEVPHASE)
++	(echo "@set version-GCC $(FULLVER_c)"; \
+ 	 if [ "$(DEVPHASE_c)" = "experimental" ]; \
+ 	 then echo "@set DEVELOPMENT"; \
+ 	 else echo "@clear DEVELOPMENT"; \
+Index: b/src/libjava/testsuite/lib/libjava.exp
+===================================================================
+--- a/src/libjava/testsuite/lib/libjava.exp
++++ b/src/libjava/testsuite/lib/libjava.exp
+@@ -179,7 +179,8 @@ proc libjava_init { args } {
+ 
+     set text [eval exec "$GCJ_UNDER_TEST -B$specdir -v 2>@ stdout"]
+     regexp " version \[^\n\r\]*" $text version
+-    set libjava_version [lindex $version 1]
++    # FIXME: Still needed?
++    set libjava_version 6
+ 
+     verbose "version: $libjava_version"
+ 
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -278,7 +278,8 @@ static const char *compiler_version;
+ 
+ /* The target version.  */
+ 
+-static const char *const spec_version = DEFAULT_TARGET_VERSION;
++static const char *const base_version = DEFAULT_TARGET_VERSION;
++static const char *const spec_version = DEFAULT_TARGET_FULL_VERSION;
+ 
+ /* The target machine.  */
+ 
+@@ -4502,7 +4503,7 @@ process_command (unsigned int decoded_op
+      running, or, if that is not available, the configured prefix.  */
+   tooldir_prefix
+     = concat (gcc_exec_prefix ? gcc_exec_prefix : standard_exec_prefix,
+-	      spec_host_machine, dir_separator_str, spec_version,
++	      spec_host_machine, dir_separator_str, base_version,
+ 	      accel_dir_suffix, dir_separator_str, tooldir_prefix2, NULL);
+   free (tooldir_prefix2);
+ 
+@@ -7377,7 +7378,7 @@ driver::set_up_specs () const
+ 
+   /* Read specs from a file if there is one.  */
+ 
+-  machine_suffix = concat (spec_host_machine, dir_separator_str, spec_version,
++  machine_suffix = concat (spec_host_machine, dir_separator_str, base_version,
+ 			   accel_dir_suffix, dir_separator_str, NULL);
+   just_machine_suffix = concat (spec_machine, dir_separator_str, NULL);
+ 
+@@ -7582,7 +7583,7 @@ driver::set_up_specs () const
+   /* If we have a GCC_EXEC_PREFIX envvar, modify it for cpp's sake.  */
+   if (gcc_exec_prefix)
+     gcc_exec_prefix = concat (gcc_exec_prefix, spec_host_machine,
+-			      dir_separator_str, spec_version,
++			      dir_separator_str, base_version,
+ 			      accel_dir_suffix, dir_separator_str, NULL);
+ 
+   /* Now we have the specs.
+Index: b/src/gcc/configure.ac
+===================================================================
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -207,7 +207,7 @@ if test x${gcc_gxx_include_dir} = x; the
+   if test x${enable_version_specific_runtime_libs} = xyes; then
+     gcc_gxx_include_dir='${libsubdir}/include/c++'
+   else
+-    libstdcxx_incdir='include/c++/$(version)'
++    libstdcxx_incdir='include/c++/$(BASEVER_c)'
+     if test x$host != x$target; then
+        libstdcxx_incdir="$target_alias/$libstdcxx_incdir"
+     fi
+@@ -1746,6 +1746,7 @@ changequote([,])dnl
+ 
+ changequote(,)dnl
+ gcc_BASEVER=`cat $srcdir/BASE-VER`
++gcc_FULLVER=`cat $srcdir/FULL-VER`
+ gcc_DEVPHASE=`cat $srcdir/DEV-PHASE`
+ gcc_DATESTAMP=`cat $srcdir/DATESTAMP`
+ if test -f $srcdir/REVISION ; then
+@@ -1756,12 +1757,12 @@ fi
+ cat > plugin-version.h <<EOF
+ #include "configargs.h"
+ 
+-#define GCCPLUGIN_VERSION_MAJOR   `echo $gcc_BASEVER | sed -e 's/^\([0-9]*\).*$/\1/'`
+-#define GCCPLUGIN_VERSION_MINOR   `echo $gcc_BASEVER | sed -e 's/^[0-9]*\.\([0-9]*\).*$/\1/'`
+-#define GCCPLUGIN_VERSION_PATCHLEVEL   `echo $gcc_BASEVER | sed -e 's/^[0-9]*\.[0-9]*\.\([0-9]*\)$/\1/'`
++#define GCCPLUGIN_VERSION_MAJOR   `echo $gcc_FULLVER | sed -e 's/^\([0-9]*\).*$/\1/'`
++#define GCCPLUGIN_VERSION_MINOR   `echo $gcc_FULLVER | sed -e 's/^[0-9]*\.\([0-9]*\).*$/\1/'`
++#define GCCPLUGIN_VERSION_PATCHLEVEL   `echo $gcc_FULLVER | sed -e 's/^[0-9]*\.[0-9]*\.\([0-9]*\)$/\1/'`
+ #define GCCPLUGIN_VERSION  (GCCPLUGIN_VERSION_MAJOR*1000 + GCCPLUGIN_VERSION_MINOR)
+ 
+-static char basever[] = "$gcc_BASEVER";
++static char basever[] = "$gcc_FULLVER";
+ static char datestamp[] = "$gcc_DATESTAMP";
+ static char devphase[] = "$gcc_DEVPHASE";
+ static char revision[] = "$gcc_REVISION";
--- gcc-6-6.4.0.orig/debian/patches/gcc-d-lang.diff
+++ gcc-6-6.4.0/debian/patches/gcc-d-lang.diff
@@ -0,0 +1,251 @@
+# DP: Add D options and specs for the gcc driver.
+
+Index: b/src/gcc/d/lang-specs.h
+===================================================================
+--- /dev/null
++++ b/src/gcc/d/lang-specs.h
+@@ -0,0 +1,31 @@
++/* lang-specs.h -- D frontend for GCC.
++   Copyright (C) 2011, 2012 Free Software Foundation, Inc.
++
++   GCC is free software; you can redistribute it and/or modify it under
++   the terms of the GNU General Public License as published by the Free
++   Software Foundation; either version 3, or (at your option) any later
++   version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT ANY
++   WARRANTY; without even the implied warranty of MERCHANTABILITY or
++   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++   for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with GCC; see the file COPYING3.  If not see
++   <http://www.gnu.org/licenses/>.
++*/
++
++/* %{!M} probably doesn't make sense because we would need
++   to do that -- -MD and -MMD doesn't sound like a plan for D.... */
++
++{".d", "@d", 0, 1, 0 },
++{".D", "@d", 0, 1, 0 },
++{".dd", "@d", 0, 1, 0 },
++{".DD", "@d", 0, 1, 0 },
++{".di", "@d", 0, 1, 0 },
++{".DI", "@d", 0, 1, 0 },
++{"@d",
++  "%{!E:cc1d %i %(cc1_options) %(cc1d) %I %{nostdinc*} %{+e*} %{I*} %{J*}\
++    %{M} %{MM} %{!fsyntax-only:%(invoke_as)}}", 0, 1, 0 },
++
+Index: b/src/gcc/d/lang.opt
+===================================================================
+--- /dev/null
++++ b/src/gcc/d/lang.opt
+@@ -0,0 +1,208 @@
++; GDC -- D front-end for GCC
++; Copyright (C) 2011, 2012 Free Software Foundation, Inc.
++;
++; This program is free software; you can redistribute it and/or modify
++; it under the terms of the GNU General Public License as published by
++; the Free Software Foundation; either version 2 of the License, or
++; (at your option) any later version.
++;
++; This program is distributed in the hope that it will be useful,
++; but WITHOUT ANY WARRANTY; without even the implied warranty of
++; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++; GNU General Public License for more details.
++;
++; You should have received a copy of the GNU General Public License
++; along with GCC; see the file COPYING3.  If not see
++; <http://www.gnu.org/licenses/>.
++
++Language
++D
++
++debuglib=
++Driver Joined
++Debug library to use instead of phobos
++
++defaultlib=
++Driver Joined
++Default library to use instead of phobos
++
++fassert
++D
++Permit the use of the assert keyword
++
++; For D: defaults to on
++fbounds-check
++D
++Generate code to check bounds before indexing arrays
++
++fbuiltin
++D Var(flag_no_builtin, 0)
++Recognize built-in functions
++
++fdebug
++D
++Compile in debug code
++
++fdebug=
++D Joined RejectNegative
++-fdebug,-fdebug=<level>,-fdebug=<ident> Compile in debug code, code <= level, or code identified by ident
++
++fdeps=
++D Joined RejectNegative
++-fdeps=<filename> Write module dependencies to filename
++
++fdoc
++D
++Generate documentation
++
++fdoc-dir=
++D Joined RejectNegative
++-fdoc-dir=<docdir> Write documentation file to docdir directory
++
++fdoc-file=
++D Joined RejectNegative
++-fdoc-file=<filename> Write documentation file to filename
++
++fdoc-inc=
++D Joined RejectNegative
++-fdoc-inc=<filename> Include a Ddoc macro file
++
++fdump-source
++D RejectNegative
++Dump decoded UTF-8 text and source from HTML
++
++fd-verbose
++D
++Print information about D language processing to stdout
++
++fd-vtls
++D
++List all variables going into thread local storage
++
++femit-templates
++D
++-femit-templates Emit templates code and data even if the linker cannot merge multiple copies
++
++fignore-unknown-pragmas
++D
++Ignore unsupported pragmas
++
++fin
++D
++Generate runtime code for in() contracts
++
++fintfc
++Generate D interface files
++
++fintfc-dir=
++D Joined RejectNegative
++-fintfc-dir=<dir> Write D interface files to directory <dir>
++
++fintfc-file=
++D Joined RejectNegative
++-fintfc-file=<filename> Write D interface file to <filename>
++
++finvariants
++D
++Generate runtime code for invariant()'s
++
++fmake-deps=
++D Joined RejectNegative
++-fmake-deps=<file> Write dependency output to the given file
++
++fmake-mdeps=
++D Joined RejectNegative
++Like -fmake-deps=<file> but ignore system modules
++
++femit-moduleinfo
++D
++Generate ModuleInfo struct for output module
++
++fonly=
++D Joined RejectNegative
++Process all modules specified on the command line, but only generate code for the module specified by the argument
++
++fout
++D
++Generate runtime code for out() contracts
++
++fproperty
++D
++Enforce property syntax
++
++frelease
++D
++Compile release version
++
++fsplit-dynamic-arrays
++D Var(flag_split_darrays)
++Split dynamic arrays into length and pointer when passing to functions
++
++funittest
++D
++Compile in unittest code
++
++fversion=
++D Joined RejectNegative
++-fversion=<level|ident> Compile in version code >= <level> or identified by <ident>
++
++fXf=
++D Joined RejectNegative
++-fXf=<filename> Write JSON file to <filename>
++
++imultilib
++D Joined Separate
++-imultilib <dir>	Set <dir> to be the multilib include subdirectory
++
++iprefix
++D Joined Separate
++-iprefix <path>	Specify <path> as a prefix for next two options
++
++isysroot
++D Joined Separate
++-isysroot <dir>	Set <dir> to be the system root directory
++
++isystem
++D Joined Separate
++-isystem <dir>	Add <dir> to the start of the system include path
++
++I
++D Joined Separate
++-I <dir>	Add <dir> to the end of the main include path
++
++J
++D Joined Separate
++-J<directory>	Put MODULE files in 'directory'
++
++nophoboslib
++Driver
++Do not link the standard D library in the compilation
++
++nostdinc
++D
++Do not search standard system include directories (those specified with -isystem will still be used)
++
++static-libphobos
++Driver
++Link the standard D library statically in the compilation
++
++Wall
++D
++; Documented in c.opt
++
++Wcast-result
++D Warning Var(warn_cast_result)
++Warn about casts that will produce a null or nil result
++
++Wdeprecated
++D
++; Documented in c.opt
++
++Werror
++D
++; Documented in common.opt
++
++Wunknown-pragmas
++D
++; Documented in c.opt
++
--- gcc-6-6.4.0.orig/debian/patches/gcc-default-format-security.diff
+++ gcc-6-6.4.0/debian/patches/gcc-default-format-security.diff
@@ -0,0 +1,39 @@
+# DP: Turn on -Wformat -Wformat-security by  default for C, C++, ObjC, ObjC++.
+
+Index: b/src/gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -3799,6 +3799,11 @@ included in @option{-Wformat-nonliteral}
+ If @option{-Wformat} is specified, also warn if the format string
+ requires an unsigned argument and the argument is signed and vice versa.
+ 
++NOTE: In Ubuntu 8.10 and later versions this option is enabled by default
++for C, C++, ObjC, ObjC++.  To disable, use @option{-Wno-format-security},
++or disable all format warnings with @option{-Wformat=0}.  To make format
++security warnings fatal, specify @option{-Werror=format-security}.
++
+ @item -Wformat-y2k
+ @opindex Wformat-y2k
+ @opindex Wno-format-y2k
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -858,11 +858,14 @@ proper position among the other output f
+ #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G"
+ #endif
+ 
++/* no separate spec, just shove it into the ssp default spec */
++#define FORMAT_SECURITY_SPEC "%{!Wformat:%{!Wformat=2:%{!Wformat=0:%{!Wall:-Wformat} %{!Wno-format-security:-Wformat-security}}}}"
++
+ #ifndef SSP_DEFAULT_SPEC
+ #ifdef TARGET_LIBC_PROVIDES_SSP
+-#define SSP_DEFAULT_SPEC "%{!fno-stack-protector:%{!fstack-protector-all:%{!ffreestanding:%{!nostdlib:-fstack-protector}}}}"
++#define SSP_DEFAULT_SPEC "%{!fno-stack-protector:%{!fstack-protector-all:%{!ffreestanding:%{!nostdlib:-fstack-protector}}}} " FORMAT_SECURITY_SPEC
+ #else
+-#define SSP_DEFAULT_SPEC ""
++#define SSP_DEFAULT_SPEC FORMAT_SECURITY_SPEC
+ #endif
+ #endif
+ 
--- gcc-6-6.4.0.orig/debian/patches/gcc-default-fortify-source.diff
+++ gcc-6-6.4.0/debian/patches/gcc-default-fortify-source.diff
@@ -0,0 +1,40 @@
+# DP: Turn on -D_FORTIFY_SOURCE=2 by default for C, C++, ObjC, ObjC++,
+# DP: if the optimization level is > 0
+
+---
+ gcc/doc/invoke.texi          |    6 ++++++
+ gcc/c-family/c-cppbuiltin.c  |    3 +
+ 2 files changed, 9 insertions(+), 0 deletions(-)
+
+Index: b/src/gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -7840,6 +7840,12 @@ also turns on the following optimization
+ Please note the warning under @option{-fgcse} about
+ invoking @option{-O2} on programs that use computed gotos.
+ 
++NOTE: In Ubuntu 8.10 and later versions, @option{-D_FORTIFY_SOURCE=2} is
++set by default, and is activated when @option{-O} is set to 2 or higher.
++This enables additional compile-time and run-time checks for several libc
++functions.  To disable, specify either @option{-U_FORTIFY_SOURCE} or
++@option{-D_FORTIFY_SOURCE=0}.
++
+ @item -O3
+ @opindex O3
+ Optimize yet more.  @option{-O3} turns on all optimizations specified
+Index: b/src/gcc/c-family/c-cppbuiltin.c
+===================================================================
+--- a/src/gcc/c-family/c-cppbuiltin.c
++++ b/src/gcc/c-family/c-cppbuiltin.c
+@@ -1176,6 +1176,10 @@ c_cpp_builtins (cpp_reader *pfile)
+   builtin_define_with_value ("__REGISTER_PREFIX__", REGISTER_PREFIX, 0);
+   builtin_define_with_value ("__USER_LABEL_PREFIX__", user_label_prefix, 0);
+ 
++  /* Fortify Source enabled by default for optimization levels > 0 */
++  if (optimize)
++    builtin_define_with_int_value ("_FORTIFY_SOURCE", 2);
++
+   /* Misc.  */
+   if (flag_gnu89_inline)
+     cpp_define (pfile, "__GNUC_GNU_INLINE__");
--- gcc-6-6.4.0.orig/debian/patches/gcc-default-relro.diff
+++ gcc-6-6.4.0/debian/patches/gcc-default-relro.diff
@@ -0,0 +1,33 @@
+# DP: Turn on -Wl,-z,relro by default.
+
+---
+ gcc/doc/invoke.texi |    3 +++
+ gcc/gcc.c           |    1 +
+ 2 files changed, 4 insertions(+), 0 deletions(-)
+
+Index: b/src/gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -11638,6 +11638,9 @@ For example, @option{-Wl,-Map,output.map
+ linker.  When using the GNU linker, you can also get the same effect with
+ @option{-Wl,-Map=output.map}.
+ 
++NOTE: In Ubuntu 8.10 and later versions, for LDFLAGS, the option
++@option{-Wl,-z,relro} is used.  To disable, use @option{-Wl,-z,norelro}.
++
+ @item -u @var{symbol}
+ @opindex u
+ Pretend the symbol @var{symbol} is undefined, to force linking of
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -1027,6 +1027,7 @@ proper position among the other output f
+    "%{flto|flto=*:%<fcompare-debug*} \
+     %{flto} %{fno-lto} %{flto=*} %l " LINK_PIE_SPEC \
+    "%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \
++   "-z relro " \
+    "%X %{o*} %{e*} %{N} %{n} %{r}\
+     %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!nostartfiles:%S}} \
+     %{static:} %{L*} %(mfwrap) %(link_libgcc) " \
--- gcc-6-6.4.0.orig/debian/patches/gcc-default-ssp-strong.diff
+++ gcc-6-6.4.0/debian/patches/gcc-default-ssp-strong.diff
@@ -0,0 +1,59 @@
+# DP: Default to -fstack-protector-strong starting with Ubuntu 14.10.
+
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -863,7 +863,7 @@ proper position among the other output f
+ 
+ #ifndef SSP_DEFAULT_SPEC
+ #ifdef TARGET_LIBC_PROVIDES_SSP
+-#define SSP_DEFAULT_SPEC "%{!fno-stack-protector:%{!fstack-protector-all:%{!ffreestanding:%{!nostdlib:-fstack-protector}}}} " FORMAT_SECURITY_SPEC
++#define SSP_DEFAULT_SPEC "%{!fno-stack-protector:%{!fstack-protector-all:%{!ffreestanding:%{!nostdlib:%{!fstack-protector:-fstack-protector-strong}}}}} " FORMAT_SECURITY_SPEC
+ #else
+ #define SSP_DEFAULT_SPEC FORMAT_SECURITY_SPEC
+ #endif
+Index: b/src/gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -9771,6 +9771,11 @@ branch target registers within any basic
+ Optimize the prologue of variadic argument functions with respect to usage of
+ those arguments.
+ 
++NOTE: In Ubuntu 14.10 and later versions,
++@option{-fstack-protector-strong} is enabled by default for C,
++C++, ObjC, ObjC++, if none of @option{-fno-stack-protector},
++@option{-nostdlib}, nor @option{-ffreestanding} are found.
++
+ @item -fsection-anchors
+ @opindex fsection-anchors
+ Try to reduce the number of symbolic address calculations by using
+@@ -10351,13 +10356,13 @@ value of a shared integer constant.  The
+ The minimum size of buffers (i.e.@: arrays) that receive stack smashing
+ protection when @option{-fstack-protection} is used.
+ 
++This default before Ubuntu 10.10 was "8". Currently it is "4", to increase
++the number of functions protected by the stack protector.
++
+ @item min-size-for-stack-sharing
+ The minimum size of variables taking part in stack slot sharing when not
+ optimizing. The default value is 32.
+ 
+-This default before Ubuntu 10.10 was "8". Currently it is "4", to increase
+-the number of functions protected by the stack protector.
+-
+ @item max-jump-thread-duplication-stmts
+ Maximum number of statements allowed in a block that needs to be
+ duplicated when threading jumps.
+@@ -11276,10 +11281,6 @@ functions with buffers larger than 8 byt
+ when a function is entered and then checked when the function exits.
+ If a guard check fails, an error message is printed and the program exits.
+ 
+-NOTE: In Ubuntu 6.10 and later versions this option is enabled by default
+-for C, C++, ObjC, ObjC++, if none of @option{-fno-stack-protector},
+-@option{-nostdlib}, nor @option{-ffreestanding} are found.
+-
+ @item -fstack-protector-all
+ @opindex fstack-protector-all
+ Like @option{-fstack-protector} except that all functions are protected.
--- gcc-6-6.4.0.orig/debian/patches/gcc-default-ssp.diff
+++ gcc-6-6.4.0/debian/patches/gcc-default-ssp.diff
@@ -0,0 +1,214 @@
+# DP: Turn on -fstack-protector by default for C, C++, ObjC, ObjC++.
+# DP: Build libgcc using -fno-stack-protector.
+
+---
+ gcc/Makefile.in        |    2 ++
+ gcc/cp/lang-specs.h    |    6 +++---
+ gcc/doc/invoke.texi    |    4 ++++
+ gcc/gcc.c              |   18 ++++++++++++++----
+ gcc/objc/lang-specs.h  |   10 +++++-----
+ gcc/objcp/lang-specs.h |    8 ++++----
+ 6 files changed, 32 insertions(+), 16 deletions(-)
+
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -858,6 +858,14 @@ proper position among the other output f
+ #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G"
+ #endif
+ 
++#ifndef SSP_DEFAULT_SPEC
++#ifdef TARGET_LIBC_PROVIDES_SSP
++#define SSP_DEFAULT_SPEC "%{!fno-stack-protector:%{!fstack-protector-all:%{!ffreestanding:%{!nostdlib:-fstack-protector}}}}"
++#else
++#define SSP_DEFAULT_SPEC ""
++#endif
++#endif
++
+ #ifndef LINK_SSP_SPEC
+ #ifdef TARGET_LIBC_PROVIDES_SSP
+ #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
+@@ -1057,6 +1065,7 @@ static const char *cc1_spec = CC1_SPEC;
+ static const char *cc1plus_spec = CC1PLUS_SPEC;
+ static const char *link_gcc_c_sequence_spec = LINK_GCC_C_SEQUENCE_SPEC;
+ static const char *link_ssp_spec = LINK_SSP_SPEC;
++static const char *ssp_default_spec = SSP_DEFAULT_SPEC;
+ static const char *asm_spec = ASM_SPEC;
+ static const char *asm_final_spec = ASM_FINAL_SPEC;
+ static const char *link_spec = LINK_SPEC;
+@@ -1112,7 +1121,7 @@ static const char *cpp_unique_options =
+ static const char *cpp_options =
+ "%(cpp_unique_options) %1 %{m*} %{std*&ansi&trigraphs} %{W*&pedantic*} %{w}\
+  %{f*} %{g*:%{!g0:%{g*} %{!fno-working-directory:-fworking-directory}}} %{O*}\
+- %{undef} %{save-temps*:-fpch-preprocess}";
++ %{undef} %{save-temps*:-fpch-preprocess} %(ssp_default)";
+ 
+ /* This contains cpp options which are not passed when the preprocessor
+    output will be used by another program.  */
+@@ -1301,9 +1310,9 @@ static const struct compiler default_com
+       %{save-temps*|traditional-cpp|no-integrated-cpp:%(trad_capable_cpp) \
+ 	  %(cpp_options) -o %{save-temps*:%b.i} %{!save-temps*:%g.i} \n\
+ 	    cc1 -fpreprocessed %{save-temps*:%b.i} %{!save-temps*:%g.i} \
+-	  %(cc1_options)}\
++	  %(cc1_options) %(ssp_default)}\
+       %{!save-temps*:%{!traditional-cpp:%{!no-integrated-cpp:\
+-	  cc1 %(cpp_unique_options) %(cc1_options)}}}\
++	  cc1 %(cpp_unique_options) %(cc1_options) %(ssp_default)}}}\
+       %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 1},
+   {"-",
+    "%{!E:%e-E or -x required when input is from standard input}\
+@@ -1328,7 +1337,7 @@ static const struct compiler default_com
+ 					   %W{o*:--output-pch=%*}}%V}}}}}}}", 0, 0, 0},
+   {".i", "@cpp-output", 0, 0, 0},
+   {"@cpp-output",
+-   "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %(cc1_options) %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
++   "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %(cc1_options) %(ssp_default) %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+   {".s", "@assembler", 0, 0, 0},
+   {"@assembler",
+    "%{!M:%{!MM:%{!E:%{!S:as %(asm_debug) %(asm_options) %i %A }}}}", 0, 0, 0},
+@@ -1560,6 +1569,7 @@ static struct spec_list static_specs[] =
+   INIT_STATIC_SPEC ("cc1plus",			&cc1plus_spec),
+   INIT_STATIC_SPEC ("link_gcc_c_sequence",	&link_gcc_c_sequence_spec),
+   INIT_STATIC_SPEC ("link_ssp",			&link_ssp_spec),
++  INIT_STATIC_SPEC ("ssp_default",		&ssp_default_spec),
+   INIT_STATIC_SPEC ("endfile",			&endfile_spec),
+   INIT_STATIC_SPEC ("link",			&link_spec),
+   INIT_STATIC_SPEC ("lib",			&lib_spec),
+Index: b/src/gcc/cp/lang-specs.h
+===================================================================
+--- a/src/gcc/cp/lang-specs.h
++++ b/src/gcc/cp/lang-specs.h
+@@ -46,7 +46,7 @@ along with GCC; see the file COPYING3.
+ 		%(cpp_options) %2 -o %{save-temps*:%b.ii} %{!save-temps*:%g.ii} \n}\
+       cc1plus %{save-temps*|no-integrated-cpp:-fpreprocessed %{save-temps*:%b.ii} %{!save-temps*:%g.ii}}\
+ 	      %{!save-temps*:%{!no-integrated-cpp:%(cpp_unique_options)}}\
+-	%(cc1_options) %2\
++	%(cc1_options) %(ssp_default) %2\
+ 	%{!fsyntax-only:-o %g.s \
+ 	    %{!fdump-ada-spec*:%{!o*:--output-pch=%i.gch}\
+ 			       %W{o*:--output-pch=%*}}%V}}}}",
+@@ -58,11 +58,11 @@ along with GCC; see the file COPYING3.
+ 		%(cpp_options) %2 -o %{save-temps*:%b.ii} %{!save-temps*:%g.ii} \n}\
+       cc1plus %{save-temps*|no-integrated-cpp:-fpreprocessed %{save-temps*:%b.ii} %{!save-temps*:%g.ii}}\
+ 	      %{!save-temps*:%{!no-integrated-cpp:%(cpp_unique_options)}}\
+-	%(cc1_options) %2\
++	%(cc1_options) %(ssp_default) %2\
+        %{!fsyntax-only:%(invoke_as)}}}}",
+      CPLUSPLUS_CPP_SPEC, 0, 0},
+   {".ii", "@c++-cpp-output", 0, 0, 0},
+   {"@c++-cpp-output",
+    "%{!M:%{!MM:%{!E:\
+-    cc1plus -fpreprocessed %i %(cc1_options) %2\
++    cc1plus -fpreprocessed %i %(cc1_options) %(ssp_default) %2\
+     %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+Index: b/src/gcc/params.def
+===================================================================
+--- a/src/gcc/params.def
++++ b/src/gcc/params.def
+@@ -673,7 +673,7 @@ DEFPARAM (PARAM_INTEGER_SHARE_LIMIT,
+ DEFPARAM (PARAM_SSP_BUFFER_SIZE,
+ 	  "ssp-buffer-size",
+ 	  "The lower bound for a buffer to be considered for stack smashing protection.",
+-	  8, 1, 0)
++	  4, 1, 0)
+ 
+ DEFPARAM (PARAM_MIN_SIZE_FOR_STACK_SHARING,
+ 	  "min-size-for-stack-sharing",
+Index: b/src/gcc/objc/lang-specs.h
+===================================================================
+--- a/src/gcc/objc/lang-specs.h
++++ b/src/gcc/objc/lang-specs.h
+@@ -29,9 +29,9 @@ along with GCC; see the file COPYING3.
+ 	%{traditional|traditional-cpp:\
+ %eGNU Objective C no longer supports traditional compilation}\
+ 	%{save-temps*|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps*:%b.mi} %{!save-temps*:%g.mi} \n\
+-	    cc1obj -fpreprocessed %{save-temps*:%b.mi} %{!save-temps*:%g.mi} %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}\
++	    cc1obj -fpreprocessed %{save-temps*:%b.mi} %{!save-temps*:%g.mi} %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}}\
+ 	%{!save-temps*:%{!no-integrated-cpp:\
+-	    cc1obj %(cpp_unique_options) %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}}\
++	    cc1obj %(cpp_unique_options) %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}}}\
+         %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+   {"@objective-c-header",
+      "%{E|M|MM:cc1obj -E %{traditional|traditional-cpp:-traditional-cpp}\
+@@ -40,18 +40,18 @@ along with GCC; see the file COPYING3.
+ 	%{traditional|traditional-cpp:\
+ %eGNU Objective C no longer supports traditional compilation}\
+ 	%{save-temps*|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps*:%b.mi} %{!save-temps*:%g.mi} \n\
+-	    cc1obj -fpreprocessed %b.mi %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\
++	    cc1obj -fpreprocessed %b.mi %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}\
+                         -o %g.s %{!o*:--output-pch=%i.gch}\
+                         %W{o*:--output-pch=%*}%V}\
+ 	%{!save-temps*:%{!no-integrated-cpp:\
+-	    cc1obj %(cpp_unique_options) %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\
++	    cc1obj %(cpp_unique_options) %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}\
+                         -o %g.s %{!o*:--output-pch=%i.gch}\
+                         %W{o*:--output-pch=%*}%V}}}}}", 0, 0, 0},
+   {".mi", "@objective-c-cpp-output", 0, 0, 0},
+   {"@objective-c-cpp-output",
+-     "%{!M:%{!MM:%{!E:cc1obj -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\
++     "%{!M:%{!MM:%{!E:cc1obj -fpreprocessed %i %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}\
+ 			     %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+   {"@objc-cpp-output",
+       "%nobjc-cpp-output is deprecated; please use objective-c-cpp-output instead\n\
+-       %{!M:%{!MM:%{!E:cc1obj -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\
++       %{!M:%{!MM:%{!E:cc1obj -fpreprocessed %i %(cc1_options) %(ssp_default) %{print-objc-runtime-info} %{gen-decls}\
+ 			     %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+Index: b/src/gcc/objcp/lang-specs.h
+===================================================================
+--- a/src/gcc/objcp/lang-specs.h
++++ b/src/gcc/objcp/lang-specs.h
+@@ -36,7 +36,7 @@ along with GCC; see the file COPYING3.
+ 		%(cpp_options) %2 -o %{save-temps*:%b.mii} %{!save-temps*:%g.mii} \n}\
+       cc1objplus %{save-temps*|no-integrated-cpp:-fpreprocessed %{save-temps*:%b.mii} %{!save-temps*:%g.mii}}\
+ 	      %{!save-temps*:%{!no-integrated-cpp:%(cpp_unique_options)}}\
+-	%(cc1_options) %2\
++	%(cc1_options) %(ssp_default) %2\
+         -o %g.s %{!o*:--output-pch=%i.gch} %W{o*:--output-pch=%*}%V}}}",
+      CPLUSPLUS_CPP_SPEC, 0, 0},
+   {"@objective-c++",
+@@ -46,16 +46,16 @@ along with GCC; see the file COPYING3.
+ 		%(cpp_options) %2 -o %{save-temps*:%b.mii} %{!save-temps*:%g.mii} \n}\
+       cc1objplus %{save-temps*|no-integrated-cpp:-fpreprocessed %{save-temps*:%b.mii} %{!save-temps*:%g.mii}}\
+ 	      %{!save-temps*:%{!no-integrated-cpp:%(cpp_unique_options)}}\
+-	%(cc1_options) %2\
++	%(cc1_options) %(ssp_default) %2\
+        %{!fsyntax-only:%(invoke_as)}}}}",
+      CPLUSPLUS_CPP_SPEC, 0, 0},
+   {".mii", "@objective-c++-cpp-output", 0, 0, 0},
+   {"@objective-c++-cpp-output",
+    "%{!M:%{!MM:%{!E:\
+-    cc1objplus -fpreprocessed %i %(cc1_options) %2\
++    cc1objplus -fpreprocessed %i %(cc1_options) %(ssp_default) %2\
+     %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+   {"@objc++-cpp-output",
+    "%nobjc++-cpp-output is deprecated; please use objective-c++-cpp-output instead\n\
+     %{!M:%{!MM:%{!E:\
+-    cc1objplus -fpreprocessed %i %(cc1_options) %2\
++    cc1objplus -fpreprocessed %i %(cc1_options) %(ssp_default) %2\
+     %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
+Index: b/src/gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -10350,6 +10350,9 @@ protection when @option{-fstack-protecti
+ The minimum size of variables taking part in stack slot sharing when not
+ optimizing. The default value is 32.
+ 
++This default before Ubuntu 10.10 was "8". Currently it is "4", to increase
++the number of functions protected by the stack protector.
++
+ @item max-jump-thread-duplication-stmts
+ Maximum number of statements allowed in a block that needs to be
+ duplicated when threading jumps.
+@@ -11268,6 +11271,10 @@ functions with buffers larger than 8 byt
+ when a function is entered and then checked when the function exits.
+ If a guard check fails, an error message is printed and the program exits.
+ 
++NOTE: In Ubuntu 6.10 and later versions this option is enabled by default
++for C, C++, ObjC, ObjC++, if none of @option{-fno-stack-protector},
++@option{-nostdlib}, nor @option{-ffreestanding} are found.
++
+ @item -fstack-protector-all
+ @opindex fstack-protector-all
+ Like @option{-fstack-protector} except that all functions are protected.
--- gcc-6-6.4.0.orig/debian/patches/gcc-driver-extra-langs-linaro.diff
+++ gcc-6-6.4.0/debian/patches/gcc-driver-extra-langs-linaro.diff
@@ -0,0 +1,22 @@
+# DP: Add options and specs for languages that are not built from a source
+# DP: (but built from separate sources).
+
+---
+ gcc/Makefile.in |    4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -527,8 +527,8 @@ xm_include_list=@xm_include_list@
+ xm_defines=@xm_defines@
+ lang_checks=
+ lang_checks_parallelized=
+-lang_opt_files=@lang_opt_files@ $(srcdir)/c-family/c.opt $(srcdir)/common.opt
+-lang_specs_files=@lang_specs_files@
++lang_opt_files=$(sort @lang_opt_files@ $(srcdir)/c-family/c.opt $(srcdir)/common.opt $(foreach lang,$(subst ada,ada/gcc-interface,$(debian_extra_langs)),$(srcdir)/$(lang)/lang.opt))
++lang_specs_files=$(sort @lang_specs_files@ $(foreach lang,$(subst ada,ada/gcc-interface,$(debian_extra_langs)),$(srcdir)/$(lang)/lang-specs.h))
+ lang_tree_files=@lang_tree_files@
+ target_cpu_default=@target_cpu_default@
+ OBJC_BOEHM_GC=@objc_boehm_gc@
--- gcc-6-6.4.0.orig/debian/patches/gcc-driver-extra-langs.diff
+++ gcc-6-6.4.0/debian/patches/gcc-driver-extra-langs.diff
@@ -0,0 +1,22 @@
+# DP: Add options and specs for languages that are not built from a source
+# DP: (but built from separate sources).
+
+---
+ gcc/Makefile.in |    4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -542,8 +542,8 @@ xm_include_list=@xm_include_list@
+ xm_defines=@xm_defines@
+ lang_checks=
+ lang_checks_parallelized=
+-lang_opt_files=@lang_opt_files@ $(srcdir)/c-family/c.opt $(srcdir)/common.opt
+-lang_specs_files=@lang_specs_files@
++lang_opt_files=$(sort @lang_opt_files@ $(srcdir)/c-family/c.opt $(srcdir)/common.opt $(foreach lang,$(subst ada,ada/gcc-interface,$(debian_extra_langs)),$(srcdir)/$(lang)/lang.opt))
++lang_specs_files=$(sort @lang_specs_files@ $(foreach lang,$(subst ada,ada/gcc-interface,$(debian_extra_langs)),$(srcdir)/$(lang)/lang-specs.h))
+ lang_tree_files=@lang_tree_files@
+ target_cpu_default=@target_cpu_default@
+ OBJC_BOEHM_GC=@objc_boehm_gc@
--- gcc-6-6.4.0.orig/debian/patches/gcc-fuse-ld-lld-doc.diff
+++ gcc-6-6.4.0/debian/patches/gcc-fuse-ld-lld-doc.diff
@@ -0,0 +1,17 @@
+# DP: Allow to use lld with -fuse-ld=ld.lld (documentation)
+
+Index: gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi	(revision 246158)
++++ a/src/gcc/doc/invoke.texi	(working copy)
+@@ -10501,6 +10501,10 @@
+ @opindex fuse-ld=gold
+ Use the @command{gold} linker instead of the default linker.
+ 
++@item -fuse-ld=lld
++@opindex fuse-ld=lld
++Use the LLVM @command{lld} linker instead of the default linker.
++
+ @cindex Libraries
+ @item -l@var{library}
+ @itemx -l @var{library}
--- gcc-6-6.4.0.orig/debian/patches/gcc-fuse-ld-lld.diff
+++ gcc-6-6.4.0/debian/patches/gcc-fuse-ld-lld.diff
@@ -0,0 +1,83 @@
+# DP: Allow to use lld with -fuse-ld=ld.lld
+
+Index: gcc/collect2.c
+===================================================================
+--- a/src/gcc/collect2.c	(revision 246158)
++++ a/src/gcc/collect2.c	(working copy)
+@@ -831,6 +831,7 @@
+       USE_PLUGIN_LD,
+       USE_GOLD_LD,
+       USE_BFD_LD,
++      USE_LLD_LD,
+       USE_LD_MAX
+     } selected_linker = USE_DEFAULT_LD;
+   static const char *const ld_suffixes[USE_LD_MAX] =
+@@ -838,7 +839,8 @@
+       "ld",
+       PLUGIN_LD_SUFFIX,
+       "ld.gold",
+-      "ld.bfd"
++      "ld.bfd",
++      "ld.lld"
+     };
+   static const char *const real_ld_suffix = "real-ld";
+   static const char *const collect_ld_suffix = "collect-ld";
+@@ -1004,6 +1006,8 @@
+ 	  selected_linker = USE_BFD_LD;
+ 	else if (strcmp (argv[i], "-fuse-ld=gold") == 0)
+ 	  selected_linker = USE_GOLD_LD;
++  else if (strcmp (argv[i], "-fuse-ld=lld") == 0)
++    selected_linker = USE_LLD_LD;
+ 
+ #ifdef COLLECT_EXPORT_LIST
+ 	/* These flags are position independent, although their order
+@@ -1093,7 +1097,8 @@
+   /* Maybe we know the right file to use (if not cross).  */
+   ld_file_name = 0;
+ #ifdef DEFAULT_LINKER
+-  if (selected_linker == USE_BFD_LD || selected_linker == USE_GOLD_LD)
++  if (selected_linker == USE_BFD_LD || selected_linker == USE_GOLD_LD ||
++      selected_linker == USE_LLD_LD)
+     {
+       char *linker_name;
+ # ifdef HOST_EXECUTABLE_SUFFIX
+@@ -1307,7 +1312,7 @@
+ 	      else if (!use_collect_ld
+ 		       && strncmp (arg, "-fuse-ld=", 9) == 0)
+ 		{
+-		  /* Do not pass -fuse-ld={bfd|gold} to the linker. */
++		  /* Do not pass -fuse-ld={bfd|gold|lld} to the linker. */
+ 		  ld1--;
+ 		  ld2--;
+ 		}
+Index: gcc/common.opt
+===================================================================
+--- a/src/gcc/common.opt	(revision 246158)
++++ a/src/gcc/common.opt	(working copy)
+@@ -2512,9 +2512,13 @@
+ Use the bfd linker instead of the default linker.
+ 
+ fuse-ld=gold
+-Common Driver Negative(fuse-ld=bfd)
++Common Driver Negative(fuse-ld=lld)
+ Use the gold linker instead of the default linker.
+ 
++fuse-ld=lld
++Common Driver Negative(fuse-ld=bfd)
++Use the lld LLVM linker instead of the default linker.
++
+ fuse-linker-plugin
+ Common Undocumented Var(flag_use_linker_plugin)
+ 
+Index: gcc/opts.c
+===================================================================
+--- a/src/gcc/opts.c	(revision 246158)
++++ a/src/gcc/opts.c	(working copy)
+@@ -2168,6 +2168,7 @@
+ 
+     case OPT_fuse_ld_bfd:
+     case OPT_fuse_ld_gold:
++    case OPT_fuse_ld_lld:
+     case OPT_fuse_linker_plugin:
+       /* No-op. Used by the driver and passed to us because it starts with f.*/
+       break;
--- gcc-6-6.4.0.orig/debian/patches/gcc-gfdl-build.diff
+++ gcc-6-6.4.0/debian/patches/gcc-gfdl-build.diff
@@ -0,0 +1,39 @@
+# DP: Build a dummy s-tm-texi without access to the texinfo sources
+
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -2314,30 +2314,8 @@ s-tm-texi: $(srcdir)/doc/../doc/tm.texi
+ # \r is not portable to Solaris tr, therefore we have a special
+ # case for ASCII.  We use \r for other encodings like EBCDIC.
+ s-tm-texi: build/genhooks$(build_exeext) $(srcdir)/doc/tm.texi.in
+-	$(RUN_GEN) build/genhooks$(build_exeext) -d \
+-			$(srcdir)/doc/tm.texi.in > tmp-tm.texi
+-	case `echo X|tr X '\101'` in \
+-	  A) tr -d '\015' < tmp-tm.texi > tmp2-tm.texi ;; \
+-	  *) tr -d '\r' < tmp-tm.texi > tmp2-tm.texi ;; \
+-	esac
+-	mv tmp2-tm.texi tmp-tm.texi
+-	$(SHELL) $(srcdir)/../move-if-change tmp-tm.texi tm.texi
+-	@if cmp -s $(srcdir)/doc/tm.texi tm.texi; then \
+-	  $(STAMP) $@; \
+-	elif test $(srcdir)/doc/tm.texi -nt $(srcdir)/doc/tm.texi.in \
+-	  && ( test $(srcdir)/doc/tm.texi -nt $(srcdir)/target.def \
+-	    || test $(srcdir)/doc/tm.texi -nt $(srcdir)/c-family/c-target.def \
+-	    || test $(srcdir)/doc/tm.texi -nt $(srcdir)/common/common-target.def \
+-	  ); then \
+-	  echo >&2 ; \
+-	  echo You should edit $(srcdir)/doc/tm.texi.in rather than $(srcdir)/doc/tm.texi . >&2 ; \
+-	  false; \
+-	else \
+-	  echo >&2 ; \
+-	  echo Verify that you have permission to grant a GFDL license for all >&2 ; \
+-	  echo new text in tm.texi, then copy it to $(srcdir)/doc/tm.texi. >&2 ; \
+-	  false; \
+-	fi
++	cat $(srcdir)/doc/tm.texi.in > tmp-tm.texi
++	$(STAMP) $@
+ 
+ gimple-match.c: s-match gimple-match-head.c ; @true
+ generic-match.c: s-match generic-match-head.c ; @true
--- gcc-6-6.4.0.orig/debian/patches/gcc-hash-style-both.diff
+++ gcc-6-6.4.0/debian/patches/gcc-hash-style-both.diff
@@ -0,0 +1,167 @@
+# DP: Link using --hash-style=both (alpha, amd64, armel, armhf, ia64, i386, powerpc, ppc64, s390, sparc)
+
+2006-07-11  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/i386/linux.h (LINK_SPEC): Add --hash-style=both.
+	* config/i386/linux64.h (LINK_SPEC): Likewise.
+	* config/rs6000/sysv4.h (LINK_OS_LINUX_SPEC): Likewise.
+	* config/rs6000/linux64.h (LINK_OS_LINUX_SPEC32,
+	LINK_OS_LINUX_SPEC64): Likewise.
+	* config/s390/linux.h (LINK_SPEC): Likewise.
+	* config/ia64/linux.h (LINK_SPEC): Likewise.
+	* config/sparc/linux.h (LINK_SPEC): Likewise.
+	* config/sparc/linux64.h (LINK_SPEC, LINK_ARCH32_SPEC,
+	LINK_ARCH64_SPEC): Likewise.
+	* config/alpha/linux-elf.h (LINK_SPEC): Likewise.
+
+2009-12-21  Matthias Klose  <doko@ubuntu.com>
+
+	* config/arm/linux-elf.h (LINK_SPEC): Add --hash-style=both.
+
+2012-11-17  Matthias Klose  <doko@ubuntu.com>
+
+	* config/aarch64/aarch64-linux.h (LINK_SPEC): Add --hash-style=both.
+	
+---
+ gcc/config/alpha/linux-elf.h |    2 +-
+ gcc/config/i386/linux.h      |    2 +-
+ gcc/config/i386/linux64.h    |    2 +-
+ gcc/config/ia64/linux.h      |    2 +-
+ gcc/config/rs6000/linux64.h  |    4 ++--
+ gcc/config/rs6000/sysv4.h    |    2 +-
+ gcc/config/s390/linux.h      |    2 +-
+ gcc/config/sparc/linux.h     |    2 +-
+ 8 files changed, 9 insertions(+), 9 deletions(-)
+
+Index: b/src/gcc/config/alpha/linux-elf.h
+===================================================================
+--- a/src/gcc/config/alpha/linux-elf.h
++++ b/src/gcc/config/alpha/linux-elf.h
+@@ -37,7 +37,7 @@
+ 
+ #define ELF_DYNAMIC_LINKER	GNU_USER_DYNAMIC_LINKER
+ 
+-#define LINK_SPEC "-m elf64alpha %{G*} %{relax:-relax}		\
++#define LINK_SPEC "-m elf64alpha --hash-style=both %{G*} %{relax:-relax}	\
+   %{O*:-O3} %{!O*:-O1}						\
+   %{shared:-shared}						\
+   %{!shared:							\
+Index: b/src/gcc/config/ia64/linux.h
+===================================================================
+--- a/src/gcc/config/ia64/linux.h
++++ b/src/gcc/config/ia64/linux.h
+@@ -58,7 +58,7 @@
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
+ 
+ #undef LINK_SPEC
+-#define LINK_SPEC "\
++#define LINK_SPEC " --hash-style=both \
+   %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/rs6000/linux64.h
+===================================================================
+--- a/src/gcc/config/rs6000/linux64.h
++++ b/src/gcc/config/rs6000/linux64.h
+@@ -385,11 +385,11 @@
+ 					   " -m elf64ppc")
+ #endif
+ 
+-#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " --hash-style=both %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}}"
+ 
+-#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " --hash-style=both %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "}}"
+ 
+Index: b/src/gcc/config/rs6000/sysv4.h
+===================================================================
+--- a/src/gcc/config/rs6000/sysv4.h
++++ b/src/gcc/config/rs6000/sysv4.h
+@@ -788,7 +788,7 @@
+ #define GNU_USER_DYNAMIC_LINKER \
+   CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
+ 
+-#define LINK_OS_LINUX_SPEC "-m elf32ppclinux %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC "-m elf32ppclinux --hash-style=both %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}"
+ 
+Index: b/src/gcc/config/s390/linux.h
+===================================================================
+--- a/src/gcc/config/s390/linux.h
++++ b/src/gcc/config/s390/linux.h
+@@ -65,7 +65,7 @@
+ 
+ #undef  LINK_SPEC
+ #define LINK_SPEC \
+-  "%{m31:-m elf_s390}%{m64:-m elf64_s390} \
++  "%{m31:-m elf_s390}%{m64:-m elf64_s390} --hash-style=both \
+    %{shared:-shared} \
+    %{!shared: \
+       %{static:-static} \
+Index: b/src/gcc/config/sparc/linux.h
+===================================================================
+--- a/src/gcc/config/sparc/linux.h
++++ b/src/gcc/config/sparc/linux.h
+@@ -86,7 +86,7 @@
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+ 
+ #undef  LINK_SPEC
+-#define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
++#define LINK_SPEC "-m elf32_sparc --hash-style=both %{shared:-shared} \
+   %{!mno-relax:%{!r:-relax}} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/arm/linux-elf.h
+===================================================================
+--- a/src/gcc/config/arm/linux-elf.h
++++ b/src/gcc/config/arm/linux-elf.h
+@@ -67,6 +67,7 @@
+      %{rdynamic:-export-dynamic} \
+      -dynamic-linker " GNU_USER_DYNAMIC_LINKER "} \
+    -X \
++   --hash-style=both \
+    %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
+    SUBTARGET_EXTRA_LINK_SPEC
+ 
+Index: b/src/gcc/config/i386/gnu-user.h
+===================================================================
+--- a/src/gcc/config/i386/gnu-user.h
++++ b/src/gcc/config/i386/gnu-user.h
+@@ -74,7 +74,7 @@
+   { "link_emulation", GNU_USER_LINK_EMULATION },\
+   { "dynamic_linker", GNU_USER_DYNAMIC_LINKER }
+ 
+-#define GNU_USER_TARGET_LINK_SPEC "-m %(link_emulation) %{shared:-shared} \
++#define GNU_USER_TARGET_LINK_SPEC "-m %(link_emulation) --hash-style=both %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+       %{rdynamic:-export-dynamic} \
+Index: b/src/gcc/config/i386/gnu-user64.h
+===================================================================
+--- a/src/gcc/config/i386/gnu-user64.h
++++ b/src/gcc/config/i386/gnu-user64.h
+@@ -56,6 +56,7 @@
+                   "%{" SPEC_64 ":-m " GNU_USER_LINK_EMULATION64 "} \
+                    %{" SPEC_32 ":-m " GNU_USER_LINK_EMULATION32 "} \
+                    %{" SPEC_X32 ":-m " GNU_USER_LINK_EMULATIONX32 "} \
++  --hash-style=both \
+   %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/aarch64/aarch64-linux.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64-linux.h
++++ b/src/gcc/config/aarch64/aarch64-linux.h
+@@ -24,6 +24,7 @@
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64.so.1"
+ 
+ #define LINUX_TARGET_LINK_SPEC  "%{h*}		\
++   --hash-style=both				\
+    %{static:-Bstatic}				\
+    %{shared:-shared}				\
+    %{symbolic:-Bsymbolic}			\
--- gcc-6-6.4.0.orig/debian/patches/gcc-hash-style-gnu.diff
+++ gcc-6-6.4.0/debian/patches/gcc-hash-style-gnu.diff
@@ -0,0 +1,169 @@
+# DP: Link using --hash-style=gnu (aarch64, alpha, amd64, armel, armhf, ia64,
+# DP: i386, powerpc, ppc64, s390, sparc)
+
+2006-07-11  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/i386/linux.h (LINK_SPEC): Add --hash-style=gnu.
+	* config/i386/linux64.h (LINK_SPEC): Likewise.
+	* config/rs6000/sysv4.h (LINK_OS_LINUX_SPEC): Likewise.
+	* config/rs6000/linux64.h (LINK_OS_LINUX_SPEC32,
+	LINK_OS_LINUX_SPEC64): Likewise.
+	* config/s390/linux.h (LINK_SPEC): Likewise.
+	* config/ia64/linux.h (LINK_SPEC): Likewise.
+	* config/sparc/linux.h (LINK_SPEC): Likewise.
+	* config/sparc/linux64.h (LINK_SPEC, LINK_ARCH32_SPEC,
+	LINK_ARCH64_SPEC): Likewise.
+	* config/alpha/linux-elf.h (LINK_SPEC): Likewise.
+
+2009-12-21  Matthias Klose  <doko@ubuntu.com>
+
+	* config/arm/linux-elf.h (LINK_SPEC): Add --hash-style=gnu.
+
+2012-11-17  Matthias Klose  <doko@ubuntu.com>
+
+	* config/aarch64/aarch64-linux.h (LINK_SPEC): Add --hash-style=gnu.
+	
+---
+ gcc/config/alpha/linux-elf.h |    2 +-
+ gcc/config/i386/linux.h      |    2 +-
+ gcc/config/i386/linux64.h    |    2 +-
+ gcc/config/ia64/linux.h      |    2 +-
+ gcc/config/rs6000/linux64.h  |    4 ++--
+ gcc/config/rs6000/sysv4.h    |    2 +-
+ gcc/config/s390/linux.h      |    2 +-
+ gcc/config/sparc/linux.h     |    2 +-
+ 8 files changed, 9 insertions(+), 9 deletions(-)
+
+Index: b/src/gcc/config/alpha/linux-elf.h
+===================================================================
+--- a/src/gcc/config/alpha/linux-elf.h
++++ b/src/gcc/config/alpha/linux-elf.h
+@@ -37,7 +37,7 @@ along with GCC; see the file COPYING3.
+ 
+ #define ELF_DYNAMIC_LINKER	GNU_USER_DYNAMIC_LINKER
+ 
+-#define LINK_SPEC "-m elf64alpha %{G*} %{relax:-relax}		\
++#define LINK_SPEC "-m elf64alpha --hash-style=gnu %{G*} %{relax:-relax}	\
+   %{O*:-O3} %{!O*:-O1}						\
+   %{shared:-shared}						\
+   %{!shared:							\
+Index: b/src/gcc/config/ia64/linux.h
+===================================================================
+--- a/src/gcc/config/ia64/linux.h
++++ b/src/gcc/config/ia64/linux.h
+@@ -58,7 +58,7 @@ do {						\
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
+ 
+ #undef LINK_SPEC
+-#define LINK_SPEC "\
++#define LINK_SPEC " --hash-style=gnu \
+   %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/rs6000/linux64.h
+===================================================================
+--- a/src/gcc/config/rs6000/linux64.h
++++ b/src/gcc/config/rs6000/linux64.h
+@@ -469,12 +469,12 @@ extern int dot_symbols;
+ 					   " -m elf64ppc")
+ #endif
+ 
+-#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " --hash-style=gnu %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}} \
+   %(link_os_extra_spec32)"
+ 
+-#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " --hash-style=gnu %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "}} \
+   %(link_os_extra_spec64)"
+Index: b/src/gcc/config/rs6000/sysv4.h
+===================================================================
+--- a/src/gcc/config/rs6000/sysv4.h
++++ b/src/gcc/config/rs6000/sysv4.h
+@@ -795,7 +795,7 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEF
+   CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, \
+ 			 MUSL_DYNAMIC_LINKER)
+ 
+-#define LINK_OS_LINUX_SPEC "-m elf32ppclinux %{!shared: %{!static: \
++#define LINK_OS_LINUX_SPEC "-m elf32ppclinux --hash-style=gnu %{!shared: %{!static: \
+   %{rdynamic:-export-dynamic} \
+   -dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}"
+ 
+Index: b/src/gcc/config/s390/linux.h
+===================================================================
+--- a/src/gcc/config/s390/linux.h
++++ b/src/gcc/config/s390/linux.h
+@@ -65,7 +65,7 @@ along with GCC; see the file COPYING3.
+ 
+ #undef  LINK_SPEC
+ #define LINK_SPEC \
+-  "%{m31:-m elf_s390}%{m64:-m elf64_s390} \
++  "%{m31:-m elf_s390}%{m64:-m elf64_s390} --hash-style=gnu \
+    %{shared:-shared} \
+    %{!shared: \
+       %{static:-static} \
+Index: b/src/gcc/config/sparc/linux.h
+===================================================================
+--- a/src/gcc/config/sparc/linux.h
++++ b/src/gcc/config/sparc/linux.h
+@@ -86,7 +86,7 @@ extern const char *host_detect_local_cpu
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+ 
+ #undef  LINK_SPEC
+-#define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
++#define LINK_SPEC "-m elf32_sparc --hash-style=gnu %{shared:-shared} \
+   %{!mno-relax:%{!r:-relax}} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/arm/linux-elf.h
+===================================================================
+--- a/src/gcc/config/arm/linux-elf.h
++++ b/src/gcc/config/arm/linux-elf.h
+@@ -72,6 +72,7 @@
+      %{rdynamic:-export-dynamic} \
+      %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} \
+    -X \
++   --hash-style=gnu \
+    %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
+    SUBTARGET_EXTRA_LINK_SPEC
+ 
+Index: b/src/gcc/config/i386/gnu-user.h
+===================================================================
+--- a/src/gcc/config/i386/gnu-user.h
++++ b/src/gcc/config/i386/gnu-user.h
+@@ -74,7 +74,7 @@ along with GCC; see the file COPYING3.
+   { "link_emulation", GNU_USER_LINK_EMULATION },\
+   { "dynamic_linker", GNU_USER_DYNAMIC_LINKER }
+ 
+-#define GNU_USER_TARGET_LINK_SPEC "-m %(link_emulation) %{shared:-shared} \
++#define GNU_USER_TARGET_LINK_SPEC "-m %(link_emulation) --hash-style=gnu %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+       %{rdynamic:-export-dynamic} \
+Index: b/src/gcc/config/i386/gnu-user64.h
+===================================================================
+--- a/src/gcc/config/i386/gnu-user64.h
++++ b/src/gcc/config/i386/gnu-user64.h
+@@ -56,6 +56,7 @@ see the files COPYING3 and COPYING.RUNTI
+                   "%{" SPEC_64 ":-m " GNU_USER_LINK_EMULATION64 "} \
+                    %{" SPEC_32 ":-m " GNU_USER_LINK_EMULATION32 "} \
+                    %{" SPEC_X32 ":-m " GNU_USER_LINK_EMULATIONX32 "} \
++  --hash-style=gnu \
+   %{shared:-shared} \
+   %{!shared: \
+     %{!static: \
+Index: b/src/gcc/config/aarch64/aarch64-linux.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64-linux.h
++++ b/src/gcc/config/aarch64/aarch64-linux.h
+@@ -35,6 +35,7 @@
+ #define CPP_SPEC "%{pthread:-D_REENTRANT}"
+ 
+ #define LINUX_TARGET_LINK_SPEC  "%{h*}		\
++   --hash-style=gnu				\
+    %{static:-Bstatic}				\
+    %{shared:-shared}				\
+    %{symbolic:-Bsymbolic}			\
--- gcc-6-6.4.0.orig/debian/patches/gcc-ia64-bootstrap-ignore.diff
+++ gcc-6-6.4.0/debian/patches/gcc-ia64-bootstrap-ignore.diff
@@ -0,0 +1,17 @@
+# DP: Ignore bootstrap comparison failure on ia64. Filed upstream as
+# DP: PR middle-end/65874.
+
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -3598,6 +3598,9 @@ fi
+ 
+ compare_exclusions="gcc/cc*-checksum\$(objext) | gcc/ada/*tools/*"
+ case "$target" in
++  ia64-*linux-gnu)
++    compare_exclusions="gcc/cc*-checksum\$(objext) | gcc/ada/*tools/* | gcc/ira.o"
++    ;;
+   hppa*64*-*-hpux*) ;;
+   hppa*-*-hpux*) compare_exclusions="gcc/cc*-checksum\$(objext) | */libgcc/lib2funcs* | gcc/ada/*tools/*" ;;
+   powerpc*-ibm-aix*) compare_exclusions="gcc/cc*-checksum\$(objext) | gcc/ada/*tools/* | *libgomp*\$(objext)" ;;
--- gcc-6-6.4.0.orig/debian/patches/gcc-ice-apport.diff
+++ gcc-6-6.4.0/debian/patches/gcc-ice-apport.diff
@@ -0,0 +1,24 @@
+# DP: Report an ICE to apport (if apport is available
+# DP: and the environment variable GCC_NOAPPORT is not set)
+
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -6870,6 +6870,16 @@ do_report_bug (const char **new_argv, co
+ 	  fflush(stderr);
+ 	  free(cmd);
+ 	}
++      if (!env.get ("GCC_NOAPPORT")
++	  && !access ("/usr/share/apport/gcc_ice_hook", R_OK | X_OK))
++	{
++	  char *cmd = XNEWVEC (char, 50 + strlen (*out_file)
++			       + strlen (new_argv[0]));
++	  sprintf (cmd, "/usr/share/apport/gcc_ice_hook %s %s",
++		   new_argv[0], *out_file);
++	  system (cmd);
++	  free (cmd);
++	}
+       /* Make sure it is not deleted.  */
+       free (*out_file);
+       *out_file = NULL;
--- gcc-6-6.4.0.orig/debian/patches/gcc-ice-dump.diff
+++ gcc-6-6.4.0/debian/patches/gcc-ice-dump.diff
@@ -0,0 +1,41 @@
+# DP: For ICEs, dump the preprocessed source file to stderr
+# DP: when in a distro build environment.
+
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -3143,7 +3143,8 @@ execute (void)
+ 	    /* For ICEs in cc1, cc1obj, cc1plus see if it is
+ 	       reproducible or not.  */
+ 	    const char *p;
+-	    if (flag_report_bug
++	    const char *deb_build_options = env.get("DEB_BUILD_OPTIONS");
++	    if ((flag_report_bug || deb_build_options)
+ 		&& WEXITSTATUS (status) == ICE_EXIT_CODE
+ 		&& i == 0
+ 		&& (p = strrchr (commands[0].argv[0], DIR_SEPARATOR))
+@@ -6852,8 +6853,23 @@ do_report_bug (const char **new_argv, co
+ 
+   if (status == ATTEMPT_STATUS_SUCCESS)
+     {
++      const char *deb_build_options = env.get("DEB_BUILD_OPTIONS");
++
+       fnotice (stderr, "Preprocessed source stored into %s file,"
+ 	       " please attach this to your bugreport.\n", *out_file);
++      if (deb_build_options)
++	{
++	  char *cmd = XNEWVEC (char, 50 + strlen (*out_file));
++
++	  sprintf(cmd, "/usr/bin/awk '{print \"%d:\", $0}' %s >&2", getpid(), *out_file);
++	  fprintf(stderr, "=== BEGIN GCC DUMP ===\n");
++	  fflush(stderr);
++	  system(cmd);
++	  fflush(stderr);
++	  fprintf(stderr, "=== END GCC DUMP ===\n");
++	  fflush(stderr);
++	  free(cmd);
++	}
+       /* Make sure it is not deleted.  */
+       free (*out_file);
+       *out_file = NULL;
--- gcc-6-6.4.0.orig/debian/patches/gcc-linaro-doc.diff
+++ gcc-6-6.4.0/debian/patches/gcc-linaro-doc.diff
@@ -0,0 +1,756 @@
+# DP: Changes for the Linaro 6-2017.11 snapshot (documentation).
+
+--- a/src/gcc/doc/cpp.texi
++++ b/src/gcc/doc/cpp.texi
+@@ -1984,7 +1984,7 @@ by GCC, or a non-GCC compiler that claims to accept the GNU C dialects,
+ you can simply test @code{__GNUC__}.  If you need to write code
+ which depends on a specific version, you must be more careful.  Each
+ time the minor version is increased, the patch level is reset to zero;
+-each time the major version is increased (which happens rarely), the
++each time the major version is increased, the
+ minor version and patch level are reset.  If you wish to use the
+ predefined macros directly in the conditional, you will need to write it
+ like this:
+--- a/src/gcc/doc/extend.texi
++++ b/src/gcc/doc/extend.texi
+@@ -11416,6 +11416,7 @@ instructions, but allow the compiler to schedule those calls.
+ * ARM iWMMXt Built-in Functions::
+ * ARM C Language Extensions (ACLE)::
+ * ARM Floating Point Status and Control Intrinsics::
++* ARM ARMv8-M Security Extensions::
+ * AVR Built-in Functions::
+ * Blackfin Built-in Functions::
+ * FR-V Built-in Functions::
+@@ -12260,6 +12261,35 @@ unsigned int __builtin_arm_get_fpscr ()
+ void __builtin_arm_set_fpscr (unsigned int)
+ @end smallexample
+ 
++@node ARM ARMv8-M Security Extensions
++@subsection ARM ARMv8-M Security Extensions
++
++GCC implements the ARMv8-M Security Extensions as described in the ARMv8-M
++Security Extensions: Requiremenets on Development Tools Engineering
++Specification, which can be found at
++@uref{http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf}.
++
++As part of the Security Extensions GCC implements two new function attributes:
++@code{cmse_nonsecure_entry} and @code{cmse_nonsecure_call}.
++
++As part of the Security Extensions GCC implements the intrinsics below.  FPTR
++is used here to mean any function pointer type.
++
++@smallexample
++cmse_address_info_t cmse_TT (void *)
++cmse_address_info_t cmse_TT_fptr (FPTR)
++cmse_address_info_t cmse_TTT (void *)
++cmse_address_info_t cmse_TTT_fptr (FPTR)
++cmse_address_info_t cmse_TTA (void *)
++cmse_address_info_t cmse_TTA_fptr (FPTR)
++cmse_address_info_t cmse_TTAT (void *)
++cmse_address_info_t cmse_TTAT_fptr (FPTR)
++void * cmse_check_address_range (void *, size_t, int)
++typeof(p) cmse_nsfptr_create (FPTR p)
++intptr_t cmse_is_nsfptr (FPTR)
++int cmse_nonsecure_caller (void)
++@end smallexample
++
+ @node AVR Built-in Functions
+ @subsection AVR Built-in Functions
+ 
+--- a/src/gcc/doc/fragments.texi
++++ b/src/gcc/doc/fragments.texi
+@@ -156,15 +156,16 @@ variants.  And for some targets it is better to reuse an existing multilib
+ than to fall back to default multilib when there is no corresponding multilib.
+ This can be done by adding reuse rules to @code{MULTILIB_REUSE}.
+ 
+-A reuse rule is comprised of two parts connected by equality sign.  The left part
+-is option set used to build multilib and the right part is option set that will
+-reuse this multilib.  The order of options in the left part matters and should be
+-same with those specified in @code{MULTILIB_REQUIRED} or aligned with order in
+-@code{MULTILIB_OPTIONS}.  There is no such limitation for options in right part
+-as we don't build multilib from them.  But the equality sign in both parts should
+-be replaced with period.
+-
+-The @code{MULTILIB_REUSE} is different from @code{MULTILIB_MATCHES} in that it
++A reuse rule is comprised of two parts connected by equality sign.  The left
++part is the option set used to build multilib and the right part is the option
++set that will reuse this multilib.  Both parts should only use options
++specified in @code{MULTILIB_OPTIONS} and the equality signs found in options
++name should be replaced with periods.  The order of options in the left part
++matters and should be same with those specified in @code{MULTILIB_REQUIRED} or
++aligned with the order in @code{MULTILIB_OPTIONS}.  There is no such limitation
++for options in the right part as we don't build multilib from them.
++
++@code{MULTILIB_REUSE} is different from @code{MULTILIB_MATCHES} in that it
+ sets up relations between two option sets rather than two options.  Here is an
+ example to demo how we reuse libraries built in Thumb mode for applications built
+ in ARM mode:
+--- a/src/gcc/doc/install.texi
++++ b/src/gcc/doc/install.texi
+@@ -1106,19 +1106,59 @@ sysv, aix.
+ 
+ @item --with-multilib-list=@var{list}
+ @itemx --without-multilib-list
+-Specify what multilibs to build.
+-Currently only implemented for arm*-*-*, sh*-*-* and x86-64-*-linux*.
++Specify what multilibs to build.  @var{list} is a comma separated list of
++values, possibly consisting of a single value.  Currently only implemented
++for arm*-*-*, sh*-*-* and x86-64-*-linux*.  The accepted values and meaning
++for each target is given below.
+ 
+ @table @code
+ @item arm*-*-*
+-@var{list} is either @code{default} or @code{aprofile}.  Specifying
+-@code{default} is equivalent to omitting this option while specifying
+-@code{aprofile} builds multilibs for each combination of ISA (@code{-marm} or
+-@code{-mthumb}), architecture (@code{-march=armv7-a}, @code{-march=armv7ve},
+-or @code{-march=armv8-a}), FPU available (none, @code{-mfpu=vfpv3-d16},
+-@code{-mfpu=neon}, @code{-mfpu=vfpv4-d16}, @code{-mfpu=neon-vfpv4} or
+-@code{-mfpu=neon-fp-armv8} depending on architecture) and floating-point ABI
+-(@code{-mfloat-abi=softfp} or @code{-mfloat-abi=hard}).
++@var{list} is one of@code{default}, @code{aprofile} or @code{rmprofile}.
++Specifying @code{default} is equivalent to omitting this option, ie. only the
++default runtime library will be enabled.  Specifying @code{aprofile} or
++@code{rmprofile} builds multilibs for a combination of ISA, architecture,
++FPU available and floating-point ABI.
++
++The table below gives the combination of ISAs, architectures, FPUs and
++floating-point ABIs for which multilibs are built for each accepted value.
++
++@multitable @columnfractions .15 .28 .30
++@item Option @tab aprofile @tab rmprofile
++@item ISAs
++@tab @code{-marm} and @code{-mthumb}
++@tab @code{-mthumb}
++@item Architectures@*@*@*@*@*@*
++@tab default architecture@*
++@code{-march=armv7-a}@*
++@code{-march=armv7ve}@*
++@code{-march=armv8-a}@*@*@*
++@tab default architecture@*
++@code{-march=armv6s-m}@*
++@code{-march=armv7-m}@*
++@code{-march=armv7e-m}@*
++@code{-march=armv8-m.base}@*
++@code{-march=armv8-m.main}@*
++@code{-march=armv7}
++@item FPUs@*@*@*@*@*
++@tab none@*
++@code{-mfpu=vfpv3-d16}@*
++@code{-mfpu=neon}@*
++@code{-mfpu=vfpv4-d16}@*
++@code{-mfpu=neon-vfpv4}@*
++@code{-mfpu=neon-fp-armv8}
++@tab none@*
++@code{-mfpu=vfpv3-d16}@*
++@code{-mfpu=fpv4-sp-d16}@*
++@code{-mfpu=fpv5-sp-d16}@*
++@code{-mfpu=fpv5-d16}@*
++@item floating-point@/ ABIs@*@*
++@tab @code{-mfloat-abi=soft}@*
++@code{-mfloat-abi=softfp}@*
++@code{-mfloat-abi=hard}
++@tab @code{-mfloat-abi=soft}@*
++@code{-mfloat-abi=softfp}@*
++@code{-mfloat-abi=hard}
++@end multitable
+ 
+ @item sh*-*-*
+ @var{list} is a comma separated list of CPU names.  These must be of the
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -573,6 +573,8 @@ Objective-C and Objective-C++ Dialects}.
+ -mfix-cortex-a53-835769  -mno-fix-cortex-a53-835769 @gol
+ -mfix-cortex-a53-843419  -mno-fix-cortex-a53-843419 @gol
+ -mlow-precision-recip-sqrt -mno-low-precision-recip-sqrt@gol
++-mlow-precision-sqrt -mno-low-precision-sqrt@gol
++-mlow-precision-div -mno-low-precision-div @gol
+ -march=@var{name}  -mcpu=@var{name}  -mtune=@var{name}}
+ 
+ @emph{Adapteva Epiphany Options}
+@@ -606,7 +608,6 @@ Objective-C and Objective-C++ Dialects}.
+ @gccoptlist{-mapcs-frame  -mno-apcs-frame @gol
+ -mabi=@var{name} @gol
+ -mapcs-stack-check  -mno-apcs-stack-check @gol
+--mapcs-float  -mno-apcs-float @gol
+ -mapcs-reentrant  -mno-apcs-reentrant @gol
+ -msched-prolog  -mno-sched-prolog @gol
+ -mlittle-endian  -mbig-endian @gol
+@@ -632,7 +633,9 @@ Objective-C and Objective-C++ Dialects}.
+ -mneon-for-64bits @gol
+ -mslow-flash-data @gol
+ -masm-syntax-unified @gol
+--mrestrict-it}
++-mrestrict-it @gol
++-mpure-code @gol
++-mcmse}
+ 
+ @emph{AVR Options}
+ @gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol
+@@ -9483,6 +9486,11 @@ Size of minimal partition for WHOPR (in estimated instructions).
+ This prevents expenses of splitting very small programs into too many
+ partitions.
+ 
++@item lto-max-partition
++Size of max partition for WHOPR (in estimated instructions).
++to provide an upper bound for individual size of partition.
++Meant to be used only with balanced partitioning.
++
+ @item cxx-max-namespaces-for-diagnostic-help
+ The maximum number of namespaces to consult for suggestions when C++
+ name lookup fails for an identifier.  The default is 1000.
+@@ -12833,9 +12841,9 @@ These options are defined for AArch64 implementations:
+ @item -mabi=@var{name}
+ @opindex mabi
+ Generate code for the specified data model.  Permissible values
+-are @samp{ilp32} for SysV-like data model where int, long int and pointer
+-are 32-bit, and @samp{lp64} for SysV-like data model where int is 32-bit,
+-but long int and pointer are 64-bit.
++are @samp{ilp32} for SysV-like data model where int, long int and pointers
++are 32 bits, and @samp{lp64} for SysV-like data model where int is 32 bits,
++but long int and pointers are 64 bits.
+ 
+ The default depends on the specific target configuration.  Note that
+ the LP64 and ILP32 ABIs are not link-compatible; you must compile your
+@@ -12860,25 +12868,24 @@ Generate little-endian code.  This is the default when GCC is configured for an
+ @item -mcmodel=tiny
+ @opindex mcmodel=tiny
+ Generate code for the tiny code model.  The program and its statically defined
+-symbols must be within 1GB of each other.  Pointers are 64 bits.  Programs can
+-be statically or dynamically linked.  This model is not fully implemented and
+-mostly treated as @samp{small}.
++symbols must be within 1MB of each other.  Programs can be statically or
++dynamically linked.
+ 
+ @item -mcmodel=small
+ @opindex mcmodel=small
+ Generate code for the small code model.  The program and its statically defined
+-symbols must be within 4GB of each other.  Pointers are 64 bits.  Programs can
+-be statically or dynamically linked.  This is the default code model.
++symbols must be within 4GB of each other.  Programs can be statically or
++dynamically linked.  This is the default code model.
+ 
+ @item -mcmodel=large
+ @opindex mcmodel=large
+ Generate code for the large code model.  This makes no assumptions about
+-addresses and sizes of sections.  Pointers are 64 bits.  Programs can be
+-statically linked only.
++addresses and sizes of sections.  Programs can be statically linked only.
+ 
+ @item -mstrict-align
+ @opindex mstrict-align
+-Do not assume that unaligned memory references are handled by the system.
++Avoid generating memory accesses that may not be aligned on a natural object
++boundary as described in the architecture specification.
+ 
+ @item -momit-leaf-frame-pointer
+ @itemx -mno-omit-leaf-frame-pointer
+@@ -12900,7 +12907,7 @@ of TLS variables.
+ @item -mtls-size=@var{size}
+ @opindex mtls-size
+ Specify bit size of immediate TLS offsets.  Valid values are 12, 24, 32, 48.
+-This option depends on binutils higher than 2.25.
++This option requires binutils 2.26 or newer.
+ 
+ @item -mfix-cortex-a53-835769
+ @itemx -mno-fix-cortex-a53-835769
+@@ -12920,12 +12927,34 @@ corresponding flag to the linker.
+ 
+ @item -mlow-precision-recip-sqrt
+ @item -mno-low-precision-recip-sqrt
+-@opindex -mlow-precision-recip-sqrt
+-@opindex -mno-low-precision-recip-sqrt
+-When calculating the reciprocal square root approximation,
+-uses one less step than otherwise, thus reducing latency and precision.
+-This is only relevant if @option{-ffast-math} enables the reciprocal square root
+-approximation, which in turn depends on the target processor.
++@opindex mlow-precision-recip-sqrt
++@opindex mno-low-precision-recip-sqrt
++Enable or disable the reciprocal square root approximation.
++This option only has an effect if @option{-ffast-math} or
++@option{-funsafe-math-optimizations} is used as well.  Enabling this reduces
++precision of reciprocal square root results to about 16 bits for
++single precision and to 32 bits for double precision.
++
++@item -mlow-precision-sqrt
++@item -mno-low-precision-sqrt
++@opindex -mlow-precision-sqrt
++@opindex -mno-low-precision-sqrt
++Enable or disable the square root approximation.
++This option only has an effect if @option{-ffast-math} or
++@option{-funsafe-math-optimizations} is used as well.  Enabling this reduces
++precision of square root results to about 16 bits for
++single precision and to 32 bits for double precision.
++If enabled, it implies @option{-mlow-precision-recip-sqrt}.
++
++@item -mlow-precision-div
++@item -mno-low-precision-div
++@opindex -mlow-precision-div
++@opindex -mno-low-precision-div
++Enable or disable the division approximation.
++This option only has an effect if @option{-ffast-math} or
++@option{-funsafe-math-optimizations} is used as well.  Enabling this reduces
++precision of division results to about 16 bits for
++single precision and to 32 bits for double precision.
+ 
+ @item -march=@var{name}
+ @opindex march
+@@ -12934,10 +12963,16 @@ more feature modifiers.  This option has the form
+ @option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}.
+ 
+ The permissible values for @var{arch} are @samp{armv8-a},
+-@samp{armv8.1-a} or @var{native}.
++@samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a} or @var{native}.
++
++The value @samp{armv8.3-a} implies @samp{armv8.2-a} and enables compiler
++support for the ARMv8.3-A architecture extensions.
++
++The value @samp{armv8.2-a} implies @samp{armv8.1-a} and enables compiler
++support for the ARMv8.2-A architecture extensions.
+ 
+ The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler
+-support for the ARMv8.1 architecture extension.  In particular, it
++support for the ARMv8.1-A architecture extension.  In particular, it
+ enables the @samp{+crc} and @samp{+lse} features.
+ 
+ The value @samp{native} is available on native AArch64 GNU/Linux and
+@@ -12961,18 +12996,18 @@ processors implementing the target architecture.
+ Specify the name of the target processor for which GCC should tune the
+ performance of the code.  Permissible values for this option are:
+ @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
+-@samp{cortex-a72}, @samp{exynos-m1}, @samp{qdf24xx}, @samp{thunderx},
+-@samp{xgene1}.
++@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, @samp{qdf24xx},
++@samp{thunderx}, @samp{xgene1}, @samp{vulcan}, @samp{cortex-a57.cortex-a53},
++@samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35},
++@samp{cortex-a73.cortex-a53}, @samp{native}.
+ 
+-Additionally, this option can specify that GCC should tune the performance
+-of the code for a big.LITTLE system.  Permissible values for this
+-option are: @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}.
++The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
++@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53}
++specify that GCC should tune for a big.LITTLE system.
+ 
+ Additionally on native AArch64 GNU/Linux systems the value
+-@samp{native} is available.  This option causes the compiler to pick
+-the architecture of and tune the performance of the code for the
+-processor of the host system.  This option has no effect if the
+-compiler is unable to recognize the architecture of the host system.
++@samp{native} tunes performance to the host system.  This option has no effect
++if the compiler is unable to recognize the processor of the host system.
+ 
+ Where none of @option{-mtune=}, @option{-mcpu=} or @option{-march=}
+ are specified, the code is tuned to perform well across a range
+@@ -12992,12 +13027,6 @@ documented in the sub-section on
+ Feature Modifiers}.  Where conflicting feature modifiers are
+ specified, the right-most feature is used.
+ 
+-Additionally on native AArch64 GNU/Linux systems the value
+-@samp{native} is available.  This option causes the compiler to tune
+-the performance of the code for the processor of the host system.
+-This option has no effect if the compiler is unable to recognize the
+-architecture of the host system.
+-
+ GCC uses @var{name} to determine what kind of instructions it can emit when
+ generating assembly code (as if by @option{-march}) and to determine
+ the target processor for which to tune for performance (as if
+@@ -13015,11 +13044,11 @@ across releases.
+ This option is only intended to be useful when developing GCC.
+ 
+ @item -mpc-relative-literal-loads
+-@opindex mpcrelativeliteralloads
+-Enable PC relative literal loads. If this option is used, literal
+-pools are assumed to have a range of up to 1MiB and an appropriate
+-instruction sequence is used. This option has no impact when used
+-with @option{-mcmodel=tiny}.
++@opindex mpc-relative-literal-loads
++Enable PC-relative literal loads.  With this option literal pools are
++accessed using a single instruction and emitted after each function.  This
++limits the maximum size of functions to 1MB.  This is enabled by default for
++@option{-mcmodel=tiny}.
+ 
+ @end table
+ 
+@@ -13047,12 +13076,14 @@ instructions.  This is on by default for all possible values for options
+ @item lse
+ Enable Large System Extension instructions.  This is on by default for
+ @option{-march=armv8.1-a}.
++@item fp16
++Enable FP16 extension.  This also enables floating-point instructions.
+ 
+ @end table
+ 
+-That is, @option{crypto} implies @option{simd} implies @option{fp}.
+-Conversely, @option{nofp} (or equivalently, @option{-mgeneral-regs-only})
+-implies @option{nosimd} implies @option{nocrypto}.
++Feature @option{crypto} implies @option{simd}, which implies @option{fp}.
++Conversely, @option{nofp} implies @option{nosimd}, which implies
++@option{nocrypto}.
+ 
+ @node Adapteva Epiphany Options
+ @subsection Adapteva Epiphany Options
+@@ -13902,16 +13933,6 @@ called, depending upon the amount of stack space required.  The runtime
+ system is required to provide these functions.  The default is
+ @option{-mno-apcs-stack-check}, since this produces smaller code.
+ 
+-@c not currently implemented
+-@item -mapcs-float
+-@opindex mapcs-float
+-Pass floating-point arguments using the floating-point registers.  This is
+-one of the variants of the APCS@.  This option is recommended if the
+-target hardware has a floating-point unit or if a lot of floating-point
+-arithmetic is going to be performed by the code.  The default is
+-@option{-mno-apcs-float}, since the size of integer-only code is 
+-slightly increased if @option{-mapcs-float} is used.
+-
+ @c not currently implemented
+ @item -mapcs-reentrant
+ @opindex mapcs-reentrant
+@@ -13972,21 +13993,42 @@ name to determine what kind of instructions it can emit when generating
+ assembly code.  This option can be used in conjunction with or instead
+ of the @option{-mcpu=} option.  Permissible names are: @samp{armv2},
+ @samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
+-@samp{armv5}, @samp{armv5t}, @samp{armv5e}, @samp{armv5te},
+-@samp{armv6}, @samp{armv6j},
+-@samp{armv6t2}, @samp{armv6z}, @samp{armv6kz}, @samp{armv6-m},
+-@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, @samp{armv7e-m},
++@samp{armv5}, @samp{armv5e}, @samp{armv5t}, @samp{armv5te},
++@samp{armv6}, @samp{armv6-m}, @samp{armv6j}, @samp{armv6k},
++@samp{armv6kz}, @samp{armv6s-m},
++@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk},
++@samp{armv7}, @samp{armv7-a}, @samp{armv7-m}, @samp{armv7-r}, @samp{armv7e-m},
+ @samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, @samp{armv8.1-a},
+-@samp{armv8.1-a+crc}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
++@samp{armv8.1-a+crc}, @samp{armv8-m.base}, @samp{armv8-m.main},
++@samp{armv8-m.main+dsp}, @samp{iwmmxt}, @samp{iwmmxt2}.
+ 
+-Architecture revisions older than @option{armv4t} are deprecated.
++Architecture revisions older than @samp{armv4t} are deprecated.
+ 
+-@option{-march=armv7ve} is the armv7-a architecture with virtualization
++@option{-march=armv6s-m} is the @samp{armv6-m} architecture with support for
++the (now mandatory) SVC instruction.
++
++@option{-march=armv6zk} is an alias for @samp{armv6kz}, existing for backwards
++compatibility.
++
++@option{-march=armv7ve} is the @samp{armv7-a} architecture with virtualization
+ extensions.
+ 
+ @option{-march=armv8-a+crc} enables code generation for the ARMv8-A
+ architecture together with the optional CRC32 extensions.
+ 
++@option{-march=armv8.1-a} enables compiler support for the ARMv8.1-A
++architecture.  This also enables the features provided by
++@option{-march=armv8-a+crc}.
++
++@option{-march=armv8.2-a} enables compiler support for the ARMv8.2-A
++architecture.  This also enables the features provided by
++@option{-march=armv8.1-a}.
++
++@option{-march=armv8.2-a+fp16} enables compiler support for the
++ARMv8.2-A architecture with the optional FP16 instructions extension.
++This also enables the features provided by @option{-march=armv8.1-a}
++and implies @option{-mfp16-format=ieee}.
++
+ @option{-march=native} causes the compiler to auto-detect the architecture
+ of the build computer.  At present, this feature is only supported on
+ GNU/Linux, and not all architectures are recognized.  If the auto-detect
+@@ -14018,8 +14060,10 @@ Permissible names are: @samp{arm2}, @samp{arm250},
+ @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8},
+ @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
+ @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
+-@samp{cortex-a72}, @samp{cortex-r4},
++@samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-r4},
+ @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
++@samp{cortex-m33},
++@samp{cortex-m23},
+ @samp{cortex-m7},
+ @samp{cortex-m4},
+ @samp{cortex-m3},
+@@ -14040,7 +14084,8 @@ Permissible names are: @samp{arm2}, @samp{arm250},
+ Additionally, this option can specify that GCC should tune the performance
+ of the code for a big.LITTLE system.  Permissible names are:
+ @samp{cortex-a15.cortex-a7}, @samp{cortex-a17.cortex-a7},
+-@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}.
++@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
++@samp{cortex-a72.cortex-a35}, @samp{cortex-a73.cortex-a53}.
+ 
+ @option{-mtune=generic-@var{arch}} specifies that GCC should tune the
+ performance for a blend of processors within architecture @var{arch}.
+@@ -14078,12 +14123,14 @@ is unsuccessful the option has no effect.
+ @item -mfpu=@var{name}
+ @opindex mfpu
+ This specifies what floating-point hardware (or hardware emulation) is
+-available on the target.  Permissible names are: @samp{vfp}, @samp{vfpv3},
++available on the target.  Permissible names are: @samp{vfpv2}, @samp{vfpv3},
+ @samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd},
+-@samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4},
++@samp{vfpv3xd-fp16}, @samp{neon-vfpv3}, @samp{neon-fp16}, @samp{vfpv4},
+ @samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4},
+ @samp{fpv5-d16}, @samp{fpv5-sp-d16},
+ @samp{fp-armv8}, @samp{neon-fp-armv8} and @samp{crypto-neon-fp-armv8}.
++Note that @samp{neon} is an alias for @samp{neon-vfpv3} and @samp{vfp}
++is an alias for @samp{vfpv2}.
+ 
+ If @option{-msoft-float} is specified this specifies the format of
+ floating-point values.
+@@ -14170,9 +14217,12 @@ otherwise the default is @samp{R10}.
+ 
+ @item -mpic-data-is-text-relative
+ @opindex mpic-data-is-text-relative
+-Assume that each data segments are relative to text segment at load time.
+-Therefore, it permits addressing data using PC-relative operations.
+-This option is on by default for targets other than VxWorks RTP.
++Assume that the displacement between the text and data segments is fixed
++at static link time.  This permits using PC-relative addressing
++operations to access data known to be in the data segment.  For
++non-VxWorks RTP targets, this option is enabled by default.  When
++disabled on such targets, it will enable @option{-msingle-pic-base} by
++default.
+ 
+ @item -mpoke-function-name
+ @opindex mpoke-function-name
+@@ -14282,10 +14332,10 @@ generating these instructions.  This option is enabled by default when
+ @opindex mno-unaligned-access
+ Enables (or disables) reading and writing of 16- and 32- bit values
+ from addresses that are not 16- or 32- bit aligned.  By default
+-unaligned access is disabled for all pre-ARMv6 and all ARMv6-M
+-architectures, and enabled for all other architectures.  If unaligned
+-access is not enabled then words in packed data structures are
+-accessed a byte at a time.
++unaligned access is disabled for all pre-ARMv6, all ARMv6-M and for
++ARMv8-M Baseline architectures, and enabled for all other
++architectures.  If unaligned access is not enabled then words in packed
++data structures are accessed a byte at a time.
+ 
+ The ARM attribute @code{Tag_CPU_unaligned_access} is set in the
+ generated object file to either true or false, depending upon the
+@@ -14325,6 +14375,20 @@ Print CPU tuning information as comment in assembler file.  This is
+ an option used only for regression testing of the compiler and not
+ intended for ordinary use in compiling code.  This option is disabled
+ by default.
++
++@item -mpure-code
++@opindex mpure-code
++Do not allow constant data to be placed in code sections.
++Additionally, when compiling for ELF object format give all text sections the
++ELF processor-specific section attribute @code{SHF_ARM_PURECODE}.  This option
++is only available when generating non-pic code for M-profile targets with the
++MOVT instruction.
++
++@item -mcmse
++@opindex mcmse
++Generate secure code as per the "ARMv8-M Security Extensions: Requirements on
++Development Tools Engineering Specification", which can be found on
++@url{http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf}.
+ @end table
+ 
+ @node AVR Options
+@@ -18092,7 +18156,7 @@ IEEE 754 floating-point data.
+ 
+ The @option{-mnan=legacy} option selects the legacy encoding.  In this
+ case quiet NaNs (qNaNs) are denoted by the first bit of their trailing
+-significand field being 0, whereas signalling NaNs (sNaNs) are denoted
++significand field being 0, whereas signaling NaNs (sNaNs) are denoted
+ by the first bit of their trailing significand field being 1.
+ 
+ The @option{-mnan=2008} option selects the IEEE 754-2008 encoding.  In
+--- a/src/gcc/doc/md.texi
++++ b/src/gcc/doc/md.texi
+@@ -5030,7 +5030,7 @@ it is unspecified which of the two operands is returned as the result.
+ IEEE-conformant minimum and maximum operations.  If one operand is a quiet
+ @code{NaN}, then the other operand is returned.  If both operands are quiet
+ @code{NaN}, then a quiet @code{NaN} is returned.  In the case when gcc supports
+-signalling @code{NaN} (-fsignaling-nans) an invalid floating point exception is
++signaling @code{NaN} (-fsignaling-nans) an invalid floating point exception is
+ raised and a quiet @code{NaN} is returned.
+ 
+ All operands have mode @var{m}, which is a scalar or vector
+--- a/src/gcc/doc/sourcebuild.texi
++++ b/src/gcc/doc/sourcebuild.texi
+@@ -1555,6 +1555,16 @@ options.  Some multilibs may be incompatible with these options.
+ ARM Target supports @code{-mfpu=neon-vfpv4 -mfloat-abi=softfp} or compatible
+ options.  Some multilibs may be incompatible with these options.
+ 
++@item arm_fp16_ok
++@anchor{arm_fp16_ok}
++Target supports options to generate VFP half-precision floating-point
++instructions.  Some multilibs may be incompatible with these
++options.  This test is valid for ARM only.
++
++@item arm_fp16_hw
++Target supports executing VFP half-precision floating-point
++instructions.  This test is valid for ARM only.
++
+ @item arm_neon_fp16_ok
+ @anchor{arm_neon_fp16_ok}
+ ARM Target supports @code{-mfpu=neon-fp16 -mfloat-abi=softfp} or compatible
+@@ -1565,6 +1575,13 @@ options, including @code{-mfp16-format=ieee} if necessary to obtain the
+ Test system supports executing Neon half-precision float instructions.
+ (Implies previous.)
+ 
++@item arm_fp16_alternative_ok
++ARM target supports the ARM FP16 alternative format.  Some multilibs
++may be incompatible with the options needed.
++
++@item arm_fp16_none_ok
++ARM target supports specifying none as the ARM FP16 format.
++
+ @item arm_thumb1_ok
+ ARM target generates Thumb-1 code for @code{-mthumb}.
+ 
+@@ -1589,6 +1606,7 @@ ARM target supports @code{-mfpu=neon-fp-armv8 -mfloat-abi=softfp}.
+ Some multilibs may be incompatible with these options.
+ 
+ @item arm_v8_1a_neon_ok
++@anchor{arm_v8_1a_neon_ok}
+ ARM target supports options to generate ARMv8.1 Adv.SIMD instructions.
+ Some multilibs may be incompatible with these options.
+ 
+@@ -1597,10 +1615,47 @@ ARM target supports executing ARMv8.1 Adv.SIMD instructions.  Some
+ multilibs may be incompatible with the options needed.  Implies
+ arm_v8_1a_neon_ok.
+ 
++@item arm_acq_rel
++ARM target supports acquire-release instructions.
++
++@item arm_v8_2a_fp16_scalar_ok
++@anchor{arm_v8_2a_fp16_scalar_ok}
++ARM target supports options to generate instructions for ARMv8.2 and
++scalar instructions from the FP16 extension.  Some multilibs may be
++incompatible with these options.
++
++@item arm_v8_2a_fp16_scalar_hw
++ARM target supports executing instructions for ARMv8.2 and scalar
++instructions from the FP16 extension.  Some multilibs may be
++incompatible with these options.  Implies arm_v8_2a_fp16_neon_ok.
++
++@item arm_v8_2a_fp16_neon_ok
++@anchor{arm_v8_2a_fp16_neon_ok}
++ARM target supports options to generate instructions from ARMv8.2 with
++the FP16 extension.  Some multilibs may be incompatible with these
++options.  Implies arm_v8_2a_fp16_scalar_ok.
++
++@item arm_v8_2a_fp16_neon_hw
++ARM target supports executing instructions from ARMv8.2 with the FP16
++extension.  Some multilibs may be incompatible with these options.
++Implies arm_v8_2a_fp16_neon_ok and arm_v8_2a_fp16_scalar_hw.
++
+ @item arm_prefer_ldrd_strd
+ ARM target prefers @code{LDRD} and @code{STRD} instructions over
+ @code{LDM} and @code{STM} instructions.
+ 
++@item arm_thumb1_movt_ok
++ARM target generates Thumb-1 code for @code{-mthumb} with @code{MOVW}
++and @code{MOVT} instructions available.
++
++@item arm_thumb1_cbz_ok
++ARM target generates Thumb-1 code for @code{-mthumb} with
++@code{CBZ} and @code{CBNZ} instructions available.
++
++@item arm_cmse_ok
++ARM target supports ARMv8-M Security Extensions, enabled by the @code{-mcmse}
++option.
++
+ @end table
+ 
+ @subsubsection AArch64-specific attributes
+@@ -2069,6 +2124,28 @@ NEON support.  Only ARM targets support this feature, and only then
+ in certain modes; see the @ref{arm_neon_ok,,arm_neon_ok effective target
+ keyword}.
+ 
++@item arm_fp16
++VFP half-precision floating point support.  This does not select the
++FP16 format; for that, use @ref{arm_fp16_ieee,,arm_fp16_ieee} or
++@ref{arm_fp16_alternative,,arm_fp16_alternative} instead.  This
++feature is only supported by ARM targets and then only in certain
++modes; see the @ref{arm_fp16_ok,,arm_fp16_ok effective target
++keyword}.
++
++@item arm_fp16_ieee
++@anchor{arm_fp16_ieee}
++ARM IEEE 754-2008 format VFP half-precision floating point support.
++This feature is only supported by ARM targets and then only in certain
++modes; see the @ref{arm_fp16_ok,,arm_fp16_ok effective target
++keyword}.
++
++@item arm_fp16_alternative
++@anchor{arm_fp16_alternative}
++ARM Alternative format VFP half-precision floating point support.
++This feature is only supported by ARM targets and then only in certain
++modes; see the @ref{arm_fp16_ok,,arm_fp16_ok effective target
++keyword}.
++
+ @item arm_neon_fp16
+ NEON and half-precision floating point support.  Only ARM targets
+ support this feature, and only then in certain modes; see
+@@ -2078,6 +2155,23 @@ the @ref{arm_neon_fp16_ok,,arm_neon_fp16_ok effective target keyword}.
+ arm vfp3 floating point support; see
+ the @ref{arm_vfp3_ok,,arm_vfp3_ok effective target keyword}.
+ 
++@item arm_v8_1a_neon
++Add options for ARMv8.1 with Adv.SIMD support, if this is supported
++by the target; see the @ref{arm_v8_1a_neon_ok,,arm_v8_1a_neon_ok}
++effective target keyword.
++
++@item arm_v8_2a_fp16_scalar
++Add options for ARMv8.2 with scalar FP16 support, if this is
++supported by the target; see the
++@ref{arm_v8_2a_fp16_scalar_ok,,arm_v8_2a_fp16_scalar_ok} effective
++target keyword.
++
++@item arm_v8_2a_fp16_neon
++Add options for ARMv8.2 with Adv.SIMD FP16 support, if this is
++supported by the target; see the
++@ref{arm_v8_2a_fp16_neon_ok,,arm_v8_2a_fp16_neon_ok} effective target
++keyword.
++
+ @item bind_pic_locally
+ Add the target-specific flags needed to enable functions to bind
+ locally when using pic/PIC passes in the testsuite.
+@@ -2111,6 +2205,11 @@ the codeset to convert to.
+ Skip the test if the target does not support profiling with option
+ @var{profopt}.
+ 
++@item dg-require-stack-check @var{check}
++Skip the test if the target does not support the @code{-fstack-check}
++option.  If @var{check} is @code{""}, support for @code{-fstack-check}
++is checked, for @code{-fstack-check=("@var{check}")} otherwise.
++
+ @item dg-require-visibility @var{vis}
+ Skip the test if the target does not support the @code{visibility} attribute.
+ If @var{vis} is @code{""}, support for @code{visibility("hidden")} is
+--- a/src/gcc/doc/tm.texi
++++ b/src/gcc/doc/tm.texi
+@@ -7510,6 +7510,18 @@ is non-NULL, it is the @code{VAR_DECL} or @code{FUNCTION_DECL} with which
+ this section is associated.
+ @end deftypefn
+ 
++@deftypefn {Target Hook} bool TARGET_ASM_ELF_FLAGS_NUMERIC (unsigned int @var{flags}, unsigned int *@var{num})
++This hook can be used to encode ELF section flags for which no letter
++code has been defined in the assembler.  It is called by
++@code{default_asm_named_section} whenever the section flags need to be
++emitted in the assembler output.  If the hook returns true, then the
++numerical value for ELF section flags should be calculated from
++@var{flags} and saved in @var{*num}; the value is printed out instead of the
++normal sequence of letter codes.  If the hook is not defined, or if it
++returns false, then @var{num} is ignored and the traditional letter sequence
++is emitted.
++@end deftypefn
++
+ @deftypefn {Target Hook} {section *} TARGET_ASM_FUNCTION_SECTION (tree @var{decl}, enum node_frequency @var{freq}, bool @var{startup}, bool @var{exit})
+ Return preferred text (sub)section for function @var{decl}.
+ Main purpose of this function is to separate cold, normal and hot
+--- a/src/gcc/doc/tm.texi.in
++++ b/src/gcc/doc/tm.texi.in
+@@ -5209,6 +5209,8 @@ of the filename using this macro.
+ 
+ @hook TARGET_ASM_NAMED_SECTION
+ 
++@hook TARGET_ASM_ELF_FLAGS_NUMERIC
++
+ @hook TARGET_ASM_FUNCTION_SECTION
+ 
+ @hook TARGET_ASM_FUNCTION_SWITCHED_TEXT_SECTIONS
--- gcc-6-6.4.0.orig/debian/patches/gcc-linaro-no-macros.diff
+++ gcc-6-6.4.0/debian/patches/gcc-linaro-no-macros.diff
@@ -0,0 +1,105 @@
+# DP : Don't add the __LINARO_RELEASE__ and __LINARO_SPIN__ macros for distro builds.
+
+Index: b/src/gcc/cppbuiltin.c
+===================================================================
+--- a/src/gcc/cppbuiltin.c
++++ b/src/gcc/cppbuiltin.c
+@@ -52,41 +52,18 @@ parse_basever (int *major, int *minor, i
+     *patchlevel = s_patchlevel;
+ }
+ 
+-/* Parse a LINAROVER version string of the format "M.m-year.month[-spin][~dev]"
+-   to create Linaro release number YYYYMM and spin version.  */
+-static void
+-parse_linarover (int *release, int *spin)
+-{
+-  static int s_year = -1, s_month, s_spin;
+-
+-  if (s_year == -1)
+-    if (sscanf (LINAROVER, "%*[^-]-%d.%d-%d", &s_year, &s_month, &s_spin) != 3)
+-      {
+-	sscanf (LINAROVER, "%*[^-]-%d.%d", &s_year, &s_month);
+-	s_spin = 0;
+-      }
+-
+-  if (release)
+-    *release = s_year * 100 + s_month;
+-
+-  if (spin)
+-    *spin = s_spin;
+-}
+ 
+ /* Define __GNUC__, __GNUC_MINOR__, __GNUC_PATCHLEVEL__ and __VERSION__.  */
+ static void
+ define__GNUC__ (cpp_reader *pfile)
+ {
+-  int major, minor, patchlevel, linaro_release, linaro_spin;
++  int major, minor, patchlevel;
+ 
+   parse_basever (&major, &minor, &patchlevel);
+-  parse_linarover (&linaro_release, &linaro_spin);
+   cpp_define_formatted (pfile, "__GNUC__=%d", major);
+   cpp_define_formatted (pfile, "__GNUC_MINOR__=%d", minor);
+   cpp_define_formatted (pfile, "__GNUC_PATCHLEVEL__=%d", patchlevel);
+   cpp_define_formatted (pfile, "__VERSION__=\"%s\"", version_string);
+-  cpp_define_formatted (pfile, "__LINARO_RELEASE__=%d", linaro_release);
+-  cpp_define_formatted (pfile, "__LINARO_SPIN__=%d", linaro_spin);
+   cpp_define_formatted (pfile, "__ATOMIC_RELAXED=%d", MEMMODEL_RELAXED);
+   cpp_define_formatted (pfile, "__ATOMIC_SEQ_CST=%d", MEMMODEL_SEQ_CST);
+   cpp_define_formatted (pfile, "__ATOMIC_ACQUIRE=%d", MEMMODEL_ACQUIRE);
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -833,12 +833,10 @@ BASEVER     := $(srcdir)/BASE-VER  # 4.x
+ DEVPHASE    := $(srcdir)/DEV-PHASE # experimental, prerelease, ""
+ DATESTAMP   := $(srcdir)/DATESTAMP # YYYYMMDD or empty
+ REVISION    := $(srcdir)/REVISION  # [BRANCH revision XXXXXX]
+-LINAROVER   := $(srcdir)/LINARO-VERSION # M.x-YYYY.MM[-S][~dev]
+ 
+ BASEVER_c   := $(shell cat $(BASEVER))
+ DEVPHASE_c  := $(shell cat $(DEVPHASE))
+ DATESTAMP_c := $(shell cat $(DATESTAMP))
+-LINAROVER_c := $(shell cat $(LINAROVER))
+ 
+ ifeq (,$(wildcard $(REVISION)))
+ REVISION_c  :=
+@@ -865,7 +863,6 @@ DATESTAMP_s := \
+   "\"$(if $(DEVPHASE_c)$(filter-out 0,$(PATCHLEVEL_c)), $(DATESTAMP_c))\""
+ PKGVERSION_s:= "\"@PKGVERSION@\""
+ BUGURL_s    := "\"@REPORT_BUGS_TO@\""
+-LINAROVER_s := "\"$(LINAROVER_c)\""
+ 
+ PKGVERSION  := @PKGVERSION@
+ BUGURL_TEXI := @REPORT_BUGS_TEXI@
+@@ -2706,9 +2703,8 @@ PREPROCESSOR_DEFINES = \
+   -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
+   @TARGET_SYSTEM_ROOT_DEFINE@
+ 
+-CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(BASEVER_s) \
+-	-DLINAROVER=$(LINAROVER_s)
+-cppbuiltin.o: $(BASEVER) $(LINAROVER)
++CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(BASEVER_s)
++cppbuiltin.o: $(BASEVER)
+ 
+ CFLAGS-cppdefault.o += $(PREPROCESSOR_DEFINES)
+ 
+Index: b/src/gcc/LINARO-VERSION
+===================================================================
+--- a/src/gcc/LINARO-VERSION
++++ /dev/null
+@@ -1,1 +0,0 @@
+-Snapshot 6.4-2017.11
+Index: b/src/gcc/configure.ac
+===================================================================
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -910,7 +910,7 @@ AC_ARG_WITH(specs,
+ )
+ AC_SUBST(CONFIGURE_SPECS)
+ 
+-ACX_PKGVERSION([Linaro GCC `cat $srcdir/LINARO-VERSION`])
++ACX_PKGVERSION([GCC])
+ ACX_BUGURL([http://gcc.gnu.org/bugs.html])
+ 
+ # Sanity check enable_languages in case someone does not run the toplevel
--- gcc-6-6.4.0.orig/debian/patches/gcc-linaro.diff
+++ gcc-6-6.4.0/debian/patches/gcc-linaro.diff
@@ -0,0 +1,165191 @@
+# DP: Changes for the Linaro 6-2017.11 snapshot.
+
+MSG=$(git log origin/linaro/gcc-6-branch --format=format:"%s" -n 1 --grep "Merge branches"); SVN=${MSG##* }; git log origin/gcc-6-branch --format=format:"%H" -n 1 --grep "gcc-6-branch@${SVN%.}"
+
+LANG=C git diff --no-renames a28ee6004c07ad9b0f4891b25ef25a171c70d93a d9adb30d5631885cefdbc2ccf80db597a934df81 \
+ | egrep -v '^(diff|index) ' \
+ | filterdiff --strip=1 --addoldprefix=a/src/  --addnewprefix=b/src/ \
+ | sed 's,a/src//dev/null,/dev/null,'
+
+--- a/src/contrib/compare_tests
++++ b/src/contrib/compare_tests
+@@ -107,8 +107,8 @@ elif [ -d "$1" -o -d "$2" ] ; then
+ 	usage "Must specify either two directories or two files"
+ fi
+ 
+-sed 's/^XFAIL/FAIL/; s/^XPASS/PASS/' < "$1" | awk '/^Running target / {target = $3} { if (target != "unix") { sub(/: /, "&"target": " ); }; print $0; }' | cut -c1-2000 >$tmp1
+-sed 's/^XFAIL/FAIL/; s/^XPASS/PASS/' < "$2" | awk '/^Running target / {target = $3} { if (target != "unix") { sub(/: /, "&"target": " ); }; print $0; }' | cut -c1-2000 >$tmp2
++sed 's/^XFAIL/FAIL/; s/^ERROR/FAIL/; s/^XPASS/PASS/' < "$1" | awk '/^Running target / {target = $3} { if (target != "unix") { sub(/: /, "&"target": " ); }; print $0; }' | cut -c1-2000 >$tmp1
++sed 's/^XFAIL/FAIL/; s/^ERROR/FAIL/; s/^XPASS/PASS/' < "$2" | awk '/^Running target / {target = $3} { if (target != "unix") { sub(/: /, "&"target": " ); }; print $0; }' | cut -c1-2000 >$tmp2
+ 
+ before=$tmp1
+ now=$tmp2
+--- a/src/contrib/dg-extract-results.py
++++ b/src/contrib/dg-extract-results.py
+@@ -134,6 +134,7 @@ class Prog:
+         self.end_line = None
+         # Known summary types.
+         self.count_names = [
++            '# of DejaGnu errors\t\t',
+             '# of expected passes\t\t',
+             '# of unexpected failures\t',
+             '# of unexpected successes\t',
+@@ -245,6 +246,10 @@ class Prog:
+             segment = Segment (filename, file.tell())
+             variation.header = segment
+ 
++        # Parse the rest of the summary (the '# of ' lines).
++        if len (variation.counts) == 0:
++            variation.counts = self.zero_counts()
++
+         # Parse up until the first line of the summary.
+         if num_variations == 1:
+             end = '\t\t=== ' + tool.name + ' Summary ===\n'
+@@ -291,6 +296,11 @@ class Prog:
+                 harness.results.append ((key, line))
+                 if not first_key and sort_logs:
+                     first_key = key
++                if line.startswith ('ERROR: (DejaGnu)'):
++                    for i in range (len (self.count_names)):
++                        if 'DejaGnu errors' in self.count_names[i]:
++                            variation.counts[i] += 1
++                            break
+ 
+             # 'Using ...' lines are only interesting in a header.  Splitting
+             # the test up into parallel runs leads to more 'Using ...' lines
+@@ -309,9 +319,6 @@ class Prog:
+             segment.lines -= final_using
+             harness.add_segment (first_key, segment)
+ 
+-        # Parse the rest of the summary (the '# of ' lines).
+-        if len (variation.counts) == 0:
+-            variation.counts = self.zero_counts()
+         while True:
+             before = file.tell()
+             line = file.readline()
+--- a/src/contrib/dg-extract-results.sh
++++ b/src/contrib/dg-extract-results.sh
+@@ -369,10 +369,11 @@ EOF
+ BEGIN {
+   variant="$VAR"
+   tool="$TOOL"
+-  passcnt=0; failcnt=0; untstcnt=0; xpasscnt=0; xfailcnt=0; kpasscnt=0; kfailcnt=0; unsupcnt=0; unrescnt=0;
++  passcnt=0; failcnt=0; untstcnt=0; xpasscnt=0; xfailcnt=0; kpasscnt=0; kfailcnt=0; unsupcnt=0; unrescnt=0; dgerrorcnt=0;
+   curvar=""; insummary=0
+ }
+ /^Running target /		{ curvar = \$3; next }
++/^ERROR: \(DejaGnu\)/		{ if (variant == curvar) dgerrorcnt += 1 }
+ /^# of /			{ if (variant == curvar) insummary = 1 }
+ /^# of expected passes/		{ if (insummary == 1) passcnt += \$5; next; }
+ /^# of unexpected successes/	{ if (insummary == 1) xpasscnt += \$5; next; }
+@@ -390,6 +391,7 @@ BEGIN {
+ { next }
+ END {
+   printf ("\t\t=== %s Summary for %s ===\n\n", tool, variant)
++  if (dgerrorcnt != 0) printf ("# of DejaGnu errors\t\t%d\n", dgerrorcnt)
+   if (passcnt != 0) printf ("# of expected passes\t\t%d\n", passcnt)
+   if (failcnt != 0) printf ("# of unexpected failures\t%d\n", failcnt)
+   if (xpasscnt != 0) printf ("# of unexpected successes\t%d\n", xpasscnt)
+@@ -419,8 +421,9 @@ TOTAL_AWK=${TMP}/total.awk
+ cat << EOF > $TOTAL_AWK
+ BEGIN {
+   tool="$TOOL"
+-  passcnt=0; failcnt=0; untstcnt=0; xpasscnt=0; xfailcnt=0; kfailcnt=0; unsupcnt=0; unrescnt=0
++  passcnt=0; failcnt=0; untstcnt=0; xpasscnt=0; xfailcnt=0; kfailcnt=0; unsupcnt=0; unrescnt=0; dgerrorcnt=0
+ }
++/^# of DejaGnu errors/		{ dgerrorcnt += \$5 }
+ /^# of expected passes/		{ passcnt += \$5 }
+ /^# of unexpected failures/	{ failcnt += \$5 }
+ /^# of unexpected successes/	{ xpasscnt += \$5 }
+@@ -431,7 +434,8 @@ BEGIN {
+ /^# of unresolved testcases/	{ unrescnt += \$5 }
+ /^# of unsupported tests/	{ unsupcnt += \$5 }
+ END {
+-  printf ("\n\t\t=== %s Summary ===\n\n", tool)
++  printf ("\n\t\t=== %s MySummary ===\n\n", tool)
++  if (dgerrorcnt != 0) printf ("# of DejaGnu errors\t\t%d\n", dgerrorcnt)
+   if (passcnt != 0) printf ("# of expected passes\t\t%d\n", passcnt)
+   if (failcnt != 0) printf ("# of unexpected failures\t%d\n", failcnt)
+   if (xpasscnt != 0) printf ("# of unexpected successes\t%d\n", xpasscnt)
+--- /dev/null
++++ b/src/gcc/LINARO-VERSION
+@@ -0,0 +1 @@
++Snapshot 6.4-2017.11
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -833,10 +833,12 @@ BASEVER     := $(srcdir)/BASE-VER  # 4.x.y
+ DEVPHASE    := $(srcdir)/DEV-PHASE # experimental, prerelease, ""
+ DATESTAMP   := $(srcdir)/DATESTAMP # YYYYMMDD or empty
+ REVISION    := $(srcdir)/REVISION  # [BRANCH revision XXXXXX]
++LINAROVER   := $(srcdir)/LINARO-VERSION # M.x-YYYY.MM[-S][~dev]
+ 
+ BASEVER_c   := $(shell cat $(BASEVER))
+ DEVPHASE_c  := $(shell cat $(DEVPHASE))
+ DATESTAMP_c := $(shell cat $(DATESTAMP))
++LINAROVER_c := $(shell cat $(LINAROVER))
+ 
+ ifeq (,$(wildcard $(REVISION)))
+ REVISION_c  :=
+@@ -863,6 +865,7 @@ DATESTAMP_s := \
+   "\"$(if $(DEVPHASE_c)$(filter-out 0,$(PATCHLEVEL_c)), $(DATESTAMP_c))\""
+ PKGVERSION_s:= "\"@PKGVERSION@\""
+ BUGURL_s    := "\"@REPORT_BUGS_TO@\""
++LINAROVER_s := "\"$(LINAROVER_c)\""
+ 
+ PKGVERSION  := @PKGVERSION@
+ BUGURL_TEXI := @REPORT_BUGS_TEXI@
+@@ -2703,8 +2706,9 @@ PREPROCESSOR_DEFINES = \
+   -DSTANDARD_EXEC_PREFIX=\"$(libdir)/gcc/\" \
+   @TARGET_SYSTEM_ROOT_DEFINE@
+ 
+-CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(BASEVER_s)
+-cppbuiltin.o: $(BASEVER)
++CFLAGS-cppbuiltin.o += $(PREPROCESSOR_DEFINES) -DBASEVER=$(BASEVER_s) \
++	-DLINAROVER=$(LINAROVER_s)
++cppbuiltin.o: $(BASEVER) $(LINAROVER)
+ 
+ CFLAGS-cppdefault.o += $(PREPROCESSOR_DEFINES)
+ 
+--- a/src/gcc/ada/gcc-interface/misc.c
++++ b/src/gcc/ada/gcc-interface/misc.c
+@@ -255,8 +255,7 @@ static bool
+ gnat_post_options (const char **pfilename ATTRIBUTE_UNUSED)
+ {
+   /* Excess precision other than "fast" requires front-end support.  */
+-  if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD
+-      && TARGET_FLT_EVAL_METHOD_NON_DEFAULT)
++  if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD)
+     sorry ("-fexcess-precision=standard for Ada");
+   flag_excess_precision_cmdline = EXCESS_PRECISION_FAST;
+ 
+--- a/src/gcc/builtins.c
++++ b/src/gcc/builtins.c
+@@ -28,6 +28,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "predict.h"
+ #include "tm_p.h"
+--- a/src/gcc/c-family/c-common.c
++++ b/src/gcc/c-family/c-common.c
+@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "function.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "c-common.h"
+ #include "gimple-expr.h"
+ #include "tm_p.h"
+--- a/src/gcc/c-family/c-opts.c
++++ b/src/gcc/c-family/c-opts.c
+@@ -772,8 +772,7 @@ c_common_post_options (const char **pfilename)
+      support.  */
+   if (c_dialect_cxx ())
+     {
+-      if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD
+-	  && TARGET_FLT_EVAL_METHOD_NON_DEFAULT)
++      if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD)
+ 	sorry ("-fexcess-precision=standard for C++");
+       flag_excess_precision_cmdline = EXCESS_PRECISION_FAST;
+     }
+--- a/src/gcc/calls.c
++++ b/src/gcc/calls.c
+@@ -194,10 +194,19 @@ prepare_call_address (tree fndecl_or_type, rtx funexp, rtx static_chain_value,
+ 	       && targetm.small_register_classes_for_mode_p (FUNCTION_MODE))
+ 	      ? force_not_mem (memory_address (FUNCTION_MODE, funexp))
+ 	      : memory_address (FUNCTION_MODE, funexp));
+-  else if (! sibcallp)
++  else
+     {
+-      if (!NO_FUNCTION_CSE && optimize && ! flag_no_function_cse)
+-	funexp = force_reg (Pmode, funexp);
++      /* funexp could be a SYMBOL_REF represents a function pointer which is
++	 of ptr_mode.  In this case, it should be converted into address mode
++	 to be a valid address for memory rtx pattern.  See PR 64971.  */
++      if (GET_MODE (funexp) != Pmode)
++	funexp = convert_memory_address (Pmode, funexp);
++
++      if (! sibcallp)
++	{
++	  if (!NO_FUNCTION_CSE && optimize && ! flag_no_function_cse)
++	    funexp = force_reg (Pmode, funexp);
++	}
+     }
+ 
+   if (static_chain_value != 0
+--- a/src/gcc/cfg.c
++++ b/src/gcc/cfg.c
+@@ -1064,7 +1064,7 @@ free_original_copy_tables (void)
+   delete bb_copy;
+   bb_copy = NULL;
+   delete bb_original;
+-  bb_copy = NULL;
++  bb_original = NULL;
+   delete loop_copy;
+   loop_copy = NULL;
+   delete original_copy_bb_pool;
+--- a/src/gcc/common/config/arm/arm-common.c
++++ b/src/gcc/common/config/arm/arm-common.c
+@@ -97,6 +97,49 @@ arm_rewrite_mcpu (int argc, const char **argv)
+   return arm_rewrite_selected_cpu (argv[argc - 1]);
+ }
+ 
++struct arm_arch_core_flag
++{
++  const char *const name;
++  const arm_feature_set flags;
++};
++
++static const struct arm_arch_core_flag arm_arch_core_flags[] =
++{
++#undef ARM_CORE
++#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
++  {NAME, FLAGS},
++#include "config/arm/arm-cores.def"
++#undef ARM_CORE
++#undef ARM_ARCH
++#define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
++  {NAME, FLAGS},
++#include "config/arm/arm-arches.def"
++#undef ARM_ARCH
++};
++
++/* Called by the driver to check whether the target denoted by current
++   command line options is a Thumb-only target.  ARGV is an array of
++   -march and -mcpu values (ie. it contains the rhs after the equal
++   sign) and we use the last one of them to make a decision.  The
++   number of elements in ARGV is given in ARGC.  */
++const char *
++arm_target_thumb_only (int argc, const char **argv)
++{
++  unsigned int opt;
++
++  if (argc)
++    {
++      for (opt = 0; opt < (ARRAY_SIZE (arm_arch_core_flags)); opt++)
++	if ((strcmp (argv[argc - 1], arm_arch_core_flags[opt].name) == 0)
++	    && !ARM_FSET_HAS_CPU1(arm_arch_core_flags[opt].flags, FL_NOTM))
++	  return "-mthumb";
++
++      return NULL;
++    }
++  else
++    return NULL;
++}
++
+ #undef ARM_CPU_NAME_LENGTH
+ 
+ 
+--- a/src/gcc/config.gcc
++++ b/src/gcc/config.gcc
+@@ -307,7 +307,7 @@ m32c*-*-*)
+         ;;
+ aarch64*-*-*)
+ 	cpu_type=aarch64
+-	extra_headers="arm_neon.h arm_acle.h"
++	extra_headers="arm_fp16.h arm_neon.h arm_acle.h"
+ 	c_target_objs="aarch64-c.o"
+ 	cxx_target_objs="aarch64-c.o"
+ 	extra_objs="aarch64-builtins.o aarch-common.o cortex-a57-fma-steering.o"
+@@ -327,7 +327,7 @@ arc*-*-*)
+ arm*-*-*)
+ 	cpu_type=arm
+ 	extra_objs="arm-builtins.o aarch-common.o"
+-	extra_headers="mmintrin.h arm_neon.h arm_acle.h"
++	extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h"
+ 	target_type_format_char='%'
+ 	c_target_objs="arm-c.o"
+ 	cxx_target_objs="arm-c.o"
+@@ -573,7 +573,7 @@ x86_64-*-*)
+ 	tm_file="vxworks-dummy.h ${tm_file}"
+ 	;;
+ arm*-*-*)
+-	tm_p_file="${tm_p_file} arm/aarch-common-protos.h"
++	tm_p_file="arm/arm-flags.h ${tm_p_file} arm/aarch-common-protos.h"
+ 	tm_file="vxworks-dummy.h ${tm_file}"
+ 	;;
+ mips*-*-* | sh*-*-* | sparc*-*-*)
+@@ -1504,7 +1504,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i
+ 		extra_options="${extra_options} linux-android.opt"
+ 		# Assume modern glibc if not targeting Android nor uclibc.
+ 		case ${target} in
+-		*-*-*android*|*-*-*uclibc*)
++		*-*-*android*|*-*-*uclibc*|*-*-*musl*)
+ 		  ;;
+ 		*)
+ 		  default_gnu_indirect_function=yes
+@@ -1573,7 +1573,7 @@ x86_64-*-linux* | x86_64-*-kfreebsd*-gnu | x86_64-*-knetbsd*-gnu)
+ 		extra_options="${extra_options} linux-android.opt"
+ 		# Assume modern glibc if not targeting Android nor uclibc.
+ 		case ${target} in
+-		*-*-*android*|*-*-*uclibc*)
++		*-*-*android*|*-*-*uclibc*|*-*-*musl*)
+ 		  ;;
+ 		*)
+ 		  default_gnu_indirect_function=yes
+@@ -3815,38 +3815,51 @@ case "${target}" in
+ 		# Add extra multilibs
+ 		if test "x$with_multilib_list" != x; then
+ 			arm_multilibs=`echo $with_multilib_list | sed -e 's/,/ /g'`
+-			for arm_multilib in ${arm_multilibs}; do
+-				case ${arm_multilib} in
+-				aprofile)
++			case ${arm_multilibs} in
++			aprofile)
+ 				# Note that arm/t-aprofile is a
+ 				# stand-alone make file fragment to be
+ 				# used only with itself.  We do not
+ 				# specifically use the
+ 				# TM_MULTILIB_OPTION framework because
+ 				# this shorthand is more
+-				# pragmatic. Additionally it is only
+-				# designed to work without any
+-				# with-cpu, with-arch with-mode
+-				# with-fpu or with-float options.
+-					if test "x$with_arch" != x \
+-					    || test "x$with_cpu" != x \
+-					    || test "x$with_float" != x \
+-					    || test "x$with_fpu" != x \
+-					    || test "x$with_mode" != x ; then
+-					    echo "Error: You cannot use any of --with-arch/cpu/fpu/float/mode with --with-multilib-list=aprofile" 1>&2
+-					    exit 1
+-					fi
+-					tmake_file="${tmake_file} arm/t-aprofile"
+-					break
+-					;;
+-				default)
+-					;;
+-				*)
+-					echo "Error: --with-multilib-list=${with_multilib_list} not supported." 1>&2
+-					exit 1
+-					;;
+-				esac
+-			done
++				# pragmatic.
++				tmake_profile_file="arm/t-aprofile"
++				;;
++			rmprofile)
++				# Note that arm/t-rmprofile is a
++				# stand-alone make file fragment to be
++				# used only with itself.  We do not
++				# specifically use the
++				# TM_MULTILIB_OPTION framework because
++				# this shorthand is more
++				# pragmatic.
++				tmake_profile_file="arm/t-rmprofile"
++				;;
++			default)
++				;;
++			*)
++				echo "Error: --with-multilib-list=${with_multilib_list} not supported." 1>&2
++				exit 1
++				;;
++			esac
++
++			if test "x${tmake_profile_file}" != x ; then
++				# arm/t-aprofile and arm/t-rmprofile are only
++				# designed to work without any with-cpu,
++				# with-arch, with-mode, with-fpu or with-float
++				# options.
++				if test "x$with_arch" != x \
++				    || test "x$with_cpu" != x \
++				    || test "x$with_float" != x \
++				    || test "x$with_fpu" != x \
++				    || test "x$with_mode" != x ; then
++				    echo "Error: You cannot use any of --with-arch/cpu/fpu/float/mode with --with-multilib-list=${with_multilib_list}" 1>&2
++				    exit 1
++				fi
++
++				tmake_file="${tmake_file} ${tmake_profile_file}"
++			fi
+ 		fi
+ 		;;
+ 
+--- a/src/gcc/config/aarch64/aarch64-arches.def
++++ b/src/gcc/config/aarch64/aarch64-arches.def
+@@ -32,4 +32,6 @@
+ 
+ AARCH64_ARCH("armv8-a",	      generic,	     8A,	8,  AARCH64_FL_FOR_ARCH8)
+ AARCH64_ARCH("armv8.1-a",     generic,	     8_1A,	8,  AARCH64_FL_FOR_ARCH8_1)
++AARCH64_ARCH("armv8.2-a",     generic,	     8_2A,	8,  AARCH64_FL_FOR_ARCH8_2)
++AARCH64_ARCH("armv8.3-a",     generic,	     8_3A,	8,  AARCH64_FL_FOR_ARCH8_3)
+ 
+--- a/src/gcc/config/aarch64/aarch64-builtins.c
++++ b/src/gcc/config/aarch64/aarch64-builtins.c
+@@ -62,6 +62,7 @@
+ #define si_UP    SImode
+ #define sf_UP    SFmode
+ #define hi_UP    HImode
++#define hf_UP    HFmode
+ #define qi_UP    QImode
+ #define UP(X) X##_UP
+ 
+@@ -139,6 +140,10 @@ aarch64_types_binop_ssu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_none, qualifier_none, qualifier_unsigned };
+ #define TYPES_BINOP_SSU (aarch64_types_binop_ssu_qualifiers)
+ static enum aarch64_type_qualifiers
++aarch64_types_binop_uss_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_unsigned, qualifier_none, qualifier_none };
++#define TYPES_BINOP_USS (aarch64_types_binop_uss_qualifiers)
++static enum aarch64_type_qualifiers
+ aarch64_types_binopp_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_poly, qualifier_poly, qualifier_poly };
+ #define TYPES_BINOPP (aarch64_types_binopp_qualifiers)
+@@ -163,6 +168,10 @@ aarch64_types_quadop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+       qualifier_none, qualifier_lane_index };
+ #define TYPES_QUADOP_LANE (aarch64_types_quadop_lane_qualifiers)
+ 
++static enum aarch64_type_qualifiers
++aarch64_types_binop_imm_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_poly, qualifier_none, qualifier_immediate };
++#define TYPES_GETREGP (aarch64_types_binop_imm_p_qualifiers)
+ static enum aarch64_type_qualifiers
+ aarch64_types_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_none, qualifier_none, qualifier_immediate };
+@@ -173,16 +182,29 @@ aarch64_types_shift_to_unsigned_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_unsigned, qualifier_none, qualifier_immediate };
+ #define TYPES_SHIFTIMM_USS (aarch64_types_shift_to_unsigned_qualifiers)
+ static enum aarch64_type_qualifiers
++aarch64_types_fcvt_from_unsigned_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_none, qualifier_unsigned, qualifier_immediate };
++#define TYPES_FCVTIMM_SUS (aarch64_types_fcvt_from_unsigned_qualifiers)
++static enum aarch64_type_qualifiers
+ aarch64_types_unsigned_shift_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate };
+ #define TYPES_USHIFTIMM (aarch64_types_unsigned_shift_qualifiers)
+ 
+ static enum aarch64_type_qualifiers
+-aarch64_types_ternop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+-  = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate };
+-#define TYPES_SETREG (aarch64_types_ternop_imm_qualifiers)
+-#define TYPES_SHIFTINSERT (aarch64_types_ternop_imm_qualifiers)
+-#define TYPES_SHIFTACC (aarch64_types_ternop_imm_qualifiers)
++aarch64_types_ternop_s_imm_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_none, qualifier_none, qualifier_poly, qualifier_immediate};
++#define TYPES_SETREGP (aarch64_types_ternop_s_imm_p_qualifiers)
++static enum aarch64_type_qualifiers
++aarch64_types_ternop_s_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate};
++#define TYPES_SETREG (aarch64_types_ternop_s_imm_qualifiers)
++#define TYPES_SHIFTINSERT (aarch64_types_ternop_s_imm_qualifiers)
++#define TYPES_SHIFTACC (aarch64_types_ternop_s_imm_qualifiers)
++
++static enum aarch64_type_qualifiers
++aarch64_types_ternop_p_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_poly, qualifier_poly, qualifier_poly, qualifier_immediate};
++#define TYPES_SHIFTINSERTP (aarch64_types_ternop_p_imm_qualifiers)
+ 
+ static enum aarch64_type_qualifiers
+ aarch64_types_unsigned_shiftacc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+@@ -196,6 +218,11 @@ aarch64_types_combine_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_none, qualifier_none, qualifier_none };
+ #define TYPES_COMBINE (aarch64_types_combine_qualifiers)
+ 
++static enum aarch64_type_qualifiers
++aarch64_types_combine_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_poly, qualifier_poly, qualifier_poly };
++#define TYPES_COMBINEP (aarch64_types_combine_p_qualifiers)
++
+ static enum aarch64_type_qualifiers
+ aarch64_types_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_none, qualifier_const_pointer_map_mode };
+@@ -229,6 +256,10 @@ aarch64_types_bsl_u_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+    qualifier_map_mode | qualifier_pointer to build a pointer to the
+    element type of the vector.  */
+ static enum aarch64_type_qualifiers
++aarch64_types_store1_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
++  = { qualifier_void, qualifier_pointer_map_mode, qualifier_poly };
++#define TYPES_STORE1P (aarch64_types_store1_p_qualifiers)
++static enum aarch64_type_qualifiers
+ aarch64_types_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+   = { qualifier_void, qualifier_pointer_map_mode, qualifier_none };
+ #define TYPES_STORE1 (aarch64_types_store1_qualifiers)
+@@ -753,16 +784,16 @@ aarch64_init_simd_builtins (void)
+ 
+ 	  if (qualifiers & qualifier_unsigned)
+ 	    {
+-	      type_signature[arg_num] = 'u';
++	      type_signature[op_num] = 'u';
+ 	      print_type_signature_p = true;
+ 	    }
+ 	  else if (qualifiers & qualifier_poly)
+ 	    {
+-	      type_signature[arg_num] = 'p';
++	      type_signature[op_num] = 'p';
+ 	      print_type_signature_p = true;
+ 	    }
+ 	  else
+-	    type_signature[arg_num] = 's';
++	    type_signature[op_num] = 's';
+ 
+ 	  /* Skip an internal operand for vget_{low, high}.  */
+ 	  if (qualifiers & qualifier_internal)
+--- a/src/gcc/config/aarch64/aarch64-c.c
++++ b/src/gcc/config/aarch64/aarch64-c.c
+@@ -95,6 +95,11 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
+   else
+     cpp_undef (pfile, "__ARM_FP");
+ 
++  aarch64_def_or_undef (TARGET_FP_F16INST,
++			"__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", pfile);
++  aarch64_def_or_undef (TARGET_SIMD_F16INST,
++			"__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", pfile);
++
+   aarch64_def_or_undef (TARGET_SIMD, "__ARM_FEATURE_NUMERIC_MAXMIN", pfile);
+   aarch64_def_or_undef (TARGET_SIMD, "__ARM_NEON", pfile);
+ 
+--- a/src/gcc/config/aarch64/aarch64-cores.def
++++ b/src/gcc/config/aarch64/aarch64-cores.def
+@@ -40,17 +40,33 @@
+ 
+ /* V8 Architecture Processors.  */
+ 
++/* ARM ('A') cores. */
+ AARCH64_CORE("cortex-a35",  cortexa35, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa35, "0x41", "0xd04")
+ AARCH64_CORE("cortex-a53",  cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53, "0x41", "0xd03")
+ AARCH64_CORE("cortex-a57",  cortexa57, cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07")
+ AARCH64_CORE("cortex-a72",  cortexa72, cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08")
++AARCH64_CORE("cortex-a73",  cortexa73, cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, "0x41", "0xd09")
++
++/* Samsung ('S') cores. */
+ AARCH64_CORE("exynos-m1",   exynosm1,  exynosm1,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1,  "0x53", "0x001")
+-AARCH64_CORE("qdf24xx",     qdf24xx,   cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57, "0x51", "0x800")
++
++/* Qualcomm ('Q') cores. */
++AARCH64_CORE("qdf24xx",     qdf24xx,   cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx,   "0x51", "0x800")
++
++/* Cavium ('C') cores. */
+ AARCH64_CORE("thunderx",    thunderx,  thunderx,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx,  "0x43", "0x0a1")
++
++/* APM ('P') cores. */
+ AARCH64_CORE("xgene1",      xgene1,    xgene1,    8A,  AARCH64_FL_FOR_ARCH8, xgene1, "0x50", "0x000")
+ 
++/* V8.1 Architecture Processors.  */
++
++/* Broadcom ('B') cores. */
++AARCH64_CORE("vulcan",  vulcan, cortexa57, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, vulcan, "0x42", "0x516")
++
+ /* V8 big.LITTLE implementations.  */
+ 
+ AARCH64_CORE("cortex-a57.cortex-a53",  cortexa57cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07.0xd03")
+ AARCH64_CORE("cortex-a72.cortex-a53",  cortexa72cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08.0xd03")
+-
++AARCH64_CORE("cortex-a73.cortex-a35",  cortexa73cortexa35, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, "0x41", "0xd09.0xd04")
++AARCH64_CORE("cortex-a73.cortex-a53",  cortexa73cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, "0x41", "0xd09.0xd03")
+--- a/src/gcc/config/aarch64/aarch64-cost-tables.h
++++ b/src/gcc/config/aarch64/aarch64-cost-tables.h
+@@ -127,6 +127,108 @@ const struct cpu_cost_table thunderx_extra_costs =
+   }
+ };
+ 
++const struct cpu_cost_table vulcan_extra_costs =
++{
++  /* ALU */
++  {
++    0,			/* Arith.  */
++    0,			/* Logical.  */
++    0,			/* Shift.  */
++    0,			/* Shift_reg.  */
++    COSTS_N_INSNS (1),	/* Arith_shift.  */
++    COSTS_N_INSNS (1),	/* Arith_shift_reg.  */
++    COSTS_N_INSNS (1),	/* Log_shift.  */
++    COSTS_N_INSNS (1),	/* Log_shift_reg.  */
++    0,			/* Extend.  */
++    COSTS_N_INSNS (1),	/* Extend_arith.  */
++    0,			/* Bfi.  */
++    0,			/* Bfx.  */
++    COSTS_N_INSNS (3),	/* Clz.  */
++    0,			/* Rev.  */
++    0,			/* Non_exec.  */
++    true		/* Non_exec_costs_exec.  */
++  },
++  {
++    /* MULT SImode */
++    {
++      COSTS_N_INSNS (4),	/* Simple.  */
++      COSTS_N_INSNS (4),	/* Flag_setting.  */
++      COSTS_N_INSNS (4),	/* Extend.  */
++      COSTS_N_INSNS (5),	/* Add.  */
++      COSTS_N_INSNS (5),	/* Extend_add.  */
++      COSTS_N_INSNS (18)	/* Idiv.  */
++    },
++    /* MULT DImode */
++    {
++      COSTS_N_INSNS (4),       /* Simple.  */
++      0,                       /* Flag_setting.  */
++      COSTS_N_INSNS (4),       /* Extend.  */
++      COSTS_N_INSNS (5),       /* Add.  */
++      COSTS_N_INSNS (5),       /* Extend_add.  */
++      COSTS_N_INSNS (26)       /* Idiv.  */
++    }
++  },
++  /* LD/ST */
++  {
++    COSTS_N_INSNS (4),	/* Load.  */
++    COSTS_N_INSNS (4),	/* Load_sign_extend.  */
++    COSTS_N_INSNS (5),	/* Ldrd.  */
++    COSTS_N_INSNS (4),	/* Ldm_1st.  */
++    1,			/* Ldm_regs_per_insn_1st.  */
++    1,			/* Ldm_regs_per_insn_subsequent.  */
++    COSTS_N_INSNS (4),	/* Loadf.  */
++    COSTS_N_INSNS (4),	/* Loadd.  */
++    COSTS_N_INSNS (4),	/* Load_unaligned.  */
++    0,			/* Store.  */
++    0,			/* Strd.  */
++    0,			/* Stm_1st.  */
++    1,			/* Stm_regs_per_insn_1st.  */
++    1,			/* Stm_regs_per_insn_subsequent.  */
++    0,			/* Storef.  */
++    0,			/* Stored.  */
++    0,			/* Store_unaligned.  */
++    COSTS_N_INSNS (1),	/* Loadv.  */
++    COSTS_N_INSNS (1)	/* Storev.  */
++  },
++  {
++    /* FP SFmode */
++    {
++      COSTS_N_INSNS (4),	/* Div.  */
++      COSTS_N_INSNS (1),	/* Mult.  */
++      COSTS_N_INSNS (1),	/* Mult_addsub. */
++      COSTS_N_INSNS (1),	/* Fma.  */
++      COSTS_N_INSNS (1),	/* Addsub.  */
++      COSTS_N_INSNS (1),	/* Fpconst. */
++      COSTS_N_INSNS (1),	/* Neg.  */
++      COSTS_N_INSNS (1),	/* Compare.  */
++      COSTS_N_INSNS (2),	/* Widen.  */
++      COSTS_N_INSNS (2),	/* Narrow.  */
++      COSTS_N_INSNS (2),	/* Toint.  */
++      COSTS_N_INSNS (2),	/* Fromint.  */
++      COSTS_N_INSNS (2) 	/* Roundint.  */
++    },
++    /* FP DFmode */
++    {
++      COSTS_N_INSNS (6),	/* Div.  */
++      COSTS_N_INSNS (1),	/* Mult.  */
++      COSTS_N_INSNS (1),	/* Mult_addsub.  */
++      COSTS_N_INSNS (1),	/* Fma.  */
++      COSTS_N_INSNS (1),	/* Addsub.  */
++      COSTS_N_INSNS (1),	/* Fpconst.  */
++      COSTS_N_INSNS (1),	/* Neg.  */
++      COSTS_N_INSNS (1),	/* Compare.  */
++      COSTS_N_INSNS (2),	/* Widen.  */
++      COSTS_N_INSNS (2),	/* Narrow.  */
++      COSTS_N_INSNS (2),	/* Toint.  */
++      COSTS_N_INSNS (2),	/* Fromint.  */
++      COSTS_N_INSNS (2) 	/* Roundint.  */
++    }
++  },
++  /* Vector */
++  {
++    COSTS_N_INSNS (1)	/* Alu.  */
++  }
++};
+ 
+ 
+ #endif
+--- a/src/gcc/config/aarch64/aarch64-elf.h
++++ b/src/gcc/config/aarch64/aarch64-elf.h
+@@ -25,15 +25,6 @@
+ #define ASM_OUTPUT_LABELREF(FILE, NAME) \
+   aarch64_asm_output_labelref (FILE, NAME)
+ 
+-#define ASM_OUTPUT_DEF(FILE, NAME1, NAME2)	\
+-  do						\
+-    {						\
+-      assemble_name (FILE, NAME1);		\
+-      fputs (" = ", FILE);			\
+-      assemble_name (FILE, NAME2);		\
+-      fputc ('\n', FILE);			\
+-    } while (0)
+-
+ #define TEXT_SECTION_ASM_OP	"\t.text"
+ #define DATA_SECTION_ASM_OP	"\t.data"
+ #define BSS_SECTION_ASM_OP	"\t.bss"
+--- a/src/gcc/config/aarch64/aarch64-modes.def
++++ b/src/gcc/config/aarch64/aarch64-modes.def
+@@ -21,8 +21,6 @@
+ CC_MODE (CCFP);
+ CC_MODE (CCFPE);
+ CC_MODE (CC_SWP);
+-CC_MODE (CC_ZESWP); /* zero-extend LHS (but swap to make it RHS).  */
+-CC_MODE (CC_SESWP); /* sign-extend LHS (but swap to make it RHS).  */
+ CC_MODE (CC_NZ);    /* Only N and Z bits of condition flags are valid.  */
+ CC_MODE (CC_Z);     /* Only Z bit of condition flags is valid.  */
+ CC_MODE (CC_C);     /* Only C bit of condition flags is valid.  */
+--- a/src/gcc/config/aarch64/aarch64-option-extensions.def
++++ b/src/gcc/config/aarch64/aarch64-option-extensions.def
+@@ -39,8 +39,8 @@
+    that are required.  Their order is not important.  */
+ 
+ /* Enabling "fp" just enables "fp".
+-   Disabling "fp" also disables "simd", "crypto".  */
+-AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO, "fp")
++   Disabling "fp" also disables "simd", "crypto" and "fp16".  */
++AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO | AARCH64_FL_F16, "fp")
+ 
+ /* Enabling "simd" also enables "fp".
+    Disabling "simd" also disables "crypto".  */
+@@ -55,3 +55,7 @@ AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, "crc32")
+ 
+ /* Enabling or disabling "lse" only changes "lse".  */
+ AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, "atomics")
++
++/* Enabling "fp16" also enables "fp".
++   Disabling "fp16" just disables "fp16".  */
++AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, 0, "fp16")
+--- /dev/null
++++ b/src/gcc/config/aarch64/aarch64-passes.def
+@@ -0,0 +1,21 @@
++/* AArch64-specific passes declarations.
++   Copyright (C) 2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3, or (at your option)
++   any later version.
++
++   GCC is distributed in the hope that it will be useful, but
++   WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with GCC; see the file COPYING3.  If not see
++   <http://www.gnu.org/licenses/>.  */
++
++INSERT_PASS_AFTER (pass_regrename, 1, pass_fma_steering);
+--- a/src/gcc/config/aarch64/aarch64-protos.h
++++ b/src/gcc/config/aarch64/aarch64-protos.h
+@@ -151,11 +151,17 @@ struct cpu_regmove_cost
+ /* Cost for vector insn classes.  */
+ struct cpu_vector_cost
+ {
+-  const int scalar_stmt_cost;		 /* Cost of any scalar operation,
++  const int scalar_int_stmt_cost;	 /* Cost of any int scalar operation,
++					    excluding load and store.  */
++  const int scalar_fp_stmt_cost;	 /* Cost of any fp scalar operation,
+ 					    excluding load and store.  */
+   const int scalar_load_cost;		 /* Cost of scalar load.  */
+   const int scalar_store_cost;		 /* Cost of scalar store.  */
+-  const int vec_stmt_cost;		 /* Cost of any vector operation,
++  const int vec_int_stmt_cost;		 /* Cost of any int vector operation,
++					    excluding load, store, permute,
++					    vector-to-scalar and
++					    scalar-to-vector operation.  */
++  const int vec_fp_stmt_cost;		 /* Cost of any fp vector operation,
+ 					    excluding load, store, permute,
+ 					    vector-to-scalar and
+ 					    scalar-to-vector operation.  */
+@@ -178,6 +184,25 @@ struct cpu_branch_cost
+   const int unpredictable;  /* Unpredictable branch or optimizing for speed.  */
+ };
+ 
++/* Control approximate alternatives to certain FP operators.  */
++#define AARCH64_APPROX_MODE(MODE) \
++  ((MIN_MODE_FLOAT <= (MODE) && (MODE) <= MAX_MODE_FLOAT) \
++   ? (1 << ((MODE) - MIN_MODE_FLOAT)) \
++   : (MIN_MODE_VECTOR_FLOAT <= (MODE) && (MODE) <= MAX_MODE_VECTOR_FLOAT) \
++     ? (1 << ((MODE) - MIN_MODE_VECTOR_FLOAT \
++	      + MAX_MODE_FLOAT - MIN_MODE_FLOAT + 1)) \
++     : (0))
++#define AARCH64_APPROX_NONE (0)
++#define AARCH64_APPROX_ALL (-1)
++
++/* Allowed modes for approximations.  */
++struct cpu_approx_modes
++{
++  const unsigned int division;		/* Division.  */
++  const unsigned int sqrt;		/* Square root.  */
++  const unsigned int recip_sqrt;	/* Reciprocal square root.  */
++};
++
+ struct tune_params
+ {
+   const struct cpu_cost_table *insn_extra_cost;
+@@ -185,6 +210,7 @@ struct tune_params
+   const struct cpu_regmove_cost *regmove_cost;
+   const struct cpu_vector_cost *vec_costs;
+   const struct cpu_branch_cost *branch_costs;
++  const struct cpu_approx_modes *approx_modes;
+   int memmov_cost;
+   int issue_rate;
+   unsigned int fusible_ops;
+@@ -282,14 +308,14 @@ int aarch64_get_condition_code (rtx);
+ bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode);
+ int aarch64_branch_cost (bool, bool);
+ enum aarch64_symbol_type aarch64_classify_symbolic_expression (rtx);
+-bool aarch64_cannot_change_mode_class (machine_mode,
+-				       machine_mode,
+-				       enum reg_class);
+ bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
+ bool aarch64_constant_address_p (rtx);
++bool aarch64_emit_approx_div (rtx, rtx, rtx);
++bool aarch64_emit_approx_sqrt (rtx, rtx, bool);
+ bool aarch64_expand_movmem (rtx *);
+ bool aarch64_float_const_zero_rtx_p (rtx);
+ bool aarch64_function_arg_regno_p (unsigned);
++bool aarch64_fusion_enabled_p (enum aarch64_fusion_pairs);
+ bool aarch64_gen_movmemqi (rtx *);
+ bool aarch64_gimple_fold_builtin (gimple_stmt_iterator *);
+ bool aarch64_is_extend_from_extract (machine_mode, rtx, rtx);
+@@ -298,6 +324,7 @@ bool aarch64_is_noplt_call_p (rtx);
+ bool aarch64_label_mentioned_p (rtx);
+ void aarch64_declare_function_name (FILE *, const char*, tree);
+ bool aarch64_legitimate_pic_operand_p (rtx);
++bool aarch64_mask_and_shift_for_ubfiz_p (machine_mode, rtx, rtx);
+ bool aarch64_modes_tieable_p (machine_mode mode1,
+ 			      machine_mode mode2);
+ bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx);
+@@ -320,6 +347,7 @@ bool aarch64_simd_scalar_immediate_valid_for_move (rtx, machine_mode);
+ bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool);
+ bool aarch64_simd_valid_immediate (rtx, machine_mode, bool,
+ 				   struct simd_immediate_info *);
++bool aarch64_split_dimode_const_store (rtx, rtx);
+ bool aarch64_symbolic_address_p (rtx);
+ bool aarch64_uimm12_shift (HOST_WIDE_INT);
+ bool aarch64_use_return_insn_p (void);
+@@ -335,11 +363,9 @@ machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
+ 						       machine_mode);
+ int aarch64_hard_regno_mode_ok (unsigned, machine_mode);
+ int aarch64_hard_regno_nregs (unsigned, machine_mode);
+-int aarch64_simd_attr_length_move (rtx_insn *);
+ int aarch64_uxt_size (int, HOST_WIDE_INT);
+ int aarch64_vec_fpconst_pow_of_2 (rtx);
+ rtx aarch64_eh_return_handler_rtx (void);
+-rtx aarch64_legitimize_reload_address (rtx *, machine_mode, int, int, int);
+ rtx aarch64_mask_from_zextract_ops (rtx, rtx);
+ const char *aarch64_output_move_struct (rtx *operands);
+ rtx aarch64_return_addr (int, rtx);
+@@ -352,7 +378,6 @@ unsigned aarch64_dbx_register_number (unsigned);
+ unsigned aarch64_trampoline_size (void);
+ void aarch64_asm_output_labelref (FILE *, const char *);
+ void aarch64_cpu_cpp_builtins (cpp_reader *);
+-void aarch64_elf_asm_named_section (const char *, unsigned, tree);
+ const char * aarch64_gen_far_branch (rtx *, int, const char *, const char *);
+ const char * aarch64_output_probe_stack_range (rtx, rtx);
+ void aarch64_err_no_fpadvsimd (machine_mode, const char *);
+@@ -369,7 +394,6 @@ void aarch64_register_pragmas (void);
+ void aarch64_relayout_simd_types (void);
+ void aarch64_reset_previous_fndecl (void);
+ void aarch64_save_restore_target_globals (tree);
+-void aarch64_emit_approx_rsqrt (rtx, rtx);
+ 
+ /* Initialize builtins for SIMD intrinsics.  */
+ void init_aarch64_simd_builtins (void);
+@@ -436,7 +460,6 @@ int aarch64_ccmp_mode_to_code (enum machine_mode mode);
+ bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);
+ bool aarch64_operands_ok_for_ldpstp (rtx *, bool, enum machine_mode);
+ bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, enum machine_mode);
+-extern bool aarch64_nopcrelative_literal_loads;
+ 
+ extern void aarch64_asm_output_pool_epilogue (FILE *, const char *,
+ 					      tree, HOST_WIDE_INT);
+@@ -450,4 +473,6 @@ enum aarch64_parse_opt_result aarch64_parse_extension (const char *,
+ std::string aarch64_get_extension_string_for_isa_flags (unsigned long,
+ 							unsigned long);
+ 
++rtl_opt_pass *make_pass_fma_steering (gcc::context *ctxt);
++
+ #endif /* GCC_AARCH64_PROTOS_H */
+--- a/src/gcc/config/aarch64/aarch64-simd-builtins.def
++++ b/src/gcc/config/aarch64/aarch64-simd-builtins.def
+@@ -40,9 +40,10 @@
+    10 - CODE_FOR_<name><mode>.  */
+ 
+   BUILTIN_VDC (COMBINE, combine, 0)
++  VAR1 (COMBINEP, combine, 0, di)
+   BUILTIN_VB (BINOP, pmul, 0)
+-  BUILTIN_VALLF (BINOP, fmulx, 0)
+-  BUILTIN_VDQF_DF (UNOP, sqrt, 2)
++  BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0)
++  BUILTIN_VHSDF_DF (UNOP, sqrt, 2)
+   BUILTIN_VD_BHSI (BINOP, addp, 0)
+   VAR1 (UNOP, addp, 0, di)
+   BUILTIN_VDQ_BHSI (UNOP, clrsb, 2)
+@@ -68,14 +69,23 @@
+   BUILTIN_VDC (GETREG, get_dregoi, 0)
+   BUILTIN_VDC (GETREG, get_dregci, 0)
+   BUILTIN_VDC (GETREG, get_dregxi, 0)
++  VAR1 (GETREGP, get_dregoi, 0, di)
++  VAR1 (GETREGP, get_dregci, 0, di)
++  VAR1 (GETREGP, get_dregxi, 0, di)
+   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
+   BUILTIN_VQ (GETREG, get_qregoi, 0)
+   BUILTIN_VQ (GETREG, get_qregci, 0)
+   BUILTIN_VQ (GETREG, get_qregxi, 0)
++  VAR1 (GETREGP, get_qregoi, 0, v2di)
++  VAR1 (GETREGP, get_qregci, 0, v2di)
++  VAR1 (GETREGP, get_qregxi, 0, v2di)
+   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
+   BUILTIN_VQ (SETREG, set_qregoi, 0)
+   BUILTIN_VQ (SETREG, set_qregci, 0)
+   BUILTIN_VQ (SETREG, set_qregxi, 0)
++  VAR1 (SETREGP, set_qregoi, 0, v2di)
++  VAR1 (SETREGP, set_qregci, 0, v2di)
++  VAR1 (SETREGP, set_qregxi, 0, v2di)
+   /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>.  */
+   BUILTIN_VDC (LOADSTRUCT, ld2, 0)
+   BUILTIN_VDC (LOADSTRUCT, ld3, 0)
+@@ -224,6 +234,7 @@
+   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
+   BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0)
+   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
++  VAR2 (SHIFTINSERTP, ssli_n, 0, di, v2di)
+   BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0)
+   /* Implemented by aarch64_<sur>qshl<u>_n<mode>.  */
+   BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0)
+@@ -234,105 +245,145 @@
+   BUILTIN_VALL (UNOP, reduc_plus_scal_, 10)
+ 
+   /* Implemented by reduc_<maxmin_uns>_scal_<mode> (producing scalar).  */
+-  BUILTIN_VDQIF (UNOP, reduc_smax_scal_, 10)
+-  BUILTIN_VDQIF (UNOP, reduc_smin_scal_, 10)
++  BUILTIN_VDQIF_F16 (UNOP, reduc_smax_scal_, 10)
++  BUILTIN_VDQIF_F16 (UNOP, reduc_smin_scal_, 10)
+   BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10)
+   BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10)
+-  BUILTIN_VDQF (UNOP, reduc_smax_nan_scal_, 10)
+-  BUILTIN_VDQF (UNOP, reduc_smin_nan_scal_, 10)
++  BUILTIN_VHSDF (UNOP, reduc_smax_nan_scal_, 10)
++  BUILTIN_VHSDF (UNOP, reduc_smin_nan_scal_, 10)
+ 
+-  /* Implemented by <maxmin><mode>3.
++  /* Implemented by <maxmin_uns><mode>3.
+      smax variants map to fmaxnm,
+      smax_nan variants map to fmax.  */
+   BUILTIN_VDQ_BHSI (BINOP, smax, 3)
+   BUILTIN_VDQ_BHSI (BINOP, smin, 3)
+   BUILTIN_VDQ_BHSI (BINOP, umax, 3)
+   BUILTIN_VDQ_BHSI (BINOP, umin, 3)
+-  BUILTIN_VDQF (BINOP, smax_nan, 3)
+-  BUILTIN_VDQF (BINOP, smin_nan, 3)
++  BUILTIN_VHSDF_DF (BINOP, smax_nan, 3)
++  BUILTIN_VHSDF_DF (BINOP, smin_nan, 3)
+ 
+-  /* Implemented by <fmaxmin><mode>3.  */
+-  BUILTIN_VDQF (BINOP, fmax, 3)
+-  BUILTIN_VDQF (BINOP, fmin, 3)
++  /* Implemented by <maxmin_uns><mode>3.  */
++  BUILTIN_VHSDF_HSDF (BINOP, fmax, 3)
++  BUILTIN_VHSDF_HSDF (BINOP, fmin, 3)
+ 
+   /* Implemented by aarch64_<maxmin_uns>p<mode>.  */
+   BUILTIN_VDQ_BHSI (BINOP, smaxp, 0)
+   BUILTIN_VDQ_BHSI (BINOP, sminp, 0)
+   BUILTIN_VDQ_BHSI (BINOP, umaxp, 0)
+   BUILTIN_VDQ_BHSI (BINOP, uminp, 0)
+-  BUILTIN_VDQF (BINOP, smaxp, 0)
+-  BUILTIN_VDQF (BINOP, sminp, 0)
+-  BUILTIN_VDQF (BINOP, smax_nanp, 0)
+-  BUILTIN_VDQF (BINOP, smin_nanp, 0)
++  BUILTIN_VHSDF (BINOP, smaxp, 0)
++  BUILTIN_VHSDF (BINOP, sminp, 0)
++  BUILTIN_VHSDF (BINOP, smax_nanp, 0)
++  BUILTIN_VHSDF (BINOP, smin_nanp, 0)
+ 
+   /* Implemented by <frint_pattern><mode>2.  */
+-  BUILTIN_VDQF (UNOP, btrunc, 2)
+-  BUILTIN_VDQF (UNOP, ceil, 2)
+-  BUILTIN_VDQF (UNOP, floor, 2)
+-  BUILTIN_VDQF (UNOP, nearbyint, 2)
+-  BUILTIN_VDQF (UNOP, rint, 2)
+-  BUILTIN_VDQF (UNOP, round, 2)
+-  BUILTIN_VDQF_DF (UNOP, frintn, 2)
++  BUILTIN_VHSDF (UNOP, btrunc, 2)
++  BUILTIN_VHSDF (UNOP, ceil, 2)
++  BUILTIN_VHSDF (UNOP, floor, 2)
++  BUILTIN_VHSDF (UNOP, nearbyint, 2)
++  BUILTIN_VHSDF (UNOP, rint, 2)
++  BUILTIN_VHSDF (UNOP, round, 2)
++  BUILTIN_VHSDF_DF (UNOP, frintn, 2)
++
++  VAR1 (UNOP, btrunc, 2, hf)
++  VAR1 (UNOP, ceil, 2, hf)
++  VAR1 (UNOP, floor, 2, hf)
++  VAR1 (UNOP, frintn, 2, hf)
++  VAR1 (UNOP, nearbyint, 2, hf)
++  VAR1 (UNOP, rint, 2, hf)
++  VAR1 (UNOP, round, 2, hf)
+ 
+   /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2.  */
++  VAR1 (UNOP, lbtruncv4hf, 2, v4hi)
++  VAR1 (UNOP, lbtruncv8hf, 2, v8hi)
+   VAR1 (UNOP, lbtruncv2sf, 2, v2si)
+   VAR1 (UNOP, lbtruncv4sf, 2, v4si)
+   VAR1 (UNOP, lbtruncv2df, 2, v2di)
+ 
++  VAR1 (UNOPUS, lbtruncuv4hf, 2, v4hi)
++  VAR1 (UNOPUS, lbtruncuv8hf, 2, v8hi)
+   VAR1 (UNOPUS, lbtruncuv2sf, 2, v2si)
+   VAR1 (UNOPUS, lbtruncuv4sf, 2, v4si)
+   VAR1 (UNOPUS, lbtruncuv2df, 2, v2di)
+ 
++  VAR1 (UNOP, lroundv4hf, 2, v4hi)
++  VAR1 (UNOP, lroundv8hf, 2, v8hi)
+   VAR1 (UNOP, lroundv2sf, 2, v2si)
+   VAR1 (UNOP, lroundv4sf, 2, v4si)
+   VAR1 (UNOP, lroundv2df, 2, v2di)
+-  /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2.  */
++  /* Implemented by l<fcvt_pattern><su_optab><GPF_F16:mode><GPI:mode>2.  */
++  BUILTIN_GPI_I16 (UNOP, lroundhf, 2)
+   VAR1 (UNOP, lroundsf, 2, si)
+   VAR1 (UNOP, lrounddf, 2, di)
+ 
++  VAR1 (UNOPUS, lrounduv4hf, 2, v4hi)
++  VAR1 (UNOPUS, lrounduv8hf, 2, v8hi)
+   VAR1 (UNOPUS, lrounduv2sf, 2, v2si)
+   VAR1 (UNOPUS, lrounduv4sf, 2, v4si)
+   VAR1 (UNOPUS, lrounduv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOPUS, lrounduhf, 2)
+   VAR1 (UNOPUS, lroundusf, 2, si)
+   VAR1 (UNOPUS, lroundudf, 2, di)
+ 
++  VAR1 (UNOP, lceilv4hf, 2, v4hi)
++  VAR1 (UNOP, lceilv8hf, 2, v8hi)
+   VAR1 (UNOP, lceilv2sf, 2, v2si)
+   VAR1 (UNOP, lceilv4sf, 2, v4si)
+   VAR1 (UNOP, lceilv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOP, lceilhf, 2)
+ 
++  VAR1 (UNOPUS, lceiluv4hf, 2, v4hi)
++  VAR1 (UNOPUS, lceiluv8hf, 2, v8hi)
+   VAR1 (UNOPUS, lceiluv2sf, 2, v2si)
+   VAR1 (UNOPUS, lceiluv4sf, 2, v4si)
+   VAR1 (UNOPUS, lceiluv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOPUS, lceiluhf, 2)
+   VAR1 (UNOPUS, lceilusf, 2, si)
+   VAR1 (UNOPUS, lceiludf, 2, di)
+ 
++  VAR1 (UNOP, lfloorv4hf, 2, v4hi)
++  VAR1 (UNOP, lfloorv8hf, 2, v8hi)
+   VAR1 (UNOP, lfloorv2sf, 2, v2si)
+   VAR1 (UNOP, lfloorv4sf, 2, v4si)
+   VAR1 (UNOP, lfloorv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOP, lfloorhf, 2)
+ 
++  VAR1 (UNOPUS, lflooruv4hf, 2, v4hi)
++  VAR1 (UNOPUS, lflooruv8hf, 2, v8hi)
+   VAR1 (UNOPUS, lflooruv2sf, 2, v2si)
+   VAR1 (UNOPUS, lflooruv4sf, 2, v4si)
+   VAR1 (UNOPUS, lflooruv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOPUS, lflooruhf, 2)
+   VAR1 (UNOPUS, lfloorusf, 2, si)
+   VAR1 (UNOPUS, lfloorudf, 2, di)
+ 
++  VAR1 (UNOP, lfrintnv4hf, 2, v4hi)
++  VAR1 (UNOP, lfrintnv8hf, 2, v8hi)
+   VAR1 (UNOP, lfrintnv2sf, 2, v2si)
+   VAR1 (UNOP, lfrintnv4sf, 2, v4si)
+   VAR1 (UNOP, lfrintnv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOP, lfrintnhf, 2)
+   VAR1 (UNOP, lfrintnsf, 2, si)
+   VAR1 (UNOP, lfrintndf, 2, di)
+ 
++  VAR1 (UNOPUS, lfrintnuv4hf, 2, v4hi)
++  VAR1 (UNOPUS, lfrintnuv8hf, 2, v8hi)
+   VAR1 (UNOPUS, lfrintnuv2sf, 2, v2si)
+   VAR1 (UNOPUS, lfrintnuv4sf, 2, v4si)
+   VAR1 (UNOPUS, lfrintnuv2df, 2, v2di)
++  BUILTIN_GPI_I16 (UNOPUS, lfrintnuhf, 2)
+   VAR1 (UNOPUS, lfrintnusf, 2, si)
+   VAR1 (UNOPUS, lfrintnudf, 2, di)
+ 
+   /* Implemented by <optab><fcvt_target><VDQF:mode>2.  */
++  VAR1 (UNOP, floatv4hi, 2, v4hf)
++  VAR1 (UNOP, floatv8hi, 2, v8hf)
+   VAR1 (UNOP, floatv2si, 2, v2sf)
+   VAR1 (UNOP, floatv4si, 2, v4sf)
+   VAR1 (UNOP, floatv2di, 2, v2df)
+ 
++  VAR1 (UNOP, floatunsv4hi, 2, v4hf)
++  VAR1 (UNOP, floatunsv8hi, 2, v8hf)
+   VAR1 (UNOP, floatunsv2si, 2, v2sf)
+   VAR1 (UNOP, floatunsv4si, 2, v4sf)
+   VAR1 (UNOP, floatunsv2di, 2, v2df)
+@@ -352,19 +403,19 @@
+ 
+   /* Implemented by
+      aarch64_frecp<FRECP:frecp_suffix><mode>.  */
+-  BUILTIN_GPF (UNOP, frecpe, 0)
+-  BUILTIN_GPF (BINOP, frecps, 0)
+-  BUILTIN_GPF (UNOP, frecpx, 0)
++  BUILTIN_GPF_F16 (UNOP, frecpe, 0)
++  BUILTIN_GPF_F16 (UNOP, frecpx, 0)
+ 
+   BUILTIN_VDQ_SI (UNOP, urecpe, 0)
+ 
+-  BUILTIN_VDQF (UNOP, frecpe, 0)
+-  BUILTIN_VDQF (BINOP, frecps, 0)
++  BUILTIN_VHSDF (UNOP, frecpe, 0)
++  BUILTIN_VHSDF_HSDF (BINOP, frecps, 0)
+ 
+   /* Implemented by a mixture of abs2 patterns.  Note the DImode builtin is
+      only ever used for the int64x1_t intrinsic, there is no scalar version.  */
+   BUILTIN_VSDQ_I_DI (UNOP, abs, 0)
+-  BUILTIN_VDQF (UNOP, abs, 2)
++  BUILTIN_VHSDF (UNOP, abs, 2)
++  VAR1 (UNOP, abs, 2, hf)
+ 
+   BUILTIN_VQ_HSF (UNOP, vec_unpacks_hi_, 10)
+   VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
+@@ -376,15 +427,22 @@
+ 
+   /* Implemented by aarch64_ld1<VALL_F16:mode>.  */
+   BUILTIN_VALL_F16 (LOAD1, ld1, 0)
++  VAR1(STORE1P, ld1, 0, v2di)
+ 
+   /* Implemented by aarch64_st1<VALL_F16:mode>.  */
+   BUILTIN_VALL_F16 (STORE1, st1, 0)
++  VAR1(STORE1P, st1, 0, v2di)
+ 
+   /* Implemented by fma<mode>4.  */
+-  BUILTIN_VDQF (TERNOP, fma, 4)
++  BUILTIN_VHSDF (TERNOP, fma, 4)
++  VAR1 (TERNOP, fma, 4, hf)
++  /* Implemented by fnma<mode>4.  */
++  BUILTIN_VHSDF (TERNOP, fnma, 4)
++  VAR1 (TERNOP, fnma, 4, hf)
+ 
+   /* Implemented by aarch64_simd_bsl<mode>.  */
+   BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
++  VAR2 (BSL_P, simd_bsl,0, di, v2di)
+   BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
+   BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
+ 
+@@ -436,7 +494,7 @@
+   VAR1 (TERNOP, qtbx4, 0, v8qi)
+   VAR1 (TERNOP, qtbx4, 0, v16qi)
+ 
+-  /* Builtins for ARMv8.1 Adv.SIMD instructions.  */
++  /* Builtins for ARMv8.1-A Adv.SIMD instructions.  */
+ 
+   /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>.  */
+   BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0)
+@@ -449,3 +507,60 @@
+   /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>.  */
+   BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0)
+   BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0)
++
++  /* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3.  */
++  BUILTIN_VSDQ_HSDI (SHIFTIMM, scvtf, 3)
++  BUILTIN_VSDQ_HSDI (FCVTIMM_SUS, ucvtf, 3)
++  BUILTIN_VHSDF_HSDF (SHIFTIMM, fcvtzs, 3)
++  BUILTIN_VHSDF_HSDF (SHIFTIMM_USS, fcvtzu, 3)
++  VAR1 (SHIFTIMM, scvtfsi, 3, hf)
++  VAR1 (SHIFTIMM, scvtfdi, 3, hf)
++  VAR1 (FCVTIMM_SUS, ucvtfsi, 3, hf)
++  VAR1 (FCVTIMM_SUS, ucvtfdi, 3, hf)
++  BUILTIN_GPI (SHIFTIMM, fcvtzshf, 3)
++  BUILTIN_GPI (SHIFTIMM_USS, fcvtzuhf, 3)
++
++  /* Implemented by aarch64_rsqrte<mode>.  */
++  BUILTIN_VHSDF_HSDF (UNOP, rsqrte, 0)
++
++  /* Implemented by aarch64_rsqrts<mode>.  */
++  BUILTIN_VHSDF_HSDF (BINOP, rsqrts, 0)
++
++  /* Implemented by fabd<mode>3.  */
++  BUILTIN_VHSDF_HSDF (BINOP, fabd, 3)
++
++  /* Implemented by aarch64_faddp<mode>.  */
++  BUILTIN_VHSDF (BINOP, faddp, 0)
++
++  /* Implemented by aarch64_cm<optab><mode>.  */
++  BUILTIN_VHSDF_HSDF (BINOP_USS, cmeq, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, cmge, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, cmgt, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, cmle, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, cmlt, 0)
++
++  /* Implemented by neg<mode>2.  */
++  BUILTIN_VHSDF_HSDF (UNOP, neg, 2)
++
++  /* Implemented by aarch64_fac<optab><mode>.  */
++  BUILTIN_VHSDF_HSDF (BINOP_USS, faclt, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, facle, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, facgt, 0)
++  BUILTIN_VHSDF_HSDF (BINOP_USS, facge, 0)
++
++  /* Implemented by sqrt<mode>2.  */
++  VAR1 (UNOP, sqrt, 2, hf)
++
++  /* Implemented by <optab><mode>hf2.  */
++  VAR1 (UNOP, floatdi, 2, hf)
++  VAR1 (UNOP, floatsi, 2, hf)
++  VAR1 (UNOP, floathi, 2, hf)
++  VAR1 (UNOPUS, floatunsdi, 2, hf)
++  VAR1 (UNOPUS, floatunssi, 2, hf)
++  VAR1 (UNOPUS, floatunshi, 2, hf)
++  BUILTIN_GPI_I16 (UNOP, fix_trunchf, 2)
++  BUILTIN_GPI (UNOP, fix_truncsf, 2)
++  BUILTIN_GPI (UNOP, fix_truncdf, 2)
++  BUILTIN_GPI_I16 (UNOPUS, fixuns_trunchf, 2)
++  BUILTIN_GPI (UNOPUS, fixuns_truncsf, 2)
++  BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2)
+\ No newline at end of file
+--- a/src/gcc/config/aarch64/aarch64-simd.md
++++ b/src/gcc/config/aarch64/aarch64-simd.md
+@@ -77,8 +77,8 @@
+ )
+ 
+ (define_insn "aarch64_dup_lane_<vswap_width_name><mode>"
+-  [(set (match_operand:VALL_F16 0 "register_operand" "=w")
+-	(vec_duplicate:VALL_F16
++  [(set (match_operand:VALL_F16_NO_V2Q 0 "register_operand" "=w")
++	(vec_duplicate:VALL_F16_NO_V2Q
+ 	  (vec_select:<VEL>
+ 	    (match_operand:<VSWAP_WIDTH> 1 "register_operand" "w")
+ 	    (parallel [(match_operand:SI 2 "immediate_operand" "i")])
+@@ -351,7 +351,7 @@
+     operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
+     return "<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
+   }
+-  [(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
++  [(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
+ )
+ 
+ (define_insn "*aarch64_mul3_elt_<vswap_width_name><mode>"
+@@ -371,33 +371,33 @@
+   [(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
+ )
+ 
+-(define_insn "*aarch64_mul3_elt_to_128df"
+-  [(set (match_operand:V2DF 0 "register_operand" "=w")
+-     (mult:V2DF
+-       (vec_duplicate:V2DF
+-	 (match_operand:DF 2 "register_operand" "w"))
+-      (match_operand:V2DF 1 "register_operand" "w")))]
++(define_insn "*aarch64_mul3_elt_from_dup<mode>"
++ [(set (match_operand:VMUL 0 "register_operand" "=w")
++    (mult:VMUL
++      (vec_duplicate:VMUL
++	    (match_operand:<VEL> 1 "register_operand" "<h_con>"))
++      (match_operand:VMUL 2 "register_operand" "w")))]
+   "TARGET_SIMD"
+-  "fmul\\t%0.2d, %1.2d, %2.d[0]"
+-  [(set_attr "type" "neon_fp_mul_d_scalar_q")]
++  "<f>mul\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]";
++  [(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
+ )
+ 
+-(define_insn "aarch64_rsqrte_<mode>2"
+-  [(set (match_operand:VALLF 0 "register_operand" "=w")
+-	(unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")]
++(define_insn "aarch64_rsqrte<mode>"
++  [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w")
++	(unspec:VHSDF_HSDF [(match_operand:VHSDF_HSDF 1 "register_operand" "w")]
+ 		     UNSPEC_RSQRTE))]
+   "TARGET_SIMD"
+   "frsqrte\\t%<v>0<Vmtype>, %<v>1<Vmtype>"
+-  [(set_attr "type" "neon_fp_rsqrte_<Vetype><q>")])
++  [(set_attr "type" "neon_fp_rsqrte_<stype><q>")])
+ 
+-(define_insn "aarch64_rsqrts_<mode>3"
+-  [(set (match_operand:VALLF 0 "register_operand" "=w")
+-	(unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")
+-	       (match_operand:VALLF 2 "register_operand" "w")]
+-		     UNSPEC_RSQRTS))]
++(define_insn "aarch64_rsqrts<mode>"
++  [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w")
++	(unspec:VHSDF_HSDF [(match_operand:VHSDF_HSDF 1 "register_operand" "w")
++			    (match_operand:VHSDF_HSDF 2 "register_operand" "w")]
++	 UNSPEC_RSQRTS))]
+   "TARGET_SIMD"
+   "frsqrts\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
+-  [(set_attr "type" "neon_fp_rsqrts_<Vetype><q>")])
++  [(set_attr "type" "neon_fp_rsqrts_<stype><q>")])
+ 
+ (define_expand "rsqrt<mode>2"
+   [(set (match_operand:VALLF 0 "register_operand" "=w")
+@@ -405,7 +405,7 @@
+ 		     UNSPEC_RSQRT))]
+   "TARGET_SIMD"
+ {
+-  aarch64_emit_approx_rsqrt (operands[0], operands[1]);
++  aarch64_emit_approx_sqrt (operands[0], operands[1], true);
+   DONE;
+ })
+ 
+@@ -474,24 +474,15 @@
+   [(set_attr "type" "neon_arith_acc<q>")]
+ )
+ 
+-(define_insn "fabd<mode>_3"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-	(abs:VDQF (minus:VDQF
+-		   (match_operand:VDQF 1 "register_operand" "w")
+-		   (match_operand:VDQF 2 "register_operand" "w"))))]
++(define_insn "fabd<mode>3"
++  [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w")
++	(abs:VHSDF_HSDF
++	  (minus:VHSDF_HSDF
++	    (match_operand:VHSDF_HSDF 1 "register_operand" "w")
++	    (match_operand:VHSDF_HSDF 2 "register_operand" "w"))))]
+   "TARGET_SIMD"
+-  "fabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_abd_<Vetype><q>")]
+-)
+-
+-(define_insn "*fabd_scalar<mode>3"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (abs:GPF (minus:GPF
+-                 (match_operand:GPF 1 "register_operand" "w")
+-                 (match_operand:GPF 2 "register_operand" "w"))))]
+-  "TARGET_SIMD"
+-  "fabd\t%<s>0, %<s>1, %<s>2"
+-  [(set_attr "type" "neon_fp_abd_<Vetype><q>")]
++  "fabd\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
++  [(set_attr "type" "neon_fp_abd_<stype><q>")]
+ )
+ 
+ (define_insn "and<mode>3"
+@@ -552,7 +543,50 @@
+ 	gcc_unreachable ();
+      }
+   }
+-  [(set_attr "type" "neon_from_gp<q>, neon_ins<q>, neon_load1_1reg<q>")]
++  [(set_attr "type" "neon_from_gp<q>, neon_ins<q>, neon_load1_one_lane<q>")]
++)
++
++(define_insn "*aarch64_simd_vec_copy_lane<mode>"
++  [(set (match_operand:VALL 0 "register_operand" "=w")
++	(vec_merge:VALL
++	    (vec_duplicate:VALL
++	      (vec_select:<VEL>
++		(match_operand:VALL 3 "register_operand" "w")
++		(parallel
++		  [(match_operand:SI 4 "immediate_operand" "i")])))
++	    (match_operand:VALL 1 "register_operand" "0")
++	    (match_operand:SI 2 "immediate_operand" "i")))]
++  "TARGET_SIMD"
++  {
++    int elt = ENDIAN_LANE_N (<MODE>mode, exact_log2 (INTVAL (operands[2])));
++    operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt);
++    operands[4] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[4])));
++
++    return "ins\t%0.<Vetype>[%p2], %3.<Vetype>[%4]";
++  }
++  [(set_attr "type" "neon_ins<q>")]
++)
++
++(define_insn "*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>"
++  [(set (match_operand:VALL_F16_NO_V2Q 0 "register_operand" "=w")
++	(vec_merge:VALL_F16_NO_V2Q
++	    (vec_duplicate:VALL_F16_NO_V2Q
++	      (vec_select:<VEL>
++		(match_operand:<VSWAP_WIDTH> 3 "register_operand" "w")
++		(parallel
++		  [(match_operand:SI 4 "immediate_operand" "i")])))
++	    (match_operand:VALL_F16_NO_V2Q 1 "register_operand" "0")
++	    (match_operand:SI 2 "immediate_operand" "i")))]
++  "TARGET_SIMD"
++  {
++    int elt = ENDIAN_LANE_N (<MODE>mode, exact_log2 (INTVAL (operands[2])));
++    operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt);
++    operands[4] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
++			   INTVAL (operands[4])));
++
++    return "ins\t%0.<Vetype>[%p2], %3.<Vetype>[%4]";
++  }
++  [(set_attr "type" "neon_ins<q>")]
+ )
+ 
+ (define_insn "aarch64_simd_lshr<mode>"
+@@ -1071,10 +1105,10 @@
+ 
+ ;; Pairwise FP Max/Min operations.
+ (define_insn "aarch64_<maxmin_uns>p<mode>"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")
+-		     (match_operand:VDQF 2 "register_operand" "w")]
+-		    FMAXMINV))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")
++		      (match_operand:VHSDF 2 "register_operand" "w")]
++		      FMAXMINV))]
+  "TARGET_SIMD"
+  "<maxmin_uns_op>p\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+   [(set_attr "type" "neon_minmax<q>")]
+@@ -1483,65 +1517,77 @@
+ ;; FP arithmetic operations.
+ 
+ (define_insn "add<mode>3"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (plus:VDQF (match_operand:VDQF 1 "register_operand" "w")
+-		  (match_operand:VDQF 2 "register_operand" "w")))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (plus:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		   (match_operand:VHSDF 2 "register_operand" "w")))]
+  "TARGET_SIMD"
+  "fadd\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_addsub_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_addsub_<stype><q>")]
+ )
+ 
+ (define_insn "sub<mode>3"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (minus:VDQF (match_operand:VDQF 1 "register_operand" "w")
+-		   (match_operand:VDQF 2 "register_operand" "w")))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (minus:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		    (match_operand:VHSDF 2 "register_operand" "w")))]
+  "TARGET_SIMD"
+  "fsub\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_addsub_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_addsub_<stype><q>")]
+ )
+ 
+ (define_insn "mul<mode>3"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (mult:VDQF (match_operand:VDQF 1 "register_operand" "w")
+-		  (match_operand:VDQF 2 "register_operand" "w")))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (mult:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		   (match_operand:VHSDF 2 "register_operand" "w")))]
+  "TARGET_SIMD"
+  "fmul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_mul_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_mul_<stype><q>")]
+ )
+ 
+-(define_insn "div<mode>3"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (div:VDQF (match_operand:VDQF 1 "register_operand" "w")
+-		 (match_operand:VDQF 2 "register_operand" "w")))]
++(define_expand "div<mode>3"
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (div:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		  (match_operand:VHSDF 2 "register_operand" "w")))]
++ "TARGET_SIMD"
++{
++  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
++    DONE;
++
++  operands[1] = force_reg (<MODE>mode, operands[1]);
++})
++
++(define_insn "*div<mode>3"
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (div:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		 (match_operand:VHSDF 2 "register_operand" "w")))]
+  "TARGET_SIMD"
+  "fdiv\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_div_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_div_<stype><q>")]
+ )
+ 
+ (define_insn "neg<mode>2"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (neg:VDQF (match_operand:VDQF 1 "register_operand" "w")))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (neg:VHSDF (match_operand:VHSDF 1 "register_operand" "w")))]
+  "TARGET_SIMD"
+  "fneg\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_neg_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_neg_<stype><q>")]
+ )
+ 
+ (define_insn "abs<mode>2"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (abs:VDQF (match_operand:VDQF 1 "register_operand" "w")))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (abs:VHSDF (match_operand:VHSDF 1 "register_operand" "w")))]
+  "TARGET_SIMD"
+  "fabs\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_abs_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_abs_<stype><q>")]
+ )
+ 
+ (define_insn "fma<mode>4"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (fma:VDQF (match_operand:VDQF 1 "register_operand" "w")
+-                (match_operand:VDQF 2 "register_operand" "w")
+-                (match_operand:VDQF 3 "register_operand" "0")))]
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (fma:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		  (match_operand:VHSDF 2 "register_operand" "w")
++		  (match_operand:VHSDF 3 "register_operand" "0")))]
+   "TARGET_SIMD"
+  "fmla\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_mla_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_mla_<stype><q>")]
+ )
+ 
+ (define_insn "*aarch64_fma4_elt<mode>"
+@@ -1579,16 +1625,16 @@
+   [(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
+ )
+ 
+-(define_insn "*aarch64_fma4_elt_to_128df"
+-  [(set (match_operand:V2DF 0 "register_operand" "=w")
+-    (fma:V2DF
+-      (vec_duplicate:V2DF
+-	  (match_operand:DF 1 "register_operand" "w"))
+-      (match_operand:V2DF 2 "register_operand" "w")
+-      (match_operand:V2DF 3 "register_operand" "0")))]
++(define_insn "*aarch64_fma4_elt_from_dup<mode>"
++  [(set (match_operand:VMUL 0 "register_operand" "=w")
++    (fma:VMUL
++      (vec_duplicate:VMUL
++	  (match_operand:<VEL> 1 "register_operand" "<h_con>"))
++      (match_operand:VMUL 2 "register_operand" "w")
++      (match_operand:VMUL 3 "register_operand" "0")))]
+   "TARGET_SIMD"
+-  "fmla\\t%0.2d, %2.2d, %1.2d[0]"
+-  [(set_attr "type" "neon_fp_mla_d_scalar_q")]
++  "fmla\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]"
++  [(set_attr "type" "neon<fp>_mla_<stype>_scalar<q>")]
+ )
+ 
+ (define_insn "*aarch64_fma4_elt_to_64v2df"
+@@ -1608,15 +1654,15 @@
+ )
+ 
+ (define_insn "fnma<mode>4"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-	(fma:VDQF
+-	  (match_operand:VDQF 1 "register_operand" "w")
+-          (neg:VDQF
+-	    (match_operand:VDQF 2 "register_operand" "w"))
+-	  (match_operand:VDQF 3 "register_operand" "0")))]
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(fma:VHSDF
++	  (match_operand:VHSDF 1 "register_operand" "w")
++          (neg:VHSDF
++	    (match_operand:VHSDF 2 "register_operand" "w"))
++	  (match_operand:VHSDF 3 "register_operand" "0")))]
+   "TARGET_SIMD"
+- "fmls\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_mla_<Vetype><q>")]
++  "fmls\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
++  [(set_attr "type" "neon_fp_mla_<stype><q>")]
+ )
+ 
+ (define_insn "*aarch64_fnma4_elt<mode>"
+@@ -1656,17 +1702,17 @@
+   [(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
+ )
+ 
+-(define_insn "*aarch64_fnma4_elt_to_128df"
+-  [(set (match_operand:V2DF 0 "register_operand" "=w")
+-    (fma:V2DF
+-      (neg:V2DF
+-        (match_operand:V2DF 2 "register_operand" "w"))
+-      (vec_duplicate:V2DF
+-	(match_operand:DF 1 "register_operand" "w"))
+-      (match_operand:V2DF 3 "register_operand" "0")))]
++(define_insn "*aarch64_fnma4_elt_from_dup<mode>"
++  [(set (match_operand:VMUL 0 "register_operand" "=w")
++    (fma:VMUL
++      (neg:VMUL
++        (match_operand:VMUL 2 "register_operand" "w"))
++      (vec_duplicate:VMUL
++	(match_operand:<VEL> 1 "register_operand" "<h_con>"))
++      (match_operand:VMUL 3 "register_operand" "0")))]
+   "TARGET_SIMD"
+-  "fmls\\t%0.2d, %2.2d, %1.2d[0]"
+-  [(set_attr "type" "neon_fp_mla_d_scalar_q")]
++  "fmls\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]"
++  [(set_attr "type" "neon<fp>_mla_<stype>_scalar<q>")]
+ )
+ 
+ (define_insn "*aarch64_fnma4_elt_to_64v2df"
+@@ -1689,24 +1735,50 @@
+ ;; Vector versions of the floating-point frint patterns.
+ ;; Expands to btrunc, ceil, floor, nearbyint, rint, round, frintn.
+ (define_insn "<frint_pattern><mode>2"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-	(unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")]
+-		      FRINT))]
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")]
++		       FRINT))]
+   "TARGET_SIMD"
+   "frint<frint_suffix>\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_round_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_round_<stype><q>")]
+ )
+ 
+ ;; Vector versions of the fcvt standard patterns.
+ ;; Expands to lbtrunc, lround, lceil, lfloor
+-(define_insn "l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2"
++(define_insn "l<fcvt_pattern><su_optab><VHSDF:mode><fcvt_target>2"
+   [(set (match_operand:<FCVT_TARGET> 0 "register_operand" "=w")
+ 	(FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
+-			       [(match_operand:VDQF 1 "register_operand" "w")]
++			       [(match_operand:VHSDF 1 "register_operand" "w")]
+ 			       FCVT)))]
+   "TARGET_SIMD"
+   "fcvt<frint_suffix><su>\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_to_int_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_to_int_<stype><q>")]
++)
++
++;; HF Scalar variants of related SIMD instructions.
++(define_insn "l<fcvt_pattern><su_optab>hfhi2"
++  [(set (match_operand:HI 0 "register_operand" "=w")
++	(FIXUORS:HI (unspec:HF [(match_operand:HF 1 "register_operand" "w")]
++		      FCVT)))]
++  "TARGET_SIMD_F16INST"
++  "fcvt<frint_suffix><su>\t%h0, %h1"
++  [(set_attr "type" "neon_fp_to_int_s")]
++)
++
++(define_insn "<optab>_trunchfhi2"
++  [(set (match_operand:HI 0 "register_operand" "=w")
++	(FIXUORS:HI (match_operand:HF 1 "register_operand" "w")))]
++  "TARGET_SIMD_F16INST"
++  "fcvtz<su>\t%h0, %h1"
++  [(set_attr "type" "neon_fp_to_int_s")]
++)
++
++(define_insn "<optab>hihf2"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++	(FLOATUORS:HF (match_operand:HI 1 "register_operand" "w")))]
++  "TARGET_SIMD_F16INST"
++  "<su_optab>cvtf\t%h0, %h1"
++  [(set_attr "type" "neon_int_to_fp_s")]
+ )
+ 
+ (define_insn "*aarch64_fcvt<su_optab><VDQF:mode><fcvt_target>2_mult"
+@@ -1729,36 +1801,36 @@
+   [(set_attr "type" "neon_fp_to_int_<Vetype><q>")]
+ )
+ 
+-(define_expand "<optab><VDQF:mode><fcvt_target>2"
++(define_expand "<optab><VHSDF:mode><fcvt_target>2"
+   [(set (match_operand:<FCVT_TARGET> 0 "register_operand")
+ 	(FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
+-			       [(match_operand:VDQF 1 "register_operand")]
+-			       UNSPEC_FRINTZ)))]
++			       [(match_operand:VHSDF 1 "register_operand")]
++				UNSPEC_FRINTZ)))]
+   "TARGET_SIMD"
+   {})
+ 
+-(define_expand "<fix_trunc_optab><VDQF:mode><fcvt_target>2"
++(define_expand "<fix_trunc_optab><VHSDF:mode><fcvt_target>2"
+   [(set (match_operand:<FCVT_TARGET> 0 "register_operand")
+ 	(FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
+-			       [(match_operand:VDQF 1 "register_operand")]
+-			       UNSPEC_FRINTZ)))]
++			       [(match_operand:VHSDF 1 "register_operand")]
++				UNSPEC_FRINTZ)))]
+   "TARGET_SIMD"
+   {})
+ 
+-(define_expand "ftrunc<VDQF:mode>2"
+-  [(set (match_operand:VDQF 0 "register_operand")
+-	(unspec:VDQF [(match_operand:VDQF 1 "register_operand")]
+-		      UNSPEC_FRINTZ))]
++(define_expand "ftrunc<VHSDF:mode>2"
++  [(set (match_operand:VHSDF 0 "register_operand")
++	(unspec:VHSDF [(match_operand:VHSDF 1 "register_operand")]
++		       UNSPEC_FRINTZ))]
+   "TARGET_SIMD"
+   {})
+ 
+-(define_insn "<optab><fcvt_target><VDQF:mode>2"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-	(FLOATUORS:VDQF
++(define_insn "<optab><fcvt_target><VHSDF:mode>2"
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(FLOATUORS:VHSDF
+ 	  (match_operand:<FCVT_TARGET> 1 "register_operand" "w")))]
+   "TARGET_SIMD"
+   "<su_optab>cvtf\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_int_to_fp_<Vetype><q>")]
++  [(set_attr "type" "neon_int_to_fp_<stype><q>")]
+ )
+ 
+ ;; Conversions between vectors of floats and doubles.
+@@ -1778,6 +1850,30 @@
+   [(set_attr "type" "neon_fp_cvt_widen_s")]
+ )
+ 
++;; Convert between fixed-point and floating-point (vector modes)
++
++(define_insn "<FCVT_F2FIXED:fcvt_fixed_insn><VHSDF:mode>3"
++  [(set (match_operand:<VHSDF:FCVT_TARGET> 0 "register_operand" "=w")
++	(unspec:<VHSDF:FCVT_TARGET>
++	  [(match_operand:VHSDF 1 "register_operand" "w")
++	   (match_operand:SI 2 "immediate_operand" "i")]
++	 FCVT_F2FIXED))]
++  "TARGET_SIMD"
++  "<FCVT_F2FIXED:fcvt_fixed_insn>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #%2"
++  [(set_attr "type" "neon_fp_to_int_<VHSDF:stype><q>")]
++)
++
++(define_insn "<FCVT_FIXED2F:fcvt_fixed_insn><VDQ_HSDI:mode>3"
++  [(set (match_operand:<VDQ_HSDI:FCVT_TARGET> 0 "register_operand" "=w")
++	(unspec:<VDQ_HSDI:FCVT_TARGET>
++	  [(match_operand:VDQ_HSDI 1 "register_operand" "w")
++	   (match_operand:SI 2 "immediate_operand" "i")]
++	 FCVT_FIXED2F))]
++  "TARGET_SIMD"
++  "<FCVT_FIXED2F:fcvt_fixed_insn>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #%2"
++  [(set_attr "type" "neon_int_to_fp_<VDQ_HSDI:stype><q>")]
++)
++
+ ;; ??? Note that the vectorizer usage of the vec_unpacks_[lo/hi] patterns
+ ;; is inconsistent with vector ordering elsewhere in the compiler, in that
+ ;; the meaning of HI and LO changes depending on the target endianness.
+@@ -1934,33 +2030,25 @@
+ ;; NaNs.
+ 
+ (define_insn "<su><maxmin><mode>3"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-        (FMAXMIN:VDQF (match_operand:VDQF 1 "register_operand" "w")
+-		   (match_operand:VDQF 2 "register_operand" "w")))]
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(FMAXMIN:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
++		       (match_operand:VHSDF 2 "register_operand" "w")))]
+   "TARGET_SIMD"
+   "f<maxmin>nm\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_minmax_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_minmax_<stype><q>")]
+ )
+ 
++;; Vector forms for fmax, fmin, fmaxnm, fminnm.
++;; fmaxnm and fminnm are used for the fmax<mode>3 standard pattern names,
++;; which implement the IEEE fmax ()/fmin () functions.
+ (define_insn "<maxmin_uns><mode>3"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")
+-		     (match_operand:VDQF 2 "register_operand" "w")]
+-		    FMAXMIN_UNS))]
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")
++		      (match_operand:VHSDF 2 "register_operand" "w")]
++		      FMAXMIN_UNS))]
+   "TARGET_SIMD"
+   "<maxmin_uns_op>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_minmax_<Vetype><q>")]
+-)
+-
+-;; Auto-vectorized forms for the IEEE-754 fmax()/fmin() functions
+-(define_insn "<fmaxmin><mode>3"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-	(unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")
+-		      (match_operand:VDQF 2 "register_operand" "w")]
+-		      FMAXMIN))]
+-  "TARGET_SIMD"
+-  "<fmaxmin_op>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+-  [(set_attr "type" "neon_fp_minmax_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_minmax_<stype><q>")]
+ )
+ 
+ ;; 'across lanes' add.
+@@ -1979,17 +2067,14 @@
+   }
+ )
+ 
+-(define_expand "reduc_plus_scal_<mode>"
+-  [(match_operand:<VEL> 0 "register_operand" "=w")
+-   (match_operand:V2F 1 "register_operand" "w")]
+-  "TARGET_SIMD"
+-  {
+-    rtx elt = GEN_INT (ENDIAN_LANE_N (<MODE>mode, 0));
+-    rtx scratch = gen_reg_rtx (<MODE>mode);
+-    emit_insn (gen_aarch64_reduc_plus_internal<mode> (scratch, operands[1]));
+-    emit_insn (gen_aarch64_get_lane<mode> (operands[0], scratch, elt));
+-    DONE;
+-  }
++(define_insn "aarch64_faddp<mode>"
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")
++		      (match_operand:VHSDF 2 "register_operand" "w")]
++	UNSPEC_FADDV))]
++ "TARGET_SIMD"
++ "faddp\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
++  [(set_attr "type" "neon_fp_reduc_add_<stype><q>")]
+ )
+ 
+ (define_insn "aarch64_reduc_plus_internal<mode>"
+@@ -2010,24 +2095,15 @@
+   [(set_attr "type" "neon_reduc_add")]
+ )
+ 
+-(define_insn "aarch64_reduc_plus_internal<mode>"
+- [(set (match_operand:V2F 0 "register_operand" "=w")
+-       (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")]
++(define_insn "reduc_plus_scal_<mode>"
++ [(set (match_operand:<VEL> 0 "register_operand" "=w")
++       (unspec:<VEL> [(match_operand:V2F 1 "register_operand" "w")]
+ 		   UNSPEC_FADDV))]
+  "TARGET_SIMD"
+  "faddp\\t%<Vetype>0, %1.<Vtype>"
+   [(set_attr "type" "neon_fp_reduc_add_<Vetype><q>")]
+ )
+ 
+-(define_insn "aarch64_addpv4sf"
+- [(set (match_operand:V4SF 0 "register_operand" "=w")
+-       (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")]
+-		    UNSPEC_FADDV))]
+- "TARGET_SIMD"
+- "faddp\\t%0.4s, %1.4s, %1.4s"
+-  [(set_attr "type" "neon_fp_reduc_add_s_q")]
+-)
+-
+ (define_expand "reduc_plus_scal_v4sf"
+  [(set (match_operand:SF 0 "register_operand")
+        (unspec:V4SF [(match_operand:V4SF 1 "register_operand")]
+@@ -2036,8 +2112,8 @@
+ {
+   rtx elt = GEN_INT (ENDIAN_LANE_N (V4SFmode, 0));
+   rtx scratch = gen_reg_rtx (V4SFmode);
+-  emit_insn (gen_aarch64_addpv4sf (scratch, operands[1]));
+-  emit_insn (gen_aarch64_addpv4sf (scratch, scratch));
++  emit_insn (gen_aarch64_faddpv4sf (scratch, operands[1], operands[1]));
++  emit_insn (gen_aarch64_faddpv4sf (scratch, scratch, scratch));
+   emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt));
+   DONE;
+ })
+@@ -2072,8 +2148,8 @@
+ ;; gimple_fold'd to the REDUC_(MAX|MIN)_EXPR tree code.  (This is FP smax/smin).
+ (define_expand "reduc_<maxmin_uns>_scal_<mode>"
+   [(match_operand:<VEL> 0 "register_operand")
+-   (unspec:VDQF [(match_operand:VDQF 1 "register_operand")]
+-		FMAXMINV)]
++   (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand")]
++		  FMAXMINV)]
+   "TARGET_SIMD"
+   {
+     rtx elt = GEN_INT (ENDIAN_LANE_N (<MODE>mode, 0));
+@@ -2120,12 +2196,12 @@
+ )
+ 
+ (define_insn "aarch64_reduc_<maxmin_uns>_internal<mode>"
+- [(set (match_operand:VDQF 0 "register_operand" "=w")
+-       (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")]
+-		    FMAXMINV))]
++ [(set (match_operand:VHSDF 0 "register_operand" "=w")
++       (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")]
++		      FMAXMINV))]
+  "TARGET_SIMD"
+  "<maxmin_uns_op><vp>\\t%<Vetype>0, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_reduc_minmax_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_reduc_minmax_<stype><q>")]
+ )
+ 
+ ;; aarch64_simd_bsl may compile to any of bsl/bif/bit depending on register
+@@ -2635,7 +2711,7 @@
+ (define_insn "*aarch64_combinez<mode>"
+   [(set (match_operand:<VDBL> 0 "register_operand" "=w,w,w")
+         (vec_concat:<VDBL>
+-	   (match_operand:VD_BHSI 1 "general_operand" "w,r,m")
++	   (match_operand:VD_BHSI 1 "general_operand" "w,?r,m")
+ 	   (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz")))]
+   "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+   "@
+@@ -2651,7 +2727,7 @@
+   [(set (match_operand:<VDBL> 0 "register_operand" "=w,w,w")
+         (vec_concat:<VDBL>
+ 	   (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz")
+-	   (match_operand:VD_BHSI 1 "general_operand" "w,r,m")))]
++	   (match_operand:VD_BHSI 1 "general_operand" "w,?r,m")))]
+   "TARGET_SIMD && BYTES_BIG_ENDIAN"
+   "@
+    mov\\t%0.8b, %1.8b
+@@ -2994,13 +3070,14 @@
+ ;; fmulx.
+ 
+ (define_insn "aarch64_fmulx<mode>"
+-  [(set (match_operand:VALLF 0 "register_operand" "=w")
+-	(unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")
+-		       (match_operand:VALLF 2 "register_operand" "w")]
+-		      UNSPEC_FMULX))]
++  [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w")
++	(unspec:VHSDF_HSDF
++	  [(match_operand:VHSDF_HSDF 1 "register_operand" "w")
++	   (match_operand:VHSDF_HSDF 2 "register_operand" "w")]
++	   UNSPEC_FMULX))]
+  "TARGET_SIMD"
+  "fmulx\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
+- [(set_attr "type" "neon_fp_mul_<Vetype>")]
++ [(set_attr "type" "neon_fp_mul_<stype>")]
+ )
+ 
+ ;; vmulxq_lane_f32, and vmulx_laneq_f32
+@@ -3042,20 +3119,18 @@
+   [(set_attr "type" "neon_fp_mul_<Vetype><q>")]
+ )
+ 
+-;; vmulxq_lane_f64
++;; vmulxq_lane
+ 
+-(define_insn "*aarch64_mulx_elt_to_64v2df"
+-  [(set (match_operand:V2DF 0 "register_operand" "=w")
+-	(unspec:V2DF
+-	 [(match_operand:V2DF 1 "register_operand" "w")
+-	  (vec_duplicate:V2DF
+-	    (match_operand:DF 2 "register_operand" "w"))]
++(define_insn "*aarch64_mulx_elt_from_dup<mode>"
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(unspec:VHSDF
++	 [(match_operand:VHSDF 1 "register_operand" "w")
++	  (vec_duplicate:VHSDF
++	    (match_operand:<VEL> 2 "register_operand" "<h_con>"))]
+ 	 UNSPEC_FMULX))]
+   "TARGET_SIMD"
+-  {
+-    return "fmulx\t%0.2d, %1.2d, %2.d[0]";
+-  }
+-  [(set_attr "type" "neon_fp_mul_d_scalar_q")]
++  "fmulx\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[0]";
++  [(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
+ )
+ 
+ ;; vmulxs_lane_f32, vmulxs_laneq_f32
+@@ -3067,7 +3142,7 @@
+ 	(unspec:<VEL>
+ 	 [(match_operand:<VEL> 1 "register_operand" "w")
+ 	  (vec_select:<VEL>
+-	   (match_operand:VDQF_DF 2 "register_operand" "w")
++	   (match_operand:VDQF 2 "register_operand" "w")
+ 	    (parallel [(match_operand:SI 3 "immediate_operand" "i")]))]
+ 	 UNSPEC_FMULX))]
+   "TARGET_SIMD"
+@@ -3937,15 +4012,12 @@
+ 			   "aarch64_simd_shift_imm_bitsize_<ve_mode>" "i")]
+                          VSHLL))]
+   "TARGET_SIMD"
+-  "*
+-  int bit_width = GET_MODE_UNIT_SIZE (<MODE>mode) * BITS_PER_UNIT;
+-  if (INTVAL (operands[2]) == bit_width)
+   {
+-    return \"shll\\t%0.<Vwtype>, %1.<Vtype>, %2\";
++    if (INTVAL (operands[2]) == GET_MODE_UNIT_BITSIZE (<MODE>mode))
++      return "shll\\t%0.<Vwtype>, %1.<Vtype>, %2";
++    else
++      return "<sur>shll\\t%0.<Vwtype>, %1.<Vtype>, %2";
+   }
+-  else {
+-    return \"<sur>shll\\t%0.<Vwtype>, %1.<Vtype>, %2\";
+-  }"
+   [(set_attr "type" "neon_shift_imm_long")]
+ )
+ 
+@@ -3957,15 +4029,12 @@
+ 			 (match_operand:SI 2 "immediate_operand" "i")]
+                          VSHLL))]
+   "TARGET_SIMD"
+-  "*
+-  int bit_width = GET_MODE_UNIT_SIZE (<MODE>mode) * BITS_PER_UNIT;
+-  if (INTVAL (operands[2]) == bit_width)
+   {
+-    return \"shll2\\t%0.<Vwtype>, %1.<Vtype>, %2\";
++    if (INTVAL (operands[2]) == GET_MODE_UNIT_BITSIZE (<MODE>mode))
++      return "shll2\\t%0.<Vwtype>, %1.<Vtype>, %2";
++    else
++      return "<sur>shll2\\t%0.<Vwtype>, %1.<Vtype>, %2";
+   }
+-  else {
+-    return \"<sur>shll2\\t%0.<Vwtype>, %1.<Vtype>, %2\";
+-  }"
+   [(set_attr "type" "neon_shift_imm_long")]
+ )
+ 
+@@ -4246,30 +4315,32 @@
+   [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")
+ 	(neg:<V_cmp_result>
+ 	  (COMPARISONS:<V_cmp_result>
+-	    (match_operand:VALLF 1 "register_operand" "w,w")
+-	    (match_operand:VALLF 2 "aarch64_simd_reg_or_zero" "w,YDz")
++	    (match_operand:VHSDF_HSDF 1 "register_operand" "w,w")
++	    (match_operand:VHSDF_HSDF 2 "aarch64_simd_reg_or_zero" "w,YDz")
+ 	  )))]
+   "TARGET_SIMD"
+   "@
+   fcm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>
+   fcm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"
+-  [(set_attr "type" "neon_fp_compare_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_compare_<stype><q>")]
+ )
+ 
+ ;; fac(ge|gt)
+ ;; Note we can also handle what would be fac(le|lt) by
+ ;; generating fac(ge|gt).
+ 
+-(define_insn "*aarch64_fac<optab><mode>"
++(define_insn "aarch64_fac<optab><mode>"
+   [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
+ 	(neg:<V_cmp_result>
+ 	  (FAC_COMPARISONS:<V_cmp_result>
+-	    (abs:VALLF (match_operand:VALLF 1 "register_operand" "w"))
+-	    (abs:VALLF (match_operand:VALLF 2 "register_operand" "w"))
++	    (abs:VHSDF_HSDF
++	      (match_operand:VHSDF_HSDF 1 "register_operand" "w"))
++	    (abs:VHSDF_HSDF
++	      (match_operand:VHSDF_HSDF 2 "register_operand" "w"))
+   )))]
+   "TARGET_SIMD"
+   "fac<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"
+-  [(set_attr "type" "neon_fp_compare_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_compare_<stype><q>")]
+ )
+ 
+ ;; addp
+@@ -4297,12 +4368,21 @@
+ 
+ ;; sqrt
+ 
+-(define_insn "sqrt<mode>2"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-        (sqrt:VDQF (match_operand:VDQF 1 "register_operand" "w")))]
++(define_expand "sqrt<mode>2"
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(sqrt:VHSDF (match_operand:VHSDF 1 "register_operand" "w")))]
++  "TARGET_SIMD"
++{
++  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
++    DONE;
++})
++
++(define_insn "*sqrt<mode>2"
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(sqrt:VHSDF (match_operand:VHSDF 1 "register_operand" "w")))]
+   "TARGET_SIMD"
+   "fsqrt\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_sqrt_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_sqrt_<stype><q>")]
+ )
+ 
+ ;; Patterns for vector struct loads and stores.
+@@ -4652,7 +4732,7 @@
+    ld1\\t{%S0.16b - %<Vendreg>0.16b}, %1"
+   [(set_attr "type" "multiple,neon_store<nregs>_<nregs>reg_q,\
+ 		     neon_load<nregs>_<nregs>reg_q")
+-   (set (attr "length") (symbol_ref "aarch64_simd_attr_length_move (insn)"))]
++   (set_attr "length" "<insn_count>,4,4")]
+ )
+ 
+ (define_insn "aarch64_be_ld1<mode>"
+@@ -4685,7 +4765,7 @@
+    stp\\t%q1, %R1, %0
+    ldp\\t%q0, %R0, %1"
+   [(set_attr "type" "multiple,neon_stp_q,neon_ldp_q")
+-   (set (attr "length") (symbol_ref "aarch64_simd_attr_length_move (insn)"))]
++   (set_attr "length" "8,4,4")]
+ )
+ 
+ (define_insn "*aarch64_be_movci"
+@@ -4696,7 +4776,7 @@
+        || register_operand (operands[1], CImode))"
+   "#"
+   [(set_attr "type" "multiple")
+-   (set (attr "length") (symbol_ref "aarch64_simd_attr_length_move (insn)"))]
++   (set_attr "length" "12,4,4")]
+ )
+ 
+ (define_insn "*aarch64_be_movxi"
+@@ -4707,7 +4787,7 @@
+        || register_operand (operands[1], XImode))"
+   "#"
+   [(set_attr "type" "multiple")
+-   (set (attr "length") (symbol_ref "aarch64_simd_attr_length_move (insn)"))]
++   (set_attr "length" "16,4,4")]
+ )
+ 
+ (define_split
+@@ -4787,7 +4867,7 @@
+   DONE;
+ })
+ 
+-(define_insn "aarch64_ld2<mode>_dreg"
++(define_insn "aarch64_ld2<mode>_dreg_le"
+   [(set (match_operand:OI 0 "register_operand" "=w")
+ 	(subreg:OI
+ 	  (vec_concat:<VRL2>
+@@ -4800,12 +4880,30 @@
+ 	     (unspec:VD [(match_dup 1)]
+ 			UNSPEC_LD2)
+ 	     (vec_duplicate:VD (const_int 0)))) 0))]
+-  "TARGET_SIMD"
++  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
++  "ld2\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
++  [(set_attr "type" "neon_load2_2reg<q>")]
++)
++
++(define_insn "aarch64_ld2<mode>_dreg_be"
++  [(set (match_operand:OI 0 "register_operand" "=w")
++	(subreg:OI
++	  (vec_concat:<VRL2>
++	    (vec_concat:<VDBL>
++	     (vec_duplicate:VD (const_int 0))
++	     (unspec:VD
++		[(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
++		UNSPEC_LD2))
++	    (vec_concat:<VDBL>
++	     (vec_duplicate:VD (const_int 0))
++	     (unspec:VD [(match_dup 1)]
++			UNSPEC_LD2))) 0))]
++  "TARGET_SIMD && BYTES_BIG_ENDIAN"
+   "ld2\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
+   [(set_attr "type" "neon_load2_2reg<q>")]
+ )
+ 
+-(define_insn "aarch64_ld2<mode>_dreg"
++(define_insn "aarch64_ld2<mode>_dreg_le"
+   [(set (match_operand:OI 0 "register_operand" "=w")
+ 	(subreg:OI
+ 	  (vec_concat:<VRL2>
+@@ -4818,12 +4916,30 @@
+ 	     (unspec:DX [(match_dup 1)]
+ 			UNSPEC_LD2)
+ 	     (const_int 0))) 0))]
+-  "TARGET_SIMD"
++  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
++  "ld1\\t{%S0.1d - %T0.1d}, %1"
++  [(set_attr "type" "neon_load1_2reg<q>")]
++)
++
++(define_insn "aarch64_ld2<mode>_dreg_be"
++  [(set (match_operand:OI 0 "register_operand" "=w")
++	(subreg:OI
++	  (vec_concat:<VRL2>
++	    (vec_concat:<VDBL>
++	     (const_int 0)
++	     (unspec:DX
++		[(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
++		UNSPEC_LD2))
++	    (vec_concat:<VDBL>
++	     (const_int 0)
++	     (unspec:DX [(match_dup 1)]
++			UNSPEC_LD2))) 0))]
++  "TARGET_SIMD && BYTES_BIG_ENDIAN"
+   "ld1\\t{%S0.1d - %T0.1d}, %1"
+   [(set_attr "type" "neon_load1_2reg<q>")]
+ )
+ 
+-(define_insn "aarch64_ld3<mode>_dreg"
++(define_insn "aarch64_ld3<mode>_dreg_le"
+   [(set (match_operand:CI 0 "register_operand" "=w")
+ 	(subreg:CI
+ 	 (vec_concat:<VRL3>
+@@ -4841,12 +4957,35 @@
+ 	     (unspec:VD [(match_dup 1)]
+ 			UNSPEC_LD3)
+ 	     (vec_duplicate:VD (const_int 0)))) 0))]
+-  "TARGET_SIMD"
++  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+   "ld3\\t{%S0.<Vtype> - %U0.<Vtype>}, %1"
+   [(set_attr "type" "neon_load3_3reg<q>")]
+ )
+ 
+-(define_insn "aarch64_ld3<mode>_dreg"
++(define_insn "aarch64_ld3<mode>_dreg_be"
++  [(set (match_operand:CI 0 "register_operand" "=w")
++	(subreg:CI
++	 (vec_concat:<VRL3>
++	  (vec_concat:<VRL2>
++	    (vec_concat:<VDBL>
++	     (vec_duplicate:VD (const_int 0))
++	     (unspec:VD
++		[(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
++		UNSPEC_LD3))
++	    (vec_concat:<VDBL>
++	     (vec_duplicate:VD (const_int 0))
++	     (unspec:VD [(match_dup 1)]
++			UNSPEC_LD3)))
++	  (vec_concat:<VDBL>
++	     (vec_duplicate:VD (const_int 0))
++	     (unspec:VD [(match_dup 1)]
++			UNSPEC_LD3))) 0))]
++  "TARGET_SIMD && BYTES_BIG_ENDIAN"
++  "ld3\\t{%S0.<Vtype> - %U0.<Vtype>}, %1"
++  [(set_attr "type" "neon_load3_3reg<q>")]
++)
++
++(define_insn "aarch64_ld3<mode>_dreg_le"
+   [(set (match_operand:CI 0 "register_operand" "=w")
+ 	(subreg:CI
+ 	 (vec_concat:<VRL3>
+@@ -4864,12 +5003,35 @@
+ 	     (unspec:DX [(match_dup 1)]
+ 			UNSPEC_LD3)
+ 	     (const_int 0))) 0))]
+-  "TARGET_SIMD"
++  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+   "ld1\\t{%S0.1d - %U0.1d}, %1"
+   [(set_attr "type" "neon_load1_3reg<q>")]
+ )
+ 
+-(define_insn "aarch64_ld4<mode>_dreg"
++(define_insn "aarch64_ld3<mode>_dreg_be"
++  [(set (match_operand:CI 0 "register_operand" "=w")
++	(subreg:CI
++	 (vec_concat:<VRL3>
++	  (vec_concat:<VRL2>
++	    (vec_concat:<VDBL>
++	     (const_int 0)
++	     (unspec:DX
++		[(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
++		UNSPEC_LD3))
++	    (vec_concat:<VDBL>
++	     (const_int 0)
++	     (unspec:DX [(match_dup 1)]
++			UNSPEC_LD3)))
++	  (vec_concat:<VDBL>
++	     (const_int 0)
++	     (unspec:DX [(match_dup 1)]
++			UNSPEC_LD3))) 0))]
++  "TARGET_SIMD && BYTES_BIG_ENDIAN"
++  "ld1\\t{%S0.1d - %U0.1d}, %1"
++  [(set_attr "type" "neon_load1_3reg<q>")]
++)
++
++(define_insn "aarch64_ld4<mode>_dreg_le"
+   [(set (match_operand:XI 0 "register_operand" "=w")
+ 	(subreg:XI
+ 	 (vec_concat:<VRL4>
+@@ -4880,9 +5042,9 @@
+ 		UNSPEC_LD4)
+ 	       (vec_duplicate:VD (const_int 0)))
+ 	      (vec_concat:<VDBL>
+-	        (unspec:VD [(match_dup 1)]
++		(unspec:VD [(match_dup 1)]
+ 			UNSPEC_LD4)
+-	        (vec_duplicate:VD (const_int 0))))
++		(vec_duplicate:VD (const_int 0))))
+ 	   (vec_concat:<VRL2>
+ 	     (vec_concat:<VDBL>
+ 	       (unspec:VD [(match_dup 1)]
+@@ -4892,12 +5054,40 @@
+ 	       (unspec:VD [(match_dup 1)]
+ 			UNSPEC_LD4)
+ 	       (vec_duplicate:VD (const_int 0))))) 0))]
+-  "TARGET_SIMD"
++  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+   "ld4\\t{%S0.<Vtype> - %V0.<Vtype>}, %1"
+   [(set_attr "type" "neon_load4_4reg<q>")]
+ )
+ 
+-(define_insn "aarch64_ld4<mode>_dreg"
++(define_insn "aarch64_ld4<mode>_dreg_be"
++  [(set (match_operand:XI 0 "register_operand" "=w")
++	(subreg:XI
++	 (vec_concat:<VRL4>
++	   (vec_concat:<VRL2>
++	     (vec_concat:<VDBL>
++	       (vec_duplicate:VD (const_int 0))
++	       (unspec:VD
++		[(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
++		UNSPEC_LD4))
++	      (vec_concat:<VDBL>
++		(vec_duplicate:VD (const_int 0))
++		(unspec:VD [(match_dup 1)]
++			UNSPEC_LD4)))
++	   (vec_concat:<VRL2>
++	     (vec_concat:<VDBL>
++	       (vec_duplicate:VD (const_int 0))
++	       (unspec:VD [(match_dup 1)]
++			UNSPEC_LD4))
++	     (vec_concat:<VDBL>
++	       (vec_duplicate:VD (const_int 0))
++	       (unspec:VD [(match_dup 1)]
++			UNSPEC_LD4)))) 0))]
++  "TARGET_SIMD && BYTES_BIG_ENDIAN"
++  "ld4\\t{%S0.<Vtype> - %V0.<Vtype>}, %1"
++  [(set_attr "type" "neon_load4_4reg<q>")]
++)
++
++(define_insn "aarch64_ld4<mode>_dreg_le"
+   [(set (match_operand:XI 0 "register_operand" "=w")
+ 	(subreg:XI
+ 	 (vec_concat:<VRL4>
+@@ -4910,7 +5100,7 @@
+ 	      (vec_concat:<VDBL>
+ 	        (unspec:DX [(match_dup 1)]
+ 			UNSPEC_LD4)
+-	        (const_int 0)))
++		(const_int 0)))
+ 	   (vec_concat:<VRL2>
+ 	     (vec_concat:<VDBL>
+ 	       (unspec:DX [(match_dup 1)]
+@@ -4920,7 +5110,35 @@
+ 	       (unspec:DX [(match_dup 1)]
+ 			UNSPEC_LD4)
+ 	       (const_int 0)))) 0))]
+-  "TARGET_SIMD"
++  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
++  "ld1\\t{%S0.1d - %V0.1d}, %1"
++  [(set_attr "type" "neon_load1_4reg<q>")]
++)
++
++(define_insn "aarch64_ld4<mode>_dreg_be"
++  [(set (match_operand:XI 0 "register_operand" "=w")
++	(subreg:XI
++	 (vec_concat:<VRL4>
++	   (vec_concat:<VRL2>
++	     (vec_concat:<VDBL>
++	       (const_int 0)
++	       (unspec:DX
++		[(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
++		UNSPEC_LD4))
++	      (vec_concat:<VDBL>
++		(const_int 0)
++		(unspec:DX [(match_dup 1)]
++			UNSPEC_LD4)))
++	   (vec_concat:<VRL2>
++	     (vec_concat:<VDBL>
++	       (const_int 0)
++	       (unspec:DX [(match_dup 1)]
++			UNSPEC_LD4))
++	     (vec_concat:<VDBL>
++	       (const_int 0)
++	       (unspec:DX [(match_dup 1)]
++			UNSPEC_LD4)))) 0))]
++  "TARGET_SIMD && BYTES_BIG_ENDIAN"
+   "ld1\\t{%S0.1d - %V0.1d}, %1"
+   [(set_attr "type" "neon_load1_4reg<q>")]
+ )
+@@ -4934,7 +5152,12 @@
+   rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+   set_mem_size (mem, <VSTRUCT:nregs> * 8);
+ 
+-  emit_insn (gen_aarch64_ld<VSTRUCT:nregs><VDC:mode>_dreg (operands[0], mem));
++  if (BYTES_BIG_ENDIAN)
++    emit_insn (gen_aarch64_ld<VSTRUCT:nregs><VDC:mode>_dreg_be (operands[0],
++								mem));
++  else
++    emit_insn (gen_aarch64_ld<VSTRUCT:nregs><VDC:mode>_dreg_le (operands[0],
++								mem));
+   DONE;
+ })
+ 
+@@ -5160,10 +5383,10 @@
+ )
+ 
+ (define_insn "aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>"
+-  [(set (match_operand:VALL 0 "register_operand" "=w")
+-	(unspec:VALL [(match_operand:VALL 1 "register_operand" "w")
+-		      (match_operand:VALL 2 "register_operand" "w")]
+-		       PERMUTE))]
++  [(set (match_operand:VALL_F16 0 "register_operand" "=w")
++	(unspec:VALL_F16 [(match_operand:VALL_F16 1 "register_operand" "w")
++			  (match_operand:VALL_F16 2 "register_operand" "w")]
++	 PERMUTE))]
+   "TARGET_SIMD"
+   "<PERMUTE:perm_insn><PERMUTE:perm_hilo>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+   [(set_attr "type" "neon_permute<q>")]
+@@ -5171,11 +5394,11 @@
+ 
+ ;; Note immediate (third) operand is lane index not byte index.
+ (define_insn "aarch64_ext<mode>"
+-  [(set (match_operand:VALL 0 "register_operand" "=w")
+-        (unspec:VALL [(match_operand:VALL 1 "register_operand" "w")
+-                      (match_operand:VALL 2 "register_operand" "w")
+-                      (match_operand:SI 3 "immediate_operand" "i")]
+-                     UNSPEC_EXT))]
++  [(set (match_operand:VALL_F16 0 "register_operand" "=w")
++        (unspec:VALL_F16 [(match_operand:VALL_F16 1 "register_operand" "w")
++			  (match_operand:VALL_F16 2 "register_operand" "w")
++			  (match_operand:SI 3 "immediate_operand" "i")]
++	 UNSPEC_EXT))]
+   "TARGET_SIMD"
+ {
+   operands[3] = GEN_INT (INTVAL (operands[3])
+@@ -5186,8 +5409,8 @@
+ )
+ 
+ (define_insn "aarch64_rev<REVERSE:rev_op><mode>"
+-  [(set (match_operand:VALL 0 "register_operand" "=w")
+-	(unspec:VALL [(match_operand:VALL 1 "register_operand" "w")]
++  [(set (match_operand:VALL_F16 0 "register_operand" "=w")
++	(unspec:VALL_F16 [(match_operand:VALL_F16 1 "register_operand" "w")]
+                     REVERSE))]
+   "TARGET_SIMD"
+   "rev<REVERSE:rev_op>\\t%0.<Vtype>, %1.<Vtype>"
+@@ -5354,31 +5577,32 @@
+ )
+ 
+ (define_insn "aarch64_frecpe<mode>"
+-  [(set (match_operand:VDQF 0 "register_operand" "=w")
+-	(unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")]
+-		    UNSPEC_FRECPE))]
++  [(set (match_operand:VHSDF 0 "register_operand" "=w")
++	(unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")]
++	 UNSPEC_FRECPE))]
+   "TARGET_SIMD"
+   "frecpe\\t%0.<Vtype>, %1.<Vtype>"
+-  [(set_attr "type" "neon_fp_recpe_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_recpe_<stype><q>")]
+ )
+ 
+ (define_insn "aarch64_frecp<FRECP:frecp_suffix><mode>"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-	(unspec:GPF [(match_operand:GPF 1 "register_operand" "w")]
+-		    FRECP))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(unspec:GPF_F16 [(match_operand:GPF_F16 1 "register_operand" "w")]
++	 FRECP))]
+   "TARGET_SIMD"
+   "frecp<FRECP:frecp_suffix>\\t%<s>0, %<s>1"
+-  [(set_attr "type" "neon_fp_recp<FRECP:frecp_suffix>_<GPF:Vetype><GPF:q>")]
++  [(set_attr "type" "neon_fp_recp<FRECP:frecp_suffix>_<GPF_F16:stype>")]
+ )
+ 
+ (define_insn "aarch64_frecps<mode>"
+-  [(set (match_operand:VALLF 0 "register_operand" "=w")
+-	(unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")
+-		     (match_operand:VALLF 2 "register_operand" "w")]
+-		    UNSPEC_FRECPS))]
++  [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w")
++	(unspec:VHSDF_HSDF
++	  [(match_operand:VHSDF_HSDF 1 "register_operand" "w")
++	  (match_operand:VHSDF_HSDF 2 "register_operand" "w")]
++	  UNSPEC_FRECPS))]
+   "TARGET_SIMD"
+   "frecps\\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
+-  [(set_attr "type" "neon_fp_recps_<Vetype><q>")]
++  [(set_attr "type" "neon_fp_recps_<stype><q>")]
+ )
+ 
+ (define_insn "aarch64_urecpe<mode>"
+@@ -5414,13 +5638,25 @@
+   [(set_attr "type" "crypto_aese")]
+ )
+ 
++;; When AES/AESMC fusion is enabled we want the register allocation to
++;; look like:
++;;    AESE Vn, _
++;;    AESMC Vn, Vn
++;; So prefer to tie operand 1 to operand 0 when fusing.
++
+ (define_insn "aarch64_crypto_aes<aesmc_op>v16qi"
+-  [(set (match_operand:V16QI 0 "register_operand" "=w")
+-	(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "w")]
++  [(set (match_operand:V16QI 0 "register_operand" "=w,w")
++	(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0,w")]
+ 	 CRYPTO_AESMC))]
+   "TARGET_SIMD && TARGET_CRYPTO"
+   "aes<aesmc_op>\\t%0.16b, %1.16b"
+-  [(set_attr "type" "crypto_aesmc")]
++  [(set_attr "type" "crypto_aesmc")
++   (set_attr_alternative "enabled"
++     [(if_then_else (match_test
++		       "aarch64_fusion_enabled_p (AARCH64_FUSE_AES_AESMC)")
++		     (const_string "yes" )
++		     (const_string "no"))
++      (const_string "yes")])]
+ )
+ 
+ ;; sha1
+@@ -5435,6 +5671,26 @@
+   [(set_attr "type" "crypto_sha1_fast")]
+ )
+ 
++(define_insn "aarch64_crypto_sha1hv4si"
++  [(set (match_operand:SI 0 "register_operand" "=w")
++	(unspec:SI [(vec_select:SI (match_operand:V4SI 1 "register_operand" "w")
++		     (parallel [(const_int 0)]))]
++	 UNSPEC_SHA1H))]
++  "TARGET_SIMD && TARGET_CRYPTO && !BYTES_BIG_ENDIAN"
++  "sha1h\\t%s0, %s1"
++  [(set_attr "type" "crypto_sha1_fast")]
++)
++
++(define_insn "aarch64_be_crypto_sha1hv4si"
++  [(set (match_operand:SI 0 "register_operand" "=w")
++	(unspec:SI [(vec_select:SI (match_operand:V4SI 1 "register_operand" "w")
++		     (parallel [(const_int 3)]))]
++	 UNSPEC_SHA1H))]
++  "TARGET_SIMD && TARGET_CRYPTO && BYTES_BIG_ENDIAN"
++  "sha1h\\t%s0, %s1"
++  [(set_attr "type" "crypto_sha1_fast")]
++)
++
+ (define_insn "aarch64_crypto_sha1su1v4si"
+   [(set (match_operand:V4SI 0 "register_operand" "=w")
+         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
+--- a/src/gcc/config/aarch64/aarch64-tune.md
++++ b/src/gcc/config/aarch64/aarch64-tune.md
+@@ -1,5 +1,5 @@
+ ;; -*- buffer-read-only: t -*-
+ ;; Generated automatically by gentune.sh from aarch64-cores.def
+ (define_attr "tune"
+-	"cortexa35,cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
++	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,exynosm1,qdf24xx,thunderx,xgene1,vulcan,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53"
+ 	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
+--- a/src/gcc/config/aarch64/aarch64-tuning-flags.def
++++ b/src/gcc/config/aarch64/aarch64-tuning-flags.def
+@@ -29,5 +29,8 @@
+      AARCH64_TUNE_ to give an enum name. */
+ 
+ AARCH64_EXTRA_TUNING_OPTION ("rename_fma_regs", RENAME_FMA_REGS)
+-AARCH64_EXTRA_TUNING_OPTION ("approx_rsqrt", APPROX_RSQRT)
+ 
++/* Don't create non-8 byte aligned load/store pair.  That is if the
++two load/stores are not at least 8 byte aligned don't create load/store
++pairs.   */
++AARCH64_EXTRA_TUNING_OPTION ("slow_unaligned_ldpw", SLOW_UNALIGNED_LDPW)
+--- a/src/gcc/config/aarch64/aarch64.c
++++ b/src/gcc/config/aarch64/aarch64.c
+@@ -26,6 +26,7 @@
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "cfghooks.h"
+ #include "cfgloop.h"
+@@ -61,7 +62,6 @@
+ #include "rtl-iter.h"
+ #include "tm-constrs.h"
+ #include "sched-int.h"
+-#include "cortex-a57-fma-steering.h"
+ #include "target-globals.h"
+ #include "common/common-target.h"
+ 
+@@ -141,6 +141,10 @@ static bool aarch64_vector_mode_supported_p (machine_mode);
+ static bool aarch64_vectorize_vec_perm_const_ok (machine_mode vmode,
+ 						 const unsigned char *sel);
+ static int aarch64_address_cost (rtx, machine_mode, addr_space_t, bool);
++static bool aarch64_builtin_support_vector_misalignment (machine_mode mode,
++							 const_tree type,
++							 int misalignment,
++							 bool is_packed);
+ 
+ /* Major revision number of the ARM Architecture implemented by the target.  */
+ unsigned aarch64_architecture_version;
+@@ -152,7 +156,7 @@ enum aarch64_processor aarch64_tune = cortexa53;
+ unsigned long aarch64_tune_flags = 0;
+ 
+ /* Global flag for PC relative loads.  */
+-bool aarch64_nopcrelative_literal_loads;
++bool aarch64_pcrelative_literal_loads;
+ 
+ /* Support for command line parsing of boolean flags in the tuning
+    structures.  */
+@@ -250,6 +254,38 @@ static const struct cpu_addrcost_table xgene1_addrcost_table =
+   0, /* imm_offset  */
+ };
+ 
++static const struct cpu_addrcost_table qdf24xx_addrcost_table =
++{
++    {
++      1, /* hi  */
++      0, /* si  */
++      0, /* di  */
++      1, /* ti  */
++    },
++  0, /* pre_modify  */
++  0, /* post_modify  */
++  0, /* register_offset  */
++  0, /* register_sextend  */
++  0, /* register_zextend  */
++  0 /* imm_offset  */
++};
++
++static const struct cpu_addrcost_table vulcan_addrcost_table =
++{
++    {
++      0, /* hi  */
++      0, /* si  */
++      0, /* di  */
++      2, /* ti  */
++    },
++  0, /* pre_modify  */
++  0, /* post_modify  */
++  2, /* register_offset  */
++  3, /* register_sextend  */
++  3, /* register_zextend  */
++  0, /* imm_offset  */
++};
++
+ static const struct cpu_regmove_cost generic_regmove_cost =
+ {
+   1, /* GP2GP  */
+@@ -308,13 +344,33 @@ static const struct cpu_regmove_cost xgene1_regmove_cost =
+   2 /* FP2FP  */
+ };
+ 
++static const struct cpu_regmove_cost qdf24xx_regmove_cost =
++{
++  2, /* GP2GP  */
++  /* Avoid the use of int<->fp moves for spilling.  */
++  6, /* GP2FP  */
++  6, /* FP2GP  */
++  4 /* FP2FP  */
++};
++
++static const struct cpu_regmove_cost vulcan_regmove_cost =
++{
++  1, /* GP2GP  */
++  /* Avoid the use of int<->fp moves for spilling.  */
++  8, /* GP2FP  */
++  8, /* FP2GP  */
++  4  /* FP2FP  */
++};
++
+ /* Generic costs for vector insn classes.  */
+ static const struct cpu_vector_cost generic_vector_cost =
+ {
+-  1, /* scalar_stmt_cost  */
++  1, /* scalar_int_stmt_cost  */
++  1, /* scalar_fp_stmt_cost  */
+   1, /* scalar_load_cost  */
+   1, /* scalar_store_cost  */
+-  1, /* vec_stmt_cost  */
++  1, /* vec_int_stmt_cost  */
++  1, /* vec_fp_stmt_cost  */
+   2, /* vec_permute_cost  */
+   1, /* vec_to_scalar_cost  */
+   1, /* scalar_to_vec_cost  */
+@@ -326,18 +382,40 @@ static const struct cpu_vector_cost generic_vector_cost =
+   1 /* cond_not_taken_branch_cost  */
+ };
+ 
++/* ThunderX costs for vector insn classes.  */
++static const struct cpu_vector_cost thunderx_vector_cost =
++{
++  1, /* scalar_int_stmt_cost  */
++  1, /* scalar_fp_stmt_cost  */
++  3, /* scalar_load_cost  */
++  1, /* scalar_store_cost  */
++  4, /* vec_int_stmt_cost  */
++  4, /* vec_fp_stmt_cost  */
++  4, /* vec_permute_cost  */
++  2, /* vec_to_scalar_cost  */
++  2, /* scalar_to_vec_cost  */
++  3, /* vec_align_load_cost  */
++  10, /* vec_unalign_load_cost  */
++  10, /* vec_unalign_store_cost  */
++  1, /* vec_store_cost  */
++  3, /* cond_taken_branch_cost  */
++  3 /* cond_not_taken_branch_cost  */
++};
++
+ /* Generic costs for vector insn classes.  */
+ static const struct cpu_vector_cost cortexa57_vector_cost =
+ {
+-  1, /* scalar_stmt_cost  */
++  1, /* scalar_int_stmt_cost  */
++  1, /* scalar_fp_stmt_cost  */
+   4, /* scalar_load_cost  */
+   1, /* scalar_store_cost  */
+-  3, /* vec_stmt_cost  */
++  2, /* vec_int_stmt_cost  */
++  2, /* vec_fp_stmt_cost  */
+   3, /* vec_permute_cost  */
+   8, /* vec_to_scalar_cost  */
+   8, /* scalar_to_vec_cost  */
+-  5, /* vec_align_load_cost  */
+-  5, /* vec_unalign_load_cost  */
++  4, /* vec_align_load_cost  */
++  4, /* vec_unalign_load_cost  */
+   1, /* vec_unalign_store_cost  */
+   1, /* vec_store_cost  */
+   1, /* cond_taken_branch_cost  */
+@@ -346,10 +424,12 @@ static const struct cpu_vector_cost cortexa57_vector_cost =
+ 
+ static const struct cpu_vector_cost exynosm1_vector_cost =
+ {
+-  1, /* scalar_stmt_cost  */
++  1, /* scalar_int_stmt_cost  */
++  1, /* scalar_fp_stmt_cost  */
+   5, /* scalar_load_cost  */
+   1, /* scalar_store_cost  */
+-  3, /* vec_stmt_cost  */
++  3, /* vec_int_stmt_cost  */
++  3, /* vec_fp_stmt_cost  */
+   3, /* vec_permute_cost  */
+   3, /* vec_to_scalar_cost  */
+   3, /* scalar_to_vec_cost  */
+@@ -364,10 +444,12 @@ static const struct cpu_vector_cost exynosm1_vector_cost =
+ /* Generic costs for vector insn classes.  */
+ static const struct cpu_vector_cost xgene1_vector_cost =
+ {
+-  1, /* scalar_stmt_cost  */
++  1, /* scalar_int_stmt_cost  */
++  1, /* scalar_fp_stmt_cost  */
+   5, /* scalar_load_cost  */
+   1, /* scalar_store_cost  */
+-  2, /* vec_stmt_cost  */
++  2, /* vec_int_stmt_cost  */
++  2, /* vec_fp_stmt_cost  */
+   2, /* vec_permute_cost  */
+   4, /* vec_to_scalar_cost  */
+   4, /* scalar_to_vec_cost  */
+@@ -379,11 +461,31 @@ static const struct cpu_vector_cost xgene1_vector_cost =
+   1 /* cond_not_taken_branch_cost  */
+ };
+ 
++/* Costs for vector insn classes for Vulcan.  */
++static const struct cpu_vector_cost vulcan_vector_cost =
++{
++  1, /* scalar_int_stmt_cost  */
++  6, /* scalar_fp_stmt_cost  */
++  4, /* scalar_load_cost  */
++  1, /* scalar_store_cost  */
++  5, /* vec_int_stmt_cost  */
++  6, /* vec_fp_stmt_cost  */
++  3, /* vec_permute_cost  */
++  6, /* vec_to_scalar_cost  */
++  5, /* scalar_to_vec_cost  */
++  8, /* vec_align_load_cost  */
++  8, /* vec_unalign_load_cost  */
++  4, /* vec_unalign_store_cost  */
++  4, /* vec_store_cost  */
++  2, /* cond_taken_branch_cost  */
++  1  /* cond_not_taken_branch_cost  */
++};
++
+ /* Generic costs for branch instructions.  */
+ static const struct cpu_branch_cost generic_branch_cost =
+ {
+-  2,  /* Predictable.  */
+-  2   /* Unpredictable.  */
++  1,  /* Predictable.  */
++  3   /* Unpredictable.  */
+ };
+ 
+ /* Branch costs for Cortex-A57.  */
+@@ -393,6 +495,37 @@ static const struct cpu_branch_cost cortexa57_branch_cost =
+   3   /* Unpredictable.  */
+ };
+ 
++/* Branch costs for Vulcan.  */
++static const struct cpu_branch_cost vulcan_branch_cost =
++{
++  1,  /* Predictable.  */
++  3   /* Unpredictable.  */
++};
++
++/* Generic approximation modes.  */
++static const cpu_approx_modes generic_approx_modes =
++{
++  AARCH64_APPROX_NONE,	/* division  */
++  AARCH64_APPROX_NONE,	/* sqrt  */
++  AARCH64_APPROX_NONE	/* recip_sqrt  */
++};
++
++/* Approximation modes for Exynos M1.  */
++static const cpu_approx_modes exynosm1_approx_modes =
++{
++  AARCH64_APPROX_NONE,	/* division  */
++  AARCH64_APPROX_ALL,	/* sqrt  */
++  AARCH64_APPROX_ALL	/* recip_sqrt  */
++};
++
++/* Approximation modes for X-Gene 1.  */
++static const cpu_approx_modes xgene1_approx_modes =
++{
++  AARCH64_APPROX_NONE,	/* division  */
++  AARCH64_APPROX_NONE,	/* sqrt  */
++  AARCH64_APPROX_ALL	/* recip_sqrt  */
++};
++
+ static const struct tune_params generic_tunings =
+ {
+   &cortexa57_extra_costs,
+@@ -400,9 +533,10 @@ static const struct tune_params generic_tunings =
+   &generic_regmove_cost,
+   &generic_vector_cost,
+   &generic_branch_cost,
++  &generic_approx_modes,
+   4, /* memmov_cost  */
+   2, /* issue_rate  */
+-  AARCH64_FUSE_NOTHING, /* fusible_ops  */
++  (AARCH64_FUSE_AES_AESMC), /* fusible_ops  */
+   8,	/* function_align.  */
+   8,	/* jump_align.  */
+   4,	/* loop_align.  */
+@@ -423,14 +557,15 @@ static const struct tune_params cortexa35_tunings =
+   &generic_addrcost_table,
+   &cortexa53_regmove_cost,
+   &generic_vector_cost,
+-  &generic_branch_cost,
++  &cortexa57_branch_cost,
++  &generic_approx_modes,
+   4, /* memmov_cost  */
+   1, /* issue_rate  */
+-  (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
++  (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+    | AARCH64_FUSE_MOVK_MOVK | AARCH64_FUSE_ADRP_LDR), /* fusible_ops  */
+-  8,	/* function_align.  */
++  16,	/* function_align.  */
+   8,	/* jump_align.  */
+-  4,	/* loop_align.  */
++  8,	/* loop_align.  */
+   2,	/* int_reassoc_width.  */
+   4,	/* fp_reassoc_width.  */
+   1,	/* vec_reassoc_width.  */
+@@ -448,14 +583,15 @@ static const struct tune_params cortexa53_tunings =
+   &generic_addrcost_table,
+   &cortexa53_regmove_cost,
+   &generic_vector_cost,
+-  &generic_branch_cost,
++  &cortexa57_branch_cost,
++  &generic_approx_modes,
+   4, /* memmov_cost  */
+   2, /* issue_rate  */
+   (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+    | AARCH64_FUSE_MOVK_MOVK | AARCH64_FUSE_ADRP_LDR), /* fusible_ops  */
+-  8,	/* function_align.  */
++  16,	/* function_align.  */
+   8,	/* jump_align.  */
+-  4,	/* loop_align.  */
++  8,	/* loop_align.  */
+   2,	/* int_reassoc_width.  */
+   4,	/* fp_reassoc_width.  */
+   1,	/* vec_reassoc_width.  */
+@@ -474,13 +610,14 @@ static const struct tune_params cortexa57_tunings =
+   &cortexa57_regmove_cost,
+   &cortexa57_vector_cost,
+   &cortexa57_branch_cost,
++  &generic_approx_modes,
+   4, /* memmov_cost  */
+   3, /* issue_rate  */
+   (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+    | AARCH64_FUSE_MOVK_MOVK), /* fusible_ops  */
+   16,	/* function_align.  */
+   8,	/* jump_align.  */
+-  4,	/* loop_align.  */
++  8,	/* loop_align.  */
+   2,	/* int_reassoc_width.  */
+   4,	/* fp_reassoc_width.  */
+   1,	/* vec_reassoc_width.  */
+@@ -498,14 +635,15 @@ static const struct tune_params cortexa72_tunings =
+   &cortexa57_addrcost_table,
+   &cortexa57_regmove_cost,
+   &cortexa57_vector_cost,
+-  &generic_branch_cost,
++  &cortexa57_branch_cost,
++  &generic_approx_modes,
+   4, /* memmov_cost  */
+   3, /* issue_rate  */
+   (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+    | AARCH64_FUSE_MOVK_MOVK), /* fusible_ops  */
+   16,	/* function_align.  */
+   8,	/* jump_align.  */
+-  4,	/* loop_align.  */
++  8,	/* loop_align.  */
+   2,	/* int_reassoc_width.  */
+   4,	/* fp_reassoc_width.  */
+   1,	/* vec_reassoc_width.  */
+@@ -513,7 +651,33 @@ static const struct tune_params cortexa72_tunings =
+   2,	/* min_div_recip_mul_df.  */
+   0,	/* max_case_values.  */
+   0,	/* cache_line_size.  */
+-  tune_params::AUTOPREFETCHER_OFF,	/* autoprefetcher_model.  */
++  tune_params::AUTOPREFETCHER_WEAK,	/* autoprefetcher_model.  */
++  (AARCH64_EXTRA_TUNE_NONE)	/* tune_flags.  */
++};
++
++static const struct tune_params cortexa73_tunings =
++{
++  &cortexa57_extra_costs,
++  &cortexa57_addrcost_table,
++  &cortexa57_regmove_cost,
++  &cortexa57_vector_cost,
++  &cortexa57_branch_cost,
++  &generic_approx_modes,
++  4, /* memmov_cost.  */
++  2, /* issue_rate.  */
++  (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
++   | AARCH64_FUSE_MOVK_MOVK | AARCH64_FUSE_ADRP_LDR), /* fusible_ops  */
++  16,	/* function_align.  */
++  8,	/* jump_align.  */
++  8,	/* loop_align.  */
++  2,	/* int_reassoc_width.  */
++  4,	/* fp_reassoc_width.  */
++  1,	/* vec_reassoc_width.  */
++  2,	/* min_div_recip_mul_sf.  */
++  2,	/* min_div_recip_mul_df.  */
++  0,	/* max_case_values.  */
++  0,	/* cache_line_size.  */
++  tune_params::AUTOPREFETCHER_WEAK,	/* autoprefetcher_model.  */
+   (AARCH64_EXTRA_TUNE_NONE)	/* tune_flags.  */
+ };
+ 
+@@ -524,6 +688,7 @@ static const struct tune_params exynosm1_tunings =
+   &exynosm1_regmove_cost,
+   &exynosm1_vector_cost,
+   &generic_branch_cost,
++  &exynosm1_approx_modes,
+   4,	/* memmov_cost  */
+   3,	/* issue_rate  */
+   (AARCH64_FUSE_AES_AESMC), /* fusible_ops  */
+@@ -538,7 +703,7 @@ static const struct tune_params exynosm1_tunings =
+   48,	/* max_case_values.  */
+   64,	/* cache_line_size.  */
+   tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model.  */
+-  (AARCH64_EXTRA_TUNE_APPROX_RSQRT) /* tune_flags.  */
++  (AARCH64_EXTRA_TUNE_NONE) /* tune_flags.  */
+ };
+ 
+ static const struct tune_params thunderx_tunings =
+@@ -546,8 +711,9 @@ static const struct tune_params thunderx_tunings =
+   &thunderx_extra_costs,
+   &generic_addrcost_table,
+   &thunderx_regmove_cost,
+-  &generic_vector_cost,
++  &thunderx_vector_cost,
+   &generic_branch_cost,
++  &generic_approx_modes,
+   6, /* memmov_cost  */
+   2, /* issue_rate  */
+   AARCH64_FUSE_CMP_BRANCH, /* fusible_ops  */
+@@ -562,7 +728,7 @@ static const struct tune_params thunderx_tunings =
+   0,	/* max_case_values.  */
+   0,	/* cache_line_size.  */
+   tune_params::AUTOPREFETCHER_OFF,	/* autoprefetcher_model.  */
+-  (AARCH64_EXTRA_TUNE_NONE)	/* tune_flags.  */
++  (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW)	/* tune_flags.  */
+ };
+ 
+ static const struct tune_params xgene1_tunings =
+@@ -572,6 +738,7 @@ static const struct tune_params xgene1_tunings =
+   &xgene1_regmove_cost,
+   &xgene1_vector_cost,
+   &generic_branch_cost,
++  &xgene1_approx_modes,
+   6, /* memmov_cost  */
+   4, /* issue_rate  */
+   AARCH64_FUSE_NOTHING, /* fusible_ops  */
+@@ -586,7 +753,58 @@ static const struct tune_params xgene1_tunings =
+   0,	/* max_case_values.  */
+   0,	/* cache_line_size.  */
+   tune_params::AUTOPREFETCHER_OFF,	/* autoprefetcher_model.  */
+-  (AARCH64_EXTRA_TUNE_APPROX_RSQRT)	/* tune_flags.  */
++  (AARCH64_EXTRA_TUNE_NONE)	/* tune_flags.  */
++};
++
++static const struct tune_params qdf24xx_tunings =
++{
++  &qdf24xx_extra_costs,
++  &qdf24xx_addrcost_table,
++  &qdf24xx_regmove_cost,
++  &generic_vector_cost,
++  &generic_branch_cost,
++  &generic_approx_modes,
++  4, /* memmov_cost  */
++  4, /* issue_rate  */
++  (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
++   | AARCH64_FUSE_MOVK_MOVK), /* fuseable_ops  */
++  16,	/* function_align.  */
++  8,	/* jump_align.  */
++  16,	/* loop_align.  */
++  2,	/* int_reassoc_width.  */
++  4,	/* fp_reassoc_width.  */
++  1,	/* vec_reassoc_width.  */
++  2,	/* min_div_recip_mul_sf.  */
++  2,	/* min_div_recip_mul_df.  */
++  0,	/* max_case_values.  */
++  64,	/* cache_line_size.  */
++  tune_params::AUTOPREFETCHER_STRONG,	/* autoprefetcher_model.  */
++  (AARCH64_EXTRA_TUNE_NONE)		/* tune_flags.  */
++};
++
++static const struct tune_params vulcan_tunings =
++{
++  &vulcan_extra_costs,
++  &vulcan_addrcost_table,
++  &vulcan_regmove_cost,
++  &vulcan_vector_cost,
++  &vulcan_branch_cost,
++  &generic_approx_modes,
++  4, /* memmov_cost.  */
++  4, /* issue_rate.  */
++  AARCH64_FUSE_NOTHING, /* fuseable_ops.  */
++  16,	/* function_align.  */
++  8,	/* jump_align.  */
++  16,	/* loop_align.  */
++  3,	/* int_reassoc_width.  */
++  2,	/* fp_reassoc_width.  */
++  2,	/* vec_reassoc_width.  */
++  2,	/* min_div_recip_mul_sf.  */
++  2,	/* min_div_recip_mul_df.  */
++  0,	/* max_case_values.  */
++  64,	/* cache_line_size.  */
++  tune_params::AUTOPREFETCHER_OFF,	/* autoprefetcher_model.  */
++  (AARCH64_EXTRA_TUNE_NONE)	/* tune_flags.  */
+ };
+ 
+ /* Support for fine-grained override of the tuning structures.  */
+@@ -663,16 +881,6 @@ struct aarch64_option_extension
+   const unsigned long flags_off;
+ };
+ 
+-/* ISA extensions in AArch64.  */
+-static const struct aarch64_option_extension all_extensions[] =
+-{
+-#define AARCH64_OPT_EXTENSION(NAME, X, FLAGS_ON, FLAGS_OFF, FEATURE_STRING) \
+-  {NAME, FLAGS_ON, FLAGS_OFF},
+-#include "aarch64-option-extensions.def"
+-#undef AARCH64_OPT_EXTENSION
+-  {NULL, 0, 0}
+-};
+-
+ typedef enum aarch64_cond_code
+ {
+   AARCH64_EQ = 0, AARCH64_NE, AARCH64_CS, AARCH64_CC, AARCH64_MI, AARCH64_PL,
+@@ -1186,10 +1394,14 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
+     case SYMBOL_SMALL_TLSGD:
+       {
+ 	rtx_insn *insns;
+-	rtx result = gen_rtx_REG (Pmode, R0_REGNUM);
++	machine_mode mode = GET_MODE (dest);
++	rtx result = gen_rtx_REG (mode, R0_REGNUM);
+ 
+ 	start_sequence ();
+-	aarch64_emit_call_insn (gen_tlsgd_small (result, imm));
++	if (TARGET_ILP32)
++	  aarch64_emit_call_insn (gen_tlsgd_small_si (result, imm));
++	else
++	  aarch64_emit_call_insn (gen_tlsgd_small_di (result, imm));
+ 	insns = get_insns ();
+ 	end_sequence ();
+ 
+@@ -1703,7 +1915,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
+ 	     we need to expand the literal pool access carefully.
+ 	     This is something that needs to be done in a number
+ 	     of places, so could well live as a separate function.  */
+-	  if (aarch64_nopcrelative_literal_loads)
++	  if (!aarch64_pcrelative_literal_loads)
+ 	    {
+ 	      gcc_assert (can_create_pseudo_p ());
+ 	      base = gen_reg_rtx (ptr_mode);
+@@ -1766,6 +1978,88 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
+   aarch64_internal_mov_immediate (dest, imm, true, GET_MODE (dest));
+ }
+ 
++/* Add DELTA to REGNUM in mode MODE.  SCRATCHREG can be used to hold a
++   temporary value if necessary.  FRAME_RELATED_P should be true if
++   the RTX_FRAME_RELATED flag should be set and CFA adjustments added
++   to the generated instructions.  If SCRATCHREG is known to hold
++   abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
++   immediate again.
++
++   Since this function may be used to adjust the stack pointer, we must
++   ensure that it cannot cause transient stack deallocation (for example
++   by first incrementing SP and then decrementing when adjusting by a
++   large immediate).  */
++
++static void
++aarch64_add_constant_internal (machine_mode mode, int regnum, int scratchreg,
++			       HOST_WIDE_INT delta, bool frame_related_p,
++			       bool emit_move_imm)
++{
++  HOST_WIDE_INT mdelta = abs_hwi (delta);
++  rtx this_rtx = gen_rtx_REG (mode, regnum);
++  rtx_insn *insn;
++
++  if (!mdelta)
++    return;
++
++  /* Single instruction adjustment.  */
++  if (aarch64_uimm12_shift (mdelta))
++    {
++      insn = emit_insn (gen_add2_insn (this_rtx, GEN_INT (delta)));
++      RTX_FRAME_RELATED_P (insn) = frame_related_p;
++      return;
++    }
++
++  /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
++     Only do this if mdelta is not a 16-bit move as adjusting using a move
++     is better.  */
++  if (mdelta < 0x1000000 && !aarch64_move_imm (mdelta, mode))
++    {
++      HOST_WIDE_INT low_off = mdelta & 0xfff;
++
++      low_off = delta < 0 ? -low_off : low_off;
++      insn = emit_insn (gen_add2_insn (this_rtx, GEN_INT (low_off)));
++      RTX_FRAME_RELATED_P (insn) = frame_related_p;
++      insn = emit_insn (gen_add2_insn (this_rtx, GEN_INT (delta - low_off)));
++      RTX_FRAME_RELATED_P (insn) = frame_related_p;
++      return;
++    }
++
++  /* Emit a move immediate if required and an addition/subtraction.  */
++  rtx scratch_rtx = gen_rtx_REG (mode, scratchreg);
++  if (emit_move_imm)
++    aarch64_internal_mov_immediate (scratch_rtx, GEN_INT (mdelta), true, mode);
++  insn = emit_insn (delta < 0 ? gen_sub2_insn (this_rtx, scratch_rtx)
++			      : gen_add2_insn (this_rtx, scratch_rtx));
++  if (frame_related_p)
++    {
++      RTX_FRAME_RELATED_P (insn) = frame_related_p;
++      rtx adj = plus_constant (mode, this_rtx, delta);
++      add_reg_note (insn , REG_CFA_ADJUST_CFA, gen_rtx_SET (this_rtx, adj));
++    }
++}
++
++static inline void
++aarch64_add_constant (machine_mode mode, int regnum, int scratchreg,
++		      HOST_WIDE_INT delta)
++{
++  aarch64_add_constant_internal (mode, regnum, scratchreg, delta, false, true);
++}
++
++static inline void
++aarch64_add_sp (int scratchreg, HOST_WIDE_INT delta, bool emit_move_imm)
++{
++  aarch64_add_constant_internal (Pmode, SP_REGNUM, scratchreg, delta,
++				 true, emit_move_imm);
++}
++
++static inline void
++aarch64_sub_sp (int scratchreg, HOST_WIDE_INT delta, bool frame_related_p)
++{
++  aarch64_add_constant_internal (Pmode, SP_REGNUM, scratchreg, -delta,
++				 frame_related_p, true);
++}
++
+ static bool
+ aarch64_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
+ 				 tree exp ATTRIBUTE_UNUSED)
+@@ -2388,11 +2682,19 @@ aarch64_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
+ 		     plus_constant (Pmode, stack_pointer_rtx, -first));
+ 
+       /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE.  */
+-      emit_set_insn (reg2,
+-		     plus_constant (Pmode, stack_pointer_rtx,
+-				    -(first + rounded_size)));
+-
+-
++      HOST_WIDE_INT adjustment = - (first + rounded_size);
++      if (! aarch64_uimm12_shift (adjustment))
++	{
++	  aarch64_internal_mov_immediate (reg2, GEN_INT (adjustment),
++					  true, Pmode);
++	  emit_set_insn (reg2, gen_rtx_PLUS (Pmode, stack_pointer_rtx, reg2));
++	}
++      else
++	{
++	  emit_set_insn (reg2,
++			 plus_constant (Pmode, stack_pointer_rtx, adjustment));
++	}
++	  	
+       /* Step 3: the loop
+ 
+ 	 do
+@@ -2491,7 +2793,7 @@ static void
+ aarch64_layout_frame (void)
+ {
+   HOST_WIDE_INT offset = 0;
+-  int regno;
++  int regno, last_fp_reg = INVALID_REGNUM;
+ 
+   if (reload_completed && cfun->machine->frame.laid_out)
+     return;
+@@ -2499,8 +2801,8 @@ aarch64_layout_frame (void)
+ #define SLOT_NOT_REQUIRED (-2)
+ #define SLOT_REQUIRED     (-1)
+ 
+-  cfun->machine->frame.wb_candidate1 = FIRST_PSEUDO_REGISTER;
+-  cfun->machine->frame.wb_candidate2 = FIRST_PSEUDO_REGISTER;
++  cfun->machine->frame.wb_candidate1 = INVALID_REGNUM;
++  cfun->machine->frame.wb_candidate2 = INVALID_REGNUM;
+ 
+   /* First mark all the registers that really need to be saved...  */
+   for (regno = R0_REGNUM; regno <= R30_REGNUM; regno++)
+@@ -2525,7 +2827,10 @@ aarch64_layout_frame (void)
+   for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
+     if (df_regs_ever_live_p (regno)
+ 	&& !call_used_regs[regno])
+-      cfun->machine->frame.reg_offset[regno] = SLOT_REQUIRED;
++      {
++	cfun->machine->frame.reg_offset[regno] = SLOT_REQUIRED;
++	last_fp_reg = regno;
++      }
+ 
+   if (frame_pointer_needed)
+     {
+@@ -2534,7 +2839,6 @@ aarch64_layout_frame (void)
+       cfun->machine->frame.wb_candidate1 = R29_REGNUM;
+       cfun->machine->frame.reg_offset[R30_REGNUM] = UNITS_PER_WORD;
+       cfun->machine->frame.wb_candidate2 = R30_REGNUM;
+-      cfun->machine->frame.hardfp_offset = 2 * UNITS_PER_WORD;
+       offset += 2 * UNITS_PER_WORD;
+     }
+ 
+@@ -2543,35 +2847,46 @@ aarch64_layout_frame (void)
+     if (cfun->machine->frame.reg_offset[regno] == SLOT_REQUIRED)
+       {
+ 	cfun->machine->frame.reg_offset[regno] = offset;
+-	if (cfun->machine->frame.wb_candidate1 == FIRST_PSEUDO_REGISTER)
++	if (cfun->machine->frame.wb_candidate1 == INVALID_REGNUM)
+ 	  cfun->machine->frame.wb_candidate1 = regno;
+-	else if (cfun->machine->frame.wb_candidate2 == FIRST_PSEUDO_REGISTER)
++	else if (cfun->machine->frame.wb_candidate2 == INVALID_REGNUM)
+ 	  cfun->machine->frame.wb_candidate2 = regno;
+ 	offset += UNITS_PER_WORD;
+       }
+ 
++  HOST_WIDE_INT max_int_offset = offset;
++  offset = ROUND_UP (offset, STACK_BOUNDARY / BITS_PER_UNIT);
++  bool has_align_gap = offset != max_int_offset;
++
+   for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
+     if (cfun->machine->frame.reg_offset[regno] == SLOT_REQUIRED)
+       {
++	/* If there is an alignment gap between integer and fp callee-saves,
++	   allocate the last fp register to it if possible.  */
++	if (regno == last_fp_reg && has_align_gap && (offset & 8) == 0)
++	  {
++	    cfun->machine->frame.reg_offset[regno] = max_int_offset;
++	    break;
++	  }
++
+ 	cfun->machine->frame.reg_offset[regno] = offset;
+-	if (cfun->machine->frame.wb_candidate1 == FIRST_PSEUDO_REGISTER)
++	if (cfun->machine->frame.wb_candidate1 == INVALID_REGNUM)
+ 	  cfun->machine->frame.wb_candidate1 = regno;
+-	else if (cfun->machine->frame.wb_candidate2 == FIRST_PSEUDO_REGISTER
++	else if (cfun->machine->frame.wb_candidate2 == INVALID_REGNUM
+ 		 && cfun->machine->frame.wb_candidate1 >= V0_REGNUM)
+ 	  cfun->machine->frame.wb_candidate2 = regno;
+ 	offset += UNITS_PER_WORD;
+       }
+ 
+-  cfun->machine->frame.padding0 =
+-    (ROUND_UP (offset, STACK_BOUNDARY / BITS_PER_UNIT) - offset);
+   offset = ROUND_UP (offset, STACK_BOUNDARY / BITS_PER_UNIT);
+ 
+   cfun->machine->frame.saved_regs_size = offset;
+ 
++  HOST_WIDE_INT varargs_and_saved_regs_size
++    = offset + cfun->machine->frame.saved_varargs_size;
++
+   cfun->machine->frame.hard_fp_offset
+-    = ROUND_UP (cfun->machine->frame.saved_varargs_size
+-		+ get_frame_size ()
+-		+ cfun->machine->frame.saved_regs_size,
++    = ROUND_UP (varargs_and_saved_regs_size + get_frame_size (),
+ 		STACK_BOUNDARY / BITS_PER_UNIT);
+ 
+   cfun->machine->frame.frame_size
+@@ -2579,15 +2894,92 @@ aarch64_layout_frame (void)
+ 		+ crtl->outgoing_args_size,
+ 		STACK_BOUNDARY / BITS_PER_UNIT);
+ 
++  cfun->machine->frame.locals_offset = cfun->machine->frame.saved_varargs_size;
++
++  cfun->machine->frame.initial_adjust = 0;
++  cfun->machine->frame.final_adjust = 0;
++  cfun->machine->frame.callee_adjust = 0;
++  cfun->machine->frame.callee_offset = 0;
++
++  HOST_WIDE_INT max_push_offset = 0;
++  if (cfun->machine->frame.wb_candidate2 != INVALID_REGNUM)
++    max_push_offset = 512;
++  else if (cfun->machine->frame.wb_candidate1 != INVALID_REGNUM)
++    max_push_offset = 256;
++
++  if (cfun->machine->frame.frame_size < max_push_offset
++      && crtl->outgoing_args_size == 0)
++    {
++      /* Simple, small frame with no outgoing arguments:
++	 stp reg1, reg2, [sp, -frame_size]!
++	 stp reg3, reg4, [sp, 16]  */
++      cfun->machine->frame.callee_adjust = cfun->machine->frame.frame_size;
++    }
++  else if ((crtl->outgoing_args_size
++	    + cfun->machine->frame.saved_regs_size < 512)
++	   && !(cfun->calls_alloca
++		&& cfun->machine->frame.hard_fp_offset < max_push_offset))
++    {
++      /* Frame with small outgoing arguments:
++	 sub sp, sp, frame_size
++	 stp reg1, reg2, [sp, outgoing_args_size]
++	 stp reg3, reg4, [sp, outgoing_args_size + 16]  */
++      cfun->machine->frame.initial_adjust = cfun->machine->frame.frame_size;
++      cfun->machine->frame.callee_offset
++	= cfun->machine->frame.frame_size - cfun->machine->frame.hard_fp_offset;
++    }
++  else if (cfun->machine->frame.hard_fp_offset < max_push_offset)
++    {
++      /* Frame with large outgoing arguments but a small local area:
++	 stp reg1, reg2, [sp, -hard_fp_offset]!
++	 stp reg3, reg4, [sp, 16]
++	 sub sp, sp, outgoing_args_size  */
++      cfun->machine->frame.callee_adjust = cfun->machine->frame.hard_fp_offset;
++      cfun->machine->frame.final_adjust
++	= cfun->machine->frame.frame_size - cfun->machine->frame.callee_adjust;
++    }
++  else if (!frame_pointer_needed
++	   && varargs_and_saved_regs_size < max_push_offset)
++    {
++      /* Frame with large local area and outgoing arguments (this pushes the
++	 callee-saves first, followed by the locals and outgoing area):
++	 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
++	 stp reg3, reg4, [sp, 16]
++	 sub sp, sp, frame_size - varargs_and_saved_regs_size  */
++      cfun->machine->frame.callee_adjust = varargs_and_saved_regs_size;
++      cfun->machine->frame.final_adjust
++	= cfun->machine->frame.frame_size - cfun->machine->frame.callee_adjust;
++      cfun->machine->frame.hard_fp_offset = cfun->machine->frame.callee_adjust;
++      cfun->machine->frame.locals_offset = cfun->machine->frame.hard_fp_offset;
++    }
++  else
++    {
++      /* Frame with large local area and outgoing arguments using frame pointer:
++	 sub sp, sp, hard_fp_offset
++	 stp x29, x30, [sp, 0]
++	 add x29, sp, 0
++	 stp reg3, reg4, [sp, 16]
++	 sub sp, sp, outgoing_args_size  */
++      cfun->machine->frame.initial_adjust = cfun->machine->frame.hard_fp_offset;
++      cfun->machine->frame.final_adjust
++	= cfun->machine->frame.frame_size - cfun->machine->frame.initial_adjust;
++    }
++
+   cfun->machine->frame.laid_out = true;
+ }
+ 
++/* Return true if the register REGNO is saved on entry to
++   the current function.  */
++
+ static bool
+ aarch64_register_saved_on_entry (int regno)
+ {
+   return cfun->machine->frame.reg_offset[regno] >= 0;
+ }
+ 
++/* Return the next register up from REGNO up to LIMIT for the callee
++   to save.  */
++
+ static unsigned
+ aarch64_next_callee_save (unsigned regno, unsigned limit)
+ {
+@@ -2596,6 +2988,9 @@ aarch64_next_callee_save (unsigned regno, unsigned limit)
+   return regno;
+ }
+ 
++/* Push the register number REGNO of mode MODE to the stack with write-back
++   adjusting the stack by ADJUSTMENT.  */
++
+ static void
+ aarch64_pushwb_single_reg (machine_mode mode, unsigned regno,
+ 			   HOST_WIDE_INT adjustment)
+@@ -2612,6 +3007,10 @@ aarch64_pushwb_single_reg (machine_mode mode, unsigned regno,
+   RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ 
++/* Generate and return an instruction to store the pair of registers
++   REG and REG2 of mode MODE to location BASE with write-back adjusting
++   the stack location BASE by ADJUSTMENT.  */
++
+ static rtx
+ aarch64_gen_storewb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
+ 			  HOST_WIDE_INT adjustment)
+@@ -2631,11 +3030,18 @@ aarch64_gen_storewb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
+     }
+ }
+ 
++/* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
++   stack pointer by ADJUSTMENT.  */
++
+ static void
+-aarch64_pushwb_pair_reg (machine_mode mode, unsigned regno1,
+-			 unsigned regno2, HOST_WIDE_INT adjustment)
++aarch64_push_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment)
+ {
+   rtx_insn *insn;
++  machine_mode mode = (regno1 <= R30_REGNUM) ? DImode : DFmode;
++
++  if (regno2 == INVALID_REGNUM)
++    return aarch64_pushwb_single_reg (mode, regno1, adjustment);
++
+   rtx reg1 = gen_rtx_REG (mode, regno1);
+   rtx reg2 = gen_rtx_REG (mode, regno2);
+ 
+@@ -2646,6 +3052,9 @@ aarch64_pushwb_pair_reg (machine_mode mode, unsigned regno1,
+   RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ 
++/* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
++   adjusting it by ADJUSTMENT afterwards.  */
++
+ static rtx
+ aarch64_gen_loadwb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
+ 			 HOST_WIDE_INT adjustment)
+@@ -2663,6 +3072,37 @@ aarch64_gen_loadwb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
+     }
+ }
+ 
++/* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
++   afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
++   into CFI_OPS.  */
++
++static void
++aarch64_pop_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment,
++		  rtx *cfi_ops)
++{
++  machine_mode mode = (regno1 <= R30_REGNUM) ? DImode : DFmode;
++  rtx reg1 = gen_rtx_REG (mode, regno1);
++
++  *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg1, *cfi_ops);
++
++  if (regno2 == INVALID_REGNUM)
++    {
++      rtx mem = plus_constant (Pmode, stack_pointer_rtx, adjustment);
++      mem = gen_rtx_POST_MODIFY (Pmode, stack_pointer_rtx, mem);
++      emit_move_insn (reg1, gen_rtx_MEM (mode, mem));
++    }
++  else
++    {
++      rtx reg2 = gen_rtx_REG (mode, regno2);
++      *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg2, *cfi_ops);
++      emit_insn (aarch64_gen_loadwb_pair (mode, stack_pointer_rtx, reg1,
++					  reg2, adjustment));
++    }
++}
++
++/* Generate and return a store pair instruction of mode MODE to store
++   register REG1 to MEM1 and register REG2 to MEM2.  */
++
+ static rtx
+ aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2,
+ 			rtx reg2)
+@@ -2680,6 +3120,9 @@ aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2,
+     }
+ }
+ 
++/* Generate and regurn a load pair isntruction of mode MODE to load register
++   REG1 from MEM1 and register REG2 from MEM2.  */
++
+ static rtx
+ aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2,
+ 		       rtx mem2)
+@@ -2697,6 +3140,9 @@ aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2,
+     }
+ }
+ 
++/* Emit code to save the callee-saved registers from register number START
++   to LIMIT to the stack at the location starting at offset START_OFFSET,
++   skipping any write-back candidates if SKIP_WB is true.  */
+ 
+ static void
+ aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset,
+@@ -2755,6 +3201,11 @@ aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset,
+     }
+ }
+ 
++/* Emit code to restore the callee registers of mode MODE from register
++   number START up to and including LIMIT.  Restore from the stack offset
++   START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
++   Write the appropriate REG_CFA_RESTORE notes into CFI_OPS.  */
++
+ static void
+ aarch64_restore_callee_saves (machine_mode mode,
+ 			      HOST_WIDE_INT start_offset, unsigned start,
+@@ -2849,23 +3300,16 @@ aarch64_restore_callee_saves (machine_mode mode,
+ void
+ aarch64_expand_prologue (void)
+ {
+-  /* sub sp, sp, #<frame_size>
+-     stp {fp, lr}, [sp, #<frame_size> - 16]
+-     add fp, sp, #<frame_size> - hardfp_offset
+-     stp {cs_reg}, [fp, #-16] etc.
+-
+-     sub sp, sp, <final_adjustment_if_any>
+-  */
+-  HOST_WIDE_INT frame_size, offset;
+-  HOST_WIDE_INT fp_offset;		/* Offset from hard FP to SP.  */
+-  HOST_WIDE_INT hard_fp_offset;
+-  rtx_insn *insn;
+-
+   aarch64_layout_frame ();
+ 
+-  offset = frame_size = cfun->machine->frame.frame_size;
+-  hard_fp_offset = cfun->machine->frame.hard_fp_offset;
+-  fp_offset = frame_size - hard_fp_offset;
++  HOST_WIDE_INT frame_size = cfun->machine->frame.frame_size;
++  HOST_WIDE_INT initial_adjust = cfun->machine->frame.initial_adjust;
++  HOST_WIDE_INT callee_adjust = cfun->machine->frame.callee_adjust;
++  HOST_WIDE_INT final_adjust = cfun->machine->frame.final_adjust;
++  HOST_WIDE_INT callee_offset = cfun->machine->frame.callee_offset;
++  unsigned reg1 = cfun->machine->frame.wb_candidate1;
++  unsigned reg2 = cfun->machine->frame.wb_candidate2;
++  rtx_insn *insn;
+ 
+   if (flag_stack_usage_info)
+     current_function_static_stack_size = frame_size;
+@@ -2882,129 +3326,28 @@ aarch64_expand_prologue (void)
+ 	aarch64_emit_probe_stack_range (STACK_CHECK_PROTECT, frame_size);
+     }
+ 
+-  /* Store pairs and load pairs have a range only -512 to 504.  */
+-  if (offset >= 512)
+-    {
+-      /* When the frame has a large size, an initial decrease is done on
+-	 the stack pointer to jump over the callee-allocated save area for
+-	 register varargs, the local variable area and/or the callee-saved
+-	 register area.  This will allow the pre-index write-back
+-	 store pair instructions to be used for setting up the stack frame
+-	 efficiently.  */
+-      offset = hard_fp_offset;
+-      if (offset >= 512)
+-	offset = cfun->machine->frame.saved_regs_size;
++  aarch64_sub_sp (IP0_REGNUM, initial_adjust, true);
+ 
+-      frame_size -= (offset + crtl->outgoing_args_size);
+-      fp_offset = 0;
++  if (callee_adjust != 0)
++    aarch64_push_regs (reg1, reg2, callee_adjust);
+ 
+-      if (frame_size >= 0x1000000)
+-	{
+-	  rtx op0 = gen_rtx_REG (Pmode, IP0_REGNUM);
+-	  emit_move_insn (op0, GEN_INT (-frame_size));
+-	  insn = emit_insn (gen_add2_insn (stack_pointer_rtx, op0));
+-
+-	  add_reg_note (insn, REG_CFA_ADJUST_CFA,
+-			gen_rtx_SET (stack_pointer_rtx,
+-				     plus_constant (Pmode, stack_pointer_rtx,
+-						    -frame_size)));
+-	  RTX_FRAME_RELATED_P (insn) = 1;
+-	}
+-      else if (frame_size > 0)
+-	{
+-	  int hi_ofs = frame_size & 0xfff000;
+-	  int lo_ofs = frame_size & 0x000fff;
+-
+-	  if (hi_ofs)
+-	    {
+-	      insn = emit_insn (gen_add2_insn
+-				(stack_pointer_rtx, GEN_INT (-hi_ofs)));
+-	      RTX_FRAME_RELATED_P (insn) = 1;
+-	    }
+-	  if (lo_ofs)
+-	    {
+-	      insn = emit_insn (gen_add2_insn
+-				(stack_pointer_rtx, GEN_INT (-lo_ofs)));
+-	      RTX_FRAME_RELATED_P (insn) = 1;
+-	    }
+-	}
+-    }
+-  else
+-    frame_size = -1;
+-
+-  if (offset > 0)
++  if (frame_pointer_needed)
+     {
+-      bool skip_wb = false;
+-
+-      if (frame_pointer_needed)
+-	{
+-	  skip_wb = true;
+-
+-	  if (fp_offset)
+-	    {
+-	      insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
+-					       GEN_INT (-offset)));
+-	      RTX_FRAME_RELATED_P (insn) = 1;
+-
+-	      aarch64_save_callee_saves (DImode, fp_offset, R29_REGNUM,
+-					 R30_REGNUM, false);
+-	    }
+-	  else
+-	    aarch64_pushwb_pair_reg (DImode, R29_REGNUM, R30_REGNUM, offset);
+-
+-	  /* Set up frame pointer to point to the location of the
+-	     previous frame pointer on the stack.  */
+-	  insn = emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
+-					   stack_pointer_rtx,
+-					   GEN_INT (fp_offset)));
+-	  RTX_FRAME_RELATED_P (insn) = 1;
+-	  emit_insn (gen_stack_tie (stack_pointer_rtx, hard_frame_pointer_rtx));
+-	}
+-      else
+-	{
+-	  unsigned reg1 = cfun->machine->frame.wb_candidate1;
+-	  unsigned reg2 = cfun->machine->frame.wb_candidate2;
+-
+-	  if (fp_offset
+-	      || reg1 == FIRST_PSEUDO_REGISTER
+-	      || (reg2 == FIRST_PSEUDO_REGISTER
+-		  && offset >= 256))
+-	    {
+-	      insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
+-					       GEN_INT (-offset)));
+-	      RTX_FRAME_RELATED_P (insn) = 1;
+-	    }
+-	  else
+-	    {
+-	      machine_mode mode1 = (reg1 <= R30_REGNUM) ? DImode : DFmode;
+-
+-	      skip_wb = true;
+-
+-	      if (reg2 == FIRST_PSEUDO_REGISTER)
+-		aarch64_pushwb_single_reg (mode1, reg1, offset);
+-	      else
+-		aarch64_pushwb_pair_reg (mode1, reg1, reg2, offset);
+-	    }
+-	}
+-
+-      aarch64_save_callee_saves (DImode, fp_offset, R0_REGNUM, R30_REGNUM,
+-				 skip_wb);
+-      aarch64_save_callee_saves (DFmode, fp_offset, V0_REGNUM, V31_REGNUM,
+-				 skip_wb);
++      if (callee_adjust == 0)
++	aarch64_save_callee_saves (DImode, callee_offset, R29_REGNUM,
++				   R30_REGNUM, false);
++      insn = emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
++				       stack_pointer_rtx,
++				       GEN_INT (callee_offset)));
++      RTX_FRAME_RELATED_P (insn) = 1;
++      emit_insn (gen_stack_tie (stack_pointer_rtx, hard_frame_pointer_rtx));
+     }
+ 
+-  /* when offset >= 512,
+-     sub sp, sp, #<outgoing_args_size> */
+-  if (frame_size > -1)
+-    {
+-      if (crtl->outgoing_args_size > 0)
+-	{
+-	  insn = emit_insn (gen_add2_insn
+-			    (stack_pointer_rtx,
+-			     GEN_INT (- crtl->outgoing_args_size)));
+-	  RTX_FRAME_RELATED_P (insn) = 1;
+-	}
+-    }
++  aarch64_save_callee_saves (DImode, callee_offset, R0_REGNUM, R30_REGNUM,
++			     callee_adjust != 0 || frame_pointer_needed);
++  aarch64_save_callee_saves (DFmode, callee_offset, V0_REGNUM, V31_REGNUM,
++			     callee_adjust != 0 || frame_pointer_needed);
++  aarch64_sub_sp (IP1_REGNUM, final_adjust, !frame_pointer_needed);
+ }
+ 
+ /* Return TRUE if we can use a simple_return insn.
+@@ -3027,151 +3370,80 @@ aarch64_use_return_insn_p (void)
+   return cfun->machine->frame.frame_size == 0;
+ }
+ 
+-/* Generate the epilogue instructions for returning from a function.  */
++/* Generate the epilogue instructions for returning from a function.
++   This is almost exactly the reverse of the prolog sequence, except
++   that we need to insert barriers to avoid scheduling loads that read
++   from a deallocated stack, and we optimize the unwind records by
++   emitting them all together if possible.  */
+ void
+ aarch64_expand_epilogue (bool for_sibcall)
+ {
+-  HOST_WIDE_INT frame_size, offset;
+-  HOST_WIDE_INT fp_offset;
+-  HOST_WIDE_INT hard_fp_offset;
+-  rtx_insn *insn;
+-  /* We need to add memory barrier to prevent read from deallocated stack.  */
+-  bool need_barrier_p = (get_frame_size () != 0
+-			 || cfun->machine->frame.saved_varargs_size
+-			 || crtl->calls_eh_return);
+-
+   aarch64_layout_frame ();
+ 
+-  offset = frame_size = cfun->machine->frame.frame_size;
+-  hard_fp_offset = cfun->machine->frame.hard_fp_offset;
+-  fp_offset = frame_size - hard_fp_offset;
++  HOST_WIDE_INT initial_adjust = cfun->machine->frame.initial_adjust;
++  HOST_WIDE_INT callee_adjust = cfun->machine->frame.callee_adjust;
++  HOST_WIDE_INT final_adjust = cfun->machine->frame.final_adjust;
++  HOST_WIDE_INT callee_offset = cfun->machine->frame.callee_offset;
++  unsigned reg1 = cfun->machine->frame.wb_candidate1;
++  unsigned reg2 = cfun->machine->frame.wb_candidate2;
++  rtx cfi_ops = NULL;
++  rtx_insn *insn;
+ 
+-  /* Store pairs and load pairs have a range only -512 to 504.  */
+-  if (offset >= 512)
+-    {
+-      offset = hard_fp_offset;
+-      if (offset >= 512)
+-	offset = cfun->machine->frame.saved_regs_size;
++  /* We need to add memory barrier to prevent read from deallocated stack.  */
++  bool need_barrier_p = (get_frame_size ()
++			 + cfun->machine->frame.saved_varargs_size) != 0;
+ 
+-      frame_size -= (offset + crtl->outgoing_args_size);
+-      fp_offset = 0;
+-      if (!frame_pointer_needed && crtl->outgoing_args_size > 0)
+-	{
+-	  insn = emit_insn (gen_add2_insn
+-			    (stack_pointer_rtx,
+-			     GEN_INT (crtl->outgoing_args_size)));
+-	  RTX_FRAME_RELATED_P (insn) = 1;
+-	}
++  /* Emit a barrier to prevent loads from a deallocated stack.  */
++  if (final_adjust > crtl->outgoing_args_size || cfun->calls_alloca
++      || crtl->calls_eh_return)
++    {
++      emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
++      need_barrier_p = false;
+     }
+-  else
+-    frame_size = -1;
+ 
+-  /* If there were outgoing arguments or we've done dynamic stack
+-     allocation, then restore the stack pointer from the frame
+-     pointer.  This is at most one insn and more efficient than using
+-     GCC's internal mechanism.  */
+-  if (frame_pointer_needed
+-      && (crtl->outgoing_args_size || cfun->calls_alloca))
++  /* Restore the stack pointer from the frame pointer if it may not
++     be the same as the stack pointer.  */
++  if (frame_pointer_needed && (final_adjust || cfun->calls_alloca))
+     {
+-      if (cfun->calls_alloca)
+-	emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
+-
+       insn = emit_insn (gen_add3_insn (stack_pointer_rtx,
+ 				       hard_frame_pointer_rtx,
+-				       GEN_INT (0)));
+-      offset = offset - fp_offset;
++				       GEN_INT (-callee_offset)));
++      /* If writeback is used when restoring callee-saves, the CFA
++	 is restored on the instruction doing the writeback.  */
++      RTX_FRAME_RELATED_P (insn) = callee_adjust == 0;
+     }
++  else
++    aarch64_add_sp (IP1_REGNUM, final_adjust, df_regs_ever_live_p (IP1_REGNUM));
+ 
+-  if (offset > 0)
+-    {
+-      unsigned reg1 = cfun->machine->frame.wb_candidate1;
+-      unsigned reg2 = cfun->machine->frame.wb_candidate2;
+-      bool skip_wb = true;
+-      rtx cfi_ops = NULL;
+-
+-      if (frame_pointer_needed)
+-	fp_offset = 0;
+-      else if (fp_offset
+-	       || reg1 == FIRST_PSEUDO_REGISTER
+-	       || (reg2 == FIRST_PSEUDO_REGISTER
+-		   && offset >= 256))
+-	skip_wb = false;
++  aarch64_restore_callee_saves (DImode, callee_offset, R0_REGNUM, R30_REGNUM,
++				callee_adjust != 0, &cfi_ops);
++  aarch64_restore_callee_saves (DFmode, callee_offset, V0_REGNUM, V31_REGNUM,
++				callee_adjust != 0, &cfi_ops);
+ 
+-      aarch64_restore_callee_saves (DImode, fp_offset, R0_REGNUM, R30_REGNUM,
+-				    skip_wb, &cfi_ops);
+-      aarch64_restore_callee_saves (DFmode, fp_offset, V0_REGNUM, V31_REGNUM,
+-				    skip_wb, &cfi_ops);
++  if (need_barrier_p)
++    emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
+ 
+-      if (need_barrier_p)
+-	emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
++  if (callee_adjust != 0)
++    aarch64_pop_regs (reg1, reg2, callee_adjust, &cfi_ops);
+ 
+-      if (skip_wb)
+-	{
+-	  machine_mode mode1 = (reg1 <= R30_REGNUM) ? DImode : DFmode;
+-	  rtx rreg1 = gen_rtx_REG (mode1, reg1);
+-
+-	  cfi_ops = alloc_reg_note (REG_CFA_RESTORE, rreg1, cfi_ops);
+-	  if (reg2 == FIRST_PSEUDO_REGISTER)
+-	    {
+-	      rtx mem = plus_constant (Pmode, stack_pointer_rtx, offset);
+-	      mem = gen_rtx_POST_MODIFY (Pmode, stack_pointer_rtx, mem);
+-	      mem = gen_rtx_MEM (mode1, mem);
+-	      insn = emit_move_insn (rreg1, mem);
+-	    }
+-	  else
+-	    {
+-	      rtx rreg2 = gen_rtx_REG (mode1, reg2);
+-
+-	      cfi_ops = alloc_reg_note (REG_CFA_RESTORE, rreg2, cfi_ops);
+-	      insn = emit_insn (aarch64_gen_loadwb_pair
+-				(mode1, stack_pointer_rtx, rreg1,
+-				 rreg2, offset));
+-	    }
+-	}
+-      else
+-	{
+-	  insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
+-					   GEN_INT (offset)));
+-	}
+-
+-      /* Reset the CFA to be SP + FRAME_SIZE.  */
+-      rtx new_cfa = stack_pointer_rtx;
+-      if (frame_size > 0)
+-	new_cfa = plus_constant (Pmode, new_cfa, frame_size);
+-      cfi_ops = alloc_reg_note (REG_CFA_DEF_CFA, new_cfa, cfi_ops);
+-      REG_NOTES (insn) = cfi_ops;
++  if (callee_adjust != 0 || initial_adjust > 65536)
++    {
++      /* Emit delayed restores and set the CFA to be SP + initial_adjust.  */
++      insn = get_last_insn ();
++      rtx new_cfa = plus_constant (Pmode, stack_pointer_rtx, initial_adjust);
++      REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA, new_cfa, cfi_ops);
+       RTX_FRAME_RELATED_P (insn) = 1;
++      cfi_ops = NULL;
+     }
+ 
+-  if (frame_size > 0)
+-    {
+-      if (need_barrier_p)
+-	emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
+-
+-      if (frame_size >= 0x1000000)
+-	{
+-	  rtx op0 = gen_rtx_REG (Pmode, IP0_REGNUM);
+-	  emit_move_insn (op0, GEN_INT (frame_size));
+-	  insn = emit_insn (gen_add2_insn (stack_pointer_rtx, op0));
+-	}
+-      else
+-	{
+-          int hi_ofs = frame_size & 0xfff000;
+-          int lo_ofs = frame_size & 0x000fff;
+-
+-	  if (hi_ofs && lo_ofs)
+-	    {
+-	      insn = emit_insn (gen_add2_insn
+-				(stack_pointer_rtx, GEN_INT (hi_ofs)));
+-	      RTX_FRAME_RELATED_P (insn) = 1;
+-	      frame_size = lo_ofs;
+-	    }
+-	  insn = emit_insn (gen_add2_insn
+-			    (stack_pointer_rtx, GEN_INT (frame_size)));
+-	}
++  aarch64_add_sp (IP0_REGNUM, initial_adjust, df_regs_ever_live_p (IP0_REGNUM));
+ 
+-      /* Reset the CFA to be SP + 0.  */
+-      add_reg_note (insn, REG_CFA_DEF_CFA, stack_pointer_rtx);
++  if (cfi_ops)
++    {
++      /* Emit delayed restores and reset the CFA to be SP.  */
++      insn = get_last_insn ();
++      cfi_ops = alloc_reg_note (REG_CFA_DEF_CFA, stack_pointer_rtx, cfi_ops);
++      REG_NOTES (insn) = cfi_ops;
+       RTX_FRAME_RELATED_P (insn) = 1;
+     }
+ 
+@@ -3227,122 +3499,6 @@ aarch64_eh_return_handler_rtx (void)
+   return tmp;
+ }
+ 
+-/* Possibly output code to build up a constant in a register.  For
+-   the benefit of the costs infrastructure, returns the number of
+-   instructions which would be emitted.  GENERATE inhibits or
+-   enables code generation.  */
+-
+-static int
+-aarch64_build_constant (int regnum, HOST_WIDE_INT val, bool generate)
+-{
+-  int insns = 0;
+-
+-  if (aarch64_bitmask_imm (val, DImode))
+-    {
+-      if (generate)
+-	emit_move_insn (gen_rtx_REG (Pmode, regnum), GEN_INT (val));
+-      insns = 1;
+-    }
+-  else
+-    {
+-      int i;
+-      int ncount = 0;
+-      int zcount = 0;
+-      HOST_WIDE_INT valp = val >> 16;
+-      HOST_WIDE_INT valm;
+-      HOST_WIDE_INT tval;
+-
+-      for (i = 16; i < 64; i += 16)
+-	{
+-	  valm = (valp & 0xffff);
+-
+-	  if (valm != 0)
+-	    ++ zcount;
+-
+-	  if (valm != 0xffff)
+-	    ++ ncount;
+-
+-	  valp >>= 16;
+-	}
+-
+-      /* zcount contains the number of additional MOVK instructions
+-	 required if the constant is built up with an initial MOVZ instruction,
+-	 while ncount is the number of MOVK instructions required if starting
+-	 with a MOVN instruction.  Choose the sequence that yields the fewest
+-	 number of instructions, preferring MOVZ instructions when they are both
+-	 the same.  */
+-      if (ncount < zcount)
+-	{
+-	  if (generate)
+-	    emit_move_insn (gen_rtx_REG (Pmode, regnum),
+-			    GEN_INT (val | ~(HOST_WIDE_INT) 0xffff));
+-	  tval = 0xffff;
+-	  insns++;
+-	}
+-      else
+-	{
+-	  if (generate)
+-	    emit_move_insn (gen_rtx_REG (Pmode, regnum),
+-			    GEN_INT (val & 0xffff));
+-	  tval = 0;
+-	  insns++;
+-	}
+-
+-      val >>= 16;
+-
+-      for (i = 16; i < 64; i += 16)
+-	{
+-	  if ((val & 0xffff) != tval)
+-	    {
+-	      if (generate)
+-		emit_insn (gen_insv_immdi (gen_rtx_REG (Pmode, regnum),
+-					   GEN_INT (i),
+-					   GEN_INT (val & 0xffff)));
+-	      insns++;
+-	    }
+-	  val >>= 16;
+-	}
+-    }
+-  return insns;
+-}
+-
+-static void
+-aarch64_add_constant (int regnum, int scratchreg, HOST_WIDE_INT delta)
+-{
+-  HOST_WIDE_INT mdelta = delta;
+-  rtx this_rtx = gen_rtx_REG (Pmode, regnum);
+-  rtx scratch_rtx = gen_rtx_REG (Pmode, scratchreg);
+-
+-  if (mdelta < 0)
+-    mdelta = -mdelta;
+-
+-  if (mdelta >= 4096 * 4096)
+-    {
+-      (void) aarch64_build_constant (scratchreg, delta, true);
+-      emit_insn (gen_add3_insn (this_rtx, this_rtx, scratch_rtx));
+-    }
+-  else if (mdelta > 0)
+-    {
+-      if (mdelta >= 4096)
+-	{
+-	  emit_insn (gen_rtx_SET (scratch_rtx, GEN_INT (mdelta / 4096)));
+-	  rtx shift = gen_rtx_ASHIFT (Pmode, scratch_rtx, GEN_INT (12));
+-	  if (delta < 0)
+-	    emit_insn (gen_rtx_SET (this_rtx,
+-				    gen_rtx_MINUS (Pmode, this_rtx, shift)));
+-	  else
+-	    emit_insn (gen_rtx_SET (this_rtx,
+-				    gen_rtx_PLUS (Pmode, this_rtx, shift)));
+-	}
+-      if (mdelta % 4096 != 0)
+-	{
+-	  scratch_rtx = GEN_INT ((delta < 0 ? -1 : 1) * (mdelta % 4096));
+-	  emit_insn (gen_rtx_SET (this_rtx,
+-				  gen_rtx_PLUS (Pmode, this_rtx, scratch_rtx)));
+-	}
+-    }
+-}
+-
+ /* Output code to add DELTA to the first argument, and then jump
+    to FUNCTION.  Used for C++ multiple inheritance.  */
+ static void
+@@ -3363,7 +3519,7 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+   emit_note (NOTE_INSN_PROLOGUE_END);
+ 
+   if (vcall_offset == 0)
+-    aarch64_add_constant (this_regno, IP1_REGNUM, delta);
++    aarch64_add_constant (Pmode, this_regno, IP1_REGNUM, delta);
+   else
+     {
+       gcc_assert ((vcall_offset & (POINTER_BYTES - 1)) == 0);
+@@ -3379,7 +3535,7 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+ 	    addr = gen_rtx_PRE_MODIFY (Pmode, this_rtx,
+ 				       plus_constant (Pmode, this_rtx, delta));
+ 	  else
+-	    aarch64_add_constant (this_regno, IP1_REGNUM, delta);
++	    aarch64_add_constant (Pmode, this_regno, IP1_REGNUM, delta);
+ 	}
+ 
+       if (Pmode == ptr_mode)
+@@ -3393,7 +3549,8 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+ 	  addr = plus_constant (Pmode, temp0, vcall_offset);
+       else
+ 	{
+-	  (void) aarch64_build_constant (IP1_REGNUM, vcall_offset, true);
++	  aarch64_internal_mov_immediate (temp1, GEN_INT (vcall_offset), true,
++					  Pmode);
+ 	  addr = gen_rtx_PLUS (Pmode, temp0, temp1);
+ 	}
+ 
+@@ -3572,7 +3729,12 @@ aarch64_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
+   return aarch64_tls_referenced_p (x);
+ }
+ 
+-/* Implement TARGET_CASE_VALUES_THRESHOLD.  */
++/* Implement TARGET_CASE_VALUES_THRESHOLD.
++   The expansion for a table switch is quite expensive due to the number
++   of instructions, the table lookup and hard to predict indirect jump.
++   When optimizing for speed, and -O3 enabled, use the per-core tuning if 
++   set, otherwise use tables for > 16 cases as a tradeoff between size and
++   performance.  When optimizing for size, use the default setting.  */
+ 
+ static unsigned int
+ aarch64_case_values_threshold (void)
+@@ -3583,7 +3745,7 @@ aarch64_case_values_threshold (void)
+       && selected_cpu->tune->max_case_values != 0)
+     return selected_cpu->tune->max_case_values;
+   else
+-    return default_case_values_threshold ();
++    return optimize_size ? default_case_values_threshold () : 17;
+ }
+ 
+ /* Return true if register REGNO is a valid index register.
+@@ -3918,9 +4080,11 @@ aarch64_classify_address (struct aarch64_address_info *info,
+ 	     X,X: 7-bit signed scaled offset
+ 	     Q:   9-bit signed offset
+ 	     We conservatively require an offset representable in either mode.
+-	   */
++	     When performing the check for pairs of X registers i.e.  LDP/STP
++	     pass down DImode since that is the natural size of the LDP/STP
++	     instruction memory accesses.  */
+ 	  if (mode == TImode || mode == TFmode)
+-	    return (aarch64_offset_7bit_signed_scaled_p (mode, offset)
++	    return (aarch64_offset_7bit_signed_scaled_p (DImode, offset)
+ 		    && offset_9bit_signed_unscaled_p (mode, offset));
+ 
+ 	  /* A 7bit offset check because OImode will emit a ldp/stp
+@@ -4028,7 +4192,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
+ 	  return ((GET_CODE (sym) == LABEL_REF
+ 		   || (GET_CODE (sym) == SYMBOL_REF
+ 		       && CONSTANT_POOL_ADDRESS_P (sym)
+-		       && !aarch64_nopcrelative_literal_loads)));
++		       && aarch64_pcrelative_literal_loads)));
+ 	}
+       return false;
+ 
+@@ -4122,6 +4286,24 @@ aarch64_legitimate_address_p (machine_mode mode, rtx x,
+   return aarch64_classify_address (&addr, x, mode, outer_code, strict_p);
+ }
+ 
++/* Split an out-of-range address displacement into a base and offset.
++   Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
++   to increase opportunities for sharing the base address of different sizes.
++   For TI/TFmode and unaligned accesses use a 256-byte range.  */
++static bool
++aarch64_legitimize_address_displacement (rtx *disp, rtx *off, machine_mode mode)
++{
++  HOST_WIDE_INT mask = GET_MODE_SIZE (mode) < 4 ? 0xfff : 0x3fff;
++
++  if (mode == TImode || mode == TFmode ||
++      (INTVAL (*disp) & (GET_MODE_SIZE (mode) - 1)) != 0)
++    mask = 0xff;
++
++  *off = GEN_INT (INTVAL (*disp) & ~mask);
++  *disp = GEN_INT (INTVAL (*disp) & mask);
++  return true;
++}
++
+ /* Return TRUE if rtx X is immediate constant 0.0 */
+ bool
+ aarch64_float_const_zero_rtx_p (rtx x)
+@@ -4195,6 +4377,14 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
+       && (GET_MODE (x) == HImode || GET_MODE (x) == QImode))
+     return CC_NZmode;
+ 
++  /* Similarly, comparisons of zero_extends from shorter modes can
++     be performed using an ANDS with an immediate mask.  */
++  if (y == const0_rtx && GET_CODE (x) == ZERO_EXTEND
++      && (GET_MODE (x) == SImode || GET_MODE (x) == DImode)
++      && (GET_MODE (XEXP (x, 0)) == HImode || GET_MODE (XEXP (x, 0)) == QImode)
++      && (code == EQ || code == NE))
++    return CC_NZmode;
++
+   if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode)
+       && y == const0_rtx
+       && (code == EQ || code == NE || code == LT || code == GE)
+@@ -4222,14 +4412,6 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
+       && GET_CODE (x) == NEG)
+     return CC_Zmode;
+ 
+-  /* A compare of a mode narrower than SI mode against zero can be done
+-     by extending the value in the comparison.  */
+-  if ((GET_MODE (x) == QImode || GET_MODE (x) == HImode)
+-      && y == const0_rtx)
+-    /* Only use sign-extension if we really need it.  */
+-    return ((code == GT || code == GE || code == LE || code == LT)
+-	    ? CC_SESWPmode : CC_ZESWPmode);
+-
+   /* A test for unsigned overflow.  */
+   if ((GET_MODE (x) == DImode || GET_MODE (x) == TImode)
+       && code == NE
+@@ -4298,8 +4480,6 @@ aarch64_get_condition_code_1 (enum machine_mode mode, enum rtx_code comp_code)
+       break;
+ 
+     case CC_SWPmode:
+-    case CC_ZESWPmode:
+-    case CC_SESWPmode:
+       switch (comp_code)
+ 	{
+ 	case NE: return AARCH64_NE;
+@@ -4954,7 +5134,7 @@ aarch64_legitimize_address (rtx x, rtx /* orig_x  */, machine_mode mode)
+   if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
+     {
+       rtx base = XEXP (x, 0);
+-      rtx offset_rtx XEXP (x, 1);
++      rtx offset_rtx = XEXP (x, 1);
+       HOST_WIDE_INT offset = INTVAL (offset_rtx);
+ 
+       if (GET_CODE (base) == PLUS)
+@@ -5012,120 +5192,6 @@ aarch64_legitimize_address (rtx x, rtx /* orig_x  */, machine_mode mode)
+   return x;
+ }
+ 
+-/* Try a machine-dependent way of reloading an illegitimate address
+-   operand.  If we find one, push the reload and return the new rtx.  */
+-
+-rtx
+-aarch64_legitimize_reload_address (rtx *x_p,
+-				   machine_mode mode,
+-				   int opnum, int type,
+-				   int ind_levels ATTRIBUTE_UNUSED)
+-{
+-  rtx x = *x_p;
+-
+-  /* Do not allow mem (plus (reg, const)) if vector struct mode.  */
+-  if (aarch64_vect_struct_mode_p (mode)
+-      && GET_CODE (x) == PLUS
+-      && REG_P (XEXP (x, 0))
+-      && CONST_INT_P (XEXP (x, 1)))
+-    {
+-      rtx orig_rtx = x;
+-      x = copy_rtx (x);
+-      push_reload (orig_rtx, NULL_RTX, x_p, NULL,
+-		   BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
+-		   opnum, (enum reload_type) type);
+-      return x;
+-    }
+-
+-  /* We must recognize output that we have already generated ourselves.  */
+-  if (GET_CODE (x) == PLUS
+-      && GET_CODE (XEXP (x, 0)) == PLUS
+-      && REG_P (XEXP (XEXP (x, 0), 0))
+-      && CONST_INT_P (XEXP (XEXP (x, 0), 1))
+-      && CONST_INT_P (XEXP (x, 1)))
+-    {
+-      push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
+-		   BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
+-		   opnum, (enum reload_type) type);
+-      return x;
+-    }
+-
+-  /* We wish to handle large displacements off a base register by splitting
+-     the addend across an add and the mem insn.  This can cut the number of
+-     extra insns needed from 3 to 1.  It is only useful for load/store of a
+-     single register with 12 bit offset field.  */
+-  if (GET_CODE (x) == PLUS
+-      && REG_P (XEXP (x, 0))
+-      && CONST_INT_P (XEXP (x, 1))
+-      && HARD_REGISTER_P (XEXP (x, 0))
+-      && mode != TImode
+-      && mode != TFmode
+-      && aarch64_regno_ok_for_base_p (REGNO (XEXP (x, 0)), true))
+-    {
+-      HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
+-      HOST_WIDE_INT low = val & 0xfff;
+-      HOST_WIDE_INT high = val - low;
+-      HOST_WIDE_INT offs;
+-      rtx cst;
+-      machine_mode xmode = GET_MODE (x);
+-
+-      /* In ILP32, xmode can be either DImode or SImode.  */
+-      gcc_assert (xmode == DImode || xmode == SImode);
+-
+-      /* Reload non-zero BLKmode offsets.  This is because we cannot ascertain
+-	 BLKmode alignment.  */
+-      if (GET_MODE_SIZE (mode) == 0)
+-	return NULL_RTX;
+-
+-      offs = low % GET_MODE_SIZE (mode);
+-
+-      /* Align misaligned offset by adjusting high part to compensate.  */
+-      if (offs != 0)
+-	{
+-	  if (aarch64_uimm12_shift (high + offs))
+-	    {
+-	      /* Align down.  */
+-	      low = low - offs;
+-	      high = high + offs;
+-	    }
+-	  else
+-	    {
+-	      /* Align up.  */
+-	      offs = GET_MODE_SIZE (mode) - offs;
+-	      low = low + offs;
+-	      high = high + (low & 0x1000) - offs;
+-	      low &= 0xfff;
+-	    }
+-	}
+-
+-      /* Check for overflow.  */
+-      if (high + low != val)
+-	return NULL_RTX;
+-
+-      cst = GEN_INT (high);
+-      if (!aarch64_uimm12_shift (high))
+-	cst = force_const_mem (xmode, cst);
+-
+-      /* Reload high part into base reg, leaving the low part
+-	 in the mem instruction.
+-	 Note that replacing this gen_rtx_PLUS with plus_constant is
+-	 wrong in this case because we rely on the
+-	 (plus (plus reg c1) c2) structure being preserved so that
+-	 XEXP (*p, 0) in push_reload below uses the correct term.  */
+-      x = gen_rtx_PLUS (xmode,
+-			gen_rtx_PLUS (xmode, XEXP (x, 0), cst),
+-			GEN_INT (low));
+-
+-      push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
+-		   BASE_REG_CLASS, xmode, VOIDmode, 0, 0,
+-		   opnum, (enum reload_type) type);
+-      return x;
+-    }
+-
+-  return NULL_RTX;
+-}
+-
+-
+ /* Return the reload icode required for a constant pool in mode.  */
+ static enum insn_code
+ aarch64_constant_pool_reload_icode (machine_mode mode)
+@@ -5183,7 +5249,7 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
+   if (MEM_P (x) && GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)
+       && (SCALAR_FLOAT_MODE_P (GET_MODE (x))
+ 	  || targetm.vector_mode_supported_p (GET_MODE (x)))
+-      && aarch64_nopcrelative_literal_loads)
++      && !aarch64_pcrelative_literal_loads)
+     {
+       sri->icode = aarch64_constant_pool_reload_icode (mode);
+       return NO_REGS;
+@@ -5257,18 +5323,18 @@ aarch64_initial_elimination_offset (unsigned from, unsigned to)
+   if (to == HARD_FRAME_POINTER_REGNUM)
+     {
+       if (from == ARG_POINTER_REGNUM)
+-	return cfun->machine->frame.frame_size - crtl->outgoing_args_size;
++	return cfun->machine->frame.hard_fp_offset;
+ 
+       if (from == FRAME_POINTER_REGNUM)
+-	return (cfun->machine->frame.hard_fp_offset
+-		- cfun->machine->frame.saved_varargs_size);
++	return cfun->machine->frame.hard_fp_offset
++	       - cfun->machine->frame.locals_offset;
+     }
+ 
+   if (to == STACK_POINTER_REGNUM)
+     {
+       if (from == FRAME_POINTER_REGNUM)
+-	  return (cfun->machine->frame.frame_size
+-		  - cfun->machine->frame.saved_varargs_size);
++	  return cfun->machine->frame.frame_size
++		 - cfun->machine->frame.locals_offset;
+     }
+ 
+   return cfun->machine->frame.frame_size;
+@@ -5415,7 +5481,10 @@ aarch64_elf_asm_constructor (rtx symbol, int priority)
+   else
+     {
+       section *s;
+-      char buf[18];
++      /* While priority is known to be in range [0, 65535], so 18 bytes
++         would be enough, the compiler might not know that.  To avoid
++         -Wformat-truncation false positive, use a larger size.  */
++      char buf[23];
+       snprintf (buf, sizeof (buf), ".init_array.%.5u", priority);
+       s = get_section (buf, SECTION_WRITE, NULL);
+       switch_to_section (s);
+@@ -5432,7 +5501,10 @@ aarch64_elf_asm_destructor (rtx symbol, int priority)
+   else
+     {
+       section *s;
+-      char buf[18];
++      /* While priority is known to be in range [0, 65535], so 18 bytes
++         would be enough, the compiler might not know that.  To avoid
++         -Wformat-truncation false positive, use a larger size.  */
++      char buf[23];
+       snprintf (buf, sizeof (buf), ".fini_array.%.5u", priority);
+       s = get_section (buf, SECTION_WRITE, NULL);
+       switch_to_section (s);
+@@ -5517,7 +5589,7 @@ aarch64_uxt_size (int shift, HOST_WIDE_INT mask)
+ static inline bool
+ aarch64_can_use_per_function_literal_pools_p (void)
+ {
+-  return (!aarch64_nopcrelative_literal_loads
++  return (aarch64_pcrelative_literal_loads
+ 	  || aarch64_cmodel == AARCH64_CMODEL_LARGE);
+ }
+ 
+@@ -6136,6 +6208,19 @@ aarch64_extend_bitfield_pattern_p (rtx x)
+   return op;
+ }
+ 
++/* Return true if the mask and a shift amount from an RTX of the form
++   (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
++   mode MODE.  See the *andim_ashift<mode>_bfiz pattern.  */
++
++bool
++aarch64_mask_and_shift_for_ubfiz_p (machine_mode mode, rtx mask, rtx shft_amnt)
++{
++  return CONST_INT_P (mask) && CONST_INT_P (shft_amnt)
++	 && INTVAL (shft_amnt) < GET_MODE_BITSIZE (mode)
++	 && exact_log2 ((INTVAL (mask) >> INTVAL (shft_amnt)) + 1) >= 0
++	 && (INTVAL (mask) & ((1 << INTVAL (shft_amnt)) - 1)) == 0;
++}
++
+ /* Calculate the cost of calculating X, storing it in *COST.  Result
+    is true if the total cost of the operation has now been calculated.  */
+ static bool
+@@ -6401,10 +6486,6 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED,
+           /* TODO: A write to the CC flags possibly costs extra, this
+ 	     needs encoding in the cost tables.  */
+ 
+-          /* CC_ZESWPmode supports zero extend for free.  */
+-          if (mode == CC_ZESWPmode && GET_CODE (op0) == ZERO_EXTEND)
+-            op0 = XEXP (op0, 0);
+-
+ 	  mode = GET_MODE (op0);
+           /* ANDS.  */
+           if (GET_CODE (op0) == AND)
+@@ -6714,17 +6795,31 @@ cost_plus:
+ 
+       if (GET_MODE_CLASS (mode) == MODE_INT)
+ 	{
+-	  /* We possibly get the immediate for free, this is not
+-	     modelled.  */
+-	  if (CONST_INT_P (op1)
+-	      && aarch64_bitmask_imm (INTVAL (op1), mode))
++	  if (CONST_INT_P (op1))
+ 	    {
+-	      *cost += rtx_cost (op0, mode, (enum rtx_code) code, 0, speed);
++	      /* We have a mask + shift version of a UBFIZ
++		 i.e. the *andim_ashift<mode>_bfiz pattern.  */
++	      if (GET_CODE (op0) == ASHIFT
++		  && aarch64_mask_and_shift_for_ubfiz_p (mode, op1,
++							  XEXP (op0, 1)))
++		{
++		  *cost += rtx_cost (XEXP (op0, 0), mode,
++				     (enum rtx_code) code, 0, speed);
++		  if (speed)
++		    *cost += extra_cost->alu.bfx;
+ 
+-	      if (speed)
+-		*cost += extra_cost->alu.logical;
++		  return true;
++		}
++	      else if (aarch64_bitmask_imm (INTVAL (op1), mode))
++		{
++		/* We possibly get the immediate for free, this is not
++		   modelled.  */
++		  *cost += rtx_cost (op0, mode, (enum rtx_code) code, 0, speed);
++		  if (speed)
++		    *cost += extra_cost->alu.logical;
+ 
+-	      return true;
++		  return true;
++		}
+ 	    }
+ 	  else
+ 	    {
+@@ -6828,11 +6923,12 @@ cost_plus:
+ 	{
+ 	  int op_cost = rtx_cost (op0, VOIDmode, ZERO_EXTEND, 0, speed);
+ 
+-	  if (!op_cost && speed)
+-	    /* MOV.  */
+-	    *cost += extra_cost->alu.extend;
+-	  else
+-	    /* Free, the cost is that of the SI mode operation.  */
++	/* If OP_COST is non-zero, then the cost of the zero extend
++	   is effectively the cost of the inner operation.  Otherwise
++	   we have a MOV instruction and we take the cost from the MOV
++	   itself.  This is true independently of whether we are
++	   optimizing for space or time.  */
++	  if (op_cost)
+ 	    *cost = op_cost;
+ 
+ 	  return true;
+@@ -6862,8 +6958,8 @@ cost_plus:
+ 	    }
+ 	  else
+ 	    {
+-	      /* UXTB/UXTH.  */
+-	      *cost += extra_cost->alu.extend;
++	      /* We generate an AND instead of UXTB/UXTH.  */
++	      *cost += extra_cost->alu.logical;
+ 	    }
+ 	}
+       return false;
+@@ -7346,7 +7442,8 @@ cost_plus:
+       break;
+     }
+ 
+-  if (dump_file && (dump_flags & TDF_DETAILS))
++  if (dump_file
++      && flag_aarch64_verbose_cost)
+     fprintf (dump_file,
+       "\nFailed to cost RTX.  Assuming default cost.\n");
+ 
+@@ -7362,7 +7459,8 @@ aarch64_rtx_costs_wrapper (rtx x, machine_mode mode, int outer,
+ {
+   bool result = aarch64_rtx_costs (x, mode, outer, param, cost, speed);
+ 
+-  if (dump_file && (dump_flags & TDF_DETAILS))
++  if (dump_file
++      && flag_aarch64_verbose_cost)
+     {
+       print_rtl_single (dump_file, x);
+       fprintf (dump_file, "\n%s cost: %d (%s)\n",
+@@ -7442,12 +7540,12 @@ aarch64_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
+    to optimize 1.0/sqrt.  */
+ 
+ static bool
+-use_rsqrt_p (void)
++use_rsqrt_p (machine_mode mode)
+ {
+   return (!flag_trapping_math
+ 	  && flag_unsafe_math_optimizations
+-	  && ((aarch64_tune_params.extra_tuning_flags
+-	       & AARCH64_EXTRA_TUNE_APPROX_RSQRT)
++	  && ((aarch64_tune_params.approx_modes->recip_sqrt
++	       & AARCH64_APPROX_MODE (mode))
+ 	      || flag_mrecip_low_precision_sqrt));
+ }
+ 
+@@ -7457,89 +7555,225 @@ use_rsqrt_p (void)
+ static tree
+ aarch64_builtin_reciprocal (tree fndecl)
+ {
+-  if (!use_rsqrt_p ())
++  machine_mode mode = TYPE_MODE (TREE_TYPE (fndecl));
++
++  if (!use_rsqrt_p (mode))
+     return NULL_TREE;
+   return aarch64_builtin_rsqrt (DECL_FUNCTION_CODE (fndecl));
+ }
+ 
+ typedef rtx (*rsqrte_type) (rtx, rtx);
+ 
+-/* Select reciprocal square root initial estimate
+-   insn depending on machine mode.  */
++/* Select reciprocal square root initial estimate insn depending on machine
++   mode.  */
+ 
+-rsqrte_type
++static rsqrte_type
+ get_rsqrte_type (machine_mode mode)
+ {
+   switch (mode)
+   {
+-    case DFmode:   return gen_aarch64_rsqrte_df2;
+-    case SFmode:   return gen_aarch64_rsqrte_sf2;
+-    case V2DFmode: return gen_aarch64_rsqrte_v2df2;
+-    case V2SFmode: return gen_aarch64_rsqrte_v2sf2;
+-    case V4SFmode: return gen_aarch64_rsqrte_v4sf2;
++    case DFmode:   return gen_aarch64_rsqrtedf;
++    case SFmode:   return gen_aarch64_rsqrtesf;
++    case V2DFmode: return gen_aarch64_rsqrtev2df;
++    case V2SFmode: return gen_aarch64_rsqrtev2sf;
++    case V4SFmode: return gen_aarch64_rsqrtev4sf;
+     default: gcc_unreachable ();
+   }
+ }
+ 
+ typedef rtx (*rsqrts_type) (rtx, rtx, rtx);
+ 
+-/* Select reciprocal square root Newton-Raphson step
+-   insn depending on machine mode.  */
++/* Select reciprocal square root series step insn depending on machine mode.  */
+ 
+-rsqrts_type
++static rsqrts_type
+ get_rsqrts_type (machine_mode mode)
+ {
+   switch (mode)
+   {
+-    case DFmode:   return gen_aarch64_rsqrts_df3;
+-    case SFmode:   return gen_aarch64_rsqrts_sf3;
+-    case V2DFmode: return gen_aarch64_rsqrts_v2df3;
+-    case V2SFmode: return gen_aarch64_rsqrts_v2sf3;
+-    case V4SFmode: return gen_aarch64_rsqrts_v4sf3;
++    case DFmode:   return gen_aarch64_rsqrtsdf;
++    case SFmode:   return gen_aarch64_rsqrtssf;
++    case V2DFmode: return gen_aarch64_rsqrtsv2df;
++    case V2SFmode: return gen_aarch64_rsqrtsv2sf;
++    case V4SFmode: return gen_aarch64_rsqrtsv4sf;
+     default: gcc_unreachable ();
+   }
+ }
+ 
+-/* Emit instruction sequence to compute the reciprocal square root using the
+-   Newton-Raphson series.  Iterate over the series twice for SF
+-   and thrice for DF.  */
++/* Emit instruction sequence to compute either the approximate square root
++   or its approximate reciprocal, depending on the flag RECP, and return
++   whether the sequence was emitted or not.  */
+ 
+-void
+-aarch64_emit_approx_rsqrt (rtx dst, rtx src)
++bool
++aarch64_emit_approx_sqrt (rtx dst, rtx src, bool recp)
+ {
+-  machine_mode mode = GET_MODE (src);
+-  gcc_assert (
+-    mode == SFmode || mode == V2SFmode || mode == V4SFmode
+-	|| mode == DFmode || mode == V2DFmode);
++  machine_mode mode = GET_MODE (dst);
++
++  if (GET_MODE_INNER (mode) == HFmode)
++    return false;
+ 
+-  rtx xsrc = gen_reg_rtx (mode);
+-  emit_move_insn (xsrc, src);
+-  rtx x0 = gen_reg_rtx (mode);
++  machine_mode mmsk = mode_for_vector
++		        (int_mode_for_mode (GET_MODE_INNER (mode)),
++			 GET_MODE_NUNITS (mode));
++  bool use_approx_sqrt_p = (!recp
++			    && (flag_mlow_precision_sqrt
++			        || (aarch64_tune_params.approx_modes->sqrt
++				    & AARCH64_APPROX_MODE (mode))));
++  bool use_approx_rsqrt_p = (recp
++			     && (flag_mrecip_low_precision_sqrt
++				 || (aarch64_tune_params.approx_modes->recip_sqrt
++				     & AARCH64_APPROX_MODE (mode))));
++
++  if (!flag_finite_math_only
++      || flag_trapping_math
++      || !flag_unsafe_math_optimizations
++      || !(use_approx_sqrt_p || use_approx_rsqrt_p)
++      || optimize_function_for_size_p (cfun))
++    return false;
+ 
+-  emit_insn ((*get_rsqrte_type (mode)) (x0, xsrc));
++  rtx xmsk = gen_reg_rtx (mmsk);
++  if (!recp)
++    /* When calculating the approximate square root, compare the argument with
++       0.0 and create a mask.  */
++    emit_insn (gen_rtx_SET (xmsk, gen_rtx_NEG (mmsk, gen_rtx_EQ (mmsk, src,
++							  CONST0_RTX (mode)))));
+ 
+-  bool double_mode = (mode == DFmode || mode == V2DFmode);
++  /* Estimate the approximate reciprocal square root.  */
++  rtx xdst = gen_reg_rtx (mode);
++  emit_insn ((*get_rsqrte_type (mode)) (xdst, src));
+ 
+-  int iterations = double_mode ? 3 : 2;
++  /* Iterate over the series twice for SF and thrice for DF.  */
++  int iterations = (GET_MODE_INNER (mode) == DFmode) ? 3 : 2;
+ 
+-  /* Optionally iterate over the series one less time than otherwise.  */
+-  if (flag_mrecip_low_precision_sqrt)
++  /* Optionally iterate over the series once less for faster performance
++     while sacrificing the accuracy.  */
++  if ((recp && flag_mrecip_low_precision_sqrt)
++      || (!recp && flag_mlow_precision_sqrt))
+     iterations--;
+ 
+-  for (int i = 0; i < iterations; ++i)
++  /* Iterate over the series to calculate the approximate reciprocal square
++     root.  */
++  rtx x1 = gen_reg_rtx (mode);
++  while (iterations--)
+     {
+-      rtx x1 = gen_reg_rtx (mode);
+       rtx x2 = gen_reg_rtx (mode);
+-      rtx x3 = gen_reg_rtx (mode);
+-      emit_set_insn (x2, gen_rtx_MULT (mode, x0, x0));
++      emit_set_insn (x2, gen_rtx_MULT (mode, xdst, xdst));
++
++      emit_insn ((*get_rsqrts_type (mode)) (x1, src, x2));
++
++      if (iterations > 0)
++	emit_set_insn (xdst, gen_rtx_MULT (mode, xdst, x1));
++    }
++
++  if (!recp)
++    {
++      /* Qualify the approximate reciprocal square root when the argument is
++	 0.0 by squashing the intermediary result to 0.0.  */
++      rtx xtmp = gen_reg_rtx (mmsk);
++      emit_set_insn (xtmp, gen_rtx_AND (mmsk, gen_rtx_NOT (mmsk, xmsk),
++					      gen_rtx_SUBREG (mmsk, xdst, 0)));
++      emit_move_insn (xdst, gen_rtx_SUBREG (mode, xtmp, 0));
++
++      /* Calculate the approximate square root.  */
++      emit_set_insn (xdst, gen_rtx_MULT (mode, xdst, src));
++    }
++
++  /* Finalize the approximation.  */
++  emit_set_insn (dst, gen_rtx_MULT (mode, xdst, x1));
++
++  return true;
++}
++
++typedef rtx (*recpe_type) (rtx, rtx);
++
++/* Select reciprocal initial estimate insn depending on machine mode.  */
++
++static recpe_type
++get_recpe_type (machine_mode mode)
++{
++  switch (mode)
++  {
++    case SFmode:   return (gen_aarch64_frecpesf);
++    case V2SFmode: return (gen_aarch64_frecpev2sf);
++    case V4SFmode: return (gen_aarch64_frecpev4sf);
++    case DFmode:   return (gen_aarch64_frecpedf);
++    case V2DFmode: return (gen_aarch64_frecpev2df);
++    default:       gcc_unreachable ();
++  }
++}
++
++typedef rtx (*recps_type) (rtx, rtx, rtx);
++
++/* Select reciprocal series step insn depending on machine mode.  */
++
++static recps_type
++get_recps_type (machine_mode mode)
++{
++  switch (mode)
++  {
++    case SFmode:   return (gen_aarch64_frecpssf);
++    case V2SFmode: return (gen_aarch64_frecpsv2sf);
++    case V4SFmode: return (gen_aarch64_frecpsv4sf);
++    case DFmode:   return (gen_aarch64_frecpsdf);
++    case V2DFmode: return (gen_aarch64_frecpsv2df);
++    default:       gcc_unreachable ();
++  }
++}
++
++/* Emit the instruction sequence to compute the approximation for the division
++   of NUM by DEN in QUO and return whether the sequence was emitted or not.  */
++
++bool
++aarch64_emit_approx_div (rtx quo, rtx num, rtx den)
++{
++  machine_mode mode = GET_MODE (quo);
++
++  if (GET_MODE_INNER (mode) == HFmode)
++    return false;
++
++  bool use_approx_division_p = (flag_mlow_precision_div
++			        || (aarch64_tune_params.approx_modes->division
++				    & AARCH64_APPROX_MODE (mode)));
++
++  if (!flag_finite_math_only
++      || flag_trapping_math
++      || !flag_unsafe_math_optimizations
++      || optimize_function_for_size_p (cfun)
++      || !use_approx_division_p)
++    return false;
+ 
+-      emit_insn ((*get_rsqrts_type (mode)) (x3, xsrc, x2));
++  /* Estimate the approximate reciprocal.  */
++  rtx xrcp = gen_reg_rtx (mode);
++  emit_insn ((*get_recpe_type (mode)) (xrcp, den));
+ 
+-      emit_set_insn (x1, gen_rtx_MULT (mode, x0, x3));
+-      x0 = x1;
++  /* Iterate over the series twice for SF and thrice for DF.  */
++  int iterations = (GET_MODE_INNER (mode) == DFmode) ? 3 : 2;
++
++  /* Optionally iterate over the series once less for faster performance,
++     while sacrificing the accuracy.  */
++  if (flag_mlow_precision_div)
++    iterations--;
++
++  /* Iterate over the series to calculate the approximate reciprocal.  */
++  rtx xtmp = gen_reg_rtx (mode);
++  while (iterations--)
++    {
++      emit_insn ((*get_recps_type (mode)) (xtmp, xrcp, den));
++
++      if (iterations > 0)
++	emit_set_insn (xrcp, gen_rtx_MULT (mode, xrcp, xtmp));
++    }
++
++  if (num != CONST1_RTX (mode))
++    {
++      /* As the approximate reciprocal of DEN is already calculated, only
++	 calculate the approximate division when NUM is not 1.0.  */
++      rtx xnum = force_reg (mode, num);
++      emit_set_insn (xrcp, gen_rtx_MULT (mode, xrcp, xnum));
+     }
+ 
+-  emit_move_insn (dst, x0);
++  /* Finalize the approximation.  */
++  emit_set_insn (quo, gen_rtx_MULT (mode, xrcp, xtmp));
++  return true;
+ }
+ 
+ /* Return the number of instructions that can be issued per cycle.  */
+@@ -7579,50 +7813,55 @@ aarch64_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
+ 				    int misalign ATTRIBUTE_UNUSED)
+ {
+   unsigned elements;
++  const cpu_vector_cost *costs = aarch64_tune_params.vec_costs;
++  bool fp = false;
++
++  if (vectype != NULL)
++    fp = FLOAT_TYPE_P (vectype);
+ 
+   switch (type_of_cost)
+     {
+       case scalar_stmt:
+-	return aarch64_tune_params.vec_costs->scalar_stmt_cost;
++	return fp ? costs->scalar_fp_stmt_cost : costs->scalar_int_stmt_cost;
+ 
+       case scalar_load:
+-	return aarch64_tune_params.vec_costs->scalar_load_cost;
++	return costs->scalar_load_cost;
+ 
+       case scalar_store:
+-	return aarch64_tune_params.vec_costs->scalar_store_cost;
++	return costs->scalar_store_cost;
+ 
+       case vector_stmt:
+-	return aarch64_tune_params.vec_costs->vec_stmt_cost;
++	return fp ? costs->vec_fp_stmt_cost : costs->vec_int_stmt_cost;
+ 
+       case vector_load:
+-	return aarch64_tune_params.vec_costs->vec_align_load_cost;
++	return costs->vec_align_load_cost;
+ 
+       case vector_store:
+-	return aarch64_tune_params.vec_costs->vec_store_cost;
++	return costs->vec_store_cost;
+ 
+       case vec_to_scalar:
+-	return aarch64_tune_params.vec_costs->vec_to_scalar_cost;
++	return costs->vec_to_scalar_cost;
+ 
+       case scalar_to_vec:
+-	return aarch64_tune_params.vec_costs->scalar_to_vec_cost;
++	return costs->scalar_to_vec_cost;
+ 
+       case unaligned_load:
+-	return aarch64_tune_params.vec_costs->vec_unalign_load_cost;
++	return costs->vec_unalign_load_cost;
+ 
+       case unaligned_store:
+-	return aarch64_tune_params.vec_costs->vec_unalign_store_cost;
++	return costs->vec_unalign_store_cost;
+ 
+       case cond_branch_taken:
+-	return aarch64_tune_params.vec_costs->cond_taken_branch_cost;
++	return costs->cond_taken_branch_cost;
+ 
+       case cond_branch_not_taken:
+-	return aarch64_tune_params.vec_costs->cond_not_taken_branch_cost;
++	return costs->cond_not_taken_branch_cost;
+ 
+       case vec_perm:
+-	return aarch64_tune_params.vec_costs->vec_permute_cost;
++	return costs->vec_permute_cost;
+ 
+       case vec_promote_demote:
+-	return aarch64_tune_params.vec_costs->vec_stmt_cost;
++	return fp ? costs->vec_fp_stmt_cost : costs->vec_int_stmt_cost;
+ 
+       case vec_construct:
+         elements = TYPE_VECTOR_SUBPARTS (vectype);
+@@ -8043,32 +8282,37 @@ aarch64_override_options_after_change_1 (struct gcc_options *opts)
+ 	opts->x_align_functions = aarch64_tune_params.function_align;
+     }
+ 
+-  /* If nopcrelative_literal_loads is set on the command line, this
++  /* We default to no pc-relative literal loads.  */
++
++  aarch64_pcrelative_literal_loads = false;
++
++  /* If -mpc-relative-literal-loads is set on the command line, this
+      implies that the user asked for PC relative literal loads.  */
+-  if (opts->x_nopcrelative_literal_loads == 1)
+-    aarch64_nopcrelative_literal_loads = false;
++  if (opts->x_pcrelative_literal_loads == 1)
++    aarch64_pcrelative_literal_loads = true;
+ 
+-  /* If it is not set on the command line, we default to no pc
+-     relative literal loads, unless the workaround for Cortex-A53
+-     erratum 843419 is in effect.  */
+   /* This is PR70113. When building the Linux kernel with
+      CONFIG_ARM64_ERRATUM_843419, support for relocations
+      R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
+      removed from the kernel to avoid loading objects with possibly
+-     offending sequences. With nopcrelative_literal_loads, we would
++     offending sequences.  Without -mpc-relative-literal-loads we would
+      generate such relocations, preventing the kernel build from
+      succeeding.  */
+-  if (opts->x_nopcrelative_literal_loads == 2
+-      && !TARGET_FIX_ERR_A53_843419)
+-    aarch64_nopcrelative_literal_loads = true;
++  if (opts->x_pcrelative_literal_loads == 2
++      && TARGET_FIX_ERR_A53_843419)
++    aarch64_pcrelative_literal_loads = true;
+ 
+-  /* In the tiny memory model it makes no sense
+-     to disallow non PC relative literal pool loads
+-     as many other things will break anyway.  */
+-  if (opts->x_nopcrelative_literal_loads
+-      && (aarch64_cmodel == AARCH64_CMODEL_TINY
+-	  || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC))
+-    aarch64_nopcrelative_literal_loads = false;
++  /* In the tiny memory model it makes no sense to disallow PC relative
++     literal pool loads.  */
++  if (aarch64_cmodel == AARCH64_CMODEL_TINY
++      || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
++    aarch64_pcrelative_literal_loads = true;
++
++  /* When enabling the lower precision Newton series for the square root, also
++     enable it for the reciprocal square root, since the latter is an
++     intermediary step for the former.  */
++  if (flag_mlow_precision_sqrt)
++    flag_mrecip_low_precision_sqrt = true;
+ }
+ 
+ /* 'Unpack' up the internal tuning structs and update the options
+@@ -8148,13 +8392,13 @@ aarch64_validate_mcpu (const char *str, const struct processor **res,
+   switch (parse_res)
+     {
+       case AARCH64_PARSE_MISSING_ARG:
+-	error ("missing cpu name in -mcpu=%qs", str);
++	error ("missing cpu name in %<-mcpu=%s%>", str);
+ 	break;
+       case AARCH64_PARSE_INVALID_ARG:
+ 	error ("unknown value %qs for -mcpu", str);
+ 	break;
+       case AARCH64_PARSE_INVALID_FEATURE:
+-	error ("invalid feature modifier in -mcpu=%qs", str);
++	error ("invalid feature modifier in %<-mcpu=%s%>", str);
+ 	break;
+       default:
+ 	gcc_unreachable ();
+@@ -8181,13 +8425,13 @@ aarch64_validate_march (const char *str, const struct processor **res,
+   switch (parse_res)
+     {
+       case AARCH64_PARSE_MISSING_ARG:
+-	error ("missing arch name in -march=%qs", str);
++	error ("missing arch name in %<-march=%s%>", str);
+ 	break;
+       case AARCH64_PARSE_INVALID_ARG:
+ 	error ("unknown value %qs for -march", str);
+ 	break;
+       case AARCH64_PARSE_INVALID_FEATURE:
+-	error ("invalid feature modifier in -march=%qs", str);
++	error ("invalid feature modifier in %<-march=%s%>", str);
+ 	break;
+       default:
+ 	gcc_unreachable ();
+@@ -8213,7 +8457,7 @@ aarch64_validate_mtune (const char *str, const struct processor **res)
+   switch (parse_res)
+     {
+       case AARCH64_PARSE_MISSING_ARG:
+-	error ("missing cpu name in -mtune=%qs", str);
++	error ("missing cpu name in %<-mtune=%s%>", str);
+ 	break;
+       case AARCH64_PARSE_INVALID_ARG:
+ 	error ("unknown value %qs for -mtune", str);
+@@ -8371,9 +8615,6 @@ aarch64_override_options (void)
+      while processing functions with potential target attributes.  */
+   target_option_default_node = target_option_current_node
+       = build_target_option_node (&global_options);
+-
+-  aarch64_register_fma_steering ();
+-
+ }
+ 
+ /* Implement targetm.override_options_after_change.  */
+@@ -8925,8 +9166,12 @@ aarch64_process_target_attr (tree args, const char* pragma_or_attr)
+ 
+       return true;
+     }
+-  /* We expect to find a string to parse.  */
+-  gcc_assert (TREE_CODE (args) == STRING_CST);
++
++  if (TREE_CODE (args) != STRING_CST)
++    {
++      error ("attribute %<target%> argument not a string");
++      return false;
++    }
+ 
+   size_t len = strlen (TREE_STRING_POINTER (args));
+   char *str_to_check = (char *) alloca (len + 1);
+@@ -9276,15 +9521,18 @@ aarch64_classify_symbol (rtx x, rtx offset)
+       switch (aarch64_cmodel)
+ 	{
+ 	case AARCH64_CMODEL_TINY:
+-	  /* When we retreive symbol + offset address, we have to make sure
++	  /* When we retrieve symbol + offset address, we have to make sure
+ 	     the offset does not cause overflow of the final address.  But
+ 	     we have no way of knowing the address of symbol at compile time
+ 	     so we can't accurately say if the distance between the PC and
+ 	     symbol + offset is outside the addressible range of +/-1M in the
+ 	     TINY code model.  So we rely on images not being greater than
+ 	     1M and cap the offset at 1M and anything beyond 1M will have to
+-	     be loaded using an alternative mechanism.  */
+-	  if (SYMBOL_REF_WEAK (x)
++	     be loaded using an alternative mechanism.  Furthermore if the
++	     symbol is a weak reference to something that isn't known to
++	     resolve to a symbol in this module, then force to memory.  */
++	  if ((SYMBOL_REF_WEAK (x)
++	       && !aarch64_symbol_binds_local_p (x))
+ 	      || INTVAL (offset) < -1048575 || INTVAL (offset) > 1048575)
+ 	    return SYMBOL_FORCE_TO_MEM;
+ 	  return SYMBOL_TINY_ABSOLUTE;
+@@ -9292,7 +9540,8 @@ aarch64_classify_symbol (rtx x, rtx offset)
+ 	case AARCH64_CMODEL_SMALL:
+ 	  /* Same reasoning as the tiny code model, but the offset cap here is
+ 	     4G.  */
+-	  if (SYMBOL_REF_WEAK (x)
++	  if ((SYMBOL_REF_WEAK (x)
++	       && !aarch64_symbol_binds_local_p (x))
+ 	      || !IN_RANGE (INTVAL (offset), HOST_WIDE_INT_C (-4294967263),
+ 			    HOST_WIDE_INT_C (4294967264)))
+ 	    return SYMBOL_FORCE_TO_MEM;
+@@ -9314,8 +9563,7 @@ aarch64_classify_symbol (rtx x, rtx offset)
+ 	  /* This is alright even in PIC code as the constant
+ 	     pool reference is always PC relative and within
+ 	     the same translation unit.  */
+-	  if (nopcrelative_literal_loads
+-	      && CONSTANT_POOL_ADDRESS_P (x))
++	  if (CONSTANT_POOL_ADDRESS_P (x))
+ 	    return SYMBOL_SMALL_ABSOLUTE;
+ 	  else
+ 	    return SYMBOL_FORCE_TO_MEM;
+@@ -9451,6 +9699,13 @@ aarch64_build_builtin_va_list (void)
+ 			FIELD_DECL, get_identifier ("__vr_offs"),
+ 			integer_type_node);
+ 
++  /* Tell tree-stdarg pass about our internal offset fields.
++     NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
++     purpose to identify whether the code is updating va_list internal
++     offset fields through irregular way.  */
++  va_list_gpr_counter_field = f_groff;
++  va_list_fpr_counter_field = f_vroff;
++
+   DECL_ARTIFICIAL (f_stack) = 1;
+   DECL_ARTIFICIAL (f_grtop) = 1;
+   DECL_ARTIFICIAL (f_vrtop) = 1;
+@@ -9483,15 +9738,17 @@ aarch64_expand_builtin_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
+   tree f_stack, f_grtop, f_vrtop, f_groff, f_vroff;
+   tree stack, grtop, vrtop, groff, vroff;
+   tree t;
+-  int gr_save_area_size;
+-  int vr_save_area_size;
++  int gr_save_area_size = cfun->va_list_gpr_size;
++  int vr_save_area_size = cfun->va_list_fpr_size;
+   int vr_offset;
+ 
+   cum = &crtl->args.info;
+-  gr_save_area_size
+-    = (NUM_ARG_REGS - cum->aapcs_ncrn) * UNITS_PER_WORD;
+-  vr_save_area_size
+-    = (NUM_FP_ARG_REGS - cum->aapcs_nvrn) * UNITS_PER_VREG;
++  if (cfun->va_list_gpr_size)
++    gr_save_area_size = MIN ((NUM_ARG_REGS - cum->aapcs_ncrn) * UNITS_PER_WORD,
++			     cfun->va_list_gpr_size);
++  if (cfun->va_list_fpr_size)
++    vr_save_area_size = MIN ((NUM_FP_ARG_REGS - cum->aapcs_nvrn)
++			     * UNITS_PER_VREG, cfun->va_list_fpr_size);
+ 
+   if (!TARGET_FLOAT)
+     {
+@@ -9820,7 +10077,8 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
+ {
+   CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
+   CUMULATIVE_ARGS local_cum;
+-  int gr_saved, vr_saved;
++  int gr_saved = cfun->va_list_gpr_size;
++  int vr_saved = cfun->va_list_fpr_size;
+ 
+   /* The caller has advanced CUM up to, but not beyond, the last named
+      argument.  Advance a local copy of CUM past the last "real" named
+@@ -9828,9 +10086,14 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
+   local_cum = *cum;
+   aarch64_function_arg_advance (pack_cumulative_args(&local_cum), mode, type, true);
+ 
+-  /* Found out how many registers we need to save.  */
+-  gr_saved = NUM_ARG_REGS - local_cum.aapcs_ncrn;
+-  vr_saved = NUM_FP_ARG_REGS - local_cum.aapcs_nvrn;
++  /* Found out how many registers we need to save.
++     Honor tree-stdvar analysis results.  */
++  if (cfun->va_list_gpr_size)
++    gr_saved = MIN (NUM_ARG_REGS - local_cum.aapcs_ncrn,
++		    cfun->va_list_gpr_size / UNITS_PER_WORD);
++  if (cfun->va_list_fpr_size)
++    vr_saved = MIN (NUM_FP_ARG_REGS - local_cum.aapcs_nvrn,
++		    cfun->va_list_fpr_size / UNITS_PER_VREG);
+ 
+   if (!TARGET_FLOAT)
+     {
+@@ -9858,7 +10121,7 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
+ 	  /* We can't use move_block_from_reg, because it will use
+ 	     the wrong mode, storing D regs only.  */
+ 	  machine_mode mode = TImode;
+-	  int off, i;
++	  int off, i, vr_start;
+ 
+ 	  /* Set OFF to the offset from virtual_incoming_args_rtx of
+ 	     the first vector register.  The VR save area lies below
+@@ -9867,14 +10130,15 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
+ 			   STACK_BOUNDARY / BITS_PER_UNIT);
+ 	  off -= vr_saved * UNITS_PER_VREG;
+ 
+-	  for (i = local_cum.aapcs_nvrn; i < NUM_FP_ARG_REGS; ++i)
++	  vr_start = V0_REGNUM + local_cum.aapcs_nvrn;
++	  for (i = 0; i < vr_saved; ++i)
+ 	    {
+ 	      rtx ptr, mem;
+ 
+ 	      ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
+ 	      mem = gen_frame_mem (mode, ptr);
+ 	      set_mem_alias_set (mem, get_varargs_alias_set ());
+-	      aarch64_emit_move (mem, gen_rtx_REG (mode, V0_REGNUM + i));
++	      aarch64_emit_move (mem, gen_rtx_REG (mode, vr_start + i));
+ 	      off += UNITS_PER_VREG;
+ 	    }
+ 	}
+@@ -10836,33 +11100,6 @@ aarch64_simd_emit_reg_reg_move (rtx *operands, enum machine_mode mode,
+ 		      gen_rtx_REG (mode, rsrc + count - i - 1));
+ }
+ 
+-/* Compute and return the length of aarch64_simd_mov<mode>, where <mode> is
+-   one of VSTRUCT modes: OI, CI or XI.  */
+-int
+-aarch64_simd_attr_length_move (rtx_insn *insn)
+-{
+-  machine_mode mode;
+-
+-  extract_insn_cached (insn);
+-
+-  if (REG_P (recog_data.operand[0]) && REG_P (recog_data.operand[1]))
+-    {
+-      mode = GET_MODE (recog_data.operand[0]);
+-      switch (mode)
+-	{
+-	case OImode:
+-	  return 8;
+-	case CImode:
+-	  return 12;
+-	case XImode:
+-	  return 16;
+-	default:
+-	  gcc_unreachable ();
+-	}
+-    }
+-  return 4;
+-}
+-
+ /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
+    one of VSTRUCT modes: OI, CI, or XI.  */
+ int
+@@ -10896,6 +11133,37 @@ aarch64_simd_vector_alignment_reachable (const_tree type, bool is_packed)
+   return true;
+ }
+ 
++/* Return true if the vector misalignment factor is supported by the
++   target.  */
++static bool
++aarch64_builtin_support_vector_misalignment (machine_mode mode,
++					     const_tree type, int misalignment,
++					     bool is_packed)
++{
++  if (TARGET_SIMD && STRICT_ALIGNMENT)
++    {
++      /* Return if movmisalign pattern is not supported for this mode.  */
++      if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
++        return false;
++
++      if (misalignment == -1)
++	{
++	  /* Misalignment factor is unknown at compile time but we know
++	     it's word aligned.  */
++	  if (aarch64_simd_vector_alignment_reachable (type, is_packed))
++            {
++              int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
++
++              if (element_size != 64)
++                return true;
++            }
++	  return false;
++	}
++    }
++  return default_builtin_support_vector_misalignment (mode, type, misalignment,
++						      is_packed);
++}
++
+ /* If VALS is a vector constant that can be loaded into a register
+    using DUP, generate instructions to do so and return an RTX to
+    assign to the register.  Otherwise return NULL_RTX.  */
+@@ -11874,7 +12142,7 @@ aarch64_float_const_representable_p (rtx x)
+ 
+   /* If the low part of the mantissa has bits set we cannot represent
+      the value.  */
+-  if (w.elt (0) != 0)
++  if (w.ulow () != 0)
+     return false;
+   /* We have rejected the lower HOST_WIDE_INT, so update our
+      understanding of how many bits lie in the mantissa and
+@@ -11944,12 +12212,11 @@ aarch64_output_simd_mov_immediate (rtx const_vector,
+         info.value = GEN_INT (0);
+       else
+ 	{
+-#define buf_size 20
++	  const unsigned int buf_size = 20;
+ 	  char float_buf[buf_size] = {'\0'};
+ 	  real_to_decimal_for_mode (float_buf,
+ 				    CONST_DOUBLE_REAL_VALUE (info.value),
+ 				    buf_size, buf_size, 1, mode);
+-#undef buf_size
+ 
+ 	  if (lane_count == 1)
+ 	    snprintf (templ, sizeof (templ), "fmov\t%%d0, %s", float_buf);
+@@ -12183,6 +12450,8 @@ aarch64_evpc_trn (struct expand_vec_perm_d *d)
+ 	case V4SImode: gen = gen_aarch64_trn2v4si; break;
+ 	case V2SImode: gen = gen_aarch64_trn2v2si; break;
+ 	case V2DImode: gen = gen_aarch64_trn2v2di; break;
++	case V4HFmode: gen = gen_aarch64_trn2v4hf; break;
++	case V8HFmode: gen = gen_aarch64_trn2v8hf; break;
+ 	case V4SFmode: gen = gen_aarch64_trn2v4sf; break;
+ 	case V2SFmode: gen = gen_aarch64_trn2v2sf; break;
+ 	case V2DFmode: gen = gen_aarch64_trn2v2df; break;
+@@ -12201,6 +12470,8 @@ aarch64_evpc_trn (struct expand_vec_perm_d *d)
+ 	case V4SImode: gen = gen_aarch64_trn1v4si; break;
+ 	case V2SImode: gen = gen_aarch64_trn1v2si; break;
+ 	case V2DImode: gen = gen_aarch64_trn1v2di; break;
++	case V4HFmode: gen = gen_aarch64_trn1v4hf; break;
++	case V8HFmode: gen = gen_aarch64_trn1v8hf; break;
+ 	case V4SFmode: gen = gen_aarch64_trn1v4sf; break;
+ 	case V2SFmode: gen = gen_aarch64_trn1v2sf; break;
+ 	case V2DFmode: gen = gen_aarch64_trn1v2df; break;
+@@ -12266,6 +12537,8 @@ aarch64_evpc_uzp (struct expand_vec_perm_d *d)
+ 	case V4SImode: gen = gen_aarch64_uzp2v4si; break;
+ 	case V2SImode: gen = gen_aarch64_uzp2v2si; break;
+ 	case V2DImode: gen = gen_aarch64_uzp2v2di; break;
++	case V4HFmode: gen = gen_aarch64_uzp2v4hf; break;
++	case V8HFmode: gen = gen_aarch64_uzp2v8hf; break;
+ 	case V4SFmode: gen = gen_aarch64_uzp2v4sf; break;
+ 	case V2SFmode: gen = gen_aarch64_uzp2v2sf; break;
+ 	case V2DFmode: gen = gen_aarch64_uzp2v2df; break;
+@@ -12284,6 +12557,8 @@ aarch64_evpc_uzp (struct expand_vec_perm_d *d)
+ 	case V4SImode: gen = gen_aarch64_uzp1v4si; break;
+ 	case V2SImode: gen = gen_aarch64_uzp1v2si; break;
+ 	case V2DImode: gen = gen_aarch64_uzp1v2di; break;
++	case V4HFmode: gen = gen_aarch64_uzp1v4hf; break;
++	case V8HFmode: gen = gen_aarch64_uzp1v8hf; break;
+ 	case V4SFmode: gen = gen_aarch64_uzp1v4sf; break;
+ 	case V2SFmode: gen = gen_aarch64_uzp1v2sf; break;
+ 	case V2DFmode: gen = gen_aarch64_uzp1v2df; break;
+@@ -12354,6 +12629,8 @@ aarch64_evpc_zip (struct expand_vec_perm_d *d)
+ 	case V4SImode: gen = gen_aarch64_zip2v4si; break;
+ 	case V2SImode: gen = gen_aarch64_zip2v2si; break;
+ 	case V2DImode: gen = gen_aarch64_zip2v2di; break;
++	case V4HFmode: gen = gen_aarch64_zip2v4hf; break;
++	case V8HFmode: gen = gen_aarch64_zip2v8hf; break;
+ 	case V4SFmode: gen = gen_aarch64_zip2v4sf; break;
+ 	case V2SFmode: gen = gen_aarch64_zip2v2sf; break;
+ 	case V2DFmode: gen = gen_aarch64_zip2v2df; break;
+@@ -12372,6 +12649,8 @@ aarch64_evpc_zip (struct expand_vec_perm_d *d)
+ 	case V4SImode: gen = gen_aarch64_zip1v4si; break;
+ 	case V2SImode: gen = gen_aarch64_zip1v2si; break;
+ 	case V2DImode: gen = gen_aarch64_zip1v2di; break;
++	case V4HFmode: gen = gen_aarch64_zip1v4hf; break;
++	case V8HFmode: gen = gen_aarch64_zip1v8hf; break;
+ 	case V4SFmode: gen = gen_aarch64_zip1v4sf; break;
+ 	case V2SFmode: gen = gen_aarch64_zip1v2sf; break;
+ 	case V2DFmode: gen = gen_aarch64_zip1v2df; break;
+@@ -12416,6 +12695,8 @@ aarch64_evpc_ext (struct expand_vec_perm_d *d)
+     case V8HImode: gen = gen_aarch64_extv8hi; break;
+     case V2SImode: gen = gen_aarch64_extv2si; break;
+     case V4SImode: gen = gen_aarch64_extv4si; break;
++    case V4HFmode: gen = gen_aarch64_extv4hf; break;
++    case V8HFmode: gen = gen_aarch64_extv8hf; break;
+     case V2SFmode: gen = gen_aarch64_extv2sf; break;
+     case V4SFmode: gen = gen_aarch64_extv4sf; break;
+     case V2DImode: gen = gen_aarch64_extv2di; break;
+@@ -12491,6 +12772,8 @@ aarch64_evpc_rev (struct expand_vec_perm_d *d)
+ 	case V2SImode: gen = gen_aarch64_rev64v2si;  break;
+ 	case V4SFmode: gen = gen_aarch64_rev64v4sf;  break;
+ 	case V2SFmode: gen = gen_aarch64_rev64v2sf;  break;
++	case V8HFmode: gen = gen_aarch64_rev64v8hf;  break;
++	case V4HFmode: gen = gen_aarch64_rev64v4hf;  break;
+ 	default:
+ 	  return false;
+ 	}
+@@ -12734,24 +13017,6 @@ aarch64_vectorize_vec_perm_const_ok (machine_mode vmode,
+   return ret;
+ }
+ 
+-/* Implement target hook CANNOT_CHANGE_MODE_CLASS.  */
+-bool
+-aarch64_cannot_change_mode_class (machine_mode from,
+-				  machine_mode to,
+-				  enum reg_class rclass)
+-{
+-  /* We cannot allow word_mode subregs of full vector modes.
+-     Otherwise the middle-end will assume it's ok to store to
+-     (subreg:DI (reg:TI 100) 0) in order to modify only the low 64 bits
+-     of the 128-bit register.  However, after reload the subreg will
+-     be dropped leaving a plain DImode store.  See PR67609 for a more
+-     detailed dicussion.  In all other cases, we want to be permissive
+-     and return false.  */
+-  return (reg_classes_intersect_p (FP_REGS, rclass)
+-	  && GET_MODE_SIZE (to) == UNITS_PER_WORD
+-	  && GET_MODE_SIZE (from) > UNITS_PER_WORD);
+-}
+-
+ rtx
+ aarch64_reverse_mask (enum machine_mode mode)
+ {
+@@ -12773,7 +13038,14 @@ aarch64_reverse_mask (enum machine_mode mode)
+   return force_reg (V16QImode, mask);
+ }
+ 
+-/* Implement MODES_TIEABLE_P.  */
++/* Implement MODES_TIEABLE_P.  In principle we should always return true.
++   However due to issues with register allocation it is preferable to avoid
++   tieing integer scalar and FP scalar modes.  Executing integer operations
++   in general registers is better than treating them as scalar vector
++   operations.  This reduces latency and avoids redundant int<->FP moves.
++   So tie modes if they are either the same class, or vector modes with
++   other vector modes, vector structs or any scalar mode.
++*/
+ 
+ bool
+ aarch64_modes_tieable_p (machine_mode mode1, machine_mode mode2)
+@@ -12784,9 +13056,12 @@ aarch64_modes_tieable_p (machine_mode mode1, machine_mode mode2)
+   /* We specifically want to allow elements of "structure" modes to
+      be tieable to the structure.  This more general condition allows
+      other rarer situations too.  */
+-  if (TARGET_SIMD
+-      && aarch64_vector_mode_p (mode1)
+-      && aarch64_vector_mode_p (mode2))
++  if (aarch64_vector_mode_p (mode1) && aarch64_vector_mode_p (mode2))
++    return true;
++
++  /* Also allow any scalar modes with vectors.  */
++  if (aarch64_vector_mode_supported_p (mode1)
++      || aarch64_vector_mode_supported_p (mode2))
+     return true;
+ 
+   return false;
+@@ -12950,6 +13225,63 @@ aarch64_expand_movmem (rtx *operands)
+   return true;
+ }
+ 
++/* Split a DImode store of a CONST_INT SRC to MEM DST as two
++   SImode stores.  Handle the case when the constant has identical
++   bottom and top halves.  This is beneficial when the two stores can be
++   merged into an STP and we avoid synthesising potentially expensive
++   immediates twice.  Return true if such a split is possible.  */
++
++bool
++aarch64_split_dimode_const_store (rtx dst, rtx src)
++{
++  rtx lo = gen_lowpart (SImode, src);
++  rtx hi = gen_highpart_mode (SImode, DImode, src);
++
++  bool size_p = optimize_function_for_size_p (cfun);
++
++  if (!rtx_equal_p (lo, hi))
++    return false;
++
++  unsigned int orig_cost
++    = aarch64_internal_mov_immediate (NULL_RTX, src, false, DImode);
++  unsigned int lo_cost
++    = aarch64_internal_mov_immediate (NULL_RTX, lo, false, SImode);
++
++  /* We want to transform:
++     MOV	x1, 49370
++     MOVK	x1, 0x140, lsl 16
++     MOVK	x1, 0xc0da, lsl 32
++     MOVK	x1, 0x140, lsl 48
++     STR	x1, [x0]
++   into:
++     MOV	w1, 49370
++     MOVK	w1, 0x140, lsl 16
++     STP	w1, w1, [x0]
++   So we want to perform this only when we save two instructions
++   or more.  When optimizing for size, however, accept any code size
++   savings we can.  */
++  if (size_p && orig_cost <= lo_cost)
++    return false;
++
++  if (!size_p
++      && (orig_cost <= lo_cost + 1))
++    return false;
++
++  rtx mem_lo = adjust_address (dst, SImode, 0);
++  if (!aarch64_mem_pair_operand (mem_lo, SImode))
++    return false;
++
++  rtx tmp_reg = gen_reg_rtx (SImode);
++  aarch64_expand_mov_immediate (tmp_reg, lo);
++  rtx mem_hi = aarch64_move_pointer (mem_lo, GET_MODE_SIZE (SImode));
++  /* Don't emit an explicit store pair as this may not be always profitable.
++     Let the sched-fusion logic decide whether to merge them.  */
++  emit_move_insn (mem_lo, tmp_reg);
++  emit_move_insn (mem_hi, tmp_reg);
++
++  return true;
++}
++
+ /* Implement the TARGET_ASAN_SHADOW_OFFSET hook.  */
+ 
+ static unsigned HOST_WIDE_INT
+@@ -13302,6 +13634,14 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
+   return false;
+ }
+ 
++/* Return true iff the instruction fusion described by OP is enabled.  */
++
++bool
++aarch64_fusion_enabled_p (enum aarch64_fusion_pairs op)
++{
++  return (aarch64_tune_params.fusible_ops & op) != 0;
++}
++
+ /* If MEM is in the form of [base+offset], extract the two parts
+    of address and set to BASE and OFFSET, otherwise return false
+    after clearing BASE and OFFSET.  */
+@@ -13446,6 +13786,26 @@ aarch64_sched_fusion_priority (rtx_insn *insn, int max_pri,
+   return;
+ }
+ 
++/* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
++   Adjust priority of sha1h instructions so they are scheduled before
++   other SHA1 instructions.  */
++
++static int
++aarch64_sched_adjust_priority (rtx_insn *insn, int priority)
++{
++  rtx x = PATTERN (insn);
++
++  if (GET_CODE (x) == SET)
++    {
++      x = SET_SRC (x);
++
++      if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_SHA1H)
++	return priority + 10;
++    }
++
++  return priority;
++}
++
+ /* Given OPERANDS of consecutive load/store, check if we can merge
+    them into ldp/stp.  LOAD is true if they are load instructions.
+    MODE is the mode of memory operands.  */
+@@ -13480,6 +13840,15 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,
+   if (MEM_VOLATILE_P (mem_1) || MEM_VOLATILE_P (mem_2))
+     return false;
+ 
++  /* If we have SImode and slow unaligned ldp,
++     check the alignment to be at least 8 byte. */
++  if (mode == SImode
++      && (aarch64_tune_params.extra_tuning_flags
++          & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW)
++      && !optimize_size
++      && MEM_ALIGN (mem_1) < 8 * BITS_PER_UNIT)
++    return false;
++
+   /* Check if the addresses are in the form of [base+offset].  */
+   extract_base_offset_in_addr (mem_1, &base_1, &offset_1);
+   if (base_1 == NULL_RTX || offset_1 == NULL_RTX)
+@@ -13639,6 +14008,15 @@ aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load,
+ 	return false;
+     }
+ 
++  /* If we have SImode and slow unaligned ldp,
++     check the alignment to be at least 8 byte. */
++  if (mode == SImode
++      && (aarch64_tune_params.extra_tuning_flags
++          & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW)
++      && !optimize_size
++      && MEM_ALIGN (mem_1) < 8 * BITS_PER_UNIT)
++    return false;
++
+   if (REG_P (reg_1) && FP_REGNUM_P (REGNO (reg_1)))
+     rclass_1 = FP_REGS;
+   else
+@@ -13874,13 +14252,13 @@ aarch64_promoted_type (const_tree t)
+ /* Implement the TARGET_OPTAB_SUPPORTED_P hook.  */
+ 
+ static bool
+-aarch64_optab_supported_p (int op, machine_mode, machine_mode,
++aarch64_optab_supported_p (int op, machine_mode mode1, machine_mode,
+ 			   optimization_type opt_type)
+ {
+   switch (op)
+     {
+     case rsqrt_optab:
+-      return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ();
++      return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p (mode1);
+ 
+     default:
+       return true;
+@@ -14014,6 +14392,10 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
+ #undef TARGET_LEGITIMATE_CONSTANT_P
+ #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
+ 
++#undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
++#define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
++  aarch64_legitimize_address_displacement
++
+ #undef TARGET_LIBGCC_CMP_RETURN_MODE
+ #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
+ 
+@@ -14116,6 +14498,10 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
+ #undef TARGET_VECTOR_MODE_SUPPORTED_P
+ #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
+ 
++#undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
++#define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
++  aarch64_builtin_support_vector_misalignment
++
+ #undef TARGET_ARRAY_MODE_SUPPORTED_P
+ #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
+ 
+@@ -14193,6 +14579,9 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
+ #undef TARGET_CAN_USE_DOLOOP_P
+ #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
+ 
++#undef TARGET_SCHED_ADJUST_PRIORITY
++#define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
++
+ #undef TARGET_SCHED_MACRO_FUSION_P
+ #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
+ 
+@@ -14217,6 +14606,9 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
+ #undef TARGET_OPTAB_SUPPORTED_P
+ #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
+ 
++#undef TARGET_OMIT_STRUCT_RETURN_REG
++#define TARGET_OMIT_STRUCT_RETURN_REG true
++
+ struct gcc_target targetm = TARGET_INITIALIZER;
+ 
+ #include "gt-aarch64.h"
+--- a/src/gcc/config/aarch64/aarch64.h
++++ b/src/gcc/config/aarch64/aarch64.h
+@@ -132,9 +132,14 @@ extern unsigned aarch64_architecture_version;
+ #define AARCH64_FL_FP         (1 << 1)	/* Has FP.  */
+ #define AARCH64_FL_CRYPTO     (1 << 2)	/* Has crypto.  */
+ #define AARCH64_FL_CRC        (1 << 3)	/* Has CRC.  */
+-/* ARMv8.1 architecture extensions.  */
++/* ARMv8.1-A architecture extensions.  */
+ #define AARCH64_FL_LSE	      (1 << 4)  /* Has Large System Extensions.  */
+-#define AARCH64_FL_V8_1	      (1 << 5)  /* Has ARMv8.1 extensions.  */
++#define AARCH64_FL_V8_1	      (1 << 5)  /* Has ARMv8.1-A extensions.  */
++/* ARMv8.2-A architecture extensions.  */
++#define AARCH64_FL_V8_2	      (1 << 8)  /* Has ARMv8.2-A features.  */
++#define AARCH64_FL_F16	      (1 << 9)  /* Has ARMv8.2-A FP16 extensions.  */
++/* ARMv8.3-A architecture extensions.  */
++#define AARCH64_FL_V8_3	      (1 << 10)  /* Has ARMv8.3-A features.  */
+ 
+ /* Has FP and SIMD.  */
+ #define AARCH64_FL_FPSIMD     (AARCH64_FL_FP | AARCH64_FL_SIMD)
+@@ -146,6 +151,10 @@ extern unsigned aarch64_architecture_version;
+ #define AARCH64_FL_FOR_ARCH8       (AARCH64_FL_FPSIMD)
+ #define AARCH64_FL_FOR_ARCH8_1			       \
+   (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC | AARCH64_FL_V8_1)
++#define AARCH64_FL_FOR_ARCH8_2			\
++  (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2)
++#define AARCH64_FL_FOR_ARCH8_3			\
++  (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3)
+ 
+ /* Macros to test ISA flags.  */
+ 
+@@ -155,6 +164,9 @@ extern unsigned aarch64_architecture_version;
+ #define AARCH64_ISA_SIMD           (aarch64_isa_flags & AARCH64_FL_SIMD)
+ #define AARCH64_ISA_LSE		   (aarch64_isa_flags & AARCH64_FL_LSE)
+ #define AARCH64_ISA_RDMA	   (aarch64_isa_flags & AARCH64_FL_V8_1)
++#define AARCH64_ISA_V8_2	   (aarch64_isa_flags & AARCH64_FL_V8_2)
++#define AARCH64_ISA_F16		   (aarch64_isa_flags & AARCH64_FL_F16)
++#define AARCH64_ISA_V8_3	   (aarch64_isa_flags & AARCH64_FL_V8_3)
+ 
+ /* Crypto is an optional extension to AdvSIMD.  */
+ #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
+@@ -165,6 +177,13 @@ extern unsigned aarch64_architecture_version;
+ /* Atomic instructions that can be enabled through the +lse extension.  */
+ #define TARGET_LSE (AARCH64_ISA_LSE)
+ 
++/* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension.  */
++#define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16)
++#define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16)
++
++/* ARMv8.3-A features.  */
++#define TARGET_ARMV8_3	(AARCH64_ISA_V8_3)
++
+ /* Make sure this is always defined so we don't have to check for ifdefs
+    but rather use normal ifs.  */
+ #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
+@@ -193,7 +212,7 @@ extern unsigned aarch64_architecture_version;
+   ((aarch64_fix_a53_err843419 == 2)	\
+   ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419)
+ 
+-/* ARMv8.1 Adv.SIMD support.  */
++/* ARMv8.1-A Adv.SIMD support.  */
+ #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
+ 
+ /* Standard register usage.  */
+@@ -539,11 +558,14 @@ struct GTY (()) aarch64_frame
+      STACK_BOUNDARY.  */
+   HOST_WIDE_INT saved_varargs_size;
+ 
++  /* The size of the saved callee-save int/FP registers.  */
++
+   HOST_WIDE_INT saved_regs_size;
+-  /* Padding if needed after the all the callee save registers have
+-     been saved.  */
+-  HOST_WIDE_INT padding0;
+-  HOST_WIDE_INT hardfp_offset;	/* HARD_FRAME_POINTER_REGNUM */
++
++  /* Offset from the base of the frame (incomming SP) to the
++     top of the locals area.  This value is always a multiple of
++     STACK_BOUNDARY.  */
++  HOST_WIDE_INT locals_offset;
+ 
+   /* Offset from the base of the frame (incomming SP) to the
+      hard_frame_pointer.  This value is always a multiple of
+@@ -553,12 +575,25 @@ struct GTY (()) aarch64_frame
+   /* The size of the frame.  This value is the offset from base of the
+    * frame (incomming SP) to the stack_pointer.  This value is always
+    * a multiple of STACK_BOUNDARY.  */
++  HOST_WIDE_INT frame_size;
++
++  /* The size of the initial stack adjustment before saving callee-saves.  */
++  HOST_WIDE_INT initial_adjust;
++
++  /* The writeback value when pushing callee-save registers.
++     It is zero when no push is used.  */
++  HOST_WIDE_INT callee_adjust;
++
++  /* The offset from SP to the callee-save registers after initial_adjust.
++     It may be non-zero if no push is used (ie. callee_adjust == 0).  */
++  HOST_WIDE_INT callee_offset;
++
++  /* The size of the stack adjustment after saving callee-saves.  */
++  HOST_WIDE_INT final_adjust;
+ 
+   unsigned wb_candidate1;
+   unsigned wb_candidate2;
+ 
+-  HOST_WIDE_INT frame_size;
+-
+   bool laid_out;
+ };
+ 
+@@ -652,21 +687,6 @@ typedef struct
+ 
+ #define CONSTANT_ADDRESS_P(X)		aarch64_constant_address_p(X)
+ 
+-/* Try a machine-dependent way of reloading an illegitimate address
+-   operand.  If we find one, push the reload and jump to WIN.  This
+-   macro is used in only one place: `find_reloads_address' in reload.c.  */
+-
+-#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN)	     \
+-do {									     \
+-  rtx new_x = aarch64_legitimize_reload_address (&(X), MODE, OPNUM, TYPE,    \
+-						 IND_L);		     \
+-  if (new_x)								     \
+-    {									     \
+-      X = new_x;							     \
+-      goto WIN;								     \
+-    }									     \
+-} while (0)
+-
+ #define REGNO_OK_FOR_BASE_P(REGNO)	\
+   aarch64_regno_ok_for_base_p (REGNO, true)
+ 
+@@ -722,7 +742,12 @@ do {									     \
+ #define USE_STORE_PRE_INCREMENT(MODE)   0
+ #define USE_STORE_PRE_DECREMENT(MODE)   0
+ 
+-/* ?? #define WORD_REGISTER_OPERATIONS  */
++/* WORD_REGISTER_OPERATIONS does not hold for AArch64.
++   The assigned word_mode is DImode but operations narrower than SImode
++   behave as 32-bit operations if using the W-form of the registers rather
++   than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS
++   expects.  */
++#define WORD_REGISTER_OPERATIONS 0
+ 
+ /* Define if loading from memory in MODE, an integral mode narrower than
+    BITS_PER_WORD will either zero-extend or sign-extend.  The value of this
+@@ -842,10 +867,7 @@ do {									     \
+   extern void  __aarch64_sync_cache_range (void *, void *);	\
+   __aarch64_sync_cache_range (beg, end)
+ 
+-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)	\
+-  aarch64_cannot_change_mode_class (FROM, TO, CLASS)
+-
+-#define SHIFT_COUNT_TRUNCATED !TARGET_SIMD
++#define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD)
+ 
+ /* Choose appropriate mode for caller saves, so we do the minimum
+    required size of load/store.  */
+--- a/src/gcc/config/aarch64/aarch64.md
++++ b/src/gcc/config/aarch64/aarch64.md
+@@ -75,6 +75,8 @@
+     UNSPEC_CRC32H
+     UNSPEC_CRC32W
+     UNSPEC_CRC32X
++    UNSPEC_FCVTZS
++    UNSPEC_FCVTZU
+     UNSPEC_URECPE
+     UNSPEC_FRECPE
+     UNSPEC_FRECPS
+@@ -105,6 +107,7 @@
+     UNSPEC_NOP
+     UNSPEC_PRLG_STK
+     UNSPEC_RBIT
++    UNSPEC_SCVTF
+     UNSPEC_SISD_NEG
+     UNSPEC_SISD_SSHL
+     UNSPEC_SISD_USHL
+@@ -122,6 +125,7 @@
+     UNSPEC_TLSLE24
+     UNSPEC_TLSLE32
+     UNSPEC_TLSLE48
++    UNSPEC_UCVTF
+     UNSPEC_USHL_2S
+     UNSPEC_VSTRUCTDUMMY
+     UNSPEC_SP_SET
+@@ -837,13 +841,6 @@
+ 	   || aarch64_is_noplt_call_p (callee)))
+       XEXP (operands[0], 0) = force_reg (Pmode, callee);
+ 
+-    /* FIXME: This is a band-aid.  Need to analyze why expand_expr_addr_expr
+-       is generating an SImode symbol reference.  See PR 64971.  */
+-    if (TARGET_ILP32
+-	&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
+-	&& GET_MODE (XEXP (operands[0], 0)) == SImode)
+-      XEXP (operands[0], 0) = convert_memory_address (Pmode,
+-						      XEXP (operands[0], 0));
+     if (operands[2] == NULL_RTX)
+       operands[2] = const0_rtx;
+ 
+@@ -875,14 +872,6 @@
+ 	   || aarch64_is_noplt_call_p (callee)))
+       XEXP (operands[1], 0) = force_reg (Pmode, callee);
+ 
+-    /* FIXME: This is a band-aid.  Need to analyze why expand_expr_addr_expr
+-       is generating an SImode symbol reference.  See PR 64971.  */
+-    if (TARGET_ILP32
+-	&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
+-	&& GET_MODE (XEXP (operands[1], 0)) == SImode)
+-      XEXP (operands[1], 0) = convert_memory_address (Pmode,
+-						      XEXP (operands[1], 0));
+-
+     if (operands[3] == NULL_RTX)
+       operands[3] = const0_rtx;
+ 
+@@ -1003,6 +992,11 @@
+ 	(match_operand:GPI 1 "general_operand" ""))]
+   ""
+   "
++    if (MEM_P (operands[0]) && CONST_INT_P (operands[1])
++	&& <MODE>mode == DImode
++	&& aarch64_split_dimode_const_store (operands[0], operands[1]))
++      DONE;
++
+     if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
+       operands[1] = force_reg (<MODE>mode, operands[1]);
+ 
+@@ -1160,11 +1154,12 @@
+ )
+ 
+ (define_insn "*movhf_aarch64"
+-  [(set (match_operand:HF 0 "nonimmediate_operand" "=w, ?r,w,w,m,r,m ,r")
+-	(match_operand:HF 1 "general_operand"      "?rY, w,w,m,w,m,rY,r"))]
++  [(set (match_operand:HF 0 "nonimmediate_operand" "=w,w  ,?r,w,w,m,r,m ,r")
++	(match_operand:HF 1 "general_operand"      "Y ,?rY, w,w,m,w,m,rY,r"))]
+   "TARGET_FLOAT && (register_operand (operands[0], HFmode)
+     || aarch64_reg_or_fp_zero (operands[1], HFmode))"
+   "@
++   movi\\t%0.4h, #0
+    mov\\t%0.h[0], %w1
+    umov\\t%w0, %1.h[0]
+    mov\\t%0.h[0], %1.h[0]
+@@ -1173,18 +1168,18 @@
+    ldrh\\t%w0, %1
+    strh\\t%w1, %0
+    mov\\t%w0, %w1"
+-  [(set_attr "type" "neon_from_gp,neon_to_gp,neon_move,\
++  [(set_attr "type" "neon_move,neon_from_gp,neon_to_gp,neon_move,\
+                      f_loads,f_stores,load1,store1,mov_reg")
+-   (set_attr "simd" "yes,yes,yes,*,*,*,*,*")
+-   (set_attr "fp"   "*,*,*,yes,yes,*,*,*")]
++   (set_attr "simd" "yes,yes,yes,yes,*,*,*,*,*")]
+ )
+ 
+ (define_insn "*movsf_aarch64"
+-  [(set (match_operand:SF 0 "nonimmediate_operand" "=w, ?r,w,w  ,w,m,r,m ,r")
+-	(match_operand:SF 1 "general_operand"      "?rY, w,w,Ufc,m,w,m,rY,r"))]
++  [(set (match_operand:SF 0 "nonimmediate_operand" "=w,w  ,?r,w,w  ,w,m,r,m ,r")
++	(match_operand:SF 1 "general_operand"      "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))]
+   "TARGET_FLOAT && (register_operand (operands[0], SFmode)
+     || aarch64_reg_or_fp_zero (operands[1], SFmode))"
+   "@
++   movi\\t%0.2s, #0
+    fmov\\t%s0, %w1
+    fmov\\t%w0, %s1
+    fmov\\t%s0, %s1
+@@ -1194,16 +1189,18 @@
+    ldr\\t%w0, %1
+    str\\t%w1, %0
+    mov\\t%w0, %w1"
+-  [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\
+-                     f_loads,f_stores,load1,store1,mov_reg")]
++  [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconsts,\
++                     f_loads,f_stores,load1,store1,mov_reg")
++   (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")]
+ )
+ 
+ (define_insn "*movdf_aarch64"
+-  [(set (match_operand:DF 0 "nonimmediate_operand" "=w, ?r,w,w  ,w,m,r,m ,r")
+-	(match_operand:DF 1 "general_operand"      "?rY, w,w,Ufc,m,w,m,rY,r"))]
++  [(set (match_operand:DF 0 "nonimmediate_operand" "=w,w  ,?r,w,w  ,w,m,r,m ,r")
++	(match_operand:DF 1 "general_operand"      "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))]
+   "TARGET_FLOAT && (register_operand (operands[0], DFmode)
+     || aarch64_reg_or_fp_zero (operands[1], DFmode))"
+   "@
++   movi\\t%d0, #0
+    fmov\\t%d0, %x1
+    fmov\\t%x0, %d1
+    fmov\\t%d0, %d1
+@@ -1213,8 +1210,9 @@
+    ldr\\t%x0, %1
+    str\\t%x1, %0
+    mov\\t%x0, %x1"
+-  [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\
+-                     f_loadd,f_stored,load1,store1,mov_reg")]
++  [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,\
++                     f_loadd,f_stored,load1,store1,mov_reg")
++   (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")]
+ )
+ 
+ (define_insn "*movtf_aarch64"
+@@ -1239,7 +1237,6 @@
+   [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\
+                      f_loadd,f_stored,load2,store2,store2")
+    (set_attr "length" "4,8,8,8,4,4,4,4,4,4,4")
+-   (set_attr "fp" "*,*,yes,yes,*,yes,yes,yes,*,*,*")
+    (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")]
+ )
+ 
+@@ -1552,10 +1549,10 @@
+         (zero_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m,m")))]
+   ""
+   "@
+-   uxt<SHORT:size>\t%<GPI:w>0, %w1
++   and\t%<GPI:w>0, %<GPI:w>1, <SHORT:short_mask>
+    ldr<SHORT:size>\t%w0, %1
+    ldr\t%<SHORT:size>0, %1"
+-  [(set_attr "type" "extend,load1,load1")]
++  [(set_attr "type" "logic_imm,load1,load1")]
+ )
+ 
+ (define_expand "<optab>qihi2"
+@@ -1564,16 +1561,26 @@
+   ""
+ )
+ 
+-(define_insn "*<optab>qihi2_aarch64"
++(define_insn "*extendqihi2_aarch64"
+   [(set (match_operand:HI 0 "register_operand" "=r,r")
+-        (ANY_EXTEND:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
++	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
+   ""
+   "@
+-   <su>xtb\t%w0, %w1
+-   <ldrxt>b\t%w0, %1"
++   sxtb\t%w0, %w1
++   ldrsb\t%w0, %1"
+   [(set_attr "type" "extend,load1")]
+ )
+ 
++(define_insn "*zero_extendqihi2_aarch64"
++  [(set (match_operand:HI 0 "register_operand" "=r,r")
++	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
++  ""
++  "@
++   and\t%w0, %w1, 255
++   ldrb\t%w0, %1"
++  [(set_attr "type" "logic_imm,load1")]
++)
++
+ ;; -------------------------------------------------------------------
+ ;; Simple arithmetic
+ ;; -------------------------------------------------------------------
+@@ -1585,25 +1592,16 @@
+ 	      (match_operand:GPI 2 "aarch64_pluslong_operand" "")))]
+   ""
+ {
+-  if (aarch64_pluslong_strict_immedate (operands[2], <MODE>mode))
+-    {
+-      /* Give CSE the opportunity to share this constant across additions.  */
+-      if (!cse_not_expected && can_create_pseudo_p ())
+-        operands[2] = force_reg (<MODE>mode, operands[2]);
+-
+-      /* Split will refuse to operate on a modification to the stack pointer.
+-	 Aid the prologue and epilogue expanders by splitting this now.  */
+-      else if (reload_completed && operands[0] == stack_pointer_rtx)
+-	{
+-	  HOST_WIDE_INT i = INTVAL (operands[2]);
+-	  HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff));
+-	  emit_insn (gen_rtx_SET (operands[0],
+-				  gen_rtx_PLUS (<MODE>mode, operands[1],
+-						GEN_INT (i - s))));
+-	  operands[1] = operands[0];
+-	  operands[2] = GEN_INT (s);
+-	}
+-    }
++  /* If operands[1] is a subreg extract the inner RTX.  */
++  rtx op1 = REG_P (operands[1]) ? operands[1] : SUBREG_REG (operands[1]);
++
++  /* If the constant is too large for a single instruction and isn't frame
++     based, split off the immediate so it is available for CSE.  */
++  if (!aarch64_plus_immediate (operands[2], <MODE>mode)
++      && can_create_pseudo_p ()
++      && (!REG_P (op1)
++	 || !REGNO_PTR_FRAME_P (REGNO (op1))))
++    operands[2] = force_reg (<MODE>mode, operands[2]);
+ })
+ 
+ (define_insn "*add<mode>3_aarch64"
+@@ -1765,7 +1763,7 @@
+   "aarch64_zero_extend_const_eq (<DWI>mode, operands[2],
+ 				 <MODE>mode, operands[1])"
+   "@
+-  cmn\\t%<w>0, %<w>1
++  cmn\\t%<w>0, %1
+   cmp\\t%<w>0, #%n1"
+   [(set_attr "type" "alus_imm")]
+ )
+@@ -1797,11 +1795,11 @@
+   "aarch64_zero_extend_const_eq (<DWI>mode, operands[3],
+                                  <MODE>mode, operands[2])"
+   "@
+-  adds\\t%<w>0, %<w>1, %<w>2
++  adds\\t%<w>0, %<w>1, %2
+   subs\\t%<w>0, %<w>1, #%n2"
+   [(set_attr "type" "alus_imm")]
+ )
+- 
++
+ (define_insn "add<mode>3_compareC"
+   [(set (reg:CC_C CC_REGNUM)
+ 	(ne:CC_C
+@@ -3404,7 +3402,9 @@
+          (LOGICAL:SI (match_operand:SI 1 "register_operand" "%r,r")
+ 		     (match_operand:SI 2 "aarch64_logical_operand" "r,K"))))]
+   ""
+-  "<logical>\\t%w0, %w1, %w2"
++  "@
++   <logical>\\t%w0, %w1, %w2
++   <logical>\\t%w0, %w1, %2"
+   [(set_attr "type" "logic_reg,logic_imm")]
+ )
+ 
+@@ -3417,7 +3417,9 @@
+    (set (match_operand:GPI 0 "register_operand" "=r,r")
+ 	(and:GPI (match_dup 1) (match_dup 2)))]
+   ""
+-  "ands\\t%<w>0, %<w>1, %<w>2"
++  "@
++   ands\\t%<w>0, %<w>1, %<w>2
++   ands\\t%<w>0, %<w>1, %2"
+   [(set_attr "type" "logics_reg,logics_imm")]
+ )
+ 
+@@ -3431,7 +3433,9 @@
+    (set (match_operand:DI 0 "register_operand" "=r,r")
+ 	(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
+   ""
+-  "ands\\t%w0, %w1, %w2"
++  "@
++   ands\\t%w0, %w1, %w2
++   ands\\t%w0, %w1, %2"
+   [(set_attr "type" "logics_reg,logics_imm")]
+ )
+ 
+@@ -3741,6 +3745,39 @@
+   }
+ )
+ 
++;; Pop count be done via the "CNT" instruction in AdvSIMD.
++;;
++;; MOV	v.1d, x0
++;; CNT	v1.8b, v.8b
++;; ADDV b2, v1.8b
++;; MOV	w0, v2.b[0]
++
++(define_expand "popcount<mode>2"
++  [(match_operand:GPI 0 "register_operand")
++   (match_operand:GPI 1 "register_operand")]
++  "TARGET_SIMD"
++{
++  rtx v = gen_reg_rtx (V8QImode);
++  rtx v1 = gen_reg_rtx (V8QImode);
++  rtx r = gen_reg_rtx (QImode);
++  rtx in = operands[1];
++  rtx out = operands[0];
++  if(<MODE>mode == SImode)
++    {
++      rtx tmp;
++      tmp = gen_reg_rtx (DImode);
++      /* If we have SImode, zero extend to DImode, pop count does
++         not change if we have extra zeros. */
++      emit_insn (gen_zero_extendsidi2 (tmp, in));
++      in = tmp;
++    }
++  emit_move_insn (v, gen_lowpart (V8QImode, in));
++  emit_insn (gen_popcountv8qi2 (v1, v));
++  emit_insn (gen_reduc_plus_scal_v8qi (r, v1));
++  emit_insn (gen_zero_extendqi<mode>2 (out, r));
++  DONE;
++})
++
+ (define_insn "clrsb<mode>2"
+   [(set (match_operand:GPI 0 "register_operand" "=r")
+         (clrsb:GPI (match_operand:GPI 1 "register_operand" "r")))]
+@@ -3757,16 +3794,23 @@
+   [(set_attr "type" "rbit")]
+ )
+ 
+-(define_expand "ctz<mode>2"
+-  [(match_operand:GPI 0 "register_operand")
+-   (match_operand:GPI 1 "register_operand")]
++;; Split after reload into RBIT + CLZ.  Since RBIT is represented as an UNSPEC
++;; it is unlikely to fold with any other operation, so keep this as a CTZ
++;; expression and split after reload to enable scheduling them apart if
++;; needed.
++
++(define_insn_and_split "ctz<mode>2"
++ [(set (match_operand:GPI           0 "register_operand" "=r")
++       (ctz:GPI (match_operand:GPI  1 "register_operand" "r")))]
+   ""
+-  {
+-    emit_insn (gen_rbit<mode>2 (operands[0], operands[1]));
+-    emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+-    DONE;
+-  }
+-)
++  "#"
++  "reload_completed"
++  [(const_int 0)]
++  "
++  emit_insn (gen_rbit<mode>2 (operands[0], operands[1]));
++  emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
++  DONE;
++")
+ 
+ (define_insn "*and<mode>_compare0"
+   [(set (reg:CC_NZ CC_REGNUM)
+@@ -3778,6 +3822,18 @@
+   [(set_attr "type" "alus_imm")]
+ )
+ 
++(define_insn "*ands<mode>_compare0"
++  [(set (reg:CC_NZ CC_REGNUM)
++	(compare:CC_NZ
++	 (zero_extend:GPI (match_operand:SHORT 1 "register_operand" "r"))
++	 (const_int 0)))
++   (set (match_operand:GPI 0 "register_operand" "=r")
++	(zero_extend:GPI (match_dup 1)))]
++  ""
++  "ands\\t%<GPI:w>0, %<GPI:w>1, <short_mask>"
++  [(set_attr "type" "alus_imm")]
++)
++
+ (define_insn "*and<mode>3nr_compare0"
+   [(set (reg:CC_NZ CC_REGNUM)
+ 	(compare:CC_NZ
+@@ -3785,7 +3841,9 @@
+ 		  (match_operand:GPI 1 "aarch64_logical_operand" "r,<lconst>"))
+ 	 (const_int 0)))]
+   ""
+-  "tst\\t%<w>0, %<w>1"
++  "@
++   tst\\t%<w>0, %<w>1
++   tst\\t%<w>0, %1"
+   [(set_attr "type" "logics_reg,logics_imm")]
+ )
+ 
+@@ -3851,22 +3909,16 @@
+ (define_expand "ashl<mode>3"
+   [(set (match_operand:SHORT 0 "register_operand")
+ 	(ashift:SHORT (match_operand:SHORT 1 "register_operand")
+-		      (match_operand:QI 2 "nonmemory_operand")))]
++		      (match_operand:QI 2 "const_int_operand")))]
+   ""
+   {
+-    if (CONST_INT_P (operands[2]))
+-      {
+-        operands[2] = GEN_INT (INTVAL (operands[2])
+-                               & (GET_MODE_BITSIZE (<MODE>mode) - 1));
++    operands[2] = GEN_INT (INTVAL (operands[2]) & GET_MODE_MASK (<MODE>mode));
+ 
+-        if (operands[2] == const0_rtx)
+-          {
+-	    emit_insn (gen_mov<mode> (operands[0], operands[1]));
+-	    DONE;
+-          }
++    if (operands[2] == const0_rtx)
++      {
++	emit_insn (gen_mov<mode> (operands[0], operands[1]));
++	DONE;
+       }
+-    else
+-      FAIL;
+   }
+ )
+ 
+@@ -3915,33 +3967,35 @@
+ 
+ ;; Logical left shift using SISD or Integer instruction
+ (define_insn "*aarch64_ashl_sisd_or_int_<mode>3"
+-  [(set (match_operand:GPI 0 "register_operand" "=r,w,w")
+-        (ashift:GPI
+-          (match_operand:GPI 1 "register_operand" "r,w,w")
+-          (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>,Us<cmode>,w")))]
++  [(set (match_operand:GPI 0 "register_operand" "=r,r,w,w")
++	(ashift:GPI
++	  (match_operand:GPI 1 "register_operand" "r,r,w,w")
++	  (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,r,Us<cmode>,w")))]
+   ""
+   "@
++   lsl\t%<w>0, %<w>1, %2
+    lsl\t%<w>0, %<w>1, %<w>2
+    shl\t%<rtn>0<vas>, %<rtn>1<vas>, %2
+    ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>"
+-  [(set_attr "simd" "no,yes,yes")
+-   (set_attr "type" "shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")]
++  [(set_attr "simd" "no,no,yes,yes")
++   (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")]
+ )
+ 
+ ;; Logical right shift using SISD or Integer instruction
+ (define_insn "*aarch64_lshr_sisd_or_int_<mode>3"
+-  [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w")
+-        (lshiftrt:GPI
+-          (match_operand:GPI 1 "register_operand" "r,w,w,w")
+-          (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>,Us<cmode>,w,0")))]
++  [(set (match_operand:GPI 0 "register_operand" "=r,r,w,&w,&w")
++	(lshiftrt:GPI
++	 (match_operand:GPI 1 "register_operand" "r,r,w,w,w")
++	 (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,r,Us<cmode>,w,0")))]
+   ""
+   "@
++   lsr\t%<w>0, %<w>1, %2
+    lsr\t%<w>0, %<w>1, %<w>2
+    ushr\t%<rtn>0<vas>, %<rtn>1<vas>, %2
+    #
+    #"
+-  [(set_attr "simd" "no,yes,yes,yes")
+-   (set_attr "type" "shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
++  [(set_attr "simd" "no,no,yes,yes,yes")
++   (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
+ )
+ 
+ (define_split
+@@ -3976,18 +4030,19 @@
+ 
+ ;; Arithmetic right shift using SISD or Integer instruction
+ (define_insn "*aarch64_ashr_sisd_or_int_<mode>3"
+-  [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w")
++  [(set (match_operand:GPI 0 "register_operand" "=r,r,w,&w,&w")
+         (ashiftrt:GPI
+-          (match_operand:GPI 1 "register_operand" "r,w,w,w")
+-          (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "rUs<cmode>,Us<cmode>,w,0")))]
++          (match_operand:GPI 1 "register_operand" "r,r,w,w,w")
++          (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "Us<cmode>,r,Us<cmode>,w,0")))]
+   ""
+   "@
++   asr\t%<w>0, %<w>1, %2
+    asr\t%<w>0, %<w>1, %<w>2
+    sshr\t%<rtn>0<vas>, %<rtn>1<vas>, %2
+    #
+    #"
+-  [(set_attr "simd" "no,yes,yes,yes")
+-   (set_attr "type" "shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
++  [(set_attr "simd" "no,no,yes,yes,yes")
++   (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
+ )
+ 
+ (define_split
+@@ -4079,21 +4134,25 @@
+   [(set (match_operand:GPI 0 "register_operand" "=r,r")
+      (rotatert:GPI
+        (match_operand:GPI 1 "register_operand" "r,r")
+-       (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "r,Us<cmode>")))]
++       (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,r")))]
+   ""
+-  "ror\\t%<w>0, %<w>1, %<w>2"
+-  [(set_attr "type" "shift_reg, rotate_imm")]
++  "@
++   ror\\t%<w>0, %<w>1, %2
++   ror\\t%<w>0, %<w>1, %<w>2"
++  [(set_attr "type" "rotate_imm,shift_reg")]
+ )
+ 
+ ;; zero_extend version of above
+ (define_insn "*<optab>si3_insn_uxtw"
+-  [(set (match_operand:DI 0 "register_operand" "=r")
++  [(set (match_operand:DI 0 "register_operand" "=r,r")
+ 	(zero_extend:DI (SHIFT:SI
+-	 (match_operand:SI 1 "register_operand" "r")
+-	 (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss"))))]
++	 (match_operand:SI 1 "register_operand" "r,r")
++	 (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "Uss,r"))))]
+   ""
+-  "<shift>\\t%w0, %w1, %w2"
+-  [(set_attr "type" "shift_reg")]
++  "@
++   <shift>\\t%w0, %w1, %2
++   <shift>\\t%w0, %w1, %w2"
++  [(set_attr "type" "bfx,shift_reg")]
+ )
+ 
+ (define_insn "*<optab><mode>3_insn"
+@@ -4105,7 +4164,7 @@
+   operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2]));
+   return "<bfshift>\t%w0, %w1, %2, %3";
+ }
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
+ )
+ 
+ (define_insn "*extr<mode>5_insn"
+@@ -4117,7 +4176,7 @@
+   "UINTVAL (operands[3]) < GET_MODE_BITSIZE (<MODE>mode) &&
+    (UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))"
+   "extr\\t%<w>0, %<w>1, %<w>2, %4"
+-  [(set_attr "type" "shift_imm")]
++  [(set_attr "type" "rotate_imm")]
+ )
+ 
+ ;; There are no canonicalisation rules for ashift and lshiftrt inside an ior
+@@ -4132,7 +4191,7 @@
+    && (UINTVAL (operands[3]) + UINTVAL (operands[4])
+        == GET_MODE_BITSIZE (<MODE>mode))"
+   "extr\\t%<w>0, %<w>1, %<w>2, %4"
+-  [(set_attr "type" "shift_imm")]
++  [(set_attr "type" "rotate_imm")]
+ )
+ 
+ ;; zero_extend version of the above
+@@ -4146,7 +4205,7 @@
+   "UINTVAL (operands[3]) < 32 &&
+    (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)"
+   "extr\\t%w0, %w1, %w2, %4"
+-  [(set_attr "type" "shift_imm")]
++  [(set_attr "type" "rotate_imm")]
+ )
+ 
+ (define_insn "*extrsi5_insn_uxtw_alt"
+@@ -4159,7 +4218,7 @@
+   "UINTVAL (operands[3]) < 32 &&
+    (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)"
+   "extr\\t%w0, %w1, %w2, %4"
+-  [(set_attr "type" "shift_imm")]
++  [(set_attr "type" "rotate_imm")]
+ )
+ 
+ (define_insn "*ror<mode>3_insn"
+@@ -4198,7 +4257,7 @@
+   operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
+   return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
+ }
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
+ )
+ 
+ (define_insn "*zero_extend<GPI:mode>_lshr<SHORT:mode>"
+@@ -4211,7 +4270,7 @@
+   operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
+   return "ubfx\t%<GPI:w>0, %<GPI:w>1, %2, %3";
+ }
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
+ )
+ 
+ (define_insn "*extend<GPI:mode>_ashr<SHORT:mode>"
+@@ -4224,7 +4283,7 @@
+   operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
+   return "sbfx\\t%<GPI:w>0, %<GPI:w>1, %2, %3";
+ }
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
+ )
+ 
+ ;; -------------------------------------------------------------------
+@@ -4256,7 +4315,27 @@
+   "IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]),
+ 	     1, GET_MODE_BITSIZE (<MODE>mode) - 1)"
+   "<su>bfx\\t%<w>0, %<w>1, %3, %2"
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
++)
++
++;; When the bit position and width add up to 32 we can use a W-reg LSR
++;; instruction taking advantage of the implicit zero-extension of the X-reg.
++(define_split
++  [(set (match_operand:DI 0 "register_operand")
++	(zero_extract:DI (match_operand:DI 1 "register_operand")
++			 (match_operand 2
++			   "aarch64_simd_shift_imm_offset_di")
++			 (match_operand 3
++			   "aarch64_simd_shift_imm_di")))]
++  "IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]), 1,
++	     GET_MODE_BITSIZE (DImode) - 1)
++   && (INTVAL (operands[2]) + INTVAL (operands[3]))
++       == GET_MODE_BITSIZE (SImode)"
++  [(set (match_dup 0)
++	(zero_extend:DI (lshiftrt:SI (match_dup 4) (match_dup 3))))]
++  {
++    operands[4] = gen_lowpart (SImode, operands[1]);
++  }
+ )
+ 
+ ;; Bitfield Insert (insv)
+@@ -4338,7 +4417,7 @@
+ 	      : GEN_INT (<GPI:sizen> - UINTVAL (operands[2]));
+   return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
+ }
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
+ )
+ 
+ ;; XXX We should match (any_extend (ashift)) here, like (and (ashift)) below
+@@ -4348,11 +4427,27 @@
+ 	(and:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
+ 			     (match_operand 2 "const_int_operand" "n"))
+ 		 (match_operand 3 "const_int_operand" "n")))]
+-  "(INTVAL (operands[2]) < (<GPI:sizen>))
+-   && exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) >= 0
+-   && (INTVAL (operands[3]) & ((1 << INTVAL (operands[2])) - 1)) == 0"
++  "aarch64_mask_and_shift_for_ubfiz_p (<MODE>mode, operands[3], operands[2])"
+   "ubfiz\\t%<w>0, %<w>1, %2, %P3"
+-  [(set_attr "type" "bfm")]
++  [(set_attr "type" "bfx")]
++)
++
++;; When the bit position and width of the equivalent extraction add up to 32
++;; we can use a W-reg LSL instruction taking advantage of the implicit
++;; zero-extension of the X-reg.
++(define_split
++  [(set (match_operand:DI 0 "register_operand")
++	(and:DI (ashift:DI (match_operand:DI 1 "register_operand")
++			     (match_operand 2 "const_int_operand"))
++		 (match_operand 3 "const_int_operand")))]
++ "aarch64_mask_and_shift_for_ubfiz_p (DImode, operands[3], operands[2])
++  && (INTVAL (operands[2]) + popcount_hwi (INTVAL (operands[3])))
++      == GET_MODE_BITSIZE (SImode)"
++  [(set (match_dup 0)
++	(zero_extend:DI (ashift:SI (match_dup 4) (match_dup 2))))]
++  {
++    operands[4] = gen_lowpart (SImode, operands[1]);
++  }
+ )
+ 
+ (define_insn "bswap<mode>2"
+@@ -4420,22 +4515,23 @@
+ ;; Expands to btrunc, ceil, floor, nearbyint, rint, round, frintn.
+ 
+ (define_insn "<frint_pattern><mode>2"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-	(unspec:GPF [(match_operand:GPF 1 "register_operand" "w")]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(unspec:GPF_F16 [(match_operand:GPF_F16 1 "register_operand" "w")]
+ 	 FRINT))]
+   "TARGET_FLOAT"
+   "frint<frint_suffix>\\t%<s>0, %<s>1"
+-  [(set_attr "type" "f_rint<s>")]
++  [(set_attr "type" "f_rint<stype>")]
+ )
+ 
+ ;; frcvt floating-point round to integer and convert standard patterns.
+ ;; Expands to lbtrunc, lceil, lfloor, lround.
+-(define_insn "l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2"
++(define_insn "l<fcvt_pattern><su_optab><GPF_F16:mode><GPI:mode>2"
+   [(set (match_operand:GPI 0 "register_operand" "=r")
+-	(FIXUORS:GPI (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")]
+-		      FCVT)))]
++	(FIXUORS:GPI
++	  (unspec:GPF_F16 [(match_operand:GPF_F16 1 "register_operand" "w")]
++	   FCVT)))]
+   "TARGET_FLOAT"
+-  "fcvt<frint_suffix><su>\\t%<GPI:w>0, %<GPF:s>1"
++  "fcvt<frint_suffix><su>\\t%<GPI:w>0, %<GPF_F16:s>1"
+   [(set_attr "type" "f_cvtf2i")]
+ )
+ 
+@@ -4461,23 +4557,24 @@
+ ;; fma - no throw
+ 
+ (define_insn "fma<mode>4"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (fma:GPF (match_operand:GPF 1 "register_operand" "w")
+-		 (match_operand:GPF 2 "register_operand" "w")
+-		 (match_operand:GPF 3 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++        (fma:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")
++		     (match_operand:GPF_F16 2 "register_operand" "w")
++		     (match_operand:GPF_F16 3 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fmadd\\t%<s>0, %<s>1, %<s>2, %<s>3"
+-  [(set_attr "type" "fmac<s>")]
++  [(set_attr "type" "fmac<stype>")]
+ )
+ 
+ (define_insn "fnma<mode>4"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-	(fma:GPF (neg:GPF (match_operand:GPF 1 "register_operand" "w"))
+-		 (match_operand:GPF 2 "register_operand" "w")
+-		 (match_operand:GPF 3 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(fma:GPF_F16
++	  (neg:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w"))
++	  (match_operand:GPF_F16 2 "register_operand" "w")
++	  (match_operand:GPF_F16 3 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fmsub\\t%<s>0, %<s>1, %<s>2, %<s>3"
+-  [(set_attr "type" "fmac<s>")]
++  [(set_attr "type" "fmac<stype>")]
+ )
+ 
+ (define_insn "fms<mode>4"
+@@ -4563,19 +4660,11 @@
+   [(set_attr "type" "f_cvt")]
+ )
+ 
+-(define_insn "fix_trunc<GPF:mode><GPI:mode>2"
+-  [(set (match_operand:GPI 0 "register_operand" "=r")
+-        (fix:GPI (match_operand:GPF 1 "register_operand" "w")))]
+-  "TARGET_FLOAT"
+-  "fcvtzs\\t%<GPI:w>0, %<GPF:s>1"
+-  [(set_attr "type" "f_cvtf2i")]
+-)
+-
+-(define_insn "fixuns_trunc<GPF:mode><GPI:mode>2"
++(define_insn "<optab>_trunc<GPF_F16:mode><GPI:mode>2"
+   [(set (match_operand:GPI 0 "register_operand" "=r")
+-        (unsigned_fix:GPI (match_operand:GPF 1 "register_operand" "w")))]
++	(FIXUORS:GPI (match_operand:GPF_F16 1 "register_operand" "w")))]
+   "TARGET_FLOAT"
+-  "fcvtzu\\t%<GPI:w>0, %<GPF:s>1"
++  "fcvtz<su>\t%<GPI:w>0, %<GPF_F16:s>1"
+   [(set_attr "type" "f_cvtf2i")]
+ )
+ 
+@@ -4599,38 +4688,116 @@
+   [(set_attr "type" "f_cvti2f")]
+ )
+ 
++(define_insn "<optab><mode>hf2"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++	(FLOATUORS:HF (match_operand:GPI 1 "register_operand" "r")))]
++  "TARGET_FP_F16INST"
++  "<su_optab>cvtf\t%h0, %<w>1"
++  [(set_attr "type" "f_cvti2f")]
++)
++
++;; Convert between fixed-point and floating-point (scalar modes)
++
++(define_insn "<FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3"
++  [(set (match_operand:<GPF:FCVT_TARGET> 0 "register_operand" "=r, w")
++	(unspec:<GPF:FCVT_TARGET> [(match_operand:GPF 1 "register_operand" "w, w")
++				   (match_operand:SI 2 "immediate_operand" "i, i")]
++	 FCVT_F2FIXED))]
++  ""
++  "@
++   <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:w1>0, %<GPF:s>1, #%2
++   <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:s>0, %<GPF:s>1, #%2"
++  [(set_attr "type" "f_cvtf2i, neon_fp_to_int_<GPF:Vetype>")
++   (set_attr "fp" "yes, *")
++   (set_attr "simd" "*, yes")]
++)
++
++(define_insn "<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3"
++  [(set (match_operand:<GPI:FCVT_TARGET> 0 "register_operand" "=w, w")
++	(unspec:<GPI:FCVT_TARGET> [(match_operand:GPI 1 "register_operand" "r, w")
++				   (match_operand:SI 2 "immediate_operand" "i, i")]
++	 FCVT_FIXED2F))]
++  ""
++  "@
++   <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:w>1, #%2
++   <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:v>1, #%2"
++  [(set_attr "type" "f_cvti2f, neon_int_to_fp_<GPI:Vetype>")
++   (set_attr "fp" "yes, *")
++   (set_attr "simd" "*, yes")]
++)
++
++(define_insn "<FCVT_F2FIXED:fcvt_fixed_insn>hf<mode>3"
++  [(set (match_operand:GPI 0 "register_operand" "=r")
++	(unspec:GPI [(match_operand:HF 1 "register_operand" "w")
++		     (match_operand:SI 2 "immediate_operand" "i")]
++	 FCVT_F2FIXED))]
++  "TARGET_FP_F16INST"
++   "<FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPI:w>0, %h1, #%2"
++  [(set_attr "type" "f_cvtf2i")]
++)
++
++(define_insn "<FCVT_FIXED2F:fcvt_fixed_insn><mode>hf3"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++	(unspec:HF [(match_operand:GPI 1 "register_operand" "r")
++		    (match_operand:SI 2 "immediate_operand" "i")]
++	 FCVT_FIXED2F))]
++  "TARGET_FP_F16INST"
++  "<FCVT_FIXED2F:fcvt_fixed_insn>\t%h0, %<GPI:w>1, #%2"
++  [(set_attr "type" "f_cvti2f")]
++)
++
++(define_insn "<FCVT_F2FIXED:fcvt_fixed_insn>hf3"
++  [(set (match_operand:HI 0 "register_operand" "=w")
++	(unspec:HI [(match_operand:HF 1 "register_operand" "w")
++		    (match_operand:SI 2 "immediate_operand" "i")]
++	 FCVT_F2FIXED))]
++  "TARGET_SIMD"
++  "<FCVT_F2FIXED:fcvt_fixed_insn>\t%h0, %h1, #%2"
++  [(set_attr "type" "neon_fp_to_int_s")]
++)
++
++(define_insn "<FCVT_FIXED2F:fcvt_fixed_insn>hi3"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++	(unspec:HF [(match_operand:HI 1 "register_operand" "w")
++		    (match_operand:SI 2 "immediate_operand" "i")]
++	 FCVT_FIXED2F))]
++  "TARGET_SIMD"
++  "<FCVT_FIXED2F:fcvt_fixed_insn>\t%h0, %h1, #%2"
++  [(set_attr "type" "neon_int_to_fp_s")]
++)
++
+ ;; -------------------------------------------------------------------
+ ;; Floating-point arithmetic
+ ;; -------------------------------------------------------------------
+ 
+ (define_insn "add<mode>3"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (plus:GPF
+-         (match_operand:GPF 1 "register_operand" "w")
+-         (match_operand:GPF 2 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(plus:GPF_F16
++	 (match_operand:GPF_F16 1 "register_operand" "w")
++	 (match_operand:GPF_F16 2 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fadd\\t%<s>0, %<s>1, %<s>2"
+-  [(set_attr "type" "fadd<s>")]
++  [(set_attr "type" "fadd<stype>")]
+ )
+ 
+ (define_insn "sub<mode>3"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (minus:GPF
+-         (match_operand:GPF 1 "register_operand" "w")
+-         (match_operand:GPF 2 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(minus:GPF_F16
++	 (match_operand:GPF_F16 1 "register_operand" "w")
++	 (match_operand:GPF_F16 2 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fsub\\t%<s>0, %<s>1, %<s>2"
+-  [(set_attr "type" "fadd<s>")]
++  [(set_attr "type" "fadd<stype>")]
+ )
+ 
+ (define_insn "mul<mode>3"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (mult:GPF
+-         (match_operand:GPF 1 "register_operand" "w")
+-         (match_operand:GPF 2 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(mult:GPF_F16
++	 (match_operand:GPF_F16 1 "register_operand" "w")
++	 (match_operand:GPF_F16 2 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fmul\\t%<s>0, %<s>1, %<s>2"
+-  [(set_attr "type" "fmul<s>")]
++  [(set_attr "type" "fmul<stype>")]
+ )
+ 
+ (define_insn "*fnmul<mode>3"
+@@ -4653,38 +4820,58 @@
+   [(set_attr "type" "fmul<s>")]
+ )
+ 
+-(define_insn "div<mode>3"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (div:GPF
+-         (match_operand:GPF 1 "register_operand" "w")
+-         (match_operand:GPF 2 "register_operand" "w")))]
++(define_expand "div<mode>3"
++ [(set (match_operand:GPF_F16 0 "register_operand")
++       (div:GPF_F16 (match_operand:GPF_F16 1 "general_operand")
++		    (match_operand:GPF_F16 2 "register_operand")))]
++ "TARGET_SIMD"
++{
++  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
++    DONE;
++
++  operands[1] = force_reg (<MODE>mode, operands[1]);
++})
++
++(define_insn "*div<mode>3"
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(div:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")
++		     (match_operand:GPF_F16 2 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fdiv\\t%<s>0, %<s>1, %<s>2"
+-  [(set_attr "type" "fdiv<s>")]
++  [(set_attr "type" "fdiv<stype>")]
+ )
+ 
+ (define_insn "neg<mode>2"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (neg:GPF (match_operand:GPF 1 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(neg:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fneg\\t%<s>0, %<s>1"
+-  [(set_attr "type" "ffarith<s>")]
++  [(set_attr "type" "ffarith<stype>")]
+ )
+ 
+-(define_insn "sqrt<mode>2"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (sqrt:GPF (match_operand:GPF 1 "register_operand" "w")))]
++(define_expand "sqrt<mode>2"
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(sqrt:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")))]
++  "TARGET_FLOAT"
++{
++  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
++    DONE;
++})
++
++(define_insn "*sqrt<mode>2"
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(sqrt:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fsqrt\\t%<s>0, %<s>1"
+-  [(set_attr "type" "fsqrt<s>")]
++  [(set_attr "type" "fsqrt<stype>")]
+ )
+ 
+ (define_insn "abs<mode>2"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-        (abs:GPF (match_operand:GPF 1 "register_operand" "w")))]
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(abs:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")))]
+   "TARGET_FLOAT"
+   "fabs\\t%<s>0, %<s>1"
+-  [(set_attr "type" "ffarith<s>")]
++  [(set_attr "type" "ffarith<stype>")]
+ )
+ 
+ ;; Given that smax/smin do not specify the result when either input is NaN,
+@@ -4709,15 +4896,17 @@
+   [(set_attr "type" "f_minmax<s>")]
+ )
+ 
+-;; Scalar forms for the IEEE-754 fmax()/fmin() functions
+-(define_insn "<fmaxmin><mode>3"
+-  [(set (match_operand:GPF 0 "register_operand" "=w")
+-	(unspec:GPF [(match_operand:GPF 1 "register_operand" "w")
+-		     (match_operand:GPF 2 "register_operand" "w")]
+-		     FMAXMIN))]
++;; Scalar forms for fmax, fmin, fmaxnm, fminnm.
++;; fmaxnm and fminnm are used for the fmax<mode>3 standard pattern names,
++;; which implement the IEEE fmax ()/fmin () functions.
++(define_insn "<maxmin_uns><mode>3"
++  [(set (match_operand:GPF_F16 0 "register_operand" "=w")
++	(unspec:GPF_F16 [(match_operand:GPF_F16 1 "register_operand" "w")
++		     (match_operand:GPF_F16 2 "register_operand" "w")]
++		     FMAXMIN_UNS))]
+   "TARGET_FLOAT"
+-  "<fmaxmin_op>\\t%<s>0, %<s>1, %<s>2"
+-  [(set_attr "type" "f_minmax<s>")]
++  "<maxmin_uns_op>\\t%<s>0, %<s>1, %<s>2"
++  [(set_attr "type" "f_minmax<stype>")]
+ )
+ 
+ ;; For copysign (x, y), we want to generate:
+@@ -4775,7 +4964,7 @@
+  [(set (match_operand:GPF_TF 0 "register_operand" "=w")
+        (mem:GPF_TF (match_operand 1 "aarch64_constant_pool_symref" "S")))
+   (clobber (match_operand:P 2 "register_operand" "=&r"))]
+- "TARGET_FLOAT && aarch64_nopcrelative_literal_loads"
++ "TARGET_FLOAT"
+  {
+    aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
+    emit_move_insn (operands[0], gen_rtx_MEM (<GPF_TF:MODE>mode, operands[2]));
+@@ -4788,7 +4977,7 @@
+  [(set (match_operand:VALL 0 "register_operand" "=w")
+        (mem:VALL (match_operand 1 "aarch64_constant_pool_symref" "S")))
+   (clobber (match_operand:P 2 "register_operand" "=&r"))]
+- "TARGET_FLOAT && aarch64_nopcrelative_literal_loads"
++ "TARGET_FLOAT"
+  {
+    aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
+    emit_move_insn (operands[0], gen_rtx_MEM (<VALL:MODE>mode, operands[2]));
+@@ -4961,20 +5150,20 @@
+ ;; The TLS ABI specifically requires that the compiler does not schedule
+ ;; instructions in the TLS stubs, in order to enable linker relaxation.
+ ;; Therefore we treat the stubs as an atomic sequence.
+-(define_expand "tlsgd_small"
++(define_expand "tlsgd_small_<mode>"
+  [(parallel [(set (match_operand 0 "register_operand" "")
+                   (call (mem:DI (match_dup 2)) (const_int 1)))
+-	     (unspec:DI [(match_operand:DI 1 "aarch64_valid_symref" "")] UNSPEC_GOTSMALLTLS)
++	     (unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref" "")] UNSPEC_GOTSMALLTLS)
+ 	     (clobber (reg:DI LR_REGNUM))])]
+  ""
+ {
+   operands[2] = aarch64_tls_get_addr ();
+ })
+ 
+-(define_insn "*tlsgd_small"
++(define_insn "*tlsgd_small_<mode>"
+   [(set (match_operand 0 "register_operand" "")
+ 	(call (mem:DI (match_operand:DI 2 "" "")) (const_int 1)))
+-   (unspec:DI [(match_operand:DI 1 "aarch64_valid_symref" "S")] UNSPEC_GOTSMALLTLS)
++   (unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref" "S")] UNSPEC_GOTSMALLTLS)
+    (clobber (reg:DI LR_REGNUM))
+   ]
+   ""
+@@ -5182,7 +5371,7 @@
+ 	 UNSPEC_SP_TEST))
+    (clobber (match_scratch:PTR 3 "=&r"))]
+   ""
+-  "ldr\t%<w>3, %x1\;ldr\t%<w>0, %x2\;eor\t%<w>0, %<w>3, %<w>0"
++  "ldr\t%<w>3, %1\;ldr\t%<w>0, %2\;eor\t%<w>0, %<w>3, %<w>0"
+   [(set_attr "length" "12")
+    (set_attr "type" "multiple")])
+ 
+--- a/src/gcc/config/aarch64/aarch64.opt
++++ b/src/gcc/config/aarch64/aarch64.opt
+@@ -146,10 +146,28 @@ EnumValue
+ Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64)
+ 
+ mpc-relative-literal-loads
+-Target Report Save Var(nopcrelative_literal_loads) Init(2) Save
++Target Report Save Var(pcrelative_literal_loads) Init(2) Save
+ PC relative literal loads.
+ 
+ mlow-precision-recip-sqrt
+ Common Var(flag_mrecip_low_precision_sqrt) Optimization
+-When calculating the reciprocal square root approximation,
+-uses one less step than otherwise, thus reducing latency and precision.
++Enable the reciprocal square root approximation.  Enabling this reduces
++precision of reciprocal square root results to about 16 bits for
++single precision and to 32 bits for double precision.
++
++mlow-precision-sqrt
++Common Var(flag_mlow_precision_sqrt) Optimization
++Enable the square root approximation.  Enabling this reduces
++precision of square root results to about 16 bits for
++single precision and to 32 bits for double precision.
++If enabled, it implies -mlow-precision-recip-sqrt.
++
++mlow-precision-div
++Common Var(flag_mlow_precision_div) Optimization
++Enable the division approximation.  Enabling this reduces
++precision of division results to about 16 bits for
++single precision and to 32 bits for double precision.
++
++mverbose-cost-dump
++Common Undocumented Var(flag_aarch64_verbose_cost)
++Enables verbose cost model dumping in the debug dump files.
+--- /dev/null
++++ b/src/gcc/config/aarch64/arm_fp16.h
+@@ -0,0 +1,579 @@
++/* ARM FP16 scalar intrinsics include file.
++
++   Copyright (C) 2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   Under Section 7 of GPL version 3, you are granted additional
++   permissions described in the GCC Runtime Library Exception, version
++   3.1, as published by the Free Software Foundation.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++#ifndef _AARCH64_FP16_H_
++#define _AARCH64_FP16_H_
++
++#include <stdint.h>
++
++#pragma GCC push_options
++#pragma GCC target ("arch=armv8.2-a+fp16")
++
++typedef __fp16 float16_t;
++
++/* ARMv8.2-A FP16 one operand scalar intrinsics.  */
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vabsh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_abshf (__a);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vceqzh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_cmeqhf_uss (__a, 0.0f);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcgezh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_cmgehf_uss (__a, 0.0f);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcgtzh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_cmgthf_uss (__a, 0.0f);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vclezh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_cmlehf_uss (__a, 0.0f);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcltzh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_cmlthf_uss (__a, 0.0f);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_s16 (int16_t __a)
++{
++  return __builtin_aarch64_floathihf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_s32 (int32_t __a)
++{
++  return __builtin_aarch64_floatsihf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_s64 (int64_t __a)
++{
++  return __builtin_aarch64_floatdihf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_u16 (uint16_t __a)
++{
++  return __builtin_aarch64_floatunshihf_us (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_u32 (uint32_t __a)
++{
++  return __builtin_aarch64_floatunssihf_us (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_u64 (uint64_t __a)
++{
++  return __builtin_aarch64_floatunsdihf_us (__a);
++}
++
++__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++vcvth_s16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_fix_trunchfhi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvth_s32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_fix_trunchfsi (__a);
++}
++
++__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++vcvth_s64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_fix_trunchfdi (__a);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcvth_u16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_fixuns_trunchfhi_us (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvth_u32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_fixuns_trunchfsi_us (__a);
++}
++
++__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++vcvth_u64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_fixuns_trunchfdi_us (__a);
++}
++
++__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++vcvtah_s16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lroundhfhi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtah_s32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lroundhfsi (__a);
++}
++
++__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++vcvtah_s64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lroundhfdi (__a);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcvtah_u16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lrounduhfhi_us (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtah_u32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lrounduhfsi_us (__a);
++}
++
++__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++vcvtah_u64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lrounduhfdi_us (__a);
++}
++
++__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++vcvtmh_s16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfloorhfhi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtmh_s32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfloorhfsi (__a);
++}
++
++__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++vcvtmh_s64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfloorhfdi (__a);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcvtmh_u16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lflooruhfhi_us (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtmh_u32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lflooruhfsi_us (__a);
++}
++
++__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++vcvtmh_u64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lflooruhfdi_us (__a);
++}
++
++__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++vcvtnh_s16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfrintnhfhi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtnh_s32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfrintnhfsi (__a);
++}
++
++__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++vcvtnh_s64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfrintnhfdi (__a);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcvtnh_u16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfrintnuhfhi_us (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtnh_u32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfrintnuhfsi_us (__a);
++}
++
++__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++vcvtnh_u64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lfrintnuhfdi_us (__a);
++}
++
++__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++vcvtph_s16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lceilhfhi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtph_s32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lceilhfsi (__a);
++}
++
++__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++vcvtph_s64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lceilhfdi (__a);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcvtph_u16_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lceiluhfhi_us (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtph_u32_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lceiluhfsi_us (__a);
++}
++
++__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++vcvtph_u64_f16 (float16_t __a)
++{
++  return __builtin_aarch64_lceiluhfdi_us (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vnegh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_neghf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrecpeh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_frecpehf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrecpxh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_frecpxhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_btrunchf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndah_f16 (float16_t __a)
++{
++  return __builtin_aarch64_roundhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndih_f16 (float16_t __a)
++{
++  return __builtin_aarch64_nearbyinthf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndmh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_floorhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndnh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_frintnhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndph_f16 (float16_t __a)
++{
++  return __builtin_aarch64_ceilhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndxh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_rinthf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrsqrteh_f16 (float16_t __a)
++{
++  return __builtin_aarch64_rsqrtehf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vsqrth_f16 (float16_t __a)
++{
++  return __builtin_aarch64_sqrthf (__a);
++}
++
++/* ARMv8.2-A FP16 two operands scalar intrinsics.  */
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vaddh_f16 (float16_t __a, float16_t __b)
++{
++  return __a + __b;
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vabdh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_fabdhf (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcageh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_facgehf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcagth_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_facgthf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcaleh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_faclehf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcalth_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_faclthf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vceqh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_cmeqhf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcgeh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_cmgehf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcgth_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_cmgthf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcleh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_cmlehf_uss (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vclth_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_cmlthf_uss (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_s16 (int16_t __a, const int __b)
++{
++  return __builtin_aarch64_scvtfhi (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_s32 (int32_t __a, const int __b)
++{
++  return __builtin_aarch64_scvtfsihf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_s64 (int64_t __a, const int __b)
++{
++  return __builtin_aarch64_scvtfdihf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_u16 (uint16_t __a, const int __b)
++{
++  return __builtin_aarch64_ucvtfhi_sus (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_u32 (uint32_t __a, const int __b)
++{
++  return __builtin_aarch64_ucvtfsihf_sus (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_u64 (uint64_t __a, const int __b)
++{
++  return __builtin_aarch64_ucvtfdihf_sus (__a, __b);
++}
++
++__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++vcvth_n_s16_f16 (float16_t __a, const int __b)
++{
++  return __builtin_aarch64_fcvtzshf (__a, __b);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvth_n_s32_f16 (float16_t __a, const int __b)
++{
++  return __builtin_aarch64_fcvtzshfsi (__a, __b);
++}
++
++__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++vcvth_n_s64_f16 (float16_t __a, const int __b)
++{
++  return __builtin_aarch64_fcvtzshfdi (__a, __b);
++}
++
++__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++vcvth_n_u16_f16 (float16_t __a, const int __b)
++{
++  return __builtin_aarch64_fcvtzuhf_uss (__a, __b);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvth_n_u32_f16 (float16_t __a, const int __b)
++{
++  return __builtin_aarch64_fcvtzuhfsi_uss (__a, __b);
++}
++
++__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++vcvth_n_u64_f16 (float16_t __a, const int __b)
++{
++  return __builtin_aarch64_fcvtzuhfdi_uss (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vdivh_f16 (float16_t __a, float16_t __b)
++{
++  return __a / __b;
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vmaxh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_fmaxhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vmaxnmh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_fmaxhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vminh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_fminhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vminnmh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_fminhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vmulh_f16 (float16_t __a, float16_t __b)
++{
++  return __a * __b;
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vmulxh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_fmulxhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrecpsh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_frecpshf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrsqrtsh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_aarch64_rsqrtshf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vsubh_f16 (float16_t __a, float16_t __b)
++{
++  return __a - __b;
++}
++
++/* ARMv8.2-A FP16 three operands scalar intrinsics.  */
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vfmah_f16 (float16_t __a, float16_t __b, float16_t __c)
++{
++  return __builtin_aarch64_fmahf (__b, __c, __a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vfmsh_f16 (float16_t __a, float16_t __b, float16_t __c)
++{
++  return __builtin_aarch64_fnmahf (__b, __c, __a);
++}
++
++#pragma GCC pop_options
++
++#endif
+--- a/src/gcc/config/aarch64/arm_neon.h
++++ b/src/gcc/config/aarch64/arm_neon.h
+@@ -58,6 +58,7 @@ typedef __Float64x2_t float64x2_t;
+ typedef __Poly8x16_t poly8x16_t;
+ typedef __Poly16x8_t poly16x8_t;
+ typedef __Poly64x2_t poly64x2_t;
++typedef __Poly64x1_t poly64x1_t;
+ typedef __Uint8x16_t uint8x16_t;
+ typedef __Uint16x8_t uint16x8_t;
+ typedef __Uint32x4_t uint32x4_t;
+@@ -202,6 +203,36 @@ typedef struct poly16x8x2_t
+   poly16x8_t val[2];
+ } poly16x8x2_t;
+ 
++typedef struct poly64x1x2_t
++{
++  poly64x1_t val[2];
++} poly64x1x2_t;
++
++typedef struct poly64x1x3_t
++{
++  poly64x1_t val[3];
++} poly64x1x3_t;
++
++typedef struct poly64x1x4_t
++{
++  poly64x1_t val[4];
++} poly64x1x4_t;
++
++typedef struct poly64x2x2_t
++{
++  poly64x2_t val[2];
++} poly64x2x2_t;
++
++typedef struct poly64x2x3_t
++{
++  poly64x2_t val[3];
++} poly64x2x3_t;
++
++typedef struct poly64x2x4_t
++{
++  poly64x2_t val[4];
++} poly64x2x4_t;
++
+ typedef struct int8x8x3_t
+ {
+   int8x8_t val[3];
+@@ -466,6 +497,8 @@ typedef struct poly16x8x4_t
+ #define __aarch64_vdup_lane_any(__size, __q, __a, __b) \
+   vdup##__q##_n_##__size (__aarch64_vget_lane_any (__a, __b))
+ 
++#define __aarch64_vdup_lane_f16(__a, __b) \
++   __aarch64_vdup_lane_any (f16, , __a, __b)
+ #define __aarch64_vdup_lane_f32(__a, __b) \
+    __aarch64_vdup_lane_any (f32, , __a, __b)
+ #define __aarch64_vdup_lane_f64(__a, __b) \
+@@ -474,6 +507,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (p8, , __a, __b)
+ #define __aarch64_vdup_lane_p16(__a, __b) \
+    __aarch64_vdup_lane_any (p16, , __a, __b)
++#define __aarch64_vdup_lane_p64(__a, __b) \
++   __aarch64_vdup_lane_any (p64, , __a, __b)
+ #define __aarch64_vdup_lane_s8(__a, __b) \
+    __aarch64_vdup_lane_any (s8, , __a, __b)
+ #define __aarch64_vdup_lane_s16(__a, __b) \
+@@ -492,6 +527,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (u64, , __a, __b)
+ 
+ /* __aarch64_vdup_laneq internal macros.  */
++#define __aarch64_vdup_laneq_f16(__a, __b) \
++   __aarch64_vdup_lane_any (f16, , __a, __b)
+ #define __aarch64_vdup_laneq_f32(__a, __b) \
+    __aarch64_vdup_lane_any (f32, , __a, __b)
+ #define __aarch64_vdup_laneq_f64(__a, __b) \
+@@ -500,6 +537,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (p8, , __a, __b)
+ #define __aarch64_vdup_laneq_p16(__a, __b) \
+    __aarch64_vdup_lane_any (p16, , __a, __b)
++#define __aarch64_vdup_laneq_p64(__a, __b) \
++   __aarch64_vdup_lane_any (p64, , __a, __b)
+ #define __aarch64_vdup_laneq_s8(__a, __b) \
+    __aarch64_vdup_lane_any (s8, , __a, __b)
+ #define __aarch64_vdup_laneq_s16(__a, __b) \
+@@ -518,6 +557,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (u64, , __a, __b)
+ 
+ /* __aarch64_vdupq_lane internal macros.  */
++#define __aarch64_vdupq_lane_f16(__a, __b) \
++   __aarch64_vdup_lane_any (f16, q, __a, __b)
+ #define __aarch64_vdupq_lane_f32(__a, __b) \
+    __aarch64_vdup_lane_any (f32, q, __a, __b)
+ #define __aarch64_vdupq_lane_f64(__a, __b) \
+@@ -526,6 +567,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (p8, q, __a, __b)
+ #define __aarch64_vdupq_lane_p16(__a, __b) \
+    __aarch64_vdup_lane_any (p16, q, __a, __b)
++#define __aarch64_vdupq_lane_p64(__a, __b) \
++   __aarch64_vdup_lane_any (p64, q, __a, __b)
+ #define __aarch64_vdupq_lane_s8(__a, __b) \
+    __aarch64_vdup_lane_any (s8, q, __a, __b)
+ #define __aarch64_vdupq_lane_s16(__a, __b) \
+@@ -544,6 +587,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (u64, q, __a, __b)
+ 
+ /* __aarch64_vdupq_laneq internal macros.  */
++#define __aarch64_vdupq_laneq_f16(__a, __b) \
++   __aarch64_vdup_lane_any (f16, q, __a, __b)
+ #define __aarch64_vdupq_laneq_f32(__a, __b) \
+    __aarch64_vdup_lane_any (f32, q, __a, __b)
+ #define __aarch64_vdupq_laneq_f64(__a, __b) \
+@@ -552,6 +597,8 @@ typedef struct poly16x8x4_t
+    __aarch64_vdup_lane_any (p8, q, __a, __b)
+ #define __aarch64_vdupq_laneq_p16(__a, __b) \
+    __aarch64_vdup_lane_any (p16, q, __a, __b)
++#define __aarch64_vdupq_laneq_p64(__a, __b) \
++   __aarch64_vdup_lane_any (p64, q, __a, __b)
+ #define __aarch64_vdupq_laneq_s8(__a, __b) \
+    __aarch64_vdup_lane_any (s8, q, __a, __b)
+ #define __aarch64_vdupq_laneq_s16(__a, __b) \
+@@ -601,535 +648,619 @@ typedef struct poly16x8x4_t
+   })
+ 
+ /* vadd  */
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_f64 (float64x1_t __a, float64x1_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_saddlv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_saddlv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_saddlv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_uaddlv8qi ((int8x8_t) __a,
+ 						   (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_uaddlv4hi ((int16x4_t) __a,
+ 						   (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_uaddlv2si ((int32x2_t) __a,
+ 						   (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_high_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_saddl2v16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_high_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_saddl2v8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_high_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_saddl2v4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_high_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_uaddl2v16qi ((int8x16_t) __a,
+ 						     (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_high_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_uaddl2v8hi ((int16x8_t) __a,
+ 						    (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_high_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_uaddl2v4si ((int32x4_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_s8 (int16x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_saddwv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_s16 (int32x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_saddwv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_s32 (int64x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_saddwv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_u8 (uint16x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_uaddwv8qi ((int16x8_t) __a,
+ 						   (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_u16 (uint32x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_uaddwv4hi ((int32x4_t) __a,
+ 						   (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_u32 (uint64x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_uaddwv2si ((int64x2_t) __a,
+ 						   (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_high_s8 (int16x8_t __a, int8x16_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_saddw2v16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_high_s16 (int32x4_t __a, int16x8_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_saddw2v8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_high_s32 (int64x2_t __a, int32x4_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_saddw2v4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_high_u8 (uint16x8_t __a, uint8x16_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_uaddw2v16qi ((int16x8_t) __a,
+ 						     (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_high_u16 (uint32x4_t __a, uint16x8_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_uaddw2v8hi ((int32x4_t) __a,
+ 						    (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_high_u32 (uint64x2_t __a, uint32x4_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_uaddw2v4si ((int64x2_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_shaddv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_shaddv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_shaddv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_uhaddv8qi ((int8x8_t) __a,
+ 						  (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_uhaddv4hi ((int16x4_t) __a,
+ 						   (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_uhaddv2si ((int32x2_t) __a,
+ 						   (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t) __builtin_aarch64_shaddv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_shaddv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_shaddv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t) __builtin_aarch64_uhaddv16qi ((int8x16_t) __a,
+ 						    (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_uhaddv8hi ((int16x8_t) __a,
+ 						   (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_uhaddv4si ((int32x4_t) __a,
+ 						   (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_srhaddv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_srhaddv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_srhaddv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_urhaddv8qi ((int8x8_t) __a,
+ 						   (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_urhaddv4hi ((int16x4_t) __a,
+ 						    (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_urhaddv2si ((int32x2_t) __a,
+ 						    (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t) __builtin_aarch64_srhaddv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_srhaddv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_srhaddv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t) __builtin_aarch64_urhaddv16qi ((int8x16_t) __a,
+ 						     (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_urhaddv8hi ((int16x8_t) __a,
+ 						    (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_urhaddv4si ((int32x4_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_addhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_addhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_addhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_addhnv8hi ((int16x8_t) __a,
+ 						  (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_addhnv4si ((int32x4_t) __a,
+ 						   (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_addhnv2di ((int64x2_t) __a,
+ 						   (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_raddhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_raddhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_raddhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_raddhnv8hi ((int16x8_t) __a,
+ 						   (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_raddhnv4si ((int32x4_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_raddhnv2di ((int64x2_t) __a,
+ 						    (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_high_s16 (int8x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int8x16_t) __builtin_aarch64_addhn2v8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_high_s32 (int16x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int16x8_t) __builtin_aarch64_addhn2v4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_high_s64 (int32x2_t __a, int64x2_t __b, int64x2_t __c)
+ {
+   return (int32x4_t) __builtin_aarch64_addhn2v2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint8x16_t) __builtin_aarch64_addhn2v8hi ((int8x8_t) __a,
+@@ -1137,7 +1268,8 @@ vaddhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ 						    (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint16x8_t) __builtin_aarch64_addhn2v4si ((int16x4_t) __a,
+@@ -1145,7 +1277,8 @@ vaddhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ 						    (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ {
+   return (uint32x4_t) __builtin_aarch64_addhn2v2di ((int32x2_t) __a,
+@@ -1153,25 +1286,29 @@ vaddhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ 						    (int64x2_t) __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_high_s16 (int8x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int8x16_t) __builtin_aarch64_raddhn2v8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_high_s32 (int16x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int16x8_t) __builtin_aarch64_raddhn2v4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_high_s64 (int32x2_t __a, int64x2_t __b, int64x2_t __c)
+ {
+   return (int32x4_t) __builtin_aarch64_raddhn2v2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint8x16_t) __builtin_aarch64_raddhn2v8hi ((int8x8_t) __a,
+@@ -1179,7 +1316,8 @@ vraddhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ 						     (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint16x8_t) __builtin_aarch64_raddhn2v4si ((int16x4_t) __a,
+@@ -1187,7 +1325,8 @@ vraddhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ 						     (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ {
+   return (uint32x4_t) __builtin_aarch64_raddhn2v2di ((int32x2_t) __a,
+@@ -1195,1101 +1334,1280 @@ vraddhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ 						     (int64x2_t) __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vdiv_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return __a / __b;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vdiv_f64 (float64x1_t __a, float64x1_t __b)
+ {
+   return __a / __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vdivq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return __a / __b;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vdivq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+   return __a / __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_f64 (float64x1_t __a, float64x1_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (poly8x8_t) __builtin_aarch64_pmulv8qi ((int8x8_t) __a,
+ 						 (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   return (poly8x16_t) __builtin_aarch64_pmulv16qi ((int8x16_t) __a,
+ 						   (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_f64 (float64x1_t __a, float64x1_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_ssublv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_ssublv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_ssublv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_usublv8qi ((int8x8_t) __a,
+ 						   (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_usublv4hi ((int16x4_t) __a,
+ 						   (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_usublv2si ((int32x2_t) __a,
+ 						   (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_high_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_ssubl2v16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_high_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_ssubl2v8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_high_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_ssubl2v4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_high_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_usubl2v16qi ((int8x16_t) __a,
+ 						     (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_high_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_usubl2v8hi ((int16x8_t) __a,
+ 						    (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_high_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_usubl2v4si ((int32x4_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_s8 (int16x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_ssubwv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_s16 (int32x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_ssubwv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_s32 (int64x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_ssubwv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_u8 (uint16x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_usubwv8qi ((int16x8_t) __a,
+ 						   (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_u16 (uint32x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_usubwv4hi ((int32x4_t) __a,
+ 						   (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_u32 (uint64x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_usubwv2si ((int64x2_t) __a,
+ 						   (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_high_s8 (int16x8_t __a, int8x16_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_ssubw2v16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_high_s16 (int32x4_t __a, int16x8_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_ssubw2v8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_high_s32 (int64x2_t __a, int32x4_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_ssubw2v4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_high_u8 (uint16x8_t __a, uint8x16_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_usubw2v16qi ((int16x8_t) __a,
+ 						     (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_high_u16 (uint32x4_t __a, uint16x8_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_usubw2v8hi ((int32x4_t) __a,
+ 						    (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_high_u32 (uint64x2_t __a, uint32x4_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_usubw2v4si ((int64x2_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_sqaddv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_sqaddv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_sqaddv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t) {__builtin_aarch64_sqadddi (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __builtin_aarch64_uqaddv8qi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_aarch64_shsubv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_shsubv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_shsubv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_uhsubv8qi ((int8x8_t) __a,
+ 						  (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_uhsubv4hi ((int16x4_t) __a,
+ 						   (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_uhsubv2si ((int32x2_t) __a,
+ 						   (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t) __builtin_aarch64_shsubv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_shsubv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_shsubv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t) __builtin_aarch64_uhsubv16qi ((int8x16_t) __a,
+ 						    (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_uhsubv8hi ((int16x8_t) __a,
+ 						   (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_uhsubv4si ((int32x4_t) __a,
+ 						   (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_subhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_subhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_subhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_subhnv8hi ((int16x8_t) __a,
+ 						  (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_subhnv4si ((int32x4_t) __a,
+ 						   (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_subhnv2di ((int64x2_t) __a,
+ 						   (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_rsubhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_rsubhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_rsubhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t) __builtin_aarch64_rsubhnv8hi ((int16x8_t) __a,
+ 						   (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t) __builtin_aarch64_rsubhnv4si ((int32x4_t) __a,
+ 						    (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t) __builtin_aarch64_rsubhnv2di ((int64x2_t) __a,
+ 						    (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_high_s16 (int8x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int8x16_t) __builtin_aarch64_rsubhn2v8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_high_s32 (int16x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int16x8_t) __builtin_aarch64_rsubhn2v4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_high_s64 (int32x2_t __a, int64x2_t __b, int64x2_t __c)
+ {
+   return (int32x4_t) __builtin_aarch64_rsubhn2v2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint8x16_t) __builtin_aarch64_rsubhn2v8hi ((int8x8_t) __a,
+@@ -2297,7 +2615,8 @@ vrsubhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ 						     (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint16x8_t) __builtin_aarch64_rsubhn2v4si ((int16x4_t) __a,
+@@ -2305,7 +2624,8 @@ vrsubhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ 						     (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ {
+   return (uint32x4_t) __builtin_aarch64_rsubhn2v2di ((int32x2_t) __a,
+@@ -2313,25 +2633,29 @@ vrsubhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ 						     (int64x2_t) __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_high_s16 (int8x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int8x16_t) __builtin_aarch64_subhn2v8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_high_s32 (int16x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int16x8_t) __builtin_aarch64_subhn2v4si (__a, __b, __c);;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_high_s64 (int32x2_t __a, int64x2_t __b, int64x2_t __c)
+ {
+   return (int32x4_t) __builtin_aarch64_subhn2v2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint8x16_t) __builtin_aarch64_subhn2v8hi ((int8x8_t) __a,
+@@ -2339,7 +2663,8 @@ vsubhn_high_u16 (uint8x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ 						    (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint16x8_t) __builtin_aarch64_subhn2v4si ((int16x4_t) __a,
+@@ -2347,7 +2672,8 @@ vsubhn_high_u32 (uint16x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ 						    (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ {
+   return (uint32x4_t) __builtin_aarch64_subhn2v2di ((int32x2_t) __a,
+@@ -2355,453 +2681,542 @@ vsubhn_high_u64 (uint32x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ 						    (int64x2_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __builtin_aarch64_uqaddv4hi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __builtin_aarch64_uqaddv2si_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return (uint64x1_t) {__builtin_aarch64_uqadddi_uuu (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t) __builtin_aarch64_sqaddv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_sqaddv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_sqaddv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_sqaddv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __builtin_aarch64_uqaddv16qi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __builtin_aarch64_uqaddv8hi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __builtin_aarch64_uqaddv4si_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __builtin_aarch64_uqaddv2di_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t) __builtin_aarch64_sqsubv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_sqsubv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_sqsubv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t) {__builtin_aarch64_sqsubdi (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __builtin_aarch64_uqsubv8qi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __builtin_aarch64_uqsubv4hi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __builtin_aarch64_uqsubv2si_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return (uint64x1_t) {__builtin_aarch64_uqsubdi_uuu (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t) __builtin_aarch64_sqsubv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_sqsubv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_sqsubv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t) __builtin_aarch64_sqsubv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __builtin_aarch64_uqsubv16qi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __builtin_aarch64_uqsubv8hi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __builtin_aarch64_uqsubv4si_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __builtin_aarch64_uqsubv2di_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s8 (int8x8_t __a)
+ {
+   return (int8x8_t) __builtin_aarch64_sqnegv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s16 (int16x4_t __a)
+ {
+   return (int16x4_t) __builtin_aarch64_sqnegv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s32 (int32x2_t __a)
+ {
+   return (int32x2_t) __builtin_aarch64_sqnegv2si (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s64 (int64x1_t __a)
+ {
+   return (int64x1_t) {__builtin_aarch64_sqnegdi (__a[0])};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqnegq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t) __builtin_aarch64_sqnegv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqnegq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t) __builtin_aarch64_sqnegv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqnegq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t) __builtin_aarch64_sqnegv4si (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s8 (int8x8_t __a)
+ {
+   return (int8x8_t) __builtin_aarch64_sqabsv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s16 (int16x4_t __a)
+ {
+   return (int16x4_t) __builtin_aarch64_sqabsv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s32 (int32x2_t __a)
+ {
+   return (int32x2_t) __builtin_aarch64_sqabsv2si (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s64 (int64x1_t __a)
+ {
+   return (int64x1_t) {__builtin_aarch64_sqabsdi (__a[0])};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabsq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t) __builtin_aarch64_sqabsv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabsq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t) __builtin_aarch64_sqabsv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabsq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t) __builtin_aarch64_sqabsv4si (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_sqdmulhv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_sqdmulhv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_sqdmulhv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_sqdmulhv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t) __builtin_aarch64_sqrdmulhv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t) __builtin_aarch64_sqrdmulhv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_sqrdmulhv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_sqrdmulhv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s8 (uint64_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s16 (uint64_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s32 (uint64_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s64 (uint64_t __a)
+ {
+   return (int64x1_t) {__a};
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_f16 (uint64_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_f32 (uint64_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u8 (uint64_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u16 (uint64_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u32 (uint64_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u64 (uint64_t __a)
+ {
+   return (uint64x1_t) {__a};
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_f64 (uint64_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_p8 (uint64_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_p16 (uint64_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcreate_p64 (uint64_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
+ /* vget_lane  */
+ 
+-__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_f16 (float16x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_f32 (float32x2_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_f64 (float64x1_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_p8 (poly8x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_p16 (poly16x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vget_lane_p64 (poly64x1_t __a, const int __b)
++{
++  return __aarch64_vget_lane_any (__a, __b);
++}
++
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s8 (int8x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s16 (int16x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s32 (int32x2_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s64 (int64x1_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u8 (uint8x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u16 (uint16x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u32 (uint32x2_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u64 (uint64x1_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+@@ -2809,79 +3224,99 @@ vget_lane_u64 (uint64x1_t __a, const int __b)
+ 
+ /* vgetq_lane  */
+ 
+-__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_f16 (float16x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_f32 (float32x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_f64 (float64x2_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_p8 (poly8x16_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_p16 (poly16x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vgetq_lane_p64 (poly64x2_t __a, const int __b)
++{
++  return __aarch64_vget_lane_any (__a, __b);
++}
++
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s8 (int8x16_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s16 (int16x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s32 (int32x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s64 (int64x2_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u8 (uint8x16_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u16 (uint16x8_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u32 (uint32x4_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u64 (uint64x2_t __a, const int __b)
+ {
+   return __aarch64_vget_lane_any (__a, __b);
+@@ -2889,1953 +3324,2832 @@ vgetq_lane_u64 (uint64x2_t __a, const int __b)
+ 
+ /* vreinterpret  */
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_f16 (float16x4_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_f64 (float64x1_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s8 (int8x8_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s16 (int16x4_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s32 (int32x2_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s64 (int64x1_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_f32 (float32x2_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u8 (uint8x8_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u16 (uint16x4_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u32 (uint32x2_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u64 (uint64x1_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_p16 (poly16x4_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p8_p64 (poly64x1_t __a)
++{
++  return (poly8x8_t) __a;
++}
++
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_f64 (float64x2_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s8 (int8x16_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s16 (int16x8_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s32 (int32x4_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s64 (int64x2_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_f16 (float16x8_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_f32 (float32x4_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u8 (uint8x16_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u16 (uint16x8_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u32 (uint32x4_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u64 (uint64x2_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_p16 (poly16x8_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p8_p64 (poly64x2_t __a)
++{
++  return (poly8x16_t) __a;
++}
++
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p8_p128 (poly128_t __a)
++{
++  return (poly8x16_t)__a;
++}
++
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_f16 (float16x4_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_f64 (float64x1_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s8 (int8x8_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s16 (int16x4_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s32 (int32x2_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s64 (int64x1_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_f32 (float32x2_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u8 (uint8x8_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u16 (uint16x4_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u32 (uint32x2_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u64 (uint64x1_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_p8 (poly8x8_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p16_p64 (poly64x1_t __a)
++{
++  return (poly16x4_t) __a;
++}
++
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_f64 (float64x2_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s8 (int8x16_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s16 (int16x8_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s32 (int32x4_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s64 (int64x2_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_f16 (float16x8_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_f32 (float32x4_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u8 (uint8x16_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u16 (uint16x8_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u32 (uint32x4_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u64 (uint64x2_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_p8 (poly8x16_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p16_p64 (poly64x2_t __a)
++{
++  return (poly16x8_t) __a;
++}
++
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p16_p128 (poly128_t __a)
++{
++  return (poly16x8_t)__a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_f16 (float16x4_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_f64 (float64x1_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_s8 (int8x8_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_s16 (int16x4_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_s32 (int32x2_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_s64 (int64x1_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_f32 (float32x2_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_u8 (uint8x8_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_u16 (uint16x4_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_u32 (uint32x2_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_u64 (uint64x1_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_p8 (poly8x8_t __a)
++{
++  return (poly64x1_t) __a;
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_p64_p16 (poly16x4_t __a)
++{
++  return (poly64x1_t)__a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_f64 (float64x2_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_s8 (int8x16_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_s16 (int16x8_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_s32 (int32x4_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_s64 (int64x2_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_f16 (float16x8_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_f32 (float32x4_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_p128 (poly128_t __a)
++{
++  return (poly64x2_t)__a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_u8 (uint8x16_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_u16 (uint16x8_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_p16 (poly16x8_t __a)
++{
++  return (poly64x2_t)__a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_u32 (uint32x4_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_u64 (uint64x2_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p64_p8 (poly8x16_t __a)
++{
++  return (poly64x2_t) __a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_p8 (poly8x16_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_p16 (poly16x8_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_f16 (float16x8_t __a)
++{
++  return (poly128_t) __a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_f32 (float32x4_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_p64 (poly64x2_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_s64 (int64x2_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_u64 (uint64x2_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_s8 (int8x16_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_s16 (int16x8_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_s32 (int32x4_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_u8 (uint8x16_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_u16 (uint16x8_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_p128_u32 (uint32x4_t __a)
++{
++  return (poly128_t)__a;
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_f64 (float64x1_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s8 (int8x8_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s16 (int16x4_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s32 (int32x2_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s64 (int64x1_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_f32 (float32x2_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u8 (uint8x8_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u16 (uint16x4_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u32 (uint32x2_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u64 (uint64x1_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_p8 (poly8x8_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_p16 (poly16x4_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_f16_p64 (poly64x1_t __a)
++{
++  return (float16x4_t) __a;
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_f64 (float64x2_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s8 (int8x16_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s16 (int16x8_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s32 (int32x4_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s64 (int64x2_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_f32 (float32x4_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u8 (uint8x16_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u16 (uint16x8_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u32 (uint32x4_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u64 (uint64x2_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_p8 (poly8x16_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_f16_p128 (poly128_t __a)
++{
++  return (float16x8_t) __a;
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_p16 (poly16x8_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_f16_p64 (poly64x2_t __a)
++{
++  return (float16x8_t) __a;
++}
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_f16 (float16x4_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_f64 (float64x1_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s8 (int8x8_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s16 (int16x4_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s32 (int32x2_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s64 (int64x1_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u8 (uint8x8_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u16 (uint16x4_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u32 (uint32x2_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u64 (uint64x1_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_p8 (poly8x8_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_p16 (poly16x4_t __a)
+ {
+   return (float32x2_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_f32_p64 (poly64x1_t __a)
++{
++  return (float32x2_t) __a;
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_f16 (float16x8_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_f64 (float64x2_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s8 (int8x16_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s16 (int16x8_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s32 (int32x4_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s64 (int64x2_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u8 (uint8x16_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u16 (uint16x8_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u32 (uint32x4_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u64 (uint64x2_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_p8 (poly8x16_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_p16 (poly16x8_t __a)
+ {
+   return (float32x4_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_f32_p64 (poly64x2_t __a)
++{
++  return (float32x4_t) __a;
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_f32_p128 (poly128_t __a)
++{
++  return (float32x4_t)__a;
++}
++
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_f16 (float16x4_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_f32 (float32x2_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_p8 (poly8x8_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_p16 (poly16x4_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_f64_p64 (poly64x1_t __a)
++{
++  return (float64x1_t) __a;
++}
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_s8 (int8x8_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_s16 (int16x4_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_s32 (int32x2_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_s64 (int64x1_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_u8 (uint8x8_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_u16 (uint16x4_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_u32 (uint32x2_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f64_u64 (uint64x1_t __a)
+ {
+   return (float64x1_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_f16 (float16x8_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_f32 (float32x4_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_p8 (poly8x16_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_p16 (poly16x8_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_f64_p64 (poly64x2_t __a)
++{
++  return (float64x2_t) __a;
++}
++
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_s8 (int8x16_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_s16 (int16x8_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_s32 (int32x4_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_s64 (int64x2_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_u8 (uint8x16_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_u16 (uint16x8_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_u32 (uint32x4_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f64_u64 (uint64x2_t __a)
+ {
+   return (float64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_f16 (float16x4_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_f64 (float64x1_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_s8 (int8x8_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_s16 (int16x4_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_s32 (int32x2_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_f32 (float32x2_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u8 (uint8x8_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u16 (uint16x4_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u32 (uint32x2_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u64 (uint64x1_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_p8 (poly8x8_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_p16 (poly16x4_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_s64_p64 (poly64x1_t __a)
++{
++  return (int64x1_t) __a;
++}
++
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_f64 (float64x2_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_s8 (int8x16_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_s16 (int16x8_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_s32 (int32x4_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_f16 (float16x8_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_f32 (float32x4_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u8 (uint8x16_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u16 (uint16x8_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u32 (uint32x4_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u64 (uint64x2_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_p8 (poly8x16_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_p16 (poly16x8_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s64_p64 (poly64x2_t __a)
++{
++  return (int64x2_t) __a;
++}
++
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s64_p128 (poly128_t __a)
++{
++  return (int64x2_t)__a;
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_f16 (float16x4_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_f64 (float64x1_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s8 (int8x8_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s16 (int16x4_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s32 (int32x2_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s64 (int64x1_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_f32 (float32x2_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_u8 (uint8x8_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_u16 (uint16x4_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_u32 (uint32x2_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_p8 (poly8x8_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_p16 (poly16x4_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_u64_p64 (poly64x1_t __a)
++{
++  return (uint64x1_t) __a;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_f64 (float64x2_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s8 (int8x16_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s16 (int16x8_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s32 (int32x4_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s64 (int64x2_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_f16 (float16x8_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_f32 (float32x4_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_u8 (uint8x16_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_u16 (uint16x8_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_u32 (uint32x4_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_p8 (poly8x16_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_p16 (poly16x8_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u64_p64 (poly64x2_t __a)
++{
++  return (uint64x2_t) __a;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u64_p128 (poly128_t __a)
++{
++  return (uint64x2_t)__a;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_f16 (float16x4_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_f64 (float64x1_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_s16 (int16x4_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_s32 (int32x2_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_s64 (int64x1_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_f32 (float32x2_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u8 (uint8x8_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u16 (uint16x4_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u32 (uint32x2_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u64 (uint64x1_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_p8 (poly8x8_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_p16 (poly16x4_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_s8_p64 (poly64x1_t __a)
++{
++  return (int8x8_t) __a;
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_f64 (float64x2_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_s16 (int16x8_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_s32 (int32x4_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_s64 (int64x2_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_f16 (float16x8_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_f32 (float32x4_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u8 (uint8x16_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u16 (uint16x8_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u32 (uint32x4_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u64 (uint64x2_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_p8 (poly8x16_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_p16 (poly16x8_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s8_p64 (poly64x2_t __a)
++{
++  return (int8x16_t) __a;
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s8_p128 (poly128_t __a)
++{
++  return (int8x16_t)__a;
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_f16 (float16x4_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_f64 (float64x1_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_s8 (int8x8_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_s32 (int32x2_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_s64 (int64x1_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_f32 (float32x2_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u8 (uint8x8_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u16 (uint16x4_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u32 (uint32x2_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u64 (uint64x1_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_p8 (poly8x8_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_p16 (poly16x4_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_s16_p64 (poly64x1_t __a)
++{
++  return (int16x4_t) __a;
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_f64 (float64x2_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_s8 (int8x16_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_s32 (int32x4_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_s64 (int64x2_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_f16 (float16x8_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_f32 (float32x4_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u8 (uint8x16_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u16 (uint16x8_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u32 (uint32x4_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u64 (uint64x2_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_p8 (poly8x16_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_p16 (poly16x8_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s16_p64 (poly64x2_t __a)
++{
++  return (int16x8_t) __a;
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s16_p128 (poly128_t __a)
++{
++  return (int16x8_t)__a;
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_f16 (float16x4_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_f64 (float64x1_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_s8 (int8x8_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_s16 (int16x4_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_s64 (int64x1_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_f32 (float32x2_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u8 (uint8x8_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u16 (uint16x4_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u32 (uint32x2_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u64 (uint64x1_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_p8 (poly8x8_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_p16 (poly16x4_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_s32_p64 (poly64x1_t __a)
++{
++  return (int32x2_t) __a;
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_f64 (float64x2_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_s8 (int8x16_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_s16 (int16x8_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_s64 (int64x2_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_f16 (float16x8_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_f32 (float32x4_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u8 (uint8x16_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u16 (uint16x8_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u32 (uint32x4_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u64 (uint64x2_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_p8 (poly8x16_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_p16 (poly16x8_t __a)
+ {
+   return (int32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s32_p64 (poly64x2_t __a)
++{
++  return (int32x4_t) __a;
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_s32_p128 (poly128_t __a)
++{
++  return (int32x4_t)__a;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_f16 (float16x4_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_f64 (float64x1_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s8 (int8x8_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s16 (int16x4_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s32 (int32x2_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s64 (int64x1_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_f32 (float32x2_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_u16 (uint16x4_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_u32 (uint32x2_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_u64 (uint64x1_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_p8 (poly8x8_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_p16 (poly16x4_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_u8_p64 (poly64x1_t __a)
++{
++  return (uint8x8_t) __a;
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_f64 (float64x2_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s8 (int8x16_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s16 (int16x8_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s32 (int32x4_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s64 (int64x2_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_f16 (float16x8_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_f32 (float32x4_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_u16 (uint16x8_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_u32 (uint32x4_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_u64 (uint64x2_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_p8 (poly8x16_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_p16 (poly16x8_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u8_p64 (poly64x2_t __a)
++{
++  return (uint8x16_t) __a;
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u8_p128 (poly128_t __a)
++{
++  return (uint8x16_t)__a;
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_f16 (float16x4_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_f64 (float64x1_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s8 (int8x8_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s16 (int16x4_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s32 (int32x2_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s64 (int64x1_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_f32 (float32x2_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_u8 (uint8x8_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_u32 (uint32x2_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_u64 (uint64x1_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_p8 (poly8x8_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_p16 (poly16x4_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_u16_p64 (poly64x1_t __a)
++{
++  return (uint16x4_t) __a;
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_f64 (float64x2_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s8 (int8x16_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s16 (int16x8_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s32 (int32x4_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s64 (int64x2_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_f16 (float16x8_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_f32 (float32x4_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_u8 (uint8x16_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_u32 (uint32x4_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_u64 (uint64x2_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_p8 (poly8x16_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_p16 (poly16x8_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u16_p64 (poly64x2_t __a)
++{
++  return (uint16x8_t) __a;
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u16_p128 (poly128_t __a)
++{
++  return (uint16x8_t)__a;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_f16 (float16x4_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_f64 (float64x1_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s8 (int8x8_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s16 (int16x4_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s32 (int32x2_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s64 (int64x1_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_f32 (float32x2_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_u8 (uint8x8_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_u16 (uint16x4_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_u64 (uint64x1_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_p8 (poly8x8_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_p16 (poly16x4_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpret_u32_p64 (poly64x1_t __a)
++{
++  return (uint32x2_t) __a;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_f64 (float64x2_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s8 (int8x16_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s16 (int16x8_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s32 (int32x4_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s64 (int64x2_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_f16 (float16x8_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_f32 (float32x4_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_u8 (uint8x16_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_u16 (uint16x8_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_u64 (uint64x2_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_p8 (poly8x16_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_p16 (poly16x8_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ 
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u32_p64 (poly64x2_t __a)
++{
++  return (uint32x4_t) __a;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vreinterpretq_u32_p128 (poly128_t __a)
++{
++  return (uint32x4_t)__a;
++}
++
+ /* vset_lane  */
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_f16 (float16_t __elem, float16x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_f32 (float32_t __elem, float32x2_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_f64 (float64_t __elem, float64x1_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_p8 (poly8_t __elem, poly8x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_p16 (poly16_t __elem, poly16x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vset_lane_p64 (poly64_t __elem, poly64x1_t __vec, const int __index)
++{
++  return __aarch64_vset_lane_any (__elem, __vec, __index);
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s8 (int8_t __elem, int8x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s16 (int16_t __elem, int16x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s32 (int32_t __elem, int32x2_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s64 (int64_t __elem, int64x1_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u8 (uint8_t __elem, uint8x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u16 (uint16_t __elem, uint16x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u32 (uint32_t __elem, uint32x2_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u64 (uint64_t __elem, uint64x1_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+@@ -4843,79 +6157,99 @@ vset_lane_u64 (uint64_t __elem, uint64x1_t __vec, const int __index)
+ 
+ /* vsetq_lane  */
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_f16 (float16_t __elem, float16x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_f32 (float32_t __elem, float32x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_f64 (float64_t __elem, float64x2_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_p8 (poly8_t __elem, poly8x16_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_p16 (poly16_t __elem, poly16x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsetq_lane_p64 (poly64_t __elem, poly64x2_t __vec, const int __index)
++{
++  return __aarch64_vset_lane_any (__elem, __vec, __index);
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s8 (int8_t __elem, int8x16_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s16 (int16_t __elem, int16x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s32 (int32_t __elem, int32x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s64 (int64_t __elem, int64x2_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u8 (uint8_t __elem, uint8x16_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u16 (uint16_t __elem, uint16x8_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u32 (uint32_t __elem, uint32x4_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u64 (uint64_t __elem, uint64x2_t __vec, const int __index)
+ {
+   return __aarch64_vset_lane_any (__elem, __vec, __index);
+@@ -4926,79 +6260,99 @@ vsetq_lane_u64 (uint64_t __elem, uint64x2_t __vec, const int __index)
+   uint64x1_t lo = vcreate_u64 (vgetq_lane_u64 (tmp, 0));  \
+   return vreinterpret_##__TYPE##_u64 (lo);
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_f16 (float16x8_t __a)
+ {
+   __GET_LOW (f16);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_f32 (float32x4_t __a)
+ {
+   __GET_LOW (f32);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_f64 (float64x2_t __a)
+ {
+   return (float64x1_t) {vgetq_lane_f64 (__a, 0)};
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_p8 (poly8x16_t __a)
+ {
+   __GET_LOW (p8);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_p16 (poly16x8_t __a)
+ {
+   __GET_LOW (p16);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vget_low_p64 (poly64x2_t __a)
++{
++  __GET_LOW (p64);
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s8 (int8x16_t __a)
+ {
+   __GET_LOW (s8);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s16 (int16x8_t __a)
+ {
+   __GET_LOW (s16);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s32 (int32x4_t __a)
+ {
+   __GET_LOW (s32);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s64 (int64x2_t __a)
+ {
+   __GET_LOW (s64);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u8 (uint8x16_t __a)
+ {
+   __GET_LOW (u8);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u16 (uint16x8_t __a)
+ {
+   __GET_LOW (u16);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u32 (uint32x4_t __a)
+ {
+   __GET_LOW (u32);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u64 (uint64x2_t __a)
+ {
+   return vcreate_u64 (vgetq_lane_u64 (__a, 0));
+@@ -5011,73 +6365,92 @@ vget_low_u64 (uint64x2_t __a)
+   uint64x1_t hi = vcreate_u64 (vgetq_lane_u64 (tmp, 1));	\
+   return vreinterpret_##__TYPE##_u64 (hi);
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_f16 (float16x8_t __a)
+ {
+   __GET_HIGH (f16);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_f32 (float32x4_t __a)
+ {
+   __GET_HIGH (f32);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_f64 (float64x2_t __a)
+ {
+   __GET_HIGH (f64);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_p8 (poly8x16_t __a)
+ {
+   __GET_HIGH (p8);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_p16 (poly16x8_t __a)
+ {
+   __GET_HIGH (p16);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vget_high_p64 (poly64x2_t __a)
++{
++  __GET_HIGH (p64);
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s8 (int8x16_t __a)
+ {
+   __GET_HIGH (s8);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s16 (int16x8_t __a)
+ {
+   __GET_HIGH (s16);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s32 (int32x4_t __a)
+ {
+   __GET_HIGH (s32);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s64 (int64x2_t __a)
+ {
+   __GET_HIGH (s64);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u8 (uint8x16_t __a)
+ {
+   __GET_HIGH (u8);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u16 (uint16x8_t __a)
+ {
+   __GET_HIGH (u16);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u32 (uint32x4_t __a)
+ {
+   __GET_HIGH (u32);
+@@ -5085,98 +6458,120 @@ vget_high_u32 (uint32x4_t __a)
+ 
+ #undef __GET_HIGH
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u64 (uint64x2_t __a)
+ {
+   return vcreate_u64 (vgetq_lane_u64 (__a, 1));
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x16_t) __builtin_aarch64_combinev8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x8_t) __builtin_aarch64_combinev4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x4_t) __builtin_aarch64_combinev2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __builtin_aarch64_combinedi (__a[0], __b[0]);
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_f16 (float16x4_t __a, float16x4_t __b)
+ {
+   return __builtin_aarch64_combinev4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x4_t) __builtin_aarch64_combinev2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x16_t) __builtin_aarch64_combinev8qi ((int8x8_t) __a,
+ 						     (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x8_t) __builtin_aarch64_combinev4hi ((int16x4_t) __a,
+ 						     (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x4_t) __builtin_aarch64_combinev2si ((int32x2_t) __a,
+ 						     (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return (uint64x2_t) __builtin_aarch64_combinedi (__a[0], __b[0]);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_f64 (float64x1_t __a, float64x1_t __b)
+ {
+   return __builtin_aarch64_combinedf (__a[0], __b[0]);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (poly8x16_t) __builtin_aarch64_combinev8qi ((int8x8_t) __a,
+ 						     (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+   return (poly16x8_t) __builtin_aarch64_combinev4hi ((int16x4_t) __a,
+ 						     (int16x4_t) __b);
+ }
+ 
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcombine_p64 (poly64x1_t __a, poly64x1_t __b)
++{
++  return (poly64x2_t) __builtin_aarch64_combinedi_ppp (__a[0], __b[0]);
++}
++
+ /* Start of temporary inline asm implementations.  */
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
+ {
+   int8x8_t result;
+@@ -5187,7 +6582,8 @@ vaba_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
+ {
+   int16x4_t result;
+@@ -5198,7 +6594,8 @@ vaba_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
+ {
+   int32x2_t result;
+@@ -5209,7 +6606,8 @@ vaba_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
+ {
+   uint8x8_t result;
+@@ -5220,7 +6618,8 @@ vaba_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
+ {
+   uint16x4_t result;
+@@ -5231,7 +6630,8 @@ vaba_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
+ {
+   uint32x2_t result;
+@@ -5242,7 +6642,8 @@ vaba_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
+ {
+   int16x8_t result;
+@@ -5253,7 +6654,8 @@ vabal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+ {
+   int32x4_t result;
+@@ -5264,7 +6666,8 @@ vabal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
+ {
+   int64x2_t result;
+@@ -5275,7 +6678,8 @@ vabal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
+ {
+   uint16x8_t result;
+@@ -5286,7 +6690,8 @@ vabal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
+ {
+   uint32x4_t result;
+@@ -5297,7 +6702,8 @@ vabal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
+ {
+   uint64x2_t result;
+@@ -5308,7 +6714,8 @@ vabal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
+ {
+   int16x8_t result;
+@@ -5319,7 +6726,8 @@ vabal_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+ {
+   int32x4_t result;
+@@ -5330,7 +6738,8 @@ vabal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
+ {
+   int64x2_t result;
+@@ -5341,7 +6750,8 @@ vabal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
+ {
+   uint16x8_t result;
+@@ -5352,7 +6762,8 @@ vabal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
+ {
+   uint32x4_t result;
+@@ -5363,7 +6774,8 @@ vabal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
+ {
+   uint64x2_t result;
+@@ -5374,7 +6786,8 @@ vabal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
+ {
+   int8x16_t result;
+@@ -5385,7 +6798,8 @@ vabaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
+ {
+   int16x8_t result;
+@@ -5396,7 +6810,8 @@ vabaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
+ {
+   int32x4_t result;
+@@ -5407,7 +6822,8 @@ vabaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ {
+   uint8x16_t result;
+@@ -5418,7 +6834,8 @@ vabaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ {
+   uint16x8_t result;
+@@ -5429,7 +6846,8 @@ vabaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ {
+   uint32x4_t result;
+@@ -5440,18 +6858,8 @@ vabaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+   return result;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vabd_f32 (float32x2_t a, float32x2_t b)
+-{
+-  float32x2_t result;
+-  __asm__ ("fabd %0.2s, %1.2s, %2.2s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_s8 (int8x8_t a, int8x8_t b)
+ {
+   int8x8_t result;
+@@ -5462,7 +6870,8 @@ vabd_s8 (int8x8_t a, int8x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_s16 (int16x4_t a, int16x4_t b)
+ {
+   int16x4_t result;
+@@ -5473,7 +6882,8 @@ vabd_s16 (int16x4_t a, int16x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_s32 (int32x2_t a, int32x2_t b)
+ {
+   int32x2_t result;
+@@ -5484,7 +6894,8 @@ vabd_s32 (int32x2_t a, int32x2_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_u8 (uint8x8_t a, uint8x8_t b)
+ {
+   uint8x8_t result;
+@@ -5495,7 +6906,8 @@ vabd_u8 (uint8x8_t a, uint8x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_u16 (uint16x4_t a, uint16x4_t b)
+ {
+   uint16x4_t result;
+@@ -5506,7 +6918,8 @@ vabd_u16 (uint16x4_t a, uint16x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_u32 (uint32x2_t a, uint32x2_t b)
+ {
+   uint32x2_t result;
+@@ -5517,18 +6930,8 @@ vabd_u32 (uint32x2_t a, uint32x2_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vabdd_f64 (float64_t a, float64_t b)
+-{
+-  float64_t result;
+-  __asm__ ("fabd %d0, %d1, %d2"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_high_s8 (int8x16_t a, int8x16_t b)
+ {
+   int16x8_t result;
+@@ -5539,7 +6942,8 @@ vabdl_high_s8 (int8x16_t a, int8x16_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_high_s16 (int16x8_t a, int16x8_t b)
+ {
+   int32x4_t result;
+@@ -5550,7 +6954,8 @@ vabdl_high_s16 (int16x8_t a, int16x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_high_s32 (int32x4_t a, int32x4_t b)
+ {
+   int64x2_t result;
+@@ -5561,7 +6966,8 @@ vabdl_high_s32 (int32x4_t a, int32x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_high_u8 (uint8x16_t a, uint8x16_t b)
+ {
+   uint16x8_t result;
+@@ -5572,7 +6978,8 @@ vabdl_high_u8 (uint8x16_t a, uint8x16_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_high_u16 (uint16x8_t a, uint16x8_t b)
+ {
+   uint32x4_t result;
+@@ -5583,7 +6990,8 @@ vabdl_high_u16 (uint16x8_t a, uint16x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_high_u32 (uint32x4_t a, uint32x4_t b)
+ {
+   uint64x2_t result;
+@@ -5594,7 +7002,8 @@ vabdl_high_u32 (uint32x4_t a, uint32x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_s8 (int8x8_t a, int8x8_t b)
+ {
+   int16x8_t result;
+@@ -5605,7 +7014,8 @@ vabdl_s8 (int8x8_t a, int8x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_s16 (int16x4_t a, int16x4_t b)
+ {
+   int32x4_t result;
+@@ -5616,7 +7026,8 @@ vabdl_s16 (int16x4_t a, int16x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_s32 (int32x2_t a, int32x2_t b)
+ {
+   int64x2_t result;
+@@ -5627,7 +7038,8 @@ vabdl_s32 (int32x2_t a, int32x2_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_u8 (uint8x8_t a, uint8x8_t b)
+ {
+   uint16x8_t result;
+@@ -5638,7 +7050,8 @@ vabdl_u8 (uint8x8_t a, uint8x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_u16 (uint16x4_t a, uint16x4_t b)
+ {
+   uint32x4_t result;
+@@ -5649,7 +7062,8 @@ vabdl_u16 (uint16x4_t a, uint16x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_u32 (uint32x2_t a, uint32x2_t b)
+ {
+   uint64x2_t result;
+@@ -5660,29 +7074,8 @@ vabdl_u32 (uint32x2_t a, uint32x2_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vabdq_f32 (float32x4_t a, float32x4_t b)
+-{
+-  float32x4_t result;
+-  __asm__ ("fabd %0.4s, %1.4s, %2.4s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vabdq_f64 (float64x2_t a, float64x2_t b)
+-{
+-  float64x2_t result;
+-  __asm__ ("fabd %0.2d, %1.2d, %2.2d"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_s8 (int8x16_t a, int8x16_t b)
+ {
+   int8x16_t result;
+@@ -5693,7 +7086,8 @@ vabdq_s8 (int8x16_t a, int8x16_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_s16 (int16x8_t a, int16x8_t b)
+ {
+   int16x8_t result;
+@@ -5704,7 +7098,8 @@ vabdq_s16 (int16x8_t a, int16x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_s32 (int32x4_t a, int32x4_t b)
+ {
+   int32x4_t result;
+@@ -5715,7 +7110,8 @@ vabdq_s32 (int32x4_t a, int32x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_u8 (uint8x16_t a, uint8x16_t b)
+ {
+   uint8x16_t result;
+@@ -5726,7 +7122,8 @@ vabdq_u8 (uint8x16_t a, uint8x16_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_u16 (uint16x8_t a, uint16x8_t b)
+ {
+   uint16x8_t result;
+@@ -5737,7 +7134,8 @@ vabdq_u16 (uint16x8_t a, uint16x8_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_u32 (uint32x4_t a, uint32x4_t b)
+ {
+   uint32x4_t result;
+@@ -5748,18 +7146,8 @@ vabdq_u32 (uint32x4_t a, uint32x4_t b)
+   return result;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vabds_f32 (float32_t a, float32_t b)
+-{
+-  float32_t result;
+-  __asm__ ("fabd %s0, %s1, %s2"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlv_s8 (int8x8_t a)
+ {
+   int16_t result;
+@@ -5770,7 +7158,8 @@ vaddlv_s8 (int8x8_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlv_s16 (int16x4_t a)
+ {
+   int32_t result;
+@@ -5781,7 +7170,8 @@ vaddlv_s16 (int16x4_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlv_u8 (uint8x8_t a)
+ {
+   uint16_t result;
+@@ -5792,7 +7182,8 @@ vaddlv_u8 (uint8x8_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlv_u16 (uint16x4_t a)
+ {
+   uint32_t result;
+@@ -5803,7 +7194,8 @@ vaddlv_u16 (uint16x4_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlvq_s8 (int8x16_t a)
+ {
+   int16_t result;
+@@ -5814,7 +7206,8 @@ vaddlvq_s8 (int8x16_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlvq_s16 (int16x8_t a)
+ {
+   int32_t result;
+@@ -5825,7 +7218,8 @@ vaddlvq_s16 (int16x8_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlvq_s32 (int32x4_t a)
+ {
+   int64_t result;
+@@ -5836,7 +7230,8 @@ vaddlvq_s32 (int32x4_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlvq_u8 (uint8x16_t a)
+ {
+   uint16_t result;
+@@ -5847,7 +7242,8 @@ vaddlvq_u8 (uint8x16_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlvq_u16 (uint16x8_t a)
+ {
+   uint32_t result;
+@@ -5858,7 +7254,8 @@ vaddlvq_u16 (uint16x8_t a)
+   return result;
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddlvq_u32 (uint32x4_t a)
+ {
+   uint64_t result;
+@@ -5869,18584 +7266,23099 @@ vaddlvq_u32 (uint32x4_t a)
+   return result;
+ }
+ 
+-#define vcopyq_lane_f32(a, b, c, d)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float32x4_t c_ = (c);                                            \
+-       float32x4_t a_ = (a);                                            \
+-       float32x4_t result;                                              \
+-       __asm__ ("ins %0.s[%2], %3.s[%4]"                                \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtx_f32_f64 (float64x2_t a)
++{
++  float32x2_t result;
++  __asm__ ("fcvtxn %0.2s,%1.2d"
++           : "=w"(result)
++           : "w"(a)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtx_high_f32_f64 (float32x2_t a, float64x2_t b)
++{
++  float32x4_t result;
++  __asm__ ("fcvtxn2 %0.4s,%1.2d"
++           : "=w"(result)
++           : "w" (b), "0"(a)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtxd_f32_f64 (float64_t a)
++{
++  float32_t result;
++  __asm__ ("fcvtxn %s0,%d1"
++           : "=w"(result)
++           : "w"(a)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_n_f32 (float32x2_t a, float32x2_t b, float32_t c)
++{
++  float32x2_t result;
++  float32x2_t t1;
++  __asm__ ("fmul %1.2s, %3.2s, %4.s[0]; fadd %0.2s, %0.2s, %1.2s"
++           : "=w"(result), "=w"(t1)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_n_s16 (int16x4_t a, int16x4_t b, int16_t c)
++{
++  int16x4_t result;
++  __asm__ ("mla %0.4h,%2.4h,%3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_n_s32 (int32x2_t a, int32x2_t b, int32_t c)
++{
++  int32x2_t result;
++  __asm__ ("mla %0.2s,%2.2s,%3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c)
++{
++  uint16x4_t result;
++  __asm__ ("mla %0.4h,%2.4h,%3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c)
++{
++  uint32x2_t result;
++  __asm__ ("mla %0.2s,%2.2s,%3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
++{
++  int8x8_t result;
++  __asm__ ("mla %0.8b, %2.8b, %3.8b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
++{
++  int16x4_t result;
++  __asm__ ("mla %0.4h, %2.4h, %3.4h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
++{
++  int32x2_t result;
++  __asm__ ("mla %0.2s, %2.2s, %3.2s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
++{
++  uint8x8_t result;
++  __asm__ ("mla %0.8b, %2.8b, %3.8b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
++{
++  uint16x4_t result;
++  __asm__ ("mla %0.4h, %2.4h, %3.4h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
++{
++  uint32x2_t result;
++  __asm__ ("mla %0.2s, %2.2s, %3.2s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcopyq_lane_f64(a, b, c, d)                                     \
++#define vmlal_high_lane_s16(a, b, c, d)                                 \
+   __extension__                                                         \
+     ({                                                                  \
+-       float64x2_t c_ = (c);                                            \
+-       float64x2_t a_ = (a);                                            \
+-       float64x2_t result;                                              \
+-       __asm__ ("ins %0.d[%2], %3.d[%4]"                                \
++       int16x4_t c_ = (c);                                              \
++       int16x8_t b_ = (b);                                              \
++       int32x4_t a_ = (a);                                              \
++       int32x4_t result;                                                \
++       __asm__ ("smlal2 %0.4s, %2.8h, %3.h[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_p8(a, b, c, d)                                      \
++#define vmlal_high_lane_s32(a, b, c, d)                                 \
+   __extension__                                                         \
+     ({                                                                  \
+-       poly8x16_t c_ = (c);                                             \
+-       poly8x16_t a_ = (a);                                             \
+-       poly8x16_t result;                                               \
+-       __asm__ ("ins %0.b[%2], %3.b[%4]"                                \
++       int32x2_t c_ = (c);                                              \
++       int32x4_t b_ = (b);                                              \
++       int64x2_t a_ = (a);                                              \
++       int64x2_t result;                                                \
++       __asm__ ("smlal2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_p16(a, b, c, d)                                     \
++#define vmlal_high_lane_u16(a, b, c, d)                                 \
+   __extension__                                                         \
+     ({                                                                  \
+-       poly16x8_t c_ = (c);                                             \
+-       poly16x8_t a_ = (a);                                             \
+-       poly16x8_t result;                                               \
+-       __asm__ ("ins %0.h[%2], %3.h[%4]"                                \
++       uint16x4_t c_ = (c);                                             \
++       uint16x8_t b_ = (b);                                             \
++       uint32x4_t a_ = (a);                                             \
++       uint32x4_t result;                                               \
++       __asm__ ("umlal2 %0.4s, %2.8h, %3.h[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_s8(a, b, c, d)                                      \
++#define vmlal_high_lane_u32(a, b, c, d)                                 \
+   __extension__                                                         \
+     ({                                                                  \
+-       int8x16_t c_ = (c);                                              \
+-       int8x16_t a_ = (a);                                              \
+-       int8x16_t result;                                                \
+-       __asm__ ("ins %0.b[%2], %3.b[%4]"                                \
++       uint32x2_t c_ = (c);                                             \
++       uint32x4_t b_ = (b);                                             \
++       uint64x2_t a_ = (a);                                             \
++       uint64x2_t result;                                               \
++       __asm__ ("umlal2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_s16(a, b, c, d)                                     \
++#define vmlal_high_laneq_s16(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+        int16x8_t c_ = (c);                                              \
+-       int16x8_t a_ = (a);                                              \
+-       int16x8_t result;                                                \
+-       __asm__ ("ins %0.h[%2], %3.h[%4]"                                \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vcopyq_lane_s32(a, b, c, d)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t c_ = (c);                                              \
++       int16x8_t b_ = (b);                                              \
+        int32x4_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("ins %0.s[%2], %3.s[%4]"                                \
++       __asm__ ("smlal2 %0.4s, %2.8h, %3.h[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_s64(a, b, c, d)                                     \
++#define vmlal_high_laneq_s32(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+-       int64x2_t c_ = (c);                                              \
++       int32x4_t c_ = (c);                                              \
++       int32x4_t b_ = (b);                                              \
+        int64x2_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("ins %0.d[%2], %3.d[%4]"                                \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vcopyq_lane_u8(a, b, c, d)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint8x16_t c_ = (c);                                             \
+-       uint8x16_t a_ = (a);                                             \
+-       uint8x16_t result;                                               \
+-       __asm__ ("ins %0.b[%2], %3.b[%4]"                                \
++       __asm__ ("smlal2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_u16(a, b, c, d)                                     \
++#define vmlal_high_laneq_u16(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+        uint16x8_t c_ = (c);                                             \
+-       uint16x8_t a_ = (a);                                             \
+-       uint16x8_t result;                                               \
+-       __asm__ ("ins %0.h[%2], %3.h[%4]"                                \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vcopyq_lane_u32(a, b, c, d)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t c_ = (c);                                             \
++       uint16x8_t b_ = (b);                                             \
+        uint32x4_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("ins %0.s[%2], %3.s[%4]"                                \
++       __asm__ ("umlal2 %0.4s, %2.8h, %3.h[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcopyq_lane_u64(a, b, c, d)                                     \
++#define vmlal_high_laneq_u32(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint64x2_t c_ = (c);                                             \
++       uint32x4_t c_ = (c);                                             \
++       uint32x4_t b_ = (b);                                             \
+        uint64x2_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("ins %0.d[%2], %3.d[%4]"                                \
++       __asm__ ("umlal2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "i"(b), "w"(c_), "i"(d)                      \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvt_n_f32_s32(a, b)                                            \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x2_t a_ = (a);                                              \
+-       float32x2_t result;                                              \
+-       __asm__ ("scvtf %0.2s, %1.2s, #%2"                               \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c)
++{
++  int32x4_t result;
++  __asm__ ("smlal2 %0.4s,%2.8h,%3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvt_n_f32_u32(a, b)                                            \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x2_t a_ = (a);                                             \
+-       float32x2_t result;                                              \
+-       __asm__ ("ucvtf %0.2s, %1.2s, #%2"                               \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c)
++{
++  int64x2_t result;
++  __asm__ ("smlal2 %0.2d,%2.4s,%3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvt_n_s32_f32(a, b)                                            \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float32x2_t a_ = (a);                                            \
+-       int32x2_t result;                                                \
+-       __asm__ ("fcvtzs %0.2s, %1.2s, #%2"                              \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_n_u16 (uint32x4_t a, uint16x8_t b, uint16_t c)
++{
++  uint32x4_t result;
++  __asm__ ("umlal2 %0.4s,%2.8h,%3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvt_n_u32_f32(a, b)                                            \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float32x2_t a_ = (a);                                            \
+-       uint32x2_t result;                                               \
+-       __asm__ ("fcvtzu %0.2s, %1.2s, #%2"                              \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_n_u32 (uint64x2_t a, uint32x4_t b, uint32_t c)
++{
++  uint64x2_t result;
++  __asm__ ("umlal2 %0.2d,%2.4s,%3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvtd_n_f64_s64(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64_t a_ = (a);                                                \
+-       float64_t result;                                                \
+-       __asm__ ("scvtf %d0,%d1,%2"                                      \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
++{
++  int16x8_t result;
++  __asm__ ("smlal2 %0.8h,%2.16b,%3.16b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvtd_n_f64_u64(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64_t a_ = (a);                                               \
+-       float64_t result;                                                \
+-       __asm__ ("ucvtf %d0,%d1,%2"                                      \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
++{
++  int32x4_t result;
++  __asm__ ("smlal2 %0.4s,%2.8h,%3.8h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvtd_n_s64_f64(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float64_t a_ = (a);                                              \
+-       int64_t result;                                                  \
+-       __asm__ ("fcvtzs %d0,%d1,%2"                                     \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
++{
++  int64x2_t result;
++  __asm__ ("smlal2 %0.2d,%2.4s,%3.4s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvtd_n_u64_f64(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float64_t a_ = (a);                                              \
+-       uint64_t result;                                                 \
+-       __asm__ ("fcvtzu %d0,%d1,%2"                                     \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
++{
++  uint16x8_t result;
++  __asm__ ("umlal2 %0.8h,%2.16b,%3.16b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
++{
++  uint32x4_t result;
++  __asm__ ("umlal2 %0.4s,%2.8h,%3.8h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
++{
++  uint64x2_t result;
++  __asm__ ("umlal2 %0.2d,%2.4s,%3.4s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvtq_n_f32_s32(a, b)                                           \
++#define vmlal_lane_s16(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
++       int16x4_t c_ = (c);                                              \
++       int16x4_t b_ = (b);                                              \
+        int32x4_t a_ = (a);                                              \
+-       float32x4_t result;                                              \
+-       __asm__ ("scvtf %0.4s, %1.4s, #%2"                               \
++       int32x4_t result;                                                \
++       __asm__ ("smlal %0.4s,%2.4h,%3.h[%4]"                            \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_f32_u32(a, b)                                           \
++#define vmlal_lane_s32(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint32x4_t a_ = (a);                                             \
+-       float32x4_t result;                                              \
+-       __asm__ ("ucvtf %0.4s, %1.4s, #%2"                               \
++       int32x2_t c_ = (c);                                              \
++       int32x2_t b_ = (b);                                              \
++       int64x2_t a_ = (a);                                              \
++       int64x2_t result;                                                \
++       __asm__ ("smlal %0.2d,%2.2s,%3.s[%4]"                            \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_f64_s64(a, b)                                           \
++#define vmlal_lane_u16(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+-       int64x2_t a_ = (a);                                              \
+-       float64x2_t result;                                              \
+-       __asm__ ("scvtf %0.2d, %1.2d, #%2"                               \
++       uint16x4_t c_ = (c);                                             \
++       uint16x4_t b_ = (b);                                             \
++       uint32x4_t a_ = (a);                                             \
++       uint32x4_t result;                                               \
++       __asm__ ("umlal %0.4s,%2.4h,%3.h[%4]"                            \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_f64_u64(a, b)                                           \
++#define vmlal_lane_u32(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
++       uint32x2_t c_ = (c);                                             \
++       uint32x2_t b_ = (b);                                             \
+        uint64x2_t a_ = (a);                                             \
+-       float64x2_t result;                                              \
+-       __asm__ ("ucvtf %0.2d, %1.2d, #%2"                               \
++       uint64x2_t result;                                               \
++       __asm__ ("umlal %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_s32_f32(a, b)                                           \
++#define vmlal_laneq_s16(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       float32x4_t a_ = (a);                                            \
++       int16x8_t c_ = (c);                                              \
++       int16x4_t b_ = (b);                                              \
++       int32x4_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("fcvtzs %0.4s, %1.4s, #%2"                              \
++       __asm__ ("smlal %0.4s, %2.4h, %3.h[%4]"                          \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_s64_f64(a, b)                                           \
++#define vmlal_laneq_s32(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       float64x2_t a_ = (a);                                            \
++       int32x4_t c_ = (c);                                              \
++       int32x2_t b_ = (b);                                              \
++       int64x2_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("fcvtzs %0.2d, %1.2d, #%2"                              \
++       __asm__ ("smlal %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_u32_f32(a, b)                                           \
++#define vmlal_laneq_u16(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       float32x4_t a_ = (a);                                            \
++       uint16x8_t c_ = (c);                                             \
++       uint16x4_t b_ = (b);                                             \
++       uint32x4_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("fcvtzu %0.4s, %1.4s, #%2"                              \
++       __asm__ ("umlal %0.4s, %2.4h, %3.h[%4]"                          \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvtq_n_u64_f64(a, b)                                           \
++#define vmlal_laneq_u32(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       float64x2_t a_ = (a);                                            \
+-       uint64x2_t result;                                               \
+-       __asm__ ("fcvtzu %0.2d, %1.2d, #%2"                              \
++       uint32x4_t c_ = (c);                                             \
++       uint32x2_t b_ = (b);                                             \
++       uint64x2_t a_ = (a);                                             \
++       uint64x2_t result;                                               \
++       __asm__ ("umlal %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vcvts_n_f32_s32(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32_t a_ = (a);                                                \
+-       float32_t result;                                                \
+-       __asm__ ("scvtf %s0,%s1,%2"                                      \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_n_s16 (int32x4_t a, int16x4_t b, int16_t c)
++{
++  int32x4_t result;
++  __asm__ ("smlal %0.4s,%2.4h,%3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvts_n_f32_u32(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32_t a_ = (a);                                               \
+-       float32_t result;                                                \
+-       __asm__ ("ucvtf %s0,%s1,%2"                                      \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_n_s32 (int64x2_t a, int32x2_t b, int32_t c)
++{
++  int64x2_t result;
++  __asm__ ("smlal %0.2d,%2.2s,%3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvts_n_s32_f32(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float32_t a_ = (a);                                              \
+-       int32_t result;                                                  \
+-       __asm__ ("fcvtzs %s0,%s1,%2"                                     \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_n_u16 (uint32x4_t a, uint16x4_t b, uint16_t c)
++{
++  uint32x4_t result;
++  __asm__ ("umlal %0.4s,%2.4h,%3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vcvts_n_u32_f32(a, b)                                           \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       float32_t a_ = (a);                                              \
+-       uint32_t result;                                                 \
+-       __asm__ ("fcvtzu %s0,%s1,%2"                                     \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_n_u32 (uint64x2_t a, uint32x2_t b, uint32_t c)
++{
++  uint64x2_t result;
++  __asm__ ("umlal %0.2d,%2.2s,%3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vcvtx_f32_f64 (float64x2_t a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
+ {
+-  float32x2_t result;
+-  __asm__ ("fcvtxn %0.2s,%1.2d"
++  int16x8_t result;
++  __asm__ ("smlal %0.8h,%2.8b,%3.8b"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vcvtx_high_f32_f64 (float32x2_t a, float64x2_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+ {
+-  float32x4_t result;
+-  __asm__ ("fcvtxn2 %0.4s,%1.2d"
++  int32x4_t result;
++  __asm__ ("smlal %0.4s,%2.4h,%3.4h"
+            : "=w"(result)
+-           : "w" (b), "0"(a)
++           : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vcvtxd_f32_f64 (float64_t a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
+ {
+-  float32_t result;
+-  __asm__ ("fcvtxn %s0,%d1"
++  int64x2_t result;
++  __asm__ ("smlal %0.2d,%2.2s,%3.2s"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmla_n_f32 (float32x2_t a, float32x2_t b, float32_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
+ {
+-  float32x2_t result;
+-  float32x2_t t1;
+-  __asm__ ("fmul %1.2s, %3.2s, %4.s[0]; fadd %0.2s, %0.2s, %1.2s"
++  uint16x8_t result;
++  __asm__ ("umlal %0.8h,%2.8b,%3.8b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
++{
++  uint32x4_t result;
++  __asm__ ("umlal %0.4s,%2.4h,%3.4h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
++{
++  uint64x2_t result;
++  __asm__ ("umlal %0.2d,%2.2s,%3.2s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_n_f32 (float32x4_t a, float32x4_t b, float32_t c)
++{
++  float32x4_t result;
++  float32x4_t t1;
++  __asm__ ("fmul %1.4s, %3.4s, %4.s[0]; fadd %0.4s, %0.4s, %1.4s"
+            : "=w"(result), "=w"(t1)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmla_n_s16 (int16x4_t a, int16x4_t b, int16_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)
+ {
+-  int16x4_t result;
+-  __asm__ ("mla %0.4h,%2.4h,%3.h[0]"
++  int16x8_t result;
++  __asm__ ("mla %0.8h,%2.8h,%3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmla_n_s32 (int32x2_t a, int32x2_t b, int32_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_n_s32 (int32x4_t a, int32x4_t b, int32_t c)
+ {
+-  int32x2_t result;
+-  __asm__ ("mla %0.2s,%2.2s,%3.s[0]"
++  int32x4_t result;
++  __asm__ ("mla %0.4s,%2.4s,%3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmla_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c)
+ {
+-  uint16x4_t result;
+-  __asm__ ("mla %0.4h,%2.4h,%3.h[0]"
++  uint16x8_t result;
++  __asm__ ("mla %0.8h,%2.8h,%3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmla_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c)
+ {
+-  uint32x2_t result;
+-  __asm__ ("mla %0.2s,%2.2s,%3.s[0]"
++  uint32x4_t result;
++  __asm__ ("mla %0.4s,%2.4s,%3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmla_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
+ {
+-  int8x8_t result;
+-  __asm__ ("mla %0.8b, %2.8b, %3.8b"
++  int8x16_t result;
++  __asm__ ("mla %0.16b, %2.16b, %3.16b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmla_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
+ {
+-  int16x4_t result;
+-  __asm__ ("mla %0.4h, %2.4h, %3.4h"
++  int16x8_t result;
++  __asm__ ("mla %0.8h, %2.8h, %3.8h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmla_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
+ {
+-  int32x2_t result;
+-  __asm__ ("mla %0.2s, %2.2s, %3.2s"
++  int32x4_t result;
++  __asm__ ("mla %0.4s, %2.4s, %3.4s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmla_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ {
+-  uint8x8_t result;
+-  __asm__ ("mla %0.8b, %2.8b, %3.8b"
++  uint8x16_t result;
++  __asm__ ("mla %0.16b, %2.16b, %3.16b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmla_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ {
+-  uint16x4_t result;
+-  __asm__ ("mla %0.4h, %2.4h, %3.4h"
++  uint16x8_t result;
++  __asm__ ("mla %0.8h, %2.8h, %3.8h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmla_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ {
+-  uint32x2_t result;
+-  __asm__ ("mla %0.2s, %2.2s, %3.2s"
++  uint32x4_t result;
++  __asm__ ("mla %0.4s, %2.4s, %3.4s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-#define vmlal_high_lane_s16(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x4_t c_ = (c);                                              \
+-       int16x8_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smlal2 %0.4s, %2.8h, %3.h[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmlal_high_lane_s32(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x2_t c_ = (c);                                              \
+-       int32x4_t b_ = (b);                                              \
+-       int64x2_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smlal2 %0.2d, %2.4s, %3.s[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_n_f32 (float32x2_t a, float32x2_t b, float32_t c)
++{
++  float32x2_t result;
++  float32x2_t t1;
++  __asm__ ("fmul %1.2s, %3.2s, %4.s[0]; fsub %0.2s, %0.2s, %1.2s"
++           : "=w"(result), "=w"(t1)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlal_high_lane_u16(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x4_t c_ = (c);                                             \
+-       uint16x8_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umlal2 %0.4s, %2.8h, %3.h[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_n_s16 (int16x4_t a, int16x4_t b, int16_t c)
++{
++  int16x4_t result;
++  __asm__ ("mls %0.4h, %2.4h, %3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlal_high_lane_u32(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x2_t c_ = (c);                                             \
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_n_s32 (int32x2_t a, int32x2_t b, int32_t c)
++{
++  int32x2_t result;
++  __asm__ ("mls %0.2s, %2.2s, %3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c)
++{
++  uint16x4_t result;
++  __asm__ ("mls %0.4h, %2.4h, %3.h[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "x"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c)
++{
++  uint32x2_t result;
++  __asm__ ("mls %0.2s, %2.2s, %3.s[0]"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
++{
++  int8x8_t result;
++  __asm__ ("mls %0.8b,%2.8b,%3.8b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
++{
++  int16x4_t result;
++  __asm__ ("mls %0.4h,%2.4h,%3.4h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
++{
++  int32x2_t result;
++  __asm__ ("mls %0.2s,%2.2s,%3.2s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
++{
++  uint8x8_t result;
++  __asm__ ("mls %0.8b,%2.8b,%3.8b"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
++{
++  uint16x4_t result;
++  __asm__ ("mls %0.4h,%2.4h,%3.4h"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
++{
++  uint32x2_t result;
++  __asm__ ("mls %0.2s,%2.2s,%3.2s"
++           : "=w"(result)
++           : "0"(a), "w"(b), "w"(c)
++           : /* No clobbers */);
++  return result;
++}
++
++#define vmlsl_high_lane_s16(a, b, c, d)                                 \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x4_t c_ = (c);                                              \
++       int16x8_t b_ = (b);                                              \
++       int32x4_t a_ = (a);                                              \
++       int32x4_t result;                                                \
++       __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmlsl_high_lane_s32(a, b, c, d)                                 \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x2_t c_ = (c);                                              \
++       int32x4_t b_ = (b);                                              \
++       int64x2_t a_ = (a);                                              \
++       int64x2_t result;                                                \
++       __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmlsl_high_lane_u16(a, b, c, d)                                 \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x4_t c_ = (c);                                             \
++       uint16x8_t b_ = (b);                                             \
++       uint32x4_t a_ = (a);                                             \
++       uint32x4_t result;                                               \
++       __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmlsl_high_lane_u32(a, b, c, d)                                 \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x2_t c_ = (c);                                             \
+        uint32x4_t b_ = (b);                                             \
+        uint64x2_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("umlal2 %0.2d, %2.4s, %3.s[%4]"                         \
++       __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_high_laneq_s16(a, b, c, d)                                \
++#define vmlsl_high_laneq_s16(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+        int16x8_t c_ = (c);                                              \
+        int16x8_t b_ = (b);                                              \
+        int32x4_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("smlal2 %0.4s, %2.8h, %3.h[%4]"                         \
++       __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_high_laneq_s32(a, b, c, d)                                \
++#define vmlsl_high_laneq_s32(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+        int32x4_t c_ = (c);                                              \
+        int32x4_t b_ = (b);                                              \
+        int64x2_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("smlal2 %0.2d, %2.4s, %3.s[%4]"                         \
++       __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_high_laneq_u16(a, b, c, d)                                \
++#define vmlsl_high_laneq_u16(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+        uint16x8_t c_ = (c);                                             \
+        uint16x8_t b_ = (b);                                             \
+        uint32x4_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("umlal2 %0.4s, %2.8h, %3.h[%4]"                         \
++       __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_high_laneq_u32(a, b, c, d)                                \
++#define vmlsl_high_laneq_u32(a, b, c, d)                                \
+   __extension__                                                         \
+     ({                                                                  \
+        uint32x4_t c_ = (c);                                             \
+        uint32x4_t b_ = (b);                                             \
+        uint64x2_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("umlal2 %0.2d, %2.4s, %3.s[%4]"                         \
++       __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlal_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c)
+ {
+   int32x4_t result;
+-  __asm__ ("smlal2 %0.4s,%2.8h,%3.h[0]"
++  __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlal_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c)
+ {
+   int64x2_t result;
+-  __asm__ ("smlal2 %0.2d,%2.4s,%3.s[0]"
++  __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlal_high_n_u16 (uint32x4_t a, uint16x8_t b, uint16_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_n_u16 (uint32x4_t a, uint16x8_t b, uint16_t c)
+ {
+   uint32x4_t result;
+-  __asm__ ("umlal2 %0.4s,%2.8h,%3.h[0]"
++  __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlal_high_n_u32 (uint64x2_t a, uint32x4_t b, uint32_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_n_u32 (uint64x2_t a, uint32x4_t b, uint32_t c)
+ {
+   uint64x2_t result;
+-  __asm__ ("umlal2 %0.2d,%2.4s,%3.s[0]"
++  __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
+ {
+   int16x8_t result;
+-  __asm__ ("smlal2 %0.8h,%2.16b,%3.16b"
++  __asm__ ("smlsl2 %0.8h,%2.16b,%3.16b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+ {
+   int32x4_t result;
+-  __asm__ ("smlal2 %0.4s,%2.8h,%3.8h"
++  __asm__ ("smlsl2 %0.4s,%2.8h,%3.8h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
+ {
+   int64x2_t result;
+-  __asm__ ("smlal2 %0.2d,%2.4s,%3.4s"
++  __asm__ ("smlsl2 %0.2d,%2.4s,%3.4s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
+ {
+   uint16x8_t result;
+-  __asm__ ("umlal2 %0.8h,%2.16b,%3.16b"
++  __asm__ ("umlsl2 %0.8h,%2.16b,%3.16b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
+ {
+   uint32x4_t result;
+-  __asm__ ("umlal2 %0.4s,%2.8h,%3.8h"
++  __asm__ ("umlsl2 %0.4s,%2.8h,%3.8h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
+ {
+   uint64x2_t result;
+-  __asm__ ("umlal2 %0.2d,%2.4s,%3.4s"
++  __asm__ ("umlsl2 %0.2d,%2.4s,%3.4s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-#define vmlal_lane_s16(a, b, c, d)                                      \
++#define vmlsl_lane_s16(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        int16x4_t c_ = (c);                                              \
+        int16x4_t b_ = (b);                                              \
+        int32x4_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("smlal %0.4s,%2.4h,%3.h[%4]"                            \
++       __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_lane_s32(a, b, c, d)                                      \
++#define vmlsl_lane_s32(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        int32x2_t c_ = (c);                                              \
+        int32x2_t b_ = (b);                                              \
+        int64x2_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("smlal %0.2d,%2.2s,%3.s[%4]"                            \
++       __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_lane_u16(a, b, c, d)                                      \
++#define vmlsl_lane_u16(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        uint16x4_t c_ = (c);                                             \
+        uint16x4_t b_ = (b);                                             \
+        uint32x4_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("umlal %0.4s,%2.4h,%3.h[%4]"                            \
++       __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_lane_u32(a, b, c, d)                                      \
++#define vmlsl_lane_u32(a, b, c, d)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        uint32x2_t c_ = (c);                                             \
+        uint32x2_t b_ = (b);                                             \
+        uint64x2_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("umlal %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_laneq_s16(a, b, c, d)                                     \
++#define vmlsl_laneq_s16(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+        int16x8_t c_ = (c);                                              \
+        int16x4_t b_ = (b);                                              \
+        int32x4_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("smlal %0.4s, %2.4h, %3.h[%4]"                          \
++       __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_laneq_s32(a, b, c, d)                                     \
++#define vmlsl_laneq_s32(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+        int32x4_t c_ = (c);                                              \
+        int32x2_t b_ = (b);                                              \
+        int64x2_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("smlal %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_laneq_u16(a, b, c, d)                                     \
++#define vmlsl_laneq_u16(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+        uint16x8_t c_ = (c);                                             \
+        uint16x4_t b_ = (b);                                             \
+        uint32x4_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("umlal %0.4s, %2.4h, %3.h[%4]"                          \
++       __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlal_laneq_u32(a, b, c, d)                                     \
++#define vmlsl_laneq_u32(a, b, c, d)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+        uint32x4_t c_ = (c);                                             \
+        uint32x2_t b_ = (b);                                             \
+        uint64x2_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("umlal %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]"                          \
+                 : "=w"(result)                                          \
+                 : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlal_n_s16 (int32x4_t a, int16x4_t b, int16_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_n_s16 (int32x4_t a, int16x4_t b, int16_t c)
+ {
+   int32x4_t result;
+-  __asm__ ("smlal %0.4s,%2.4h,%3.h[0]"
++  __asm__ ("smlsl %0.4s, %2.4h, %3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlal_n_s32 (int64x2_t a, int32x2_t b, int32_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_n_s32 (int64x2_t a, int32x2_t b, int32_t c)
+ {
+   int64x2_t result;
+-  __asm__ ("smlal %0.2d,%2.2s,%3.s[0]"
++  __asm__ ("smlsl %0.2d, %2.2s, %3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlal_n_u16 (uint32x4_t a, uint16x4_t b, uint16_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_n_u16 (uint32x4_t a, uint16x4_t b, uint16_t c)
+ {
+   uint32x4_t result;
+-  __asm__ ("umlal %0.4s,%2.4h,%3.h[0]"
++  __asm__ ("umlsl %0.4s, %2.4h, %3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlal_n_u32 (uint64x2_t a, uint32x2_t b, uint32_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_n_u32 (uint64x2_t a, uint32x2_t b, uint32_t c)
+ {
+   uint64x2_t result;
+-  __asm__ ("umlal %0.2d,%2.2s,%3.s[0]"
++  __asm__ ("umlsl %0.2d, %2.2s, %3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlal_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
+ {
+   int16x8_t result;
+-  __asm__ ("smlal %0.8h,%2.8b,%3.8b"
++  __asm__ ("smlsl %0.8h, %2.8b, %3.8b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+ {
+   int32x4_t result;
+-  __asm__ ("smlal %0.4s,%2.4h,%3.4h"
++  __asm__ ("smlsl %0.4s, %2.4h, %3.4h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
+ {
+   int64x2_t result;
+-  __asm__ ("smlal %0.2d,%2.2s,%3.2s"
++  __asm__ ("smlsl %0.2d, %2.2s, %3.2s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
+ {
+   uint16x8_t result;
+-  __asm__ ("umlal %0.8h,%2.8b,%3.8b"
++  __asm__ ("umlsl %0.8h, %2.8b, %3.8b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
+ {
+   uint32x4_t result;
+-  __asm__ ("umlal %0.4s,%2.4h,%3.4h"
++  __asm__ ("umlsl %0.4s, %2.4h, %3.4h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsl_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
+ {
+   uint64x2_t result;
+-  __asm__ ("umlal %0.2d,%2.2s,%3.2s"
++  __asm__ ("umlsl %0.2d, %2.2s, %3.2s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlaq_n_f32 (float32x4_t a, float32x4_t b, float32_t c)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_n_f32 (float32x4_t a, float32x4_t b, float32_t c)
+ {
+   float32x4_t result;
+   float32x4_t t1;
+-  __asm__ ("fmul %1.4s, %3.4s, %4.s[0]; fadd %0.4s, %0.4s, %1.4s"
++  __asm__ ("fmul %1.4s, %3.4s, %4.s[0]; fsub %0.4s, %0.4s, %1.4s"
+            : "=w"(result), "=w"(t1)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlaq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)
+ {
+   int16x8_t result;
+-  __asm__ ("mla %0.8h,%2.8h,%3.h[0]"
++  __asm__ ("mls %0.8h, %2.8h, %3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlaq_n_s32 (int32x4_t a, int32x4_t b, int32_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_n_s32 (int32x4_t a, int32x4_t b, int32_t c)
+ {
+   int32x4_t result;
+-  __asm__ ("mla %0.4s,%2.4s,%3.s[0]"
++  __asm__ ("mls %0.4s, %2.4s, %3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlaq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c)
+ {
+   uint16x8_t result;
+-  __asm__ ("mla %0.8h,%2.8h,%3.h[0]"
++  __asm__ ("mls %0.8h, %2.8h, %3.h[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "x"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlaq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c)
+ {
+   uint32x4_t result;
+-  __asm__ ("mla %0.4s,%2.4s,%3.s[0]"
++  __asm__ ("mls %0.4s, %2.4s, %3.s[0]"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vmlaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
+ {
+   int8x16_t result;
+-  __asm__ ("mla %0.16b, %2.16b, %3.16b"
++  __asm__ ("mls %0.16b,%2.16b,%3.16b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
+ {
+   int16x8_t result;
+-  __asm__ ("mla %0.8h, %2.8h, %3.8h"
++  __asm__ ("mls %0.8h,%2.8h,%3.8h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
+ {
+   int32x4_t result;
+-  __asm__ ("mla %0.4s, %2.4s, %3.4s"
++  __asm__ ("mls %0.4s,%2.4s,%3.4s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vmlaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ {
+   uint8x16_t result;
+-  __asm__ ("mla %0.16b, %2.16b, %3.16b"
++  __asm__ ("mls %0.16b,%2.16b,%3.16b"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ {
+   uint16x8_t result;
+-  __asm__ ("mla %0.8h, %2.8h, %3.8h"
++  __asm__ ("mls %0.8h,%2.8h,%3.8h"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ {
+   uint32x4_t result;
+-  __asm__ ("mla %0.4s, %2.4s, %3.4s"
++  __asm__ ("mls %0.4s,%2.4s,%3.4s"
+            : "=w"(result)
+            : "0"(a), "w"(b), "w"(c)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmls_n_f32 (float32x2_t a, float32x2_t b, float32_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_high_s8 (int8x16_t a)
+ {
+-  float32x2_t result;
+-  float32x2_t t1;
+-  __asm__ ("fmul %1.2s, %3.2s, %4.s[0]; fsub %0.2s, %0.2s, %1.2s"
+-           : "=w"(result), "=w"(t1)
+-           : "0"(a), "w"(b), "w"(c)
++  int16x8_t result;
++  __asm__ ("sshll2 %0.8h,%1.16b,#0"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmls_n_s16 (int16x4_t a, int16x4_t b, int16_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_high_s16 (int16x8_t a)
+ {
+-  int16x4_t result;
+-  __asm__ ("mls %0.4h, %2.4h, %3.h[0]"
++  int32x4_t result;
++  __asm__ ("sshll2 %0.4s,%1.8h,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmls_n_s32 (int32x2_t a, int32x2_t b, int32_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_high_s32 (int32x4_t a)
+ {
+-  int32x2_t result;
+-  __asm__ ("mls %0.2s, %2.2s, %3.s[0]"
++  int64x2_t result;
++  __asm__ ("sshll2 %0.2d,%1.4s,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmls_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_high_u8 (uint8x16_t a)
+ {
+-  uint16x4_t result;
+-  __asm__ ("mls %0.4h, %2.4h, %3.h[0]"
++  uint16x8_t result;
++  __asm__ ("ushll2 %0.8h,%1.16b,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmls_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_high_u16 (uint16x8_t a)
+ {
+-  uint32x2_t result;
+-  __asm__ ("mls %0.2s, %2.2s, %3.s[0]"
++  uint32x4_t result;
++  __asm__ ("ushll2 %0.4s,%1.8h,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmls_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_high_u32 (uint32x4_t a)
+ {
+-  int8x8_t result;
+-  __asm__ ("mls %0.8b,%2.8b,%3.8b"
++  uint64x2_t result;
++  __asm__ ("ushll2 %0.2d,%1.4s,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmls_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_s8 (int8x8_t a)
+ {
+-  int16x4_t result;
+-  __asm__ ("mls %0.4h,%2.4h,%3.4h"
++  int16x8_t result;
++  __asm__ ("sshll %0.8h,%1.8b,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmls_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_s16 (int16x4_t a)
+ {
+-  int32x2_t result;
+-  __asm__ ("mls %0.2s,%2.2s,%3.2s"
++  int32x4_t result;
++  __asm__ ("sshll %0.4s,%1.4h,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmls_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_s32 (int32x2_t a)
+ {
+-  uint8x8_t result;
+-  __asm__ ("mls %0.8b,%2.8b,%3.8b"
++  int64x2_t result;
++  __asm__ ("sshll %0.2d,%1.2s,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmls_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_u8 (uint8x8_t a)
+ {
+-  uint16x4_t result;
+-  __asm__ ("mls %0.4h,%2.4h,%3.4h"
++  uint16x8_t result;
++  __asm__ ("ushll %0.8h,%1.8b,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmls_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_u16 (uint16x4_t a)
+ {
+-  uint32x2_t result;
+-  __asm__ ("mls %0.2s,%2.2s,%3.2s"
++  uint32x4_t result;
++  __asm__ ("ushll %0.4s,%1.4h,#0"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-#define vmlsl_high_lane_s16(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x4_t c_ = (c);                                              \
+-       int16x8_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovl_u32 (uint32x2_t a)
++{
++  uint64x2_t result;
++  __asm__ ("ushll %0.2d,%1.2s,#0"
++           : "=w"(result)
++           : "w"(a)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlsl_high_lane_s32(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x2_t c_ = (c);                                              \
+-       int32x4_t b_ = (b);                                              \
+-       int64x2_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_high_s16 (int8x8_t a, int16x8_t b)
++{
++  int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("xtn2 %0.16b,%1.8h"
++           : "+w"(result)
++           : "w"(b)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlsl_high_lane_u16(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x4_t c_ = (c);                                             \
+-       uint16x8_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_high_s32 (int16x4_t a, int32x4_t b)
++{
++  int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("xtn2 %0.8h,%1.4s"
++           : "+w"(result)
++           : "w"(b)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlsl_high_lane_u32(a, b, c, d)                                 \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x2_t c_ = (c);                                             \
+-       uint32x4_t b_ = (b);                                             \
+-       uint64x2_t a_ = (a);                                             \
+-       uint64x2_t result;                                               \
+-       __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_high_s64 (int32x2_t a, int64x2_t b)
++{
++  int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("xtn2 %0.4s,%1.2d"
++           : "+w"(result)
++           : "w"(b)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlsl_high_laneq_s16(a, b, c, d)                                \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t c_ = (c);                                              \
+-       int16x8_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_high_u16 (uint8x8_t a, uint16x8_t b)
++{
++  uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("xtn2 %0.16b,%1.8h"
++           : "+w"(result)
++           : "w"(b)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmlsl_high_laneq_s32(a, b, c, d)                                \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t c_ = (c);                                              \
+-       int32x4_t b_ = (b);                                              \
+-       int64x2_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmlsl_high_laneq_u16(a, b, c, d)                                \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t c_ = (c);                                             \
+-       uint16x8_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmlsl_high_laneq_u32(a, b, c, d)                                \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t c_ = (c);                                             \
+-       uint32x4_t b_ = (b);                                             \
+-       uint64x2_t a_ = (a);                                             \
+-       uint64x2_t result;                                               \
+-       __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[%4]"                         \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsl_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c)
+-{
+-  int32x4_t result;
+-  __asm__ ("smlsl2 %0.4s, %2.8h, %3.h[0]"
+-           : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlsl_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c)
+-{
+-  int64x2_t result;
+-  __asm__ ("smlsl2 %0.2d, %2.4s, %3.s[0]"
+-           : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsl_high_n_u16 (uint32x4_t a, uint16x8_t b, uint16_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_high_u32 (uint16x4_t a, uint32x4_t b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("umlsl2 %0.4s, %2.8h, %3.h[0]"
+-           : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++  uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("xtn2 %0.8h,%1.4s"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlsl_high_n_u32 (uint64x2_t a, uint32x4_t b, uint32_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_high_u64 (uint32x2_t a, uint64x2_t b)
+ {
+-  uint64x2_t result;
+-  __asm__ ("umlsl2 %0.2d, %2.4s, %3.s[0]"
+-           : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++  uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("xtn2 %0.4s,%1.2d"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlsl_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_s16 (int16x8_t a)
+ {
+-  int16x8_t result;
+-  __asm__ ("smlsl2 %0.8h,%2.16b,%3.16b"
++  int8x8_t result;
++  __asm__ ("xtn %0.8b,%1.8h"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsl_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_s32 (int32x4_t a)
+ {
+-  int32x4_t result;
+-  __asm__ ("smlsl2 %0.4s,%2.8h,%3.8h"
++  int16x4_t result;
++  __asm__ ("xtn %0.4h,%1.4s"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlsl_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_s64 (int64x2_t a)
+ {
+-  int64x2_t result;
+-  __asm__ ("smlsl2 %0.2d,%2.4s,%3.4s"
++  int32x2_t result;
++  __asm__ ("xtn %0.2s,%1.2d"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlsl_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_u16 (uint16x8_t a)
+ {
+-  uint16x8_t result;
+-  __asm__ ("umlsl2 %0.8h,%2.16b,%3.16b"
++  uint8x8_t result;
++  __asm__ ("xtn %0.8b,%1.8h"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsl_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_u32 (uint32x4_t a)
+ {
+-  uint32x4_t result;
+-  __asm__ ("umlsl2 %0.4s,%2.8h,%3.8h"
++  uint16x4_t result;
++  __asm__ ("xtn %0.4h,%1.4s"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlsl_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovn_u64 (uint64x2_t a)
+ {
+-  uint64x2_t result;
+-  __asm__ ("umlsl2 %0.2d,%2.4s,%3.4s"
++  uint32x2_t result;
++  __asm__ ("xtn %0.2s,%1.2d"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-#define vmlsl_lane_s16(a, b, c, d)                                      \
++#define vmull_high_lane_s16(a, b, c)                                    \
+   __extension__                                                         \
+     ({                                                                  \
+-       int16x4_t c_ = (c);                                              \
+        int16x4_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
++       int16x8_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]"                          \
++       __asm__ ("smull2 %0.4s, %1.8h, %2.h[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
++                : "w"(a_), "x"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_lane_s32(a, b, c, d)                                      \
++#define vmull_high_lane_s32(a, b, c)                                    \
+   __extension__                                                         \
+     ({                                                                  \
+-       int32x2_t c_ = (c);                                              \
+        int32x2_t b_ = (b);                                              \
+-       int64x2_t a_ = (a);                                              \
++       int32x4_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("smull2 %0.2d, %1.4s, %2.s[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
++                : "w"(a_), "w"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_lane_u16(a, b, c, d)                                      \
++#define vmull_high_lane_u16(a, b, c)                                    \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint16x4_t c_ = (c);                                             \
+        uint16x4_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
++       uint16x8_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]"                          \
++       __asm__ ("umull2 %0.4s, %1.8h, %2.h[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
++                : "w"(a_), "x"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_lane_u32(a, b, c, d)                                      \
++#define vmull_high_lane_u32(a, b, c)                                    \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint32x2_t c_ = (c);                                             \
+        uint32x2_t b_ = (b);                                             \
+-       uint64x2_t a_ = (a);                                             \
++       uint32x4_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("umull2 %0.2d, %1.4s, %2.s[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
++                : "w"(a_), "w"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_laneq_s16(a, b, c, d)                                     \
++#define vmull_high_laneq_s16(a, b, c)                                   \
+   __extension__                                                         \
+     ({                                                                  \
+-       int16x8_t c_ = (c);                                              \
+-       int16x4_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
++       int16x8_t b_ = (b);                                              \
++       int16x8_t a_ = (a);                                              \
+        int32x4_t result;                                                \
+-       __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]"                          \
++       __asm__ ("smull2 %0.4s, %1.8h, %2.h[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
++                : "w"(a_), "x"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_laneq_s32(a, b, c, d)                                     \
++#define vmull_high_laneq_s32(a, b, c)                                   \
+   __extension__                                                         \
+     ({                                                                  \
+-       int32x4_t c_ = (c);                                              \
+-       int32x2_t b_ = (b);                                              \
+-       int64x2_t a_ = (a);                                              \
++       int32x4_t b_ = (b);                                              \
++       int32x4_t a_ = (a);                                              \
+        int64x2_t result;                                                \
+-       __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("smull2 %0.2d, %1.4s, %2.s[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
++                : "w"(a_), "w"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_laneq_u16(a, b, c, d)                                     \
++#define vmull_high_laneq_u16(a, b, c)                                   \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint16x8_t c_ = (c);                                             \
+-       uint16x4_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
++       uint16x8_t b_ = (b);                                             \
++       uint16x8_t a_ = (a);                                             \
+        uint32x4_t result;                                               \
+-       __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]"                          \
++       __asm__ ("umull2 %0.4s, %1.8h, %2.h[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "x"(c_), "i"(d)                     \
++                : "w"(a_), "x"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmlsl_laneq_u32(a, b, c, d)                                     \
++#define vmull_high_laneq_u32(a, b, c)                                   \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint32x4_t c_ = (c);                                             \
+-       uint32x2_t b_ = (b);                                             \
+-       uint64x2_t a_ = (a);                                             \
++       uint32x4_t b_ = (b);                                             \
++       uint32x4_t a_ = (a);                                             \
+        uint64x2_t result;                                               \
+-       __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]"                          \
++       __asm__ ("umull2 %0.2d, %1.4s, %2.s[%3]"                         \
+                 : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "w"(c_), "i"(d)                     \
++                : "w"(a_), "w"(b_), "i"(c)                              \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsl_n_s16 (int32x4_t a, int16x4_t b, int16_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_n_s16 (int16x8_t a, int16_t b)
+ {
+   int32x4_t result;
+-  __asm__ ("smlsl %0.4s, %2.4h, %3.h[0]"
++  __asm__ ("smull2 %0.4s,%1.8h,%2.h[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++           : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlsl_n_s32 (int64x2_t a, int32x2_t b, int32_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_n_s32 (int32x4_t a, int32_t b)
+ {
+   int64x2_t result;
+-  __asm__ ("smlsl %0.2d, %2.2s, %3.s[0]"
++  __asm__ ("smull2 %0.2d,%1.4s,%2.s[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsl_n_u16 (uint32x4_t a, uint16x4_t b, uint16_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_n_u16 (uint16x8_t a, uint16_t b)
+ {
+   uint32x4_t result;
+-  __asm__ ("umlsl %0.4s, %2.4h, %3.h[0]"
++  __asm__ ("umull2 %0.4s,%1.8h,%2.h[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++           : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlsl_n_u32 (uint64x2_t a, uint32x2_t b, uint32_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_n_u32 (uint32x4_t a, uint32_t b)
+ {
+   uint64x2_t result;
+-  __asm__ ("umlsl %0.2d, %2.2s, %3.s[0]"
++  __asm__ ("umull2 %0.2d,%1.4s,%2.s[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlsl_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_p8 (poly8x16_t a, poly8x16_t b)
+ {
+-  int16x8_t result;
+-  __asm__ ("smlsl %0.8h, %2.8b, %3.8b"
++  poly16x8_t result;
++  __asm__ ("pmull2 %0.8h,%1.16b,%2.16b"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsl_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_s8 (int8x16_t a, int8x16_t b)
+ {
+-  int32x4_t result;
+-  __asm__ ("smlsl %0.4s, %2.4h, %3.4h"
++  int16x8_t result;
++  __asm__ ("smull2 %0.8h,%1.16b,%2.16b"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmlsl_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_s16 (int16x8_t a, int16x8_t b)
+ {
+-  int64x2_t result;
+-  __asm__ ("smlsl %0.2d, %2.2s, %3.2s"
++  int32x4_t result;
++  __asm__ ("smull2 %0.4s,%1.8h,%2.8h"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlsl_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_s32 (int32x4_t a, int32x4_t b)
+ {
+-  uint16x8_t result;
+-  __asm__ ("umlsl %0.8h, %2.8b, %3.8b"
++  int64x2_t result;
++  __asm__ ("smull2 %0.2d,%1.4s,%2.4s"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsl_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_u8 (uint8x16_t a, uint8x16_t b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("umlsl %0.4s, %2.4h, %3.4h"
++  uint16x8_t result;
++  __asm__ ("umull2 %0.8h,%1.16b,%2.16b"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmlsl_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_u16 (uint16x8_t a, uint16x8_t b)
+ {
+-  uint64x2_t result;
+-  __asm__ ("umlsl %0.2d, %2.2s, %3.2s"
++  uint32x4_t result;
++  __asm__ ("umull2 %0.4s,%1.8h,%2.8h"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlsq_n_f32 (float32x4_t a, float32x4_t b, float32_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_u32 (uint32x4_t a, uint32x4_t b)
+ {
+-  float32x4_t result;
+-  float32x4_t t1;
+-  __asm__ ("fmul %1.4s, %3.4s, %4.s[0]; fsub %0.4s, %0.4s, %1.4s"
+-           : "=w"(result), "=w"(t1)
+-           : "0"(a), "w"(b), "w"(c)
++  uint64x2_t result;
++  __asm__ ("umull2 %0.2d,%1.4s,%2.4s"
++           : "=w"(result)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlsq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)
++#define vmull_lane_s16(a, b, c)                                         \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x4_t b_ = (b);                                              \
++       int16x4_t a_ = (a);                                              \
++       int32x4_t result;                                                \
++       __asm__ ("smull %0.4s,%1.4h,%2.h[%3]"                            \
++                : "=w"(result)                                          \
++                : "w"(a_), "x"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_lane_s32(a, b, c)                                         \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x2_t b_ = (b);                                              \
++       int32x2_t a_ = (a);                                              \
++       int64x2_t result;                                                \
++       __asm__ ("smull %0.2d,%1.2s,%2.s[%3]"                            \
++                : "=w"(result)                                          \
++                : "w"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_lane_u16(a, b, c)                                         \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x4_t b_ = (b);                                             \
++       uint16x4_t a_ = (a);                                             \
++       uint32x4_t result;                                               \
++       __asm__ ("umull %0.4s,%1.4h,%2.h[%3]"                            \
++                : "=w"(result)                                          \
++                : "w"(a_), "x"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_lane_u32(a, b, c)                                         \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x2_t b_ = (b);                                             \
++       uint32x2_t a_ = (a);                                             \
++       uint64x2_t result;                                               \
++       __asm__ ("umull %0.2d, %1.2s, %2.s[%3]"                          \
++                : "=w"(result)                                          \
++                : "w"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_laneq_s16(a, b, c)                                        \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t b_ = (b);                                              \
++       int16x4_t a_ = (a);                                              \
++       int32x4_t result;                                                \
++       __asm__ ("smull %0.4s, %1.4h, %2.h[%3]"                          \
++                : "=w"(result)                                          \
++                : "w"(a_), "x"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_laneq_s32(a, b, c)                                        \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t b_ = (b);                                              \
++       int32x2_t a_ = (a);                                              \
++       int64x2_t result;                                                \
++       __asm__ ("smull %0.2d, %1.2s, %2.s[%3]"                          \
++                : "=w"(result)                                          \
++                : "w"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_laneq_u16(a, b, c)                                        \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x8_t b_ = (b);                                             \
++       uint16x4_t a_ = (a);                                             \
++       uint32x4_t result;                                               \
++       __asm__ ("umull %0.4s, %1.4h, %2.h[%3]"                          \
++                : "=w"(result)                                          \
++                : "w"(a_), "x"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vmull_laneq_u32(a, b, c)                                        \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x4_t b_ = (b);                                             \
++       uint32x2_t a_ = (a);                                             \
++       uint64x2_t result;                                               \
++       __asm__ ("umull %0.2d, %1.2s, %2.s[%3]"                          \
++                : "=w"(result)                                          \
++                : "w"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_n_s16 (int16x4_t a, int16_t b)
+ {
+-  int16x8_t result;
+-  __asm__ ("mls %0.8h, %2.8h, %3.h[0]"
++  int32x4_t result;
++  __asm__ ("smull %0.4s,%1.4h,%2.h[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++           : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsq_n_s32 (int32x4_t a, int32x4_t b, int32_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_n_s32 (int32x2_t a, int32_t b)
+ {
+-  int32x4_t result;
+-  __asm__ ("mls %0.4s, %2.4s, %3.s[0]"
++  int64x2_t result;
++  __asm__ ("smull %0.2d,%1.2s,%2.s[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlsq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_n_u16 (uint16x4_t a, uint16_t b)
+ {
+-  uint16x8_t result;
+-  __asm__ ("mls %0.8h, %2.8h, %3.h[0]"
++  uint32x4_t result;
++  __asm__ ("umull %0.4s,%1.4h,%2.h[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "x"(c)
++           : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_n_u32 (uint32x2_t a, uint32_t b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("mls %0.4s, %2.4s, %3.s[0]"
++  uint64x2_t result;
++  __asm__ ("umull %0.2d,%1.2s,%2.s[0]"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vmlsq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_p8 (poly8x8_t a, poly8x8_t b)
+ {
+-  int8x16_t result;
+-  __asm__ ("mls %0.16b,%2.16b,%3.16b"
++  poly16x8_t result;
++  __asm__ ("pmull %0.8h, %1.8b, %2.8b"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlsq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_s8 (int8x8_t a, int8x8_t b)
+ {
+   int16x8_t result;
+-  __asm__ ("mls %0.8h,%2.8h,%3.8h"
++  __asm__ ("smull %0.8h, %1.8b, %2.8b"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_s16 (int16x4_t a, int16x4_t b)
+ {
+   int32x4_t result;
+-  __asm__ ("mls %0.4s,%2.4s,%3.4s"
++  __asm__ ("smull %0.4s, %1.4h, %2.4h"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vmlsq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_s32 (int32x2_t a, int32x2_t b)
+ {
+-  uint8x16_t result;
+-  __asm__ ("mls %0.16b,%2.16b,%3.16b"
++  int64x2_t result;
++  __asm__ ("smull %0.2d, %1.2s, %2.2s"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlsq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_u8 (uint8x8_t a, uint8x8_t b)
+ {
+   uint16x8_t result;
+-  __asm__ ("mls %0.8h,%2.8h,%3.8h"
++  __asm__ ("umull %0.8h, %1.8b, %2.8b"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_u16 (uint16x4_t a, uint16x4_t b)
+ {
+   uint32x4_t result;
+-  __asm__ ("mls %0.4s,%2.4s,%3.4s"
++  __asm__ ("umull %0.4s, %1.4h, %2.4h"
+            : "=w"(result)
+-           : "0"(a), "w"(b), "w"(c)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmovl_high_s8 (int8x16_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_u32 (uint32x2_t a, uint32x2_t b)
+ {
+-  int16x8_t result;
+-  __asm__ ("sshll2 %0.8h,%1.16b,#0"
++  uint64x2_t result;
++  __asm__ ("umull %0.2d, %1.2s, %2.2s"
+            : "=w"(result)
+-           : "w"(a)
++           : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmovl_high_s16 (int16x8_t a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadal_s8 (int16x4_t a, int8x8_t b)
+ {
+-  int32x4_t result;
+-  __asm__ ("sshll2 %0.4s,%1.8h,#0"
++  int16x4_t result;
++  __asm__ ("sadalp %0.4h,%2.8b"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmovl_high_s32 (int32x4_t a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadal_s16 (int32x2_t a, int16x4_t b)
+ {
+-  int64x2_t result;
+-  __asm__ ("sshll2 %0.2d,%1.4s,#0"
++  int32x2_t result;
++  __asm__ ("sadalp %0.2s,%2.4h"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmovl_high_u8 (uint8x16_t a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadal_s32 (int64x1_t a, int32x2_t b)
+ {
+-  uint16x8_t result;
+-  __asm__ ("ushll2 %0.8h,%1.16b,#0"
++  int64x1_t result;
++  __asm__ ("sadalp %0.1d,%2.2s"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmovl_high_u16 (uint16x8_t a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadal_u8 (uint16x4_t a, uint8x8_t b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("ushll2 %0.4s,%1.8h,#0"
++  uint16x4_t result;
++  __asm__ ("uadalp %0.4h,%2.8b"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmovl_high_u32 (uint32x4_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadal_u16 (uint32x2_t a, uint16x4_t b)
+ {
+-  uint64x2_t result;
+-  __asm__ ("ushll2 %0.2d,%1.4s,#0"
++  uint32x2_t result;
++  __asm__ ("uadalp %0.2s,%2.4h"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmovl_s8 (int8x8_t a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadal_u32 (uint64x1_t a, uint32x2_t b)
++{
++  uint64x1_t result;
++  __asm__ ("uadalp %0.1d,%2.2s"
++           : "=w"(result)
++           : "0"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadalq_s8 (int16x8_t a, int8x16_t b)
+ {
+   int16x8_t result;
+-  __asm__ ("sshll %0.8h,%1.8b,#0"
++  __asm__ ("sadalp %0.8h,%2.16b"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmovl_s16 (int16x4_t a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadalq_s16 (int32x4_t a, int16x8_t b)
+ {
+   int32x4_t result;
+-  __asm__ ("sshll %0.4s,%1.4h,#0"
++  __asm__ ("sadalp %0.4s,%2.8h"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmovl_s32 (int32x2_t a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadalq_s32 (int64x2_t a, int32x4_t b)
+ {
+   int64x2_t result;
+-  __asm__ ("sshll %0.2d,%1.2s,#0"
++  __asm__ ("sadalp %0.2d,%2.4s"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmovl_u8 (uint8x8_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadalq_u8 (uint16x8_t a, uint8x16_t b)
+ {
+   uint16x8_t result;
+-  __asm__ ("ushll %0.8h,%1.8b,#0"
++  __asm__ ("uadalp %0.8h,%2.16b"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmovl_u16 (uint16x4_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadalq_u16 (uint32x4_t a, uint16x8_t b)
+ {
+   uint32x4_t result;
+-  __asm__ ("ushll %0.4s,%1.4h,#0"
++  __asm__ ("uadalp %0.4s,%2.8h"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmovl_u32 (uint32x2_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadalq_u32 (uint64x2_t a, uint32x4_t b)
+ {
+   uint64x2_t result;
+-  __asm__ ("ushll %0.2d,%1.2s,#0"
++  __asm__ ("uadalp %0.2d,%2.4s"
+            : "=w"(result)
+-           : "w"(a)
++           : "0"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vmovn_high_s16 (int8x8_t a, int16x8_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddl_s8 (int8x8_t a)
+ {
+-  int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("xtn2 %0.16b,%1.8h"
+-           : "+w"(result)
+-           : "w"(b)
++  int16x4_t result;
++  __asm__ ("saddlp %0.4h,%1.8b"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmovn_high_s32 (int16x4_t a, int32x4_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddl_s16 (int16x4_t a)
+ {
+-  int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("xtn2 %0.8h,%1.4s"
+-           : "+w"(result)
+-           : "w"(b)
++  int32x2_t result;
++  __asm__ ("saddlp %0.2s,%1.4h"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmovn_high_s64 (int32x2_t a, int64x2_t b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddl_s32 (int32x2_t a)
+ {
+-  int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("xtn2 %0.4s,%1.2d"
+-           : "+w"(result)
+-           : "w"(b)
++  int64x1_t result;
++  __asm__ ("saddlp %0.1d,%1.2s"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vmovn_high_u16 (uint8x8_t a, uint16x8_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddl_u8 (uint8x8_t a)
+ {
+-  uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("xtn2 %0.16b,%1.8h"
+-           : "+w"(result)
+-           : "w"(b)
++  uint16x4_t result;
++  __asm__ ("uaddlp %0.4h,%1.8b"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmovn_high_u32 (uint16x4_t a, uint32x4_t b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddl_u16 (uint16x4_t a)
+ {
+-  uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("xtn2 %0.8h,%1.4s"
+-           : "+w"(result)
+-           : "w"(b)
++  uint32x2_t result;
++  __asm__ ("uaddlp %0.2s,%1.4h"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmovn_high_u64 (uint32x2_t a, uint64x2_t b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddl_u32 (uint32x2_t a)
+ {
+-  uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("xtn2 %0.4s,%1.2d"
+-           : "+w"(result)
+-           : "w"(b)
++  uint64x1_t result;
++  __asm__ ("uaddlp %0.1d,%1.2s"
++           : "=w"(result)
++           : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmovn_s16 (int16x8_t a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddlq_s8 (int8x16_t a)
+ {
+-  int8x8_t result;
+-  __asm__ ("xtn %0.8b,%1.8h"
++  int16x8_t result;
++  __asm__ ("saddlp %0.8h,%1.16b"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmovn_s32 (int32x4_t a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddlq_s16 (int16x8_t a)
+ {
+-  int16x4_t result;
+-  __asm__ ("xtn %0.4h,%1.4s"
++  int32x4_t result;
++  __asm__ ("saddlp %0.4s,%1.8h"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmovn_s64 (int64x2_t a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddlq_s32 (int32x4_t a)
+ {
+-  int32x2_t result;
+-  __asm__ ("xtn %0.2s,%1.2d"
++  int64x2_t result;
++  __asm__ ("saddlp %0.2d,%1.4s"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmovn_u16 (uint16x8_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddlq_u8 (uint8x16_t a)
+ {
+-  uint8x8_t result;
+-  __asm__ ("xtn %0.8b,%1.8h"
++  uint16x8_t result;
++  __asm__ ("uaddlp %0.8h,%1.16b"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmovn_u32 (uint32x4_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddlq_u16 (uint16x8_t a)
+ {
+-  uint16x4_t result;
+-  __asm__ ("xtn %0.4h,%1.4s"
++  uint32x4_t result;
++  __asm__ ("uaddlp %0.4s,%1.8h"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmovn_u64 (uint64x2_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddlq_u32 (uint32x4_t a)
+ {
+-  uint32x2_t result;
+-  __asm__ ("xtn %0.2s,%1.2d"
++  uint64x2_t result;
++  __asm__ ("uaddlp %0.2d,%1.4s"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmul_n_f32 (float32x2_t a, float32_t b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_s8 (int8x16_t a, int8x16_t b)
+ {
+-  float32x2_t result;
+-  __asm__ ("fmul %0.2s,%1.2s,%2.s[0]"
++  int8x16_t result;
++  __asm__ ("addp %0.16b,%1.16b,%2.16b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_s16 (int16x8_t a, int16x8_t b)
++{
++  int16x8_t result;
++  __asm__ ("addp %0.8h,%1.8h,%2.8h"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_s32 (int32x4_t a, int32x4_t b)
++{
++  int32x4_t result;
++  __asm__ ("addp %0.4s,%1.4s,%2.4s"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_s64 (int64x2_t a, int64x2_t b)
++{
++  int64x2_t result;
++  __asm__ ("addp %0.2d,%1.2d,%2.2d"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_u8 (uint8x16_t a, uint8x16_t b)
++{
++  uint8x16_t result;
++  __asm__ ("addp %0.16b,%1.16b,%2.16b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_u16 (uint16x8_t a, uint16x8_t b)
++{
++  uint16x8_t result;
++  __asm__ ("addp %0.8h,%1.8h,%2.8h"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_u32 (uint32x4_t a, uint32x4_t b)
++{
++  uint32x4_t result;
++  __asm__ ("addp %0.4s,%1.4s,%2.4s"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_u64 (uint64x2_t a, uint64x2_t b)
++{
++  uint64x2_t result;
++  __asm__ ("addp %0.2d,%1.2d,%2.2d"
+            : "=w"(result)
+            : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmul_n_s16 (int16x4_t a, int16_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulh_n_s16 (int16x4_t a, int16_t b)
+ {
+   int16x4_t result;
+-  __asm__ ("mul %0.4h,%1.4h,%2.h[0]"
++  __asm__ ("sqdmulh %0.4h,%1.4h,%2.h[0]"
+            : "=w"(result)
+            : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmul_n_s32 (int32x2_t a, int32_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulh_n_s32 (int32x2_t a, int32_t b)
+ {
+   int32x2_t result;
+-  __asm__ ("mul %0.2s,%1.2s,%2.s[0]"
++  __asm__ ("sqdmulh %0.2s,%1.2s,%2.s[0]"
+            : "=w"(result)
+            : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmul_n_u16 (uint16x4_t a, uint16_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhq_n_s16 (int16x8_t a, int16_t b)
+ {
+-  uint16x4_t result;
+-  __asm__ ("mul %0.4h,%1.4h,%2.h[0]"
++  int16x8_t result;
++  __asm__ ("sqdmulh %0.8h,%1.8h,%2.h[0]"
+            : "=w"(result)
+            : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmul_n_u32 (uint32x2_t a, uint32_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhq_n_s32 (int32x4_t a, int32_t b)
+ {
+-  uint32x2_t result;
+-  __asm__ ("mul %0.2s,%1.2s,%2.s[0]"
++  int32x4_t result;
++  __asm__ ("sqdmulh %0.4s,%1.4s,%2.s[0]"
+            : "=w"(result)
+            : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-#define vmull_high_lane_s16(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x4_t b_ = (b);                                              \
+-       int16x8_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smull2 %0.4s, %1.8h, %2.h[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_high_s16 (int8x8_t a, int16x8_t b)
++{
++  int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("sqxtn2 %0.16b, %1.8h"
++           : "+w"(result)
++           : "w"(b)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-#define vmull_high_lane_s32(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x2_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smull2 %0.2d, %1.4s, %2.s[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmull_high_lane_u16(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x4_t b_ = (b);                                             \
+-       uint16x8_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umull2 %0.4s, %1.8h, %2.h[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmull_high_lane_u32(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x2_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
+-       uint64x2_t result;                                               \
+-       __asm__ ("umull2 %0.2d, %1.4s, %2.s[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmull_high_laneq_s16(a, b, c)                                   \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       int16x8_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smull2 %0.4s, %1.8h, %2.h[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmull_high_laneq_s32(a, b, c)                                   \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       int32x4_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smull2 %0.2d, %1.4s, %2.s[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmull_high_laneq_u16(a, b, c)                                   \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t b_ = (b);                                             \
+-       uint16x8_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umull2 %0.4s, %1.8h, %2.h[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vmull_high_laneq_u32(a, b, c)                                   \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t b_ = (b);                                             \
+-       uint32x4_t a_ = (a);                                             \
+-       uint64x2_t result;                                               \
+-       __asm__ ("umull2 %0.2d, %1.4s, %2.s[%3]"                         \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_high_s32 (int16x4_t a, int32x4_t b)
++{
++  int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("sqxtn2 %0.8h, %1.4s"
++           : "+w"(result)
++           : "w"(b)
++           : /* No clobbers */);
++  return result;
++}
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmull_high_n_s16 (int16x8_t a, int16_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_high_s64 (int32x2_t a, int64x2_t b)
+ {
+-  int32x4_t result;
+-  __asm__ ("smull2 %0.4s,%1.8h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
++  int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("sqxtn2 %0.4s, %1.2d"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmull_high_n_s32 (int32x4_t a, int32_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_high_u16 (uint8x8_t a, uint16x8_t b)
+ {
+-  int64x2_t result;
+-  __asm__ ("smull2 %0.2d,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
++  uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("uqxtn2 %0.16b, %1.8h"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmull_high_n_u16 (uint16x8_t a, uint16_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_high_u32 (uint16x4_t a, uint32x4_t b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("umull2 %0.4s,%1.8h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
++  uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("uqxtn2 %0.8h, %1.4s"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmull_high_n_u32 (uint32x4_t a, uint32_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_high_u64 (uint32x2_t a, uint64x2_t b)
+ {
+-  uint64x2_t result;
+-  __asm__ ("umull2 %0.2d,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
++  uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("uqxtn2 %0.4s, %1.2d"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vmull_high_p8 (poly8x16_t a, poly8x16_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovun_high_s16 (uint8x8_t a, int16x8_t b)
+ {
+-  poly16x8_t result;
+-  __asm__ ("pmull2 %0.8h,%1.16b,%2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
++  uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("sqxtun2 %0.16b, %1.8h"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmull_high_s8 (int8x16_t a, int8x16_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovun_high_s32 (uint16x4_t a, int32x4_t b)
+ {
+-  int16x8_t result;
+-  __asm__ ("smull2 %0.8h,%1.16b,%2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
++  uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("sqxtun2 %0.8h, %1.4s"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmull_high_s16 (int16x8_t a, int16x8_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovun_high_s64 (uint32x2_t a, int64x2_t b)
+ {
+-  int32x4_t result;
+-  __asm__ ("smull2 %0.4s,%1.8h,%2.8h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
++  uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("sqxtun2 %0.4s, %1.2d"
++           : "+w"(result)
++           : "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmull_high_s32 (int32x4_t a, int32x4_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulh_n_s16 (int16x4_t a, int16_t b)
+ {
+-  int64x2_t result;
+-  __asm__ ("smull2 %0.2d,%1.4s,%2.4s"
++  int16x4_t result;
++  __asm__ ("sqrdmulh %0.4h,%1.4h,%2.h[0]"
+            : "=w"(result)
+-           : "w"(a), "w"(b)
++           : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmull_high_u8 (uint8x16_t a, uint8x16_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulh_n_s32 (int32x2_t a, int32_t b)
+ {
+-  uint16x8_t result;
+-  __asm__ ("umull2 %0.8h,%1.16b,%2.16b"
++  int32x2_t result;
++  __asm__ ("sqrdmulh %0.2s,%1.2s,%2.s[0]"
+            : "=w"(result)
+            : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmull_high_u16 (uint16x8_t a, uint16x8_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhq_n_s16 (int16x8_t a, int16_t b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("umull2 %0.4s,%1.8h,%2.8h"
++  int16x8_t result;
++  __asm__ ("sqrdmulh %0.8h,%1.8h,%2.h[0]"
+            : "=w"(result)
+-           : "w"(a), "w"(b)
++           : "w"(a), "x"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmull_high_u32 (uint32x4_t a, uint32x4_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhq_n_s32 (int32x4_t a, int32_t b)
+ {
+-  uint64x2_t result;
+-  __asm__ ("umull2 %0.2d,%1.4s,%2.4s"
++  int32x4_t result;
++  __asm__ ("sqrdmulh %0.4s,%1.4s,%2.s[0]"
+            : "=w"(result)
+            : "w"(a), "w"(b)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-#define vmull_lane_s16(a, b, c)                                         \
++#define vqrshrn_high_n_s16(a, b, c)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       int16x4_t b_ = (b);                                              \
++       int16x8_t b_ = (b);                                              \
++       int8x8_t a_ = (a);                                               \
++       int8x16_t result = vcombine_s8                                   \
++                            (a_, vcreate_s8                             \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("sqrshrn2 %0.16b, %1.8h, #%2"                           \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vqrshrn_high_n_s32(a, b, c)                                     \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t b_ = (b);                                              \
+        int16x4_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smull %0.4s,%1.4h,%2.h[%3]"                            \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
++       int16x8_t result = vcombine_s16                                  \
++                            (a_, vcreate_s16                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("sqrshrn2 %0.8h, %1.4s, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_lane_s32(a, b, c)                                         \
++#define vqrshrn_high_n_s64(a, b, c)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       int32x2_t b_ = (b);                                              \
++       int64x2_t b_ = (b);                                              \
+        int32x2_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smull %0.2d,%1.2s,%2.s[%3]"                            \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
++       int32x4_t result = vcombine_s32                                  \
++                            (a_, vcreate_s32                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("sqrshrn2 %0.4s, %1.2d, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_lane_u16(a, b, c)                                         \
++#define vqrshrn_high_n_u16(a, b, c)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint16x4_t b_ = (b);                                             \
+-       uint16x4_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umull %0.4s,%1.4h,%2.h[%3]"                            \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
++       uint16x8_t b_ = (b);                                             \
++       uint8x8_t a_ = (a);                                              \
++       uint8x16_t result = vcombine_u8                                  \
++                             (a_, vcreate_u8                            \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("uqrshrn2 %0.16b, %1.8h, #%2"                           \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_lane_u32(a, b, c)                                         \
++#define vqrshrn_high_n_u32(a, b, c)                                     \
+   __extension__                                                         \
+     ({                                                                  \
+-       uint32x2_t b_ = (b);                                             \
++       uint32x4_t b_ = (b);                                             \
++       uint16x4_t a_ = (a);                                             \
++       uint16x8_t result = vcombine_u16                                 \
++                             (a_, vcreate_u16                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("uqrshrn2 %0.8h, %1.4s, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vqrshrn_high_n_u64(a, b, c)                                     \
++  __extension__                                                         \
++    ({                                                                  \
++       uint64x2_t b_ = (b);                                             \
+        uint32x2_t a_ = (a);                                             \
+-       uint64x2_t result;                                               \
+-       __asm__ ("umull %0.2d, %1.2s, %2.s[%3]"                          \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
++       uint32x4_t result = vcombine_u32                                 \
++                             (a_, vcreate_u32                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("uqrshrn2 %0.4s, %1.2d, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_laneq_s16(a, b, c)                                        \
++#define vqrshrun_high_n_s16(a, b, c)                                    \
+   __extension__                                                         \
+     ({                                                                  \
+        int16x8_t b_ = (b);                                              \
+-       int16x4_t a_ = (a);                                              \
+-       int32x4_t result;                                                \
+-       __asm__ ("smull %0.4s, %1.4h, %2.h[%3]"                          \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
++       uint8x8_t a_ = (a);                                              \
++       uint8x16_t result = vcombine_u8                                  \
++                             (a_, vcreate_u8                            \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("sqrshrun2 %0.16b, %1.8h, #%2"                          \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_laneq_s32(a, b, c)                                        \
++#define vqrshrun_high_n_s32(a, b, c)                                    \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t b_ = (b);                                              \
++       uint16x4_t a_ = (a);                                             \
++       uint16x8_t result = vcombine_u16                                 \
++                             (a_, vcreate_u16                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("sqrshrun2 %0.8h, %1.4s, #%2"                           \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vqrshrun_high_n_s64(a, b, c)                                    \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t b_ = (b);                                              \
++       uint32x2_t a_ = (a);                                             \
++       uint32x4_t result = vcombine_u32                                 \
++                             (a_, vcreate_u32                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("sqrshrun2 %0.4s, %1.2d, #%2"                           \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vqshrn_high_n_s16(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t b_ = (b);                                              \
++       int8x8_t a_ = (a);                                               \
++       int8x16_t result = vcombine_s8                                   \
++                            (a_, vcreate_s8                             \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("sqshrn2 %0.16b, %1.8h, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vqshrn_high_n_s32(a, b, c)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        int32x4_t b_ = (b);                                              \
++       int16x4_t a_ = (a);                                              \
++       int16x8_t result = vcombine_s16                                  \
++                            (a_, vcreate_s16                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("sqshrn2 %0.8h, %1.4s, #%2"                             \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vqshrn_high_n_s64(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t b_ = (b);                                              \
+        int32x2_t a_ = (a);                                              \
+-       int64x2_t result;                                                \
+-       __asm__ ("smull %0.2d, %1.2s, %2.s[%3]"                          \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
++       int32x4_t result = vcombine_s32                                  \
++                            (a_, vcreate_s32                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("sqshrn2 %0.4s, %1.2d, #%2"                             \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_laneq_u16(a, b, c)                                        \
++#define vqshrn_high_n_u16(a, b, c)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        uint16x8_t b_ = (b);                                             \
+-       uint16x4_t a_ = (a);                                             \
+-       uint32x4_t result;                                               \
+-       __asm__ ("umull %0.4s, %1.4h, %2.h[%3]"                          \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "x"(b_), "i"(c)                              \
++       uint8x8_t a_ = (a);                                              \
++       uint8x16_t result = vcombine_u8                                  \
++                             (a_, vcreate_u8                            \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("uqshrn2 %0.16b, %1.8h, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-#define vmull_laneq_u32(a, b, c)                                        \
++#define vqshrn_high_n_u32(a, b, c)                                      \
+   __extension__                                                         \
+     ({                                                                  \
+        uint32x4_t b_ = (b);                                             \
+-       uint32x2_t a_ = (a);                                             \
+-       uint64x2_t result;                                               \
+-       __asm__ ("umull %0.2d, %1.2s, %2.s[%3]"                          \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "w"(b_), "i"(c)                              \
++       uint16x4_t a_ = (a);                                             \
++       uint16x8_t result = vcombine_u16                                 \
++                             (a_, vcreate_u16                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("uqshrn2 %0.8h, %1.4s, #%2"                             \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
+                 : /* No clobbers */);                                   \
+        result;                                                          \
+      })
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmull_n_s16 (int16x4_t a, int16_t b)
+-{
+-  int32x4_t result;
+-  __asm__ ("smull %0.4s,%1.4h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vqshrn_high_n_u64(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       uint64x2_t b_ = (b);                                             \
++       uint32x2_t a_ = (a);                                             \
++       uint32x4_t result = vcombine_u32                                 \
++                             (a_, vcreate_u32                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("uqshrn2 %0.4s, %1.2d, #%2"                             \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmull_n_s32 (int32x2_t a, int32_t b)
+-{
+-  int64x2_t result;
+-  __asm__ ("smull %0.2d,%1.2s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vqshrun_high_n_s16(a, b, c)                                     \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t b_ = (b);                                              \
++       uint8x8_t a_ = (a);                                              \
++       uint8x16_t result = vcombine_u8                                  \
++                             (a_, vcreate_u8                            \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("sqshrun2 %0.16b, %1.8h, #%2"                           \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmull_n_u16 (uint16x4_t a, uint16_t b)
+-{
+-  uint32x4_t result;
+-  __asm__ ("umull %0.4s,%1.4h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vqshrun_high_n_s32(a, b, c)                                     \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t b_ = (b);                                              \
++       uint16x4_t a_ = (a);                                             \
++       uint16x8_t result = vcombine_u16                                 \
++                             (a_, vcreate_u16                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("sqshrun2 %0.8h, %1.4s, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmull_n_u32 (uint32x2_t a, uint32_t b)
+-{
+-  uint64x2_t result;
+-  __asm__ ("umull %0.2d,%1.2s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vqshrun_high_n_s64(a, b, c)                                     \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t b_ = (b);                                              \
++       uint32x2_t a_ = (a);                                             \
++       uint32x4_t result = vcombine_u32                                 \
++                             (a_, vcreate_u32                           \
++                                    (__AARCH64_UINT64_C (0x0)));        \
++       __asm__ ("sqshrun2 %0.4s, %1.2d, #%2"                            \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vmull_p8 (poly8x8_t a, poly8x8_t b)
+-{
+-  poly16x8_t result;
+-  __asm__ ("pmull %0.8h, %1.8b, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_high_n_s16(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t b_ = (b);                                              \
++       int8x8_t a_ = (a);                                               \
++       int8x16_t result = vcombine_s8                                   \
++                            (a_, vcreate_s8                             \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("rshrn2 %0.16b,%1.8h,#%2"                               \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmull_s8 (int8x8_t a, int8x8_t b)
+-{
+-  int16x8_t result;
+-  __asm__ ("smull %0.8h, %1.8b, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmull_s16 (int16x4_t a, int16x4_t b)
+-{
+-  int32x4_t result;
+-  __asm__ ("smull %0.4s, %1.4h, %2.4h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmull_s32 (int32x2_t a, int32x2_t b)
+-{
+-  int64x2_t result;
+-  __asm__ ("smull %0.2d, %1.2s, %2.2s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
+-
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmull_u8 (uint8x8_t a, uint8x8_t b)
+-{
+-  uint16x8_t result;
+-  __asm__ ("umull %0.8h, %1.8b, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_high_n_s32(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t b_ = (b);                                              \
++       int16x4_t a_ = (a);                                              \
++       int16x8_t result = vcombine_s16                                  \
++                            (a_, vcreate_s16                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("rshrn2 %0.8h,%1.4s,#%2"                                \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmull_u16 (uint16x4_t a, uint16x4_t b)
+-{
+-  uint32x4_t result;
+-  __asm__ ("umull %0.4s, %1.4h, %2.4h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_high_n_s64(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t b_ = (b);                                              \
++       int32x2_t a_ = (a);                                              \
++       int32x4_t result = vcombine_s32                                  \
++                            (a_, vcreate_s32                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("rshrn2 %0.4s,%1.2d,#%2"                                \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmull_u32 (uint32x2_t a, uint32x2_t b)
+-{
+-  uint64x2_t result;
+-  __asm__ ("umull %0.2d, %1.2s, %2.2s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_high_n_u16(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x8_t b_ = (b);                                             \
++       uint8x8_t a_ = (a);                                              \
++       uint8x16_t result = vcombine_u8                                  \
++                            (a_, vcreate_u8                             \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("rshrn2 %0.16b,%1.8h,#%2"                               \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmulq_n_f32 (float32x4_t a, float32_t b)
+-{
+-  float32x4_t result;
+-  __asm__ ("fmul %0.4s,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_high_n_u32(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x4_t b_ = (b);                                             \
++       uint16x4_t a_ = (a);                                             \
++       uint16x8_t result = vcombine_u16                                 \
++                            (a_, vcreate_u16                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("rshrn2 %0.8h,%1.4s,#%2"                                \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmulq_n_f64 (float64x2_t a, float64_t b)
+-{
+-  float64x2_t result;
+-  __asm__ ("fmul %0.2d,%1.2d,%2.d[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_high_n_u64(a, b, c)                                      \
++  __extension__                                                         \
++    ({                                                                  \
++       uint64x2_t b_ = (b);                                             \
++       uint32x2_t a_ = (a);                                             \
++       uint32x4_t result = vcombine_u32                                 \
++                            (a_, vcreate_u32                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("rshrn2 %0.4s,%1.2d,#%2"                                \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmulq_n_s16 (int16x8_t a, int16_t b)
+-{
+-  int16x8_t result;
+-  __asm__ ("mul %0.8h,%1.8h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_n_s16(a, b)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t a_ = (a);                                              \
++       int8x8_t result;                                                 \
++       __asm__ ("rshrn %0.8b,%1.8h,%2"                                  \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmulq_n_s32 (int32x4_t a, int32_t b)
+-{
+-  int32x4_t result;
+-  __asm__ ("mul %0.4s,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_n_s32(a, b)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t a_ = (a);                                              \
++       int16x4_t result;                                                \
++       __asm__ ("rshrn %0.4h,%1.4s,%2"                                  \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmulq_n_u16 (uint16x8_t a, uint16_t b)
+-{
+-  uint16x8_t result;
+-  __asm__ ("mul %0.8h,%1.8h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_n_s64(a, b)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t a_ = (a);                                              \
++       int32x2_t result;                                                \
++       __asm__ ("rshrn %0.2s,%1.2d,%2"                                  \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmulq_n_u32 (uint32x4_t a, uint32_t b)
+-{
+-  uint32x4_t result;
+-  __asm__ ("mul %0.4s,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_n_u16(a, b)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x8_t a_ = (a);                                             \
++       uint8x8_t result;                                                \
++       __asm__ ("rshrn %0.8b,%1.8h,%2"                                  \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vmvn_p8 (poly8x8_t a)
+-{
+-  poly8x8_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_n_u32(a, b)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x4_t a_ = (a);                                             \
++       uint16x4_t result;                                               \
++       __asm__ ("rshrn %0.4h,%1.4s,%2"                                  \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmvn_s8 (int8x8_t a)
+-{
+-  int8x8_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
+-}
++#define vrshrn_n_u64(a, b)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       uint64x2_t a_ = (a);                                             \
++       uint32x2_t result;                                               \
++       __asm__ ("rshrn %0.2s,%1.2d,%2"                                  \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmvn_s16 (int16x4_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrte_u32 (uint32x2_t a)
+ {
+-  int16x4_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
++  uint32x2_t result;
++  __asm__ ("ursqrte %0.2s,%1.2s"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmvn_s32 (int32x2_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrteq_u32 (uint32x4_t a)
+ {
+-  int32x2_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
++  uint32x4_t result;
++  __asm__ ("ursqrte %0.4s,%1.4s"
+            : "=w"(result)
+            : "w"(a)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmvn_u8 (uint8x8_t a)
+-{
++#define vshrn_high_n_s16(a, b, c)                                       \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t b_ = (b);                                              \
++       int8x8_t a_ = (a);                                               \
++       int8x16_t result = vcombine_s8                                   \
++                            (a_, vcreate_s8                             \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("shrn2 %0.16b,%1.8h,#%2"                                \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_high_n_s32(a, b, c)                                       \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t b_ = (b);                                              \
++       int16x4_t a_ = (a);                                              \
++       int16x8_t result = vcombine_s16                                  \
++                            (a_, vcreate_s16                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("shrn2 %0.8h,%1.4s,#%2"                                 \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_high_n_s64(a, b, c)                                       \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t b_ = (b);                                              \
++       int32x2_t a_ = (a);                                              \
++       int32x4_t result = vcombine_s32                                  \
++                            (a_, vcreate_s32                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("shrn2 %0.4s,%1.2d,#%2"                                 \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_high_n_u16(a, b, c)                                       \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x8_t b_ = (b);                                             \
++       uint8x8_t a_ = (a);                                              \
++       uint8x16_t result = vcombine_u8                                  \
++                            (a_, vcreate_u8                             \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("shrn2 %0.16b,%1.8h,#%2"                                \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_high_n_u32(a, b, c)                                       \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x4_t b_ = (b);                                             \
++       uint16x4_t a_ = (a);                                             \
++       uint16x8_t result = vcombine_u16                                 \
++                            (a_, vcreate_u16                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("shrn2 %0.8h,%1.4s,#%2"                                 \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_high_n_u64(a, b, c)                                       \
++  __extension__                                                         \
++    ({                                                                  \
++       uint64x2_t b_ = (b);                                             \
++       uint32x2_t a_ = (a);                                             \
++       uint32x4_t result = vcombine_u32                                 \
++                            (a_, vcreate_u32                            \
++                                   (__AARCH64_UINT64_C (0x0)));         \
++       __asm__ ("shrn2 %0.4s,%1.2d,#%2"                                 \
++                : "+w"(result)                                          \
++                : "w"(b_), "i"(c)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_n_s16(a, b)                                               \
++  __extension__                                                         \
++    ({                                                                  \
++       int16x8_t a_ = (a);                                              \
++       int8x8_t result;                                                 \
++       __asm__ ("shrn %0.8b,%1.8h,%2"                                   \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_n_s32(a, b)                                               \
++  __extension__                                                         \
++    ({                                                                  \
++       int32x4_t a_ = (a);                                              \
++       int16x4_t result;                                                \
++       __asm__ ("shrn %0.4h,%1.4s,%2"                                   \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_n_s64(a, b)                                               \
++  __extension__                                                         \
++    ({                                                                  \
++       int64x2_t a_ = (a);                                              \
++       int32x2_t result;                                                \
++       __asm__ ("shrn %0.2s,%1.2d,%2"                                   \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_n_u16(a, b)                                               \
++  __extension__                                                         \
++    ({                                                                  \
++       uint16x8_t a_ = (a);                                             \
++       uint8x8_t result;                                                \
++       __asm__ ("shrn %0.8b,%1.8h,%2"                                   \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_n_u32(a, b)                                               \
++  __extension__                                                         \
++    ({                                                                  \
++       uint32x4_t a_ = (a);                                             \
++       uint16x4_t result;                                               \
++       __asm__ ("shrn %0.4h,%1.4s,%2"                                   \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vshrn_n_u64(a, b)                                               \
++  __extension__                                                         \
++    ({                                                                  \
++       uint64x2_t a_ = (a);                                             \
++       uint32x2_t result;                                               \
++       __asm__ ("shrn %0.2s,%1.2d,%2"                                   \
++                : "=w"(result)                                          \
++                : "w"(a_), "i"(b)                                       \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsli_n_p8(a, b, c)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       poly8x8_t b_ = (b);                                              \
++       poly8x8_t a_ = (a);                                              \
++       poly8x8_t result;                                                \
++       __asm__ ("sli %0.8b,%2.8b,%3"                                    \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsli_n_p16(a, b, c)                                             \
++  __extension__                                                         \
++    ({                                                                  \
++       poly16x4_t b_ = (b);                                             \
++       poly16x4_t a_ = (a);                                             \
++       poly16x4_t result;                                               \
++       __asm__ ("sli %0.4h,%2.4h,%3"                                    \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsliq_n_p8(a, b, c)                                             \
++  __extension__                                                         \
++    ({                                                                  \
++       poly8x16_t b_ = (b);                                             \
++       poly8x16_t a_ = (a);                                             \
++       poly8x16_t result;                                               \
++       __asm__ ("sli %0.16b,%2.16b,%3"                                  \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsliq_n_p16(a, b, c)                                            \
++  __extension__                                                         \
++    ({                                                                  \
++       poly16x8_t b_ = (b);                                             \
++       poly16x8_t a_ = (a);                                             \
++       poly16x8_t result;                                               \
++       __asm__ ("sli %0.8h,%2.8h,%3"                                    \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsri_n_p8(a, b, c)                                              \
++  __extension__                                                         \
++    ({                                                                  \
++       poly8x8_t b_ = (b);                                              \
++       poly8x8_t a_ = (a);                                              \
++       poly8x8_t result;                                                \
++       __asm__ ("sri %0.8b,%2.8b,%3"                                    \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsri_n_p16(a, b, c)                                             \
++  __extension__                                                         \
++    ({                                                                  \
++       poly16x4_t b_ = (b);                                             \
++       poly16x4_t a_ = (a);                                             \
++       poly16x4_t result;                                               \
++       __asm__ ("sri %0.4h,%2.4h,%3"                                    \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsri_n_p64(a, b, c)						\
++  __extension__								\
++    ({									\
++       poly64x1_t b_ = (b);						\
++       poly64x1_t a_ = (a);						\
++       poly64x1_t result;						\
++       __asm__ ("sri %d0,%d2,%3"					\
++		: "=w"(result)						\
++		: "0"(a_), "w"(b_), "i"(c)				\
++		: /* No clobbers.  */);					\
++       result;								\
++     })
++
++#define vsriq_n_p8(a, b, c)                                             \
++  __extension__                                                         \
++    ({                                                                  \
++       poly8x16_t b_ = (b);                                             \
++       poly8x16_t a_ = (a);                                             \
++       poly8x16_t result;                                               \
++       __asm__ ("sri %0.16b,%2.16b,%3"                                  \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsriq_n_p16(a, b, c)                                            \
++  __extension__                                                         \
++    ({                                                                  \
++       poly16x8_t b_ = (b);                                             \
++       poly16x8_t a_ = (a);                                             \
++       poly16x8_t result;                                               \
++       __asm__ ("sri %0.8h,%2.8h,%3"                                    \
++                : "=w"(result)                                          \
++                : "0"(a_), "w"(b_), "i"(c)                              \
++                : /* No clobbers */);                                   \
++       result;                                                          \
++     })
++
++#define vsriq_n_p64(a, b, c)						\
++  __extension__								\
++    ({									\
++       poly64x2_t b_ = (b);						\
++       poly64x2_t a_ = (a);						\
++       poly64x2_t result;						\
++       __asm__ ("sri %0.2d,%2.2d,%3"					\
++		: "=w"(result)						\
++		: "0"(a_), "w"(b_), "i"(c)				\
++		: /* No clobbers.  */);					\
++       result;								\
++     })
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_p8 (poly8x8_t a, poly8x8_t b)
++{
++  return (uint8x8_t) ((((uint8x8_t) a) & ((uint8x8_t) b))
++		       != 0);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_p16 (poly16x4_t a, poly16x4_t b)
++{
++  return (uint16x4_t) ((((uint16x4_t) a) & ((uint16x4_t) b))
++		       != 0);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_p64 (poly64x1_t a, poly64x1_t b)
++{
++  return (uint64x1_t) ((a & b) != __AARCH64_INT64_C (0));
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_p8 (poly8x16_t a, poly8x16_t b)
++{
++  return (uint8x16_t) ((((uint8x16_t) a) & ((uint8x16_t) b))
++		       != 0);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_p16 (poly16x8_t a, poly16x8_t b)
++{
++  return (uint16x8_t) ((((uint16x8_t) a) & ((uint16x8_t) b))
++		       != 0);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_p64 (poly64x2_t a, poly64x2_t b)
++{
++  return (uint64x2_t) ((((uint64x2_t) a) & ((uint64x2_t) b))
++		       != __AARCH64_INT64_C (0));
++}
++
++/* End of temporary inline asm implementations.  */
++
++/* Start of temporary inline asm for vldn, vstn and friends.  */
++
++/* Create struct element types for duplicating loads.
++
++   Create 2 element structures of:
++
++   +------+----+----+----+----+
++   |      | 8  | 16 | 32 | 64 |
++   +------+----+----+----+----+
++   |int   | Y  | Y  | N  | N  |
++   +------+----+----+----+----+
++   |uint  | Y  | Y  | N  | N  |
++   +------+----+----+----+----+
++   |float | -  | Y  | N  | N  |
++   +------+----+----+----+----+
++   |poly  | Y  | Y  | -  | -  |
++   +------+----+----+----+----+
++
++   Create 3 element structures of:
++
++   +------+----+----+----+----+
++   |      | 8  | 16 | 32 | 64 |
++   +------+----+----+----+----+
++   |int   | Y  | Y  | Y  | Y  |
++   +------+----+----+----+----+
++   |uint  | Y  | Y  | Y  | Y  |
++   +------+----+----+----+----+
++   |float | -  | Y  | Y  | Y  |
++   +------+----+----+----+----+
++   |poly  | Y  | Y  | -  | -  |
++   +------+----+----+----+----+
++
++   Create 4 element structures of:
++
++   +------+----+----+----+----+
++   |      | 8  | 16 | 32 | 64 |
++   +------+----+----+----+----+
++   |int   | Y  | N  | N  | Y  |
++   +------+----+----+----+----+
++   |uint  | Y  | N  | N  | Y  |
++   +------+----+----+----+----+
++   |float | -  | N  | N  | Y  |
++   +------+----+----+----+----+
++   |poly  | Y  | N  | -  | -  |
++   +------+----+----+----+----+
++
++  This is required for casting memory reference.  */
++#define __STRUCTN(t, sz, nelem)			\
++  typedef struct t ## sz ## x ## nelem ## _t {	\
++    t ## sz ## _t val[nelem];			\
++  }  t ## sz ## x ## nelem ## _t;
++
++/* 2-element structs.  */
++__STRUCTN (int, 8, 2)
++__STRUCTN (int, 16, 2)
++__STRUCTN (uint, 8, 2)
++__STRUCTN (uint, 16, 2)
++__STRUCTN (float, 16, 2)
++__STRUCTN (poly, 8, 2)
++__STRUCTN (poly, 16, 2)
++/* 3-element structs.  */
++__STRUCTN (int, 8, 3)
++__STRUCTN (int, 16, 3)
++__STRUCTN (int, 32, 3)
++__STRUCTN (int, 64, 3)
++__STRUCTN (uint, 8, 3)
++__STRUCTN (uint, 16, 3)
++__STRUCTN (uint, 32, 3)
++__STRUCTN (uint, 64, 3)
++__STRUCTN (float, 16, 3)
++__STRUCTN (float, 32, 3)
++__STRUCTN (float, 64, 3)
++__STRUCTN (poly, 8, 3)
++__STRUCTN (poly, 16, 3)
++/* 4-element structs.  */
++__STRUCTN (int, 8, 4)
++__STRUCTN (int, 64, 4)
++__STRUCTN (uint, 8, 4)
++__STRUCTN (uint, 64, 4)
++__STRUCTN (poly, 8, 4)
++__STRUCTN (float, 64, 4)
++#undef __STRUCTN
++
++
++#define __ST2_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
++			qmode, ptr_mode, funcsuffix, signedtype)	     \
++__extension__ extern __inline void					     \
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++vst2_lane_ ## funcsuffix (ptrtype *__ptr,				     \
++			  intype __b, const int __c)			     \
++{									     \
++  __builtin_aarch64_simd_oi __o;					     \
++  largetype __temp;							     \
++  __temp.val[0]								     \
++    = vcombine_##funcsuffix (__b.val[0],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __temp.val[1]								     \
++    = vcombine_##funcsuffix (__b.val[1],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __o = __builtin_aarch64_set_qregoi##qmode (__o,			     \
++					     (signedtype) __temp.val[0], 0); \
++  __o = __builtin_aarch64_set_qregoi##qmode (__o,			     \
++					     (signedtype) __temp.val[1], 1); \
++  __builtin_aarch64_st2_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
++				     __ptr, __o, __c);			     \
++}
++
++__ST2_LANE_FUNC (float16x4x2_t, float16x8x2_t, float16_t, v4hf, v8hf, hf, f16,
++		 float16x8_t)
++__ST2_LANE_FUNC (float32x2x2_t, float32x4x2_t, float32_t, v2sf, v4sf, sf, f32,
++		 float32x4_t)
++__ST2_LANE_FUNC (float64x1x2_t, float64x2x2_t, float64_t, df, v2df, df, f64,
++		 float64x2_t)
++__ST2_LANE_FUNC (poly8x8x2_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8,
++		 int8x16_t)
++__ST2_LANE_FUNC (poly16x4x2_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi, p16,
++		 int16x8_t)
++__ST2_LANE_FUNC (poly64x1x2_t, poly64x2x2_t, poly64_t, di, v2di_ssps, di, p64,
++		 poly64x2_t)
++__ST2_LANE_FUNC (int8x8x2_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8,
++		 int8x16_t)
++__ST2_LANE_FUNC (int16x4x2_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16,
++		 int16x8_t)
++__ST2_LANE_FUNC (int32x2x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32,
++		 int32x4_t)
++__ST2_LANE_FUNC (int64x1x2_t, int64x2x2_t, int64_t, di, v2di, di, s64,
++		 int64x2_t)
++__ST2_LANE_FUNC (uint8x8x2_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8,
++		 int8x16_t)
++__ST2_LANE_FUNC (uint16x4x2_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi, u16,
++		 int16x8_t)
++__ST2_LANE_FUNC (uint32x2x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si, u32,
++		 int32x4_t)
++__ST2_LANE_FUNC (uint64x1x2_t, uint64x2x2_t, uint64_t, di, v2di, di, u64,
++		 int64x2_t)
++
++#undef __ST2_LANE_FUNC
++#define __ST2_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
++__extension__ extern __inline void					    \
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++vst2q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
++			   intype __b, const int __c)			    \
++{									    \
++  union { intype __i;							    \
++	  __builtin_aarch64_simd_oi __o; } __temp = { __b };		    \
++  __builtin_aarch64_st2_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
++				    __ptr, __temp.__o, __c);		    \
++}
++
++__ST2_LANE_FUNC (float16x8x2_t, float16_t, v8hf, hf, f16)
++__ST2_LANE_FUNC (float32x4x2_t, float32_t, v4sf, sf, f32)
++__ST2_LANE_FUNC (float64x2x2_t, float64_t, v2df, df, f64)
++__ST2_LANE_FUNC (poly8x16x2_t, poly8_t, v16qi, qi, p8)
++__ST2_LANE_FUNC (poly16x8x2_t, poly16_t, v8hi, hi, p16)
++__ST2_LANE_FUNC (poly64x2x2_t, poly64_t, v2di, di, p64)
++__ST2_LANE_FUNC (int8x16x2_t, int8_t, v16qi, qi, s8)
++__ST2_LANE_FUNC (int16x8x2_t, int16_t, v8hi, hi, s16)
++__ST2_LANE_FUNC (int32x4x2_t, int32_t, v4si, si, s32)
++__ST2_LANE_FUNC (int64x2x2_t, int64_t, v2di, di, s64)
++__ST2_LANE_FUNC (uint8x16x2_t, uint8_t, v16qi, qi, u8)
++__ST2_LANE_FUNC (uint16x8x2_t, uint16_t, v8hi, hi, u16)
++__ST2_LANE_FUNC (uint32x4x2_t, uint32_t, v4si, si, u32)
++__ST2_LANE_FUNC (uint64x2x2_t, uint64_t, v2di, di, u64)
++
++#define __ST3_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
++			qmode, ptr_mode, funcsuffix, signedtype)	     \
++__extension__ extern __inline void					     \
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++vst3_lane_ ## funcsuffix (ptrtype *__ptr,				     \
++			  intype __b, const int __c)			     \
++{									     \
++  __builtin_aarch64_simd_ci __o;					     \
++  largetype __temp;							     \
++  __temp.val[0]								     \
++    = vcombine_##funcsuffix (__b.val[0],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __temp.val[1]								     \
++    = vcombine_##funcsuffix (__b.val[1],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __temp.val[2]								     \
++    = vcombine_##funcsuffix (__b.val[2],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
++					     (signedtype) __temp.val[0], 0); \
++  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
++					     (signedtype) __temp.val[1], 1); \
++  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
++					     (signedtype) __temp.val[2], 2); \
++  __builtin_aarch64_st3_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
++				     __ptr, __o, __c);			     \
++}
++
++__ST3_LANE_FUNC (float16x4x3_t, float16x8x3_t, float16_t, v4hf, v8hf, hf, f16,
++		 float16x8_t)
++__ST3_LANE_FUNC (float32x2x3_t, float32x4x3_t, float32_t, v2sf, v4sf, sf, f32,
++		 float32x4_t)
++__ST3_LANE_FUNC (float64x1x3_t, float64x2x3_t, float64_t, df, v2df, df, f64,
++		 float64x2_t)
++__ST3_LANE_FUNC (poly8x8x3_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8,
++		 int8x16_t)
++__ST3_LANE_FUNC (poly16x4x3_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi, p16,
++		 int16x8_t)
++__ST3_LANE_FUNC (poly64x1x3_t, poly64x2x3_t, poly64_t, di, v2di_ssps, di, p64,
++		 poly64x2_t)
++__ST3_LANE_FUNC (int8x8x3_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8,
++		 int8x16_t)
++__ST3_LANE_FUNC (int16x4x3_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16,
++		 int16x8_t)
++__ST3_LANE_FUNC (int32x2x3_t, int32x4x3_t, int32_t, v2si, v4si, si, s32,
++		 int32x4_t)
++__ST3_LANE_FUNC (int64x1x3_t, int64x2x3_t, int64_t, di, v2di, di, s64,
++		 int64x2_t)
++__ST3_LANE_FUNC (uint8x8x3_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8,
++		 int8x16_t)
++__ST3_LANE_FUNC (uint16x4x3_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi, u16,
++		 int16x8_t)
++__ST3_LANE_FUNC (uint32x2x3_t, uint32x4x3_t, uint32_t, v2si, v4si, si, u32,
++		 int32x4_t)
++__ST3_LANE_FUNC (uint64x1x3_t, uint64x2x3_t, uint64_t, di, v2di, di, u64,
++		 int64x2_t)
++
++#undef __ST3_LANE_FUNC
++#define __ST3_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
++__extension__ extern __inline void					    \
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++vst3q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
++			   intype __b, const int __c)			    \
++{									    \
++  union { intype __i;							    \
++	  __builtin_aarch64_simd_ci __o; } __temp = { __b };		    \
++  __builtin_aarch64_st3_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
++				    __ptr, __temp.__o, __c);		    \
++}
++
++__ST3_LANE_FUNC (float16x8x3_t, float16_t, v8hf, hf, f16)
++__ST3_LANE_FUNC (float32x4x3_t, float32_t, v4sf, sf, f32)
++__ST3_LANE_FUNC (float64x2x3_t, float64_t, v2df, df, f64)
++__ST3_LANE_FUNC (poly8x16x3_t, poly8_t, v16qi, qi, p8)
++__ST3_LANE_FUNC (poly16x8x3_t, poly16_t, v8hi, hi, p16)
++__ST3_LANE_FUNC (poly64x2x3_t, poly64_t, v2di, di, p64)
++__ST3_LANE_FUNC (int8x16x3_t, int8_t, v16qi, qi, s8)
++__ST3_LANE_FUNC (int16x8x3_t, int16_t, v8hi, hi, s16)
++__ST3_LANE_FUNC (int32x4x3_t, int32_t, v4si, si, s32)
++__ST3_LANE_FUNC (int64x2x3_t, int64_t, v2di, di, s64)
++__ST3_LANE_FUNC (uint8x16x3_t, uint8_t, v16qi, qi, u8)
++__ST3_LANE_FUNC (uint16x8x3_t, uint16_t, v8hi, hi, u16)
++__ST3_LANE_FUNC (uint32x4x3_t, uint32_t, v4si, si, u32)
++__ST3_LANE_FUNC (uint64x2x3_t, uint64_t, v2di, di, u64)
++
++#define __ST4_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
++			qmode, ptr_mode, funcsuffix, signedtype)	     \
++__extension__ extern __inline void					     \
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++vst4_lane_ ## funcsuffix (ptrtype *__ptr,				     \
++			  intype __b, const int __c)			     \
++{									     \
++  __builtin_aarch64_simd_xi __o;					     \
++  largetype __temp;							     \
++  __temp.val[0]								     \
++    = vcombine_##funcsuffix (__b.val[0],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __temp.val[1]								     \
++    = vcombine_##funcsuffix (__b.val[1],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __temp.val[2]								     \
++    = vcombine_##funcsuffix (__b.val[2],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __temp.val[3]								     \
++    = vcombine_##funcsuffix (__b.val[3],				     \
++			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
++					     (signedtype) __temp.val[0], 0); \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
++					     (signedtype) __temp.val[1], 1); \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
++					     (signedtype) __temp.val[2], 2); \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
++					     (signedtype) __temp.val[3], 3); \
++  __builtin_aarch64_st4_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
++				     __ptr, __o, __c);			     \
++}
++
++__ST4_LANE_FUNC (float16x4x4_t, float16x8x4_t, float16_t, v4hf, v8hf, hf, f16,
++		 float16x8_t)
++__ST4_LANE_FUNC (float32x2x4_t, float32x4x4_t, float32_t, v2sf, v4sf, sf, f32,
++		 float32x4_t)
++__ST4_LANE_FUNC (float64x1x4_t, float64x2x4_t, float64_t, df, v2df, df, f64,
++		 float64x2_t)
++__ST4_LANE_FUNC (poly8x8x4_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8,
++		 int8x16_t)
++__ST4_LANE_FUNC (poly16x4x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi, p16,
++		 int16x8_t)
++__ST4_LANE_FUNC (poly64x1x4_t, poly64x2x4_t, poly64_t, di, v2di_ssps, di, p64,
++		 poly64x2_t)
++__ST4_LANE_FUNC (int8x8x4_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8,
++		 int8x16_t)
++__ST4_LANE_FUNC (int16x4x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16,
++		 int16x8_t)
++__ST4_LANE_FUNC (int32x2x4_t, int32x4x4_t, int32_t, v2si, v4si, si, s32,
++		 int32x4_t)
++__ST4_LANE_FUNC (int64x1x4_t, int64x2x4_t, int64_t, di, v2di, di, s64,
++		 int64x2_t)
++__ST4_LANE_FUNC (uint8x8x4_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8,
++		 int8x16_t)
++__ST4_LANE_FUNC (uint16x4x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi, u16,
++		 int16x8_t)
++__ST4_LANE_FUNC (uint32x2x4_t, uint32x4x4_t, uint32_t, v2si, v4si, si, u32,
++		 int32x4_t)
++__ST4_LANE_FUNC (uint64x1x4_t, uint64x2x4_t, uint64_t, di, v2di, di, u64,
++		 int64x2_t)
++
++#undef __ST4_LANE_FUNC
++#define __ST4_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
++__extension__ extern __inline void					    \
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++vst4q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
++			   intype __b, const int __c)			    \
++{									    \
++  union { intype __i;							    \
++	  __builtin_aarch64_simd_xi __o; } __temp = { __b };		    \
++  __builtin_aarch64_st4_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
++				    __ptr, __temp.__o, __c);		    \
++}
++
++__ST4_LANE_FUNC (float16x8x4_t, float16_t, v8hf, hf, f16)
++__ST4_LANE_FUNC (float32x4x4_t, float32_t, v4sf, sf, f32)
++__ST4_LANE_FUNC (float64x2x4_t, float64_t, v2df, df, f64)
++__ST4_LANE_FUNC (poly8x16x4_t, poly8_t, v16qi, qi, p8)
++__ST4_LANE_FUNC (poly16x8x4_t, poly16_t, v8hi, hi, p16)
++__ST4_LANE_FUNC (poly64x2x4_t, poly64_t, v2di, di, p64)
++__ST4_LANE_FUNC (int8x16x4_t, int8_t, v16qi, qi, s8)
++__ST4_LANE_FUNC (int16x8x4_t, int16_t, v8hi, hi, s16)
++__ST4_LANE_FUNC (int32x4x4_t, int32_t, v4si, si, s32)
++__ST4_LANE_FUNC (int64x2x4_t, int64_t, v2di, di, s64)
++__ST4_LANE_FUNC (uint8x16x4_t, uint8_t, v16qi, qi, u8)
++__ST4_LANE_FUNC (uint16x8x4_t, uint16_t, v8hi, hi, u16)
++__ST4_LANE_FUNC (uint32x4x4_t, uint32_t, v4si, si, u32)
++__ST4_LANE_FUNC (uint64x2x4_t, uint64_t, v2di, di, u64)
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddlv_s32 (int32x2_t a)
++{
++  int64_t result;
++  __asm__ ("saddlp %0.1d, %1.2s" : "=w"(result) : "w"(a) : );
++  return result;
++}
++
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddlv_u32 (uint32x2_t a)
++{
++  uint64_t result;
++  __asm__ ("uaddlp %0.1d, %1.2s" : "=w"(result) : "w"(a) : );
++  return result;
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c)
++{
++  return __builtin_aarch64_sqdmulh_laneqv4hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c)
++{
++  return __builtin_aarch64_sqdmulh_laneqv2si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++{
++  return __builtin_aarch64_sqdmulh_laneqv8hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++{
++  return __builtin_aarch64_sqdmulh_laneqv4si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c)
++{
++  return  __builtin_aarch64_sqrdmulh_laneqv4hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c)
++{
++  return __builtin_aarch64_sqrdmulh_laneqv2si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++{
++  return __builtin_aarch64_sqrdmulh_laneqv8hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++{
++  return __builtin_aarch64_sqrdmulh_laneqv4si (__a, __b, __c);
++}
++
++/* Table intrinsics.  */
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl1_p8 (poly8x16_t a, uint8x8_t b)
++{
++  poly8x8_t result;
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl1_s8 (int8x16_t a, uint8x8_t b)
++{
++  int8x8_t result;
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl1_u8 (uint8x16_t a, uint8x8_t b)
++{
++  uint8x8_t result;
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl1q_p8 (poly8x16_t a, uint8x16_t b)
++{
++  poly8x16_t result;
++  __asm__ ("tbl %0.16b, {%1.16b}, %2.16b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl1q_s8 (int8x16_t a, uint8x16_t b)
++{
++  int8x16_t result;
++  __asm__ ("tbl %0.16b, {%1.16b}, %2.16b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl1q_u8 (uint8x16_t a, uint8x16_t b)
++{
++  uint8x16_t result;
++  __asm__ ("tbl %0.16b, {%1.16b}, %2.16b"
++           : "=w"(result)
++           : "w"(a), "w"(b)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx1_s8 (int8x8_t r, int8x16_t tab, uint8x8_t idx)
++{
++  int8x8_t result = r;
++  __asm__ ("tbx %0.8b,{%1.16b},%2.8b"
++           : "+w"(result)
++           : "w"(tab), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx1_u8 (uint8x8_t r, uint8x16_t tab, uint8x8_t idx)
++{
++  uint8x8_t result = r;
++  __asm__ ("tbx %0.8b,{%1.16b},%2.8b"
++           : "+w"(result)
++           : "w"(tab), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx1_p8 (poly8x8_t r, poly8x16_t tab, uint8x8_t idx)
++{
++  poly8x8_t result = r;
++  __asm__ ("tbx %0.8b,{%1.16b},%2.8b"
++           : "+w"(result)
++           : "w"(tab), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx1q_s8 (int8x16_t r, int8x16_t tab, uint8x16_t idx)
++{
++  int8x16_t result = r;
++  __asm__ ("tbx %0.16b,{%1.16b},%2.16b"
++           : "+w"(result)
++           : "w"(tab), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx1q_u8 (uint8x16_t r, uint8x16_t tab, uint8x16_t idx)
++{
++  uint8x16_t result = r;
++  __asm__ ("tbx %0.16b,{%1.16b},%2.16b"
++           : "+w"(result)
++           : "w"(tab), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx1q_p8 (poly8x16_t r, poly8x16_t tab, uint8x16_t idx)
++{
++  poly8x16_t result = r;
++  __asm__ ("tbx %0.16b,{%1.16b},%2.16b"
++           : "+w"(result)
++           : "w"(tab), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++/* V7 legacy table intrinsics.  */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl1_s8 (int8x8_t tab, int8x8_t idx)
++{
++  int8x8_t result;
++  int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl1_u8 (uint8x8_t tab, uint8x8_t idx)
++{
+   uint8x8_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
++  uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+            : "=w"(result)
+-           : "w"(a)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl1_p8 (poly8x8_t tab, uint8x8_t idx)
++{
++  poly8x8_t result;
++  poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (__AARCH64_UINT64_C (0x0)));
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl2_s8 (int8x8x2_t tab, int8x8_t idx)
++{
++  int8x8_t result;
++  int8x16_t temp = vcombine_s8 (tab.val[0], tab.val[1]);
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl2_u8 (uint8x8x2_t tab, uint8x8_t idx)
++{
++  uint8x8_t result;
++  uint8x16_t temp = vcombine_u8 (tab.val[0], tab.val[1]);
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl2_p8 (poly8x8x2_t tab, uint8x8_t idx)
++{
++  poly8x8_t result;
++  poly8x16_t temp = vcombine_p8 (tab.val[0], tab.val[1]);
++  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
++           : "=w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl3_s8 (int8x8x3_t tab, int8x8_t idx)
++{
++  int8x8_t result;
++  int8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]);
++  temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (__AARCH64_UINT64_C (0x0)));
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = __builtin_aarch64_tbl3v8qi (__o, idx);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl3_u8 (uint8x8x3_t tab, uint8x8_t idx)
++{
++  uint8x8_t result;
++  uint8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]);
++  temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (__AARCH64_UINT64_C (0x0)));
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = (uint8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return result;
++}
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl3_p8 (poly8x8x3_t tab, uint8x8_t idx)
++{
++  poly8x8_t result;
++  poly8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]);
++  temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (__AARCH64_UINT64_C (0x0)));
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = (poly8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl4_s8 (int8x8x4_t tab, int8x8_t idx)
++{
++  int8x8_t result;
++  int8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]);
++  temp.val[1] = vcombine_s8 (tab.val[2], tab.val[3]);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = __builtin_aarch64_tbl3v8qi (__o, idx);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl4_u8 (uint8x8x4_t tab, uint8x8_t idx)
++{
++  uint8x8_t result;
++  uint8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]);
++  temp.val[1] = vcombine_u8 (tab.val[2], tab.val[3]);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = (uint8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return result;
++}
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbl4_p8 (poly8x8x4_t tab, uint8x8_t idx)
++{
++  poly8x8_t result;
++  poly8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]);
++  temp.val[1] = vcombine_p8 (tab.val[2], tab.val[3]);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = (poly8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return result;
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx2_s8 (int8x8_t r, int8x8x2_t tab, int8x8_t idx)
++{
++  int8x8_t result = r;
++  int8x16_t temp = vcombine_s8 (tab.val[0], tab.val[1]);
++  __asm__ ("tbx %0.8b, {%1.16b}, %2.8b"
++           : "+w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx2_u8 (uint8x8_t r, uint8x8x2_t tab, uint8x8_t idx)
++{
++  uint8x8_t result = r;
++  uint8x16_t temp = vcombine_u8 (tab.val[0], tab.val[1]);
++  __asm__ ("tbx %0.8b, {%1.16b}, %2.8b"
++           : "+w"(result)
++           : "w"(temp), "w"(idx)
+            : /* No clobbers */);
+   return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmvn_u16 (uint16x4_t a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx2_p8 (poly8x8_t r, poly8x8x2_t tab, uint8x8_t idx)
++{
++  poly8x8_t result = r;
++  poly8x16_t temp = vcombine_p8 (tab.val[0], tab.val[1]);
++  __asm__ ("tbx %0.8b, {%1.16b}, %2.8b"
++           : "+w"(result)
++           : "w"(temp), "w"(idx)
++           : /* No clobbers */);
++  return result;
++}
++
++/* End of temporary inline asm.  */
++
++/* Start of optimal implementations in approved order.  */
++
++/* vabd.  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabds_f32 (float32_t __a, float32_t __b)
++{
++  return __builtin_aarch64_fabdsf (__a, __b);
++}
++
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabdd_f64 (float64_t __a, float64_t __b)
++{
++  return __builtin_aarch64_fabddf (__a, __b);
++}
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabd_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return __builtin_aarch64_fabdv2sf (__a, __b);
++}
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabd_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return (float64x1_t) {vabdd_f64 (vget_lane_f64 (__a, 0),
++				   vget_lane_f64 (__b, 0))};
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabdq_f32 (float32x4_t __a, float32x4_t __b)
++{
++  return __builtin_aarch64_fabdv4sf (__a, __b);
++}
++
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabdq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return __builtin_aarch64_fabdv2df (__a, __b);
++}
++
++/* vabs  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_f32 (float32x2_t __a)
++{
++  return __builtin_aarch64_absv2sf (__a);
++}
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_f64 (float64x1_t __a)
++{
++  return (float64x1_t) {__builtin_fabs (__a[0])};
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_s8 (int8x8_t __a)
++{
++  return __builtin_aarch64_absv8qi (__a);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_s16 (int16x4_t __a)
++{
++  return __builtin_aarch64_absv4hi (__a);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_s32 (int32x2_t __a)
++{
++  return __builtin_aarch64_absv2si (__a);
++}
++
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_s64 (int64x1_t __a)
++{
++  return (int64x1_t) {__builtin_aarch64_absdi (__a[0])};
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_f32 (float32x4_t __a)
++{
++  return __builtin_aarch64_absv4sf (__a);
++}
++
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_f64 (float64x2_t __a)
++{
++  return __builtin_aarch64_absv2df (__a);
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_s8 (int8x16_t __a)
++{
++  return __builtin_aarch64_absv16qi (__a);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_s16 (int16x8_t __a)
++{
++  return __builtin_aarch64_absv8hi (__a);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_s32 (int32x4_t __a)
++{
++  return __builtin_aarch64_absv4si (__a);
++}
++
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_s64 (int64x2_t __a)
++{
++  return __builtin_aarch64_absv2di (__a);
++}
++
++/* vadd */
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddd_s64 (int64_t __a, int64_t __b)
++{
++  return __a + __b;
++}
++
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddd_u64 (uint64_t __a, uint64_t __b)
++{
++  return __a + __b;
++}
++
++/* vaddv */
++
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_s8 (int8x8_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v8qi (__a);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_s16 (int16x4_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v4hi (__a);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_s32 (int32x2_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v2si (__a);
++}
++
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_u8 (uint8x8_t __a)
++{
++  return (uint8_t) __builtin_aarch64_reduc_plus_scal_v8qi ((int8x8_t) __a);
++}
++
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_u16 (uint16x4_t __a)
++{
++  return (uint16_t) __builtin_aarch64_reduc_plus_scal_v4hi ((int16x4_t) __a);
++}
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_u32 (uint32x2_t __a)
++{
++  return (int32_t) __builtin_aarch64_reduc_plus_scal_v2si ((int32x2_t) __a);
++}
++
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_s8 (int8x16_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v16qi (__a);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_s16 (int16x8_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v8hi (__a);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_s32 (int32x4_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v4si (__a);
++}
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_s64 (int64x2_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v2di (__a);
++}
++
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_u8 (uint8x16_t __a)
++{
++  return (uint8_t) __builtin_aarch64_reduc_plus_scal_v16qi ((int8x16_t) __a);
++}
++
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_u16 (uint16x8_t __a)
++{
++  return (uint16_t) __builtin_aarch64_reduc_plus_scal_v8hi ((int16x8_t) __a);
++}
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_u32 (uint32x4_t __a)
++{
++  return (uint32_t) __builtin_aarch64_reduc_plus_scal_v4si ((int32x4_t) __a);
++}
++
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_u64 (uint64x2_t __a)
++{
++  return (uint64_t) __builtin_aarch64_reduc_plus_scal_v2di ((int64x2_t) __a);
++}
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddv_f32 (float32x2_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v2sf (__a);
++}
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_f32 (float32x4_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v4sf (__a);
++}
++
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddvq_f64 (float64x2_t __a)
++{
++  return __builtin_aarch64_reduc_plus_scal_v2df (__a);
++}
++
++/* vbsl  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_f16 (uint16x4_t __a, float16x4_t __b, float16x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4hf_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_f32 (uint32x2_t __a, float32x2_t __b, float32x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2sf_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_f64 (uint64x1_t __a, float64x1_t __b, float64x1_t __c)
++{
++  return (float64x1_t)
++    { __builtin_aarch64_simd_bsldf_suss (__a[0], __b[0], __c[0]) };
++}
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_p8 (uint8x8_t __a, poly8x8_t __b, poly8x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8qi_pupp (__a, __b, __c);
++}
++
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_p16 (uint16x4_t __a, poly16x4_t __b, poly16x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4hi_pupp (__a, __b, __c);
++}
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_p64 (uint64x1_t __a, poly64x1_t __b, poly64x1_t __c)
++{
++  return (poly64x1_t)
++      {__builtin_aarch64_simd_bsldi_pupp (__a[0], __b[0], __c[0])};
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_s8 (uint8x8_t __a, int8x8_t __b, int8x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8qi_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_s16 (uint16x4_t __a, int16x4_t __b, int16x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4hi_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_s32 (uint32x2_t __a, int32x2_t __b, int32x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2si_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_s64 (uint64x1_t __a, int64x1_t __b, int64x1_t __c)
++{
++  return (int64x1_t)
++      {__builtin_aarch64_simd_bsldi_suss (__a[0], __b[0], __c[0])};
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8qi_uuuu (__a, __b, __c);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4hi_uuuu (__a, __b, __c);
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2si_uuuu (__a, __b, __c);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_u64 (uint64x1_t __a, uint64x1_t __b, uint64x1_t __c)
++{
++  return (uint64x1_t)
++      {__builtin_aarch64_simd_bsldi_uuuu (__a[0], __b[0], __c[0])};
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_f16 (uint16x8_t __a, float16x8_t __b, float16x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8hf_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_f32 (uint32x4_t __a, float32x4_t __b, float32x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4sf_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_f64 (uint64x2_t __a, float64x2_t __b, float64x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2df_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_p8 (uint8x16_t __a, poly8x16_t __b, poly8x16_t __c)
++{
++  return __builtin_aarch64_simd_bslv16qi_pupp (__a, __b, __c);
++}
++
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_p16 (uint16x8_t __a, poly16x8_t __b, poly16x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8hi_pupp (__a, __b, __c);
++}
++
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_s8 (uint8x16_t __a, int8x16_t __b, int8x16_t __c)
++{
++  return __builtin_aarch64_simd_bslv16qi_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_s16 (uint16x8_t __a, int16x8_t __b, int16x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8hi_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_p64 (uint64x2_t __a, poly64x2_t __b, poly64x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2di_pupp (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_s32 (uint32x4_t __a, int32x4_t __b, int32x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4si_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_s64 (uint64x2_t __a, int64x2_t __b, int64x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2di_suss (__a, __b, __c);
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
++{
++  return __builtin_aarch64_simd_bslv16qi_uuuu (__a, __b, __c);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
++{
++  return __builtin_aarch64_simd_bslv8hi_uuuu (__a, __b, __c);
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
++{
++  return __builtin_aarch64_simd_bslv4si_uuuu (__a, __b, __c);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
++{
++  return __builtin_aarch64_simd_bslv2di_uuuu (__a, __b, __c);
++}
++
++/* ARMv8.1-A instrinsics.  */
++#pragma GCC push_options
++#pragma GCC target ("arch=armv8.1-a")
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlah_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
++{
++  return __builtin_aarch64_sqrdmlahv4hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlah_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
++{
++  return __builtin_aarch64_sqrdmlahv2si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
++{
++  return __builtin_aarch64_sqrdmlahv8hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
++{
++  return __builtin_aarch64_sqrdmlahv4si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlsh_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
++{
++  return __builtin_aarch64_sqrdmlshv4hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlsh_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
++{
++  return __builtin_aarch64_sqrdmlshv2si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
++{
++  return __builtin_aarch64_sqrdmlshv8hi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
++{
++  return __builtin_aarch64_sqrdmlshv4si (__a, __b, __c);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlah_laneq_s16 (int16x4_t __a, int16x4_t __b, int16x8_t __c, const int __d)
++{
++  return  __builtin_aarch64_sqrdmlah_laneqv4hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlah_laneq_s32 (int32x2_t __a, int32x2_t __b, int32x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_laneqv2si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahq_laneq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_laneqv8hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahq_laneq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_laneqv4si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlsh_laneq_s16 (int16x4_t __a, int16x4_t __b, int16x8_t __c, const int __d)
++{
++  return  __builtin_aarch64_sqrdmlsh_laneqv4hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlsh_laneq_s32 (int32x2_t __a, int32x2_t __b, int32x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_laneqv2si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshq_laneq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_laneqv8hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshq_laneq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_laneqv4si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlah_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
++{
++  return  __builtin_aarch64_sqrdmlah_lanev4hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlah_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_lanev2si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_lanev8hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_lanev4si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahh_s16 (int16_t __a, int16_t __b, int16_t __c)
++{
++  return (int16_t) __builtin_aarch64_sqrdmlahhi (__a, __b, __c);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahh_lane_s16 (int16_t __a, int16_t __b, int16x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_lanehi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahh_laneq_s16 (int16_t __a, int16_t __b, int16x8_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_laneqhi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahs_s32 (int32_t __a, int32_t __b, int32_t __c)
++{
++  return (int32_t) __builtin_aarch64_sqrdmlahsi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahs_lane_s32 (int32_t __a, int32_t __b, int32x2_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_lanesi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlahs_laneq_s32 (int32_t __a, int32_t __b, int32x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlah_laneqsi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlsh_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
++{
++  return  __builtin_aarch64_sqrdmlsh_lanev4hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlsh_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_lanev2si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_lanev8hi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_lanev4si (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshh_s16 (int16_t __a, int16_t __b, int16_t __c)
++{
++  return (int16_t) __builtin_aarch64_sqrdmlshhi (__a, __b, __c);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshh_lane_s16 (int16_t __a, int16_t __b, int16x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_lanehi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshh_laneq_s16 (int16_t __a, int16_t __b, int16x8_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_laneqhi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshs_s32 (int32_t __a, int32_t __b, int32_t __c)
++{
++  return (int32_t) __builtin_aarch64_sqrdmlshsi (__a, __b, __c);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshs_lane_s32 (int32_t __a, int32_t __b, int32x2_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_lanesi (__a, __b, __c, __d);
++}
++
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmlshs_laneq_s32 (int32_t __a, int32_t __b, int32x4_t __c, const int __d)
++{
++  return __builtin_aarch64_sqrdmlsh_laneqsi (__a, __b, __c, __d);
++}
++#pragma GCC pop_options
++
++#pragma GCC push_options
++#pragma GCC target ("+nothing+crypto")
++/* vaes  */
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaeseq_u8 (uint8x16_t data, uint8x16_t key)
+ {
+-  uint16x4_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __builtin_aarch64_crypto_aesev16qi_uuu (data, key);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmvn_u32 (uint32x2_t a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaesdq_u8 (uint8x16_t data, uint8x16_t key)
+ {
+-  uint32x2_t result;
+-  __asm__ ("mvn %0.8b,%1.8b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __builtin_aarch64_crypto_aesdv16qi_uuu (data, key);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vmvnq_p8 (poly8x16_t a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaesmcq_u8 (uint8x16_t data)
+ {
+-  poly8x16_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __builtin_aarch64_crypto_aesmcv16qi_uu (data);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vmvnq_s8 (int8x16_t a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaesimcq_u8 (uint8x16_t data)
+ {
+-  int8x16_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __builtin_aarch64_crypto_aesimcv16qi_uu (data);
+ }
++#pragma GCC pop_options
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmvnq_s16 (int16x8_t a)
++/* vcage  */
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcage_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  int16x8_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return vabs_f64 (__a) >= vabs_f64 (__b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmvnq_s32 (int32x4_t a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcages_f32 (float32_t __a, float32_t __b)
+ {
+-  int32x4_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __builtin_fabsf (__a) >= __builtin_fabsf (__b) ? -1 : 0;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vmvnq_u8 (uint8x16_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcage_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  uint8x16_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return vabs_f32 (__a) >= vabs_f32 (__b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmvnq_u16 (uint16x8_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcageq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  uint16x8_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return vabsq_f32 (__a) >= vabsq_f32 (__b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmvnq_u32 (uint32x4_t a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaged_f64 (float64_t __a, float64_t __b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("mvn %0.16b,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __builtin_fabs (__a) >= __builtin_fabs (__b) ? -1 : 0;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcageq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return vabsq_f64 (__a) >= vabsq_f64 (__b);
+ }
+ 
++/* vcagt  */
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vpadal_s8 (int16x4_t a, int8x8_t b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagts_f32 (float32_t __a, float32_t __b)
++{
++  return __builtin_fabsf (__a) > __builtin_fabsf (__b) ? -1 : 0;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagt_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return vabs_f32 (__a) > vabs_f32 (__b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagt_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return vabs_f64 (__a) > vabs_f64 (__b);
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagtq_f32 (float32x4_t __a, float32x4_t __b)
++{
++  return vabsq_f32 (__a) > vabsq_f32 (__b);
++}
++
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagtd_f64 (float64_t __a, float64_t __b)
++{
++  return __builtin_fabs (__a) > __builtin_fabs (__b) ? -1 : 0;
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagtq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return vabsq_f64 (__a) > vabsq_f64 (__b);
++}
++
++/* vcale  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcale_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return vabs_f32 (__a) <= vabs_f32 (__b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcale_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return vabs_f64 (__a) <= vabs_f64 (__b);
++}
++
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaled_f64 (float64_t __a, float64_t __b)
++{
++  return __builtin_fabs (__a) <= __builtin_fabs (__b) ? -1 : 0;
++}
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcales_f32 (float32_t __a, float32_t __b)
++{
++  return __builtin_fabsf (__a) <= __builtin_fabsf (__b) ? -1 : 0;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaleq_f32 (float32x4_t __a, float32x4_t __b)
++{
++  return vabsq_f32 (__a) <= vabsq_f32 (__b);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaleq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return vabsq_f64 (__a) <= vabsq_f64 (__b);
++}
++
++/* vcalt  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcalt_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return vabs_f32 (__a) < vabs_f32 (__b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcalt_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return vabs_f64 (__a) < vabs_f64 (__b);
++}
++
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaltd_f64 (float64_t __a, float64_t __b)
++{
++  return __builtin_fabs (__a) < __builtin_fabs (__b) ? -1 : 0;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaltq_f32 (float32x4_t __a, float32x4_t __b)
++{
++  return vabsq_f32 (__a) < vabsq_f32 (__b);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaltq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return vabsq_f64 (__a) < vabsq_f64 (__b);
++}
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcalts_f32 (float32_t __a, float32_t __b)
++{
++  return __builtin_fabsf (__a) < __builtin_fabsf (__b) ? -1 : 0;
++}
++
++/* vceq - vector.  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return (uint32x2_t) (__a == __b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return (uint64x1_t) (__a == __b);
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_p8 (poly8x8_t __a, poly8x8_t __b)
++{
++  return (uint8x8_t) (__a == __b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_p64 (poly64x1_t __a, poly64x1_t __b)
++{
++  return (uint64x1_t) (__a == __b);
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_s8 (int8x8_t __a, int8x8_t __b)
++{
++  return (uint8x8_t) (__a == __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_s16 (int16x4_t __a, int16x4_t __b)
++{
++  return (uint16x4_t) (__a == __b);
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_s32 (int32x2_t __a, int32x2_t __b)
++{
++  return (uint32x2_t) (__a == __b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_s64 (int64x1_t __a, int64x1_t __b)
++{
++  return (uint64x1_t) (__a == __b);
++}
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_u8 (uint8x8_t __a, uint8x8_t __b)
++{
++  return (__a == __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_u16 (uint16x4_t __a, uint16x4_t __b)
++{
++  return (__a == __b);
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_u32 (uint32x2_t __a, uint32x2_t __b)
++{
++  return (__a == __b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_u64 (uint64x1_t __a, uint64x1_t __b)
++{
++  return (__a == __b);
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_f32 (float32x4_t __a, float32x4_t __b)
++{
++  return (uint32x4_t) (__a == __b);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return (uint64x2_t) (__a == __b);
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_p8 (poly8x16_t __a, poly8x16_t __b)
++{
++  return (uint8x16_t) (__a == __b);
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_s8 (int8x16_t __a, int8x16_t __b)
++{
++  return (uint8x16_t) (__a == __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  int16x4_t result;
+-  __asm__ ("sadalp %0.4h,%2.8b"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x8_t) (__a == __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vpadal_s16 (int32x2_t a, int16x4_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  int32x2_t result;
+-  __asm__ ("sadalp %0.2s,%2.4h"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a == __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vpadal_s32 (int64x1_t a, int32x2_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  int64x1_t result;
+-  __asm__ ("sadalp %0.1d,%2.2s"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a == __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vpadal_u8 (uint16x4_t a, uint8x8_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  uint16x4_t result;
+-  __asm__ ("uadalp %0.4h,%2.8b"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vpadal_u16 (uint32x2_t a, uint16x4_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  uint32x2_t result;
+-  __asm__ ("uadalp %0.2s,%2.4h"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vpadal_u32 (uint64x1_t a, uint32x2_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  uint64x1_t result;
+-  __asm__ ("uadalp %0.1d,%2.2s"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vpadalq_s8 (int16x8_t a, int8x16_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+-  int16x8_t result;
+-  __asm__ ("sadalp %0.8h,%2.16b"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vpadalq_s16 (int32x4_t a, int16x8_t b)
++/* vceq - scalar.  */
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqs_f32 (float32_t __a, float32_t __b)
+ {
+-  int32x4_t result;
+-  __asm__ ("sadalp %0.4s,%2.8h"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == __b ? -1 : 0;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vpadalq_s32 (int64x2_t a, int32x4_t b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqd_s64 (int64_t __a, int64_t __b)
+ {
+-  int64x2_t result;
+-  __asm__ ("sadalp %0.2d,%2.4s"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vpadalq_u8 (uint16x8_t a, uint8x16_t b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqd_u64 (uint64_t __a, uint64_t __b)
+ {
+-  uint16x8_t result;
+-  __asm__ ("uadalp %0.8h,%2.16b"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vpadalq_u16 (uint32x4_t a, uint16x8_t b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqd_f64 (float64_t __a, float64_t __b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("uadalp %0.4s,%2.8h"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vpadalq_u32 (uint64x2_t a, uint32x4_t b)
++/* vceqz - vector.  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_f32 (float32x2_t __a)
+ {
+-  uint64x2_t result;
+-  __asm__ ("uadalp %0.2d,%2.4s"
+-           : "=w"(result)
+-           : "0"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x2_t) (__a == 0.0f);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vpadd_f32 (float32x2_t a, float32x2_t b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_f64 (float64x1_t __a)
+ {
+-  float32x2_t result;
+-  __asm__ ("faddp %0.2s,%1.2s,%2.2s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x1_t) (__a == (float64x1_t) {0.0});
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vpaddl_s8 (int8x8_t a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_p8 (poly8x8_t __a)
+ {
+-  int16x4_t result;
+-  __asm__ ("saddlp %0.4h,%1.8b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x8_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vpaddl_s16 (int16x4_t a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_s8 (int8x8_t __a)
+ {
+-  int32x2_t result;
+-  __asm__ ("saddlp %0.2s,%1.4h"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x8_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vpaddl_s32 (int32x2_t a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_s16 (int16x4_t __a)
+ {
+-  int64x1_t result;
+-  __asm__ ("saddlp %0.1d,%1.2s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x4_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vpaddl_u8 (uint8x8_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_s32 (int32x2_t __a)
+ {
+-  uint16x4_t result;
+-  __asm__ ("uaddlp %0.4h,%1.8b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x2_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vpaddl_u16 (uint16x4_t a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_s64 (int64x1_t __a)
+ {
+-  uint32x2_t result;
+-  __asm__ ("uaddlp %0.2s,%1.4h"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x1_t) (__a == __AARCH64_INT64_C (0));
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vpaddl_u32 (uint32x2_t a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_u8 (uint8x8_t __a)
+ {
+-  uint64x1_t result;
+-  __asm__ ("uaddlp %0.1d,%1.2s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == 0);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vpaddlq_s8 (int8x16_t a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_u16 (uint16x4_t __a)
+ {
+-  int16x8_t result;
+-  __asm__ ("saddlp %0.8h,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == 0);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vpaddlq_s16 (int16x8_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_u32 (uint32x2_t __a)
+ {
+-  int32x4_t result;
+-  __asm__ ("saddlp %0.4s,%1.8h"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == 0);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vpaddlq_s32 (int32x4_t a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_u64 (uint64x1_t __a)
+ {
+-  int64x2_t result;
+-  __asm__ ("saddlp %0.2d,%1.4s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == __AARCH64_UINT64_C (0));
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vpaddlq_u8 (uint8x16_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_f32 (float32x4_t __a)
+ {
+-  uint16x8_t result;
+-  __asm__ ("uaddlp %0.8h,%1.16b"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a == 0.0f);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vpaddlq_u16 (uint16x8_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_f64 (float64x2_t __a)
+ {
+-  uint32x4_t result;
+-  __asm__ ("uaddlp %0.4s,%1.8h"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a == 0.0f);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vpaddlq_u32 (uint32x4_t a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_p8 (poly8x16_t __a)
+ {
+-  uint64x2_t result;
+-  __asm__ ("uaddlp %0.2d,%1.4s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x16_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vpaddq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_s8 (int8x16_t __a)
+ {
+-  float32x4_t result;
+-  __asm__ ("faddp %0.4s,%1.4s,%2.4s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x16_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vpaddq_f64 (float64x2_t a, float64x2_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_s16 (int16x8_t __a)
+ {
+-  float64x2_t result;
+-  __asm__ ("faddp %0.2d,%1.2d,%2.2d"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x8_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vpaddq_s8 (int8x16_t a, int8x16_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_s32 (int32x4_t __a)
+ {
+-  int8x16_t result;
+-  __asm__ ("addp %0.16b,%1.16b,%2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a == 0);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vpaddq_s16 (int16x8_t a, int16x8_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_s64 (int64x2_t __a)
+ {
+-  int16x8_t result;
+-  __asm__ ("addp %0.8h,%1.8h,%2.8h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a == __AARCH64_INT64_C (0));
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vpaddq_s32 (int32x4_t a, int32x4_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_u8 (uint8x16_t __a)
+ {
+-  int32x4_t result;
+-  __asm__ ("addp %0.4s,%1.4s,%2.4s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == 0);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vpaddq_s64 (int64x2_t a, int64x2_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_u16 (uint16x8_t __a)
+ {
+-  int64x2_t result;
+-  __asm__ ("addp %0.2d,%1.2d,%2.2d"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == 0);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vpaddq_u8 (uint8x16_t a, uint8x16_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_u32 (uint32x4_t __a)
+ {
+-  uint8x16_t result;
+-  __asm__ ("addp %0.16b,%1.16b,%2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == 0);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vpaddq_u16 (uint16x8_t a, uint16x8_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_u64 (uint64x2_t __a)
+ {
+-  uint16x8_t result;
+-  __asm__ ("addp %0.8h,%1.8h,%2.8h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a == __AARCH64_UINT64_C (0));
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vpaddq_u32 (uint32x4_t a, uint32x4_t b)
++/* vceqz - scalar.  */
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzs_f32 (float32_t __a)
+ {
+-  uint32x4_t result;
+-  __asm__ ("addp %0.4s,%1.4s,%2.4s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == 0.0f ? -1 : 0;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vpaddq_u64 (uint64x2_t a, uint64x2_t b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzd_s64 (int64_t __a)
+ {
+-  uint64x2_t result;
+-  __asm__ ("addp %0.2d,%1.2d,%2.2d"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == 0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vpadds_f32 (float32x2_t a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzd_u64 (uint64_t __a)
+ {
+-  float32_t result;
+-  __asm__ ("faddp %s0,%1.2s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return __a == 0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqdmulh_n_s16 (int16x4_t a, int16_t b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzd_f64 (float64_t __a)
+ {
+-  int16x4_t result;
+-  __asm__ ("sqdmulh %0.4h,%1.4h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
++  return __a == 0.0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqdmulh_n_s32 (int32x2_t a, int32_t b)
++/* vcge - vector.  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  int32x2_t result;
+-  __asm__ ("sqdmulh %0.2s,%1.2s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x2_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqdmulhq_n_s16 (int16x8_t a, int16_t b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  int16x8_t result;
+-  __asm__ ("sqdmulh %0.8h,%1.8h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x1_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmulhq_n_s32 (int32x4_t a, int32_t b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  int32x4_t result;
+-  __asm__ ("sqdmulh %0.4s,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x8_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqmovn_high_s16 (int8x8_t a, int16x8_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("sqxtn2 %0.16b, %1.8h"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x4_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqmovn_high_s32 (int16x4_t a, int32x4_t b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("sqxtn2 %0.8h, %1.4s"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x2_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqmovn_high_s64 (int32x2_t a, int64x2_t b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("sqxtn2 %0.4s, %1.2d"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x1_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqmovn_high_u16 (uint8x8_t a, uint16x8_t b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("uqxtn2 %0.16b, %1.8h"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a >= __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vqmovn_high_u32 (uint16x4_t a, uint32x4_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("uqxtn2 %0.8h, %1.4s"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a >= __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vqmovn_high_u64 (uint32x2_t a, uint64x2_t b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("uqxtn2 %0.4s, %1.2d"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a >= __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqmovun_high_s16 (uint8x8_t a, int16x8_t b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+-  uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("sqxtun2 %0.16b, %1.8h"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a >= __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vqmovun_high_s32 (uint16x4_t a, int32x4_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("sqxtun2 %0.8h, %1.4s"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vqmovun_high_s64 (uint32x2_t a, int64x2_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("sqxtun2 %0.4s, %1.2d"
+-           : "+w"(result)
+-           : "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmulh_n_s16 (int16x4_t a, int16_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  int16x4_t result;
+-  __asm__ ("sqrdmulh %0.4h,%1.4h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x16_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmulh_n_s32 (int32x2_t a, int32_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  int32x2_t result;
+-  __asm__ ("sqrdmulh %0.2s,%1.2s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x8_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmulhq_n_s16 (int16x8_t a, int16_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  int16x8_t result;
+-  __asm__ ("sqrdmulh %0.8h,%1.8h,%2.h[0]"
+-           : "=w"(result)
+-           : "w"(a), "x"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a >= __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmulhq_n_s32 (int32x4_t a, int32_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  int32x4_t result;
+-  __asm__ ("sqrdmulh %0.4s,%1.4s,%2.s[0]"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a >= __b);
+ }
+ 
+-#define vqrshrn_high_n_s16(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       int8x8_t a_ = (a);                                               \
+-       int8x16_t result = vcombine_s8                                   \
+-                            (a_, vcreate_s8                             \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("sqrshrn2 %0.16b, %1.8h, #%2"                           \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_u8 (uint8x16_t __a, uint8x16_t __b)
++{
++  return (__a >= __b);
++}
+ 
+-#define vqrshrn_high_n_s32(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       int16x4_t a_ = (a);                                              \
+-       int16x8_t result = vcombine_s16                                  \
+-                            (a_, vcreate_s16                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("sqrshrn2 %0.8h, %1.4s, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_u16 (uint16x8_t __a, uint16x8_t __b)
++{
++  return (__a >= __b);
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_u32 (uint32x4_t __a, uint32x4_t __b)
++{
++  return (__a >= __b);
++}
+ 
+-#define vqrshrn_high_n_s64(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t b_ = (b);                                              \
+-       int32x2_t a_ = (a);                                              \
+-       int32x4_t result = vcombine_s32                                  \
+-                            (a_, vcreate_s32                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("sqrshrn2 %0.4s, %1.2d, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_u64 (uint64x2_t __a, uint64x2_t __b)
++{
++  return (__a >= __b);
++}
+ 
+-#define vqrshrn_high_n_u16(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t b_ = (b);                                             \
+-       uint8x8_t a_ = (a);                                              \
+-       uint8x16_t result = vcombine_u8                                  \
+-                             (a_, vcreate_u8                            \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("uqrshrn2 %0.16b, %1.8h, #%2"                           \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++/* vcge - scalar.  */
+ 
+-#define vqrshrn_high_n_u32(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t b_ = (b);                                             \
+-       uint16x4_t a_ = (a);                                             \
+-       uint16x8_t result = vcombine_u16                                 \
+-                             (a_, vcreate_u16                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("uqrshrn2 %0.8h, %1.4s, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcges_f32 (float32_t __a, float32_t __b)
++{
++  return __a >= __b ? -1 : 0;
++}
+ 
+-#define vqrshrn_high_n_u64(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64x2_t b_ = (b);                                             \
+-       uint32x2_t a_ = (a);                                             \
+-       uint32x4_t result = vcombine_u32                                 \
+-                             (a_, vcreate_u32                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("uqrshrn2 %0.4s, %1.2d, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcged_s64 (int64_t __a, int64_t __b)
++{
++  return __a >= __b ? -1ll : 0ll;
++}
+ 
+-#define vqrshrun_high_n_s16(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       uint8x8_t a_ = (a);                                              \
+-       uint8x16_t result = vcombine_u8                                  \
+-                             (a_, vcreate_u8                            \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("sqrshrun2 %0.16b, %1.8h, #%2"                          \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcged_u64 (uint64_t __a, uint64_t __b)
++{
++  return __a >= __b ? -1ll : 0ll;
++}
+ 
+-#define vqrshrun_high_n_s32(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       uint16x4_t a_ = (a);                                             \
+-       uint16x8_t result = vcombine_u16                                 \
+-                             (a_, vcreate_u16                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("sqrshrun2 %0.8h, %1.4s, #%2"                           \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcged_f64 (float64_t __a, float64_t __b)
++{
++  return __a >= __b ? -1ll : 0ll;
++}
+ 
+-#define vqrshrun_high_n_s64(a, b, c)                                    \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t b_ = (b);                                              \
+-       uint32x2_t a_ = (a);                                             \
+-       uint32x4_t result = vcombine_u32                                 \
+-                             (a_, vcreate_u32                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("sqrshrun2 %0.4s, %1.2d, #%2"                           \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++/* vcgez - vector.  */
+ 
+-#define vqshrn_high_n_s16(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       int8x8_t a_ = (a);                                               \
+-       int8x16_t result = vcombine_s8                                   \
+-                            (a_, vcreate_s8                             \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("sqshrn2 %0.16b, %1.8h, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_f32 (float32x2_t __a)
++{
++  return (uint32x2_t) (__a >= 0.0f);
++}
+ 
+-#define vqshrn_high_n_s32(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       int16x4_t a_ = (a);                                              \
+-       int16x8_t result = vcombine_s16                                  \
+-                            (a_, vcreate_s16                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("sqshrn2 %0.8h, %1.4s, #%2"                             \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_f64 (float64x1_t __a)
++{
++  return (uint64x1_t) (__a[0] >= (float64x1_t) {0.0});
++}
+ 
+-#define vqshrn_high_n_s64(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t b_ = (b);                                              \
+-       int32x2_t a_ = (a);                                              \
+-       int32x4_t result = vcombine_s32                                  \
+-                            (a_, vcreate_s32                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("sqshrn2 %0.4s, %1.2d, #%2"                             \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_s8 (int8x8_t __a)
++{
++  return (uint8x8_t) (__a >= 0);
++}
+ 
+-#define vqshrn_high_n_u16(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t b_ = (b);                                             \
+-       uint8x8_t a_ = (a);                                              \
+-       uint8x16_t result = vcombine_u8                                  \
+-                             (a_, vcreate_u8                            \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("uqshrn2 %0.16b, %1.8h, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_s16 (int16x4_t __a)
++{
++  return (uint16x4_t) (__a >= 0);
++}
+ 
+-#define vqshrn_high_n_u32(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t b_ = (b);                                             \
+-       uint16x4_t a_ = (a);                                             \
+-       uint16x8_t result = vcombine_u16                                 \
+-                             (a_, vcreate_u16                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("uqshrn2 %0.8h, %1.4s, #%2"                             \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_s32 (int32x2_t __a)
++{
++  return (uint32x2_t) (__a >= 0);
++}
+ 
+-#define vqshrn_high_n_u64(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64x2_t b_ = (b);                                             \
+-       uint32x2_t a_ = (a);                                             \
+-       uint32x4_t result = vcombine_u32                                 \
+-                             (a_, vcreate_u32                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("uqshrn2 %0.4s, %1.2d, #%2"                             \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_s64 (int64x1_t __a)
++{
++  return (uint64x1_t) (__a >= __AARCH64_INT64_C (0));
++}
+ 
+-#define vqshrun_high_n_s16(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       uint8x8_t a_ = (a);                                              \
+-       uint8x16_t result = vcombine_u8                                  \
+-                             (a_, vcreate_u8                            \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("sqshrun2 %0.16b, %1.8h, #%2"                           \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_f32 (float32x4_t __a)
++{
++  return (uint32x4_t) (__a >= 0.0f);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_f64 (float64x2_t __a)
++{
++  return (uint64x2_t) (__a >= 0.0);
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_s8 (int8x16_t __a)
++{
++  return (uint8x16_t) (__a >= 0);
++}
+ 
+-#define vqshrun_high_n_s32(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       uint16x4_t a_ = (a);                                             \
+-       uint16x8_t result = vcombine_u16                                 \
+-                             (a_, vcreate_u16                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("sqshrun2 %0.8h, %1.4s, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_s16 (int16x8_t __a)
++{
++  return (uint16x8_t) (__a >= 0);
++}
+ 
+-#define vqshrun_high_n_s64(a, b, c)                                     \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t b_ = (b);                                              \
+-       uint32x2_t a_ = (a);                                             \
+-       uint32x4_t result = vcombine_u32                                 \
+-                             (a_, vcreate_u32                           \
+-                                    (__AARCH64_UINT64_C (0x0)));        \
+-       __asm__ ("sqshrun2 %0.4s, %1.2d, #%2"                            \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_s32 (int32x4_t __a)
++{
++  return (uint32x4_t) (__a >= 0);
++}
+ 
+-#define vrshrn_high_n_s16(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       int8x8_t a_ = (a);                                               \
+-       int8x16_t result = vcombine_s8                                   \
+-                            (a_, vcreate_s8                             \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("rshrn2 %0.16b,%1.8h,#%2"                               \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_s64 (int64x2_t __a)
++{
++  return (uint64x2_t) (__a >= __AARCH64_INT64_C (0));
++}
+ 
+-#define vrshrn_high_n_s32(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       int16x4_t a_ = (a);                                              \
+-       int16x8_t result = vcombine_s16                                  \
+-                            (a_, vcreate_s16                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("rshrn2 %0.8h,%1.4s,#%2"                                \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++/* vcgez - scalar.  */
+ 
+-#define vrshrn_high_n_s64(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t b_ = (b);                                              \
+-       int32x2_t a_ = (a);                                              \
+-       int32x4_t result = vcombine_s32                                  \
+-                            (a_, vcreate_s32                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("rshrn2 %0.4s,%1.2d,#%2"                                \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezs_f32 (float32_t __a)
++{
++  return __a >= 0.0f ? -1 : 0;
++}
+ 
+-#define vrshrn_high_n_u16(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t b_ = (b);                                             \
+-       uint8x8_t a_ = (a);                                              \
+-       uint8x16_t result = vcombine_u8                                  \
+-                            (a_, vcreate_u8                             \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("rshrn2 %0.16b,%1.8h,#%2"                               \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezd_s64 (int64_t __a)
++{
++  return __a >= 0 ? -1ll : 0ll;
++}
+ 
+-#define vrshrn_high_n_u32(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t b_ = (b);                                             \
+-       uint16x4_t a_ = (a);                                             \
+-       uint16x8_t result = vcombine_u16                                 \
+-                            (a_, vcreate_u16                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("rshrn2 %0.8h,%1.4s,#%2"                                \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezd_f64 (float64_t __a)
++{
++  return __a >= 0.0 ? -1ll : 0ll;
++}
+ 
+-#define vrshrn_high_n_u64(a, b, c)                                      \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64x2_t b_ = (b);                                             \
+-       uint32x2_t a_ = (a);                                             \
+-       uint32x4_t result = vcombine_u32                                 \
+-                            (a_, vcreate_u32                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("rshrn2 %0.4s,%1.2d,#%2"                                \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++/* vcgt - vector.  */
+ 
+-#define vrshrn_n_s16(a, b)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t a_ = (a);                                              \
+-       int8x8_t result;                                                 \
+-       __asm__ ("rshrn %0.8b,%1.8h,%2"                                  \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return (uint32x2_t) (__a > __b);
++}
+ 
+-#define vrshrn_n_s32(a, b)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t a_ = (a);                                              \
+-       int16x4_t result;                                                \
+-       __asm__ ("rshrn %0.4h,%1.4s,%2"                                  \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return (uint64x1_t) (__a > __b);
++}
+ 
+-#define vrshrn_n_s64(a, b)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t a_ = (a);                                              \
+-       int32x2_t result;                                                \
+-       __asm__ ("rshrn %0.2s,%1.2d,%2"                                  \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_s8 (int8x8_t __a, int8x8_t __b)
++{
++  return (uint8x8_t) (__a > __b);
++}
+ 
+-#define vrshrn_n_u16(a, b)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t a_ = (a);                                             \
+-       uint8x8_t result;                                                \
+-       __asm__ ("rshrn %0.8b,%1.8h,%2"                                  \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_s16 (int16x4_t __a, int16x4_t __b)
++{
++  return (uint16x4_t) (__a > __b);
++}
+ 
+-#define vrshrn_n_u32(a, b)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t a_ = (a);                                             \
+-       uint16x4_t result;                                               \
+-       __asm__ ("rshrn %0.4h,%1.4s,%2"                                  \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_s32 (int32x2_t __a, int32x2_t __b)
++{
++  return (uint32x2_t) (__a > __b);
++}
+ 
+-#define vrshrn_n_u64(a, b)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64x2_t a_ = (a);                                             \
+-       uint32x2_t result;                                               \
+-       __asm__ ("rshrn %0.2s,%1.2d,%2"                                  \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_s64 (int64x1_t __a, int64x1_t __b)
++{
++  return (uint64x1_t) (__a > __b);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrsqrte_f32 (float32x2_t a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  float32x2_t result;
+-  __asm__ ("frsqrte %0.2s,%1.2s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrsqrte_f64 (float64x1_t a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  float64x1_t result;
+-  __asm__ ("frsqrte %d0,%d1"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vrsqrte_u32 (uint32x2_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  uint32x2_t result;
+-  __asm__ ("ursqrte %0.2s,%1.2s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_u64 (uint64x1_t __a, uint64x1_t __b)
++{
++  return (__a > __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vrsqrted_f64 (float64_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  float64_t result;
+-  __asm__ ("frsqrte %d0,%d1"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a > __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrsqrteq_f32 (float32x4_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  float32x4_t result;
+-  __asm__ ("frsqrte %0.4s,%1.4s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a > __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrsqrteq_f64 (float64x2_t a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  float64x2_t result;
+-  __asm__ ("frsqrte %0.2d,%1.2d"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x16_t) (__a > __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vrsqrteq_u32 (uint32x4_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  uint32x4_t result;
+-  __asm__ ("ursqrte %0.4s,%1.4s"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x8_t) (__a > __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vrsqrtes_f32 (float32_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  float32_t result;
+-  __asm__ ("frsqrte %s0,%s1"
+-           : "=w"(result)
+-           : "w"(a)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a > __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrsqrts_f32 (float32x2_t a, float32x2_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  float32x2_t result;
+-  __asm__ ("frsqrts %0.2s,%1.2s,%2.2s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a > __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vrsqrtsd_f64 (float64_t a, float64_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  float64_t result;
+-  __asm__ ("frsqrts %d0,%d1,%d2"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrsqrtsq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  float32x4_t result;
+-  __asm__ ("frsqrts %0.4s,%1.4s,%2.4s"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrsqrtsq_f64 (float64x2_t a, float64x2_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  float64x2_t result;
+-  __asm__ ("frsqrts %0.2d,%1.2d,%2.2d"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vrsqrtss_f32 (float32_t a, float32_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+-  float32_t result;
+-  __asm__ ("frsqrts %s0,%s1,%s2"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (__a > __b);
+ }
+ 
+-#define vshrn_high_n_s16(a, b, c)                                       \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t b_ = (b);                                              \
+-       int8x8_t a_ = (a);                                               \
+-       int8x16_t result = vcombine_s8                                   \
+-                            (a_, vcreate_s8                             \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("shrn2 %0.16b,%1.8h,#%2"                                \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vshrn_high_n_s32(a, b, c)                                       \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t b_ = (b);                                              \
+-       int16x4_t a_ = (a);                                              \
+-       int16x8_t result = vcombine_s16                                  \
+-                            (a_, vcreate_s16                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("shrn2 %0.8h,%1.4s,#%2"                                 \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vshrn_high_n_s64(a, b, c)                                       \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t b_ = (b);                                              \
+-       int32x2_t a_ = (a);                                              \
+-       int32x4_t result = vcombine_s32                                  \
+-                            (a_, vcreate_s32                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("shrn2 %0.4s,%1.2d,#%2"                                 \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vshrn_high_n_u16(a, b, c)                                       \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t b_ = (b);                                             \
+-       uint8x8_t a_ = (a);                                              \
+-       uint8x16_t result = vcombine_u8                                  \
+-                            (a_, vcreate_u8                             \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("shrn2 %0.16b,%1.8h,#%2"                                \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vshrn_high_n_u32(a, b, c)                                       \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t b_ = (b);                                             \
+-       uint16x4_t a_ = (a);                                             \
+-       uint16x8_t result = vcombine_u16                                 \
+-                            (a_, vcreate_u16                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("shrn2 %0.8h,%1.4s,#%2"                                 \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vshrn_high_n_u64(a, b, c)                                       \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64x2_t b_ = (b);                                             \
+-       uint32x2_t a_ = (a);                                             \
+-       uint32x4_t result = vcombine_u32                                 \
+-                            (a_, vcreate_u32                            \
+-                                   (__AARCH64_UINT64_C (0x0)));         \
+-       __asm__ ("shrn2 %0.4s,%1.2d,#%2"                                 \
+-                : "+w"(result)                                          \
+-                : "w"(b_), "i"(c)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
+-
+-#define vshrn_n_s16(a, b)                                               \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int16x8_t a_ = (a);                                              \
+-       int8x8_t result;                                                 \
+-       __asm__ ("shrn %0.8b,%1.8h,%2"                                   \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++/* vcgt - scalar.  */
+ 
+-#define vshrn_n_s32(a, b)                                               \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int32x4_t a_ = (a);                                              \
+-       int16x4_t result;                                                \
+-       __asm__ ("shrn %0.4h,%1.4s,%2"                                   \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgts_f32 (float32_t __a, float32_t __b)
++{
++  return __a > __b ? -1 : 0;
++}
+ 
+-#define vshrn_n_s64(a, b)                                               \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       int64x2_t a_ = (a);                                              \
+-       int32x2_t result;                                                \
+-       __asm__ ("shrn %0.2s,%1.2d,%2"                                   \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtd_s64 (int64_t __a, int64_t __b)
++{
++  return __a > __b ? -1ll : 0ll;
++}
+ 
+-#define vshrn_n_u16(a, b)                                               \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint16x8_t a_ = (a);                                             \
+-       uint8x8_t result;                                                \
+-       __asm__ ("shrn %0.8b,%1.8h,%2"                                   \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtd_u64 (uint64_t __a, uint64_t __b)
++{
++  return __a > __b ? -1ll : 0ll;
++}
+ 
+-#define vshrn_n_u32(a, b)                                               \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint32x4_t a_ = (a);                                             \
+-       uint16x4_t result;                                               \
+-       __asm__ ("shrn %0.4h,%1.4s,%2"                                   \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtd_f64 (float64_t __a, float64_t __b)
++{
++  return __a > __b ? -1ll : 0ll;
++}
+ 
+-#define vshrn_n_u64(a, b)                                               \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       uint64x2_t a_ = (a);                                             \
+-       uint32x2_t result;                                               \
+-       __asm__ ("shrn %0.2s,%1.2d,%2"                                   \
+-                : "=w"(result)                                          \
+-                : "w"(a_), "i"(b)                                       \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++/* vcgtz - vector.  */
+ 
+-#define vsli_n_p8(a, b, c)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly8x8_t b_ = (b);                                              \
+-       poly8x8_t a_ = (a);                                              \
+-       poly8x8_t result;                                                \
+-       __asm__ ("sli %0.8b,%2.8b,%3"                                    \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_f32 (float32x2_t __a)
++{
++  return (uint32x2_t) (__a > 0.0f);
++}
+ 
+-#define vsli_n_p16(a, b, c)                                             \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly16x4_t b_ = (b);                                             \
+-       poly16x4_t a_ = (a);                                             \
+-       poly16x4_t result;                                               \
+-       __asm__ ("sli %0.4h,%2.4h,%3"                                    \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_f64 (float64x1_t __a)
++{
++  return (uint64x1_t) (__a > (float64x1_t) {0.0});
++}
+ 
+-#define vsliq_n_p8(a, b, c)                                             \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly8x16_t b_ = (b);                                             \
+-       poly8x16_t a_ = (a);                                             \
+-       poly8x16_t result;                                               \
+-       __asm__ ("sli %0.16b,%2.16b,%3"                                  \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_s8 (int8x8_t __a)
++{
++  return (uint8x8_t) (__a > 0);
++}
+ 
+-#define vsliq_n_p16(a, b, c)                                            \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly16x8_t b_ = (b);                                             \
+-       poly16x8_t a_ = (a);                                             \
+-       poly16x8_t result;                                               \
+-       __asm__ ("sli %0.8h,%2.8h,%3"                                    \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_s16 (int16x4_t __a)
++{
++  return (uint16x4_t) (__a > 0);
++}
+ 
+-#define vsri_n_p8(a, b, c)                                              \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly8x8_t b_ = (b);                                              \
+-       poly8x8_t a_ = (a);                                              \
+-       poly8x8_t result;                                                \
+-       __asm__ ("sri %0.8b,%2.8b,%3"                                    \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_s32 (int32x2_t __a)
++{
++  return (uint32x2_t) (__a > 0);
++}
+ 
+-#define vsri_n_p16(a, b, c)                                             \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly16x4_t b_ = (b);                                             \
+-       poly16x4_t a_ = (a);                                             \
+-       poly16x4_t result;                                               \
+-       __asm__ ("sri %0.4h,%2.4h,%3"                                    \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_s64 (int64x1_t __a)
++{
++  return (uint64x1_t) (__a > __AARCH64_INT64_C (0));
++}
+ 
+-#define vsriq_n_p8(a, b, c)                                             \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly8x16_t b_ = (b);                                             \
+-       poly8x16_t a_ = (a);                                             \
+-       poly8x16_t result;                                               \
+-       __asm__ ("sri %0.16b,%2.16b,%3"                                  \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_f32 (float32x4_t __a)
++{
++  return (uint32x4_t) (__a > 0.0f);
++}
+ 
+-#define vsriq_n_p16(a, b, c)                                            \
+-  __extension__                                                         \
+-    ({                                                                  \
+-       poly16x8_t b_ = (b);                                             \
+-       poly16x8_t a_ = (a);                                             \
+-       poly16x8_t result;                                               \
+-       __asm__ ("sri %0.8h,%2.8h,%3"                                    \
+-                : "=w"(result)                                          \
+-                : "0"(a_), "w"(b_), "i"(c)                              \
+-                : /* No clobbers */);                                   \
+-       result;                                                          \
+-     })
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_f64 (float64x2_t __a)
++{
++    return (uint64x2_t) (__a > 0.0);
++}
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtst_p8 (poly8x8_t a, poly8x8_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_s8 (int8x16_t __a)
+ {
+-  uint8x8_t result;
+-  __asm__ ("cmtst %0.8b, %1.8b, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x16_t) (__a > 0);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vtst_p16 (poly16x4_t a, poly16x4_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_s16 (int16x8_t __a)
+ {
+-  uint16x4_t result;
+-  __asm__ ("cmtst %0.4h, %1.4h, %2.4h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x8_t) (__a > 0);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vtstq_p8 (poly8x16_t a, poly8x16_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_s32 (int32x4_t __a)
+ {
+-  uint8x16_t result;
+-  __asm__ ("cmtst %0.16b, %1.16b, %2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a > 0);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vtstq_p16 (poly16x8_t a, poly16x8_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_s64 (int64x2_t __a)
+ {
+-  uint16x8_t result;
+-  __asm__ ("cmtst %0.8h, %1.8h, %2.8h"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a > __AARCH64_INT64_C (0));
+ }
+ 
+-/* End of temporary inline asm implementations.  */
++/* vcgtz - scalar.  */
+ 
+-/* Start of temporary inline asm for vldn, vstn and friends.  */
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzs_f32 (float32_t __a)
++{
++  return __a > 0.0f ? -1 : 0;
++}
+ 
+-/* Create struct element types for duplicating loads.
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzd_s64 (int64_t __a)
++{
++  return __a > 0 ? -1ll : 0ll;
++}
+ 
+-   Create 2 element structures of:
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzd_f64 (float64_t __a)
++{
++  return __a > 0.0 ? -1ll : 0ll;
++}
+ 
+-   +------+----+----+----+----+
+-   |      | 8  | 16 | 32 | 64 |
+-   +------+----+----+----+----+
+-   |int   | Y  | Y  | N  | N  |
+-   +------+----+----+----+----+
+-   |uint  | Y  | Y  | N  | N  |
+-   +------+----+----+----+----+
+-   |float | -  | Y  | N  | N  |
+-   +------+----+----+----+----+
+-   |poly  | Y  | Y  | -  | -  |
+-   +------+----+----+----+----+
++/* vcle - vector.  */
+ 
+-   Create 3 element structures of:
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_f32 (float32x2_t __a, float32x2_t __b)
++{
++  return (uint32x2_t) (__a <= __b);
++}
+ 
+-   +------+----+----+----+----+
+-   |      | 8  | 16 | 32 | 64 |
+-   +------+----+----+----+----+
+-   |int   | Y  | Y  | Y  | Y  |
+-   +------+----+----+----+----+
+-   |uint  | Y  | Y  | Y  | Y  |
+-   +------+----+----+----+----+
+-   |float | -  | Y  | Y  | Y  |
+-   +------+----+----+----+----+
+-   |poly  | Y  | Y  | -  | -  |
+-   +------+----+----+----+----+
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_f64 (float64x1_t __a, float64x1_t __b)
++{
++  return (uint64x1_t) (__a <= __b);
++}
+ 
+-   Create 4 element structures of:
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_s8 (int8x8_t __a, int8x8_t __b)
++{
++  return (uint8x8_t) (__a <= __b);
++}
+ 
+-   +------+----+----+----+----+
+-   |      | 8  | 16 | 32 | 64 |
+-   +------+----+----+----+----+
+-   |int   | Y  | N  | N  | Y  |
+-   +------+----+----+----+----+
+-   |uint  | Y  | N  | N  | Y  |
+-   +------+----+----+----+----+
+-   |float | -  | N  | N  | Y  |
+-   +------+----+----+----+----+
+-   |poly  | Y  | N  | -  | -  |
+-   +------+----+----+----+----+
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_s16 (int16x4_t __a, int16x4_t __b)
++{
++  return (uint16x4_t) (__a <= __b);
++}
+ 
+-  This is required for casting memory reference.  */
+-#define __STRUCTN(t, sz, nelem)			\
+-  typedef struct t ## sz ## x ## nelem ## _t {	\
+-    t ## sz ## _t val[nelem];			\
+-  }  t ## sz ## x ## nelem ## _t;
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_s32 (int32x2_t __a, int32x2_t __b)
++{
++  return (uint32x2_t) (__a <= __b);
++}
+ 
+-/* 2-element structs.  */
+-__STRUCTN (int, 8, 2)
+-__STRUCTN (int, 16, 2)
+-__STRUCTN (uint, 8, 2)
+-__STRUCTN (uint, 16, 2)
+-__STRUCTN (float, 16, 2)
+-__STRUCTN (poly, 8, 2)
+-__STRUCTN (poly, 16, 2)
+-/* 3-element structs.  */
+-__STRUCTN (int, 8, 3)
+-__STRUCTN (int, 16, 3)
+-__STRUCTN (int, 32, 3)
+-__STRUCTN (int, 64, 3)
+-__STRUCTN (uint, 8, 3)
+-__STRUCTN (uint, 16, 3)
+-__STRUCTN (uint, 32, 3)
+-__STRUCTN (uint, 64, 3)
+-__STRUCTN (float, 16, 3)
+-__STRUCTN (float, 32, 3)
+-__STRUCTN (float, 64, 3)
+-__STRUCTN (poly, 8, 3)
+-__STRUCTN (poly, 16, 3)
+-/* 4-element structs.  */
+-__STRUCTN (int, 8, 4)
+-__STRUCTN (int, 64, 4)
+-__STRUCTN (uint, 8, 4)
+-__STRUCTN (uint, 64, 4)
+-__STRUCTN (poly, 8, 4)
+-__STRUCTN (float, 64, 4)
+-#undef __STRUCTN
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_s64 (int64x1_t __a, int64x1_t __b)
++{
++  return (uint64x1_t) (__a <= __b);
++}
+ 
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_u8 (uint8x8_t __a, uint8x8_t __b)
++{
++  return (__a <= __b);
++}
+ 
+-#define __ST2_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
+-			qmode, ptr_mode, funcsuffix, signedtype)	     \
+-__extension__ static __inline void					     \
+-__attribute__ ((__always_inline__))					     \
+-vst2_lane_ ## funcsuffix (ptrtype *__ptr,				     \
+-			  intype __b, const int __c)			     \
+-{									     \
+-  __builtin_aarch64_simd_oi __o;					     \
+-  largetype __temp;							     \
+-  __temp.val[0]								     \
+-    = vcombine_##funcsuffix (__b.val[0],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __temp.val[1]								     \
+-    = vcombine_##funcsuffix (__b.val[1],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __o = __builtin_aarch64_set_qregoi##qmode (__o,			     \
+-					     (signedtype) __temp.val[0], 0); \
+-  __o = __builtin_aarch64_set_qregoi##qmode (__o,			     \
+-					     (signedtype) __temp.val[1], 1); \
+-  __builtin_aarch64_st2_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
+-				     __ptr, __o, __c);			     \
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_u16 (uint16x4_t __a, uint16x4_t __b)
++{
++  return (__a <= __b);
+ }
+ 
+-__ST2_LANE_FUNC (float16x4x2_t, float16x8x2_t, float16_t, v4hf, v8hf, hf, f16,
+-		 float16x8_t)
+-__ST2_LANE_FUNC (float32x2x2_t, float32x4x2_t, float32_t, v2sf, v4sf, sf, f32,
+-		 float32x4_t)
+-__ST2_LANE_FUNC (float64x1x2_t, float64x2x2_t, float64_t, df, v2df, df, f64,
+-		 float64x2_t)
+-__ST2_LANE_FUNC (poly8x8x2_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8,
+-		 int8x16_t)
+-__ST2_LANE_FUNC (poly16x4x2_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi, p16,
+-		 int16x8_t)
+-__ST2_LANE_FUNC (int8x8x2_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8,
+-		 int8x16_t)
+-__ST2_LANE_FUNC (int16x4x2_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16,
+-		 int16x8_t)
+-__ST2_LANE_FUNC (int32x2x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32,
+-		 int32x4_t)
+-__ST2_LANE_FUNC (int64x1x2_t, int64x2x2_t, int64_t, di, v2di, di, s64,
+-		 int64x2_t)
+-__ST2_LANE_FUNC (uint8x8x2_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8,
+-		 int8x16_t)
+-__ST2_LANE_FUNC (uint16x4x2_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi, u16,
+-		 int16x8_t)
+-__ST2_LANE_FUNC (uint32x2x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si, u32,
+-		 int32x4_t)
+-__ST2_LANE_FUNC (uint64x1x2_t, uint64x2x2_t, uint64_t, di, v2di, di, u64,
+-		 int64x2_t)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_u32 (uint32x2_t __a, uint32x2_t __b)
++{
++  return (__a <= __b);
++}
+ 
+-#undef __ST2_LANE_FUNC
+-#define __ST2_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
+-__extension__ static __inline void					    \
+-__attribute__ ((__always_inline__))					    \
+-vst2q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
+-			   intype __b, const int __c)			    \
+-{									    \
+-  union { intype __i;							    \
+-	  __builtin_aarch64_simd_oi __o; } __temp = { __b };		    \
+-  __builtin_aarch64_st2_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
+-				    __ptr, __temp.__o, __c);		    \
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_u64 (uint64x1_t __a, uint64x1_t __b)
++{
++  return (__a <= __b);
+ }
+ 
+-__ST2_LANE_FUNC (float16x8x2_t, float16_t, v8hf, hf, f16)
+-__ST2_LANE_FUNC (float32x4x2_t, float32_t, v4sf, sf, f32)
+-__ST2_LANE_FUNC (float64x2x2_t, float64_t, v2df, df, f64)
+-__ST2_LANE_FUNC (poly8x16x2_t, poly8_t, v16qi, qi, p8)
+-__ST2_LANE_FUNC (poly16x8x2_t, poly16_t, v8hi, hi, p16)
+-__ST2_LANE_FUNC (int8x16x2_t, int8_t, v16qi, qi, s8)
+-__ST2_LANE_FUNC (int16x8x2_t, int16_t, v8hi, hi, s16)
+-__ST2_LANE_FUNC (int32x4x2_t, int32_t, v4si, si, s32)
+-__ST2_LANE_FUNC (int64x2x2_t, int64_t, v2di, di, s64)
+-__ST2_LANE_FUNC (uint8x16x2_t, uint8_t, v16qi, qi, u8)
+-__ST2_LANE_FUNC (uint16x8x2_t, uint16_t, v8hi, hi, u16)
+-__ST2_LANE_FUNC (uint32x4x2_t, uint32_t, v4si, si, u32)
+-__ST2_LANE_FUNC (uint64x2x2_t, uint64_t, v2di, di, u64)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_f32 (float32x4_t __a, float32x4_t __b)
++{
++  return (uint32x4_t) (__a <= __b);
++}
+ 
+-#define __ST3_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
+-			qmode, ptr_mode, funcsuffix, signedtype)	     \
+-__extension__ static __inline void					     \
+-__attribute__ ((__always_inline__))					     \
+-vst3_lane_ ## funcsuffix (ptrtype *__ptr,				     \
+-			  intype __b, const int __c)			     \
+-{									     \
+-  __builtin_aarch64_simd_ci __o;					     \
+-  largetype __temp;							     \
+-  __temp.val[0]								     \
+-    = vcombine_##funcsuffix (__b.val[0],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __temp.val[1]								     \
+-    = vcombine_##funcsuffix (__b.val[1],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __temp.val[2]								     \
+-    = vcombine_##funcsuffix (__b.val[2],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
+-					     (signedtype) __temp.val[0], 0); \
+-  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
+-					     (signedtype) __temp.val[1], 1); \
+-  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
+-					     (signedtype) __temp.val[2], 2); \
+-  __builtin_aarch64_st3_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
+-				     __ptr, __o, __c);			     \
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_f64 (float64x2_t __a, float64x2_t __b)
++{
++  return (uint64x2_t) (__a <= __b);
+ }
+ 
+-__ST3_LANE_FUNC (float16x4x3_t, float16x8x3_t, float16_t, v4hf, v8hf, hf, f16,
+-		 float16x8_t)
+-__ST3_LANE_FUNC (float32x2x3_t, float32x4x3_t, float32_t, v2sf, v4sf, sf, f32,
+-		 float32x4_t)
+-__ST3_LANE_FUNC (float64x1x3_t, float64x2x3_t, float64_t, df, v2df, df, f64,
+-		 float64x2_t)
+-__ST3_LANE_FUNC (poly8x8x3_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8,
+-		 int8x16_t)
+-__ST3_LANE_FUNC (poly16x4x3_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi, p16,
+-		 int16x8_t)
+-__ST3_LANE_FUNC (int8x8x3_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8,
+-		 int8x16_t)
+-__ST3_LANE_FUNC (int16x4x3_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16,
+-		 int16x8_t)
+-__ST3_LANE_FUNC (int32x2x3_t, int32x4x3_t, int32_t, v2si, v4si, si, s32,
+-		 int32x4_t)
+-__ST3_LANE_FUNC (int64x1x3_t, int64x2x3_t, int64_t, di, v2di, di, s64,
+-		 int64x2_t)
+-__ST3_LANE_FUNC (uint8x8x3_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8,
+-		 int8x16_t)
+-__ST3_LANE_FUNC (uint16x4x3_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi, u16,
+-		 int16x8_t)
+-__ST3_LANE_FUNC (uint32x2x3_t, uint32x4x3_t, uint32_t, v2si, v4si, si, u32,
+-		 int32x4_t)
+-__ST3_LANE_FUNC (uint64x1x3_t, uint64x2x3_t, uint64_t, di, v2di, di, u64,
+-		 int64x2_t)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_s8 (int8x16_t __a, int8x16_t __b)
++{
++  return (uint8x16_t) (__a <= __b);
++}
+ 
+-#undef __ST3_LANE_FUNC
+-#define __ST3_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
+-__extension__ static __inline void					    \
+-__attribute__ ((__always_inline__))					    \
+-vst3q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
+-			   intype __b, const int __c)			    \
+-{									    \
+-  union { intype __i;							    \
+-	  __builtin_aarch64_simd_ci __o; } __temp = { __b };		    \
+-  __builtin_aarch64_st3_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
+-				    __ptr, __temp.__o, __c);		    \
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_s16 (int16x8_t __a, int16x8_t __b)
++{
++  return (uint16x8_t) (__a <= __b);
+ }
+ 
+-__ST3_LANE_FUNC (float16x8x3_t, float16_t, v8hf, hf, f16)
+-__ST3_LANE_FUNC (float32x4x3_t, float32_t, v4sf, sf, f32)
+-__ST3_LANE_FUNC (float64x2x3_t, float64_t, v2df, df, f64)
+-__ST3_LANE_FUNC (poly8x16x3_t, poly8_t, v16qi, qi, p8)
+-__ST3_LANE_FUNC (poly16x8x3_t, poly16_t, v8hi, hi, p16)
+-__ST3_LANE_FUNC (int8x16x3_t, int8_t, v16qi, qi, s8)
+-__ST3_LANE_FUNC (int16x8x3_t, int16_t, v8hi, hi, s16)
+-__ST3_LANE_FUNC (int32x4x3_t, int32_t, v4si, si, s32)
+-__ST3_LANE_FUNC (int64x2x3_t, int64_t, v2di, di, s64)
+-__ST3_LANE_FUNC (uint8x16x3_t, uint8_t, v16qi, qi, u8)
+-__ST3_LANE_FUNC (uint16x8x3_t, uint16_t, v8hi, hi, u16)
+-__ST3_LANE_FUNC (uint32x4x3_t, uint32_t, v4si, si, u32)
+-__ST3_LANE_FUNC (uint64x2x3_t, uint64_t, v2di, di, u64)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_s32 (int32x4_t __a, int32x4_t __b)
++{
++  return (uint32x4_t) (__a <= __b);
++}
+ 
+-#define __ST4_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
+-			qmode, ptr_mode, funcsuffix, signedtype)	     \
+-__extension__ static __inline void					     \
+-__attribute__ ((__always_inline__))					     \
+-vst4_lane_ ## funcsuffix (ptrtype *__ptr,				     \
+-			  intype __b, const int __c)			     \
+-{									     \
+-  __builtin_aarch64_simd_xi __o;					     \
+-  largetype __temp;							     \
+-  __temp.val[0]								     \
+-    = vcombine_##funcsuffix (__b.val[0],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __temp.val[1]								     \
+-    = vcombine_##funcsuffix (__b.val[1],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __temp.val[2]								     \
+-    = vcombine_##funcsuffix (__b.val[2],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __temp.val[3]								     \
+-    = vcombine_##funcsuffix (__b.val[3],				     \
+-			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
+-					     (signedtype) __temp.val[0], 0); \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
+-					     (signedtype) __temp.val[1], 1); \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
+-					     (signedtype) __temp.val[2], 2); \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
+-					     (signedtype) __temp.val[3], 3); \
+-  __builtin_aarch64_st4_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
+-				     __ptr, __o, __c);			     \
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_s64 (int64x2_t __a, int64x2_t __b)
++{
++  return (uint64x2_t) (__a <= __b);
+ }
+ 
+-__ST4_LANE_FUNC (float16x4x4_t, float16x8x4_t, float16_t, v4hf, v8hf, hf, f16,
+-		 float16x8_t)
+-__ST4_LANE_FUNC (float32x2x4_t, float32x4x4_t, float32_t, v2sf, v4sf, sf, f32,
+-		 float32x4_t)
+-__ST4_LANE_FUNC (float64x1x4_t, float64x2x4_t, float64_t, df, v2df, df, f64,
+-		 float64x2_t)
+-__ST4_LANE_FUNC (poly8x8x4_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8,
+-		 int8x16_t)
+-__ST4_LANE_FUNC (poly16x4x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi, p16,
+-		 int16x8_t)
+-__ST4_LANE_FUNC (int8x8x4_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8,
+-		 int8x16_t)
+-__ST4_LANE_FUNC (int16x4x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16,
+-		 int16x8_t)
+-__ST4_LANE_FUNC (int32x2x4_t, int32x4x4_t, int32_t, v2si, v4si, si, s32,
+-		 int32x4_t)
+-__ST4_LANE_FUNC (int64x1x4_t, int64x2x4_t, int64_t, di, v2di, di, s64,
+-		 int64x2_t)
+-__ST4_LANE_FUNC (uint8x8x4_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8,
+-		 int8x16_t)
+-__ST4_LANE_FUNC (uint16x4x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi, u16,
+-		 int16x8_t)
+-__ST4_LANE_FUNC (uint32x2x4_t, uint32x4x4_t, uint32_t, v2si, v4si, si, u32,
+-		 int32x4_t)
+-__ST4_LANE_FUNC (uint64x1x4_t, uint64x2x4_t, uint64_t, di, v2di, di, u64,
+-		 int64x2_t)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_u8 (uint8x16_t __a, uint8x16_t __b)
++{
++  return (__a <= __b);
++}
+ 
+-#undef __ST4_LANE_FUNC
+-#define __ST4_LANE_FUNC(intype, ptrtype, mode, ptr_mode, funcsuffix)	    \
+-__extension__ static __inline void					    \
+-__attribute__ ((__always_inline__))					    \
+-vst4q_lane_ ## funcsuffix (ptrtype *__ptr,				    \
+-			   intype __b, const int __c)			    \
+-{									    \
+-  union { intype __i;							    \
+-	  __builtin_aarch64_simd_xi __o; } __temp = { __b };		    \
+-  __builtin_aarch64_st4_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *) \
+-				    __ptr, __temp.__o, __c);		    \
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_u16 (uint16x8_t __a, uint16x8_t __b)
++{
++  return (__a <= __b);
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_u32 (uint32x4_t __a, uint32x4_t __b)
++{
++  return (__a <= __b);
++}
++
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_u64 (uint64x2_t __a, uint64x2_t __b)
++{
++  return (__a <= __b);
+ }
+ 
+-__ST4_LANE_FUNC (float16x8x4_t, float16_t, v8hf, hf, f16)
+-__ST4_LANE_FUNC (float32x4x4_t, float32_t, v4sf, sf, f32)
+-__ST4_LANE_FUNC (float64x2x4_t, float64_t, v2df, df, f64)
+-__ST4_LANE_FUNC (poly8x16x4_t, poly8_t, v16qi, qi, p8)
+-__ST4_LANE_FUNC (poly16x8x4_t, poly16_t, v8hi, hi, p16)
+-__ST4_LANE_FUNC (int8x16x4_t, int8_t, v16qi, qi, s8)
+-__ST4_LANE_FUNC (int16x8x4_t, int16_t, v8hi, hi, s16)
+-__ST4_LANE_FUNC (int32x4x4_t, int32_t, v4si, si, s32)
+-__ST4_LANE_FUNC (int64x2x4_t, int64_t, v2di, di, s64)
+-__ST4_LANE_FUNC (uint8x16x4_t, uint8_t, v16qi, qi, u8)
+-__ST4_LANE_FUNC (uint16x8x4_t, uint16_t, v8hi, hi, u16)
+-__ST4_LANE_FUNC (uint32x4x4_t, uint32_t, v4si, si, u32)
+-__ST4_LANE_FUNC (uint64x2x4_t, uint64_t, v2di, di, u64)
++/* vcle - scalar.  */
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vaddlv_s32 (int32x2_t a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcles_f32 (float32_t __a, float32_t __b)
+ {
+-  int64_t result;
+-  __asm__ ("saddlp %0.1d, %1.2s" : "=w"(result) : "w"(a) : );
+-  return result;
++  return __a <= __b ? -1 : 0;
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vaddlv_u32 (uint32x2_t a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcled_s64 (int64_t __a, int64_t __b)
+ {
+-  uint64_t result;
+-  __asm__ ("uaddlp %0.1d, %1.2s" : "=w"(result) : "w"(a) : );
+-  return result;
++  return __a <= __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcled_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return __builtin_aarch64_sqdmulh_laneqv4hi (__a, __b, __c);
++  return __a <= __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcled_f64 (float64_t __a, float64_t __b)
+ {
+-  return __builtin_aarch64_sqdmulh_laneqv2si (__a, __b, __c);
++  return __a <= __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++/* vclez - vector.  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_sqdmulh_laneqv8hi (__a, __b, __c);
++  return (uint32x2_t) (__a <= 0.0f);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_sqdmulh_laneqv4si (__a, __b, __c);
++  return (uint64x1_t) (__a <= (float64x1_t) {0.0});
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmulh_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_s8 (int8x8_t __a)
+ {
+-  return  __builtin_aarch64_sqrdmulh_laneqv4hi (__a, __b, __c);
++  return (uint8x8_t) (__a <= 0);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmulh_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_s16 (int16x4_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_laneqv2si (__a, __b, __c);
++  return (uint16x4_t) (__a <= 0);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmulhq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_s32 (int32x2_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_laneqv8hi (__a, __b, __c);
++  return (uint32x2_t) (__a <= 0);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmulhq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_s64 (int64x1_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_laneqv4si (__a, __b, __c);
++  return (uint64x1_t) (__a <= __AARCH64_INT64_C (0));
+ }
+ 
+-/* Table intrinsics.  */
+-
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbl1_p8 (poly8x16_t a, uint8x8_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_f32 (float32x4_t __a)
+ {
+-  poly8x8_t result;
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a <= 0.0f);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbl1_s8 (int8x16_t a, uint8x8_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_f64 (float64x2_t __a)
+ {
+-  int8x8_t result;
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a <= 0.0);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbl1_u8 (uint8x16_t a, uint8x8_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_s8 (int8x16_t __a)
+ {
+-  uint8x8_t result;
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x16_t) (__a <= 0);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbl1q_p8 (poly8x16_t a, uint8x16_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_s16 (int16x8_t __a)
+ {
+-  poly8x16_t result;
+-  __asm__ ("tbl %0.16b, {%1.16b}, %2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint16x8_t) (__a <= 0);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbl1q_s8 (int8x16_t a, uint8x16_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_s32 (int32x4_t __a)
+ {
+-  int8x16_t result;
+-  __asm__ ("tbl %0.16b, {%1.16b}, %2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x4_t) (__a <= 0);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbl1q_u8 (uint8x16_t a, uint8x16_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_s64 (int64x2_t __a)
+ {
+-  uint8x16_t result;
+-  __asm__ ("tbl %0.16b, {%1.16b}, %2.16b"
+-           : "=w"(result)
+-           : "w"(a), "w"(b)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x2_t) (__a <= __AARCH64_INT64_C (0));
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbx1_s8 (int8x8_t r, int8x16_t tab, uint8x8_t idx)
++/* vclez - scalar.  */
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezs_f32 (float32_t __a)
+ {
+-  int8x8_t result = r;
+-  __asm__ ("tbx %0.8b,{%1.16b},%2.8b"
+-           : "+w"(result)
+-           : "w"(tab), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return __a <= 0.0f ? -1 : 0;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbx1_u8 (uint8x8_t r, uint8x16_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezd_s64 (int64_t __a)
+ {
+-  uint8x8_t result = r;
+-  __asm__ ("tbx %0.8b,{%1.16b},%2.8b"
+-           : "+w"(result)
+-           : "w"(tab), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return __a <= 0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbx1_p8 (poly8x8_t r, poly8x16_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezd_f64 (float64_t __a)
+ {
+-  poly8x8_t result = r;
+-  __asm__ ("tbx %0.8b,{%1.16b},%2.8b"
+-           : "+w"(result)
+-           : "w"(tab), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return __a <= 0.0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbx1q_s8 (int8x16_t r, int8x16_t tab, uint8x16_t idx)
++/* vclt - vector.  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  int8x16_t result = r;
+-  __asm__ ("tbx %0.16b,{%1.16b},%2.16b"
+-           : "+w"(result)
+-           : "w"(tab), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x2_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbx1q_u8 (uint8x16_t r, uint8x16_t tab, uint8x16_t idx)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  uint8x16_t result = r;
+-  __asm__ ("tbx %0.16b,{%1.16b},%2.16b"
+-           : "+w"(result)
+-           : "w"(tab), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x1_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbx1q_p8 (poly8x16_t r, poly8x16_t tab, uint8x16_t idx)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  poly8x16_t result = r;
+-  __asm__ ("tbx %0.16b,{%1.16b},%2.16b"
+-           : "+w"(result)
+-           : "w"(tab), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (uint8x8_t) (__a < __b);
+ }
+ 
+-/* V7 legacy table intrinsics.  */
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_s16 (int16x4_t __a, int16x4_t __b)
++{
++  return (uint16x4_t) (__a < __b);
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbl1_s8 (int8x8_t tab, int8x8_t idx)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  int8x8_t result;
+-  int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (uint32x2_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbl1_u8 (uint8x8_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  uint8x8_t result;
+-  uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (uint64x1_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbl1_p8 (poly8x8_t tab, uint8x8_t idx)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  poly8x8_t result;
+-  poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (__AARCH64_UINT64_C (0x0)));
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbl2_s8 (int8x8x2_t tab, int8x8_t idx)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  int8x8_t result;
+-  int8x16_t temp = vcombine_s8 (tab.val[0], tab.val[1]);
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbl2_u8 (uint8x8x2_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  uint8x8_t result;
+-  uint8x16_t temp = vcombine_u8 (tab.val[0], tab.val[1]);
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbl2_p8 (poly8x8x2_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+-  poly8x8_t result;
+-  poly8x16_t temp = vcombine_p8 (tab.val[0], tab.val[1]);
+-  __asm__ ("tbl %0.8b, {%1.16b}, %2.8b"
+-           : "=w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbl3_s8 (int8x8x3_t tab, int8x8_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  int8x8_t result;
+-  int8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]);
+-  temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (__AARCH64_UINT64_C (0x0)));
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = __builtin_aarch64_tbl3v8qi (__o, idx);
+-  return result;
++  return (uint32x4_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbl3_u8 (uint8x8x3_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  uint8x8_t result;
+-  uint8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]);
+-  temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (__AARCH64_UINT64_C (0x0)));
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = (uint8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+-  return result;
++  return (uint64x2_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbl3_p8 (poly8x8x3_t tab, uint8x8_t idx)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  poly8x8_t result;
+-  poly8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]);
+-  temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (__AARCH64_UINT64_C (0x0)));
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = (poly8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+-  return result;
++  return (uint8x16_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbl4_s8 (int8x8x4_t tab, int8x8_t idx)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  int8x8_t result;
+-  int8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]);
+-  temp.val[1] = vcombine_s8 (tab.val[2], tab.val[3]);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = __builtin_aarch64_tbl3v8qi (__o, idx);
+-  return result;
++  return (uint16x8_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbl4_u8 (uint8x8x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  uint8x8_t result;
+-  uint8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]);
+-  temp.val[1] = vcombine_u8 (tab.val[2], tab.val[3]);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = (uint8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+-  return result;
++  return (uint32x4_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbl4_p8 (poly8x8x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  poly8x8_t result;
+-  poly8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]);
+-  temp.val[1] = vcombine_p8 (tab.val[2], tab.val[3]);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = (poly8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+-  return result;
++  return (uint64x2_t) (__a < __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbx2_s8 (int8x8_t r, int8x8x2_t tab, int8x8_t idx)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  int8x8_t result = r;
+-  int8x16_t temp = vcombine_s8 (tab.val[0], tab.val[1]);
+-  __asm__ ("tbx %0.8b, {%1.16b}, %2.8b"
+-           : "+w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbx2_u8 (uint8x8_t r, uint8x8x2_t tab, uint8x8_t idx)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  uint8x8_t result = r;
+-  uint8x16_t temp = vcombine_u8 (tab.val[0], tab.val[1]);
+-  __asm__ ("tbx %0.8b, {%1.16b}, %2.8b"
+-           : "+w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbx2_p8 (poly8x8_t r, poly8x8x2_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  poly8x8_t result = r;
+-  poly8x16_t temp = vcombine_p8 (tab.val[0], tab.val[1]);
+-  __asm__ ("tbx %0.8b, {%1.16b}, %2.8b"
+-           : "+w"(result)
+-           : "w"(temp), "w"(idx)
+-           : /* No clobbers */);
+-  return result;
++  return (__a < __b);
+ }
+ 
+-/* End of temporary inline asm.  */
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_u64 (uint64x2_t __a, uint64x2_t __b)
++{
++  return (__a < __b);
++}
+ 
+-/* Start of optimal implementations in approved order.  */
++/* vclt - scalar.  */
+ 
+-/* vabs  */
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclts_f32 (float32_t __a, float32_t __b)
++{
++  return __a < __b ? -1 : 0;
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vabs_f32 (float32x2_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltd_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_absv2sf (__a);
++  return __a < __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vabs_f64 (float64x1_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltd_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return (float64x1_t) {__builtin_fabs (__a[0])};
++  return __a < __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vabs_s8 (int8x8_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltd_f64 (float64_t __a, float64_t __b)
+ {
+-  return __builtin_aarch64_absv8qi (__a);
++  return __a < __b ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vabs_s16 (int16x4_t __a)
++/* vcltz - vector.  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_absv4hi (__a);
++  return (uint32x2_t) (__a < 0.0f);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vabs_s32 (int32x2_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_absv2si (__a);
++  return (uint64x1_t) (__a < (float64x1_t) {0.0});
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vabs_s64 (int64x1_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_s8 (int8x8_t __a)
+ {
+-  return (int64x1_t) {__builtin_aarch64_absdi (__a[0])};
++  return (uint8x8_t) (__a < 0);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vabsq_f32 (float32x4_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_s16 (int16x4_t __a)
+ {
+-  return __builtin_aarch64_absv4sf (__a);
++  return (uint16x4_t) (__a < 0);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vabsq_f64 (float64x2_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_s32 (int32x2_t __a)
+ {
+-  return __builtin_aarch64_absv2df (__a);
++  return (uint32x2_t) (__a < 0);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vabsq_s8 (int8x16_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_s64 (int64x1_t __a)
+ {
+-  return __builtin_aarch64_absv16qi (__a);
++  return (uint64x1_t) (__a < __AARCH64_INT64_C (0));
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vabsq_s16 (int16x8_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_absv8hi (__a);
++  return (uint32x4_t) (__a < 0.0f);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vabsq_s32 (int32x4_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_absv4si (__a);
++  return (uint64x2_t) (__a < 0.0);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vabsq_s64 (int64x2_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_s8 (int8x16_t __a)
+ {
+-  return __builtin_aarch64_absv2di (__a);
++  return (uint8x16_t) (__a < 0);
+ }
+ 
+-/* vadd */
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_s16 (int16x8_t __a)
++{
++  return (uint16x8_t) (__a < 0);
++}
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vaddd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_s32 (int32x4_t __a)
+ {
+-  return __a + __b;
++  return (uint32x4_t) (__a < 0);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vaddd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_s64 (int64x2_t __a)
+ {
+-  return __a + __b;
++  return (uint64x2_t) (__a < __AARCH64_INT64_C (0));
+ }
+ 
+-/* vaddv */
++/* vcltz - scalar.  */
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vaddv_s8 (int8x8_t __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzs_f32 (float32_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v8qi (__a);
++  return __a < 0.0f ? -1 : 0;
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vaddv_s16 (int16x4_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzd_s64 (int64_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v4hi (__a);
++  return __a < 0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vaddv_s32 (int32x2_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzd_f64 (float64_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v2si (__a);
++  return __a < 0.0 ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vaddv_u8 (uint8x8_t __a)
++/* vcls.  */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcls_s8 (int8x8_t __a)
+ {
+-  return (uint8_t) __builtin_aarch64_reduc_plus_scal_v8qi ((int8x8_t) __a);
++  return __builtin_aarch64_clrsbv8qi (__a);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vaddv_u16 (uint16x4_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcls_s16 (int16x4_t __a)
+ {
+-  return (uint16_t) __builtin_aarch64_reduc_plus_scal_v4hi ((int16x4_t) __a);
++  return __builtin_aarch64_clrsbv4hi (__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vaddv_u32 (uint32x2_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcls_s32 (int32x2_t __a)
+ {
+-  return (int32_t) __builtin_aarch64_reduc_plus_scal_v2si ((int32x2_t) __a);
++  return __builtin_aarch64_clrsbv2si (__a);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vaddvq_s8 (int8x16_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclsq_s8 (int8x16_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v16qi (__a);
++  return __builtin_aarch64_clrsbv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vaddvq_s16 (int16x8_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclsq_s16 (int16x8_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v8hi (__a);
++  return __builtin_aarch64_clrsbv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vaddvq_s32 (int32x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclsq_s32 (int32x4_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v4si (__a);
++  return __builtin_aarch64_clrsbv4si (__a);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vaddvq_s64 (int64x2_t __a)
++/* vclz.  */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclz_s8 (int8x8_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v2di (__a);
++  return __builtin_aarch64_clzv8qi (__a);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vaddvq_u8 (uint8x16_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclz_s16 (int16x4_t __a)
+ {
+-  return (uint8_t) __builtin_aarch64_reduc_plus_scal_v16qi ((int8x16_t) __a);
++  return __builtin_aarch64_clzv4hi (__a);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vaddvq_u16 (uint16x8_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclz_s32 (int32x2_t __a)
+ {
+-  return (uint16_t) __builtin_aarch64_reduc_plus_scal_v8hi ((int16x8_t) __a);
++  return __builtin_aarch64_clzv2si (__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vaddvq_u32 (uint32x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclz_u8 (uint8x8_t __a)
+ {
+-  return (uint32_t) __builtin_aarch64_reduc_plus_scal_v4si ((int32x4_t) __a);
++  return (uint8x8_t)__builtin_aarch64_clzv8qi ((int8x8_t)__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vaddvq_u64 (uint64x2_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclz_u16 (uint16x4_t __a)
+ {
+-  return (uint64_t) __builtin_aarch64_reduc_plus_scal_v2di ((int64x2_t) __a);
++  return (uint16x4_t)__builtin_aarch64_clzv4hi ((int16x4_t)__a);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vaddv_f32 (float32x2_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclz_u32 (uint32x2_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v2sf (__a);
++  return (uint32x2_t)__builtin_aarch64_clzv2si ((int32x2_t)__a);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vaddvq_f32 (float32x4_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclzq_s8 (int8x16_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v4sf (__a);
++  return __builtin_aarch64_clzv16qi (__a);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vaddvq_f64 (float64x2_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclzq_s16 (int16x8_t __a)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v2df (__a);
++  return __builtin_aarch64_clzv8hi (__a);
+ }
+ 
+-/* vbsl  */
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclzq_s32 (int32x4_t __a)
++{
++  return __builtin_aarch64_clzv4si (__a);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vbsl_f32 (uint32x2_t __a, float32x2_t __b, float32x2_t __c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclzq_u8 (uint8x16_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv2sf_suss (__a, __b, __c);
++  return (uint8x16_t)__builtin_aarch64_clzv16qi ((int8x16_t)__a);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vbsl_f64 (uint64x1_t __a, float64x1_t __b, float64x1_t __c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclzq_u16 (uint16x8_t __a)
+ {
+-  return (float64x1_t)
+-    { __builtin_aarch64_simd_bsldf_suss (__a[0], __b[0], __c[0]) };
++  return (uint16x8_t)__builtin_aarch64_clzv8hi ((int16x8_t)__a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vbsl_p8 (uint8x8_t __a, poly8x8_t __b, poly8x8_t __c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclzq_u32 (uint32x4_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv8qi_pupp (__a, __b, __c);
++  return (uint32x4_t)__builtin_aarch64_clzv4si ((int32x4_t)__a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vbsl_p16 (uint16x4_t __a, poly16x4_t __b, poly16x4_t __c)
++/* vcnt.  */
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcnt_p8 (poly8x8_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv4hi_pupp (__a, __b, __c);
++  return (poly8x8_t) __builtin_aarch64_popcountv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vbsl_s8 (uint8x8_t __a, int8x8_t __b, int8x8_t __c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcnt_s8 (int8x8_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv8qi_suss (__a, __b, __c);
++  return __builtin_aarch64_popcountv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vbsl_s16 (uint16x4_t __a, int16x4_t __b, int16x4_t __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcnt_u8 (uint8x8_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv4hi_suss (__a, __b, __c);
++  return (uint8x8_t) __builtin_aarch64_popcountv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vbsl_s32 (uint32x2_t __a, int32x2_t __b, int32x2_t __c)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcntq_p8 (poly8x16_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv2si_suss (__a, __b, __c);
++  return (poly8x16_t) __builtin_aarch64_popcountv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vbsl_s64 (uint64x1_t __a, int64x1_t __b, int64x1_t __c)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcntq_s8 (int8x16_t __a)
+ {
+-  return (int64x1_t)
+-      {__builtin_aarch64_simd_bsldi_suss (__a[0], __b[0], __c[0])};
++  return __builtin_aarch64_popcountv16qi (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vbsl_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcntq_u8 (uint8x16_t __a)
+ {
+-  return __builtin_aarch64_simd_bslv8qi_uuuu (__a, __b, __c);
++  return (uint8x16_t) __builtin_aarch64_popcountv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vbsl_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
++/* vcopy_lane.  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_f32 (float32x2_t __a, const int __lane1,
++		float32x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv4hi_uuuu (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vbsl_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_f64 (float64x1_t __a, const int __lane1,
++		float64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv2si_uuuu (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vbsl_u64 (uint64x1_t __a, uint64x1_t __b, uint64x1_t __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_p8 (poly8x8_t __a, const int __lane1,
++	       poly8x8_t __b, const int __lane2)
+ {
+-  return (uint64x1_t)
+-      {__builtin_aarch64_simd_bsldi_uuuu (__a[0], __b[0], __c[0])};
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				 __a, __lane1);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vbslq_f32 (uint32x4_t __a, float32x4_t __b, float32x4_t __c)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_p16 (poly16x4_t __a, const int __lane1,
++		poly16x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv4sf_suss (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vbslq_f64 (uint64x2_t __a, float64x2_t __b, float64x2_t __c)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_p64 (poly64x1_t __a, const int __lane1,
++		poly64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv2df_suss (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vbslq_p8 (uint8x16_t __a, poly8x16_t __b, poly8x16_t __c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_s8 (int8x8_t __a, const int __lane1,
++	       int8x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv16qi_pupp (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				 __a, __lane1);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vbslq_p16 (uint16x8_t __a, poly16x8_t __b, poly16x8_t __c)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_s16 (int16x4_t __a, const int __lane1,
++		int16x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv8hi_pupp (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vbslq_s8 (uint8x16_t __a, int8x16_t __b, int8x16_t __c)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_s32 (int32x2_t __a, const int __lane1,
++		int32x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv16qi_suss (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vbslq_s16 (uint16x8_t __a, int16x8_t __b, int16x8_t __c)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_s64 (int64x1_t __a, const int __lane1,
++		int64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv8hi_suss (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vbslq_s32 (uint32x4_t __a, int32x4_t __b, int32x4_t __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_u8 (uint8x8_t __a, const int __lane1,
++	       uint8x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv4si_suss (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				 __a, __lane1);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vbslq_s64 (uint64x2_t __a, int64x2_t __b, int64x2_t __c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_u16 (uint16x4_t __a, const int __lane1,
++		uint16x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv2di_suss (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vbslq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_u32 (uint32x2_t __a, const int __lane1,
++		uint32x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv16qi_uuuu (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vbslq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_lane_u64 (uint64x1_t __a, const int __lane1,
++		uint64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv8hi_uuuu (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vbslq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
++/* vcopy_laneq.  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_f32 (float32x2_t __a, const int __lane1,
++		 float32x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv4si_uuuu (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vbslq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_f64 (float64x1_t __a, const int __lane1,
++		 float64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_simd_bslv2di_uuuu (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-/* ARMv8.1 instrinsics.  */
+-#pragma GCC push_options
+-#pragma GCC target ("arch=armv8.1-a")
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_p8 (poly8x8_t __a, const int __lane1,
++		poly8x16_t __b, const int __lane2)
++{
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				 __a, __lane1);
++}
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmlah_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_p16 (poly16x4_t __a, const int __lane1,
++		 poly16x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlahv4hi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmlah_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_p64 (poly64x1_t __a, const int __lane1,
++		 poly64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlahv2si (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmlahq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_s8 (int8x8_t __a, const int __lane1,
++		int8x16_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlahv8hi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				 __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmlahq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_s16 (int16x4_t __a, const int __lane1,
++		 int16x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlahv4si (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmlsh_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_s32 (int32x2_t __a, const int __lane1,
++		 int32x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlshv4hi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmlsh_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_s64 (int64x1_t __a, const int __lane1,
++		 int64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlshv2si (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmlshq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_u8 (uint8x8_t __a, const int __lane1,
++		uint8x16_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlshv8hi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				 __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmlshq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_u16 (uint16x4_t __a, const int __lane1,
++		 uint16x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlshv4si (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmlah_laneq_s16 (int16x4_t __a, int16x4_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_u32 (uint32x2_t __a, const int __lane1,
++		 uint32x4_t __b, const int __lane2)
+ {
+-  return  __builtin_aarch64_sqrdmlah_laneqv4hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmlah_laneq_s32 (int32x2_t __a, int32x2_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopy_laneq_u64 (uint64x1_t __a, const int __lane1,
++		 uint64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_laneqv2si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmlahq_laneq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c, const int __d)
++/* vcopyq_lane.  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_f32 (float32x4_t __a, const int __lane1,
++		 float32x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_laneqv8hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmlahq_laneq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_f64 (float64x2_t __a, const int __lane1,
++		 float64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_laneqv4si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmlsh_laneq_s16 (int16x4_t __a, int16x4_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_p8 (poly8x16_t __a, const int __lane1,
++		poly8x8_t __b, const int __lane2)
+ {
+-  return  __builtin_aarch64_sqrdmlsh_laneqv4hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmlsh_laneq_s32 (int32x2_t __a, int32x2_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_p16 (poly16x8_t __a, const int __lane1,
++		 poly16x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_laneqv2si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmlshq_laneq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_p64 (poly64x2_t __a, const int __lane1,
++		 poly64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_laneqv8hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmlshq_laneq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_s8 (int8x16_t __a, const int __lane1,
++		int8x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_laneqv4si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmlah_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_s16 (int16x8_t __a, const int __lane1,
++		 int16x4_t __b, const int __lane2)
+ {
+-  return  __builtin_aarch64_sqrdmlah_lanev4hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmlah_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_s32 (int32x4_t __a, const int __lane1,
++		 int32x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_lanev2si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmlahq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_s64 (int64x2_t __a, const int __lane1,
++		 int64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_lanev8hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmlahq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_u8 (uint8x16_t __a, const int __lane1,
++		uint8x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_lanev4si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmlahh_s16 (int16_t __a, int16_t __b, int16_t __c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_u16 (uint16x8_t __a, const int __lane1,
++		 uint16x4_t __b, const int __lane2)
+ {
+-  return (int16_t) __builtin_aarch64_sqrdmlahhi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmlahh_lane_s16 (int16_t __a, int16_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_u32 (uint32x4_t __a, const int __lane1,
++		 uint32x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_lanehi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmlahh_laneq_s16 (int16_t __a, int16_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_lane_u64 (uint64x2_t __a, const int __lane1,
++		 uint64x1_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_laneqhi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmlahs_s32 (int32_t __a, int32_t __b, int32_t __c)
++/* vcopyq_laneq.  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_f32 (float32x4_t __a, const int __lane1,
++		  float32x4_t __b, const int __lane2)
+ {
+-  return (int32_t) __builtin_aarch64_sqrdmlahsi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmlahs_lane_s32 (int32_t __a, int32_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_f64 (float64x2_t __a, const int __lane1,
++		  float64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_lanesi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmlahs_laneq_s32 (int32_t __a, int32_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_p8 (poly8x16_t __a, const int __lane1,
++		 poly8x16_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlah_laneqsi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmlsh_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_p16 (poly16x8_t __a, const int __lane1,
++		  poly16x8_t __b, const int __lane2)
+ {
+-  return  __builtin_aarch64_sqrdmlsh_lanev4hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmlsh_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_p64 (poly64x2_t __a, const int __lane1,
++		  poly64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_lanev2si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmlshq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_s8 (int8x16_t __a, const int __lane1,
++		 int8x16_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_lanev8hi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmlshq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_s16 (int16x8_t __a, const int __lane1,
++		  int16x8_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_lanev4si (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmlshh_s16 (int16_t __a, int16_t __b, int16_t __c)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_s32 (int32x4_t __a, const int __lane1,
++		  int32x4_t __b, const int __lane2)
+ {
+-  return (int16_t) __builtin_aarch64_sqrdmlshhi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmlshh_lane_s16 (int16_t __a, int16_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_s64 (int64x2_t __a, const int __lane1,
++		  int64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_lanehi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmlshh_laneq_s16 (int16_t __a, int16_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_u8 (uint8x16_t __a, const int __lane1,
++		 uint8x16_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_laneqhi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				  __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmlshs_s32 (int32_t __a, int32_t __b, int32_t __c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_u16 (uint16x8_t __a, const int __lane1,
++		  uint16x8_t __b, const int __lane2)
+ {
+-  return (int32_t) __builtin_aarch64_sqrdmlshsi (__a, __b, __c);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmlshs_lane_s32 (int32_t __a, int32_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_u32 (uint32x4_t __a, const int __lane1,
++		  uint32x4_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_lanesi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmlshs_laneq_s32 (int32_t __a, int32_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcopyq_laneq_u64 (uint64x2_t __a, const int __lane1,
++		  uint64x2_t __b, const int __lane2)
+ {
+-  return __builtin_aarch64_sqrdmlsh_laneqsi (__a, __b, __c, __d);
++  return __aarch64_vset_lane_any (__aarch64_vget_lane_any (__b, __lane2),
++				   __a, __lane1);
+ }
+-#pragma GCC pop_options
+ 
+-#pragma GCC push_options
+-#pragma GCC target ("+nothing+crypto")
+-/* vaes  */
++/* vcvt (double -> float).  */
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaeseq_u8 (uint8x16_t data, uint8x16_t key)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f16_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_crypto_aesev16qi_uuu (data, key);
++  return __builtin_aarch64_float_truncate_lo_v4hf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaesdq_u8 (uint8x16_t data, uint8x16_t key)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_high_f16_f32 (float16x4_t __a, float32x4_t __b)
+ {
+-  return __builtin_aarch64_crypto_aesdv16qi_uuu (data, key);
++  return __builtin_aarch64_float_truncate_hi_v8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaesmcq_u8 (uint8x16_t data)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f32_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_crypto_aesmcv16qi_uu (data);
++  return __builtin_aarch64_float_truncate_lo_v2sf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaesimcq_u8 (uint8x16_t data)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_high_f32_f64 (float32x2_t __a, float64x2_t __b)
+ {
+-  return __builtin_aarch64_crypto_aesimcv16qi_uu (data);
++  return __builtin_aarch64_float_truncate_hi_v4sf (__a, __b);
+ }
+-#pragma GCC pop_options
+ 
+-/* vcage  */
++/* vcvt (float -> double).  */
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcage_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f32_f16 (float16x4_t __a)
+ {
+-  return vabs_f64 (__a) >= vabs_f64 (__b);
++  return __builtin_aarch64_float_extend_lo_v4sf (__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcages_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f64_f32 (float32x2_t __a)
+ {
+-  return __builtin_fabsf (__a) >= __builtin_fabsf (__b) ? -1 : 0;
++
++  return __builtin_aarch64_float_extend_lo_v2df (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcage_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_high_f32_f16 (float16x8_t __a)
+ {
+-  return vabs_f32 (__a) >= vabs_f32 (__b);
++  return __builtin_aarch64_vec_unpacks_hi_v8hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcageq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_high_f64_f32 (float32x4_t __a)
+ {
+-  return vabsq_f32 (__a) >= vabsq_f32 (__b);
++  return __builtin_aarch64_vec_unpacks_hi_v4sf (__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcaged_f64 (float64_t __a, float64_t __b)
++/* vcvt (<u>fixed-point -> float).  */
++
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_n_f64_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_fabs (__a) >= __builtin_fabs (__b) ? -1 : 0;
++  return __builtin_aarch64_scvtfdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcageq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_n_f64_u64 (uint64_t __a, const int __b)
+ {
+-  return vabsq_f64 (__a) >= vabsq_f64 (__b);
++  return __builtin_aarch64_ucvtfdi_sus (__a, __b);
+ }
+ 
+-/* vcagt  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcagts_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_n_f32_s32 (int32_t __a, const int __b)
+ {
+-  return __builtin_fabsf (__a) > __builtin_fabsf (__b) ? -1 : 0;
++  return __builtin_aarch64_scvtfsi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcagt_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_n_f32_u32 (uint32_t __a, const int __b)
+ {
+-  return vabs_f32 (__a) > vabs_f32 (__b);
++  return __builtin_aarch64_ucvtfsi_sus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcagt_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f32_s32 (int32x2_t __a, const int __b)
+ {
+-  return vabs_f64 (__a) > vabs_f64 (__b);
++  return __builtin_aarch64_scvtfv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcagtq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f32_u32 (uint32x2_t __a, const int __b)
+ {
+-  return vabsq_f32 (__a) > vabsq_f32 (__b);
++  return __builtin_aarch64_ucvtfv2si_sus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcagtd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f64_s64 (int64x1_t __a, const int __b)
+ {
+-  return __builtin_fabs (__a) > __builtin_fabs (__b) ? -1 : 0;
++  return (float64x1_t)
++    { __builtin_aarch64_scvtfdi (vget_lane_s64 (__a, 0), __b) };
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcagtq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f64_u64 (uint64x1_t __a, const int __b)
+ {
+-  return vabsq_f64 (__a) > vabsq_f64 (__b);
++  return (float64x1_t)
++    { __builtin_aarch64_ucvtfdi_sus (vget_lane_u64 (__a, 0), __b) };
+ }
+ 
+-/* vcale  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcale_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f32_s32 (int32x4_t __a, const int __b)
+ {
+-  return vabs_f32 (__a) <= vabs_f32 (__b);
++  return __builtin_aarch64_scvtfv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcale_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f32_u32 (uint32x4_t __a, const int __b)
+ {
+-  return vabs_f64 (__a) <= vabs_f64 (__b);
++  return __builtin_aarch64_ucvtfv4si_sus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcaled_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f64_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_fabs (__a) <= __builtin_fabs (__b) ? -1 : 0;
++  return __builtin_aarch64_scvtfv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcales_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f64_u64 (uint64x2_t __a, const int __b)
+ {
+-  return __builtin_fabsf (__a) <= __builtin_fabsf (__b) ? -1 : 0;
++  return __builtin_aarch64_ucvtfv2di_sus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcaleq_f32 (float32x4_t __a, float32x4_t __b)
++/* vcvt (float -> <u>fixed-point).  */
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_n_s64_f64 (float64_t __a, const int __b)
+ {
+-  return vabsq_f32 (__a) <= vabsq_f32 (__b);
++  return __builtin_aarch64_fcvtzsdf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcaleq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_n_u64_f64 (float64_t __a, const int __b)
+ {
+-  return vabsq_f64 (__a) <= vabsq_f64 (__b);
++  return __builtin_aarch64_fcvtzudf_uss (__a, __b);
+ }
+ 
+-/* vcalt  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcalt_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_n_s32_f32 (float32_t __a, const int __b)
+ {
+-  return vabs_f32 (__a) < vabs_f32 (__b);
++  return __builtin_aarch64_fcvtzssf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcalt_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_n_u32_f32 (float32_t __a, const int __b)
+ {
+-  return vabs_f64 (__a) < vabs_f64 (__b);
++  return __builtin_aarch64_fcvtzusf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcaltd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_s32_f32 (float32x2_t __a, const int __b)
+ {
+-  return __builtin_fabs (__a) < __builtin_fabs (__b) ? -1 : 0;
++  return __builtin_aarch64_fcvtzsv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcaltq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_u32_f32 (float32x2_t __a, const int __b)
+ {
+-  return vabsq_f32 (__a) < vabsq_f32 (__b);
++  return __builtin_aarch64_fcvtzuv2sf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcaltq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_s64_f64 (float64x1_t __a, const int __b)
+ {
+-  return vabsq_f64 (__a) < vabsq_f64 (__b);
++  return (int64x1_t)
++    { __builtin_aarch64_fcvtzsdf (vget_lane_f64 (__a, 0), __b) };
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcalts_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_u64_f64 (float64x1_t __a, const int __b)
+ {
+-  return __builtin_fabsf (__a) < __builtin_fabsf (__b) ? -1 : 0;
++  return (uint64x1_t)
++    { __builtin_aarch64_fcvtzudf_uss (vget_lane_f64 (__a, 0), __b) };
+ }
+ 
+-/* vceq - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vceq_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_s32_f32 (float32x4_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a == __b);
++  return __builtin_aarch64_fcvtzsv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceq_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_u32_f32 (float32x4_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a == __b);
++  return __builtin_aarch64_fcvtzuv4sf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vceq_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_s64_f64 (float64x2_t __a, const int __b)
+ {
+-  return (uint8x8_t) (__a == __b);
++  return __builtin_aarch64_fcvtzsv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vceq_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_u64_f64 (float64x2_t __a, const int __b)
+ {
+-  return (uint8x8_t) (__a == __b);
++  return __builtin_aarch64_fcvtzuv2df_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vceq_s16 (int16x4_t __a, int16x4_t __b)
++/* vcvt  (<u>int -> float)  */
++
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_f64_s64 (int64_t __a)
+ {
+-  return (uint16x4_t) (__a == __b);
++  return (float64_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vceq_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_f64_u64 (uint64_t __a)
+ {
+-  return (uint32x2_t) (__a == __b);
++  return (float64_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceq_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_f32_s32 (int32_t __a)
+ {
+-  return (uint64x1_t) (__a == __b);
++  return (float32_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vceq_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_f32_u32 (uint32_t __a)
+ {
+-  return (__a == __b);
++  return (float32_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vceq_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f32_s32 (int32x2_t __a)
+ {
+-  return (__a == __b);
++  return __builtin_aarch64_floatv2siv2sf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vceq_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f32_u32 (uint32x2_t __a)
+ {
+-  return (__a == __b);
++  return __builtin_aarch64_floatunsv2siv2sf ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceq_u64 (uint64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f64_s64 (int64x1_t __a)
+ {
+-  return (__a == __b);
++  return (float64x1_t) { vget_lane_s64 (__a, 0) };
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vceqq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f64_u64 (uint64x1_t __a)
+ {
+-  return (uint32x4_t) (__a == __b);
++  return (float64x1_t) { vget_lane_u64 (__a, 0) };
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vceqq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f32_s32 (int32x4_t __a)
+ {
+-  return (uint64x2_t) (__a == __b);
++  return __builtin_aarch64_floatv4siv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vceqq_p8 (poly8x16_t __a, poly8x16_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f32_u32 (uint32x4_t __a)
+ {
+-  return (uint8x16_t) (__a == __b);
++  return __builtin_aarch64_floatunsv4siv4sf ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vceqq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f64_s64 (int64x2_t __a)
+ {
+-  return (uint8x16_t) (__a == __b);
++  return __builtin_aarch64_floatv2div2df (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vceqq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f64_u64 (uint64x2_t __a)
+ {
+-  return (uint16x8_t) (__a == __b);
++  return __builtin_aarch64_floatunsv2div2df ((int64x2_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vceqq_s32 (int32x4_t __a, int32x4_t __b)
++/* vcvt (float -> <u>int)  */
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_s64_f64 (float64_t __a)
+ {
+-  return (uint32x4_t) (__a == __b);
++  return (int64_t) __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vceqq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtd_u64_f64 (float64_t __a)
+ {
+-  return (uint64x2_t) (__a == __b);
++  return (uint64_t) __a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vceqq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_s32_f32 (float32_t __a)
+ {
+-  return (__a == __b);
++  return (int32_t) __a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vceqq_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvts_u32_f32 (float32_t __a)
+ {
+-  return (__a == __b);
++  return (uint32_t) __a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vceqq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_s32_f32 (float32x2_t __a)
+ {
+-  return (__a == __b);
++  return __builtin_aarch64_lbtruncv2sfv2si (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vceqq_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_u32_f32 (float32x2_t __a)
+ {
+-  return (__a == __b);
++  return __builtin_aarch64_lbtruncuv2sfv2si_us (__a);
+ }
+ 
+-/* vceq - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vceqs_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_s32_f32 (float32x4_t __a)
+ {
+-  return __a == __b ? -1 : 0;
++  return __builtin_aarch64_lbtruncv4sfv4si (__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vceqd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_u32_f32 (float32x4_t __a)
+ {
+-  return __a == __b ? -1ll : 0ll;
++  return __builtin_aarch64_lbtruncuv4sfv4si_us (__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vceqd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_s64_f64 (float64x1_t __a)
+ {
+-  return __a == __b ? -1ll : 0ll;
++  return (int64x1_t) {vcvtd_s64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vceqd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_u64_f64 (float64x1_t __a)
+ {
+-  return __a == __b ? -1ll : 0ll;
++  return (uint64x1_t) {vcvtd_u64_f64 (__a[0])};
+ }
+ 
+-/* vceqz - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vceqz_f32 (float32x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_s64_f64 (float64x2_t __a)
+ {
+-  return (uint32x2_t) (__a == 0.0f);
++  return __builtin_aarch64_lbtruncv2dfv2di (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceqz_f64 (float64x1_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_u64_f64 (float64x2_t __a)
+ {
+-  return (uint64x1_t) (__a == (float64x1_t) {0.0});
++  return __builtin_aarch64_lbtruncuv2dfv2di_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vceqz_p8 (poly8x8_t __a)
++/* vcvta  */
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtad_s64_f64 (float64_t __a)
+ {
+-  return (uint8x8_t) (__a == 0);
++  return __builtin_aarch64_lrounddfdi (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vceqz_s8 (int8x8_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtad_u64_f64 (float64_t __a)
+ {
+-  return (uint8x8_t) (__a == 0);
++  return __builtin_aarch64_lroundudfdi_us (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vceqz_s16 (int16x4_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtas_s32_f32 (float32_t __a)
+ {
+-  return (uint16x4_t) (__a == 0);
++  return __builtin_aarch64_lroundsfsi (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vceqz_s32 (int32x2_t __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtas_u32_f32 (float32_t __a)
+ {
+-  return (uint32x2_t) (__a == 0);
++  return __builtin_aarch64_lroundusfsi_us (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceqz_s64 (int64x1_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_s32_f32 (float32x2_t __a)
+ {
+-  return (uint64x1_t) (__a == __AARCH64_INT64_C (0));
++  return __builtin_aarch64_lroundv2sfv2si (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vceqz_u8 (uint8x8_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_u32_f32 (float32x2_t __a)
+ {
+-  return (__a == 0);
++  return __builtin_aarch64_lrounduv2sfv2si_us (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vceqz_u16 (uint16x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_s32_f32 (float32x4_t __a)
+ {
+-  return (__a == 0);
++  return __builtin_aarch64_lroundv4sfv4si (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vceqz_u32 (uint32x2_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_u32_f32 (float32x4_t __a)
+ {
+-  return (__a == 0);
++  return __builtin_aarch64_lrounduv4sfv4si_us (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceqz_u64 (uint64x1_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_s64_f64 (float64x1_t __a)
+ {
+-  return (__a == __AARCH64_UINT64_C (0));
++  return (int64x1_t) {vcvtad_s64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vceqzq_f32 (float32x4_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_u64_f64 (float64x1_t __a)
+ {
+-  return (uint32x4_t) (__a == 0.0f);
++  return (uint64x1_t) {vcvtad_u64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vceqzq_f64 (float64x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_s64_f64 (float64x2_t __a)
+ {
+-  return (uint64x2_t) (__a == 0.0f);
++  return __builtin_aarch64_lroundv2dfv2di (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vceqzq_p8 (poly8x16_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_u64_f64 (float64x2_t __a)
+ {
+-  return (uint8x16_t) (__a == 0);
++  return __builtin_aarch64_lrounduv2dfv2di_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vceqzq_s8 (int8x16_t __a)
++/* vcvtm  */
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmd_s64_f64 (float64_t __a)
+ {
+-  return (uint8x16_t) (__a == 0);
++  return __builtin_llfloor (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vceqzq_s16 (int16x8_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmd_u64_f64 (float64_t __a)
+ {
+-  return (uint16x8_t) (__a == 0);
++  return __builtin_aarch64_lfloorudfdi_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vceqzq_s32 (int32x4_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtms_s32_f32 (float32_t __a)
+ {
+-  return (uint32x4_t) (__a == 0);
++  return __builtin_ifloorf (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vceqzq_s64 (int64x2_t __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtms_u32_f32 (float32_t __a)
+ {
+-  return (uint64x2_t) (__a == __AARCH64_INT64_C (0));
++  return __builtin_aarch64_lfloorusfsi_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vceqzq_u8 (uint8x16_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_s32_f32 (float32x2_t __a)
+ {
+-  return (__a == 0);
++  return __builtin_aarch64_lfloorv2sfv2si (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vceqzq_u16 (uint16x8_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_u32_f32 (float32x2_t __a)
+ {
+-  return (__a == 0);
++  return __builtin_aarch64_lflooruv2sfv2si_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vceqzq_u32 (uint32x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_s32_f32 (float32x4_t __a)
+ {
+-  return (__a == 0);
++  return __builtin_aarch64_lfloorv4sfv4si (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vceqzq_u64 (uint64x2_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_u32_f32 (float32x4_t __a)
+ {
+-  return (__a == __AARCH64_UINT64_C (0));
++  return __builtin_aarch64_lflooruv4sfv4si_us (__a);
+ }
+ 
+-/* vceqz - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vceqzs_f32 (float32_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_s64_f64 (float64x1_t __a)
+ {
+-  return __a == 0.0f ? -1 : 0;
++  return (int64x1_t) {vcvtmd_s64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vceqzd_s64 (int64_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_u64_f64 (float64x1_t __a)
+ {
+-  return __a == 0 ? -1ll : 0ll;
++  return (uint64x1_t) {vcvtmd_u64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vceqzd_u64 (uint64_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_s64_f64 (float64x2_t __a)
+ {
+-  return __a == 0 ? -1ll : 0ll;
++  return __builtin_aarch64_lfloorv2dfv2di (__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vceqzd_f64 (float64_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_u64_f64 (float64x2_t __a)
+ {
+-  return __a == 0.0 ? -1ll : 0ll;
++  return __builtin_aarch64_lflooruv2dfv2di_us (__a);
+ }
+ 
+-/* vcge - vector.  */
++/* vcvtn  */
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcge_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnd_s64_f64 (float64_t __a)
+ {
+-  return (uint32x2_t) (__a >= __b);
++  return __builtin_aarch64_lfrintndfdi (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcge_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnd_u64_f64 (float64_t __a)
+ {
+-  return (uint64x1_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnudfdi_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcge_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtns_s32_f32 (float32_t __a)
+ {
+-  return (uint8x8_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnsfsi (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcge_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtns_u32_f32 (float32_t __a)
+ {
+-  return (uint16x4_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnusfsi_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcge_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_s32_f32 (float32x2_t __a)
+ {
+-  return (uint32x2_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnv2sfv2si (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcge_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_u32_f32 (float32x2_t __a)
+ {
+-  return (uint64x1_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnuv2sfv2si_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcge_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_s32_f32 (float32x4_t __a)
+ {
+-  return (__a >= __b);
++  return __builtin_aarch64_lfrintnv4sfv4si (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcge_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_u32_f32 (float32x4_t __a)
+ {
+-  return (__a >= __b);
++  return __builtin_aarch64_lfrintnuv4sfv4si_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcge_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_s64_f64 (float64x1_t __a)
+ {
+-  return (__a >= __b);
++  return (int64x1_t) {vcvtnd_s64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcge_u64 (uint64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_u64_f64 (float64x1_t __a)
+ {
+-  return (__a >= __b);
++  return (uint64x1_t) {vcvtnd_u64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgeq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_s64_f64 (float64x2_t __a)
+ {
+-  return (uint32x4_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnv2dfv2di (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgeq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_u64_f64 (float64x2_t __a)
+ {
+-  return (uint64x2_t) (__a >= __b);
++  return __builtin_aarch64_lfrintnuv2dfv2di_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcgeq_s8 (int8x16_t __a, int8x16_t __b)
++/* vcvtp  */
++
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpd_s64_f64 (float64_t __a)
+ {
+-  return (uint8x16_t) (__a >= __b);
++  return __builtin_llceil (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcgeq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpd_u64_f64 (float64_t __a)
+ {
+-  return (uint16x8_t) (__a >= __b);
++  return __builtin_aarch64_lceiludfdi_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgeq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtps_s32_f32 (float32_t __a)
+ {
+-  return (uint32x4_t) (__a >= __b);
++  return __builtin_iceilf (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgeq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtps_u32_f32 (float32_t __a)
+ {
+-  return (uint64x2_t) (__a >= __b);
++  return __builtin_aarch64_lceilusfsi_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcgeq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_s32_f32 (float32x2_t __a)
+ {
+-  return (__a >= __b);
++  return __builtin_aarch64_lceilv2sfv2si (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcgeq_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_u32_f32 (float32x2_t __a)
+ {
+-  return (__a >= __b);
++  return __builtin_aarch64_lceiluv2sfv2si_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgeq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_s32_f32 (float32x4_t __a)
+ {
+-  return (__a >= __b);
++  return __builtin_aarch64_lceilv4sfv4si (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgeq_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_u32_f32 (float32x4_t __a)
+ {
+-  return (__a >= __b);
++  return __builtin_aarch64_lceiluv4sfv4si_us (__a);
+ }
+ 
+-/* vcge - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcges_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_s64_f64 (float64x1_t __a)
+ {
+-  return __a >= __b ? -1 : 0;
++  return (int64x1_t) {vcvtpd_s64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcged_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_u64_f64 (float64x1_t __a)
+ {
+-  return __a >= __b ? -1ll : 0ll;
++  return (uint64x1_t) {vcvtpd_u64_f64 (__a[0])};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcged_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_s64_f64 (float64x2_t __a)
+ {
+-  return __a >= __b ? -1ll : 0ll;
++  return __builtin_aarch64_lceilv2dfv2di (__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcged_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_u64_f64 (float64x2_t __a)
+ {
+-  return __a >= __b ? -1ll : 0ll;
++  return __builtin_aarch64_lceiluv2dfv2di_us (__a);
+ }
+ 
+-/* vcgez - vector.  */
++/* vdup_n  */
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgez_f32 (float32x2_t __a)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_f16 (float16_t __a)
+ {
+-  return (uint32x2_t) (__a >= 0.0f);
++  return (float16x4_t) {__a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgez_f64 (float64x1_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_f32 (float32_t __a)
+ {
+-  return (uint64x1_t) (__a[0] >= (float64x1_t) {0.0});
++  return (float32x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcgez_s8 (int8x8_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_f64 (float64_t __a)
+ {
+-  return (uint8x8_t) (__a >= 0);
++  return (float64x1_t) {__a};
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcgez_s16 (int16x4_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_p8 (poly8_t __a)
+ {
+-  return (uint16x4_t) (__a >= 0);
++  return (poly8x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgez_s32 (int32x2_t __a)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_p16 (poly16_t __a)
+ {
+-  return (uint32x2_t) (__a >= 0);
++  return (poly16x4_t) {__a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgez_s64 (int64x1_t __a)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_p64 (poly64_t __a)
+ {
+-  return (uint64x1_t) (__a >= __AARCH64_INT64_C (0));
++  return (poly64x1_t) {__a};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgezq_f32 (float32x4_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_s8 (int8_t __a)
+ {
+-  return (uint32x4_t) (__a >= 0.0f);
++  return (int8x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgezq_f64 (float64x2_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_s16 (int16_t __a)
+ {
+-  return (uint64x2_t) (__a >= 0.0);
++  return (int16x4_t) {__a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcgezq_s8 (int8x16_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_s32 (int32_t __a)
+ {
+-  return (uint8x16_t) (__a >= 0);
++  return (int32x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcgezq_s16 (int16x8_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_s64 (int64_t __a)
+ {
+-  return (uint16x8_t) (__a >= 0);
++  return (int64x1_t) {__a};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgezq_s32 (int32x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_u8 (uint8_t __a)
+ {
+-  return (uint32x4_t) (__a >= 0);
++  return (uint8x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgezq_s64 (int64x2_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_u16 (uint16_t __a)
+ {
+-  return (uint64x2_t) (__a >= __AARCH64_INT64_C (0));
++  return (uint16x4_t) {__a, __a, __a, __a};
+ }
+ 
+-/* vcgez - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcgezs_f32 (float32_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_u32 (uint32_t __a)
+ {
+-  return __a >= 0.0f ? -1 : 0;
++  return (uint32x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgezd_s64 (int64_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_u64 (uint64_t __a)
+ {
+-  return __a >= 0 ? -1ll : 0ll;
++  return (uint64x1_t) {__a};
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgezd_f64 (float64_t __a)
++/* vdupq_n  */
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_f16 (float16_t __a)
+ {
+-  return __a >= 0.0 ? -1ll : 0ll;
++  return (float16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-/* vcgt - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgt_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_f32 (float32_t __a)
+ {
+-  return (uint32x2_t) (__a > __b);
++  return (float32x4_t) {__a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgt_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_f64 (float64_t __a)
+ {
+-  return (uint64x1_t) (__a > __b);
++  return (float64x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcgt_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_p8 (uint32_t __a)
+ {
+-  return (uint8x8_t) (__a > __b);
++  return (poly8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
++		       __a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcgt_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_p16 (uint32_t __a)
+ {
+-  return (uint16x4_t) (__a > __b);
++  return (poly16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgt_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_p64 (uint64_t __a)
+ {
+-  return (uint32x2_t) (__a > __b);
++  return (poly64x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgt_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_s8 (int32_t __a)
+ {
+-  return (uint64x1_t) (__a > __b);
++  return (int8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
++		      __a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcgt_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_s16 (int32_t __a)
+ {
+-  return (__a > __b);
++  return (int16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcgt_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_s32 (int32_t __a)
+ {
+-  return (__a > __b);
++  return (int32x4_t) {__a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgt_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_s64 (int64_t __a)
+ {
+-  return (__a > __b);
++  return (int64x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgt_u64 (uint64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_u8 (uint32_t __a)
+ {
+-  return (__a > __b);
++  return (uint8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
++		       __a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgtq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_u16 (uint32_t __a)
+ {
+-  return (uint32x4_t) (__a > __b);
++  return (uint16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgtq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_u32 (uint32_t __a)
+ {
+-  return (uint64x2_t) (__a > __b);
++  return (uint32x4_t) {__a, __a, __a, __a};
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcgtq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_u64 (uint64_t __a)
+ {
+-  return (uint8x16_t) (__a > __b);
++  return (uint64x2_t) {__a, __a};
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcgtq_s16 (int16x8_t __a, int16x8_t __b)
++/* vdup_lane  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_f16 (float16x4_t __a, const int __b)
+ {
+-  return (uint16x8_t) (__a > __b);
++  return __aarch64_vdup_lane_f16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgtq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_f32 (float32x2_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a > __b);
++  return __aarch64_vdup_lane_f32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgtq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_f64 (float64x1_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a > __b);
++  return __aarch64_vdup_lane_f64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcgtq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_p8 (poly8x8_t __a, const int __b)
+ {
+-  return (__a > __b);
++  return __aarch64_vdup_lane_p8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcgtq_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_p16 (poly16x4_t __a, const int __b)
+ {
+-  return (__a > __b);
++  return __aarch64_vdup_lane_p16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgtq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_p64 (poly64x1_t __a, const int __b)
+ {
+-  return (__a > __b);
++  return __aarch64_vdup_lane_p64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgtq_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_s8 (int8x8_t __a, const int __b)
+ {
+-  return (__a > __b);
++  return __aarch64_vdup_lane_s8 (__a, __b);
+ }
+ 
+-/* vcgt - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcgts_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_s16 (int16x4_t __a, const int __b)
+ {
+-  return __a > __b ? -1 : 0;
++  return __aarch64_vdup_lane_s16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgtd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_s32 (int32x2_t __a, const int __b)
+ {
+-  return __a > __b ? -1ll : 0ll;
++  return __aarch64_vdup_lane_s32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgtd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_s64 (int64x1_t __a, const int __b)
+ {
+-  return __a > __b ? -1ll : 0ll;
++  return __aarch64_vdup_lane_s64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgtd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_u8 (uint8x8_t __a, const int __b)
+ {
+-  return __a > __b ? -1ll : 0ll;
++  return __aarch64_vdup_lane_u8 (__a, __b);
+ }
+ 
+-/* vcgtz - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgtz_f32 (float32x2_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_u16 (uint16x4_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a > 0.0f);
++  return __aarch64_vdup_lane_u16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgtz_f64 (float64x1_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_u32 (uint32x2_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a > (float64x1_t) {0.0});
++  return __aarch64_vdup_lane_u32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcgtz_s8 (int8x8_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_u64 (uint64x1_t __a, const int __b)
+ {
+-  return (uint8x8_t) (__a > 0);
++  return __aarch64_vdup_lane_u64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcgtz_s16 (int16x4_t __a)
++/* vdup_laneq  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_f16 (float16x8_t __a, const int __b)
+ {
+-  return (uint16x4_t) (__a > 0);
++  return __aarch64_vdup_laneq_f16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcgtz_s32 (int32x2_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_f32 (float32x4_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a > 0);
++  return __aarch64_vdup_laneq_f32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcgtz_s64 (int64x1_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_f64 (float64x2_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a > __AARCH64_INT64_C (0));
++  return __aarch64_vdup_laneq_f64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgtzq_f32 (float32x4_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_p8 (poly8x16_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a > 0.0f);
++  return __aarch64_vdup_laneq_p8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgtzq_f64 (float64x2_t __a)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_p16 (poly16x8_t __a, const int __b)
+ {
+-    return (uint64x2_t) (__a > 0.0);
++  return __aarch64_vdup_laneq_p16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcgtzq_s8 (int8x16_t __a)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_p64 (poly64x2_t __a, const int __b)
+ {
+-  return (uint8x16_t) (__a > 0);
++  return __aarch64_vdup_laneq_p64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcgtzq_s16 (int16x8_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_s8 (int8x16_t __a, const int __b)
+ {
+-  return (uint16x8_t) (__a > 0);
++  return __aarch64_vdup_laneq_s8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcgtzq_s32 (int32x4_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_s16 (int16x8_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a > 0);
++  return __aarch64_vdup_laneq_s16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcgtzq_s64 (int64x2_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_s32 (int32x4_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a > __AARCH64_INT64_C (0));
++  return __aarch64_vdup_laneq_s32 (__a, __b);
+ }
+ 
+-/* vcgtz - scalar.  */
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_s64 (int64x2_t __a, const int __b)
++{
++  return __aarch64_vdup_laneq_s64 (__a, __b);
++}
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcgtzs_f32 (float32_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_u8 (uint8x16_t __a, const int __b)
+ {
+-  return __a > 0.0f ? -1 : 0;
++  return __aarch64_vdup_laneq_u8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgtzd_s64 (int64_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_u16 (uint16x8_t __a, const int __b)
+ {
+-  return __a > 0 ? -1ll : 0ll;
++  return __aarch64_vdup_laneq_u16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcgtzd_f64 (float64_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_u32 (uint32x4_t __a, const int __b)
+ {
+-  return __a > 0.0 ? -1ll : 0ll;
++  return __aarch64_vdup_laneq_u32 (__a, __b);
+ }
+ 
+-/* vcle - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcle_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_laneq_u64 (uint64x2_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a <= __b);
++  return __aarch64_vdup_laneq_u64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcle_f64 (float64x1_t __a, float64x1_t __b)
++/* vdupq_lane  */
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_f16 (float16x4_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a <= __b);
++  return __aarch64_vdupq_lane_f16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcle_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_f32 (float32x2_t __a, const int __b)
+ {
+-  return (uint8x8_t) (__a <= __b);
++  return __aarch64_vdupq_lane_f32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcle_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_f64 (float64x1_t __a, const int __b)
+ {
+-  return (uint16x4_t) (__a <= __b);
++  return __aarch64_vdupq_lane_f64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcle_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_p8 (poly8x8_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a <= __b);
++  return __aarch64_vdupq_lane_p8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcle_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_p16 (poly16x4_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a <= __b);
++  return __aarch64_vdupq_lane_p16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcle_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_p64 (poly64x1_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_lane_p64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcle_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_s8 (int8x8_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_lane_s8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcle_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_s16 (int16x4_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_lane_s16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcle_u64 (uint64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_s32 (int32x2_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_lane_s32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcleq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_s64 (int64x1_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a <= __b);
++  return __aarch64_vdupq_lane_s64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcleq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_u8 (uint8x8_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a <= __b);
++  return __aarch64_vdupq_lane_u8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcleq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_u16 (uint16x4_t __a, const int __b)
+ {
+-  return (uint8x16_t) (__a <= __b);
++  return __aarch64_vdupq_lane_u16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcleq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_u32 (uint32x2_t __a, const int __b)
+ {
+-  return (uint16x8_t) (__a <= __b);
++  return __aarch64_vdupq_lane_u32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcleq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_u64 (uint64x1_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a <= __b);
++  return __aarch64_vdupq_lane_u64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcleq_s64 (int64x2_t __a, int64x2_t __b)
++/* vdupq_laneq  */
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_f16 (float16x8_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a <= __b);
++  return __aarch64_vdupq_laneq_f16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcleq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_f32 (float32x4_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_laneq_f32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcleq_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_f64 (float64x2_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_laneq_f64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcleq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_p8 (poly8x16_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_laneq_p8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcleq_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_p16 (poly16x8_t __a, const int __b)
+ {
+-  return (__a <= __b);
++  return __aarch64_vdupq_laneq_p16 (__a, __b);
+ }
+ 
+-/* vcle - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcles_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_p64 (poly64x2_t __a, const int __b)
+ {
+-  return __a <= __b ? -1 : 0;
++  return __aarch64_vdupq_laneq_p64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcled_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_s8 (int8x16_t __a, const int __b)
+ {
+-  return __a <= __b ? -1ll : 0ll;
++  return __aarch64_vdupq_laneq_s8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcled_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_s16 (int16x8_t __a, const int __b)
+ {
+-  return __a <= __b ? -1ll : 0ll;
++  return __aarch64_vdupq_laneq_s16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcled_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_s32 (int32x4_t __a, const int __b)
+ {
+-  return __a <= __b ? -1ll : 0ll;
++  return __aarch64_vdupq_laneq_s32 (__a, __b);
+ }
+ 
+-/* vclez - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vclez_f32 (float32x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_s64 (int64x2_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a <= 0.0f);
++  return __aarch64_vdupq_laneq_s64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vclez_f64 (float64x1_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_u8 (uint8x16_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a <= (float64x1_t) {0.0});
++  return __aarch64_vdupq_laneq_u8 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vclez_s8 (int8x8_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_u16 (uint16x8_t __a, const int __b)
+ {
+-  return (uint8x8_t) (__a <= 0);
++  return __aarch64_vdupq_laneq_u16 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vclez_s16 (int16x4_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_u32 (uint32x4_t __a, const int __b)
+ {
+-  return (uint16x4_t) (__a <= 0);
++  return __aarch64_vdupq_laneq_u32 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vclez_s32 (int32x2_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_laneq_u64 (uint64x2_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a <= 0);
++  return __aarch64_vdupq_laneq_u64 (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vclez_s64 (int64x1_t __a)
++/* vdupb_lane  */
++__extension__ extern __inline poly8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupb_lane_p8 (poly8x8_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a <= __AARCH64_INT64_C (0));
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vclezq_f32 (float32x4_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupb_lane_s8 (int8x8_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a <= 0.0f);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vclezq_f64 (float64x2_t __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupb_lane_u8 (uint8x8_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a <= 0.0);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vclezq_s8 (int8x16_t __a)
++/* vduph_lane  */
++
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_lane_f16 (float16x4_t __a, const int __b)
+ {
+-  return (uint8x16_t) (__a <= 0);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vclezq_s16 (int16x8_t __a)
++__extension__ extern __inline poly16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_lane_p16 (poly16x4_t __a, const int __b)
+ {
+-  return (uint16x8_t) (__a <= 0);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vclezq_s32 (int32x4_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_lane_s16 (int16x4_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a <= 0);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vclezq_s64 (int64x2_t __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_lane_u16 (uint16x4_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a <= __AARCH64_INT64_C (0));
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-/* vclez - scalar.  */
++/* vdups_lane  */
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vclezs_f32 (float32_t __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdups_lane_f32 (float32x2_t __a, const int __b)
+ {
+-  return __a <= 0.0f ? -1 : 0;
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vclezd_s64 (int64_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdups_lane_s32 (int32x2_t __a, const int __b)
+ {
+-  return __a <= 0 ? -1ll : 0ll;
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vclezd_f64 (float64_t __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdups_lane_u32 (uint32x2_t __a, const int __b)
+ {
+-  return __a <= 0.0 ? -1ll : 0ll;
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-/* vclt - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vclt_f32 (float32x2_t __a, float32x2_t __b)
++/* vdupd_lane  */
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupd_lane_f64 (float64x1_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a < __b);
++  __AARCH64_LANE_CHECK (__a, __b);
++  return __a[0];
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vclt_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupd_lane_s64 (int64x1_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a < __b);
++  __AARCH64_LANE_CHECK (__a, __b);
++  return __a[0];
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vclt_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupd_lane_u64 (uint64x1_t __a, const int __b)
+ {
+-  return (uint8x8_t) (__a < __b);
++  __AARCH64_LANE_CHECK (__a, __b);
++  return __a[0];
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vclt_s16 (int16x4_t __a, int16x4_t __b)
++/* vdupb_laneq  */
++__extension__ extern __inline poly8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupb_laneq_p8 (poly8x16_t __a, const int __b)
+ {
+-  return (uint16x4_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vclt_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupb_laneq_s8 (int8x16_t __a, const int __b)
+ {
+-  return (uint32x2_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vclt_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupb_laneq_u8 (uint8x16_t __a, const int __b)
+ {
+-  return (uint64x1_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vclt_u8 (uint8x8_t __a, uint8x8_t __b)
+-{
+-  return (__a < __b);
+-}
++/* vduph_laneq  */
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vclt_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_laneq_f16 (float16x8_t __a, const int __b)
+ {
+-  return (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vclt_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline poly16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_laneq_p16 (poly16x8_t __a, const int __b)
+ {
+-  return (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vclt_u64 (uint64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_laneq_s16 (int16x8_t __a, const int __b)
+ {
+-  return (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcltq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vduph_laneq_u16 (uint16x8_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcltq_f64 (float64x2_t __a, float64x2_t __b)
++/* vdups_laneq  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdups_laneq_f32 (float32x4_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcltq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdups_laneq_s32 (int32x4_t __a, const int __b)
+ {
+-  return (uint8x16_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcltq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdups_laneq_u32 (uint32x4_t __a, const int __b)
+ {
+-  return (uint16x8_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcltq_s32 (int32x4_t __a, int32x4_t __b)
++/* vdupd_laneq  */
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupd_laneq_f64 (float64x2_t __a, const int __b)
+ {
+-  return (uint32x4_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcltq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupd_laneq_s64 (int64x2_t __a, const int __b)
+ {
+-  return (uint64x2_t) (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcltq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdupd_laneq_u64 (uint64x2_t __a, const int __b)
+ {
+-  return (__a < __b);
++  return __aarch64_vget_lane_any (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcltq_u16 (uint16x8_t __a, uint16x8_t __b)
++/* vext  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_f16 (float16x4_t __a, float16x4_t __b, __const int __c)
+ {
+-  return (__a < __b);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++			    (uint16x4_t) {4 - __c, 5 - __c, 6 - __c, 7 - __c});
++#else
++  return __builtin_shuffle (__a, __b,
++			    (uint16x4_t) {__c, __c + 1, __c + 2, __c + 3});
++#endif
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcltq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_f32 (float32x2_t __a, float32x2_t __b, __const int __c)
+ {
+-  return (__a < __b);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcltq_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_f64 (float64x1_t __a, float64x1_t __b, __const int __c)
+ {
+-  return (__a < __b);
++  __AARCH64_LANE_CHECK (__a, __c);
++  /* The only possible index to the assembler instruction returns element 0.  */
++  return __a;
+ }
+-
+-/* vclt - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vclts_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_p8 (poly8x8_t __a, poly8x8_t __b, __const int __c)
+ {
+-  return __a < __b ? -1 : 0;
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint8x8_t)
++      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
++#endif
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcltd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_p16 (poly16x4_t __a, poly16x4_t __b, __const int __c)
+ {
+-  return __a < __b ? -1ll : 0ll;
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
++#endif
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcltd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_p64 (poly64x1_t __a, poly64x1_t __b, __const int __c)
+ {
+-  return __a < __b ? -1ll : 0ll;
++  __AARCH64_LANE_CHECK (__a, __c);
++  /* The only possible index to the assembler instruction returns element 0.  */
++  return __a;
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcltd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_s8 (int8x8_t __a, int8x8_t __b, __const int __c)
+ {
+-  return __a < __b ? -1ll : 0ll;
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint8x8_t)
++      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
++#endif
+ }
+ 
+-/* vcltz - vector.  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcltz_f32 (float32x2_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_s16 (int16x4_t __a, int16x4_t __b, __const int __c)
+ {
+-  return (uint32x2_t) (__a < 0.0f);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
++#endif
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcltz_f64 (float64x1_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_s32 (int32x2_t __a, int32x2_t __b, __const int __c)
+ {
+-  return (uint64x1_t) (__a < (float64x1_t) {0.0});
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcltz_s8 (int8x8_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_s64 (int64x1_t __a, int64x1_t __b, __const int __c)
+ {
+-  return (uint8x8_t) (__a < 0);
++  __AARCH64_LANE_CHECK (__a, __c);
++  /* The only possible index to the assembler instruction returns element 0.  */
++  return __a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vcltz_s16 (int16x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_u8 (uint8x8_t __a, uint8x8_t __b, __const int __c)
+ {
+-  return (uint16x4_t) (__a < 0);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint8x8_t)
++      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
++#endif
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcltz_s32 (int32x2_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_u16 (uint16x4_t __a, uint16x4_t __b, __const int __c)
+ {
+-  return (uint32x2_t) (__a < 0);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
++#endif
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcltz_s64 (int64x1_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_u32 (uint32x2_t __a, uint32x2_t __b, __const int __c)
+ {
+-  return (uint64x1_t) (__a < __AARCH64_INT64_C (0));
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcltzq_f32 (float32x4_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vext_u64 (uint64x1_t __a, uint64x1_t __b, __const int __c)
+ {
+-  return (uint32x4_t) (__a < 0.0f);
++  __AARCH64_LANE_CHECK (__a, __c);
++  /* The only possible index to the assembler instruction returns element 0.  */
++  return __a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcltzq_f64 (float64x2_t __a)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_f16 (float16x8_t __a, float16x8_t __b, __const int __c)
+ {
+-  return (uint64x2_t) (__a < 0.0);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++			    (uint16x8_t) {8 - __c, 9 - __c, 10 - __c, 11 - __c,
++					  12 - __c, 13 - __c, 14 - __c,
++					  15 - __c});
++#else
++  return __builtin_shuffle (__a, __b,
++			    (uint16x8_t) {__c, __c + 1, __c + 2, __c + 3,
++					  __c + 4, __c + 5, __c + 6, __c + 7});
++#endif
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcltzq_s8 (int8x16_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_f32 (float32x4_t __a, float32x4_t __b, __const int __c)
+ {
+-  return (uint8x16_t) (__a < 0);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
++#endif
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vcltzq_s16 (int16x8_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_f64 (float64x2_t __a, float64x2_t __b, __const int __c)
+ {
+-  return (uint16x8_t) (__a < 0);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcltzq_s32 (int32x4_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_p8 (poly8x16_t __a, poly8x16_t __b, __const int __c)
+ {
+-  return (uint32x4_t) (__a < 0);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint8x16_t)
++      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
++       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
++       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
++#endif
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcltzq_s64 (int64x2_t __a)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_p16 (poly16x8_t __a, poly16x8_t __b, __const int __c)
+ {
+-  return (uint64x2_t) (__a < __AARCH64_INT64_C (0));
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint16x8_t)
++      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
++#endif
+ }
+ 
+-/* vcltz - scalar.  */
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcltzs_f32 (float32_t __a)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_p64 (poly64x2_t __a, poly64x2_t __b, __const int __c)
+ {
+-  return __a < 0.0f ? -1 : 0;
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcltzd_s64 (int64_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_s8 (int8x16_t __a, int8x16_t __b, __const int __c)
+ {
+-  return __a < 0 ? -1ll : 0ll;
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint8x16_t)
++      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
++       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
++       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
++#endif
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcltzd_f64 (float64_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_s16 (int16x8_t __a, int16x8_t __b, __const int __c)
+ {
+-  return __a < 0.0 ? -1ll : 0ll;
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint16x8_t)
++      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
++#endif
+ }
+ 
+-/* vcls.  */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vcls_s8 (int8x8_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_s32 (int32x4_t __a, int32x4_t __b, __const int __c)
+ {
+-  return __builtin_aarch64_clrsbv8qi (__a);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
++#endif
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vcls_s16 (int16x4_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_s64 (int64x2_t __a, int64x2_t __b, __const int __c)
+ {
+-  return __builtin_aarch64_clrsbv4hi (__a);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vcls_s32 (int32x2_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_u8 (uint8x16_t __a, uint8x16_t __b, __const int __c)
+ {
+-  return __builtin_aarch64_clrsbv2si (__a);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint8x16_t)
++      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
++       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
++       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
++#endif
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vclsq_s8 (int8x16_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_u16 (uint16x8_t __a, uint16x8_t __b, __const int __c)
+ {
+-  return __builtin_aarch64_clrsbv16qi (__a);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint16x8_t)
++      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
++#endif
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vclsq_s16 (int16x8_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_u32 (uint32x4_t __a, uint32x4_t __b, __const int __c)
+ {
+-  return __builtin_aarch64_clrsbv8hi (__a);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a,
++      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
++#endif
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vclsq_s32 (int32x4_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_u64 (uint64x2_t __a, uint64x2_t __b, __const int __c)
+ {
+-  return __builtin_aarch64_clrsbv4si (__a);
++  __AARCH64_LANE_CHECK (__a, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
++#endif
+ }
+ 
+-/* vclz.  */
++/* vfma  */
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vclz_s8 (int8x8_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
+ {
+-  return __builtin_aarch64_clzv8qi (__a);
++  return (float64x1_t) {__builtin_fma (__b[0], __c[0], __a[0])};
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vclz_s16 (int16x4_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+-  return __builtin_aarch64_clzv4hi (__a);
++  return __builtin_aarch64_fmav2sf (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vclz_s32 (int32x2_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+-  return __builtin_aarch64_clzv2si (__a);
++  return __builtin_aarch64_fmav4sf (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vclz_u8 (uint8x8_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_f64 (float64x2_t __a, float64x2_t __b, float64x2_t __c)
+ {
+-  return (uint8x8_t)__builtin_aarch64_clzv8qi ((int8x8_t)__a);
++  return __builtin_aarch64_fmav2df (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vclz_u16 (uint16x4_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
+ {
+-  return (uint16x4_t)__builtin_aarch64_clzv4hi ((int16x4_t)__a);
++  return __builtin_aarch64_fmav2sf (__b, vdup_n_f32 (__c), __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vclz_u32 (uint32x2_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_n_f64 (float64x1_t __a, float64x1_t __b, float64_t __c)
+ {
+-  return (uint32x2_t)__builtin_aarch64_clzv2si ((int32x2_t)__a);
++  return (float64x1_t) {__b[0] * __c + __a[0]};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vclzq_s8 (int8x16_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
+ {
+-  return __builtin_aarch64_clzv16qi (__a);
++  return __builtin_aarch64_fmav4sf (__b, vdupq_n_f32 (__c), __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vclzq_s16 (int16x8_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_n_f64 (float64x2_t __a, float64x2_t __b, float64_t __c)
+ {
+-  return __builtin_aarch64_clzv8hi (__a);
++  return __builtin_aarch64_fmav2df (__b, vdupq_n_f64 (__c), __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vclzq_s32 (int32x4_t __a)
++/* vfma_lane  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_lane_f32 (float32x2_t __a, float32x2_t __b,
++	       float32x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_clzv4si (__a);
++  return __builtin_aarch64_fmav2sf (__b,
++				    __aarch64_vdup_lane_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vclzq_u8 (uint8x16_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_lane_f64 (float64x1_t __a, float64x1_t __b,
++	       float64x1_t __c, const int __lane)
+ {
+-  return (uint8x16_t)__builtin_aarch64_clzv16qi ((int8x16_t)__a);
++  return (float64x1_t) {__builtin_fma (__b[0], __c[0], __a[0])};
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vclzq_u16 (uint16x8_t __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmad_lane_f64 (float64_t __a, float64_t __b,
++	        float64x1_t __c, const int __lane)
+ {
+-  return (uint16x8_t)__builtin_aarch64_clzv8hi ((int16x8_t)__a);
++  return __builtin_fma (__b, __c[0], __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vclzq_u32 (uint32x4_t __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmas_lane_f32 (float32_t __a, float32_t __b,
++	        float32x2_t __c, const int __lane)
+ {
+-  return (uint32x4_t)__builtin_aarch64_clzv4si ((int32x4_t)__a);
++  return __builtin_fmaf (__b, __aarch64_vget_lane_any (__c, __lane), __a);
+ }
+ 
+-/* vcnt.  */
++/* vfma_laneq  */
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vcnt_p8 (poly8x8_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_laneq_f32 (float32x2_t __a, float32x2_t __b,
++	        float32x4_t __c, const int __lane)
+ {
+-  return (poly8x8_t) __builtin_aarch64_popcountv8qi ((int8x8_t) __a);
++  return __builtin_aarch64_fmav2sf (__b,
++				    __aarch64_vdup_laneq_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vcnt_s8 (int8x8_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_laneq_f64 (float64x1_t __a, float64x1_t __b,
++	        float64x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_popcountv8qi (__a);
++  float64_t __c0 = __aarch64_vget_lane_any (__c, __lane);
++  return (float64x1_t) {__builtin_fma (__b[0], __c0, __a[0])};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vcnt_u8 (uint8x8_t __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmad_laneq_f64 (float64_t __a, float64_t __b,
++	         float64x2_t __c, const int __lane)
+ {
+-  return (uint8x8_t) __builtin_aarch64_popcountv8qi ((int8x8_t) __a);
++  return __builtin_fma (__b, __aarch64_vget_lane_any (__c, __lane), __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vcntq_p8 (poly8x16_t __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmas_laneq_f32 (float32_t __a, float32_t __b,
++		 float32x4_t __c, const int __lane)
+ {
+-  return (poly8x16_t) __builtin_aarch64_popcountv16qi ((int8x16_t) __a);
++  return __builtin_fmaf (__b, __aarch64_vget_lane_any (__c, __lane), __a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vcntq_s8 (int8x16_t __a)
++/* vfmaq_lane  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_lane_f32 (float32x4_t __a, float32x4_t __b,
++	        float32x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_popcountv16qi (__a);
++  return __builtin_aarch64_fmav4sf (__b,
++				    __aarch64_vdupq_lane_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vcntq_u8 (uint8x16_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_lane_f64 (float64x2_t __a, float64x2_t __b,
++	        float64x1_t __c, const int __lane)
+ {
+-  return (uint8x16_t) __builtin_aarch64_popcountv16qi ((int8x16_t) __a);
++  return __builtin_aarch64_fmav2df (__b, vdupq_n_f64 (__c[0]), __a);
+ }
+ 
+-/* vcvt (double -> float).  */
++/* vfmaq_laneq  */
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
+-vcvt_f16_f32 (float32x4_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_laneq_f32 (float32x4_t __a, float32x4_t __b,
++	         float32x4_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_float_truncate_lo_v4hf (__a);
++  return __builtin_aarch64_fmav4sf (__b,
++				    __aarch64_vdupq_laneq_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
+-vcvt_high_f16_f32 (float16x4_t __a, float32x4_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_laneq_f64 (float64x2_t __a, float64x2_t __b,
++	         float64x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_float_truncate_hi_v8hf (__a, __b);
++  return __builtin_aarch64_fmav2df (__b,
++				    __aarch64_vdupq_laneq_f64 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vcvt_f32_f64 (float64x2_t __a)
++/* vfms  */
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
+ {
+-  return __builtin_aarch64_float_truncate_lo_v2sf (__a);
++  return (float64x1_t) {__builtin_fma (-__b[0], __c[0], __a[0])};
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vcvt_high_f32_f64 (float32x2_t __a, float64x2_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+-  return __builtin_aarch64_float_truncate_hi_v4sf (__a, __b);
++  return __builtin_aarch64_fmav2sf (-__b, __c, __a);
+ }
+ 
+-/* vcvt (float -> double).  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vcvt_f32_f16 (float16x4_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+-  return __builtin_aarch64_float_extend_lo_v4sf (__a);
++  return __builtin_aarch64_fmav4sf (-__b, __c, __a);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vcvt_f64_f32 (float32x2_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_f64 (float64x2_t __a, float64x2_t __b, float64x2_t __c)
+ {
+-
+-  return __builtin_aarch64_float_extend_lo_v2df (__a);
++  return __builtin_aarch64_fmav2df (-__b, __c, __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vcvt_high_f32_f16 (float16x8_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
+ {
+-  return __builtin_aarch64_vec_unpacks_hi_v8hf (__a);
++  return __builtin_aarch64_fmav2sf (-__b, vdup_n_f32 (__c), __a);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vcvt_high_f64_f32 (float32x4_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_n_f64 (float64x1_t __a, float64x1_t __b, float64_t __c)
+ {
+-  return __builtin_aarch64_vec_unpacks_hi_v4sf (__a);
++  return (float64x1_t) {-__b[0] * __c + __a[0]};
+ }
+ 
+-/* vcvt  (<u>int -> float)  */
+-
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vcvtd_f64_s64 (int64_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
+ {
+-  return (float64_t) __a;
++  return __builtin_aarch64_fmav4sf (-__b, vdupq_n_f32 (__c), __a);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vcvtd_f64_u64 (uint64_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_n_f64 (float64x2_t __a, float64x2_t __b, float64_t __c)
+ {
+-  return (float64_t) __a;
++  return __builtin_aarch64_fmav2df (-__b, vdupq_n_f64 (__c), __a);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vcvts_f32_s32 (int32_t __a)
++/* vfms_lane  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_lane_f32 (float32x2_t __a, float32x2_t __b,
++	       float32x2_t __c, const int __lane)
+ {
+-  return (float32_t) __a;
++  return __builtin_aarch64_fmav2sf (-__b,
++				    __aarch64_vdup_lane_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vcvts_f32_u32 (uint32_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_lane_f64 (float64x1_t __a, float64x1_t __b,
++	       float64x1_t __c, const int __lane)
+ {
+-  return (float32_t) __a;
++  return (float64x1_t) {__builtin_fma (-__b[0], __c[0], __a[0])};
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vcvt_f32_s32 (int32x2_t __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsd_lane_f64 (float64_t __a, float64_t __b,
++	        float64x1_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_floatv2siv2sf (__a);
++  return __builtin_fma (-__b, __c[0], __a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vcvt_f32_u32 (uint32x2_t __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmss_lane_f32 (float32_t __a, float32_t __b,
++	        float32x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_floatunsv2siv2sf ((int32x2_t) __a);
++  return __builtin_fmaf (-__b, __aarch64_vget_lane_any (__c, __lane), __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vcvtq_f32_s32 (int32x4_t __a)
++/* vfms_laneq  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_laneq_f32 (float32x2_t __a, float32x2_t __b,
++	        float32x4_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_floatv4siv4sf (__a);
++  return __builtin_aarch64_fmav2sf (-__b,
++				    __aarch64_vdup_laneq_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vcvtq_f32_u32 (uint32x4_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_laneq_f64 (float64x1_t __a, float64x1_t __b,
++	        float64x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_floatunsv4siv4sf ((int32x4_t) __a);
++  float64_t __c0 = __aarch64_vget_lane_any (__c, __lane);
++  return (float64x1_t) {__builtin_fma (-__b[0], __c0, __a[0])};
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vcvtq_f64_s64 (int64x2_t __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsd_laneq_f64 (float64_t __a, float64_t __b,
++	         float64x2_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_floatv2div2df (__a);
++  return __builtin_fma (-__b, __aarch64_vget_lane_any (__c, __lane), __a);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vcvtq_f64_u64 (uint64x2_t __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmss_laneq_f32 (float32_t __a, float32_t __b,
++		 float32x4_t __c, const int __lane)
+ {
+-  return __builtin_aarch64_floatunsv2div2df ((int64x2_t) __a);
++  return __builtin_fmaf (-__b, __aarch64_vget_lane_any (__c, __lane), __a);
+ }
+ 
+-/* vcvt (float -> <u>int)  */
++/* vfmsq_lane  */
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vcvtd_s64_f64 (float64_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_lane_f32 (float32x4_t __a, float32x4_t __b,
++	        float32x2_t __c, const int __lane)
+ {
+-  return (int64_t) __a;
++  return __builtin_aarch64_fmav4sf (-__b,
++				    __aarch64_vdupq_lane_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcvtd_u64_f64 (float64_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_lane_f64 (float64x2_t __a, float64x2_t __b,
++	        float64x1_t __c, const int __lane)
+ {
+-  return (uint64_t) __a;
++  return __builtin_aarch64_fmav2df (-__b, vdupq_n_f64 (__c[0]), __a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vcvts_s32_f32 (float32_t __a)
++/* vfmsq_laneq  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_laneq_f32 (float32x4_t __a, float32x4_t __b,
++	         float32x4_t __c, const int __lane)
+ {
+-  return (int32_t) __a;
++  return __builtin_aarch64_fmav4sf (-__b,
++				    __aarch64_vdupq_laneq_f32 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcvts_u32_f32 (float32_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_laneq_f64 (float64x2_t __a, float64x2_t __b,
++	         float64x2_t __c, const int __lane)
+ {
+-  return (uint32_t) __a;
++  return __builtin_aarch64_fmav2df (-__b,
++				    __aarch64_vdupq_laneq_f64 (__c, __lane),
++				    __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vcvt_s32_f32 (float32x2_t __a)
++/* vld1 */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_f16 (const float16_t *__a)
+ {
+-  return __builtin_aarch64_lbtruncv2sfv2si (__a);
++  return __builtin_aarch64_ld1v4hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcvt_u32_f32 (float32x2_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_f32 (const float32_t *a)
+ {
+-  return __builtin_aarch64_lbtruncuv2sfv2si_us (__a);
++  return __builtin_aarch64_ld1v2sf ((const __builtin_aarch64_simd_sf *) a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vcvtq_s32_f32 (float32x4_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_f64 (const float64_t *a)
+ {
+-  return __builtin_aarch64_lbtruncv4sfv4si (__a);
++  return (float64x1_t) {*a};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcvtq_u32_f32 (float32x4_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_p8 (const poly8_t *a)
+ {
+-  return __builtin_aarch64_lbtruncuv4sfv4si_us (__a);
++  return (poly8x8_t)
++    __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vcvt_s64_f64 (float64x1_t __a)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_p16 (const poly16_t *a)
+ {
+-  return (int64x1_t) {vcvtd_s64_f64 (__a[0])};
++  return (poly16x4_t)
++    __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcvt_u64_f64 (float64x1_t __a)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_p64 (const poly64_t *a)
+ {
+-  return (uint64x1_t) {vcvtd_u64_f64 (__a[0])};
++  return (poly64x1_t) {*a};
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vcvtq_s64_f64 (float64x2_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_s8 (const int8_t *a)
+ {
+-  return __builtin_aarch64_lbtruncv2dfv2di (__a);
++  return __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcvtq_u64_f64 (float64x2_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_s16 (const int16_t *a)
+ {
+-  return __builtin_aarch64_lbtruncuv2dfv2di_us (__a);
++  return __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a);
+ }
+ 
+-/* vcvta  */
+-
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vcvtad_s64_f64 (float64_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_s32 (const int32_t *a)
+ {
+-  return __builtin_aarch64_lrounddfdi (__a);
++  return __builtin_aarch64_ld1v2si ((const __builtin_aarch64_simd_si *) a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcvtad_u64_f64 (float64_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_s64 (const int64_t *a)
+ {
+-  return __builtin_aarch64_lroundudfdi_us (__a);
++  return (int64x1_t) {*a};
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vcvtas_s32_f32 (float32_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_u8 (const uint8_t *a)
+ {
+-  return __builtin_aarch64_lroundsfsi (__a);
++  return (uint8x8_t)
++    __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcvtas_u32_f32 (float32_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_u16 (const uint16_t *a)
+ {
+-  return __builtin_aarch64_lroundusfsi_us (__a);
++  return (uint16x4_t)
++    __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vcvta_s32_f32 (float32x2_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_u32 (const uint32_t *a)
+ {
+-  return __builtin_aarch64_lroundv2sfv2si (__a);
++  return (uint32x2_t)
++    __builtin_aarch64_ld1v2si ((const __builtin_aarch64_simd_si *) a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcvta_u32_f32 (float32x2_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_u64 (const uint64_t *a)
+ {
+-  return __builtin_aarch64_lrounduv2sfv2si_us (__a);
++  return (uint64x1_t) {*a};
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vcvtaq_s32_f32 (float32x4_t __a)
++/* vld1q */
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_f16 (const float16_t *__a)
+ {
+-  return __builtin_aarch64_lroundv4sfv4si (__a);
++  return __builtin_aarch64_ld1v8hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcvtaq_u32_f32 (float32x4_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_f32 (const float32_t *a)
+ {
+-  return __builtin_aarch64_lrounduv4sfv4si_us (__a);
++  return __builtin_aarch64_ld1v4sf ((const __builtin_aarch64_simd_sf *) a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vcvta_s64_f64 (float64x1_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_f64 (const float64_t *a)
+ {
+-  return (int64x1_t) {vcvtad_s64_f64 (__a[0])};
++  return __builtin_aarch64_ld1v2df ((const __builtin_aarch64_simd_df *) a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcvta_u64_f64 (float64x1_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_p8 (const poly8_t *a)
+ {
+-  return (uint64x1_t) {vcvtad_u64_f64 (__a[0])};
++  return (poly8x16_t)
++    __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vcvtaq_s64_f64 (float64x2_t __a)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_p16 (const poly16_t *a)
+ {
+-  return __builtin_aarch64_lroundv2dfv2di (__a);
++  return (poly16x8_t)
++    __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcvtaq_u64_f64 (float64x2_t __a)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_p64 (const poly64_t *a)
+ {
+-  return __builtin_aarch64_lrounduv2dfv2di_us (__a);
++  return (poly64x2_t)
++    __builtin_aarch64_ld1v2di ((const __builtin_aarch64_simd_di *) a);
+ }
+ 
+-/* vcvtm  */
+-
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vcvtmd_s64_f64 (float64_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_s8 (const int8_t *a)
+ {
+-  return __builtin_llfloor (__a);
++  return __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcvtmd_u64_f64 (float64_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_s16 (const int16_t *a)
+ {
+-  return __builtin_aarch64_lfloorudfdi_us (__a);
++  return __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vcvtms_s32_f32 (float32_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_s32 (const int32_t *a)
+ {
+-  return __builtin_ifloorf (__a);
++  return __builtin_aarch64_ld1v4si ((const __builtin_aarch64_simd_si *) a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcvtms_u32_f32 (float32_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_s64 (const int64_t *a)
+ {
+-  return __builtin_aarch64_lfloorusfsi_us (__a);
++  return __builtin_aarch64_ld1v2di ((const __builtin_aarch64_simd_di *) a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vcvtm_s32_f32 (float32x2_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_u8 (const uint8_t *a)
+ {
+-  return __builtin_aarch64_lfloorv2sfv2si (__a);
++  return (uint8x16_t)
++    __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcvtm_u32_f32 (float32x2_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_u16 (const uint16_t *a)
+ {
+-  return __builtin_aarch64_lflooruv2sfv2si_us (__a);
++  return (uint16x8_t)
++    __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vcvtmq_s32_f32 (float32x4_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_u32 (const uint32_t *a)
+ {
+-  return __builtin_aarch64_lfloorv4sfv4si (__a);
++  return (uint32x4_t)
++    __builtin_aarch64_ld1v4si ((const __builtin_aarch64_simd_si *) a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcvtmq_u32_f32 (float32x4_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_u64 (const uint64_t *a)
+ {
+-  return __builtin_aarch64_lflooruv4sfv4si_us (__a);
++  return (uint64x2_t)
++    __builtin_aarch64_ld1v2di ((const __builtin_aarch64_simd_di *) a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vcvtm_s64_f64 (float64x1_t __a)
++/* vld1_dup  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_f16 (const float16_t* __a)
+ {
+-  return (int64x1_t) {vcvtmd_s64_f64 (__a[0])};
++  return vdup_n_f16 (*__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcvtm_u64_f64 (float64x1_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_f32 (const float32_t* __a)
+ {
+-  return (uint64x1_t) {vcvtmd_u64_f64 (__a[0])};
++  return vdup_n_f32 (*__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vcvtmq_s64_f64 (float64x2_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_f64 (const float64_t* __a)
+ {
+-  return __builtin_aarch64_lfloorv2dfv2di (__a);
++  return vdup_n_f64 (*__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcvtmq_u64_f64 (float64x2_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_p8 (const poly8_t* __a)
+ {
+-  return __builtin_aarch64_lflooruv2dfv2di_us (__a);
++  return vdup_n_p8 (*__a);
+ }
+ 
+-/* vcvtn  */
+-
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vcvtnd_s64_f64 (float64_t __a)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_p16 (const poly16_t* __a)
+ {
+-  return __builtin_aarch64_lfrintndfdi (__a);
++  return vdup_n_p16 (*__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcvtnd_u64_f64 (float64_t __a)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_p64 (const poly64_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnudfdi_us (__a);
++  return vdup_n_p64 (*__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vcvtns_s32_f32 (float32_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_s8 (const int8_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnsfsi (__a);
++  return vdup_n_s8 (*__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcvtns_u32_f32 (float32_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_s16 (const int16_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnusfsi_us (__a);
++  return vdup_n_s16 (*__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vcvtn_s32_f32 (float32x2_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_s32 (const int32_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnv2sfv2si (__a);
++  return vdup_n_s32 (*__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcvtn_u32_f32 (float32x2_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_s64 (const int64_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnuv2sfv2si_us (__a);
++  return vdup_n_s64 (*__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vcvtnq_s32_f32 (float32x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_u8 (const uint8_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnv4sfv4si (__a);
++  return vdup_n_u8 (*__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcvtnq_u32_f32 (float32x4_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_u16 (const uint16_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnuv4sfv4si_us (__a);
++  return vdup_n_u16 (*__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vcvtn_s64_f64 (float64x1_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_u32 (const uint32_t* __a)
+ {
+-  return (int64x1_t) {vcvtnd_s64_f64 (__a[0])};
++  return vdup_n_u32 (*__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcvtn_u64_f64 (float64x1_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_dup_u64 (const uint64_t* __a)
+ {
+-  return (uint64x1_t) {vcvtnd_u64_f64 (__a[0])};
++  return vdup_n_u64 (*__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vcvtnq_s64_f64 (float64x2_t __a)
++/* vld1q_dup  */
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_f16 (const float16_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnv2dfv2di (__a);
++  return vdupq_n_f16 (*__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcvtnq_u64_f64 (float64x2_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_f32 (const float32_t* __a)
+ {
+-  return __builtin_aarch64_lfrintnuv2dfv2di_us (__a);
++  return vdupq_n_f32 (*__a);
+ }
+ 
+-/* vcvtp  */
+-
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vcvtpd_s64_f64 (float64_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_f64 (const float64_t* __a)
+ {
+-  return __builtin_llceil (__a);
++  return vdupq_n_f64 (*__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vcvtpd_u64_f64 (float64_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_p8 (const poly8_t* __a)
+ {
+-  return __builtin_aarch64_lceiludfdi_us (__a);
++  return vdupq_n_p8 (*__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vcvtps_s32_f32 (float32_t __a)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_p16 (const poly16_t* __a)
+ {
+-  return __builtin_iceilf (__a);
++  return vdupq_n_p16 (*__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vcvtps_u32_f32 (float32_t __a)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_p64 (const poly64_t* __a)
+ {
+-  return __builtin_aarch64_lceilusfsi_us (__a);
++  return vdupq_n_p64 (*__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vcvtp_s32_f32 (float32x2_t __a)
++ __extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_s8 (const int8_t* __a)
+ {
+-  return __builtin_aarch64_lceilv2sfv2si (__a);
++  return vdupq_n_s8 (*__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vcvtp_u32_f32 (float32x2_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_s16 (const int16_t* __a)
+ {
+-  return __builtin_aarch64_lceiluv2sfv2si_us (__a);
++  return vdupq_n_s16 (*__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vcvtpq_s32_f32 (float32x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_s32 (const int32_t* __a)
+ {
+-  return __builtin_aarch64_lceilv4sfv4si (__a);
++  return vdupq_n_s32 (*__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vcvtpq_u32_f32 (float32x4_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_s64 (const int64_t* __a)
+ {
+-  return __builtin_aarch64_lceiluv4sfv4si_us (__a);
++  return vdupq_n_s64 (*__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vcvtp_s64_f64 (float64x1_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_u8 (const uint8_t* __a)
+ {
+-  return (int64x1_t) {vcvtpd_s64_f64 (__a[0])};
++  return vdupq_n_u8 (*__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vcvtp_u64_f64 (float64x1_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_u16 (const uint16_t* __a)
+ {
+-  return (uint64x1_t) {vcvtpd_u64_f64 (__a[0])};
++  return vdupq_n_u16 (*__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vcvtpq_s64_f64 (float64x2_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_u32 (const uint32_t* __a)
+ {
+-  return __builtin_aarch64_lceilv2dfv2di (__a);
++  return vdupq_n_u32 (*__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vcvtpq_u64_f64 (float64x2_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_dup_u64 (const uint64_t* __a)
+ {
+-  return __builtin_aarch64_lceiluv2dfv2di_us (__a);
++  return vdupq_n_u64 (*__a);
+ }
+ 
+-/* vdup_n  */
++/* vld1_lane  */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vdup_n_f32 (float32_t __a)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_f16 (const float16_t *__src, float16x4_t __vec, const int __lane)
+ {
+-  return (float32x2_t) {__a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vdup_n_f64 (float64_t __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_f32 (const float32_t *__src, float32x2_t __vec, const int __lane)
+ {
+-  return (float64x1_t) {__a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vdup_n_p8 (poly8_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_f64 (const float64_t *__src, float64x1_t __vec, const int __lane)
+ {
+-  return (poly8x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vdup_n_p16 (poly16_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_p8 (const poly8_t *__src, poly8x8_t __vec, const int __lane)
+ {
+-  return (poly16x4_t) {__a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vdup_n_s8 (int8_t __a)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_p16 (const poly16_t *__src, poly16x4_t __vec, const int __lane)
+ {
+-  return (int8x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vdup_n_s16 (int16_t __a)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_p64 (const poly64_t *__src, poly64x1_t __vec, const int __lane)
+ {
+-  return (int16x4_t) {__a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vdup_n_s32 (int32_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_s8 (const int8_t *__src, int8x8_t __vec, const int __lane)
+ {
+-  return (int32x2_t) {__a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vdup_n_s64 (int64_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_s16 (const int16_t *__src, int16x4_t __vec, const int __lane)
+ {
+-  return (int64x1_t) {__a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vdup_n_u8 (uint8_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_s32 (const int32_t *__src, int32x2_t __vec, const int __lane)
+ {
+-  return (uint8x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vdup_n_u16 (uint16_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_s64 (const int64_t *__src, int64x1_t __vec, const int __lane)
+ {
+-  return (uint16x4_t) {__a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vdup_n_u32 (uint32_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_u8 (const uint8_t *__src, uint8x8_t __vec, const int __lane)
+ {
+-  return (uint32x2_t) {__a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vdup_n_u64 (uint64_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_u16 (const uint16_t *__src, uint16x4_t __vec, const int __lane)
+ {
+-  return (uint64x1_t) {__a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-/* vdupq_n  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vdupq_n_f32 (float32_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_u32 (const uint32_t *__src, uint32x2_t __vec, const int __lane)
+ {
+-  return (float32x4_t) {__a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vdupq_n_f64 (float64_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1_lane_u64 (const uint64_t *__src, uint64x1_t __vec, const int __lane)
+ {
+-  return (float64x2_t) {__a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vdupq_n_p8 (uint32_t __a)
++/* vld1q_lane  */
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_f16 (const float16_t *__src, float16x8_t __vec, const int __lane)
+ {
+-  return (poly8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
+-		       __a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vdupq_n_p16 (uint32_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_f32 (const float32_t *__src, float32x4_t __vec, const int __lane)
+ {
+-  return (poly16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vdupq_n_s8 (int32_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_f64 (const float64_t *__src, float64x2_t __vec, const int __lane)
+ {
+-  return (int8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
+-		      __a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vdupq_n_s16 (int32_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_p8 (const poly8_t *__src, poly8x16_t __vec, const int __lane)
+ {
+-  return (int16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vdupq_n_s32 (int32_t __a)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_p16 (const poly16_t *__src, poly16x8_t __vec, const int __lane)
+ {
+-  return (int32x4_t) {__a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vdupq_n_s64 (int64_t __a)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_p64 (const poly64_t *__src, poly64x2_t __vec, const int __lane)
+ {
+-  return (int64x2_t) {__a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vdupq_n_u8 (uint32_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_s8 (const int8_t *__src, int8x16_t __vec, const int __lane)
+ {
+-  return (uint8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
+-		       __a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vdupq_n_u16 (uint32_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_s16 (const int16_t *__src, int16x8_t __vec, const int __lane)
+ {
+-  return (uint16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vdupq_n_u32 (uint32_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_s32 (const int32_t *__src, int32x4_t __vec, const int __lane)
+ {
+-  return (uint32x4_t) {__a, __a, __a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vdupq_n_u64 (uint64_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_s64 (const int64_t *__src, int64x2_t __vec, const int __lane)
+ {
+-  return (uint64x2_t) {__a, __a};
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-/* vdup_lane  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vdup_lane_f32 (float32x2_t __a, const int __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_u8 (const uint8_t *__src, uint8x16_t __vec, const int __lane)
+ {
+-  return __aarch64_vdup_lane_f32 (__a, __b);
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vdup_lane_f64 (float64x1_t __a, const int __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_u16 (const uint16_t *__src, uint16x8_t __vec, const int __lane)
+ {
+-  return __aarch64_vdup_lane_f64 (__a, __b);
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vdup_lane_p8 (poly8x8_t __a, const int __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_u32 (const uint32_t *__src, uint32x4_t __vec, const int __lane)
+ {
+-  return __aarch64_vdup_lane_p8 (__a, __b);
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vdup_lane_p16 (poly16x4_t __a, const int __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld1q_lane_u64 (const uint64_t *__src, uint64x2_t __vec, const int __lane)
+ {
+-  return __aarch64_vdup_lane_p16 (__a, __b);
++  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vdup_lane_s8 (int8x8_t __a, const int __b)
++/* vldn */
++
++__extension__ extern __inline int64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_s64 (const int64_t * __a)
+ {
+-  return __aarch64_vdup_lane_s8 (__a, __b);
++  int64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
++  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vdup_lane_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline uint64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_u64 (const uint64_t * __a)
+ {
+-  return __aarch64_vdup_lane_s16 (__a, __b);
++  uint64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
++  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vdup_lane_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline float64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_f64 (const float64_t * __a)
+ {
+-  return __aarch64_vdup_lane_s32 (__a, __b);
++  float64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 0)};
++  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 1)};
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vdup_lane_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline int8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_s8 (const int8_t * __a)
+ {
+-  return __aarch64_vdup_lane_s64 (__a, __b);
++  int8x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
++  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vdup_lane_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline poly8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_p8 (const poly8_t * __a)
+ {
+-  return __aarch64_vdup_lane_u8 (__a, __b);
++  poly8x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
++  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vdup_lane_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline poly64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_p64 (const poly64_t * __a)
+ {
+-  return __aarch64_vdup_lane_u16 (__a, __b);
++  poly64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x1_t) __builtin_aarch64_get_dregoidi_pss (__o, 0);
++  ret.val[1] = (poly64x1_t) __builtin_aarch64_get_dregoidi_pss (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vdup_lane_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline int16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_s16 (const int16_t * __a)
+ {
+-  return __aarch64_vdup_lane_u32 (__a, __b);
++  int16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
++  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vdup_lane_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline poly16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_p16 (const poly16_t * __a)
+ {
+-  return __aarch64_vdup_lane_u64 (__a, __b);
++  poly16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
++  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
++  return ret;
+ }
+ 
+-/* vdup_laneq  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vdup_laneq_f32 (float32x4_t __a, const int __b)
++__extension__ extern __inline int32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_s32 (const int32_t * __a)
+ {
+-  return __aarch64_vdup_laneq_f32 (__a, __b);
++  int32x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
++  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vdup_laneq_f64 (float64x2_t __a, const int __b)
++__extension__ extern __inline uint8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_u8 (const uint8_t * __a)
+ {
+-  return __aarch64_vdup_laneq_f64 (__a, __b);
++  uint8x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
++  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vdup_laneq_p8 (poly8x16_t __a, const int __b)
++__extension__ extern __inline uint16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_u16 (const uint16_t * __a)
+ {
+-  return __aarch64_vdup_laneq_p8 (__a, __b);
++  uint16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
++  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vdup_laneq_p16 (poly16x8_t __a, const int __b)
++__extension__ extern __inline uint32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_u32 (const uint32_t * __a)
+ {
+-  return __aarch64_vdup_laneq_p16 (__a, __b);
++  uint32x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
++  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vdup_laneq_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline float16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_f16 (const float16_t * __a)
+ {
+-  return __aarch64_vdup_laneq_s8 (__a, __b);
++  float16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4hf (__a);
++  ret.val[0] = __builtin_aarch64_get_dregoiv4hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_dregoiv4hf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vdup_laneq_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline float32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_f32 (const float32_t * __a)
+ {
+-  return __aarch64_vdup_laneq_s16 (__a, __b);
++  float32x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 0);
++  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vdup_laneq_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline int8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_s8 (const int8_t * __a)
+ {
+-  return __aarch64_vdup_laneq_s32 (__a, __b);
++  int8x16x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
++  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vdup_laneq_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline poly8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_p8 (const poly8_t * __a)
+ {
+-  return __aarch64_vdup_laneq_s64 (__a, __b);
++  poly8x16x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
++  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vdup_laneq_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline int16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_s16 (const int16_t * __a)
+ {
+-  return __aarch64_vdup_laneq_u8 (__a, __b);
++  int16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
++  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vdup_laneq_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline poly16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_p16 (const poly16_t * __a)
+ {
+-  return __aarch64_vdup_laneq_u16 (__a, __b);
++  poly16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
++  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vdup_laneq_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline poly64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_p64 (const poly64_t * __a)
+ {
+-  return __aarch64_vdup_laneq_u32 (__a, __b);
++  poly64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x2_t) __builtin_aarch64_get_qregoiv2di_pss (__o, 0);
++  ret.val[1] = (poly64x2_t) __builtin_aarch64_get_qregoiv2di_pss (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vdup_laneq_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline int32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_s32 (const int32_t * __a)
+ {
+-  return __aarch64_vdup_laneq_u64 (__a, __b);
++  int32x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
++  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
++  return ret;
+ }
+ 
+-/* vdupq_lane  */
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vdupq_lane_f32 (float32x2_t __a, const int __b)
++__extension__ extern __inline int64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_s64 (const int64_t * __a)
+ {
+-  return __aarch64_vdupq_lane_f32 (__a, __b);
++  int64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
++  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vdupq_lane_f64 (float64x1_t __a, const int __b)
++__extension__ extern __inline uint8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_u8 (const uint8_t * __a)
+ {
+-  return __aarch64_vdupq_lane_f64 (__a, __b);
++  uint8x16x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
++  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vdupq_lane_p8 (poly8x8_t __a, const int __b)
++__extension__ extern __inline uint16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_u16 (const uint16_t * __a)
+ {
+-  return __aarch64_vdupq_lane_p8 (__a, __b);
++  uint16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
++  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vdupq_lane_p16 (poly16x4_t __a, const int __b)
++__extension__ extern __inline uint32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_u32 (const uint32_t * __a)
+ {
+-  return __aarch64_vdupq_lane_p16 (__a, __b);
++  uint32x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
++  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vdupq_lane_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline uint64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_u64 (const uint64_t * __a)
+ {
+-  return __aarch64_vdupq_lane_s8 (__a, __b);
++  uint64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
++  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vdupq_lane_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline float16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_f16 (const float16_t * __a)
+ {
+-  return __aarch64_vdupq_lane_s16 (__a, __b);
++  float16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v8hf (__a);
++  ret.val[0] = __builtin_aarch64_get_qregoiv8hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_qregoiv8hf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vdupq_lane_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline float32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_f32 (const float32_t * __a)
+ {
+-  return __aarch64_vdupq_lane_s32 (__a, __b);
++  float32x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v4sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 0);
++  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vdupq_lane_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline float64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_f64 (const float64_t * __a)
+ {
+-  return __aarch64_vdupq_lane_s64 (__a, __b);
++  float64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2v2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 0);
++  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vdupq_lane_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline int64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_s64 (const int64_t * __a)
+ {
+-  return __aarch64_vdupq_lane_u8 (__a, __b);
++  int64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
++  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
++  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vdupq_lane_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline uint64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_u64 (const uint64_t * __a)
+ {
+-  return __aarch64_vdupq_lane_u16 (__a, __b);
++  uint64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
++  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
++  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vdupq_lane_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline float64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_f64 (const float64_t * __a)
+ {
+-  return __aarch64_vdupq_lane_u32 (__a, __b);
++  float64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 0)};
++  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 1)};
++  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 2)};
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vdupq_lane_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline int8x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_s8 (const int8_t * __a)
+ {
+-  return __aarch64_vdupq_lane_u64 (__a, __b);
++  int8x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
++  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
++  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
++  return ret;
+ }
+ 
+-/* vdupq_laneq  */
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vdupq_laneq_f32 (float32x4_t __a, const int __b)
++__extension__ extern __inline poly8x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_p8 (const poly8_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_f32 (__a, __b);
++  poly8x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
++  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
++  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vdupq_laneq_f64 (float64x2_t __a, const int __b)
++__extension__ extern __inline int16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_s16 (const int16_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_f64 (__a, __b);
++  int16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
++  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
++  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vdupq_laneq_p8 (poly8x16_t __a, const int __b)
++__extension__ extern __inline poly16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_p16 (const poly16_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_p8 (__a, __b);
++  poly16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
++  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
++  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vdupq_laneq_p16 (poly16x8_t __a, const int __b)
++__extension__ extern __inline int32x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_s32 (const int32_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_p16 (__a, __b);
++  int32x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
++  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
++  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vdupq_laneq_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline uint8x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_u8 (const uint8_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_s8 (__a, __b);
++  uint8x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
++  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
++  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vdupq_laneq_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline uint16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_u16 (const uint16_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_s16 (__a, __b);
++  uint16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
++  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
++  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vdupq_laneq_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline uint32x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_u32 (const uint32_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_s32 (__a, __b);
++  uint32x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
++  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
++  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vdupq_laneq_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline float16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_f16 (const float16_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_s64 (__a, __b);
++  float16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4hf (__a);
++  ret.val[0] = __builtin_aarch64_get_dregciv4hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_dregciv4hf (__o, 1);
++  ret.val[2] = __builtin_aarch64_get_dregciv4hf (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vdupq_laneq_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline float32x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_f32 (const float32_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_u8 (__a, __b);
++  float32x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 0);
++  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 1);
++  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vdupq_laneq_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline poly64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_p64 (const poly64_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_u16 (__a, __b);
++  poly64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x1_t) __builtin_aarch64_get_dregcidi_pss (__o, 0);
++  ret.val[1] = (poly64x1_t) __builtin_aarch64_get_dregcidi_pss (__o, 1);
++  ret.val[2] = (poly64x1_t) __builtin_aarch64_get_dregcidi_pss (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vdupq_laneq_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline int8x16x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_s8 (const int8_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_u32 (__a, __b);
++  int8x16x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
++  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
++  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vdupq_laneq_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline poly8x16x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_p8 (const poly8_t * __a)
+ {
+-  return __aarch64_vdupq_laneq_u64 (__a, __b);
++  poly8x16x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
++  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
++  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
++  return ret;
+ }
+ 
+-/* vdupb_lane  */
+-__extension__ static __inline poly8_t __attribute__ ((__always_inline__))
+-vdupb_lane_p8 (poly8x8_t __a, const int __b)
++__extension__ extern __inline int16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_s16 (const int16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
++  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
++  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vdupb_lane_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline poly16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_p16 (const poly16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  poly16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
++  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
++  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vdupb_lane_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline int32x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_s32 (const int32_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int32x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
++  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
++  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
++  return ret;
+ }
+ 
+-/* vduph_lane  */
+-__extension__ static __inline poly16_t __attribute__ ((__always_inline__))
+-vduph_lane_p16 (poly16x4_t __a, const int __b)
++__extension__ extern __inline int64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_s64 (const int64_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
++  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
++  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vduph_lane_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline uint8x16x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_u8 (const uint8_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint8x16x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
++  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
++  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vduph_lane_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline uint16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_u16 (const uint16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
++  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
++  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
++  return ret;
+ }
+ 
+-/* vdups_lane  */
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vdups_lane_f32 (float32x2_t __a, const int __b)
++__extension__ extern __inline uint32x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_u32 (const uint32_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint32x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
++  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
++  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vdups_lane_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline uint64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_u64 (const uint64_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
++  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
++  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vdups_lane_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline float16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_f16 (const float16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  float16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v8hf (__a);
++  ret.val[0] = __builtin_aarch64_get_qregciv8hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_qregciv8hf (__o, 1);
++  ret.val[2] = __builtin_aarch64_get_qregciv8hf (__o, 2);
++  return ret;
+ }
+ 
+-/* vdupd_lane  */
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vdupd_lane_f64 (float64x1_t __a, const int __b)
++__extension__ extern __inline float32x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_f32 (const float32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __b);
+-  return __a[0];
++  float32x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v4sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 0);
++  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 1);
++  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vdupd_lane_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline float64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_f64 (const float64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __b);
+-  return __a[0];
++  float64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 0);
++  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 1);
++  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vdupd_lane_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline poly64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_p64 (const poly64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __b);
+-  return __a[0];
++  poly64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x2_t) __builtin_aarch64_get_qregciv2di_pss (__o, 0);
++  ret.val[1] = (poly64x2_t) __builtin_aarch64_get_qregciv2di_pss (__o, 1);
++  ret.val[2] = (poly64x2_t) __builtin_aarch64_get_qregciv2di_pss (__o, 2);
++  return ret;
+ }
+ 
+-/* vdupb_laneq  */
+-__extension__ static __inline poly8_t __attribute__ ((__always_inline__))
+-vdupb_laneq_p8 (poly8x16_t __a, const int __b)
++__extension__ extern __inline int64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_s64 (const int64_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
++  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
++  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
++  ret.val[3] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vdupb_laneq_s8 (int8x16_t __a, const int __attribute__ ((unused)) __b)
++__extension__ extern __inline uint64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_u64 (const uint64_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
++  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
++  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
++  ret.val[3] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vdupb_laneq_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline float64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_f64 (const float64_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  float64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 0)};
++  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 1)};
++  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 2)};
++  ret.val[3] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 3)};
++  return ret;
+ }
+ 
+-/* vduph_laneq  */
+-__extension__ static __inline poly16_t __attribute__ ((__always_inline__))
+-vduph_laneq_p16 (poly16x8_t __a, const int __b)
++__extension__ extern __inline int8x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_s8 (const int8_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int8x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
++  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
++  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
++  ret.val[3] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vduph_laneq_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline poly8x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_p8 (const poly8_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  poly8x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
++  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
++  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
++  ret.val[3] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vduph_laneq_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline int16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_s16 (const int16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
++  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
++  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
++  ret.val[3] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
++  return ret;
+ }
+ 
+-/* vdups_laneq  */
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vdups_laneq_f32 (float32x4_t __a, const int __b)
++__extension__ extern __inline poly16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_p16 (const poly16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  poly16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
++  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
++  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
++  ret.val[3] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vdups_laneq_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline int32x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_s32 (const int32_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  int32x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
++  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
++  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
++  ret.val[3] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vdups_laneq_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline uint8x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_u8 (const uint8_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint8x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
++  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
++  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
++  ret.val[3] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
++  return ret;
+ }
+ 
+-/* vdupd_laneq  */
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vdupd_laneq_f64 (float64x2_t __a, const int __b)
++__extension__ extern __inline uint16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_u16 (const uint16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
++  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
++  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
++  ret.val[3] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vdupd_laneq_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline uint32x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_u32 (const uint32_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  uint32x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
++  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
++  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
++  ret.val[3] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vdupd_laneq_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline float16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_f16 (const float16_t * __a)
+ {
+-  return __aarch64_vget_lane_any (__a, __b);
++  float16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4hf (__a);
++  ret.val[0] = __builtin_aarch64_get_dregxiv4hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_dregxiv4hf (__o, 1);
++  ret.val[2] = __builtin_aarch64_get_dregxiv4hf (__o, 2);
++  ret.val[3] = __builtin_aarch64_get_dregxiv4hf (__o, 3);
++  return ret;
+ }
+ 
+-/* vext  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vext_f32 (float32x2_t __a, float32x2_t __b, __const int __c)
++__extension__ extern __inline float32x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_f32 (const float32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
+-#endif
++  float32x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 0);
++  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 1);
++  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 2);
++  ret.val[3] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vext_f64 (float64x1_t __a, float64x1_t __b, __const int __c)
++__extension__ extern __inline poly64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_p64 (const poly64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-  /* The only possible index to the assembler instruction returns element 0.  */
+-  return __a;
++  poly64x1x4_t  ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 0);
++  ret.val[1] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 1);
++  ret.val[2] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 2);
++  ret.val[3] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 3);
++  return ret;
+ }
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vext_p8 (poly8x8_t __a, poly8x8_t __b, __const int __c)
++
++__extension__ extern __inline int8x16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_s8 (const int8_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint8x8_t)
+-      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
+-#endif
++  int8x16x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
++  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
++  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
++  ret.val[3] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vext_p16 (poly16x4_t __a, poly16x4_t __b, __const int __c)
++__extension__ extern __inline poly8x16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_p8 (const poly8_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a,
+-      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
+-#endif
++  poly8x16x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
++  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
++  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
++  ret.val[3] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vext_s8 (int8x8_t __a, int8x8_t __b, __const int __c)
++__extension__ extern __inline int16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_s16 (const int16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint8x8_t)
+-      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
+-#endif
++  int16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
++  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
++  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
++  ret.val[3] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vext_s16 (int16x4_t __a, int16x4_t __b, __const int __c)
++__extension__ extern __inline poly16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_p16 (const poly16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a,
+-      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
+-#endif
++  poly16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
++  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
++  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
++  ret.val[3] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vext_s32 (int32x2_t __a, int32x2_t __b, __const int __c)
++__extension__ extern __inline int32x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_s32 (const int32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
+-#endif
++  int32x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
++  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
++  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
++  ret.val[3] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vext_s64 (int64x1_t __a, int64x1_t __b, __const int __c)
++__extension__ extern __inline int64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_s64 (const int64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-  /* The only possible index to the assembler instruction returns element 0.  */
+-  return __a;
++  int64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
++  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
++  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
++  ret.val[3] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vext_u8 (uint8x8_t __a, uint8x8_t __b, __const int __c)
++__extension__ extern __inline uint8x16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_u8 (const uint8_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint8x8_t)
+-      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
+-#endif
++  uint8x16x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
++  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
++  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
++  ret.val[3] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vext_u16 (uint16x4_t __a, uint16x4_t __b, __const int __c)
++__extension__ extern __inline uint16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_u16 (const uint16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a,
+-      (uint16x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {__c, __c+1, __c+2, __c+3});
+-#endif
++  uint16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
++  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
++  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
++  ret.val[3] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vext_u32 (uint32x2_t __a, uint32x2_t __b, __const int __c)
++__extension__ extern __inline uint32x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_u32 (const uint32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint32x2_t) {2-__c, 3-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {__c, __c+1});
+-#endif
++  uint32x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
++  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
++  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
++  ret.val[3] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vext_u64 (uint64x1_t __a, uint64x1_t __b, __const int __c)
++__extension__ extern __inline uint64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_u64 (const uint64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-  /* The only possible index to the assembler instruction returns element 0.  */
+-  return __a;
++  uint64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
++  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
++  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
++  ret.val[3] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vextq_f32 (float32x4_t __a, float32x4_t __b, __const int __c)
++__extension__ extern __inline float16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_f16 (const float16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a,
+-      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
+-#endif
++  float16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v8hf (__a);
++  ret.val[0] = __builtin_aarch64_get_qregxiv8hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_qregxiv8hf (__o, 1);
++  ret.val[2] = __builtin_aarch64_get_qregxiv8hf (__o, 2);
++  ret.val[3] = __builtin_aarch64_get_qregxiv8hf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vextq_f64 (float64x2_t __a, float64x2_t __b, __const int __c)
++__extension__ extern __inline float32x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_f32 (const float32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
+-#endif
++  float32x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v4sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 0);
++  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 1);
++  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 2);
++  ret.val[3] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vextq_p8 (poly8x16_t __a, poly8x16_t __b, __const int __c)
++__extension__ extern __inline float64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_f64 (const float64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint8x16_t)
+-      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
+-       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
+-       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
+-#endif
++  float64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 0);
++  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 1);
++  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 2);
++  ret.val[3] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vextq_p16 (poly16x8_t __a, poly16x8_t __b, __const int __c)
++__extension__ extern __inline poly64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_p64 (const poly64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint16x8_t)
+-      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
+-#endif
++  poly64x2x4_t  ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4v2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 0);
++  ret.val[1] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 1);
++  ret.val[2] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 2);
++  ret.val[3] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vextq_s8 (int8x16_t __a, int8x16_t __b, __const int __c)
++/* vldn_dup */
++
++__extension__ extern __inline int8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_s8 (const int8_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint8x16_t)
+-      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
+-       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
+-       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
+-#endif
++  int8x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
++  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vextq_s16 (int16x8_t __a, int16x8_t __b, __const int __c)
++__extension__ extern __inline int16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_s16 (const int16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint16x8_t)
+-      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
+-#endif
++  int16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
++  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vextq_s32 (int32x4_t __a, int32x4_t __b, __const int __c)
++__extension__ extern __inline int32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_s32 (const int32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a,
+-      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
+-#endif
++  int32x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
++  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vextq_s64 (int64x2_t __a, int64x2_t __b, __const int __c)
++__extension__ extern __inline float16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_f16 (const float16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
+-#endif
++  float16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4hf ((const __builtin_aarch64_simd_hf *) __a);
++  ret.val[0] = __builtin_aarch64_get_dregoiv4hf (__o, 0);
++  ret.val[1] = (float16x4_t) __builtin_aarch64_get_dregoiv4hf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vextq_u8 (uint8x16_t __a, uint8x16_t __b, __const int __c)
++__extension__ extern __inline float32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_f32 (const float32_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint8x16_t)
+-      {16-__c, 17-__c, 18-__c, 19-__c, 20-__c, 21-__c, 22-__c, 23-__c,
+-       24-__c, 25-__c, 26-__c, 27-__c, 28-__c, 29-__c, 30-__c, 31-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7,
+-       __c+8, __c+9, __c+10, __c+11, __c+12, __c+13, __c+14, __c+15});
+-#endif
++  float32x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 0);
++  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vextq_u16 (uint16x8_t __a, uint16x8_t __b, __const int __c)
++__extension__ extern __inline float64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_f64 (const float64_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint16x8_t)
+-      {8-__c, 9-__c, 10-__c, 11-__c, 12-__c, 13-__c, 14-__c, 15-__c});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint16x8_t) {__c, __c+1, __c+2, __c+3, __c+4, __c+5, __c+6, __c+7});
+-#endif
++  float64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rdf ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 0)};
++  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 1)};
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vextq_u32 (uint32x4_t __a, uint32x4_t __b, __const int __c)
++__extension__ extern __inline uint8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_u8 (const uint8_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a,
+-      (uint32x4_t) {4-__c, 5-__c, 6-__c, 7-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {__c, __c+1, __c+2, __c+3});
+-#endif
++  uint8x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
++  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vextq_u64 (uint64x2_t __a, uint64x2_t __b, __const int __c)
++__extension__ extern __inline uint16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_u16 (const uint16_t * __a)
+ {
+-  __AARCH64_LANE_CHECK (__a, __c);
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__b, __a, (uint64x2_t) {2-__c, 3-__c});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {__c, __c+1});
+-#endif
++  uint16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
++  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
++  return ret;
+ }
+ 
+-/* vfma  */
+-
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vfma_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
++__extension__ extern __inline uint32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_u32 (const uint32_t * __a)
+ {
+-  return (float64x1_t) {__builtin_fma (__b[0], __c[0], __a[0])};
++  uint32x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
++  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfma_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
++__extension__ extern __inline poly8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_p8 (const poly8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (__b, __c, __a);
++  poly8x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
++  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
++__extension__ extern __inline poly16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_p16 (const poly16_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (__b, __c, __a);
++  poly16x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
++  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmaq_f64 (float64x2_t __a, float64x2_t __b, float64x2_t __c)
++__extension__ extern __inline poly64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_p64 (const poly64_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (__b, __c, __a);
++  poly64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x1_t) __builtin_aarch64_get_dregoidi_pss (__o, 0);
++  ret.val[1] = (poly64x1_t) __builtin_aarch64_get_dregoidi_pss (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfma_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
++
++__extension__ extern __inline int64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_s64 (const int64_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (__b, vdup_n_f32 (__c), __a);
++  int64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rdi ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
++  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
++__extension__ extern __inline uint64x1x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2_dup_u64 (const uint64_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (__b, vdupq_n_f32 (__c), __a);
++  uint64x1x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rdi ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
++  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmaq_n_f64 (float64x2_t __a, float64x2_t __b, float64_t __c)
++__extension__ extern __inline int8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_s8 (const int8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (__b, vdupq_n_f64 (__c), __a);
++  int8x16x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
++  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
++  return ret;
+ }
+ 
+-/* vfma_lane  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfma_lane_f32 (float32x2_t __a, float32x2_t __b,
+-	       float32x2_t __c, const int __lane)
++__extension__ extern __inline poly8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_p8 (const poly8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (__b,
+-				    __aarch64_vdup_lane_f32 (__c, __lane),
+-				    __a);
++  poly8x16x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
++  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vfma_lane_f64 (float64x1_t __a, float64x1_t __b,
+-	       float64x1_t __c, const int __lane)
++__extension__ extern __inline int16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_s16 (const int16_t * __a)
+ {
+-  return (float64x1_t) {__builtin_fma (__b[0], __c[0], __a[0])};
++  int16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
++  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vfmad_lane_f64 (float64_t __a, float64_t __b,
+-	        float64x1_t __c, const int __lane)
++__extension__ extern __inline poly16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_p16 (const poly16_t * __a)
+ {
+-  return __builtin_fma (__b, __c[0], __a);
++  poly16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
++  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vfmas_lane_f32 (float32_t __a, float32_t __b,
+-	        float32x2_t __c, const int __lane)
++__extension__ extern __inline int32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_s32 (const int32_t * __a)
+ {
+-  return __builtin_fmaf (__b, __aarch64_vget_lane_any (__c, __lane), __a);
++  int32x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
++  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
++  return ret;
+ }
+ 
+-/* vfma_laneq  */
++__extension__ extern __inline int64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_s64 (const int64_t * __a)
++{
++  int64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
++  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
++  return ret;
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfma_laneq_f32 (float32x2_t __a, float32x2_t __b,
+-	        float32x4_t __c, const int __lane)
++__extension__ extern __inline uint8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_u8 (const uint8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (__b,
+-				    __aarch64_vdup_laneq_f32 (__c, __lane),
+-				    __a);
++  uint8x16x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
++  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vfma_laneq_f64 (float64x1_t __a, float64x1_t __b,
+-	        float64x2_t __c, const int __lane)
++__extension__ extern __inline uint16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_u16 (const uint16_t * __a)
+ {
+-  float64_t __c0 = __aarch64_vget_lane_any (__c, __lane);
+-  return (float64x1_t) {__builtin_fma (__b[0], __c0, __a[0])};
++  uint16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
++  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vfmad_laneq_f64 (float64_t __a, float64_t __b,
+-	         float64x2_t __c, const int __lane)
++__extension__ extern __inline uint32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_u32 (const uint32_t * __a)
+ {
+-  return __builtin_fma (__b, __aarch64_vget_lane_any (__c, __lane), __a);
++  uint32x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
++  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vfmas_laneq_f32 (float32_t __a, float32_t __b,
+-		 float32x4_t __c, const int __lane)
++__extension__ extern __inline uint64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_u64 (const uint64_t * __a)
+ {
+-  return __builtin_fmaf (__b, __aarch64_vget_lane_any (__c, __lane), __a);
++  uint64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
++  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
++  return ret;
+ }
+ 
+-/* vfmaq_lane  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmaq_lane_f32 (float32x4_t __a, float32x4_t __b,
+-	        float32x2_t __c, const int __lane)
++__extension__ extern __inline float16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_f16 (const float16_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (__b,
+-				    __aarch64_vdupq_lane_f32 (__c, __lane),
+-				    __a);
++  float16x8x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv8hf ((const __builtin_aarch64_simd_hf *) __a);
++  ret.val[0] = (float16x8_t) __builtin_aarch64_get_qregoiv8hf (__o, 0);
++  ret.val[1] = __builtin_aarch64_get_qregoiv8hf (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmaq_lane_f64 (float64x2_t __a, float64x2_t __b,
+-	        float64x1_t __c, const int __lane)
++__extension__ extern __inline float32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_f32 (const float32_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (__b, vdupq_n_f64 (__c[0]), __a);
++  float32x4x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv4sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 0);
++  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 1);
++  return ret;
+ }
+ 
+-/* vfmaq_laneq  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmaq_laneq_f32 (float32x4_t __a, float32x4_t __b,
+-	         float32x4_t __c, const int __lane)
++__extension__ extern __inline float64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_f64 (const float64_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (__b,
+-				    __aarch64_vdupq_laneq_f32 (__c, __lane),
+-				    __a);
++  float64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 0);
++  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 1);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmaq_laneq_f64 (float64x2_t __a, float64x2_t __b,
+-	         float64x2_t __c, const int __lane)
++__extension__ extern __inline poly64x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld2q_dup_p64 (const poly64_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (__b,
+-				    __aarch64_vdupq_laneq_f64 (__c, __lane),
+-				    __a);
++  poly64x2x2_t ret;
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x2_t) __builtin_aarch64_get_qregoiv2di_pss (__o, 0);
++  ret.val[1] = (poly64x2_t) __builtin_aarch64_get_qregoiv2di_pss (__o, 1);
++  return ret;
+ }
+ 
+-/* vfms  */
+-
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vfms_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
++__extension__ extern __inline int64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_s64 (const int64_t * __a)
+ {
+-  return (float64x1_t) {__builtin_fma (-__b[0], __c[0], __a[0])};
++  int64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rdi ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
++  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
++  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfms_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
++__extension__ extern __inline uint64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_u64 (const uint64_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (-__b, __c, __a);
++  uint64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rdi ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
++  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
++  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
++__extension__ extern __inline float64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_f64 (const float64_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (-__b, __c, __a);
++  float64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rdf ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 0)};
++  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 1)};
++  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 2)};
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmsq_f64 (float64x2_t __a, float64x2_t __b, float64x2_t __c)
++__extension__ extern __inline int8x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_s8 (const int8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (-__b, __c, __a);
++  int8x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
++  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
++  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
++  return ret;
+ }
+ 
+-
+-/* vfms_lane  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfms_lane_f32 (float32x2_t __a, float32x2_t __b,
+-	       float32x2_t __c, const int __lane)
++__extension__ extern __inline poly8x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_p8 (const poly8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (-__b,
+-				    __aarch64_vdup_lane_f32 (__c, __lane),
+-				    __a);
++  poly8x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
++  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
++  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vfms_lane_f64 (float64x1_t __a, float64x1_t __b,
+-	       float64x1_t __c, const int __lane)
++__extension__ extern __inline int16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_s16 (const int16_t * __a)
+ {
+-  return (float64x1_t) {__builtin_fma (-__b[0], __c[0], __a[0])};
++  int16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
++  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
++  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vfmsd_lane_f64 (float64_t __a, float64_t __b,
+-	        float64x1_t __c, const int __lane)
++__extension__ extern __inline poly16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_p16 (const poly16_t * __a)
+ {
+-  return __builtin_fma (-__b, __c[0], __a);
++  poly16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
++  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
++  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vfmss_lane_f32 (float32_t __a, float32_t __b,
+-	        float32x2_t __c, const int __lane)
++__extension__ extern __inline int32x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_s32 (const int32_t * __a)
+ {
+-  return __builtin_fmaf (-__b, __aarch64_vget_lane_any (__c, __lane), __a);
++  int32x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
++  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
++  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
++  return ret;
+ }
+ 
+-/* vfms_laneq  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vfms_laneq_f32 (float32x2_t __a, float32x2_t __b,
+-	        float32x4_t __c, const int __lane)
++__extension__ extern __inline uint8x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_u8 (const uint8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2sf (-__b,
+-				    __aarch64_vdup_laneq_f32 (__c, __lane),
+-				    __a);
++  uint8x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
++  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
++  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vfms_laneq_f64 (float64x1_t __a, float64x1_t __b,
+-	        float64x2_t __c, const int __lane)
++__extension__ extern __inline uint16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_u16 (const uint16_t * __a)
+ {
+-  float64_t __c0 = __aarch64_vget_lane_any (__c, __lane);
+-  return (float64x1_t) {__builtin_fma (-__b[0], __c0, __a[0])};
++  uint16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
++  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
++  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vfmsd_laneq_f64 (float64_t __a, float64_t __b,
+-	         float64x2_t __c, const int __lane)
++__extension__ extern __inline uint32x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_u32 (const uint32_t * __a)
+ {
+-  return __builtin_fma (-__b, __aarch64_vget_lane_any (__c, __lane), __a);
++  uint32x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
++  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
++  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vfmss_laneq_f32 (float32_t __a, float32_t __b,
+-		 float32x4_t __c, const int __lane)
++__extension__ extern __inline float16x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_f16 (const float16_t * __a)
+ {
+-  return __builtin_fmaf (-__b, __aarch64_vget_lane_any (__c, __lane), __a);
++  float16x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4hf ((const __builtin_aarch64_simd_hf *) __a);
++  ret.val[0] = (float16x4_t) __builtin_aarch64_get_dregciv4hf (__o, 0);
++  ret.val[1] = (float16x4_t) __builtin_aarch64_get_dregciv4hf (__o, 1);
++  ret.val[2] = (float16x4_t) __builtin_aarch64_get_dregciv4hf (__o, 2);
++  return ret;
+ }
+ 
+-/* vfmsq_lane  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmsq_lane_f32 (float32x4_t __a, float32x4_t __b,
+-	        float32x2_t __c, const int __lane)
++__extension__ extern __inline float32x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_f32 (const float32_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (-__b,
+-				    __aarch64_vdupq_lane_f32 (__c, __lane),
+-				    __a);
++  float32x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 0);
++  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 1);
++  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmsq_lane_f64 (float64x2_t __a, float64x2_t __b,
+-	        float64x1_t __c, const int __lane)
++__extension__ extern __inline poly64x1x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3_dup_p64 (const poly64_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (-__b, vdupq_n_f64 (__c[0]), __a);
++  poly64x1x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x1_t) __builtin_aarch64_get_dregcidi_pss (__o, 0);
++  ret.val[1] = (poly64x1_t) __builtin_aarch64_get_dregcidi_pss (__o, 1);
++  ret.val[2] = (poly64x1_t) __builtin_aarch64_get_dregcidi_pss (__o, 2);
++  return ret;
+ }
+ 
+-/* vfmsq_laneq  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vfmsq_laneq_f32 (float32x4_t __a, float32x4_t __b,
+-	         float32x4_t __c, const int __lane)
++__extension__ extern __inline int8x16x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_s8 (const int8_t * __a)
+ {
+-  return __builtin_aarch64_fmav4sf (-__b,
+-				    __aarch64_vdupq_laneq_f32 (__c, __lane),
+-				    __a);
++  int8x16x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
++  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
++  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vfmsq_laneq_f64 (float64x2_t __a, float64x2_t __b,
+-	         float64x2_t __c, const int __lane)
++__extension__ extern __inline poly8x16x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_p8 (const poly8_t * __a)
+ {
+-  return __builtin_aarch64_fmav2df (-__b,
+-				    __aarch64_vdupq_laneq_f64 (__c, __lane),
+-				    __a);
++  poly8x16x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
++  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
++  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
++  return ret;
+ }
+ 
+-/* vld1 */
++__extension__ extern __inline int16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_s16 (const int16_t * __a)
++{
++  int16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
++  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
++  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
++  return ret;
++}
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
+-vld1_f16 (const float16_t *__a)
++__extension__ extern __inline poly16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_p16 (const poly16_t * __a)
+ {
+-  return __builtin_aarch64_ld1v4hf (__a);
++  poly16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
++  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
++  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vld1_f32 (const float32_t *a)
++__extension__ extern __inline int32x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_s32 (const int32_t * __a)
+ {
+-  return __builtin_aarch64_ld1v2sf ((const __builtin_aarch64_simd_sf *) a);
++  int32x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
++  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
++  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vld1_f64 (const float64_t *a)
++__extension__ extern __inline int64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_s64 (const int64_t * __a)
+ {
+-  return (float64x1_t) {*a};
++  int64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
++  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
++  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vld1_p8 (const poly8_t *a)
++__extension__ extern __inline uint8x16x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_u8 (const uint8_t * __a)
+ {
+-  return (poly8x8_t)
+-    __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a);
++  uint8x16x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
++  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
++  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vld1_p16 (const poly16_t *a)
++__extension__ extern __inline uint16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_u16 (const uint16_t * __a)
+ {
+-  return (poly16x4_t)
+-    __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a);
++  uint16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
++  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
++  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vld1_s8 (const int8_t *a)
++__extension__ extern __inline uint32x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_u32 (const uint32_t * __a)
+ {
+-  return __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a);
++  uint32x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
++  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
++  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vld1_s16 (const int16_t *a)
++__extension__ extern __inline uint64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_u64 (const uint64_t * __a)
+ {
+-  return __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a);
++  uint64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
++  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
++  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vld1_s32 (const int32_t *a)
++__extension__ extern __inline float16x8x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_f16 (const float16_t * __a)
+ {
+-  return __builtin_aarch64_ld1v2si ((const __builtin_aarch64_simd_si *) a);
++  float16x8x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv8hf ((const __builtin_aarch64_simd_hf *) __a);
++  ret.val[0] = (float16x8_t) __builtin_aarch64_get_qregciv8hf (__o, 0);
++  ret.val[1] = (float16x8_t) __builtin_aarch64_get_qregciv8hf (__o, 1);
++  ret.val[2] = (float16x8_t) __builtin_aarch64_get_qregciv8hf (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vld1_s64 (const int64_t *a)
++__extension__ extern __inline float32x4x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_f32 (const float32_t * __a)
+ {
+-  return (int64x1_t) {*a};
++  float32x4x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv4sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 0);
++  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 1);
++  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vld1_u8 (const uint8_t *a)
++__extension__ extern __inline float64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_f64 (const float64_t * __a)
+ {
+-  return (uint8x8_t)
+-    __builtin_aarch64_ld1v8qi ((const __builtin_aarch64_simd_qi *) a);
++  float64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 0);
++  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 1);
++  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vld1_u16 (const uint16_t *a)
++__extension__ extern __inline poly64x2x3_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld3q_dup_p64 (const poly64_t * __a)
+ {
+-  return (uint16x4_t)
+-    __builtin_aarch64_ld1v4hi ((const __builtin_aarch64_simd_hi *) a);
++  poly64x2x3_t ret;
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x2_t) __builtin_aarch64_get_qregciv2di_pss (__o, 0);
++  ret.val[1] = (poly64x2_t) __builtin_aarch64_get_qregciv2di_pss (__o, 1);
++  ret.val[2] = (poly64x2_t) __builtin_aarch64_get_qregciv2di_pss (__o, 2);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vld1_u32 (const uint32_t *a)
++__extension__ extern __inline int64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_s64 (const int64_t * __a)
+ {
+-  return (uint32x2_t)
+-    __builtin_aarch64_ld1v2si ((const __builtin_aarch64_simd_si *) a);
++  int64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rdi ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
++  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
++  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
++  ret.val[3] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vld1_u64 (const uint64_t *a)
++__extension__ extern __inline uint64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_u64 (const uint64_t * __a)
+ {
+-  return (uint64x1_t) {*a};
++  uint64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rdi ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
++  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
++  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
++  ret.val[3] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
++  return ret;
+ }
+ 
+-/* vld1q */
++__extension__ extern __inline float64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_f64 (const float64_t * __a)
++{
++  float64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rdf ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 0)};
++  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 1)};
++  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 2)};
++  ret.val[3] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 3)};
++  return ret;
++}
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
+-vld1q_f16 (const float16_t *__a)
++__extension__ extern __inline int8x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_s8 (const int8_t * __a)
+ {
+-  return __builtin_aarch64_ld1v8hf (__a);
++  int8x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
++  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
++  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
++  ret.val[3] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vld1q_f32 (const float32_t *a)
++__extension__ extern __inline poly8x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_p8 (const poly8_t * __a)
+ {
+-  return __builtin_aarch64_ld1v4sf ((const __builtin_aarch64_simd_sf *) a);
++  poly8x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
++  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
++  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
++  ret.val[3] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vld1q_f64 (const float64_t *a)
++__extension__ extern __inline int16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_s16 (const int16_t * __a)
+ {
+-  return __builtin_aarch64_ld1v2df ((const __builtin_aarch64_simd_df *) a);
++  int16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
++  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
++  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
++  ret.val[3] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vld1q_p8 (const poly8_t *a)
++__extension__ extern __inline poly16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_p16 (const poly16_t * __a)
+ {
+-  return (poly8x16_t)
+-    __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a);
++  poly16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
++  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
++  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
++  ret.val[3] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vld1q_p16 (const poly16_t *a)
++__extension__ extern __inline int32x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_s32 (const int32_t * __a)
+ {
+-  return (poly16x8_t)
+-    __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a);
++  int32x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
++  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
++  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
++  ret.val[3] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vld1q_s8 (const int8_t *a)
++__extension__ extern __inline uint8x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_u8 (const uint8_t * __a)
+ {
+-  return __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a);
++  uint8x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
++  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
++  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
++  ret.val[3] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vld1q_s16 (const int16_t *a)
++__extension__ extern __inline uint16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_u16 (const uint16_t * __a)
+ {
+-  return __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a);
++  uint16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
++  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
++  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
++  ret.val[3] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vld1q_s32 (const int32_t *a)
++__extension__ extern __inline uint32x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_u32 (const uint32_t * __a)
+ {
+-  return __builtin_aarch64_ld1v4si ((const __builtin_aarch64_simd_si *) a);
++  uint32x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
++  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
++  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
++  ret.val[3] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vld1q_s64 (const int64_t *a)
++__extension__ extern __inline float16x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_f16 (const float16_t * __a)
+ {
+-  return __builtin_aarch64_ld1v2di ((const __builtin_aarch64_simd_di *) a);
++  float16x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4hf ((const __builtin_aarch64_simd_hf *) __a);
++  ret.val[0] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 0);
++  ret.val[1] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 1);
++  ret.val[2] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 2);
++  ret.val[3] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vld1q_u8 (const uint8_t *a)
++__extension__ extern __inline float32x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_f32 (const float32_t * __a)
+ {
+-  return (uint8x16_t)
+-    __builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a);
++  float32x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 0);
++  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 1);
++  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 2);
++  ret.val[3] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vld1q_u16 (const uint16_t *a)
++__extension__ extern __inline poly64x1x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4_dup_p64 (const poly64_t * __a)
+ {
+-  return (uint16x8_t)
+-    __builtin_aarch64_ld1v8hi ((const __builtin_aarch64_simd_hi *) a);
++  poly64x1x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 0);
++  ret.val[1] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 1);
++  ret.val[2] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 2);
++  ret.val[3] = (poly64x1_t) __builtin_aarch64_get_dregxidi_pss (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vld1q_u32 (const uint32_t *a)
++__extension__ extern __inline int8x16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_s8 (const int8_t * __a)
+ {
+-  return (uint32x4_t)
+-    __builtin_aarch64_ld1v4si ((const __builtin_aarch64_simd_si *) a);
++  int8x16x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
++  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
++  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
++  ret.val[3] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vld1q_u64 (const uint64_t *a)
++__extension__ extern __inline poly8x16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_p8 (const poly8_t * __a)
+ {
+-  return (uint64x2_t)
+-    __builtin_aarch64_ld1v2di ((const __builtin_aarch64_simd_di *) a);
++  poly8x16x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
++  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
++  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
++  ret.val[3] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
++  return ret;
+ }
+ 
+-/* vld1_dup  */
+-
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
+-vld1_dup_f16 (const float16_t* __a)
++__extension__ extern __inline int16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_s16 (const int16_t * __a)
+ {
+-  float16_t __f = *__a;
+-  return (float16x4_t) { __f, __f, __f, __f };
++  int16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
++  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
++  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
++  ret.val[3] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vld1_dup_f32 (const float32_t* __a)
++__extension__ extern __inline poly16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_p16 (const poly16_t * __a)
+ {
+-  return vdup_n_f32 (*__a);
++  poly16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
++  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
++  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
++  ret.val[3] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vld1_dup_f64 (const float64_t* __a)
++__extension__ extern __inline int32x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_s32 (const int32_t * __a)
+ {
+-  return vdup_n_f64 (*__a);
++  int32x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
++  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
++  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
++  ret.val[3] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vld1_dup_p8 (const poly8_t* __a)
++__extension__ extern __inline int64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_s64 (const int64_t * __a)
+ {
+-  return vdup_n_p8 (*__a);
++  int64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
++  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
++  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
++  ret.val[3] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vld1_dup_p16 (const poly16_t* __a)
++__extension__ extern __inline uint8x16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_u8 (const uint8_t * __a)
+ {
+-  return vdup_n_p16 (*__a);
++  uint8x16x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
++  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
++  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
++  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
++  ret.val[3] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vld1_dup_s8 (const int8_t* __a)
++__extension__ extern __inline uint16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_u16 (const uint16_t * __a)
+ {
+-  return vdup_n_s8 (*__a);
++  uint16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
++  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
++  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
++  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
++  ret.val[3] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vld1_dup_s16 (const int16_t* __a)
++__extension__ extern __inline uint32x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_u32 (const uint32_t * __a)
+ {
+-  return vdup_n_s16 (*__a);
++  uint32x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4si ((const __builtin_aarch64_simd_si *) __a);
++  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
++  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
++  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
++  ret.val[3] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vld1_dup_s32 (const int32_t* __a)
++__extension__ extern __inline uint64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_u64 (const uint64_t * __a)
+ {
+-  return vdup_n_s32 (*__a);
++  uint64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
++  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
++  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
++  ret.val[3] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vld1_dup_s64 (const int64_t* __a)
++__extension__ extern __inline float16x8x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_f16 (const float16_t * __a)
+ {
+-  return vdup_n_s64 (*__a);
++  float16x8x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv8hf ((const __builtin_aarch64_simd_hf *) __a);
++  ret.val[0] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 0);
++  ret.val[1] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 1);
++  ret.val[2] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 2);
++  ret.val[3] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vld1_dup_u8 (const uint8_t* __a)
++__extension__ extern __inline float32x4x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_f32 (const float32_t * __a)
+ {
+-  return vdup_n_u8 (*__a);
++  float32x4x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv4sf ((const __builtin_aarch64_simd_sf *) __a);
++  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 0);
++  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 1);
++  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 2);
++  ret.val[3] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vld1_dup_u16 (const uint16_t* __a)
++__extension__ extern __inline float64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_f64 (const float64_t * __a)
+ {
+-  return vdup_n_u16 (*__a);
++  float64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2df ((const __builtin_aarch64_simd_df *) __a);
++  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 0);
++  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 1);
++  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 2);
++  ret.val[3] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vld1_dup_u32 (const uint32_t* __a)
++__extension__ extern __inline poly64x2x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vld4q_dup_p64 (const poly64_t * __a)
+ {
+-  return vdup_n_u32 (*__a);
++  poly64x2x4_t ret;
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
++  ret.val[0] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 0);
++  ret.val[1] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 1);
++  ret.val[2] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 2);
++  ret.val[3] = (poly64x2_t) __builtin_aarch64_get_qregxiv2di_pss (__o, 3);
++  return ret;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vld1_dup_u64 (const uint64_t* __a)
+-{
+-  return vdup_n_u64 (*__a);
++/* vld2_lane */
++
++#define __LD2_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
++			 qmode, ptrmode, funcsuffix, signedtype)	   \
++__extension__ extern __inline intype \
++__attribute__ ((__always_inline__, __gnu_inline__,__artificial__)) \
++vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
++{									   \
++  __builtin_aarch64_simd_oi __o;					   \
++  largetype __temp;							   \
++  __temp.val[0] =							   \
++    vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0));	   \
++  __temp.val[1] =							   \
++    vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
++  __o = __builtin_aarch64_set_qregoi##qmode (__o,			   \
++					    (signedtype) __temp.val[0],	   \
++					    0);				   \
++  __o = __builtin_aarch64_set_qregoi##qmode (__o,			   \
++					    (signedtype) __temp.val[1],	   \
++					    1);				   \
++  __o =	__builtin_aarch64_ld2_lane##mode (				   \
++	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
++  __b.val[0] = (vectype) __builtin_aarch64_get_dregoidi (__o, 0);	   \
++  __b.val[1] = (vectype) __builtin_aarch64_get_dregoidi (__o, 1);	   \
++  return __b;								   \
+ }
+ 
+-/* vld1q_dup  */
++__LD2_LANE_FUNC (float16x4x2_t, float16x4_t, float16x8x2_t, float16_t, v4hf,
++		 v8hf, hf, f16, float16x8_t)
++__LD2_LANE_FUNC (float32x2x2_t, float32x2_t, float32x4x2_t, float32_t, v2sf, v4sf,
++		 sf, f32, float32x4_t)
++__LD2_LANE_FUNC (float64x1x2_t, float64x1_t, float64x2x2_t, float64_t, df, v2df,
++		 df, f64, float64x2_t)
++__LD2_LANE_FUNC (poly8x8x2_t, poly8x8_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8,
++		 int8x16_t)
++__LD2_LANE_FUNC (poly16x4x2_t, poly16x4_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi,
++		 p16, int16x8_t)
++__LD2_LANE_FUNC (poly64x1x2_t, poly64x1_t, poly64x2x2_t, poly64_t, di,
++		 v2di_ssps, di, p64, poly64x2_t)
++__LD2_LANE_FUNC (int8x8x2_t, int8x8_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8,
++		 int8x16_t)
++__LD2_LANE_FUNC (int16x4x2_t, int16x4_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16,
++		 int16x8_t)
++__LD2_LANE_FUNC (int32x2x2_t, int32x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32,
++		 int32x4_t)
++__LD2_LANE_FUNC (int64x1x2_t, int64x1_t, int64x2x2_t, int64_t, di, v2di, di, s64,
++		 int64x2_t)
++__LD2_LANE_FUNC (uint8x8x2_t, uint8x8_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8,
++		 int8x16_t)
++__LD2_LANE_FUNC (uint16x4x2_t, uint16x4_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi,
++		 u16, int16x8_t)
++__LD2_LANE_FUNC (uint32x2x2_t, uint32x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si,
++		 u32, int32x4_t)
++__LD2_LANE_FUNC (uint64x1x2_t, uint64x1_t, uint64x2x2_t, uint64_t, di, v2di, di,
++		 u64, int64x2_t)
+ 
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
+-vld1q_dup_f16 (const float16_t* __a)
+-{
+-  float16_t __f = *__a;
+-  return (float16x8_t) { __f, __f, __f, __f, __f, __f, __f, __f };
++#undef __LD2_LANE_FUNC
++
++/* vld2q_lane */
++
++#define __LD2_LANE_FUNC(intype, vtype, ptrtype, mode, ptrmode, funcsuffix) \
++__extension__ extern __inline intype \
++__attribute__ ((__always_inline__, __gnu_inline__,__artificial__)) \
++vld2q_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \
++{									   \
++  __builtin_aarch64_simd_oi __o;					   \
++  intype ret;								   \
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) __b.val[0], 0); \
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) __b.val[1], 1); \
++  __o = __builtin_aarch64_ld2_lane##mode (				   \
++	(__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);		   \
++  ret.val[0] = (vtype) __builtin_aarch64_get_qregoiv4si (__o, 0);	   \
++  ret.val[1] = (vtype) __builtin_aarch64_get_qregoiv4si (__o, 1);	   \
++  return ret;								   \
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vld1q_dup_f32 (const float32_t* __a)
+-{
+-  return vdupq_n_f32 (*__a);
++__LD2_LANE_FUNC (float16x8x2_t, float16x8_t, float16_t, v8hf, hf, f16)
++__LD2_LANE_FUNC (float32x4x2_t, float32x4_t, float32_t, v4sf, sf, f32)
++__LD2_LANE_FUNC (float64x2x2_t, float64x2_t, float64_t, v2df, df, f64)
++__LD2_LANE_FUNC (poly8x16x2_t, poly8x16_t, poly8_t, v16qi, qi, p8)
++__LD2_LANE_FUNC (poly16x8x2_t, poly16x8_t, poly16_t, v8hi, hi, p16)
++__LD2_LANE_FUNC (poly64x2x2_t, poly64x2_t, poly64_t, v2di, di, p64)
++__LD2_LANE_FUNC (int8x16x2_t, int8x16_t, int8_t, v16qi, qi, s8)
++__LD2_LANE_FUNC (int16x8x2_t, int16x8_t, int16_t, v8hi, hi, s16)
++__LD2_LANE_FUNC (int32x4x2_t, int32x4_t, int32_t, v4si, si, s32)
++__LD2_LANE_FUNC (int64x2x2_t, int64x2_t, int64_t, v2di, di, s64)
++__LD2_LANE_FUNC (uint8x16x2_t, uint8x16_t, uint8_t, v16qi, qi, u8)
++__LD2_LANE_FUNC (uint16x8x2_t, uint16x8_t, uint16_t, v8hi, hi, u16)
++__LD2_LANE_FUNC (uint32x4x2_t, uint32x4_t, uint32_t, v4si, si, u32)
++__LD2_LANE_FUNC (uint64x2x2_t, uint64x2_t, uint64_t, v2di, di, u64)
++
++#undef __LD2_LANE_FUNC
++
++/* vld3_lane */
++
++#define __LD3_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
++			 qmode, ptrmode, funcsuffix, signedtype)	   \
++__extension__ extern __inline intype \
++__attribute__ ((__always_inline__, __gnu_inline__,__artificial__)) \
++vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
++{									   \
++  __builtin_aarch64_simd_ci __o;					   \
++  largetype __temp;							   \
++  __temp.val[0] =							   \
++    vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0));	   \
++  __temp.val[1] =							   \
++    vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
++  __temp.val[2] =							   \
++    vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0));	   \
++  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
++					    (signedtype) __temp.val[0],	   \
++					    0);				   \
++  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
++					    (signedtype) __temp.val[1],	   \
++					    1);				   \
++  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
++					    (signedtype) __temp.val[2],	   \
++					    2);				   \
++  __o =	__builtin_aarch64_ld3_lane##mode (				   \
++	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
++  __b.val[0] = (vectype) __builtin_aarch64_get_dregcidi (__o, 0);	   \
++  __b.val[1] = (vectype) __builtin_aarch64_get_dregcidi (__o, 1);	   \
++  __b.val[2] = (vectype) __builtin_aarch64_get_dregcidi (__o, 2);	   \
++  return __b;								   \
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vld1q_dup_f64 (const float64_t* __a)
+-{
+-  return vdupq_n_f64 (*__a);
+-}
++__LD3_LANE_FUNC (float16x4x3_t, float16x4_t, float16x8x3_t, float16_t, v4hf,
++		 v8hf, hf, f16, float16x8_t)
++__LD3_LANE_FUNC (float32x2x3_t, float32x2_t, float32x4x3_t, float32_t, v2sf, v4sf,
++		 sf, f32, float32x4_t)
++__LD3_LANE_FUNC (float64x1x3_t, float64x1_t, float64x2x3_t, float64_t, df, v2df,
++		 df, f64, float64x2_t)
++__LD3_LANE_FUNC (poly8x8x3_t, poly8x8_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8,
++		 int8x16_t)
++__LD3_LANE_FUNC (poly16x4x3_t, poly16x4_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi,
++		 p16, int16x8_t)
++__LD3_LANE_FUNC (poly64x1x3_t, poly64x1_t, poly64x2x3_t, poly64_t, di,
++		 v2di_ssps, di, p64, poly64x2_t)
++__LD3_LANE_FUNC (int8x8x3_t, int8x8_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8,
++		 int8x16_t)
++__LD3_LANE_FUNC (int16x4x3_t, int16x4_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16,
++		 int16x8_t)
++__LD3_LANE_FUNC (int32x2x3_t, int32x2_t, int32x4x3_t, int32_t, v2si, v4si, si, s32,
++		 int32x4_t)
++__LD3_LANE_FUNC (int64x1x3_t, int64x1_t, int64x2x3_t, int64_t, di, v2di, di, s64,
++		 int64x2_t)
++__LD3_LANE_FUNC (uint8x8x3_t, uint8x8_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8,
++		 int8x16_t)
++__LD3_LANE_FUNC (uint16x4x3_t, uint16x4_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi,
++		 u16, int16x8_t)
++__LD3_LANE_FUNC (uint32x2x3_t, uint32x2_t, uint32x4x3_t, uint32_t, v2si, v4si, si,
++		 u32, int32x4_t)
++__LD3_LANE_FUNC (uint64x1x3_t, uint64x1_t, uint64x2x3_t, uint64_t, di, v2di, di,
++		 u64, int64x2_t)
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vld1q_dup_p8 (const poly8_t* __a)
+-{
+-  return vdupq_n_p8 (*__a);
+-}
++#undef __LD3_LANE_FUNC
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vld1q_dup_p16 (const poly16_t* __a)
+-{
+-  return vdupq_n_p16 (*__a);
+-}
++/* vld3q_lane */
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vld1q_dup_s8 (const int8_t* __a)
+-{
+-  return vdupq_n_s8 (*__a);
++#define __LD3_LANE_FUNC(intype, vtype, ptrtype, mode, ptrmode, funcsuffix) \
++__extension__ extern __inline intype \
++__attribute__ ((__always_inline__, __gnu_inline__,__artificial__)) \
++vld3q_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \
++{									   \
++  __builtin_aarch64_simd_ci __o;					   \
++  intype ret;								   \
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) __b.val[0], 0); \
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) __b.val[1], 1); \
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) __b.val[2], 2); \
++  __o = __builtin_aarch64_ld3_lane##mode (				   \
++	(__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);		   \
++  ret.val[0] = (vtype) __builtin_aarch64_get_qregciv4si (__o, 0);	   \
++  ret.val[1] = (vtype) __builtin_aarch64_get_qregciv4si (__o, 1);	   \
++  ret.val[2] = (vtype) __builtin_aarch64_get_qregciv4si (__o, 2);	   \
++  return ret;								   \
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vld1q_dup_s16 (const int16_t* __a)
+-{
+-  return vdupq_n_s16 (*__a);
+-}
++__LD3_LANE_FUNC (float16x8x3_t, float16x8_t, float16_t, v8hf, hf, f16)
++__LD3_LANE_FUNC (float32x4x3_t, float32x4_t, float32_t, v4sf, sf, f32)
++__LD3_LANE_FUNC (float64x2x3_t, float64x2_t, float64_t, v2df, df, f64)
++__LD3_LANE_FUNC (poly8x16x3_t, poly8x16_t, poly8_t, v16qi, qi, p8)
++__LD3_LANE_FUNC (poly16x8x3_t, poly16x8_t, poly16_t, v8hi, hi, p16)
++__LD3_LANE_FUNC (poly64x2x3_t, poly64x2_t, poly64_t, v2di, di, p64)
++__LD3_LANE_FUNC (int8x16x3_t, int8x16_t, int8_t, v16qi, qi, s8)
++__LD3_LANE_FUNC (int16x8x3_t, int16x8_t, int16_t, v8hi, hi, s16)
++__LD3_LANE_FUNC (int32x4x3_t, int32x4_t, int32_t, v4si, si, s32)
++__LD3_LANE_FUNC (int64x2x3_t, int64x2_t, int64_t, v2di, di, s64)
++__LD3_LANE_FUNC (uint8x16x3_t, uint8x16_t, uint8_t, v16qi, qi, u8)
++__LD3_LANE_FUNC (uint16x8x3_t, uint16x8_t, uint16_t, v8hi, hi, u16)
++__LD3_LANE_FUNC (uint32x4x3_t, uint32x4_t, uint32_t, v4si, si, u32)
++__LD3_LANE_FUNC (uint64x2x3_t, uint64x2_t, uint64_t, v2di, di, u64)
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vld1q_dup_s32 (const int32_t* __a)
+-{
+-  return vdupq_n_s32 (*__a);
+-}
++#undef __LD3_LANE_FUNC
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vld1q_dup_s64 (const int64_t* __a)
+-{
+-  return vdupq_n_s64 (*__a);
+-}
++/* vld4_lane */
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vld1q_dup_u8 (const uint8_t* __a)
+-{
+-  return vdupq_n_u8 (*__a);
++#define __LD4_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
++			 qmode, ptrmode, funcsuffix, signedtype)	   \
++__extension__ extern __inline intype \
++__attribute__ ((__always_inline__, __gnu_inline__,__artificial__)) \
++vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
++{									   \
++  __builtin_aarch64_simd_xi __o;					   \
++  largetype __temp;							   \
++  __temp.val[0] =							   \
++    vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0));	   \
++  __temp.val[1] =							   \
++    vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
++  __temp.val[2] =							   \
++    vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0));	   \
++  __temp.val[3] =							   \
++    vcombine_##funcsuffix (__b.val[3], vcreate_##funcsuffix (0));	   \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
++					    (signedtype) __temp.val[0],	   \
++					    0);				   \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
++					    (signedtype) __temp.val[1],	   \
++					    1);				   \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
++					    (signedtype) __temp.val[2],	   \
++					    2);				   \
++  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
++					    (signedtype) __temp.val[3],	   \
++					    3);				   \
++  __o =	__builtin_aarch64_ld4_lane##mode (				   \
++	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
++  __b.val[0] = (vectype) __builtin_aarch64_get_dregxidi (__o, 0);	   \
++  __b.val[1] = (vectype) __builtin_aarch64_get_dregxidi (__o, 1);	   \
++  __b.val[2] = (vectype) __builtin_aarch64_get_dregxidi (__o, 2);	   \
++  __b.val[3] = (vectype) __builtin_aarch64_get_dregxidi (__o, 3);	   \
++  return __b;								   \
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vld1q_dup_u16 (const uint16_t* __a)
+-{
+-  return vdupq_n_u16 (*__a);
+-}
++/* vld4q_lane */
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vld1q_dup_u32 (const uint32_t* __a)
+-{
+-  return vdupq_n_u32 (*__a);
+-}
++__LD4_LANE_FUNC (float16x4x4_t, float16x4_t, float16x8x4_t, float16_t, v4hf,
++		 v8hf, hf, f16, float16x8_t)
++__LD4_LANE_FUNC (float32x2x4_t, float32x2_t, float32x4x4_t, float32_t, v2sf, v4sf,
++		 sf, f32, float32x4_t)
++__LD4_LANE_FUNC (float64x1x4_t, float64x1_t, float64x2x4_t, float64_t, df, v2df,
++		 df, f64, float64x2_t)
++__LD4_LANE_FUNC (poly8x8x4_t, poly8x8_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8,
++		 int8x16_t)
++__LD4_LANE_FUNC (poly16x4x4_t, poly16x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi,
++		 p16, int16x8_t)
++__LD4_LANE_FUNC (poly64x1x4_t, poly64x1_t, poly64x2x4_t, poly64_t, di,
++		 v2di_ssps, di, p64, poly64x2_t)
++__LD4_LANE_FUNC (int8x8x4_t, int8x8_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8,
++		 int8x16_t)
++__LD4_LANE_FUNC (int16x4x4_t, int16x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16,
++		 int16x8_t)
++__LD4_LANE_FUNC (int32x2x4_t, int32x2_t, int32x4x4_t, int32_t, v2si, v4si, si, s32,
++		 int32x4_t)
++__LD4_LANE_FUNC (int64x1x4_t, int64x1_t, int64x2x4_t, int64_t, di, v2di, di, s64,
++		 int64x2_t)
++__LD4_LANE_FUNC (uint8x8x4_t, uint8x8_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8,
++		 int8x16_t)
++__LD4_LANE_FUNC (uint16x4x4_t, uint16x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi,
++		 u16, int16x8_t)
++__LD4_LANE_FUNC (uint32x2x4_t, uint32x2_t, uint32x4x4_t, uint32_t, v2si, v4si, si,
++		 u32, int32x4_t)
++__LD4_LANE_FUNC (uint64x1x4_t, uint64x1_t, uint64x2x4_t, uint64_t, di, v2di, di,
++		 u64, int64x2_t)
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vld1q_dup_u64 (const uint64_t* __a)
+-{
+-  return vdupq_n_u64 (*__a);
+-}
++#undef __LD4_LANE_FUNC
+ 
+-/* vld1_lane  */
++/* vld4q_lane */
+ 
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
+-vld1_lane_f16 (const float16_t *__src, float16x4_t __vec, const int __lane)
+-{
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++#define __LD4_LANE_FUNC(intype, vtype, ptrtype, mode, ptrmode, funcsuffix) \
++__extension__ extern __inline intype \
++__attribute__ ((__always_inline__, __gnu_inline__,__artificial__)) \
++vld4q_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \
++{									   \
++  __builtin_aarch64_simd_xi __o;					   \
++  intype ret;								   \
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[0], 0); \
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[1], 1); \
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[2], 2); \
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[3], 3); \
++  __o = __builtin_aarch64_ld4_lane##mode (				   \
++	(__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);		   \
++  ret.val[0] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 0);	   \
++  ret.val[1] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 1);	   \
++  ret.val[2] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 2);	   \
++  ret.val[3] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 3);	   \
++  return ret;								   \
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vld1_lane_f32 (const float32_t *__src, float32x2_t __vec, const int __lane)
+-{
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+-}
++__LD4_LANE_FUNC (float16x8x4_t, float16x8_t, float16_t, v8hf, hf, f16)
++__LD4_LANE_FUNC (float32x4x4_t, float32x4_t, float32_t, v4sf, sf, f32)
++__LD4_LANE_FUNC (float64x2x4_t, float64x2_t, float64_t, v2df, df, f64)
++__LD4_LANE_FUNC (poly8x16x4_t, poly8x16_t, poly8_t, v16qi, qi, p8)
++__LD4_LANE_FUNC (poly16x8x4_t, poly16x8_t, poly16_t, v8hi, hi, p16)
++__LD4_LANE_FUNC (poly64x2x4_t, poly64x2_t, poly64_t, v2di, di, p64)
++__LD4_LANE_FUNC (int8x16x4_t, int8x16_t, int8_t, v16qi, qi, s8)
++__LD4_LANE_FUNC (int16x8x4_t, int16x8_t, int16_t, v8hi, hi, s16)
++__LD4_LANE_FUNC (int32x4x4_t, int32x4_t, int32_t, v4si, si, s32)
++__LD4_LANE_FUNC (int64x2x4_t, int64x2_t, int64_t, v2di, di, s64)
++__LD4_LANE_FUNC (uint8x16x4_t, uint8x16_t, uint8_t, v16qi, qi, u8)
++__LD4_LANE_FUNC (uint16x8x4_t, uint16x8_t, uint16_t, v8hi, hi, u16)
++__LD4_LANE_FUNC (uint32x4x4_t, uint32x4_t, uint32_t, v4si, si, u32)
++__LD4_LANE_FUNC (uint64x2x4_t, uint64x2_t, uint64_t, v2di, di, u64)
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vld1_lane_f64 (const float64_t *__src, float64x1_t __vec, const int __lane)
+-{
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+-}
++#undef __LD4_LANE_FUNC
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vld1_lane_p8 (const poly8_t *__src, poly8x8_t __vec, const int __lane)
+-{
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
+-}
++/* vmax */
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vld1_lane_p16 (const poly16_t *__src, poly16x4_t __vec, const int __lane)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smax_nanv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vld1_lane_s8 (const int8_t *__src, int8x8_t __vec, const int __lane)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++    return (float64x1_t)
++      { __builtin_aarch64_smax_nandf (vget_lane_f64 (__a, 0),
++				      vget_lane_f64 (__b, 0)) };
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vld1_lane_s16 (const int16_t *__src, int16x4_t __vec, const int __lane)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smaxv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vld1_lane_s32 (const int32_t *__src, int32x2_t __vec, const int __lane)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smaxv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vld1_lane_s64 (const int64_t *__src, int64x1_t __vec, const int __lane)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smaxv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vld1_lane_u8 (const uint8_t *__src, uint8x8_t __vec, const int __lane)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (uint8x8_t) __builtin_aarch64_umaxv8qi ((int8x8_t) __a,
++						 (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vld1_lane_u16 (const uint16_t *__src, uint16x4_t __vec, const int __lane)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (uint16x4_t) __builtin_aarch64_umaxv4hi ((int16x4_t) __a,
++						  (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vld1_lane_u32 (const uint32_t *__src, uint32x2_t __vec, const int __lane)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (uint32x2_t) __builtin_aarch64_umaxv2si ((int32x2_t) __a,
++						  (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vld1_lane_u64 (const uint64_t *__src, uint64x1_t __vec, const int __lane)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smax_nanv4sf (__a, __b);
+ }
+ 
+-/* vld1q_lane  */
+-
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
+-vld1q_lane_f16 (const float16_t *__src, float16x8_t __vec, const int __lane)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smax_nanv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vld1q_lane_f32 (const float32_t *__src, float32x4_t __vec, const int __lane)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smaxv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vld1q_lane_f64 (const float64_t *__src, float64x2_t __vec, const int __lane)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smaxv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vld1q_lane_p8 (const poly8_t *__src, poly8x16_t __vec, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_smaxv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vld1q_lane_p16 (const poly16_t *__src, poly16x8_t __vec, const int __lane)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (uint8x16_t) __builtin_aarch64_umaxv16qi ((int8x16_t) __a,
++						   (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vld1q_lane_s8 (const int8_t *__src, int8x16_t __vec, const int __lane)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (uint16x8_t) __builtin_aarch64_umaxv8hi ((int16x8_t) __a,
++						  (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vld1q_lane_s16 (const int16_t *__src, int16x8_t __vec, const int __lane)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (uint32x4_t) __builtin_aarch64_umaxv4si ((int32x4_t) __a,
++						  (int32x4_t) __b);
+ }
++/* vmulx */
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vld1q_lane_s32 (const int32_t *__src, int32x4_t __vec, const int __lane)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_fmulxv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vld1q_lane_s64 (const int64_t *__src, int64x2_t __vec, const int __lane)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_fmulxv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vld1q_lane_u8 (const uint8_t *__src, uint8x16_t __vec, const int __lane)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return (float64x1_t) {__builtin_aarch64_fmulxdf (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vld1q_lane_u16 (const uint16_t *__src, uint16x8_t __vec, const int __lane)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_fmulxv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vld1q_lane_u32 (const uint32_t *__src, uint32x4_t __vec, const int __lane)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxs_f32 (float32_t __a, float32_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_fmulxsf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vld1q_lane_u64 (const uint64_t *__src, uint64x2_t __vec, const int __lane)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxd_f64 (float64_t __a, float64_t __b)
+ {
+-  return __aarch64_vset_lane_any (*__src, __vec, __lane);
++  return __builtin_aarch64_fmulxdf (__a, __b);
+ }
+ 
+-/* vldn */
+-
+-__extension__ static __inline int64x1x2_t __attribute__ ((__always_inline__))
+-vld2_s64 (const int64_t * __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_lane_f32 (float32x2_t __a, float32x2_t __v, const int __lane)
+ {
+-  int64x1x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
+-  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
+-  return ret;
++  return vmulx_f32 (__a, __aarch64_vdup_lane_f32 (__v, __lane));
+ }
+ 
+-__extension__ static __inline uint64x1x2_t __attribute__ ((__always_inline__))
+-vld2_u64 (const uint64_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_lane_f64 (float64x1_t __a, float64x1_t __v, const int __lane)
+ {
+-  uint64x1x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
+-  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
+-  return ret;
++  return vmulx_f64 (__a, __aarch64_vdup_lane_f64 (__v, __lane));
+ }
+ 
+-__extension__ static __inline float64x1x2_t __attribute__ ((__always_inline__))
+-vld2_f64 (const float64_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_lane_f32 (float32x4_t __a, float32x2_t __v, const int __lane)
+ {
+-  float64x1x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 0)};
+-  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 1)};
+-  return ret;
++  return vmulxq_f32 (__a, __aarch64_vdupq_lane_f32 (__v, __lane));
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
+-vld2_s8 (const int8_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_lane_f64 (float64x2_t __a, float64x1_t __v, const int __lane)
+ {
+-  int8x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
+-  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
+-  return ret;
++  return vmulxq_f64 (__a, __aarch64_vdupq_lane_f64 (__v, __lane));
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
+-vld2_p8 (const poly8_t * __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_laneq_f32 (float32x2_t __a, float32x4_t __v, const int __lane)
+ {
+-  poly8x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
+-  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
+-  return ret;
++  return vmulx_f32 (__a, __aarch64_vdup_laneq_f32 (__v, __lane));
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
+-vld2_s16 (const int16_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_laneq_f64 (float64x1_t __a, float64x2_t __v, const int __lane)
+ {
+-  int16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
+-  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
+-  return ret;
++  return vmulx_f64 (__a, __aarch64_vdup_laneq_f64 (__v, __lane));
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
+-vld2_p16 (const poly16_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_laneq_f32 (float32x4_t __a, float32x4_t __v, const int __lane)
+ {
+-  poly16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
+-  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
+-  return ret;
++  return vmulxq_f32 (__a, __aarch64_vdupq_laneq_f32 (__v, __lane));
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
+-vld2_s32 (const int32_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_laneq_f64 (float64x2_t __a, float64x2_t __v, const int __lane)
+ {
+-  int32x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
+-  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
+-  return ret;
++  return vmulxq_f64 (__a, __aarch64_vdupq_laneq_f64 (__v, __lane));
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
+-vld2_u8 (const uint8_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxs_lane_f32 (float32_t __a, float32x2_t __v, const int __lane)
+ {
+-  uint8x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
+-  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
+-  return ret;
++  return vmulxs_f32 (__a, __aarch64_vget_lane_any (__v, __lane));
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
+-vld2_u16 (const uint16_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxs_laneq_f32 (float32_t __a, float32x4_t __v, const int __lane)
+ {
+-  uint16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
+-  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
+-  return ret;
++  return vmulxs_f32 (__a, __aarch64_vget_lane_any (__v, __lane));
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
+-vld2_u32 (const uint32_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxd_lane_f64 (float64_t __a, float64x1_t __v, const int __lane)
+ {
+-  uint32x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
+-  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
+-  return ret;
++  return vmulxd_f64 (__a, __aarch64_vget_lane_any (__v, __lane));
+ }
+ 
+-__extension__ static __inline float16x4x2_t __attribute__ ((__always_inline__))
+-vld2_f16 (const float16_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxd_laneq_f64 (float64_t __a, float64x2_t __v, const int __lane)
+ {
+-  float16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4hf (__a);
+-  ret.val[0] = __builtin_aarch64_get_dregoiv4hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_dregoiv4hf (__o, 1);
+-  return ret;
++  return vmulxd_f64 (__a, __aarch64_vget_lane_any (__v, __lane));
+ }
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
+-vld2_f32 (const float32_t * __a)
++/* vpmax  */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_s8 (int8x8_t a, int8x8_t b)
+ {
+-  float32x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v2sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 0);
+-  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smaxpv8qi (a, b);
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
+-vld2q_s8 (const int8_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_s16 (int16x4_t a, int16x4_t b)
+ {
+-  int8x16x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
+-  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smaxpv4hi (a, b);
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
+-vld2q_p8 (const poly8_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_s32 (int32x2_t a, int32x2_t b)
+ {
+-  poly8x16x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
+-  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smaxpv2si (a, b);
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_s16 (const int16_t * __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_u8 (uint8x8_t a, uint8x8_t b)
+ {
+-  int16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
+-  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
+-  return ret;
++  return (uint8x8_t) __builtin_aarch64_umaxpv8qi ((int8x8_t) a,
++						  (int8x8_t) b);
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_p16 (const poly16_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_u16 (uint16x4_t a, uint16x4_t b)
+ {
+-  poly16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
+-  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
+-  return ret;
++  return (uint16x4_t) __builtin_aarch64_umaxpv4hi ((int16x4_t) a,
++						   (int16x4_t) b);
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
+-vld2q_s32 (const int32_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_u32 (uint32x2_t a, uint32x2_t b)
+ {
+-  int32x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
+-  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
+-  return ret;
++  return (uint32x2_t) __builtin_aarch64_umaxpv2si ((int32x2_t) a,
++						   (int32x2_t) b);
+ }
+ 
+-__extension__ static __inline int64x2x2_t __attribute__ ((__always_inline__))
+-vld2q_s64 (const int64_t * __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_s8 (int8x16_t a, int8x16_t b)
+ {
+-  int64x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
+-  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smaxpv16qi (a, b);
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
+-vld2q_u8 (const uint8_t * __a)
+-{
+-  uint8x16x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
+-  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
+-  return ret;
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_s16 (int16x8_t a, int16x8_t b)
++{
++  return __builtin_aarch64_smaxpv8hi (a, b);
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_u16 (const uint16_t * __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_s32 (int32x4_t a, int32x4_t b)
+ {
+-  uint16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
+-  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smaxpv4si (a, b);
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
+-vld2q_u32 (const uint32_t * __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_u8 (uint8x16_t a, uint8x16_t b)
+ {
+-  uint32x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
+-  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
+-  return ret;
++  return (uint8x16_t) __builtin_aarch64_umaxpv16qi ((int8x16_t) a,
++						    (int8x16_t) b);
+ }
+ 
+-__extension__ static __inline uint64x2x2_t __attribute__ ((__always_inline__))
+-vld2q_u64 (const uint64_t * __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_u16 (uint16x8_t a, uint16x8_t b)
+ {
+-  uint64x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
+-  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
+-  return ret;
++  return (uint16x8_t) __builtin_aarch64_umaxpv8hi ((int16x8_t) a,
++						   (int16x8_t) b);
+ }
+ 
+-__extension__ static __inline float16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_f16 (const float16_t * __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_u32 (uint32x4_t a, uint32x4_t b)
+ {
+-  float16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v8hf (__a);
+-  ret.val[0] = __builtin_aarch64_get_qregoiv8hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_qregoiv8hf (__o, 1);
+-  return ret;
++  return (uint32x4_t) __builtin_aarch64_umaxpv4si ((int32x4_t) a,
++						   (int32x4_t) b);
+ }
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
+-vld2q_f32 (const float32_t * __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_f32 (float32x2_t a, float32x2_t b)
+ {
+-  float32x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v4sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 0);
+-  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smax_nanpv2sf (a, b);
+ }
+ 
+-__extension__ static __inline float64x2x2_t __attribute__ ((__always_inline__))
+-vld2q_f64 (const float64_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_f32 (float32x4_t a, float32x4_t b)
+ {
+-  float64x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2v2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 0);
+-  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smax_nanpv4sf (a, b);
+ }
+ 
+-__extension__ static __inline int64x1x3_t __attribute__ ((__always_inline__))
+-vld3_s64 (const int64_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_f64 (float64x2_t a, float64x2_t b)
+ {
+-  int64x1x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
+-  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
+-  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smax_nanpv2df (a, b);
+ }
+ 
+-__extension__ static __inline uint64x1x3_t __attribute__ ((__always_inline__))
+-vld3_u64 (const uint64_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxqd_f64 (float64x2_t a)
+ {
+-  uint64x1x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
+-  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
+-  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_nan_scal_v2df (a);
+ }
+ 
+-__extension__ static __inline float64x1x3_t __attribute__ ((__always_inline__))
+-vld3_f64 (const float64_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxs_f32 (float32x2_t a)
+ {
+-  float64x1x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 0)};
+-  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 1)};
+-  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 2)};
+-  return ret;
++  return __builtin_aarch64_reduc_smax_nan_scal_v2sf (a);
+ }
+ 
+-__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__))
+-vld3_s8 (const int8_t * __a)
++/* vpmaxnm  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnm_f32 (float32x2_t a, float32x2_t b)
+ {
+-  int8x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
+-  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
+-  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smaxpv2sf (a, b);
+ }
+ 
+-__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__))
+-vld3_p8 (const poly8_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnmq_f32 (float32x4_t a, float32x4_t b)
+ {
+-  poly8x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
+-  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
+-  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smaxpv4sf (a, b);
+ }
+ 
+-__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__))
+-vld3_s16 (const int16_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnmq_f64 (float64x2_t a, float64x2_t b)
+ {
+-  int16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
+-  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
+-  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smaxpv2df (a, b);
+ }
+ 
+-__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__))
+-vld3_p16 (const poly16_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnmqd_f64 (float64x2_t a)
+ {
+-  poly16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
+-  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
+-  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v2df (a);
+ }
+ 
+-__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__))
+-vld3_s32 (const int32_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnms_f32 (float32x2_t a)
+ {
+-  int32x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
+-  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
+-  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v2sf (a);
+ }
+ 
+-__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__))
+-vld3_u8 (const uint8_t * __a)
++/* vpmin  */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_s8 (int8x8_t a, int8x8_t b)
+ {
+-  uint8x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
+-  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
+-  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv8qi (a, b);
+ }
+ 
+-__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__))
+-vld3_u16 (const uint16_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_s16 (int16x4_t a, int16x4_t b)
+ {
+-  uint16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
+-  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
+-  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv4hi (a, b);
+ }
+ 
+-__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__))
+-vld3_u32 (const uint32_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_s32 (int32x2_t a, int32x2_t b)
+ {
+-  uint32x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
+-  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
+-  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv2si (a, b);
+ }
+ 
+-__extension__ static __inline float16x4x3_t __attribute__ ((__always_inline__))
+-vld3_f16 (const float16_t * __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_u8 (uint8x8_t a, uint8x8_t b)
+ {
+-  float16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4hf (__a);
+-  ret.val[0] = __builtin_aarch64_get_dregciv4hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_dregciv4hf (__o, 1);
+-  ret.val[2] = __builtin_aarch64_get_dregciv4hf (__o, 2);
+-  return ret;
++  return (uint8x8_t) __builtin_aarch64_uminpv8qi ((int8x8_t) a,
++						  (int8x8_t) b);
+ }
+ 
+-__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__))
+-vld3_f32 (const float32_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_u16 (uint16x4_t a, uint16x4_t b)
+ {
+-  float32x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v2sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 0);
+-  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 1);
+-  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 2);
+-  return ret;
++  return (uint16x4_t) __builtin_aarch64_uminpv4hi ((int16x4_t) a,
++						   (int16x4_t) b);
+ }
+ 
+-__extension__ static __inline int8x16x3_t __attribute__ ((__always_inline__))
+-vld3q_s8 (const int8_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_u32 (uint32x2_t a, uint32x2_t b)
+ {
+-  int8x16x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
+-  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
+-  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
+-  return ret;
++  return (uint32x2_t) __builtin_aarch64_uminpv2si ((int32x2_t) a,
++						   (int32x2_t) b);
+ }
+ 
+-__extension__ static __inline poly8x16x3_t __attribute__ ((__always_inline__))
+-vld3q_p8 (const poly8_t * __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_s8 (int8x16_t a, int8x16_t b)
+ {
+-  poly8x16x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
+-  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
+-  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv16qi (a, b);
+ }
+ 
+-__extension__ static __inline int16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_s16 (const int16_t * __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_s16 (int16x8_t a, int16x8_t b)
+ {
+-  int16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
+-  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
+-  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv8hi (a, b);
+ }
+ 
+-__extension__ static __inline poly16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_p16 (const poly16_t * __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_s32 (int32x4_t a, int32x4_t b)
+ {
+-  poly16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
+-  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
+-  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv4si (a, b);
+ }
+ 
+-__extension__ static __inline int32x4x3_t __attribute__ ((__always_inline__))
+-vld3q_s32 (const int32_t * __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_u8 (uint8x16_t a, uint8x16_t b)
+ {
+-  int32x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
+-  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
+-  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
+-  return ret;
++  return (uint8x16_t) __builtin_aarch64_uminpv16qi ((int8x16_t) a,
++						    (int8x16_t) b);
+ }
+ 
+-__extension__ static __inline int64x2x3_t __attribute__ ((__always_inline__))
+-vld3q_s64 (const int64_t * __a)
+-{
+-  int64x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
+-  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
+-  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
+-  return ret;
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_u16 (uint16x8_t a, uint16x8_t b)
++{
++  return (uint16x8_t) __builtin_aarch64_uminpv8hi ((int16x8_t) a,
++						   (int16x8_t) b);
+ }
+ 
+-__extension__ static __inline uint8x16x3_t __attribute__ ((__always_inline__))
+-vld3q_u8 (const uint8_t * __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_u32 (uint32x4_t a, uint32x4_t b)
+ {
+-  uint8x16x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
+-  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
+-  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
+-  return ret;
++  return (uint32x4_t) __builtin_aarch64_uminpv4si ((int32x4_t) a,
++						   (int32x4_t) b);
+ }
+ 
+-__extension__ static __inline uint16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_u16 (const uint16_t * __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_f32 (float32x2_t a, float32x2_t b)
+ {
+-  uint16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
+-  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
+-  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smin_nanpv2sf (a, b);
+ }
+ 
+-__extension__ static __inline uint32x4x3_t __attribute__ ((__always_inline__))
+-vld3q_u32 (const uint32_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_f32 (float32x4_t a, float32x4_t b)
+ {
+-  uint32x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
+-  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
+-  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smin_nanpv4sf (a, b);
+ }
+ 
+-__extension__ static __inline uint64x2x3_t __attribute__ ((__always_inline__))
+-vld3q_u64 (const uint64_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_f64 (float64x2_t a, float64x2_t b)
+ {
+-  uint64x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
+-  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
+-  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
+-  return ret;
++  return __builtin_aarch64_smin_nanpv2df (a, b);
+ }
+ 
+-__extension__ static __inline float16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_f16 (const float16_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminqd_f64 (float64x2_t a)
+ {
+-  float16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v8hf (__a);
+-  ret.val[0] = __builtin_aarch64_get_qregciv8hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_qregciv8hf (__o, 1);
+-  ret.val[2] = __builtin_aarch64_get_qregciv8hf (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_nan_scal_v2df (a);
+ }
+ 
+-__extension__ static __inline float32x4x3_t __attribute__ ((__always_inline__))
+-vld3q_f32 (const float32_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmins_f32 (float32x2_t a)
+ {
+-  float32x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v4sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 0);
+-  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 1);
+-  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_nan_scal_v2sf (a);
+ }
+ 
+-__extension__ static __inline float64x2x3_t __attribute__ ((__always_inline__))
+-vld3q_f64 (const float64_t * __a)
++/* vpminnm  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnm_f32 (float32x2_t a, float32x2_t b)
+ {
+-  float64x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3v2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 0);
+-  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 1);
+-  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 2);
+-  return ret;
++  return __builtin_aarch64_sminpv2sf (a, b);
+ }
+ 
+-__extension__ static __inline int64x1x4_t __attribute__ ((__always_inline__))
+-vld4_s64 (const int64_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnmq_f32 (float32x4_t a, float32x4_t b)
+ {
+-  int64x1x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
+-  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
+-  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
+-  ret.val[3] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_sminpv4sf (a, b);
+ }
+ 
+-__extension__ static __inline uint64x1x4_t __attribute__ ((__always_inline__))
+-vld4_u64 (const uint64_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnmq_f64 (float64x2_t a, float64x2_t b)
+ {
+-  uint64x1x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
+-  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
+-  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
+-  ret.val[3] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_sminpv2df (a, b);
+ }
+ 
+-__extension__ static __inline float64x1x4_t __attribute__ ((__always_inline__))
+-vld4_f64 (const float64_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnmqd_f64 (float64x2_t a)
+ {
+-  float64x1x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 0)};
+-  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 1)};
+-  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 2)};
+-  ret.val[3] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 3)};
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v2df (a);
+ }
+ 
+-__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__))
+-vld4_s8 (const int8_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnms_f32 (float32x2_t a)
+ {
+-  int8x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
+-  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
+-  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
+-  ret.val[3] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v2sf (a);
+ }
+ 
+-__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__))
+-vld4_p8 (const poly8_t * __a)
++/* vmaxnm  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnm_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  poly8x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
+-  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
+-  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
+-  ret.val[3] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_fmaxv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__))
+-vld4_s16 (const int16_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnm_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  int16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
+-  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
+-  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
+-  ret.val[3] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
+-  return ret;
++  return (float64x1_t)
++    { __builtin_aarch64_fmaxdf (vget_lane_f64 (__a, 0),
++				vget_lane_f64 (__b, 0)) };
+ }
+ 
+-__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__))
+-vld4_p16 (const poly16_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  poly16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
+-  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
+-  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
+-  ret.val[3] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_fmaxv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__))
+-vld4_s32 (const int32_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  int32x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
+-  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
+-  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
+-  ret.val[3] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
+-  return ret;
++  return __builtin_aarch64_fmaxv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__))
+-vld4_u8 (const uint8_t * __a)
++/* vmaxv  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_f32 (float32x2_t __a)
+ {
+-  uint8x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
+-  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
+-  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
+-  ret.val[3] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_nan_scal_v2sf (__a);
+ }
+ 
+-__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__))
+-vld4_u16 (const uint16_t * __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_s8 (int8x8_t __a)
+ {
+-  uint16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
+-  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
+-  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
+-  ret.val[3] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v8qi (__a);
+ }
+ 
+-__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__))
+-vld4_u32 (const uint32_t * __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_s16 (int16x4_t __a)
+ {
+-  uint32x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
+-  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
+-  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
+-  ret.val[3] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v4hi (__a);
+ }
+ 
+-__extension__ static __inline float16x4x4_t __attribute__ ((__always_inline__))
+-vld4_f16 (const float16_t * __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_s32 (int32x2_t __a)
+ {
+-  float16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4hf (__a);
+-  ret.val[0] = __builtin_aarch64_get_dregxiv4hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_dregxiv4hf (__o, 1);
+-  ret.val[2] = __builtin_aarch64_get_dregxiv4hf (__o, 2);
+-  ret.val[3] = __builtin_aarch64_get_dregxiv4hf (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v2si (__a);
+ }
+ 
+-__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__))
+-vld4_f32 (const float32_t * __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_u8 (uint8x8_t __a)
+ {
+-  float32x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v2sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 0);
+-  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 1);
+-  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 2);
+-  ret.val[3] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_umax_scal_v8qi_uu (__a);
+ }
+ 
+-__extension__ static __inline int8x16x4_t __attribute__ ((__always_inline__))
+-vld4q_s8 (const int8_t * __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_u16 (uint16x4_t __a)
+ {
+-  int8x16x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
+-  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
+-  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
+-  ret.val[3] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_umax_scal_v4hi_uu (__a);
+ }
+ 
+-__extension__ static __inline poly8x16x4_t __attribute__ ((__always_inline__))
+-vld4q_p8 (const poly8_t * __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_u32 (uint32x2_t __a)
+ {
+-  poly8x16x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
+-  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
+-  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
+-  ret.val[3] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_umax_scal_v2si_uu (__a);
+ }
+ 
+-__extension__ static __inline int16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_s16 (const int16_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_f32 (float32x4_t __a)
+ {
+-  int16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
+-  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
+-  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
+-  ret.val[3] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_nan_scal_v4sf (__a);
+ }
+ 
+-__extension__ static __inline poly16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_p16 (const poly16_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_f64 (float64x2_t __a)
+ {
+-  poly16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
+-  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
+-  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
+-  ret.val[3] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_nan_scal_v2df (__a);
+ }
+ 
+-__extension__ static __inline int32x4x4_t __attribute__ ((__always_inline__))
+-vld4q_s32 (const int32_t * __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_s8 (int8x16_t __a)
+ {
+-  int32x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
+-  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
+-  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
+-  ret.val[3] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v16qi (__a);
+ }
+ 
+-__extension__ static __inline int64x2x4_t __attribute__ ((__always_inline__))
+-vld4q_s64 (const int64_t * __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_s16 (int16x8_t __a)
+ {
+-  int64x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
+-  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
+-  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
+-  ret.val[3] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v8hi (__a);
+ }
+ 
+-__extension__ static __inline uint8x16x4_t __attribute__ ((__always_inline__))
+-vld4q_u8 (const uint8_t * __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_s32 (int32x4_t __a)
+ {
+-  uint8x16x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
+-  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
+-  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
+-  ret.val[3] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v4si (__a);
+ }
+ 
+-__extension__ static __inline uint16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_u16 (const uint16_t * __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_u8 (uint8x16_t __a)
+ {
+-  uint16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
+-  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
+-  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
+-  ret.val[3] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_umax_scal_v16qi_uu (__a);
+ }
+ 
+-__extension__ static __inline uint32x4x4_t __attribute__ ((__always_inline__))
+-vld4q_u32 (const uint32_t * __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_u16 (uint16x8_t __a)
+ {
+-  uint32x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
+-  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
+-  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
+-  ret.val[3] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_umax_scal_v8hi_uu (__a);
+ }
+ 
+-__extension__ static __inline uint64x2x4_t __attribute__ ((__always_inline__))
+-vld4q_u64 (const uint64_t * __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_u32 (uint32x4_t __a)
+ {
+-  uint64x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
+-  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
+-  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
+-  ret.val[3] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_umax_scal_v4si_uu (__a);
+ }
+ 
+-__extension__ static __inline float16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_f16 (const float16_t * __a)
++/* vmaxnmv  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmv_f32 (float32x2_t __a)
+ {
+-  float16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v8hf (__a);
+-  ret.val[0] = __builtin_aarch64_get_qregxiv8hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_qregxiv8hf (__o, 1);
+-  ret.val[2] = __builtin_aarch64_get_qregxiv8hf (__o, 2);
+-  ret.val[3] = __builtin_aarch64_get_qregxiv8hf (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v2sf (__a);
+ }
+ 
+-__extension__ static __inline float32x4x4_t __attribute__ ((__always_inline__))
+-vld4q_f32 (const float32_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmvq_f32 (float32x4_t __a)
+ {
+-  float32x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v4sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 0);
+-  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 1);
+-  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 2);
+-  ret.val[3] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v4sf (__a);
+ }
+ 
+-__extension__ static __inline float64x2x4_t __attribute__ ((__always_inline__))
+-vld4q_f64 (const float64_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmvq_f64 (float64x2_t __a)
+ {
+-  float64x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4v2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 0);
+-  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 1);
+-  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 2);
+-  ret.val[3] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 3);
+-  return ret;
++  return __builtin_aarch64_reduc_smax_scal_v2df (__a);
+ }
+ 
+-/* vldn_dup */
++/* vmin  */
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
+-vld2_dup_s8 (const int8_t * __a)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  int8x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
+-  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smin_nanv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
+-vld2_dup_s16 (const int16_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  int16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
+-  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
+-  return ret;
++    return (float64x1_t)
++	  { __builtin_aarch64_smin_nandf (vget_lane_f64 (__a, 0),
++					  vget_lane_f64 (__b, 0)) };
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
+-vld2_dup_s32 (const int32_t * __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  int32x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
+-  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
+-  return ret;
++  return __builtin_aarch64_sminv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline float16x4x2_t __attribute__ ((__always_inline__))
+-vld2_dup_f16 (const float16_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  float16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4hf ((const __builtin_aarch64_simd_hf *) __a);
+-  ret.val[0] = __builtin_aarch64_get_dregoiv4hf (__o, 0);
+-  ret.val[1] = (float16x4_t) __builtin_aarch64_get_dregoiv4hf (__o, 1);
+-  return ret;
++  return __builtin_aarch64_sminv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
+-vld2_dup_f32 (const float32_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  float32x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv2sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 0);
+-  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 1);
+-  return ret;
++  return __builtin_aarch64_sminv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x1x2_t __attribute__ ((__always_inline__))
+-vld2_dup_f64 (const float64_t * __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  float64x1x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rdf ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 0)};
+-  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 1)};
+-  return ret;
++  return (uint8x8_t) __builtin_aarch64_uminv8qi ((int8x8_t) __a,
++						 (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
+-vld2_dup_u8 (const uint8_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  uint8x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
+-  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
+-  return ret;
++  return (uint16x4_t) __builtin_aarch64_uminv4hi ((int16x4_t) __a,
++						  (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
+-vld2_dup_u16 (const uint16_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  uint16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
+-  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
+-  return ret;
++  return (uint32x2_t) __builtin_aarch64_uminv2si ((int32x2_t) __a,
++						  (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
+-vld2_dup_u32 (const uint32_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  uint32x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
+-  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smin_nanv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
+-vld2_dup_p8 (const poly8_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  poly8x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
+-  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_smin_nanv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
+-vld2_dup_p16 (const poly16_t * __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  poly16x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
+-  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_sminv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1x2_t __attribute__ ((__always_inline__))
+-vld2_dup_s64 (const int64_t * __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  int64x1x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rdi ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
+-  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_sminv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1x2_t __attribute__ ((__always_inline__))
+-vld2_dup_u64 (const uint64_t * __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  uint64x1x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rdi ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
+-  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_sminv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_s8 (const int8_t * __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  int8x16x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
+-  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
+-  return ret;
++  return (uint8x16_t) __builtin_aarch64_uminv16qi ((int8x16_t) __a,
++						   (int8x16_t) __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_u16 (uint16x8_t __a, uint16x8_t __b)
++{
++  return (uint16x8_t) __builtin_aarch64_uminv8hi ((int16x8_t) __a,
++						  (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_p8 (const poly8_t * __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_u32 (uint32x4_t __a, uint32x4_t __b)
++{
++  return (uint32x4_t) __builtin_aarch64_uminv4si ((int32x4_t) __a,
++						  (int32x4_t) __b);
++}
++
++/* vminnm  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnm_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  poly8x16x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
+-  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_fminv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_s16 (const int16_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnm_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  int16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
+-  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
+-  return ret;
++  return (float64x1_t)
++    { __builtin_aarch64_fmindf (vget_lane_f64 (__a, 0),
++				vget_lane_f64 (__b, 0)) };
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_p16 (const poly16_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  poly16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
+-  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_fminv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_s32 (const int32_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  int32x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
+-  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
+-  return ret;
++  return __builtin_aarch64_fminv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_s64 (const int64_t * __a)
++/* vminv  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_f32 (float32x2_t __a)
+ {
+-  int64x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
+-  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_nan_scal_v2sf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_u8 (const uint8_t * __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_s8 (int8x8_t __a)
+ {
+-  uint8x16x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
+-  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v8qi (__a);
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_u16 (const uint16_t * __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_s16 (int16x4_t __a)
+ {
+-  uint16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
+-  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v4hi (__a);
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_u32 (const uint32_t * __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_s32 (int32x2_t __a)
+ {
+-  uint32x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
+-  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v2si (__a);
+ }
+ 
+-__extension__ static __inline uint64x2x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_u64 (const uint64_t * __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_u8 (uint8x8_t __a)
+ {
+-  uint64x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
+-  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_umin_scal_v8qi_uu (__a);
+ }
+ 
+-__extension__ static __inline float16x8x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_f16 (const float16_t * __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_u16 (uint16x4_t __a)
+ {
+-  float16x8x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv8hf ((const __builtin_aarch64_simd_hf *) __a);
+-  ret.val[0] = (float16x8_t) __builtin_aarch64_get_qregoiv8hf (__o, 0);
+-  ret.val[1] = __builtin_aarch64_get_qregoiv8hf (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_umin_scal_v4hi_uu (__a);
+ }
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_f32 (const float32_t * __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_u32 (uint32x2_t __a)
+ {
+-  float32x4x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv4sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 0);
+-  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_umin_scal_v2si_uu (__a);
+ }
+ 
+-__extension__ static __inline float64x2x2_t __attribute__ ((__always_inline__))
+-vld2q_dup_f64 (const float64_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_f32 (float32x4_t __a)
+ {
+-  float64x2x2_t ret;
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_ld2rv2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 0);
+-  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 1);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_nan_scal_v4sf (__a);
+ }
+ 
+-__extension__ static __inline int64x1x3_t __attribute__ ((__always_inline__))
+-vld3_dup_s64 (const int64_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_f64 (float64x2_t __a)
+ {
+-  int64x1x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rdi ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
+-  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
+-  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_nan_scal_v2df (__a);
+ }
+ 
+-__extension__ static __inline uint64x1x3_t __attribute__ ((__always_inline__))
+-vld3_dup_u64 (const uint64_t * __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_s8 (int8x16_t __a)
+ {
+-  uint64x1x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rdi ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
+-  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
+-  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v16qi (__a);
+ }
+ 
+-__extension__ static __inline float64x1x3_t __attribute__ ((__always_inline__))
+-vld3_dup_f64 (const float64_t * __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_s16 (int16x8_t __a)
+ {
+-  float64x1x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rdf ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 0)};
+-  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 1)};
+-  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregcidf (__o, 2)};
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v8hi (__a);
+ }
+ 
+-__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__))
+-vld3_dup_s8 (const int8_t * __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_s32 (int32x4_t __a)
+ {
+-  int8x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
+-  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
+-  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v4si (__a);
+ }
+ 
+-__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__))
+-vld3_dup_p8 (const poly8_t * __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_u8 (uint8x16_t __a)
+ {
+-  poly8x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
+-  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
+-  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_umin_scal_v16qi_uu (__a);
+ }
+ 
+-__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__))
+-vld3_dup_s16 (const int16_t * __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_u16 (uint16x8_t __a)
+ {
+-  int16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
+-  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
+-  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_umin_scal_v8hi_uu (__a);
+ }
+ 
+-__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__))
+-vld3_dup_p16 (const poly16_t * __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_u32 (uint32x4_t __a)
+ {
+-  poly16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
+-  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
+-  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_umin_scal_v4si_uu (__a);
+ }
+ 
+-__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__))
+-vld3_dup_s32 (const int32_t * __a)
++/* vminnmv  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmv_f32 (float32x2_t __a)
+ {
+-  int32x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
+-  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
+-  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v2sf (__a);
+ }
+ 
+-__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__))
+-vld3_dup_u8 (const uint8_t * __a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmvq_f32 (float32x4_t __a)
+ {
+-  uint8x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 0);
+-  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 1);
+-  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v4sf (__a);
+ }
+ 
+-__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__))
+-vld3_dup_u16 (const uint16_t * __a)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmvq_f64 (float64x2_t __a)
+ {
+-  uint16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 0);
+-  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 1);
+-  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi (__o, 2);
+-  return ret;
++  return __builtin_aarch64_reduc_smin_scal_v2df (__a);
+ }
+ 
+-__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__))
+-vld3_dup_u32 (const uint32_t * __a)
++/* vmla */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_f32 (float32x2_t a, float32x2_t b, float32x2_t c)
+ {
+-  uint32x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 0);
+-  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 1);
+-  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregciv2si (__o, 2);
+-  return ret;
++  return a + b * c;
+ }
+ 
+-__extension__ static __inline float16x4x3_t __attribute__ ((__always_inline__))
+-vld3_dup_f16 (const float16_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
+ {
+-  float16x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4hf ((const __builtin_aarch64_simd_hf *) __a);
+-  ret.val[0] = (float16x4_t) __builtin_aarch64_get_dregciv4hf (__o, 0);
+-  ret.val[1] = (float16x4_t) __builtin_aarch64_get_dregciv4hf (__o, 1);
+-  ret.val[2] = (float16x4_t) __builtin_aarch64_get_dregciv4hf (__o, 2);
+-  return ret;
++  return __a + __b * __c;
+ }
+ 
+-__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__))
+-vld3_dup_f32 (const float32_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)
+ {
+-  float32x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv2sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 0);
+-  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 1);
+-  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregciv2sf (__o, 2);
+-  return ret;
++  return a + b * c;
+ }
+ 
+-__extension__ static __inline int8x16x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_s8 (const int8_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)
+ {
+-  int8x16x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
+-  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
+-  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
+-  return ret;
++  return a + b * c;
+ }
+ 
+-__extension__ static __inline poly8x16x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_p8 (const poly8_t * __a)
++/* vmla_lane  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_lane_f32 (float32x2_t __a, float32x2_t __b,
++	       float32x2_t __c, const int __lane)
+ {
+-  poly8x16x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
+-  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
+-  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_s16 (const int16_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_lane_s16 (int16x4_t __a, int16x4_t __b,
++		int16x4_t __c, const int __lane)
+ {
+-  int16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
+-  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
+-  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline poly16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_p16 (const poly16_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_lane_s32 (int32x2_t __a, int32x2_t __b,
++		int32x2_t __c, const int __lane)
+ {
+-  poly16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
+-  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
+-  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int32x4x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_s32 (const int32_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_lane_u16 (uint16x4_t __a, uint16x4_t __b,
++		uint16x4_t __c, const int __lane)
+ {
+-  int32x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
+-  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
+-  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int64x2x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_s64 (const int64_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_lane_u32 (uint32x2_t __a, uint32x2_t __b,
++	       uint32x2_t __c, const int __lane)
+ {
+-  int64x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
+-  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
+-  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint8x16x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_u8 (const uint8_t * __a)
++/* vmla_laneq  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_laneq_f32 (float32x2_t __a, float32x2_t __b,
++	        float32x4_t __c, const int __lane)
+ {
+-  uint8x16x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 0);
+-  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 1);
+-  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_u16 (const uint16_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_laneq_s16 (int16x4_t __a, int16x4_t __b,
++		int16x8_t __c, const int __lane)
+ {
+-  uint16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 0);
+-  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 1);
+-  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint32x4x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_u32 (const uint32_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_laneq_s32 (int32x2_t __a, int32x2_t __b,
++		int32x4_t __c, const int __lane)
+ {
+-  uint32x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 0);
+-  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 1);
+-  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregciv4si (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint64x2x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_u64 (const uint64_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_laneq_u16 (uint16x4_t __a, uint16x4_t __b,
++		uint16x8_t __c, const int __lane)
+ {
+-  uint64x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 0);
+-  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 1);
+-  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregciv2di (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float16x8x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_f16 (const float16_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmla_laneq_u32 (uint32x2_t __a, uint32x2_t __b,
++		uint32x4_t __c, const int __lane)
+ {
+-  float16x8x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv8hf ((const __builtin_aarch64_simd_hf *) __a);
+-  ret.val[0] = (float16x8_t) __builtin_aarch64_get_qregciv8hf (__o, 0);
+-  ret.val[1] = (float16x8_t) __builtin_aarch64_get_qregciv8hf (__o, 1);
+-  ret.val[2] = (float16x8_t) __builtin_aarch64_get_qregciv8hf (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float32x4x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_f32 (const float32_t * __a)
++/* vmlaq_lane  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_lane_f32 (float32x4_t __a, float32x4_t __b,
++		float32x2_t __c, const int __lane)
+ {
+-  float32x4x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv4sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 0);
+-  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 1);
+-  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregciv4sf (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float64x2x3_t __attribute__ ((__always_inline__))
+-vld3q_dup_f64 (const float64_t * __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_lane_s16 (int16x8_t __a, int16x8_t __b,
++		int16x4_t __c, const int __lane)
+ {
+-  float64x2x3_t ret;
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_ld3rv2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 0);
+-  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 1);
+-  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregciv2df (__o, 2);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int64x1x4_t __attribute__ ((__always_inline__))
+-vld4_dup_s64 (const int64_t * __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_lane_s32 (int32x4_t __a, int32x4_t __b,
++		int32x2_t __c, const int __lane)
+ {
+-  int64x1x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rdi ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
+-  ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
+-  ret.val[2] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
+-  ret.val[3] = (int64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint64x1x4_t __attribute__ ((__always_inline__))
+-vld4_dup_u64 (const uint64_t * __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_lane_u16 (uint16x8_t __a, uint16x8_t __b,
++		uint16x4_t __c, const int __lane)
+ {
+-  uint64x1x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rdi ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 0);
+-  ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 1);
+-  ret.val[2] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 2);
+-  ret.val[3] = (uint64x1_t) __builtin_aarch64_get_dregxidi (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float64x1x4_t __attribute__ ((__always_inline__))
+-vld4_dup_f64 (const float64_t * __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_lane_u32 (uint32x4_t __a, uint32x4_t __b,
++		uint32x2_t __c, const int __lane)
+ {
+-  float64x1x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rdf ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 0)};
+-  ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 1)};
+-  ret.val[2] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 2)};
+-  ret.val[3] = (float64x1_t) {__builtin_aarch64_get_dregxidf (__o, 3)};
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__))
+-vld4_dup_s8 (const int8_t * __a)
++  /* vmlaq_laneq  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_laneq_f32 (float32x4_t __a, float32x4_t __b,
++		 float32x4_t __c, const int __lane)
+ {
+-  int8x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
+-  ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
+-  ret.val[2] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
+-  ret.val[3] = (int8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__))
+-vld4_dup_p8 (const poly8_t * __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_laneq_s16 (int16x8_t __a, int16x8_t __b,
++		int16x8_t __c, const int __lane)
+ {
+-  poly8x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
+-  ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
+-  ret.val[2] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
+-  ret.val[3] = (poly8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__))
+-vld4_dup_s16 (const int16_t * __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_laneq_s32 (int32x4_t __a, int32x4_t __b,
++		int32x4_t __c, const int __lane)
+ {
+-  int16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
+-  ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
+-  ret.val[2] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
+-  ret.val[3] = (int16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__))
+-vld4_dup_p16 (const poly16_t * __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_laneq_u16 (uint16x8_t __a, uint16x8_t __b,
++		uint16x8_t __c, const int __lane)
+ {
+-  poly16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
+-  ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
+-  ret.val[2] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
+-  ret.val[3] = (poly16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__))
+-vld4_dup_s32 (const int32_t * __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlaq_laneq_u32 (uint32x4_t __a, uint32x4_t __b,
++		uint32x4_t __c, const int __lane)
+ {
+-  int32x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
+-  ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
+-  ret.val[2] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
+-  ret.val[3] = (int32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
+-  return ret;
++  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__))
+-vld4_dup_u8 (const uint8_t * __a)
++/* vmls  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_f32 (float32x2_t a, float32x2_t b, float32x2_t c)
+ {
+-  uint8x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 0);
+-  ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 1);
+-  ret.val[2] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 2);
+-  ret.val[3] = (uint8x8_t) __builtin_aarch64_get_dregxiv8qi (__o, 3);
+-  return ret;
++  return a - b * c;
+ }
+ 
+-__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__))
+-vld4_dup_u16 (const uint16_t * __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
+ {
+-  uint16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 0);
+-  ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 1);
+-  ret.val[2] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 2);
+-  ret.val[3] = (uint16x4_t) __builtin_aarch64_get_dregxiv4hi (__o, 3);
+-  return ret;
++  return __a - __b * __c;
+ }
+ 
+-__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__))
+-vld4_dup_u32 (const uint32_t * __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)
+ {
+-  uint32x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv2si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 0);
+-  ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 1);
+-  ret.val[2] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 2);
+-  ret.val[3] = (uint32x2_t) __builtin_aarch64_get_dregxiv2si (__o, 3);
+-  return ret;
++  return a - b * c;
+ }
+ 
+-__extension__ static __inline float16x4x4_t __attribute__ ((__always_inline__))
+-vld4_dup_f16 (const float16_t * __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)
+ {
+-  float16x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4hf ((const __builtin_aarch64_simd_hf *) __a);
+-  ret.val[0] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 0);
+-  ret.val[1] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 1);
+-  ret.val[2] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 2);
+-  ret.val[3] = (float16x4_t) __builtin_aarch64_get_dregxiv4hf (__o, 3);
+-  return ret;
++  return a - b * c;
+ }
+ 
+-__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__))
+-vld4_dup_f32 (const float32_t * __a)
++/* vmls_lane  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_lane_f32 (float32x2_t __a, float32x2_t __b,
++	       float32x2_t __c, const int __lane)
+ {
+-  float32x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv2sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 0);
+-  ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 1);
+-  ret.val[2] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 2);
+-  ret.val[3] = (float32x2_t) __builtin_aarch64_get_dregxiv2sf (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int8x16x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_s8 (const int8_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_lane_s16 (int16x4_t __a, int16x4_t __b,
++		int16x4_t __c, const int __lane)
+ {
+-  int8x16x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
+-  ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
+-  ret.val[2] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
+-  ret.val[3] = (int8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline poly8x16x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_p8 (const poly8_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_lane_s32 (int32x2_t __a, int32x2_t __b,
++		int32x2_t __c, const int __lane)
+ {
+-  poly8x16x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
+-  ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
+-  ret.val[2] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
+-  ret.val[3] = (poly8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_s16 (const int16_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_lane_u16 (uint16x4_t __a, uint16x4_t __b,
++		uint16x4_t __c, const int __lane)
+ {
+-  int16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
+-  ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
+-  ret.val[2] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
+-  ret.val[3] = (int16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline poly16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_p16 (const poly16_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_lane_u32 (uint32x2_t __a, uint32x2_t __b,
++	       uint32x2_t __c, const int __lane)
+ {
+-  poly16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
+-  ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
+-  ret.val[2] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
+-  ret.val[3] = (poly16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int32x4x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_s32 (const int32_t * __a)
++/* vmls_laneq  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_laneq_f32 (float32x2_t __a, float32x2_t __b,
++	       float32x4_t __c, const int __lane)
+ {
+-  int32x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
+-  ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
+-  ret.val[2] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
+-  ret.val[3] = (int32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline int64x2x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_s64 (const int64_t * __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_laneq_s16 (int16x4_t __a, int16x4_t __b,
++		int16x8_t __c, const int __lane)
+ {
+-  int64x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
+-  ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
+-  ret.val[2] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
+-  ret.val[3] = (int64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint8x16x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_u8 (const uint8_t * __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_laneq_s32 (int32x2_t __a, int32x2_t __b,
++		int32x4_t __c, const int __lane)
+ {
+-  uint8x16x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv16qi ((const __builtin_aarch64_simd_qi *) __a);
+-  ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 0);
+-  ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 1);
+-  ret.val[2] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 2);
+-  ret.val[3] = (uint8x16_t) __builtin_aarch64_get_qregxiv16qi (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_u16 (const uint16_t * __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_laneq_u16 (uint16x4_t __a, uint16x4_t __b,
++		uint16x8_t __c, const int __lane)
+ {
+-  uint16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8hi ((const __builtin_aarch64_simd_hi *) __a);
+-  ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 0);
+-  ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 1);
+-  ret.val[2] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 2);
+-  ret.val[3] = (uint16x8_t) __builtin_aarch64_get_qregxiv8hi (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint32x4x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_u32 (const uint32_t * __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmls_laneq_u32 (uint32x2_t __a, uint32x2_t __b,
++		uint32x4_t __c, const int __lane)
+ {
+-  uint32x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4si ((const __builtin_aarch64_simd_si *) __a);
+-  ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 0);
+-  ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 1);
+-  ret.val[2] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 2);
+-  ret.val[3] = (uint32x4_t) __builtin_aarch64_get_qregxiv4si (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline uint64x2x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_u64 (const uint64_t * __a)
++/* vmlsq_lane  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_lane_f32 (float32x4_t __a, float32x4_t __b,
++		float32x2_t __c, const int __lane)
+ {
+-  uint64x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv2di ((const __builtin_aarch64_simd_di *) __a);
+-  ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 0);
+-  ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 1);
+-  ret.val[2] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 2);
+-  ret.val[3] = (uint64x2_t) __builtin_aarch64_get_qregxiv2di (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float16x8x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_f16 (const float16_t * __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_lane_s16 (int16x8_t __a, int16x8_t __b,
++		int16x4_t __c, const int __lane)
+ {
+-  float16x8x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv8hf ((const __builtin_aarch64_simd_hf *) __a);
+-  ret.val[0] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 0);
+-  ret.val[1] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 1);
+-  ret.val[2] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 2);
+-  ret.val[3] = (float16x8_t) __builtin_aarch64_get_qregxiv8hf (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float32x4x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_f32 (const float32_t * __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_lane_s32 (int32x4_t __a, int32x4_t __b,
++		int32x2_t __c, const int __lane)
+ {
+-  float32x4x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv4sf ((const __builtin_aarch64_simd_sf *) __a);
+-  ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 0);
+-  ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 1);
+-  ret.val[2] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 2);
+-  ret.val[3] = (float32x4_t) __builtin_aarch64_get_qregxiv4sf (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__extension__ static __inline float64x2x4_t __attribute__ ((__always_inline__))
+-vld4q_dup_f64 (const float64_t * __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_lane_u16 (uint16x8_t __a, uint16x8_t __b,
++		uint16x4_t __c, const int __lane)
+ {
+-  float64x2x4_t ret;
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_ld4rv2df ((const __builtin_aarch64_simd_df *) __a);
+-  ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 0);
+-  ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 1);
+-  ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 2);
+-  ret.val[3] = (float64x2_t) __builtin_aarch64_get_qregxiv2df (__o, 3);
+-  return ret;
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-/* vld2_lane */
+-
+-#define __LD2_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
+-			 qmode, ptrmode, funcsuffix, signedtype)	   \
+-__extension__ static __inline intype __attribute__ ((__always_inline__))   \
+-vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
+-{									   \
+-  __builtin_aarch64_simd_oi __o;					   \
+-  largetype __temp;							   \
+-  __temp.val[0] =							   \
+-    vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0));	   \
+-  __temp.val[1] =							   \
+-    vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
+-  __o = __builtin_aarch64_set_qregoi##qmode (__o,			   \
+-					    (signedtype) __temp.val[0],	   \
+-					    0);				   \
+-  __o = __builtin_aarch64_set_qregoi##qmode (__o,			   \
+-					    (signedtype) __temp.val[1],	   \
+-					    1);				   \
+-  __o =	__builtin_aarch64_ld2_lane##mode (				   \
+-	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
+-  __b.val[0] = (vectype) __builtin_aarch64_get_dregoidi (__o, 0);	   \
+-  __b.val[1] = (vectype) __builtin_aarch64_get_dregoidi (__o, 1);	   \
+-  return __b;								   \
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_lane_u32 (uint32x4_t __a, uint32x4_t __b,
++		uint32x2_t __c, const int __lane)
++{
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__LD2_LANE_FUNC (float16x4x2_t, float16x4_t, float16x8x2_t, float16_t, v4hf,
+-		 v8hf, hf, f16, float16x8_t)
+-__LD2_LANE_FUNC (float32x2x2_t, float32x2_t, float32x4x2_t, float32_t, v2sf, v4sf,
+-		 sf, f32, float32x4_t)
+-__LD2_LANE_FUNC (float64x1x2_t, float64x1_t, float64x2x2_t, float64_t, df, v2df,
+-		 df, f64, float64x2_t)
+-__LD2_LANE_FUNC (poly8x8x2_t, poly8x8_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8,
+-		 int8x16_t)
+-__LD2_LANE_FUNC (poly16x4x2_t, poly16x4_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi,
+-		 p16, int16x8_t)
+-__LD2_LANE_FUNC (int8x8x2_t, int8x8_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8,
+-		 int8x16_t)
+-__LD2_LANE_FUNC (int16x4x2_t, int16x4_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16,
+-		 int16x8_t)
+-__LD2_LANE_FUNC (int32x2x2_t, int32x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32,
+-		 int32x4_t)
+-__LD2_LANE_FUNC (int64x1x2_t, int64x1_t, int64x2x2_t, int64_t, di, v2di, di, s64,
+-		 int64x2_t)
+-__LD2_LANE_FUNC (uint8x8x2_t, uint8x8_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8,
+-		 int8x16_t)
+-__LD2_LANE_FUNC (uint16x4x2_t, uint16x4_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi,
+-		 u16, int16x8_t)
+-__LD2_LANE_FUNC (uint32x2x2_t, uint32x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si,
+-		 u32, int32x4_t)
+-__LD2_LANE_FUNC (uint64x1x2_t, uint64x1_t, uint64x2x2_t, uint64_t, di, v2di, di,
+-		 u64, int64x2_t)
++  /* vmlsq_laneq  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_laneq_f32 (float32x4_t __a, float32x4_t __b,
++		float32x4_t __c, const int __lane)
++{
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++}
+ 
+-#undef __LD2_LANE_FUNC
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_laneq_s16 (int16x8_t __a, int16x8_t __b,
++		int16x8_t __c, const int __lane)
++{
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++}
+ 
+-/* vld2q_lane */
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_laneq_s32 (int32x4_t __a, int32x4_t __b,
++		int32x4_t __c, const int __lane)
++{
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++}
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_laneq_u16 (uint16x8_t __a, uint16x8_t __b,
++		uint16x8_t __c, const int __lane)
++{
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++}
+ 
+-#define __LD2_LANE_FUNC(intype, vtype, ptrtype, mode, ptrmode, funcsuffix) \
+-__extension__ static __inline intype __attribute__ ((__always_inline__))   \
+-vld2q_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \
+-{									   \
+-  __builtin_aarch64_simd_oi __o;					   \
+-  intype ret;								   \
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) __b.val[0], 0); \
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) __b.val[1], 1); \
+-  __o = __builtin_aarch64_ld2_lane##mode (				   \
+-	(__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);		   \
+-  ret.val[0] = (vtype) __builtin_aarch64_get_qregoiv4si (__o, 0);	   \
+-  ret.val[1] = (vtype) __builtin_aarch64_get_qregoiv4si (__o, 1);	   \
+-  return ret;								   \
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmlsq_laneq_u32 (uint32x4_t __a, uint32x4_t __b,
++		uint32x4_t __c, const int __lane)
++{
++  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
+ }
+ 
+-__LD2_LANE_FUNC (float16x8x2_t, float16x8_t, float16_t, v8hf, hf, f16)
+-__LD2_LANE_FUNC (float32x4x2_t, float32x4_t, float32_t, v4sf, sf, f32)
+-__LD2_LANE_FUNC (float64x2x2_t, float64x2_t, float64_t, v2df, df, f64)
+-__LD2_LANE_FUNC (poly8x16x2_t, poly8x16_t, poly8_t, v16qi, qi, p8)
+-__LD2_LANE_FUNC (poly16x8x2_t, poly16x8_t, poly16_t, v8hi, hi, p16)
+-__LD2_LANE_FUNC (int8x16x2_t, int8x16_t, int8_t, v16qi, qi, s8)
+-__LD2_LANE_FUNC (int16x8x2_t, int16x8_t, int16_t, v8hi, hi, s16)
+-__LD2_LANE_FUNC (int32x4x2_t, int32x4_t, int32_t, v4si, si, s32)
+-__LD2_LANE_FUNC (int64x2x2_t, int64x2_t, int64_t, v2di, di, s64)
+-__LD2_LANE_FUNC (uint8x16x2_t, uint8x16_t, uint8_t, v16qi, qi, u8)
+-__LD2_LANE_FUNC (uint16x8x2_t, uint16x8_t, uint16_t, v8hi, hi, u16)
+-__LD2_LANE_FUNC (uint32x4x2_t, uint32x4_t, uint32_t, v4si, si, u32)
+-__LD2_LANE_FUNC (uint64x2x2_t, uint64x2_t, uint64_t, v2di, di, u64)
++/* vmov_n_  */
+ 
+-#undef __LD2_LANE_FUNC
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_f16 (float16_t __a)
++{
++  return vdup_n_f16 (__a);
++}
+ 
+-/* vld3_lane */
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_f32 (float32_t __a)
++{
++  return vdup_n_f32 (__a);
++}
+ 
+-#define __LD3_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
+-			 qmode, ptrmode, funcsuffix, signedtype)	   \
+-__extension__ static __inline intype __attribute__ ((__always_inline__))   \
+-vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
+-{									   \
+-  __builtin_aarch64_simd_ci __o;					   \
+-  largetype __temp;							   \
+-  __temp.val[0] =							   \
+-    vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0));	   \
+-  __temp.val[1] =							   \
+-    vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
+-  __temp.val[2] =							   \
+-    vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0));	   \
+-  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
+-					    (signedtype) __temp.val[0],	   \
+-					    0);				   \
+-  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
+-					    (signedtype) __temp.val[1],	   \
+-					    1);				   \
+-  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
+-					    (signedtype) __temp.val[2],	   \
+-					    2);				   \
+-  __o =	__builtin_aarch64_ld3_lane##mode (				   \
+-	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
+-  __b.val[0] = (vectype) __builtin_aarch64_get_dregcidi (__o, 0);	   \
+-  __b.val[1] = (vectype) __builtin_aarch64_get_dregcidi (__o, 1);	   \
+-  __b.val[2] = (vectype) __builtin_aarch64_get_dregcidi (__o, 2);	   \
+-  return __b;								   \
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_f64 (float64_t __a)
++{
++  return (float64x1_t) {__a};
+ }
+ 
+-__LD3_LANE_FUNC (float16x4x3_t, float16x4_t, float16x8x3_t, float16_t, v4hf,
+-		 v8hf, hf, f16, float16x8_t)
+-__LD3_LANE_FUNC (float32x2x3_t, float32x2_t, float32x4x3_t, float32_t, v2sf, v4sf,
+-		 sf, f32, float32x4_t)
+-__LD3_LANE_FUNC (float64x1x3_t, float64x1_t, float64x2x3_t, float64_t, df, v2df,
+-		 df, f64, float64x2_t)
+-__LD3_LANE_FUNC (poly8x8x3_t, poly8x8_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8,
+-		 int8x16_t)
+-__LD3_LANE_FUNC (poly16x4x3_t, poly16x4_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi,
+-		 p16, int16x8_t)
+-__LD3_LANE_FUNC (int8x8x3_t, int8x8_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8,
+-		 int8x16_t)
+-__LD3_LANE_FUNC (int16x4x3_t, int16x4_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16,
+-		 int16x8_t)
+-__LD3_LANE_FUNC (int32x2x3_t, int32x2_t, int32x4x3_t, int32_t, v2si, v4si, si, s32,
+-		 int32x4_t)
+-__LD3_LANE_FUNC (int64x1x3_t, int64x1_t, int64x2x3_t, int64_t, di, v2di, di, s64,
+-		 int64x2_t)
+-__LD3_LANE_FUNC (uint8x8x3_t, uint8x8_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8,
+-		 int8x16_t)
+-__LD3_LANE_FUNC (uint16x4x3_t, uint16x4_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi,
+-		 u16, int16x8_t)
+-__LD3_LANE_FUNC (uint32x2x3_t, uint32x2_t, uint32x4x3_t, uint32_t, v2si, v4si, si,
+-		 u32, int32x4_t)
+-__LD3_LANE_FUNC (uint64x1x3_t, uint64x1_t, uint64x2x3_t, uint64_t, di, v2di, di,
+-		 u64, int64x2_t)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_p8 (poly8_t __a)
++{
++  return vdup_n_p8 (__a);
++}
+ 
+-#undef __LD3_LANE_FUNC
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_p16 (poly16_t __a)
++{
++  return vdup_n_p16 (__a);
++}
+ 
+-/* vld3q_lane */
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_p64 (poly64_t __a)
++{
++  return vdup_n_p64 (__a);
++}
+ 
+-#define __LD3_LANE_FUNC(intype, vtype, ptrtype, mode, ptrmode, funcsuffix) \
+-__extension__ static __inline intype __attribute__ ((__always_inline__))   \
+-vld3q_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \
+-{									   \
+-  __builtin_aarch64_simd_ci __o;					   \
+-  intype ret;								   \
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) __b.val[0], 0); \
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) __b.val[1], 1); \
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) __b.val[2], 2); \
+-  __o = __builtin_aarch64_ld3_lane##mode (				   \
+-	(__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);		   \
+-  ret.val[0] = (vtype) __builtin_aarch64_get_qregciv4si (__o, 0);	   \
+-  ret.val[1] = (vtype) __builtin_aarch64_get_qregciv4si (__o, 1);	   \
+-  ret.val[2] = (vtype) __builtin_aarch64_get_qregciv4si (__o, 2);	   \
+-  return ret;								   \
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_s8 (int8_t __a)
++{
++  return vdup_n_s8 (__a);
+ }
+ 
+-__LD3_LANE_FUNC (float16x8x3_t, float16x8_t, float16_t, v8hf, hf, f16)
+-__LD3_LANE_FUNC (float32x4x3_t, float32x4_t, float32_t, v4sf, sf, f32)
+-__LD3_LANE_FUNC (float64x2x3_t, float64x2_t, float64_t, v2df, df, f64)
+-__LD3_LANE_FUNC (poly8x16x3_t, poly8x16_t, poly8_t, v16qi, qi, p8)
+-__LD3_LANE_FUNC (poly16x8x3_t, poly16x8_t, poly16_t, v8hi, hi, p16)
+-__LD3_LANE_FUNC (int8x16x3_t, int8x16_t, int8_t, v16qi, qi, s8)
+-__LD3_LANE_FUNC (int16x8x3_t, int16x8_t, int16_t, v8hi, hi, s16)
+-__LD3_LANE_FUNC (int32x4x3_t, int32x4_t, int32_t, v4si, si, s32)
+-__LD3_LANE_FUNC (int64x2x3_t, int64x2_t, int64_t, v2di, di, s64)
+-__LD3_LANE_FUNC (uint8x16x3_t, uint8x16_t, uint8_t, v16qi, qi, u8)
+-__LD3_LANE_FUNC (uint16x8x3_t, uint16x8_t, uint16_t, v8hi, hi, u16)
+-__LD3_LANE_FUNC (uint32x4x3_t, uint32x4_t, uint32_t, v4si, si, u32)
+-__LD3_LANE_FUNC (uint64x2x3_t, uint64x2_t, uint64_t, v2di, di, u64)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_s16 (int16_t __a)
++{
++  return vdup_n_s16 (__a);
++}
+ 
+-#undef __LD3_LANE_FUNC
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_s32 (int32_t __a)
++{
++  return vdup_n_s32 (__a);
++}
+ 
+-/* vld4_lane */
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_s64 (int64_t __a)
++{
++  return (int64x1_t) {__a};
++}
+ 
+-#define __LD4_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
+-			 qmode, ptrmode, funcsuffix, signedtype)	   \
+-__extension__ static __inline intype __attribute__ ((__always_inline__))   \
+-vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
+-{									   \
+-  __builtin_aarch64_simd_xi __o;					   \
+-  largetype __temp;							   \
+-  __temp.val[0] =							   \
+-    vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0));	   \
+-  __temp.val[1] =							   \
+-    vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
+-  __temp.val[2] =							   \
+-    vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0));	   \
+-  __temp.val[3] =							   \
+-    vcombine_##funcsuffix (__b.val[3], vcreate_##funcsuffix (0));	   \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
+-					    (signedtype) __temp.val[0],	   \
+-					    0);				   \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
+-					    (signedtype) __temp.val[1],	   \
+-					    1);				   \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
+-					    (signedtype) __temp.val[2],	   \
+-					    2);				   \
+-  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
+-					    (signedtype) __temp.val[3],	   \
+-					    3);				   \
+-  __o =	__builtin_aarch64_ld4_lane##mode (				   \
+-	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
+-  __b.val[0] = (vectype) __builtin_aarch64_get_dregxidi (__o, 0);	   \
+-  __b.val[1] = (vectype) __builtin_aarch64_get_dregxidi (__o, 1);	   \
+-  __b.val[2] = (vectype) __builtin_aarch64_get_dregxidi (__o, 2);	   \
+-  __b.val[3] = (vectype) __builtin_aarch64_get_dregxidi (__o, 3);	   \
+-  return __b;								   \
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_u8 (uint8_t __a)
++{
++  return vdup_n_u8 (__a);
+ }
+ 
+-/* vld4q_lane */
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_u16 (uint16_t __a)
++{
++    return vdup_n_u16 (__a);
++}
+ 
+-__LD4_LANE_FUNC (float16x4x4_t, float16x4_t, float16x8x4_t, float16_t, v4hf,
+-		 v8hf, hf, f16, float16x8_t)
+-__LD4_LANE_FUNC (float32x2x4_t, float32x2_t, float32x4x4_t, float32_t, v2sf, v4sf,
+-		 sf, f32, float32x4_t)
+-__LD4_LANE_FUNC (float64x1x4_t, float64x1_t, float64x2x4_t, float64_t, df, v2df,
+-		 df, f64, float64x2_t)
+-__LD4_LANE_FUNC (poly8x8x4_t, poly8x8_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8,
+-		 int8x16_t)
+-__LD4_LANE_FUNC (poly16x4x4_t, poly16x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi,
+-		 p16, int16x8_t)
+-__LD4_LANE_FUNC (int8x8x4_t, int8x8_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8,
+-		 int8x16_t)
+-__LD4_LANE_FUNC (int16x4x4_t, int16x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16,
+-		 int16x8_t)
+-__LD4_LANE_FUNC (int32x2x4_t, int32x2_t, int32x4x4_t, int32_t, v2si, v4si, si, s32,
+-		 int32x4_t)
+-__LD4_LANE_FUNC (int64x1x4_t, int64x1_t, int64x2x4_t, int64_t, di, v2di, di, s64,
+-		 int64x2_t)
+-__LD4_LANE_FUNC (uint8x8x4_t, uint8x8_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8,
+-		 int8x16_t)
+-__LD4_LANE_FUNC (uint16x4x4_t, uint16x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi,
+-		 u16, int16x8_t)
+-__LD4_LANE_FUNC (uint32x2x4_t, uint32x2_t, uint32x4x4_t, uint32_t, v2si, v4si, si,
+-		 u32, int32x4_t)
+-__LD4_LANE_FUNC (uint64x1x4_t, uint64x1_t, uint64x2x4_t, uint64_t, di, v2di, di,
+-		 u64, int64x2_t)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_u32 (uint32_t __a)
++{
++   return vdup_n_u32 (__a);
++}
++
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_u64 (uint64_t __a)
++{
++  return (uint64x1_t) {__a};
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_f16 (float16_t __a)
++{
++  return vdupq_n_f16 (__a);
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_f32 (float32_t __a)
++{
++  return vdupq_n_f32 (__a);
++}
++
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_f64 (float64_t __a)
++{
++  return vdupq_n_f64 (__a);
++}
+ 
+-#undef __LD4_LANE_FUNC
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_p8 (poly8_t __a)
++{
++  return vdupq_n_p8 (__a);
++}
+ 
+-/* vld4q_lane */
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_p16 (poly16_t __a)
++{
++  return vdupq_n_p16 (__a);
++}
+ 
+-#define __LD4_LANE_FUNC(intype, vtype, ptrtype, mode, ptrmode, funcsuffix) \
+-__extension__ static __inline intype __attribute__ ((__always_inline__))   \
+-vld4q_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \
+-{									   \
+-  __builtin_aarch64_simd_xi __o;					   \
+-  intype ret;								   \
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[0], 0); \
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[1], 1); \
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[2], 2); \
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[3], 3); \
+-  __o = __builtin_aarch64_ld4_lane##mode (				   \
+-	(__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);		   \
+-  ret.val[0] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 0);	   \
+-  ret.val[1] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 1);	   \
+-  ret.val[2] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 2);	   \
+-  ret.val[3] = (vtype) __builtin_aarch64_get_qregxiv4si (__o, 3);	   \
+-  return ret;								   \
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_p64 (poly64_t __a)
++{
++  return vdupq_n_p64 (__a);
+ }
+ 
+-__LD4_LANE_FUNC (float16x8x4_t, float16x8_t, float16_t, v8hf, hf, f16)
+-__LD4_LANE_FUNC (float32x4x4_t, float32x4_t, float32_t, v4sf, sf, f32)
+-__LD4_LANE_FUNC (float64x2x4_t, float64x2_t, float64_t, v2df, df, f64)
+-__LD4_LANE_FUNC (poly8x16x4_t, poly8x16_t, poly8_t, v16qi, qi, p8)
+-__LD4_LANE_FUNC (poly16x8x4_t, poly16x8_t, poly16_t, v8hi, hi, p16)
+-__LD4_LANE_FUNC (int8x16x4_t, int8x16_t, int8_t, v16qi, qi, s8)
+-__LD4_LANE_FUNC (int16x8x4_t, int16x8_t, int16_t, v8hi, hi, s16)
+-__LD4_LANE_FUNC (int32x4x4_t, int32x4_t, int32_t, v4si, si, s32)
+-__LD4_LANE_FUNC (int64x2x4_t, int64x2_t, int64_t, v2di, di, s64)
+-__LD4_LANE_FUNC (uint8x16x4_t, uint8x16_t, uint8_t, v16qi, qi, u8)
+-__LD4_LANE_FUNC (uint16x8x4_t, uint16x8_t, uint16_t, v8hi, hi, u16)
+-__LD4_LANE_FUNC (uint32x4x4_t, uint32x4_t, uint32_t, v4si, si, u32)
+-__LD4_LANE_FUNC (uint64x2x4_t, uint64x2_t, uint64_t, v2di, di, u64)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_s8 (int8_t __a)
++{
++  return vdupq_n_s8 (__a);
++}
+ 
+-#undef __LD4_LANE_FUNC
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_s16 (int16_t __a)
++{
++  return vdupq_n_s16 (__a);
++}
+ 
+-/* vmax */
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_s32 (int32_t __a)
++{
++  return vdupq_n_s32 (__a);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmax_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_s64 (int64_t __a)
+ {
+-  return __builtin_aarch64_smax_nanv2sf (__a, __b);
++  return vdupq_n_s64 (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmax_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_u8 (uint8_t __a)
+ {
+-  return __builtin_aarch64_smaxv8qi (__a, __b);
++  return vdupq_n_u8 (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmax_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_u16 (uint16_t __a)
+ {
+-  return __builtin_aarch64_smaxv4hi (__a, __b);
++  return vdupq_n_u16 (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmax_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_u32 (uint32_t __a)
+ {
+-  return __builtin_aarch64_smaxv2si (__a, __b);
++  return vdupq_n_u32 (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmax_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_u64 (uint64_t __a)
+ {
+-  return (uint8x8_t) __builtin_aarch64_umaxv8qi ((int8x8_t) __a,
+-						 (int8x8_t) __b);
++  return vdupq_n_u64 (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmax_u16 (uint16x4_t __a, uint16x4_t __b)
++/* vmul_lane  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_f32 (float32x2_t __a, float32x2_t __b, const int __lane)
+ {
+-  return (uint16x4_t) __builtin_aarch64_umaxv4hi ((int16x4_t) __a,
+-						  (int16x4_t) __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmax_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_f64 (float64x1_t __a, float64x1_t __b, const int __lane)
+ {
+-  return (uint32x2_t) __builtin_aarch64_umaxv2si ((int32x2_t) __a,
+-						  (int32x2_t) __b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmaxq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_s16 (int16x4_t __a, int16x4_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_smax_nanv4sf (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmaxq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_s32 (int32x2_t __a, int32x2_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_smax_nanv2df (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vmaxq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_u16 (uint16x4_t __a, uint16x4_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_smaxv16qi (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmaxq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_u32 (uint32x2_t __a, uint32x2_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_smaxv8hi (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmaxq_s32 (int32x4_t __a, int32x4_t __b)
++/* vmuld_lane  */
++
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmuld_lane_f64 (float64_t __a, float64x1_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_smaxv4si (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vmaxq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmuld_laneq_f64 (float64_t __a, float64x2_t __b, const int __lane)
+ {
+-  return (uint8x16_t) __builtin_aarch64_umaxv16qi ((int8x16_t) __a,
+-						   (int8x16_t) __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmaxq_u16 (uint16x8_t __a, uint16x8_t __b)
++/* vmuls_lane  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmuls_lane_f32 (float32_t __a, float32x2_t __b, const int __lane)
+ {
+-  return (uint16x8_t) __builtin_aarch64_umaxv8hi ((int16x8_t) __a,
+-						  (int16x8_t) __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmaxq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmuls_laneq_f32 (float32_t __a, float32x4_t __b, const int __lane)
+ {
+-  return (uint32x4_t) __builtin_aarch64_umaxv4si ((int32x4_t) __a,
+-						  (int32x4_t) __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+-/* vmulx */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmulx_f32 (float32x2_t __a, float32x2_t __b)
++/* vmul_laneq  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_f32 (float32x2_t __a, float32x4_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_fmulxv2sf (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmulxq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_f64 (float64x1_t __a, float64x2_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_fmulxv4sf (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmulx_f64 (float64x1_t __a, float64x1_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __lane)
+ {
+-  return (float64x1_t) {__builtin_aarch64_fmulxdf (__a[0], __b[0])};
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmulxq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_fmulxv2df (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmulxs_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_u16 (uint16x4_t __a, uint16x8_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_fmulxsf (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmulxd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_u32 (uint32x2_t __a, uint32x4_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_fmulxdf (__a, __b);
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmulx_lane_f32 (float32x2_t __a, float32x2_t __v, const int __lane)
++/* vmul_n  */
++
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_f64  (float64x1_t __a, float64_t __b)
+ {
+-  return vmulx_f32 (__a, __aarch64_vdup_lane_f32 (__v, __lane));
++  return (float64x1_t) { vget_lane_f64 (__a, 0) * __b };
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmulx_lane_f64 (float64x1_t __a, float64x1_t __v, const int __lane)
++/* vmulq_lane  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_f32 (float32x4_t __a, float32x2_t __b, const int __lane)
+ {
+-  return vmulx_f64 (__a, __aarch64_vdup_lane_f64 (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmulxq_lane_f32 (float32x4_t __a, float32x2_t __v, const int __lane)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_f64 (float64x2_t __a, float64x1_t __b, const int __lane)
+ {
+-  return vmulxq_f32 (__a, __aarch64_vdupq_lane_f32 (__v, __lane));
++  __AARCH64_LANE_CHECK (__a, __lane);
++  return __a * __b[0];
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmulxq_lane_f64 (float64x2_t __a, float64x1_t __v, const int __lane)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __lane)
+ {
+-  return vmulxq_f64 (__a, __aarch64_vdupq_lane_f64 (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmulx_laneq_f32 (float32x2_t __a, float32x4_t __v, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __lane)
+ {
+-  return vmulx_f32 (__a, __aarch64_vdup_laneq_f32 (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmulx_laneq_f64 (float64x1_t __a, float64x2_t __v, const int __lane)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_u16 (uint16x8_t __a, uint16x4_t __b, const int __lane)
+ {
+-  return vmulx_f64 (__a, __aarch64_vdup_laneq_f64 (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmulxq_laneq_f32 (float32x4_t __a, float32x4_t __v, const int __lane)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_u32 (uint32x4_t __a, uint32x2_t __b, const int __lane)
+ {
+-  return vmulxq_f32 (__a, __aarch64_vdupq_laneq_f32 (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmulxq_laneq_f64 (float64x2_t __a, float64x2_t __v, const int __lane)
++/* vmulq_laneq  */
++
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_f32 (float32x4_t __a, float32x4_t __b, const int __lane)
+ {
+-  return vmulxq_f64 (__a, __aarch64_vdupq_laneq_f64 (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmulxs_lane_f32 (float32_t __a, float32x2_t __v, const int __lane)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_f64 (float64x2_t __a, float64x2_t __b, const int __lane)
+ {
+-  return vmulxs_f32 (__a, __aarch64_vget_lane_any (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmulxs_laneq_f32 (float32_t __a, float32x4_t __v, const int __lane)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __lane)
+ {
+-  return vmulxs_f32 (__a, __aarch64_vget_lane_any (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmulxd_lane_f64 (float64_t __a, float64x1_t __v, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __lane)
+ {
+-  return vmulxd_f64 (__a, __aarch64_vget_lane_any (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmulxd_laneq_f64 (float64_t __a, float64x2_t __v, const int __lane)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_u16 (uint16x8_t __a, uint16x8_t __b, const int __lane)
+ {
+-  return vmulxd_f64 (__a, __aarch64_vget_lane_any (__v, __lane));
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-/* vpmax  */
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_u32 (uint32x4_t __a, uint32x4_t __b, const int __lane)
++{
++  return __a * __aarch64_vget_lane_any (__b, __lane);
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vpmax_s8 (int8x8_t a, int8x8_t b)
++/* vmul_n.  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_f32 (float32x2_t __a, float32_t __b)
+ {
+-  return __builtin_aarch64_smaxpv8qi (a, b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vpmax_s16 (int16x4_t a, int16x4_t b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_f32 (float32x4_t __a, float32_t __b)
+ {
+-  return __builtin_aarch64_smaxpv4hi (a, b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vpmax_s32 (int32x2_t a, int32x2_t b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_f64 (float64x2_t __a, float64_t __b)
+ {
+-  return __builtin_aarch64_smaxpv2si (a, b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vpmax_u8 (uint8x8_t a, uint8x8_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_s16 (int16x4_t __a, int16_t __b)
+ {
+-  return (uint8x8_t) __builtin_aarch64_umaxpv8qi ((int8x8_t) a,
+-						  (int8x8_t) b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vpmax_u16 (uint16x4_t a, uint16x4_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_s16 (int16x8_t __a, int16_t __b)
+ {
+-  return (uint16x4_t) __builtin_aarch64_umaxpv4hi ((int16x4_t) a,
+-						   (int16x4_t) b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vpmax_u32 (uint32x2_t a, uint32x2_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_s32 (int32x2_t __a, int32_t __b)
+ {
+-  return (uint32x2_t) __builtin_aarch64_umaxpv2si ((int32x2_t) a,
+-						   (int32x2_t) b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vpmaxq_s8 (int8x16_t a, int8x16_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_s32 (int32x4_t __a, int32_t __b)
+ {
+-  return __builtin_aarch64_smaxpv16qi (a, b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vpmaxq_s16 (int16x8_t a, int16x8_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_u16 (uint16x4_t __a, uint16_t __b)
+ {
+-  return __builtin_aarch64_smaxpv8hi (a, b);
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vpmaxq_s32 (int32x4_t a, int32x4_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_u16 (uint16x8_t __a, uint16_t __b)
++{
++  return __a * __b;
++}
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_u32 (uint32x2_t __a, uint32_t __b)
++{
++  return __a * __b;
++}
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_u32 (uint32x4_t __a, uint32_t __b)
++{
++  return __a * __b;
++}
++
++/* vmvn  */
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_p8 (poly8x8_t __a)
+ {
+-  return __builtin_aarch64_smaxpv4si (a, b);
++  return (poly8x8_t) ~((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vpmaxq_u8 (uint8x16_t a, uint8x16_t b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_s8 (int8x8_t __a)
+ {
+-  return (uint8x16_t) __builtin_aarch64_umaxpv16qi ((int8x16_t) a,
+-						    (int8x16_t) b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vpmaxq_u16 (uint16x8_t a, uint16x8_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_s16 (int16x4_t __a)
+ {
+-  return (uint16x8_t) __builtin_aarch64_umaxpv8hi ((int16x8_t) a,
+-						   (int16x8_t) b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vpmaxq_u32 (uint32x4_t a, uint32x4_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_s32 (int32x2_t __a)
+ {
+-  return (uint32x4_t) __builtin_aarch64_umaxpv4si ((int32x4_t) a,
+-						   (int32x4_t) b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vpmax_f32 (float32x2_t a, float32x2_t b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_u8 (uint8x8_t __a)
+ {
+-  return __builtin_aarch64_smax_nanpv2sf (a, b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vpmaxq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_u16 (uint16x4_t __a)
+ {
+-  return __builtin_aarch64_smax_nanpv4sf (a, b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vpmaxq_f64 (float64x2_t a, float64x2_t b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvn_u32 (uint32x2_t __a)
+ {
+-  return __builtin_aarch64_smax_nanpv2df (a, b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vpmaxqd_f64 (float64x2_t a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_p8 (poly8x16_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_nan_scal_v2df (a);
++  return (poly8x16_t) ~((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vpmaxs_f32 (float32x2_t a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_s8 (int8x16_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_nan_scal_v2sf (a);
++  return ~__a;
+ }
+ 
+-/* vpmaxnm  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vpmaxnm_f32 (float32x2_t a, float32x2_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_s16 (int16x8_t __a)
+ {
+-  return __builtin_aarch64_smaxpv2sf (a, b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vpmaxnmq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_s32 (int32x4_t __a)
+ {
+-  return __builtin_aarch64_smaxpv4sf (a, b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vpmaxnmq_f64 (float64x2_t a, float64x2_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_u8 (uint8x16_t __a)
+ {
+-  return __builtin_aarch64_smaxpv2df (a, b);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vpmaxnmqd_f64 (float64x2_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_u16 (uint16x8_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v2df (a);
++  return ~__a;
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vpmaxnms_f32 (float32x2_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmvnq_u32 (uint32x4_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v2sf (a);
++  return ~__a;
+ }
+ 
+-/* vpmin  */
++/* vneg  */
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vpmin_s8 (int8x8_t a, int8x8_t b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_sminpv8qi (a, b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vpmin_s16 (int16x4_t a, int16x4_t b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_sminpv4hi (a, b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vpmin_s32 (int32x2_t a, int32x2_t b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_s8 (int8x8_t __a)
+ {
+-  return __builtin_aarch64_sminpv2si (a, b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vpmin_u8 (uint8x8_t a, uint8x8_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_s16 (int16x4_t __a)
+ {
+-  return (uint8x8_t) __builtin_aarch64_uminpv8qi ((int8x8_t) a,
+-						  (int8x8_t) b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vpmin_u16 (uint16x4_t a, uint16x4_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_s32 (int32x2_t __a)
+ {
+-  return (uint16x4_t) __builtin_aarch64_uminpv4hi ((int16x4_t) a,
+-						   (int16x4_t) b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vpmin_u32 (uint32x2_t a, uint32x2_t b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_s64 (int64x1_t __a)
+ {
+-  return (uint32x2_t) __builtin_aarch64_uminpv2si ((int32x2_t) a,
+-						   (int32x2_t) b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vpminq_s8 (int8x16_t a, int8x16_t b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_sminpv16qi (a, b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vpminq_s16 (int16x8_t a, int16x8_t b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_sminpv8hi (a, b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vpminq_s32 (int32x4_t a, int32x4_t b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_s8 (int8x16_t __a)
+ {
+-  return __builtin_aarch64_sminpv4si (a, b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vpminq_u8 (uint8x16_t a, uint8x16_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_s16 (int16x8_t __a)
+ {
+-  return (uint8x16_t) __builtin_aarch64_uminpv16qi ((int8x16_t) a,
+-						    (int8x16_t) b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vpminq_u16 (uint16x8_t a, uint16x8_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_s32 (int32x4_t __a)
+ {
+-  return (uint16x8_t) __builtin_aarch64_uminpv8hi ((int16x8_t) a,
+-						   (int16x8_t) b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vpminq_u32 (uint32x4_t a, uint32x4_t b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_s64 (int64x2_t __a)
+ {
+-  return (uint32x4_t) __builtin_aarch64_uminpv4si ((int32x4_t) a,
+-						   (int32x4_t) b);
++  return -__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vpmin_f32 (float32x2_t a, float32x2_t b)
++/* vpadd  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return __builtin_aarch64_smin_nanpv2sf (a, b);
++  return __builtin_aarch64_faddpv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vpminq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  return __builtin_aarch64_smin_nanpv4sf (a, b);
++  return __builtin_aarch64_faddpv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vpminq_f64 (float64x2_t a, float64x2_t b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  return __builtin_aarch64_smin_nanpv2df (a, b);
++  return __builtin_aarch64_faddpv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vpminqd_f64 (float64x2_t a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return __builtin_aarch64_reduc_smin_nan_scal_v2df (a);
++  return __builtin_aarch64_addpv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vpmins_f32 (float32x2_t a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return __builtin_aarch64_reduc_smin_nan_scal_v2sf (a);
++  return __builtin_aarch64_addpv4hi (__a, __b);
+ }
+ 
+-/* vpminnm  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vpminnm_f32 (float32x2_t a, float32x2_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return __builtin_aarch64_sminpv2sf (a, b);
++  return __builtin_aarch64_addpv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vpminnmq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  return __builtin_aarch64_sminpv4sf (a, b);
++  return (uint8x8_t) __builtin_aarch64_addpv8qi ((int8x8_t) __a,
++						 (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vpminnmq_f64 (float64x2_t a, float64x2_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  return __builtin_aarch64_sminpv2df (a, b);
++  return (uint16x4_t) __builtin_aarch64_addpv4hi ((int16x4_t) __a,
++						  (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vpminnmqd_f64 (float64x2_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v2df (a);
++  return (uint32x2_t) __builtin_aarch64_addpv2si ((int32x2_t) __a,
++						  (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vpminnms_f32 (float32x2_t a)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadds_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v2sf (a);
++  return __builtin_aarch64_reduc_plus_scal_v2sf (__a);
+ }
+ 
+-/* vmaxnm  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmaxnm_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddd_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_fmaxv2sf (__a, __b);
++  return __builtin_aarch64_reduc_plus_scal_v2df (__a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmaxnmq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddd_s64 (int64x2_t __a)
+ {
+-  return __builtin_aarch64_fmaxv4sf (__a, __b);
++  return __builtin_aarch64_addpdi (__a);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmaxnmq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddd_u64 (uint64x2_t __a)
+ {
+-  return __builtin_aarch64_fmaxv2df (__a, __b);
++  return __builtin_aarch64_addpdi ((int64x2_t) __a);
+ }
+ 
+-/* vmaxv  */
++/* vqabs */
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmaxv_f32 (float32x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqabsq_s64 (int64x2_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_nan_scal_v2sf (__a);
++  return (int64x2_t) __builtin_aarch64_sqabsv2di (__a);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vmaxv_s8 (int8x8_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqabsb_s8 (int8_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v8qi (__a);
++  return (int8_t) __builtin_aarch64_sqabsqi (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vmaxv_s16 (int16x4_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqabsh_s16 (int16_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v4hi (__a);
++  return (int16_t) __builtin_aarch64_sqabshi (__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vmaxv_s32 (int32x2_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqabss_s32 (int32_t __a)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v2si (__a);
++  return (int32_t) __builtin_aarch64_sqabssi (__a);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vmaxv_u8 (uint8x8_t __a)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqabsd_s64 (int64_t __a)
+ {
+-  return __builtin_aarch64_reduc_umax_scal_v8qi_uu (__a);
++  return __builtin_aarch64_sqabsdi (__a);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vmaxv_u16 (uint16x4_t __a)
+-{
+-  return __builtin_aarch64_reduc_umax_scal_v4hi_uu (__a);
+-}
++/* vqadd */
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vmaxv_u32 (uint32x2_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqaddb_s8 (int8_t __a, int8_t __b)
+ {
+-  return __builtin_aarch64_reduc_umax_scal_v2si_uu (__a);
++  return (int8_t) __builtin_aarch64_sqaddqi (__a, __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmaxvq_f32 (float32x4_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqaddh_s16 (int16_t __a, int16_t __b)
+ {
+-  return __builtin_aarch64_reduc_smax_nan_scal_v4sf (__a);
++  return (int16_t) __builtin_aarch64_sqaddhi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmaxvq_f64 (float64x2_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqadds_s32 (int32_t __a, int32_t __b)
+ {
+-  return __builtin_aarch64_reduc_smax_nan_scal_v2df (__a);
++  return (int32_t) __builtin_aarch64_sqaddsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vmaxvq_s8 (int8x16_t __a)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqaddd_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v16qi (__a);
++  return __builtin_aarch64_sqadddi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vmaxvq_s16 (int16x8_t __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqaddb_u8 (uint8_t __a, uint8_t __b)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v8hi (__a);
++  return (uint8_t) __builtin_aarch64_uqaddqi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vmaxvq_s32 (int32x4_t __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqaddh_u16 (uint16_t __a, uint16_t __b)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v4si (__a);
++  return (uint16_t) __builtin_aarch64_uqaddhi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vmaxvq_u8 (uint8x16_t __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqadds_u32 (uint32_t __a, uint32_t __b)
+ {
+-  return __builtin_aarch64_reduc_umax_scal_v16qi_uu (__a);
++  return (uint32_t) __builtin_aarch64_uqaddsi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vmaxvq_u16 (uint16x8_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqaddd_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return __builtin_aarch64_reduc_umax_scal_v8hi_uu (__a);
++  return __builtin_aarch64_uqadddi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vmaxvq_u32 (uint32x4_t __a)
++/* vqdmlal */
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+-  return __builtin_aarch64_reduc_umax_scal_v4si_uu (__a);
++  return __builtin_aarch64_sqdmlalv4hi (__a, __b, __c);
+ }
+ 
+-/* vmaxnmv  */
+-
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmaxnmv_f32 (float32x2_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v2sf (__a);
++  return __builtin_aarch64_sqdmlal2v8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmaxnmvq_f32 (float32x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_lane_s16 (int32x4_t __a, int16x8_t __b, int16x4_t __c,
++		       int const __d)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v4sf (__a);
++  return __builtin_aarch64_sqdmlal2_lanev8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmaxnmvq_f64 (float64x2_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_laneq_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c,
++			int const __d)
+ {
+-  return __builtin_aarch64_reduc_smax_scal_v2df (__a);
++  return __builtin_aarch64_sqdmlal2_laneqv8hi (__a, __b, __c, __d);
+ }
+ 
+-/* vmin  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmin_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c)
+ {
+-  return __builtin_aarch64_smin_nanv2sf (__a, __b);
++  return __builtin_aarch64_sqdmlal2_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmin_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, int const __d)
+ {
+-  return __builtin_aarch64_sminv8qi (__a, __b);
++  return __builtin_aarch64_sqdmlal_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmin_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_laneq_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __c, int const __d)
+ {
+-  return __builtin_aarch64_sminv4hi (__a, __b);
++  return __builtin_aarch64_sqdmlal_laneqv4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmin_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+ {
+-  return __builtin_aarch64_sminv2si (__a, __b);
++  return __builtin_aarch64_sqdmlal_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmin_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+-  return (uint8x8_t) __builtin_aarch64_uminv8qi ((int8x8_t) __a,
+-						 (int8x8_t) __b);
++  return __builtin_aarch64_sqdmlalv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmin_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+ {
+-  return (uint16x4_t) __builtin_aarch64_uminv4hi ((int16x4_t) __a,
+-						  (int16x4_t) __b);
++  return __builtin_aarch64_sqdmlal2v4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmin_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x2_t __c,
++		       int const __d)
+ {
+-  return (uint32x2_t) __builtin_aarch64_uminv2si ((int32x2_t) __a,
+-						  (int32x2_t) __b);
++  return __builtin_aarch64_sqdmlal2_lanev4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vminq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c,
++			int const __d)
+ {
+-  return __builtin_aarch64_smin_nanv4sf (__a, __b);
++  return __builtin_aarch64_sqdmlal2_laneqv4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vminq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c)
+ {
+-  return __builtin_aarch64_smin_nanv2df (__a, __b);
++  return __builtin_aarch64_sqdmlal2_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vminq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, int const __d)
+ {
+-  return __builtin_aarch64_sminv16qi (__a, __b);
++  return __builtin_aarch64_sqdmlal_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vminq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c, int const __d)
+ {
+-  return __builtin_aarch64_sminv8hi (__a, __b);
++  return __builtin_aarch64_sqdmlal_laneqv2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vminq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ {
+-  return __builtin_aarch64_sminv4si (__a, __b);
++  return __builtin_aarch64_sqdmlal_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vminq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlalh_s16 (int32_t __a, int16_t __b, int16_t __c)
+ {
+-  return (uint8x16_t) __builtin_aarch64_uminv16qi ((int8x16_t) __a,
+-						   (int8x16_t) __b);
++  return __builtin_aarch64_sqdmlalhi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vminq_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlalh_lane_s16 (int32_t __a, int16_t __b, int16x4_t __c, const int __d)
+ {
+-  return (uint16x8_t) __builtin_aarch64_uminv8hi ((int16x8_t) __a,
+-						  (int16x8_t) __b);
++  return __builtin_aarch64_sqdmlal_lanehi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vminq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlalh_laneq_s16 (int32_t __a, int16_t __b, int16x8_t __c, const int __d)
+ {
+-  return (uint32x4_t) __builtin_aarch64_uminv4si ((int32x4_t) __a,
+-						  (int32x4_t) __b);
++  return __builtin_aarch64_sqdmlal_laneqhi (__a, __b, __c, __d);
+ }
+ 
+-/* vminnm  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vminnm_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlals_s32 (int64_t __a, int32_t __b, int32_t __c)
+ {
+-  return __builtin_aarch64_fminv2sf (__a, __b);
++  return __builtin_aarch64_sqdmlalsi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vminnmq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlals_lane_s32 (int64_t __a, int32_t __b, int32x2_t __c, const int __d)
+ {
+-  return __builtin_aarch64_fminv4sf (__a, __b);
++  return __builtin_aarch64_sqdmlal_lanesi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vminnmq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlals_laneq_s32 (int64_t __a, int32_t __b, int32x4_t __c, const int __d)
+ {
+-  return __builtin_aarch64_fminv2df (__a, __b);
++  return __builtin_aarch64_sqdmlal_laneqsi (__a, __b, __c, __d);
+ }
+ 
+-/* vminv  */
++/* vqdmlsl */
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vminv_f32 (float32x2_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_nan_scal_v2sf (__a);
++  return __builtin_aarch64_sqdmlslv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vminv_s8 (int8x8_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v8qi (__a);
++  return __builtin_aarch64_sqdmlsl2v8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vminv_s16 (int16x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_lane_s16 (int32x4_t __a, int16x8_t __b, int16x4_t __c,
++		       int const __d)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v4hi (__a);
++  return __builtin_aarch64_sqdmlsl2_lanev8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vminv_s32 (int32x2_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_laneq_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c,
++			int const __d)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v2si (__a);
++  return __builtin_aarch64_sqdmlsl2_laneqv8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vminv_u8 (uint8x8_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c)
+ {
+-  return __builtin_aarch64_reduc_umin_scal_v8qi_uu (__a);
++  return __builtin_aarch64_sqdmlsl2_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vminv_u16 (uint16x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, int const __d)
+ {
+-  return __builtin_aarch64_reduc_umin_scal_v4hi_uu (__a);
++  return __builtin_aarch64_sqdmlsl_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vminv_u32 (uint32x2_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_laneq_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __c, int const __d)
+ {
+-  return __builtin_aarch64_reduc_umin_scal_v2si_uu (__a);
++  return __builtin_aarch64_sqdmlsl_laneqv4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vminvq_f32 (float32x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_nan_scal_v4sf (__a);
++  return __builtin_aarch64_sqdmlsl_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vminvq_f64 (float64x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_nan_scal_v2df (__a);
++  return __builtin_aarch64_sqdmlslv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vminvq_s8 (int8x16_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v16qi (__a);
++  return __builtin_aarch64_sqdmlsl2v4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vminvq_s16 (int16x8_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x2_t __c,
++		       int const __d)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v8hi (__a);
++  return __builtin_aarch64_sqdmlsl2_lanev4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vminvq_s32 (int32x4_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c,
++			int const __d)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v4si (__a);
++  return __builtin_aarch64_sqdmlsl2_laneqv4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vminvq_u8 (uint8x16_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c)
+ {
+-  return __builtin_aarch64_reduc_umin_scal_v16qi_uu (__a);
++  return __builtin_aarch64_sqdmlsl2_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vminvq_u16 (uint16x8_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, int const __d)
+ {
+-  return __builtin_aarch64_reduc_umin_scal_v8hi_uu (__a);
++  return __builtin_aarch64_sqdmlsl_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vminvq_u32 (uint32x4_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c, int const __d)
+ {
+-  return __builtin_aarch64_reduc_umin_scal_v4si_uu (__a);
++  return __builtin_aarch64_sqdmlsl_laneqv2si (__a, __b, __c, __d);
+ }
+ 
+-/* vminnmv  */
+-
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vminnmv_f32 (float32x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v2sf (__a);
++  return __builtin_aarch64_sqdmlsl_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vminnmvq_f32 (float32x4_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlslh_s16 (int32_t __a, int16_t __b, int16_t __c)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v4sf (__a);
++  return __builtin_aarch64_sqdmlslhi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vminnmvq_f64 (float64x2_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlslh_lane_s16 (int32_t __a, int16_t __b, int16x4_t __c, const int __d)
+ {
+-  return __builtin_aarch64_reduc_smin_scal_v2df (__a);
++  return __builtin_aarch64_sqdmlsl_lanehi (__a, __b, __c, __d);
+ }
+ 
+-/* vmla */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmla_f32 (float32x2_t a, float32x2_t b, float32x2_t c)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlslh_laneq_s16 (int32_t __a, int16_t __b, int16x8_t __c, const int __d)
+ {
+-  return a + b * c;
++  return __builtin_aarch64_sqdmlsl_laneqhi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmla_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsls_s32 (int64_t __a, int32_t __b, int32_t __c)
+ {
+-  return __a + __b * __c;
++  return __builtin_aarch64_sqdmlslsi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlaq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsls_lane_s32 (int64_t __a, int32_t __b, int32x2_t __c, const int __d)
+ {
+-  return a + b * c;
++  return __builtin_aarch64_sqdmlsl_lanesi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmlaq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmlsls_laneq_s32 (int64_t __a, int32_t __b, int32x4_t __c, const int __d)
+ {
+-  return a + b * c;
++  return __builtin_aarch64_sqdmlsl_laneqsi (__a, __b, __c, __d);
+ }
+ 
+-/* vmla_lane  */
++/* vqdmulh */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmla_lane_f32 (float32x2_t __a, float32x2_t __b,
+-	       float32x2_t __c, const int __lane)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmla_lane_s16 (int16x4_t __a, int16x4_t __b,
+-		int16x4_t __c, const int __lane)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmla_lane_s32 (int32x2_t __a, int32x2_t __b,
+-		int32x2_t __c, const int __lane)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_lanev8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmla_lane_u16 (uint16x4_t __a, uint16x4_t __b,
+-		uint16x4_t __c, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_lanev4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmla_lane_u32 (uint32x2_t __a, uint32x2_t __b,
+-	       uint32x2_t __c, const int __lane)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhh_s16 (int16_t __a, int16_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int16_t) __builtin_aarch64_sqdmulhhi (__a, __b);
+ }
+ 
+-/* vmla_laneq  */
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhh_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
++{
++  return __builtin_aarch64_sqdmulh_lanehi (__a, __b, __c);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmla_laneq_f32 (float32x2_t __a, float32x2_t __b,
+-	        float32x4_t __c, const int __lane)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhh_laneq_s16 (int16_t __a, int16x8_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_laneqhi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmla_laneq_s16 (int16x4_t __a, int16x4_t __b,
+-		int16x8_t __c, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhs_s32 (int32_t __a, int32_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int32_t) __builtin_aarch64_sqdmulhsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmla_laneq_s32 (int32x2_t __a, int32x2_t __b,
+-		int32x4_t __c, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhs_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_lanesi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmla_laneq_u16 (uint16x4_t __a, uint16x4_t __b,
+-		uint16x8_t __c, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulhs_laneq_s32 (int32_t __a, int32x4_t __b, const int __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmulh_laneqsi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmla_laneq_u32 (uint32x2_t __a, uint32x2_t __b,
+-		uint32x4_t __c, const int __lane)
++/* vqdmull */
++
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmullv4hi (__a, __b);
+ }
+ 
+-/* vmlaq_lane  */
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_s16 (int16x8_t __a, int16x8_t __b)
++{
++  return __builtin_aarch64_sqdmull2v8hi (__a, __b);
++}
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlaq_lane_f32 (float32x4_t __a, float32x4_t __b,
+-		float32x2_t __c, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_lane_s16 (int16x8_t __a, int16x4_t __b, int const __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2_lanev8hi (__a, __b,__c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlaq_lane_s16 (int16x8_t __a, int16x8_t __b,
+-		int16x4_t __c, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_laneq_s16 (int16x8_t __a, int16x8_t __b, int const __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2_laneqv8hi (__a, __b,__c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlaq_lane_s32 (int32x4_t __a, int32x4_t __b,
+-		int32x2_t __c, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_n_s16 (int16x8_t __a, int16_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlaq_lane_u16 (uint16x8_t __a, uint16x8_t __b,
+-		uint16x4_t __c, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_lane_s16 (int16x4_t __a, int16x4_t __b, int const __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlaq_lane_u32 (uint32x4_t __a, uint32x4_t __b,
+-		uint32x2_t __c, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_laneq_s16 (int16x4_t __a, int16x8_t __b, int const __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull_laneqv4hi (__a, __b, __c);
+ }
+ 
+-  /* vmlaq_laneq  */
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_n_s16 (int16x4_t __a, int16_t __b)
++{
++  return __builtin_aarch64_sqdmull_nv4hi (__a, __b);
++}
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlaq_laneq_f32 (float32x4_t __a, float32x4_t __b,
+-		 float32x4_t __c, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmullv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlaq_laneq_s16 (int16x8_t __a, int16x8_t __b,
+-		int16x8_t __c, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2v4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlaq_laneq_s32 (int32x4_t __a, int32x4_t __b,
+-		int32x4_t __c, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_lane_s32 (int32x4_t __a, int32x2_t __b, int const __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2_lanev4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlaq_laneq_u16 (uint16x8_t __a, uint16x8_t __b,
+-		uint16x8_t __c, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_laneq_s32 (int32x4_t __a, int32x4_t __b, int const __c)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2_laneqv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlaq_laneq_u32 (uint32x4_t __a, uint32x4_t __b,
+-		uint32x4_t __c, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_high_n_s32 (int32x4_t __a, int32_t __b)
+ {
+-  return (__a + (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull2_nv4si (__a, __b);
+ }
+ 
+-/* vmls  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmls_f32 (float32x2_t a, float32x2_t b, float32x2_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_lane_s32 (int32x2_t __a, int32x2_t __b, int const __c)
+ {
+-  return a - b * c;
++  return __builtin_aarch64_sqdmull_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmls_f64 (float64x1_t __a, float64x1_t __b, float64x1_t __c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_laneq_s32 (int32x2_t __a, int32x4_t __b, int const __c)
+ {
+-  return __a - __b * __c;
++  return __builtin_aarch64_sqdmull_laneqv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlsq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmull_n_s32 (int32x2_t __a, int32_t __b)
+ {
+-  return a - b * c;
++  return __builtin_aarch64_sqdmull_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmlsq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmullh_s16 (int16_t __a, int16_t __b)
+ {
+-  return a - b * c;
++  return (int32_t) __builtin_aarch64_sqdmullhi (__a, __b);
+ }
+ 
+-/* vmls_lane  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmls_lane_f32 (float32x2_t __a, float32x2_t __b,
+-	       float32x2_t __c, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmullh_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull_lanehi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmls_lane_s16 (int16x4_t __a, int16x4_t __b,
+-		int16x4_t __c, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmullh_laneq_s16 (int16_t __a, int16x8_t __b, const int __c)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull_laneqhi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmls_lane_s32 (int32x2_t __a, int32x2_t __b,
+-		int32x2_t __c, const int __lane)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulls_s32 (int32_t __a, int32_t __b)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmullsi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmls_lane_u16 (uint16x4_t __a, uint16x4_t __b,
+-		uint16x4_t __c, const int __lane)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulls_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull_lanesi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmls_lane_u32 (uint32x2_t __a, uint32x2_t __b,
+-	       uint32x2_t __c, const int __lane)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqdmulls_laneq_s32 (int32_t __a, int32x4_t __b, const int __c)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return __builtin_aarch64_sqdmull_laneqsi (__a, __b, __c);
+ }
+ 
+-/* vmls_laneq  */
++/* vqmovn */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmls_laneq_f32 (float32x2_t __a, float32x2_t __b,
+-	       float32x4_t __c, const int __lane)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_s16 (int16x8_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int8x8_t) __builtin_aarch64_sqmovnv8hi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmls_laneq_s16 (int16x4_t __a, int16x4_t __b,
+-		int16x8_t __c, const int __lane)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_s32 (int32x4_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int16x4_t) __builtin_aarch64_sqmovnv4si (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmls_laneq_s32 (int32x2_t __a, int32x2_t __b,
+-		int32x4_t __c, const int __lane)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_s64 (int64x2_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int32x2_t) __builtin_aarch64_sqmovnv2di (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmls_laneq_u16 (uint16x4_t __a, uint16x4_t __b,
+-		uint16x8_t __c, const int __lane)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_u16 (uint16x8_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint8x8_t) __builtin_aarch64_uqmovnv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmls_laneq_u32 (uint32x2_t __a, uint32x2_t __b,
+-		uint32x4_t __c, const int __lane)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_u32 (uint32x4_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint16x4_t) __builtin_aarch64_uqmovnv4si ((int32x4_t) __a);
+ }
+ 
+-/* vmlsq_lane  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlsq_lane_f32 (float32x4_t __a, float32x4_t __b,
+-		float32x2_t __c, const int __lane)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovn_u64 (uint64x2_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint32x2_t) __builtin_aarch64_uqmovnv2di ((int64x2_t) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlsq_lane_s16 (int16x8_t __a, int16x8_t __b,
+-		int16x4_t __c, const int __lane)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovnh_s16 (int16_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int8_t) __builtin_aarch64_sqmovnhi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsq_lane_s32 (int32x4_t __a, int32x4_t __b,
+-		int32x2_t __c, const int __lane)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovns_s32 (int32_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int16_t) __builtin_aarch64_sqmovnsi (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlsq_lane_u16 (uint16x8_t __a, uint16x8_t __b,
+-		uint16x4_t __c, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovnd_s64 (int64_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (int32_t) __builtin_aarch64_sqmovndi (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsq_lane_u32 (uint32x4_t __a, uint32x4_t __b,
+-		uint32x2_t __c, const int __lane)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovnh_u16 (uint16_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint8_t) __builtin_aarch64_uqmovnhi (__a);
+ }
+ 
+-  /* vmlsq_laneq  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmlsq_laneq_f32 (float32x4_t __a, float32x4_t __b,
+-		float32x4_t __c, const int __lane)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovns_u32 (uint32_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint16_t) __builtin_aarch64_uqmovnsi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmlsq_laneq_s16 (int16x8_t __a, int16x8_t __b,
+-		int16x8_t __c, const int __lane)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovnd_u64 (uint64_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint32_t) __builtin_aarch64_uqmovndi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmlsq_laneq_s32 (int32x4_t __a, int32x4_t __b,
+-		int32x4_t __c, const int __lane)
++/* vqmovun */
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovun_s16 (int16x8_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint8x8_t) __builtin_aarch64_sqmovunv8hi (__a);
+ }
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmlsq_laneq_u16 (uint16x8_t __a, uint16x8_t __b,
+-		uint16x8_t __c, const int __lane)
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovun_s32 (int32x4_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint16x4_t) __builtin_aarch64_sqmovunv4si (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmlsq_laneq_u32 (uint32x4_t __a, uint32x4_t __b,
+-		uint32x4_t __c, const int __lane)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovun_s64 (int64x2_t __a)
+ {
+-  return (__a - (__b * __aarch64_vget_lane_any (__c, __lane)));
++  return (uint32x2_t) __builtin_aarch64_sqmovunv2di (__a);
+ }
+ 
+-/* vmov_n_  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmov_n_f32 (float32_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovunh_s16 (int16_t __a)
+ {
+-  return vdup_n_f32 (__a);
++  return (int8_t) __builtin_aarch64_sqmovunhi (__a);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmov_n_f64 (float64_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovuns_s32 (int32_t __a)
+ {
+-  return (float64x1_t) {__a};
++  return (int16_t) __builtin_aarch64_sqmovunsi (__a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vmov_n_p8 (poly8_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqmovund_s64 (int64_t __a)
+ {
+-  return vdup_n_p8 (__a);
++  return (int32_t) __builtin_aarch64_sqmovundi (__a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vmov_n_p16 (poly16_t __a)
++/* vqneg */
++
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqnegq_s64 (int64x2_t __a)
+ {
+-  return vdup_n_p16 (__a);
++  return (int64x2_t) __builtin_aarch64_sqnegv2di (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vmov_n_s8 (int8_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqnegb_s8 (int8_t __a)
+ {
+-  return vdup_n_s8 (__a);
++  return (int8_t) __builtin_aarch64_sqnegqi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmov_n_s16 (int16_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqnegh_s16 (int16_t __a)
+ {
+-  return vdup_n_s16 (__a);
++  return (int16_t) __builtin_aarch64_sqneghi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmov_n_s32 (int32_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqnegs_s32 (int32_t __a)
+ {
+-  return vdup_n_s32 (__a);
++  return (int32_t) __builtin_aarch64_sqnegsi (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vmov_n_s64 (int64_t __a)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqnegd_s64 (int64_t __a)
+ {
+-  return (int64x1_t) {__a};
++  return __builtin_aarch64_sqnegdi (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vmov_n_u8 (uint8_t __a)
++/* vqrdmulh */
++
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+-  return vdup_n_u8 (__a);
++  return  __builtin_aarch64_sqrdmulh_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmov_n_u16 (uint16_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+-    return vdup_n_u16 (__a);
++  return __builtin_aarch64_sqrdmulh_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmov_n_u32 (uint32_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
+ {
+-   return vdup_n_u32 (__a);
++  return __builtin_aarch64_sqrdmulh_lanev8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vmov_n_u64 (uint64_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
+ {
+-  return (uint64x1_t) {__a};
++  return __builtin_aarch64_sqrdmulh_lanev4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmovq_n_f32 (float32_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhh_s16 (int16_t __a, int16_t __b)
+ {
+-  return vdupq_n_f32 (__a);
++  return (int16_t) __builtin_aarch64_sqrdmulhhi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmovq_n_f64 (float64_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhh_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
+ {
+-  return vdupq_n_f64 (__a);
++  return __builtin_aarch64_sqrdmulh_lanehi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vmovq_n_p8 (poly8_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhh_laneq_s16 (int16_t __a, int16x8_t __b, const int __c)
+ {
+-  return vdupq_n_p8 (__a);
++  return __builtin_aarch64_sqrdmulh_laneqhi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vmovq_n_p16 (poly16_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhs_s32 (int32_t __a, int32_t __b)
+ {
+-  return vdupq_n_p16 (__a);
++  return (int32_t) __builtin_aarch64_sqrdmulhsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vmovq_n_s8 (int8_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhs_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
+ {
+-  return vdupq_n_s8 (__a);
++  return __builtin_aarch64_sqrdmulh_lanesi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmovq_n_s16 (int16_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrdmulhs_laneq_s32 (int32_t __a, int32x4_t __b, const int __c)
+ {
+-  return vdupq_n_s16 (__a);
++  return __builtin_aarch64_sqrdmulh_laneqsi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmovq_n_s32 (int32_t __a)
++/* vqrshl */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return vdupq_n_s32 (__a);
++  return __builtin_aarch64_sqrshlv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vmovq_n_s64 (int64_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return vdupq_n_s64 (__a);
++  return __builtin_aarch64_sqrshlv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vmovq_n_u8 (uint8_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return vdupq_n_u8 (__a);
++  return __builtin_aarch64_sqrshlv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmovq_n_u16 (uint16_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  return vdupq_n_u16 (__a);
++  return (int64x1_t) {__builtin_aarch64_sqrshldi (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmovq_n_u32 (uint32_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+-  return vdupq_n_u32 (__a);
++  return __builtin_aarch64_uqrshlv8qi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vmovq_n_u64 (uint64_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+-  return vdupq_n_u64 (__a);
++  return __builtin_aarch64_uqrshlv4hi_uus ( __a, __b);
+ }
+ 
+-/* vmul_lane  */
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_u32 (uint32x2_t __a, int32x2_t __b)
++{
++  return __builtin_aarch64_uqrshlv2si_uus ( __a, __b);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmul_lane_f32 (float32x2_t __a, float32x2_t __b, const int __lane)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return (uint64x1_t) {__builtin_aarch64_uqrshldi_uus (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmul_lane_f64 (float64x1_t __a, float64x1_t __b, const int __lane)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  return __a * __b;
++  return __builtin_aarch64_sqrshlv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmul_lane_s16 (int16x4_t __a, int16x4_t __b, const int __lane)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshlv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmul_lane_s32 (int32x2_t __a, int32x2_t __b, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshlv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmul_lane_u16 (uint16x4_t __a, uint16x4_t __b, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshlv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmul_lane_u32 (uint32x2_t __a, uint32x2_t __b, const int __lane)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlv16qi_uus ( __a, __b);
+ }
+ 
+-/* vmuld_lane  */
+-
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmuld_lane_f64 (float64_t __a, float64x1_t __b, const int __lane)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlv8hi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vmuld_laneq_f64 (float64_t __a, float64x2_t __b, const int __lane)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlv4si_uus ( __a, __b);
+ }
+ 
+-/* vmuls_lane  */
+-
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmuls_lane_f32 (float32_t __a, float32x2_t __b, const int __lane)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlv2di_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vmuls_laneq_f32 (float32_t __a, float32x4_t __b, const int __lane)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlb_s8 (int8_t __a, int8_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshlqi (__a, __b);
+ }
+ 
+-/* vmul_laneq  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vmul_laneq_f32 (float32x2_t __a, float32x4_t __b, const int __lane)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlh_s16 (int16_t __a, int16_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshlhi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmul_laneq_f64 (float64x1_t __a, float64x2_t __b, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshls_s32 (int32_t __a, int32_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshlsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vmul_laneq_s16 (int16x4_t __a, int16x8_t __b, const int __lane)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshld_s64 (int64_t __a, int64_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_sqrshldi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vmul_laneq_s32 (int32x2_t __a, int32x4_t __b, const int __lane)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlb_u8 (uint8_t __a, uint8_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlqi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vmul_laneq_u16 (uint16x4_t __a, uint16x8_t __b, const int __lane)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshlh_u16 (uint16_t __a, uint16_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlhi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vmul_laneq_u32 (uint32x2_t __a, uint32x4_t __b, const int __lane)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshls_u32 (uint32_t __a, uint32_t __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshlsi_uus (__a, __b);
+ }
+ 
+-/* vmul_n  */
+-
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vmul_n_f64  (float64x1_t __a, float64_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshld_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return (float64x1_t) { vget_lane_f64 (__a, 0) * __b };
++  return __builtin_aarch64_uqrshldi_uus (__a, __b);
+ }
+ 
+-/* vmulq_lane  */
++/* vqrshrn */
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmulq_lane_f32 (float32x4_t __a, float32x2_t __b, const int __lane)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrn_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return (int8x8_t) __builtin_aarch64_sqrshrn_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmulq_lane_f64 (float64x2_t __a, float64x1_t __b, const int __lane)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrn_n_s32 (int32x4_t __a, const int __b)
+ {
+-  __AARCH64_LANE_CHECK (__a, __lane);
+-  return __a * __b[0];
++  return (int16x4_t) __builtin_aarch64_sqrshrn_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmulq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __lane)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrn_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return (int32x2_t) __builtin_aarch64_sqrshrn_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmulq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __lane)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrn_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshrn_nv8hi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmulq_lane_u16 (uint16x8_t __a, uint16x4_t __b, const int __lane)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrn_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshrn_nv4si_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmulq_lane_u32 (uint32x4_t __a, uint32x2_t __b, const int __lane)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrn_n_u64 (uint64x2_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshrn_nv2di_uus ( __a, __b);
+ }
+ 
+-/* vmulq_laneq  */
+-
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vmulq_laneq_f32 (float32x4_t __a, float32x4_t __b, const int __lane)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrnh_n_s16 (int16_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return (int8_t) __builtin_aarch64_sqrshrn_nhi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vmulq_laneq_f64 (float64x2_t __a, float64x2_t __b, const int __lane)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrns_n_s32 (int32_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return (int16_t) __builtin_aarch64_sqrshrn_nsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vmulq_laneq_s16 (int16x8_t __a, int16x8_t __b, const int __lane)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrnd_n_s64 (int64_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return (int32_t) __builtin_aarch64_sqrshrn_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vmulq_laneq_s32 (int32x4_t __a, int32x4_t __b, const int __lane)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrnh_n_u16 (uint16_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshrn_nhi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vmulq_laneq_u16 (uint16x8_t __a, uint16x8_t __b, const int __lane)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrns_n_u32 (uint32_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshrn_nsi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vmulq_laneq_u32 (uint32x4_t __a, uint32x4_t __b, const int __lane)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrnd_n_u64 (uint64_t __a, const int __b)
+ {
+-  return __a * __aarch64_vget_lane_any (__b, __lane);
++  return __builtin_aarch64_uqrshrn_ndi_uus (__a, __b);
+ }
+ 
+-/* vneg  */
++/* vqrshrun */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vneg_f32 (float32x2_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrun_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return -__a;
++  return (uint8x8_t) __builtin_aarch64_sqrshrun_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vneg_f64 (float64x1_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrun_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return -__a;
++  return (uint16x4_t) __builtin_aarch64_sqrshrun_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vneg_s8 (int8x8_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrun_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return -__a;
++  return (uint32x2_t) __builtin_aarch64_sqrshrun_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vneg_s16 (int16x4_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrunh_n_s16 (int16_t __a, const int __b)
+ {
+-  return -__a;
++  return (int8_t) __builtin_aarch64_sqrshrun_nhi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vneg_s32 (int32x2_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshruns_n_s32 (int32_t __a, const int __b)
+ {
+-  return -__a;
++  return (int16_t) __builtin_aarch64_sqrshrun_nsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vneg_s64 (int64x1_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqrshrund_n_s64 (int64_t __a, const int __b)
+ {
+-  return -__a;
++  return (int32_t) __builtin_aarch64_sqrshrun_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vnegq_f32 (float32x4_t __a)
++/* vqshl */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return -__a;
++  return __builtin_aarch64_sqshlv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vnegq_f64 (float64x2_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return -__a;
++  return __builtin_aarch64_sqshlv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vnegq_s8 (int8x16_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return -__a;
++  return __builtin_aarch64_sqshlv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vnegq_s16 (int16x8_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  return -__a;
++  return (int64x1_t) {__builtin_aarch64_sqshldi (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vnegq_s32 (int32x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+-  return -__a;
++  return __builtin_aarch64_uqshlv8qi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vnegq_s64 (int64x2_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+-  return -__a;
++  return __builtin_aarch64_uqshlv4hi_uus ( __a, __b);
+ }
+ 
+-/* vpadd  */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vpadd_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+-  return __builtin_aarch64_addpv8qi (__a, __b);
++  return __builtin_aarch64_uqshlv2si_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vpadd_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+-  return __builtin_aarch64_addpv4hi (__a, __b);
++  return (uint64x1_t) {__builtin_aarch64_uqshldi_uus (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vpadd_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  return __builtin_aarch64_addpv2si (__a, __b);
++  return __builtin_aarch64_sqshlv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vpadd_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  return (uint8x8_t) __builtin_aarch64_addpv8qi ((int8x8_t) __a,
+-						 (int8x8_t) __b);
++  return __builtin_aarch64_sqshlv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vpadd_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  return (uint16x4_t) __builtin_aarch64_addpv4hi ((int16x4_t) __a,
+-						  (int16x4_t) __b);
++  return __builtin_aarch64_sqshlv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vpadd_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  return (uint32x2_t) __builtin_aarch64_addpv2si ((int32x2_t) __a,
+-						  (int32x2_t) __b);
++  return __builtin_aarch64_sqshlv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vpaddd_f64 (float64x2_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+-  return __builtin_aarch64_reduc_plus_scal_v2df (__a);
++  return __builtin_aarch64_uqshlv16qi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vpaddd_s64 (int64x2_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+-  return __builtin_aarch64_addpdi (__a);
++  return __builtin_aarch64_uqshlv8hi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vpaddd_u64 (uint64x2_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+-  return __builtin_aarch64_addpdi ((int64x2_t) __a);
++  return __builtin_aarch64_uqshlv4si_uus ( __a, __b);
+ }
+ 
+-/* vqabs */
+-
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqabsq_s64 (int64x2_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+-  return (int64x2_t) __builtin_aarch64_sqabsv2di (__a);
++  return __builtin_aarch64_uqshlv2di_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqabsb_s8 (int8_t __a)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlb_s8 (int8_t __a, int8_t __b)
+ {
+-  return (int8_t) __builtin_aarch64_sqabsqi (__a);
++  return __builtin_aarch64_sqshlqi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqabsh_s16 (int16_t __a)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlh_s16 (int16_t __a, int16_t __b)
+ {
+-  return (int16_t) __builtin_aarch64_sqabshi (__a);
++  return __builtin_aarch64_sqshlhi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqabss_s32 (int32_t __a)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshls_s32 (int32_t __a, int32_t __b)
+ {
+-  return (int32_t) __builtin_aarch64_sqabssi (__a);
++  return __builtin_aarch64_sqshlsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqabsd_s64 (int64_t __a)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshld_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_sqabsdi (__a);
++  return __builtin_aarch64_sqshldi (__a, __b);
+ }
+ 
+-/* vqadd */
+-
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqaddb_s8 (int8_t __a, int8_t __b)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlb_u8 (uint8_t __a, uint8_t __b)
+ {
+-  return (int8_t) __builtin_aarch64_sqaddqi (__a, __b);
++  return __builtin_aarch64_uqshlqi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqaddh_s16 (int16_t __a, int16_t __b)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlh_u16 (uint16_t __a, uint16_t __b)
+ {
+-  return (int16_t) __builtin_aarch64_sqaddhi (__a, __b);
++  return __builtin_aarch64_uqshlhi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqadds_s32 (int32_t __a, int32_t __b)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshls_u32 (uint32_t __a, uint32_t __b)
+ {
+-  return (int32_t) __builtin_aarch64_sqaddsi (__a, __b);
++  return __builtin_aarch64_uqshlsi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqaddd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshld_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return __builtin_aarch64_sqadddi (__a, __b);
++  return __builtin_aarch64_uqshldi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqaddb_u8 (uint8_t __a, uint8_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_s8 (int8x8_t __a, const int __b)
+ {
+-  return (uint8_t) __builtin_aarch64_uqaddqi_uuu (__a, __b);
++  return (int8x8_t) __builtin_aarch64_sqshl_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqaddh_u16 (uint16_t __a, uint16_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_s16 (int16x4_t __a, const int __b)
+ {
+-  return (uint16_t) __builtin_aarch64_uqaddhi_uuu (__a, __b);
++  return (int16x4_t) __builtin_aarch64_sqshl_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqadds_u32 (uint32_t __a, uint32_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_s32 (int32x2_t __a, const int __b)
+ {
+-  return (uint32_t) __builtin_aarch64_uqaddsi_uuu (__a, __b);
++  return (int32x2_t) __builtin_aarch64_sqshl_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vqaddd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_s64 (int64x1_t __a, const int __b)
+ {
+-  return __builtin_aarch64_uqadddi_uuu (__a, __b);
++  return (int64x1_t) {__builtin_aarch64_sqshl_ndi (__a[0], __b)};
+ }
+ 
+-/* vqdmlal */
+-
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_u8 (uint8x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlalv4hi (__a, __b, __c);
++  return __builtin_aarch64_uqshl_nv8qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_u16 (uint16x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2v8hi (__a, __b, __c);
++  return __builtin_aarch64_uqshl_nv4hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_high_lane_s16 (int32x4_t __a, int16x8_t __b, int16x4_t __c,
+-		       int const __d)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_u32 (uint32x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2_lanev8hi (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshl_nv2si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_high_laneq_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c,
+-			int const __d)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshl_n_u64 (uint64x1_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2_laneqv8hi (__a, __b, __c, __d);
++  return (uint64x1_t) {__builtin_aarch64_uqshl_ndi_uus (__a[0], __b)};
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_s8 (int8x16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2_nv8hi (__a, __b, __c);
++  return (int8x16_t) __builtin_aarch64_sqshl_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, int const __d)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_lanev4hi (__a, __b, __c, __d);
++  return (int16x8_t) __builtin_aarch64_sqshl_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_laneq_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __c, int const __d)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_laneqv4hi (__a, __b, __c, __d);
++  return (int32x4_t) __builtin_aarch64_sqshl_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_nv4hi (__a, __b, __c);
++  return (int64x2_t) __builtin_aarch64_sqshl_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_u8 (uint8x16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlalv2si (__a, __b, __c);
++  return __builtin_aarch64_uqshl_nv16qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2v4si (__a, __b, __c);
++  return __builtin_aarch64_uqshl_nv8hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x2_t __c,
+-		       int const __d)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2_lanev4si (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshl_nv4si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c,
+-			int const __d)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlq_n_u64 (uint64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2_laneqv4si (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshl_nv2di_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlb_n_s8 (int8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal2_nv4si (__a, __b, __c);
++  return (int8_t) __builtin_aarch64_sqshl_nqi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, int const __d)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlh_n_s16 (int16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_lanev2si (__a, __b, __c, __d);
++  return (int16_t) __builtin_aarch64_sqshl_nhi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c, int const __d)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshls_n_s32 (int32_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_laneqv2si (__a, __b, __c, __d);
++  return (int32_t) __builtin_aarch64_sqshl_nsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshld_n_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_nv2si (__a, __b, __c);
++  return __builtin_aarch64_sqshl_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmlalh_s16 (int32_t __a, int16_t __b, int16_t __c)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlb_n_u8 (uint8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlalhi (__a, __b, __c);
++  return __builtin_aarch64_uqshl_nqi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmlalh_lane_s16 (int32_t __a, int16_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlh_n_u16 (uint16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_lanehi (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshl_nhi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmlalh_laneq_s16 (int32_t __a, int16_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshls_n_u32 (uint32_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_laneqhi (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshl_nsi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmlals_s32 (int64_t __a, int32_t __b, int32_t __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshld_n_u64 (uint64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlalsi (__a, __b, __c);
++  return __builtin_aarch64_uqshl_ndi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmlals_lane_s32 (int64_t __a, int32_t __b, int32x2_t __c, const int __d)
++/* vqshlu */
++
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlu_n_s8 (int8x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_lanesi (__a, __b, __c, __d);
++  return __builtin_aarch64_sqshlu_nv8qi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmlals_laneq_s32 (int64_t __a, int32_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlu_n_s16 (int16x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlal_laneqsi (__a, __b, __c, __d);
++  return __builtin_aarch64_sqshlu_nv4hi_uss (__a, __b);
+ }
+ 
+-/* vqdmlsl */
+-
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlu_n_s32 (int32x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlslv4hi (__a, __b, __c);
++  return __builtin_aarch64_sqshlu_nv2si_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlu_n_s64 (int64x1_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2v8hi (__a, __b, __c);
++  return (uint64x1_t) {__builtin_aarch64_sqshlu_ndi_uss (__a[0], __b)};
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_lane_s16 (int32x4_t __a, int16x8_t __b, int16x4_t __c,
+-		       int const __d)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshluq_n_s8 (int8x16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2_lanev8hi (__a, __b, __c, __d);
++  return __builtin_aarch64_sqshlu_nv16qi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_laneq_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c,
+-			int const __d)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshluq_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2_laneqv8hi (__a, __b, __c, __d);
++  return __builtin_aarch64_sqshlu_nv8hi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshluq_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2_nv8hi (__a, __b, __c);
++  return __builtin_aarch64_sqshlu_nv4si_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, int const __d)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshluq_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_lanev4hi (__a, __b, __c, __d);
++  return __builtin_aarch64_sqshlu_nv2di_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_laneq_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __c, int const __d)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlub_n_s8 (int8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_laneqv4hi (__a, __b, __c, __d);
++  return (int8_t) __builtin_aarch64_sqshlu_nqi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshluh_n_s16 (int16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_nv4hi (__a, __b, __c);
++  return (int16_t) __builtin_aarch64_sqshlu_nhi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlus_n_s32 (int32_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlslv2si (__a, __b, __c);
++  return (int32_t) __builtin_aarch64_sqshlu_nsi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshlud_n_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2v4si (__a, __b, __c);
++  return __builtin_aarch64_sqshlu_ndi_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x2_t __c,
+-		       int const __d)
++/* vqshrn */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrn_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2_lanev4si (__a, __b, __c, __d);
++  return (int8x8_t) __builtin_aarch64_sqshrn_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c,
+-			int const __d)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrn_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2_laneqv4si (__a, __b, __c, __d);
++  return (int16x4_t) __builtin_aarch64_sqshrn_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrn_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl2_nv4si (__a, __b, __c);
++  return (int32x2_t) __builtin_aarch64_sqshrn_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, int const __d)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrn_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_lanev2si (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshrn_nv8hi_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c, int const __d)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrn_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_laneqv2si (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshrn_nv4si_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrn_n_u64 (uint64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_nv2si (__a, __b, __c);
++  return __builtin_aarch64_uqshrn_nv2di_uus ( __a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmlslh_s16 (int32_t __a, int16_t __b, int16_t __c)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrnh_n_s16 (int16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlslhi (__a, __b, __c);
++  return (int8_t) __builtin_aarch64_sqshrn_nhi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmlslh_lane_s16 (int32_t __a, int16_t __b, int16x4_t __c, const int __d)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrns_n_s32 (int32_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_lanehi (__a, __b, __c, __d);
++  return (int16_t) __builtin_aarch64_sqshrn_nsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmlslh_laneq_s16 (int32_t __a, int16_t __b, int16x8_t __c, const int __d)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrnd_n_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_laneqhi (__a, __b, __c, __d);
++  return (int32_t) __builtin_aarch64_sqshrn_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmlsls_s32 (int64_t __a, int32_t __b, int32_t __c)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrnh_n_u16 (uint16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlslsi (__a, __b, __c);
++  return __builtin_aarch64_uqshrn_nhi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmlsls_lane_s32 (int64_t __a, int32_t __b, int32x2_t __c, const int __d)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrns_n_u32 (uint32_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_lanesi (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshrn_nsi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmlsls_laneq_s32 (int64_t __a, int32_t __b, int32x4_t __c, const int __d)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrnd_n_u64 (uint64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmlsl_laneqsi (__a, __b, __c, __d);
++  return __builtin_aarch64_uqshrn_ndi_uus (__a, __b);
+ }
+ 
+-/* vqdmulh */
++/* vqshrun */
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrun_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmulh_lanev4hi (__a, __b, __c);
++  return (uint8x8_t) __builtin_aarch64_sqshrun_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrun_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmulh_lanev2si (__a, __b, __c);
++  return (uint16x4_t) __builtin_aarch64_sqshrun_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrun_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmulh_lanev8hi (__a, __b, __c);
++  return (uint32x2_t) __builtin_aarch64_sqshrun_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrunh_n_s16 (int16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmulh_lanev4si (__a, __b, __c);
++  return (int8_t) __builtin_aarch64_sqshrun_nhi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqdmulhh_s16 (int16_t __a, int16_t __b)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshruns_n_s32 (int32_t __a, const int __b)
+ {
+-  return (int16_t) __builtin_aarch64_sqdmulhhi (__a, __b);
++  return (int16_t) __builtin_aarch64_sqshrun_nsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqdmulhh_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqshrund_n_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqdmulh_lanehi (__a, __b, __c);
++  return (int32_t) __builtin_aarch64_sqshrun_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqdmulhh_laneq_s16 (int16_t __a, int16x8_t __b, const int __c)
++/* vqsub */
++
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubb_s8 (int8_t __a, int8_t __b)
+ {
+-  return __builtin_aarch64_sqdmulh_laneqhi (__a, __b, __c);
++  return (int8_t) __builtin_aarch64_sqsubqi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmulhs_s32 (int32_t __a, int32_t __b)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubh_s16 (int16_t __a, int16_t __b)
+ {
+-  return (int32_t) __builtin_aarch64_sqdmulhsi (__a, __b);
++  return (int16_t) __builtin_aarch64_sqsubhi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmulhs_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubs_s32 (int32_t __a, int32_t __b)
+ {
+-  return __builtin_aarch64_sqdmulh_lanesi (__a, __b, __c);
++  return (int32_t) __builtin_aarch64_sqsubsi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmulhs_laneq_s32 (int32_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubd_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_sqdmulh_laneqsi (__a, __b, __c);
++  return __builtin_aarch64_sqsubdi (__a, __b);
+ }
+ 
+-/* vqdmull */
+-
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubb_u8 (uint8_t __a, uint8_t __b)
+ {
+-  return __builtin_aarch64_sqdmullv4hi (__a, __b);
++  return (uint8_t) __builtin_aarch64_uqsubqi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_high_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubh_u16 (uint16_t __a, uint16_t __b)
+ {
+-  return __builtin_aarch64_sqdmull2v8hi (__a, __b);
++  return (uint16_t) __builtin_aarch64_uqsubhi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_high_lane_s16 (int16x8_t __a, int16x4_t __b, int const __c)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubs_u32 (uint32_t __a, uint32_t __b)
+ {
+-  return __builtin_aarch64_sqdmull2_lanev8hi (__a, __b,__c);
++  return (uint32_t) __builtin_aarch64_uqsubsi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_high_laneq_s16 (int16x8_t __a, int16x8_t __b, int const __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqsubd_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return __builtin_aarch64_sqdmull2_laneqv8hi (__a, __b,__c);
++  return __builtin_aarch64_uqsubdi_uuu (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_high_n_s16 (int16x8_t __a, int16_t __b)
++/* vqtbl2 */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl2_s8 (int8x16x2_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull2_nv8hi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[1], 1);
++  return __builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_lane_s16 (int16x4_t __a, int16x4_t __b, int const __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl2_u8 (uint8x16x2_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_lanev4hi (__a, __b, __c);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (uint8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_laneq_s16 (int16x4_t __a, int16x8_t __b, int const __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl2_p8 (poly8x16x2_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_laneqv4hi (__a, __b, __c);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (poly8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqdmull_n_s16 (int16x4_t __a, int16_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl2q_s8 (int8x16x2_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_nv4hi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return __builtin_aarch64_tbl3v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl2q_u8 (uint8x16x2_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmullv2si (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (uint8x16_t)__builtin_aarch64_tbl3v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_high_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl2q_p8 (poly8x16x2_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull2v4si (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (poly8x16_t)__builtin_aarch64_tbl3v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_high_lane_s32 (int32x4_t __a, int32x2_t __b, int const __c)
++/* vqtbl3 */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl3_s8 (int8x16x3_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull2_lanev4si (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return __builtin_aarch64_qtbl3v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_high_laneq_s32 (int32x4_t __a, int32x4_t __b, int const __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl3_u8 (uint8x16x3_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull2_laneqv4si (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (uint8x8_t)__builtin_aarch64_qtbl3v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_high_n_s32 (int32x4_t __a, int32_t __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl3_p8 (poly8x16x3_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull2_nv4si (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (poly8x8_t)__builtin_aarch64_qtbl3v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_lane_s32 (int32x2_t __a, int32x2_t __b, int const __c)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl3q_s8 (int8x16x3_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_lanev2si (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return __builtin_aarch64_qtbl3v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_laneq_s32 (int32x2_t __a, int32x4_t __b, int const __c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl3q_u8 (uint8x16x3_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_laneqv2si (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (uint8x16_t)__builtin_aarch64_qtbl3v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqdmull_n_s32 (int32x2_t __a, int32_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl3q_p8 (poly8x16x3_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_nv2si (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (poly8x16_t)__builtin_aarch64_qtbl3v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmullh_s16 (int16_t __a, int16_t __b)
++/* vqtbl4 */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl4_s8 (int8x16x4_t tab, uint8x8_t idx)
+ {
+-  return (int32_t) __builtin_aarch64_sqdmullhi (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return __builtin_aarch64_qtbl4v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmullh_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl4_u8 (uint8x16x4_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_lanehi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (uint8x8_t)__builtin_aarch64_qtbl4v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqdmullh_laneq_s16 (int16_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl4_p8 (poly8x16x4_t tab, uint8x8_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_laneqhi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (poly8x8_t)__builtin_aarch64_qtbl4v8qi (__o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmulls_s32 (int32_t __a, int32_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl4q_s8 (int8x16x4_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmullsi (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return __builtin_aarch64_qtbl4v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmulls_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl4q_u8 (uint8x16x4_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_lanesi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (uint8x16_t)__builtin_aarch64_qtbl4v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqdmulls_laneq_s32 (int32_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbl4q_p8 (poly8x16x4_t tab, uint8x16_t idx)
+ {
+-  return __builtin_aarch64_sqdmull_laneqsi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (poly8x16_t)__builtin_aarch64_qtbl4v16qi (__o, (int8x16_t)idx);
+ }
+ 
+-/* vqmovn */
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqmovn_s16 (int16x8_t __a)
++/* vqtbx2 */
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx2_s8 (int8x8_t r, int8x16x2_t tab, uint8x8_t idx)
+ {
+-  return (int8x8_t) __builtin_aarch64_sqmovnv8hi (__a);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[1], 1);
++  return __builtin_aarch64_tbx4v8qi (r, __o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqmovn_s32 (int32x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx2_u8 (uint8x8_t r, uint8x16x2_t tab, uint8x8_t idx)
+ {
+-  return (int16x4_t) __builtin_aarch64_sqmovnv4si (__a);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (uint8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)r, __o,
++						(int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqmovn_s64 (int64x2_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx2_p8 (poly8x8_t r, poly8x16x2_t tab, uint8x8_t idx)
+ {
+-  return (int32x2_t) __builtin_aarch64_sqmovnv2di (__a);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (poly8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)r, __o,
++						(int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqmovn_u16 (uint16x8_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx2q_s8 (int8x16_t r, int8x16x2_t tab, uint8x16_t idx)
+ {
+-  return (uint8x8_t) __builtin_aarch64_uqmovnv8hi ((int16x8_t) __a);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[1], 1);
++  return __builtin_aarch64_tbx4v16qi (r, __o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqmovn_u32 (uint32x4_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx2q_u8 (uint8x16_t r, uint8x16x2_t tab, uint8x16_t idx)
+ {
+-  return (uint16x4_t) __builtin_aarch64_uqmovnv4si ((int32x4_t) __a);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (uint8x16_t)__builtin_aarch64_tbx4v16qi ((int8x16_t)r, __o,
++						  (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqmovn_u64 (uint64x2_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx2q_p8 (poly8x16_t r, poly8x16x2_t tab, uint8x16_t idx)
+ {
+-  return (uint32x2_t) __builtin_aarch64_uqmovnv2di ((int64x2_t) __a);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  return (poly8x16_t)__builtin_aarch64_tbx4v16qi ((int8x16_t)r, __o,
++						  (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqmovnh_s16 (int16_t __a)
++/* vqtbx3 */
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx3_s8 (int8x8_t r, int8x16x3_t tab, uint8x8_t idx)
+ {
+-  return (int8_t) __builtin_aarch64_sqmovnhi (__a);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[2], 2);
++  return __builtin_aarch64_qtbx3v8qi (r, __o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqmovns_s32 (int32_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx3_u8 (uint8x8_t r, uint8x16x3_t tab, uint8x8_t idx)
+ {
+-  return (int16_t) __builtin_aarch64_sqmovnsi (__a);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (uint8x8_t)__builtin_aarch64_qtbx3v8qi ((int8x8_t)r, __o,
++						 (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqmovnd_s64 (int64_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx3_p8 (poly8x8_t r, poly8x16x3_t tab, uint8x8_t idx)
+ {
+-  return (int32_t) __builtin_aarch64_sqmovndi (__a);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (poly8x8_t)__builtin_aarch64_qtbx3v8qi ((int8x8_t)r, __o,
++						 (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqmovnh_u16 (uint16_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx3q_s8 (int8x16_t r, int8x16x3_t tab, uint8x16_t idx)
+ {
+-  return (uint8_t) __builtin_aarch64_uqmovnhi (__a);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[2], 2);
++  return __builtin_aarch64_qtbx3v16qi (r, __o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqmovns_u32 (uint32_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx3q_u8 (uint8x16_t r, uint8x16x3_t tab, uint8x16_t idx)
+ {
+-  return (uint16_t) __builtin_aarch64_uqmovnsi (__a);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (uint8x16_t)__builtin_aarch64_qtbx3v16qi ((int8x16_t)r, __o,
++						   (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqmovnd_u64 (uint64_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx3q_p8 (poly8x16_t r, poly8x16x3_t tab, uint8x16_t idx)
+ {
+-  return (uint32_t) __builtin_aarch64_uqmovndi (__a);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
++  return (poly8x16_t)__builtin_aarch64_qtbx3v16qi ((int8x16_t)r, __o,
++						   (int8x16_t)idx);
+ }
+ 
+-/* vqmovun */
++/* vqtbx4 */
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqmovun_s16 (int16x8_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx4_s8 (int8x8_t r, int8x16x4_t tab, uint8x8_t idx)
+ {
+-  return (uint8x8_t) __builtin_aarch64_sqmovunv8hi (__a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[3], 3);
++  return __builtin_aarch64_qtbx4v8qi (r, __o, (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqmovun_s32 (int32x4_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx4_u8 (uint8x8_t r, uint8x16x4_t tab, uint8x8_t idx)
+ {
+-  return (uint16x4_t) __builtin_aarch64_sqmovunv4si (__a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (uint8x8_t)__builtin_aarch64_qtbx4v8qi ((int8x8_t)r, __o,
++						 (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqmovun_s64 (int64x2_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx4_p8 (poly8x8_t r, poly8x16x4_t tab, uint8x8_t idx)
+ {
+-  return (uint32x2_t) __builtin_aarch64_sqmovunv2di (__a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (poly8x8_t)__builtin_aarch64_qtbx4v8qi ((int8x8_t)r, __o,
++						 (int8x8_t)idx);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqmovunh_s16 (int16_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx4q_s8 (int8x16_t r, int8x16x4_t tab, uint8x16_t idx)
+ {
+-  return (int8_t) __builtin_aarch64_sqmovunhi (__a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[3], 3);
++  return __builtin_aarch64_qtbx4v16qi (r, __o, (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqmovuns_s32 (int32_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx4q_u8 (uint8x16_t r, uint8x16x4_t tab, uint8x16_t idx)
+ {
+-  return (int16_t) __builtin_aarch64_sqmovunsi (__a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (uint8x16_t)__builtin_aarch64_qtbx4v16qi ((int8x16_t)r, __o,
++						   (int8x16_t)idx);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqmovund_s64 (int64_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vqtbx4q_p8 (poly8x16_t r, poly8x16x4_t tab, uint8x16_t idx)
+ {
+-  return (int32_t) __builtin_aarch64_sqmovundi (__a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
++  return (poly8x16_t)__builtin_aarch64_qtbx4v16qi ((int8x16_t)r, __o,
++						   (int8x16_t)idx);
+ }
+ 
+-/* vqneg */
++/* vrbit  */
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqnegq_s64 (int64x2_t __a)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrbit_p8 (poly8x8_t __a)
+ {
+-  return (int64x2_t) __builtin_aarch64_sqnegv2di (__a);
++  return (poly8x8_t) __builtin_aarch64_rbitv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqnegb_s8 (int8_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrbit_s8 (int8x8_t __a)
+ {
+-  return (int8_t) __builtin_aarch64_sqnegqi (__a);
++  return __builtin_aarch64_rbitv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqnegh_s16 (int16_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrbit_u8 (uint8x8_t __a)
+ {
+-  return (int16_t) __builtin_aarch64_sqneghi (__a);
++  return (uint8x8_t) __builtin_aarch64_rbitv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqnegs_s32 (int32_t __a)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrbitq_p8 (poly8x16_t __a)
+ {
+-  return (int32_t) __builtin_aarch64_sqnegsi (__a);
++  return (poly8x16_t) __builtin_aarch64_rbitv16qi ((int8x16_t)__a);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqnegd_s64 (int64_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrbitq_s8 (int8x16_t __a)
+ {
+-  return __builtin_aarch64_sqnegdi (__a);
++  return __builtin_aarch64_rbitv16qi (__a);
+ }
+ 
+-/* vqrdmulh */
+-
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrbitq_u8 (uint8x16_t __a)
+ {
+-  return  __builtin_aarch64_sqrdmulh_lanev4hi (__a, __b, __c);
++  return (uint8x16_t) __builtin_aarch64_rbitv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
++/* vrecpe  */
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpe_u32 (uint32x2_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_lanev2si (__a, __b, __c);
++  return (uint32x2_t) __builtin_aarch64_urecpev2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpeq_u32 (uint32x4_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_lanev8hi (__a, __b, __c);
++  return (uint32x4_t) __builtin_aarch64_urecpev4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpes_f32 (float32_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_lanev4si (__a, __b, __c);
++  return __builtin_aarch64_frecpesf (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmulhh_s16 (int16_t __a, int16_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecped_f64 (float64_t __a)
+ {
+-  return (int16_t) __builtin_aarch64_sqrdmulhhi (__a, __b);
++  return __builtin_aarch64_frecpedf (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmulhh_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpe_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_lanehi (__a, __b, __c);
++  return __builtin_aarch64_frecpev2sf (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrdmulhh_laneq_s16 (int16_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpe_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_laneqhi (__a, __b, __c);
++  return (float64x1_t) { vrecped_f64 (vget_lane_f64 (__a, 0)) };
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmulhs_s32 (int32_t __a, int32_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpeq_f32 (float32x4_t __a)
+ {
+-  return (int32_t) __builtin_aarch64_sqrdmulhsi (__a, __b);
++  return __builtin_aarch64_frecpev4sf (__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmulhs_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpeq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_sqrdmulh_lanesi (__a, __b, __c);
++  return __builtin_aarch64_frecpev2df (__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrdmulhs_laneq_s32 (int32_t __a, int32x4_t __b, const int __c)
++/* vrecps  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpss_f32 (float32_t __a, float32_t __b)
+ {
+-  return __builtin_aarch64_sqrdmulh_laneqsi (__a, __b, __c);
++  return __builtin_aarch64_frecpssf (__a, __b);
+ }
+ 
+-/* vqrshl */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqrshl_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpsd_f64 (float64_t __a, float64_t __b)
+ {
+-  return __builtin_aarch64_sqrshlv8qi (__a, __b);
++  return __builtin_aarch64_frecpsdf (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrshl_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecps_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return __builtin_aarch64_sqrshlv4hi (__a, __b);
++  return __builtin_aarch64_frecpsv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrshl_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecps_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  return __builtin_aarch64_sqrshlv2si (__a, __b);
++  return (float64x1_t) { vrecpsd_f64 (vget_lane_f64 (__a, 0),
++				      vget_lane_f64 (__b, 0)) };
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vqrshl_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpsq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  return (int64x1_t) {__builtin_aarch64_sqrshldi (__a[0], __b[0])};
++  return __builtin_aarch64_frecpsv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqrshl_u8 (uint8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpsq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  return __builtin_aarch64_uqrshlv8qi_uus ( __a, __b);
++  return __builtin_aarch64_frecpsv2df (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqrshl_u16 (uint16x4_t __a, int16x4_t __b)
++/* vrecpx  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpxs_f32 (float32_t __a)
+ {
+-  return __builtin_aarch64_uqrshlv4hi_uus ( __a, __b);
++  return __builtin_aarch64_frecpxsf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqrshl_u32 (uint32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpxd_f64 (float64_t __a)
+ {
+-  return __builtin_aarch64_uqrshlv2si_uus ( __a, __b);
++  return __builtin_aarch64_frecpxdf (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vqrshl_u64 (uint64x1_t __a, int64x1_t __b)
++
++/* vrev  */
++
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev16_p8 (poly8x8_t a)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_uqrshldi_uus (__a[0], __b[0])};
++  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqrshlq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev16_s8 (int8x8_t a)
+ {
+-  return __builtin_aarch64_sqrshlv16qi (__a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqrshlq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev16_u8 (uint8x8_t a)
+ {
+-  return __builtin_aarch64_sqrshlv8hi (__a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqrshlq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev16q_p8 (poly8x16_t a)
+ {
+-  return __builtin_aarch64_sqrshlv4si (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqrshlq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev16q_s8 (int8x16_t a)
+ {
+-  return __builtin_aarch64_sqrshlv2di (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqrshlq_u8 (uint8x16_t __a, int8x16_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev16q_u8 (uint8x16_t a)
+ {
+-  return __builtin_aarch64_uqrshlv16qi_uus ( __a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vqrshlq_u16 (uint16x8_t __a, int16x8_t __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32_p8 (poly8x8_t a)
+ {
+-  return __builtin_aarch64_uqrshlv8hi_uus ( __a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vqrshlq_u32 (uint32x4_t __a, int32x4_t __b)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32_p16 (poly16x4_t a)
+ {
+-  return __builtin_aarch64_uqrshlv4si_uus ( __a, __b);
++  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vqrshlq_u64 (uint64x2_t __a, int64x2_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32_s8 (int8x8_t a)
+ {
+-  return __builtin_aarch64_uqrshlv2di_uus ( __a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqrshlb_s8 (int8_t __a, int8_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32_s16 (int16x4_t a)
+ {
+-  return __builtin_aarch64_sqrshlqi (__a, __b);
++  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrshlh_s16 (int16_t __a, int16_t __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32_u8 (uint8x8_t a)
+ {
+-  return __builtin_aarch64_sqrshlhi (__a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrshls_s32 (int32_t __a, int32_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32_u16 (uint16x4_t a)
+ {
+-  return __builtin_aarch64_sqrshlsi (__a, __b);
++  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqrshld_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32q_p8 (poly8x16_t a)
+ {
+-  return __builtin_aarch64_sqrshldi (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqrshlb_u8 (uint8_t __a, uint8_t __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32q_p16 (poly16x8_t a)
+ {
+-  return __builtin_aarch64_uqrshlqi_uus (__a, __b);
++  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqrshlh_u16 (uint16_t __a, uint16_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32q_s8 (int8x16_t a)
+ {
+-  return __builtin_aarch64_uqrshlhi_uus (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqrshls_u32 (uint32_t __a, uint32_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32q_s16 (int16x8_t a)
+ {
+-  return __builtin_aarch64_uqrshlsi_uus (__a, __b);
++  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vqrshld_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32q_u8 (uint8x16_t a)
+ {
+-  return __builtin_aarch64_uqrshldi_uus (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
+ }
+ 
+-/* vqrshrn */
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev32q_u16 (uint16x8_t a)
++{
++  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqrshrn_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_f16 (float16x4_t __a)
+ {
+-  return (int8x8_t) __builtin_aarch64_sqrshrn_nv8hi (__a, __b);
++  return __builtin_shuffle (__a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqrshrn_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_f32 (float32x2_t a)
+ {
+-  return (int16x4_t) __builtin_aarch64_sqrshrn_nv4si (__a, __b);
++  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqrshrn_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_p8 (poly8x8_t a)
+ {
+-  return (int32x2_t) __builtin_aarch64_sqrshrn_nv2di (__a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqrshrn_n_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_p16 (poly16x4_t a)
+ {
+-  return __builtin_aarch64_uqrshrn_nv8hi_uus ( __a, __b);
++  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqrshrn_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_s8 (int8x8_t a)
+ {
+-  return __builtin_aarch64_uqrshrn_nv4si_uus ( __a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqrshrn_n_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_s16 (int16x4_t a)
+ {
+-  return __builtin_aarch64_uqrshrn_nv2di_uus ( __a, __b);
++  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqrshrnh_n_s16 (int16_t __a, const int __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_s32 (int32x2_t a)
+ {
+-  return (int8_t) __builtin_aarch64_sqrshrn_nhi (__a, __b);
++  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrshrns_n_s32 (int32_t __a, const int __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_u8 (uint8x8_t a)
+ {
+-  return (int16_t) __builtin_aarch64_sqrshrn_nsi (__a, __b);
++  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrshrnd_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_u16 (uint16x4_t a)
+ {
+-  return (int32_t) __builtin_aarch64_sqrshrn_ndi (__a, __b);
++  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqrshrnh_n_u16 (uint16_t __a, const int __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_u32 (uint32x2_t a)
+ {
+-  return __builtin_aarch64_uqrshrn_nhi_uus (__a, __b);
++  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqrshrns_n_u32 (uint32_t __a, const int __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_f16 (float16x8_t __a)
+ {
+-  return __builtin_aarch64_uqrshrn_nsi_uus (__a, __b);
++  return __builtin_shuffle (__a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqrshrnd_n_u64 (uint64_t __a, const int __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_f32 (float32x4_t a)
+ {
+-  return __builtin_aarch64_uqrshrn_ndi_uus (__a, __b);
++  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-/* vqrshrun */
+-
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqrshrun_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_p8 (poly8x16_t a)
+ {
+-  return (uint8x8_t) __builtin_aarch64_sqrshrun_nv8hi (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqrshrun_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_p16 (poly16x8_t a)
+ {
+-  return (uint16x4_t) __builtin_aarch64_sqrshrun_nv4si (__a, __b);
++  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqrshrun_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_s8 (int8x16_t a)
+ {
+-  return (uint32x2_t) __builtin_aarch64_sqrshrun_nv2di (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqrshrunh_n_s16 (int16_t __a, const int __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_s16 (int16x8_t a)
+ {
+-  return (int8_t) __builtin_aarch64_sqrshrun_nhi (__a, __b);
++  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqrshruns_n_s32 (int32_t __a, const int __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_s32 (int32x4_t a)
+ {
+-  return (int16_t) __builtin_aarch64_sqrshrun_nsi (__a, __b);
++  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqrshrund_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_u8 (uint8x16_t a)
+ {
+-  return (int32_t) __builtin_aarch64_sqrshrun_ndi (__a, __b);
++  return __builtin_shuffle (a,
++      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
+ }
+ 
+-/* vqshl */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqshl_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_u16 (uint16x8_t a)
+ {
+-  return __builtin_aarch64_sqshlv8qi (__a, __b);
++  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqshl_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_u32 (uint32x4_t a)
+ {
+-  return __builtin_aarch64_sqshlv4hi (__a, __b);
++  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqshl_s32 (int32x2_t __a, int32x2_t __b)
++/* vrnd  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrnd_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_sqshlv2si (__a, __b);
++  return __builtin_aarch64_btruncv2sf (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vqshl_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrnd_f64 (float64x1_t __a)
+ {
+-  return (int64x1_t) {__builtin_aarch64_sqshldi (__a[0], __b[0])};
++  return vset_lane_f64 (__builtin_trunc (vget_lane_f64 (__a, 0)), __a, 0);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqshl_u8 (uint8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_uqshlv8qi_uus ( __a, __b);
++  return __builtin_aarch64_btruncv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqshl_u16 (uint16x4_t __a, int16x4_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_uqshlv4hi_uus ( __a, __b);
++  return __builtin_aarch64_btruncv2df (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqshl_u32 (uint32x2_t __a, int32x2_t __b)
++/* vrnda  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrnda_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_uqshlv2si_uus ( __a, __b);
++  return __builtin_aarch64_roundv2sf (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vqshl_u64 (uint64x1_t __a, int64x1_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrnda_f64 (float64x1_t __a)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_uqshldi_uus (__a[0], __b[0])};
++  return vset_lane_f64 (__builtin_round (vget_lane_f64 (__a, 0)), __a, 0);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqshlq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndaq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_sqshlv16qi (__a, __b);
++  return __builtin_aarch64_roundv4sf (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqshlq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndaq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_sqshlv8hi (__a, __b);
++  return __builtin_aarch64_roundv2df (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqshlq_s32 (int32x4_t __a, int32x4_t __b)
++/* vrndi  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndi_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_sqshlv4si (__a, __b);
++  return __builtin_aarch64_nearbyintv2sf (__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqshlq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndi_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_sqshlv2di (__a, __b);
++  return vset_lane_f64 (__builtin_nearbyint (vget_lane_f64 (__a, 0)), __a, 0);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqshlq_u8 (uint8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndiq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_uqshlv16qi_uus ( __a, __b);
++  return __builtin_aarch64_nearbyintv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vqshlq_u16 (uint16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndiq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_uqshlv8hi_uus ( __a, __b);
++  return __builtin_aarch64_nearbyintv2df (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vqshlq_u32 (uint32x4_t __a, int32x4_t __b)
++/* vrndm  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndm_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_uqshlv4si_uus ( __a, __b);
++  return __builtin_aarch64_floorv2sf (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vqshlq_u64 (uint64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndm_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_uqshlv2di_uus ( __a, __b);
++  return vset_lane_f64 (__builtin_floor (vget_lane_f64 (__a, 0)), __a, 0);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqshlb_s8 (int8_t __a, int8_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndmq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_sqshlqi (__a, __b);
++  return __builtin_aarch64_floorv4sf (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqshlh_s16 (int16_t __a, int16_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndmq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_sqshlhi (__a, __b);
++  return __builtin_aarch64_floorv2df (__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqshls_s32 (int32_t __a, int32_t __b)
++/* vrndn  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndn_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_sqshlsi (__a, __b);
++  return __builtin_aarch64_frintnv2sf (__a);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqshld_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndn_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_sqshldi (__a, __b);
++  return (float64x1_t) {__builtin_aarch64_frintndf (__a[0])};
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqshlb_u8 (uint8_t __a, uint8_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndnq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_uqshlqi_uus (__a, __b);
++  return __builtin_aarch64_frintnv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqshlh_u16 (uint16_t __a, uint16_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndnq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_uqshlhi_uus (__a, __b);
++  return __builtin_aarch64_frintnv2df (__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqshls_u32 (uint32_t __a, uint32_t __b)
++/* vrndp  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndp_f32 (float32x2_t __a)
+ {
+-  return __builtin_aarch64_uqshlsi_uus (__a, __b);
++  return __builtin_aarch64_ceilv2sf (__a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vqshld_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndp_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_uqshldi_uus (__a, __b);
++  return vset_lane_f64 (__builtin_ceil (vget_lane_f64 (__a, 0)), __a, 0);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqshl_n_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndpq_f32 (float32x4_t __a)
+ {
+-  return (int8x8_t) __builtin_aarch64_sqshl_nv8qi (__a, __b);
++  return __builtin_aarch64_ceilv4sf (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqshl_n_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndpq_f64 (float64x2_t __a)
+ {
+-  return (int16x4_t) __builtin_aarch64_sqshl_nv4hi (__a, __b);
++  return __builtin_aarch64_ceilv2df (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqshl_n_s32 (int32x2_t __a, const int __b)
++/* vrndx  */
++
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndx_f32 (float32x2_t __a)
+ {
+-  return (int32x2_t) __builtin_aarch64_sqshl_nv2si (__a, __b);
++  return __builtin_aarch64_rintv2sf (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vqshl_n_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndx_f64 (float64x1_t __a)
+ {
+-  return (int64x1_t) {__builtin_aarch64_sqshl_ndi (__a[0], __b)};
++  return vset_lane_f64 (__builtin_rint (vget_lane_f64 (__a, 0)), __a, 0);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqshl_n_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndxq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_uqshl_nv8qi_uus (__a, __b);
++  return __builtin_aarch64_rintv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqshl_n_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndxq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_uqshl_nv4hi_uus (__a, __b);
++  return __builtin_aarch64_rintv2df (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqshl_n_u32 (uint32x2_t __a, const int __b)
++/* vrshl */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nv2si_uus (__a, __b);
++  return (int8x8_t) __builtin_aarch64_srshlv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vqshl_n_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_uqshl_ndi_uus (__a[0], __b)};
++  return (int16x4_t) __builtin_aarch64_srshlv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqshlq_n_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return (int8x16_t) __builtin_aarch64_sqshl_nv16qi (__a, __b);
++  return (int32x2_t) __builtin_aarch64_srshlv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vqshlq_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  return (int16x8_t) __builtin_aarch64_sqshl_nv8hi (__a, __b);
++  return (int64x1_t) {__builtin_aarch64_srshldi (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vqshlq_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+-  return (int32x4_t) __builtin_aarch64_sqshl_nv4si (__a, __b);
++  return __builtin_aarch64_urshlv8qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vqshlq_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+-  return (int64x2_t) __builtin_aarch64_sqshl_nv2di (__a, __b);
++  return __builtin_aarch64_urshlv4hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqshlq_n_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nv16qi_uus (__a, __b);
++  return __builtin_aarch64_urshlv2si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vqshlq_n_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nv8hi_uus (__a, __b);
++  return (uint64x1_t) {__builtin_aarch64_urshldi_uus (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vqshlq_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nv4si_uus (__a, __b);
++  return (int8x16_t) __builtin_aarch64_srshlv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vqshlq_n_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nv2di_uus (__a, __b);
++  return (int16x8_t) __builtin_aarch64_srshlv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqshlb_n_s8 (int8_t __a, const int __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  return (int8_t) __builtin_aarch64_sqshl_nqi (__a, __b);
++  return (int32x4_t) __builtin_aarch64_srshlv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqshlh_n_s16 (int16_t __a, const int __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  return (int16_t) __builtin_aarch64_sqshl_nhi (__a, __b);
++  return (int64x2_t) __builtin_aarch64_srshlv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqshls_n_s32 (int32_t __a, const int __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+-  return (int32_t) __builtin_aarch64_sqshl_nsi (__a, __b);
++  return __builtin_aarch64_urshlv16qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqshld_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+-  return __builtin_aarch64_sqshl_ndi (__a, __b);
++  return __builtin_aarch64_urshlv8hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqshlb_n_u8 (uint8_t __a, const int __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nqi_uus (__a, __b);
++  return __builtin_aarch64_urshlv4si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqshlh_n_u16 (uint16_t __a, const int __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nhi_uus (__a, __b);
++  return __builtin_aarch64_urshlv2di_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqshls_n_u32 (uint32_t __a, const int __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshld_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_uqshl_nsi_uus (__a, __b);
++  return __builtin_aarch64_srshldi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vqshld_n_u64 (uint64_t __a, const int __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshld_u64 (uint64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_uqshl_ndi_uus (__a, __b);
++  return __builtin_aarch64_urshldi_uus (__a, __b);
+ }
+ 
+-/* vqshlu */
++/* vrshr */
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqshlu_n_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_s8 (int8x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv8qi_uss (__a, __b);
++  return (int8x8_t) __builtin_aarch64_srshr_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqshlu_n_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_s16 (int16x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv4hi_uss (__a, __b);
++  return (int16x4_t) __builtin_aarch64_srshr_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqshlu_n_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_s32 (int32x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv2si_uss (__a, __b);
++  return (int32x2_t) __builtin_aarch64_srshr_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vqshlu_n_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_s64 (int64x1_t __a, const int __b)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_sqshlu_ndi_uss (__a[0], __b)};
++  return (int64x1_t) {__builtin_aarch64_srshr_ndi (__a[0], __b)};
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqshluq_n_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_u8 (uint8x8_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv16qi_uss (__a, __b);
++  return __builtin_aarch64_urshr_nv8qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vqshluq_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_u16 (uint16x4_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv8hi_uss (__a, __b);
++  return __builtin_aarch64_urshr_nv4hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vqshluq_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_u32 (uint32x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv4si_uss (__a, __b);
++  return __builtin_aarch64_urshr_nv2si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vqshluq_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshr_n_u64 (uint64x1_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_nv2di_uss (__a, __b);
++  return (uint64x1_t) {__builtin_aarch64_urshr_ndi_uus (__a[0], __b)};
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqshlub_n_s8 (int8_t __a, const int __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_s8 (int8x16_t __a, const int __b)
+ {
+-  return (int8_t) __builtin_aarch64_sqshlu_nqi_uss (__a, __b);
++  return (int8x16_t) __builtin_aarch64_srshr_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqshluh_n_s16 (int16_t __a, const int __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return (int16_t) __builtin_aarch64_sqshlu_nhi_uss (__a, __b);
++  return (int16x8_t) __builtin_aarch64_srshr_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqshlus_n_s32 (int32_t __a, const int __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return (int32_t) __builtin_aarch64_sqshlu_nsi_uss (__a, __b);
++  return (int32x4_t) __builtin_aarch64_srshr_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vqshlud_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_sqshlu_ndi_uss (__a, __b);
++  return (int64x2_t) __builtin_aarch64_srshr_nv2di (__a, __b);
+ }
+ 
+-/* vqshrn */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqshrn_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_u8 (uint8x16_t __a, const int __b)
+ {
+-  return (int8x8_t) __builtin_aarch64_sqshrn_nv8hi (__a, __b);
++  return __builtin_aarch64_urshr_nv16qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vqshrn_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  return (int16x4_t) __builtin_aarch64_sqshrn_nv4si (__a, __b);
++  return __builtin_aarch64_urshr_nv8hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vqshrn_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  return (int32x2_t) __builtin_aarch64_sqshrn_nv2di (__a, __b);
++  return __builtin_aarch64_urshr_nv4si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqshrn_n_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrq_n_u64 (uint64x2_t __a, const int __b)
+ {
+-  return __builtin_aarch64_uqshrn_nv8hi_uus ( __a, __b);
++  return __builtin_aarch64_urshr_nv2di_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqshrn_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrd_n_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_uqshrn_nv4si_uus ( __a, __b);
++  return __builtin_aarch64_srshr_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqshrn_n_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrshrd_n_u64 (uint64_t __a, const int __b)
+ {
+-  return __builtin_aarch64_uqshrn_nv2di_uus ( __a, __b);
++  return __builtin_aarch64_urshr_ndi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqshrnh_n_s16 (int16_t __a, const int __b)
++/* vrsqrte.  */
++
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtes_f32 (float32_t __a)
+ {
+-  return (int8_t) __builtin_aarch64_sqshrn_nhi (__a, __b);
++  return __builtin_aarch64_rsqrtesf (__a);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqshrns_n_s32 (int32_t __a, const int __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrted_f64 (float64_t __a)
+ {
+-  return (int16_t) __builtin_aarch64_sqshrn_nsi (__a, __b);
++  return __builtin_aarch64_rsqrtedf (__a);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqshrnd_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrte_f32 (float32x2_t __a)
+ {
+-  return (int32_t) __builtin_aarch64_sqshrn_ndi (__a, __b);
++  return __builtin_aarch64_rsqrtev2sf (__a);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqshrnh_n_u16 (uint16_t __a, const int __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrte_f64 (float64x1_t __a)
+ {
+-  return __builtin_aarch64_uqshrn_nhi_uus (__a, __b);
++  return (float64x1_t) {vrsqrted_f64 (vget_lane_f64 (__a, 0))};
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqshrns_n_u32 (uint32_t __a, const int __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrteq_f32 (float32x4_t __a)
+ {
+-  return __builtin_aarch64_uqshrn_nsi_uus (__a, __b);
++  return __builtin_aarch64_rsqrtev4sf (__a);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqshrnd_n_u64 (uint64_t __a, const int __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrteq_f64 (float64x2_t __a)
+ {
+-  return __builtin_aarch64_uqshrn_ndi_uus (__a, __b);
++  return __builtin_aarch64_rsqrtev2df (__a);
+ }
+ 
+-/* vqshrun */
++/* vrsqrts.  */
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqshrun_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline float32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtss_f32 (float32_t __a, float32_t __b)
+ {
+-  return (uint8x8_t) __builtin_aarch64_sqshrun_nv8hi (__a, __b);
++  return __builtin_aarch64_rsqrtssf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vqshrun_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline float64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtsd_f64 (float64_t __a, float64_t __b)
+ {
+-  return (uint16x4_t) __builtin_aarch64_sqshrun_nv4si (__a, __b);
++  return __builtin_aarch64_rsqrtsdf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vqshrun_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrts_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return (uint32x2_t) __builtin_aarch64_sqshrun_nv2di (__a, __b);
++  return __builtin_aarch64_rsqrtsv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqshrunh_n_s16 (int16_t __a, const int __b)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrts_f64 (float64x1_t __a, float64x1_t __b)
+ {
+-  return (int8_t) __builtin_aarch64_sqshrun_nhi (__a, __b);
++  return (float64x1_t) {vrsqrtsd_f64 (vget_lane_f64 (__a, 0),
++				      vget_lane_f64 (__b, 0))};
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqshruns_n_s32 (int32_t __a, const int __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtsq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  return (int16_t) __builtin_aarch64_sqshrun_nsi (__a, __b);
++  return __builtin_aarch64_rsqrtsv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqshrund_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtsq_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  return (int32_t) __builtin_aarch64_sqshrun_ndi (__a, __b);
++  return __builtin_aarch64_rsqrtsv2df (__a, __b);
+ }
+ 
+-/* vqsub */
++/* vrsra */
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vqsubb_s8 (int8_t __a, int8_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+-  return (int8_t) __builtin_aarch64_sqsubqi (__a, __b);
++  return (int8x8_t) __builtin_aarch64_srsra_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vqsubh_s16 (int16_t __a, int16_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+-  return (int16_t) __builtin_aarch64_sqsubhi (__a, __b);
++  return (int16x4_t) __builtin_aarch64_srsra_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vqsubs_s32 (int32_t __a, int32_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+-  return (int32_t) __builtin_aarch64_sqsubsi (__a, __b);
++  return (int32x2_t) __builtin_aarch64_srsra_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vqsubd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+-  return __builtin_aarch64_sqsubdi (__a, __b);
++  return (int64x1_t) {__builtin_aarch64_srsra_ndi (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vqsubb_u8 (uint8_t __a, uint8_t __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+-  return (uint8_t) __builtin_aarch64_uqsubqi_uuu (__a, __b);
++  return __builtin_aarch64_ursra_nv8qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vqsubh_u16 (uint16_t __a, uint16_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+-  return (uint16_t) __builtin_aarch64_uqsubhi_uuu (__a, __b);
++  return __builtin_aarch64_ursra_nv4hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vqsubs_u32 (uint32_t __a, uint32_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+-  return (uint32_t) __builtin_aarch64_uqsubsi_uuu (__a, __b);
++  return __builtin_aarch64_ursra_nv2si_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vqsubd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+-  return __builtin_aarch64_uqsubdi_uuu (__a, __b);
++  return (uint64x1_t) {__builtin_aarch64_ursra_ndi_uuus (__a[0], __b[0], __c)};
+ }
+ 
+-/* vqtbl2 */
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
++{
++  return (int8x16_t) __builtin_aarch64_srsra_nv16qi (__a, __b, __c);
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbl2_s8 (int8x16x2_t tab, uint8x8_t idx)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[1], 1);
+-  return __builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return (int16x8_t) __builtin_aarch64_srsra_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbl2_u8 (uint8x16x2_t tab, uint8x8_t idx)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (uint8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return (int32x4_t) __builtin_aarch64_srsra_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbl2_p8 (poly8x16x2_t tab, uint8x8_t idx)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (poly8x8_t)__builtin_aarch64_tbl3v8qi (__o, (int8x8_t)idx);
++  return (int64x2_t) __builtin_aarch64_srsra_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbl2q_s8 (int8x16x2_t tab, uint8x16_t idx)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return __builtin_aarch64_tbl3v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_ursra_nv16qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbl2q_u8 (uint8x16x2_t tab, uint8x16_t idx)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (uint8x16_t)__builtin_aarch64_tbl3v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_ursra_nv8hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbl2q_p8 (poly8x16x2_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (poly8x16_t)__builtin_aarch64_tbl3v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_ursra_nv4si_uuus (__a, __b, __c);
+ }
+ 
+-/* vqtbl3 */
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
++{
++  return __builtin_aarch64_ursra_nv2di_uuus (__a, __b, __c);
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbl3_s8 (int8x16x3_t tab, uint8x8_t idx)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsrad_n_s64 (int64_t __a, int64_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return __builtin_aarch64_qtbl3v8qi (__o, (int8x8_t)idx);
++  return __builtin_aarch64_srsra_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbl3_u8 (uint8x16x3_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsrad_n_u64 (uint64_t __a, uint64_t __b, const int __c)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (uint8x8_t)__builtin_aarch64_qtbl3v8qi (__o, (int8x8_t)idx);
++  return __builtin_aarch64_ursra_ndi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbl3_p8 (poly8x16x3_t tab, uint8x8_t idx)
++#pragma GCC push_options
++#pragma GCC target ("+nothing+crypto")
++
++/* vsha1  */
++
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha1cq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (poly8x8_t)__builtin_aarch64_qtbl3v8qi (__o, (int8x8_t)idx);
++  return __builtin_aarch64_crypto_sha1cv4si_uuuu (hash_abcd, hash_e, wk);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbl3q_s8 (int8x16x3_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha1mq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return __builtin_aarch64_qtbl3v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_crypto_sha1mv4si_uuuu (hash_abcd, hash_e, wk);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbl3q_u8 (uint8x16x3_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha1pq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (uint8x16_t)__builtin_aarch64_qtbl3v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_crypto_sha1pv4si_uuuu (hash_abcd, hash_e, wk);
++}
++
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha1h_u32 (uint32_t hash_e)
++{
++  return __builtin_aarch64_crypto_sha1hsi_uu (hash_e);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbl3q_p8 (poly8x16x3_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha1su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (poly8x16_t)__builtin_aarch64_qtbl3v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_crypto_sha1su0v4si_uuuu (w0_3, w4_7, w8_11);
+ }
+ 
+-/* vqtbl4 */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbl4_s8 (int8x16x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha1su1q_u32 (uint32x4_t tw0_3, uint32x4_t w12_15)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return __builtin_aarch64_qtbl4v8qi (__o, (int8x8_t)idx);
++  return __builtin_aarch64_crypto_sha1su1v4si_uuu (tw0_3, w12_15);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbl4_u8 (uint8x16x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha256hq_u32 (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (uint8x8_t)__builtin_aarch64_qtbl4v8qi (__o, (int8x8_t)idx);
++  return __builtin_aarch64_crypto_sha256hv4si_uuuu (hash_abcd, hash_efgh, wk);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbl4_p8 (poly8x16x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha256h2q_u32 (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (poly8x8_t)__builtin_aarch64_qtbl4v8qi (__o, (int8x8_t)idx);
++  return __builtin_aarch64_crypto_sha256h2v4si_uuuu (hash_efgh, hash_abcd, wk);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbl4q_s8 (int8x16x4_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha256su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return __builtin_aarch64_qtbl4v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_crypto_sha256su0v4si_uuu (w0_3, w4_7);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbl4q_u8 (uint8x16x4_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (uint8x16_t)__builtin_aarch64_qtbl4v16qi (__o, (int8x16_t)idx);
++  return __builtin_aarch64_crypto_sha256su1v4si_uuuu (tw0_3, w8_11, w12_15);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbl4q_p8 (poly8x16x4_t tab, uint8x16_t idx)
++__extension__ extern __inline poly128_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_p64 (poly64_t a, poly64_t b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (poly8x16_t)__builtin_aarch64_qtbl4v16qi (__o, (int8x16_t)idx);
++  return
++    __builtin_aarch64_crypto_pmulldi_ppp (a, b);
+ }
+ 
+-
+-/* vqtbx2 */
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbx2_s8 (int8x8_t r, int8x16x2_t tab, uint8x8_t idx)
++__extension__ extern __inline poly128_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmull_high_p64 (poly64x2_t a, poly64x2_t b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[1], 1);
+-  return __builtin_aarch64_tbx4v8qi (r, __o, (int8x8_t)idx);
++  return __builtin_aarch64_crypto_pmullv2di_ppp (a, b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbx2_u8 (uint8x8_t r, uint8x16x2_t tab, uint8x8_t idx)
++#pragma GCC pop_options
++
++/* vshl */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_s8 (int8x8_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (uint8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)r, __o,
+-						(int8x8_t)idx);
++  return (int8x8_t) __builtin_aarch64_ashlv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbx2_p8 (poly8x8_t r, poly8x16x2_t tab, uint8x8_t idx)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_s16 (int16x4_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (poly8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)r, __o,
+-						(int8x8_t)idx);
++  return (int16x4_t) __builtin_aarch64_ashlv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbx2q_s8 (int8x16_t r, int8x16x2_t tab, uint8x16_t idx)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_s32 (int32x2_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, tab.val[1], 1);
+-  return __builtin_aarch64_tbx4v16qi (r, __o, (int8x16_t)idx);
++  return (int32x2_t) __builtin_aarch64_ashlv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbx2q_u8 (uint8x16_t r, uint8x16x2_t tab, uint8x16_t idx)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_s64 (int64x1_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (uint8x16_t)__builtin_aarch64_tbx4v16qi ((int8x16_t)r, __o,
+-						  (int8x16_t)idx);
++  return (int64x1_t) {__builtin_aarch64_ashldi (__a[0], __b)};
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbx2q_p8 (poly8x16_t r, poly8x16x2_t tab, uint8x16_t idx)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_u8 (uint8x8_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  return (poly8x16_t)__builtin_aarch64_tbx4v16qi ((int8x16_t)r, __o,
+-						  (int8x16_t)idx);
++  return (uint8x8_t) __builtin_aarch64_ashlv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-/* vqtbx3 */
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbx3_s8 (int8x8_t r, int8x16x3_t tab, uint8x8_t idx)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_u16 (uint16x4_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[2], 2);
+-  return __builtin_aarch64_qtbx3v8qi (r, __o, (int8x8_t)idx);
++  return (uint16x4_t) __builtin_aarch64_ashlv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbx3_u8 (uint8x8_t r, uint8x16x3_t tab, uint8x8_t idx)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_u32 (uint32x2_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (uint8x8_t)__builtin_aarch64_qtbx3v8qi ((int8x8_t)r, __o,
+-						 (int8x8_t)idx);
++  return (uint32x2_t) __builtin_aarch64_ashlv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbx3_p8 (poly8x8_t r, poly8x16x3_t tab, uint8x8_t idx)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_n_u64 (uint64x1_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (poly8x8_t)__builtin_aarch64_qtbx3v8qi ((int8x8_t)r, __o,
+-						 (int8x8_t)idx);
++  return (uint64x1_t) {__builtin_aarch64_ashldi ((int64_t) __a[0], __b)};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbx3q_s8 (int8x16_t r, int8x16x3_t tab, uint8x16_t idx)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_s8 (int8x16_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, tab.val[2], 2);
+-  return __builtin_aarch64_qtbx3v16qi (r, __o, (int8x16_t)idx);
++  return (int8x16_t) __builtin_aarch64_ashlv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbx3q_u8 (uint8x16_t r, uint8x16x3_t tab, uint8x16_t idx)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_s16 (int16x8_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (uint8x16_t)__builtin_aarch64_qtbx3v16qi ((int8x16_t)r, __o,
+-						   (int8x16_t)idx);
++  return (int16x8_t) __builtin_aarch64_ashlv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbx3q_p8 (poly8x16_t r, poly8x16x3_t tab, uint8x16_t idx)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_s32 (int32x4_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  return (poly8x16_t)__builtin_aarch64_qtbx3v16qi ((int8x16_t)r, __o,
+-						   (int8x16_t)idx);
++  return (int32x4_t) __builtin_aarch64_ashlv4si (__a, __b);
+ }
+ 
+-/* vqtbx4 */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vqtbx4_s8 (int8x8_t r, int8x16x4_t tab, uint8x8_t idx)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_s64 (int64x2_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[3], 3);
+-  return __builtin_aarch64_qtbx4v8qi (r, __o, (int8x8_t)idx);
++  return (int64x2_t) __builtin_aarch64_ashlv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vqtbx4_u8 (uint8x8_t r, uint8x16x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_u8 (uint8x16_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (uint8x8_t)__builtin_aarch64_qtbx4v8qi ((int8x8_t)r, __o,
+-						 (int8x8_t)idx);
++  return (uint8x16_t) __builtin_aarch64_ashlv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vqtbx4_p8 (poly8x8_t r, poly8x16x4_t tab, uint8x8_t idx)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (poly8x8_t)__builtin_aarch64_qtbx4v8qi ((int8x8_t)r, __o,
+-						 (int8x8_t)idx);
++  return (uint16x8_t) __builtin_aarch64_ashlv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vqtbx4q_s8 (int8x16_t r, int8x16x4_t tab, uint8x16_t idx)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, tab.val[3], 3);
+-  return __builtin_aarch64_qtbx4v16qi (r, __o, (int8x16_t)idx);
++  return (uint32x4_t) __builtin_aarch64_ashlv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vqtbx4q_u8 (uint8x16_t r, uint8x16x4_t tab, uint8x16_t idx)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_n_u64 (uint64x2_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (uint8x16_t)__builtin_aarch64_qtbx4v16qi ((int8x16_t)r, __o,
+-						   (int8x16_t)idx);
++  return (uint64x2_t) __builtin_aarch64_ashlv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vqtbx4q_p8 (poly8x16_t r, poly8x16x4_t tab, uint8x16_t idx)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshld_n_s64 (int64_t __a, const int __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t)tab.val[3], 3);
+-  return (poly8x16_t)__builtin_aarch64_qtbx4v16qi ((int8x16_t)r, __o,
+-						   (int8x16_t)idx);
++  return __builtin_aarch64_ashldi (__a, __b);
+ }
+ 
+-/* vrbit  */
+-
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vrbit_p8 (poly8x8_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshld_n_u64 (uint64_t __a, const int __b)
+ {
+-  return (poly8x8_t) __builtin_aarch64_rbitv8qi ((int8x8_t) __a);
++  return (uint64_t) __builtin_aarch64_ashldi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrbit_s8 (int8x8_t __a)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return __builtin_aarch64_rbitv8qi (__a);
++  return __builtin_aarch64_sshlv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrbit_u8 (uint8x8_t __a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return (uint8x8_t) __builtin_aarch64_rbitv8qi ((int8x8_t) __a);
++  return __builtin_aarch64_sshlv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vrbitq_p8 (poly8x16_t __a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return (poly8x16_t) __builtin_aarch64_rbitv16qi ((int8x16_t)__a);
++  return __builtin_aarch64_sshlv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrbitq_s8 (int8x16_t __a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  return __builtin_aarch64_rbitv16qi (__a);
++  return (int64x1_t) {__builtin_aarch64_sshldi (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrbitq_u8 (uint8x16_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+-  return (uint8x16_t) __builtin_aarch64_rbitv16qi ((int8x16_t) __a);
++  return __builtin_aarch64_ushlv8qi_uus (__a, __b);
+ }
+ 
+-/* vrecpe  */
+-
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vrecpe_u32 (uint32x2_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+-  return (uint32x2_t) __builtin_aarch64_urecpev2si ((int32x2_t) __a);
++  return __builtin_aarch64_ushlv4hi_uus (__a, __b);
+ }
+- 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vrecpeq_u32 (uint32x4_t __a)
++
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+-  return (uint32x4_t) __builtin_aarch64_urecpev4si ((int32x4_t) __a);
++  return __builtin_aarch64_ushlv2si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vrecpes_f32 (float32_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+-  return __builtin_aarch64_frecpesf (__a);
++  return (uint64x1_t) {__builtin_aarch64_ushldi_uus (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vrecped_f64 (float64_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  return __builtin_aarch64_frecpedf (__a);
++  return __builtin_aarch64_sshlv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrecpe_f32 (float32x2_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  return __builtin_aarch64_frecpev2sf (__a);
++  return __builtin_aarch64_sshlv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrecpeq_f32 (float32x4_t __a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  return __builtin_aarch64_frecpev4sf (__a);
++  return __builtin_aarch64_sshlv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrecpeq_f64 (float64x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  return __builtin_aarch64_frecpev2df (__a);
++  return __builtin_aarch64_sshlv2di (__a, __b);
+ }
+ 
+-/* vrecps  */
+-
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vrecpss_f32 (float32_t __a, float32_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+-  return __builtin_aarch64_frecpssf (__a, __b);
++  return __builtin_aarch64_ushlv16qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vrecpsd_f64 (float64_t __a, float64_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+-  return __builtin_aarch64_frecpsdf (__a, __b);
++  return __builtin_aarch64_ushlv8hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrecps_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+-  return __builtin_aarch64_frecpsv2sf (__a, __b);
++  return __builtin_aarch64_ushlv4si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrecpsq_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+-  return __builtin_aarch64_frecpsv4sf (__a, __b);
++  return __builtin_aarch64_ushlv2di_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrecpsq_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshld_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_frecpsv2df (__a, __b);
++  return __builtin_aarch64_sshldi (__a, __b);
+ }
+ 
+-/* vrecpx  */
+-
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+-vrecpxs_f32 (float32_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshld_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return __builtin_aarch64_frecpxsf (__a);
++  return __builtin_aarch64_ushldi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+-vrecpxd_f64 (float64_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_high_n_s8 (int8x16_t __a, const int __b)
+ {
+-  return __builtin_aarch64_frecpxdf (__a);
++  return __builtin_aarch64_sshll2_nv16qi (__a, __b);
+ }
+ 
+-
+-/* vrev  */
+-
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vrev16_p8 (poly8x8_t a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_high_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++  return __builtin_aarch64_sshll2_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrev16_s8 (int8x8_t a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_high_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++  return __builtin_aarch64_sshll2_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrev16_u8 (uint8x8_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_high_n_u8 (uint8x16_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++  return (uint16x8_t) __builtin_aarch64_ushll2_nv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vrev16q_p8 (poly8x16_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_high_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
++  return (uint32x4_t) __builtin_aarch64_ushll2_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrev16q_s8 (int8x16_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_high_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
++  return (uint64x2_t) __builtin_aarch64_ushll2_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrev16q_u8 (uint8x16_t a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_n_s8 (int8x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
++  return __builtin_aarch64_sshll_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vrev32_p8 (poly8x8_t a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_n_s16 (int16x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
++  return __builtin_aarch64_sshll_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vrev32_p16 (poly16x4_t a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_n_s32 (int32x2_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
++  return __builtin_aarch64_sshll_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrev32_s8 (int8x8_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_n_u8 (uint8x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
++  return __builtin_aarch64_ushll_nv8qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vrev32_s16 (int16x4_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_n_u16 (uint16x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
++  return __builtin_aarch64_ushll_nv4hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrev32_u8 (uint8x8_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshll_n_u32 (uint32x2_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
++  return __builtin_aarch64_ushll_nv2si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vrev32_u16 (uint16x4_t a)
++/* vshr */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_s8 (int8x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x4_t) { 1, 0, 3, 2 });
++  return (int8x8_t) __builtin_aarch64_ashrv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vrev32q_p8 (poly8x16_t a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_s16 (int16x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
++  return (int16x4_t) __builtin_aarch64_ashrv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vrev32q_p16 (poly16x8_t a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_s32 (int32x2_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++  return (int32x2_t) __builtin_aarch64_ashrv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrev32q_s8 (int8x16_t a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_s64 (int64x1_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
++  return (int64x1_t) {__builtin_aarch64_ashr_simddi (__a[0], __b)};
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vrev32q_s16 (int16x8_t a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_u8 (uint8x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++  return (uint8x8_t) __builtin_aarch64_lshrv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrev32q_u8 (uint8x16_t a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_u16 (uint16x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
++  return (uint16x4_t) __builtin_aarch64_lshrv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vrev32q_u16 (uint16x8_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_u32 (uint32x2_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
++  return (uint32x2_t) __builtin_aarch64_lshrv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrev64_f32 (float32x2_t a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshr_n_u64 (uint64x1_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
++  return (uint64x1_t) {__builtin_aarch64_lshr_simddi_uus ( __a[0], __b)};
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vrev64_p8 (poly8x8_t a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_s8 (int8x16_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
++  return (int8x16_t) __builtin_aarch64_ashrv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vrev64_p16 (poly16x4_t a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_s16 (int16x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
++  return (int16x8_t) __builtin_aarch64_ashrv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrev64_s8 (int8x8_t a)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_s32 (int32x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
++  return (int32x4_t) __builtin_aarch64_ashrv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vrev64_s16 (int16x4_t a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_s64 (int64x2_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
++  return (int64x2_t) __builtin_aarch64_ashrv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vrev64_s32 (int32x2_t a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_u8 (uint8x16_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
++  return (uint8x16_t) __builtin_aarch64_lshrv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrev64_u8 (uint8x8_t a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_u16 (uint16x8_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
++  return (uint16x8_t) __builtin_aarch64_lshrv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vrev64_u16 (uint16x4_t a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_u32 (uint32x4_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint16x4_t) { 3, 2, 1, 0 });
++  return (uint32x4_t) __builtin_aarch64_lshrv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vrev64_u32 (uint32x2_t a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrq_n_u64 (uint64x2_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint32x2_t) { 1, 0 });
++  return (uint64x2_t) __builtin_aarch64_lshrv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrev64q_f32 (float32x4_t a)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrd_n_s64 (int64_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
++  return __builtin_aarch64_ashr_simddi (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vrev64q_p8 (poly8x16_t a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vshrd_n_u64 (uint64_t __a, const int __b)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
++  return __builtin_aarch64_lshr_simddi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vrev64q_p16 (poly16x8_t a)
++/* vsli */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
++  return (int8x8_t) __builtin_aarch64_ssli_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrev64q_s8 (int8x16_t a)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
++  return (int16x4_t) __builtin_aarch64_ssli_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vrev64q_s16 (int16x8_t a)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
++  return (int32x2_t) __builtin_aarch64_ssli_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vrev64q_s32 (int32x4_t a)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
++  return (int64x1_t) {__builtin_aarch64_ssli_ndi (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrev64q_u8 (uint8x16_t a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a,
+-      (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
++  return __builtin_aarch64_usli_nv8qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vrev64q_u16 (uint16x8_t a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
++  return __builtin_aarch64_usli_nv4hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vrev64q_u32 (uint32x4_t a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+-  return __builtin_shuffle (a, (uint32x4_t) { 1, 0, 3, 2 });
++  return __builtin_aarch64_usli_nv2si_uuus (__a, __b, __c);
+ }
+ 
+-/* vrnd  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrnd_f32 (float32x2_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+-  return __builtin_aarch64_btruncv2sf (__a);
++  return (uint64x1_t) {__builtin_aarch64_usli_ndi_uuus (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrnd_f64 (float64x1_t __a)
++__extension__ extern __inline poly64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsli_n_p64 (poly64x1_t __a, poly64x1_t __b, const int __c)
+ {
+-  return vset_lane_f64 (__builtin_trunc (vget_lane_f64 (__a, 0)), __a, 0);
++  return (poly64x1_t) {__builtin_aarch64_ssli_ndi_ppps (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndq_f32 (float32x4_t __a)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+-  return __builtin_aarch64_btruncv4sf (__a);
++  return (int8x16_t) __builtin_aarch64_ssli_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndq_f64 (float64x2_t __a)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+-  return __builtin_aarch64_btruncv2df (__a);
++  return (int16x8_t) __builtin_aarch64_ssli_nv8hi (__a, __b, __c);
+ }
+ 
+-/* vrnda  */
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++{
++  return (int32x4_t) __builtin_aarch64_ssli_nv4si (__a, __b, __c);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrnda_f32 (float32x2_t __a)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+-  return __builtin_aarch64_roundv2sf (__a);
++  return (int64x2_t) __builtin_aarch64_ssli_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrnda_f64 (float64x1_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+-  return vset_lane_f64 (__builtin_round (vget_lane_f64 (__a, 0)), __a, 0);
++  return __builtin_aarch64_usli_nv16qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndaq_f32 (float32x4_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+-  return __builtin_aarch64_roundv4sf (__a);
++  return __builtin_aarch64_usli_nv8hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndaq_f64 (float64x2_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+-  return __builtin_aarch64_roundv2df (__a);
++  return __builtin_aarch64_usli_nv4si_uuus (__a, __b, __c);
+ }
+ 
+-/* vrndi  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrndi_f32 (float32x2_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+-  return __builtin_aarch64_nearbyintv2sf (__a);
++  return __builtin_aarch64_usli_nv2di_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrndi_f64 (float64x1_t __a)
++__extension__ extern __inline poly64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsliq_n_p64 (poly64x2_t __a, poly64x2_t __b, const int __c)
+ {
+-  return vset_lane_f64 (__builtin_nearbyint (vget_lane_f64 (__a, 0)), __a, 0);
++  return __builtin_aarch64_ssli_nv2di_ppps (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndiq_f32 (float32x4_t __a)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vslid_n_s64 (int64_t __a, int64_t __b, const int __c)
+ {
+-  return __builtin_aarch64_nearbyintv4sf (__a);
++  return __builtin_aarch64_ssli_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndiq_f64 (float64x2_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vslid_n_u64 (uint64_t __a, uint64_t __b, const int __c)
+ {
+-  return __builtin_aarch64_nearbyintv2df (__a);
++  return __builtin_aarch64_usli_ndi_uuus (__a, __b, __c);
+ }
+ 
+-/* vrndm  */
++/* vsqadd */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrndm_f32 (float32x2_t __a)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqadd_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+-  return __builtin_aarch64_floorv2sf (__a);
++  return __builtin_aarch64_usqaddv8qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrndm_f64 (float64x1_t __a)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqadd_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+-  return vset_lane_f64 (__builtin_floor (vget_lane_f64 (__a, 0)), __a, 0);
++  return __builtin_aarch64_usqaddv4hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndmq_f32 (float32x4_t __a)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqadd_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+-  return __builtin_aarch64_floorv4sf (__a);
++  return __builtin_aarch64_usqaddv2si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndmq_f64 (float64x2_t __a)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqadd_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+-  return __builtin_aarch64_floorv2df (__a);
++  return (uint64x1_t) {__builtin_aarch64_usqadddi_uus (__a[0], __b[0])};
+ }
+ 
+-/* vrndn  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrndn_f32 (float32x2_t __a)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+-  return __builtin_aarch64_frintnv2sf (__a);
++  return __builtin_aarch64_usqaddv16qi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrndn_f64 (float64x1_t __a)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+-  return (float64x1_t) {__builtin_aarch64_frintndf (__a[0])};
++  return __builtin_aarch64_usqaddv8hi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndnq_f32 (float32x4_t __a)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+-  return __builtin_aarch64_frintnv4sf (__a);
++  return __builtin_aarch64_usqaddv4si_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndnq_f64 (float64x2_t __a)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+-  return __builtin_aarch64_frintnv2df (__a);
++  return __builtin_aarch64_usqaddv2di_uus (__a, __b);
+ }
+ 
+-/* vrndp  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrndp_f32 (float32x2_t __a)
++__extension__ extern __inline uint8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddb_u8 (uint8_t __a, int8_t __b)
+ {
+-  return __builtin_aarch64_ceilv2sf (__a);
++  return __builtin_aarch64_usqaddqi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrndp_f64 (float64x1_t __a)
++__extension__ extern __inline uint16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddh_u16 (uint16_t __a, int16_t __b)
+ {
+-  return vset_lane_f64 (__builtin_ceil (vget_lane_f64 (__a, 0)), __a, 0);
++  return __builtin_aarch64_usqaddhi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndpq_f32 (float32x4_t __a)
++__extension__ extern __inline uint32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqadds_u32 (uint32_t __a, int32_t __b)
+ {
+-  return __builtin_aarch64_ceilv4sf (__a);
++  return __builtin_aarch64_usqaddsi_uus (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndpq_f64 (float64x2_t __a)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqaddd_u64 (uint64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_ceilv2df (__a);
++  return __builtin_aarch64_usqadddi_uus (__a, __b);
+ }
+ 
+-/* vrndx  */
+-
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vrndx_f32 (float32x2_t __a)
++/* vsqrt */
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqrt_f32 (float32x2_t a)
+ {
+-  return __builtin_aarch64_rintv2sf (__a);
++  return __builtin_aarch64_sqrtv2sf (a);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vrndx_f64 (float64x1_t __a)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqrtq_f32 (float32x4_t a)
+ {
+-  return vset_lane_f64 (__builtin_rint (vget_lane_f64 (__a, 0)), __a, 0);
++  return __builtin_aarch64_sqrtv4sf (a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vrndxq_f32 (float32x4_t __a)
++__extension__ extern __inline float64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqrt_f64 (float64x1_t a)
+ {
+-  return __builtin_aarch64_rintv4sf (__a);
++  return (float64x1_t) { __builtin_aarch64_sqrtdf (a[0]) };
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vrndxq_f64 (float64x2_t __a)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqrtq_f64 (float64x2_t a)
+ {
+-  return __builtin_aarch64_rintv2df (__a);
++  return __builtin_aarch64_sqrtv2df (a);
+ }
+ 
+-/* vrshl */
++/* vsra */
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrshl_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+-  return (int8x8_t) __builtin_aarch64_srshlv8qi (__a, __b);
++  return (int8x8_t) __builtin_aarch64_ssra_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vrshl_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+-  return (int16x4_t) __builtin_aarch64_srshlv4hi (__a, __b);
++  return (int16x4_t) __builtin_aarch64_ssra_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vrshl_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+-  return (int32x2_t) __builtin_aarch64_srshlv2si (__a, __b);
++  return (int32x2_t) __builtin_aarch64_ssra_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vrshl_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+-  return (int64x1_t) {__builtin_aarch64_srshldi (__a[0], __b[0])};
++  return (int64x1_t) {__builtin_aarch64_ssra_ndi (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrshl_u8 (uint8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv8qi_uus (__a, __b);
++  return __builtin_aarch64_usra_nv8qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vrshl_u16 (uint16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv4hi_uus (__a, __b);
++  return __builtin_aarch64_usra_nv4hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vrshl_u32 (uint32x2_t __a, int32x2_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv2si_uus (__a, __b);
++  return __builtin_aarch64_usra_nv2si_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vrshl_u64 (uint64x1_t __a, int64x1_t __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_urshldi_uus (__a[0], __b[0])};
++  return (uint64x1_t) {__builtin_aarch64_usra_ndi_uuus (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrshlq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+-  return (int8x16_t) __builtin_aarch64_srshlv16qi (__a, __b);
++  return (int8x16_t) __builtin_aarch64_ssra_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vrshlq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+-  return (int16x8_t) __builtin_aarch64_srshlv8hi (__a, __b);
++  return (int16x8_t) __builtin_aarch64_ssra_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vrshlq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+-  return (int32x4_t) __builtin_aarch64_srshlv4si (__a, __b);
++  return (int32x4_t) __builtin_aarch64_ssra_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vrshlq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+-  return (int64x2_t) __builtin_aarch64_srshlv2di (__a, __b);
++  return (int64x2_t) __builtin_aarch64_ssra_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrshlq_u8 (uint8x16_t __a, int8x16_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv16qi_uus (__a, __b);
++  return __builtin_aarch64_usra_nv16qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vrshlq_u16 (uint16x8_t __a, int16x8_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv8hi_uus (__a, __b);
++  return __builtin_aarch64_usra_nv8hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vrshlq_u32 (uint32x4_t __a, int32x4_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv4si_uus (__a, __b);
++  return __builtin_aarch64_usra_nv4si_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vrshlq_u64 (uint64x2_t __a, int64x2_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshlv2di_uus (__a, __b);
++  return __builtin_aarch64_usra_nv2di_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vrshld_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsrad_n_s64 (int64_t __a, int64_t __b, const int __c)
+ {
+-  return __builtin_aarch64_srshldi (__a, __b);
++  return __builtin_aarch64_ssra_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vrshld_u64 (uint64_t __a, int64_t __b)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsrad_n_u64 (uint64_t __a, uint64_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshldi_uus (__a, __b);
++  return __builtin_aarch64_usra_ndi_uuus (__a, __b, __c);
+ }
+ 
+-/* vrshr */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrshr_n_s8 (int8x8_t __a, const int __b)
+-{
+-  return (int8x8_t) __builtin_aarch64_srshr_nv8qi (__a, __b);
+-}
++/* vsri */
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vrshr_n_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+-  return (int16x4_t) __builtin_aarch64_srshr_nv4hi (__a, __b);
++  return (int8x8_t) __builtin_aarch64_ssri_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vrshr_n_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+-  return (int32x2_t) __builtin_aarch64_srshr_nv2si (__a, __b);
++  return (int16x4_t) __builtin_aarch64_ssri_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vrshr_n_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+-  return (int64x1_t) {__builtin_aarch64_srshr_ndi (__a[0], __b)};
++  return (int32x2_t) __builtin_aarch64_ssri_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrshr_n_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv8qi_uus (__a, __b);
++  return (int64x1_t) {__builtin_aarch64_ssri_ndi (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vrshr_n_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv4hi_uus (__a, __b);
++  return __builtin_aarch64_usri_nv8qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vrshr_n_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv2si_uus (__a, __b);
++  return __builtin_aarch64_usri_nv4hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vrshr_n_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_urshr_ndi_uus (__a[0], __b)};
++  return __builtin_aarch64_usri_nv2si_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrshrq_n_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsri_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+-  return (int8x16_t) __builtin_aarch64_srshr_nv16qi (__a, __b);
++  return (uint64x1_t) {__builtin_aarch64_usri_ndi_uuus (__a[0], __b[0], __c)};
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vrshrq_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+-  return (int16x8_t) __builtin_aarch64_srshr_nv8hi (__a, __b);
++  return (int8x16_t) __builtin_aarch64_ssri_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vrshrq_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+-  return (int32x4_t) __builtin_aarch64_srshr_nv4si (__a, __b);
++  return (int16x8_t) __builtin_aarch64_ssri_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vrshrq_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+-  return (int64x2_t) __builtin_aarch64_srshr_nv2di (__a, __b);
++  return (int32x4_t) __builtin_aarch64_ssri_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrshrq_n_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv16qi_uus (__a, __b);
++  return (int64x2_t) __builtin_aarch64_ssri_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vrshrq_n_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv8hi_uus (__a, __b);
++  return __builtin_aarch64_usri_nv16qi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vrshrq_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv4si_uus (__a, __b);
++  return __builtin_aarch64_usri_nv8hi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vrshrq_n_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_nv2di_uus (__a, __b);
++  return __builtin_aarch64_usri_nv4si_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vrshrd_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsriq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+-  return __builtin_aarch64_srshr_ndi (__a, __b);
++  return __builtin_aarch64_usri_nv2di_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vrshrd_n_u64 (uint64_t __a, const int __b)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsrid_n_s64 (int64_t __a, int64_t __b, const int __c)
+ {
+-  return __builtin_aarch64_urshr_ndi_uus (__a, __b);
++  return __builtin_aarch64_ssri_ndi (__a, __b, __c);
+ }
+ 
+-/* vrsra */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vrsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsrid_n_u64 (uint64_t __a, uint64_t __b, const int __c)
+ {
+-  return (int8x8_t) __builtin_aarch64_srsra_nv8qi (__a, __b, __c);
++  return __builtin_aarch64_usri_ndi_uuus (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vrsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+-{
+-  return (int16x4_t) __builtin_aarch64_srsra_nv4hi (__a, __b, __c);
+-}
++/* vst1 */
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vrsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_f16 (float16_t *__a, float16x4_t __b)
+ {
+-  return (int32x2_t) __builtin_aarch64_srsra_nv2si (__a, __b, __c);
++  __builtin_aarch64_st1v4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vrsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_f32 (float32_t *a, float32x2_t b)
+ {
+-  return (int64x1_t) {__builtin_aarch64_srsra_ndi (__a[0], __b[0], __c)};
++  __builtin_aarch64_st1v2sf ((__builtin_aarch64_simd_sf *) a, b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vrsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_f64 (float64_t *a, float64x1_t b)
+ {
+-  return __builtin_aarch64_ursra_nv8qi_uuus (__a, __b, __c);
++  *a = b[0];
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vrsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_p8 (poly8_t *a, poly8x8_t b)
+ {
+-  return __builtin_aarch64_ursra_nv4hi_uuus (__a, __b, __c);
++  __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a,
++			     (int8x8_t) b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vrsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_p16 (poly16_t *a, poly16x4_t b)
+ {
+-  return __builtin_aarch64_ursra_nv2si_uuus (__a, __b, __c);
++  __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a,
++			     (int16x4_t) b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vrsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_p64 (poly64_t *a, poly64x1_t b)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_ursra_ndi_uuus (__a[0], __b[0], __c)};
++  *a = b[0];
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vrsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_s8 (int8_t *a, int8x8_t b)
+ {
+-  return (int8x16_t) __builtin_aarch64_srsra_nv16qi (__a, __b, __c);
++  __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a, b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vrsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_s16 (int16_t *a, int16x4_t b)
+ {
+-  return (int16x8_t) __builtin_aarch64_srsra_nv8hi (__a, __b, __c);
++  __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a, b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vrsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_s32 (int32_t *a, int32x2_t b)
+ {
+-  return (int32x4_t) __builtin_aarch64_srsra_nv4si (__a, __b, __c);
++  __builtin_aarch64_st1v2si ((__builtin_aarch64_simd_si *) a, b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vrsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_s64 (int64_t *a, int64x1_t b)
+ {
+-  return (int64x2_t) __builtin_aarch64_srsra_nv2di (__a, __b, __c);
++  *a = b[0];
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vrsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_u8 (uint8_t *a, uint8x8_t b)
+ {
+-  return __builtin_aarch64_ursra_nv16qi_uuus (__a, __b, __c);
++  __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a,
++			     (int8x8_t) b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vrsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_u16 (uint16_t *a, uint16x4_t b)
+ {
+-  return __builtin_aarch64_ursra_nv8hi_uuus (__a, __b, __c);
++  __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a,
++			     (int16x4_t) b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vrsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_u32 (uint32_t *a, uint32x2_t b)
+ {
+-  return __builtin_aarch64_ursra_nv4si_uuus (__a, __b, __c);
++  __builtin_aarch64_st1v2si ((__builtin_aarch64_simd_si *) a,
++			     (int32x2_t) b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vrsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_u64 (uint64_t *a, uint64x1_t b)
+ {
+-  return __builtin_aarch64_ursra_nv2di_uuus (__a, __b, __c);
++  *a = b[0];
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vrsrad_n_s64 (int64_t __a, int64_t __b, const int __c)
++/* vst1q */
++
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_f16 (float16_t *__a, float16x8_t __b)
+ {
+-  return __builtin_aarch64_srsra_ndi (__a, __b, __c);
++  __builtin_aarch64_st1v8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vrsrad_n_u64 (uint64_t __a, uint64_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_f32 (float32_t *a, float32x4_t b)
+ {
+-  return __builtin_aarch64_ursra_ndi_uuus (__a, __b, __c);
++  __builtin_aarch64_st1v4sf ((__builtin_aarch64_simd_sf *) a, b);
+ }
+ 
+-#pragma GCC push_options
+-#pragma GCC target ("+nothing+crypto")
+-
+-/* vsha1  */
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1cq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_f64 (float64_t *a, float64x2_t b)
+ {
+-  return __builtin_aarch64_crypto_sha1cv4si_uuuu (hash_abcd, hash_e, wk);
++  __builtin_aarch64_st1v2df ((__builtin_aarch64_simd_df *) a, b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1mq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_p8 (poly8_t *a, poly8x16_t b)
+ {
+-  return __builtin_aarch64_crypto_sha1mv4si_uuuu (hash_abcd, hash_e, wk);
++  __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a,
++			      (int8x16_t) b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1pq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_p16 (poly16_t *a, poly16x8_t b)
+ {
+-  return __builtin_aarch64_crypto_sha1pv4si_uuuu (hash_abcd, hash_e, wk);
++  __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a,
++			     (int16x8_t) b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vsha1h_u32 (uint32_t hash_e)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_p64 (poly64_t *a, poly64x2_t b)
+ {
+-  return __builtin_aarch64_crypto_sha1hsi_uu (hash_e);
++  __builtin_aarch64_st1v2di_sp ((__builtin_aarch64_simd_di *) a,
++				(poly64x2_t) b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_s8 (int8_t *a, int8x16_t b)
+ {
+-  return __builtin_aarch64_crypto_sha1su0v4si_uuuu (w0_3, w4_7, w8_11);
++  __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a, b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1su1q_u32 (uint32x4_t tw0_3, uint32x4_t w12_15)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_s16 (int16_t *a, int16x8_t b)
+ {
+-  return __builtin_aarch64_crypto_sha1su1v4si_uuu (tw0_3, w12_15);
++  __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a, b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256hq_u32 (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_s32 (int32_t *a, int32x4_t b)
+ {
+-  return __builtin_aarch64_crypto_sha256hv4si_uuuu (hash_abcd, hash_efgh, wk);
++  __builtin_aarch64_st1v4si ((__builtin_aarch64_simd_si *) a, b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256h2q_u32 (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_s64 (int64_t *a, int64x2_t b)
+ {
+-  return __builtin_aarch64_crypto_sha256h2v4si_uuuu (hash_efgh, hash_abcd, wk);
++  __builtin_aarch64_st1v2di ((__builtin_aarch64_simd_di *) a, b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_u8 (uint8_t *a, uint8x16_t b)
+ {
+-  return __builtin_aarch64_crypto_sha256su0v4si_uuu (w0_3, w4_7);
++  __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a,
++			      (int8x16_t) b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_u16 (uint16_t *a, uint16x8_t b)
+ {
+-  return __builtin_aarch64_crypto_sha256su1v4si_uuuu (tw0_3, w8_11, w12_15);
++  __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a,
++			     (int16x8_t) b);
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
+-vmull_p64 (poly64_t a, poly64_t b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_u32 (uint32_t *a, uint32x4_t b)
+ {
+-  return
+-    __builtin_aarch64_crypto_pmulldi_ppp (a, b);
++  __builtin_aarch64_st1v4si ((__builtin_aarch64_simd_si *) a,
++			     (int32x4_t) b);
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
+-vmull_high_p64 (poly64x2_t a, poly64x2_t b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_u64 (uint64_t *a, uint64x2_t b)
+ {
+-  return __builtin_aarch64_crypto_pmullv2di_ppp (a, b);
++  __builtin_aarch64_st1v2di ((__builtin_aarch64_simd_di *) a,
++			     (int64x2_t) b);
+ }
+ 
+-#pragma GCC pop_options
++/* vst1_lane */
+ 
+-/* vshl */
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_f16 (float16_t *__a, float16x4_t __b, const int __lane)
++{
++  *__a = __aarch64_vget_lane_any (__b, __lane);
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vshl_n_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_f32 (float32_t *__a, float32x2_t __b, const int __lane)
+ {
+-  return (int8x8_t) __builtin_aarch64_ashlv8qi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vshl_n_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_f64 (float64_t *__a, float64x1_t __b, const int __lane)
+ {
+-  return (int16x4_t) __builtin_aarch64_ashlv4hi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vshl_n_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_p8 (poly8_t *__a, poly8x8_t __b, const int __lane)
+ {
+-  return (int32x2_t) __builtin_aarch64_ashlv2si (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vshl_n_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_p16 (poly16_t *__a, poly16x4_t __b, const int __lane)
+ {
+-  return (int64x1_t) {__builtin_aarch64_ashldi (__a[0], __b)};
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vshl_n_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_p64 (poly64_t *__a, poly64x1_t __b, const int __lane)
+ {
+-  return (uint8x8_t) __builtin_aarch64_ashlv8qi ((int8x8_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vshl_n_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_s8 (int8_t *__a, int8x8_t __b, const int __lane)
+ {
+-  return (uint16x4_t) __builtin_aarch64_ashlv4hi ((int16x4_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vshl_n_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_s16 (int16_t *__a, int16x4_t __b, const int __lane)
+ {
+-  return (uint32x2_t) __builtin_aarch64_ashlv2si ((int32x2_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vshl_n_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_s32 (int32_t *__a, int32x2_t __b, const int __lane)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_ashldi ((int64_t) __a[0], __b)};
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vshlq_n_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_s64 (int64_t *__a, int64x1_t __b, const int __lane)
+ {
+-  return (int8x16_t) __builtin_aarch64_ashlv16qi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vshlq_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_u8 (uint8_t *__a, uint8x8_t __b, const int __lane)
+ {
+-  return (int16x8_t) __builtin_aarch64_ashlv8hi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vshlq_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_u16 (uint16_t *__a, uint16x4_t __b, const int __lane)
+ {
+-  return (int32x4_t) __builtin_aarch64_ashlv4si (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vshlq_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_u32 (uint32_t *__a, uint32x2_t __b, const int __lane)
+ {
+-  return (int64x2_t) __builtin_aarch64_ashlv2di (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vshlq_n_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1_lane_u64 (uint64_t *__a, uint64x1_t __b, const int __lane)
+ {
+-  return (uint8x16_t) __builtin_aarch64_ashlv16qi ((int8x16_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vshlq_n_u16 (uint16x8_t __a, const int __b)
++/* vst1q_lane */
++
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_f16 (float16_t *__a, float16x8_t __b, const int __lane)
+ {
+-  return (uint16x8_t) __builtin_aarch64_ashlv8hi ((int16x8_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vshlq_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_f32 (float32_t *__a, float32x4_t __b, const int __lane)
+ {
+-  return (uint32x4_t) __builtin_aarch64_ashlv4si ((int32x4_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vshlq_n_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_f64 (float64_t *__a, float64x2_t __b, const int __lane)
+ {
+-  return (uint64x2_t) __builtin_aarch64_ashlv2di ((int64x2_t) __a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vshld_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_p8 (poly8_t *__a, poly8x16_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_ashldi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vshld_n_u64 (uint64_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_p16 (poly16_t *__a, poly16x8_t __b, const int __lane)
+ {
+-  return (uint64_t) __builtin_aarch64_ashldi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vshl_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_p64 (poly64_t *__a, poly64x2_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_sshlv8qi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vshl_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_s8 (int8_t *__a, int8x16_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_sshlv4hi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vshl_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_s16 (int16_t *__a, int16x8_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_sshlv2si (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vshl_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_s32 (int32_t *__a, int32x4_t __b, const int __lane)
+ {
+-  return (int64x1_t) {__builtin_aarch64_sshldi (__a[0], __b[0])};
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vshl_u8 (uint8x8_t __a, int8x8_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_s64 (int64_t *__a, int64x2_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_ushlv8qi_uus (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vshl_u16 (uint16x4_t __a, int16x4_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_u8 (uint8_t *__a, uint8x16_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_ushlv4hi_uus (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vshl_u32 (uint32x2_t __a, int32x2_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_u16 (uint16_t *__a, uint16x8_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_ushlv2si_uus (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vshl_u64 (uint64x1_t __a, int64x1_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_u32 (uint32_t *__a, uint32x4_t __b, const int __lane)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_ushldi_uus (__a[0], __b[0])};
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vshlq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst1q_lane_u64 (uint64_t *__a, uint64x2_t __b, const int __lane)
+ {
+-  return __builtin_aarch64_sshlv16qi (__a, __b);
++  *__a = __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vshlq_s16 (int16x8_t __a, int16x8_t __b)
++/* vstn */
++
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_s64 (int64_t * __a, int64x1x2_t val)
+ {
+-  return __builtin_aarch64_sshlv8hi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  int64x2x2_t temp;
++  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1);
++  __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vshlq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_u64 (uint64_t * __a, uint64x1x2_t val)
+ {
+-  return __builtin_aarch64_sshlv4si (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  uint64x2x2_t temp;
++  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1);
++  __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vshlq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_f64 (float64_t * __a, float64x1x2_t val)
+ {
+-  return __builtin_aarch64_sshlv2di (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  float64x2x2_t temp;
++  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[1], 1);
++  __builtin_aarch64_st2df ((__builtin_aarch64_simd_df *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vshlq_u8 (uint8x16_t __a, int8x16_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_s8 (int8_t * __a, int8x8x2_t val)
+ {
+-  return __builtin_aarch64_ushlv16qi_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  int8x16x2_t temp;
++  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vshlq_u16 (uint16x8_t __a, int16x8_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_p8 (poly8_t * __a, poly8x8x2_t val)
+ {
+-  return __builtin_aarch64_ushlv8hi_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  poly8x16x2_t temp;
++  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vshlq_u32 (uint32x4_t __a, int32x4_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_s16 (int16_t * __a, int16x4x2_t val)
+ {
+-  return __builtin_aarch64_ushlv4si_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  int16x8x2_t temp;
++  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vshlq_u64 (uint64x2_t __a, int64x2_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_p16 (poly16_t * __a, poly16x4x2_t val)
+ {
+-  return __builtin_aarch64_ushlv2di_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  poly16x8x2_t temp;
++  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vshld_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_s32 (int32_t * __a, int32x2x2_t val)
+ {
+-  return __builtin_aarch64_sshldi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  int32x4x2_t temp;
++  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1);
++  __builtin_aarch64_st2v2si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vshld_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_u8 (uint8_t * __a, uint8x8x2_t val)
+ {
+-  return __builtin_aarch64_ushldi_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  uint8x16x2_t temp;
++  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vshll_high_n_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_u16 (uint16_t * __a, uint16x4x2_t val)
+ {
+-  return __builtin_aarch64_sshll2_nv16qi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  uint16x8x2_t temp;
++  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vshll_high_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_u32 (uint32_t * __a, uint32x2x2_t val)
+ {
+-  return __builtin_aarch64_sshll2_nv8hi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  uint32x4x2_t temp;
++  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1);
++  __builtin_aarch64_st2v2si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vshll_high_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_f16 (float16_t * __a, float16x4x2_t val)
+ {
+-  return __builtin_aarch64_sshll2_nv4si (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  float16x8x2_t temp;
++  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv8hf (__o, temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hf (__o, temp.val[1], 1);
++  __builtin_aarch64_st2v4hf (__a, __o);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vshll_high_n_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_f32 (float32_t * __a, float32x2x2_t val)
+ {
+-  return (uint16x8_t) __builtin_aarch64_ushll2_nv16qi ((int8x16_t) __a, __b);
++  __builtin_aarch64_simd_oi __o;
++  float32x4x2_t temp;
++  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[1], 1);
++  __builtin_aarch64_st2v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vshll_high_n_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2_p64 (poly64_t * __a, poly64x1x2_t val)
+ {
+-  return (uint32x4_t) __builtin_aarch64_ushll2_nv8hi ((int16x8_t) __a, __b);
++  __builtin_aarch64_simd_oi __o;
++  poly64x2x2_t temp;
++  temp.val[0] = vcombine_p64 (val.val[0], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p64 (val.val[1], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregoiv2di_ssps (__o,
++					       (poly64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2di_ssps (__o,
++					       (poly64x2_t) temp.val[1], 1);
++  __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vshll_high_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_s8 (int8_t * __a, int8x16x2_t val)
+ {
+-  return (uint64x2_t) __builtin_aarch64_ushll2_nv4si ((int32x4_t) __a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
++  __builtin_aarch64_st2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vshll_n_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_p8 (poly8_t * __a, poly8x16x2_t val)
+ {
+-  return __builtin_aarch64_sshll_nv8qi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
++  __builtin_aarch64_st2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vshll_n_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_s16 (int16_t * __a, int16x8x2_t val)
+ {
+-  return __builtin_aarch64_sshll_nv4hi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
++  __builtin_aarch64_st2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vshll_n_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_p16 (poly16_t * __a, poly16x8x2_t val)
+ {
+-  return __builtin_aarch64_sshll_nv2si (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
++  __builtin_aarch64_st2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vshll_n_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_s32 (int32_t * __a, int32x4x2_t val)
+ {
+-  return __builtin_aarch64_ushll_nv8qi_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[1], 1);
++  __builtin_aarch64_st2v4si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vshll_n_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_s64 (int64_t * __a, int64x2x2_t val)
+ {
+-  return __builtin_aarch64_ushll_nv4hi_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[1], 1);
++  __builtin_aarch64_st2v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vshll_n_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_u8 (uint8_t * __a, uint8x16x2_t val)
+ {
+-  return __builtin_aarch64_ushll_nv2si_uus (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
++  __builtin_aarch64_st2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-/* vshr */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vshr_n_s8 (int8x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_u16 (uint16_t * __a, uint16x8x2_t val)
+ {
+-  return (int8x8_t) __builtin_aarch64_ashrv8qi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
++  __builtin_aarch64_st2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vshr_n_s16 (int16x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_u32 (uint32_t * __a, uint32x4x2_t val)
+ {
+-  return (int16x4_t) __builtin_aarch64_ashrv4hi (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[1], 1);
++  __builtin_aarch64_st2v4si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vshr_n_s32 (int32x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_u64 (uint64_t * __a, uint64x2x2_t val)
+ {
+-  return (int32x2_t) __builtin_aarch64_ashrv2si (__a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[1], 1);
++  __builtin_aarch64_st2v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vshr_n_s64 (int64x1_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_f16 (float16_t * __a, float16x8x2_t val)
+ {
+-  return (int64x1_t) {__builtin_aarch64_ashr_simddi (__a[0], __b)};
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv8hf (__o, val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv8hf (__o, val.val[1], 1);
++  __builtin_aarch64_st2v8hf (__a, __o);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vshr_n_u8 (uint8x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_f32 (float32_t * __a, float32x4x2_t val)
+ {
+-  return (uint8x8_t) __builtin_aarch64_lshrv8qi ((int8x8_t) __a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) val.val[1], 1);
++  __builtin_aarch64_st2v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vshr_n_u16 (uint16x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_f64 (float64_t * __a, float64x2x2_t val)
+ {
+-  return (uint16x4_t) __builtin_aarch64_lshrv4hi ((int16x4_t) __a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) val.val[1], 1);
++  __builtin_aarch64_st2v2df ((__builtin_aarch64_simd_df *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vshr_n_u32 (uint32x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst2q_p64 (poly64_t * __a, poly64x2x2_t val)
+ {
+-  return (uint32x2_t) __builtin_aarch64_lshrv2si ((int32x2_t) __a, __b);
++  __builtin_aarch64_simd_oi __o;
++  __o = __builtin_aarch64_set_qregoiv2di_ssps (__o,
++					       (poly64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv2di_ssps (__o,
++					       (poly64x2_t) val.val[1], 1);
++  __builtin_aarch64_st2v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vshr_n_u64 (uint64x1_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_s64 (int64_t * __a, int64x1x3_t val)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_lshr_simddi_uus ( __a[0], __b)};
++  __builtin_aarch64_simd_ci __o;
++  int64x2x3_t temp;
++  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2);
++  __builtin_aarch64_st3di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vshrq_n_s8 (int8x16_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_u64 (uint64_t * __a, uint64x1x3_t val)
+ {
+-  return (int8x16_t) __builtin_aarch64_ashrv16qi (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  uint64x2x3_t temp;
++  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2);
++  __builtin_aarch64_st3di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vshrq_n_s16 (int16x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_f64 (float64_t * __a, float64x1x3_t val)
+ {
+-  return (int16x8_t) __builtin_aarch64_ashrv8hi (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  float64x2x3_t temp;
++  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[2], 2);
++  __builtin_aarch64_st3df ((__builtin_aarch64_simd_df *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vshrq_n_s32 (int32x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_s8 (int8_t * __a, int8x8x3_t val)
+ {
+-  return (int32x4_t) __builtin_aarch64_ashrv4si (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  int8x16x3_t temp;
++  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
++  __builtin_aarch64_st3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vshrq_n_s64 (int64x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_p8 (poly8_t * __a, poly8x8x3_t val)
+ {
+-  return (int64x2_t) __builtin_aarch64_ashrv2di (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  poly8x16x3_t temp;
++  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
++  __builtin_aarch64_st3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vshrq_n_u8 (uint8x16_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_s16 (int16_t * __a, int16x4x3_t val)
+ {
+-  return (uint8x16_t) __builtin_aarch64_lshrv16qi ((int8x16_t) __a, __b);
++  __builtin_aarch64_simd_ci __o;
++  int16x8x3_t temp;
++  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
++  __builtin_aarch64_st3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vshrq_n_u16 (uint16x8_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_p16 (poly16_t * __a, poly16x4x3_t val)
+ {
+-  return (uint16x8_t) __builtin_aarch64_lshrv8hi ((int16x8_t) __a, __b);
++  __builtin_aarch64_simd_ci __o;
++  poly16x8x3_t temp;
++  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
++  __builtin_aarch64_st3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vshrq_n_u32 (uint32x4_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_s32 (int32_t * __a, int32x2x3_t val)
+ {
+-  return (uint32x4_t) __builtin_aarch64_lshrv4si ((int32x4_t) __a, __b);
++  __builtin_aarch64_simd_ci __o;
++  int32x4x3_t temp;
++  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2);
++  __builtin_aarch64_st3v2si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vshrq_n_u64 (uint64x2_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_u8 (uint8_t * __a, uint8x8x3_t val)
+ {
+-  return (uint64x2_t) __builtin_aarch64_lshrv2di ((int64x2_t) __a, __b);
++  __builtin_aarch64_simd_ci __o;
++  uint8x16x3_t temp;
++  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
++  __builtin_aarch64_st3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vshrd_n_s64 (int64_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_u16 (uint16_t * __a, uint16x4x3_t val)
+ {
+-  return __builtin_aarch64_ashr_simddi (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  uint16x8x3_t temp;
++  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
++  __builtin_aarch64_st3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vshrd_n_u64 (uint64_t __a, const int __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_u32 (uint32_t * __a, uint32x2x3_t val)
+ {
+-  return __builtin_aarch64_lshr_simddi_uus (__a, __b);
++  __builtin_aarch64_simd_ci __o;
++  uint32x4x3_t temp;
++  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2);
++  __builtin_aarch64_st3v2si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-/* vsli */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vsli_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_f16 (float16_t * __a, float16x4x3_t val)
+ {
+-  return (int8x8_t) __builtin_aarch64_ssli_nv8qi (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  float16x8x3_t temp;
++  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_f16 (val.val[2], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[2], 2);
++  __builtin_aarch64_st3v4hf ((__builtin_aarch64_simd_hf *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vsli_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_f32 (float32_t * __a, float32x2x3_t val)
+ {
+-  return (int16x4_t) __builtin_aarch64_ssli_nv4hi (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  float32x4x3_t temp;
++  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[2], 2);
++  __builtin_aarch64_st3v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vsli_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3_p64 (poly64_t * __a, poly64x1x3_t val)
+ {
+-  return (int32x2_t) __builtin_aarch64_ssli_nv2si (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  poly64x2x3_t temp;
++  temp.val[0] = vcombine_p64 (val.val[0], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p64 (val.val[1], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_p64 (val.val[2], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
++					       (poly64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
++					       (poly64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
++					       (poly64x2_t) temp.val[2], 2);
++  __builtin_aarch64_st3di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vsli_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_s8 (int8_t * __a, int8x16x3_t val)
+ {
+-  return (int64x1_t) {__builtin_aarch64_ssli_ndi (__a[0], __b[0], __c)};
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
++  __builtin_aarch64_st3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vsli_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_p8 (poly8_t * __a, poly8x16x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv8qi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
++  __builtin_aarch64_st3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vsli_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_s16 (int16_t * __a, int16x8x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv4hi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
++  __builtin_aarch64_st3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vsli_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_p16 (poly16_t * __a, poly16x8x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv2si_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
++  __builtin_aarch64_st3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vsli_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_s32 (int32_t * __a, int32x4x3_t val)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_usli_ndi_uuus (__a[0], __b[0], __c)};
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[2], 2);
++  __builtin_aarch64_st3v4si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vsliq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_s64 (int64_t * __a, int64x2x3_t val)
+ {
+-  return (int8x16_t) __builtin_aarch64_ssli_nv16qi (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[2], 2);
++  __builtin_aarch64_st3v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vsliq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_u8 (uint8_t * __a, uint8x16x3_t val)
+ {
+-  return (int16x8_t) __builtin_aarch64_ssli_nv8hi (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
++  __builtin_aarch64_st3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vsliq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_u16 (uint16_t * __a, uint16x8x3_t val)
+ {
+-  return (int32x4_t) __builtin_aarch64_ssli_nv4si (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
++  __builtin_aarch64_st3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vsliq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_u32 (uint32_t * __a, uint32x4x3_t val)
+ {
+-  return (int64x2_t) __builtin_aarch64_ssli_nv2di (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[2], 2);
++  __builtin_aarch64_st3v4si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_u64 (uint64_t * __a, uint64x2x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv16qi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[2], 2);
++  __builtin_aarch64_st3v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_f16 (float16_t * __a, float16x8x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv8hi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[2], 2);
++  __builtin_aarch64_st3v8hf ((__builtin_aarch64_simd_hf *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_f32 (float32_t * __a, float32x4x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv4si_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[2], 2);
++  __builtin_aarch64_st3v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vsliq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_f64 (float64_t * __a, float64x2x3_t val)
+ {
+-  return __builtin_aarch64_usli_nv2di_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[2], 2);
++  __builtin_aarch64_st3v2df ((__builtin_aarch64_simd_df *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vslid_n_s64 (int64_t __a, int64_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst3q_p64 (poly64_t * __a, poly64x2x3_t val)
+ {
+-  return __builtin_aarch64_ssli_ndi (__a, __b, __c);
++  __builtin_aarch64_simd_ci __o;
++  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
++					       (poly64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
++					       (poly64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
++					       (poly64x2_t) val.val[2], 2);
++  __builtin_aarch64_st3v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vslid_n_u64 (uint64_t __a, uint64_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_s64 (int64_t * __a, int64x1x4_t val)
+ {
+-  return __builtin_aarch64_usli_ndi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  int64x2x4_t temp;
++  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (__AARCH64_INT64_C (0)));
++  temp.val[3] = vcombine_s64 (val.val[3], vcreate_s64 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[3], 3);
++  __builtin_aarch64_st4di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-/* vsqadd */
+-
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vsqadd_u8 (uint8x8_t __a, int8x8_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_u64 (uint64_t * __a, uint64x1x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv8qi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  uint64x2x4_t temp;
++  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_u64 (val.val[3], vcreate_u64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[3], 3);
++  __builtin_aarch64_st4di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vsqadd_u16 (uint16x4_t __a, int16x4_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_f64 (float64_t * __a, float64x1x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv4hi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  float64x2x4_t temp;
++  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_f64 (val.val[3], vcreate_f64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[3], 3);
++  __builtin_aarch64_st4df ((__builtin_aarch64_simd_df *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vsqadd_u32 (uint32x2_t __a, int32x2_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_s8 (int8_t * __a, int8x8x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv2si_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  int8x16x4_t temp;
++  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (__AARCH64_INT64_C (0)));
++  temp.val[3] = vcombine_s8 (val.val[3], vcreate_s8 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[3], 3);
++  __builtin_aarch64_st4v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vsqadd_u64 (uint64x1_t __a, int64x1_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_p8 (poly8_t * __a, poly8x8x4_t val)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_usqadddi_uus (__a[0], __b[0])};
++  __builtin_aarch64_simd_xi __o;
++  poly8x16x4_t temp;
++  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_p8 (val.val[3], vcreate_p8 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[3], 3);
++  __builtin_aarch64_st4v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vsqaddq_u8 (uint8x16_t __a, int8x16_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_s16 (int16_t * __a, int16x4x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv16qi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  int16x8x4_t temp;
++  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (__AARCH64_INT64_C (0)));
++  temp.val[3] = vcombine_s16 (val.val[3], vcreate_s16 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[3], 3);
++  __builtin_aarch64_st4v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vsqaddq_u16 (uint16x8_t __a, int16x8_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_p16 (poly16_t * __a, poly16x4x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv8hi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  poly16x8x4_t temp;
++  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_p16 (val.val[3], vcreate_p16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[3], 3);
++  __builtin_aarch64_st4v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsqaddq_u32 (uint32x4_t __a, int32x4_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_s32 (int32_t * __a, int32x2x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv4si_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  int32x4x4_t temp;
++  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
++  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
++  temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (__AARCH64_INT64_C (0)));
++  temp.val[3] = vcombine_s32 (val.val[3], vcreate_s32 (__AARCH64_INT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[3], 3);
++  __builtin_aarch64_st4v2si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vsqaddq_u64 (uint64x2_t __a, int64x2_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_u8 (uint8_t * __a, uint8x8x4_t val)
+ {
+-  return __builtin_aarch64_usqaddv2di_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  uint8x16x4_t temp;
++  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_u8 (val.val[3], vcreate_u8 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[3], 3);
++  __builtin_aarch64_st4v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
+-vsqaddb_u8 (uint8_t __a, int8_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_u16 (uint16_t * __a, uint16x4x4_t val)
+ {
+-  return __builtin_aarch64_usqaddqi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  uint16x8x4_t temp;
++  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_u16 (val.val[3], vcreate_u16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[3], 3);
++  __builtin_aarch64_st4v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
+-vsqaddh_u16 (uint16_t __a, int16_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_u32 (uint32_t * __a, uint32x2x4_t val)
+ {
+-  return __builtin_aarch64_usqaddhi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  uint32x4x4_t temp;
++  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_u32 (val.val[3], vcreate_u32 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[3], 3);
++  __builtin_aarch64_st4v2si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vsqadds_u32 (uint32_t __a, int32_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_f16 (float16_t * __a, float16x4x4_t val)
+ {
+-  return __builtin_aarch64_usqaddsi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  float16x8x4_t temp;
++  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_f16 (val.val[2], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_f16 (val.val[3], vcreate_f16 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[3], 3);
++  __builtin_aarch64_st4v4hf ((__builtin_aarch64_simd_hf *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vsqaddd_u64 (uint64_t __a, int64_t __b)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_f32 (float32_t * __a, float32x2x4_t val)
+ {
+-  return __builtin_aarch64_usqadddi_uus (__a, __b);
++  __builtin_aarch64_simd_xi __o;
++  float32x4x4_t temp;
++  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_f32 (val.val[3], vcreate_f32 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[3], 3);
++  __builtin_aarch64_st4v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
+ }
+ 
+-/* vsqrt */
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vsqrt_f32 (float32x2_t a)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4_p64 (poly64_t * __a, poly64x1x4_t val)
+ {
+-  return __builtin_aarch64_sqrtv2sf (a);
++  __builtin_aarch64_simd_xi __o;
++  poly64x2x4_t temp;
++  temp.val[0] = vcombine_p64 (val.val[0], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  temp.val[1] = vcombine_p64 (val.val[1], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  temp.val[2] = vcombine_p64 (val.val[2], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  temp.val[3] = vcombine_p64 (val.val[3], vcreate_p64 (__AARCH64_UINT64_C (0)));
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) temp.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) temp.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) temp.val[3], 3);
++  __builtin_aarch64_st4di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vsqrtq_f32 (float32x4_t a)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_s8 (int8_t * __a, int8x16x4_t val)
+ {
+-  return __builtin_aarch64_sqrtv4sf (a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[3], 3);
++  __builtin_aarch64_st4v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+-vsqrt_f64 (float64x1_t a)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_p8 (poly8_t * __a, poly8x16x4_t val)
+ {
+-  return (float64x1_t) { __builtin_aarch64_sqrtdf (a[0]) };
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[3], 3);
++  __builtin_aarch64_st4v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vsqrtq_f64 (float64x2_t a)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_s16 (int16_t * __a, int16x8x4_t val)
+ {
+-  return __builtin_aarch64_sqrtv2df (a);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[3], 3);
++  __builtin_aarch64_st4v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-/* vsra */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_p16 (poly16_t * __a, poly16x8x4_t val)
+ {
+-  return (int8x8_t) __builtin_aarch64_ssra_nv8qi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[3], 3);
++  __builtin_aarch64_st4v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_s32 (int32_t * __a, int32x4x4_t val)
+ {
+-  return (int16x4_t) __builtin_aarch64_ssra_nv4hi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[3], 3);
++  __builtin_aarch64_st4v4si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_s64 (int64_t * __a, int64x2x4_t val)
+ {
+-  return (int32x2_t) __builtin_aarch64_ssra_nv2si (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[3], 3);
++  __builtin_aarch64_st4v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_u8 (uint8_t * __a, uint8x16x4_t val)
+ {
+-  return (int64x1_t) {__builtin_aarch64_ssra_ndi (__a[0], __b[0], __c)};
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[3], 3);
++  __builtin_aarch64_st4v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_u16 (uint16_t * __a, uint16x8x4_t val)
+ {
+-  return __builtin_aarch64_usra_nv8qi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[3], 3);
++  __builtin_aarch64_st4v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_u32 (uint32_t * __a, uint32x4x4_t val)
+ {
+-  return __builtin_aarch64_usra_nv4hi_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[3], 3);
++  __builtin_aarch64_st4v4si ((__builtin_aarch64_simd_si *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_u64 (uint64_t * __a, uint64x2x4_t val)
+ {
+-  return __builtin_aarch64_usra_nv2si_uuus (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[3], 3);
++  __builtin_aarch64_st4v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_f16 (float16_t * __a, float16x8x4_t val)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_usra_ndi_uuus (__a[0], __b[0], __c)};
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[3], 3);
++  __builtin_aarch64_st4v8hf ((__builtin_aarch64_simd_hf *) __a, __o);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_f32 (float32_t * __a, float32x4x4_t val)
+ {
+-  return (int8x16_t) __builtin_aarch64_ssra_nv16qi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[3], 3);
++  __builtin_aarch64_st4v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_f64 (float64_t * __a, float64x2x4_t val)
+ {
+-  return (int16x8_t) __builtin_aarch64_ssra_nv8hi (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[3], 3);
++  __builtin_aarch64_st4v2df ((__builtin_aarch64_simd_df *) __a, __o);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline void
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vst4q_p64 (poly64_t * __a, poly64x2x4_t val)
+ {
+-  return (int32x4_t) __builtin_aarch64_ssra_nv4si (__a, __b, __c);
++  __builtin_aarch64_simd_xi __o;
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) val.val[0], 0);
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) val.val[1], 1);
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) val.val[2], 2);
++  __o = __builtin_aarch64_set_qregxiv2di_ssps (__o,
++					       (poly64x2_t) val.val[3], 3);
++  __builtin_aarch64_st4v2di ((__builtin_aarch64_simd_di *) __a, __o);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+-{
+-  return (int64x2_t) __builtin_aarch64_ssra_nv2di (__a, __b, __c);
+-}
++/* vsub */
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsubd_s64 (int64_t __a, int64_t __b)
+ {
+-  return __builtin_aarch64_usra_nv16qi_uuus (__a, __b, __c);
++  return __a - __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsubd_u64 (uint64_t __a, uint64_t __b)
+ {
+-  return __builtin_aarch64_usra_nv8hi_uuus (__a, __b, __c);
++  return __a - __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+-{
+-  return __builtin_aarch64_usra_nv4si_uuus (__a, __b, __c);
+-}
++/* vtbx1  */
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx1_s8 (int8x8_t __r, int8x8_t __tab, int8x8_t __idx)
+ {
+-  return __builtin_aarch64_usra_nv2di_uuus (__a, __b, __c);
++  uint8x8_t __mask = vclt_u8 (vreinterpret_u8_s8 (__idx),
++			      vmov_n_u8 (8));
++  int8x8_t __tbl = vtbl1_s8 (__tab, __idx);
++
++  return vbsl_s8 (__mask, __tbl, __r);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vsrad_n_s64 (int64_t __a, int64_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx1_u8 (uint8x8_t __r, uint8x8_t __tab, uint8x8_t __idx)
+ {
+-  return __builtin_aarch64_ssra_ndi (__a, __b, __c);
++  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (8));
++  uint8x8_t __tbl = vtbl1_u8 (__tab, __idx);
++
++  return vbsl_u8 (__mask, __tbl, __r);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vsrad_n_u64 (uint64_t __a, uint64_t __b, const int __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx1_p8 (poly8x8_t __r, poly8x8_t __tab, uint8x8_t __idx)
+ {
+-  return __builtin_aarch64_usra_ndi_uuus (__a, __b, __c);
++  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (8));
++  poly8x8_t __tbl = vtbl1_p8 (__tab, __idx);
++
++  return vbsl_p8 (__mask, __tbl, __r);
+ }
+ 
+-/* vsri */
++/* vtbx3  */
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vsri_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx3_s8 (int8x8_t __r, int8x8x3_t __tab, int8x8_t __idx)
+ {
+-  return (int8x8_t) __builtin_aarch64_ssri_nv8qi (__a, __b, __c);
++  uint8x8_t __mask = vclt_u8 (vreinterpret_u8_s8 (__idx),
++			      vmov_n_u8 (24));
++  int8x8_t __tbl = vtbl3_s8 (__tab, __idx);
++
++  return vbsl_s8 (__mask, __tbl, __r);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vsri_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx3_u8 (uint8x8_t __r, uint8x8x3_t __tab, uint8x8_t __idx)
+ {
+-  return (int16x4_t) __builtin_aarch64_ssri_nv4hi (__a, __b, __c);
++  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (24));
++  uint8x8_t __tbl = vtbl3_u8 (__tab, __idx);
++
++  return vbsl_u8 (__mask, __tbl, __r);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vsri_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx3_p8 (poly8x8_t __r, poly8x8x3_t __tab, uint8x8_t __idx)
+ {
+-  return (int32x2_t) __builtin_aarch64_ssri_nv2si (__a, __b, __c);
++  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (24));
++  poly8x8_t __tbl = vtbl3_p8 (__tab, __idx);
++
++  return vbsl_p8 (__mask, __tbl, __r);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vsri_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
++/* vtbx4  */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx4_s8 (int8x8_t __r, int8x8x4_t __tab, int8x8_t __idx)
+ {
+-  return (int64x1_t) {__builtin_aarch64_ssri_ndi (__a[0], __b[0], __c)};
++  int8x8_t result;
++  int8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_s8 (__tab.val[0], __tab.val[1]);
++  temp.val[1] = vcombine_s8 (__tab.val[2], __tab.val[3]);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = __builtin_aarch64_tbx4v8qi (__r, __o, __idx);
++  return result;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vsri_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx4_u8 (uint8x8_t __r, uint8x8x4_t __tab, uint8x8_t __idx)
+ {
+-  return __builtin_aarch64_usri_nv8qi_uuus (__a, __b, __c);
++  uint8x8_t result;
++  uint8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_u8 (__tab.val[0], __tab.val[1]);
++  temp.val[1] = vcombine_u8 (__tab.val[2], __tab.val[3]);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = (uint8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)__r, __o,
++						  (int8x8_t)__idx);
++  return result;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vsri_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtbx4_p8 (poly8x8_t __r, poly8x8x4_t __tab, uint8x8_t __idx)
+ {
+-  return __builtin_aarch64_usri_nv4hi_uuus (__a, __b, __c);
++  poly8x8_t result;
++  poly8x16x2_t temp;
++  __builtin_aarch64_simd_oi __o;
++  temp.val[0] = vcombine_p8 (__tab.val[0], __tab.val[1]);
++  temp.val[1] = vcombine_p8 (__tab.val[2], __tab.val[3]);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[0], 0);
++  __o = __builtin_aarch64_set_qregoiv16qi (__o,
++					   (int8x16_t) temp.val[1], 1);
++  result = (poly8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)__r, __o,
++						  (int8x8_t)__idx);
++  return result;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vsri_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
++/* vtrn */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __builtin_aarch64_usri_nv2si_uuus (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vsri_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return (uint64x1_t) {__builtin_aarch64_usri_ndi_uuus (__a[0], __b[0], __c)};
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vsriq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+-  return (int8x16_t) __builtin_aarch64_ssri_nv16qi (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vsriq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+-  return (int16x8_t) __builtin_aarch64_ssri_nv8hi (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vsriq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  return (int32x4_t) __builtin_aarch64_ssri_nv4si (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vsriq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  return (int64x2_t) __builtin_aarch64_ssri_nv2di (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vsriq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  return __builtin_aarch64_usri_nv16qi_uuus (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  return __builtin_aarch64_usri_nv8hi_uuus (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  return __builtin_aarch64_usri_nv4si_uuus (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vsriq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  return __builtin_aarch64_usri_nv2di_uuus (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vsrid_n_s64 (int64_t __a, int64_t __b, const int __c)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  return __builtin_aarch64_ssri_ndi (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vsrid_n_u64 (uint64_t __a, uint64_t __b, const int __c)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  return __builtin_aarch64_usri_ndi_uuus (__a, __b, __c);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-/* vst1 */
+-
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_f16 (float16_t *__a, float16x4_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  __builtin_aarch64_st1v4hf (__a, __b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_f32 (float32_t *a, float32x2_t b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+-  __builtin_aarch64_st1v2sf ((__builtin_aarch64_simd_sf *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_f64 (float64_t *a, float64x1_t b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+-  *a = b[0];
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_p8 (poly8_t *a, poly8x8_t b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a,
+-			     (int8x8_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_p16 (poly16_t *a, poly16x4_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a,
+-			     (int16x4_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_s8 (int8_t *a, int8x8_t b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_s16 (int16_t *a, int16x4_t b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_s32 (int32_t *a, int32x2_t b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  __builtin_aarch64_st1v2si ((__builtin_aarch64_simd_si *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_s64 (int64_t *a, int64x1_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  *a = b[0];
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_u8 (uint8_t *a, uint8x8_t b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  __builtin_aarch64_st1v8qi ((__builtin_aarch64_simd_qi *) a,
+-			     (int8x8_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_u16 (uint16_t *a, uint16x4_t b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn1q_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+-  __builtin_aarch64_st1v4hi ((__builtin_aarch64_simd_hi *) a,
+-			     (int16x4_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_u32 (uint32_t *a, uint32x2_t b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  __builtin_aarch64_st1v2si ((__builtin_aarch64_simd_si *) a,
+-			     (int32x2_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_u64 (uint64_t *a, uint64x1_t b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  *a = b[0];
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++#endif
+ }
+ 
+-/* vst1q */
+-
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_f16 (float16_t *__a, float16x8_t __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+-  __builtin_aarch64_st1v8hf (__a, __b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_f32 (float32_t *a, float32x4_t b)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+-  __builtin_aarch64_st1v4sf ((__builtin_aarch64_simd_sf *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_f64 (float64_t *a, float64x2_t b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  __builtin_aarch64_st1v2df ((__builtin_aarch64_simd_df *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_p8 (poly8_t *a, poly8x16_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a,
+-			      (int8x16_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_p16 (poly16_t *a, poly16x8_t b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a,
+-			     (int16x8_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_s8 (int8_t *a, int8x16_t b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_s16 (int16_t *a, int16x8_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_s32 (int32_t *a, int32x4_t b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  __builtin_aarch64_st1v4si ((__builtin_aarch64_simd_si *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_s64 (int64_t *a, int64x2_t b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  __builtin_aarch64_st1v2di ((__builtin_aarch64_simd_di *) a, b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_u8 (uint8_t *a, uint8x16_t b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  __builtin_aarch64_st1v16qi ((__builtin_aarch64_simd_qi *) a,
+-			      (int8x16_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_u16 (uint16_t *a, uint16x8_t b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  __builtin_aarch64_st1v8hi ((__builtin_aarch64_simd_hi *) a,
+-			     (int16x8_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_u32 (uint32_t *a, uint32x4_t b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+-  __builtin_aarch64_st1v4si ((__builtin_aarch64_simd_si *) a,
+-			     (int32x4_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_u64 (uint64_t *a, uint64x2_t b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+-  __builtin_aarch64_st1v2di ((__builtin_aarch64_simd_di *) a,
+-			     (int64x2_t) b);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-/* vst1_lane */
+-
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_f16 (float16_t *__a, float16x4_t __b, const int __lane)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_f32 (float32_t *__a, float32x2_t __b, const int __lane)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_f64 (float64_t *__a, float64x1_t __b, const int __lane)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_p8 (poly8_t *__a, poly8x8_t __b, const int __lane)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_p16 (poly16_t *__a, poly16x4_t __b, const int __lane)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_s8 (int8_t *__a, int8x8_t __b, const int __lane)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_s16 (int16_t *__a, int16x4_t __b, const int __lane)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_s32 (int32_t *__a, int32x2_t __b, const int __lane)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn2q_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_s64 (int64_t *__a, int64x1_t __b, const int __lane)
++__extension__ extern __inline float16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (float16x4x2_t) {vtrn1_f16 (__a, __b), vtrn2_f16 (__a, __b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_u8 (uint8_t *__a, uint8x8_t __b, const int __lane)
++__extension__ extern __inline float32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_f32 (float32x2_t a, float32x2_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (float32x2x2_t) {vtrn1_f32 (a, b), vtrn2_f32 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_u16 (uint16_t *__a, uint16x4_t __b, const int __lane)
++__extension__ extern __inline poly8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_p8 (poly8x8_t a, poly8x8_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (poly8x8x2_t) {vtrn1_p8 (a, b), vtrn2_p8 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_u32 (uint32_t *__a, uint32x2_t __b, const int __lane)
++__extension__ extern __inline poly16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_p16 (poly16x4_t a, poly16x4_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (poly16x4x2_t) {vtrn1_p16 (a, b), vtrn2_p16 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1_lane_u64 (uint64_t *__a, uint64x1_t __b, const int __lane)
++__extension__ extern __inline int8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_s8 (int8x8_t a, int8x8_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (int8x8x2_t) {vtrn1_s8 (a, b), vtrn2_s8 (a, b)};
+ }
+ 
+-/* vst1q_lane */
+-
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_f16 (float16_t *__a, float16x8_t __b, const int __lane)
++__extension__ extern __inline int16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_s16 (int16x4_t a, int16x4_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (int16x4x2_t) {vtrn1_s16 (a, b), vtrn2_s16 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_f32 (float32_t *__a, float32x4_t __b, const int __lane)
++__extension__ extern __inline int32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_s32 (int32x2_t a, int32x2_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (int32x2x2_t) {vtrn1_s32 (a, b), vtrn2_s32 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_f64 (float64_t *__a, float64x2_t __b, const int __lane)
++__extension__ extern __inline uint8x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_u8 (uint8x8_t a, uint8x8_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (uint8x8x2_t) {vtrn1_u8 (a, b), vtrn2_u8 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_p8 (poly8_t *__a, poly8x16_t __b, const int __lane)
++__extension__ extern __inline uint16x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_u16 (uint16x4_t a, uint16x4_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (uint16x4x2_t) {vtrn1_u16 (a, b), vtrn2_u16 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_p16 (poly16_t *__a, poly16x8_t __b, const int __lane)
++__extension__ extern __inline uint32x2x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_u32 (uint32x2_t a, uint32x2_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (uint32x2x2_t) {vtrn1_u32 (a, b), vtrn2_u32 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_s8 (int8_t *__a, int8x16_t __b, const int __lane)
++__extension__ extern __inline float16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (float16x8x2_t) {vtrn1q_f16 (__a, __b), vtrn2q_f16 (__a, __b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_s16 (int16_t *__a, int16x8_t __b, const int __lane)
++__extension__ extern __inline float32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_f32 (float32x4_t a, float32x4_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (float32x4x2_t) {vtrn1q_f32 (a, b), vtrn2q_f32 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_s32 (int32_t *__a, int32x4_t __b, const int __lane)
++__extension__ extern __inline poly8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_p8 (poly8x16_t a, poly8x16_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (poly8x16x2_t) {vtrn1q_p8 (a, b), vtrn2q_p8 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_s64 (int64_t *__a, int64x2_t __b, const int __lane)
++__extension__ extern __inline poly16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_p16 (poly16x8_t a, poly16x8_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (poly16x8x2_t) {vtrn1q_p16 (a, b), vtrn2q_p16 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_u8 (uint8_t *__a, uint8x16_t __b, const int __lane)
++__extension__ extern __inline int8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_s8 (int8x16_t a, int8x16_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (int8x16x2_t) {vtrn1q_s8 (a, b), vtrn2q_s8 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_u16 (uint16_t *__a, uint16x8_t __b, const int __lane)
++__extension__ extern __inline int16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_s16 (int16x8_t a, int16x8_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (int16x8x2_t) {vtrn1q_s16 (a, b), vtrn2q_s16 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_u32 (uint32_t *__a, uint32x4_t __b, const int __lane)
++__extension__ extern __inline int32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_s32 (int32x4_t a, int32x4_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (int32x4x2_t) {vtrn1q_s32 (a, b), vtrn2q_s32 (a, b)};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst1q_lane_u64 (uint64_t *__a, uint64x2_t __b, const int __lane)
++__extension__ extern __inline uint8x16x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_u8 (uint8x16_t a, uint8x16_t b)
+ {
+-  *__a = __aarch64_vget_lane_any (__b, __lane);
++  return (uint8x16x2_t) {vtrn1q_u8 (a, b), vtrn2q_u8 (a, b)};
+ }
+ 
+-/* vstn */
+-
+-__extension__ static __inline void
+-vst2_s64 (int64_t * __a, int64x1x2_t val)
++__extension__ extern __inline uint16x8x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_u16 (uint16x8_t a, uint16x8_t b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  int64x2x2_t temp;
+-  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1);
+-  __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o);
++  return (uint16x8x2_t) {vtrn1q_u16 (a, b), vtrn2q_u16 (a, b)};
+ }
+ 
+-__extension__ static __inline void
+-vst2_u64 (uint64_t * __a, uint64x1x2_t val)
++__extension__ extern __inline uint32x4x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_u32 (uint32x4_t a, uint32x4_t b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  uint64x2x2_t temp;
+-  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1);
+-  __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o);
++  return (uint32x4x2_t) {vtrn1q_u32 (a, b), vtrn2q_u32 (a, b)};
+ }
+ 
+-__extension__ static __inline void
+-vst2_f64 (float64_t * __a, float64x1x2_t val)
+-{
+-  __builtin_aarch64_simd_oi __o;
+-  float64x2x2_t temp;
+-  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[1], 1);
+-  __builtin_aarch64_st2df ((__builtin_aarch64_simd_df *) __a, __o);
+-}
++/* vtst */
+ 
+-__extension__ static __inline void
+-vst2_s8 (int8_t * __a, int8x8x2_t val)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  int8x16x2_t temp;
+-  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return (uint8x8_t) ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_p8 (poly8_t * __a, poly8x8x2_t val)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  poly8x16x2_t temp;
+-  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return (uint16x4_t) ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_s16 (int16_t * __a, int16x4x2_t val)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  int16x8x2_t temp;
+-  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return (uint32x2_t) ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_p16 (poly16_t * __a, poly16x4x2_t val)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_s64 (int64x1_t __a, int64x1_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  poly16x8x2_t temp;
+-  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return (uint64x1_t) ((__a & __b) != __AARCH64_INT64_C (0));
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_s32 (int32_t * __a, int32x2x2_t val)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  int32x4x2_t temp;
+-  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v2si ((__builtin_aarch64_simd_si *) __a, __o);
++  return ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_u8 (uint8_t * __a, uint8x8x2_t val)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  uint8x16x2_t temp;
+-  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_u16 (uint16_t * __a, uint16x4x2_t val)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  uint16x8x2_t temp;
+-  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_u32 (uint32_t * __a, uint32x2x2_t val)
++__extension__ extern __inline uint64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  uint32x4x2_t temp;
+-  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v2si ((__builtin_aarch64_simd_si *) __a, __o);
++  return ((__a & __b) != __AARCH64_UINT64_C (0));
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_f16 (float16_t * __a, float16x4x2_t val)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  float16x8x2_t temp;
+-  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv8hf (__o, temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hf (__o, temp.val[1], 1);
+-  __builtin_aarch64_st2v4hf (__a, __o);
++  return (uint8x16_t) ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2_f32 (float32_t * __a, float32x2x2_t val)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  float32x4x2_t temp;
+-  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[1], 1);
+-  __builtin_aarch64_st2v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
++  return (uint16x8_t) ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_s8 (int8_t * __a, int8x16x2_t val)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __builtin_aarch64_st2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return (uint32x4_t) ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_p8 (poly8_t * __a, poly8x16x2_t val)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __builtin_aarch64_st2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return (uint64x2_t) ((__a & __b) != __AARCH64_INT64_C (0));
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_s16 (int16_t * __a, int16x8x2_t val)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __builtin_aarch64_st2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_p16 (poly16_t * __a, poly16x8x2_t val)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __builtin_aarch64_st2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_s32 (int32_t * __a, int32x4x2_t val)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[1], 1);
+-  __builtin_aarch64_st2v4si ((__builtin_aarch64_simd_si *) __a, __o);
++  return ((__a & __b) != 0);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_s64 (int64_t * __a, int64x2x2_t val)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[1], 1);
+-  __builtin_aarch64_st2v2di ((__builtin_aarch64_simd_di *) __a, __o);
++  return ((__a & __b) != __AARCH64_UINT64_C (0));
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_u8 (uint8_t * __a, uint8x16x2_t val)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstd_s64 (int64_t __a, int64_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __builtin_aarch64_st2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return (__a & __b) ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_u16 (uint16_t * __a, uint16x8x2_t val)
++__extension__ extern __inline uint64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vtstd_u64 (uint64_t __a, uint64_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __builtin_aarch64_st2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return (__a & __b) ? -1ll : 0ll;
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_u32 (uint32_t * __a, uint32x4x2_t val)
++/* vuqadd */
++
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqadd_s8 (int8x8_t __a, uint8x8_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[1], 1);
+-  __builtin_aarch64_st2v4si ((__builtin_aarch64_simd_si *) __a, __o);
++  return __builtin_aarch64_suqaddv8qi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_u64 (uint64_t * __a, uint64x2x2_t val)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqadd_s16 (int16x4_t __a, uint16x4_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[1], 1);
+-  __builtin_aarch64_st2v2di ((__builtin_aarch64_simd_di *) __a, __o);
++  return __builtin_aarch64_suqaddv4hi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_f16 (float16_t * __a, float16x8x2_t val)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqadd_s32 (int32x2_t __a, uint32x2_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv8hf (__o, val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv8hf (__o, val.val[1], 1);
+-  __builtin_aarch64_st2v8hf (__a, __o);
++  return __builtin_aarch64_suqaddv2si_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_f32 (float32_t * __a, float32x4x2_t val)
++__extension__ extern __inline int64x1_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqadd_s64 (int64x1_t __a, uint64x1_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) val.val[1], 1);
+-  __builtin_aarch64_st2v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
++  return (int64x1_t) {__builtin_aarch64_suqadddi_ssu (__a[0], __b[0])};
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst2q_f64 (float64_t * __a, float64x2x2_t val)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddq_s8 (int8x16_t __a, uint8x16_t __b)
+ {
+-  __builtin_aarch64_simd_oi __o;
+-  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) val.val[1], 1);
+-  __builtin_aarch64_st2v2df ((__builtin_aarch64_simd_df *) __a, __o);
++  return __builtin_aarch64_suqaddv16qi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void
+-vst3_s64 (int64_t * __a, int64x1x3_t val)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddq_s16 (int16x8_t __a, uint16x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  int64x2x3_t temp;
+-  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2);
+-  __builtin_aarch64_st3di ((__builtin_aarch64_simd_di *) __a, __o);
++  return __builtin_aarch64_suqaddv8hi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void
+-vst3_u64 (uint64_t * __a, uint64x1x3_t val)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddq_s32 (int32x4_t __a, uint32x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  uint64x2x3_t temp;
+-  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2);
+-  __builtin_aarch64_st3di ((__builtin_aarch64_simd_di *) __a, __o);
++  return __builtin_aarch64_suqaddv4si_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void
+-vst3_f64 (float64_t * __a, float64x1x3_t val)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddq_s64 (int64x2_t __a, uint64x2_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  float64x2x3_t temp;
+-  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[2], 2);
+-  __builtin_aarch64_st3df ((__builtin_aarch64_simd_df *) __a, __o);
++  return __builtin_aarch64_suqaddv2di_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void
+-vst3_s8 (int8_t * __a, int8x8x3_t val)
++__extension__ extern __inline int8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddb_s8 (int8_t __a, uint8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  int8x16x3_t temp;
+-  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return __builtin_aarch64_suqaddqi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_p8 (poly8_t * __a, poly8x8x3_t val)
++__extension__ extern __inline int16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddh_s16 (int16_t __a, uint16_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  poly8x16x3_t temp;
+-  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++  return __builtin_aarch64_suqaddhi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_s16 (int16_t * __a, int16x4x3_t val)
++__extension__ extern __inline int32_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqadds_s32 (int32_t __a, uint32_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  int16x8x3_t temp;
+-  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return __builtin_aarch64_suqaddsi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_p16 (poly16_t * __a, poly16x4x3_t val)
++__extension__ extern __inline int64_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuqaddd_s64 (int64_t __a, uint64_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  poly16x8x3_t temp;
+-  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++  return __builtin_aarch64_suqadddi_ssu (__a,  __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_s32 (int32_t * __a, int32x2x3_t val)
++#define __DEFINTERLEAVE(op, rettype, intype, funcsuffix, Q) 		\
++  __extension__ extern __inline rettype					\
++  __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
++  v ## op ## Q ## _ ## funcsuffix (intype a, intype b)			\
++  {									\
++    return (rettype) {v ## op ## 1 ## Q ## _ ## funcsuffix (a, b),	\
++		      v ## op ## 2 ## Q ## _ ## funcsuffix (a, b)};	\
++  }
++
++#define __INTERLEAVE_LIST(op)					\
++  __DEFINTERLEAVE (op, float16x4x2_t, float16x4_t, f16,)	\
++  __DEFINTERLEAVE (op, float32x2x2_t, float32x2_t, f32,)	\
++  __DEFINTERLEAVE (op, poly8x8x2_t, poly8x8_t, p8,)		\
++  __DEFINTERLEAVE (op, poly16x4x2_t, poly16x4_t, p16,)		\
++  __DEFINTERLEAVE (op, int8x8x2_t, int8x8_t, s8,)		\
++  __DEFINTERLEAVE (op, int16x4x2_t, int16x4_t, s16,)		\
++  __DEFINTERLEAVE (op, int32x2x2_t, int32x2_t, s32,)		\
++  __DEFINTERLEAVE (op, uint8x8x2_t, uint8x8_t, u8,)		\
++  __DEFINTERLEAVE (op, uint16x4x2_t, uint16x4_t, u16,)		\
++  __DEFINTERLEAVE (op, uint32x2x2_t, uint32x2_t, u32,)		\
++  __DEFINTERLEAVE (op, float16x8x2_t, float16x8_t, f16, q)	\
++  __DEFINTERLEAVE (op, float32x4x2_t, float32x4_t, f32, q)	\
++  __DEFINTERLEAVE (op, poly8x16x2_t, poly8x16_t, p8, q)		\
++  __DEFINTERLEAVE (op, poly16x8x2_t, poly16x8_t, p16, q)	\
++  __DEFINTERLEAVE (op, int8x16x2_t, int8x16_t, s8, q)		\
++  __DEFINTERLEAVE (op, int16x8x2_t, int16x8_t, s16, q)		\
++  __DEFINTERLEAVE (op, int32x4x2_t, int32x4_t, s32, q)		\
++  __DEFINTERLEAVE (op, uint8x16x2_t, uint8x16_t, u8, q)		\
++  __DEFINTERLEAVE (op, uint16x8x2_t, uint16x8_t, u16, q)	\
++  __DEFINTERLEAVE (op, uint32x4x2_t, uint32x4_t, u32, q)
++
++/* vuzp */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  int32x4x3_t temp;
+-  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v2si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_u8 (uint8_t * __a, uint8x8x3_t val)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  uint8x16x3_t temp;
+-  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_u16 (uint16_t * __a, uint16x4x3_t val)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  uint16x8x3_t temp;
+-  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_u32 (uint32_t * __a, uint32x2x3_t val)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  uint32x4x3_t temp;
+-  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v2si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_f16 (float16_t * __a, float16x4x3_t val)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  float16x8x3_t temp;
+-  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_f16 (val.val[2], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v4hf ((__builtin_aarch64_simd_hf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3_f32 (float32_t * __a, float32x2x3_t val)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  float32x4x3_t temp;
+-  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[2], 2);
+-  __builtin_aarch64_st3v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_s8 (int8_t * __a, int8x16x3_t val)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
+-  __builtin_aarch64_st3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_p8 (poly8_t * __a, poly8x16x3_t val)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
+-  __builtin_aarch64_st3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_s16 (int16_t * __a, int16x8x3_t val)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
+-  __builtin_aarch64_st3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_p16 (poly16_t * __a, poly16x8x3_t val)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
+-  __builtin_aarch64_st3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_s32 (int32_t * __a, int32x4x3_t val)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[2], 2);
+-  __builtin_aarch64_st3v4si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_s64 (int64_t * __a, int64x2x3_t val)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[2], 2);
+-  __builtin_aarch64_st3v2di ((__builtin_aarch64_simd_di *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_u8 (uint8_t * __a, uint8x16x3_t val)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
+-  __builtin_aarch64_st3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_u16 (uint16_t * __a, uint16x8x3_t val)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
+-  __builtin_aarch64_st3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_u32 (uint32_t * __a, uint32x4x3_t val)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[2], 2);
+-  __builtin_aarch64_st3v4si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_u64 (uint64_t * __a, uint64x2x3_t val)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[2], 2);
+-  __builtin_aarch64_st3v2di ((__builtin_aarch64_simd_di *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_f16 (float16_t * __a, float16x8x3_t val)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[2], 2);
+-  __builtin_aarch64_st3v8hf ((__builtin_aarch64_simd_hf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_f32 (float32_t * __a, float32x4x3_t val)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[2], 2);
+-  __builtin_aarch64_st3v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst3q_f64 (float64_t * __a, float64x2x3_t val)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  __builtin_aarch64_simd_ci __o;
+-  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[2], 2);
+-  __builtin_aarch64_st3v2df ((__builtin_aarch64_simd_df *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline void
+-vst4_s64 (int64_t * __a, int64x1x4_t val)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  int64x2x4_t temp;
+-  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  temp.val[3] = vcombine_s64 (val.val[3], vcreate_s64 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[3], 3);
+-  __builtin_aarch64_st4di ((__builtin_aarch64_simd_di *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
++#endif
+ }
+ 
+-__extension__ static __inline void
+-vst4_u64 (uint64_t * __a, uint64x1x4_t val)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  uint64x2x4_t temp;
+-  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_u64 (val.val[3], vcreate_u64 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[3], 3);
+-  __builtin_aarch64_st4di ((__builtin_aarch64_simd_di *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
++#endif
+ }
+ 
+-__extension__ static __inline void
+-vst4_f64 (float64_t * __a, float64x1x4_t val)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  float64x2x4_t temp;
+-  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_f64 (val.val[3], vcreate_f64 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[3], 3);
+-  __builtin_aarch64_st4df ((__builtin_aarch64_simd_df *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
++#endif
+ }
+ 
+-__extension__ static __inline void
+-vst4_s8 (int8_t * __a, int8x8x4_t val)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp1q_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  int8x16x4_t temp;
+-  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  temp.val[3] = vcombine_s8 (val.val[3], vcreate_s8 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_f16 (float16x4_t __a, float16x4_t __b)
++{
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_p8 (poly8_t * __a, poly8x8x4_t val)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  poly8x16x4_t temp;
+-  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_p8 (val.val[3], vcreate_p8 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_s16 (int16_t * __a, int16x4x4_t val)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  int16x8x4_t temp;
+-  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  temp.val[3] = vcombine_s16 (val.val[3], vcreate_s16 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_p16 (poly16_t * __a, poly16x4x4_t val)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  poly16x8x4_t temp;
+-  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_p16 (val.val[3], vcreate_p16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_s32 (int32_t * __a, int32x2x4_t val)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  int32x4x4_t temp;
+-  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  temp.val[3] = vcombine_s32 (val.val[3], vcreate_s32 (__AARCH64_INT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v2si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_u8 (uint8_t * __a, uint8x8x4_t val)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  uint8x16x4_t temp;
+-  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_u8 (val.val[3], vcreate_u8 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_u16 (uint16_t * __a, uint16x4x4_t val)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  uint16x8x4_t temp;
+-  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_u16 (val.val[3], vcreate_u16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_u32 (uint32_t * __a, uint32x2x4_t val)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  uint32x4x4_t temp;
+-  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_u32 (val.val[3], vcreate_u32 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v2si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_f16 (float16_t * __a, float16x4x4_t val)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  float16x8x4_t temp;
+-  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_f16 (val.val[2], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_f16 (val.val[3], vcreate_f16 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v4hf ((__builtin_aarch64_simd_hf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4_f32 (float32_t * __a, float32x2x4_t val)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  float32x4x4_t temp;
+-  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  temp.val[3] = vcombine_f32 (val.val[3], vcreate_f32 (__AARCH64_UINT64_C (0)));
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[3], 3);
+-  __builtin_aarch64_st4v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_s8 (int8_t * __a, int8x16x4_t val)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[3], 3);
+-  __builtin_aarch64_st4v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_p8 (poly8_t * __a, poly8x16x4_t val)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[3], 3);
+-  __builtin_aarch64_st4v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_s16 (int16_t * __a, int16x8x4_t val)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[3], 3);
+-  __builtin_aarch64_st4v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_p16 (poly16_t * __a, poly16x8x4_t val)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[3], 3);
+-  __builtin_aarch64_st4v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_s32 (int32_t * __a, int32x4x4_t val)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[3], 3);
+-  __builtin_aarch64_st4v4si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_s64 (int64_t * __a, int64x2x4_t val)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_s8 (int8x16_t __a, int8x16_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[3], 3);
+-  __builtin_aarch64_st4v2di ((__builtin_aarch64_simd_di *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
++#else
++  return __builtin_shuffle (__a, __b,
++      (uint8x16_t) {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_u8 (uint8_t * __a, uint8x16x4_t val)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_s16 (int16x8_t __a, int16x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) val.val[3], 3);
+-  __builtin_aarch64_st4v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_u16 (uint16_t * __a, uint16x8x4_t val)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_s32 (int32x4_t __a, int32x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) val.val[3], 3);
+-  __builtin_aarch64_st4v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_u32 (uint32_t * __a, uint32x4x4_t val)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_s64 (int64x2_t __a, int64x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) val.val[3], 3);
+-  __builtin_aarch64_st4v4si ((__builtin_aarch64_simd_si *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_u64 (uint64_t * __a, uint64x2x4_t val)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) val.val[3], 3);
+-  __builtin_aarch64_st4v2di ((__builtin_aarch64_simd_di *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_f16 (float16_t * __a, float16x8x4_t val)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv8hf (__o, (float16x8_t) val.val[3], 3);
+-  __builtin_aarch64_st4v8hf ((__builtin_aarch64_simd_hf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_f32 (float32_t * __a, float32x4x4_t val)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) val.val[3], 3);
+-  __builtin_aarch64_st4v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
++#endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vst4q_f64 (float64_t * __a, float64x2x4_t val)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp2q_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+-  __builtin_aarch64_simd_xi __o;
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[0], 0);
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[1], 1);
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[2], 2);
+-  __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) val.val[3], 3);
+-  __builtin_aarch64_st4v2df ((__builtin_aarch64_simd_df *) __a, __o);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
++#endif
+ }
+ 
+-/* vsub */
++__INTERLEAVE_LIST (uzp)
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vsubd_s64 (int64_t __a, int64_t __b)
++/* vzip */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __a - __b;
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
++#endif
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vsubd_u64 (uint64_t __a, uint64_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-  return __a - __b;
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-/* vtbx1  */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbx1_s8 (int8x8_t __r, int8x8_t __tab, int8x8_t __idx)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+-  uint8x8_t __mask = vclt_u8 (vreinterpret_u8_s8 (__idx),
+-			      vmov_n_u8 (8));
+-  int8x8_t __tbl = vtbl1_s8 (__tab, __idx);
+-
+-  return vbsl_s8 (__mask, __tbl, __r);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
++#endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbx1_u8 (uint8x8_t __r, uint8x8_t __tab, uint8x8_t __idx)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+-  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (8));
+-  uint8x8_t __tbl = vtbl1_u8 (__tab, __idx);
+-
+-  return vbsl_u8 (__mask, __tbl, __r);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
++#endif
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbx1_p8 (poly8x8_t __r, poly8x8_t __tab, uint8x8_t __idx)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_s8 (int8x8_t __a, int8x8_t __b)
+ {
+-  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (8));
+-  poly8x8_t __tbl = vtbl1_p8 (__tab, __idx);
+-
+-  return vbsl_p8 (__mask, __tbl, __r);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
++#endif
+ }
+ 
+-/* vtbx3  */
+-
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbx3_s8 (int8x8_t __r, int8x8x3_t __tab, int8x8_t __idx)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_s16 (int16x4_t __a, int16x4_t __b)
+ {
+-  uint8x8_t __mask = vclt_u8 (vreinterpret_u8_s8 (__idx),
+-			      vmov_n_u8 (24));
+-  int8x8_t __tbl = vtbl3_s8 (__tab, __idx);
+-
+-  return vbsl_s8 (__mask, __tbl, __r);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
++#endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbx3_u8 (uint8x8_t __r, uint8x8x3_t __tab, uint8x8_t __idx)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_s32 (int32x2_t __a, int32x2_t __b)
+ {
+-  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (24));
+-  uint8x8_t __tbl = vtbl3_u8 (__tab, __idx);
+-
+-  return vbsl_u8 (__mask, __tbl, __r);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbx3_p8 (poly8x8_t __r, poly8x8x3_t __tab, uint8x8_t __idx)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+-  uint8x8_t __mask = vclt_u8 (__idx, vmov_n_u8 (24));
+-  poly8x8_t __tbl = vtbl3_p8 (__tab, __idx);
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
++#endif
++}
+ 
+-  return vbsl_p8 (__mask, __tbl, __r);
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_u16 (uint16x4_t __a, uint16x4_t __b)
++{
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
++#endif
+ }
+ 
+-/* vtbx4  */
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1_u32 (uint32x2_t __a, uint32x2_t __b)
++{
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++#endif
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtbx4_s8 (int8x8_t __r, int8x8x4_t __tab, int8x8_t __idx)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  int8x8_t result;
+-  int8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_s8 (__tab.val[0], __tab.val[1]);
+-  temp.val[1] = vcombine_s8 (__tab.val[2], __tab.val[3]);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = __builtin_aarch64_tbx4v8qi (__r, __o, __idx);
+-  return result;
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b,
++			    (uint16x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
++#else
++  return __builtin_shuffle (__a, __b,
++			    (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
++#endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtbx4_u8 (uint8x8_t __r, uint8x8x4_t __tab, uint8x8_t __idx)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-  uint8x8_t result;
+-  uint8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_u8 (__tab.val[0], __tab.val[1]);
+-  temp.val[1] = vcombine_u8 (__tab.val[2], __tab.val[3]);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = (uint8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)__r, __o,
+-						  (int8x8_t)__idx);
+-  return result;
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
++#else
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
++#endif
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtbx4_p8 (poly8x8_t __r, poly8x8x4_t __tab, uint8x8_t __idx)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_f64 (float64x2_t __a, float64x2_t __b)
+ {
+-  poly8x8_t result;
+-  poly8x16x2_t temp;
+-  __builtin_aarch64_simd_oi __o;
+-  temp.val[0] = vcombine_p8 (__tab.val[0], __tab.val[1]);
+-  temp.val[1] = vcombine_p8 (__tab.val[2], __tab.val[3]);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[0], 0);
+-  __o = __builtin_aarch64_set_qregoiv16qi (__o,
+-					   (int8x16_t) temp.val[1], 1);
+-  result = (poly8x8_t)__builtin_aarch64_tbx4v8qi ((int8x8_t)__r, __o,
+-						  (int8x8_t)__idx);
+-  return result;
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++#else
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++#endif
+ }
+ 
+-/* vtrn */
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_p8 (poly8x16_t __a, poly8x16_t __b)
++{
++#ifdef __AARCH64EB__
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
++#else
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
++#endif
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vtrn1_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++  return __builtin_shuffle (__a, __b, (uint16x8_t)
++      {12, 4, 13, 5, 14, 6, 15, 7});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+ #endif
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtrn1_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_s8 (int8x16_t __a, int8x16_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
+ #endif
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vtrn1_p16 (poly16x4_t __a, poly16x4_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_s16 (int16x8_t __a, int16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++  return __builtin_shuffle (__a, __b, (uint16x8_t)
++      {12, 4, 13, 5, 14, 6, 15, 7});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+ #endif
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtrn1_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_s32 (int32x4_t __a, int32x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
+ #endif
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vtrn1_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_s64 (int64x2_t __a, int64x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+ #endif
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vtrn1_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtrn1_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++  return __builtin_shuffle (__a, __b, (uint16x8_t)
++      {12, 4, 13, 5, 14, 6, 15, 7});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+ #endif
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vtrn1_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 1, 7, 3});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 2, 6});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
+ #endif
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vtrn1_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip1q_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+ #endif
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vtrn1q_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_f16 (float16x4_t __a, float16x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vtrn1q_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_f32 (float32x2_t __a, float32x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+ #endif
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vtrn1q_p8 (poly8x16_t __a, poly8x16_t __b)
++__extension__ extern __inline poly8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vtrn1q_p16 (poly16x8_t __a, poly16x8_t __b)
++__extension__ extern __inline poly16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vtrn1q_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline int8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_s8 (int8x8_t __a, int8x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vtrn1q_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_s16 (int16x4_t __a, int16x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vtrn1q_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline int32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_s32 (int32x2_t __a, int32x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+ #endif
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vtrn1q_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline uint8x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vtrn1q_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {17, 1, 19, 3, 21, 5, 23, 7, 25, 9, 27, 11, 29, 13, 31, 15});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30});
++  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vtrn1q_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline uint32x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 1, 11, 3, 13, 5, 15, 7});
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 2, 10, 4, 12, 6, 14});
++  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+ #endif
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vtrn1q_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_f16 (float16x8_t __a, float16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 1, 7, 3});
++  return __builtin_shuffle (__a, __b,
++			    (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 2, 6});
++  return __builtin_shuffle (__a, __b,
++			    (uint16x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vtrn1q_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_f32 (float32x4_t __a, float32x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vtrn2_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_f64 (float64x2_t __a, float64x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+ #endif
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vtrn2_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline poly8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
+ #endif
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vtrn2_p16 (poly16x4_t __a, poly16x4_t __b)
++__extension__ extern __inline poly16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++  return __builtin_shuffle (__a, __b, (uint16x8_t)
++      {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vtrn2_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline int8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_s8 (int8x16_t __a, int8x16_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
+ #endif
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vtrn2_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_s16 (int16x8_t __a, int16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++  return __builtin_shuffle (__a, __b, (uint16x8_t)
++      {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vtrn2_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline int32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_s32 (int32x4_t __a, int32x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtrn2_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline int64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_s64 (int64x2_t __a, int64x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
++  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+ #endif
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vtrn2_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline uint8x16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 6, 2});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 5, 3, 7});
++  return __builtin_shuffle (__a, __b, (uint8x16_t)
++      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
+ #endif
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vtrn2_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
++  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
++  return __builtin_shuffle (__a, __b, (uint16x8_t)
++      {4, 12, 5, 13, 6, 14, 7, 15});
+ #endif
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vtrn2q_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline uint32x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+ #ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
+ #else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
++  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
+ #endif
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vtrn2q_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint64x2_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vzip2q_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+ #ifdef __AARCH64EB__
+   return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+@@ -24455,1319 +30367,1184 @@ vtrn2q_f64 (float64x2_t __a, float64x2_t __b)
+ #endif
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vtrn2q_p8 (poly8x16_t __a, poly8x16_t __b)
++__INTERLEAVE_LIST (zip)
++
++#undef __INTERLEAVE_LIST
++#undef __DEFINTERLEAVE
++
++/* End of optimal implementations in approved order.  */
++
++#pragma GCC pop_options
++
++/* ARMv8.2-A FP16 intrinsics.  */
++
++#include "arm_fp16.h"
++
++#pragma GCC push_options
++#pragma GCC target ("arch=armv8.2-a+fp16")
++
++/* ARMv8.2-A FP16 one operand vector intrinsics.  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_absv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_absv8hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_cmeqv4hf_uss (__a, vdup_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_cmeqv8hf_uss (__a, vdupq_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_cmgev4hf_uss (__a, vdup_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_cmgev8hf_uss (__a, vdupq_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_cmgtv4hf_uss (__a, vdup_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_cmgtv8hf_uss (__a, vdupq_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_cmlev4hf_uss (__a, vdup_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_cmlev8hf_uss (__a, vdupq_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_cmltv4hf_uss (__a, vdup_n_f16 (0.0f));
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_cmltv8hf_uss (__a, vdupq_n_f16 (0.0f));
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f16_s16 (int16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
+-#endif
++  return __builtin_aarch64_floatv4hiv4hf (__a);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vtrn2q_p16 (poly16x8_t __a, poly16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f16_s16 (int16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
+-#endif
++  return __builtin_aarch64_floatv8hiv8hf (__a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vtrn2q_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f16_u16 (uint16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
+-#endif
++  return __builtin_aarch64_floatunsv4hiv4hf ((int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vtrn2q_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f16_u16 (uint16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
+-#endif
++  return __builtin_aarch64_floatunsv8hiv8hf ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vtrn2q_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_s16_f16 (float16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
+-#endif
++  return __builtin_aarch64_lbtruncv4hfv4hi (__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vtrn2q_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_s16_f16 (float16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_lbtruncv8hfv8hi (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vtrn2q_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_u16_f16 (float16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {16, 0, 18, 2, 20, 4, 22, 6, 24, 8, 26, 10, 28, 12, 30, 14});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31});
+-#endif
++  return __builtin_aarch64_lbtruncuv4hfv4hi_us (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vtrn2q_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_u16_f16 (float16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 10, 2, 12, 4, 14, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 9, 3, 11, 5, 13, 7, 15});
+-#endif
++  return __builtin_aarch64_lbtruncuv8hfv8hi_us (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vtrn2q_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_s16_f16 (float16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 6, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 5, 3, 7});
+-#endif
++  return __builtin_aarch64_lroundv4hfv4hi (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vtrn2q_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_s16_f16 (float16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_lroundv8hfv8hi (__a);
+ }
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
+-vtrn_f32 (float32x2_t a, float32x2_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_u16_f16 (float16x4_t __a)
+ {
+-  return (float32x2x2_t) {vtrn1_f32 (a, b), vtrn2_f32 (a, b)};
++  return __builtin_aarch64_lrounduv4hfv4hi_us (__a);
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
+-vtrn_p8 (poly8x8_t a, poly8x8_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_u16_f16 (float16x8_t __a)
+ {
+-  return (poly8x8x2_t) {vtrn1_p8 (a, b), vtrn2_p8 (a, b)};
++  return __builtin_aarch64_lrounduv8hfv8hi_us (__a);
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
+-vtrn_p16 (poly16x4_t a, poly16x4_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_s16_f16 (float16x4_t __a)
+ {
+-  return (poly16x4x2_t) {vtrn1_p16 (a, b), vtrn2_p16 (a, b)};
++  return __builtin_aarch64_lfloorv4hfv4hi (__a);
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
+-vtrn_s8 (int8x8_t a, int8x8_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_s16_f16 (float16x8_t __a)
+ {
+-  return (int8x8x2_t) {vtrn1_s8 (a, b), vtrn2_s8 (a, b)};
++  return __builtin_aarch64_lfloorv8hfv8hi (__a);
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
+-vtrn_s16 (int16x4_t a, int16x4_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_u16_f16 (float16x4_t __a)
+ {
+-  return (int16x4x2_t) {vtrn1_s16 (a, b), vtrn2_s16 (a, b)};
++  return __builtin_aarch64_lflooruv4hfv4hi_us (__a);
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
+-vtrn_s32 (int32x2_t a, int32x2_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_u16_f16 (float16x8_t __a)
+ {
+-  return (int32x2x2_t) {vtrn1_s32 (a, b), vtrn2_s32 (a, b)};
++  return __builtin_aarch64_lflooruv8hfv8hi_us (__a);
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
+-vtrn_u8 (uint8x8_t a, uint8x8_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_s16_f16 (float16x4_t __a)
+ {
+-  return (uint8x8x2_t) {vtrn1_u8 (a, b), vtrn2_u8 (a, b)};
++  return __builtin_aarch64_lfrintnv4hfv4hi (__a);
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
+-vtrn_u16 (uint16x4_t a, uint16x4_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_s16_f16 (float16x8_t __a)
+ {
+-  return (uint16x4x2_t) {vtrn1_u16 (a, b), vtrn2_u16 (a, b)};
++  return __builtin_aarch64_lfrintnv8hfv8hi (__a);
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
+-vtrn_u32 (uint32x2_t a, uint32x2_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_u16_f16 (float16x4_t __a)
+ {
+-  return (uint32x2x2_t) {vtrn1_u32 (a, b), vtrn2_u32 (a, b)};
++  return __builtin_aarch64_lfrintnuv4hfv4hi_us (__a);
+ }
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
+-vtrnq_f32 (float32x4_t a, float32x4_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_u16_f16 (float16x8_t __a)
+ {
+-  return (float32x4x2_t) {vtrn1q_f32 (a, b), vtrn2q_f32 (a, b)};
++  return __builtin_aarch64_lfrintnuv8hfv8hi_us (__a);
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
+-vtrnq_p8 (poly8x16_t a, poly8x16_t b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_s16_f16 (float16x4_t __a)
+ {
+-  return (poly8x16x2_t) {vtrn1q_p8 (a, b), vtrn2q_p8 (a, b)};
++  return __builtin_aarch64_lceilv4hfv4hi (__a);
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
+-vtrnq_p16 (poly16x8_t a, poly16x8_t b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_s16_f16 (float16x8_t __a)
+ {
+-  return (poly16x8x2_t) {vtrn1q_p16 (a, b), vtrn2q_p16 (a, b)};
++  return __builtin_aarch64_lceilv8hfv8hi (__a);
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
+-vtrnq_s8 (int8x16_t a, int8x16_t b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_u16_f16 (float16x4_t __a)
+ {
+-  return (int8x16x2_t) {vtrn1q_s8 (a, b), vtrn2q_s8 (a, b)};
++  return __builtin_aarch64_lceiluv4hfv4hi_us (__a);
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
+-vtrnq_s16 (int16x8_t a, int16x8_t b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_u16_f16 (float16x8_t __a)
+ {
+-  return (int16x8x2_t) {vtrn1q_s16 (a, b), vtrn2q_s16 (a, b)};
++  return __builtin_aarch64_lceiluv8hfv8hi_us (__a);
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
+-vtrnq_s32 (int32x4_t a, int32x4_t b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_f16 (float16x4_t __a)
+ {
+-  return (int32x4x2_t) {vtrn1q_s32 (a, b), vtrn2q_s32 (a, b)};
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
+-vtrnq_u8 (uint8x16_t a, uint8x16_t b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_f16 (float16x8_t __a)
+ {
+-  return (uint8x16x2_t) {vtrn1q_u8 (a, b), vtrn2q_u8 (a, b)};
++  return -__a;
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
+-vtrnq_u16 (uint16x8_t a, uint16x8_t b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpe_f16 (float16x4_t __a)
+ {
+-  return (uint16x8x2_t) {vtrn1q_u16 (a, b), vtrn2q_u16 (a, b)};
++  return __builtin_aarch64_frecpev4hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
+-vtrnq_u32 (uint32x4_t a, uint32x4_t b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpeq_f16 (float16x8_t __a)
+ {
+-  return (uint32x4x2_t) {vtrn1q_u32 (a, b), vtrn2q_u32 (a, b)};
++  return __builtin_aarch64_frecpev8hf (__a);
+ }
+ 
+-/* vtst */
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrnd_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_btruncv4hf (__a);
++}
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtst_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndq_f16 (float16x8_t __a)
+ {
+-  return (uint8x8_t) ((__a & __b) != 0);
++  return __builtin_aarch64_btruncv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vtst_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrnda_f16 (float16x4_t __a)
+ {
+-  return (uint16x4_t) ((__a & __b) != 0);
++  return __builtin_aarch64_roundv4hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vtst_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndaq_f16 (float16x8_t __a)
+ {
+-  return (uint32x2_t) ((__a & __b) != 0);
++  return __builtin_aarch64_roundv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vtst_s64 (int64x1_t __a, int64x1_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndi_f16 (float16x4_t __a)
+ {
+-  return (uint64x1_t) ((__a & __b) != __AARCH64_INT64_C (0));
++  return __builtin_aarch64_nearbyintv4hf (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vtst_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndiq_f16 (float16x8_t __a)
+ {
+-  return ((__a & __b) != 0);
++  return __builtin_aarch64_nearbyintv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vtst_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndm_f16 (float16x4_t __a)
+ {
+-  return ((__a & __b) != 0);
++  return __builtin_aarch64_floorv4hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vtst_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndmq_f16 (float16x8_t __a)
+ {
+-  return ((__a & __b) != 0);
++  return __builtin_aarch64_floorv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vtst_u64 (uint64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndn_f16 (float16x4_t __a)
+ {
+-  return ((__a & __b) != __AARCH64_UINT64_C (0));
++  return __builtin_aarch64_frintnv4hf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vtstq_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndnq_f16 (float16x8_t __a)
+ {
+-  return (uint8x16_t) ((__a & __b) != 0);
++  return __builtin_aarch64_frintnv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vtstq_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndp_f16 (float16x4_t __a)
+ {
+-  return (uint16x8_t) ((__a & __b) != 0);
++  return __builtin_aarch64_ceilv4hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vtstq_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndpq_f16 (float16x8_t __a)
+ {
+-  return (uint32x4_t) ((__a & __b) != 0);
++  return __builtin_aarch64_ceilv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vtstq_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndx_f16 (float16x4_t __a)
+ {
+-  return (uint64x2_t) ((__a & __b) != __AARCH64_INT64_C (0));
++  return __builtin_aarch64_rintv4hf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vtstq_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrndxq_f16 (float16x8_t __a)
+ {
+-  return ((__a & __b) != 0);
++  return __builtin_aarch64_rintv8hf (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vtstq_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrte_f16 (float16x4_t a)
+ {
+-  return ((__a & __b) != 0);
++  return __builtin_aarch64_rsqrtev4hf (a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vtstq_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrteq_f16 (float16x8_t a)
+ {
+-  return ((__a & __b) != 0);
++  return __builtin_aarch64_rsqrtev8hf (a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vtstq_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqrt_f16 (float16x4_t a)
+ {
+-  return ((__a & __b) != __AARCH64_UINT64_C (0));
++  return __builtin_aarch64_sqrtv4hf (a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vtstd_s64 (int64_t __a, int64_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsqrtq_f16 (float16x8_t a)
+ {
+-  return (__a & __b) ? -1ll : 0ll;
++  return __builtin_aarch64_sqrtv8hf (a);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+-vtstd_u64 (uint64_t __a, uint64_t __b)
++/* ARMv8.2-A FP16 two operands vector intrinsics.  */
++
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vadd_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return (__a & __b) ? -1ll : 0ll;
++  return __a + __b;
+ }
+ 
+-/* vuqadd */
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vaddq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __a + __b;
++}
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vuqadd_s8 (int8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabd_f16 (float16x4_t a, float16x4_t b)
+ {
+-  return __builtin_aarch64_suqaddv8qi_ssu (__a,  __b);
++  return __builtin_aarch64_fabdv4hf (a, b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vuqadd_s16 (int16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vabdq_f16 (float16x8_t a, float16x8_t b)
+ {
+-  return __builtin_aarch64_suqaddv4hi_ssu (__a,  __b);
++  return __builtin_aarch64_fabdv8hf (a, b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vuqadd_s32 (int32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcage_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __builtin_aarch64_suqaddv2si_ssu (__a,  __b);
++  return __builtin_aarch64_facgev4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+-vuqadd_s64 (int64x1_t __a, uint64x1_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcageq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  return (int64x1_t) {__builtin_aarch64_suqadddi_ssu (__a[0], __b[0])};
++  return __builtin_aarch64_facgev8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vuqaddq_s8 (int8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagt_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __builtin_aarch64_suqaddv16qi_ssu (__a,  __b);
++  return __builtin_aarch64_facgtv4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vuqaddq_s16 (int16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcagtq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  return __builtin_aarch64_suqaddv8hi_ssu (__a,  __b);
++  return __builtin_aarch64_facgtv8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vuqaddq_s32 (int32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcale_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __builtin_aarch64_suqaddv4si_ssu (__a,  __b);
++  return __builtin_aarch64_faclev4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vuqaddq_s64 (int64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaleq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  return __builtin_aarch64_suqaddv2di_ssu (__a,  __b);
++  return __builtin_aarch64_faclev8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
+-vuqaddb_s8 (int8_t __a, uint8_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcalt_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __builtin_aarch64_suqaddqi_ssu (__a,  __b);
++  return __builtin_aarch64_facltv4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
+-vuqaddh_s16 (int16_t __a, uint16_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcaltq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  return __builtin_aarch64_suqaddhi_ssu (__a,  __b);
++  return __builtin_aarch64_facltv8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+-vuqadds_s32 (int32_t __a, uint32_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-  return __builtin_aarch64_suqaddsi_ssu (__a,  __b);
++  return __builtin_aarch64_cmeqv4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+-vuqaddd_s64 (int64_t __a, uint64_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-  return __builtin_aarch64_suqadddi_ssu (__a,  __b);
++  return __builtin_aarch64_cmeqv8hf_uss (__a, __b);
+ }
+ 
+-#define __DEFINTERLEAVE(op, rettype, intype, funcsuffix, Q) 		\
+-  __extension__ static __inline rettype					\
+-  __attribute__ ((__always_inline__))					\
+-  v ## op ## Q ## _ ## funcsuffix (intype a, intype b)			\
+-  {									\
+-    return (rettype) {v ## op ## 1 ## Q ## _ ## funcsuffix (a, b),	\
+-		      v ## op ## 2 ## Q ## _ ## funcsuffix (a, b)};	\
+-  }
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_aarch64_cmgev4hf_uss (__a, __b);
++}
+ 
+-#define __INTERLEAVE_LIST(op)					\
+-  __DEFINTERLEAVE (op, float32x2x2_t, float32x2_t, f32,)	\
+-  __DEFINTERLEAVE (op, poly8x8x2_t, poly8x8_t, p8,)		\
+-  __DEFINTERLEAVE (op, poly16x4x2_t, poly16x4_t, p16,)		\
+-  __DEFINTERLEAVE (op, int8x8x2_t, int8x8_t, s8,)		\
+-  __DEFINTERLEAVE (op, int16x4x2_t, int16x4_t, s16,)		\
+-  __DEFINTERLEAVE (op, int32x2x2_t, int32x2_t, s32,)		\
+-  __DEFINTERLEAVE (op, uint8x8x2_t, uint8x8_t, u8,)		\
+-  __DEFINTERLEAVE (op, uint16x4x2_t, uint16x4_t, u16,)		\
+-  __DEFINTERLEAVE (op, uint32x2x2_t, uint32x2_t, u32,)		\
+-  __DEFINTERLEAVE (op, float32x4x2_t, float32x4_t, f32, q)	\
+-  __DEFINTERLEAVE (op, poly8x16x2_t, poly8x16_t, p8, q)		\
+-  __DEFINTERLEAVE (op, poly16x8x2_t, poly16x8_t, p16, q)	\
+-  __DEFINTERLEAVE (op, int8x16x2_t, int8x16_t, s8, q)		\
+-  __DEFINTERLEAVE (op, int16x8x2_t, int16x8_t, s16, q)		\
+-  __DEFINTERLEAVE (op, int32x4x2_t, int32x4_t, s32, q)		\
+-  __DEFINTERLEAVE (op, uint8x16x2_t, uint8x16_t, u8, q)		\
+-  __DEFINTERLEAVE (op, uint16x8x2_t, uint16x8_t, u16, q)	\
+-  __DEFINTERLEAVE (op, uint32x4x2_t, uint32x4_t, u32, q)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_aarch64_cmgev8hf_uss (__a, __b);
++}
+ 
+-/* vuzp */
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_aarch64_cmgtv4hf_uss (__a, __b);
++}
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vuzp1_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_cmgtv8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vuzp1_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
+-#endif
++  return __builtin_aarch64_cmlev4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vuzp1_p16 (poly16x4_t __a, poly16x4_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
+-#endif
++  return __builtin_aarch64_cmlev8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vuzp1_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
+-#endif
++  return __builtin_aarch64_cmltv4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vuzp1_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
+-#endif
++  return __builtin_aarch64_cmltv8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vuzp1_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f16_s16 (int16x4_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_scvtfv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vuzp1_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f16_s16 (int16x8_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
+-#endif
++  return __builtin_aarch64_scvtfv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vuzp1_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f16_u16 (uint16x4_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {5, 7, 1, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 2, 4, 6});
+-#endif
++  return __builtin_aarch64_ucvtfv4hi_sus (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f16_u16 (uint16x8_t __a, const int __b)
++{
++  return __builtin_aarch64_ucvtfv8hi_sus (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vuzp1_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline int16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_s16_f16 (float16x4_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_fcvtzsv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vuzp1q_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline int16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_s16_f16 (float16x8_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
+-#endif
++  return __builtin_aarch64_fcvtzsv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vuzp1q_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline uint16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_u16_f16 (float16x4_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_fcvtzuv4hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vuzp1q_p8 (poly8x16_t __a, poly8x16_t __b)
++__extension__ extern __inline uint16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_u16_f16 (float16x8_t __a, const int __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
+-#endif
++  return __builtin_aarch64_fcvtzuv8hf_uss (__a, __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vuzp1q_p16 (poly16x8_t __a, poly16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdiv_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
+-#endif
++  return __a / __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vuzp1q_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vdivq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
+-#endif
++  return __a / __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vuzp1q_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
+-#endif
++  return __builtin_aarch64_smax_nanv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vuzp1q_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
+-#endif
++  return __builtin_aarch64_smax_nanv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vuzp1q_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnm_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_fmaxv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vuzp1q_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
+-#endif
++  return __builtin_aarch64_fmaxv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vuzp1q_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {9, 11, 13, 15, 1, 3, 5, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 2, 4, 6, 8, 10, 12, 14});
+-#endif
++  return __builtin_aarch64_smin_nanv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vuzp1q_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {5, 7, 1, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 2, 4, 6});
+-#endif
++  return __builtin_aarch64_smin_nanv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vuzp1q_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnm_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_fminv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vuzp2_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_fminv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vuzp2_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
+-#endif
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vuzp2_p16 (poly16x4_t __a, poly16x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
+-#endif
++  return __a * __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vuzp2_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
+-#endif
++  return __builtin_aarch64_fmulxv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vuzp2_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
+-#endif
++  return __builtin_aarch64_fmulxv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vuzp2_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_f16 (float16x4_t a, float16x4_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_faddpv4hf (a, b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vuzp2_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpaddq_f16 (float16x8_t a, float16x8_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
+-#endif
++  return __builtin_aarch64_faddpv8hf (a, b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vuzp2_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_f16 (float16x4_t a, float16x4_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 6, 0, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {1, 3, 5, 7});
+-#endif
++  return __builtin_aarch64_smax_nanpv4hf (a, b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vuzp2_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxq_f16 (float16x8_t a, float16x8_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_smax_nanpv8hf (a, b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vuzp2q_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnm_f16 (float16x4_t a, float16x4_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
+-#endif
++  return __builtin_aarch64_smaxpv4hf (a, b);
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vuzp2q_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmaxnmq_f16 (float16x8_t a, float16x8_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_smaxpv8hf (a, b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vuzp2q_p8 (poly8x16_t __a, poly8x16_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_f16 (float16x4_t a, float16x4_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
+-#endif
++  return __builtin_aarch64_smin_nanpv4hf (a, b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vuzp2q_p16 (poly16x8_t __a, poly16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminq_f16 (float16x8_t a, float16x8_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
+-#endif
++  return __builtin_aarch64_smin_nanpv8hf (a, b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vuzp2q_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnm_f16 (float16x4_t a, float16x4_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
+-#else
+-  return __builtin_shuffle (__a, __b,
+-      (uint8x16_t) {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
+-#endif
++  return __builtin_aarch64_sminpv4hf (a, b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vuzp2q_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vpminnmq_f16 (float16x8_t a, float16x8_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
+-#endif
++  return __builtin_aarch64_sminpv8hf (a, b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vuzp2q_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecps_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
+-#endif
++  return __builtin_aarch64_frecpsv4hf (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vuzp2q_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpsq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_frecpsv8hf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vuzp2q_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrts_f16 (float16x4_t a, float16x4_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31});
+-#endif
++  return __builtin_aarch64_rsqrtsv4hf (a, b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vuzp2q_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtsq_f16 (float16x8_t a, float16x8_t b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 10, 12, 14, 0, 2, 4, 6});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {1, 3, 5, 7, 9, 11, 13, 15});
+-#endif
++  return __builtin_aarch64_rsqrtsv8hf (a, b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vuzp2q_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsub_f16 (float16x4_t __a, float16x4_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 6, 0, 2});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {1, 3, 5, 7});
+-#endif
++  return __a - __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vuzp2q_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vsubq_f16 (float16x8_t __a, float16x8_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __a - __b;
+ }
+ 
+-__INTERLEAVE_LIST (uzp)
+-
+-/* vzip */
++/* ARMv8.2-A FP16 three operands vector intrinsics.  */
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vzip1_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_f16 (float16x4_t __a, float16x4_t __b, float16x4_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
+-#endif
++  return __builtin_aarch64_fmav4hf (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vzip1_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+-#endif
++  return __builtin_aarch64_fmav8hf (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vzip1_p16 (poly16x4_t __a, poly16x4_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_f16 (float16x4_t __a, float16x4_t __b, float16x4_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
+-#endif
++  return __builtin_aarch64_fnmav4hf (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vzip1_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+-#endif
++  return __builtin_aarch64_fnmav8hf (__b, __c, __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vzip1_s16 (int16x4_t __a, int16x4_t __b)
+-{
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
+-#endif
++/* ARMv8.2-A FP16 lane vector intrinsics.  */
++
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmah_lane_f16 (float16_t __a, float16_t __b,
++		float16x4_t __c, const int __lane)
++{
++  return vfmah_f16 (__a, __b, __aarch64_vget_lane_any (__c, __lane));
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vzip1_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmah_laneq_f16 (float16_t __a, float16_t __b,
++		 float16x8_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
+-#endif
++  return vfmah_f16 (__a, __b, __aarch64_vget_lane_any (__c, __lane));
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vzip1_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_lane_f16 (float16x4_t __a, float16x4_t __b,
++	       float16x4_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {12, 4, 13, 5, 14, 6, 15, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+-#endif
++  return vfma_f16 (__a, __b, __aarch64_vdup_lane_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vzip1_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_lane_f16 (float16x8_t __a, float16x8_t __b,
++		float16x4_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {6, 2, 7, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {0, 4, 1, 5});
+-#endif
++  return vfmaq_f16 (__a, __b, __aarch64_vdupq_lane_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vzip1_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_laneq_f16 (float16x4_t __a, float16x4_t __b,
++		float16x8_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {0, 2});
+-#endif
++  return vfma_f16 (__a, __b, __aarch64_vdup_laneq_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vzip1q_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_laneq_f16 (float16x8_t __a, float16x8_t __b,
++		 float16x8_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
+-#endif
++  return vfmaq_f16 (__a, __b, __aarch64_vdupq_laneq_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vzip1q_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_n_f16 (float16x4_t __a, float16x4_t __b, float16_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+-#endif
++  return vfma_f16 (__a, __b, vdup_n_f16 (__c));
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vzip1q_p8 (poly8x16_t __a, poly8x16_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
+-#endif
++  return vfmaq_f16 (__a, __b, vdupq_n_f16 (__c));
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vzip1q_p16 (poly16x8_t __a, poly16x8_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsh_lane_f16 (float16_t __a, float16_t __b,
++		float16x4_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t)
+-      {12, 4, 13, 5, 14, 6, 15, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+-#endif
++  return vfmsh_f16 (__a, __b, __aarch64_vget_lane_any (__c, __lane));
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vzip1q_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsh_laneq_f16 (float16_t __a, float16_t __b,
++		 float16x8_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
+-#endif
++  return vfmsh_f16 (__a, __b, __aarch64_vget_lane_any (__c, __lane));
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vzip1q_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_lane_f16 (float16x4_t __a, float16x4_t __b,
++	       float16x4_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t)
+-      {12, 4, 13, 5, 14, 6, 15, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+-#endif
++  return vfms_f16 (__a, __b, __aarch64_vdup_lane_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vzip1q_s32 (int32x4_t __a, int32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_lane_f16 (float16x8_t __a, float16x8_t __b,
++		float16x4_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
+-#endif
++  return vfmsq_f16 (__a, __b, __aarch64_vdupq_lane_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vzip1q_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_laneq_f16 (float16x4_t __a, float16x4_t __b,
++		float16x8_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+-#endif
++  return vfms_f16 (__a, __b, __aarch64_vdup_laneq_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vzip1q_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_laneq_f16 (float16x8_t __a, float16x8_t __b,
++		 float16x8_t __c, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23});
+-#endif
++  return vfmsq_f16 (__a, __b, __aarch64_vdupq_laneq_f16 (__c, __lane));
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vzip1q_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_n_f16 (float16x4_t __a, float16x4_t __b, float16_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t)
+-      {12, 4, 13, 5, 14, 6, 15, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {0, 8, 1, 9, 2, 10, 3, 11});
+-#endif
++  return vfms_f16 (__a, __b, vdup_n_f16 (__c));
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vzip1q_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {6, 2, 7, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {0, 4, 1, 5});
+-#endif
++  return vfmsq_f16 (__a, __b, vdupq_n_f16 (__c));
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vzip1q_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulh_lane_f16 (float16_t __a, float16x4_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {3, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {0, 2});
+-#endif
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+-vzip2_f32 (float32x2_t __a, float32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_f16 (float16x4_t __a, float16x4_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+-#endif
++  return vmul_f16 (__a, vdup_n_f16 (__aarch64_vget_lane_any (__b, __lane)));
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
+-vzip2_p8 (poly8x8_t __a, poly8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_f16 (float16x8_t __a, float16x4_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+-#endif
++  return vmulq_f16 (__a, vdupq_n_f16 (__aarch64_vget_lane_any (__b, __lane)));
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
+-vzip2_p16 (poly16x4_t __a, poly16x4_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulh_laneq_f16 (float16_t __a, float16x8_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+-#endif
++  return __a * __aarch64_vget_lane_any (__b, __lane);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
+-vzip2_s8 (int8x8_t __a, int8x8_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_laneq_f16 (float16x4_t __a, float16x8_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+-#endif
++  return vmul_f16 (__a, vdup_n_f16 (__aarch64_vget_lane_any (__b, __lane)));
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
+-vzip2_s16 (int16x4_t __a, int16x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_laneq_f16 (float16x8_t __a, float16x8_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+-#endif
++  return vmulq_f16 (__a, vdupq_n_f16 (__aarch64_vget_lane_any (__b, __lane)));
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+-vzip2_s32 (int32x2_t __a, int32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_f16 (float16x4_t __a, float16_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+-#endif
++  return vmul_lane_f16 (__a, vdup_n_f16 (__b), 0);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
+-vzip2_u8 (uint8x8_t __a, uint8x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_f16 (float16x8_t __a, float16_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x8_t) {4, 12, 5, 13, 6, 14, 7, 15});
+-#endif
++  return vmulq_laneq_f16 (__a, vdupq_n_f16 (__b), 0);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
+-vzip2_u16 (uint16x4_t __a, uint16x4_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxh_lane_f16 (float16_t __a, float16x4_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {4, 0, 5, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x4_t) {2, 6, 3, 7});
+-#endif
++  return vmulxh_f16 (__a, __aarch64_vget_lane_any (__b, __lane));
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+-vzip2_u32 (uint32x2_t __a, uint32x2_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_lane_f16 (float16x4_t __a, float16x4_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x2_t) {1, 3});
+-#endif
++  return vmulx_f16 (__a, __aarch64_vdup_lane_f16 (__b, __lane));
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+-vzip2q_f32 (float32x4_t __a, float32x4_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_lane_f16 (float16x8_t __a, float16x4_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
+-#endif
++  return vmulxq_f16 (__a, __aarch64_vdupq_lane_f16 (__b, __lane));
+ }
+ 
+-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+-vzip2q_f64 (float64x2_t __a, float64x2_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxh_laneq_f16 (float16_t __a, float16x8_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return vmulxh_f16 (__a, __aarch64_vget_lane_any (__b, __lane));
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
+-vzip2q_p8 (poly8x16_t __a, poly8x16_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_laneq_f16 (float16x4_t __a, float16x8_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
+-#endif
++  return vmulx_f16 (__a, __aarch64_vdup_laneq_f16 (__b, __lane));
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
+-vzip2q_p16 (poly16x8_t __a, poly16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_laneq_f16 (float16x8_t __a, float16x8_t __b, const int __lane)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t)
+-      {4, 12, 5, 13, 6, 14, 7, 15});
+-#endif
++  return vmulxq_f16 (__a, __aarch64_vdupq_laneq_f16 (__b, __lane));
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+-vzip2q_s8 (int8x16_t __a, int8x16_t __b)
++__extension__ extern __inline float16x4_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulx_n_f16 (float16x4_t __a, float16_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
+-#endif
++  return vmulx_f16 (__a, vdup_n_f16 (__b));
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+-vzip2q_s16 (int16x8_t __a, int16x8_t __b)
++__extension__ extern __inline float16x8_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmulxq_n_f16 (float16x8_t __a, float16_t __b)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t)
+-      {4, 12, 5, 13, 6, 14, 7, 15});
+-#endif
++  return vmulxq_f16 (__a, vdupq_n_f16 (__b));
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+-vzip2q_s32 (int32x4_t __a, int32x4_t __b)
++/* ARMv8.2-A FP16 reduction vector intrinsics.  */
++
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxv_f16 (float16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
+-#endif
++  return __builtin_aarch64_reduc_smax_nan_scal_v4hf (__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+-vzip2q_s64 (int64x2_t __a, int64x2_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxvq_f16 (float16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_reduc_smax_nan_scal_v8hf (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vzip2q_u8 (uint8x16_t __a, uint8x16_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminv_f16 (float16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint8x16_t)
+-      {8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31});
+-#endif
++  return __builtin_aarch64_reduc_smin_nan_scal_v4hf (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
+-vzip2q_u16 (uint16x8_t __a, uint16x8_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminvq_f16 (float16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint16x8_t) {8, 0, 9, 1, 10, 2, 11, 3});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint16x8_t)
+-      {4, 12, 5, 13, 6, 14, 7, 15});
+-#endif
++  return __builtin_aarch64_reduc_smin_nan_scal_v8hf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vzip2q_u32 (uint32x4_t __a, uint32x4_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmv_f16 (float16x4_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {4, 0, 5, 1});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint32x4_t) {2, 6, 3, 7});
+-#endif
++  return __builtin_aarch64_reduc_smax_scal_v4hf (__a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+-vzip2q_u64 (uint64x2_t __a, uint64x2_t __b)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmvq_f16 (float16x8_t __a)
+ {
+-#ifdef __AARCH64EB__
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {2, 0});
+-#else
+-  return __builtin_shuffle (__a, __b, (uint64x2_t) {1, 3});
+-#endif
++  return __builtin_aarch64_reduc_smax_scal_v8hf (__a);
+ }
+ 
+-__INTERLEAVE_LIST (zip)
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmv_f16 (float16x4_t __a)
++{
++  return __builtin_aarch64_reduc_smin_scal_v4hf (__a);
++}
+ 
+-#undef __INTERLEAVE_LIST
+-#undef __DEFINTERLEAVE
++__extension__ extern __inline float16_t
++__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmvq_f16 (float16x8_t __a)
++{
++  return __builtin_aarch64_reduc_smin_scal_v8hf (__a);
++}
+ 
+-/* End of optimal implementations in approved order.  */
++#pragma GCC pop_options
+ 
+ #undef __aarch64_vget_lane_any
+ 
+ #undef __aarch64_vdup_lane_any
++#undef __aarch64_vdup_lane_f16
+ #undef __aarch64_vdup_lane_f32
+ #undef __aarch64_vdup_lane_f64
+ #undef __aarch64_vdup_lane_p8
+@@ -25780,6 +31557,7 @@ __INTERLEAVE_LIST (zip)
+ #undef __aarch64_vdup_lane_u16
+ #undef __aarch64_vdup_lane_u32
+ #undef __aarch64_vdup_lane_u64
++#undef __aarch64_vdup_laneq_f16
+ #undef __aarch64_vdup_laneq_f32
+ #undef __aarch64_vdup_laneq_f64
+ #undef __aarch64_vdup_laneq_p8
+@@ -25792,6 +31570,7 @@ __INTERLEAVE_LIST (zip)
+ #undef __aarch64_vdup_laneq_u16
+ #undef __aarch64_vdup_laneq_u32
+ #undef __aarch64_vdup_laneq_u64
++#undef __aarch64_vdupq_lane_f16
+ #undef __aarch64_vdupq_lane_f32
+ #undef __aarch64_vdupq_lane_f64
+ #undef __aarch64_vdupq_lane_p8
+@@ -25804,6 +31583,7 @@ __INTERLEAVE_LIST (zip)
+ #undef __aarch64_vdupq_lane_u16
+ #undef __aarch64_vdupq_lane_u32
+ #undef __aarch64_vdupq_lane_u64
++#undef __aarch64_vdupq_laneq_f16
+ #undef __aarch64_vdupq_laneq_f32
+ #undef __aarch64_vdupq_laneq_f64
+ #undef __aarch64_vdupq_laneq_p8
+@@ -25817,6 +31597,4 @@ __INTERLEAVE_LIST (zip)
+ #undef __aarch64_vdupq_laneq_u32
+ #undef __aarch64_vdupq_laneq_u64
+ 
+-#pragma GCC pop_options
+-
+ #endif
+--- a/src/gcc/config/aarch64/atomics.md
++++ b/src/gcc/config/aarch64/atomics.md
+@@ -583,7 +583,7 @@
+   }
+ )
+ 
+-;; ARMv8.1 LSE instructions.
++;; ARMv8.1-A LSE instructions.
+ 
+ ;; Atomic swap with memory.
+ (define_insn "aarch64_atomic_swp<mode>"
+--- a/src/gcc/config/aarch64/cortex-a57-fma-steering.c
++++ b/src/gcc/config/aarch64/cortex-a57-fma-steering.c
+@@ -35,7 +35,6 @@
+ #include "context.h"
+ #include "tree-pass.h"
+ #include "regrename.h"
+-#include "cortex-a57-fma-steering.h"
+ #include "aarch64-protos.h"
+ 
+ /* For better performance, the destination of FMADD/FMSUB instructions should
+@@ -923,10 +922,10 @@ func_fma_steering::analyze ()
+       FOR_BB_INSNS (bb, insn)
+ 	{
+ 	  operand_rr_info *dest_op_info;
+-	  struct du_chain *chain;
++	  struct du_chain *chain = NULL;
+ 	  unsigned dest_regno;
+-	  fma_forest *forest;
+-	  du_head_p head;
++	  fma_forest *forest = NULL;
++	  du_head_p head = NULL;
+ 	  int i;
+ 
+ 	  if (!is_fmul_fmac_insn (insn, true))
+@@ -1075,21 +1074,8 @@ public:
+ 
+ /* Create a new fma steering pass instance.  */
+ 
+-static rtl_opt_pass *
++rtl_opt_pass *
+ make_pass_fma_steering (gcc::context *ctxt)
+ {
+   return new pass_fma_steering (ctxt);
+ }
+-
+-/* Register the FMA steering pass to the pass manager.  */
+-
+-void
+-aarch64_register_fma_steering ()
+-{
+-  opt_pass *pass_fma_steering = make_pass_fma_steering (g);
+-
+-  struct register_pass_info fma_steering_info
+-    = { pass_fma_steering, "rnreg", 1, PASS_POS_INSERT_AFTER };
+-
+-  register_pass (&fma_steering_info);
+-}
+--- a/src/gcc/config/aarch64/cortex-a57-fma-steering.h
++++ b/src//dev/null
+@@ -1,22 +0,0 @@
+-/* This file contains declarations for the FMA steering optimization
+-   pass for Cortex-A57.
+-   Copyright (C) 2015-2016 Free Software Foundation, Inc.
+-   Contributed by ARM Ltd.
+-
+-   This file is part of GCC.
+-
+-   GCC is free software; you can redistribute it and/or modify it
+-   under the terms of the GNU General Public License as published by
+-   the Free Software Foundation; either version 3, or (at your option)
+-   any later version.
+-
+-   GCC is distributed in the hope that it will be useful, but
+-   WITHOUT ANY WARRANTY; without even the implied warranty of
+-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-   General Public License for more details.
+-
+-   You should have received a copy of the GNU General Public License
+-   along with GCC; see the file COPYING3.  If not see
+-   <http://www.gnu.org/licenses/>.  */
+-
+-void aarch64_register_fma_steering (void);
+--- a/src/gcc/config/aarch64/geniterators.sh
++++ b/src/gcc/config/aarch64/geniterators.sh
+@@ -23,10 +23,7 @@
+ # BUILTIN_<ITERATOR> macros, which expand to VAR<N> Macros covering the
+ # same set of modes as the iterator in iterators.md
+ #
+-# Find the <ITERATOR> definitions (may span several lines), skip the ones
+-# which does not have a simple format because it contains characters we
+-# don't want to or can't handle (e.g P, PTR iterators change depending on
+-# Pmode and ptr_mode).
++# Find the <ITERATOR> definitions (may span several lines).
+ LC_ALL=C awk '
+ BEGIN {
+ 	print "/* -*- buffer-read-only: t -*- */"
+@@ -49,12 +46,24 @@ iterdef {
+ 	sub(/.*\(define_mode_iterator/, "", s)
+ }
+ 
+-iterdef && s ~ /\)/ {
++iterdef {
++	# Count the parentheses, the iterator definition ends
++	# if there are more closing ones than opening ones.
++	nopen = gsub(/\(/, "(", s)
++	nclose = gsub(/\)/, ")", s)
++	if (nopen >= nclose)
++		next
++
+ 	iterdef = 0
+ 
+ 	gsub(/[ \t]+/, " ", s)
+-	sub(/ *\).*/, "", s)
++	sub(/ *\)[^)]*$/, "", s)
+ 	sub(/^ /, "", s)
++
++	# Drop the conditions.
++	gsub(/ *"[^"]*" *\)/, "", s)
++	gsub(/\( */, "", s)
++
+ 	if (s !~ /^[A-Za-z0-9_]+ \[[A-Z0-9 ]*\]$/)
+ 		next
+ 	sub(/\[ */, "", s)
+--- a/src/gcc/config/aarch64/iterators.md
++++ b/src/gcc/config/aarch64/iterators.md
+@@ -26,6 +26,9 @@
+ ;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
+ (define_mode_iterator GPI [SI DI])
+ 
++;; Iterator for HI, SI, DI, some instructions can only work on these modes.
++(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
++
+ ;; Iterator for QI and HI modes
+ (define_mode_iterator SHORT [QI HI])
+ 
+@@ -38,6 +41,9 @@
+ ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
+ (define_mode_iterator GPF [SF DF])
+ 
++;; Iterator for all scalar floating point modes (HF, SF, DF)
++(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
++
+ ;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
+ (define_mode_iterator GPF_TF_F16 [HF SF DF TF])
+ 
+@@ -88,11 +94,21 @@
+ ;; Vector Float modes suitable for moving, loading and storing.
+ (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
+ 
+-;; Vector Float modes, barring HF modes.
++;; Vector Float modes.
+ (define_mode_iterator VDQF [V2SF V4SF V2DF])
++(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
++			     (V8HF "TARGET_SIMD_F16INST")
++			     V2SF V4SF V2DF])
+ 
+ ;; Vector Float modes, and DF.
+-(define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF])
++(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
++				(V8HF "TARGET_SIMD_F16INST")
++				V2SF V4SF V2DF DF])
++(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
++				  (V8HF "TARGET_SIMD_F16INST")
++				  V2SF V4SF V2DF
++				  (HF "TARGET_SIMD_F16INST")
++				  SF DF])
+ 
+ ;; Vector single Float modes.
+ (define_mode_iterator VDQSF [V2SF V4SF])
+@@ -116,6 +132,10 @@
+ (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
+ 				V4HF V8HF V2SF V4SF V2DF])
+ 
++;; The VALL_F16 modes except the 128-bit 2-element ones.
++(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
++				V4HF V8HF V2SF V4SF])
++
+ ;; All vector modes barring HF modes, plus DI.
+ (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
+ 
+@@ -150,10 +170,30 @@
+ 
+ ;; Vector modes except double int.
+ (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
++(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
++                                 V4HF V8HF V2SF V4SF V2DF])
+ 
+ ;; Vector modes for S type.
+ (define_mode_iterator VDQ_SI [V2SI V4SI])
+ 
++;; Vector modes for S and D
++(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
++
++;; Vector modes for H, S and D
++(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
++				(V8HI "TARGET_SIMD_F16INST")
++				V2SI V4SI V2DI])
++
++;; Scalar and Vector modes for S and D
++(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
++
++;; Scalar and Vector modes for S and D, Vector modes for H.
++(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
++				 (V8HI "TARGET_SIMD_F16INST")
++				 V2SI V4SI V2DI
++				 (HI "TARGET_SIMD_F16INST")
++				 SI DI])
++
+ ;; Vector modes for Q and H types.
+ (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
+ 
+@@ -193,7 +233,10 @@
+ (define_mode_iterator DX [DI DF])
+ 
+ ;; Modes available for <f>mul lane operations.
+-(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
++(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
++			    (V4HF "TARGET_SIMD_F16INST")
++			    (V8HF "TARGET_SIMD_F16INST")
++			    V2SF V4SF V2DF])
+ 
+ ;; Modes available for <f>mul lane operations changing lane count.
+ (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
+@@ -342,8 +385,8 @@
+ (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
+ 
+ ;; For inequal width int to float conversion
+-(define_mode_attr w1 [(SF "w") (DF "x")])
+-(define_mode_attr w2 [(SF "x") (DF "w")])
++(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
++(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
+ 
+ (define_mode_attr short_mask [(HI "65535") (QI "255")])
+ 
+@@ -355,12 +398,13 @@
+ 
+ ;; For scalar usage of vector/FP registers
+ (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
+-		    (SF "s") (DF "d")
++		    (HF  "h") (SF "s") (DF "d")
+ 		    (V8QI "") (V16QI "")
+ 		    (V4HI "") (V8HI "")
+ 		    (V2SI "") (V4SI  "")
+ 		    (V2DI "") (V2SF "")
+-		    (V4SF "") (V2DF "")])
++		    (V4SF "") (V4HF "")
++		    (V8HF "") (V2DF "")])
+ 
+ ;; For scalar usage of vector/FP registers, narrowing
+ (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
+@@ -385,7 +429,7 @@
+ (define_mode_attr vas [(DI "") (SI ".2s")])
+ 
+ ;; Map a floating point mode to the appropriate register name prefix
+-(define_mode_attr s [(SF "s") (DF "d")])
++(define_mode_attr s [(HF "h") (SF "s") (DF "d")])
+ 
+ ;; Give the length suffix letter for a sign- or zero-extension.
+ (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
+@@ -421,8 +465,8 @@
+ 			 (V4SF ".4s") (V2DF ".2d")
+ 			 (DI   "")    (SI   "")
+ 			 (HI   "")    (QI   "")
+-			 (TI   "")    (SF   "")
+-			 (DF   "")])
++			 (TI   "")    (HF   "")
++			 (SF   "")    (DF   "")])
+ 
+ ;; Register suffix narrowed modes for VQN.
+ (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
+@@ -437,10 +481,21 @@
+ 			  (V2DI "d") (V4HF "h")
+ 			  (V8HF "h") (V2SF  "s")
+ 			  (V4SF "s") (V2DF  "d")
++			  (HF   "h")
+ 			  (SF   "s") (DF  "d")
+ 			  (QI "b")   (HI "h")
+ 			  (SI "s")   (DI "d")])
+ 
++;; Vetype is used everywhere in scheduling type and assembly output,
++;; sometimes they are not the same, for example HF modes on some
++;; instructions.  stype is defined to represent scheduling type
++;; more accurately.
++(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
++			 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
++			 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
++			 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
++			 (SI "s") (DI "d")])
++
+ ;; Mode-to-bitwise operation type mapping.
+ (define_mode_attr Vbtype [(V8QI "8b")  (V16QI "16b")
+ 			  (V4HI "8b") (V8HI  "16b")
+@@ -598,7 +653,7 @@
+ 				(V4HF "V4HI") (V8HF  "V8HI")
+ 				(V2SF "V2SI") (V4SF  "V4SI")
+ 				(V2DF "V2DI") (DF    "DI")
+-				(SF   "SI")])
++				(SF   "SI")   (HF    "HI")])
+ 
+ ;; Lower case mode of results of comparison operations.
+ (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")
+@@ -648,12 +703,21 @@
+ (define_mode_attr atomic_sfx
+   [(QI "b") (HI "h") (SI "") (DI "")])
+ 
+-(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") (SF "si") (DF "di")])
+-(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") (SF "SI") (DF "DI")])
++(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
++			       (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
++			       (SF "si") (DF "di") (SI "sf") (DI "df")
++			       (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
++			       (V8HI "v8hf") (HF "hi") (HI "hf")])
++(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
++			       (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
++			       (SF "SI") (DF "DI") (SI "SF") (DI "DF")
++			       (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
++			       (V8HI "V8HF") (HF "HI") (HI "HF")])
++
+ 
+ ;; for the inequal width integer to fp conversions
+-(define_mode_attr fcvt_iesize [(SF "di") (DF "si")])
+-(define_mode_attr FCVT_IESIZE [(SF "DI") (DF "SI")])
++(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
++(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
+ 
+ (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
+ 				(V4HI "V8HI") (V8HI  "V4HI")
+@@ -672,10 +736,11 @@
+ 				    (DF   "to_128") (V2DF  "to_64")])
+ 
+ ;; For certain vector-by-element multiplication instructions we must
+-;; constrain the HI cases to use only V0-V15.  This is covered by
++;; constrain the 16-bit cases to use only V0-V15.  This is covered by
+ ;; the 'x' constraint.  All other modes may use the 'w' constraint.
+ (define_mode_attr h_con [(V2SI "w") (V4SI "w")
+ 			 (V4HI "x") (V8HI "x")
++			 (V4HF "x") (V8HF "x")
+ 			 (V2SF "w") (V4SF "w")
+ 			 (V2DF "w") (DF "w")])
+ 
+@@ -684,6 +749,7 @@
+ 		     (V4HI "")  (V8HI  "")
+ 		     (V2SI "")  (V4SI  "")
+ 		     (DI   "")  (V2DI  "")
++		     (V4HF "f") (V8HF  "f")
+ 		     (V2SF "f") (V4SF  "f")
+ 		     (V2DF "f") (DF    "f")])
+ 
+@@ -692,6 +758,7 @@
+ 		      (V4HI "")  (V8HI  "")
+ 		      (V2SI "")  (V4SI  "")
+ 		      (DI   "")  (V2DI  "")
++		      (V4HF "_fp") (V8HF  "_fp")
+ 		      (V2SF "_fp") (V4SF  "_fp")
+ 		      (V2DF "_fp") (DF    "_fp")
+ 		      (SF "_fp")])
+@@ -704,17 +771,19 @@
+ 		     (V4HF "") (V8HF "_q")
+ 		     (V2SF "") (V4SF  "_q")
+ 			       (V2DF  "_q")
+-		     (QI "") (HI "") (SI "") (DI "") (SF "") (DF "")])
++		     (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
+ 
+ (define_mode_attr vp [(V8QI "v") (V16QI "v")
+ 		      (V4HI "v") (V8HI  "v")
+ 		      (V2SI "p") (V4SI  "v")
+-		      (V2DI  "p") (V2DF  "p")
+-		      (V2SF "p") (V4SF  "v")])
++		      (V2DI "p") (V2DF  "p")
++		      (V2SF "p") (V4SF  "v")
++		      (V4HF "v") (V8HF  "v")])
+ 
+ (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
+ (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
+ 
++;; Sum of lengths of instructions needed to move vector registers of a mode.
+ (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
+ 
+ ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
+@@ -876,9 +945,6 @@
+ ;; Similar, but when not(op)
+ (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
+ 
+-;; Sign- or zero-extending load
+-(define_code_attr ldrxt [(sign_extend "ldrs") (zero_extend "ldr")])
+-
+ ;; Sign- or zero-extending data-op
+ (define_code_attr su [(sign_extend "s") (zero_extend "u")
+ 		      (sign_extract "s") (zero_extract "u")
+@@ -953,9 +1019,8 @@
+ (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
+ 			        UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
+ 
+-(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN])
+-
+-(define_int_iterator FMAXMIN [UNSPEC_FMAXNM UNSPEC_FMINNM])
++(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
++				  UNSPEC_FMAXNM UNSPEC_FMINNM])
+ 
+ (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
+ 
+@@ -1001,6 +1066,9 @@
+ (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
+ 			    UNSPEC_FRINTA UNSPEC_FRINTN])
+ 
++(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
++(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
++
+ (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
+ 
+ (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
+@@ -1036,7 +1104,9 @@
+ 			      (UNSPEC_FMAXV "smax_nan")
+ 			      (UNSPEC_FMIN "smin_nan")
+ 			      (UNSPEC_FMINNMV "smin")
+-			      (UNSPEC_FMINV "smin_nan")])
++			      (UNSPEC_FMINV "smin_nan")
++			      (UNSPEC_FMAXNM "fmax")
++			      (UNSPEC_FMINNM "fmin")])
+ 
+ (define_int_attr  maxmin_uns_op [(UNSPEC_UMAXV "umax")
+ 				 (UNSPEC_UMINV "umin")
+@@ -1047,13 +1117,9 @@
+ 				 (UNSPEC_FMAXV "fmax")
+ 				 (UNSPEC_FMIN "fmin")
+ 				 (UNSPEC_FMINNMV "fminnm")
+-				 (UNSPEC_FMINV "fmin")])
+-
+-(define_int_attr fmaxmin [(UNSPEC_FMAXNM "fmax")
+-			  (UNSPEC_FMINNM "fmin")])
+-
+-(define_int_attr fmaxmin_op [(UNSPEC_FMAXNM "fmaxnm")
+-			     (UNSPEC_FMINNM "fminnm")])
++				 (UNSPEC_FMINV "fmin")
++				 (UNSPEC_FMAXNM "fmaxnm")
++				 (UNSPEC_FMINNM "fminnm")])
+ 
+ (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
+ 		      (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
+@@ -1137,6 +1203,11 @@
+ 			       (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
+ 			       (UNSPEC_FRINTN "frintn")])
+ 
++(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
++				  (UNSPEC_UCVTF "ucvtf")
++				  (UNSPEC_FCVTZS "fcvtzs")
++				  (UNSPEC_FCVTZU "fcvtzu")])
++
+ (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
+ 			    (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
+ 			    (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
+--- a/src/gcc/config/aarch64/predicates.md
++++ b/src/gcc/config/aarch64/predicates.md
+@@ -54,9 +54,9 @@
+ 	    (match_test "op == const0_rtx"))))
+ 
+ (define_predicate "aarch64_reg_or_fp_zero"
+-  (and (match_code "reg,subreg,const_double")
+-       (ior (match_operand 0 "register_operand")
+-	    (match_test "aarch64_float_const_zero_rtx_p (op)"))))
++  (ior (match_operand 0 "register_operand")
++	(and (match_code "const_double")
++	     (match_test "aarch64_float_const_zero_rtx_p (op)"))))
+ 
+ (define_predicate "aarch64_reg_zero_or_m1_or_1"
+   (and (match_code "reg,subreg,const_int")
+--- a/src/gcc/config/aarch64/t-aarch64
++++ b/src/gcc/config/aarch64/t-aarch64
+@@ -52,16 +52,17 @@ aarch-common.o: $(srcdir)/config/arm/aarch-common.c $(CONFIG_H) $(SYSTEM_H) \
+ 		$(srcdir)/config/arm/aarch-common.c
+ 
+ aarch64-c.o: $(srcdir)/config/aarch64/aarch64-c.c $(CONFIG_H) $(SYSTEM_H) \
+-    coretypes.h $(TM_H) $(TREE_H) output.h $(C_COMMON_H)
++    coretypes.h $(TM_H) $(TREE_H) output.h $(C_COMMON_H) $(TARGET_H)
+ 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
+ 		$(srcdir)/config/aarch64/aarch64-c.c
+ 
++PASSES_EXTRA += $(srcdir)/config/aarch64/aarch64-passes.def
++
+ cortex-a57-fma-steering.o: $(srcdir)/config/aarch64/cortex-a57-fma-steering.c \
+     $(CONFIG_H) $(SYSTEM_H) $(TM_H) $(REGS_H) insn-config.h $(RTL_BASE_H) \
+     dominance.h cfg.h cfganal.h $(BASIC_BLOCK_H) $(INSN_ATTR_H) $(RECOG_H) \
+     output.h hash-map.h $(DF_H) $(OBSTACK_H) $(TARGET_H) $(RTL_H) \
+     $(CONTEXT_H) $(TREE_PASS_H) regrename.h \
+-    $(srcdir)/config/aarch64/cortex-a57-fma-steering.h \
+     $(srcdir)/config/aarch64/aarch64-protos.h
+ 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
+ 		$(srcdir)/config/aarch64/cortex-a57-fma-steering.c
+--- a/src/gcc/config/aarch64/thunderx.md
++++ b/src/gcc/config/aarch64/thunderx.md
+@@ -39,7 +39,7 @@
+ 
+ (define_insn_reservation "thunderx_shift" 1
+   (and (eq_attr "tune" "thunderx")
+-       (eq_attr "type" "bfm,extend,rotate_imm,shift_imm,shift_reg,rbit,rev"))
++       (eq_attr "type" "bfm,bfx,extend,rotate_imm,shift_imm,shift_reg,rbit,rev"))
+   "thunderx_pipe0 | thunderx_pipe1")
+ 
+ 
+--- a/src/gcc/config/alpha/alpha.c
++++ b/src/gcc/config/alpha/alpha.c
+@@ -26,6 +26,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "df.h"
+ #include "tm_p.h"
+--- a/src/gcc/config/arm/aarch-common-protos.h
++++ b/src/gcc/config/arm/aarch-common-protos.h
+@@ -30,7 +30,9 @@ extern bool aarch_rev16_p (rtx);
+ extern bool aarch_rev16_shleft_mask_imm_p (rtx, machine_mode);
+ extern bool aarch_rev16_shright_mask_imm_p (rtx, machine_mode);
+ extern int arm_early_load_addr_dep (rtx, rtx);
++extern int arm_early_load_addr_dep_ptr (rtx, rtx);
+ extern int arm_early_store_addr_dep (rtx, rtx);
++extern int arm_early_store_addr_dep_ptr (rtx, rtx);
+ extern int arm_mac_accumulator_is_mul_result (rtx, rtx);
+ extern int arm_mac_accumulator_is_result (rtx, rtx);
+ extern int arm_no_early_alu_shift_dep (rtx, rtx);
+--- a/src/gcc/config/arm/aarch-common.c
++++ b/src/gcc/config/arm/aarch-common.c
+@@ -241,6 +241,24 @@ arm_early_load_addr_dep (rtx producer, rtx consumer)
+   return reg_overlap_mentioned_p (value, addr);
+ }
+ 
++/* Return nonzero if the CONSUMER instruction (a load) does need
++   a Pmode PRODUCER's value to calculate the address.  */
++
++int
++arm_early_load_addr_dep_ptr (rtx producer, rtx consumer)
++{
++  rtx value = arm_find_sub_rtx_with_code (PATTERN (producer), SET, false);
++  rtx addr = arm_find_sub_rtx_with_code (PATTERN (consumer), SET, false);
++
++  if (!value || !addr || !MEM_P (SET_SRC (value)))
++    return 0;
++
++  value = SET_DEST (value);
++  addr = SET_SRC (addr);
++
++  return GET_MODE (value) == Pmode && reg_overlap_mentioned_p (value, addr);
++}
++
+ /* Return nonzero if the CONSUMER instruction (an ALU op) does not
+    have an early register shift value or amount dependency on the
+    result of PRODUCER.  */
+@@ -336,6 +354,24 @@ arm_early_store_addr_dep (rtx producer, rtx consumer)
+   return !arm_no_early_store_addr_dep (producer, consumer);
+ }
+ 
++/* Return nonzero if the CONSUMER instruction (a store) does need
++   a Pmode PRODUCER's value to calculate the address.  */
++
++int
++arm_early_store_addr_dep_ptr (rtx producer, rtx consumer)
++{
++  rtx value = arm_find_sub_rtx_with_code (PATTERN (producer), SET, false);
++  rtx addr = arm_find_sub_rtx_with_code (PATTERN (consumer), SET, false);
++
++  if (!value || !addr || !MEM_P (SET_SRC (value)))
++    return 0;
++
++  value = SET_DEST (value);
++  addr = SET_DEST (addr);
++
++  return GET_MODE (value) == Pmode && reg_overlap_mentioned_p (value, addr);
++}
++
+ /* Return non-zero iff the consumer (a multiply-accumulate or a
+    multiple-subtract instruction) has an accumulator dependency on the
+    result of the producer and no other dependency on that result.  It
+--- a/src/gcc/config/arm/aarch-cost-tables.h
++++ b/src/gcc/config/arm/aarch-cost-tables.h
+@@ -191,35 +191,35 @@ const struct cpu_cost_table cortexa53_extra_costs =
+   {
+     /* FP SFmode */
+     {
+-      COSTS_N_INSNS (15),	/* div.  */
+-      COSTS_N_INSNS (3),	/* mult.  */
+-      COSTS_N_INSNS (7),	/* mult_addsub. */
+-      COSTS_N_INSNS (7),	/* fma.  */
+-      COSTS_N_INSNS (3),	/* addsub.  */
+-      COSTS_N_INSNS (1),	/* fpconst. */
+-      COSTS_N_INSNS (2),	/* neg.  */
+-      COSTS_N_INSNS (1),	/* compare.  */
+-      COSTS_N_INSNS (3),	/* widen.  */
+-      COSTS_N_INSNS (3),	/* narrow.  */
+-      COSTS_N_INSNS (3),	/* toint.  */
+-      COSTS_N_INSNS (3),	/* fromint.  */
+-      COSTS_N_INSNS (3)		/* roundint.  */
++      COSTS_N_INSNS (5),	/* div.  */
++      COSTS_N_INSNS (1),	/* mult.  */
++      COSTS_N_INSNS (2),	/* mult_addsub.  */
++      COSTS_N_INSNS (2),	/* fma.  */
++      COSTS_N_INSNS (1),	/* addsub.  */
++      0,			/* fpconst.  */
++      COSTS_N_INSNS (1),	/* neg.  */
++      0,			/* compare.  */
++      COSTS_N_INSNS (1),	/* widen.  */
++      COSTS_N_INSNS (1),	/* narrow.  */
++      COSTS_N_INSNS (1),	/* toint.  */
++      COSTS_N_INSNS (1),	/* fromint.  */
++      COSTS_N_INSNS (1)		/* roundint.  */
+     },
+     /* FP DFmode */
+     {
+-      COSTS_N_INSNS (30),	/* div.  */
+-      COSTS_N_INSNS (3),	/* mult.  */
+-      COSTS_N_INSNS (7),	/* mult_addsub.  */
+-      COSTS_N_INSNS (7),	/* fma.  */
+-      COSTS_N_INSNS (3),	/* addsub.  */
+-      COSTS_N_INSNS (1),	/* fpconst.  */
+-      COSTS_N_INSNS (2),	/* neg.  */
+-      COSTS_N_INSNS (1),	/* compare.  */
+-      COSTS_N_INSNS (3),	/* widen.  */
+-      COSTS_N_INSNS (3),	/* narrow.  */
+-      COSTS_N_INSNS (3),	/* toint.  */
+-      COSTS_N_INSNS (3),	/* fromint.  */
+-      COSTS_N_INSNS (3)		/* roundint.  */
++      COSTS_N_INSNS (10),	/* div.  */
++      COSTS_N_INSNS (1),	/* mult.  */
++      COSTS_N_INSNS (2),	/* mult_addsub.  */
++      COSTS_N_INSNS (2),	/* fma.  */
++      COSTS_N_INSNS (1),	/* addsub.  */
++      0,			/* fpconst.  */
++      COSTS_N_INSNS (1),	/* neg.  */
++      0,			/* compare.  */
++      COSTS_N_INSNS (1),	/* widen.  */
++      COSTS_N_INSNS (1),	/* narrow.  */
++      COSTS_N_INSNS (1),	/* toint.  */
++      COSTS_N_INSNS (1),	/* fromint.  */
++      COSTS_N_INSNS (1)		/* roundint.  */
+     }
+   },
+   /* Vector */
+@@ -294,35 +294,35 @@ const struct cpu_cost_table cortexa57_extra_costs =
+   {
+     /* FP SFmode */
+     {
+-      COSTS_N_INSNS (17),      /* div.  */
+-      COSTS_N_INSNS (5),       /* mult.  */
+-      COSTS_N_INSNS (9),       /* mult_addsub. */
+-      COSTS_N_INSNS (9),       /* fma.  */
+-      COSTS_N_INSNS (4),       /* addsub.  */
+-      COSTS_N_INSNS (2),       /* fpconst. */
+-      COSTS_N_INSNS (2),       /* neg.  */
+-      COSTS_N_INSNS (2),       /* compare.  */
+-      COSTS_N_INSNS (4),       /* widen.  */
+-      COSTS_N_INSNS (4),       /* narrow.  */
+-      COSTS_N_INSNS (4),       /* toint.  */
+-      COSTS_N_INSNS (4),       /* fromint.  */
+-      COSTS_N_INSNS (4)        /* roundint.  */
++      COSTS_N_INSNS (6),      /* div.  */
++      COSTS_N_INSNS (1),       /* mult.  */
++      COSTS_N_INSNS (2),       /* mult_addsub.  */
++      COSTS_N_INSNS (2),       /* fma.  */
++      COSTS_N_INSNS (1),       /* addsub.  */
++      0,		       /* fpconst.  */
++      0,		       /* neg.  */
++      0,		       /* compare.  */
++      COSTS_N_INSNS (1),       /* widen.  */
++      COSTS_N_INSNS (1),       /* narrow.  */
++      COSTS_N_INSNS (1),       /* toint.  */
++      COSTS_N_INSNS (1),       /* fromint.  */
++      COSTS_N_INSNS (1)        /* roundint.  */
+     },
+     /* FP DFmode */
+     {
+-      COSTS_N_INSNS (31),      /* div.  */
+-      COSTS_N_INSNS (5),       /* mult.  */
+-      COSTS_N_INSNS (9),       /* mult_addsub.  */
+-      COSTS_N_INSNS (9),       /* fma.  */
+-      COSTS_N_INSNS (4),       /* addsub.  */
+-      COSTS_N_INSNS (2),       /* fpconst.  */
+-      COSTS_N_INSNS (2),       /* neg.  */
+-      COSTS_N_INSNS (2),       /* compare.  */
+-      COSTS_N_INSNS (4),       /* widen.  */
+-      COSTS_N_INSNS (4),       /* narrow.  */
+-      COSTS_N_INSNS (4),       /* toint.  */
+-      COSTS_N_INSNS (4),       /* fromint.  */
+-      COSTS_N_INSNS (4)        /* roundint.  */
++      COSTS_N_INSNS (11),      /* div.  */
++      COSTS_N_INSNS (1),       /* mult.  */
++      COSTS_N_INSNS (2),       /* mult_addsub.  */
++      COSTS_N_INSNS (2),       /* fma.  */
++      COSTS_N_INSNS (1),       /* addsub.  */
++      0,		       /* fpconst.  */
++      0,		       /* neg.  */
++      0,		       /* compare.  */
++      COSTS_N_INSNS (1),       /* widen.  */
++      COSTS_N_INSNS (1),       /* narrow.  */
++      COSTS_N_INSNS (1),       /* toint.  */
++      COSTS_N_INSNS (1),       /* fromint.  */
++      COSTS_N_INSNS (1)        /* roundint.  */
+     }
+   },
+   /* Vector */
+@@ -537,4 +537,107 @@ const struct cpu_cost_table xgene1_extra_costs =
+   }
+ };
+ 
++const struct cpu_cost_table qdf24xx_extra_costs =
++{
++  /* ALU */
++  {
++    0,                 /* arith.  */
++    0,                 /* logical.  */
++    0,                 /* shift.  */
++    0,                 /* shift_reg.  */
++    COSTS_N_INSNS (1), /* arith_shift.  */
++    COSTS_N_INSNS (1), /* arith_shift_reg.  */
++    0,                 /* log_shift.  */
++    0,                 /* log_shift_reg.  */
++    0,                 /* extend.  */
++    0,                 /* extend_arith.  */
++    0,                 /* bfi.  */
++    0,                 /* bfx.  */
++    0,                 /* clz.  */
++    0,	               /* rev.  */
++    0,                 /* non_exec.  */
++    true               /* non_exec_costs_exec.  */
++  },
++  {
++    /* MULT SImode */
++    {
++      COSTS_N_INSNS (2),       /* simple.  */
++      COSTS_N_INSNS (2),       /* flag_setting.  */
++      COSTS_N_INSNS (2),       /* extend.  */
++      COSTS_N_INSNS (2),       /* add.  */
++      COSTS_N_INSNS (2),       /* extend_add.  */
++      COSTS_N_INSNS (4)       /* idiv.  */
++    },
++    /* MULT DImode */
++    {
++      COSTS_N_INSNS (3),       /* simple.  */
++      0,                       /* flag_setting (N/A).  */
++      COSTS_N_INSNS (3),       /* extend.  */
++      COSTS_N_INSNS (3),       /* add.  */
++      COSTS_N_INSNS (3),       /* extend_add.  */
++      COSTS_N_INSNS (9)       /* idiv.  */
++    }
++  },
++  /* LD/ST */
++  {
++    COSTS_N_INSNS (2),         /* load.  */
++    COSTS_N_INSNS (2),         /* load_sign_extend.  */
++    COSTS_N_INSNS (2),         /* ldrd.  */
++    COSTS_N_INSNS (2),         /* ldm_1st.  */
++    1,                         /* ldm_regs_per_insn_1st.  */
++    2,                         /* ldm_regs_per_insn_subsequent.  */
++    COSTS_N_INSNS (2),         /* loadf.  */
++    COSTS_N_INSNS (2),         /* loadd.  */
++    COSTS_N_INSNS (3),         /* load_unaligned.  */
++    0,                         /* store.  */
++    0,                         /* strd.  */
++    0,                         /* stm_1st.  */
++    1,                         /* stm_regs_per_insn_1st.  */
++    2,                         /* stm_regs_per_insn_subsequent.  */
++    0,                         /* storef.  */
++    0,                         /* stored.  */
++    COSTS_N_INSNS (1),         /* store_unaligned.  */
++    COSTS_N_INSNS (1),         /* loadv.  */
++    COSTS_N_INSNS (1)          /* storev.  */
++  },
++  {
++    /* FP SFmode */
++    {
++      COSTS_N_INSNS (6),      /* div.  */
++      COSTS_N_INSNS (5),       /* mult.  */
++      COSTS_N_INSNS (5),       /* mult_addsub. */
++      COSTS_N_INSNS (5),       /* fma.  */
++      COSTS_N_INSNS (3),       /* addsub.  */
++      COSTS_N_INSNS (1),       /* fpconst. */
++      COSTS_N_INSNS (1),       /* neg.  */
++      COSTS_N_INSNS (2),       /* compare.  */
++      COSTS_N_INSNS (4),       /* widen.  */
++      COSTS_N_INSNS (4),       /* narrow.  */
++      COSTS_N_INSNS (4),       /* toint.  */
++      COSTS_N_INSNS (4),       /* fromint.  */
++      COSTS_N_INSNS (2)        /* roundint.  */
++    },
++    /* FP DFmode */
++    {
++      COSTS_N_INSNS (11),      /* div.  */
++      COSTS_N_INSNS (6),       /* mult.  */
++      COSTS_N_INSNS (6),       /* mult_addsub.  */
++      COSTS_N_INSNS (6),       /* fma.  */
++      COSTS_N_INSNS (3),       /* addsub.  */
++      COSTS_N_INSNS (1),       /* fpconst.  */
++      COSTS_N_INSNS (1),       /* neg.  */
++      COSTS_N_INSNS (2),       /* compare.  */
++      COSTS_N_INSNS (4),       /* widen.  */
++      COSTS_N_INSNS (4),       /* narrow.  */
++      COSTS_N_INSNS (4),       /* toint.  */
++      COSTS_N_INSNS (4),       /* fromint.  */
++      COSTS_N_INSNS (2)        /* roundint.  */
++    }
++  },
++  /* Vector */
++  {
++    COSTS_N_INSNS (1)  /* alu.  */
++  }
++};
++
+ #endif /* GCC_AARCH_COST_TABLES_H */
+--- a/src/gcc/config/arm/arm-arches.def
++++ b/src/gcc/config/arm/arm-arches.def
+@@ -58,10 +58,22 @@ ARM_ARCH("armv7e-m", cortexm4,  7EM,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_F
+ ARM_ARCH("armv8-a", cortexa53,  8A,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH8A))
+ ARM_ARCH("armv8-a+crc",cortexa53, 8A,   ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_CRC32  | FL_FOR_ARCH8A))
+ ARM_ARCH("armv8.1-a", cortexa53,  8A,
+-	  ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8A,  FL2_FOR_ARCH8_1A))
++	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
++			 FL2_FOR_ARCH8_1A))
+ ARM_ARCH("armv8.1-a+crc",cortexa53, 8A,
+ 	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
+ 			 FL2_FOR_ARCH8_1A))
++ARM_ARCH ("armv8.2-a", cortexa53,  8A,
++	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
++			 FL2_FOR_ARCH8_2A))
++ARM_ARCH ("armv8.2-a+fp16", cortexa53,  8A,
++	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
++			 FL2_FOR_ARCH8_2A | FL2_FP16INST))
++ARM_ARCH("armv8-m.base", cortexm23, 8M_BASE,
++	  ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
++ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN,
++	  ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
++ARM_ARCH("armv8-m.main+dsp", cortexm33, 8M_MAIN,
++	  ARM_FSET_MAKE (FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
+ ARM_ARCH("iwmmxt",  iwmmxt,     5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
+ ARM_ARCH("iwmmxt2", iwmmxt2,    5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
+-
+--- a/src/gcc/config/arm/arm-builtins.c
++++ b/src/gcc/config/arm/arm-builtins.c
+@@ -190,6 +190,8 @@ arm_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ #define ti_UP	 TImode
+ #define ei_UP	 EImode
+ #define oi_UP	 OImode
++#define hf_UP	 HFmode
++#define si_UP	 SImode
+ 
+ #define UP(X) X##_UP
+ 
+@@ -239,12 +241,22 @@ typedef struct {
+   VAR11 (T, N, A, B, C, D, E, F, G, H, I, J, K) \
+   VAR1 (T, N, L)
+ 
+-/* The NEON builtin data can be found in arm_neon_builtins.def.
+-   The mode entries in the following table correspond to the "key" type of the
+-   instruction variant, i.e. equivalent to that which would be specified after
+-   the assembler mnemonic, which usually refers to the last vector operand.
+-   The modes listed per instruction should be the same as those defined for
+-   that instruction's pattern in neon.md.  */
++/* The NEON builtin data can be found in arm_neon_builtins.def and
++   arm_vfp_builtins.def.  The entries in arm_neon_builtins.def require
++   TARGET_NEON to be true.  The feature tests are checked when the
++   builtins are expanded.
++
++   The mode entries in the following table correspond to the "key"
++   type of the instruction variant, i.e. equivalent to that which
++   would be specified after the assembler mnemonic, which usually
++   refers to the last vector operand.  The modes listed per
++   instruction should be the same as those defined for that
++   instruction's pattern in neon.md.  */
++
++static neon_builtin_datum vfp_builtin_data[] =
++{
++#include "arm_vfp_builtins.def"
++};
+ 
+ static neon_builtin_datum neon_builtin_data[] =
+ {
+@@ -515,6 +527,8 @@ enum arm_builtins
+   ARM_BUILTIN_GET_FPSCR,
+   ARM_BUILTIN_SET_FPSCR,
+ 
++  ARM_BUILTIN_CMSE_NONSECURE_CALLER,
++
+ #undef CRYPTO1
+ #undef CRYPTO2
+ #undef CRYPTO3
+@@ -534,6 +548,10 @@ enum arm_builtins
+ #undef CRYPTO2
+ #undef CRYPTO3
+ 
++  ARM_BUILTIN_VFP_BASE,
++
++#include "arm_vfp_builtins.def"
++
+   ARM_BUILTIN_NEON_BASE,
+   ARM_BUILTIN_NEON_LANE_CHECK = ARM_BUILTIN_NEON_BASE,
+ 
+@@ -542,8 +560,11 @@ enum arm_builtins
+   ARM_BUILTIN_MAX
+ };
+ 
++#define ARM_BUILTIN_VFP_PATTERN_START \
++  (ARM_BUILTIN_VFP_BASE + 1)
++
+ #define ARM_BUILTIN_NEON_PATTERN_START \
+-    (ARM_BUILTIN_MAX - ARRAY_SIZE (neon_builtin_data))
++  (ARM_BUILTIN_NEON_BASE + 1)
+ 
+ #undef CF
+ #undef VAR1
+@@ -895,6 +916,110 @@ arm_init_simd_builtin_scalar_types (void)
+ 					     "__builtin_neon_uti");
+ }
+ 
++/* Set up a NEON builtin.  */
++
++static void
++arm_init_neon_builtin (unsigned int fcode,
++		       neon_builtin_datum *d)
++{
++  bool print_type_signature_p = false;
++  char type_signature[SIMD_MAX_BUILTIN_ARGS] = { 0 };
++  char namebuf[60];
++  tree ftype = NULL;
++  tree fndecl = NULL;
++
++  d->fcode = fcode;
++
++  /* We must track two variables here.  op_num is
++     the operand number as in the RTL pattern.  This is
++     required to access the mode (e.g. V4SF mode) of the
++     argument, from which the base type can be derived.
++     arg_num is an index in to the qualifiers data, which
++     gives qualifiers to the type (e.g. const unsigned).
++     The reason these two variables may differ by one is the
++     void return type.  While all return types take the 0th entry
++     in the qualifiers array, there is no operand for them in the
++     RTL pattern.  */
++  int op_num = insn_data[d->code].n_operands - 1;
++  int arg_num = d->qualifiers[0] & qualifier_void
++    ? op_num + 1
++    : op_num;
++  tree return_type = void_type_node, args = void_list_node;
++  tree eltype;
++
++  /* Build a function type directly from the insn_data for this
++     builtin.  The build_function_type () function takes care of
++     removing duplicates for us.  */
++  for (; op_num >= 0; arg_num--, op_num--)
++    {
++      machine_mode op_mode = insn_data[d->code].operand[op_num].mode;
++      enum arm_type_qualifiers qualifiers = d->qualifiers[arg_num];
++
++      if (qualifiers & qualifier_unsigned)
++	{
++	  type_signature[arg_num] = 'u';
++	  print_type_signature_p = true;
++	}
++      else if (qualifiers & qualifier_poly)
++	{
++	  type_signature[arg_num] = 'p';
++	  print_type_signature_p = true;
++	}
++      else
++	type_signature[arg_num] = 's';
++
++      /* Skip an internal operand for vget_{low, high}.  */
++      if (qualifiers & qualifier_internal)
++	continue;
++
++      /* Some builtins have different user-facing types
++	 for certain arguments, encoded in d->mode.  */
++      if (qualifiers & qualifier_map_mode)
++	op_mode = d->mode;
++
++      /* For pointers, we want a pointer to the basic type
++	 of the vector.  */
++      if (qualifiers & qualifier_pointer && VECTOR_MODE_P (op_mode))
++	op_mode = GET_MODE_INNER (op_mode);
++
++      eltype = arm_simd_builtin_type
++	(op_mode,
++	 (qualifiers & qualifier_unsigned) != 0,
++	 (qualifiers & qualifier_poly) != 0);
++      gcc_assert (eltype != NULL);
++
++      /* Add qualifiers.  */
++      if (qualifiers & qualifier_const)
++	eltype = build_qualified_type (eltype, TYPE_QUAL_CONST);
++
++      if (qualifiers & qualifier_pointer)
++	eltype = build_pointer_type (eltype);
++
++      /* If we have reached arg_num == 0, we are at a non-void
++	 return type.  Otherwise, we are still processing
++	 arguments.  */
++      if (arg_num == 0)
++	return_type = eltype;
++      else
++	args = tree_cons (NULL_TREE, eltype, args);
++    }
++
++  ftype = build_function_type (return_type, args);
++
++  gcc_assert (ftype != NULL);
++
++  if (print_type_signature_p)
++    snprintf (namebuf, sizeof (namebuf), "__builtin_neon_%s_%s",
++	      d->name, type_signature);
++  else
++    snprintf (namebuf, sizeof (namebuf), "__builtin_neon_%s",
++	      d->name);
++
++  fndecl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD,
++				 NULL, NULL_TREE);
++  arm_builtin_decls[fcode] = fndecl;
++}
++
+ /* Set up all the NEON builtins, even builtins for instructions that are not
+    in the current target ISA to allow the user to compile particular modules
+    with different target specific options that differ from the command line
+@@ -924,103 +1049,22 @@ arm_init_neon_builtins (void)
+ 
+   for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++, fcode++)
+     {
+-      bool print_type_signature_p = false;
+-      char type_signature[SIMD_MAX_BUILTIN_ARGS] = { 0 };
+       neon_builtin_datum *d = &neon_builtin_data[i];
+-      char namebuf[60];
+-      tree ftype = NULL;
+-      tree fndecl = NULL;
+-
+-      d->fcode = fcode;
+-
+-      /* We must track two variables here.  op_num is
+-	 the operand number as in the RTL pattern.  This is
+-	 required to access the mode (e.g. V4SF mode) of the
+-	 argument, from which the base type can be derived.
+-	 arg_num is an index in to the qualifiers data, which
+-	 gives qualifiers to the type (e.g. const unsigned).
+-	 The reason these two variables may differ by one is the
+-	 void return type.  While all return types take the 0th entry
+-	 in the qualifiers array, there is no operand for them in the
+-	 RTL pattern.  */
+-      int op_num = insn_data[d->code].n_operands - 1;
+-      int arg_num = d->qualifiers[0] & qualifier_void
+-		      ? op_num + 1
+-		      : op_num;
+-      tree return_type = void_type_node, args = void_list_node;
+-      tree eltype;
+-
+-      /* Build a function type directly from the insn_data for this
+-	 builtin.  The build_function_type () function takes care of
+-	 removing duplicates for us.  */
+-      for (; op_num >= 0; arg_num--, op_num--)
+-	{
+-	  machine_mode op_mode = insn_data[d->code].operand[op_num].mode;
+-	  enum arm_type_qualifiers qualifiers = d->qualifiers[arg_num];
+-
+-	  if (qualifiers & qualifier_unsigned)
+-	    {
+-	      type_signature[arg_num] = 'u';
+-	      print_type_signature_p = true;
+-	    }
+-	  else if (qualifiers & qualifier_poly)
+-	    {
+-	      type_signature[arg_num] = 'p';
+-	      print_type_signature_p = true;
+-	    }
+-	  else
+-	    type_signature[arg_num] = 's';
+-
+-	  /* Skip an internal operand for vget_{low, high}.  */
+-	  if (qualifiers & qualifier_internal)
+-	    continue;
+-
+-	  /* Some builtins have different user-facing types
+-	     for certain arguments, encoded in d->mode.  */
+-	  if (qualifiers & qualifier_map_mode)
+-	      op_mode = d->mode;
+-
+-	  /* For pointers, we want a pointer to the basic type
+-	     of the vector.  */
+-	  if (qualifiers & qualifier_pointer && VECTOR_MODE_P (op_mode))
+-	    op_mode = GET_MODE_INNER (op_mode);
+-
+-	  eltype = arm_simd_builtin_type
+-		     (op_mode,
+-		      (qualifiers & qualifier_unsigned) != 0,
+-		      (qualifiers & qualifier_poly) != 0);
+-	  gcc_assert (eltype != NULL);
+-
+-	  /* Add qualifiers.  */
+-	  if (qualifiers & qualifier_const)
+-	    eltype = build_qualified_type (eltype, TYPE_QUAL_CONST);
+-
+-	  if (qualifiers & qualifier_pointer)
+-	      eltype = build_pointer_type (eltype);
+-
+-	  /* If we have reached arg_num == 0, we are at a non-void
+-	     return type.  Otherwise, we are still processing
+-	     arguments.  */
+-	  if (arg_num == 0)
+-	    return_type = eltype;
+-	  else
+-	    args = tree_cons (NULL_TREE, eltype, args);
+-	}
+-
+-      ftype = build_function_type (return_type, args);
++      arm_init_neon_builtin (fcode, d);
++    }
++}
+ 
+-      gcc_assert (ftype != NULL);
++/* Set up all the scalar floating point builtins.  */
+ 
+-      if (print_type_signature_p)
+-	snprintf (namebuf, sizeof (namebuf), "__builtin_neon_%s_%s",
+-		  d->name, type_signature);
+-      else
+-	snprintf (namebuf, sizeof (namebuf), "__builtin_neon_%s",
+-		  d->name);
++static void
++arm_init_vfp_builtins (void)
++{
++  unsigned int i, fcode = ARM_BUILTIN_VFP_PATTERN_START;
+ 
+-      fndecl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD,
+-				     NULL, NULL_TREE);
+-      arm_builtin_decls[fcode] = fndecl;
++  for (i = 0; i < ARRAY_SIZE (vfp_builtin_data); i++, fcode++)
++    {
++      neon_builtin_datum *d = &vfp_builtin_data[i];
++      arm_init_neon_builtin (fcode, d);
+     }
+ }
+ 
+@@ -1768,14 +1812,14 @@ arm_init_builtins (void)
+   if (TARGET_HARD_FLOAT)
+     {
+       arm_init_neon_builtins ();
+-
++      arm_init_vfp_builtins ();
+       arm_init_crypto_builtins ();
+     }
+ 
+   if (TARGET_CRC32)
+     arm_init_crc32_builtins ();
+ 
+-  if (TARGET_VFP && TARGET_HARD_FLOAT)
++  if (TARGET_HARD_FLOAT)
+     {
+       tree ftype_set_fpscr
+ 	= build_function_type_list (void_type_node, unsigned_type_node, NULL);
+@@ -1789,6 +1833,17 @@ arm_init_builtins (void)
+ 	= add_builtin_function ("__builtin_arm_set_fpscr", ftype_set_fpscr,
+ 				ARM_BUILTIN_SET_FPSCR, BUILT_IN_MD, NULL, NULL_TREE);
+     }
++
++  if (use_cmse)
++    {
++      tree ftype_cmse_nonsecure_caller
++	= build_function_type_list (unsigned_type_node, NULL);
++      arm_builtin_decls[ARM_BUILTIN_CMSE_NONSECURE_CALLER]
++	= add_builtin_function ("__builtin_arm_cmse_nonsecure_caller",
++				ftype_cmse_nonsecure_caller,
++				ARM_BUILTIN_CMSE_NONSECURE_CALLER, BUILT_IN_MD,
++				NULL, NULL_TREE);
++    }
+ }
+ 
+ /* Return the ARM builtin for CODE.  */
+@@ -2216,40 +2271,16 @@ constant_arg:
+   return target;
+ }
+ 
+-/* Expand a Neon builtin, i.e. those registered only if TARGET_NEON holds.
+-   Most of these are "special" because they don't have symbolic
+-   constants defined per-instruction or per instruction-variant. Instead, the
+-   required info is looked up in the table neon_builtin_data.  */
++/* Expand a neon builtin.  This is also used for vfp builtins, which behave in
++   the same way.  These builtins are "special" because they don't have symbolic
++   constants defined per-instruction or per instruction-variant.  Instead, the
++   required info is looked up in the NEON_BUILTIN_DATA record that is passed
++   into the function.  */
++
+ static rtx
+-arm_expand_neon_builtin (int fcode, tree exp, rtx target)
++arm_expand_neon_builtin_1 (int fcode, tree exp, rtx target,
++			   neon_builtin_datum *d)
+ {
+-  /* Check in the context of the function making the call whether the
+-     builtin is supported.  */
+-  if (! TARGET_NEON)
+-    {
+-      fatal_error (input_location,
+-		   "You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use these intrinsics.");
+-      return const0_rtx;
+-    }
+-
+-  if (fcode == ARM_BUILTIN_NEON_LANE_CHECK)
+-    {
+-      /* Builtin is only to check bounds of the lane passed to some intrinsics
+-	 that are implemented with gcc vector extensions in arm_neon.h.  */
+-
+-      tree nlanes = CALL_EXPR_ARG (exp, 0);
+-      gcc_assert (TREE_CODE (nlanes) == INTEGER_CST);
+-      rtx lane_idx = expand_normal (CALL_EXPR_ARG (exp, 1));
+-      if (CONST_INT_P (lane_idx))
+-	neon_lane_bounds (lane_idx, 0, TREE_INT_CST_LOW (nlanes), exp);
+-      else
+-	error ("%Klane index must be a constant immediate", exp);
+-      /* Don't generate any RTL.  */
+-      return const0_rtx;
+-    }
+-
+-  neon_builtin_datum *d =
+-		&neon_builtin_data[fcode - ARM_BUILTIN_NEON_PATTERN_START];
+   enum insn_code icode = d->code;
+   builtin_arg args[SIMD_MAX_BUILTIN_ARGS + 1];
+   int num_args = insn_data[d->code].n_operands;
+@@ -2265,8 +2296,8 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
+       /* We have four arrays of data, each indexed in a different fashion.
+ 	 qualifiers - element 0 always describes the function return type.
+ 	 operands - element 0 is either the operand for return value (if
+-	   the function has a non-void return type) or the operand for the
+-	   first argument.
++	 the function has a non-void return type) or the operand for the
++	 first argument.
+ 	 expr_args - element 0 always holds the first argument.
+ 	 args - element 0 is always used for the return type.  */
+       int qualifiers_k = k;
+@@ -2288,7 +2319,7 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
+ 	  bool op_const_int_p =
+ 	    (CONST_INT_P (arg)
+ 	     && (*insn_data[icode].operand[operands_k].predicate)
+-		(arg, insn_data[icode].operand[operands_k].mode));
++	     (arg, insn_data[icode].operand[operands_k].mode));
+ 	  args[k] = op_const_int_p ? NEON_ARG_CONSTANT : NEON_ARG_COPY_TO_REG;
+ 	}
+       else if (d->qualifiers[qualifiers_k] & qualifier_pointer)
+@@ -2301,8 +2332,68 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
+   /* The interface to arm_expand_neon_args expects a 0 if
+      the function is void, and a 1 if it is not.  */
+   return arm_expand_neon_args
+-	  (target, d->mode, fcode, icode, !is_void, exp,
+-	   &args[1]);
++    (target, d->mode, fcode, icode, !is_void, exp,
++     &args[1]);
++}
++
++/* Expand a Neon builtin, i.e. those registered only if TARGET_NEON holds.
++   Most of these are "special" because they don't have symbolic
++   constants defined per-instruction or per instruction-variant.  Instead, the
++   required info is looked up in the table neon_builtin_data.  */
++
++static rtx
++arm_expand_neon_builtin (int fcode, tree exp, rtx target)
++{
++  if (fcode >= ARM_BUILTIN_NEON_BASE && ! TARGET_NEON)
++    {
++      fatal_error (input_location,
++		   "You must enable NEON instructions"
++		   " (e.g. -mfloat-abi=softfp -mfpu=neon)"
++		   " to use these intrinsics.");
++      return const0_rtx;
++    }
++
++  if (fcode == ARM_BUILTIN_NEON_LANE_CHECK)
++    {
++      /* Builtin is only to check bounds of the lane passed to some intrinsics
++	 that are implemented with gcc vector extensions in arm_neon.h.  */
++
++      tree nlanes = CALL_EXPR_ARG (exp, 0);
++      gcc_assert (TREE_CODE (nlanes) == INTEGER_CST);
++      rtx lane_idx = expand_normal (CALL_EXPR_ARG (exp, 1));
++      if (CONST_INT_P (lane_idx))
++	neon_lane_bounds (lane_idx, 0, TREE_INT_CST_LOW (nlanes), exp);
++      else
++	error ("%Klane index must be a constant immediate", exp);
++      /* Don't generate any RTL.  */
++      return const0_rtx;
++    }
++
++  neon_builtin_datum *d
++    = &neon_builtin_data[fcode - ARM_BUILTIN_NEON_PATTERN_START];
++
++  return arm_expand_neon_builtin_1 (fcode, exp, target, d);
++}
++
++/* Expand a VFP builtin.  These builtins are treated like
++   neon builtins except that the data is looked up in table
++   VFP_BUILTIN_DATA.  */
++
++static rtx
++arm_expand_vfp_builtin (int fcode, tree exp, rtx target)
++{
++  if (fcode >= ARM_BUILTIN_VFP_BASE && ! TARGET_HARD_FLOAT)
++    {
++      fatal_error (input_location,
++		   "You must enable VFP instructions"
++		   " to use these intrinsics.");
++      return const0_rtx;
++    }
++
++  neon_builtin_datum *d
++    = &vfp_builtin_data[fcode - ARM_BUILTIN_VFP_PATTERN_START];
++
++  return arm_expand_neon_builtin_1 (fcode, exp, target, d);
+ }
+ 
+ /* Expand an expression EXP that calls a built-in function,
+@@ -2342,13 +2433,18 @@ arm_expand_builtin (tree exp,
+   if (fcode >= ARM_BUILTIN_NEON_BASE)
+     return arm_expand_neon_builtin (fcode, exp, target);
+ 
++  if (fcode >= ARM_BUILTIN_VFP_BASE)
++    return arm_expand_vfp_builtin (fcode, exp, target);
++
+   /* Check in the context of the function making the call whether the
+      builtin is supported.  */
+   if (fcode >= ARM_BUILTIN_CRYPTO_BASE
+       && (!TARGET_CRYPTO || !TARGET_HARD_FLOAT))
+     {
+       fatal_error (input_location,
+-		   "You must enable crypto intrinsics (e.g. include -mfloat-abi=softfp -mfpu=crypto-neon...) to use these intrinsics.");
++		   "You must enable crypto instructions"
++		   " (e.g. include -mfloat-abi=softfp -mfpu=crypto-neon...)"
++		   " to use these intrinsics.");
+       return const0_rtx;
+     }
+ 
+@@ -2373,6 +2469,12 @@ arm_expand_builtin (tree exp,
+       emit_insn (pat);
+       return target;
+ 
++    case ARM_BUILTIN_CMSE_NONSECURE_CALLER:
++      target = gen_reg_rtx (SImode);
++      op0 = arm_return_addr (0, NULL_RTX);
++      emit_insn (gen_addsi3 (target, op0, const1_rtx));
++      return target;
++
+     case ARM_BUILTIN_TEXTRMSB:
+     case ARM_BUILTIN_TEXTRMUB:
+     case ARM_BUILTIN_TEXTRMSH:
+@@ -3000,7 +3102,7 @@ arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
+   tree new_fenv_var, reload_fenv, restore_fnenv;
+   tree update_call, atomic_feraiseexcept, hold_fnclex;
+ 
+-  if (!TARGET_VFP || !TARGET_HARD_FLOAT)
++  if (!TARGET_HARD_FLOAT)
+     return;
+ 
+   /* Generate the equivalent of :
+--- a/src/gcc/config/arm/arm-c.c
++++ b/src/gcc/config/arm/arm-c.c
+@@ -76,6 +76,14 @@ arm_cpu_builtins (struct cpp_reader* pfile)
+ 
+   def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT);
+ 
++  if (arm_arch8 && !arm_arch_notm)
++    {
++      if (arm_arch_cmse && use_cmse)
++	builtin_define_with_int_value ("__ARM_FEATURE_CMSE", 3);
++      else
++	builtin_define ("__ARM_FEATURE_CMSE");
++    }
++
+   if (TARGET_ARM_FEATURE_LDREX)
+     builtin_define_with_int_value ("__ARM_FEATURE_LDREX",
+ 				   TARGET_ARM_FEATURE_LDREX);
+@@ -86,6 +94,9 @@ arm_cpu_builtins (struct cpp_reader* pfile)
+ 		      ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB)
+ 		       || TARGET_ARM_ARCH_ISA_THUMB >=2));
+ 
++  def_or_undef_macro (pfile, "__ARM_FEATURE_NUMERIC_MAXMIN",
++		      TARGET_ARM_ARCH >= 8 && TARGET_NEON && TARGET_FPU_ARMV8);
++
+   def_or_undef_macro (pfile, "__ARM_FEATURE_SIMD32", TARGET_INT_SIMD);
+ 
+   builtin_define_with_int_value ("__ARM_SIZEOF_MINIMAL_ENUM",
+@@ -128,17 +139,24 @@ arm_cpu_builtins (struct cpp_reader* pfile)
+   if (TARGET_SOFT_FLOAT)
+     builtin_define ("__SOFTFP__");
+ 
+-  def_or_undef_macro (pfile, "__VFP_FP__", TARGET_VFP);
++  builtin_define ("__VFP_FP__");
+ 
+   if (TARGET_ARM_FP)
+     builtin_define_with_int_value ("__ARM_FP", TARGET_ARM_FP);
+   else
+     cpp_undef (pfile, "__ARM_FP");
+ 
+-  if (arm_fp16_format == ARM_FP16_FORMAT_IEEE)
+-    builtin_define ("__ARM_FP16_FORMAT_IEEE");
+-  if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
+-    builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE");
++  def_or_undef_macro (pfile, "__ARM_FP16_FORMAT_IEEE",
++		      arm_fp16_format == ARM_FP16_FORMAT_IEEE);
++  def_or_undef_macro (pfile, "__ARM_FP16_FORMAT_ALTERNATIVE",
++		      arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE);
++  def_or_undef_macro (pfile, "__ARM_FP16_ARGS",
++		      arm_fp16_format != ARM_FP16_FORMAT_NONE);
++
++  def_or_undef_macro (pfile, "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC",
++		      TARGET_VFP_FP16INST);
++  def_or_undef_macro (pfile, "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC",
++		      TARGET_NEON_FP16INST);
+ 
+   def_or_undef_macro (pfile, "__ARM_FEATURE_FMA", TARGET_FMA);
+   def_or_undef_macro (pfile, "__ARM_NEON__", TARGET_NEON);
+--- a/src/gcc/config/arm/arm-cores.def
++++ b/src/gcc/config/arm/arm-cores.def
+@@ -166,15 +166,21 @@ ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_
+ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a12)
+ 
+ /* V8 Architecture Processors */
++ARM_CORE("cortex-m23",	cortexm23, cortexm23,	8M_BASE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8M_BASE), v6m)
+ ARM_CORE("cortex-a32",	cortexa32, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
++ARM_CORE("cortex-m33",	cortexm33, cortexm33,	8M_MAIN, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m)
+ ARM_CORE("cortex-a35",	cortexa35, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
+ ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
+ ARM_CORE("cortex-a57",	cortexa57, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ ARM_CORE("cortex-a72",	cortexa72, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
++ARM_CORE("cortex-a73",	cortexa73, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+ ARM_CORE("exynos-m1",	exynosm1,  exynosm1,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
+-ARM_CORE("qdf24xx",	qdf24xx,   cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
++ARM_CORE("qdf24xx",	qdf24xx,   cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
+ ARM_CORE("xgene1",      xgene1,    xgene1,      8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A),            xgene1)
+ 
+ /* V8 big.LITTLE implementations */
+ ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
++ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, 8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
++ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
++
+--- /dev/null
++++ b/src/gcc/config/arm/arm-flags.h
+@@ -0,0 +1,212 @@
++/* Flags used to identify the presence of processor capabilities.
++
++   Copyright (C) 2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with GCC; see the file COPYING3.  If not see
++   <http://www.gnu.org/licenses/>.  */
++
++#ifndef GCC_ARM_FLAGS_H
++#define GCC_ARM_FLAGS_H
++
++/* Flags used to identify the presence of processor capabilities.  */
++
++/* Bit values used to identify processor capabilities.  */
++#define FL_NONE	      (0U)		/* No flags.  */
++#define FL_ANY	      (0xffffffffU)	/* All flags.  */
++#define FL_CO_PROC    (1U << 0)		/* Has external co-processor bus.  */
++#define FL_ARCH3M     (1U << 1)		/* Extended multiply.  */
++#define FL_MODE26     (1U << 2)		/* 26-bit mode support.  */
++#define FL_MODE32     (1U << 3)		/* 32-bit mode support.  */
++#define FL_ARCH4      (1U << 4)		/* Architecture rel 4.  */
++#define FL_ARCH5      (1U << 5)		/* Architecture rel 5.  */
++#define FL_THUMB      (1U << 6)		/* Thumb aware.  */
++#define FL_LDSCHED    (1U << 7)		/* Load scheduling necessary.  */
++#define FL_STRONG     (1U << 8)		/* StrongARM.  */
++#define FL_ARCH5E     (1U << 9)		/* DSP extensions to v5.  */
++#define FL_XSCALE     (1U << 10)	/* XScale.  */
++#define FL_LPAE       (1U << 11)	/* ARMv7-A LPAE.  */
++#define FL_ARCH6      (1U << 12)	/* Architecture rel 6.  Adds
++					   media instructions.  */
++#define FL_VFPV2      (1U << 13)	/* Vector Floating Point V2.  */
++#define FL_WBUF	      (1U << 14)	/* Schedule for write buffer ops.
++					   Note: ARM6 & 7 derivatives only.  */
++#define FL_ARCH6K     (1U << 15)	/* Architecture rel 6 K extensions.  */
++#define FL_THUMB2     (1U << 16)	/* Thumb-2.  */
++#define FL_NOTM	      (1U << 17)	/* Instructions not present in the 'M'
++					   profile.  */
++#define FL_THUMB_DIV  (1U << 18)	/* Hardware divide (Thumb mode).  */
++#define FL_VFPV3      (1U << 19)	/* Vector Floating Point V3.  */
++#define FL_NEON       (1U << 20)	/* Neon instructions.  */
++#define FL_ARCH7EM    (1U << 21)	/* Instructions present in the ARMv7E-M
++					   architecture.  */
++#define FL_ARCH7      (1U << 22)	/* Architecture 7.  */
++#define FL_ARM_DIV    (1U << 23)	/* Hardware divide (ARM mode).  */
++#define FL_ARCH8      (1U << 24)	/* Architecture 8.  */
++#define FL_CRC32      (1U << 25)	/* ARMv8 CRC32 instructions.  */
++#define FL_SMALLMUL   (1U << 26)	/* Small multiply supported.  */
++#define FL_NO_VOLATILE_CE  (1U << 27)	/* No volatile memory in IT block.  */
++
++#define FL_IWMMXT     (1U << 29)	/* XScale v2 or "Intel Wireless MMX
++					   technology".  */
++#define FL_IWMMXT2    (1U << 30)	/* "Intel Wireless MMX2
++					    technology".  */
++#define FL_ARCH6KZ    (1U << 31)	/* ARMv6KZ architecture.  */
++
++#define FL2_ARCH8_1   (1U << 0)		/* Architecture 8.1.  */
++#define FL2_ARCH8_2   (1U << 1)		/* Architecture 8.2.  */
++#define FL2_FP16INST  (1U << 2)		/* FP16 Instructions for ARMv8.2 and
++					   later.  */
++#define FL2_CMSE      (1U << 3)		/* ARMv8-M Security Extensions.  */
++
++/* Flags that only effect tuning, not available instructions.  */
++#define FL_TUNE		(FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
++			 | FL_CO_PROC)
++
++#define FL_FOR_ARCH2		FL_NOTM
++#define FL_FOR_ARCH3		(FL_FOR_ARCH2 | FL_MODE32)
++#define FL_FOR_ARCH3M		(FL_FOR_ARCH3 | FL_ARCH3M)
++#define FL_FOR_ARCH4		(FL_FOR_ARCH3M | FL_ARCH4)
++#define FL_FOR_ARCH4T		(FL_FOR_ARCH4 | FL_THUMB)
++#define FL_FOR_ARCH5		(FL_FOR_ARCH4 | FL_ARCH5)
++#define FL_FOR_ARCH5T		(FL_FOR_ARCH5 | FL_THUMB)
++#define FL_FOR_ARCH5E		(FL_FOR_ARCH5 | FL_ARCH5E)
++#define FL_FOR_ARCH5TE		(FL_FOR_ARCH5E | FL_THUMB)
++#define FL_FOR_ARCH5TEJ		FL_FOR_ARCH5TE
++#define FL_FOR_ARCH6		(FL_FOR_ARCH5TE | FL_ARCH6)
++#define FL_FOR_ARCH6J		FL_FOR_ARCH6
++#define FL_FOR_ARCH6K		(FL_FOR_ARCH6 | FL_ARCH6K)
++#define FL_FOR_ARCH6Z		FL_FOR_ARCH6
++#define FL_FOR_ARCH6ZK		FL_FOR_ARCH6K
++#define FL_FOR_ARCH6KZ		(FL_FOR_ARCH6K | FL_ARCH6KZ)
++#define FL_FOR_ARCH6T2		(FL_FOR_ARCH6 | FL_THUMB2)
++#define FL_FOR_ARCH6M		(FL_FOR_ARCH6 & ~FL_NOTM)
++#define FL_FOR_ARCH7		((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
++#define FL_FOR_ARCH7A		(FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
++#define FL_FOR_ARCH7VE		(FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV | FL_LPAE)
++#define FL_FOR_ARCH7R		(FL_FOR_ARCH7A | FL_THUMB_DIV)
++#define FL_FOR_ARCH7M		(FL_FOR_ARCH7 | FL_THUMB_DIV)
++#define FL_FOR_ARCH7EM		(FL_FOR_ARCH7M | FL_ARCH7EM)
++#define FL_FOR_ARCH8A		(FL_FOR_ARCH7VE | FL_ARCH8)
++#define FL2_FOR_ARCH8_1A	FL2_ARCH8_1
++#define FL2_FOR_ARCH8_2A	(FL2_FOR_ARCH8_1A | FL2_ARCH8_2)
++#define FL_FOR_ARCH8M_BASE	(FL_FOR_ARCH6M | FL_ARCH8 | FL_THUMB_DIV)
++#define FL_FOR_ARCH8M_MAIN	(FL_FOR_ARCH7M | FL_ARCH8)
++
++/* There are too many feature bits to fit in a single word so the set of cpu and
++   fpu capabilities is a structure.  A feature set is created and manipulated
++   with the ARM_FSET macros.  */
++
++typedef struct
++{
++  unsigned cpu[2];
++} arm_feature_set;
++
++
++/* Initialize a feature set.  */
++
++#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
++
++#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
++#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
++
++/* Accessors.  */
++
++#define ARM_FSET_CPU1(S) ((S).cpu[0])
++#define ARM_FSET_CPU2(S) ((S).cpu[1])
++
++/* Useful combinations.  */
++
++#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
++#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
++
++/* Tests for a specific CPU feature.  */
++
++#define ARM_FSET_HAS_CPU1(A, F)  \
++  (((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F)))
++#define ARM_FSET_HAS_CPU2(A, F)  \
++  (((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F)))
++#define ARM_FSET_HAS_CPU(A, F1, F2)				\
++  (ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2)))
++
++/* Add a feature to a feature set.  */
++
++#define ARM_FSET_ADD_CPU1(DST, F)		\
++  do {						\
++    (DST).cpu[0] |= (F);			\
++  } while (0)
++
++#define ARM_FSET_ADD_CPU2(DST, F)		\
++  do {						\
++    (DST).cpu[1] |= (F);			\
++  } while (0)
++
++/* Remove a feature from a feature set.  */
++
++#define ARM_FSET_DEL_CPU1(DST, F)		\
++  do {						\
++    (DST).cpu[0] &= ~(F);			\
++  } while (0)
++
++#define ARM_FSET_DEL_CPU2(DST, F)		\
++  do {						\
++    (DST).cpu[1] &= ~(F);			\
++  } while (0)
++
++/* Union of feature sets.  */
++
++#define ARM_FSET_UNION(DST,F1,F2)		\
++  do {						\
++    (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0];	\
++    (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1];	\
++  } while (0)
++
++/* Intersection of feature sets.  */
++
++#define ARM_FSET_INTER(DST,F1,F2)		\
++  do {						\
++    (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0];	\
++    (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1];	\
++  } while (0)
++
++/* Exclusive disjunction.  */
++
++#define ARM_FSET_XOR(DST,F1,F2)				\
++  do {							\
++    (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0];		\
++    (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1];		\
++  } while (0)
++
++/* Difference of feature sets: F1 excluding the elements of F2.  */
++
++#define ARM_FSET_EXCLUDE(DST,F1,F2)		\
++  do {						\
++    (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0];	\
++    (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1];	\
++  } while (0)
++
++/* Test for an empty feature set.  */
++
++#define ARM_FSET_IS_EMPTY(A)		\
++  (!((A).cpu[0]) && !((A).cpu[1]))
++
++/* Tests whether the cpu features of A are a subset of B.  */
++
++#define ARM_FSET_CPU_SUBSET(A,B)					\
++  ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0])				\
++   && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
++
++#endif /* GCC_ARM_FLAGS_H */
+--- a/src/gcc/config/arm/arm-fpus.def
++++ b/src/gcc/config/arm/arm-fpus.def
+@@ -19,30 +19,31 @@
+ 
+ /* Before using #include to read this file, define a macro:
+ 
+-      ARM_FPU(NAME, MODEL, REV, VFP_REGS, FEATURES)
++      ARM_FPU(NAME, REV, VFP_REGS, FEATURES)
+ 
+    The arguments are the fields of struct arm_fpu_desc.
+ 
+    genopt.sh assumes no whitespace up to the first "," in each entry.  */
+ 
+-ARM_FPU("vfp",		ARM_FP_MODEL_VFP, 2, VFP_REG_D16, FPU_FL_NONE)
+-ARM_FPU("vfpv3",	ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NONE)
+-ARM_FPU("vfpv3-fp16",	ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_FP16)
+-ARM_FPU("vfpv3-d16",	ARM_FP_MODEL_VFP, 3, VFP_REG_D16, FPU_FL_NONE)
+-ARM_FPU("vfpv3-d16-fp16",	ARM_FP_MODEL_VFP, 3, VFP_REG_D16, FPU_FL_FP16)
+-ARM_FPU("vfpv3xd",	ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, FPU_FL_NONE)
+-ARM_FPU("vfpv3xd-fp16",	ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, FPU_FL_FP16)
+-ARM_FPU("neon",		ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NEON)
+-ARM_FPU("neon-fp16",	ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
+-ARM_FPU("vfpv4",	ARM_FP_MODEL_VFP, 4, VFP_REG_D32, FPU_FL_FP16)
+-ARM_FPU("vfpv4-d16",	ARM_FP_MODEL_VFP, 4, VFP_REG_D16, FPU_FL_FP16)
+-ARM_FPU("fpv4-sp-d16",	ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, FPU_FL_FP16)
+-ARM_FPU("fpv5-sp-d16",	ARM_FP_MODEL_VFP, 5, VFP_REG_SINGLE, FPU_FL_FP16)
+-ARM_FPU("fpv5-d16",	ARM_FP_MODEL_VFP, 5, VFP_REG_D16, FPU_FL_FP16)
+-ARM_FPU("neon-vfpv4",	ARM_FP_MODEL_VFP, 4, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
+-ARM_FPU("fp-armv8",	ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_FP16)
+-ARM_FPU("neon-fp-armv8",ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
+-ARM_FPU("crypto-neon-fp-armv8",
+-			ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO)
++ARM_FPU("vfp",		2, VFP_REG_D16, FPU_FL_NONE)
++ARM_FPU("vfpv2",	2, VFP_REG_D16, FPU_FL_NONE)
++ARM_FPU("vfpv3",	3, VFP_REG_D32, FPU_FL_NONE)
++ARM_FPU("vfpv3-fp16",	3, VFP_REG_D32, FPU_FL_FP16)
++ARM_FPU("vfpv3-d16",	3, VFP_REG_D16, FPU_FL_NONE)
++ARM_FPU("vfpv3-d16-fp16", 3, VFP_REG_D16, FPU_FL_FP16)
++ARM_FPU("vfpv3xd",	3, VFP_REG_SINGLE, FPU_FL_NONE)
++ARM_FPU("vfpv3xd-fp16",	3, VFP_REG_SINGLE, FPU_FL_FP16)
++ARM_FPU("neon",		3, VFP_REG_D32, FPU_FL_NEON)
++ARM_FPU("neon-vfpv3",	3, VFP_REG_D32, FPU_FL_NEON)
++ARM_FPU("neon-fp16",	3, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
++ARM_FPU("vfpv4",	4, VFP_REG_D32, FPU_FL_FP16)
++ARM_FPU("vfpv4-d16",	4, VFP_REG_D16, FPU_FL_FP16)
++ARM_FPU("fpv4-sp-d16",	4, VFP_REG_SINGLE, FPU_FL_FP16)
++ARM_FPU("fpv5-sp-d16",	5, VFP_REG_SINGLE, FPU_FL_FP16)
++ARM_FPU("fpv5-d16",	5, VFP_REG_D16, FPU_FL_FP16)
++ARM_FPU("neon-vfpv4",	4, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
++ARM_FPU("fp-armv8",	8, VFP_REG_D32, FPU_FL_FP16)
++ARM_FPU("neon-fp-armv8", 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
++ARM_FPU("crypto-neon-fp-armv8", 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO)
+ /* Compatibility aliases.  */
+-ARM_FPU("vfp3",		ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NONE)
++ARM_FPU("vfp3",		3, VFP_REG_D32, FPU_FL_NONE)
+--- a/src/gcc/config/arm/arm-modes.def
++++ b/src/gcc/config/arm/arm-modes.def
+@@ -59,6 +59,7 @@ CC_MODE (CC_DGEU);
+ CC_MODE (CC_DGTU);
+ CC_MODE (CC_C);
+ CC_MODE (CC_N);
++CC_MODE (CC_V);
+ 
+ /* Vector modes.  */
+ VECTOR_MODES (INT, 4);        /*            V4QI V2HI */
+--- a/src/gcc/config/arm/arm-opts.h
++++ b/src/gcc/config/arm/arm-opts.h
+@@ -25,6 +25,8 @@
+ #ifndef ARM_OPTS_H
+ #define ARM_OPTS_H
+ 
++#include "arm-flags.h"
++
+ /* The various ARM cores.  */
+ enum processor_type
+ {
+--- a/src/gcc/config/arm/arm-protos.h
++++ b/src/gcc/config/arm/arm-protos.h
+@@ -22,6 +22,7 @@
+ #ifndef GCC_ARM_PROTOS_H
+ #define GCC_ARM_PROTOS_H
+ 
++
+ extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
+ extern int use_return_insn (int, rtx);
+ extern bool use_simple_return_p (void);
+@@ -31,6 +32,7 @@ extern int arm_volatile_func (void);
+ extern void arm_expand_prologue (void);
+ extern void arm_expand_epilogue (bool);
+ extern void arm_declare_function_name (FILE *, const char *, tree);
++extern void arm_asm_declare_function_name (FILE *, const char *, tree);
+ extern void thumb2_expand_return (bool);
+ extern const char *arm_strip_name_encoding (const char *);
+ extern void arm_asm_output_labelref (FILE *, const char *);
+@@ -50,8 +52,12 @@ extern tree arm_builtin_decl (unsigned code, bool initialize_p
+ 			      ATTRIBUTE_UNUSED);
+ extern void arm_init_builtins (void);
+ extern void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
+-
++extern rtx arm_simd_vect_par_cnst_half (machine_mode mode, bool high);
++extern bool arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode,
++						 bool high);
+ #ifdef RTX_CODE
++extern void arm_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode,
++				      rtx label_ref);
+ extern bool arm_vector_mode_supported_p (machine_mode);
+ extern bool arm_small_register_classes_for_mode_p (machine_mode);
+ extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);
+@@ -130,6 +136,7 @@ extern int arm_const_double_inline_cost (rtx);
+ extern bool arm_const_double_by_parts (rtx);
+ extern bool arm_const_double_by_immediates (rtx);
+ extern void arm_emit_call_insn (rtx, rtx, bool);
++bool detect_cmse_nonsecure_call (tree);
+ extern const char *output_call (rtx *);
+ void arm_emit_movpair (rtx, rtx);
+ extern const char *output_mov_long_double_arm_from_arm (rtx *);
+@@ -161,6 +168,7 @@ extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool)
+ extern const char *arm_output_iwmmxt_tinsr (rtx *);
+ extern unsigned int arm_sync_loop_insns (rtx , rtx *);
+ extern int arm_attr_length_push_multi(rtx, rtx);
++extern int arm_attr_length_pop_multi(rtx *, bool, bool);
+ extern void arm_expand_compare_and_swap (rtx op[]);
+ extern void arm_split_compare_and_swap (rtx op[]);
+ extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
+@@ -192,7 +200,6 @@ extern const char *thumb_call_via_reg (rtx);
+ extern void thumb_expand_movmemqi (rtx *);
+ extern rtx arm_return_addr (int, rtx);
+ extern void thumb_reload_out_hi (rtx *);
+-extern void thumb_reload_in_hi (rtx *);
+ extern void thumb_set_return_address (rtx, rtx);
+ extern const char *thumb1_output_casesi (rtx *);
+ extern const char *thumb2_output_casesi (rtx *);
+@@ -256,7 +263,6 @@ struct cpu_cost_table;
+ 
+ struct tune_params
+ {
+-  bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
+   const struct cpu_cost_table *insn_extra_cost;
+   bool (*sched_adjust_cost) (rtx_insn *, rtx, rtx_insn *, int *);
+   int (*branch_cost) (bool, bool);
+@@ -319,6 +325,7 @@ extern int vfp3_const_double_for_bits (rtx);
+ 
+ extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
+ 					   rtx);
++extern bool arm_fusion_enabled_p (tune_params::fuse_ops);
+ extern bool arm_valid_symbolic_address_p (rtx);
+ extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
+ #endif /* RTX_CODE */
+@@ -344,184 +351,6 @@ extern void arm_cpu_cpp_builtins (struct cpp_reader *);
+ 
+ extern bool arm_is_constant_pool_ref (rtx);
+ 
+-/* Flags used to identify the presence of processor capabilities.  */
+-
+-/* Bit values used to identify processor capabilities.  */
+-#define FL_NONE	      (0)	      /* No flags.  */
+-#define FL_ANY	      (0xffffffff)    /* All flags.  */
+-#define FL_CO_PROC    (1 << 0)        /* Has external co-processor bus */
+-#define FL_ARCH3M     (1 << 1)        /* Extended multiply */
+-#define FL_MODE26     (1 << 2)        /* 26-bit mode support */
+-#define FL_MODE32     (1 << 3)        /* 32-bit mode support */
+-#define FL_ARCH4      (1 << 4)        /* Architecture rel 4 */
+-#define FL_ARCH5      (1 << 5)        /* Architecture rel 5 */
+-#define FL_THUMB      (1 << 6)        /* Thumb aware */
+-#define FL_LDSCHED    (1 << 7)	      /* Load scheduling necessary */
+-#define FL_STRONG     (1 << 8)	      /* StrongARM */
+-#define FL_ARCH5E     (1 << 9)        /* DSP extensions to v5 */
+-#define FL_XSCALE     (1 << 10)	      /* XScale */
+-#define FL_LPAE       (1 << 11)       /* ARMv7-A LPAE.  */
+-#define FL_ARCH6      (1 << 12)       /* Architecture rel 6.  Adds
+-					 media instructions.  */
+-#define FL_VFPV2      (1 << 13)       /* Vector Floating Point V2.  */
+-#define FL_WBUF	      (1 << 14)	      /* Schedule for write buffer ops.
+-					 Note: ARM6 & 7 derivatives only.  */
+-#define FL_ARCH6K     (1 << 15)       /* Architecture rel 6 K extensions.  */
+-#define FL_THUMB2     (1 << 16)	      /* Thumb-2.  */
+-#define FL_NOTM	      (1 << 17)	      /* Instructions not present in the 'M'
+-					 profile.  */
+-#define FL_THUMB_DIV  (1 << 18)	      /* Hardware divide (Thumb mode).  */
+-#define FL_VFPV3      (1 << 19)       /* Vector Floating Point V3.  */
+-#define FL_NEON       (1 << 20)       /* Neon instructions.  */
+-#define FL_ARCH7EM    (1 << 21)	      /* Instructions present in the ARMv7E-M
+-					 architecture.  */
+-#define FL_ARCH7      (1 << 22)       /* Architecture 7.  */
+-#define FL_ARM_DIV    (1 << 23)	      /* Hardware divide (ARM mode).  */
+-#define FL_ARCH8      (1 << 24)       /* Architecture 8.  */
+-#define FL_CRC32      (1 << 25)	      /* ARMv8 CRC32 instructions.  */
+-
+-#define FL_SMALLMUL   (1 << 26)       /* Small multiply supported.  */
+-#define FL_NO_VOLATILE_CE   (1 << 27) /* No volatile memory in IT block.  */
+-
+-#define FL_IWMMXT     (1 << 29)	      /* XScale v2 or "Intel Wireless MMX technology".  */
+-#define FL_IWMMXT2    (1 << 30)       /* "Intel Wireless MMX2 technology".  */
+-#define FL_ARCH6KZ    (1 << 31)       /* ARMv6KZ architecture.  */
+-
+-#define FL2_ARCH8_1   (1 << 0)	      /* Architecture 8.1.  */
+-
+-/* Flags that only effect tuning, not available instructions.  */
+-#define FL_TUNE		(FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
+-			 | FL_CO_PROC)
+-
+-#define FL_FOR_ARCH2	FL_NOTM
+-#define FL_FOR_ARCH3	(FL_FOR_ARCH2 | FL_MODE32)
+-#define FL_FOR_ARCH3M	(FL_FOR_ARCH3 | FL_ARCH3M)
+-#define FL_FOR_ARCH4	(FL_FOR_ARCH3M | FL_ARCH4)
+-#define FL_FOR_ARCH4T	(FL_FOR_ARCH4 | FL_THUMB)
+-#define FL_FOR_ARCH5	(FL_FOR_ARCH4 | FL_ARCH5)
+-#define FL_FOR_ARCH5T	(FL_FOR_ARCH5 | FL_THUMB)
+-#define FL_FOR_ARCH5E	(FL_FOR_ARCH5 | FL_ARCH5E)
+-#define FL_FOR_ARCH5TE	(FL_FOR_ARCH5E | FL_THUMB)
+-#define FL_FOR_ARCH5TEJ	FL_FOR_ARCH5TE
+-#define FL_FOR_ARCH6	(FL_FOR_ARCH5TE | FL_ARCH6)
+-#define FL_FOR_ARCH6J	FL_FOR_ARCH6
+-#define FL_FOR_ARCH6K	(FL_FOR_ARCH6 | FL_ARCH6K)
+-#define FL_FOR_ARCH6Z	FL_FOR_ARCH6
+-#define FL_FOR_ARCH6KZ	(FL_FOR_ARCH6K | FL_ARCH6KZ)
+-#define FL_FOR_ARCH6T2	(FL_FOR_ARCH6 | FL_THUMB2)
+-#define FL_FOR_ARCH6M	(FL_FOR_ARCH6 & ~FL_NOTM)
+-#define FL_FOR_ARCH7	((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
+-#define FL_FOR_ARCH7A	(FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
+-#define FL_FOR_ARCH7VE	(FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV | FL_LPAE)
+-#define FL_FOR_ARCH7R	(FL_FOR_ARCH7A | FL_THUMB_DIV)
+-#define FL_FOR_ARCH7M	(FL_FOR_ARCH7 | FL_THUMB_DIV)
+-#define FL_FOR_ARCH7EM  (FL_FOR_ARCH7M | FL_ARCH7EM)
+-#define FL_FOR_ARCH8A	(FL_FOR_ARCH7VE | FL_ARCH8)
+-#define FL2_FOR_ARCH8_1A	FL2_ARCH8_1
+-
+-/* There are too many feature bits to fit in a single word so the set of cpu and
+-   fpu capabilities is a structure.  A feature set is created and manipulated
+-   with the ARM_FSET macros.  */
+-
+-typedef struct
+-{
+-  unsigned long cpu[2];
+-} arm_feature_set;
+-
+-
+-/* Initialize a feature set.  */
+-
+-#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
+-
+-#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
+-#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
+-
+-/* Accessors.  */
+-
+-#define ARM_FSET_CPU1(S) ((S).cpu[0])
+-#define ARM_FSET_CPU2(S) ((S).cpu[1])
+-
+-/* Useful combinations.  */
+-
+-#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
+-#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
+-
+-/* Tests for a specific CPU feature.  */
+-
+-#define ARM_FSET_HAS_CPU1(A, F)  \
+-  (((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F)))
+-#define ARM_FSET_HAS_CPU2(A, F)  \
+-  (((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F)))
+-#define ARM_FSET_HAS_CPU(A, F1, F2)				\
+-  (ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2)))
+-
+-/* Add a feature to a feature set.  */
+-
+-#define ARM_FSET_ADD_CPU1(DST, F)		\
+-  do {						\
+-    (DST).cpu[0] |= (F);			\
+-  } while (0)
+-
+-#define ARM_FSET_ADD_CPU2(DST, F)		\
+-  do {						\
+-    (DST).cpu[1] |= (F);			\
+-  } while (0)
+-
+-/* Remove a feature from a feature set.  */
+-
+-#define ARM_FSET_DEL_CPU1(DST, F)		\
+-  do {						\
+-    (DST).cpu[0] &= ~(F);			\
+-  } while (0)
+-
+-#define ARM_FSET_DEL_CPU2(DST, F)		\
+-  do {						\
+-    (DST).cpu[1] &= ~(F);			\
+-  } while (0)
+-
+-/* Union of feature sets.  */
+-
+-#define ARM_FSET_UNION(DST,F1,F2)		\
+-  do {						\
+-    (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0];	\
+-    (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1];	\
+-  } while (0)
+-
+-/* Intersection of feature sets.  */
+-
+-#define ARM_FSET_INTER(DST,F1,F2)		\
+-  do {						\
+-    (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0];	\
+-    (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1];	\
+-  } while (0)
+-
+-/* Exclusive disjunction.  */
+-
+-#define ARM_FSET_XOR(DST,F1,F2)				\
+-  do {							\
+-    (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0];		\
+-    (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1];		\
+-  } while (0)
+-
+-/* Difference of feature sets: F1 excluding the elements of F2.  */
+-
+-#define ARM_FSET_EXCLUDE(DST,F1,F2)		\
+-  do {						\
+-    (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0];	\
+-    (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1];	\
+-  } while (0)
+-
+-/* Test for an empty feature set.  */
+-
+-#define ARM_FSET_IS_EMPTY(A)		\
+-  (!((A).cpu[0]) && !((A).cpu[1]))
+-
+-/* Tests whether the cpu features of A are a subset of B.  */
+-
+-#define ARM_FSET_CPU_SUBSET(A,B)					\
+-  ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0])				\
+-   && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
+-
+ /* The bits in this mask specify which
+    instructions we are allowed to generate.  */
+ extern arm_feature_set insn_flags;
+@@ -601,6 +430,9 @@ extern int arm_tune_cortex_a9;
+    interworking clean.  */
+ extern int arm_cpp_interwork;
+ 
++/* Nonzero if chip supports Thumb 1.  */
++extern int arm_arch_thumb1;
++
+ /* Nonzero if chip supports Thumb 2.  */
+ extern int arm_arch_thumb2;
+ 
+--- a/src/gcc/config/arm/arm-tables.opt
++++ b/src/gcc/config/arm/arm-tables.opt
+@@ -306,9 +306,15 @@ Enum(processor_type) String(cortex-a15.cortex-a7) Value(cortexa15cortexa7)
+ EnumValue
+ Enum(processor_type) String(cortex-a17.cortex-a7) Value(cortexa17cortexa7)
+ 
++EnumValue
++Enum(processor_type) String(cortex-m23) Value(cortexm23)
++
+ EnumValue
+ Enum(processor_type) String(cortex-a32) Value(cortexa32)
+ 
++EnumValue
++Enum(processor_type) String(cortex-m33) Value(cortexm33)
++
+ EnumValue
+ Enum(processor_type) String(cortex-a35) Value(cortexa35)
+ 
+@@ -321,6 +327,9 @@ Enum(processor_type) String(cortex-a57) Value(cortexa57)
+ EnumValue
+ Enum(processor_type) String(cortex-a72) Value(cortexa72)
+ 
++EnumValue
++Enum(processor_type) String(cortex-a73) Value(cortexa73)
++
+ EnumValue
+ Enum(processor_type) String(exynos-m1) Value(exynosm1)
+ 
+@@ -336,6 +345,12 @@ Enum(processor_type) String(cortex-a57.cortex-a53) Value(cortexa57cortexa53)
+ EnumValue
+ Enum(processor_type) String(cortex-a72.cortex-a53) Value(cortexa72cortexa53)
+ 
++EnumValue
++Enum(processor_type) String(cortex-a73.cortex-a35) Value(cortexa73cortexa35)
++
++EnumValue
++Enum(processor_type) String(cortex-a73.cortex-a53) Value(cortexa73cortexa53)
++
+ Enum
+ Name(arm_arch) Type(int)
+ Known ARM architectures (for use with the -march= option):
+@@ -428,10 +443,25 @@ EnumValue
+ Enum(arm_arch) String(armv8.1-a+crc) Value(28)
+ 
+ EnumValue
+-Enum(arm_arch) String(iwmmxt) Value(29)
++Enum(arm_arch) String(armv8.2-a) Value(29)
++
++EnumValue
++Enum(arm_arch) String(armv8.2-a+fp16) Value(30)
+ 
+ EnumValue
+-Enum(arm_arch) String(iwmmxt2) Value(30)
++Enum(arm_arch) String(armv8-m.base) Value(31)
++
++EnumValue
++Enum(arm_arch) String(armv8-m.main) Value(32)
++
++EnumValue
++Enum(arm_arch) String(armv8-m.main+dsp) Value(33)
++
++EnumValue
++Enum(arm_arch) String(iwmmxt) Value(34)
++
++EnumValue
++Enum(arm_arch) String(iwmmxt2) Value(35)
+ 
+ Enum
+ Name(arm_fpu) Type(int)
+@@ -441,56 +471,62 @@ EnumValue
+ Enum(arm_fpu) String(vfp) Value(0)
+ 
+ EnumValue
+-Enum(arm_fpu) String(vfpv3) Value(1)
++Enum(arm_fpu) String(vfpv2) Value(1)
++
++EnumValue
++Enum(arm_fpu) String(vfpv3) Value(2)
++
++EnumValue
++Enum(arm_fpu) String(vfpv3-fp16) Value(3)
+ 
+ EnumValue
+-Enum(arm_fpu) String(vfpv3-fp16) Value(2)
++Enum(arm_fpu) String(vfpv3-d16) Value(4)
+ 
+ EnumValue
+-Enum(arm_fpu) String(vfpv3-d16) Value(3)
++Enum(arm_fpu) String(vfpv3-d16-fp16) Value(5)
+ 
+ EnumValue
+-Enum(arm_fpu) String(vfpv3-d16-fp16) Value(4)
++Enum(arm_fpu) String(vfpv3xd) Value(6)
+ 
+ EnumValue
+-Enum(arm_fpu) String(vfpv3xd) Value(5)
++Enum(arm_fpu) String(vfpv3xd-fp16) Value(7)
+ 
+ EnumValue
+-Enum(arm_fpu) String(vfpv3xd-fp16) Value(6)
++Enum(arm_fpu) String(neon) Value(8)
+ 
+ EnumValue
+-Enum(arm_fpu) String(neon) Value(7)
++Enum(arm_fpu) String(neon-vfpv3) Value(9)
+ 
+ EnumValue
+-Enum(arm_fpu) String(neon-fp16) Value(8)
++Enum(arm_fpu) String(neon-fp16) Value(10)
+ 
+ EnumValue
+-Enum(arm_fpu) String(vfpv4) Value(9)
++Enum(arm_fpu) String(vfpv4) Value(11)
+ 
+ EnumValue
+-Enum(arm_fpu) String(vfpv4-d16) Value(10)
++Enum(arm_fpu) String(vfpv4-d16) Value(12)
+ 
+ EnumValue
+-Enum(arm_fpu) String(fpv4-sp-d16) Value(11)
++Enum(arm_fpu) String(fpv4-sp-d16) Value(13)
+ 
+ EnumValue
+-Enum(arm_fpu) String(fpv5-sp-d16) Value(12)
++Enum(arm_fpu) String(fpv5-sp-d16) Value(14)
+ 
+ EnumValue
+-Enum(arm_fpu) String(fpv5-d16) Value(13)
++Enum(arm_fpu) String(fpv5-d16) Value(15)
+ 
+ EnumValue
+-Enum(arm_fpu) String(neon-vfpv4) Value(14)
++Enum(arm_fpu) String(neon-vfpv4) Value(16)
+ 
+ EnumValue
+-Enum(arm_fpu) String(fp-armv8) Value(15)
++Enum(arm_fpu) String(fp-armv8) Value(17)
+ 
+ EnumValue
+-Enum(arm_fpu) String(neon-fp-armv8) Value(16)
++Enum(arm_fpu) String(neon-fp-armv8) Value(18)
+ 
+ EnumValue
+-Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(17)
++Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(19)
+ 
+ EnumValue
+-Enum(arm_fpu) String(vfp3) Value(18)
++Enum(arm_fpu) String(vfp3) Value(20)
+ 
+--- a/src/gcc/config/arm/arm-tune.md
++++ b/src/gcc/config/arm/arm-tune.md
+@@ -32,8 +32,10 @@
+ 	cortexr4f,cortexr5,cortexr7,
+ 	cortexr8,cortexm7,cortexm4,
+ 	cortexm3,marvell_pj4,cortexa15cortexa7,
+-	cortexa17cortexa7,cortexa32,cortexa35,
+-	cortexa53,cortexa57,cortexa72,
++	cortexa17cortexa7,cortexm23,cortexa32,
++	cortexm33,cortexa35,cortexa53,
++	cortexa57,cortexa72,cortexa73,
+ 	exynosm1,qdf24xx,xgene1,
+-	cortexa57cortexa53,cortexa72cortexa53"
++	cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
++	cortexa73cortexa53"
+ 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
+--- a/src/gcc/config/arm/arm.c
++++ b/src/gcc/config/arm/arm.c
+@@ -27,6 +27,7 @@
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "cfghooks.h"
+ #include "df.h"
+ #include "tm_p.h"
+@@ -61,6 +62,7 @@
+ #include "builtins.h"
+ #include "tm-constrs.h"
+ #include "rtl-iter.h"
++#include "gimplify.h"
+ #include "gimple.h"
+ 
+ /* This file should be included last.  */
+@@ -105,7 +107,6 @@ static void arm_print_operand_address (FILE *, machine_mode, rtx);
+ static bool arm_print_operand_punct_valid_p (unsigned char code);
+ static const char *fp_const_from_val (REAL_VALUE_TYPE *);
+ static arm_cc get_arm_condition_code (rtx);
+-static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
+ static const char *output_multi_immediate (rtx *, const char *, const char *,
+ 					   int, HOST_WIDE_INT);
+ static const char *shift_op (rtx, HOST_WIDE_INT *);
+@@ -136,6 +137,8 @@ static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
+ #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
+ static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
+ #endif
++static tree arm_handle_cmse_nonsecure_entry (tree *, tree, tree, int, bool *);
++static tree arm_handle_cmse_nonsecure_call (tree *, tree, tree, int, bool *);
+ static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
+ static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
+ static int arm_comp_type_attributes (const_tree, const_tree);
+@@ -165,12 +168,6 @@ static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
+ static bool arm_have_conditional_execution (void);
+ static bool arm_cannot_force_const_mem (machine_mode, rtx);
+ static bool arm_legitimate_constant_p (machine_mode, rtx);
+-static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool);
+-static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
+-static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
+-static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
+-static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
+-static bool arm_9e_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
+ static bool arm_rtx_costs (rtx, machine_mode, int, int, int *, bool);
+ static int arm_address_cost (rtx, machine_mode, addr_space_t, bool);
+ static int arm_register_move_cost (machine_mode, reg_class_t, reg_class_t);
+@@ -216,8 +213,8 @@ static bool arm_return_in_memory (const_tree, const_tree);
+ static void arm_unwind_emit (FILE *, rtx_insn *);
+ static bool arm_output_ttype (rtx);
+ static void arm_asm_emit_except_personality (rtx);
+-static void arm_asm_init_sections (void);
+ #endif
++static void arm_asm_init_sections (void);
+ static rtx arm_dwarf_register_span (rtx);
+ 
+ static tree arm_cxx_guard_type (void);
+@@ -250,8 +247,6 @@ static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
+ static bool arm_output_addr_const_extra (FILE *, rtx);
+ static bool arm_allocate_stack_slots_for_args (void);
+ static bool arm_warn_func_return (tree);
+-static const char *arm_invalid_parameter_type (const_tree t);
+-static const char *arm_invalid_return_type (const_tree t);
+ static tree arm_promoted_type (const_tree t);
+ static tree arm_convert_to_type (tree type, tree expr);
+ static bool arm_scalar_mode_supported_p (machine_mode);
+@@ -301,6 +296,12 @@ static void arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
+ static unsigned HOST_WIDE_INT arm_asan_shadow_offset (void);
+ 
+ static void arm_sched_fusion_priority (rtx_insn *, int, int *, int*);
++static bool arm_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT,
++				     const_tree);
++static section *arm_function_section (tree, enum node_frequency, bool, bool);
++static bool arm_asm_elf_flags_numeric (unsigned int flags, unsigned int *num);
++static unsigned int arm_elf_section_type_flags (tree decl, const char *name,
++						int reloc);
+ 
+ /* Table of machine attributes.  */
+ static const struct attribute_spec arm_attribute_table[] =
+@@ -344,6 +345,11 @@ static const struct attribute_spec arm_attribute_table[] =
+   { "notshared",    0, 0, false, true, false, arm_handle_notshared_attribute,
+     false },
+ #endif
++  /* ARMv8-M Security Extensions support.  */
++  { "cmse_nonsecure_entry", 0, 0, true, false, false,
++    arm_handle_cmse_nonsecure_entry, false },
++  { "cmse_nonsecure_call", 0, 0, true, false, false,
++    arm_handle_cmse_nonsecure_call, true },
+   { NULL,           0, 0, false, false, false, NULL, false }
+ };
+ 
+@@ -464,7 +470,7 @@ static const struct attribute_spec arm_attribute_table[] =
+ #undef  TARGET_ASM_OUTPUT_MI_THUNK
+ #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
+ #undef  TARGET_ASM_CAN_OUTPUT_MI_THUNK
+-#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
++#define TARGET_ASM_CAN_OUTPUT_MI_THUNK arm_can_output_mi_thunk
+ 
+ #undef  TARGET_RTX_COSTS
+ #define TARGET_RTX_COSTS arm_rtx_costs
+@@ -587,9 +593,10 @@ static const struct attribute_spec arm_attribute_table[] =
+ #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
+ #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY arm_asm_emit_except_personality
+ 
++#endif /* ARM_UNWIND_INFO */
++
+ #undef TARGET_ASM_INIT_SECTIONS
+ #define TARGET_ASM_INIT_SECTIONS arm_asm_init_sections
+-#endif /* ARM_UNWIND_INFO */
+ 
+ #undef TARGET_DWARF_REGISTER_SPAN
+ #define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span
+@@ -655,12 +662,6 @@ static const struct attribute_spec arm_attribute_table[] =
+ #undef TARGET_PREFERRED_RELOAD_CLASS
+ #define TARGET_PREFERRED_RELOAD_CLASS arm_preferred_reload_class
+ 
+-#undef TARGET_INVALID_PARAMETER_TYPE
+-#define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type
+-
+-#undef TARGET_INVALID_RETURN_TYPE
+-#define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type
+-
+ #undef TARGET_PROMOTED_TYPE
+ #define TARGET_PROMOTED_TYPE arm_promoted_type
+ 
+@@ -736,6 +737,15 @@ static const struct attribute_spec arm_attribute_table[] =
+ #undef TARGET_SCHED_FUSION_PRIORITY
+ #define TARGET_SCHED_FUSION_PRIORITY arm_sched_fusion_priority
+ 
++#undef  TARGET_ASM_FUNCTION_SECTION
++#define TARGET_ASM_FUNCTION_SECTION arm_function_section
++
++#undef TARGET_ASM_ELF_FLAGS_NUMERIC
++#define TARGET_ASM_ELF_FLAGS_NUMERIC arm_asm_elf_flags_numeric
++
++#undef TARGET_SECTION_TYPE_FLAGS
++#define TARGET_SECTION_TYPE_FLAGS arm_elf_section_type_flags
++
+ struct gcc_target targetm = TARGET_INITIALIZER;
+ 
+ /* Obstack for minipool constant handling.  */
+@@ -821,6 +831,13 @@ int arm_arch8 = 0;
+ /* Nonzero if this chip supports the ARMv8.1 extensions.  */
+ int arm_arch8_1 = 0;
+ 
++/* Nonzero if this chip supports the ARM Architecture 8.2 extensions.  */
++int arm_arch8_2 = 0;
++
++/* Nonzero if this chip supports the FP16 instructions extension of ARM
++   Architecture 8.2.  */
++int arm_fp16_inst = 0;
++
+ /* Nonzero if this chip can benefit from load scheduling.  */
+ int arm_ld_sched = 0;
+ 
+@@ -853,6 +870,9 @@ int arm_tune_cortex_a9 = 0;
+    interworking clean.  */
+ int arm_cpp_interwork = 0;
+ 
++/* Nonzero if chip supports Thumb 1.  */
++int arm_arch_thumb1;
++
+ /* Nonzero if chip supports Thumb 2.  */
+ int arm_arch_thumb2;
+ 
+@@ -896,6 +916,9 @@ int arm_condexec_masklen = 0;
+ /* Nonzero if chip supports the ARMv8 CRC instructions.  */
+ int arm_arch_crc = 0;
+ 
++/* Nonzero if chip supports the ARMv8-M security extensions.  */
++int arm_arch_cmse = 0;
++
+ /* Nonzero if the core has a very small, high-latency, multiply unit.  */
+ int arm_m_profile_small_mul = 0;
+ 
+@@ -1688,8 +1711,7 @@ const struct cpu_cost_table v7m_extra_costs =
+ 
+ const struct tune_params arm_slowmul_tune =
+ {
+-  arm_slowmul_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1711,8 +1733,7 @@ const struct tune_params arm_slowmul_tune =
+ 
+ const struct tune_params arm_fastmul_tune =
+ {
+-  arm_fastmul_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1737,8 +1758,7 @@ const struct tune_params arm_fastmul_tune =
+ 
+ const struct tune_params arm_strongarm_tune =
+ {
+-  arm_fastmul_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1760,8 +1780,7 @@ const struct tune_params arm_strongarm_tune =
+ 
+ const struct tune_params arm_xscale_tune =
+ {
+-  arm_xscale_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   xscale_sched_adjust_cost,
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1783,8 +1802,7 @@ const struct tune_params arm_xscale_tune =
+ 
+ const struct tune_params arm_9e_tune =
+ {
+-  arm_9e_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1806,8 +1824,7 @@ const struct tune_params arm_9e_tune =
+ 
+ const struct tune_params arm_marvell_pj4_tune =
+ {
+-  arm_9e_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1829,8 +1846,7 @@ const struct tune_params arm_marvell_pj4_tune =
+ 
+ const struct tune_params arm_v6t2_tune =
+ {
+-  arm_9e_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -1854,7 +1870,6 @@ const struct tune_params arm_v6t2_tune =
+ /* Generic Cortex tuning.  Use more specific tunings if appropriate.  */
+ const struct tune_params arm_cortex_tune =
+ {
+-  arm_9e_rtx_costs,
+   &generic_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -1877,7 +1892,6 @@ const struct tune_params arm_cortex_tune =
+ 
+ const struct tune_params arm_cortex_a8_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa8_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -1900,7 +1914,6 @@ const struct tune_params arm_cortex_a8_tune =
+ 
+ const struct tune_params arm_cortex_a7_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa7_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -1923,7 +1936,6 @@ const struct tune_params arm_cortex_a7_tune =
+ 
+ const struct tune_params arm_cortex_a15_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa15_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -1946,7 +1958,6 @@ const struct tune_params arm_cortex_a15_tune =
+ 
+ const struct tune_params arm_cortex_a35_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa53_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -1969,7 +1980,6 @@ const struct tune_params arm_cortex_a35_tune =
+ 
+ const struct tune_params arm_cortex_a53_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa53_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -1992,7 +2002,6 @@ const struct tune_params arm_cortex_a53_tune =
+ 
+ const struct tune_params arm_cortex_a57_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa57_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -2015,7 +2024,6 @@ const struct tune_params arm_cortex_a57_tune =
+ 
+ const struct tune_params arm_exynosm1_tune =
+ {
+-  arm_9e_rtx_costs,
+   &exynosm1_extra_costs,
+   NULL,						/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -2038,7 +2046,6 @@ const struct tune_params arm_exynosm1_tune =
+ 
+ const struct tune_params arm_xgene1_tune =
+ {
+-  arm_9e_rtx_costs,
+   &xgene1_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -2059,12 +2066,33 @@ const struct tune_params arm_xgene1_tune =
+   tune_params::SCHED_AUTOPREF_OFF
+ };
+ 
++const struct tune_params arm_qdf24xx_tune =
++{
++  &qdf24xx_extra_costs,
++  NULL,                                         /* Scheduler cost adjustment.  */
++  arm_default_branch_cost,
++  &arm_default_vec_cost,			/* Vectorizer costs.  */
++  1,						/* Constant limit.  */
++  2,						/* Max cond insns.  */
++  8,						/* Memset max inline.  */
++  4,						/* Issue rate.  */
++  ARM_PREFETCH_BENEFICIAL (0, -1, 64),
++  tune_params::PREF_CONST_POOL_FALSE,
++  tune_params::PREF_LDRD_TRUE,
++  tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE,	/* Thumb.  */
++  tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE,	/* ARM.  */
++  tune_params::DISPARAGE_FLAGS_ALL,
++  tune_params::PREF_NEON_64_FALSE,
++  tune_params::PREF_NEON_STRINGOPS_TRUE,
++  FUSE_OPS (tune_params::FUSE_MOVW_MOVT),
++  tune_params::SCHED_AUTOPREF_FULL
++};
++
+ /* Branches can be dual-issued on Cortex-A5, so conditional execution is
+    less appealing.  Set max_insns_skipped to a low value.  */
+ 
+ const struct tune_params arm_cortex_a5_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa5_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_cortex_a5_branch_cost,
+@@ -2087,7 +2115,6 @@ const struct tune_params arm_cortex_a5_tune =
+ 
+ const struct tune_params arm_cortex_a9_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa9_extra_costs,
+   cortex_a9_sched_adjust_cost,
+   arm_default_branch_cost,
+@@ -2110,7 +2137,6 @@ const struct tune_params arm_cortex_a9_tune =
+ 
+ const struct tune_params arm_cortex_a12_tune =
+ {
+-  arm_9e_rtx_costs,
+   &cortexa12_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+@@ -2131,6 +2157,28 @@ const struct tune_params arm_cortex_a12_tune =
+   tune_params::SCHED_AUTOPREF_OFF
+ };
+ 
++const struct tune_params arm_cortex_a73_tune =
++{
++  &cortexa57_extra_costs,
++  NULL,						/* Sched adj cost.  */
++  arm_default_branch_cost,
++  &arm_default_vec_cost,			/* Vectorizer costs.  */
++  1,						/* Constant limit.  */
++  2,						/* Max cond insns.  */
++  8,						/* Memset max inline.  */
++  2,						/* Issue rate.  */
++  ARM_PREFETCH_NOT_BENEFICIAL,
++  tune_params::PREF_CONST_POOL_FALSE,
++  tune_params::PREF_LDRD_TRUE,
++  tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE,		/* Thumb.  */
++  tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE,		/* ARM.  */
++  tune_params::DISPARAGE_FLAGS_ALL,
++  tune_params::PREF_NEON_64_FALSE,
++  tune_params::PREF_NEON_STRINGOPS_TRUE,
++  FUSE_OPS (tune_params::FUSE_AES_AESMC | tune_params::FUSE_MOVW_MOVT),
++  tune_params::SCHED_AUTOPREF_FULL
++};
++
+ /* armv7m tuning.  On Cortex-M4 cores for example, MOVW/MOVT take a single
+    cycle to execute each.  An LDR from the constant pool also takes two cycles
+    to execute, but mildly increases pipelining opportunity (consecutive
+@@ -2140,7 +2188,6 @@ const struct tune_params arm_cortex_a12_tune =
+ 
+ const struct tune_params arm_v7m_tune =
+ {
+-  arm_9e_rtx_costs,
+   &v7m_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_cortex_m_branch_cost,
+@@ -2165,7 +2212,6 @@ const struct tune_params arm_v7m_tune =
+ 
+ const struct tune_params arm_cortex_m7_tune =
+ {
+-  arm_9e_rtx_costs,
+   &v7m_extra_costs,
+   NULL,					/* Sched adj cost.  */
+   arm_cortex_m7_branch_cost,
+@@ -2187,11 +2233,11 @@ const struct tune_params arm_cortex_m7_tune =
+ };
+ 
+ /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than
+-   arm_v6t2_tune. It is used for cortex-m0, cortex-m1 and cortex-m0plus.  */
++   arm_v6t2_tune.  It is used for cortex-m0, cortex-m1, cortex-m0plus and
++   cortex-m23.  */
+ const struct tune_params arm_v6m_tune =
+ {
+-  arm_9e_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,			/* Insn extra costs.  */
+   NULL,					/* Sched adj cost.  */
+   arm_default_branch_cost,
+   &arm_default_vec_cost,                        /* Vectorizer costs.  */
+@@ -2213,8 +2259,7 @@ const struct tune_params arm_v6m_tune =
+ 
+ const struct tune_params arm_fa726te_tune =
+ {
+-  arm_9e_rtx_costs,
+-  NULL,					/* Insn extra costs.  */
++  &generic_extra_costs,				/* Insn extra costs.  */
+   fa726te_sched_adjust_cost,
+   arm_default_branch_cost,
+   &arm_default_vec_cost,
+@@ -2268,16 +2313,18 @@ static const struct processors *arm_selected_arch;
+ static const struct processors *arm_selected_cpu;
+ static const struct processors *arm_selected_tune;
+ 
+-/* The name of the preprocessor macro to define for this architecture.  */
++/* The name of the preprocessor macro to define for this architecture.  PROFILE
++   is replaced by the architecture name (eg. 8A) in arm_option_override () and
++   is thus chosen to be big enough to hold the longest architecture name.  */
+ 
+-char arm_arch_name[] = "__ARM_ARCH_0UNK__";
++char arm_arch_name[] = "__ARM_ARCH_PROFILE__";
+ 
+ /* Available values for -mfpu=.  */
+ 
+ const struct arm_fpu_desc all_fpus[] =
+ {
+-#define ARM_FPU(NAME, MODEL, REV, VFP_REGS, FEATURES) \
+-  { NAME, MODEL, REV, VFP_REGS, FEATURES },
++#define ARM_FPU(NAME, REV, VFP_REGS, FEATURES) \
++  { NAME, REV, VFP_REGS, FEATURES },
+ #include "arm-fpus.def"
+ #undef ARM_FPU
+ };
+@@ -2756,8 +2803,8 @@ arm_option_check_internal (struct gcc_options *opts)
+   const struct arm_fpu_desc *fpu_desc = &all_fpus[opts->x_arm_fpu_index];
+ 
+   /* iWMMXt and NEON are incompatible.  */
+-    if (TARGET_IWMMXT && TARGET_VFP
+-      && ARM_FPU_FSET_HAS (fpu_desc->features, FPU_FL_NEON))
++    if (TARGET_IWMMXT
++	&& ARM_FPU_FSET_HAS (fpu_desc->features, FPU_FL_NEON))
+     error ("iWMMXt and NEON are incompatible");
+ 
+   /* Make sure that the processor choice does not conflict with any of the
+@@ -2794,11 +2841,17 @@ arm_option_check_internal (struct gcc_options *opts)
+       flag_pic = 0;
+     }
+ 
+-  /* We only support -mslow-flash-data on armv7-m targets.  */
+-  if (target_slow_flash_data
+-      && ((!(arm_arch7 && !arm_arch_notm) && !arm_arch7em)
+-	  || (TARGET_THUMB1_P (flags) || flag_pic || TARGET_NEON)))
+-    error ("-mslow-flash-data only supports non-pic code on armv7-m targets");
++  /* We only support -mpure-code and -mslow-flash-data on M-profile targets
++     with MOVT.  */
++  if ((target_pure_code || target_slow_flash_data)
++      && (!TARGET_HAVE_MOVT || arm_arch_notm || flag_pic || TARGET_NEON))
++    {
++      const char *flag = (target_pure_code ? "-mpure-code" :
++					     "-mslow-flash-data");
++      error ("%s only supports non-pic code on M-profile targets with the "
++	     "MOVT instruction", flag);
++    }
++
+ }
+ 
+ /* Recompute the global settings depending on target attribute options.  */
+@@ -2911,7 +2964,8 @@ arm_option_override_internal (struct gcc_options *opts,
+   if (! opts_set->x_arm_restrict_it)
+     opts->x_arm_restrict_it = arm_arch8;
+ 
+-  if (!TARGET_THUMB2_P (opts->x_target_flags))
++  /* ARM execution state and M profile don't have [restrict] IT.  */
++  if (!TARGET_THUMB2_P (opts->x_target_flags) || !arm_arch_notm)
+     opts->x_arm_restrict_it = 0;
+ 
+   /* Enable -munaligned-access by default for
+@@ -2922,7 +2976,8 @@ arm_option_override_internal (struct gcc_options *opts,
+ 
+      Disable -munaligned-access by default for
+      - all pre-ARMv6 architecture-based processors
+-     - ARMv6-M architecture-based processors.  */
++     - ARMv6-M architecture-based processors
++     - ARMv8-M Baseline processors.  */
+ 
+   if (! opts_set->x_unaligned_access)
+     {
+@@ -3156,9 +3211,6 @@ arm_option_override (void)
+   if (TARGET_APCS_REENT)
+     warning (0, "APCS reentrant code not supported.  Ignored");
+ 
+-  if (TARGET_APCS_FLOAT)
+-    warning (0, "passing floating point arguments in fp regs not yet supported");
+-
+   /* Initialize boolean versions of the flags, for use in the arm.md file.  */
+   arm_arch3m = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH3M);
+   arm_arch4 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH4);
+@@ -3174,6 +3226,8 @@ arm_option_override (void)
+   arm_arch7em = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7EM);
+   arm_arch8 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH8);
+   arm_arch8_1 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_1);
++  arm_arch8_2 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_2);
++  arm_arch_thumb1 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB);
+   arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2);
+   arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE);
+ 
+@@ -3189,7 +3243,15 @@ arm_option_override (void)
+   arm_arch_no_volatile_ce = ARM_FSET_HAS_CPU1 (insn_flags, FL_NO_VOLATILE_CE);
+   arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
+   arm_arch_crc = ARM_FSET_HAS_CPU1 (insn_flags, FL_CRC32);
++  arm_arch_cmse = ARM_FSET_HAS_CPU2 (insn_flags, FL2_CMSE);
+   arm_m_profile_small_mul = ARM_FSET_HAS_CPU1 (insn_flags, FL_SMALLMUL);
++  arm_fp16_inst = ARM_FSET_HAS_CPU2 (insn_flags, FL2_FP16INST);
++  if (arm_fp16_inst)
++    {
++      if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
++	error ("selected fp16 options are incompatible.");
++      arm_fp16_format = ARM_FP16_FORMAT_IEEE;
++    }
+ 
+   /* V5 code we generate is completely interworking capable, so we turn off
+      TARGET_INTERWORK here to avoid many tests later on.  */
+@@ -3227,10 +3289,8 @@ arm_option_override (void)
+   /* If soft-float is specified then don't use FPU.  */
+   if (TARGET_SOFT_FLOAT)
+     arm_fpu_attr = FPU_NONE;
+-  else if (TARGET_VFP)
+-    arm_fpu_attr = FPU_VFP;
+   else
+-    gcc_unreachable();
++    arm_fpu_attr = FPU_VFP;
+ 
+   if (TARGET_AAPCS_BASED)
+     {
+@@ -3250,15 +3310,14 @@ arm_option_override (void)
+       if (arm_abi == ARM_ABI_IWMMXT)
+ 	arm_pcs_default = ARM_PCS_AAPCS_IWMMXT;
+       else if (arm_float_abi == ARM_FLOAT_ABI_HARD
+-	       && TARGET_HARD_FLOAT
+-	       && TARGET_VFP)
++	       && TARGET_HARD_FLOAT)
+ 	arm_pcs_default = ARM_PCS_AAPCS_VFP;
+       else
+ 	arm_pcs_default = ARM_PCS_AAPCS;
+     }
+   else
+     {
+-      if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
++      if (arm_float_abi == ARM_FLOAT_ABI_HARD)
+ 	sorry ("-mfloat-abi=hard and VFP");
+ 
+       if (arm_abi == ARM_ABI_APCS)
+@@ -3303,6 +3362,20 @@ arm_option_override (void)
+ 	}
+     }
+ 
++  if (TARGET_VXWORKS_RTP)
++    {
++      if (!global_options_set.x_arm_pic_data_is_text_relative)
++	arm_pic_data_is_text_relative = 0;
++    }
++  else if (flag_pic
++	   && !arm_pic_data_is_text_relative
++	   && !(global_options_set.x_target_flags & MASK_SINGLE_PIC_BASE))
++    /* When text & data segments don't have a fixed displacement, the
++       intended use is with a single, read only, pic base register.
++       Unless the user explicitly requested not to do that, set
++       it.  */
++    target_flags |= MASK_SINGLE_PIC_BASE;
++
+   /* If stack checking is disabled, we can use r10 as the PIC register,
+      which keeps r9 available.  The EABI specifies r9 as the PIC register.  */
+   if (flag_pic && TARGET_SINGLE_PIC_BASE)
+@@ -3334,10 +3407,6 @@ arm_option_override (void)
+ 	arm_pic_register = pic_register;
+     }
+ 
+-  if (TARGET_VXWORKS_RTP
+-      && !global_options_set.x_arm_pic_data_is_text_relative)
+-    arm_pic_data_is_text_relative = 0;
+-
+   /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores.  */
+   if (fix_cm3_ldrd == 2)
+     {
+@@ -3437,10 +3506,14 @@ arm_option_override (void)
+ 			 global_options.x_param_values,
+ 			 global_options_set.x_param_values);
+ 
+-  /* Currently, for slow flash data, we just disable literal pools.  */
+-  if (target_slow_flash_data)
++  /* Currently, for slow flash data, we just disable literal pools.  We also
++     disable it for pure-code.  */
++  if (target_slow_flash_data || target_pure_code)
+     arm_disable_literal_pool = true;
+ 
++  if (use_cmse && !arm_arch_cmse)
++    error ("target CPU does not support ARMv8-M Security Extensions");
++
+   /* Disable scheduling fusion by default if it's not armv7 processor
+      or doesn't prefer ldrd/strd.  */
+   if (flag_schedule_fusion == 2
+@@ -3573,6 +3646,9 @@ arm_compute_func_type (void)
+   else
+     type |= arm_isr_value (TREE_VALUE (a));
+ 
++  if (lookup_attribute ("cmse_nonsecure_entry", attr))
++    type |= ARM_FT_CMSE_ENTRY;
++
+   return type;
+ }
+ 
+@@ -3799,6 +3875,11 @@ use_return_insn (int iscond, rtx sibling)
+ 	return 0;
+     }
+ 
++  /* ARMv8-M nonsecure entry function need to use bxns to return and thus need
++     several instructions if anything needs to be popped.  */
++  if (saved_int_regs && IS_CMSE_ENTRY (func_type))
++    return 0;
++
+   /* If there are saved registers but the LR isn't saved, then we need
+      two instructions for the return.  */
+   if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
+@@ -3806,7 +3887,7 @@ use_return_insn (int iscond, rtx sibling)
+ 
+   /* Can't be done if any of the VFP regs are pushed,
+      since this also requires an insn.  */
+-  if (TARGET_HARD_FLOAT && TARGET_VFP)
++  if (TARGET_HARD_FLOAT)
+     for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
+       if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
+ 	return 0;
+@@ -3873,7 +3954,7 @@ const_ok_for_arm (HOST_WIDE_INT i)
+ 	       || (i & ~0xfc000003) == 0))
+ 	return TRUE;
+     }
+-  else
++  else if (TARGET_THUMB2)
+     {
+       HOST_WIDE_INT v;
+ 
+@@ -3889,6 +3970,14 @@ const_ok_for_arm (HOST_WIDE_INT i)
+       if (i == v)
+ 	return TRUE;
+     }
++  else if (TARGET_HAVE_MOVT)
++    {
++      /* Thumb-1 Targets with MOVT.  */
++      if (i > 0xffff)
++	return FALSE;
++      else
++	return TRUE;
++    }
+ 
+   return FALSE;
+ }
+@@ -3904,7 +3993,7 @@ const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
+     {
+     case SET:
+       /* See if we can use movw.  */
+-      if (arm_arch_thumb2 && (i & 0xffff0000) == 0)
++      if (TARGET_HAVE_MOVT && (i & 0xffff0000) == 0)
+ 	return 1;
+       else
+ 	/* Otherwise, try mvn.  */
+@@ -4123,7 +4212,7 @@ optimal_immediate_sequence (enum rtx_code code, unsigned HOST_WIDE_INT val,
+      yield a shorter sequence, we may as well use zero.  */
+   insns1 = optimal_immediate_sequence_1 (code, val, return_sequence, best_start);
+   if (best_start != 0
+-      && ((((unsigned HOST_WIDE_INT) 1) << best_start) < val))
++      && ((HOST_WIDE_INT_1U << best_start) < val))
+     {
+       insns2 = optimal_immediate_sequence_1 (code, val, &tmp_sequence, 0);
+       if (insns2 <= insns1)
+@@ -4954,7 +5043,7 @@ arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
+   if (mode == VOIDmode)
+     mode = GET_MODE (*op1);
+ 
+-  maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
++  maxval = (HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1)) - 1;
+ 
+   /* For DImode, we have GE/LT/GEU/LTU comparisons.  In ARM mode
+      we can also use cmp/cmpeq for GTU/LEU.  GT/LE must be either
+@@ -5260,7 +5349,6 @@ arm_function_value_regno_p (const unsigned int regno)
+   if (regno == ARG_REGISTER (1)
+       || (TARGET_32BIT
+ 	  && TARGET_AAPCS_BASED
+-	  && TARGET_VFP
+ 	  && TARGET_HARD_FLOAT
+ 	  && regno == FIRST_VFP_REGNUM)
+       || (TARGET_IWMMXT_ABI
+@@ -5279,7 +5367,7 @@ arm_apply_result_size (void)
+ 
+   if (TARGET_32BIT)
+     {
+-      if (TARGET_HARD_FLOAT_ABI && TARGET_VFP)
++      if (TARGET_HARD_FLOAT_ABI)
+ 	size += 32;
+       if (TARGET_IWMMXT_ABI)
+ 	size += 8;
+@@ -5554,7 +5642,7 @@ aapcs_vfp_sub_candidate (const_tree type, machine_mode *modep)
+     {
+     case REAL_TYPE:
+       mode = TYPE_MODE (type);
+-      if (mode != DFmode && mode != SFmode)
++      if (mode != DFmode && mode != SFmode && mode != HFmode)
+ 	return -1;
+ 
+       if (*modep == VOIDmode)
+@@ -5727,7 +5815,7 @@ use_vfp_abi (enum arm_pcs pcs_variant, bool is_double)
+   if (pcs_variant != ARM_PCS_AAPCS_LOCAL)
+     return false;
+ 
+-  return (TARGET_32BIT && TARGET_VFP && TARGET_HARD_FLOAT &&
++  return (TARGET_32BIT && TARGET_HARD_FLOAT &&
+ 	  (TARGET_VFP_DOUBLE || !is_double));
+ }
+ 
+@@ -5802,11 +5890,16 @@ aapcs_vfp_is_call_candidate (CUMULATIVE_ARGS *pcum, machine_mode mode,
+ 						&pcum->aapcs_vfp_rcount);
+ }
+ 
++/* Implement the allocate field in aapcs_cp_arg_layout.  See the comment there
++   for the behaviour of this function.  */
++
+ static bool
+ aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, machine_mode mode,
+ 		    const_tree type  ATTRIBUTE_UNUSED)
+ {
+-  int shift = GET_MODE_SIZE (pcum->aapcs_vfp_rmode) / GET_MODE_SIZE (SFmode);
++  int rmode_size
++    = MAX (GET_MODE_SIZE (pcum->aapcs_vfp_rmode), GET_MODE_SIZE (SFmode));
++  int shift = rmode_size / GET_MODE_SIZE (SFmode);
+   unsigned mask = (1 << (shift * pcum->aapcs_vfp_rcount)) - 1;
+   int regno;
+ 
+@@ -5855,6 +5948,9 @@ aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, machine_mode mode,
+   return false;
+ }
+ 
++/* Implement the allocate_return_reg field in aapcs_cp_arg_layout.  See the
++   comment there for the behaviour of this function.  */
++
+ static rtx
+ aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED,
+ 			       machine_mode mode,
+@@ -5945,13 +6041,13 @@ static struct
+      required for a return from FUNCTION_ARG.  */
+   bool (*allocate) (CUMULATIVE_ARGS *, machine_mode, const_tree);
+ 
+-  /* Return true if a result of mode MODE (or type TYPE if MODE is
+-     BLKmode) is can be returned in this co-processor's registers.  */
++  /* Return true if a result of mode MODE (or type TYPE if MODE is BLKmode) can
++     be returned in this co-processor's registers.  */
+   bool (*is_return_candidate) (enum arm_pcs, machine_mode, const_tree);
+ 
+-  /* Allocate and return an RTX element to hold the return type of a
+-     call, this routine must not fail and will only be called if
+-     is_return_candidate returned true with the same parameters.  */
++  /* Allocate and return an RTX element to hold the return type of a call.  This
++     routine must not fail and will only be called if is_return_candidate
++     returned true with the same parameters.  */
+   rtx (*allocate_return_reg) (enum arm_pcs, machine_mode, const_tree);
+ 
+   /* Finish processing this argument and prepare to start processing
+@@ -6602,6 +6698,185 @@ arm_handle_notshared_attribute (tree *node,
+ }
+ #endif
+ 
++/* This function returns true if a function with declaration FNDECL and type
++   FNTYPE uses the stack to pass arguments or return variables and false
++   otherwise.  This is used for functions with the attributes
++   'cmse_nonsecure_call' or 'cmse_nonsecure_entry' and this function will issue
++   diagnostic messages if the stack is used.  NAME is the name of the attribute
++   used.  */
++
++static bool
++cmse_func_args_or_return_in_stack (tree fndecl, tree name, tree fntype)
++{
++  function_args_iterator args_iter;
++  CUMULATIVE_ARGS args_so_far_v;
++  cumulative_args_t args_so_far;
++  bool first_param = true;
++  tree arg_type, prev_arg_type = NULL_TREE, ret_type;
++
++  /* Error out if any argument is passed on the stack.  */
++  arm_init_cumulative_args (&args_so_far_v, fntype, NULL_RTX, fndecl);
++  args_so_far = pack_cumulative_args (&args_so_far_v);
++  FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
++    {
++      rtx arg_rtx;
++      machine_mode arg_mode = TYPE_MODE (arg_type);
++
++      prev_arg_type = arg_type;
++      if (VOID_TYPE_P (arg_type))
++	continue;
++
++      if (!first_param)
++	arm_function_arg_advance (args_so_far, arg_mode, arg_type, true);
++      arg_rtx = arm_function_arg (args_so_far, arg_mode, arg_type, true);
++      if (!arg_rtx
++	  || arm_arg_partial_bytes (args_so_far, arg_mode, arg_type, true))
++	{
++	  error ("%qE attribute not available to functions with arguments "
++		 "passed on the stack", name);
++	  return true;
++	}
++      first_param = false;
++    }
++
++  /* Error out for variadic functions since we cannot control how many
++     arguments will be passed and thus stack could be used.  stdarg_p () is not
++     used for the checking to avoid browsing arguments twice.  */
++  if (prev_arg_type != NULL_TREE && !VOID_TYPE_P (prev_arg_type))
++    {
++      error ("%qE attribute not available to functions with variable number "
++	     "of arguments", name);
++      return true;
++    }
++
++  /* Error out if return value is passed on the stack.  */
++  ret_type = TREE_TYPE (fntype);
++  if (arm_return_in_memory (ret_type, fntype))
++    {
++      error ("%qE attribute not available to functions that return value on "
++	     "the stack", name);
++      return true;
++    }
++  return false;
++}
++
++/* Called upon detection of the use of the cmse_nonsecure_entry attribute, this
++   function will check whether the attribute is allowed here and will add the
++   attribute to the function declaration tree or otherwise issue a warning.  */
++
++static tree
++arm_handle_cmse_nonsecure_entry (tree *node, tree name,
++				 tree /* args */,
++				 int /* flags */,
++				 bool *no_add_attrs)
++{
++  tree fndecl;
++
++  if (!use_cmse)
++    {
++      *no_add_attrs = true;
++      warning (OPT_Wattributes, "%qE attribute ignored without -mcmse option.",
++	       name);
++      return NULL_TREE;
++    }
++
++  /* Ignore attribute for function types.  */
++  if (TREE_CODE (*node) != FUNCTION_DECL)
++    {
++      warning (OPT_Wattributes, "%qE attribute only applies to functions",
++	       name);
++      *no_add_attrs = true;
++      return NULL_TREE;
++    }
++
++  fndecl = *node;
++
++  /* Warn for static linkage functions.  */
++  if (!TREE_PUBLIC (fndecl))
++    {
++      warning (OPT_Wattributes, "%qE attribute has no effect on functions "
++	       "with static linkage", name);
++      *no_add_attrs = true;
++      return NULL_TREE;
++    }
++
++  *no_add_attrs |= cmse_func_args_or_return_in_stack (fndecl, name,
++						TREE_TYPE (fndecl));
++  return NULL_TREE;
++}
++
++
++/* Called upon detection of the use of the cmse_nonsecure_call attribute, this
++   function will check whether the attribute is allowed here and will add the
++   attribute to the function type tree or otherwise issue a diagnostic.  The
++   reason we check this at declaration time is to only allow the use of the
++   attribute with declarations of function pointers and not function
++   declarations.  This function checks NODE is of the expected type and issues
++   diagnostics otherwise using NAME.  If it is not of the expected type
++   *NO_ADD_ATTRS will be set to true.  */
++
++static tree
++arm_handle_cmse_nonsecure_call (tree *node, tree name,
++				 tree /* args */,
++				 int /* flags */,
++				 bool *no_add_attrs)
++{
++  tree decl = NULL_TREE, fntype = NULL_TREE;
++  tree type;
++
++  if (!use_cmse)
++    {
++      *no_add_attrs = true;
++      warning (OPT_Wattributes, "%qE attribute ignored without -mcmse option.",
++	       name);
++      return NULL_TREE;
++    }
++
++  if (TREE_CODE (*node) == VAR_DECL || TREE_CODE (*node) == TYPE_DECL)
++    {
++      decl = *node;
++      fntype = TREE_TYPE (decl);
++    }
++
++  while (fntype != NULL_TREE && TREE_CODE (fntype) == POINTER_TYPE)
++    fntype = TREE_TYPE (fntype);
++
++  if (!decl || TREE_CODE (fntype) != FUNCTION_TYPE)
++    {
++	warning (OPT_Wattributes, "%qE attribute only applies to base type of a "
++		 "function pointer", name);
++	*no_add_attrs = true;
++	return NULL_TREE;
++    }
++
++  *no_add_attrs |= cmse_func_args_or_return_in_stack (NULL, name, fntype);
++
++  if (*no_add_attrs)
++    return NULL_TREE;
++
++  /* Prevent trees being shared among function types with and without
++     cmse_nonsecure_call attribute.  */
++  type = TREE_TYPE (decl);
++
++  type = build_distinct_type_copy (type);
++  TREE_TYPE (decl) = type;
++  fntype = type;
++
++  while (TREE_CODE (fntype) != FUNCTION_TYPE)
++    {
++      type = fntype;
++      fntype = TREE_TYPE (fntype);
++      fntype = build_distinct_type_copy (fntype);
++      TREE_TYPE (type) = fntype;
++    }
++
++  /* Construct a type attribute and add it to the function type.  */
++  tree attrs = tree_cons (get_identifier ("cmse_nonsecure_call"), NULL_TREE,
++			  TYPE_ATTRIBUTES (fntype));
++  TYPE_ATTRIBUTES (fntype) = attrs;
++  return NULL_TREE;
++}
++
+ /* Return 0 if the attributes for two types are incompatible, 1 if they
+    are compatible, and 2 if they are nearly compatible (which causes a
+    warning to be generated).  */
+@@ -6642,6 +6917,14 @@ arm_comp_type_attributes (const_tree type1, const_tree type2)
+   if (l1 != l2)
+     return 0;
+ 
++  l1 = lookup_attribute ("cmse_nonsecure_call",
++			 TYPE_ATTRIBUTES (type1)) != NULL;
++  l2 = lookup_attribute ("cmse_nonsecure_call",
++			 TYPE_ATTRIBUTES (type2)) != NULL;
++
++  if (l1 != l2)
++    return 0;
++
+   return 1;
+ }
+ 
+@@ -6752,7 +7035,7 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
+      may be used both as target of the call and base register for restoring
+      the VFP registers  */
+   if (TARGET_APCS_FRAME && TARGET_ARM
+-      && TARGET_HARD_FLOAT && TARGET_VFP
++      && TARGET_HARD_FLOAT
+       && decl && arm_is_long_call_p (decl))
+     return false;
+ 
+@@ -6768,6 +7051,20 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
+   if (IS_INTERRUPT (func_type))
+     return false;
+ 
++  /* ARMv8-M non-secure entry functions need to return with bxns which is only
++     generated for entry functions themselves.  */
++  if (IS_CMSE_ENTRY (arm_current_func_type ()))
++    return false;
++
++  /* We do not allow ARMv8-M non-secure calls to be turned into sibling calls,
++     this would complicate matters for later code generation.  */
++  if (TREE_CODE (exp) == CALL_EXPR)
++    {
++      tree fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
++      if (lookup_attribute ("cmse_nonsecure_call", TYPE_ATTRIBUTES (fntype)))
++	return false;
++    }
++
+   if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
+     {
+       /* Check that the return value locations are the same.  For
+@@ -7228,8 +7525,7 @@ arm_legitimate_address_outer_p (machine_mode mode, rtx x, RTX_CODE outer,
+     return 1;
+ 
+   use_ldrd = (TARGET_LDRD
+-	      && (mode == DImode
+-		  || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
++	      && (mode == DImode || mode == DFmode));
+ 
+   if (code == POST_INC || code == PRE_DEC
+       || ((code == PRE_INC || code == POST_DEC)
+@@ -7303,6 +7599,32 @@ arm_legitimate_address_outer_p (machine_mode mode, rtx x, RTX_CODE outer,
+   return 0;
+ }
+ 
++/* Return true if we can avoid creating a constant pool entry for x.  */
++static bool
++can_avoid_literal_pool_for_label_p (rtx x)
++{
++  /* Normally we can assign constant values to target registers without
++     the help of constant pool.  But there are cases we have to use constant
++     pool like:
++     1) assign a label to register.
++     2) sign-extend a 8bit value to 32bit and then assign to register.
++
++     Constant pool access in format:
++     (set (reg r0) (mem (symbol_ref (".LC0"))))
++     will cause the use of literal pool (later in function arm_reorg).
++     So here we mark such format as an invalid format, then the compiler
++     will adjust it into:
++     (set (reg r0) (symbol_ref (".LC0")))
++     (set (reg r0) (mem (reg r0))).
++     No extra register is required, and (mem (reg r0)) won't cause the use
++     of literal pools.  */
++  if (arm_disable_literal_pool && GET_CODE (x) == SYMBOL_REF
++      && CONSTANT_POOL_ADDRESS_P (x))
++    return 1;
++  return 0;
++}
++
++
+ /* Return nonzero if X is a valid Thumb-2 address operand.  */
+ static int
+ thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
+@@ -7314,8 +7636,7 @@ thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
+     return 1;
+ 
+   use_ldrd = (TARGET_LDRD
+-	      && (mode == DImode
+-		  || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
++	      && (mode == DImode || mode == DFmode));
+ 
+   if (code == POST_INC || code == PRE_DEC
+       || ((code == PRE_INC || code == POST_DEC)
+@@ -7367,23 +7688,7 @@ thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
+ 		  && thumb2_legitimate_index_p (mode, xop0, strict_p)));
+     }
+ 
+-  /* Normally we can assign constant values to target registers without
+-     the help of constant pool.  But there are cases we have to use constant
+-     pool like:
+-     1) assign a label to register.
+-     2) sign-extend a 8bit value to 32bit and then assign to register.
+-
+-     Constant pool access in format:
+-     (set (reg r0) (mem (symbol_ref (".LC0"))))
+-     will cause the use of literal pool (later in function arm_reorg).
+-     So here we mark such format as an invalid format, then the compiler
+-     will adjust it into:
+-     (set (reg r0) (symbol_ref (".LC0")))
+-     (set (reg r0) (mem (reg r0))).
+-     No extra register is required, and (mem (reg r0)) won't cause the use
+-     of literal pools.  */
+-  else if (arm_disable_literal_pool && code == SYMBOL_REF
+-	   && CONSTANT_POOL_ADDRESS_P (x))
++  else if (can_avoid_literal_pool_for_label_p (x))
+     return 0;
+ 
+   else if (GET_MODE_CLASS (mode) != MODE_FLOAT
+@@ -7408,7 +7713,6 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
+ 
+   /* Standard coprocessor addressing modes.  */
+   if (TARGET_HARD_FLOAT
+-      && TARGET_VFP
+       && (mode == SFmode || mode == DFmode))
+     return (code == CONST_INT && INTVAL (index) < 1024
+ 	    && INTVAL (index) > -1024
+@@ -7528,7 +7832,6 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
+   /* ??? Combine arm and thumb2 coprocessor addressing modes.  */
+   /* Standard coprocessor addressing modes.  */
+   if (TARGET_HARD_FLOAT
+-      && TARGET_VFP
+       && (mode == SFmode || mode == DFmode))
+     return (code == CONST_INT && INTVAL (index) < 1024
+ 	    /* Thumb-2 allows only > -256 index range for it's core register
+@@ -7664,6 +7967,9 @@ thumb1_index_register_rtx_p (rtx x, int strict_p)
+ int
+ thumb1_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
+ {
++  if (TARGET_HAVE_MOVT && can_avoid_literal_pool_for_label_p (x))
++    return 0;
++
+   /* ??? Not clear if this is right.  Experiment.  */
+   if (GET_MODE_SIZE (mode) < 4
+       && !(reload_in_progress || reload_completed)
+@@ -8074,8 +8380,7 @@ arm_legitimize_address (rtx x, rtx orig_x, machine_mode mode)
+ 
+ 	  /* VFP addressing modes actually allow greater offsets, but for
+ 	     now we just stick with the lowest common denominator.  */
+-	  if (mode == DImode
+-	      || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
++	  if (mode == DImode || mode == DFmode)
+ 	    {
+ 	      low_n = n & 0x0f;
+ 	      n &= ~0x0f;
+@@ -8240,7 +8545,16 @@ arm_tls_referenced_p (rtx x)
+     {
+       const_rtx x = *iter;
+       if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
+-	return true;
++	{
++	  /* ARM currently does not provide relocations to encode TLS variables
++	     into AArch32 instructions, only data, so there is no way to
++	     currently implement these if a literal pool is disabled.  */
++	  if (arm_disable_literal_pool)
++	    sorry ("accessing thread-local storage is not currently supported "
++		   "with -mpure-code or -mslow-flash-data");
++
++	  return true;
++	}
+ 
+       /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
+ 	 TLS offsets, not real symbol references.  */
+@@ -8267,9 +8581,16 @@ arm_legitimate_constant_p_1 (machine_mode, rtx x)
+ static bool
+ thumb_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
+ {
++  /* Splitters for TARGET_USE_MOVT call arm_emit_movpair which creates high
++     RTX.  These RTX must therefore be allowed for Thumb-1 so that when run
++     for ARMv8-M Baseline or later the result is valid.  */
++  if (TARGET_HAVE_MOVT && GET_CODE (x) == HIGH)
++    x = XEXP (x, 0);
++
+   return (CONST_INT_P (x)
+ 	  || CONST_DOUBLE_P (x)
+ 	  || CONSTANT_ADDRESS_P (x)
++	  || (TARGET_HAVE_MOVT && GET_CODE (x) == SYMBOL_REF)
+ 	  || flag_pic);
+ }
+ 
+@@ -8328,6 +8649,9 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+       return COSTS_N_INSNS (1);
+ 
+     case MULT:
++      if (arm_arch6m && arm_m_profile_small_mul)
++	return COSTS_N_INSNS (32);
++
+       if (CONST_INT_P (XEXP (x, 1)))
+ 	{
+ 	  int cycles = 0;
+@@ -8353,7 +8677,9 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+     case CONST_INT:
+       if (outer == SET)
+ 	{
+-	  if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
++	  if (UINTVAL (x) < 256
++	      /* 16-bit constant.  */
++	      || (TARGET_HAVE_MOVT && !(INTVAL (x) & 0xffff0000)))
+ 	    return 0;
+ 	  if (thumb_shiftable_const (INTVAL (x)))
+ 	    return COSTS_N_INSNS (2);
+@@ -8370,8 +8696,8 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+ 	  int i;
+ 	  /* This duplicates the tests in the andsi3 expander.  */
+ 	  for (i = 9; i <= 31; i++)
+-	    if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (x)
+-		|| (((HOST_WIDE_INT) 1) << i) - 1 == ~INTVAL (x))
++	    if ((HOST_WIDE_INT_1 << i) - 1 == INTVAL (x)
++		|| (HOST_WIDE_INT_1 << i) - 1 == ~INTVAL (x))
+ 	      return COSTS_N_INSNS (2);
+ 	}
+       else if (outer == ASHIFT || outer == ASHIFTRT
+@@ -8434,639 +8760,24 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+     }
+ }
+ 
+-static inline bool
+-arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
++/* Estimates the size cost of thumb1 instructions.
++   For now most of the code is copied from thumb1_rtx_costs. We need more
++   fine grain tuning when we have more related test cases.  */
++static inline int
++thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+ {
+   machine_mode mode = GET_MODE (x);
+-  enum rtx_code subcode;
+-  rtx operand;
+-  enum rtx_code code = GET_CODE (x);
+-  *total = 0;
++  int words, cost;
+ 
+   switch (code)
+     {
+-    case MEM:
+-      /* Memory costs quite a lot for the first word, but subsequent words
+-	 load at the equivalent of a single insn each.  */
+-      *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode));
+-      return true;
+-
+-    case DIV:
+-    case MOD:
+-    case UDIV:
+-    case UMOD:
+-      if (TARGET_HARD_FLOAT && mode == SFmode)
+-	*total = COSTS_N_INSNS (2);
+-      else if (TARGET_HARD_FLOAT && mode == DFmode && !TARGET_VFP_SINGLE)
+-	*total = COSTS_N_INSNS (4);
+-      else
+-	*total = COSTS_N_INSNS (20);
+-      return false;
+-
+-    case ROTATE:
+-      if (REG_P (XEXP (x, 1)))
+-	*total = COSTS_N_INSNS (1); /* Need to subtract from 32 */
+-      else if (!CONST_INT_P (XEXP (x, 1)))
+-	*total = rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-
+-      /* Fall through */
++    case ASHIFT:
++    case ASHIFTRT:
++    case LSHIFTRT:
+     case ROTATERT:
+-      if (mode != SImode)
+-	{
+-	  *total += COSTS_N_INSNS (4);
+-	  return true;
+-	}
+-
+-      /* Fall through */
+-    case ASHIFT: case LSHIFTRT: case ASHIFTRT:
+-      *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-      if (mode == DImode)
+-	{
+-	  *total += COSTS_N_INSNS (3);
+-	  return true;
+-	}
+-
+-      *total += COSTS_N_INSNS (1);
+-      /* Increase the cost of complex shifts because they aren't any faster,
+-         and reduce dual issue opportunities.  */
+-      if (arm_tune_cortex_a9
+-	  && outer != SET && !CONST_INT_P (XEXP (x, 1)))
+-	++*total;
+-
+-      return true;
++      return (mode == SImode) ? COSTS_N_INSNS (1) : COSTS_N_INSNS (2);
+ 
+-    case MINUS:
+-      if (mode == DImode)
+-	{
+-	  *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-	  if (CONST_INT_P (XEXP (x, 0))
+-	      && const_ok_for_arm (INTVAL (XEXP (x, 0))))
+-	    {
+-	      *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	      return true;
+-	    }
+-
+-	  if (CONST_INT_P (XEXP (x, 1))
+-	      && const_ok_for_arm (INTVAL (XEXP (x, 1))))
+-	    {
+-	      *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-	      return true;
+-	    }
+-
+-	  return false;
+-	}
+-
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+-	{
+-	  if (TARGET_HARD_FLOAT
+-	      && (mode == SFmode
+-		  || (mode == DFmode && !TARGET_VFP_SINGLE)))
+-	    {
+-	      *total = COSTS_N_INSNS (1);
+-	      if (CONST_DOUBLE_P (XEXP (x, 0))
+-		  && arm_const_double_rtx (XEXP (x, 0)))
+-		{
+-		  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-		  return true;
+-		}
+-
+-	      if (CONST_DOUBLE_P (XEXP (x, 1))
+-		  && arm_const_double_rtx (XEXP (x, 1)))
+-		{
+-		  *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-		  return true;
+-		}
+-
+-	      return false;
+-	    }
+-	  *total = COSTS_N_INSNS (20);
+-	  return false;
+-	}
+-
+-      *total = COSTS_N_INSNS (1);
+-      if (CONST_INT_P (XEXP (x, 0))
+-	  && const_ok_for_arm (INTVAL (XEXP (x, 0))))
+-	{
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  return true;
+-	}
+-
+-      subcode = GET_CODE (XEXP (x, 1));
+-      if (subcode == ASHIFT || subcode == ASHIFTRT
+-	  || subcode == LSHIFTRT
+-	  || subcode == ROTATE || subcode == ROTATERT)
+-	{
+-	  *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-	  *total += rtx_cost (XEXP (XEXP (x, 1), 0), mode, subcode, 0, speed);
+-	  return true;
+-	}
+-
+-      /* A shift as a part of RSB costs no more than RSB itself.  */
+-      if (GET_CODE (XEXP (x, 0)) == MULT
+-	  && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
+-	{
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, code, 0, speed);
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  return true;
+-	}
+-
+-      if (subcode == MULT
+-	  && power_of_two_operand (XEXP (XEXP (x, 1), 1), SImode))
+-	{
+-	  *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-	  *total += rtx_cost (XEXP (XEXP (x, 1), 0), mode, subcode, 0, speed);
+-	  return true;
+-	}
+-
+-      if (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMPARE
+-	  || GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMM_COMPARE)
+-	{
+-	  *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, speed);
+-	  if (REG_P (XEXP (XEXP (x, 1), 0))
+-	      && REGNO (XEXP (XEXP (x, 1), 0)) != CC_REGNUM)
+-	    *total += COSTS_N_INSNS (1);
+-
+-	  return true;
+-	}
+-
+-      /* Fall through */
+-
+-    case PLUS:
+-      if (code == PLUS && arm_arch6 && mode == SImode
+-	  && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+-	      || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
+-	{
+-	  *total = COSTS_N_INSNS (1);
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), VOIDmode,
+-			      GET_CODE (XEXP (x, 0)), 0, speed);
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  return true;
+-	}
+-
+-      /* MLA: All arguments must be registers.  We filter out
+-	 multiplication by a power of two, so that we fall down into
+-	 the code below.  */
+-      if (GET_CODE (XEXP (x, 0)) == MULT
+-	  && !power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
+-	{
+-	  /* The cost comes from the cost of the multiply.  */
+-	  return false;
+-	}
+-
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+-	{
+-	  if (TARGET_HARD_FLOAT
+-	      && (mode == SFmode
+-		  || (mode == DFmode && !TARGET_VFP_SINGLE)))
+-	    {
+-	      *total = COSTS_N_INSNS (1);
+-	      if (CONST_DOUBLE_P (XEXP (x, 1))
+-		  && arm_const_double_rtx (XEXP (x, 1)))
+-		{
+-		  *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-		  return true;
+-		}
+-
+-	      return false;
+-	    }
+-
+-	  *total = COSTS_N_INSNS (20);
+-	  return false;
+-	}
+-
+-      if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMPARE
+-	  || GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMM_COMPARE)
+-	{
+-	  *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 1), mode, code,
+-						 1, speed);
+-	  if (REG_P (XEXP (XEXP (x, 0), 0))
+-	      && REGNO (XEXP (XEXP (x, 0), 0)) != CC_REGNUM)
+-	    *total += COSTS_N_INSNS (1);
+-	  return true;
+-	}
+-
+-      /* Fall through */
+-
+-    case AND: case XOR: case IOR:
+-
+-      /* Normally the frame registers will be spilt into reg+const during
+-	 reload, so it is a bad idea to combine them with other instructions,
+-	 since then they might not be moved outside of loops.  As a compromise
+-	 we allow integration with ops that have a constant as their second
+-	 operand.  */
+-      if (REG_OR_SUBREG_REG (XEXP (x, 0))
+-	  && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
+-	  && !CONST_INT_P (XEXP (x, 1)))
+-	*total = COSTS_N_INSNS (1);
+-
+-      if (mode == DImode)
+-	{
+-	  *total += COSTS_N_INSNS (2);
+-	  if (CONST_INT_P (XEXP (x, 1))
+-	      && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
+-	    {
+-	      *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-	      return true;
+-	    }
+-
+-	  return false;
+-	}
+-
+-      *total += COSTS_N_INSNS (1);
+-      if (CONST_INT_P (XEXP (x, 1))
+-	  && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
+-	{
+-	  *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-	  return true;
+-	}
+-      subcode = GET_CODE (XEXP (x, 0));
+-      if (subcode == ASHIFT || subcode == ASHIFTRT
+-	  || subcode == LSHIFTRT
+-	  || subcode == ROTATE || subcode == ROTATERT)
+-	{
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, subcode, 0, speed);
+-	  return true;
+-	}
+-
+-      if (subcode == MULT
+-	  && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
+-	{
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, subcode, 0, speed);
+-	  return true;
+-	}
+-
+-      if (subcode == UMIN || subcode == UMAX
+-	  || subcode == SMIN || subcode == SMAX)
+-	{
+-	  *total = COSTS_N_INSNS (3);
+-	  return true;
+-	}
+-
+-      return false;
+-
+-    case MULT:
+-      /* This should have been handled by the CPU specific routines.  */
+-      gcc_unreachable ();
+-
+-    case TRUNCATE:
+-      if (arm_arch3m && mode == SImode
+-	  && GET_CODE (XEXP (x, 0)) == LSHIFTRT
+-	  && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
+-	  && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
+-	      == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
+-	  && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
+-	      || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
+-	{
+-	  *total = rtx_cost (XEXP (XEXP (x, 0), 0), VOIDmode, LSHIFTRT,
+-			     0, speed);
+-	  return true;
+-	}
+-      *total = COSTS_N_INSNS (2); /* Plus the cost of the MULT */
+-      return false;
+-
+-    case NEG:
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+-	{
+-	  if (TARGET_HARD_FLOAT
+-	      && (mode == SFmode
+-		  || (mode == DFmode && !TARGET_VFP_SINGLE)))
+-	    {
+-	      *total = COSTS_N_INSNS (1);
+-	      return false;
+-	    }
+-	  *total = COSTS_N_INSNS (2);
+-	  return false;
+-	}
+-
+-      /* Fall through */
+-    case NOT:
+-      *total = COSTS_N_INSNS (ARM_NUM_REGS(mode));
+-      if (mode == SImode && code == NOT)
+-	{
+-	  subcode = GET_CODE (XEXP (x, 0));
+-	  if (subcode == ASHIFT || subcode == ASHIFTRT
+-	      || subcode == LSHIFTRT
+-	      || subcode == ROTATE || subcode == ROTATERT
+-	      || (subcode == MULT
+-		  && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)))
+-	    {
+-	      *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, subcode,
+-				  0, speed);
+-	      /* Register shifts cost an extra cycle.  */
+-	      if (!CONST_INT_P (XEXP (XEXP (x, 0), 1)))
+-		*total += COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x, 0), 1),
+-							mode, subcode,
+-							1, speed);
+-	      return true;
+-	    }
+-	}
+-
+-      return false;
+-
+-    case IF_THEN_ELSE:
+-      if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
+-	{
+-	  *total = COSTS_N_INSNS (4);
+-	  return true;
+-	}
+-
+-      operand = XEXP (x, 0);
+-
+-      if (!((GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMPARE
+-	     || GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMM_COMPARE)
+-	    && REG_P (XEXP (operand, 0))
+-	    && REGNO (XEXP (operand, 0)) == CC_REGNUM))
+-	*total += COSTS_N_INSNS (1);
+-      *total += rtx_cost (XEXP (x, 1), VOIDmode, code, 1, speed);
+-      *total += rtx_cost (XEXP (x, 2), VOIDmode, code, 2, speed);
+-      return true;
+-
+-    case NE:
+-      if (mode == SImode && XEXP (x, 1) == const0_rtx)
+-	{
+-	  *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, speed);
+-	  return true;
+-	}
+-      goto scc_insn;
+-
+-    case GE:
+-      if ((!REG_P (XEXP (x, 0)) || REGNO (XEXP (x, 0)) != CC_REGNUM)
+-	  && mode == SImode && XEXP (x, 1) == const0_rtx)
+-	{
+-	  *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, speed);
+-	  return true;
+-	}
+-      goto scc_insn;
+-
+-    case LT:
+-      if ((!REG_P (XEXP (x, 0)) || REGNO (XEXP (x, 0)) != CC_REGNUM)
+-	  && mode == SImode && XEXP (x, 1) == const0_rtx)
+-	{
+-	  *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, speed);
+-	  return true;
+-	}
+-      goto scc_insn;
+-
+-    case EQ:
+-    case GT:
+-    case LE:
+-    case GEU:
+-    case LTU:
+-    case GTU:
+-    case LEU:
+-    case UNORDERED:
+-    case ORDERED:
+-    case UNEQ:
+-    case UNGE:
+-    case UNLT:
+-    case UNGT:
+-    case UNLE:
+-    scc_insn:
+-      /* SCC insns.  In the case where the comparison has already been
+-	 performed, then they cost 2 instructions.  Otherwise they need
+-	 an additional comparison before them.  */
+-      *total = COSTS_N_INSNS (2);
+-      if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == CC_REGNUM)
+-	{
+-	  return true;
+-	}
+-
+-      /* Fall through */
+-    case COMPARE:
+-      if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == CC_REGNUM)
+-	{
+-	  *total = 0;
+-	  return true;
+-	}
+-
+-      *total += COSTS_N_INSNS (1);
+-      if (CONST_INT_P (XEXP (x, 1))
+-	  && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
+-	{
+-	  *total += rtx_cost (XEXP (x, 0), VOIDmode, code, 0, speed);
+-	  return true;
+-	}
+-
+-      subcode = GET_CODE (XEXP (x, 0));
+-      if (subcode == ASHIFT || subcode == ASHIFTRT
+-	  || subcode == LSHIFTRT
+-	  || subcode == ROTATE || subcode == ROTATERT)
+-	{
+-	  mode = GET_MODE (XEXP (x, 0));
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, subcode, 0, speed);
+-	  return true;
+-	}
+-
+-      if (subcode == MULT
+-	  && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
+-	{
+-	  mode = GET_MODE (XEXP (x, 0));
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, subcode, 0, speed);
+-	  return true;
+-	}
+-
+-      return false;
+-
+-    case UMIN:
+-    case UMAX:
+-    case SMIN:
+-    case SMAX:
+-      *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-      if (!CONST_INT_P (XEXP (x, 1))
+-	  || !const_ok_for_arm (INTVAL (XEXP (x, 1))))
+-	*total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+-      return true;
+-
+-    case ABS:
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+-	{
+-	  if (TARGET_HARD_FLOAT
+-	      && (mode == SFmode
+-		  || (mode == DFmode && !TARGET_VFP_SINGLE)))
+-	    {
+-	      *total = COSTS_N_INSNS (1);
+-	      return false;
+-	    }
+-	  *total = COSTS_N_INSNS (20);
+-	  return false;
+-	}
+-      *total = COSTS_N_INSNS (1);
+-      if (mode == DImode)
+-	*total += COSTS_N_INSNS (3);
+-      return false;
+-
+-    case SIGN_EXTEND:
+-    case ZERO_EXTEND:
+-      *total = 0;
+-      if (GET_MODE_CLASS (mode) == MODE_INT)
+-	{
+-	  rtx op = XEXP (x, 0);
+-	  machine_mode opmode = GET_MODE (op);
+-
+-	  if (mode == DImode)
+-	    *total += COSTS_N_INSNS (1);
+-
+-	  if (opmode != SImode)
+-	    {
+-	      if (MEM_P (op))
+-		{
+-		  /* If !arm_arch4, we use one of the extendhisi2_mem
+-		     or movhi_bytes patterns for HImode.  For a QImode
+-		     sign extension, we first zero-extend from memory
+-		     and then perform a shift sequence.  */
+-		  if (!arm_arch4 && (opmode != QImode || code == SIGN_EXTEND))
+-		    *total += COSTS_N_INSNS (2);
+-		}
+-	      else if (arm_arch6)
+-		*total += COSTS_N_INSNS (1);
+-
+-	      /* We don't have the necessary insn, so we need to perform some
+-		 other operation.  */
+-	      else if (TARGET_ARM && code == ZERO_EXTEND && mode == QImode)
+-		/* An and with constant 255.  */
+-		*total += COSTS_N_INSNS (1);
+-	      else
+-		/* A shift sequence.  Increase costs slightly to avoid
+-		   combining two shifts into an extend operation.  */
+-		*total += COSTS_N_INSNS (2) + 1;
+-	    }
+-
+-	  return false;
+-	}
+-
+-      switch (GET_MODE (XEXP (x, 0)))
+-	{
+-	case V8QImode:
+-	case V4HImode:
+-	case V2SImode:
+-	case V4QImode:
+-	case V2HImode:
+-	  *total = COSTS_N_INSNS (1);
+-	  return false;
+-
+-	default:
+-	  gcc_unreachable ();
+-	}
+-      gcc_unreachable ();
+-
+-    case ZERO_EXTRACT:
+-    case SIGN_EXTRACT:
+-      mode = GET_MODE (XEXP (x, 0));
+-      *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-      return true;
+-
+-    case CONST_INT:
+-      if (const_ok_for_arm (INTVAL (x))
+-	  || const_ok_for_arm (~INTVAL (x)))
+-	*total = COSTS_N_INSNS (1);
+-      else
+-	*total = COSTS_N_INSNS (arm_gen_constant (SET, mode, NULL_RTX,
+-						  INTVAL (x), NULL_RTX,
+-						  NULL_RTX, 0, 0));
+-      return true;
+-
+-    case CONST:
+-    case LABEL_REF:
+-    case SYMBOL_REF:
+-      *total = COSTS_N_INSNS (3);
+-      return true;
+-
+-    case HIGH:
+-      *total = COSTS_N_INSNS (1);
+-      return true;
+-
+-    case LO_SUM:
+-      *total = COSTS_N_INSNS (1);
+-      *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-      return true;
+-
+-    case CONST_DOUBLE:
+-      if (TARGET_HARD_FLOAT && vfp3_const_double_rtx (x)
+-	  && (mode == SFmode || !TARGET_VFP_SINGLE))
+-	*total = COSTS_N_INSNS (1);
+-      else
+-	*total = COSTS_N_INSNS (4);
+-      return true;
+-
+-    case SET:
+-      /* The vec_extract patterns accept memory operands that require an
+-	 address reload.  Account for the cost of that reload to give the
+-	 auto-inc-dec pass an incentive to try to replace them.  */
+-      if (TARGET_NEON && MEM_P (SET_DEST (x))
+-	  && GET_CODE (SET_SRC (x)) == VEC_SELECT)
+-	{
+-	  mode = GET_MODE (SET_DEST (x));
+-	  *total = rtx_cost (SET_DEST (x), mode, code, 0, speed);
+-	  if (!neon_vector_mem_operand (SET_DEST (x), 2, true))
+-	    *total += COSTS_N_INSNS (1);
+-	  return true;
+-	}
+-      /* Likewise for the vec_set patterns.  */
+-      if (TARGET_NEON && GET_CODE (SET_SRC (x)) == VEC_MERGE
+-	  && GET_CODE (XEXP (SET_SRC (x), 0)) == VEC_DUPLICATE
+-	  && MEM_P (XEXP (XEXP (SET_SRC (x), 0), 0)))
+-	{
+-	  rtx mem = XEXP (XEXP (SET_SRC (x), 0), 0);
+-	  mode = GET_MODE (SET_DEST (x));
+-	  *total = rtx_cost (mem, mode, code, 0, speed);
+-	  if (!neon_vector_mem_operand (mem, 2, true))
+-	    *total += COSTS_N_INSNS (1);
+-	  return true;
+-	}
+-      return false;
+-
+-    case UNSPEC:
+-      /* We cost this as high as our memory costs to allow this to
+-	 be hoisted from loops.  */
+-      if (XINT (x, 1) == UNSPEC_PIC_UNIFIED)
+-	{
+-	  *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode));
+-	}
+-      return true;
+-
+-    case CONST_VECTOR:
+-      if (TARGET_NEON
+-	  && TARGET_HARD_FLOAT
+-	  && outer == SET
+-	  && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
+-	  && neon_immediate_valid_for_move (x, mode, NULL, NULL))
+-	*total = COSTS_N_INSNS (1);
+-      else
+-	*total = COSTS_N_INSNS (4);
+-      return true;
+-
+-    default:
+-      *total = COSTS_N_INSNS (4);
+-      return false;
+-    }
+-}
+-
+-/* Estimates the size cost of thumb1 instructions.
+-   For now most of the code is copied from thumb1_rtx_costs. We need more
+-   fine grain tuning when we have more related test cases.  */
+-static inline int
+-thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+-{
+-  machine_mode mode = GET_MODE (x);
+-  int words;
+-
+-  switch (code)
+-    {
+-    case ASHIFT:
+-    case ASHIFTRT:
+-    case LSHIFTRT:
+-    case ROTATERT:
+-      return (mode == SImode) ? COSTS_N_INSNS (1) : COSTS_N_INSNS (2);
+-
+-    case PLUS:
++    case PLUS:
+     case MINUS:
+       /* Thumb-1 needs two instructions to fulfill shiftadd/shiftsub0/shiftsub1
+ 	 defined by RTL expansion, especially for the expansion of
+@@ -9102,17 +8813,27 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+       /* A SET doesn't have a mode, so let's look at the SET_DEST to get
+ 	 the mode.  */
+       words = ARM_NUM_INTS (GET_MODE_SIZE (GET_MODE (SET_DEST (x))));
+-      return COSTS_N_INSNS (words)
+-	     + COSTS_N_INSNS (1) * (satisfies_constraint_J (SET_SRC (x))
+-				    || satisfies_constraint_K (SET_SRC (x))
+-				       /* thumb1_movdi_insn.  */
+-				    || ((words > 1) && MEM_P (SET_SRC (x))));
++      cost = COSTS_N_INSNS (words);
++      if (satisfies_constraint_J (SET_SRC (x))
++	  || satisfies_constraint_K (SET_SRC (x))
++	     /* Too big an immediate for a 2-byte mov, using MOVT.  */
++	  || (CONST_INT_P (SET_SRC (x))
++	      && UINTVAL (SET_SRC (x)) >= 256
++	      && TARGET_HAVE_MOVT
++	      && satisfies_constraint_j (SET_SRC (x)))
++	     /* thumb1_movdi_insn.  */
++	  || ((words > 1) && MEM_P (SET_SRC (x))))
++	cost += COSTS_N_INSNS (1);
++      return cost;
+ 
+     case CONST_INT:
+       if (outer == SET)
+         {
+-          if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
++          if (UINTVAL (x) < 256)
+             return COSTS_N_INSNS (1);
++	  /* movw is 4byte long.  */
++	  if (TARGET_HAVE_MOVT && !(INTVAL (x) & 0xffff0000))
++	    return COSTS_N_INSNS (2);
+ 	  /* See split "TARGET_THUMB1 && satisfies_constraint_J".  */
+ 	  if (INTVAL (x) >= -255 && INTVAL (x) <= -1)
+             return COSTS_N_INSNS (2);
+@@ -9132,8 +8853,8 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+           int i;
+           /* This duplicates the tests in the andsi3 expander.  */
+           for (i = 9; i <= 31; i++)
+-            if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (x)
+-                || (((HOST_WIDE_INT) 1) << i) - 1 == ~INTVAL (x))
++            if ((HOST_WIDE_INT_1 << i) - 1 == INTVAL (x)
++                || (HOST_WIDE_INT_1 << i) - 1 == ~INTVAL (x))
+               return COSTS_N_INSNS (2);
+         }
+       else if (outer == ASHIFT || outer == ASHIFTRT
+@@ -9161,279 +8882,40 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+     case IOR:
+       return COSTS_N_INSNS (1);
+ 
+-    case MEM:
+-      return (COSTS_N_INSNS (1)
+-	      + COSTS_N_INSNS (1)
+-		* ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
+-              + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
+-                 ? COSTS_N_INSNS (1) : 0));
+-
+-    case IF_THEN_ELSE:
+-      /* XXX a guess.  */
+-      if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
+-        return 14;
+-      return 2;
+-
+-    case ZERO_EXTEND:
+-      /* XXX still guessing.  */
+-      switch (GET_MODE (XEXP (x, 0)))
+-        {
+-          case QImode:
+-            return (1 + (mode == DImode ? 4 : 0)
+-                    + (MEM_P (XEXP (x, 0)) ? 10 : 0));
+-
+-          case HImode:
+-            return (4 + (mode == DImode ? 4 : 0)
+-                    + (MEM_P (XEXP (x, 0)) ? 10 : 0));
+-
+-          case SImode:
+-            return (1 + (MEM_P (XEXP (x, 0)) ? 10 : 0));
+-
+-          default:
+-            return 99;
+-        }
+-
+-    default:
+-      return 99;
+-    }
+-}
+-
+-/* RTX costs when optimizing for size.  */
+-static bool
+-arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+-		    int *total)
+-{
+-  machine_mode mode = GET_MODE (x);
+-  if (TARGET_THUMB1)
+-    {
+-      *total = thumb1_size_rtx_costs (x, code, outer_code);
+-      return true;
+-    }
+-
+-  /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions.  */
+-  switch (code)
+-    {
+-    case MEM:
+-      /* A memory access costs 1 insn if the mode is small, or the address is
+-	 a single register, otherwise it costs one insn per word.  */
+-      if (REG_P (XEXP (x, 0)))
+-	*total = COSTS_N_INSNS (1);
+-      else if (flag_pic
+-	       && GET_CODE (XEXP (x, 0)) == PLUS
+-	       && will_be_in_index_register (XEXP (XEXP (x, 0), 1)))
+-	/* This will be split into two instructions.
+-	   See arm.md:calculate_pic_address.  */
+-	*total = COSTS_N_INSNS (2);
+-      else
+-	*total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-      return true;
+-
+-    case DIV:
+-    case MOD:
+-    case UDIV:
+-    case UMOD:
+-      /* Needs a libcall, so it costs about this.  */
+-      *total = COSTS_N_INSNS (2);
+-      return false;
+-
+-    case ROTATE:
+-      if (mode == SImode && REG_P (XEXP (x, 1)))
+-	{
+-	  *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, false);
+-	  return true;
+-	}
+-      /* Fall through */
+-    case ROTATERT:
+-    case ASHIFT:
+-    case LSHIFTRT:
+-    case ASHIFTRT:
+-      if (mode == DImode && CONST_INT_P (XEXP (x, 1)))
+-	{
+-	  *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, false);
+-	  return true;
+-	}
+-      else if (mode == SImode)
+-	{
+-	  *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), mode, code,
+-						 0, false);
+-	  /* Slightly disparage register shifts, but not by much.  */
+-	  if (!CONST_INT_P (XEXP (x, 1)))
+-	    *total += 1 + rtx_cost (XEXP (x, 1), mode, code, 1, false);
+-	  return true;
+-	}
+-
+-      /* Needs a libcall.  */
+-      *total = COSTS_N_INSNS (2);
+-      return false;
+-
+-    case MINUS:
+-      if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
+-	  && (mode == SFmode || !TARGET_VFP_SINGLE))
+-	{
+-	  *total = COSTS_N_INSNS (1);
+-	  return false;
+-	}
+-
+-      if (mode == SImode)
+-	{
+-	  enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
+-	  enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
+-
+-	  if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
+-	      || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
+-	      || subcode1 == ROTATE || subcode1 == ROTATERT
+-	      || subcode1 == ASHIFT || subcode1 == LSHIFTRT
+-	      || subcode1 == ASHIFTRT)
+-	    {
+-	      /* It's just the cost of the two operands.  */
+-	      *total = 0;
+-	      return false;
+-	    }
+-
+-	  *total = COSTS_N_INSNS (1);
+-	  return false;
+-	}
+-
+-      *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-      return false;
+-
+-    case PLUS:
+-      if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
+-	  && (mode == SFmode || !TARGET_VFP_SINGLE))
+-	{
+-	  *total = COSTS_N_INSNS (1);
+-	  return false;
+-	}
+-
+-      /* A shift as a part of ADD costs nothing.  */
+-      if (GET_CODE (XEXP (x, 0)) == MULT
+-	  && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))
+-	{
+-	  *total = COSTS_N_INSNS (TARGET_THUMB2 ? 2 : 1);
+-	  *total += rtx_cost (XEXP (XEXP (x, 0), 0), mode, code, 0, false);
+-	  *total += rtx_cost (XEXP (x, 1), mode, code, 1, false);
+-	  return true;
+-	}
+-
+-      /* Fall through */
+-    case AND: case XOR: case IOR:
+-      if (mode == SImode)
+-	{
+-	  enum rtx_code subcode = GET_CODE (XEXP (x, 0));
+-
+-	  if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
+-	      || subcode == LSHIFTRT || subcode == ASHIFTRT
+-	      || (code == AND && subcode == NOT))
+-	    {
+-	      /* It's just the cost of the two operands.  */
+-	      *total = 0;
+-	      return false;
+-	    }
+-	}
+-
+-      *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-      return false;
+-
+-    case MULT:
+-      *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-      return false;
+-
+-    case NEG:
+-      if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
+-	  && (mode == SFmode || !TARGET_VFP_SINGLE))
+-	{
+-	  *total = COSTS_N_INSNS (1);
+-	  return false;
+-	}
+-
+-      /* Fall through */
+-    case NOT:
+-      *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-
+-      return false;
+-
+-    case IF_THEN_ELSE:
+-      *total = 0;
+-      return false;
+-
+-    case COMPARE:
+-      if (cc_register (XEXP (x, 0), VOIDmode))
+-	* total = 0;
+-      else
+-	*total = COSTS_N_INSNS (1);
+-      return false;
+-
+-    case ABS:
+-      if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
+-	  && (mode == SFmode || !TARGET_VFP_SINGLE))
+-	*total = COSTS_N_INSNS (1);
+-      else
+-	*total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
+-      return false;
+-
+-    case SIGN_EXTEND:
+-    case ZERO_EXTEND:
+-      return arm_rtx_costs_1 (x, outer_code, total, 0);
+-
+-    case CONST_INT:
+-      if (const_ok_for_arm (INTVAL (x)))
+-	/* A multiplication by a constant requires another instruction
+-	   to load the constant to a register.  */
+-	*total = COSTS_N_INSNS ((outer_code == SET || outer_code == MULT)
+-				? 1 : 0);
+-      else if (const_ok_for_arm (~INTVAL (x)))
+-	*total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
+-      else if (const_ok_for_arm (-INTVAL (x)))
+-	{
+-	  if (outer_code == COMPARE || outer_code == PLUS
+-	      || outer_code == MINUS)
+-	    *total = 0;
+-	  else
+-	    *total = COSTS_N_INSNS (1);
+-	}
+-      else
+-	*total = COSTS_N_INSNS (2);
+-      return true;
+-
+-    case CONST:
+-    case LABEL_REF:
+-    case SYMBOL_REF:
+-      *total = COSTS_N_INSNS (2);
+-      return true;
++    case MEM:
++      return (COSTS_N_INSNS (1)
++	      + COSTS_N_INSNS (1)
++		* ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
++              + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
++                 ? COSTS_N_INSNS (1) : 0));
+ 
+-    case CONST_DOUBLE:
+-      *total = COSTS_N_INSNS (4);
+-      return true;
++    case IF_THEN_ELSE:
++      /* XXX a guess.  */
++      if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
++        return 14;
++      return 2;
+ 
+-    case CONST_VECTOR:
+-      if (TARGET_NEON
+-	  && TARGET_HARD_FLOAT
+-	  && outer_code == SET
+-	  && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
+-	  && neon_immediate_valid_for_move (x, mode, NULL, NULL))
+-	*total = COSTS_N_INSNS (1);
+-      else
+-	*total = COSTS_N_INSNS (4);
+-      return true;
++    case ZERO_EXTEND:
++      /* XXX still guessing.  */
++      switch (GET_MODE (XEXP (x, 0)))
++        {
++          case QImode:
++            return (1 + (mode == DImode ? 4 : 0)
++                    + (MEM_P (XEXP (x, 0)) ? 10 : 0));
+ 
+-    case HIGH:
+-    case LO_SUM:
+-      /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
+-	 cost of these slightly.  */
+-      *total = COSTS_N_INSNS (1) + 1;
+-      return true;
++          case HImode:
++            return (4 + (mode == DImode ? 4 : 0)
++                    + (MEM_P (XEXP (x, 0)) ? 10 : 0));
+ 
+-    case SET:
+-      return false;
++          case SImode:
++            return (1 + (MEM_P (XEXP (x, 0)) ? 10 : 0));
++
++          default:
++            return 99;
++        }
+ 
+     default:
+-      if (mode != VOIDmode)
+-	*total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-      else
+-	*total = COSTS_N_INSNS (4); /* How knows?  */
+-      return false;
++      return 99;
+     }
+ }
+ 
+@@ -9560,7 +9042,7 @@ arm_unspec_cost (rtx x, enum rtx_code /* outer_code */, bool speed_p, int *cost)
+    flags are live or not, and thus no realistic way to determine what
+    the size will eventually be.  */
+ static bool
+-arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
++arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
+ 		   const struct cpu_cost_table *extra_cost,
+ 		   int *cost, bool speed_p)
+ {
+@@ -10812,8 +10294,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+       if ((arm_arch4 || GET_MODE (XEXP (x, 0)) == SImode)
+ 	  && MEM_P (XEXP (x, 0)))
+ 	{
+-	  *cost = rtx_cost (XEXP (x, 0), VOIDmode, code, 0, speed_p);
+-
+ 	  if (mode == DImode)
+ 	    *cost += COSTS_N_INSNS (1);
+ 
+@@ -11177,418 +10657,98 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+ 
+ 	      *cost += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0), mode,
+ 				 code, 0, speed_p);
+-	      return true;
+-	    }
+-
+-	  if (GET_MODE_CLASS (mode) == MODE_INT)
+-	    {
+-	      mode = GET_MODE (XEXP (x, 0));
+-	      if (speed_p)
+-		*cost += extra_cost->fp[mode == DFmode].toint;
+-	      /* Strip of the 'cost' of rounding towards zero.  */
+-	      if (GET_CODE (XEXP (x, 0)) == FIX)
+-		*cost += rtx_cost (XEXP (XEXP (x, 0), 0), mode, code,
+-				   0, speed_p);
+-	      else
+-		*cost += rtx_cost (XEXP (x, 0), mode, code, 0, speed_p);
+-	      /* ??? Increase the cost to deal with transferring from
+-		 FP -> CORE registers?  */
+-	      return true;
+-	    }
+-	  else if (GET_MODE_CLASS (mode) == MODE_FLOAT
+-		   && TARGET_FPU_ARMV8)
+-	    {
+-	      if (speed_p)
+-		*cost += extra_cost->fp[mode == DFmode].roundint;
+-	      return false;
+-	    }
+-	  /* Vector costs? */
+-	}
+-      *cost = LIBCALL_COST (1);
+-      return false;
+-
+-    case FLOAT:
+-    case UNSIGNED_FLOAT:
+-      if (TARGET_HARD_FLOAT)
+-	{
+-	  /* ??? Increase the cost to deal with transferring from CORE
+-	     -> FP registers?  */
+-	  if (speed_p)
+-	    *cost += extra_cost->fp[mode == DFmode].fromint;
+-	  return false;
+-	}
+-      *cost = LIBCALL_COST (1);
+-      return false;
+-
+-    case CALL:
+-      return true;
+-
+-    case ASM_OPERANDS:
+-      {
+-      /* Just a guess.  Guess number of instructions in the asm
+-         plus one insn per input.  Always a minimum of COSTS_N_INSNS (1)
+-         though (see PR60663).  */
+-        int asm_length = MAX (1, asm_str_count (ASM_OPERANDS_TEMPLATE (x)));
+-        int num_operands = ASM_OPERANDS_INPUT_LENGTH (x);
+-
+-        *cost = COSTS_N_INSNS (asm_length + num_operands);
+-        return true;
+-      }
+-    default:
+-      if (mode != VOIDmode)
+-	*cost = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+-      else
+-	*cost = COSTS_N_INSNS (4); /* Who knows?  */
+-      return false;
+-    }
+-}
+-
+-#undef HANDLE_NARROW_SHIFT_ARITH
+-
+-/* RTX costs when optimizing for size.  */
+-static bool
+-arm_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
+-	       int opno ATTRIBUTE_UNUSED, int *total, bool speed)
+-{
+-  bool result;
+-  int code = GET_CODE (x);
+-
+-  if (TARGET_OLD_RTX_COSTS
+-      || (!current_tune->insn_extra_cost && !TARGET_NEW_GENERIC_COSTS))
+-    {
+-      /* Old way.  (Deprecated.)  */
+-      if (!speed)
+-	result = arm_size_rtx_costs (x, (enum rtx_code) code,
+-				     (enum rtx_code) outer_code, total);
+-      else
+-	result = current_tune->rtx_costs (x,  (enum rtx_code) code,
+-					  (enum rtx_code) outer_code, total,
+-					  speed);
+-    }
+-  else
+-    {
+-    /* New way.  */
+-      if (current_tune->insn_extra_cost)
+-        result =  arm_new_rtx_costs (x, (enum rtx_code) code,
+-				     (enum rtx_code) outer_code,
+-				     current_tune->insn_extra_cost,
+-				     total, speed);
+-    /* TARGET_NEW_GENERIC_COSTS && !TARGET_OLD_RTX_COSTS
+-       && current_tune->insn_extra_cost != NULL  */
+-      else
+-        result =  arm_new_rtx_costs (x, (enum rtx_code) code,
+-				    (enum rtx_code) outer_code,
+-				    &generic_extra_costs, total, speed);
+-    }
+-
+-  if (dump_file && (dump_flags & TDF_DETAILS))
+-    {
+-      print_rtl_single (dump_file, x);
+-      fprintf (dump_file, "\n%s cost: %d (%s)\n", speed ? "Hot" : "Cold",
+-	       *total, result ? "final" : "partial");
+-    }
+-  return result;
+-}
+-
+-/* RTX costs for cores with a slow MUL implementation.  Thumb-2 is not
+-   supported on any "slowmul" cores, so it can be ignored.  */
+-
+-static bool
+-arm_slowmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+-		       int *total, bool speed)
+-{
+-  machine_mode mode = GET_MODE (x);
+-
+-  if (TARGET_THUMB)
+-    {
+-      *total = thumb1_rtx_costs (x, code, outer_code);
+-      return true;
+-    }
+-
+-  switch (code)
+-    {
+-    case MULT:
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT
+-	  || mode == DImode)
+-	{
+-	  *total = COSTS_N_INSNS (20);
+-	  return false;
+-	}
+-
+-      if (CONST_INT_P (XEXP (x, 1)))
+-	{
+-	  unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
+-				      & (unsigned HOST_WIDE_INT) 0xffffffff);
+-	  int cost, const_ok = const_ok_for_arm (i);
+-	  int j, booth_unit_size;
+-
+-	  /* Tune as appropriate.  */
+-	  cost = const_ok ? 4 : 8;
+-	  booth_unit_size = 2;
+-	  for (j = 0; i && j < 32; j += booth_unit_size)
+-	    {
+-	      i >>= booth_unit_size;
+-	      cost++;
+-	    }
+-
+-	  *total = COSTS_N_INSNS (cost);
+-	  *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+-	  return true;
+-	}
+-
+-      *total = COSTS_N_INSNS (20);
+-      return false;
+-
+-    default:
+-      return arm_rtx_costs_1 (x, outer_code, total, speed);;
+-    }
+-}
+-
+-
+-/* RTX cost for cores with a fast multiply unit (M variants).  */
+-
+-static bool
+-arm_fastmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+-		       int *total, bool speed)
+-{
+-  machine_mode mode = GET_MODE (x);
+-
+-  if (TARGET_THUMB1)
+-    {
+-      *total = thumb1_rtx_costs (x, code, outer_code);
+-      return true;
+-    }
+-
+-  /* ??? should thumb2 use different costs?  */
+-  switch (code)
+-    {
+-    case MULT:
+-      /* There is no point basing this on the tuning, since it is always the
+-	 fast variant if it exists at all.  */
+-      if (mode == DImode
+-	  && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
+-	  && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+-	      || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
+-	{
+-	  *total = COSTS_N_INSNS(2);
+-	  return false;
+-	}
+-
+-
+-      if (mode == DImode)
+-	{
+-	  *total = COSTS_N_INSNS (5);
+-	  return false;
+-	}
+-
+-      if (CONST_INT_P (XEXP (x, 1)))
+-	{
+-	  unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
+-				      & (unsigned HOST_WIDE_INT) 0xffffffff);
+-	  int cost, const_ok = const_ok_for_arm (i);
+-	  int j, booth_unit_size;
+-
+-	  /* Tune as appropriate.  */
+-	  cost = const_ok ? 4 : 8;
+-	  booth_unit_size = 8;
+-	  for (j = 0; i && j < 32; j += booth_unit_size)
+-	    {
+-	      i >>= booth_unit_size;
+-	      cost++;
+-	    }
+-
+-	  *total = COSTS_N_INSNS(cost);
+-	  return false;
+-	}
+-
+-      if (mode == SImode)
+-	{
+-	  *total = COSTS_N_INSNS (4);
+-	  return false;
+-	}
+-
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+-	{
+-	  if (TARGET_HARD_FLOAT
+-	      && (mode == SFmode
+-		  || (mode == DFmode && !TARGET_VFP_SINGLE)))
+-	    {
+-	      *total = COSTS_N_INSNS (1);
+-	      return false;
+-	    }
+-	}
+-
+-      /* Requires a lib call */
+-      *total = COSTS_N_INSNS (20);
+-      return false;
+-
+-    default:
+-      return arm_rtx_costs_1 (x, outer_code, total, speed);
+-    }
+-}
+-
+-
+-/* RTX cost for XScale CPUs.  Thumb-2 is not supported on any xscale cores,
+-   so it can be ignored.  */
+-
+-static bool
+-arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+-		      int *total, bool speed)
+-{
+-  machine_mode mode = GET_MODE (x);
+-
+-  if (TARGET_THUMB)
+-    {
+-      *total = thumb1_rtx_costs (x, code, outer_code);
+-      return true;
+-    }
+-
+-  switch (code)
+-    {
+-    case COMPARE:
+-      if (GET_CODE (XEXP (x, 0)) != MULT)
+-	return arm_rtx_costs_1 (x, outer_code, total, speed);
+-
+-      /* A COMPARE of a MULT is slow on XScale; the muls instruction
+-	 will stall until the multiplication is complete.  */
+-      *total = COSTS_N_INSNS (3);
+-      return false;
+-
+-    case MULT:
+-      /* There is no point basing this on the tuning, since it is always the
+-	 fast variant if it exists at all.  */
+-      if (mode == DImode
+-	  && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
+-	  && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+-	      || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
+-	{
+-	  *total = COSTS_N_INSNS (2);
+-	  return false;
+-	}
+-
+-
+-      if (mode == DImode)
+-	{
+-	  *total = COSTS_N_INSNS (5);
+-	  return false;
+-	}
+-
+-      if (CONST_INT_P (XEXP (x, 1)))
+-	{
+-	  /* If operand 1 is a constant we can more accurately
+-	     calculate the cost of the multiply.  The multiplier can
+-	     retire 15 bits on the first cycle and a further 12 on the
+-	     second.  We do, of course, have to load the constant into
+-	     a register first.  */
+-	  unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
+-	  /* There's a general overhead of one cycle.  */
+-	  int cost = 1;
+-	  unsigned HOST_WIDE_INT masked_const;
+-
+-	  if (i & 0x80000000)
+-	    i = ~i;
+-
+-	  i &= (unsigned HOST_WIDE_INT) 0xffffffff;
++	      return true;
++	    }
+ 
+-	  masked_const = i & 0xffff8000;
+-	  if (masked_const != 0)
++	  if (GET_MODE_CLASS (mode) == MODE_INT)
+ 	    {
+-	      cost++;
+-	      masked_const = i & 0xf8000000;
+-	      if (masked_const != 0)
+-		cost++;
++	      mode = GET_MODE (XEXP (x, 0));
++	      if (speed_p)
++		*cost += extra_cost->fp[mode == DFmode].toint;
++	      /* Strip of the 'cost' of rounding towards zero.  */
++	      if (GET_CODE (XEXP (x, 0)) == FIX)
++		*cost += rtx_cost (XEXP (XEXP (x, 0), 0), mode, code,
++				   0, speed_p);
++	      else
++		*cost += rtx_cost (XEXP (x, 0), mode, code, 0, speed_p);
++	      /* ??? Increase the cost to deal with transferring from
++		 FP -> CORE registers?  */
++	      return true;
+ 	    }
+-	  *total = COSTS_N_INSNS (cost);
+-	  return false;
++	  else if (GET_MODE_CLASS (mode) == MODE_FLOAT
++		   && TARGET_FPU_ARMV8)
++	    {
++	      if (speed_p)
++		*cost += extra_cost->fp[mode == DFmode].roundint;
++	      return false;
++	    }
++	  /* Vector costs? */
+ 	}
++      *cost = LIBCALL_COST (1);
++      return false;
+ 
+-      if (mode == SImode)
++    case FLOAT:
++    case UNSIGNED_FLOAT:
++      if (TARGET_HARD_FLOAT)
+ 	{
+-	  *total = COSTS_N_INSNS (3);
++	  /* ??? Increase the cost to deal with transferring from CORE
++	     -> FP registers?  */
++	  if (speed_p)
++	    *cost += extra_cost->fp[mode == DFmode].fromint;
+ 	  return false;
+ 	}
+-
+-      /* Requires a lib call */
+-      *total = COSTS_N_INSNS (20);
++      *cost = LIBCALL_COST (1);
+       return false;
+ 
++    case CALL:
++      return true;
++
++    case ASM_OPERANDS:
++      {
++      /* Just a guess.  Guess number of instructions in the asm
++         plus one insn per input.  Always a minimum of COSTS_N_INSNS (1)
++         though (see PR60663).  */
++        int asm_length = MAX (1, asm_str_count (ASM_OPERANDS_TEMPLATE (x)));
++        int num_operands = ASM_OPERANDS_INPUT_LENGTH (x);
++
++        *cost = COSTS_N_INSNS (asm_length + num_operands);
++        return true;
++      }
+     default:
+-      return arm_rtx_costs_1 (x, outer_code, total, speed);
++      if (mode != VOIDmode)
++	*cost = COSTS_N_INSNS (ARM_NUM_REGS (mode));
++      else
++	*cost = COSTS_N_INSNS (4); /* Who knows?  */
++      return false;
+     }
+ }
+ 
++#undef HANDLE_NARROW_SHIFT_ARITH
+ 
+-/* RTX costs for 9e (and later) cores.  */
++/* RTX costs entry point.  */
+ 
+ static bool
+-arm_9e_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+-		  int *total, bool speed)
++arm_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
++	       int opno ATTRIBUTE_UNUSED, int *total, bool speed)
+ {
+-  machine_mode mode = GET_MODE (x);
+-
+-  if (TARGET_THUMB1)
+-    {
+-      switch (code)
+-	{
+-	case MULT:
+-	  /* Small multiply: 32 cycles for an integer multiply inst.  */
+-	  if (arm_arch6m && arm_m_profile_small_mul)
+-	    *total = COSTS_N_INSNS (32);
+-	  else
+-	    *total = COSTS_N_INSNS (3);
+-	  return true;
++  bool result;
++  int code = GET_CODE (x);
++  gcc_assert (current_tune->insn_extra_cost);
+ 
+-	default:
+-	  *total = thumb1_rtx_costs (x, code, outer_code);
+-	  return true;
+-	}
+-    }
++  result =  arm_rtx_costs_internal (x, (enum rtx_code) code,
++				(enum rtx_code) outer_code,
++				current_tune->insn_extra_cost,
++				total, speed);
+ 
+-  switch (code)
++  if (dump_file && (dump_flags & TDF_DETAILS))
+     {
+-    case MULT:
+-      /* There is no point basing this on the tuning, since it is always the
+-	 fast variant if it exists at all.  */
+-      if (mode == DImode
+-	  && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
+-	  && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+-	      || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
+-	{
+-	  *total = COSTS_N_INSNS (2);
+-	  return false;
+-	}
+-
+-
+-      if (mode == DImode)
+-	{
+-	  *total = COSTS_N_INSNS (5);
+-	  return false;
+-	}
+-
+-      if (mode == SImode)
+-	{
+-	  *total = COSTS_N_INSNS (2);
+-	  return false;
+-	}
+-
+-      if (GET_MODE_CLASS (mode) == MODE_FLOAT)
+-	{
+-	  if (TARGET_HARD_FLOAT
+-	      && (mode == SFmode
+-		  || (mode == DFmode && !TARGET_VFP_SINGLE)))
+-	    {
+-	      *total = COSTS_N_INSNS (1);
+-	      return false;
+-	    }
+-	}
+-
+-      *total = COSTS_N_INSNS (20);
+-      return false;
+-
+-    default:
+-      return arm_rtx_costs_1 (x, outer_code, total, speed);
++      print_rtl_single (dump_file, x);
++      fprintf (dump_file, "\n%s cost: %d (%s)\n", speed ? "Hot" : "Cold",
++	       *total, result ? "final" : "partial");
+     }
++  return result;
+ }
++
+ /* All address computations that can be done are free, but rtx cost returns
+    the same for practically all of them.  So we weight the different types
+    of address here in the order (most pref first):
+@@ -12310,7 +11470,7 @@ vfp3_const_double_index (rtx x)
+ 
+   /* We can permit four significant bits of mantissa only, plus a high bit
+      which is always 1.  */
+-  mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1;
++  mask = (HOST_WIDE_INT_1U << (point_pos - 5)) - 1;
+   if ((mantissa & mask) != 0)
+     return -1;
+ 
+@@ -12464,6 +11624,12 @@ neon_valid_immediate (rtx op, machine_mode mode, int inverse,
+ 	return 18;
+     }
+ 
++  /* The tricks done in the code below apply for little-endian vector layout.
++     For big-endian vectors only allow vectors of the form { a, a, a..., a }.
++     FIXME: Implement logic for big-endian vectors.  */
++  if (BYTES_BIG_ENDIAN && vector && !const_vec_duplicate_p (op))
++    return -1;
++
+   /* Splat vector constant out into a byte vector.  */
+   for (i = 0; i < n_elts; i++)
+     {
+@@ -13192,7 +12358,7 @@ coproc_secondary_reload_class (machine_mode mode, rtx x, bool wb)
+ {
+   if (mode == HFmode)
+     {
+-      if (!TARGET_NEON_FP16)
++      if (!TARGET_NEON_FP16 && !TARGET_VFP_FP16INST)
+ 	return GENERAL_REGS;
+       if (s_register_operand (x, mode) || neon_vector_mem_operand (x, 2, true))
+ 	return NO_REGS;
+@@ -16042,14 +15208,17 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
+   /* If the same input register is used in both stores
+      when storing different constants, try to find a free register.
+      For example, the code
+-        mov r0, 0
+-        str r0, [r2]
+-        mov r0, 1
+-        str r0, [r2, #4]
++	mov r0, 0
++	str r0, [r2]
++	mov r0, 1
++	str r0, [r2, #4]
+      can be transformed into
+-        mov r1, 0
+-        strd r1, r0, [r2]
+-     in Thumb mode assuming that r1 is free.  */
++	mov r1, 0
++	mov r0, 1
++	strd r1, r0, [r2]
++     in Thumb mode assuming that r1 is free.
++     For ARM mode do the same but only if the starting register
++     can be made to be even.  */
+   if (const_store
+       && REGNO (operands[0]) == REGNO (operands[1])
+       && INTVAL (operands[4]) != INTVAL (operands[5]))
+@@ -16068,7 +15237,6 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
+       }
+     else if (TARGET_ARM)
+       {
+-        return false;
+         int regno = REGNO (operands[0]);
+         if (!peep2_reg_dead_p (4, operands[0]))
+           {
+@@ -16426,7 +15594,7 @@ get_jump_table_size (rtx_jump_table_data *insn)
+ 	{
+ 	case 1:
+ 	  /* Round up size  of TBB table to a halfword boundary.  */
+-	  size = (size + 1) & ~(HOST_WIDE_INT)1;
++	  size = (size + 1) & ~HOST_WIDE_INT_1;
+ 	  break;
+ 	case 2:
+ 	  /* No padding necessary for TBH.  */
+@@ -16895,35 +16063,37 @@ dump_minipool (rtx_insn *scan)
+ 	      fputc ('\n', dump_file);
+ 	    }
+ 
++	  rtx val = copy_rtx (mp->value);
++
+ 	  switch (GET_MODE_SIZE (mp->mode))
+ 	    {
+ #ifdef HAVE_consttable_1
+ 	    case 1:
+-	      scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
++	      scan = emit_insn_after (gen_consttable_1 (val), scan);
+ 	      break;
+ 
+ #endif
+ #ifdef HAVE_consttable_2
+ 	    case 2:
+-	      scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
++	      scan = emit_insn_after (gen_consttable_2 (val), scan);
+ 	      break;
+ 
+ #endif
+ #ifdef HAVE_consttable_4
+ 	    case 4:
+-	      scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
++	      scan = emit_insn_after (gen_consttable_4 (val), scan);
+ 	      break;
+ 
+ #endif
+ #ifdef HAVE_consttable_8
+ 	    case 8:
+-	      scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
++	      scan = emit_insn_after (gen_consttable_8 (val), scan);
+ 	      break;
+ 
+ #endif
+ #ifdef HAVE_consttable_16
+ 	    case 16:
+-              scan = emit_insn_after (gen_consttable_16 (mp->value), scan);
++              scan = emit_insn_after (gen_consttable_16 (val), scan);
+               break;
+ 
+ #endif
+@@ -17104,6 +16274,7 @@ static void
+ push_minipool_fix (rtx_insn *insn, HOST_WIDE_INT address, rtx *loc,
+ 		   machine_mode mode, rtx value)
+ {
++  gcc_assert (!arm_disable_literal_pool);
+   Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
+ 
+   fix->insn = insn;
+@@ -17155,10 +16326,6 @@ push_minipool_fix (rtx_insn *insn, HOST_WIDE_INT address, rtx *loc,
+ int
+ arm_max_const_double_inline_cost ()
+ {
+-  /* Let the value get synthesized to avoid the use of literal pools.  */
+-  if (arm_disable_literal_pool)
+-    return 99;
+-
+   return ((optimize_size || arm_ld_sched) ? 3 : 4);
+ }
+ 
+@@ -17222,109 +16389,573 @@ arm_const_double_by_parts (rtx val)
+       || const_ok_for_arm (~INTVAL (part)))
+     return true;
+ 
+-  part = gen_lowpart (SImode, val);
++  part = gen_lowpart (SImode, val);
++
++  gcc_assert (CONST_INT_P (part));
++
++  if (const_ok_for_arm (INTVAL (part))
++      || const_ok_for_arm (~INTVAL (part)))
++    return true;
++
++  return false;
++}
++
++/* Return true if it is possible to inline both the high and low parts
++   of a 64-bit constant into 32-bit data processing instructions.  */
++bool
++arm_const_double_by_immediates (rtx val)
++{
++  machine_mode mode = GET_MODE (val);
++  rtx part;
++
++  if (mode == VOIDmode)
++    mode = DImode;
++
++  part = gen_highpart_mode (SImode, mode, val);
++
++  gcc_assert (CONST_INT_P (part));
++
++  if (!const_ok_for_arm (INTVAL (part)))
++    return false;
++
++  part = gen_lowpart (SImode, val);
++
++  gcc_assert (CONST_INT_P (part));
++
++  if (!const_ok_for_arm (INTVAL (part)))
++    return false;
++
++  return true;
++}
++
++/* Scan INSN and note any of its operands that need fixing.
++   If DO_PUSHES is false we do not actually push any of the fixups
++   needed.  */
++static void
++note_invalid_constants (rtx_insn *insn, HOST_WIDE_INT address, int do_pushes)
++{
++  int opno;
++
++  extract_constrain_insn (insn);
++
++  if (recog_data.n_alternatives == 0)
++    return;
++
++  /* Fill in recog_op_alt with information about the constraints of
++     this insn.  */
++  preprocess_constraints (insn);
++
++  const operand_alternative *op_alt = which_op_alt ();
++  for (opno = 0; opno < recog_data.n_operands; opno++)
++    {
++      /* Things we need to fix can only occur in inputs.  */
++      if (recog_data.operand_type[opno] != OP_IN)
++	continue;
++
++      /* If this alternative is a memory reference, then any mention
++	 of constants in this alternative is really to fool reload
++	 into allowing us to accept one there.  We need to fix them up
++	 now so that we output the right code.  */
++      if (op_alt[opno].memory_ok)
++	{
++	  rtx op = recog_data.operand[opno];
++
++	  if (CONSTANT_P (op))
++	    {
++	      if (do_pushes)
++		push_minipool_fix (insn, address, recog_data.operand_loc[opno],
++				   recog_data.operand_mode[opno], op);
++	    }
++	  else if (MEM_P (op)
++		   && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
++		   && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
++	    {
++	      if (do_pushes)
++		{
++		  rtx cop = avoid_constant_pool_reference (op);
++
++		  /* Casting the address of something to a mode narrower
++		     than a word can cause avoid_constant_pool_reference()
++		     to return the pool reference itself.  That's no good to
++		     us here.  Lets just hope that we can use the
++		     constant pool value directly.  */
++		  if (op == cop)
++		    cop = get_pool_constant (XEXP (op, 0));
++
++		  push_minipool_fix (insn, address,
++				     recog_data.operand_loc[opno],
++				     recog_data.operand_mode[opno], cop);
++		}
++
++	    }
++	}
++    }
++
++  return;
++}
++
++/* This function computes the clear mask and PADDING_BITS_TO_CLEAR for structs
++   and unions in the context of ARMv8-M Security Extensions.  It is used as a
++   helper function for both 'cmse_nonsecure_call' and 'cmse_nonsecure_entry'
++   functions.  The PADDING_BITS_TO_CLEAR pointer can be the base to either one
++   or four masks, depending on whether it is being computed for a
++   'cmse_nonsecure_entry' return value or a 'cmse_nonsecure_call' argument
++   respectively.  The tree for the type of the argument or a field within an
++   argument is passed in ARG_TYPE, the current register this argument or field
++   starts in is kept in the pointer REGNO and updated accordingly, the bit this
++   argument or field starts at is passed in STARTING_BIT and the last used bit
++   is kept in LAST_USED_BIT which is also updated accordingly.  */
++
++static unsigned HOST_WIDE_INT
++comp_not_to_clear_mask_str_un (tree arg_type, int * regno,
++			       uint32_t * padding_bits_to_clear,
++			       unsigned starting_bit, int * last_used_bit)
++
++{
++  unsigned HOST_WIDE_INT not_to_clear_reg_mask = 0;
++
++  if (TREE_CODE (arg_type) == RECORD_TYPE)
++    {
++      unsigned current_bit = starting_bit;
++      tree field;
++      long int offset, size;
++
++
++      field = TYPE_FIELDS (arg_type);
++      while (field)
++	{
++	  /* The offset within a structure is always an offset from
++	     the start of that structure.  Make sure we take that into the
++	     calculation of the register based offset that we use here.  */
++	  offset = starting_bit;
++	  offset += TREE_INT_CST_ELT (DECL_FIELD_BIT_OFFSET (field), 0);
++	  offset %= 32;
++
++	  /* This is the actual size of the field, for bitfields this is the
++	     bitfield width and not the container size.  */
++	  size = TREE_INT_CST_ELT (DECL_SIZE (field), 0);
++
++	  if (*last_used_bit != offset)
++	    {
++	      if (offset < *last_used_bit)
++		{
++		  /* This field's offset is before the 'last_used_bit', that
++		     means this field goes on the next register.  So we need to
++		     pad the rest of the current register and increase the
++		     register number.  */
++		  uint32_t mask;
++		  mask  = ((uint32_t)-1) - ((uint32_t) 1 << *last_used_bit);
++		  mask++;
++
++		  padding_bits_to_clear[*regno] |= mask;
++		  not_to_clear_reg_mask |= HOST_WIDE_INT_1U << *regno;
++		  (*regno)++;
++		}
++	      else
++		{
++		  /* Otherwise we pad the bits between the last field's end and
++		     the start of the new field.  */
++		  uint32_t mask;
++
++		  mask = ((uint32_t)-1) >> (32 - offset);
++		  mask -= ((uint32_t) 1 << *last_used_bit) - 1;
++		  padding_bits_to_clear[*regno] |= mask;
++		}
++	      current_bit = offset;
++	    }
++
++	  /* Calculate further padding bits for inner structs/unions too.  */
++	  if (RECORD_OR_UNION_TYPE_P (TREE_TYPE (field)))
++	    {
++	      *last_used_bit = current_bit;
++	      not_to_clear_reg_mask
++		|= comp_not_to_clear_mask_str_un (TREE_TYPE (field), regno,
++						  padding_bits_to_clear, offset,
++						  last_used_bit);
++	    }
++	  else
++	    {
++	      /* Update 'current_bit' with this field's size.  If the
++		 'current_bit' lies in a subsequent register, update 'regno' and
++		 reset 'current_bit' to point to the current bit in that new
++		 register.  */
++	      current_bit += size;
++	      while (current_bit >= 32)
++		{
++		  current_bit-=32;
++		  not_to_clear_reg_mask |= HOST_WIDE_INT_1U << *regno;
++		  (*regno)++;
++		}
++	      *last_used_bit = current_bit;
++	    }
++
++	  field = TREE_CHAIN (field);
++	}
++      not_to_clear_reg_mask |= HOST_WIDE_INT_1U << *regno;
++    }
++  else if (TREE_CODE (arg_type) == UNION_TYPE)
++    {
++      tree field, field_t;
++      int i, regno_t, field_size;
++      int max_reg = -1;
++      int max_bit = -1;
++      uint32_t mask;
++      uint32_t padding_bits_to_clear_res[NUM_ARG_REGS]
++	= {-1, -1, -1, -1};
++
++      /* To compute the padding bits in a union we only consider bits as
++	 padding bits if they are always either a padding bit or fall outside a
++	 fields size for all fields in the union.  */
++      field = TYPE_FIELDS (arg_type);
++      while (field)
++	{
++	  uint32_t padding_bits_to_clear_t[NUM_ARG_REGS]
++	    = {0U, 0U, 0U, 0U};
++	  int last_used_bit_t = *last_used_bit;
++	  regno_t = *regno;
++	  field_t = TREE_TYPE (field);
++
++	  /* If the field's type is either a record or a union make sure to
++	     compute their padding bits too.  */
++	  if (RECORD_OR_UNION_TYPE_P (field_t))
++	    not_to_clear_reg_mask
++	      |= comp_not_to_clear_mask_str_un (field_t, &regno_t,
++						&padding_bits_to_clear_t[0],
++						starting_bit, &last_used_bit_t);
++	  else
++	    {
++	      field_size = TREE_INT_CST_ELT (DECL_SIZE (field), 0);
++	      regno_t = (field_size / 32) + *regno;
++	      last_used_bit_t = (starting_bit + field_size) % 32;
++	    }
++
++	  for (i = *regno; i < regno_t; i++)
++	    {
++	      /* For all but the last register used by this field only keep the
++		 padding bits that were padding bits in this field.  */
++	      padding_bits_to_clear_res[i] &= padding_bits_to_clear_t[i];
++	    }
++
++	    /* For the last register, keep all padding bits that were padding
++	       bits in this field and any padding bits that are still valid
++	       as padding bits but fall outside of this field's size.  */
++	    mask = (((uint32_t) -1) - ((uint32_t) 1 << last_used_bit_t)) + 1;
++	    padding_bits_to_clear_res[regno_t]
++	      &= padding_bits_to_clear_t[regno_t] | mask;
++
++	  /* Update the maximum size of the fields in terms of registers used
++	     ('max_reg') and the 'last_used_bit' in said register.  */
++	  if (max_reg < regno_t)
++	    {
++	      max_reg = regno_t;
++	      max_bit = last_used_bit_t;
++	    }
++	  else if (max_reg == regno_t && max_bit < last_used_bit_t)
++	    max_bit = last_used_bit_t;
++
++	  field = TREE_CHAIN (field);
++	}
++
++      /* Update the current padding_bits_to_clear using the intersection of the
++	 padding bits of all the fields.  */
++      for (i=*regno; i < max_reg; i++)
++	padding_bits_to_clear[i] |= padding_bits_to_clear_res[i];
+ 
+-  gcc_assert (CONST_INT_P (part));
++      /* Do not keep trailing padding bits, we do not know yet whether this
++	 is the end of the argument.  */
++      mask = ((uint32_t) 1 << max_bit) - 1;
++      padding_bits_to_clear[max_reg]
++	|= padding_bits_to_clear_res[max_reg] & mask;
+ 
+-  if (const_ok_for_arm (INTVAL (part))
+-      || const_ok_for_arm (~INTVAL (part)))
+-    return true;
++      *regno = max_reg;
++      *last_used_bit = max_bit;
++    }
++  else
++    /* This function should only be used for structs and unions.  */
++    gcc_unreachable ();
+ 
+-  return false;
++  return not_to_clear_reg_mask;
+ }
+ 
+-/* Return true if it is possible to inline both the high and low parts
+-   of a 64-bit constant into 32-bit data processing instructions.  */
+-bool
+-arm_const_double_by_immediates (rtx val)
++/* In the context of ARMv8-M Security Extensions, this function is used for both
++   'cmse_nonsecure_call' and 'cmse_nonsecure_entry' functions to compute what
++   registers are used when returning or passing arguments, which is then
++   returned as a mask.  It will also compute a mask to indicate padding/unused
++   bits for each of these registers, and passes this through the
++   PADDING_BITS_TO_CLEAR pointer.  The tree of the argument type is passed in
++   ARG_TYPE, the rtl representation of the argument is passed in ARG_RTX and
++   the starting register used to pass this argument or return value is passed
++   in REGNO.  It makes use of 'comp_not_to_clear_mask_str_un' to compute these
++   for struct and union types.  */
++
++static unsigned HOST_WIDE_INT
++compute_not_to_clear_mask (tree arg_type, rtx arg_rtx, int regno,
++			     uint32_t * padding_bits_to_clear)
++
+ {
+-  machine_mode mode = GET_MODE (val);
+-  rtx part;
++  int last_used_bit = 0;
++  unsigned HOST_WIDE_INT not_to_clear_mask;
+ 
+-  if (mode == VOIDmode)
+-    mode = DImode;
++  if (RECORD_OR_UNION_TYPE_P (arg_type))
++    {
++      not_to_clear_mask
++	= comp_not_to_clear_mask_str_un (arg_type, &regno,
++					 padding_bits_to_clear, 0,
++					 &last_used_bit);
+ 
+-  part = gen_highpart_mode (SImode, mode, val);
+ 
+-  gcc_assert (CONST_INT_P (part));
++      /* If the 'last_used_bit' is not zero, that means we are still using a
++	 part of the last 'regno'.  In such cases we must clear the trailing
++	 bits.  Otherwise we are not using regno and we should mark it as to
++	 clear.  */
++      if (last_used_bit != 0)
++	padding_bits_to_clear[regno]
++	  |= ((uint32_t)-1) - ((uint32_t) 1 << last_used_bit) + 1;
++      else
++	not_to_clear_mask &= ~(HOST_WIDE_INT_1U << regno);
++    }
++  else
++    {
++      not_to_clear_mask = 0;
++      /* We are not dealing with structs nor unions.  So these arguments may be
++	 passed in floating point registers too.  In some cases a BLKmode is
++	 used when returning or passing arguments in multiple VFP registers.  */
++      if (GET_MODE (arg_rtx) == BLKmode)
++	{
++	  int i, arg_regs;
++	  rtx reg;
+ 
+-  if (!const_ok_for_arm (INTVAL (part)))
+-    return false;
++	  /* This should really only occur when dealing with the hard-float
++	     ABI.  */
++	  gcc_assert (TARGET_HARD_FLOAT_ABI);
+ 
+-  part = gen_lowpart (SImode, val);
++	  for (i = 0; i < XVECLEN (arg_rtx, 0); i++)
++	    {
++	      reg = XEXP (XVECEXP (arg_rtx, 0, i), 0);
++	      gcc_assert (REG_P (reg));
+ 
+-  gcc_assert (CONST_INT_P (part));
++	      not_to_clear_mask |= HOST_WIDE_INT_1U << REGNO (reg);
+ 
+-  if (!const_ok_for_arm (INTVAL (part)))
+-    return false;
++	      /* If we are dealing with DF mode, make sure we don't
++		 clear either of the registers it addresses.  */
++	      arg_regs = ARM_NUM_REGS (GET_MODE (reg));
++	      if (arg_regs > 1)
++		{
++		  unsigned HOST_WIDE_INT mask;
++		  mask = HOST_WIDE_INT_1U << (REGNO (reg) + arg_regs);
++		  mask -= HOST_WIDE_INT_1U << REGNO (reg);
++		  not_to_clear_mask |= mask;
++		}
++	    }
++	}
++      else
++	{
++	  /* Otherwise we can rely on the MODE to determine how many registers
++	     are being used by this argument.  */
++	  int arg_regs = ARM_NUM_REGS (GET_MODE (arg_rtx));
++	  not_to_clear_mask |= HOST_WIDE_INT_1U << REGNO (arg_rtx);
++	  if (arg_regs > 1)
++	    {
++	      unsigned HOST_WIDE_INT
++	      mask = HOST_WIDE_INT_1U << (REGNO (arg_rtx) + arg_regs);
++	      mask -= HOST_WIDE_INT_1U << REGNO (arg_rtx);
++	      not_to_clear_mask |= mask;
++	    }
++	}
++    }
+ 
+-  return true;
++  return not_to_clear_mask;
+ }
+ 
+-/* Scan INSN and note any of its operands that need fixing.
+-   If DO_PUSHES is false we do not actually push any of the fixups
+-   needed.  */
++/* Saves callee saved registers, clears callee saved registers and caller saved
++   registers not used to pass arguments before a cmse_nonsecure_call.  And
++   restores the callee saved registers after.  */
++
+ static void
+-note_invalid_constants (rtx_insn *insn, HOST_WIDE_INT address, int do_pushes)
++cmse_nonsecure_call_clear_caller_saved (void)
+ {
+-  int opno;
++  basic_block bb;
+ 
+-  extract_constrain_insn (insn);
++  FOR_EACH_BB_FN (bb, cfun)
++    {
++      rtx_insn *insn;
+ 
+-  if (recog_data.n_alternatives == 0)
+-    return;
++      FOR_BB_INSNS (bb, insn)
++	{
++	  uint64_t to_clear_mask, float_mask;
++	  rtx_insn *seq;
++	  rtx pat, call, unspec, reg, cleared_reg, tmp;
++	  unsigned int regno, maxregno;
++	  rtx address;
++	  CUMULATIVE_ARGS args_so_far_v;
++	  cumulative_args_t args_so_far;
++	  tree arg_type, fntype;
++	  bool using_r4, first_param = true;
++	  function_args_iterator args_iter;
++	  uint32_t padding_bits_to_clear[4] = {0U, 0U, 0U, 0U};
++	  uint32_t * padding_bits_to_clear_ptr = &padding_bits_to_clear[0];
++
++	  if (!NONDEBUG_INSN_P (insn))
++	    continue;
+ 
+-  /* Fill in recog_op_alt with information about the constraints of
+-     this insn.  */
+-  preprocess_constraints (insn);
++	  if (!CALL_P (insn))
++	    continue;
+ 
+-  const operand_alternative *op_alt = which_op_alt ();
+-  for (opno = 0; opno < recog_data.n_operands; opno++)
+-    {
+-      /* Things we need to fix can only occur in inputs.  */
+-      if (recog_data.operand_type[opno] != OP_IN)
+-	continue;
++	  pat = PATTERN (insn);
++	  gcc_assert (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 0);
++	  call = XVECEXP (pat, 0, 0);
+ 
+-      /* If this alternative is a memory reference, then any mention
+-	 of constants in this alternative is really to fool reload
+-	 into allowing us to accept one there.  We need to fix them up
+-	 now so that we output the right code.  */
+-      if (op_alt[opno].memory_ok)
+-	{
+-	  rtx op = recog_data.operand[opno];
++	  /* Get the real call RTX if the insn sets a value, ie. returns.  */
++	  if (GET_CODE (call) == SET)
++	      call = SET_SRC (call);
+ 
+-	  if (CONSTANT_P (op))
++	  /* Check if it is a cmse_nonsecure_call.  */
++	  unspec = XEXP (call, 0);
++	  if (GET_CODE (unspec) != UNSPEC
++	      || XINT (unspec, 1) != UNSPEC_NONSECURE_MEM)
++	    continue;
++
++	  /* Determine the caller-saved registers we need to clear.  */
++	  to_clear_mask = (1LL << (NUM_ARG_REGS)) - 1;
++	  maxregno = NUM_ARG_REGS - 1;
++	  /* Only look at the caller-saved floating point registers in case of
++	     -mfloat-abi=hard.  For -mfloat-abi=softfp we will be using the
++	     lazy store and loads which clear both caller- and callee-saved
++	     registers.  */
++	  if (TARGET_HARD_FLOAT_ABI)
+ 	    {
+-	      if (do_pushes)
+-		push_minipool_fix (insn, address, recog_data.operand_loc[opno],
+-				   recog_data.operand_mode[opno], op);
++	      float_mask = (1LL << (D7_VFP_REGNUM + 1)) - 1;
++	      float_mask &= ~((1LL << FIRST_VFP_REGNUM) - 1);
++	      to_clear_mask |= float_mask;
++	      maxregno = D7_VFP_REGNUM;
+ 	    }
+-	  else if (MEM_P (op)
+-		   && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+-		   && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
++
++	  /* Make sure the register used to hold the function address is not
++	     cleared.  */
++	  address = RTVEC_ELT (XVEC (unspec, 0), 0);
++	  gcc_assert (MEM_P (address));
++	  gcc_assert (REG_P (XEXP (address, 0)));
++	  to_clear_mask &= ~(1LL << REGNO (XEXP (address, 0)));
++
++	  /* Set basic block of call insn so that df rescan is performed on
++	     insns inserted here.  */
++	  set_block_for_insn (insn, bb);
++	  df_set_flags (DF_DEFER_INSN_RESCAN);
++	  start_sequence ();
++
++	  /* Make sure the scheduler doesn't schedule other insns beyond
++	     here.  */
++	  emit_insn (gen_blockage ());
++
++	  /* Walk through all arguments and clear registers appropriately.
++	  */
++	  fntype = TREE_TYPE (MEM_EXPR (address));
++	  arm_init_cumulative_args (&args_so_far_v, fntype, NULL_RTX,
++				    NULL_TREE);
++	  args_so_far = pack_cumulative_args (&args_so_far_v);
++	  FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
+ 	    {
+-	      if (do_pushes)
+-		{
+-		  rtx cop = avoid_constant_pool_reference (op);
++	      rtx arg_rtx;
++	      machine_mode arg_mode = TYPE_MODE (arg_type);
+ 
+-		  /* Casting the address of something to a mode narrower
+-		     than a word can cause avoid_constant_pool_reference()
+-		     to return the pool reference itself.  That's no good to
+-		     us here.  Lets just hope that we can use the
+-		     constant pool value directly.  */
+-		  if (op == cop)
+-		    cop = get_pool_constant (XEXP (op, 0));
++	      if (VOID_TYPE_P (arg_type))
++		continue;
+ 
+-		  push_minipool_fix (insn, address,
+-				     recog_data.operand_loc[opno],
+-				     recog_data.operand_mode[opno], cop);
++	      if (!first_param)
++		arm_function_arg_advance (args_so_far, arg_mode, arg_type,
++					  true);
++
++	      arg_rtx = arm_function_arg (args_so_far, arg_mode, arg_type,
++					  true);
++	      gcc_assert (REG_P (arg_rtx));
++	      to_clear_mask
++		&= ~compute_not_to_clear_mask (arg_type, arg_rtx,
++					       REGNO (arg_rtx),
++					       padding_bits_to_clear_ptr);
++
++	      first_param = false;
++	    }
++
++	  /* Clear padding bits where needed.  */
++	  cleared_reg = XEXP (address, 0);
++	  reg = gen_rtx_REG (SImode, IP_REGNUM);
++	  using_r4 = false;
++	  for (regno = R0_REGNUM; regno < NUM_ARG_REGS; regno++)
++	    {
++	      if (padding_bits_to_clear[regno] == 0)
++		continue;
++
++	      /* If this is a Thumb-1 target copy the address of the function
++		 we are calling from 'r4' into 'ip' such that we can use r4 to
++		 clear the unused bits in the arguments.  */
++	      if (TARGET_THUMB1 && !using_r4)
++		{
++		  using_r4 =  true;
++		  reg = cleared_reg;
++		  emit_move_insn (gen_rtx_REG (SImode, IP_REGNUM),
++					  reg);
++		}
++
++	      tmp = GEN_INT ((((~padding_bits_to_clear[regno]) << 16u) >> 16u));
++	      emit_move_insn (reg, tmp);
++	      /* Also fill the top half of the negated
++		 padding_bits_to_clear.  */
++	      if (((~padding_bits_to_clear[regno]) >> 16) > 0)
++		{
++		  tmp = GEN_INT ((~padding_bits_to_clear[regno]) >> 16);
++		  emit_insn (gen_rtx_SET (gen_rtx_ZERO_EXTRACT (SImode, reg,
++								GEN_INT (16),
++								GEN_INT (16)),
++					  tmp));
+ 		}
+ 
++	      emit_insn (gen_andsi3 (gen_rtx_REG (SImode, regno),
++				     gen_rtx_REG (SImode, regno),
++				     reg));
++
++	    }
++	  if (using_r4)
++	    emit_move_insn (cleared_reg,
++			    gen_rtx_REG (SImode, IP_REGNUM));
++
++	  /* We use right shift and left shift to clear the LSB of the address
++	     we jump to instead of using bic, to avoid having to use an extra
++	     register on Thumb-1.  */
++	  tmp = gen_rtx_LSHIFTRT (SImode, cleared_reg, const1_rtx);
++	  emit_insn (gen_rtx_SET (cleared_reg, tmp));
++	  tmp = gen_rtx_ASHIFT (SImode, cleared_reg, const1_rtx);
++	  emit_insn (gen_rtx_SET (cleared_reg, tmp));
++
++	  /* Clearing all registers that leak before doing a non-secure
++	     call.  */
++	  for (regno = R0_REGNUM; regno <= maxregno; regno++)
++	    {
++	      if (!(to_clear_mask & (1LL << regno)))
++		continue;
++
++	      /* If regno is an even vfp register and its successor is also to
++		 be cleared, use vmov.  */
++	      if (IS_VFP_REGNUM (regno))
++		{
++		  if (TARGET_VFP_DOUBLE
++		      && VFP_REGNO_OK_FOR_DOUBLE (regno)
++		      && to_clear_mask & (1LL << (regno + 1)))
++		    emit_move_insn (gen_rtx_REG (DFmode, regno++),
++				    CONST0_RTX (DFmode));
++		  else
++		    emit_move_insn (gen_rtx_REG (SFmode, regno),
++				    CONST0_RTX (SFmode));
++		}
++	      else
++		emit_move_insn (gen_rtx_REG (SImode, regno), cleared_reg);
+ 	    }
++
++	  seq = get_insns ();
++	  end_sequence ();
++	  emit_insn_before (seq, insn);
++
+ 	}
+     }
+-
+-  return;
+ }
+ 
+ /* Rewrite move insn into subtract of 0 if the condition codes will
+@@ -17627,6 +17258,8 @@ arm_reorg (void)
+   HOST_WIDE_INT address = 0;
+   Mfix * fix;
+ 
++  if (use_cmse)
++    cmse_nonsecure_call_clear_caller_saved ();
+   if (TARGET_THUMB1)
+     thumb1_reorg ();
+   else if (TARGET_THUMB2)
+@@ -17639,6 +17272,11 @@ arm_reorg (void)
+   if (!optimize)
+     split_all_insns_noflow ();
+ 
++  /* Make sure we do not attempt to create a literal pool even though it should
++     no longer be necessary to create any.  */
++  if (arm_disable_literal_pool)
++    return ;
++
+   minipool_fix_head = minipool_fix_tail = NULL;
+ 
+   /* The first insn must always be a note, or the code below won't
+@@ -17999,6 +17637,23 @@ vfp_emit_fstmd (int base_reg, int count)
+   return count * 8;
+ }
+ 
++/* Returns true if -mcmse has been passed and the function pointed to by 'addr'
++   has the cmse_nonsecure_call attribute and returns false otherwise.  */
++
++bool
++detect_cmse_nonsecure_call (tree addr)
++{
++  if (!addr)
++    return FALSE;
++
++  tree fntype = TREE_TYPE (addr);
++  if (use_cmse && lookup_attribute ("cmse_nonsecure_call",
++				    TYPE_ATTRIBUTES (fntype)))
++    return TRUE;
++  return FALSE;
++}
++
++
+ /* Emit a call instruction with pattern PAT.  ADDR is the address of
+    the call target.  */
+ 
+@@ -18658,6 +18313,8 @@ output_move_vfp (rtx *operands)
+   rtx reg, mem, addr, ops[2];
+   int load = REG_P (operands[0]);
+   int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
++  int sp = (!TARGET_VFP_FP16INST
++	    || GET_MODE_SIZE (GET_MODE (operands[0])) == 4);
+   int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT;
+   const char *templ;
+   char buff[50];
+@@ -18670,8 +18327,10 @@ output_move_vfp (rtx *operands)
+ 
+   gcc_assert (REG_P (reg));
+   gcc_assert (IS_VFP_REGNUM (REGNO (reg)));
+-  gcc_assert (mode == SFmode
++  gcc_assert ((mode == HFmode && TARGET_HARD_FLOAT)
++	      || mode == SFmode
+ 	      || mode == DFmode
++	      || mode == HImode
+ 	      || mode == SImode
+ 	      || mode == DImode
+               || (TARGET_NEON && VALID_NEON_DREG_MODE (mode)));
+@@ -18702,7 +18361,7 @@ output_move_vfp (rtx *operands)
+ 
+   sprintf (buff, templ,
+ 	   load ? "ld" : "st",
+-	   dp ? "64" : "32",
++	   dp ? "64" : sp ? "32" : "16",
+ 	   dp ? "P" : "",
+ 	   integer_p ? "\t%@ int" : "");
+   output_asm_insn (buff, ops);
+@@ -19128,7 +18787,8 @@ shift_op (rtx op, HOST_WIDE_INT *amountp)
+ 	  return NULL;
+ 	}
+ 
+-      *amountp = int_log2 (*amountp);
++      *amountp = exact_log2 (*amountp);
++      gcc_assert (IN_RANGE (*amountp, 0, 31));
+       return ARM_LSL_NAME;
+ 
+     default:
+@@ -19160,22 +18820,6 @@ shift_op (rtx op, HOST_WIDE_INT *amountp)
+   return mnem;
+ }
+ 
+-/* Obtain the shift from the POWER of two.  */
+-
+-static HOST_WIDE_INT
+-int_log2 (HOST_WIDE_INT power)
+-{
+-  HOST_WIDE_INT shift = 0;
+-
+-  while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
+-    {
+-      gcc_assert (shift <= 31);
+-      shift++;
+-    }
+-
+-  return shift;
+-}
+-
+ /* Output a .ascii pseudo-op, keeping track of lengths.  This is
+    because /bin/as is horribly restrictive.  The judgement about
+    whether or not each character is 'printable' (and can be output as
+@@ -19532,7 +19176,7 @@ arm_get_vfp_saved_size (void)
+ 
+   saved = 0;
+   /* Space for saved VFP registers.  */
+-  if (TARGET_HARD_FLOAT && TARGET_VFP)
++  if (TARGET_HARD_FLOAT)
+     {
+       count = 0;
+       for (regno = FIRST_VFP_REGNUM;
+@@ -19621,6 +19265,7 @@ output_return_instruction (rtx operand, bool really_return, bool reverse,
+ 	 (e.g. interworking) then we can load the return address
+ 	 directly into the PC.  Otherwise we must load it into LR.  */
+       if (really_return
++	  && !IS_CMSE_ENTRY (func_type)
+ 	  && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
+ 	return_reg = reg_names[PC_REGNUM];
+       else
+@@ -19761,8 +19406,45 @@ output_return_instruction (rtx operand, bool really_return, bool reverse,
+ 	  break;
+ 
+ 	default:
++	  if (IS_CMSE_ENTRY (func_type))
++	    {
++	      /* Check if we have to clear the 'GE bits' which is only used if
++		 parallel add and subtraction instructions are available.  */
++	      if (TARGET_INT_SIMD)
++		snprintf (instr, sizeof (instr),
++			  "msr%s\tAPSR_nzcvqg, %%|lr", conditional);
++	      else
++		snprintf (instr, sizeof (instr),
++			  "msr%s\tAPSR_nzcvq, %%|lr", conditional);
++
++	      output_asm_insn (instr, & operand);
++	      if (TARGET_HARD_FLOAT && !TARGET_THUMB1)
++		{
++		  /* Clear the cumulative exception-status bits (0-4,7) and the
++		     condition code bits (28-31) of the FPSCR.  We need to
++		     remember to clear the first scratch register used (IP) and
++		     save and restore the second (r4).  */
++		  snprintf (instr, sizeof (instr), "push\t{%%|r4}");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "vmrs\t%%|ip, fpscr");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "movw\t%%|r4, #65376");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "movt\t%%|r4, #4095");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "and\t%%|ip, %%|r4");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "vmsr\tfpscr, %%|ip");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "pop\t{%%|r4}");
++		  output_asm_insn (instr, & operand);
++		  snprintf (instr, sizeof (instr), "mov\t%%|ip, %%|lr");
++		  output_asm_insn (instr, & operand);
++		}
++	      snprintf (instr, sizeof (instr), "bxns\t%%|lr");
++	    }
+ 	  /* Use bx if it's available.  */
+-	  if (arm_arch5 || arm_arch4t)
++	  else if (arm_arch5 || arm_arch4t)
+ 	    sprintf (instr, "bx%s\t%%|lr", conditional);
+ 	  else
+ 	    sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
+@@ -19775,6 +19457,44 @@ output_return_instruction (rtx operand, bool really_return, bool reverse,
+   return "";
+ }
+ 
++/* Output in FILE asm statements needed to declare the NAME of the function
++   defined by its DECL node.  */
++
++void
++arm_asm_declare_function_name (FILE *file, const char *name, tree decl)
++{
++  size_t cmse_name_len;
++  char *cmse_name = 0;
++  char cmse_prefix[] = "__acle_se_";
++
++  /* When compiling with ARMv8-M Security Extensions enabled, we should print an
++     extra function label for each function with the 'cmse_nonsecure_entry'
++     attribute.  This extra function label should be prepended with
++     '__acle_se_', telling the linker that it needs to create secure gateway
++     veneers for this function.  */
++  if (use_cmse && lookup_attribute ("cmse_nonsecure_entry",
++				    DECL_ATTRIBUTES (decl)))
++    {
++      cmse_name_len = sizeof (cmse_prefix) + strlen (name);
++      cmse_name = XALLOCAVEC (char, cmse_name_len);
++      snprintf (cmse_name, cmse_name_len, "%s%s", cmse_prefix, name);
++      targetm.asm_out.globalize_label (file, cmse_name);
++
++      ARM_DECLARE_FUNCTION_NAME (file, cmse_name, decl);
++      ASM_OUTPUT_TYPE_DIRECTIVE (file, cmse_name, "function");
++    }
++
++  ARM_DECLARE_FUNCTION_NAME (file, name, decl);
++  ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
++  ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
++  ASM_OUTPUT_LABEL (file, name);
++
++  if (cmse_name)
++    ASM_OUTPUT_LABEL (file, cmse_name);
++
++  ARM_OUTPUT_FN_UNWIND (file, TRUE);
++}
++
+ /* Write the function name into the code section, directly preceding
+    the function prologue.
+ 
+@@ -19824,10 +19544,6 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
+ {
+   unsigned long func_type;
+ 
+-  /* ??? Do we want to print some of the below anyway?  */
+-  if (TARGET_THUMB1)
+-    return;
+-
+   /* Sanity check.  */
+   gcc_assert (!arm_ccfsm_state && !arm_target_insn);
+ 
+@@ -19862,6 +19578,8 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
+     asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
+   if (IS_STACKALIGN (func_type))
+     asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
++  if (IS_CMSE_ENTRY (func_type))
++    asm_fprintf (f, "\t%@ Non-secure entry function: called from non-secure code.\n");
+ 
+   asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
+ 	       crtl->args.size,
+@@ -20531,7 +20249,7 @@ arm_emit_vfp_multi_reg_pop (int first_reg, int num_regs, rtx base_reg)
+   REG_NOTES (par) = dwarf;
+ 
+   /* Make sure cfa doesn't leave with IP_REGNUM to allow unwinding fron FP.  */
+-  if (TARGET_VFP && REGNO (base_reg) == IP_REGNUM)
++  if (REGNO (base_reg) == IP_REGNUM)
+     {
+       RTX_FRAME_RELATED_P (par) = 1;
+       add_reg_note (par, REG_CFA_DEF_CFA, hard_frame_pointer_rtx);
+@@ -20992,7 +20710,7 @@ arm_get_frame_offsets (void)
+       func_type = arm_current_func_type ();
+       /* Space for saved VFP registers.  */
+       if (! IS_VOLATILE (func_type)
+-	  && TARGET_HARD_FLOAT && TARGET_VFP)
++	  && TARGET_HARD_FLOAT)
+ 	saved += arm_get_vfp_saved_size ();
+     }
+   else /* TARGET_THUMB1 */
+@@ -21213,7 +20931,7 @@ arm_save_coproc_regs(void)
+ 	saved_size += 8;
+       }
+ 
+-  if (TARGET_HARD_FLOAT && TARGET_VFP)
++  if (TARGET_HARD_FLOAT)
+     {
+       start_reg = FIRST_VFP_REGNUM;
+ 
+@@ -22826,7 +22544,7 @@ arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
+       sprintf (buf, "%s.%.5u",
+ 	       is_ctor ? ".init_array" : ".fini_array",
+ 	       priority);
+-      s = get_section (buf, SECTION_WRITE, NULL_TREE);
++      s = get_section (buf, SECTION_WRITE | SECTION_NOTYPE, NULL_TREE);
+     }
+   else if (is_ctor)
+     s = ctors_section;
+@@ -22999,6 +22717,8 @@ maybe_get_arm_condition_code (rtx comparison)
+ 	{
+ 	case LTU: return ARM_CS;
+ 	case GEU: return ARM_CC;
++	case NE: return ARM_CS;
++	case EQ: return ARM_CC;
+ 	default: return ARM_NV;
+ 	}
+ 
+@@ -23024,6 +22744,14 @@ maybe_get_arm_condition_code (rtx comparison)
+ 	default: return ARM_NV;
+ 	}
+ 
++    case CC_Vmode:
++      switch (comp_code)
++	{
++	case NE: return ARM_VS;
++	case EQ: return ARM_VC;
++	default: return ARM_NV;
++	}
++
+     case CCmode:
+       switch (comp_code)
+ 	{
+@@ -23454,7 +23182,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+ {
+   if (GET_MODE_CLASS (mode) == MODE_CC)
+     return (regno == CC_REGNUM
+-	    || (TARGET_HARD_FLOAT && TARGET_VFP
++	    || (TARGET_HARD_FLOAT
+ 		&& regno == VFPCC_REGNUM));
+ 
+   if (regno == CC_REGNUM && GET_MODE_CLASS (mode) != MODE_CC)
+@@ -23468,8 +23196,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+        start of an even numbered register pair.  */
+     return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
+ 
+-  if (TARGET_HARD_FLOAT && TARGET_VFP
+-      && IS_VFP_REGNUM (regno))
++  if (TARGET_HARD_FLOAT && IS_VFP_REGNUM (regno))
+     {
+       if (mode == SFmode || mode == SImode)
+ 	return VFP_REGNO_OK_FOR_SINGLE (regno);
+@@ -23477,10 +23204,12 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+       if (mode == DFmode)
+ 	return VFP_REGNO_OK_FOR_DOUBLE (regno);
+ 
+-      /* VFP registers can hold HFmode values, but there is no point in
+-	 putting them there unless we have hardware conversion insns. */
+       if (mode == HFmode)
+-	return TARGET_FP16 && VFP_REGNO_OK_FOR_SINGLE (regno);
++	return VFP_REGNO_OK_FOR_SINGLE (regno);
++
++      /* VFP registers can hold HImode values.  */
++      if (mode == HImode)
++	return VFP_REGNO_OK_FOR_SINGLE (regno);
+ 
+       if (TARGET_NEON)
+         return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno))
+@@ -23684,26 +23413,6 @@ arm_debugger_arg_offset (int value, rtx addr)
+   return value;
+ }
+ 
+-/* Implement TARGET_INVALID_PARAMETER_TYPE.  */
+-
+-static const char *
+-arm_invalid_parameter_type (const_tree t)
+-{
+-  if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16)
+-    return N_("function parameters cannot have __fp16 type");
+-  return NULL;
+-}
+-
+-/* Implement TARGET_INVALID_PARAMETER_TYPE.  */
+-
+-static const char *
+-arm_invalid_return_type (const_tree t)
+-{
+-  if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16)
+-    return N_("functions cannot return __fp16 type");
+-  return NULL;
+-}
+-
+ /* Implement TARGET_PROMOTED_TYPE.  */
+ 
+ static tree
+@@ -23943,8 +23652,8 @@ thumb_pop (FILE *f, unsigned long mask)
+   if (mask & (1 << PC_REGNUM))
+     {
+       /* Catch popping the PC.  */
+-      if (TARGET_INTERWORK || TARGET_BACKTRACE
+-	  || crtl->calls_eh_return)
++      if (TARGET_INTERWORK || TARGET_BACKTRACE || crtl->calls_eh_return
++	  || IS_CMSE_ENTRY (arm_current_func_type ()))
+ 	{
+ 	  /* The PC is never poped directly, instead
+ 	     it is popped into r3 and then BX is used.  */
+@@ -24005,7 +23714,14 @@ thumb_exit (FILE *f, int reg_containing_return_addr)
+       if (crtl->calls_eh_return)
+ 	asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
+ 
+-      asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
++      if (IS_CMSE_ENTRY (arm_current_func_type ()))
++	{
++	  asm_fprintf (f, "\tmsr\tAPSR_nzcvq, %r\n",
++		       reg_containing_return_addr);
++	  asm_fprintf (f, "\tbxns\t%r\n", reg_containing_return_addr);
++	}
++      else
++	asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
+       return;
+     }
+   /* Otherwise if we are not supporting interworking and we have not created
+@@ -24014,7 +23730,8 @@ thumb_exit (FILE *f, int reg_containing_return_addr)
+   else if (!TARGET_INTERWORK
+ 	   && !TARGET_BACKTRACE
+ 	   && !is_called_in_ARM_mode (current_function_decl)
+-	   && !crtl->calls_eh_return)
++	   && !crtl->calls_eh_return
++	   && !IS_CMSE_ENTRY (arm_current_func_type ()))
+     {
+       asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
+       return;
+@@ -24237,7 +23954,21 @@ thumb_exit (FILE *f, int reg_containing_return_addr)
+     asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
+ 
+   /* Return to caller.  */
+-  asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
++  if (IS_CMSE_ENTRY (arm_current_func_type ()))
++    {
++      /* This is for the cases where LR is not being used to contain the return
++         address.  It may therefore contain information that we might not want
++	 to leak, hence it must be cleared.  The value in R0 will never be a
++	 secret at this point, so it is safe to use it, see the clearing code
++	 in 'cmse_nonsecure_entry_clear_before_return'.  */
++      if (reg_containing_return_addr != LR_REGNUM)
++	asm_fprintf (f, "\tmov\tlr, r0\n");
++
++      asm_fprintf (f, "\tmsr\tAPSR_nzcvq, %r\n", reg_containing_return_addr);
++      asm_fprintf (f, "\tbxns\t%r\n", reg_containing_return_addr);
++    }
++  else
++    asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
+ }
+ 
+ /* Scan INSN just before assembler is output for it.
+@@ -25067,39 +24798,182 @@ thumb1_expand_prologue (void)
+ 	    if (live_regs_mask & (1 << regno))
+ 	      break;
+ 
+-	  gcc_assert(regno <= LAST_LO_REGNUM);
++	  gcc_assert(regno <= LAST_LO_REGNUM);
++
++	  reg = gen_rtx_REG (SImode, regno);
++
++	  emit_insn (gen_movsi (reg, GEN_INT (- amount)));
++
++	  insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
++					stack_pointer_rtx, reg));
++
++	  dwarf = gen_rtx_SET (stack_pointer_rtx,
++			       plus_constant (Pmode, stack_pointer_rtx,
++					      -amount));
++	  add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
++	  RTX_FRAME_RELATED_P (insn) = 1;
++	}
++    }
++
++  if (frame_pointer_needed)
++    thumb_set_frame_pointer (offsets);
++
++  /* If we are profiling, make sure no instructions are scheduled before
++     the call to mcount.  Similarly if the user has requested no
++     scheduling in the prolog.  Similarly if we want non-call exceptions
++     using the EABI unwinder, to prevent faulting instructions from being
++     swapped with a stack adjustment.  */
++  if (crtl->profile || !TARGET_SCHED_PROLOG
++      || (arm_except_unwind_info (&global_options) == UI_TARGET
++	  && cfun->can_throw_non_call_exceptions))
++    emit_insn (gen_blockage ());
++
++  cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
++  if (live_regs_mask & 0xff)
++    cfun->machine->lr_save_eliminated = 0;
++}
++
++/* Clear caller saved registers not used to pass return values and leaked
++   condition flags before exiting a cmse_nonsecure_entry function.  */
++
++void
++cmse_nonsecure_entry_clear_before_return (void)
++{
++  uint64_t to_clear_mask[2];
++  uint32_t padding_bits_to_clear = 0;
++  uint32_t * padding_bits_to_clear_ptr = &padding_bits_to_clear;
++  int regno, maxregno = IP_REGNUM;
++  tree result_type;
++  rtx result_rtl;
++
++  to_clear_mask[0] = (1ULL << (NUM_ARG_REGS)) - 1;
++  to_clear_mask[0] |= (1ULL << IP_REGNUM);
++
++  /* If we are not dealing with -mfloat-abi=soft we will need to clear VFP
++     registers.  We also check that TARGET_HARD_FLOAT and !TARGET_THUMB1 hold
++     to make sure the instructions used to clear them are present.  */
++  if (TARGET_HARD_FLOAT && !TARGET_THUMB1)
++    {
++      uint64_t float_mask = (1ULL << (D7_VFP_REGNUM + 1)) - 1;
++      maxregno = LAST_VFP_REGNUM;
++
++      float_mask &= ~((1ULL << FIRST_VFP_REGNUM) - 1);
++      to_clear_mask[0] |= float_mask;
++
++      float_mask = (1ULL << (maxregno - 63)) - 1;
++      to_clear_mask[1] = float_mask;
++
++      /* Make sure we don't clear the two scratch registers used to clear the
++	 relevant FPSCR bits in output_return_instruction.  */
++      emit_use (gen_rtx_REG (SImode, IP_REGNUM));
++      to_clear_mask[0] &= ~(1ULL << IP_REGNUM);
++      emit_use (gen_rtx_REG (SImode, 4));
++      to_clear_mask[0] &= ~(1ULL << 4);
++    }
++
++  /* If the user has defined registers to be caller saved, these are no longer
++     restored by the function before returning and must thus be cleared for
++     security purposes.  */
++  for (regno = NUM_ARG_REGS; regno < LAST_VFP_REGNUM; regno++)
++    {
++      /* We do not touch registers that can be used to pass arguments as per
++	 the AAPCS, since these should never be made callee-saved by user
++	 options.  */
++      if (IN_RANGE (regno, FIRST_VFP_REGNUM, D7_VFP_REGNUM))
++	continue;
++      if (IN_RANGE (regno, IP_REGNUM, PC_REGNUM))
++	continue;
++      if (call_used_regs[regno])
++	to_clear_mask[regno / 64] |= (1ULL << (regno % 64));
++    }
++
++  /* Make sure we do not clear the registers used to return the result in.  */
++  result_type = TREE_TYPE (DECL_RESULT (current_function_decl));
++  if (!VOID_TYPE_P (result_type))
++    {
++      result_rtl = arm_function_value (result_type, current_function_decl, 0);
++
++      /* No need to check that we return in registers, because we don't
++	 support returning on stack yet.  */
++      to_clear_mask[0]
++	&= ~compute_not_to_clear_mask (result_type, result_rtl, 0,
++				       padding_bits_to_clear_ptr);
++    }
++
++  if (padding_bits_to_clear != 0)
++    {
++      rtx reg_rtx;
++      /* Padding bits to clear is not 0 so we know we are dealing with
++	 returning a composite type, which only uses r0.  Let's make sure that
++	 r1-r3 is cleared too, we will use r1 as a scratch register.  */
++      gcc_assert ((to_clear_mask[0] & 0xe) == 0xe);
+ 
+-	  reg = gen_rtx_REG (SImode, regno);
++      reg_rtx = gen_rtx_REG (SImode, R1_REGNUM);
+ 
+-	  emit_insn (gen_movsi (reg, GEN_INT (- amount)));
++      /* Fill the lower half of the negated padding_bits_to_clear.  */
++      emit_move_insn (reg_rtx,
++		      GEN_INT ((((~padding_bits_to_clear) << 16u) >> 16u)));
+ 
+-	  insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
+-					stack_pointer_rtx, reg));
++      /* Also fill the top half of the negated padding_bits_to_clear.  */
++      if (((~padding_bits_to_clear) >> 16) > 0)
++	emit_insn (gen_rtx_SET (gen_rtx_ZERO_EXTRACT (SImode, reg_rtx,
++						      GEN_INT (16),
++						      GEN_INT (16)),
++				GEN_INT ((~padding_bits_to_clear) >> 16)));
+ 
+-	  dwarf = gen_rtx_SET (stack_pointer_rtx,
+-			       plus_constant (Pmode, stack_pointer_rtx,
+-					      -amount));
+-	  add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
+-	  RTX_FRAME_RELATED_P (insn) = 1;
+-	}
++      emit_insn (gen_andsi3 (gen_rtx_REG (SImode, R0_REGNUM),
++			   gen_rtx_REG (SImode, R0_REGNUM),
++			   reg_rtx));
+     }
+ 
+-  if (frame_pointer_needed)
+-    thumb_set_frame_pointer (offsets);
+-
+-  /* If we are profiling, make sure no instructions are scheduled before
+-     the call to mcount.  Similarly if the user has requested no
+-     scheduling in the prolog.  Similarly if we want non-call exceptions
+-     using the EABI unwinder, to prevent faulting instructions from being
+-     swapped with a stack adjustment.  */
+-  if (crtl->profile || !TARGET_SCHED_PROLOG
+-      || (arm_except_unwind_info (&global_options) == UI_TARGET
+-	  && cfun->can_throw_non_call_exceptions))
+-    emit_insn (gen_blockage ());
++  for (regno = R0_REGNUM; regno <= maxregno; regno++)
++    {
++      if (!(to_clear_mask[regno / 64] & (1ULL << (regno % 64))))
++	continue;
+ 
+-  cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
+-  if (live_regs_mask & 0xff)
+-    cfun->machine->lr_save_eliminated = 0;
++      if (IS_VFP_REGNUM (regno))
++	{
++	  /* If regno is an even vfp register and its successor is also to
++	     be cleared, use vmov.  */
++	  if (TARGET_VFP_DOUBLE
++	      && VFP_REGNO_OK_FOR_DOUBLE (regno)
++	      && to_clear_mask[regno / 64] & (1ULL << ((regno % 64) + 1)))
++	    {
++	      emit_move_insn (gen_rtx_REG (DFmode, regno),
++			      CONST1_RTX (DFmode));
++	      emit_use (gen_rtx_REG (DFmode, regno));
++	      regno++;
++	    }
++	  else
++	    {
++	      emit_move_insn (gen_rtx_REG (SFmode, regno),
++			      CONST1_RTX (SFmode));
++	      emit_use (gen_rtx_REG (SFmode, regno));
++	    }
++	}
++      else
++	{
++	  if (TARGET_THUMB1)
++	    {
++	      if (regno == R0_REGNUM)
++		emit_move_insn (gen_rtx_REG (SImode, regno),
++				const0_rtx);
++	      else
++		/* R0 has either been cleared before, see code above, or it
++		   holds a return value, either way it is not secret
++		   information.  */
++		emit_move_insn (gen_rtx_REG (SImode, regno),
++				gen_rtx_REG (SImode, R0_REGNUM));
++	      emit_use (gen_rtx_REG (SImode, regno));
++	    }
++	  else
++	    {
++	      emit_move_insn (gen_rtx_REG (SImode, regno),
++			      gen_rtx_REG (SImode, LR_REGNUM));
++	      emit_use (gen_rtx_REG (SImode, regno));
++	    }
++	}
++    }
+ }
+ 
+ /* Generate pattern *pop_multiple_with_stack_update_and_return if single
+@@ -25123,6 +24997,12 @@ thumb2_expand_return (bool simple_return)
+ 
+   if (!simple_return && saved_regs_mask)
+     {
++      /* TODO: Verify that this path is never taken for cmse_nonsecure_entry
++	 functions or adapt code to handle according to ACLE.  This path should
++	 not be reachable for cmse_nonsecure_entry functions though we prefer
++	 to assert it for now to ensure that future code changes do not silently
++	 change this behavior.  */
++      gcc_assert (!IS_CMSE_ENTRY (arm_current_func_type ()));
+       if (num_regs == 1)
+         {
+           rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
+@@ -25145,6 +25025,8 @@ thumb2_expand_return (bool simple_return)
+     }
+   else
+     {
++      if (IS_CMSE_ENTRY (arm_current_func_type ()))
++	cmse_nonsecure_entry_clear_before_return ();
+       emit_jump_insn (simple_return_rtx);
+     }
+ }
+@@ -25203,6 +25085,10 @@ thumb1_expand_epilogue (void)
+ 
+   if (! df_regs_ever_live_p (LR_REGNUM))
+     emit_use (gen_rtx_REG (SImode, LR_REGNUM));
++
++  /* Clear all caller-saved regs that are not used to return.  */
++  if (IS_CMSE_ENTRY (arm_current_func_type ()))
++    cmse_nonsecure_entry_clear_before_return ();
+ }
+ 
+ /* Epilogue code for APCS frame.  */
+@@ -25237,7 +25123,7 @@ arm_expand_epilogue_apcs_frame (bool really_return)
+         floats_from_frame += 4;
+       }
+ 
+-  if (TARGET_HARD_FLOAT && TARGET_VFP)
++  if (TARGET_HARD_FLOAT)
+     {
+       int start_reg;
+       rtx ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
+@@ -25483,7 +25369,7 @@ arm_expand_epilogue (bool really_return)
+         }
+     }
+ 
+-  if (TARGET_HARD_FLOAT && TARGET_VFP)
++  if (TARGET_HARD_FLOAT)
+     {
+       /* Generate VFP register multi-pop.  */
+       int end_reg = LAST_VFP_REGNUM + 1;
+@@ -25540,6 +25426,7 @@ arm_expand_epilogue (bool really_return)
+ 
+       if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED
+           && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
++	  && !IS_CMSE_ENTRY (func_type)
+           && !IS_STACKALIGN (func_type)
+           && really_return
+           && crtl->args.pretend_args_size == 0
+@@ -25636,6 +25523,14 @@ arm_expand_epilogue (bool really_return)
+ 				   stack_pointer_rtx, stack_pointer_rtx);
+     }
+ 
++    /* Clear all caller-saved regs that are not used to return.  */
++    if (IS_CMSE_ENTRY (arm_current_func_type ()))
++      {
++	/* CMSE_ENTRY always returns.  */
++	gcc_assert (really_return);
++	cmse_nonsecure_entry_clear_before_return ();
++      }
++
+   if (!really_return)
+     return;
+ 
+@@ -25932,13 +25827,6 @@ thumb_reload_out_hi (rtx *operands)
+   emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
+ }
+ 
+-/* Handle reading a half-word from memory during reload.  */
+-void
+-thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
+-{
+-  gcc_unreachable ();
+-}
+-
+ /* Return the length of a function name prefix
+     that starts with the character 'c'.  */
+ static int
+@@ -26008,46 +25896,55 @@ arm_emit_eabi_attribute (const char *name, int num, int val)
+ void
+ arm_print_tune_info (void)
+ {
+-  asm_fprintf (asm_out_file, "\t@.tune parameters\n");
+-  asm_fprintf (asm_out_file, "\t\t@constant_limit:\t%d\n",
++  asm_fprintf (asm_out_file, "\t" ASM_COMMENT_START ".tune parameters\n");
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "constant_limit:\t%d\n",
+ 	       current_tune->constant_limit);
+-  asm_fprintf (asm_out_file, "\t\t@max_insns_skipped:\t%d\n",
+-	       current_tune->max_insns_skipped);
+-  asm_fprintf (asm_out_file, "\t\t@prefetch.num_slots:\t%d\n",
+-	       current_tune->prefetch.num_slots);
+-  asm_fprintf (asm_out_file, "\t\t@prefetch.l1_cache_size:\t%d\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++	       "max_insns_skipped:\t%d\n", current_tune->max_insns_skipped);
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++	       "prefetch.num_slots:\t%d\n", current_tune->prefetch.num_slots);
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++	       "prefetch.l1_cache_size:\t%d\n",
+ 	       current_tune->prefetch.l1_cache_size);
+-  asm_fprintf (asm_out_file, "\t\t@prefetch.l1_cache_line_size:\t%d\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++	       "prefetch.l1_cache_line_size:\t%d\n",
+ 	       current_tune->prefetch.l1_cache_line_size);
+-  asm_fprintf (asm_out_file, "\t\t@prefer_constant_pool:\t%d\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++	       "prefer_constant_pool:\t%d\n",
+ 	       (int) current_tune->prefer_constant_pool);
+-  asm_fprintf (asm_out_file, "\t\t@branch_cost:\t(s:speed, p:predictable)\n");
+-  asm_fprintf (asm_out_file, "\t\t\t\ts&p\tcost\n");
+-  asm_fprintf (asm_out_file, "\t\t\t\t00\t%d\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++	       "branch_cost:\t(s:speed, p:predictable)\n");
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "\t\ts&p\tcost\n");
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "\t\t00\t%d\n",
+ 	       current_tune->branch_cost (false, false));
+-  asm_fprintf (asm_out_file, "\t\t\t\t01\t%d\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "\t\t01\t%d\n",
+ 	       current_tune->branch_cost (false, true));
+-  asm_fprintf (asm_out_file, "\t\t\t\t10\t%d\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "\t\t10\t%d\n",
+ 	       current_tune->branch_cost (true, false));
+-  asm_fprintf (asm_out_file, "\t\t\t\t11\t%d\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "\t\t11\t%d\n",
+ 	       current_tune->branch_cost (true, true));
+-  asm_fprintf (asm_out_file, "\t\t@prefer_ldrd_strd:\t%d\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++	       "prefer_ldrd_strd:\t%d\n",
+ 	       (int) current_tune->prefer_ldrd_strd);
+-  asm_fprintf (asm_out_file, "\t\t@logical_op_non_short_circuit:\t[%d,%d]\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++	       "logical_op_non_short_circuit:\t[%d,%d]\n",
+ 	       (int) current_tune->logical_op_non_short_circuit_thumb,
+ 	       (int) current_tune->logical_op_non_short_circuit_arm);
+-  asm_fprintf (asm_out_file, "\t\t@prefer_neon_for_64bits:\t%d\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++	       "prefer_neon_for_64bits:\t%d\n",
+ 	       (int) current_tune->prefer_neon_for_64bits);
+-  asm_fprintf (asm_out_file,
+-	       "\t\t@disparage_flag_setting_t16_encodings:\t%d\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++	       "disparage_flag_setting_t16_encodings:\t%d\n",
+ 	       (int) current_tune->disparage_flag_setting_t16_encodings);
+-  asm_fprintf (asm_out_file, "\t\t@string_ops_prefer_neon:\t%d\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++	       "string_ops_prefer_neon:\t%d\n",
+ 	       (int) current_tune->string_ops_prefer_neon);
+-  asm_fprintf (asm_out_file, "\t\t@max_insns_inline_memset:\t%d\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++	       "max_insns_inline_memset:\t%d\n",
+ 	       current_tune->max_insns_inline_memset);
+-  asm_fprintf (asm_out_file, "\t\t@fusible_ops:\t%u\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "fusible_ops:\t%u\n",
+ 	       current_tune->fusible_ops);
+-  asm_fprintf (asm_out_file, "\t\t@sched_autopref:\t%d\n",
++  asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "sched_autopref:\t%d\n",
+ 	       (int) current_tune->sched_autopref);
+ }
+ 
+@@ -26076,7 +25973,7 @@ arm_file_start (void)
+ 	      const char* pos = strchr (arm_selected_arch->name, '+');
+ 	      if (pos)
+ 		{
+-		  char buf[15];
++		  char buf[32];
+ 		  gcc_assert (strlen (arm_selected_arch->name)
+ 			      <= sizeof (buf) / sizeof (*pos));
+ 		  strncpy (buf, arm_selected_arch->name,
+@@ -26101,7 +25998,7 @@ arm_file_start (void)
+       if (print_tune_info)
+ 	arm_print_tune_info ();
+ 
+-      if (! TARGET_SOFT_FLOAT && TARGET_VFP)
++      if (! TARGET_SOFT_FLOAT)
+ 	{
+ 	  if (TARGET_HARD_FLOAT && TARGET_VFP_SINGLE)
+ 	    arm_emit_eabi_attribute ("Tag_ABI_HardFP_use", 27, 1);
+@@ -26218,11 +26115,10 @@ arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
+ 
+ /* Output code to add DELTA to the first argument, and then jump
+    to FUNCTION.  Used for C++ multiple inheritance.  */
++
+ static void
+-arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+-		     HOST_WIDE_INT delta,
+-		     HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
+-		     tree function)
++arm_thumb1_mi_thunk (FILE *file, tree, HOST_WIDE_INT delta,
++		     HOST_WIDE_INT, tree function)
+ {
+   static int thunk_label = 0;
+   char label[256];
+@@ -26363,6 +26259,76 @@ arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+   final_end_function ();
+ }
+ 
++/* MI thunk handling for TARGET_32BIT.  */
++
++static void
++arm32_output_mi_thunk (FILE *file, tree, HOST_WIDE_INT delta,
++		       HOST_WIDE_INT vcall_offset, tree function)
++{
++  /* On ARM, this_regno is R0 or R1 depending on
++     whether the function returns an aggregate or not.
++  */
++  int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)),
++				       function)
++		    ? R1_REGNUM : R0_REGNUM);
++
++  rtx temp = gen_rtx_REG (Pmode, IP_REGNUM);
++  rtx this_rtx = gen_rtx_REG (Pmode, this_regno);
++  reload_completed = 1;
++  emit_note (NOTE_INSN_PROLOGUE_END);
++
++  /* Add DELTA to THIS_RTX.  */
++  if (delta != 0)
++    arm_split_constant (PLUS, Pmode, NULL_RTX,
++			delta, this_rtx, this_rtx, false);
++
++  /* Add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX.  */
++  if (vcall_offset != 0)
++    {
++      /* Load *THIS_RTX.  */
++      emit_move_insn (temp, gen_rtx_MEM (Pmode, this_rtx));
++      /* Compute *THIS_RTX + VCALL_OFFSET.  */
++      arm_split_constant (PLUS, Pmode, NULL_RTX, vcall_offset, temp, temp,
++			  false);
++      /* Compute *(*THIS_RTX + VCALL_OFFSET).  */
++      emit_move_insn (temp, gen_rtx_MEM (Pmode, temp));
++      emit_insn (gen_add3_insn (this_rtx, this_rtx, temp));
++    }
++
++  /* Generate a tail call to the target function.  */
++  if (!TREE_USED (function))
++    {
++      assemble_external (function);
++      TREE_USED (function) = 1;
++    }
++  rtx funexp = XEXP (DECL_RTL (function), 0);
++  funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
++  rtx_insn * insn = emit_call_insn (gen_sibcall (funexp, const0_rtx, NULL_RTX));
++  SIBLING_CALL_P (insn) = 1;
++
++  insn = get_insns ();
++  shorten_branches (insn);
++  final_start_function (insn, file, 1);
++  final (insn, file, 1);
++  final_end_function ();
++
++  /* Stop pretending this is a post-reload pass.  */
++  reload_completed = 0;
++}
++
++/* Output code to add DELTA to the first argument, and then jump
++   to FUNCTION.  Used for C++ multiple inheritance.  */
++
++static void
++arm_output_mi_thunk (FILE *file, tree thunk, HOST_WIDE_INT delta,
++		     HOST_WIDE_INT vcall_offset, tree function)
++{
++  if (TARGET_32BIT)
++    arm32_output_mi_thunk (file, thunk, delta, vcall_offset, function);
++  else
++    arm_thumb1_mi_thunk (file, thunk, delta, vcall_offset, function);
++}
++
+ int
+ arm_emit_vector_const (FILE *file, rtx x)
+ {
+@@ -27232,17 +27198,24 @@ arm_asm_emit_except_personality (rtx personality)
+   output_addr_const (asm_out_file, personality);
+   fputc ('\n', asm_out_file);
+ }
++#endif /* ARM_UNWIND_INFO */
+ 
+ /* Implement TARGET_ASM_INITIALIZE_SECTIONS.  */
+ 
+ static void
+ arm_asm_init_sections (void)
+ {
++#if ARM_UNWIND_INFO
+   exception_section = get_unnamed_section (0, output_section_asm_op,
+ 					   "\t.handlerdata");
+-}
+ #endif /* ARM_UNWIND_INFO */
+ 
++#ifdef OBJECT_FORMAT_ELF
++  if (target_pure_code)
++    text_section->unnamed.data = "\t.section .text,\"0x20000006\",%progbits";
++#endif
++}
++
+ /* Output unwind directives for the start/end of a function.  */
+ 
+ void
+@@ -27607,7 +27580,7 @@ arm_mangle_type (const_tree type)
+ static const int thumb_core_reg_alloc_order[] =
+ {
+    3,  2,  1,  0,  4,  5,  6,  7,
+-  14, 12,  8,  9, 10, 11
++  12, 14,  8,  9, 10, 11
+ };
+ 
+ /* Adjust register allocation order when compiling for Thumb.  */
+@@ -27753,7 +27726,7 @@ arm_conditional_register_usage (void)
+   if (TARGET_THUMB1)
+     fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1;
+ 
+-  if (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP)
++  if (TARGET_32BIT && TARGET_HARD_FLOAT)
+     {
+       /* VFPv3 registers are disabled when earlier VFP
+ 	 versions are selected due to the definition of
+@@ -27824,7 +27797,7 @@ arm_preferred_rename_class (reg_class_t rclass)
+     return NO_REGS;
+ }
+ 
+-/* Compute the atrribute "length" of insn "*push_multi".
++/* Compute the attribute "length" of insn "*push_multi".
+    So this function MUST be kept in sync with that insn pattern.  */
+ int
+ arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
+@@ -27841,6 +27814,11 @@ arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
+ 
+   /* Thumb2 mode.  */
+   regno = REGNO (first_op);
++  /* For PUSH/STM under Thumb2 mode, we can use 16-bit encodings if the register
++     list is 8-bit.  Normally this means all registers in the list must be
++     LO_REGS, that is (R0 -R7).  If any HI_REGS used, then we must use 32-bit
++     encodings.  There is one exception for PUSH that LR in HI_REGS can be used
++     with 16-bit encoding.  */
+   hi_reg = (REGNO_REG_CLASS (regno) == HI_REGS) && (regno != LR_REGNUM);
+   for (i = 1; i < num_saves && !hi_reg; i++)
+     {
+@@ -27853,6 +27831,56 @@ arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
+   return 4;
+ }
+ 
++/* Compute the attribute "length" of insn.  Currently, this function is used
++   for "*load_multiple_with_writeback", "*pop_multiple_with_return" and
++   "*pop_multiple_with_writeback_and_return".  OPERANDS is the toplevel PARALLEL
++   rtx, RETURN_PC is true if OPERANDS contains return insn.  WRITE_BACK_P is
++   true if OPERANDS contains insn which explicit updates base register.  */
++
++int
++arm_attr_length_pop_multi (rtx *operands, bool return_pc, bool write_back_p)
++{
++  /* ARM mode.  */
++  if (TARGET_ARM)
++    return 4;
++  /* Thumb1 mode.  */
++  if (TARGET_THUMB1)
++    return 2;
++
++  rtx parallel_op = operands[0];
++  /* Initialize to elements number of PARALLEL.  */
++  unsigned indx = XVECLEN (parallel_op, 0) - 1;
++  /* Initialize the value to base register.  */
++  unsigned regno = REGNO (operands[1]);
++  /* Skip return and write back pattern.
++     We only need register pop pattern for later analysis.  */
++  unsigned first_indx = 0;
++  first_indx += return_pc ? 1 : 0;
++  first_indx += write_back_p ? 1 : 0;
++
++  /* A pop operation can be done through LDM or POP.  If the base register is SP
++     and if it's with write back, then a LDM will be alias of POP.  */
++  bool pop_p = (regno == SP_REGNUM && write_back_p);
++  bool ldm_p = !pop_p;
++
++  /* Check base register for LDM.  */
++  if (ldm_p && REGNO_REG_CLASS (regno) == HI_REGS)
++    return 4;
++
++  /* Check each register in the list.  */
++  for (; indx >= first_indx; indx--)
++    {
++      regno = REGNO (XEXP (XVECEXP (parallel_op, 0, indx), 0));
++      /* For POP, PC in HI_REGS can be used with 16-bit encoding.  See similar
++	 comment in arm_attr_length_push_multi.  */
++      if (REGNO_REG_CLASS (regno) == HI_REGS
++	  && (regno != PC_REGNUM || ldm_p))
++	return 4;
++    }
++
++  return 2;
++}
++
+ /* Compute the number of instructions emitted by output_move_double.  */
+ int
+ arm_count_output_move_double_insns (rtx *operands)
+@@ -27884,7 +27912,11 @@ vfp3_const_double_for_fract_bits (rtx operand)
+ 	  HOST_WIDE_INT value = real_to_integer (&r0);
+ 	  value = value & 0xffffffff;
+ 	  if ((value != 0) && ( (value & (value - 1)) == 0))
+-	    return int_log2 (value);
++	    {
++	      int ret = exact_log2 (value);
++	      gcc_assert (IN_RANGE (ret, 0, 31));
++	      return ret;
++	    }
+ 	}
+     }
+   return 0;
+@@ -28024,9 +28056,9 @@ emit_unlikely_jump (rtx insn)
+ void
+ arm_expand_compare_and_swap (rtx operands[])
+ {
+-  rtx bval, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x;
++  rtx bval, bdst, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x;
+   machine_mode mode;
+-  rtx (*gen) (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
++  rtx (*gen) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+ 
+   bval = operands[0];
+   rval = operands[1];
+@@ -28083,43 +28115,54 @@ arm_expand_compare_and_swap (rtx operands[])
+       gcc_unreachable ();
+     }
+ 
+-  emit_insn (gen (rval, mem, oldval, newval, is_weak, mod_s, mod_f));
++  bdst = TARGET_THUMB1 ? bval : gen_rtx_REG (CCmode, CC_REGNUM);
++  emit_insn (gen (bdst, rval, mem, oldval, newval, is_weak, mod_s, mod_f));
+ 
+   if (mode == QImode || mode == HImode)
+     emit_move_insn (operands[1], gen_lowpart (mode, rval));
+ 
+   /* In all cases, we arrange for success to be signaled by Z set.
+      This arrangement allows for the boolean result to be used directly
+-     in a subsequent branch, post optimization.  */
+-  x = gen_rtx_REG (CCmode, CC_REGNUM);
+-  x = gen_rtx_EQ (SImode, x, const0_rtx);
+-  emit_insn (gen_rtx_SET (bval, x));
++     in a subsequent branch, post optimization.  For Thumb-1 targets, the
++     boolean negation of the result is also stored in bval because Thumb-1
++     backend lacks dependency tracking for CC flag due to flag-setting not
++     being represented at RTL level.  */
++  if (TARGET_THUMB1)
++      emit_insn (gen_cstoresi_eq0_thumb1 (bval, bdst));
++  else
++    {
++      x = gen_rtx_EQ (SImode, bdst, const0_rtx);
++      emit_insn (gen_rtx_SET (bval, x));
++    }
+ }
+ 
+ /* Split a compare and swap pattern.  It is IMPLEMENTATION DEFINED whether
+    another memory store between the load-exclusive and store-exclusive can
+    reset the monitor from Exclusive to Open state.  This means we must wait
+    until after reload to split the pattern, lest we get a register spill in
+-   the middle of the atomic sequence.  */
++   the middle of the atomic sequence.  Success of the compare and swap is
++   indicated by the Z flag set for 32bit targets and by neg_bval being zero
++   for Thumb-1 targets (ie. negation of the boolean value returned by
++   atomic_compare_and_swapmode standard pattern in operand 0).  */
+ 
+ void
+ arm_split_compare_and_swap (rtx operands[])
+ {
+-  rtx rval, mem, oldval, newval, scratch;
++  rtx rval, mem, oldval, newval, neg_bval;
+   machine_mode mode;
+   enum memmodel mod_s, mod_f;
+   bool is_weak;
+   rtx_code_label *label1, *label2;
+   rtx x, cond;
+ 
+-  rval = operands[0];
+-  mem = operands[1];
+-  oldval = operands[2];
+-  newval = operands[3];
+-  is_weak = (operands[4] != const0_rtx);
+-  mod_s = memmodel_from_int (INTVAL (operands[5]));
+-  mod_f = memmodel_from_int (INTVAL (operands[6]));
+-  scratch = operands[7];
++  rval = operands[1];
++  mem = operands[2];
++  oldval = operands[3];
++  newval = operands[4];
++  is_weak = (operands[5] != const0_rtx);
++  mod_s = memmodel_from_int (INTVAL (operands[6]));
++  mod_f = memmodel_from_int (INTVAL (operands[7]));
++  neg_bval = TARGET_THUMB1 ? operands[0] : operands[8];
+   mode = GET_MODE (mem);
+ 
+   bool is_armv8_sync = arm_arch8 && is_mm_sync (mod_s);
+@@ -28151,26 +28194,44 @@ arm_split_compare_and_swap (rtx operands[])
+ 
+   arm_emit_load_exclusive (mode, rval, mem, use_acquire);
+ 
+-  cond = arm_gen_compare_reg (NE, rval, oldval, scratch);
+-  x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
+-  x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
+-			    gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
+-  emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
++  /* Z is set to 0 for 32bit targets (resp. rval set to 1) if oldval != rval,
++     as required to communicate with arm_expand_compare_and_swap.  */
++  if (TARGET_32BIT)
++    {
++      cond = arm_gen_compare_reg (NE, rval, oldval, neg_bval);
++      x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
++      x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
++				gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
++      emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
++    }
++  else
++    {
++      emit_move_insn (neg_bval, const1_rtx);
++      cond = gen_rtx_NE (VOIDmode, rval, oldval);
++      if (thumb1_cmpneg_operand (oldval, SImode))
++	emit_unlikely_jump (gen_cbranchsi4_scratch (neg_bval, rval, oldval,
++						    label2, cond));
++      else
++	emit_unlikely_jump (gen_cbranchsi4_insn (cond, rval, oldval, label2));
++    }
+ 
+-  arm_emit_store_exclusive (mode, scratch, mem, newval, use_release);
++  arm_emit_store_exclusive (mode, neg_bval, mem, newval, use_release);
+ 
+   /* Weak or strong, we want EQ to be true for success, so that we
+      match the flags that we got from the compare above.  */
+-  cond = gen_rtx_REG (CCmode, CC_REGNUM);
+-  x = gen_rtx_COMPARE (CCmode, scratch, const0_rtx);
+-  emit_insn (gen_rtx_SET (cond, x));
++  if (TARGET_32BIT)
++    {
++      cond = gen_rtx_REG (CCmode, CC_REGNUM);
++      x = gen_rtx_COMPARE (CCmode, neg_bval, const0_rtx);
++      emit_insn (gen_rtx_SET (cond, x));
++    }
+ 
+   if (!is_weak)
+     {
+-      x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
+-      x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
+-				gen_rtx_LABEL_REF (Pmode, label1), pc_rtx);
+-      emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
++      /* Z is set to boolean value of !neg_bval, as required to communicate
++	 with arm_expand_compare_and_swap.  */
++      x = gen_rtx_NE (VOIDmode, neg_bval, const0_rtx);
++      emit_unlikely_jump (gen_cbranchsi4 (x, neg_bval, const0_rtx, label1));
+     }
+ 
+   if (!is_mm_relaxed (mod_f))
+@@ -28185,6 +28246,15 @@ arm_split_compare_and_swap (rtx operands[])
+     emit_label (label2);
+ }
+ 
++/* Split an atomic operation pattern.  Operation is given by CODE and is one
++   of PLUS, MINUS, IOR, XOR, SET (for an exchange operation) or NOT (for a nand
++   operation).  Operation is performed on the content at MEM and on VALUE
++   following the memory model MODEL_RTX.  The content at MEM before and after
++   the operation is returned in OLD_OUT and NEW_OUT respectively while the
++   success of the operation is returned in COND.  Using a scratch register or
++   an operand register for these determines what result is returned for that
++   pattern.  */
++
+ void
+ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
+ 		     rtx value, rtx model_rtx, rtx cond)
+@@ -28193,6 +28263,7 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
+   machine_mode mode = GET_MODE (mem);
+   machine_mode wmode = (mode == DImode ? DImode : SImode);
+   rtx_code_label *label;
++  bool all_low_regs, bind_old_new;
+   rtx x;
+ 
+   bool is_armv8_sync = arm_arch8 && is_mm_sync (model);
+@@ -28227,6 +28298,28 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
+ 
+   arm_emit_load_exclusive (mode, old_out, mem, use_acquire);
+ 
++  /* Does the operation require destination and first operand to use the same
++     register?  This is decided by register constraints of relevant insn
++     patterns in thumb1.md.  */
++  gcc_assert (!new_out || REG_P (new_out));
++  all_low_regs = REG_P (value) && REGNO_REG_CLASS (REGNO (value)) == LO_REGS
++		 && new_out && REGNO_REG_CLASS (REGNO (new_out)) == LO_REGS
++		 && REGNO_REG_CLASS (REGNO (old_out)) == LO_REGS;
++  bind_old_new =
++    (TARGET_THUMB1
++     && code != SET
++     && code != MINUS
++     && (code != PLUS || (!all_low_regs && !satisfies_constraint_L (value))));
++
++  /* We want to return the old value while putting the result of the operation
++     in the same register as the old value so copy the old value over to the
++     destination register and use that register for the operation.  */
++  if (old_out && bind_old_new)
++    {
++      emit_move_insn (new_out, old_out);
++      old_out = new_out;
++    }
++
+   switch (code)
+     {
+     case SET:
+@@ -28441,6 +28534,8 @@ arm_evpc_neon_vuzp (struct expand_vec_perm_d *d)
+     case V8QImode:  gen = gen_neon_vuzpv8qi_internal;  break;
+     case V8HImode:  gen = gen_neon_vuzpv8hi_internal;  break;
+     case V4HImode:  gen = gen_neon_vuzpv4hi_internal;  break;
++    case V8HFmode:  gen = gen_neon_vuzpv8hf_internal;  break;
++    case V4HFmode:  gen = gen_neon_vuzpv4hf_internal;  break;
+     case V4SImode:  gen = gen_neon_vuzpv4si_internal;  break;
+     case V2SImode:  gen = gen_neon_vuzpv2si_internal;  break;
+     case V2SFmode:  gen = gen_neon_vuzpv2sf_internal;  break;
+@@ -28514,6 +28609,8 @@ arm_evpc_neon_vzip (struct expand_vec_perm_d *d)
+     case V8QImode:  gen = gen_neon_vzipv8qi_internal;  break;
+     case V8HImode:  gen = gen_neon_vzipv8hi_internal;  break;
+     case V4HImode:  gen = gen_neon_vzipv4hi_internal;  break;
++    case V8HFmode:  gen = gen_neon_vzipv8hf_internal;  break;
++    case V4HFmode:  gen = gen_neon_vzipv4hf_internal;  break;
+     case V4SImode:  gen = gen_neon_vzipv4si_internal;  break;
+     case V2SImode:  gen = gen_neon_vzipv2si_internal;  break;
+     case V2SFmode:  gen = gen_neon_vzipv2sf_internal;  break;
+@@ -28566,6 +28663,8 @@ arm_evpc_neon_vrev (struct expand_vec_perm_d *d)
+ 	case V8QImode:  gen = gen_neon_vrev32v8qi;  break;
+ 	case V8HImode:  gen = gen_neon_vrev64v8hi;  break;
+ 	case V4HImode:  gen = gen_neon_vrev64v4hi;  break;
++	case V8HFmode:  gen = gen_neon_vrev64v8hf;  break;
++	case V4HFmode:  gen = gen_neon_vrev64v4hf;  break;
+ 	default:
+ 	  return false;
+ 	}
+@@ -28649,6 +28748,8 @@ arm_evpc_neon_vtrn (struct expand_vec_perm_d *d)
+     case V8QImode:  gen = gen_neon_vtrnv8qi_internal;  break;
+     case V8HImode:  gen = gen_neon_vtrnv8hi_internal;  break;
+     case V4HImode:  gen = gen_neon_vtrnv4hi_internal;  break;
++    case V8HFmode:  gen = gen_neon_vtrnv8hf_internal;  break;
++    case V4HFmode:  gen = gen_neon_vtrnv4hf_internal;  break;
+     case V4SImode:  gen = gen_neon_vtrnv4si_internal;  break;
+     case V2SImode:  gen = gen_neon_vtrnv2si_internal;  break;
+     case V2SFmode:  gen = gen_neon_vtrnv2sf_internal;  break;
+@@ -28724,6 +28825,8 @@ arm_evpc_neon_vext (struct expand_vec_perm_d *d)
+     case V8HImode: gen = gen_neon_vextv8hi; break;
+     case V2SImode: gen = gen_neon_vextv2si; break;
+     case V4SImode: gen = gen_neon_vextv4si; break;
++    case V4HFmode: gen = gen_neon_vextv4hf; break;
++    case V8HFmode: gen = gen_neon_vextv8hf; break;
+     case V2SFmode: gen = gen_neon_vextv2sf; break;
+     case V4SFmode: gen = gen_neon_vextv4sf; break;
+     case V2DImode: gen = gen_neon_vextv2di; break;
+@@ -29249,7 +29352,7 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2)
+ {
+   enum rtx_code code = GET_CODE (*comparison);
+   int code_int;
+-  machine_mode mode = (GET_MODE (*op1) == VOIDmode) 
++  machine_mode mode = (GET_MODE (*op1) == VOIDmode)
+     ? GET_MODE (*op2) : GET_MODE (*op1);
+ 
+   gcc_assert (GET_MODE (*op1) != VOIDmode || GET_MODE (*op2) != VOIDmode);
+@@ -29277,11 +29380,19 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2)
+ 	*op2 = force_reg (mode, *op2);
+       return true;
+ 
++    case HFmode:
++      if (!TARGET_VFP_FP16INST)
++	break;
++      /* FP16 comparisons are done in SF mode.  */
++      mode = SFmode;
++      *op1 = convert_to_mode (mode, *op1, 1);
++      *op2 = convert_to_mode (mode, *op2, 1);
++      /* Fall through.  */
+     case SFmode:
+     case DFmode:
+-      if (!arm_float_compare_operand (*op1, mode))
++      if (!vfp_compare_operand (*op1, mode))
+ 	*op1 = force_reg (mode, *op1);
+-      if (!arm_float_compare_operand (*op2, mode))
++      if (!vfp_compare_operand (*op2, mode))
+ 	*op2 = force_reg (mode, *op2);
+       return true;
+     default:
+@@ -29823,11 +29934,57 @@ arm_macro_fusion_p (void)
+   return current_tune->fusible_ops != tune_params::FUSE_NOTHING;
+ }
+ 
++/* Return true if the two back-to-back sets PREV_SET, CURR_SET are suitable
++   for MOVW / MOVT macro fusion.  */
++
++static bool
++arm_sets_movw_movt_fusible_p (rtx prev_set, rtx curr_set)
++{
++  /* We are trying to fuse
++     movw imm / movt imm
++    instructions as a group that gets scheduled together.  */
++
++  rtx set_dest = SET_DEST (curr_set);
++
++  if (GET_MODE (set_dest) != SImode)
++    return false;
++
++  /* We are trying to match:
++     prev (movw)  == (set (reg r0) (const_int imm16))
++     curr (movt) == (set (zero_extract (reg r0)
++					(const_int 16)
++					(const_int 16))
++			  (const_int imm16_1))
++     or
++     prev (movw) == (set (reg r1)
++			  (high (symbol_ref ("SYM"))))
++    curr (movt) == (set (reg r0)
++			(lo_sum (reg r1)
++				(symbol_ref ("SYM"))))  */
++
++    if (GET_CODE (set_dest) == ZERO_EXTRACT)
++      {
++	if (CONST_INT_P (SET_SRC (curr_set))
++	    && CONST_INT_P (SET_SRC (prev_set))
++	    && REG_P (XEXP (set_dest, 0))
++	    && REG_P (SET_DEST (prev_set))
++	    && REGNO (XEXP (set_dest, 0)) == REGNO (SET_DEST (prev_set)))
++	  return true;
++
++      }
++    else if (GET_CODE (SET_SRC (curr_set)) == LO_SUM
++	     && REG_P (SET_DEST (curr_set))
++	     && REG_P (SET_DEST (prev_set))
++	     && GET_CODE (SET_SRC (prev_set)) == HIGH
++	     && REGNO (SET_DEST (curr_set)) == REGNO (SET_DEST (prev_set)))
++      return true;
++
++  return false;
++}
+ 
+ static bool
+ aarch_macro_fusion_pair_p (rtx_insn* prev, rtx_insn* curr)
+ {
+-  rtx set_dest;
+   rtx prev_set = single_set (prev);
+   rtx curr_set = single_set (curr);
+ 
+@@ -29845,54 +30002,26 @@ aarch_macro_fusion_pair_p (rtx_insn* prev, rtx_insn* curr)
+       && aarch_crypto_can_dual_issue (prev, curr))
+     return true;
+ 
+-  if (current_tune->fusible_ops & tune_params::FUSE_MOVW_MOVT)
+-    {
+-      /* We are trying to fuse
+-	 movw imm / movt imm
+-	 instructions as a group that gets scheduled together.  */
+-
+-      set_dest = SET_DEST (curr_set);
+-
+-      if (GET_MODE (set_dest) != SImode)
+-	return false;
++  if (current_tune->fusible_ops & tune_params::FUSE_MOVW_MOVT
++      && arm_sets_movw_movt_fusible_p (prev_set, curr_set))
++    return true;
+ 
+-      /* We are trying to match:
+-	 prev (movw)  == (set (reg r0) (const_int imm16))
+-	 curr (movt) == (set (zero_extract (reg r0)
+-					  (const_int 16)
+-					   (const_int 16))
+-			     (const_int imm16_1))
+-	 or
+-	 prev (movw) == (set (reg r1)
+-			      (high (symbol_ref ("SYM"))))
+-	 curr (movt) == (set (reg r0)
+-			     (lo_sum (reg r1)
+-				     (symbol_ref ("SYM"))))  */
+-      if (GET_CODE (set_dest) == ZERO_EXTRACT)
+-	{
+-	  if (CONST_INT_P (SET_SRC (curr_set))
+-	      && CONST_INT_P (SET_SRC (prev_set))
+-	      && REG_P (XEXP (set_dest, 0))
+-	      && REG_P (SET_DEST (prev_set))
+-	      && REGNO (XEXP (set_dest, 0)) == REGNO (SET_DEST (prev_set)))
+-	    return true;
+-	}
+-      else if (GET_CODE (SET_SRC (curr_set)) == LO_SUM
+-	       && REG_P (SET_DEST (curr_set))
+-	       && REG_P (SET_DEST (prev_set))
+-	       && GET_CODE (SET_SRC (prev_set)) == HIGH
+-	       && REGNO (SET_DEST (curr_set)) == REGNO (SET_DEST (prev_set)))
+-	     return true;
+-    }
+   return false;
+ }
+ 
++/* Return true iff the instruction fusion described by OP is enabled.  */
++bool
++arm_fusion_enabled_p (tune_params::fuse_ops op)
++{
++  return current_tune->fusible_ops & op;
++}
++
+ /* Implement the TARGET_ASAN_SHADOW_OFFSET hook.  */
+ 
+ static unsigned HOST_WIDE_INT
+ arm_asan_shadow_offset (void)
+ {
+-  return (unsigned HOST_WIDE_INT) 1 << 29;
++  return HOST_WIDE_INT_1U << 29;
+ }
+ 
+ 
+@@ -29917,9 +30046,9 @@ arm_const_not_ok_for_debug_p (rtx p)
+ 	      && GET_CODE (XEXP (p, 0)) == SYMBOL_REF
+ 	      && (decl_op0 = SYMBOL_REF_DECL (XEXP (p, 0))))
+ 	    {
+-	      if ((TREE_CODE (decl_op1) == VAR_DECL
++	      if ((VAR_P (decl_op1)
+ 		   || TREE_CODE (decl_op1) == CONST_DECL)
+-		  && (TREE_CODE (decl_op0) == VAR_DECL
++		  && (VAR_P (decl_op0)
+ 		      || TREE_CODE (decl_op0) == CONST_DECL))
+ 		return (get_variable_section (decl_op1, false)
+ 			!= get_variable_section (decl_op0, false));
+@@ -30052,9 +30181,8 @@ arm_can_inline_p (tree caller, tree callee)
+   if ((caller_fpu->features & callee_fpu->features) != callee_fpu->features)
+     return false;
+ 
+-  /* Need same model and regs.  */
+-  if (callee_fpu->model != caller_fpu->model
+-      || callee_fpu->regs != callee_fpu->regs)
++  /* Need same FPU regs.  */
++  if (callee_fpu->regs != callee_fpu->regs)
+     return false;
+ 
+   /* OK to inline between different modes.
+@@ -30397,4 +30525,220 @@ arm_sched_fusion_priority (rtx_insn *insn, int max_pri,
+   return;
+ }
+ 
++
++/* Construct and return a PARALLEL RTX vector with elements numbering the
++   lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
++   the vector - from the perspective of the architecture.  This does not
++   line up with GCC's perspective on lane numbers, so we end up with
++   different masks depending on our target endian-ness.  The diagram
++   below may help.  We must draw the distinction when building masks
++   which select one half of the vector.  An instruction selecting
++   architectural low-lanes for a big-endian target, must be described using
++   a mask selecting GCC high-lanes.
++
++                 Big-Endian             Little-Endian
++
++GCC             0   1   2   3           3   2   1   0
++              | x | x | x | x |       | x | x | x | x |
++Architecture    3   2   1   0           3   2   1   0
++
++Low Mask:         { 2, 3 }                { 0, 1 }
++High Mask:        { 0, 1 }                { 2, 3 }
++*/
++
++rtx
++arm_simd_vect_par_cnst_half (machine_mode mode, bool high)
++{
++  int nunits = GET_MODE_NUNITS (mode);
++  rtvec v = rtvec_alloc (nunits / 2);
++  int high_base = nunits / 2;
++  int low_base = 0;
++  int base;
++  rtx t1;
++  int i;
++
++  if (BYTES_BIG_ENDIAN)
++    base = high ? low_base : high_base;
++  else
++    base = high ? high_base : low_base;
++
++  for (i = 0; i < nunits / 2; i++)
++    RTVEC_ELT (v, i) = GEN_INT (base + i);
++
++  t1 = gen_rtx_PARALLEL (mode, v);
++  return t1;
++}
++
++/* Check OP for validity as a PARALLEL RTX vector with elements
++   numbering the lanes of either the high (HIGH == TRUE) or low lanes,
++   from the perspective of the architecture.  See the diagram above
++   arm_simd_vect_par_cnst_half_p for more details.  */
++
++bool
++arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode,
++				       bool high)
++{
++  rtx ideal = arm_simd_vect_par_cnst_half (mode, high);
++  HOST_WIDE_INT count_op = XVECLEN (op, 0);
++  HOST_WIDE_INT count_ideal = XVECLEN (ideal, 0);
++  int i = 0;
++
++  if (!VECTOR_MODE_P (mode))
++    return false;
++
++  if (count_op != count_ideal)
++    return false;
++
++  for (i = 0; i < count_ideal; i++)
++    {
++      rtx elt_op = XVECEXP (op, 0, i);
++      rtx elt_ideal = XVECEXP (ideal, 0, i);
++
++      if (!CONST_INT_P (elt_op)
++	  || INTVAL (elt_ideal) != INTVAL (elt_op))
++	return false;
++    }
++  return true;
++}
++
++/* Can output mi_thunk for all cases except for non-zero vcall_offset
++   in Thumb1.  */
++static bool
++arm_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT vcall_offset,
++			 const_tree)
++{
++  /* For now, we punt and not handle this for TARGET_THUMB1.  */
++  if (vcall_offset && TARGET_THUMB1)
++    return false;
++
++  /* Otherwise ok.  */
++  return true;
++}
++
++/* Generate RTL for a conditional branch with rtx comparison CODE in
++   mode CC_MODE. The destination of the unlikely conditional branch
++   is LABEL_REF.  */
++
++void
++arm_gen_unlikely_cbranch (enum rtx_code code, machine_mode cc_mode,
++			  rtx label_ref)
++{
++  rtx x;
++  x = gen_rtx_fmt_ee (code, VOIDmode,
++		      gen_rtx_REG (cc_mode, CC_REGNUM),
++		      const0_rtx);
++
++  x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
++			    gen_rtx_LABEL_REF (VOIDmode, label_ref),
++			    pc_rtx);
++  emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
++}
++
++/* Implement the TARGET_ASM_ELF_FLAGS_NUMERIC hook.
++
++   For pure-code sections there is no letter code for this attribute, so
++   output all the section flags numerically when this is needed.  */
++
++static bool
++arm_asm_elf_flags_numeric (unsigned int flags, unsigned int *num)
++{
++
++  if (flags & SECTION_ARM_PURECODE)
++    {
++      *num = 0x20000000;
++
++      if (!(flags & SECTION_DEBUG))
++	*num |= 0x2;
++      if (flags & SECTION_EXCLUDE)
++	*num |= 0x80000000;
++      if (flags & SECTION_WRITE)
++	*num |= 0x1;
++      if (flags & SECTION_CODE)
++	*num |= 0x4;
++      if (flags & SECTION_MERGE)
++	*num |= 0x10;
++      if (flags & SECTION_STRINGS)
++	*num |= 0x20;
++      if (flags & SECTION_TLS)
++	*num |= 0x400;
++      if (HAVE_COMDAT_GROUP && (flags & SECTION_LINKONCE))
++	*num |= 0x200;
++
++	return true;
++    }
++
++  return false;
++}
++
++/* Implement the TARGET_ASM_FUNCTION_SECTION hook.
++
++   If pure-code is passed as an option, make sure all functions are in
++   sections that have the SHF_ARM_PURECODE attribute.  */
++
++static section *
++arm_function_section (tree decl, enum node_frequency freq,
++		      bool startup, bool exit)
++{
++  const char * section_name;
++  section * sec;
++
++  if (!decl || TREE_CODE (decl) != FUNCTION_DECL)
++    return default_function_section (decl, freq, startup, exit);
++
++  if (!target_pure_code)
++    return default_function_section (decl, freq, startup, exit);
++
++
++  section_name = DECL_SECTION_NAME (decl);
++
++  /* If a function is not in a named section then it falls under the 'default'
++     text section, also known as '.text'.  We can preserve previous behavior as
++     the default text section already has the SHF_ARM_PURECODE section
++     attribute.  */
++  if (!section_name)
++    {
++      section *default_sec = default_function_section (decl, freq, startup,
++						       exit);
++
++      /* If default_sec is not null, then it must be a special section like for
++	 example .text.startup.  We set the pure-code attribute and return the
++	 same section to preserve existing behavior.  */
++      if (default_sec)
++	  default_sec->common.flags |= SECTION_ARM_PURECODE;
++      return default_sec;
++    }
++
++  /* Otherwise look whether a section has already been created with
++     'section_name'.  */
++  sec = get_named_section (decl, section_name, 0);
++  if (!sec)
++    /* If that is not the case passing NULL as the section's name to
++       'get_named_section' will create a section with the declaration's
++       section name.  */
++    sec = get_named_section (decl, NULL, 0);
++
++  /* Set the SHF_ARM_PURECODE attribute.  */
++  sec->common.flags |= SECTION_ARM_PURECODE;
++
++  return sec;
++}
++
++/* Implements the TARGET_SECTION_FLAGS hook.
++
++   If DECL is a function declaration and pure-code is passed as an option
++   then add the SFH_ARM_PURECODE attribute to the section flags.  NAME is the
++   section's name and RELOC indicates whether the declarations initializer may
++   contain runtime relocations.  */
++
++static unsigned int
++arm_elf_section_type_flags (tree decl, const char *name, int reloc)
++{
++  unsigned int flags = default_section_type_flags (decl, name, reloc);
++
++  if (decl && TREE_CODE (decl) == FUNCTION_DECL && target_pure_code)
++    flags |= SECTION_ARM_PURECODE;
++
++  return flags;
++}
++
+ #include "gt-arm.h"
+--- a/src/gcc/config/arm/arm.h
++++ b/src/gcc/config/arm/arm.h
+@@ -80,11 +80,6 @@ extern arm_cc arm_current_cc;
+ extern int arm_target_label;
+ extern int arm_ccfsm_state;
+ extern GTY(()) rtx arm_target_insn;
+-/* The label of the current constant pool.  */
+-extern rtx pool_vector_label;
+-/* Set to 1 when a return insn is output, this means that the epilogue
+-   is not needed.  */
+-extern int return_used_this_function;
+ /* Callback to output language specific object attributes.  */
+ extern void (*arm_lang_output_object_attributes_hook)(void);
+ 
+@@ -139,7 +134,6 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
+ #define TARGET_HARD_FLOAT		(arm_float_abi != ARM_FLOAT_ABI_SOFT)
+ /* Use hardware floating point calling convention.  */
+ #define TARGET_HARD_FLOAT_ABI		(arm_float_abi == ARM_FLOAT_ABI_HARD)
+-#define TARGET_VFP		        (TARGET_FPU_MODEL == ARM_FP_MODEL_VFP)
+ #define TARGET_IWMMXT			(arm_arch_iwmmxt)
+ #define TARGET_IWMMXT2			(arm_arch_iwmmxt2)
+ #define TARGET_REALLY_IWMMXT		(TARGET_IWMMXT && TARGET_32BIT)
+@@ -177,50 +171,57 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
+    to be more careful with TARGET_NEON as noted below.  */
+ 
+ /* FPU is has the full VFPv3/NEON register file of 32 D registers.  */
+-#define TARGET_VFPD32 (TARGET_VFP && TARGET_FPU_REGS == VFP_REG_D32)
++#define TARGET_VFPD32 (TARGET_FPU_REGS == VFP_REG_D32)
+ 
+ /* FPU supports VFPv3 instructions.  */
+-#define TARGET_VFP3 (TARGET_VFP && TARGET_FPU_REV >= 3)
++#define TARGET_VFP3 (TARGET_FPU_REV >= 3)
+ 
+ /* FPU supports FPv5 instructions.  */
+-#define TARGET_VFP5 (TARGET_VFP && TARGET_FPU_REV >= 5)
++#define TARGET_VFP5 (TARGET_FPU_REV >= 5)
+ 
+ /* FPU only supports VFP single-precision instructions.  */
+-#define TARGET_VFP_SINGLE (TARGET_VFP && TARGET_FPU_REGS == VFP_REG_SINGLE)
++#define TARGET_VFP_SINGLE (TARGET_FPU_REGS == VFP_REG_SINGLE)
+ 
+ /* FPU supports VFP double-precision instructions.  */
+-#define TARGET_VFP_DOUBLE (TARGET_VFP && TARGET_FPU_REGS != VFP_REG_SINGLE)
++#define TARGET_VFP_DOUBLE (TARGET_FPU_REGS != VFP_REG_SINGLE)
+ 
+ /* FPU supports half-precision floating-point with NEON element load/store.  */
+-#define TARGET_NEON_FP16						\
+-  (TARGET_VFP								\
+-   && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON | FPU_FL_FP16))
++#define TARGET_NEON_FP16					\
++  (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON)		\
++   && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
+ 
+ /* FPU supports VFP half-precision floating-point.  */
+ #define TARGET_FP16							\
+-  (TARGET_VFP && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
++  (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
+ 
+ /* FPU supports fused-multiply-add operations.  */
+-#define TARGET_FMA (TARGET_VFP && TARGET_FPU_REV >= 4)
++#define TARGET_FMA (TARGET_FPU_REV >= 4)
+ 
+ /* FPU is ARMv8 compatible.  */
+-#define TARGET_FPU_ARMV8 (TARGET_VFP && TARGET_FPU_REV >= 8)
++#define TARGET_FPU_ARMV8 (TARGET_FPU_REV >= 8)
+ 
+ /* FPU supports Crypto extensions.  */
+ #define TARGET_CRYPTO							\
+-  (TARGET_VFP && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_CRYPTO))
++  (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_CRYPTO))
+ 
+ /* FPU supports Neon instructions.  The setting of this macro gets
+    revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
+    and TARGET_HARD_FLOAT to ensure that NEON instructions are
+    available.  */
+ #define TARGET_NEON							\
+-  (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP			\
++  (TARGET_32BIT && TARGET_HARD_FLOAT					\
+    && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON))
+ 
+ /* FPU supports ARMv8.1 Adv.SIMD extensions.  */
+ #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1)
+ 
++/* FPU supports the floating point FP16 instructions for ARMv8.2 and later.  */
++#define TARGET_VFP_FP16INST \
++  (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 && arm_fp16_inst)
++
++/* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later.  */
++#define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA)
++
+ /* Q-bit is present.  */
+ #define TARGET_ARM_QBIT \
+   (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7))
+@@ -236,7 +237,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
+ 
+ /* Should MOVW/MOVT be used in preference to a constant pool.  */
+ #define TARGET_USE_MOVT \
+-  (arm_arch_thumb2 \
++  (TARGET_HAVE_MOVT \
+    && (arm_disable_literal_pool \
+        || (!optimize_size && !current_tune->prefer_constant_pool)))
+ 
+@@ -251,13 +252,17 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
+ #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
+ 
+ /* Nonzero if this chip supports ldrex and strex */
+-#define TARGET_HAVE_LDREX        ((arm_arch6 && TARGET_ARM) || arm_arch7)
++#define TARGET_HAVE_LDREX        ((arm_arch6 && TARGET_ARM)	\
++				  || arm_arch7			\
++				  || (arm_arch8 && !arm_arch_notm))
+ 
+ /* Nonzero if this chip supports LPAE.  */
+ #define TARGET_HAVE_LPAE	(arm_arch_lpae)
+ 
+ /* Nonzero if this chip supports ldrex{bh} and strex{bh}.  */
+-#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7)
++#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM)		\
++			     || arm_arch7			\
++			     || (arm_arch8 && !arm_arch_notm))
+ 
+ /* Nonzero if this chip supports ldrexd and strexd.  */
+ #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \
+@@ -266,9 +271,20 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
+ /* Nonzero if this chip supports load-acquire and store-release.  */
+ #define TARGET_HAVE_LDACQ	(TARGET_ARM_ARCH >= 8)
+ 
++/* Nonzero if this chip supports LDAEXD and STLEXD.  */
++#define TARGET_HAVE_LDACQEXD	(TARGET_ARM_ARCH >= 8	\
++				 && TARGET_32BIT	\
++				 && arm_arch_notm)
++
++/* Nonzero if this chip provides the MOVW and MOVT instructions.  */
++#define TARGET_HAVE_MOVT	(arm_arch_thumb2 || arm_arch8)
++
++/* Nonzero if this chip provides the CBZ and CBNZ instructions.  */
++#define TARGET_HAVE_CBZ		(arm_arch_thumb2 || arm_arch8)
++
+ /* Nonzero if integer division instructions supported.  */
+ #define TARGET_IDIV	((TARGET_ARM && arm_arch_arm_hwdiv)	\
+-			 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
++			 || (TARGET_THUMB && arm_arch_thumb_hwdiv))
+ 
+ /* Nonzero if disallow volatile memory access in IT block.  */
+ #define TARGET_NO_VOLATILE_CE		(arm_arch_no_volatile_ce)
+@@ -348,7 +364,6 @@ enum vfp_reg_type
+ extern const struct arm_fpu_desc
+ {
+   const char *name;
+-  enum arm_fp_model model;
+   int rev;
+   enum vfp_reg_type regs;
+   arm_fpu_feature_set features;
+@@ -357,7 +372,6 @@ extern const struct arm_fpu_desc
+ /* Accessors.  */
+ 
+ #define TARGET_FPU_NAME     (all_fpus[arm_fpu_index].name)
+-#define TARGET_FPU_MODEL    (all_fpus[arm_fpu_index].model)
+ #define TARGET_FPU_REV      (all_fpus[arm_fpu_index].rev)
+ #define TARGET_FPU_REGS     (all_fpus[arm_fpu_index].regs)
+ #define TARGET_FPU_FEATURES (all_fpus[arm_fpu_index].features)
+@@ -407,7 +421,9 @@ enum base_architecture
+   BASE_ARCH_7R = 7,
+   BASE_ARCH_7M = 7,
+   BASE_ARCH_7EM = 7,
+-  BASE_ARCH_8A = 8
++  BASE_ARCH_8A = 8,
++  BASE_ARCH_8M_BASE = 8,
++  BASE_ARCH_8M_MAIN = 8
+ };
+ 
+ /* The major revision number of the ARM Architecture implemented by the target.  */
+@@ -452,6 +468,13 @@ extern int arm_arch8;
+ /* Nonzero if this chip supports the ARM Architecture 8.1 extensions.  */
+ extern int arm_arch8_1;
+ 
++/* Nonzero if this chip supports the ARM Architecture 8.2 extensions.  */
++extern int arm_arch8_2;
++
++/* Nonzero if this chip supports the FP16 instructions extension of ARM
++   Architecture 8.2.  */
++extern int arm_fp16_inst;
++
+ /* Nonzero if this chip can benefit from load scheduling.  */
+ extern int arm_ld_sched;
+ 
+@@ -483,6 +506,9 @@ extern int arm_tune_cortex_a9;
+    interworking clean.  */
+ extern int arm_cpp_interwork;
+ 
++/* Nonzero if chip supports Thumb 1.  */
++extern int arm_arch_thumb1;
++
+ /* Nonzero if chip supports Thumb 2.  */
+ extern int arm_arch_thumb2;
+ 
+@@ -507,6 +533,9 @@ extern bool arm_disable_literal_pool;
+ /* Nonzero if chip supports the ARMv8 CRC instructions.  */
+ extern int arm_arch_crc;
+ 
++/* Nonzero if chip supports the ARMv8-M Security Extensions.  */
++extern int arm_arch_cmse;
++
+ #ifndef TARGET_DEFAULT
+ #define TARGET_DEFAULT  (MASK_APCS_FRAME)
+ #endif
+@@ -1196,7 +1225,7 @@ enum reg_class
+    the data layout happens to be consistent for big-endian, so we explicitly allow
+    that case.  */
+ #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)		\
+-  (TARGET_VFP && TARGET_BIG_END					\
++  (TARGET_BIG_END						\
+    && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8)	\
+    && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD			\
+        || GET_MODE_SIZE (TO) > UNITS_PER_WORD)			\
+@@ -1247,8 +1276,7 @@ enum reg_class
+    NO_REGS is returned.  */
+ #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)		\
+   /* Restrict which direct reloads are allowed for VFP/iWMMXt regs.  */ \
+-  ((TARGET_VFP && TARGET_HARD_FLOAT				\
+-    && IS_VFP_CLASS (CLASS))					\
++  ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS))			\
+    ? coproc_secondary_reload_class (MODE, X, FALSE)		\
+    : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS)			\
+    ? coproc_secondary_reload_class (MODE, X, TRUE)		\
+@@ -1260,8 +1288,7 @@ enum reg_class
+ /* If we need to load shorts byte-at-a-time, then we need a scratch.  */
+ #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)		\
+   /* Restrict which direct reloads are allowed for VFP/iWMMXt regs.  */ \
+-  ((TARGET_VFP && TARGET_HARD_FLOAT				\
+-    && IS_VFP_CLASS (CLASS))					\
++  ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS))			\
+     ? coproc_secondary_reload_class (MODE, X, FALSE) :		\
+     (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ?			\
+     coproc_secondary_reload_class (MODE, X, TRUE) :		\
+@@ -1368,6 +1395,7 @@ enum reg_class
+ #define ARM_FT_VOLATILE		(1 << 4) /* Does not return.  */
+ #define ARM_FT_NESTED		(1 << 5) /* Embedded inside another func.  */
+ #define ARM_FT_STACKALIGN	(1 << 6) /* Called with misaligned stack.  */
++#define ARM_FT_CMSE_ENTRY	(1 << 7) /* ARMv8-M non-secure entry function.  */
+ 
+ /* Some macros to test these flags.  */
+ #define ARM_FUNC_TYPE(t)	(t & ARM_FT_TYPE_MASK)
+@@ -1376,6 +1404,7 @@ enum reg_class
+ #define IS_NAKED(t)        	(t & ARM_FT_NAKED)
+ #define IS_NESTED(t)       	(t & ARM_FT_NESTED)
+ #define IS_STACKALIGN(t)       	(t & ARM_FT_STACKALIGN)
++#define IS_CMSE_ENTRY(t)	(t & ARM_FT_CMSE_ENTRY)
+ 
+ 
+ /* Structure used to hold the function stack frame layout.  Offsets are
+@@ -1521,7 +1550,7 @@ typedef struct
+    On the ARM, r0-r3 are used to pass args.  */
+ #define FUNCTION_ARG_REGNO_P(REGNO)					\
+    (IN_RANGE ((REGNO), 0, 3)						\
+-    || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT		\
++    || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT				\
+ 	&& IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15))	\
+     || (TARGET_IWMMXT_ABI						\
+ 	&& IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
+@@ -2192,13 +2221,9 @@ extern int making_const_table;
+ #define TARGET_ARM_ARCH	\
+   (arm_base_arch)	\
+ 
+-#define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2)
+-#define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2)
+-
+ /* The highest Thumb instruction set version supported by the chip.  */
+-#define TARGET_ARM_ARCH_ISA_THUMB 		\
+-  (arm_arch_thumb2 ? 2				\
+-	           : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0))
++#define TARGET_ARM_ARCH_ISA_THUMB		\
++  (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0))
+ 
+ /* Expands to an upper-case char of the target's architectural
+    profile.  */
+@@ -2250,13 +2275,18 @@ extern const char *arm_rewrite_mcpu (int argc, const char **argv);
+    "   :%{march=*:-march=%*}}"					\
+    BIG_LITTLE_SPEC
+ 
++extern const char *arm_target_thumb_only (int argc, const char **argv);
++#define TARGET_MODE_SPEC_FUNCTIONS					\
++  { "target_mode_check", arm_target_thumb_only },
++
+ /* -mcpu=native handling only makes sense with compiler running on
+    an ARM chip.  */
+ #if defined(__arm__)
+ extern const char *host_detect_local_cpu (int argc, const char **argv);
+ # define EXTRA_SPEC_FUNCTIONS						\
+   { "local_cpu_detect", host_detect_local_cpu },			\
+-  BIG_LITTLE_CPU_SPEC_FUNCTIONS
++  BIG_LITTLE_CPU_SPEC_FUNCTIONS						\
++  TARGET_MODE_SPEC_FUNCTIONS
+ 
+ # define MCPU_MTUNE_NATIVE_SPECS					\
+    " %{march=native:%<march=native %:local_cpu_detect(arch)}"		\
+@@ -2264,13 +2294,28 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
+    " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
+ #else
+ # define MCPU_MTUNE_NATIVE_SPECS ""
+-# define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS
++# define EXTRA_SPEC_FUNCTIONS						\
++	BIG_LITTLE_CPU_SPEC_FUNCTIONS					\
++	TARGET_MODE_SPEC_FUNCTIONS
+ #endif
+ 
+-#define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS
++/* Automatically add -mthumb for Thumb-only targets if mode isn't specified
++   via the configuration option --with-mode or via the command line. The
++   function target_mode_check is called to do the check with either:
++   - an array of -march values if any is given;
++   - an array of -mcpu values if any is given;
++   - an empty array.  */
++#define TARGET_MODE_SPECS						\
++  " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:%*;mcpu=*:%*;:})}}"
++
++#define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS TARGET_MODE_SPECS
+ #define TARGET_SUPPORTS_WIDE_INT 1
+ 
+ /* For switching between functions with different target attributes.  */
+ #define SWITCHABLE_TARGET 1
+ 
++/* Define SECTION_ARM_PURECODE as the ARM specific section attribute
++   representation for SHF_ARM_PURECODE in GCC.  */
++#define SECTION_ARM_PURECODE SECTION_MACH_DEP
++
+ #endif /* ! GCC_ARM_H */
+--- a/src/gcc/config/arm/arm.md
++++ b/src/gcc/config/arm/arm.md
+@@ -118,10 +118,10 @@
+ ; This can be "a" for ARM, "t" for either of the Thumbs, "32" for
+ ; TARGET_32BIT, "t1" or "t2" to specify a specific Thumb mode.  "v6"
+ ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without
+-; arm_arch6.  "v6t2" for Thumb-2 with arm_arch6.  This attribute is
+-; used to compute attribute "enabled", use type "any" to enable an
+-; alternative in all cases.
+-(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2,armv6_or_vfpv3"
++; arm_arch6.  "v6t2" for Thumb-2 with arm_arch6 and "v8mb" for ARMv8-M
++; Baseline.  This attribute is used to compute attribute "enabled",
++; use type "any" to enable an alternative in all cases.
++(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,v8mb,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2,armv6_or_vfpv3,neon"
+   (const_string "any"))
+ 
+ (define_attr "arch_enabled" "no,yes"
+@@ -160,6 +160,10 @@
+ 	      (match_test "TARGET_32BIT && arm_arch6 && arm_arch_thumb2"))
+ 	 (const_string "yes")
+ 
++	 (and (eq_attr "arch" "v8mb")
++	      (match_test "TARGET_THUMB1 && arm_arch8"))
++	 (const_string "yes")
++
+ 	 (and (eq_attr "arch" "avoid_neon_for_64bits")
+ 	      (match_test "TARGET_NEON")
+ 	      (not (match_test "TARGET_PREFER_NEON_64BITS")))
+@@ -177,6 +181,10 @@
+ 	 (and (eq_attr "arch" "armv6_or_vfpv3")
+ 	      (match_test "arm_arch6 || TARGET_VFP3"))
+ 	 (const_string "yes")
++
++	 (and (eq_attr "arch" "neon")
++	      (match_test "TARGET_NEON"))
++	 (const_string "yes")
+ 	]
+ 
+ 	(const_string "no")))
+@@ -225,10 +233,6 @@
+ 	       (match_test "arm_restrict_it"))
+ 	  (const_string "no")
+ 
+-	  (and (eq_attr "use_literal_pool" "yes")
+-	       (match_test "arm_disable_literal_pool"))
+-	  (const_string "no")
+-
+ 	  (eq_attr "arch_enabled" "no")
+ 	  (const_string "no")]
+ 	 (const_string "yes")))
+@@ -539,6 +543,32 @@
+    (set_attr "type" "multiple")]
+ )
+ 
++(define_expand "addv<mode>4"
++  [(match_operand:SIDI 0 "register_operand")
++   (match_operand:SIDI 1 "register_operand")
++   (match_operand:SIDI 2 "register_operand")
++   (match_operand 3 "")]
++  "TARGET_32BIT"
++{
++  emit_insn (gen_add<mode>3_compareV (operands[0], operands[1], operands[2]));
++  arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
++
++  DONE;
++})
++
++(define_expand "uaddv<mode>4"
++  [(match_operand:SIDI 0 "register_operand")
++   (match_operand:SIDI 1 "register_operand")
++   (match_operand:SIDI 2 "register_operand")
++   (match_operand 3 "")]
++  "TARGET_32BIT"
++{
++  emit_insn (gen_add<mode>3_compareC (operands[0], operands[1], operands[2]));
++  arm_gen_unlikely_cbranch (NE, CC_Cmode, operands[3]);
++
++  DONE;
++})
++
+ (define_expand "addsi3"
+   [(set (match_operand:SI          0 "s_register_operand" "")
+ 	(plus:SI (match_operand:SI 1 "s_register_operand" "")
+@@ -617,6 +647,165 @@
+  ]
+ )
+ 
++(define_insn_and_split "adddi3_compareV"
++  [(set (reg:CC_V CC_REGNUM)
++	(ne:CC_V
++	  (plus:TI
++	    (sign_extend:TI (match_operand:DI 1 "register_operand" "r"))
++	    (sign_extend:TI (match_operand:DI 2 "register_operand" "r")))
++	  (sign_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
++   (set (match_operand:DI 0 "register_operand" "=&r")
++	(plus:DI (match_dup 1) (match_dup 2)))]
++  "TARGET_32BIT"
++  "#"
++  "&& reload_completed"
++  [(parallel [(set (reg:CC_C CC_REGNUM)
++		   (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
++				 (match_dup 1)))
++	      (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
++   (parallel [(set (reg:CC_V CC_REGNUM)
++		   (ne:CC_V
++		    (plus:DI (plus:DI
++			      (sign_extend:DI (match_dup 4))
++			      (sign_extend:DI (match_dup 5)))
++			     (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
++		    (plus:DI (sign_extend:DI
++			      (plus:SI (match_dup 4) (match_dup 5)))
++			     (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
++	     (set (match_dup 3) (plus:SI (plus:SI
++					  (match_dup 4) (match_dup 5))
++					 (ltu:SI (reg:CC_C CC_REGNUM)
++						 (const_int 0))))])]
++  "
++  {
++    operands[3] = gen_highpart (SImode, operands[0]);
++    operands[0] = gen_lowpart (SImode, operands[0]);
++    operands[4] = gen_highpart (SImode, operands[1]);
++    operands[1] = gen_lowpart (SImode, operands[1]);
++    operands[5] = gen_highpart (SImode, operands[2]);
++    operands[2] = gen_lowpart (SImode, operands[2]);
++  }"
++ [(set_attr "conds" "set")
++   (set_attr "length" "8")
++   (set_attr "type" "multiple")]
++)
++
++(define_insn "addsi3_compareV"
++  [(set (reg:CC_V CC_REGNUM)
++	(ne:CC_V
++	  (plus:DI
++	    (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
++	    (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
++	  (sign_extend:DI (plus:SI (match_dup 1) (match_dup 2)))))
++   (set (match_operand:SI 0 "register_operand" "=r")
++	(plus:SI (match_dup 1) (match_dup 2)))]
++  "TARGET_32BIT"
++  "adds%?\\t%0, %1, %2"
++  [(set_attr "conds" "set")
++   (set_attr "type" "alus_sreg")]
++)
++
++(define_insn "*addsi3_compareV_upper"
++  [(set (reg:CC_V CC_REGNUM)
++	(ne:CC_V
++	  (plus:DI
++	   (plus:DI
++	    (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
++	    (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
++	   (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
++	  (plus:DI (sign_extend:DI
++		    (plus:SI (match_dup 1) (match_dup 2)))
++		   (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
++   (set (match_operand:SI 0 "register_operand" "=r")
++	(plus:SI
++	 (plus:SI (match_dup 1) (match_dup 2))
++	 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
++  "TARGET_32BIT"
++  "adcs%?\\t%0, %1, %2"
++  [(set_attr "conds" "set")
++   (set_attr "type" "adcs_reg")]
++)
++
++(define_insn_and_split "adddi3_compareC"
++  [(set (reg:CC_C CC_REGNUM)
++	(ne:CC_C
++	  (plus:TI
++	    (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
++	    (zero_extend:TI (match_operand:DI 2 "register_operand" "r")))
++	  (zero_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
++   (set (match_operand:DI 0 "register_operand" "=&r")
++	(plus:DI (match_dup 1) (match_dup 2)))]
++  "TARGET_32BIT"
++  "#"
++  "&& reload_completed"
++  [(parallel [(set (reg:CC_C CC_REGNUM)
++		   (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
++				 (match_dup 1)))
++	      (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
++   (parallel [(set (reg:CC_C CC_REGNUM)
++		   (ne:CC_C
++		    (plus:DI (plus:DI
++			      (zero_extend:DI (match_dup 4))
++			      (zero_extend:DI (match_dup 5)))
++			     (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
++		    (plus:DI (zero_extend:DI
++			      (plus:SI (match_dup 4) (match_dup 5)))
++			     (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
++	     (set (match_dup 3) (plus:SI
++				 (plus:SI (match_dup 4) (match_dup 5))
++				 (ltu:SI (reg:CC_C CC_REGNUM)
++					 (const_int 0))))])]
++  "
++  {
++    operands[3] = gen_highpart (SImode, operands[0]);
++    operands[0] = gen_lowpart (SImode, operands[0]);
++    operands[4] = gen_highpart (SImode, operands[1]);
++    operands[5] = gen_highpart (SImode, operands[2]);
++    operands[1] = gen_lowpart (SImode, operands[1]);
++    operands[2] = gen_lowpart (SImode, operands[2]);
++  }"
++ [(set_attr "conds" "set")
++   (set_attr "length" "8")
++   (set_attr "type" "multiple")]
++)
++
++(define_insn "*addsi3_compareC_upper"
++  [(set (reg:CC_C CC_REGNUM)
++	(ne:CC_C
++	  (plus:DI
++	   (plus:DI
++	    (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
++	    (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
++	   (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
++	  (plus:DI (zero_extend:DI
++		    (plus:SI (match_dup 1) (match_dup 2)))
++		   (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
++   (set (match_operand:SI 0 "register_operand" "=r")
++	(plus:SI
++	 (plus:SI (match_dup 1) (match_dup 2))
++	 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
++  "TARGET_32BIT"
++  "adcs%?\\t%0, %1, %2"
++  [(set_attr "conds" "set")
++   (set_attr "type" "adcs_reg")]
++)
++
++(define_insn "addsi3_compareC"
++   [(set (reg:CC_C CC_REGNUM)
++	 (ne:CC_C
++	  (plus:DI
++	   (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
++	   (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
++	  (zero_extend:DI
++	   (plus:SI (match_dup 1) (match_dup 2)))))
++    (set (match_operand:SI 0 "register_operand" "=r")
++	 (plus:SI (match_dup 1) (match_dup 2)))]
++  "TARGET_32BIT"
++  "adds%?\\t%0, %1, %2"
++  [(set_attr "conds" "set")
++   (set_attr "type" "alus_sreg")]
++)
++
+ (define_insn "addsi3_compare0"
+   [(set (reg:CC_NOOV CC_REGNUM)
+ 	(compare:CC_NOOV
+@@ -866,20 +1055,90 @@
+     (set_attr "type" "adcs_reg")]
+ )
+ 
++(define_expand "subv<mode>4"
++  [(match_operand:SIDI 0 "register_operand")
++   (match_operand:SIDI 1 "register_operand")
++   (match_operand:SIDI 2 "register_operand")
++   (match_operand 3 "")]
++  "TARGET_32BIT"
++{
++  emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
++  arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
++
++  DONE;
++})
++
++(define_expand "usubv<mode>4"
++  [(match_operand:SIDI 0 "register_operand")
++   (match_operand:SIDI 1 "register_operand")
++   (match_operand:SIDI 2 "register_operand")
++   (match_operand 3 "")]
++  "TARGET_32BIT"
++{
++  emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
++  arm_gen_unlikely_cbranch (LTU, CCmode, operands[3]);
++
++  DONE;
++})
++
++(define_insn_and_split "subdi3_compare1"
++  [(set (reg:CC CC_REGNUM)
++	(compare:CC
++	  (match_operand:DI 1 "register_operand" "r")
++	  (match_operand:DI 2 "register_operand" "r")))
++   (set (match_operand:DI 0 "register_operand" "=&r")
++	(minus:DI (match_dup 1) (match_dup 2)))]
++  "TARGET_32BIT"
++  "#"
++  "&& reload_completed"
++  [(parallel [(set (reg:CC CC_REGNUM)
++		   (compare:CC (match_dup 1) (match_dup 2)))
++	      (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
++   (parallel [(set (reg:CC CC_REGNUM)
++		   (compare:CC (match_dup 4) (match_dup 5)))
++	     (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
++			       (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))])]
++  {
++    operands[3] = gen_highpart (SImode, operands[0]);
++    operands[0] = gen_lowpart (SImode, operands[0]);
++    operands[4] = gen_highpart (SImode, operands[1]);
++    operands[1] = gen_lowpart (SImode, operands[1]);
++    operands[5] = gen_highpart (SImode, operands[2]);
++    operands[2] = gen_lowpart (SImode, operands[2]);
++   }
++  [(set_attr "conds" "set")
++   (set_attr "length" "8")
++   (set_attr "type" "multiple")]
++)
++
++(define_insn "subsi3_compare1"
++  [(set (reg:CC CC_REGNUM)
++	(compare:CC
++	  (match_operand:SI 1 "register_operand" "r")
++	  (match_operand:SI 2 "register_operand" "r")))
++   (set (match_operand:SI 0 "register_operand" "=r")
++	(minus:SI (match_dup 1) (match_dup 2)))]
++  "TARGET_32BIT"
++  "subs%?\\t%0, %1, %2"
++  [(set_attr "conds" "set")
++   (set_attr "type" "alus_sreg")]
++)
++
+ (define_insn "*subsi3_carryin"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+-        (minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I")
+-                            (match_operand:SI 2 "s_register_operand" "r,r"))
+-                  (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
++	(minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I,Pz")
++			    (match_operand:SI 2 "s_register_operand" "r,r,r"))
++		  (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
+   "TARGET_32BIT"
+   "@
+    sbc%?\\t%0, %1, %2
+-   rsc%?\\t%0, %2, %1"
++   rsc%?\\t%0, %2, %1
++   sbc%?\\t%0, %2, %2, lsl #1"
+   [(set_attr "conds" "use")
+-   (set_attr "arch" "*,a")
++   (set_attr "arch" "*,a,t2")
+    (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+-   (set_attr "type" "adc_reg,adc_imm")]
++   (set_attr "type" "adc_reg,adc_imm,alu_shift_imm")]
+ )
+ 
+ (define_insn "*subsi3_carryin_const"
+@@ -1895,7 +2154,7 @@
+   [(set (match_operand:SF 0 "s_register_operand" "")
+ 	(div:SF (match_operand:SF 1 "s_register_operand" "")
+ 		(match_operand:SF 2 "s_register_operand" "")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "")
+ 
+ (define_expand "divdf3"
+@@ -2137,13 +2396,13 @@
+ 
+           for (i = 9; i <= 31; i++)
+ 	    {
+-	      if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (operands[2]))
++	      if ((HOST_WIDE_INT_1 << i) - 1 == INTVAL (operands[2]))
+ 	        {
+ 	          emit_insn (gen_extzv (operands[0], operands[1], GEN_INT (i),
+ 			 	        const0_rtx));
+ 	          DONE;
+ 	        }
+-	      else if ((((HOST_WIDE_INT) 1) << i) - 1
++	      else if ((HOST_WIDE_INT_1 << i) - 1
+ 		       == ~INTVAL (operands[2]))
+ 	        {
+ 	          rtx shift = GEN_INT (i);
+@@ -2442,7 +2701,7 @@
+   {
+     int start_bit = INTVAL (operands[2]);
+     int width = INTVAL (operands[1]);
+-    HOST_WIDE_INT mask = (((HOST_WIDE_INT)1) << width) - 1;
++    HOST_WIDE_INT mask = (HOST_WIDE_INT_1 << width) - 1;
+     rtx target, subtarget;
+ 
+     if (arm_arch_thumb2)
+@@ -3050,7 +3309,14 @@
+ 	(xor:DI (match_operand:DI 1 "s_register_operand" "")
+ 		(match_operand:DI 2 "arm_xordi_operand" "")))]
+   "TARGET_32BIT"
+-  ""
++  {
++    /* The iWMMXt pattern for xordi3 accepts only register operands but we want
++       to reuse this expander for all TARGET_32BIT targets so just force the
++       constants into a register.  Unlike for the anddi3 and iordi3 there are
++       no NEON instructions that take an immediate.  */
++    if (TARGET_IWMMXT && !REG_P (operands[2]))
++      operands[2] = force_reg (DImode, operands[2]);
++  }
+ )
+ 
+ (define_insn_and_split "*xordi3_insn"
+@@ -3744,8 +4010,7 @@
+     {
+       rtx scratch1, scratch2;
+ 
+-      if (CONST_INT_P (operands[2])
+-	  && (HOST_WIDE_INT) INTVAL (operands[2]) == 1)
++      if (operands[2] == CONST1_RTX (SImode))
+         {
+           emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1]));
+           DONE;
+@@ -3790,7 +4055,7 @@
+   "TARGET_EITHER"
+   "
+   if (CONST_INT_P (operands[2])
+-      && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
++      && (UINTVAL (operands[2])) > 31)
+     {
+       emit_insn (gen_movsi (operands[0], const0_rtx));
+       DONE;
+@@ -3818,8 +4083,7 @@
+     {
+       rtx scratch1, scratch2;
+ 
+-      if (CONST_INT_P (operands[2])
+-	  && (HOST_WIDE_INT) INTVAL (operands[2]) == 1)
++      if (operands[2] == CONST1_RTX (SImode))
+         {
+           emit_insn (gen_arm_ashrdi3_1bit (operands[0], operands[1]));
+           DONE;
+@@ -3864,7 +4128,7 @@
+   "TARGET_EITHER"
+   "
+   if (CONST_INT_P (operands[2])
+-      && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
++      && UINTVAL (operands[2]) > 31)
+     operands[2] = GEN_INT (31);
+   "
+ )
+@@ -3889,8 +4153,7 @@
+     {
+       rtx scratch1, scratch2;
+ 
+-      if (CONST_INT_P (operands[2])
+-	  && (HOST_WIDE_INT) INTVAL (operands[2]) == 1)
++      if (operands[2] == CONST1_RTX (SImode))
+         {
+           emit_insn (gen_arm_lshrdi3_1bit (operands[0], operands[1]));
+           DONE;
+@@ -3935,7 +4198,7 @@
+   "TARGET_EITHER"
+   "
+   if (CONST_INT_P (operands[2])
+-      && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
++      && (UINTVAL (operands[2])) > 31)
+     {
+       emit_insn (gen_movsi (operands[0], const0_rtx));
+       DONE;
+@@ -3969,7 +4232,7 @@
+   if (TARGET_32BIT)
+     {
+       if (CONST_INT_P (operands[2])
+-          && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
++          && UINTVAL (operands[2]) > 31)
+         operands[2] = GEN_INT (INTVAL (operands[2]) % 32);
+     }
+   else /* TARGET_THUMB1 */
+@@ -4300,9 +4563,11 @@
+ (define_insn "*extv_reg"
+   [(set (match_operand:SI 0 "s_register_operand" "=r")
+ 	(sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
+-                         (match_operand:SI 2 "const_int_M_operand" "M")
+-                         (match_operand:SI 3 "const_int_M_operand" "M")))]
+-  "arm_arch_thumb2"
++			  (match_operand:SI 2 "const_int_operand" "n")
++			  (match_operand:SI 3 "const_int_operand" "n")))]
++  "arm_arch_thumb2
++   && IN_RANGE (INTVAL (operands[3]), 0, 31)
++   && IN_RANGE (INTVAL (operands[2]), 1, 32 - INTVAL (operands[3]))"
+   "sbfx%?\t%0, %1, %3, %2"
+   [(set_attr "length" "4")
+    (set_attr "predicable" "yes")
+@@ -4313,9 +4578,11 @@
+ (define_insn "extzv_t2"
+   [(set (match_operand:SI 0 "s_register_operand" "=r")
+ 	(zero_extract:SI (match_operand:SI 1 "s_register_operand" "r")
+-                         (match_operand:SI 2 "const_int_M_operand" "M")
+-                         (match_operand:SI 3 "const_int_M_operand" "M")))]
+-  "arm_arch_thumb2"
++			  (match_operand:SI 2 "const_int_operand" "n")
++			  (match_operand:SI 3 "const_int_operand" "n")))]
++  "arm_arch_thumb2
++   && IN_RANGE (INTVAL (operands[3]), 0, 31)
++   && IN_RANGE (INTVAL (operands[2]), 1, 32 - INTVAL (operands[3]))"
+   "ubfx%?\t%0, %1, %3, %2"
+   [(set_attr "length" "4")
+    (set_attr "predicable" "yes")
+@@ -4326,23 +4593,29 @@
+ 
+ ;; Division instructions
+ (define_insn "divsi3"
+-  [(set (match_operand:SI	  0 "s_register_operand" "=r")
+-	(div:SI (match_operand:SI 1 "s_register_operand"  "r")
+-		(match_operand:SI 2 "s_register_operand"  "r")))]
++  [(set (match_operand:SI	  0 "s_register_operand" "=r,r")
++	(div:SI (match_operand:SI 1 "s_register_operand"  "r,r")
++		(match_operand:SI 2 "s_register_operand"  "r,r")))]
+   "TARGET_IDIV"
+-  "sdiv%?\t%0, %1, %2"
+-  [(set_attr "predicable" "yes")
++  "@
++   sdiv%?\t%0, %1, %2
++   sdiv\t%0, %1, %2"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+    (set_attr "type" "sdiv")]
+ )
+ 
+ (define_insn "udivsi3"
+-  [(set (match_operand:SI	   0 "s_register_operand" "=r")
+-	(udiv:SI (match_operand:SI 1 "s_register_operand"  "r")
+-		 (match_operand:SI 2 "s_register_operand"  "r")))]
++  [(set (match_operand:SI	   0 "s_register_operand" "=r,r")
++	(udiv:SI (match_operand:SI 1 "s_register_operand"  "r,r")
++		 (match_operand:SI 2 "s_register_operand"  "r,r")))]
+   "TARGET_IDIV"
+-  "udiv%?\t%0, %1, %2"
+-  [(set_attr "predicable" "yes")
++  "@
++   udiv%?\t%0, %1, %2
++   udiv\t%0, %1, %2"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+    (set_attr "type" "udiv")]
+ )
+@@ -4350,6 +4623,63 @@
+ 
+ ;; Unary arithmetic insns
+ 
++(define_expand "negvsi3"
++  [(match_operand:SI 0 "register_operand")
++   (match_operand:SI 1 "register_operand")
++   (match_operand 2 "")]
++  "TARGET_32BIT"
++{
++  emit_insn (gen_subsi3_compare (operands[0], const0_rtx, operands[1]));
++  arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
++
++  DONE;
++})
++
++(define_expand "negvdi3"
++  [(match_operand:DI 0 "register_operand")
++   (match_operand:DI 1 "register_operand")
++   (match_operand 2 "")]
++  "TARGET_ARM"
++{
++  emit_insn (gen_negdi2_compare (operands[0], operands[1]));
++  arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
++
++  DONE;
++})
++
++
++(define_insn_and_split "negdi2_compare"
++  [(set (reg:CC CC_REGNUM)
++	(compare:CC
++	  (const_int 0)
++	  (match_operand:DI 1 "register_operand" "0,r")))
++   (set (match_operand:DI 0 "register_operand" "=r,&r")
++	(minus:DI (const_int 0) (match_dup 1)))]
++  "TARGET_ARM"
++  "#"
++  "&& reload_completed"
++  [(parallel [(set (reg:CC CC_REGNUM)
++		   (compare:CC (const_int 0) (match_dup 1)))
++	      (set (match_dup 0) (minus:SI (const_int 0)
++					   (match_dup 1)))])
++   (parallel [(set (reg:CC CC_REGNUM)
++		   (compare:CC (const_int 0) (match_dup 3)))
++	     (set (match_dup 2)
++		  (minus:SI
++		   (minus:SI (const_int 0) (match_dup 3))
++		   (ltu:SI (reg:CC_C CC_REGNUM)
++			   (const_int 0))))])]
++  {
++    operands[2] = gen_highpart (SImode, operands[0]);
++    operands[0] = gen_lowpart (SImode, operands[0]);
++    operands[3] = gen_highpart (SImode, operands[1]);
++    operands[1] = gen_lowpart (SImode, operands[1]);
++  }
++  [(set_attr "conds" "set")
++   (set_attr "length" "8")
++   (set_attr "type" "multiple")]
++)
++
+ (define_expand "negdi2"
+  [(parallel
+    [(set (match_operand:DI 0 "s_register_operand" "")
+@@ -4367,12 +4697,13 @@
+ 
+ ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
+ ;; The first alternative allows the common case of a *full* overlap.
+-(define_insn_and_split "*arm_negdi2"
++(define_insn_and_split "*negdi2_insn"
+   [(set (match_operand:DI         0 "s_register_operand" "=r,&r")
+ 	(neg:DI (match_operand:DI 1 "s_register_operand"  "0,r")))
+    (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_ARM"
+-  "#"   ; "rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0"
++  "TARGET_32BIT"
++  "#"	; rsbs %Q0, %Q1, #0; rsc %R0, %R1, #0	       (ARM)
++	; negs %Q0, %Q1    ; sbc %R0, %R1, %R1, lsl #1 (Thumb-2)
+   "&& reload_completed"
+   [(parallel [(set (reg:CC CC_REGNUM)
+ 		   (compare:CC (const_int 0) (match_dup 1)))
+@@ -4390,6 +4721,20 @@
+    (set_attr "type" "multiple")]
+ )
+ 
++(define_insn "*negsi2_carryin_compare"
++  [(set (reg:CC CC_REGNUM)
++	(compare:CC (const_int 0)
++		    (match_operand:SI 1 "s_register_operand" "r")))
++   (set (match_operand:SI 0 "s_register_operand" "=r")
++	(minus:SI (minus:SI (const_int 0)
++			    (match_dup 1))
++		  (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
++  "TARGET_ARM"
++  "rscs\\t%0, %1, #0"
++  [(set_attr "conds" "set")
++   (set_attr "type" "alus_imm")]
++)
++
+ (define_expand "negsi2"
+   [(set (match_operand:SI         0 "s_register_operand" "")
+ 	(neg:SI (match_operand:SI 1 "s_register_operand" "")))]
+@@ -4412,7 +4757,7 @@
+ (define_expand "negsf2"
+   [(set (match_operand:SF         0 "s_register_operand" "")
+ 	(neg:SF (match_operand:SF 1 "s_register_operand" "")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   ""
+ )
+ 
+@@ -4685,7 +5030,7 @@
+ (define_expand "sqrtsf2"
+   [(set (match_operand:SF 0 "s_register_operand" "")
+ 	(sqrt:SF (match_operand:SF 1 "s_register_operand" "")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "")
+ 
+ (define_expand "sqrtdf2"
+@@ -4854,7 +5199,7 @@
+   ""
+ )
+ 
+-/* DFmode -> HFmode conversions have to go through SFmode.  */
++;; DFmode to HFmode conversions have to go through SFmode.
+ (define_expand "truncdfhf2"
+   [(set (match_operand:HF  0 "general_operand" "")
+ 	(float_truncate:HF
+@@ -5117,7 +5462,7 @@
+ 		     (match_operator 5 "subreg_lowpart_operator"
+ 		      [(match_operand:SI 4 "s_register_operand" "")]))))]
+   "TARGET_32BIT
+-   && ((unsigned HOST_WIDE_INT) INTVAL (operands[3])
++   && (UINTVAL (operands[3])
+        == (GET_MODE_MASK (GET_MODE (operands[5]))
+            & (GET_MODE_MASK (GET_MODE (operands[5]))
+ 	      << (INTVAL (operands[2])))))"
+@@ -5361,7 +5706,7 @@
+   ""
+ )
+ 
+-/* HFmode -> DFmode conversions have to go through SFmode.  */
++;; HFmode -> DFmode conversions have to go through SFmode.
+ (define_expand "extendhfdf2"
+   [(set (match_operand:DF                  0 "general_operand" "")
+ 	(float_extend:DF (match_operand:HF 1 "general_operand"  "")))]
+@@ -5490,7 +5835,7 @@
+   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, q, m")
+ 	(match_operand:DI 1 "di_operand"              "rDa,Db,Dc,mi,q"))]
+   "TARGET_32BIT
+-   && !(TARGET_HARD_FLOAT && TARGET_VFP)
++   && !(TARGET_HARD_FLOAT)
+    && !TARGET_IWMMXT
+    && (   register_operand (operands[0], DImode)
+        || register_operand (operands[1], DImode))"
+@@ -5518,8 +5863,9 @@
+ 	(match_operand:ANY64 1 "immediate_operand" ""))]
+   "TARGET_32BIT
+    && reload_completed
+-   && (arm_const_double_inline_cost (operands[1])
+-       <= arm_max_const_double_inline_cost ())"
++   && (arm_disable_literal_pool
++       || (arm_const_double_inline_cost (operands[1])
++	   <= arm_max_const_double_inline_cost ()))"
+   [(const_int 0)]
+   "
+   arm_split_constant (SET, SImode, curr_insn,
+@@ -5612,7 +5958,7 @@
+   {
+   rtx base, offset, tmp;
+ 
+-  if (TARGET_32BIT)
++  if (TARGET_HAVE_MOVT)
+     {
+       /* Everything except mem = const or mem = mem can be done easily.  */
+       if (MEM_P (operands[0]))
+@@ -5636,7 +5982,7 @@
+ 	     }
+         }
+     }
+-  else /* TARGET_THUMB1...  */
++  else /* Target doesn't have MOVT...  */
+     {
+       if (can_create_pseudo_p ())
+         {
+@@ -5699,12 +6045,15 @@
+ ;; LO_SUM adds in the high bits.  Fortunately these are opaque operations
+ ;; so this does not matter.
+ (define_insn "*arm_movt"
+-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+-	(lo_sum:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+-		   (match_operand:SI 2 "general_operand"      "i")))]
+-  "arm_arch_thumb2 && arm_valid_symbolic_address_p (operands[2])"
+-  "movt%?\t%0, #:upper16:%c2"
+-  [(set_attr "predicable" "yes")
++  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r")
++	(lo_sum:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
++		   (match_operand:SI 2 "general_operand"      "i,i")))]
++  "TARGET_HAVE_MOVT && arm_valid_symbolic_address_p (operands[2])"
++  "@
++   movt%?\t%0, #:upper16:%c2
++   movt\t%0, #:upper16:%c2"
++  [(set_attr "arch"  "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+    (set_attr "length" "4")
+    (set_attr "type" "alu_sreg")]
+@@ -5713,8 +6062,7 @@
+ (define_insn "*arm_movsi_insn"
+   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
+ 	(match_operand:SI 1 "general_operand"      "rk, I,K,j,mi,rk"))]
+-  "TARGET_ARM && ! TARGET_IWMMXT
+-   && !(TARGET_HARD_FLOAT && TARGET_VFP)
++  "TARGET_ARM && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
+    && (   register_operand (operands[0], SImode)
+        || register_operand (operands[1], SImode))"
+   "@
+@@ -5726,6 +6074,7 @@
+    str%?\\t%1, %0"
+   [(set_attr "type" "mov_reg,mov_imm,mvn_imm,mov_imm,load1,store1")
+    (set_attr "predicable" "yes")
++   (set_attr "arch" "*,*,*,v6t2,*,*")
+    (set_attr "pool_range" "*,*,*,*,4096,*")
+    (set_attr "neg_pool_range" "*,*,*,*,4084,*")]
+ )
+@@ -5733,7 +6082,7 @@
+ (define_split
+   [(set (match_operand:SI 0 "arm_general_register_operand" "")
+ 	(match_operand:SI 1 "const_int_operand" ""))]
+-  "TARGET_32BIT
++  "TARGET_HAVE_MOVT
+   && (!(const_ok_for_arm (INTVAL (operands[1]))
+         || const_ok_for_arm (~INTVAL (operands[1]))))"
+   [(clobber (const_int 0))]
+@@ -5762,7 +6111,8 @@
+   [(set (match_operand:SI 0 "arm_general_register_operand" "")
+ 	(const:SI (plus:SI (match_operand:SI 1 "general_operand" "")
+ 			   (match_operand:SI 2 "const_int_operand" ""))))]
+-  "TARGET_THUMB2
++  "TARGET_THUMB
++   && TARGET_HAVE_MOVT
+    && arm_disable_literal_pool
+    && reload_completed
+    && GET_CODE (operands[1]) == SYMBOL_REF"
+@@ -5793,8 +6143,7 @@
+ (define_split
+   [(set (match_operand:SI 0 "arm_general_register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))]
+-  "TARGET_32BIT
+-   && TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF
++  "TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF
+    && !flag_pic && !target_word_relocations
+    && !arm_tls_referenced_p (operands[1])"
+   [(clobber (const_int 0))]
+@@ -6362,7 +6711,7 @@
+   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r")
+ 	(match_operand:HI 1 "general_operand"      "rIk,K,n,r,mi"))]
+   "TARGET_ARM
+-   && arm_arch4
++   && arm_arch4 && !TARGET_HARD_FLOAT
+    && (register_operand (operands[0], HImode)
+        || register_operand (operands[1], HImode))"
+   "@
+@@ -6388,7 +6737,7 @@
+ (define_insn "*movhi_bytes"
+   [(set (match_operand:HI 0 "s_register_operand" "=r,r,r")
+ 	(match_operand:HI 1 "arm_rhs_operand"  "I,rk,K"))]
+-  "TARGET_ARM"
++  "TARGET_ARM && !TARGET_HARD_FLOAT"
+   "@
+    mov%?\\t%0, %1\\t%@ movhi
+    mov%?\\t%0, %1\\t%@ movhi
+@@ -6396,7 +6745,7 @@
+   [(set_attr "predicable" "yes")
+    (set_attr "type" "mov_imm,mov_reg,mvn_imm")]
+ )
+-	
++
+ ;; We use a DImode scratch because we may occasionally need an additional
+ ;; temporary if the address isn't offsettable -- push_reload doesn't seem
+ ;; to take any notice of the "o" constraints on reload_memory_operand operand.
+@@ -6518,7 +6867,7 @@
+    strb%?\\t%1, %0"
+   [(set_attr "type" "mov_reg,mov_reg,mov_imm,mov_imm,mvn_imm,load1,store1,load1,store1")
+    (set_attr "predicable" "yes")
+-   (set_attr "predicable_short_it" "yes,yes,yes,no,no,no,no,no,no")
++   (set_attr "predicable_short_it" "yes,yes,no,yes,no,no,no,no,no")
+    (set_attr "arch" "t2,any,any,t2,any,t2,t2,any,any")
+    (set_attr "length" "2,4,4,2,4,2,2,4,4")]
+ )
+@@ -6548,7 +6897,7 @@
+ (define_insn "*arm32_movhf"
+   [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,r,r")
+ 	(match_operand:HF 1 "general_operand"	   " m,r,r,F"))]
+-  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16)
++  "TARGET_32BIT && !TARGET_HARD_FLOAT
+    && (	  s_register_operand (operands[0], HFmode)
+        || s_register_operand (operands[1], HFmode))"
+   "*
+@@ -6892,7 +7241,7 @@
+   [(set (pc) (if_then_else
+ 	      (match_operator 0 "expandable_comparison_operator"
+ 	       [(match_operand:SF 1 "s_register_operand" "")
+-	        (match_operand:SF 2 "arm_float_compare_operand" "")])
++	        (match_operand:SF 2 "vfp_compare_operand" "")])
+ 	      (label_ref (match_operand 3 "" ""))
+ 	      (pc)))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT"
+@@ -6904,7 +7253,7 @@
+   [(set (pc) (if_then_else
+ 	      (match_operator 0 "expandable_comparison_operator"
+ 	       [(match_operand:DF 1 "s_register_operand" "")
+-	        (match_operand:DF 2 "arm_float_compare_operand" "")])
++	        (match_operand:DF 2 "vfp_compare_operand" "")])
+ 	      (label_ref (match_operand 3 "" ""))
+ 	      (pc)))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
+@@ -7366,11 +7715,29 @@
+   DONE;
+ }")
+ 
++(define_expand "cstorehf4"
++  [(set (match_operand:SI 0 "s_register_operand")
++	(match_operator:SI 1 "expandable_comparison_operator"
++	 [(match_operand:HF 2 "s_register_operand")
++	  (match_operand:HF 3 "vfp_compare_operand")]))]
++  "TARGET_VFP_FP16INST"
++  {
++    if (!arm_validize_comparison (&operands[1],
++				  &operands[2],
++				  &operands[3]))
++       FAIL;
++
++    emit_insn (gen_cstore_cc (operands[0], operands[1],
++			      operands[2], operands[3]));
++    DONE;
++  }
++)
++
+ (define_expand "cstoresf4"
+   [(set (match_operand:SI 0 "s_register_operand" "")
+ 	(match_operator:SI 1 "expandable_comparison_operator"
+ 	 [(match_operand:SF 2 "s_register_operand" "")
+-	  (match_operand:SF 3 "arm_float_compare_operand" "")]))]
++	  (match_operand:SF 3 "vfp_compare_operand" "")]))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "emit_insn (gen_cstore_cc (operands[0], operands[1],
+ 			     operands[2], operands[3])); DONE;"
+@@ -7380,7 +7747,7 @@
+   [(set (match_operand:SI 0 "s_register_operand" "")
+ 	(match_operator:SI 1 "expandable_comparison_operator"
+ 	 [(match_operand:DF 2 "s_register_operand" "")
+-	  (match_operand:DF 3 "arm_float_compare_operand" "")]))]
++	  (match_operand:DF 3 "vfp_compare_operand" "")]))]
+   "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
+   "emit_insn (gen_cstore_cc (operands[0], operands[1],
+ 			     operands[2], operands[3])); DONE;"
+@@ -7418,9 +7785,31 @@
+     rtx ccreg;
+ 
+     if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0), 
+-       				  &XEXP (operands[1], 1)))
++				  &XEXP (operands[1], 1)))
+       FAIL;
+-    
++
++    code = GET_CODE (operands[1]);
++    ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
++				 XEXP (operands[1], 1), NULL_RTX);
++    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
++  }"
++)
++
++(define_expand "movhfcc"
++  [(set (match_operand:HF 0 "s_register_operand")
++	(if_then_else:HF (match_operand 1 "arm_cond_move_operator")
++			 (match_operand:HF 2 "s_register_operand")
++			 (match_operand:HF 3 "s_register_operand")))]
++  "TARGET_VFP_FP16INST"
++  "
++  {
++    enum rtx_code code = GET_CODE (operands[1]);
++    rtx ccreg;
++
++    if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0),
++				  &XEXP (operands[1], 1)))
++      FAIL;
++
+     code = GET_CODE (operands[1]);
+     ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
+ 				 XEXP (operands[1], 1), NULL_RTX);
+@@ -7439,7 +7828,7 @@
+     enum rtx_code code = GET_CODE (operands[1]);
+     rtx ccreg;
+ 
+-    if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0), 
++    if (!arm_validize_comparison (&operands[1], &XEXP (operands[1], 0),
+        				  &XEXP (operands[1], 1)))
+        FAIL;
+ 
+@@ -7504,6 +7893,37 @@
+    (set_attr "type" "fcsel")]
+ )
+ 
++(define_insn "*cmovhf"
++    [(set (match_operand:HF 0 "s_register_operand" "=t")
++	(if_then_else:HF (match_operator 1 "arm_vsel_comparison_operator"
++			 [(match_operand 2 "cc_register" "") (const_int 0)])
++			  (match_operand:HF 3 "s_register_operand" "t")
++			  (match_operand:HF 4 "s_register_operand" "t")))]
++  "TARGET_VFP_FP16INST"
++  "*
++  {
++    enum arm_cond_code code = maybe_get_arm_condition_code (operands[1]);
++    switch (code)
++      {
++      case ARM_GE:
++      case ARM_GT:
++      case ARM_EQ:
++      case ARM_VS:
++	return \"vsel%d1.f16\\t%0, %3, %4\";
++      case ARM_LT:
++      case ARM_LE:
++      case ARM_NE:
++      case ARM_VC:
++	return \"vsel%D1.f16\\t%0, %4, %3\";
++      default:
++	gcc_unreachable ();
++      }
++    return \"\";
++  }"
++  [(set_attr "conds" "use")
++   (set_attr "type" "fcsel")]
++)
++
+ (define_insn_and_split "*movsicc_insn"
+   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
+ 	(if_then_else:SI
+@@ -7627,6 +8047,7 @@
+   "
+   {
+     rtx callee, pat;
++    tree addr = MEM_EXPR (operands[0]);
+     
+     /* In an untyped call, we can get NULL for operand 2.  */
+     if (operands[2] == NULL_RTX)
+@@ -7641,8 +8062,17 @@
+ 	: !REG_P (callee))
+       XEXP (operands[0], 0) = force_reg (Pmode, callee);
+ 
+-    pat = gen_call_internal (operands[0], operands[1], operands[2]);
+-    arm_emit_call_insn (pat, XEXP (operands[0], 0), false);
++    if (detect_cmse_nonsecure_call (addr))
++      {
++	pat = gen_nonsecure_call_internal (operands[0], operands[1],
++					   operands[2]);
++	emit_call_insn (pat);
++      }
++    else
++      {
++	pat = gen_call_internal (operands[0], operands[1], operands[2]);
++	arm_emit_call_insn (pat, XEXP (operands[0], 0), false);
++      }
+     DONE;
+   }"
+ )
+@@ -7653,6 +8083,24 @@
+ 	      (use (match_operand 2 "" ""))
+ 	      (clobber (reg:SI LR_REGNUM))])])
+ 
++(define_expand "nonsecure_call_internal"
++  [(parallel [(call (unspec:SI [(match_operand 0 "memory_operand" "")]
++			       UNSPEC_NONSECURE_MEM)
++		    (match_operand 1 "general_operand" ""))
++	      (use (match_operand 2 "" ""))
++	      (clobber (reg:SI LR_REGNUM))
++	      (clobber (reg:SI 4))])]
++  "use_cmse"
++  "
++  {
++    rtx tmp;
++    tmp = copy_to_suggested_reg (XEXP (operands[0], 0),
++				 gen_rtx_REG (SImode, 4),
++				 SImode);
++
++    operands[0] = replace_equiv_address (operands[0], tmp);
++  }")
++
+ (define_insn "*call_reg_armv5"
+   [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
+          (match_operand 1 "" ""))
+@@ -7688,6 +8136,7 @@
+   "
+   {
+     rtx pat, callee;
++    tree addr = MEM_EXPR (operands[1]);
+     
+     /* In an untyped call, we can get NULL for operand 2.  */
+     if (operands[3] == 0)
+@@ -7702,9 +8151,18 @@
+ 	: !REG_P (callee))
+       XEXP (operands[1], 0) = force_reg (Pmode, callee);
+ 
+-    pat = gen_call_value_internal (operands[0], operands[1],
+-				   operands[2], operands[3]);
+-    arm_emit_call_insn (pat, XEXP (operands[1], 0), false);
++    if (detect_cmse_nonsecure_call (addr))
++      {
++	pat = gen_nonsecure_call_value_internal (operands[0], operands[1],
++						 operands[2], operands[3]);
++	emit_call_insn (pat);
++      }
++    else
++      {
++	pat = gen_call_value_internal (operands[0], operands[1],
++				       operands[2], operands[3]);
++	arm_emit_call_insn (pat, XEXP (operands[1], 0), false);
++      }
+     DONE;
+   }"
+ )
+@@ -7716,6 +8174,25 @@
+ 	      (use (match_operand 3 "" ""))
+ 	      (clobber (reg:SI LR_REGNUM))])])
+ 
++(define_expand "nonsecure_call_value_internal"
++  [(parallel [(set (match_operand       0 "" "")
++		   (call (unspec:SI [(match_operand 1 "memory_operand" "")]
++				    UNSPEC_NONSECURE_MEM)
++			 (match_operand 2 "general_operand" "")))
++	      (use (match_operand 3 "" ""))
++	      (clobber (reg:SI LR_REGNUM))
++	      (clobber (reg:SI 4))])]
++  "use_cmse"
++  "
++  {
++    rtx tmp;
++    tmp = copy_to_suggested_reg (XEXP (operands[1], 0),
++				 gen_rtx_REG (SImode, 4),
++				 SImode);
++
++    operands[1] = replace_equiv_address (operands[1], tmp);
++  }")
++
+ (define_insn "*call_value_reg_armv5"
+   [(set (match_operand 0 "" "")
+         (call (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
+@@ -8153,8 +8630,8 @@
+ )
+ 
+ (define_insn "probe_stack"
+-  [(set (match_operand 0 "memory_operand" "=m")
+-        (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
++  [(set (match_operand:SI 0 "memory_operand" "=m")
++        (unspec:SI [(const_int 0)] UNSPEC_PROBE_STACK))]
+   "TARGET_32BIT"
+   "str%?\\tr0, %0"
+   [(set_attr "type" "store1")
+@@ -8180,7 +8657,7 @@
+    (match_operand:SI 2 "const_int_operand" "")	; total range
+    (match_operand:SI 3 "" "")			; table label
+    (match_operand:SI 4 "" "")]			; Out of range label
+-  "TARGET_32BIT || optimize_size || flag_pic"
++  "(TARGET_32BIT || optimize_size || flag_pic) && !target_pure_code"
+   "
+   {
+     enum insn_code code;
+@@ -10221,8 +10698,8 @@
+ 	 (match_operand 1 "const_int_operand" "")))
+    (clobber (match_scratch:SI 2 ""))]
+   "TARGET_ARM
+-   && (((unsigned HOST_WIDE_INT) INTVAL (operands[1]))
+-       == (((unsigned HOST_WIDE_INT) INTVAL (operands[1])) >> 24) << 24)"
++   && ((UINTVAL (operands[1]))
++       == ((UINTVAL (operands[1])) >> 24) << 24)"
+   [(set (match_dup 2) (zero_extend:SI (match_dup 0)))
+    (set (reg:CC CC_REGNUM) (compare:CC (match_dup 2) (match_dup 1)))]
+   "
+@@ -10562,7 +11039,11 @@
+   }
+   "
+   [(set_attr "type" "load4")
+-   (set_attr "predicable" "yes")]
++   (set_attr "predicable" "yes")
++   (set (attr "length")
++	(symbol_ref "arm_attr_length_pop_multi (operands,
++						/*return_pc=*/false,
++						/*write_back_p=*/true)"))]
+ )
+ 
+ ;; Pop with return (as used in epilogue RTL)
+@@ -10591,7 +11072,10 @@
+   }
+   "
+   [(set_attr "type" "load4")
+-   (set_attr "predicable" "yes")]
++   (set_attr "predicable" "yes")
++   (set (attr "length")
++	(symbol_ref "arm_attr_length_pop_multi (operands, /*return_pc=*/true,
++						/*write_back_p=*/true)"))]
+ )
+ 
+ (define_insn "*pop_multiple_with_return"
+@@ -10611,7 +11095,10 @@
+   }
+   "
+   [(set_attr "type" "load4")
+-   (set_attr "predicable" "yes")]
++   (set_attr "predicable" "yes")
++   (set (attr "length")
++	(symbol_ref "arm_attr_length_pop_multi (operands, /*return_pc=*/true,
++						/*write_back_p=*/false)"))]
+ )
+ 
+ ;; Load into PC and return
+@@ -10632,7 +11119,7 @@
+                    (match_operand:SI 2 "const_int_I_operand" "I")))
+      (set (match_operand:DF 3 "vfp_hard_register_operand" "")
+           (mem:DF (match_dup 1)))])]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "*
+   {
+     int num_regs = XVECLEN (operands[0], 0);
+@@ -10822,19 +11309,22 @@
+    (set_attr "predicable_short_it" "no")
+    (set_attr "type" "clz")])
+ 
+-(define_expand "ctzsi2"
+- [(set (match_operand:SI           0 "s_register_operand" "")
+-       (ctz:SI (match_operand:SI  1 "s_register_operand" "")))]
++;; Keep this as a CTZ expression until after reload and then split
++;; into RBIT + CLZ.  Since RBIT is represented as an UNSPEC it is unlikely
++;; to fold with any other expression.
++
++(define_insn_and_split "ctzsi2"
++ [(set (match_operand:SI           0 "s_register_operand" "=r")
++       (ctz:SI (match_operand:SI  1 "s_register_operand" "r")))]
+   "TARGET_32BIT && arm_arch_thumb2"
++  "#"
++  "&& reload_completed"
++  [(const_int 0)]
+   "
+-   {
+-     rtx tmp = gen_reg_rtx (SImode); 
+-     emit_insn (gen_rbitsi2 (tmp, operands[1]));
+-     emit_insn (gen_clzsi2 (operands[0], tmp));
+-   }
+-   DONE;
+-  "
+-)
++  emit_insn (gen_rbitsi2 (operands[0], operands[1]));
++  emit_insn (gen_clzsi2 (operands[0], operands[0]));
++  DONE;
++")
+ 
+ ;; V5E instructions.
+ 
+@@ -10958,13 +11448,16 @@
+ ;; We only care about the lower 16 bits of the constant 
+ ;; being inserted into the upper 16 bits of the register.
+ (define_insn "*arm_movtas_ze" 
+-  [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
++  [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r,r")
+                    (const_int 16)
+                    (const_int 16))
+         (match_operand:SI 1 "const_int_operand" ""))]
+-  "arm_arch_thumb2"
+-  "movt%?\t%0, %L1"
+- [(set_attr "predicable" "yes")
++  "TARGET_HAVE_MOVT"
++  "@
++   movt%?\t%0, %L1
++   movt\t%0, %L1"
++ [(set_attr "arch" "32,v8mb")
++  (set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")
+   (set_attr "length" "4")
+   (set_attr "type" "alu_sreg")]
+@@ -11331,12 +11824,15 @@
+ 
+ ;; Patterns in ldmstm.md don't cover more than 4 registers. This pattern covers
+ ;; large lists without explicit writeback generated for APCS_FRAME epilogue.
++;; The operands are validated through the load_multiple_operation
++;; match_parallel predicate rather than through constraints so enable it only
++;; after reload.
+ (define_insn "*load_multiple"
+   [(match_parallel 0 "load_multiple_operation"
+     [(set (match_operand:SI 2 "s_register_operand" "=rk")
+           (mem:SI (match_operand:SI 1 "s_register_operand" "rk")))
+         ])]
+-  "TARGET_32BIT"
++  "TARGET_32BIT && reload_completed"
+   "*
+   {
+     arm_output_multireg_pop (operands, /*return_pc=*/false,
+--- a/src/gcc/config/arm/arm.opt
++++ b/src/gcc/config/arm/arm.opt
+@@ -61,10 +61,6 @@ Generate a call to abort if a noreturn function returns.
+ mapcs
+ Target RejectNegative Mask(APCS_FRAME) Undocumented
+ 
+-mapcs-float
+-Target Report Mask(APCS_FLOAT)
+-Pass FP arguments in FP registers.
+-
+ mapcs-frame
+ Target Report Mask(APCS_FRAME)
+ Generate APCS conformant stack frames.
+@@ -109,6 +105,10 @@ mfloat-abi=
+ Target RejectNegative Joined Enum(float_abi_type) Var(arm_float_abi) Init(TARGET_DEFAULT_FLOAT_ABI)
+ Specify if floating point hardware should be used.
+ 
++mcmse
++Target RejectNegative Var(use_cmse)
++Specify that the compiler should target secure code as per ARMv8-M Security Extensions.
++
+ Enum
+ Name(float_abi_type) Type(enum float_abi_type)
+ Known floating-point ABIs (for use with the -mfloat-abi= option):
+@@ -253,14 +253,6 @@ mrestrict-it
+ Target Report Var(arm_restrict_it) Init(2) Save
+ Generate IT blocks appropriate for ARMv8.
+ 
+-mold-rtx-costs
+-Target Report Mask(OLD_RTX_COSTS)
+-Use the old RTX costing tables (transitional).
+-
+-mnew-generic-costs
+-Target Report Mask(NEW_GENERIC_COSTS)
+-Use the new generic RTX cost tables if new core-specific cost table not available (transitional).
+-
+ mfix-cortex-m3-ldrd
+ Target Report Var(fix_cm3_ldrd) Init(2)
+ Avoid overlapping destination and address registers on LDRD instructions
+@@ -281,3 +273,7 @@ Assume loading data from flash is slower than fetching instructions.
+ masm-syntax-unified
+ Target Report Var(inline_asm_unified) Init(0) Save
+ Assume unified syntax for inline assembly code.
++
++mpure-code
++Target Report Var(target_pure_code) Init(0)
++Do not allow constant data to be placed in code sections.
+--- /dev/null
++++ b/src/gcc/config/arm/arm_cmse.h
+@@ -0,0 +1,199 @@
++/* ARMv8-M Secure Extensions intrinsics include file.
++
++   Copyright (C) 2015-2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   Under Section 7 of GPL version 3, you are granted additional
++   permissions described in the GCC Runtime Library Exception, version
++   3.1, as published by the Free Software Foundation.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++
++#ifndef _GCC_ARM_CMSE_H
++#define _GCC_ARM_CMSE_H
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#if __ARM_FEATURE_CMSE & 1
++
++#include <stddef.h>
++#include <stdint.h>
++
++#ifdef __ARM_BIG_ENDIAN
++
++typedef union {
++  struct cmse_address_info {
++#if __ARM_FEATURE_CMSE & 2
++    unsigned idau_region:8;
++    unsigned idau_region_valid:1;
++    unsigned secure:1;
++    unsigned nonsecure_readwrite_ok:1;
++    unsigned nonsecure_read_ok:1;
++#else
++    unsigned :12;
++#endif
++    unsigned readwrite_ok:1;
++    unsigned read_ok:1;
++#if __ARM_FEATURE_CMSE & 2
++    unsigned sau_region_valid:1;
++#else
++    unsigned :1;
++#endif
++    unsigned mpu_region_valid:1;
++#if __ARM_FEATURE_CMSE & 2
++    unsigned sau_region:8;
++#else
++    unsigned :8;
++#endif
++    unsigned mpu_region:8;
++  } flags;
++  unsigned value;
++} cmse_address_info_t;
++
++#else
++
++typedef union {
++  struct cmse_address_info {
++    unsigned mpu_region:8;
++#if __ARM_FEATURE_CMSE & 2
++    unsigned sau_region:8;
++#else
++    unsigned :8;
++#endif
++    unsigned mpu_region_valid:1;
++#if __ARM_FEATURE_CMSE & 2
++    unsigned sau_region_valid:1;
++#else
++    unsigned :1;
++#endif
++    unsigned read_ok:1;
++    unsigned readwrite_ok:1;
++#if __ARM_FEATURE_CMSE & 2
++    unsigned nonsecure_read_ok:1;
++    unsigned nonsecure_readwrite_ok:1;
++    unsigned secure:1;
++    unsigned idau_region_valid:1;
++    unsigned idau_region:8;
++#else
++    unsigned :12;
++#endif
++  } flags;
++  unsigned value;
++} cmse_address_info_t;
++
++#endif /* __ARM_BIG_ENDIAN */
++
++#define cmse_TT_fptr(p) (__cmse_TT_fptr ((__cmse_fptr)(p)))
++
++typedef void (*__cmse_fptr)(void);
++
++#define __CMSE_TT_ASM(flags) \
++{ \
++  cmse_address_info_t __result; \
++   __asm__ ("tt" # flags " %0,%1" \
++	   : "=r"(__result) \
++	   : "r"(__p) \
++	   : "memory"); \
++  return __result; \
++}
++
++__extension__ static __inline __attribute__ ((__always_inline__))
++cmse_address_info_t
++__cmse_TT_fptr (__cmse_fptr __p)
++__CMSE_TT_ASM ()
++
++__extension__ static __inline __attribute__ ((__always_inline__))
++cmse_address_info_t
++cmse_TT (void *__p)
++__CMSE_TT_ASM ()
++
++#define cmse_TTT_fptr(p) (__cmse_TTT_fptr ((__cmse_fptr)(p)))
++
++__extension__ static __inline __attribute__ ((__always_inline__))
++cmse_address_info_t
++__cmse_TTT_fptr (__cmse_fptr __p)
++__CMSE_TT_ASM (t)
++
++__extension__ static __inline __attribute__ ((__always_inline__))
++cmse_address_info_t
++cmse_TTT (void *__p)
++__CMSE_TT_ASM (t)
++
++#if __ARM_FEATURE_CMSE & 2
++
++#define cmse_TTA_fptr(p) (__cmse_TTA_fptr ((__cmse_fptr)(p)))
++
++__extension__ static __inline __attribute__ ((__always_inline__))
++cmse_address_info_t
++__cmse_TTA_fptr (__cmse_fptr __p)
++__CMSE_TT_ASM (a)
++
++__extension__ static __inline __attribute__ ((__always_inline__))
++cmse_address_info_t
++cmse_TTA (void *__p)
++__CMSE_TT_ASM (a)
++
++#define cmse_TTAT_fptr(p) (__cmse_TTAT_fptr ((__cmse_fptr)(p)))
++
++__extension__ static __inline cmse_address_info_t
++__attribute__ ((__always_inline__))
++__cmse_TTAT_fptr (__cmse_fptr __p)
++__CMSE_TT_ASM (at)
++
++__extension__ static __inline cmse_address_info_t
++__attribute__ ((__always_inline__))
++cmse_TTAT (void *__p)
++__CMSE_TT_ASM (at)
++
++/* FIXME: diagnose use outside cmse_nonsecure_entry functions.  */
++__extension__ static __inline int __attribute__ ((__always_inline__))
++cmse_nonsecure_caller (void)
++{
++  return __builtin_arm_cmse_nonsecure_caller ();
++}
++
++#define CMSE_AU_NONSECURE	2
++#define CMSE_MPU_NONSECURE	16
++#define CMSE_NONSECURE		18
++
++#define cmse_nsfptr_create(p) ((typeof ((p))) ((intptr_t) (p) & ~1))
++
++#define cmse_is_nsfptr(p) (!((intptr_t) (p) & 1))
++
++#endif /* __ARM_FEATURE_CMSE & 2 */
++
++#define CMSE_MPU_UNPRIV		4
++#define CMSE_MPU_READWRITE	1
++#define CMSE_MPU_READ		8
++
++__extension__ void *
++cmse_check_address_range (void *, size_t, int);
++
++#define cmse_check_pointed_object(p, f) \
++  ((typeof ((p))) cmse_check_address_range ((p), sizeof (*(p)), (f)))
++
++#endif /* __ARM_FEATURE_CMSE & 1 */
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _GCC_ARM_CMSE_H */
+--- /dev/null
++++ b/src/gcc/config/arm/arm_fp16.h
+@@ -0,0 +1,255 @@
++/* ARM FP16 intrinsics include file.
++
++   Copyright (C) 2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   Under Section 7 of GPL version 3, you are granted additional
++   permissions described in the GCC Runtime Library Exception, version
++   3.1, as published by the Free Software Foundation.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++#ifndef _GCC_ARM_FP16_H
++#define _GCC_ARM_FP16_H 1
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#include <stdint.h>
++
++/* Intrinsics for FP16 instructions.  */
++#pragma GCC push_options
++#pragma GCC target ("fpu=fp-armv8")
++
++#if defined (__ARM_FEATURE_FP16_SCALAR_ARITHMETIC)
++
++typedef __fp16 float16_t;
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vabsh_f16 (float16_t __a)
++{
++  return __builtin_neon_vabshf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vaddh_f16 (float16_t __a, float16_t __b)
++{
++  return __a + __b;
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtah_s32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtahssi (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtah_u32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtahusi (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_s32 (int32_t __a)
++{
++  return __builtin_neon_vcvthshf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_f16_u32 (uint32_t __a)
++{
++  return __builtin_neon_vcvthuhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_s32 (int32_t __a, const int __b)
++{
++  return __builtin_neon_vcvths_nhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vcvth_n_f16_u32 (uint32_t __a, const int __b)
++{
++  return __builtin_neon_vcvthu_nhf ((int32_t)__a, __b);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvth_n_s32_f16 (float16_t __a, const int __b)
++{
++  return __builtin_neon_vcvths_nsi (__a, __b);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvth_n_u32_f16 (float16_t __a, const int __b)
++{
++  return (uint32_t)__builtin_neon_vcvthu_nsi (__a, __b);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvth_s32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvthssi (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvth_u32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvthusi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtmh_s32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtmhssi (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtmh_u32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtmhusi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtnh_s32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtnhssi (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtnh_u32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtnhusi (__a);
++}
++
++__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++vcvtph_s32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtphssi (__a);
++}
++
++__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++vcvtph_u32_f16 (float16_t __a)
++{
++  return __builtin_neon_vcvtphusi (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vdivh_f16 (float16_t __a, float16_t __b)
++{
++  return __a / __b;
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vfmah_f16 (float16_t __a, float16_t __b, float16_t __c)
++{
++  return __builtin_neon_vfmahf (__a, __b, __c);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vfmsh_f16 (float16_t __a, float16_t __b, float16_t __c)
++{
++  return __builtin_neon_vfmshf (__a, __b, __c);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vmaxnmh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_neon_vmaxnmhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vminnmh_f16 (float16_t __a, float16_t __b)
++{
++  return __builtin_neon_vminnmhf (__a, __b);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vmulh_f16 (float16_t __a, float16_t __b)
++{
++  return __a * __b;
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vnegh_f16 (float16_t __a)
++{
++  return  - __a;
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndah_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndahf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndh_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndih_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndihf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndmh_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndmhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndnh_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndnhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndph_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndphf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vrndxh_f16 (float16_t __a)
++{
++  return __builtin_neon_vrndxhf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vsqrth_f16 (float16_t __a)
++{
++  return __builtin_neon_vsqrthf (__a);
++}
++
++__extension__ static __inline float16_t __attribute__ ((__always_inline__))
++vsubh_f16 (float16_t __a, float16_t __b)
++{
++  return __a - __b;
++}
++
++#endif /* __ARM_FEATURE_FP16_SCALAR_ARITHMETIC  */
++#pragma GCC pop_options
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif
+--- a/src/gcc/config/arm/arm_neon.h
++++ b/src/gcc/config/arm/arm_neon.h
+@@ -38,6 +38,7 @@
+ extern "C" {
+ #endif
+ 
++#include <arm_fp16.h>
+ #include <stdint.h>
+ 
+ typedef __simd64_int8_t int8x8_t;
+@@ -509,528 +510,614 @@ typedef struct poly64x2x4_t
+ #pragma GCC pop_options
+ 
+ /* vadd  */
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-#ifdef __FAST_MATH
++#ifdef __FAST_MATH__
+   return __a + __b;
+ #else
+   return (float32x2_t) __builtin_neon_vaddv2sf (__a, __b);
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vadd_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-#ifdef __FAST_MATH
++#ifdef __FAST_MATH__
+   return __a + __b;
+ #else
+   return (float32x4_t) __builtin_neon_vaddv4sf (__a, __b);
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a + __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vaddlsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vaddlsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vaddlsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vaddluv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vaddluv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddl_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vaddluv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_s8 (int16x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vaddwsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_s16 (int32x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vaddwsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_s32 (int64x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vaddwsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_u8 (uint16x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vaddwuv8qi ((int16x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_u16 (uint32x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vaddwuv4hi ((int32x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddw_u32 (uint64x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vaddwuv2si ((int64x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vhaddsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vhaddsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vhaddsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vhadduv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vhadduv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vhadduv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vhaddsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vhaddsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vhaddsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vhadduv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vhadduv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vhadduv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vrhaddsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vrhaddsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vrhaddsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vrhadduv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vrhadduv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vrhadduv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vrhaddsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vrhaddsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vrhaddsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vrhadduv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vrhadduv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrhaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vrhadduv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vqaddsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqaddsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqaddsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vqaddsdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqadduv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqadduv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqadduv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqadd_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vqaddudi ((int64x1_t) __a, (int64x1_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vqaddsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqaddsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqaddsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vqaddsv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vqadduv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vqadduv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vqadduv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqaddq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vqadduv2di ((int64x2_t) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vaddhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vaddhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vaddhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vaddhnv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vaddhnv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaddhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vaddhnv2di ((int64x2_t) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vraddhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vraddhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vraddhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vraddhnv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vraddhnv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vraddhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vraddhnv2di ((int64x2_t) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-#ifdef __FAST_MATH
++#ifdef __FAST_MATH__
+   return __a * __b;
+ #else
+   return (float32x2_t) __builtin_neon_vmulfv2sf (__a, __b);
+@@ -1038,493 +1125,574 @@ vmul_f32 (float32x2_t __a, float32x2_t __b)
+ 
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-#ifdef __FAST_MATH
++#ifdef __FAST_MATH__
+   return __a * __b;
+ #else
+   return (float32x4_t) __builtin_neon_vmulfv4sf (__a, __b);
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a * __b;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (poly8x8_t)__builtin_neon_vmulpv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   return (poly8x16_t)__builtin_neon_vmulpv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqdmulhv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqdmulhv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqdmulhv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqdmulhv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmulhv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmulhv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmulhv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmulhv4si (__a, __b);
+ }
+ 
+ #ifdef __ARM_FEATURE_QRDMX
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlah_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmlahv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlah_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmlahv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlahq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmlahv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlahq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmlahv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlsh_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmlshv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlsh_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmlshv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlshq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmlshv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlshq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmlshv4si (__a, __b, __c);
+ }
+ #endif
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vmullsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vmullsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vmullsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vmulluv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vmulluv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vmulluv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (poly16x8_t)__builtin_neon_vmullpv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmull_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqdmullv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmull_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vqdmullv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int8x8_t)__builtin_neon_vmlav8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vmlav4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vmlav2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vmlav2sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint8x8_t)__builtin_neon_vmlav8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint16x4_t)__builtin_neon_vmlav4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint32x2_t)__builtin_neon_vmlav2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c)
+ {
+   return (int8x16_t)__builtin_neon_vmlav16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vmlav8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmlav4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vmlav4sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
+ {
+   return (uint8x16_t)__builtin_neon_vmlav16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmlav8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmlav4si ((int32x4_t) __a, (int32x4_t) __b, (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_s8 (int16x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vmlalsv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmlalsv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vmlalsv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_u8 (uint16x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmlaluv8qi ((int16x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmlaluv4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint64x2_t)__builtin_neon_vmlaluv2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vqdmlalv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vqdmlalv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int8x8_t)__builtin_neon_vmlsv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vmlsv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vmlsv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vmlsv2sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint8x8_t)__builtin_neon_vmlsv8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint16x4_t)__builtin_neon_vmlsv4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint32x2_t)__builtin_neon_vmlsv2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c)
+ {
+   return (int8x16_t)__builtin_neon_vmlsv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vmlsv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmlsv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vmlsv4sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
+ {
+   return (uint8x16_t)__builtin_neon_vmlsv16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmlsv8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmlsv4si ((int32x4_t) __a, (int32x4_t) __b, (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_s8 (int16x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vmlslsv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmlslsv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vmlslsv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_u8 (uint16x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmlsluv8qi ((int16x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmlsluv4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint64x2_t)__builtin_neon_vmlsluv2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vqdmlslv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vqdmlslv2si (__a, __b, __c);
+@@ -1532,25 +1700,29 @@ vqdmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=neon-vfpv4")
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vfma_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vfmav2sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vfmaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vfmav4sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vfms_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vfmsv2sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vfmsv4sf (__a, __b, __c);
+@@ -1558,7 +1730,8 @@ vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+ #pragma GCC pop_options
+ 
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndn_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrintnv2sf (__a);
+@@ -1566,7 +1739,8 @@ vrndn_f32 (float32x2_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndnq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrintnv4sf (__a);
+@@ -1574,7 +1748,8 @@ vrndnq_f32 (float32x4_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrnda_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrintav2sf (__a);
+@@ -1582,7 +1757,8 @@ vrnda_f32 (float32x2_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndaq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrintav4sf (__a);
+@@ -1590,7 +1766,8 @@ vrndaq_f32 (float32x4_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndp_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrintpv2sf (__a);
+@@ -1598,7 +1775,8 @@ vrndp_f32 (float32x2_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndpq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrintpv4sf (__a);
+@@ -1606,7 +1784,8 @@ vrndpq_f32 (float32x4_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndm_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrintmv2sf (__a);
+@@ -1614,7 +1793,8 @@ vrndm_f32 (float32x2_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndmq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrintmv4sf (__a);
+@@ -1623,7 +1803,8 @@ vrndmq_f32 (float32x4_t __a)
+ #endif
+ 
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndx_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrintxv2sf (__a);
+@@ -1632,7 +1813,8 @@ vrndx_f32 (float32x2_t __a)
+ #endif
+ 
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndxq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrintxv4sf (__a);
+@@ -1641,7 +1823,8 @@ vrndxq_f32 (float32x4_t __a)
+ #endif
+ 
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrnd_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrintzv2sf (__a);
+@@ -1649,7 +1832,8 @@ vrnd_f32 (float32x2_t __a)
+ 
+ #endif
+ #if __ARM_ARCH >= 8
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrndq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrintzv4sf (__a);
+@@ -1657,2907 +1841,3436 @@ vrndq_f32 (float32x4_t __a)
+ 
+ #endif
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_f32 (float32x2_t __a, float32x2_t __b)
+ {
+-#ifdef __FAST_MATH
++#ifdef __FAST_MATH__
+   return __a - __b;
+ #else
+   return (float32x2_t) __builtin_neon_vsubv2sf (__a, __b);
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsub_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+-#ifdef __FAST_MATH
++#ifdef __FAST_MATH__
+   return __a - __b;
+ #else
+   return (float32x4_t) __builtin_neon_vsubv4sf (__a, __b);
+ #endif
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a - __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vsublsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vsublsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vsublsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vsubluv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vsubluv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubl_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vsubluv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_s8 (int16x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vsubwsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_s16 (int32x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vsubwsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_s32 (int64x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vsubwsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_u8 (uint16x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vsubwuv8qi ((int16x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_u16 (uint32x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vsubwuv4hi ((int32x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubw_u32 (uint64x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vsubwuv2si ((int64x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vhsubsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vhsubsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vhsubsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vhsubuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vhsubuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsub_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vhsubuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vhsubsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vhsubsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vhsubsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vhsubuv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vhsubuv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vhsubq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vhsubuv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vqsubsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqsubsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqsubsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vqsubsdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqsubuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqsubuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqsubuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsub_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vqsubudi ((int64x1_t) __a, (int64x1_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vqsubsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqsubsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqsubsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vqsubsv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vqsubuv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vqsubuv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vqsubuv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqsubq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vqsubuv2di ((int64x2_t) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vsubhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vsubhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vsubhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vsubhnv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vsubhnv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsubhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vsubhnv2di ((int64x2_t) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vrsubhnv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vrsubhnv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vrsubhnv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vrsubhnv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vrsubhnv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsubhn_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vrsubhnv2di ((int64x2_t) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vceqv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vceqv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vceqv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vceqv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vceqv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vceqv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vceqv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vceqv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vceqv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vceqv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vceqv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vceqv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vceqv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vceqv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vceqv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceqq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vceqv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgev8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgev4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgev2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgev2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgeuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgeuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcge_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgeuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgev16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgev8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgev4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgev4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgeuv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgeuv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgeq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgeuv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgev8qi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgev4hi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgev2si (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgev2sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgeuv8qi ((int8x8_t) __b, (int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgeuv4hi ((int16x4_t) __b, (int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcle_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgeuv2si ((int32x2_t) __b, (int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgev16qi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgev8hi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgev4si (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgev4sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgeuv16qi ((int8x16_t) __b, (int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgeuv8hi ((int16x8_t) __b, (int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcleq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgeuv4si ((int32x4_t) __b, (int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgtv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgtv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgtv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgtv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgtuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgtuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgt_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgtuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgtv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgtv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgtv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgtv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgtuv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgtuv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcgtq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgtuv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgtv8qi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgtv4hi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgtv2si (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgtv2sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vcgtuv8qi ((int8x8_t) __b, (int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vcgtuv4hi ((int16x4_t) __b, (int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclt_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcgtuv2si ((int32x2_t) __b, (int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgtv16qi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgtv8hi (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgtv4si (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgtv4sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcgtuv16qi ((int8x16_t) __b, (int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcgtuv8hi ((int16x8_t) __b, (int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcltq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcgtuv4si ((int32x4_t) __b, (int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcage_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcagev2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcageq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcagev4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcale_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcagev2sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcaleq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcagev4sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcagt_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcagtv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcagtq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcagtv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcalt_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcagtv2sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcaltq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcagtv4sf (__b, __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vtstv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vtstv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vtstv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vtstv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vtstv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vtstv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vtstv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vtst_p16 (poly16x4_t __a, poly16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vtstv4hi ((int16x4_t) __a, (int16x4_t) __b);
++}
++
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vtstv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vtstv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vtstv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vtstv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vtstv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vtstv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtstq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vtstv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vtstq_p16 (poly16x8_t __a, poly16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vtstv8hi ((int16x8_t) __a, (int16x8_t) __b);
++}
++
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vabdsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vabdsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vabdsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vabdfv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vabduv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vabduv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vabduv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vabdsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vabdsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vabdsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vabdfv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vabduv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vabduv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vabduv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vabdlsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vabdlsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vabdlsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vabdluv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vabdluv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabdl_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vabdluv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int8x8_t)__builtin_neon_vabasv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vabasv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vabasv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint8x8_t)__builtin_neon_vabauv8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint16x4_t)__builtin_neon_vabauv4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaba_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint32x2_t)__builtin_neon_vabauv2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c)
+ {
+   return (int8x16_t)__builtin_neon_vabasv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vabasv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vabasv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
+ {
+   return (uint8x16_t)__builtin_neon_vabauv16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vabauv8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabaq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vabauv4si ((int32x4_t) __a, (int32x4_t) __b, (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_s8 (int16x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vabalsv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vabalsv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vabalsv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_u8 (uint16x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vabaluv8qi ((int16x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vabaluv4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabal_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint64x2_t)__builtin_neon_vabaluv2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vmaxsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vmaxsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vmaxsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vmaxfv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vmaxuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vmaxuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmax_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vmaxuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vmaxsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vmaxsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vmaxsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vmaxfv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++#pragma GCC push_options
++#pragma GCC target ("fpu=neon-fp-armv8")
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnm_f32 (float32x2_t a, float32x2_t b)
++{
++  return (float32x2_t)__builtin_neon_vmaxnmv2sf (a, b);
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmq_f32 (float32x4_t a, float32x4_t b)
++{
++  return (float32x4_t)__builtin_neon_vmaxnmv4sf (a, b);
++}
++
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vminnm_f32 (float32x2_t a, float32x2_t b)
++{
++  return (float32x2_t)__builtin_neon_vminnmv2sf (a, b);
++}
++
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmq_f32 (float32x4_t a, float32x4_t b)
++{
++  return (float32x4_t)__builtin_neon_vminnmv4sf (a, b);
++}
++#pragma GCC pop_options
++
++
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vmaxuv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vmaxuv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmaxq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vmaxuv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vminsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vminsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vminsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vminfv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vminuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vminuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmin_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vminuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vminsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vminsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vminsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vminfv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vminuv16qi ((int8x16_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vminuv8hi ((int16x8_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vminq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vminuv4si ((int32x4_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vpaddv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vpaddv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vpaddv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vpaddv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vpaddv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vpaddv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadd_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vpaddv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddl_s8 (int8x8_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vpaddlsv8qi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddl_s16 (int16x4_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vpaddlsv4hi (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddl_s32 (int32x2_t __a)
+ {
+   return (int64x1_t)__builtin_neon_vpaddlsv2si (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddl_u8 (uint8x8_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vpaddluv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddl_u16 (uint16x4_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vpaddluv4hi ((int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddl_u32 (uint32x2_t __a)
+ {
+   return (uint64x1_t)__builtin_neon_vpaddluv2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddlq_s8 (int8x16_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vpaddlsv16qi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddlq_s16 (int16x8_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vpaddlsv8hi (__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddlq_s32 (int32x4_t __a)
+ {
+   return (int64x2_t)__builtin_neon_vpaddlsv4si (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddlq_u8 (uint8x16_t __a)
+ {
+   return (uint16x8_t)__builtin_neon_vpaddluv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddlq_u16 (uint16x8_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vpaddluv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpaddlq_u32 (uint32x4_t __a)
+ {
+   return (uint64x2_t)__builtin_neon_vpaddluv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadal_s8 (int16x4_t __a, int8x8_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vpadalsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadal_s16 (int32x2_t __a, int16x4_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vpadalsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadal_s32 (int64x1_t __a, int32x2_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vpadalsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadal_u8 (uint16x4_t __a, uint8x8_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vpadaluv8qi ((int16x4_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadal_u16 (uint32x2_t __a, uint16x4_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vpadaluv4hi ((int32x2_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadal_u32 (uint64x1_t __a, uint32x2_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vpadaluv2si ((int64x1_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadalq_s8 (int16x8_t __a, int8x16_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vpadalsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadalq_s16 (int32x4_t __a, int16x8_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vpadalsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadalq_s32 (int64x2_t __a, int32x4_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vpadalsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadalq_u8 (uint16x8_t __a, uint8x16_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vpadaluv16qi ((int16x8_t) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadalq_u16 (uint32x4_t __a, uint16x8_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vpadaluv8hi ((int32x4_t) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpadalq_u32 (uint64x2_t __a, uint32x4_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vpadaluv4si ((int64x2_t) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vpmaxsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vpmaxsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vpmaxsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vpmaxfv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vpmaxuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vpmaxuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmax_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vpmaxuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vpminsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vpminsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vpminsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vpminfv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vpminuv8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vpminuv4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vpmin_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vpminuv2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrecps_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vrecpsv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrecpsq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vrecpsv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsqrts_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vrsqrtsv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsqrtsq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vrsqrtsv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vshlsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vshlsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vshlsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vshlsdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vshluv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vshluv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vshluv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vshludi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vshlsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vshlsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vshlsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vshlsv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vshluv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vshluv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vshluv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vshluv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vrshlsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vrshlsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vrshlsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vrshlsdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vrshluv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vrshluv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vrshluv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vrshludi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vrshlsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vrshlsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vrshlsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vrshlsv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vrshluv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vrshluv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vrshluv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vrshluv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vqshlsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqshlsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqshlsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vqshlsdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqshluv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqshluv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqshluv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vqshludi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vqshlsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqshlsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqshlsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vqshlsv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vqshluv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vqshluv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vqshluv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vqshluv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vqrshlsv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqrshlsv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqrshlsv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x1_t)__builtin_neon_vqrshlsdi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_u8 (uint8x8_t __a, int8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqrshluv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_u16 (uint16x4_t __a, int16x4_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqrshluv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_u32 (uint32x2_t __a, int32x2_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqrshluv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshl_u64 (uint64x1_t __a, int64x1_t __b)
+ {
+   return (uint64x1_t)__builtin_neon_vqrshludi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vqrshlsv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqrshlsv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqrshlsv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vqrshlsv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_u8 (uint8x16_t __a, int8x16_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vqrshluv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_u16 (uint16x8_t __a, int16x8_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vqrshluv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_u32 (uint32x4_t __a, int32x4_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vqrshluv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshlq_u64 (uint64x2_t __a, int64x2_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vqrshluv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vshrs_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vshrs_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vshrs_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64x1_t)__builtin_neon_vshrs_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vshru_nv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vshru_nv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vshru_nv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshr_n_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64x1_t)__builtin_neon_vshru_ndi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_s8 (int8x16_t __a, const int __b)
+ {
+   return (int8x16_t)__builtin_neon_vshrs_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int16x8_t)__builtin_neon_vshrs_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vshrs_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int64x2_t)__builtin_neon_vshrs_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_u8 (uint8x16_t __a, const int __b)
+ {
+   return (uint8x16_t)__builtin_neon_vshru_nv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vshru_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vshru_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrq_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vshru_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vrshrs_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vrshrs_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vrshrs_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64x1_t)__builtin_neon_vrshrs_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vrshru_nv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vrshru_nv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vrshru_nv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshr_n_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64x1_t)__builtin_neon_vrshru_ndi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_s8 (int8x16_t __a, const int __b)
+ {
+   return (int8x16_t)__builtin_neon_vrshrs_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int16x8_t)__builtin_neon_vrshrs_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vrshrs_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int64x2_t)__builtin_neon_vrshrs_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_u8 (uint8x16_t __a, const int __b)
+ {
+   return (uint8x16_t)__builtin_neon_vrshru_nv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vrshru_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vrshru_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrq_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vrshru_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrn_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vshrn_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrn_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vshrn_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrn_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vshrn_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrn_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vshrn_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrn_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vshrn_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshrn_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vshrn_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrn_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vrshrn_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrn_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vrshrn_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrn_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vrshrn_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrn_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vrshrn_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrn_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vrshrn_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrshrn_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vrshrn_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrn_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vqshrns_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrn_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vqshrns_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrn_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vqshrns_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrn_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqshrnu_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrn_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqshrnu_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrn_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqshrnu_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrn_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vqrshrns_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrn_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vqrshrns_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrn_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vqrshrns_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrn_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqrshrnu_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrn_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqrshrnu_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrn_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqrshrnu_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrun_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqshrun_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrun_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqshrun_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshrun_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqshrun_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrun_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqrshrun_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrun_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqrshrun_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrshrun_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqrshrun_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vshl_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vshl_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vshl_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64x1_t)__builtin_neon_vshl_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vshl_nv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vshl_nv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vshl_nv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshl_n_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64x1_t)__builtin_neon_vshl_ndi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_s8 (int8x16_t __a, const int __b)
+ {
+   return (int8x16_t)__builtin_neon_vshl_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int16x8_t)__builtin_neon_vshl_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vshl_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int64x2_t)__builtin_neon_vshl_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_u8 (uint8x16_t __a, const int __b)
+ {
+   return (uint8x16_t)__builtin_neon_vshl_nv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vshl_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vshl_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshlq_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vshl_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vqshl_s_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vqshl_s_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vqshl_s_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64x1_t)__builtin_neon_vqshl_s_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqshl_u_nv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqshl_u_nv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqshl_u_nv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshl_n_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64x1_t)__builtin_neon_vqshl_u_ndi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_s8 (int8x16_t __a, const int __b)
+ {
+   return (int8x16_t)__builtin_neon_vqshl_s_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (int16x8_t)__builtin_neon_vqshl_s_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vqshl_s_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (int64x2_t)__builtin_neon_vqshl_s_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_u8 (uint8x16_t __a, const int __b)
+ {
+   return (uint8x16_t)__builtin_neon_vqshl_u_nv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vqshl_u_nv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vqshl_u_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlq_n_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vqshl_u_nv2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlu_n_s8 (int8x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vqshlu_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlu_n_s16 (int16x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vqshlu_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlu_n_s32 (int32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vqshlu_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshlu_n_s64 (int64x1_t __a, const int __b)
+ {
+   return (uint64x1_t)__builtin_neon_vqshlu_ndi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshluq_n_s8 (int8x16_t __a, const int __b)
+ {
+   return (uint8x16_t)__builtin_neon_vqshlu_nv16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshluq_n_s16 (int16x8_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vqshlu_nv8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshluq_n_s32 (int32x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vqshlu_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqshluq_n_s64 (int64x2_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vqshlu_nv2di (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshll_n_s8 (int8x8_t __a, const int __b)
+ {
+   return (int16x8_t)__builtin_neon_vshlls_nv8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshll_n_s16 (int16x4_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vshlls_nv4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshll_n_s32 (int32x2_t __a, const int __b)
+ {
+   return (int64x2_t)__builtin_neon_vshlls_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshll_n_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vshllu_nv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshll_n_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vshllu_nv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vshll_n_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vshllu_nv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vsras_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vsras_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vsras_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vsras_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vsrau_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vsrau_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vsrau_nv2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vsrau_ndi ((int64x1_t) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vsras_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vsras_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vsras_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vsras_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vsrau_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vsrau_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vsrau_nv4si ((int32x4_t) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vsrau_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vrsras_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vrsras_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vrsras_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vrsras_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vrsrau_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vrsrau_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vrsrau_nv2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsra_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vrsrau_ndi ((int64x1_t) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vrsras_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vrsras_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vrsras_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vrsras_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vrsrau_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vrsrau_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vrsrau_nv4si ((int32x4_t) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vrsrau_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+@@ -4565,68 +5278,79 @@ vrsraq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_p64 (poly64x1_t __a, poly64x1_t __b, const int __c)
+ {
+   return (poly64x1_t)__builtin_neon_vsri_ndi (__a, __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vsri_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vsri_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vsri_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vsri_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vsri_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vsri_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vsri_nv2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vsri_ndi ((int64x1_t) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_p8 (poly8x8_t __a, poly8x8_t __b, const int __c)
+ {
+   return (poly8x8_t)__builtin_neon_vsri_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsri_n_p16 (poly16x4_t __a, poly16x4_t __b, const int __c)
+ {
+   return (poly16x4_t)__builtin_neon_vsri_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+@@ -4634,68 +5358,79 @@ vsri_n_p16 (poly16x4_t __a, poly16x4_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_p64 (poly64x2_t __a, poly64x2_t __b, const int __c)
+ {
+   return (poly64x2_t)__builtin_neon_vsri_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vsri_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vsri_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vsri_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vsri_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vsri_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vsri_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vsri_nv4si ((int32x4_t) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vsri_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_p8 (poly8x16_t __a, poly8x16_t __b, const int __c)
+ {
+   return (poly8x16_t)__builtin_neon_vsri_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsriq_n_p16 (poly16x8_t __a, poly16x8_t __b, const int __c)
+ {
+   return (poly16x8_t)__builtin_neon_vsri_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+@@ -4703,68 +5438,79 @@ vsriq_n_p16 (poly16x8_t __a, poly16x8_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_p64 (poly64x1_t __a, poly64x1_t __b, const int __c)
+ {
+   return (poly64x1_t)__builtin_neon_vsli_ndi (__a, __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vsli_nv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vsli_nv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vsli_nv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vsli_ndi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vsli_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vsli_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vsli_nv2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vsli_ndi ((int64x1_t) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_p8 (poly8x8_t __a, poly8x8_t __b, const int __c)
+ {
+   return (poly8x8_t)__builtin_neon_vsli_nv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsli_n_p16 (poly16x4_t __a, poly16x4_t __b, const int __c)
+ {
+   return (poly16x4_t)__builtin_neon_vsli_nv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+@@ -4772,530 +5518,618 @@ vsli_n_p16 (poly16x4_t __a, poly16x4_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_p64 (poly64x2_t __a, poly64x2_t __b, const int __c)
+ {
+   return (poly64x2_t)__builtin_neon_vsli_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vsli_nv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vsli_nv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vsli_nv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vsli_nv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vsli_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vsli_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vsli_nv4si ((int32x4_t) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vsli_nv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_p8 (poly8x16_t __a, poly8x16_t __b, const int __c)
+ {
+   return (poly8x16_t)__builtin_neon_vsli_nv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsliq_n_p16 (poly16x8_t __a, poly16x8_t __b, const int __c)
+ {
+   return (poly16x8_t)__builtin_neon_vsli_nv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabs_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vabsv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabs_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vabsv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabs_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vabsv2si (__a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabs_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vabsv2sf (__a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabsq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vabsv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabsq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vabsv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabsq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vabsv4si (__a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vabsq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vabsv4sf (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vqabsv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vqabsv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabs_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vqabsv2si (__a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabsq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vqabsv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabsq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vqabsv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqabsq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vqabsv4si (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vneg_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vnegv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vneg_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vnegv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vneg_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vnegv2si (__a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vneg_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vnegv2sf (__a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vnegq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vnegv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vnegq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vnegv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vnegq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vnegv4si (__a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vnegq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vnegv4sf (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vqnegv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vqnegv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqneg_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vqnegv2si (__a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqnegq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vqnegv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqnegq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vqnegv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqnegq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vqnegv4si (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vmvnv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vmvnv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vmvnv2si (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_u8 (uint8x8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vmvnv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_u16 (uint16x4_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vmvnv4hi ((int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_u32 (uint32x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vmvnv2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvn_p8 (poly8x8_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vmvnv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vmvnv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vmvnv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vmvnv4si (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_u8 (uint8x16_t __a)
+ {
+   return (uint8x16_t)__builtin_neon_vmvnv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_u16 (uint16x8_t __a)
+ {
+   return (uint16x8_t)__builtin_neon_vmvnv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_u32 (uint32x4_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vmvnv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmvnq_p8 (poly8x16_t __a)
+ {
+   return (poly8x16_t)__builtin_neon_vmvnv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcls_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vclsv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcls_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vclsv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcls_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vclsv2si (__a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclsq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vclsv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclsq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vclsv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclsq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vclsv4si (__a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclz_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vclzv8qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclz_s16 (int16x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vclzv4hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclz_s32 (int32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vclzv2si (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclz_u8 (uint8x8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vclzv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclz_u16 (uint16x4_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vclzv4hi ((int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclz_u32 (uint32x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vclzv2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclzq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vclzv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclzq_s16 (int16x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vclzv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclzq_s32 (int32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vclzv4si (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclzq_u8 (uint8x16_t __a)
+ {
+   return (uint8x16_t)__builtin_neon_vclzv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclzq_u16 (uint16x8_t __a)
+ {
+   return (uint16x8_t)__builtin_neon_vclzv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vclzq_u32 (uint32x4_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vclzv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcnt_s8 (int8x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vcntv8qi (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcnt_u8 (uint8x8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vcntv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcnt_p8 (poly8x8_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vcntv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcntq_s8 (int8x16_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vcntv16qi (__a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcntq_u8 (uint8x16_t __a)
+ {
+   return (uint8x16_t)__builtin_neon_vcntv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcntq_p8 (poly8x16_t __a)
+ {
+   return (poly8x16_t)__builtin_neon_vcntv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrecpe_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrecpev2sf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrecpe_u32 (uint32x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vrecpev2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrecpeq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrecpev4sf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrecpeq_u32 (uint32x4_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vrecpev4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsqrte_f32 (float32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vrsqrtev2sf (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsqrte_u32 (uint32x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vrsqrtev2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsqrteq_f32 (float32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vrsqrtev4sf (__a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrsqrteq_u32 (uint32x4_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vrsqrtev4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8_t)__builtin_neon_vget_lanev8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16_t)__builtin_neon_vget_lanev4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32_t)__builtin_neon_vget_lanev2si (__a, __b);
+@@ -5328,67 +6162,88 @@ vget_lane_s32 (int32x2_t __a, const int __b)
+   })
+ #endif
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_f32 (float32x2_t __a, const int __b)
+ {
+   return (float32_t)__builtin_neon_vget_lanev2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8_t)__builtin_neon_vget_laneuv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16_t)__builtin_neon_vget_laneuv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32_t)__builtin_neon_vget_laneuv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_p8 (poly8x8_t __a, const int __b)
+ {
+   return (poly8_t)__builtin_neon_vget_laneuv8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_p16 (poly16x4_t __a, const int __b)
+ {
+   return (poly16_t)__builtin_neon_vget_laneuv4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64_t)__builtin_neon_vget_lanedi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++#pragma GCC push_options
++#pragma GCC target ("fpu=crypto-neon-fp-armv8")
++__extension__ extern __inline poly64_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vget_lane_p64 (poly64x1_t __a, const int __b)
++{
++  return (poly64_t)__builtin_neon_vget_lanedi ((int64x1_t) __a, __b);
++}
++
++#pragma GCC pop_options
++__extension__ extern __inline uint64_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_lane_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64_t)__builtin_neon_vget_lanedi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s8 (int8x16_t __a, const int __b)
+ {
+   return (int8_t)__builtin_neon_vget_lanev16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s16 (int16x8_t __a, const int __b)
+ {
+   return (int16_t)__builtin_neon_vget_lanev8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s32 (int32x4_t __a, const int __b)
+ {
+   return (int32_t)__builtin_neon_vget_lanev4si (__a, __b);
+@@ -5405,67 +6260,88 @@ vgetq_lane_s32 (int32x4_t __a, const int __b)
+   })
+ #endif
+ 
+-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_f32 (float32x4_t __a, const int __b)
+ {
+   return (float32_t)__builtin_neon_vget_lanev4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u8 (uint8x16_t __a, const int __b)
+ {
+   return (uint8_t)__builtin_neon_vget_laneuv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u16 (uint16x8_t __a, const int __b)
+ {
+   return (uint16_t)__builtin_neon_vget_laneuv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u32 (uint32x4_t __a, const int __b)
+ {
+   return (uint32_t)__builtin_neon_vget_laneuv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_p8 (poly8x16_t __a, const int __b)
+ {
+   return (poly8_t)__builtin_neon_vget_laneuv16qi ((int8x16_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_p16 (poly16x8_t __a, const int __b)
+ {
+   return (poly16_t)__builtin_neon_vget_laneuv8hi ((int16x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int64_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_s64 (int64x2_t __a, const int __b)
+ {
+   return (int64_t)__builtin_neon_vget_lanev2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
++#pragma GCC push_options
++#pragma GCC target ("fpu=crypto-neon-fp-armv8")
++__extension__ extern __inline poly64_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vgetq_lane_p64 (poly64x2_t __a, const int __b)
++{
++  return (poly64_t)__builtin_neon_vget_lanev2di ((int64x2_t) __a, __b);
++}
++
++#pragma GCC pop_options
++__extension__ extern __inline uint64_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vgetq_lane_u64 (uint64x2_t __a, const int __b)
+ {
+   return (uint64_t)__builtin_neon_vget_lanev2di ((int64x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s8 (int8_t __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vset_lanev8qi ((__builtin_neon_qi) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vset_lanev4hi ((__builtin_neon_hi) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vset_lanev2si ((__builtin_neon_si) __a, __b, __c);
+@@ -5483,67 +6359,88 @@ vset_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
+   })
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_f32 (float32_t __a, float32x2_t __b, const int __c)
+ {
+   return (float32x2_t)__builtin_neon_vset_lanev2sf ((__builtin_neon_sf) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u8 (uint8_t __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vset_lanev8qi ((__builtin_neon_qi) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u16 (uint16_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vset_lanev4hi ((__builtin_neon_hi) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u32 (uint32_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vset_lanev2si ((__builtin_neon_si) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_p8 (poly8_t __a, poly8x8_t __b, const int __c)
+ {
+   return (poly8x8_t)__builtin_neon_vset_lanev8qi ((__builtin_neon_qi) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_p16 (poly16_t __a, poly16x4_t __b, const int __c)
+ {
+   return (poly16x4_t)__builtin_neon_vset_lanev4hi ((__builtin_neon_hi) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_s64 (int64_t __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vset_lanedi ((__builtin_neon_di) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vset_lane_u64 (uint64_t __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vset_lanedi ((__builtin_neon_di) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++#pragma GCC push_options
++#pragma GCC target ("fpu=crypto-neon-fp-armv8")
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vset_lane_p64 (poly64_t __a, poly64x1_t __b, const int __c)
++{
++  return (poly64x1_t)__builtin_neon_vset_lanedi ((__builtin_neon_di) __a, (int64x1_t) __b, __c);
++}
++
++#pragma GCC pop_options
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s8 (int8_t __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vset_lanev16qi ((__builtin_neon_qi) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s16 (int16_t __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vset_lanev8hi ((__builtin_neon_hi) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s32 (int32_t __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vset_lanev4si ((__builtin_neon_si) __a, __b, __c);
+@@ -5561,49 +6458,57 @@ vsetq_lane_s32 (int32_t __a, int32x4_t __b, const int __c)
+   })
+ #endif
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_f32 (float32_t __a, float32x4_t __b, const int __c)
+ {
+   return (float32x4_t)__builtin_neon_vset_lanev4sf ((__builtin_neon_sf) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u8 (uint8_t __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vset_lanev16qi ((__builtin_neon_qi) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u16 (uint16_t __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vset_lanev8hi ((__builtin_neon_hi) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u32 (uint32_t __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vset_lanev4si ((__builtin_neon_si) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_p8 (poly8_t __a, poly8x16_t __b, const int __c)
+ {
+   return (poly8x16_t)__builtin_neon_vset_lanev16qi ((__builtin_neon_qi) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_p16 (poly16_t __a, poly16x8_t __b, const int __c)
+ {
+   return (poly16x8_t)__builtin_neon_vset_lanev8hi ((__builtin_neon_hi) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_s64 (int64_t __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vset_lanev2di ((__builtin_neon_di) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsetq_lane_u64 (uint64_t __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vset_lanev2di ((__builtin_neon_di) __a, (int64x2_t) __b, __c);
+@@ -5611,136 +6516,165 @@ vsetq_lane_u64 (uint64_t __a, uint64x2_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vsetq_lane_p64 (poly64_t __a, poly64x2_t __b, const int __c)
++{
++  return (poly64x2_t)__builtin_neon_vset_lanev2di ((__builtin_neon_di) __a, (int64x2_t) __b, __c);
++}
++
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_p64 (uint64_t __a)
+ {
+   return (poly64x1_t)__builtin_neon_vcreatedi ((__builtin_neon_di) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s8 (uint64_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vcreatev8qi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s16 (uint64_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vcreatev4hi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s32 (uint64_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vcreatev2si ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_s64 (uint64_t __a)
+ {
+   return (int64x1_t)__builtin_neon_vcreatedi ((__builtin_neon_di) __a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_f16 (uint64_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_f32 (uint64_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vcreatev2sf ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u8 (uint64_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vcreatev8qi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u16 (uint64_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vcreatev4hi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u32 (uint64_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vcreatev2si ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_u64 (uint64_t __a)
+ {
+   return (uint64x1_t)__builtin_neon_vcreatedi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_p8 (uint64_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vcreatev8qi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcreate_p16 (uint64_t __a)
+ {
+   return (poly16x4_t)__builtin_neon_vcreatev4hi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_s8 (int8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_s16 (int16_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_s32 (int32_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vdup_nv2si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_f32 (float32_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vdup_nv2sf ((__builtin_neon_sf) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_u8 (uint8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_u16 (uint16_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_u32 (uint32_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vdup_nv2si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_p8 (poly8_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_p16 (poly16_t __a)
+ {
+   return (poly16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a);
+@@ -5748,20 +6682,23 @@ vdup_n_p16 (poly16_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_p64 (poly64_t __a)
+ {
+   return (poly64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_s64 (int64_t __a)
+ {
+   return (int64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_n_u64 (uint64_t __a)
+ {
+   return (uint64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a);
+@@ -5769,260 +6706,303 @@ vdup_n_u64 (uint64_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_p64 (poly64_t __a)
+ {
+   return (poly64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_s8 (int8_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_s16 (int16_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_s32 (int32_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vdup_nv4si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_f32 (float32_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vdup_nv4sf ((__builtin_neon_sf) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_u8 (uint8_t __a)
+ {
+   return (uint8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_u16 (uint16_t __a)
+ {
+   return (uint16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_u32 (uint32_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vdup_nv4si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_p8 (poly8_t __a)
+ {
+   return (poly8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_p16 (poly16_t __a)
+ {
+   return (poly16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_s64 (int64_t __a)
+ {
+   return (int64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_n_u64 (uint64_t __a)
+ {
+   return (uint64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_s8 (int8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_s16 (int16_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_s32 (int32_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vdup_nv2si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_f32 (float32_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vdup_nv2sf ((__builtin_neon_sf) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_u8 (uint8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_u16 (uint16_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_u32 (uint32_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vdup_nv2si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_p8 (poly8_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vdup_nv8qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_p16 (poly16_t __a)
+ {
+   return (poly16x4_t)__builtin_neon_vdup_nv4hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_s64 (int64_t __a)
+ {
+   return (int64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmov_n_u64 (uint64_t __a)
+ {
+   return (uint64x1_t)__builtin_neon_vdup_ndi ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_s8 (int8_t __a)
+ {
+   return (int8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_s16 (int16_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_s32 (int32_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vdup_nv4si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_f32 (float32_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vdup_nv4sf ((__builtin_neon_sf) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_u8 (uint8_t __a)
+ {
+   return (uint8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_u16 (uint16_t __a)
+ {
+   return (uint16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_u32 (uint32_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vdup_nv4si ((__builtin_neon_si) __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_p8 (poly8_t __a)
+ {
+   return (poly8x16_t)__builtin_neon_vdup_nv16qi ((__builtin_neon_qi) __a);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_p16 (poly16_t __a)
+ {
+   return (poly16x8_t)__builtin_neon_vdup_nv8hi ((__builtin_neon_hi) __a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_s64 (int64_t __a)
+ {
+   return (int64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovq_n_u64 (uint64_t __a)
+ {
+   return (uint64x2_t)__builtin_neon_vdup_nv2di ((__builtin_neon_di) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8x8_t)__builtin_neon_vdup_lanev8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16x4_t)__builtin_neon_vdup_lanev4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vdup_lanev2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_f32 (float32x2_t __a, const int __b)
+ {
+   return (float32x2_t)__builtin_neon_vdup_lanev2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8x8_t)__builtin_neon_vdup_lanev8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16x4_t)__builtin_neon_vdup_lanev4hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vdup_lanev2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_p8 (poly8x8_t __a, const int __b)
+ {
+   return (poly8x8_t)__builtin_neon_vdup_lanev8qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_p16 (poly16x4_t __a, const int __b)
+ {
+   return (poly16x4_t)__builtin_neon_vdup_lanev4hi ((int16x4_t) __a, __b);
+@@ -6030,74 +7010,86 @@ vdup_lane_p16 (poly16x4_t __a, const int __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_p64 (poly64x1_t __a, const int __b)
+ {
+   return (poly64x1_t)__builtin_neon_vdup_lanedi (__a, __b);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64x1_t)__builtin_neon_vdup_lanedi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdup_lane_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64x1_t)__builtin_neon_vdup_lanedi ((int64x1_t) __a, __b);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_s8 (int8x8_t __a, const int __b)
+ {
+   return (int8x16_t)__builtin_neon_vdup_lanev16qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_s16 (int16x4_t __a, const int __b)
+ {
+   return (int16x8_t)__builtin_neon_vdup_lanev8hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_s32 (int32x2_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vdup_lanev4si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_f32 (float32x2_t __a, const int __b)
+ {
+   return (float32x4_t)__builtin_neon_vdup_lanev4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_u8 (uint8x8_t __a, const int __b)
+ {
+   return (uint8x16_t)__builtin_neon_vdup_lanev16qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_u16 (uint16x4_t __a, const int __b)
+ {
+   return (uint16x8_t)__builtin_neon_vdup_lanev8hi ((int16x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_u32 (uint32x2_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vdup_lanev4si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_p8 (poly8x8_t __a, const int __b)
+ {
+   return (poly8x16_t)__builtin_neon_vdup_lanev16qi ((int8x8_t) __a, __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_p16 (poly16x4_t __a, const int __b)
+ {
+   return (poly16x8_t)__builtin_neon_vdup_lanev8hi ((int16x4_t) __a, __b);
+@@ -6105,20 +7097,23 @@ vdupq_lane_p16 (poly16x4_t __a, const int __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_p64 (poly64x1_t __a, const int __b)
+ {
+   return (poly64x2_t)__builtin_neon_vdup_lanev2di (__a, __b);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_s64 (int64x1_t __a, const int __b)
+ {
+   return (int64x2_t)__builtin_neon_vdup_lanev2di (__a, __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vdupq_lane_u64 (uint64x1_t __a, const int __b)
+ {
+   return (uint64x2_t)__builtin_neon_vdup_lanev2di ((int64x1_t) __a, __b);
+@@ -6126,82 +7121,95 @@ vdupq_lane_u64 (uint64x1_t __a, const int __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_p64 (poly64x1_t __a, poly64x1_t __b)
+ {
+   return (poly64x2_t)__builtin_neon_vcombinedi (__a, __b);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x16_t)__builtin_neon_vcombinev8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vcombinev4hi (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vcombinev2si (__a, __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vcombinedi (__a, __b);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_f16 (float16x4_t __a, float16x4_t __b)
+ {
+   return __builtin_neon_vcombinev4hf (__a, __b);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vcombinev2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x16_t)__builtin_neon_vcombinev8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vcombinev4hi ((int16x4_t) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcombinev2si ((int32x2_t) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vcombinedi ((int64x1_t) __a, (int64x1_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   return (poly8x16_t)__builtin_neon_vcombinev8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcombine_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+   return (poly16x8_t)__builtin_neon_vcombinev4hi ((int16x4_t) __a, (int16x4_t) __b);
+@@ -6209,144 +7217,167 @@ vcombine_p16 (poly16x4_t __a, poly16x4_t __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_p64 (poly64x2_t __a)
+ {
+   return (poly64x1_t)__builtin_neon_vget_highv2di ((int64x2_t) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s8 (int8x16_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vget_highv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s16 (int16x8_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vget_highv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s32 (int32x4_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vget_highv4si (__a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_s64 (int64x2_t __a)
+ {
+   return (int64x1_t)__builtin_neon_vget_highv2di (__a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_f16 (float16x8_t __a)
+ {
+   return __builtin_neon_vget_highv8hf (__a);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_f32 (float32x4_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vget_highv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u8 (uint8x16_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vget_highv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u16 (uint16x8_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vget_highv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u32 (uint32x4_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vget_highv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_u64 (uint64x2_t __a)
+ {
+   return (uint64x1_t)__builtin_neon_vget_highv2di ((int64x2_t) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_p8 (poly8x16_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vget_highv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_high_p16 (poly16x8_t __a)
+ {
+   return (poly16x4_t)__builtin_neon_vget_highv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s8 (int8x16_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vget_lowv16qi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s16 (int16x8_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vget_lowv8hi (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s32 (int32x4_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vget_lowv4si (__a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_f16 (float16x8_t __a)
+ {
+   return __builtin_neon_vget_lowv8hf (__a);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_f32 (float32x4_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vget_lowv4sf (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u8 (uint8x16_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vget_lowv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u16 (uint16x8_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vget_lowv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u32 (uint32x4_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vget_lowv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_p8 (poly8x16_t __a)
+ {
+   return (poly8x8_t)__builtin_neon_vget_lowv16qi ((int8x16_t) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_p16 (poly16x8_t __a)
+ {
+   return (poly16x4_t)__builtin_neon_vget_lowv8hi ((int16x8_t) __a);
+@@ -6354,68 +7385,79 @@ vget_low_p16 (poly16x8_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_p64 (poly64x2_t __a)
+ {
+   return (poly64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_s64 (int64x2_t __a)
+ {
+   return (int64x1_t)__builtin_neon_vget_lowv2di (__a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vget_low_u64 (uint64x2_t __a)
+ {
+   return (uint64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_s32_f32 (float32x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vcvtsv2sf (__a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_f32_s32 (int32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vcvtsv2si (__a);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_f32_u32 (uint32x2_t __a)
+ {
+   return (float32x2_t)__builtin_neon_vcvtuv2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_u32_f32 (float32x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vcvtuv2sf (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_s32_f32 (float32x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vcvtsv4sf (__a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_f32_s32 (int32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vcvtsv4si (__a);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_f32_u32 (uint32x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vcvtuv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_u32_f32 (float32x4_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vcvtuv4sf (__a);
+@@ -6424,7 +7466,8 @@ vcvtq_u32_f32 (float32x4_t __a)
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=neon-fp16")
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_f16_f32 (float32x4_t __a)
+ {
+   return (float16x4_t)__builtin_neon_vcvtv4hfv4sf (__a);
+@@ -6432,7 +7475,8 @@ vcvt_f16_f32 (float32x4_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_f32_f16 (float16x4_t __a)
+ {
+   return (float32x4_t)__builtin_neon_vcvtv4sfv4hf (__a);
+@@ -6440,1059 +7484,1232 @@ vcvt_f32_f16 (float16x4_t __a)
+ #endif
+ #pragma GCC pop_options
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_n_s32_f32 (float32x2_t __a, const int __b)
+ {
+   return (int32x2_t)__builtin_neon_vcvts_nv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_n_f32_s32 (int32x2_t __a, const int __b)
+ {
+   return (float32x2_t)__builtin_neon_vcvts_nv2si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_n_f32_u32 (uint32x2_t __a, const int __b)
+ {
+   return (float32x2_t)__builtin_neon_vcvtu_nv2si ((int32x2_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvt_n_u32_f32 (float32x2_t __a, const int __b)
+ {
+   return (uint32x2_t)__builtin_neon_vcvtu_nv2sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_n_s32_f32 (float32x4_t __a, const int __b)
+ {
+   return (int32x4_t)__builtin_neon_vcvts_nv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_n_f32_s32 (int32x4_t __a, const int __b)
+ {
+   return (float32x4_t)__builtin_neon_vcvts_nv4si (__a, __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_n_f32_u32 (uint32x4_t __a, const int __b)
+ {
+   return (float32x4_t)__builtin_neon_vcvtu_nv4si ((int32x4_t) __a, __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vcvtq_n_u32_f32 (float32x4_t __a, const int __b)
+ {
+   return (uint32x4_t)__builtin_neon_vcvtu_nv4sf (__a, __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovn_s16 (int16x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vmovnv8hi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovn_s32 (int32x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vmovnv4si (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovn_s64 (int64x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vmovnv2di (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovn_u16 (uint16x8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vmovnv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovn_u32 (uint32x4_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vmovnv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovn_u64 (uint64x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vmovnv2di ((int64x2_t) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovn_s16 (int16x8_t __a)
+ {
+   return (int8x8_t)__builtin_neon_vqmovnsv8hi (__a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovn_s32 (int32x4_t __a)
+ {
+   return (int16x4_t)__builtin_neon_vqmovnsv4si (__a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovn_s64 (int64x2_t __a)
+ {
+   return (int32x2_t)__builtin_neon_vqmovnsv2di (__a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovn_u16 (uint16x8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vqmovnuv8hi ((int16x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovn_u32 (uint32x4_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vqmovnuv4si ((int32x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovn_u64 (uint64x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vqmovnuv2di ((int64x2_t) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovun_s16 (int16x8_t __a)
+ {
+   return (uint8x8_t)__builtin_neon_vqmovunv8hi (__a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovun_s32 (int32x4_t __a)
+ {
+   return (uint16x4_t)__builtin_neon_vqmovunv4si (__a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqmovun_s64 (int64x2_t __a)
+ {
+   return (uint32x2_t)__builtin_neon_vqmovunv2di (__a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovl_s8 (int8x8_t __a)
+ {
+   return (int16x8_t)__builtin_neon_vmovlsv8qi (__a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovl_s16 (int16x4_t __a)
+ {
+   return (int32x4_t)__builtin_neon_vmovlsv4hi (__a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovl_s32 (int32x2_t __a)
+ {
+   return (int64x2_t)__builtin_neon_vmovlsv2si (__a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovl_u8 (uint8x8_t __a)
+ {
+   return (uint16x8_t)__builtin_neon_vmovluv8qi ((int8x8_t) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovl_u16 (uint16x4_t __a)
+ {
+   return (uint32x4_t)__builtin_neon_vmovluv4hi ((int16x4_t) __a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmovl_u32 (uint32x2_t __a)
+ {
+   return (uint64x2_t)__builtin_neon_vmovluv2si ((int32x2_t) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl1_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return (int8x8_t)__builtin_neon_vtbl1v8qi (__a, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl1_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return (uint8x8_t)__builtin_neon_vtbl1v8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl1_p8 (poly8x8_t __a, uint8x8_t __b)
+ {
+   return (poly8x8_t)__builtin_neon_vtbl1v8qi ((int8x8_t) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl2_s8 (int8x8x2_t __a, int8x8_t __b)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __au = { __a };
+   return (int8x8_t)__builtin_neon_vtbl2v8qi (__au.__o, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl2_u8 (uint8x8x2_t __a, uint8x8_t __b)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __au = { __a };
+   return (uint8x8_t)__builtin_neon_vtbl2v8qi (__au.__o, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl2_p8 (poly8x8x2_t __a, uint8x8_t __b)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __au = { __a };
+   return (poly8x8_t)__builtin_neon_vtbl2v8qi (__au.__o, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl3_s8 (int8x8x3_t __a, int8x8_t __b)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __au = { __a };
+   return (int8x8_t)__builtin_neon_vtbl3v8qi (__au.__o, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl3_u8 (uint8x8x3_t __a, uint8x8_t __b)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __au = { __a };
+   return (uint8x8_t)__builtin_neon_vtbl3v8qi (__au.__o, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl3_p8 (poly8x8x3_t __a, uint8x8_t __b)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __au = { __a };
+   return (poly8x8_t)__builtin_neon_vtbl3v8qi (__au.__o, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl4_s8 (int8x8x4_t __a, int8x8_t __b)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __au = { __a };
+   return (int8x8_t)__builtin_neon_vtbl4v8qi (__au.__o, __b);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl4_u8 (uint8x8x4_t __a, uint8x8_t __b)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __au = { __a };
+   return (uint8x8_t)__builtin_neon_vtbl4v8qi (__au.__o, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbl4_p8 (poly8x8x4_t __a, uint8x8_t __b)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __au = { __a };
+   return (poly8x8_t)__builtin_neon_vtbl4v8qi (__au.__o, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx1_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int8x8_t)__builtin_neon_vtbx1v8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx1_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint8x8_t)__builtin_neon_vtbx1v8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx1_p8 (poly8x8_t __a, poly8x8_t __b, uint8x8_t __c)
+ {
+   return (poly8x8_t)__builtin_neon_vtbx1v8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx2_s8 (int8x8_t __a, int8x8x2_t __b, int8x8_t __c)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   return (int8x8_t)__builtin_neon_vtbx2v8qi (__a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx2_u8 (uint8x8_t __a, uint8x8x2_t __b, uint8x8_t __c)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   return (uint8x8_t)__builtin_neon_vtbx2v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx2_p8 (poly8x8_t __a, poly8x8x2_t __b, uint8x8_t __c)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   return (poly8x8_t)__builtin_neon_vtbx2v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx3_s8 (int8x8_t __a, int8x8x3_t __b, int8x8_t __c)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   return (int8x8_t)__builtin_neon_vtbx3v8qi (__a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx3_u8 (uint8x8_t __a, uint8x8x3_t __b, uint8x8_t __c)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   return (uint8x8_t)__builtin_neon_vtbx3v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx3_p8 (poly8x8_t __a, poly8x8x3_t __b, uint8x8_t __c)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   return (poly8x8_t)__builtin_neon_vtbx3v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx4_s8 (int8x8_t __a, int8x8x4_t __b, int8x8_t __c)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   return (int8x8_t)__builtin_neon_vtbx4v8qi (__a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx4_u8 (uint8x8_t __a, uint8x8x4_t __b, uint8x8_t __c)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   return (uint8x8_t)__builtin_neon_vtbx4v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtbx4_p8 (poly8x8_t __a, poly8x8x4_t __b, uint8x8_t __c)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   return (poly8x8_t)__builtin_neon_vtbx4v8qi ((int8x8_t) __a, __bu.__o, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vmul_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vmul_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_lane_f32 (float32x2_t __a, float32x2_t __b, const int __c)
+ {
+   return (float32x2_t)__builtin_neon_vmul_lanev2sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_lane_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vmul_lanev4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_lane_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vmul_lanev2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vmul_lanev8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vmul_lanev4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_lane_f32 (float32x4_t __a, float32x2_t __b, const int __c)
+ {
+   return (float32x4_t)__builtin_neon_vmul_lanev4sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_lane_u16 (uint16x8_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmul_lanev8hi ((int16x8_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_lane_u32 (uint32x4_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmul_lanev4si ((int32x4_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x4_t)__builtin_neon_vmla_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x2_t)__builtin_neon_vmla_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_lane_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c, const int __d)
+ {
+   return (float32x2_t)__builtin_neon_vmla_lanev2sf (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_lane_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c, const int __d)
+ {
+   return (uint16x4_t)__builtin_neon_vmla_lanev4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_lane_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c, const int __d)
+ {
+   return (uint32x2_t)__builtin_neon_vmla_lanev2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, __d);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x8_t)__builtin_neon_vmla_lanev8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vmla_lanev4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_lane_f32 (float32x4_t __a, float32x4_t __b, float32x2_t __c, const int __d)
+ {
+   return (float32x4_t)__builtin_neon_vmla_lanev4sf (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_lane_u16 (uint16x8_t __a, uint16x8_t __b, uint16x4_t __c, const int __d)
+ {
+   return (uint16x8_t)__builtin_neon_vmla_lanev8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x4_t) __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_lane_u32 (uint32x4_t __a, uint32x4_t __b, uint32x2_t __c, const int __d)
+ {
+   return (uint32x4_t)__builtin_neon_vmla_lanev4si ((int32x4_t) __a, (int32x4_t) __b, (int32x2_t) __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vmlals_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int64x2_t)__builtin_neon_vmlals_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_lane_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c, const int __d)
+ {
+   return (uint32x4_t)__builtin_neon_vmlalu_lanev4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, __d);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_lane_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c, const int __d)
+ {
+   return (uint64x2_t)__builtin_neon_vmlalu_lanev2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlal_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vqdmlal_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int64x2_t)__builtin_neon_vqdmlal_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x4_t)__builtin_neon_vmls_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x2_t)__builtin_neon_vmls_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_lane_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c, const int __d)
+ {
+   return (float32x2_t)__builtin_neon_vmls_lanev2sf (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_lane_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c, const int __d)
+ {
+   return (uint16x4_t)__builtin_neon_vmls_lanev4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_lane_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c, const int __d)
+ {
+   return (uint32x2_t)__builtin_neon_vmls_lanev2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, __d);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x8_t)__builtin_neon_vmls_lanev8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vmls_lanev4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_lane_f32 (float32x4_t __a, float32x4_t __b, float32x2_t __c, const int __d)
+ {
+   return (float32x4_t)__builtin_neon_vmls_lanev4sf (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_lane_u16 (uint16x8_t __a, uint16x8_t __b, uint16x4_t __c, const int __d)
+ {
+   return (uint16x8_t)__builtin_neon_vmls_lanev8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x4_t) __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_lane_u32 (uint32x4_t __a, uint32x4_t __b, uint32x2_t __c, const int __d)
+ {
+   return (uint32x4_t)__builtin_neon_vmls_lanev4si ((int32x4_t) __a, (int32x4_t) __b, (int32x2_t) __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vmlsls_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int64x2_t)__builtin_neon_vmlsls_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_lane_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c, const int __d)
+ {
+   return (uint32x4_t)__builtin_neon_vmlslu_lanev4hi ((int32x4_t) __a, (int16x4_t) __b, (int16x4_t) __c, __d);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_lane_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c, const int __d)
+ {
+   return (uint64x2_t)__builtin_neon_vmlslu_lanev2si ((int64x2_t) __a, (int32x2_t) __b, (int32x2_t) __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vqdmlsl_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int64x2_t)__builtin_neon_vqdmlsl_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vmulls_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vmulls_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_lane_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmullu_lanev4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_lane_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vmullu_lanev2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmull_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vqdmull_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmull_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vqdmull_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vqdmulh_lanev8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vqdmulh_lanev4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vqdmulh_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vqdmulh_lanev2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_lane_s16 (int16x8_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmulh_lanev8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_lane_s32 (int32x4_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmulh_lanev4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_lane_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmulh_lanev4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmulh_lanev2si (__a, __b, __c);
+ }
+ 
+ #ifdef __ARM_FEATURE_QRDMX
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlahq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmlah_lanev8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlahq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmlah_lanev4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlah_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmlah_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlah_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmlah_lanev2si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlshq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmlsh_lanev8hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlshq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmlsh_lanev4si (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlsh_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmlsh_lanev4hi (__a, __b, __c, __d);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmlsh_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmlsh_lanev2si (__a, __b, __c, __d);
+ }
+ #endif
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_n_s16 (int16x4_t __a, int16_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vmul_nv4hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_n_s32 (int32x2_t __a, int32_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vmul_nv2si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_n_f32 (float32x2_t __a, float32_t __b)
+ {
+   return (float32x2_t)__builtin_neon_vmul_nv2sf (__a, (__builtin_neon_sf) __b);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_n_u16 (uint16x4_t __a, uint16_t __b)
+ {
+   return (uint16x4_t)__builtin_neon_vmul_nv4hi ((int16x4_t) __a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmul_n_u32 (uint32x2_t __a, uint32_t __b)
+ {
+   return (uint32x2_t)__builtin_neon_vmul_nv2si ((int32x2_t) __a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_n_s16 (int16x8_t __a, int16_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vmul_nv8hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_n_s32 (int32x4_t __a, int32_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vmul_nv4si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_n_f32 (float32x4_t __a, float32_t __b)
+ {
+   return (float32x4_t)__builtin_neon_vmul_nv4sf (__a, (__builtin_neon_sf) __b);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_n_u16 (uint16x8_t __a, uint16_t __b)
+ {
+   return (uint16x8_t)__builtin_neon_vmul_nv8hi ((int16x8_t) __a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmulq_n_u32 (uint32x4_t __a, uint32_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vmul_nv4si ((int32x4_t) __a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_n_s16 (int16x4_t __a, int16_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vmulls_nv4hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_n_s32 (int32x2_t __a, int32_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vmulls_nv2si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_n_u16 (uint16x4_t __a, uint16_t __b)
+ {
+   return (uint32x4_t)__builtin_neon_vmullu_nv4hi ((int16x4_t) __a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_n_u32 (uint32x2_t __a, uint32_t __b)
+ {
+   return (uint64x2_t)__builtin_neon_vmullu_nv2si ((int32x2_t) __a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmull_n_s16 (int16x4_t __a, int16_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqdmull_nv4hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmull_n_s32 (int32x2_t __a, int32_t __b)
+ {
+   return (int64x2_t)__builtin_neon_vqdmull_nv2si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_n_s16 (int16x8_t __a, int16_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqdmulh_nv8hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulhq_n_s32 (int32x4_t __a, int32_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqdmulh_nv4si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_n_s16 (int16x4_t __a, int16_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqdmulh_nv4hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmulh_n_s32 (int32x2_t __a, int32_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqdmulh_nv2si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_n_s16 (int16x8_t __a, int16_t __b)
+ {
+   return (int16x8_t)__builtin_neon_vqrdmulh_nv8hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulhq_n_s32 (int32x4_t __a, int32_t __b)
+ {
+   return (int32x4_t)__builtin_neon_vqrdmulh_nv4si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_n_s16 (int16x4_t __a, int16_t __b)
+ {
+   return (int16x4_t)__builtin_neon_vqrdmulh_nv4hi (__a, (__builtin_neon_hi) __b);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqrdmulh_n_s32 (int32x2_t __a, int32_t __b)
+ {
+   return (int32x2_t)__builtin_neon_vqrdmulh_nv2si (__a, (__builtin_neon_si) __b);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_n_s16 (int16x4_t __a, int16x4_t __b, int16_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vmla_nv4hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_n_s32 (int32x2_t __a, int32x2_t __b, int32_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vmla_nv2si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vmla_nv2sf (__a, __b, (__builtin_neon_sf) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_n_u16 (uint16x4_t __a, uint16x4_t __b, uint16_t __c)
+ {
+   return (uint16x4_t)__builtin_neon_vmla_nv4hi ((int16x4_t) __a, (int16x4_t) __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmla_n_u32 (uint32x2_t __a, uint32x2_t __b, uint32_t __c)
+ {
+   return (uint32x2_t)__builtin_neon_vmla_nv2si ((int32x2_t) __a, (int32x2_t) __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vmla_nv8hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmla_nv4si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vmla_nv4sf (__a, __b, (__builtin_neon_sf) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmla_nv8hi ((int16x8_t) __a, (int16x8_t) __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlaq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmla_nv4si ((int32x4_t) __a, (int32x4_t) __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmlals_nv4hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vmlals_nv2si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_n_u16 (uint32x4_t __a, uint16x4_t __b, uint16_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmlalu_nv4hi ((int32x4_t) __a, (int16x4_t) __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlal_n_u32 (uint64x2_t __a, uint32x2_t __b, uint32_t __c)
+ {
+   return (uint64x2_t)__builtin_neon_vmlalu_nv2si ((int64x2_t) __a, (int32x2_t) __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vqdmlal_nv4hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vqdmlal_nv2si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_n_s16 (int16x4_t __a, int16x4_t __b, int16_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vmls_nv4hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_n_s32 (int32x2_t __a, int32x2_t __b, int32_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vmls_nv2si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vmls_nv2sf (__a, __b, (__builtin_neon_sf) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_n_u16 (uint16x4_t __a, uint16x4_t __b, uint16_t __c)
+ {
+   return (uint16x4_t)__builtin_neon_vmls_nv4hi ((int16x4_t) __a, (int16x4_t) __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmls_n_u32 (uint32x2_t __a, uint32x2_t __b, uint32_t __c)
+ {
+   return (uint32x2_t)__builtin_neon_vmls_nv2si ((int32x2_t) __a, (int32x2_t) __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vmls_nv8hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmls_nv4si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vmls_nv4sf (__a, __b, (__builtin_neon_sf) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vmls_nv8hi ((int16x8_t) __a, (int16x8_t) __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmls_nv4si ((int32x4_t) __a, (int32x4_t) __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vmlsls_nv4hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vmlsls_nv2si (__a, __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_n_u16 (uint32x4_t __a, uint16x4_t __b, uint16_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vmlslu_nv4hi ((int32x4_t) __a, (int16x4_t) __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmlsl_n_u32 (uint64x2_t __a, uint32x2_t __b, uint32_t __c)
+ {
+   return (uint64x2_t)__builtin_neon_vmlslu_nv2si ((int64x2_t) __a, (int32x2_t) __b, (__builtin_neon_si) __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vqdmlsl_nv4hi (__a, __b, (__builtin_neon_hi) __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vqdmlsl_nv2si (__a, __b, (__builtin_neon_si) __c);
+@@ -7500,74 +8717,86 @@ vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_p64 (poly64x1_t __a, poly64x1_t __b, const int __c)
+ {
+   return (poly64x1_t)__builtin_neon_vextdi (__a, __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_s8 (int8x8_t __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vextv8qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_s16 (int16x4_t __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vextv4hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_s32 (int32x2_t __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vextv2si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_s64 (int64x1_t __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vextdi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_f32 (float32x2_t __a, float32x2_t __b, const int __c)
+ {
+   return (float32x2_t)__builtin_neon_vextv2sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_u8 (uint8x8_t __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vextv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_u16 (uint16x4_t __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vextv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_u32 (uint32x2_t __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vextv2si ((int32x2_t) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_u64 (uint64x1_t __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vextdi ((int64x1_t) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_p8 (poly8x8_t __a, poly8x8_t __b, const int __c)
+ {
+   return (poly8x8_t)__builtin_neon_vextv8qi ((int8x8_t) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vext_p16 (poly16x4_t __a, poly16x4_t __b, const int __c)
+ {
+   return (poly16x4_t)__builtin_neon_vextv4hi ((int16x4_t) __a, (int16x4_t) __b, __c);
+@@ -7575,290 +8804,338 @@ vext_p16 (poly16x4_t __a, poly16x4_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_p64 (poly64x2_t __a, poly64x2_t __b, const int __c)
+ {
+   return (poly64x2_t)__builtin_neon_vextv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_s8 (int8x16_t __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vextv16qi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_s16 (int16x8_t __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vextv8hi (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_s32 (int32x4_t __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vextv4si (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_s64 (int64x2_t __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vextv2di (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_f32 (float32x4_t __a, float32x4_t __b, const int __c)
+ {
+   return (float32x4_t)__builtin_neon_vextv4sf (__a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_u8 (uint8x16_t __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vextv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_u16 (uint16x8_t __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vextv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_u32 (uint32x4_t __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vextv4si ((int32x4_t) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_u64 (uint64x2_t __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vextv2di ((int64x2_t) __a, (int64x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_p8 (poly8x16_t __a, poly8x16_t __b, const int __c)
+ {
+   return (poly8x16_t)__builtin_neon_vextv16qi ((int8x16_t) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vextq_p16 (poly16x8_t __a, poly16x8_t __b, const int __c)
+ {
+   return (poly16x8_t)__builtin_neon_vextv8hi ((int16x8_t) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_s8 (int8x8_t __a)
+ {
+   return (int8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_s16 (int16x4_t __a)
+ {
+   return (int16x4_t) __builtin_shuffle (__a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_s32 (int32x2_t __a)
+ {
+   return (int32x2_t) __builtin_shuffle (__a, (uint32x2_t) { 1, 0 });
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_f32 (float32x2_t __a)
+ {
+   return (float32x2_t) __builtin_shuffle (__a, (uint32x2_t) { 1, 0 });
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_u8 (uint8x8_t __a)
+ {
+   return (uint8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_u16 (uint16x4_t __a)
+ {
+   return (uint16x4_t) __builtin_shuffle (__a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_u32 (uint32x2_t __a)
+ {
+   return (uint32x2_t) __builtin_shuffle (__a, (uint32x2_t) { 1, 0 });
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_p8 (poly8x8_t __a)
+ {
+   return (poly8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 7, 6, 5, 4, 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64_p16 (poly16x4_t __a)
+ {
+   return (poly16x4_t) __builtin_shuffle (__a, (uint16x4_t) { 3, 2, 1, 0 });
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_s8 (int8x16_t __a)
+ {
+   return (int8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_s16 (int16x8_t __a)
+ {
+   return (int16x8_t) __builtin_shuffle (__a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_s32 (int32x4_t __a)
+ {
+   return (int32x4_t) __builtin_shuffle (__a, (uint32x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_f32 (float32x4_t __a)
+ {
+   return (float32x4_t) __builtin_shuffle (__a, (uint32x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_u8 (uint8x16_t __a)
+ {
+   return (uint8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_u16 (uint16x8_t __a)
+ {
+   return (uint16x8_t) __builtin_shuffle (__a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_u32 (uint32x4_t __a)
+ {
+   return (uint32x4_t) __builtin_shuffle (__a, (uint32x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_p8 (poly8x16_t __a)
+ {
+   return (poly8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 });
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev64q_p16 (poly16x8_t __a)
+ {
+   return (poly16x8_t) __builtin_shuffle (__a, (uint16x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32_s8 (int8x8_t __a)
+ {
+   return (int8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32_s16 (int16x4_t __a)
+ {
+   return (int16x4_t) __builtin_shuffle (__a, (uint16x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32_u8 (uint8x8_t __a)
+ {
+   return (uint8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32_u16 (uint16x4_t __a)
+ {
+   return (uint16x4_t) __builtin_shuffle (__a, (uint16x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32_p8 (poly8x8_t __a)
+ {
+   return (poly8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 3, 2, 1, 0, 7, 6, 5, 4 });
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32_p16 (poly16x4_t __a)
+ {
+   return (poly16x4_t) __builtin_shuffle (__a, (uint16x4_t) { 1, 0, 3, 2 });
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32q_s8 (int8x16_t __a)
+ {
+   return (int8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32q_s16 (int16x8_t __a)
+ {
+   return (int16x8_t) __builtin_shuffle (__a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32q_u8 (uint8x16_t __a)
+ {
+   return (uint8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32q_u16 (uint16x8_t __a)
+ {
+   return (uint16x8_t) __builtin_shuffle (__a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32q_p8 (poly8x16_t __a)
+ {
+   return (poly8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 });
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev32q_p16 (poly16x8_t __a)
+ {
+   return (poly16x8_t) __builtin_shuffle (__a, (uint16x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev16_s8 (int8x8_t __a)
+ {
+   return (int8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev16_u8 (uint8x8_t __a)
+ {
+   return (uint8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev16_p8 (poly8x8_t __a)
+ {
+   return (poly8x8_t) __builtin_shuffle (__a, (uint8x8_t) { 1, 0, 3, 2, 5, 4, 7, 6 });
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev16q_s8 (int8x16_t __a)
+ {
+   return (int8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev16q_u8 (uint8x16_t __a)
+ {
+   return (uint8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vrev16q_p8 (poly8x16_t __a)
+ {
+   return (poly8x16_t) __builtin_shuffle (__a, (uint8x16_t) { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 });
+@@ -7866,74 +9143,86 @@ vrev16q_p8 (poly8x16_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_p64 (uint64x1_t __a, poly64x1_t __b, poly64x1_t __c)
+ {
+   return (poly64x1_t)__builtin_neon_vbsldi ((int64x1_t) __a, __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_s8 (uint8x8_t __a, int8x8_t __b, int8x8_t __c)
+ {
+   return (int8x8_t)__builtin_neon_vbslv8qi ((int8x8_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_s16 (uint16x4_t __a, int16x4_t __b, int16x4_t __c)
+ {
+   return (int16x4_t)__builtin_neon_vbslv4hi ((int16x4_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_s32 (uint32x2_t __a, int32x2_t __b, int32x2_t __c)
+ {
+   return (int32x2_t)__builtin_neon_vbslv2si ((int32x2_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_s64 (uint64x1_t __a, int64x1_t __b, int64x1_t __c)
+ {
+   return (int64x1_t)__builtin_neon_vbsldi ((int64x1_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_f32 (uint32x2_t __a, float32x2_t __b, float32x2_t __c)
+ {
+   return (float32x2_t)__builtin_neon_vbslv2sf ((int32x2_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c)
+ {
+   return (uint8x8_t)__builtin_neon_vbslv8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c)
+ {
+   return (uint16x4_t)__builtin_neon_vbslv4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c)
+ {
+   return (uint32x2_t)__builtin_neon_vbslv2si ((int32x2_t) __a, (int32x2_t) __b, (int32x2_t) __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_u64 (uint64x1_t __a, uint64x1_t __b, uint64x1_t __c)
+ {
+   return (uint64x1_t)__builtin_neon_vbsldi ((int64x1_t) __a, (int64x1_t) __b, (int64x1_t) __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_p8 (uint8x8_t __a, poly8x8_t __b, poly8x8_t __c)
+ {
+   return (poly8x8_t)__builtin_neon_vbslv8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbsl_p16 (uint16x4_t __a, poly16x4_t __b, poly16x4_t __c)
+ {
+   return (poly16x4_t)__builtin_neon_vbslv4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
+@@ -7941,74 +9230,86 @@ vbsl_p16 (uint16x4_t __a, poly16x4_t __b, poly16x4_t __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_p64 (uint64x2_t __a, poly64x2_t __b, poly64x2_t __c)
+ {
+   return (poly64x2_t)__builtin_neon_vbslv2di ((int64x2_t) __a, (int64x2_t) __b, (int64x2_t) __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_s8 (uint8x16_t __a, int8x16_t __b, int8x16_t __c)
+ {
+   return (int8x16_t)__builtin_neon_vbslv16qi ((int8x16_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_s16 (uint16x8_t __a, int16x8_t __b, int16x8_t __c)
+ {
+   return (int16x8_t)__builtin_neon_vbslv8hi ((int16x8_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_s32 (uint32x4_t __a, int32x4_t __b, int32x4_t __c)
+ {
+   return (int32x4_t)__builtin_neon_vbslv4si ((int32x4_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_s64 (uint64x2_t __a, int64x2_t __b, int64x2_t __c)
+ {
+   return (int64x2_t)__builtin_neon_vbslv2di ((int64x2_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_f32 (uint32x4_t __a, float32x4_t __b, float32x4_t __c)
+ {
+   return (float32x4_t)__builtin_neon_vbslv4sf ((int32x4_t) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
+ {
+   return (uint8x16_t)__builtin_neon_vbslv16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
+ {
+   return (uint16x8_t)__builtin_neon_vbslv8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
+ {
+   return (uint32x4_t)__builtin_neon_vbslv4si ((int32x4_t) __a, (int32x4_t) __b, (int32x4_t) __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
+ {
+   return (uint64x2_t)__builtin_neon_vbslv2di ((int64x2_t) __a, (int64x2_t) __b, (int64x2_t) __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_p8 (uint8x16_t __a, poly8x16_t __b, poly8x16_t __c)
+ {
+   return (poly8x16_t)__builtin_neon_vbslv16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbslq_p16 (uint16x8_t __a, poly16x8_t __b, poly16x8_t __c)
+ {
+   return (poly16x8_t)__builtin_neon_vbslv8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c);
+@@ -8025,7 +9326,8 @@ vbslq_p16 (uint16x8_t __a, poly16x8_t __b, poly16x8_t __c)
+    vector, and will itself be loaded in reverse order (again, relative to the
+    neon intrinsics view, i.e. that would result from a "vld1" instruction).  */
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   int8x8x2_t __rv;
+@@ -8043,7 +9345,8 @@ vtrn_s8 (int8x8_t __a, int8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   int16x4x2_t __rv;
+@@ -8057,7 +9360,8 @@ vtrn_s16 (int16x4_t __a, int16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   uint8x8x2_t __rv;
+@@ -8075,7 +9379,8 @@ vtrn_u8 (uint8x8_t __a, uint8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   uint16x4x2_t __rv;
+@@ -8089,7 +9394,8 @@ vtrn_u16 (uint16x4_t __a, uint16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   poly8x8x2_t __rv;
+@@ -8107,7 +9413,8 @@ vtrn_p8 (poly8x8_t __a, poly8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+   poly16x4x2_t __rv;
+@@ -8121,7 +9428,8 @@ vtrn_p16 (poly16x4_t __a, poly16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   int32x2x2_t __rv;
+@@ -8135,7 +9443,8 @@ vtrn_s32 (int32x2_t __a, int32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   float32x2x2_t __rv;
+@@ -8149,7 +9458,8 @@ vtrn_f32 (float32x2_t __a, float32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrn_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   uint32x2x2_t __rv;
+@@ -8163,7 +9473,8 @@ vtrn_u32 (uint32x2_t __a, uint32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   int8x16x2_t __rv;
+@@ -8181,7 +9492,8 @@ vtrnq_s8 (int8x16_t __a, int8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   int16x8x2_t __rv;
+@@ -8199,7 +9511,8 @@ vtrnq_s16 (int16x8_t __a, int16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   int32x4x2_t __rv;
+@@ -8213,7 +9526,8 @@ vtrnq_s32 (int32x4_t __a, int32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   float32x4x2_t __rv;
+@@ -8227,7 +9541,8 @@ vtrnq_f32 (float32x4_t __a, float32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   uint8x16x2_t __rv;
+@@ -8245,7 +9560,8 @@ vtrnq_u8 (uint8x16_t __a, uint8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   uint16x8x2_t __rv;
+@@ -8263,7 +9579,8 @@ vtrnq_u16 (uint16x8_t __a, uint16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   uint32x4x2_t __rv;
+@@ -8277,7 +9594,8 @@ vtrnq_u32 (uint32x4_t __a, uint32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   poly8x16x2_t __rv;
+@@ -8295,7 +9613,8 @@ vtrnq_p8 (poly8x16_t __a, poly8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtrnq_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+   poly16x8x2_t __rv;
+@@ -8313,7 +9632,8 @@ vtrnq_p16 (poly16x8_t __a, poly16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   int8x8x2_t __rv;
+@@ -8331,7 +9651,8 @@ vzip_s8 (int8x8_t __a, int8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   int16x4x2_t __rv;
+@@ -8345,7 +9666,8 @@ vzip_s16 (int16x4_t __a, int16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   uint8x8x2_t __rv;
+@@ -8363,7 +9685,8 @@ vzip_u8 (uint8x8_t __a, uint8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   uint16x4x2_t __rv;
+@@ -8377,7 +9700,8 @@ vzip_u16 (uint16x4_t __a, uint16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   poly8x8x2_t __rv;
+@@ -8395,7 +9719,8 @@ vzip_p8 (poly8x8_t __a, poly8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+   poly16x4x2_t __rv;
+@@ -8409,7 +9734,8 @@ vzip_p16 (poly16x4_t __a, poly16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   int32x2x2_t __rv;
+@@ -8423,7 +9749,8 @@ vzip_s32 (int32x2_t __a, int32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   float32x2x2_t __rv;
+@@ -8437,7 +9764,8 @@ vzip_f32 (float32x2_t __a, float32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzip_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   uint32x2x2_t __rv;
+@@ -8451,7 +9779,8 @@ vzip_u32 (uint32x2_t __a, uint32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   int8x16x2_t __rv;
+@@ -8469,7 +9798,8 @@ vzipq_s8 (int8x16_t __a, int8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   int16x8x2_t __rv;
+@@ -8487,7 +9817,8 @@ vzipq_s16 (int16x8_t __a, int16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   int32x4x2_t __rv;
+@@ -8501,7 +9832,8 @@ vzipq_s32 (int32x4_t __a, int32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   float32x4x2_t __rv;
+@@ -8515,7 +9847,8 @@ vzipq_f32 (float32x4_t __a, float32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   uint8x16x2_t __rv;
+@@ -8533,7 +9866,8 @@ vzipq_u8 (uint8x16_t __a, uint8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   uint16x8x2_t __rv;
+@@ -8551,7 +9885,8 @@ vzipq_u16 (uint16x8_t __a, uint16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   uint32x4x2_t __rv;
+@@ -8565,7 +9900,8 @@ vzipq_u32 (uint32x4_t __a, uint32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   poly8x16x2_t __rv;
+@@ -8583,7 +9919,8 @@ vzipq_p8 (poly8x16_t __a, poly8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vzipq_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+   poly16x8x2_t __rv;
+@@ -8601,7 +9938,8 @@ vzipq_p16 (poly16x8_t __a, poly16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   int8x8x2_t __rv;
+@@ -8619,7 +9957,8 @@ vuzp_s8 (int8x8_t __a, int8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   int16x4x2_t __rv;
+@@ -8633,7 +9972,8 @@ vuzp_s16 (int16x4_t __a, int16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   int32x2x2_t __rv;
+@@ -8647,7 +9987,8 @@ vuzp_s32 (int32x2_t __a, int32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_f32 (float32x2_t __a, float32x2_t __b)
+ {
+   float32x2x2_t __rv;
+@@ -8661,7 +10002,8 @@ vuzp_f32 (float32x2_t __a, float32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   uint8x8x2_t __rv;
+@@ -8679,7 +10021,8 @@ vuzp_u8 (uint8x8_t __a, uint8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   uint16x4x2_t __rv;
+@@ -8693,7 +10036,8 @@ vuzp_u16 (uint16x4_t __a, uint16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   uint32x2x2_t __rv;
+@@ -8707,7 +10051,8 @@ vuzp_u32 (uint32x2_t __a, uint32x2_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_p8 (poly8x8_t __a, poly8x8_t __b)
+ {
+   poly8x8x2_t __rv;
+@@ -8725,7 +10070,8 @@ vuzp_p8 (poly8x8_t __a, poly8x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzp_p16 (poly16x4_t __a, poly16x4_t __b)
+ {
+   poly16x4x2_t __rv;
+@@ -8739,7 +10085,8 @@ vuzp_p16 (poly16x4_t __a, poly16x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   int8x16x2_t __rv;
+@@ -8757,7 +10104,8 @@ vuzpq_s8 (int8x16_t __a, int8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   int16x8x2_t __rv;
+@@ -8775,7 +10123,8 @@ vuzpq_s16 (int16x8_t __a, int16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   int32x4x2_t __rv;
+@@ -8789,7 +10138,8 @@ vuzpq_s32 (int32x4_t __a, int32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_f32 (float32x4_t __a, float32x4_t __b)
+ {
+   float32x4x2_t __rv;
+@@ -8803,7 +10153,8 @@ vuzpq_f32 (float32x4_t __a, float32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   uint8x16x2_t __rv;
+@@ -8821,7 +10172,8 @@ vuzpq_u8 (uint8x16_t __a, uint8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   uint16x8x2_t __rv;
+@@ -8839,7 +10191,8 @@ vuzpq_u16 (uint16x8_t __a, uint16x8_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   uint32x4x2_t __rv;
+@@ -8853,7 +10206,8 @@ vuzpq_u32 (uint32x4_t __a, uint32x4_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_p8 (poly8x16_t __a, poly8x16_t __b)
+ {
+   poly8x16x2_t __rv;
+@@ -8871,7 +10225,8 @@ vuzpq_p8 (poly8x16_t __a, poly8x16_t __b)
+   return __rv;
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vuzpq_p16 (poly16x8_t __a, poly16x8_t __b)
+ {
+   poly16x8x2_t __rv;
+@@ -8891,82 +10246,95 @@ vuzpq_p16 (poly16x8_t __a, poly16x8_t __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_p64 (const poly64_t * __a)
+ {
+   return (poly64x1_t)__builtin_neon_vld1di ((const __builtin_neon_di *) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_s8 (const int8_t * __a)
+ {
+   return (int8x8_t)__builtin_neon_vld1v8qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_s16 (const int16_t * __a)
+ {
+   return (int16x4_t)__builtin_neon_vld1v4hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_s32 (const int32_t * __a)
+ {
+   return (int32x2_t)__builtin_neon_vld1v2si ((const __builtin_neon_si *) __a);
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_s64 (const int64_t * __a)
+ {
+   return (int64x1_t)__builtin_neon_vld1di ((const __builtin_neon_di *) __a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_f16 (const float16_t * __a)
+ {
+   return __builtin_neon_vld1v4hf (__a);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_f32 (const float32_t * __a)
+ {
+   return (float32x2_t)__builtin_neon_vld1v2sf ((const __builtin_neon_sf *) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_u8 (const uint8_t * __a)
+ {
+   return (uint8x8_t)__builtin_neon_vld1v8qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_u16 (const uint16_t * __a)
+ {
+   return (uint16x4_t)__builtin_neon_vld1v4hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_u32 (const uint32_t * __a)
+ {
+   return (uint32x2_t)__builtin_neon_vld1v2si ((const __builtin_neon_si *) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_u64 (const uint64_t * __a)
+ {
+   return (uint64x1_t)__builtin_neon_vld1di ((const __builtin_neon_di *) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_p8 (const poly8_t * __a)
+ {
+   return (poly8x8_t)__builtin_neon_vld1v8qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_p16 (const poly16_t * __a)
+ {
+   return (poly16x4_t)__builtin_neon_vld1v4hi ((const __builtin_neon_hi *) __a);
+@@ -8974,144 +10342,167 @@ vld1_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_p64 (const poly64_t * __a)
+ {
+   return (poly64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_s8 (const int8_t * __a)
+ {
+   return (int8x16_t)__builtin_neon_vld1v16qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_s16 (const int16_t * __a)
+ {
+   return (int16x8_t)__builtin_neon_vld1v8hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_s32 (const int32_t * __a)
+ {
+   return (int32x4_t)__builtin_neon_vld1v4si ((const __builtin_neon_si *) __a);
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_s64 (const int64_t * __a)
+ {
+   return (int64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) __a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_f16 (const float16_t * __a)
+ {
+   return __builtin_neon_vld1v8hf (__a);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_f32 (const float32_t * __a)
+ {
+   return (float32x4_t)__builtin_neon_vld1v4sf ((const __builtin_neon_sf *) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_u8 (const uint8_t * __a)
+ {
+   return (uint8x16_t)__builtin_neon_vld1v16qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_u16 (const uint16_t * __a)
+ {
+   return (uint16x8_t)__builtin_neon_vld1v8hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_u32 (const uint32_t * __a)
+ {
+   return (uint32x4_t)__builtin_neon_vld1v4si ((const __builtin_neon_si *) __a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_u64 (const uint64_t * __a)
+ {
+   return (uint64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_p8 (const poly8_t * __a)
+ {
+   return (poly8x16_t)__builtin_neon_vld1v16qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_p16 (const poly16_t * __a)
+ {
+   return (poly16x8_t)__builtin_neon_vld1v8hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_s8 (const int8_t * __a, int8x8_t __b, const int __c)
+ {
+   return (int8x8_t)__builtin_neon_vld1_lanev8qi ((const __builtin_neon_qi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_s16 (const int16_t * __a, int16x4_t __b, const int __c)
+ {
+   return (int16x4_t)__builtin_neon_vld1_lanev4hi ((const __builtin_neon_hi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_s32 (const int32_t * __a, int32x2_t __b, const int __c)
+ {
+   return (int32x2_t)__builtin_neon_vld1_lanev2si ((const __builtin_neon_si *) __a, __b, __c);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_f16 (const float16_t * __a, float16x4_t __b, const int __c)
+ {
+   return vset_lane_f16 (*__a, __b, __c);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_f32 (const float32_t * __a, float32x2_t __b, const int __c)
+ {
+   return (float32x2_t)__builtin_neon_vld1_lanev2sf ((const __builtin_neon_sf *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_u8 (const uint8_t * __a, uint8x8_t __b, const int __c)
+ {
+   return (uint8x8_t)__builtin_neon_vld1_lanev8qi ((const __builtin_neon_qi *) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_u16 (const uint16_t * __a, uint16x4_t __b, const int __c)
+ {
+   return (uint16x4_t)__builtin_neon_vld1_lanev4hi ((const __builtin_neon_hi *) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_u32 (const uint32_t * __a, uint32x2_t __b, const int __c)
+ {
+   return (uint32x2_t)__builtin_neon_vld1_lanev2si ((const __builtin_neon_si *) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_p8 (const poly8_t * __a, poly8x8_t __b, const int __c)
+ {
+   return (poly8x8_t)__builtin_neon_vld1_lanev8qi ((const __builtin_neon_qi *) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_p16 (const poly16_t * __a, poly16x4_t __b, const int __c)
+ {
+   return (poly16x4_t)__builtin_neon_vld1_lanev4hi ((const __builtin_neon_hi *) __a, (int16x4_t) __b, __c);
+@@ -9119,82 +10510,95 @@ vld1_lane_p16 (const poly16_t * __a, poly16x4_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_p64 (const poly64_t * __a, poly64x1_t __b, const int __c)
+ {
+   return (poly64x1_t)__builtin_neon_vld1_lanedi ((const __builtin_neon_di *) __a, __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_s64 (const int64_t * __a, int64x1_t __b, const int __c)
+ {
+   return (int64x1_t)__builtin_neon_vld1_lanedi ((const __builtin_neon_di *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_lane_u64 (const uint64_t * __a, uint64x1_t __b, const int __c)
+ {
+   return (uint64x1_t)__builtin_neon_vld1_lanedi ((const __builtin_neon_di *) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_s8 (const int8_t * __a, int8x16_t __b, const int __c)
+ {
+   return (int8x16_t)__builtin_neon_vld1_lanev16qi ((const __builtin_neon_qi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_s16 (const int16_t * __a, int16x8_t __b, const int __c)
+ {
+   return (int16x8_t)__builtin_neon_vld1_lanev8hi ((const __builtin_neon_hi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_s32 (const int32_t * __a, int32x4_t __b, const int __c)
+ {
+   return (int32x4_t)__builtin_neon_vld1_lanev4si ((const __builtin_neon_si *) __a, __b, __c);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_f16 (const float16_t * __a, float16x8_t __b, const int __c)
+ {
+   return vsetq_lane_f16 (*__a, __b, __c);
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_f32 (const float32_t * __a, float32x4_t __b, const int __c)
+ {
+   return (float32x4_t)__builtin_neon_vld1_lanev4sf ((const __builtin_neon_sf *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_u8 (const uint8_t * __a, uint8x16_t __b, const int __c)
+ {
+   return (uint8x16_t)__builtin_neon_vld1_lanev16qi ((const __builtin_neon_qi *) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_u16 (const uint16_t * __a, uint16x8_t __b, const int __c)
+ {
+   return (uint16x8_t)__builtin_neon_vld1_lanev8hi ((const __builtin_neon_hi *) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_u32 (const uint32_t * __a, uint32x4_t __b, const int __c)
+ {
+   return (uint32x4_t)__builtin_neon_vld1_lanev4si ((const __builtin_neon_si *) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_p8 (const poly8_t * __a, poly8x16_t __b, const int __c)
+ {
+   return (poly8x16_t)__builtin_neon_vld1_lanev16qi ((const __builtin_neon_qi *) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_p16 (const poly16_t * __a, poly16x8_t __b, const int __c)
+ {
+   return (poly16x8_t)__builtin_neon_vld1_lanev8hi ((const __builtin_neon_hi *) __a, (int16x8_t) __b, __c);
+@@ -9202,45 +10606,52 @@ vld1q_lane_p16 (const poly16_t * __a, poly16x8_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_p64 (const poly64_t * __a, poly64x2_t __b, const int __c)
+ {
+   return (poly64x2_t)__builtin_neon_vld1_lanev2di ((const __builtin_neon_di *) __a, (int64x2_t) __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_s64 (const int64_t * __a, int64x2_t __b, const int __c)
+ {
+   return (int64x2_t)__builtin_neon_vld1_lanev2di ((const __builtin_neon_di *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_lane_u64 (const uint64_t * __a, uint64x2_t __b, const int __c)
+ {
+   return (uint64x2_t)__builtin_neon_vld1_lanev2di ((const __builtin_neon_di *) __a, (int64x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_s8 (const int8_t * __a)
+ {
+   return (int8x8_t)__builtin_neon_vld1_dupv8qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_s16 (const int16_t * __a)
+ {
+   return (int16x4_t)__builtin_neon_vld1_dupv4hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_s32 (const int32_t * __a)
+ {
+   return (int32x2_t)__builtin_neon_vld1_dupv2si ((const __builtin_neon_si *) __a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_f16 (const float16_t * __a)
+ {
+   float16_t __f = *__a;
+@@ -9248,37 +10659,43 @@ vld1_dup_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_f32 (const float32_t * __a)
+ {
+   return (float32x2_t)__builtin_neon_vld1_dupv2sf ((const __builtin_neon_sf *) __a);
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_u8 (const uint8_t * __a)
+ {
+   return (uint8x8_t)__builtin_neon_vld1_dupv8qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_u16 (const uint16_t * __a)
+ {
+   return (uint16x4_t)__builtin_neon_vld1_dupv4hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_u32 (const uint32_t * __a)
+ {
+   return (uint32x2_t)__builtin_neon_vld1_dupv2si ((const __builtin_neon_si *) __a);
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_p8 (const poly8_t * __a)
+ {
+   return (poly8x8_t)__builtin_neon_vld1_dupv8qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_p16 (const poly16_t * __a)
+ {
+   return (poly16x4_t)__builtin_neon_vld1_dupv4hi ((const __builtin_neon_hi *) __a);
+@@ -9286,45 +10703,52 @@ vld1_dup_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_p64 (const poly64_t * __a)
+ {
+   return (poly64x1_t)__builtin_neon_vld1_dupdi ((const __builtin_neon_di *) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_s64 (const int64_t * __a)
+ {
+   return (int64x1_t)__builtin_neon_vld1_dupdi ((const __builtin_neon_di *) __a);
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1_dup_u64 (const uint64_t * __a)
+ {
+   return (uint64x1_t)__builtin_neon_vld1_dupdi ((const __builtin_neon_di *) __a);
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_s8 (const int8_t * __a)
+ {
+   return (int8x16_t)__builtin_neon_vld1_dupv16qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_s16 (const int16_t * __a)
+ {
+   return (int16x8_t)__builtin_neon_vld1_dupv8hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_s32 (const int32_t * __a)
+ {
+   return (int32x4_t)__builtin_neon_vld1_dupv4si ((const __builtin_neon_si *) __a);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_f16 (const float16_t * __a)
+ {
+   float16_t __f = *__a;
+@@ -9332,37 +10756,43 @@ vld1q_dup_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_f32 (const float32_t * __a)
+ {
+   return (float32x4_t)__builtin_neon_vld1_dupv4sf ((const __builtin_neon_sf *) __a);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_u8 (const uint8_t * __a)
+ {
+   return (uint8x16_t)__builtin_neon_vld1_dupv16qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_u16 (const uint16_t * __a)
+ {
+   return (uint16x8_t)__builtin_neon_vld1_dupv8hi ((const __builtin_neon_hi *) __a);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_u32 (const uint32_t * __a)
+ {
+   return (uint32x4_t)__builtin_neon_vld1_dupv4si ((const __builtin_neon_si *) __a);
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_p8 (const poly8_t * __a)
+ {
+   return (poly8x16_t)__builtin_neon_vld1_dupv16qi ((const __builtin_neon_qi *) __a);
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_p16 (const poly16_t * __a)
+ {
+   return (poly16x8_t)__builtin_neon_vld1_dupv8hi ((const __builtin_neon_hi *) __a);
+@@ -9370,20 +10800,23 @@ vld1q_dup_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_p64 (const poly64_t * __a)
+ {
+   return (poly64x2_t)__builtin_neon_vld1_dupv2di ((const __builtin_neon_di *) __a);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_s64 (const int64_t * __a)
+ {
+   return (int64x2_t)__builtin_neon_vld1_dupv2di ((const __builtin_neon_di *) __a);
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld1q_dup_u64 (const uint64_t * __a)
+ {
+   return (uint64x2_t)__builtin_neon_vld1_dupv2di ((const __builtin_neon_di *) __a);
+@@ -9391,82 +10824,95 @@ vld1q_dup_u64 (const uint64_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_p64 (poly64_t * __a, poly64x1_t __b)
+ {
+   __builtin_neon_vst1di ((__builtin_neon_di *) __a, __b);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_s8 (int8_t * __a, int8x8_t __b)
+ {
+   __builtin_neon_vst1v8qi ((__builtin_neon_qi *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_s16 (int16_t * __a, int16x4_t __b)
+ {
+   __builtin_neon_vst1v4hi ((__builtin_neon_hi *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_s32 (int32_t * __a, int32x2_t __b)
+ {
+   __builtin_neon_vst1v2si ((__builtin_neon_si *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_s64 (int64_t * __a, int64x1_t __b)
+ {
+   __builtin_neon_vst1di ((__builtin_neon_di *) __a, __b);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_f16 (float16_t * __a, float16x4_t __b)
+ {
+   __builtin_neon_vst1v4hf (__a, __b);
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_f32 (float32_t * __a, float32x2_t __b)
+ {
+   __builtin_neon_vst1v2sf ((__builtin_neon_sf *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_u8 (uint8_t * __a, uint8x8_t __b)
+ {
+   __builtin_neon_vst1v8qi ((__builtin_neon_qi *) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_u16 (uint16_t * __a, uint16x4_t __b)
+ {
+   __builtin_neon_vst1v4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_u32 (uint32_t * __a, uint32x2_t __b)
+ {
+   __builtin_neon_vst1v2si ((__builtin_neon_si *) __a, (int32x2_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_u64 (uint64_t * __a, uint64x1_t __b)
+ {
+   __builtin_neon_vst1di ((__builtin_neon_di *) __a, (int64x1_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_p8 (poly8_t * __a, poly8x8_t __b)
+ {
+   __builtin_neon_vst1v8qi ((__builtin_neon_qi *) __a, (int8x8_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_p16 (poly16_t * __a, poly16x4_t __b)
+ {
+   __builtin_neon_vst1v4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b);
+@@ -9474,144 +10920,167 @@ vst1_p16 (poly16_t * __a, poly16x4_t __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_p64 (poly64_t * __a, poly64x2_t __b)
+ {
+   __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_s8 (int8_t * __a, int8x16_t __b)
+ {
+   __builtin_neon_vst1v16qi ((__builtin_neon_qi *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_s16 (int16_t * __a, int16x8_t __b)
+ {
+   __builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_s32 (int32_t * __a, int32x4_t __b)
+ {
+   __builtin_neon_vst1v4si ((__builtin_neon_si *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_s64 (int64_t * __a, int64x2_t __b)
+ {
+   __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, __b);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_f16 (float16_t * __a, float16x8_t __b)
+ {
+   __builtin_neon_vst1v8hf (__a, __b);
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_f32 (float32_t * __a, float32x4_t __b)
+ {
+   __builtin_neon_vst1v4sf ((__builtin_neon_sf *) __a, __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_u8 (uint8_t * __a, uint8x16_t __b)
+ {
+   __builtin_neon_vst1v16qi ((__builtin_neon_qi *) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_u16 (uint16_t * __a, uint16x8_t __b)
+ {
+   __builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_u32 (uint32_t * __a, uint32x4_t __b)
+ {
+   __builtin_neon_vst1v4si ((__builtin_neon_si *) __a, (int32x4_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_u64 (uint64_t * __a, uint64x2_t __b)
+ {
+   __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_p8 (poly8_t * __a, poly8x16_t __b)
+ {
+   __builtin_neon_vst1v16qi ((__builtin_neon_qi *) __a, (int8x16_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_p16 (poly16_t * __a, poly16x8_t __b)
+ {
+   __builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8qi ((__builtin_neon_qi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_s16 (int16_t * __a, int16x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4hi ((__builtin_neon_hi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_s32 (int32_t * __a, int32x2_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev2si ((__builtin_neon_si *) __a, __b, __c);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_f16 (float16_t * __a, float16x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4hf (__a, __b, __c);
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_f32 (float32_t * __a, float32x2_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev2sf ((__builtin_neon_sf *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_u8 (uint8_t * __a, uint8x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8qi ((__builtin_neon_qi *) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_u16 (uint16_t * __a, uint16x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_u32 (uint32_t * __a, uint32x2_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev2si ((__builtin_neon_si *) __a, (int32x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_p8 (poly8_t * __a, poly8x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8qi ((__builtin_neon_qi *) __a, (int8x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_p16 (poly16_t * __a, poly16x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b, __c);
+@@ -9619,82 +11088,95 @@ vst1_lane_p16 (poly16_t * __a, poly16x4_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_p64 (poly64_t * __a, poly64x1_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanedi ((__builtin_neon_di *) __a, __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_s64 (int64_t * __a, int64x1_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanedi ((__builtin_neon_di *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1_lane_u64 (uint64_t * __a, uint64x1_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanedi ((__builtin_neon_di *) __a, (int64x1_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_s8 (int8_t * __a, int8x16_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev16qi ((__builtin_neon_qi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_s16 (int16_t * __a, int16x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8hi ((__builtin_neon_hi *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_s32 (int32_t * __a, int32x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4si ((__builtin_neon_si *) __a, __b, __c);
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_f16 (float16_t * __a, float16x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8hf (__a, __b, __c);
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_f32 (float32_t * __a, float32x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4sf ((__builtin_neon_sf *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_u8 (uint8_t * __a, uint8x16_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev16qi ((__builtin_neon_qi *) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_u16 (uint16_t * __a, uint16x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_u32 (uint32_t * __a, uint32x4_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev4si ((__builtin_neon_si *) __a, (int32x4_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_p8 (poly8_t * __a, poly8x16_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev16qi ((__builtin_neon_qi *) __a, (int8x16_t) __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_p16 (poly16_t * __a, poly16x8_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b, __c);
+@@ -9702,26 +11184,30 @@ vst1q_lane_p16 (poly16_t * __a, poly16x8_t __b, const int __c)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_p64 (poly64_t * __a, poly64x2_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev2di ((__builtin_neon_di *) __a, (int64x2_t) __b, __c);
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_s64 (int64_t * __a, int64x2_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev2di ((__builtin_neon_di *) __a, __b, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst1q_lane_u64 (uint64_t * __a, uint64x2_t __b, const int __c)
+ {
+   __builtin_neon_vst1_lanev2di ((__builtin_neon_di *) __a, (int64x2_t) __b, __c);
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_s8 (const int8_t * __a)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9729,7 +11215,8 @@ vld2_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_s16 (const int16_t * __a)
+ {
+   union { int16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9737,7 +11224,8 @@ vld2_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_s32 (const int32_t * __a)
+ {
+   union { int32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9746,7 +11234,8 @@ vld2_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_f16 (const float16_t * __a)
+ {
+   union { float16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9755,7 +11244,8 @@ vld2_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_f32 (const float32_t * __a)
+ {
+   union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9763,7 +11253,8 @@ vld2_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_u8 (const uint8_t * __a)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9771,7 +11262,8 @@ vld2_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_u16 (const uint16_t * __a)
+ {
+   union { uint16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9779,7 +11271,8 @@ vld2_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_u32 (const uint32_t * __a)
+ {
+   union { uint32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9787,7 +11280,8 @@ vld2_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_p8 (const poly8_t * __a)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9795,7 +11289,8 @@ vld2_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_p16 (const poly16_t * __a)
+ {
+   union { poly16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9805,7 +11300,8 @@ vld2_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_p64 (const poly64_t * __a)
+ {
+   union { poly64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9814,7 +11310,8 @@ vld2_p64 (const poly64_t * __a)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_s64 (const int64_t * __a)
+ {
+   union { int64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9822,7 +11319,8 @@ vld2_s64 (const int64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint64x1x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_u64 (const uint64_t * __a)
+ {
+   union { uint64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -9830,7 +11328,8 @@ vld2_u64 (const uint64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_s8 (const int8_t * __a)
+ {
+   union { int8x16x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9838,7 +11337,8 @@ vld2q_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_s16 (const int16_t * __a)
+ {
+   union { int16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9846,7 +11346,8 @@ vld2q_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_s32 (const int32_t * __a)
+ {
+   union { int32x4x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9855,7 +11356,8 @@ vld2q_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_f16 (const float16_t * __a)
+ {
+   union { float16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9864,7 +11366,8 @@ vld2q_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_f32 (const float32_t * __a)
+ {
+   union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9872,7 +11375,8 @@ vld2q_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_u8 (const uint8_t * __a)
+ {
+   union { uint8x16x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9880,7 +11384,8 @@ vld2q_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_u16 (const uint16_t * __a)
+ {
+   union { uint16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9888,7 +11393,8 @@ vld2q_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_u32 (const uint32_t * __a)
+ {
+   union { uint32x4x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9896,7 +11402,8 @@ vld2q_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x16x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_p8 (const poly8_t * __a)
+ {
+   union { poly8x16x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9904,7 +11411,8 @@ vld2q_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_p16 (const poly16_t * __a)
+ {
+   union { poly16x8x2_t __i; __builtin_neon_oi __o; } __rv;
+@@ -9912,7 +11420,8 @@ vld2q_p16 (const poly16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_s8 (const int8_t * __a, int8x8x2_t __b, const int __c)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9921,7 +11430,8 @@ vld2_lane_s8 (const int8_t * __a, int8x8x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_s16 (const int16_t * __a, int16x4x2_t __b, const int __c)
+ {
+   union { int16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9930,7 +11440,8 @@ vld2_lane_s16 (const int16_t * __a, int16x4x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_s32 (const int32_t * __a, int32x2x2_t __b, const int __c)
+ {
+   union { int32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9940,7 +11451,8 @@ vld2_lane_s32 (const int32_t * __a, int32x2x2_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_f16 (const float16_t * __a, float16x4x2_t __b, const int __c)
+ {
+   union { float16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9950,7 +11462,8 @@ vld2_lane_f16 (const float16_t * __a, float16x4x2_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_f32 (const float32_t * __a, float32x2x2_t __b, const int __c)
+ {
+   union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9959,7 +11472,8 @@ vld2_lane_f32 (const float32_t * __a, float32x2x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_u8 (const uint8_t * __a, uint8x8x2_t __b, const int __c)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9968,7 +11482,8 @@ vld2_lane_u8 (const uint8_t * __a, uint8x8x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_u16 (const uint16_t * __a, uint16x4x2_t __b, const int __c)
+ {
+   union { uint16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9977,7 +11492,8 @@ vld2_lane_u16 (const uint16_t * __a, uint16x4x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_u32 (const uint32_t * __a, uint32x2x2_t __b, const int __c)
+ {
+   union { uint32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9986,7 +11502,8 @@ vld2_lane_u32 (const uint32_t * __a, uint32x2x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_p8 (const poly8_t * __a, poly8x8x2_t __b, const int __c)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -9995,7 +11512,8 @@ vld2_lane_p8 (const poly8_t * __a, poly8x8x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_lane_p16 (const poly16_t * __a, poly16x4x2_t __b, const int __c)
+ {
+   union { poly16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10004,7 +11522,8 @@ vld2_lane_p16 (const poly16_t * __a, poly16x4x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_s16 (const int16_t * __a, int16x8x2_t __b, const int __c)
+ {
+   union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10013,7 +11532,8 @@ vld2q_lane_s16 (const int16_t * __a, int16x8x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_s32 (const int32_t * __a, int32x4x2_t __b, const int __c)
+ {
+   union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10023,7 +11543,8 @@ vld2q_lane_s32 (const int32_t * __a, int32x4x2_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_f16 (const float16_t * __a, float16x8x2_t __b, const int __c)
+ {
+   union { float16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10033,7 +11554,8 @@ vld2q_lane_f16 (const float16_t * __a, float16x8x2_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_f32 (const float32_t * __a, float32x4x2_t __b, const int __c)
+ {
+   union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10042,7 +11564,8 @@ vld2q_lane_f32 (const float32_t * __a, float32x4x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_u16 (const uint16_t * __a, uint16x8x2_t __b, const int __c)
+ {
+   union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10051,7 +11574,8 @@ vld2q_lane_u16 (const uint16_t * __a, uint16x8x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_u32 (const uint32_t * __a, uint32x4x2_t __b, const int __c)
+ {
+   union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10060,7 +11584,8 @@ vld2q_lane_u32 (const uint32_t * __a, uint32x4x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2q_lane_p16 (const poly16_t * __a, poly16x8x2_t __b, const int __c)
+ {
+   union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10069,7 +11594,8 @@ vld2q_lane_p16 (const poly16_t * __a, poly16x8x2_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_s8 (const int8_t * __a)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10077,7 +11603,8 @@ vld2_dup_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_s16 (const int16_t * __a)
+ {
+   union { int16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10085,7 +11612,8 @@ vld2_dup_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_s32 (const int32_t * __a)
+ {
+   union { int32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10094,7 +11622,8 @@ vld2_dup_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_f16 (const float16_t * __a)
+ {
+   union { float16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10103,7 +11632,8 @@ vld2_dup_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_f32 (const float32_t * __a)
+ {
+   union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10111,7 +11641,8 @@ vld2_dup_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_u8 (const uint8_t * __a)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10119,7 +11650,8 @@ vld2_dup_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_u16 (const uint16_t * __a)
+ {
+   union { uint16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10127,7 +11659,8 @@ vld2_dup_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_u32 (const uint32_t * __a)
+ {
+   union { uint32x2x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10135,7 +11668,8 @@ vld2_dup_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_p8 (const poly8_t * __a)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10143,7 +11677,8 @@ vld2_dup_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_p16 (const poly16_t * __a)
+ {
+   union { poly16x4x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10153,7 +11688,8 @@ vld2_dup_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_p64 (const poly64_t * __a)
+ {
+   union { poly64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10162,7 +11698,8 @@ vld2_dup_p64 (const poly64_t * __a)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_s64 (const int64_t * __a)
+ {
+   union { int64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10170,7 +11707,8 @@ vld2_dup_s64 (const int64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint64x1x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld2_dup_u64 (const uint64_t * __a)
+ {
+   union { uint64x1x2_t __i; __builtin_neon_ti __o; } __rv;
+@@ -10178,21 +11716,24 @@ vld2_dup_u64 (const uint64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_s8 (int8_t * __a, int8x8x2_t __b)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_s16 (int16_t * __a, int16x4x2_t __b)
+ {
+   union { int16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_s32 (int32_t * __a, int32x2x2_t __b)
+ {
+   union { int32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10200,7 +11741,8 @@ vst2_s32 (int32_t * __a, int32x2x2_t __b)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_f16 (float16_t * __a, float16x4x2_t __b)
+ {
+   union { float16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10208,42 +11750,48 @@ vst2_f16 (float16_t * __a, float16x4x2_t __b)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_f32 (float32_t * __a, float32x2x2_t __b)
+ {
+   union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v2sf ((__builtin_neon_sf *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_u8 (uint8_t * __a, uint8x8x2_t __b)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_u16 (uint16_t * __a, uint16x4x2_t __b)
+ {
+   union { uint16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_u32 (uint32_t * __a, uint32x2x2_t __b)
+ {
+   union { uint32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v2si ((__builtin_neon_si *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_p8 (poly8_t * __a, poly8x8x2_t __b)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_p16 (poly16_t * __a, poly16x4x2_t __b)
+ {
+   union { poly16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10252,7 +11800,8 @@ vst2_p16 (poly16_t * __a, poly16x4x2_t __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_p64 (poly64_t * __a, poly64x1x2_t __b)
+ {
+   union { poly64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10260,35 +11809,40 @@ vst2_p64 (poly64_t * __a, poly64x1x2_t __b)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_s64 (int64_t * __a, int64x1x2_t __b)
+ {
+   union { int64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2di ((__builtin_neon_di *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_u64 (uint64_t * __a, uint64x1x2_t __b)
+ {
+   union { uint64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2di ((__builtin_neon_di *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_s8 (int8_t * __a, int8x16x2_t __b)
+ {
+   union { int8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_s16 (int16_t * __a, int16x8x2_t __b)
+ {
+   union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_s32 (int32_t * __a, int32x4x2_t __b)
+ {
+   union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10296,7 +11850,8 @@ vst2q_s32 (int32_t * __a, int32x4x2_t __b)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_f16 (float16_t * __a, float16x8x2_t __b)
+ {
+   union { float16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10304,63 +11859,72 @@ vst2q_f16 (float16_t * __a, float16x8x2_t __b)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_f32 (float32_t * __a, float32x4x2_t __b)
+ {
+   union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v4sf ((__builtin_neon_sf *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_u8 (uint8_t * __a, uint8x16x2_t __b)
+ {
+   union { uint8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_u16 (uint16_t * __a, uint16x8x2_t __b)
+ {
+   union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_u32 (uint32_t * __a, uint32x4x2_t __b)
+ {
+   union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v4si ((__builtin_neon_si *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_p8 (poly8_t * __a, poly8x16x2_t __b)
+ {
+   union { poly8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_p16 (poly16_t * __a, poly16x8x2_t __b)
+ {
+   union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_s8 (int8_t * __a, int8x8x2_t __b, const int __c)
+ {
+   union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_s16 (int16_t * __a, int16x4x2_t __b, const int __c)
+ {
+   union { int16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_s32 (int32_t * __a, int32x2x2_t __b, const int __c)
+ {
+   union { int32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10368,7 +11932,8 @@ vst2_lane_s32 (int32_t * __a, int32x2x2_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_f16 (float16_t * __a, float16x4x2_t __b, const int __c)
+ {
+   union { float16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+@@ -10376,56 +11941,64 @@ vst2_lane_f16 (float16_t * __a, float16x4x2_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_f32 (float32_t * __a, float32x2x2_t __b, const int __c)
+ {
+   union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev2sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_u8 (uint8_t * __a, uint8x8x2_t __b, const int __c)
+ {
+   union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_u16 (uint16_t * __a, uint16x4x2_t __b, const int __c)
+ {
+   union { uint16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_u32 (uint32_t * __a, uint32x2x2_t __b, const int __c)
+ {
+   union { uint32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev2si ((__builtin_neon_si *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_p8 (poly8_t * __a, poly8x8x2_t __b, const int __c)
+ {
+   union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2_lane_p16 (poly16_t * __a, poly16x4x2_t __b, const int __c)
+ {
+   union { poly16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_s16 (int16_t * __a, int16x8x2_t __b, const int __c)
+ {
+   union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_s32 (int32_t * __a, int32x4x2_t __b, const int __c)
+ {
+   union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10433,7 +12006,8 @@ vst2q_lane_s32 (int32_t * __a, int32x4x2_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_f16 (float16_t * __a, float16x8x2_t __b, const int __c)
+ {
+   union { float16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -10441,35 +12015,40 @@ vst2q_lane_f16 (float16_t * __a, float16x8x2_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_f32 (float32_t * __a, float32x4x2_t __b, const int __c)
+ {
+   union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev4sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_u16 (uint16_t * __a, uint16x8x2_t __b, const int __c)
+ {
+   union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_u32 (uint32_t * __a, uint32x4x2_t __b, const int __c)
+ {
+   union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev4si ((__builtin_neon_si *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst2q_lane_p16 (poly16_t * __a, poly16x8x2_t __b, const int __c)
+ {
+   union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst2_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_s8 (const int8_t * __a)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10477,7 +12056,8 @@ vld3_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_s16 (const int16_t * __a)
+ {
+   union { int16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10485,7 +12065,8 @@ vld3_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_s32 (const int32_t * __a)
+ {
+   union { int32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10494,7 +12075,8 @@ vld3_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_f16 (const float16_t * __a)
+ {
+   union { float16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10503,7 +12085,8 @@ vld3_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_f32 (const float32_t * __a)
+ {
+   union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10511,7 +12094,8 @@ vld3_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_u8 (const uint8_t * __a)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10519,7 +12103,8 @@ vld3_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_u16 (const uint16_t * __a)
+ {
+   union { uint16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10527,7 +12112,8 @@ vld3_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_u32 (const uint32_t * __a)
+ {
+   union { uint32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10535,7 +12121,8 @@ vld3_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_p8 (const poly8_t * __a)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10543,7 +12130,8 @@ vld3_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_p16 (const poly16_t * __a)
+ {
+   union { poly16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10553,7 +12141,8 @@ vld3_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_p64 (const poly64_t * __a)
+ {
+   union { poly64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10562,7 +12151,8 @@ vld3_p64 (const poly64_t * __a)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_s64 (const int64_t * __a)
+ {
+   union { int64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10570,7 +12160,8 @@ vld3_s64 (const int64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint64x1x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_u64 (const uint64_t * __a)
+ {
+   union { uint64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10578,7 +12169,8 @@ vld3_u64 (const uint64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x16x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_s8 (const int8_t * __a)
+ {
+   union { int8x16x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10586,7 +12178,8 @@ vld3q_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_s16 (const int16_t * __a)
+ {
+   union { int16x8x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10594,7 +12187,8 @@ vld3q_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_s32 (const int32_t * __a)
+ {
+   union { int32x4x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10603,7 +12197,8 @@ vld3q_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_f16 (const float16_t * __a)
+ {
+   union { float16x8x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10612,7 +12207,8 @@ vld3q_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_f32 (const float32_t * __a)
+ {
+   union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10620,7 +12216,8 @@ vld3q_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x16x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_u8 (const uint8_t * __a)
+ {
+   union { uint8x16x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10628,7 +12225,8 @@ vld3q_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_u16 (const uint16_t * __a)
+ {
+   union { uint16x8x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10636,7 +12234,8 @@ vld3q_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_u32 (const uint32_t * __a)
+ {
+   union { uint32x4x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10644,7 +12243,8 @@ vld3q_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x16x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_p8 (const poly8_t * __a)
+ {
+   union { poly8x16x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10652,7 +12252,8 @@ vld3q_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_p16 (const poly16_t * __a)
+ {
+   union { poly16x8x3_t __i; __builtin_neon_ci __o; } __rv;
+@@ -10660,7 +12261,8 @@ vld3q_p16 (const poly16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_s8 (const int8_t * __a, int8x8x3_t __b, const int __c)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10669,7 +12271,8 @@ vld3_lane_s8 (const int8_t * __a, int8x8x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_s16 (const int16_t * __a, int16x4x3_t __b, const int __c)
+ {
+   union { int16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10678,7 +12281,8 @@ vld3_lane_s16 (const int16_t * __a, int16x4x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_s32 (const int32_t * __a, int32x2x3_t __b, const int __c)
+ {
+   union { int32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10688,7 +12292,8 @@ vld3_lane_s32 (const int32_t * __a, int32x2x3_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_f16 (const float16_t * __a, float16x4x3_t __b, const int __c)
+ {
+   union { float16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10698,7 +12303,8 @@ vld3_lane_f16 (const float16_t * __a, float16x4x3_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_f32 (const float32_t * __a, float32x2x3_t __b, const int __c)
+ {
+   union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10707,7 +12313,8 @@ vld3_lane_f32 (const float32_t * __a, float32x2x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_u8 (const uint8_t * __a, uint8x8x3_t __b, const int __c)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10716,7 +12323,8 @@ vld3_lane_u8 (const uint8_t * __a, uint8x8x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_u16 (const uint16_t * __a, uint16x4x3_t __b, const int __c)
+ {
+   union { uint16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10725,7 +12333,8 @@ vld3_lane_u16 (const uint16_t * __a, uint16x4x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_u32 (const uint32_t * __a, uint32x2x3_t __b, const int __c)
+ {
+   union { uint32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10734,7 +12343,8 @@ vld3_lane_u32 (const uint32_t * __a, uint32x2x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_p8 (const poly8_t * __a, poly8x8x3_t __b, const int __c)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10743,7 +12353,8 @@ vld3_lane_p8 (const poly8_t * __a, poly8x8x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_lane_p16 (const poly16_t * __a, poly16x4x3_t __b, const int __c)
+ {
+   union { poly16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10752,7 +12363,8 @@ vld3_lane_p16 (const poly16_t * __a, poly16x4x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_s16 (const int16_t * __a, int16x8x3_t __b, const int __c)
+ {
+   union { int16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10761,7 +12373,8 @@ vld3q_lane_s16 (const int16_t * __a, int16x8x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_s32 (const int32_t * __a, int32x4x3_t __b, const int __c)
+ {
+   union { int32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10771,7 +12384,8 @@ vld3q_lane_s32 (const int32_t * __a, int32x4x3_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_f16 (const float16_t * __a, float16x8x3_t __b, const int __c)
+ {
+   union { float16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10781,7 +12395,8 @@ vld3q_lane_f16 (const float16_t * __a, float16x8x3_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_f32 (const float32_t * __a, float32x4x3_t __b, const int __c)
+ {
+   union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10790,7 +12405,8 @@ vld3q_lane_f32 (const float32_t * __a, float32x4x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_u16 (const uint16_t * __a, uint16x8x3_t __b, const int __c)
+ {
+   union { uint16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10799,7 +12415,8 @@ vld3q_lane_u16 (const uint16_t * __a, uint16x8x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_u32 (const uint32_t * __a, uint32x4x3_t __b, const int __c)
+ {
+   union { uint32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10808,7 +12425,8 @@ vld3q_lane_u32 (const uint32_t * __a, uint32x4x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3q_lane_p16 (const poly16_t * __a, poly16x8x3_t __b, const int __c)
+ {
+   union { poly16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -10817,7 +12435,8 @@ vld3q_lane_p16 (const poly16_t * __a, poly16x8x3_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_s8 (const int8_t * __a)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10825,7 +12444,8 @@ vld3_dup_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_s16 (const int16_t * __a)
+ {
+   union { int16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10833,7 +12453,8 @@ vld3_dup_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_s32 (const int32_t * __a)
+ {
+   union { int32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10842,7 +12463,8 @@ vld3_dup_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_f16 (const float16_t * __a)
+ {
+   union { float16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10851,7 +12473,8 @@ vld3_dup_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_f32 (const float32_t * __a)
+ {
+   union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10859,7 +12482,8 @@ vld3_dup_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_u8 (const uint8_t * __a)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10867,7 +12491,8 @@ vld3_dup_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_u16 (const uint16_t * __a)
+ {
+   union { uint16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10875,7 +12500,8 @@ vld3_dup_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_u32 (const uint32_t * __a)
+ {
+   union { uint32x2x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10883,7 +12509,8 @@ vld3_dup_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_p8 (const poly8_t * __a)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10891,7 +12518,8 @@ vld3_dup_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_p16 (const poly16_t * __a)
+ {
+   union { poly16x4x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10901,7 +12529,8 @@ vld3_dup_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_p64 (const poly64_t * __a)
+ {
+   union { poly64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10910,7 +12539,8 @@ vld3_dup_p64 (const poly64_t * __a)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_s64 (const int64_t * __a)
+ {
+   union { int64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10918,7 +12548,8 @@ vld3_dup_s64 (const int64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint64x1x3_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1x3_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld3_dup_u64 (const uint64_t * __a)
+ {
+   union { uint64x1x3_t __i; __builtin_neon_ei __o; } __rv;
+@@ -10926,21 +12557,24 @@ vld3_dup_u64 (const uint64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_s8 (int8_t * __a, int8x8x3_t __b)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_s16 (int16_t * __a, int16x4x3_t __b)
+ {
+   union { int16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_s32 (int32_t * __a, int32x2x3_t __b)
+ {
+   union { int32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10948,7 +12582,8 @@ vst3_s32 (int32_t * __a, int32x2x3_t __b)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_f16 (float16_t * __a, float16x4x3_t __b)
+ {
+   union { float16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -10956,42 +12591,48 @@ vst3_f16 (float16_t * __a, float16x4x3_t __b)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_f32 (float32_t * __a, float32x2x3_t __b)
+ {
+   union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v2sf ((__builtin_neon_sf *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_u8 (uint8_t * __a, uint8x8x3_t __b)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_u16 (uint16_t * __a, uint16x4x3_t __b)
+ {
+   union { uint16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_u32 (uint32_t * __a, uint32x2x3_t __b)
+ {
+   union { uint32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v2si ((__builtin_neon_si *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_p8 (poly8_t * __a, poly8x8x3_t __b)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_p16 (poly16_t * __a, poly16x4x3_t __b)
+ {
+   union { poly16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -11000,7 +12641,8 @@ vst3_p16 (poly16_t * __a, poly16x4x3_t __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_p64 (poly64_t * __a, poly64x1x3_t __b)
+ {
+   union { poly64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -11008,35 +12650,40 @@ vst3_p64 (poly64_t * __a, poly64x1x3_t __b)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_s64 (int64_t * __a, int64x1x3_t __b)
+ {
+   union { int64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3di ((__builtin_neon_di *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_u64 (uint64_t * __a, uint64x1x3_t __b)
+ {
+   union { uint64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3di ((__builtin_neon_di *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_s8 (int8_t * __a, int8x16x3_t __b)
+ {
+   union { int8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_s16 (int16_t * __a, int16x8x3_t __b)
+ {
+   union { int16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_s32 (int32_t * __a, int32x4x3_t __b)
+ {
+   union { int32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -11044,7 +12691,8 @@ vst3q_s32 (int32_t * __a, int32x4x3_t __b)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_f16 (float16_t * __a, float16x8x3_t __b)
+ {
+   union { float16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -11052,63 +12700,72 @@ vst3q_f16 (float16_t * __a, float16x8x3_t __b)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_f32 (float32_t * __a, float32x4x3_t __b)
+ {
+   union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v4sf ((__builtin_neon_sf *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_u8 (uint8_t * __a, uint8x16x3_t __b)
+ {
+   union { uint8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_u16 (uint16_t * __a, uint16x8x3_t __b)
+ {
+   union { uint16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_u32 (uint32_t * __a, uint32x4x3_t __b)
+ {
+   union { uint32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v4si ((__builtin_neon_si *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_p8 (poly8_t * __a, poly8x16x3_t __b)
+ {
+   union { poly8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_p16 (poly16_t * __a, poly16x8x3_t __b)
+ {
+   union { poly16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_s8 (int8_t * __a, int8x8x3_t __b, const int __c)
+ {
+   union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_s16 (int16_t * __a, int16x4x3_t __b, const int __c)
+ {
+   union { int16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_s32 (int32_t * __a, int32x2x3_t __b, const int __c)
+ {
+   union { int32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -11116,7 +12773,8 @@ vst3_lane_s32 (int32_t * __a, int32x2x3_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_f16 (float16_t * __a, float16x4x3_t __b, const int __c)
+ {
+   union { float16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+@@ -11124,56 +12782,64 @@ vst3_lane_f16 (float16_t * __a, float16x4x3_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_f32 (float32_t * __a, float32x2x3_t __b, const int __c)
+ {
+   union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev2sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_u8 (uint8_t * __a, uint8x8x3_t __b, const int __c)
+ {
+   union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_u16 (uint16_t * __a, uint16x4x3_t __b, const int __c)
+ {
+   union { uint16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_u32 (uint32_t * __a, uint32x2x3_t __b, const int __c)
+ {
+   union { uint32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev2si ((__builtin_neon_si *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_p8 (poly8_t * __a, poly8x8x3_t __b, const int __c)
+ {
+   union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3_lane_p16 (poly16_t * __a, poly16x4x3_t __b, const int __c)
+ {
+   union { poly16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_s16 (int16_t * __a, int16x8x3_t __b, const int __c)
+ {
+   union { int16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_s32 (int32_t * __a, int32x4x3_t __b, const int __c)
+ {
+   union { int32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -11181,7 +12847,8 @@ vst3q_lane_s32 (int32_t * __a, int32x4x3_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_f16 (float16_t * __a, float16x8x3_t __b, const int __c)
+ {
+   union { float16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+@@ -11189,35 +12856,40 @@ vst3q_lane_f16 (float16_t * __a, float16x8x3_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_f32 (float32_t * __a, float32x4x3_t __b, const int __c)
+ {
+   union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev4sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_u16 (uint16_t * __a, uint16x8x3_t __b, const int __c)
+ {
+   union { uint16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_u32 (uint32_t * __a, uint32x4x3_t __b, const int __c)
+ {
+   union { uint32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev4si ((__builtin_neon_si *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst3q_lane_p16 (poly16_t * __a, poly16x8x3_t __b, const int __c)
+ {
+   union { poly16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
+   __builtin_neon_vst3_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_s8 (const int8_t * __a)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11225,7 +12897,8 @@ vld4_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_s16 (const int16_t * __a)
+ {
+   union { int16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11233,7 +12906,8 @@ vld4_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_s32 (const int32_t * __a)
+ {
+   union { int32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11242,7 +12916,8 @@ vld4_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_f16 (const float16_t * __a)
+ {
+   union { float16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11251,7 +12926,8 @@ vld4_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_f32 (const float32_t * __a)
+ {
+   union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11259,7 +12935,8 @@ vld4_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_u8 (const uint8_t * __a)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11267,7 +12944,8 @@ vld4_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_u16 (const uint16_t * __a)
+ {
+   union { uint16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11275,7 +12953,8 @@ vld4_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_u32 (const uint32_t * __a)
+ {
+   union { uint32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11283,7 +12962,8 @@ vld4_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_p8 (const poly8_t * __a)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11291,7 +12971,8 @@ vld4_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_p16 (const poly16_t * __a)
+ {
+   union { poly16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11301,7 +12982,8 @@ vld4_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_p64 (const poly64_t * __a)
+ {
+   union { poly64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11310,7 +12992,8 @@ vld4_p64 (const poly64_t * __a)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_s64 (const int64_t * __a)
+ {
+   union { int64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11318,7 +13001,8 @@ vld4_s64 (const int64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint64x1x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_u64 (const uint64_t * __a)
+ {
+   union { uint64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11326,7 +13010,8 @@ vld4_u64 (const uint64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_s8 (const int8_t * __a)
+ {
+   union { int8x16x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11334,7 +13019,8 @@ vld4q_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_s16 (const int16_t * __a)
+ {
+   union { int16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11342,7 +13028,8 @@ vld4q_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_s32 (const int32_t * __a)
+ {
+   union { int32x4x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11351,7 +13038,8 @@ vld4q_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_f16 (const float16_t * __a)
+ {
+   union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11360,7 +13048,8 @@ vld4q_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_f32 (const float32_t * __a)
+ {
+   union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11368,7 +13057,8 @@ vld4q_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_u8 (const uint8_t * __a)
+ {
+   union { uint8x16x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11376,7 +13066,8 @@ vld4q_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_u16 (const uint16_t * __a)
+ {
+   union { uint16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11384,7 +13075,8 @@ vld4q_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_u32 (const uint32_t * __a)
+ {
+   union { uint32x4x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11392,7 +13084,8 @@ vld4q_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_p8 (const poly8_t * __a)
+ {
+   union { poly8x16x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11400,7 +13093,8 @@ vld4q_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_p16 (const poly16_t * __a)
+ {
+   union { poly16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+@@ -11408,7 +13102,8 @@ vld4q_p16 (const poly16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_s8 (const int8_t * __a, int8x8x4_t __b, const int __c)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11417,7 +13112,8 @@ vld4_lane_s8 (const int8_t * __a, int8x8x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_s16 (const int16_t * __a, int16x4x4_t __b, const int __c)
+ {
+   union { int16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11426,7 +13122,8 @@ vld4_lane_s16 (const int16_t * __a, int16x4x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_s32 (const int32_t * __a, int32x2x4_t __b, const int __c)
+ {
+   union { int32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11436,7 +13133,8 @@ vld4_lane_s32 (const int32_t * __a, int32x2x4_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_f16 (const float16_t * __a, float16x4x4_t __b, const int __c)
+ {
+   union { float16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11447,7 +13145,8 @@ vld4_lane_f16 (const float16_t * __a, float16x4x4_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_f32 (const float32_t * __a, float32x2x4_t __b, const int __c)
+ {
+   union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11456,7 +13155,8 @@ vld4_lane_f32 (const float32_t * __a, float32x2x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_u8 (const uint8_t * __a, uint8x8x4_t __b, const int __c)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11465,7 +13165,8 @@ vld4_lane_u8 (const uint8_t * __a, uint8x8x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_u16 (const uint16_t * __a, uint16x4x4_t __b, const int __c)
+ {
+   union { uint16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11474,7 +13175,8 @@ vld4_lane_u16 (const uint16_t * __a, uint16x4x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_u32 (const uint32_t * __a, uint32x2x4_t __b, const int __c)
+ {
+   union { uint32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11483,7 +13185,8 @@ vld4_lane_u32 (const uint32_t * __a, uint32x2x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_p8 (const poly8_t * __a, poly8x8x4_t __b, const int __c)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11492,7 +13195,8 @@ vld4_lane_p8 (const poly8_t * __a, poly8x8x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_lane_p16 (const poly16_t * __a, poly16x4x4_t __b, const int __c)
+ {
+   union { poly16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11501,7 +13205,8 @@ vld4_lane_p16 (const poly16_t * __a, poly16x4x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_s16 (const int16_t * __a, int16x8x4_t __b, const int __c)
+ {
+   union { int16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11510,7 +13215,8 @@ vld4q_lane_s16 (const int16_t * __a, int16x8x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_s32 (const int32_t * __a, int32x4x4_t __b, const int __c)
+ {
+   union { int32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11520,7 +13226,8 @@ vld4q_lane_s32 (const int32_t * __a, int32x4x4_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_f16 (const float16_t * __a, float16x8x4_t __b, const int __c)
+ {
+   union { float16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11531,7 +13238,8 @@ vld4q_lane_f16 (const float16_t * __a, float16x8x4_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_f32 (const float32_t * __a, float32x4x4_t __b, const int __c)
+ {
+   union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11540,7 +13248,8 @@ vld4q_lane_f32 (const float32_t * __a, float32x4x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_u16 (const uint16_t * __a, uint16x8x4_t __b, const int __c)
+ {
+   union { uint16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11549,7 +13258,8 @@ vld4q_lane_u16 (const uint16_t * __a, uint16x8x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_u32 (const uint32_t * __a, uint32x4x4_t __b, const int __c)
+ {
+   union { uint32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11558,7 +13268,8 @@ vld4q_lane_u32 (const uint32_t * __a, uint32x4x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4q_lane_p16 (const poly16_t * __a, poly16x8x4_t __b, const int __c)
+ {
+   union { poly16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11567,7 +13278,8 @@ vld4q_lane_p16 (const poly16_t * __a, poly16x8x4_t __b, const int __c)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_s8 (const int8_t * __a)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11575,7 +13287,8 @@ vld4_dup_s8 (const int8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_s16 (const int16_t * __a)
+ {
+   union { int16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11583,7 +13296,8 @@ vld4_dup_s16 (const int16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline int32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_s32 (const int32_t * __a)
+ {
+   union { int32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11592,7 +13306,8 @@ vld4_dup_s32 (const int32_t * __a)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_f16 (const float16_t * __a)
+ {
+   union { float16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11601,7 +13316,8 @@ vld4_dup_f16 (const float16_t * __a)
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_f32 (const float32_t * __a)
+ {
+   union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11609,7 +13325,8 @@ vld4_dup_f32 (const float32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_u8 (const uint8_t * __a)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11617,7 +13334,8 @@ vld4_dup_u8 (const uint8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_u16 (const uint16_t * __a)
+ {
+   union { uint16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11625,7 +13343,8 @@ vld4_dup_u16 (const uint16_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint32x2x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_u32 (const uint32_t * __a)
+ {
+   union { uint32x2x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11633,7 +13352,8 @@ vld4_dup_u32 (const uint32_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly8x8x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_p8 (const poly8_t * __a)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11641,7 +13361,8 @@ vld4_dup_p8 (const poly8_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline poly16x4x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_p16 (const poly16_t * __a)
+ {
+   union { poly16x4x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11651,7 +13372,8 @@ vld4_dup_p16 (const poly16_t * __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_p64 (const poly64_t * __a)
+ {
+   union { poly64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11660,7 +13382,8 @@ vld4_dup_p64 (const poly64_t * __a)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_s64 (const int64_t * __a)
+ {
+   union { int64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11668,7 +13391,8 @@ vld4_dup_s64 (const int64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline uint64x1x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vld4_dup_u64 (const uint64_t * __a)
+ {
+   union { uint64x1x4_t __i; __builtin_neon_oi __o; } __rv;
+@@ -11676,21 +13400,24 @@ vld4_dup_u64 (const uint64_t * __a)
+   return __rv.__i;
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_s8 (int8_t * __a, int8x8x4_t __b)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_s16 (int16_t * __a, int16x4x4_t __b)
+ {
+   union { int16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_s32 (int32_t * __a, int32x2x4_t __b)
+ {
+   union { int32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11698,7 +13425,8 @@ vst4_s32 (int32_t * __a, int32x2x4_t __b)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_f16 (float16_t * __a, float16x4x4_t __b)
+ {
+   union { float16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11706,42 +13434,48 @@ vst4_f16 (float16_t * __a, float16x4x4_t __b)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_f32 (float32_t * __a, float32x2x4_t __b)
+ {
+   union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v2sf ((__builtin_neon_sf *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_u8 (uint8_t * __a, uint8x8x4_t __b)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_u16 (uint16_t * __a, uint16x4x4_t __b)
+ {
+   union { uint16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_u32 (uint32_t * __a, uint32x2x4_t __b)
+ {
+   union { uint32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v2si ((__builtin_neon_si *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_p8 (poly8_t * __a, poly8x8x4_t __b)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_p16 (poly16_t * __a, poly16x4x4_t __b)
+ {
+   union { poly16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11750,7 +13484,8 @@ vst4_p16 (poly16_t * __a, poly16x4x4_t __b)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_p64 (poly64_t * __a, poly64x1x4_t __b)
+ {
+   union { poly64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11758,35 +13493,40 @@ vst4_p64 (poly64_t * __a, poly64x1x4_t __b)
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_s64 (int64_t * __a, int64x1x4_t __b)
+ {
+   union { int64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4di ((__builtin_neon_di *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_u64 (uint64_t * __a, uint64x1x4_t __b)
+ {
+   union { uint64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4di ((__builtin_neon_di *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_s8 (int8_t * __a, int8x16x4_t __b)
+ {
+   union { int8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_s16 (int16_t * __a, int16x8x4_t __b)
+ {
+   union { int16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_s32 (int32_t * __a, int32x4x4_t __b)
+ {
+   union { int32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11794,7 +13534,8 @@ vst4q_s32 (int32_t * __a, int32x4x4_t __b)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_f16 (float16_t * __a, float16x8x4_t __b)
+ {
+   union { float16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11802,63 +13543,72 @@ vst4q_f16 (float16_t * __a, float16x8x4_t __b)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_f32 (float32_t * __a, float32x4x4_t __b)
+ {
+   union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v4sf ((__builtin_neon_sf *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_u8 (uint8_t * __a, uint8x16x4_t __b)
+ {
+   union { uint8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_u16 (uint16_t * __a, uint16x8x4_t __b)
+ {
+   union { uint16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_u32 (uint32_t * __a, uint32x4x4_t __b)
+ {
+   union { uint32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v4si ((__builtin_neon_si *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_p8 (poly8_t * __a, poly8x16x4_t __b)
+ {
+   union { poly8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_p16 (poly16_t * __a, poly16x8x4_t __b)
+ {
+   union { poly16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_s8 (int8_t * __a, int8x8x4_t __b, const int __c)
+ {
+   union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_s16 (int16_t * __a, int16x4x4_t __b, const int __c)
+ {
+   union { int16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_s32 (int32_t * __a, int32x2x4_t __b, const int __c)
+ {
+   union { int32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11866,7 +13616,8 @@ vst4_lane_s32 (int32_t * __a, int32x2x4_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_f16 (float16_t * __a, float16x4x4_t __b, const int __c)
+ {
+   union { float16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+@@ -11874,56 +13625,64 @@ vst4_lane_f16 (float16_t * __a, float16x4x4_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_f32 (float32_t * __a, float32x2x4_t __b, const int __c)
+ {
+   union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev2sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_u8 (uint8_t * __a, uint8x8x4_t __b, const int __c)
+ {
+   union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_u16 (uint16_t * __a, uint16x4x4_t __b, const int __c)
+ {
+   union { uint16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_u32 (uint32_t * __a, uint32x2x4_t __b, const int __c)
+ {
+   union { uint32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev2si ((__builtin_neon_si *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_p8 (poly8_t * __a, poly8x8x4_t __b, const int __c)
+ {
+   union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev8qi ((__builtin_neon_qi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4_lane_p16 (poly16_t * __a, poly16x4x4_t __b, const int __c)
+ {
+   union { poly16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev4hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_s16 (int16_t * __a, int16x8x4_t __b, const int __c)
+ {
+   union { int16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_s32 (int32_t * __a, int32x4x4_t __b, const int __c)
+ {
+   union { int32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11931,7 +13690,8 @@ vst4q_lane_s32 (int32_t * __a, int32x4x4_t __b, const int __c)
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_f16 (float16_t * __a, float16x8x4_t __b, const int __c)
+ {
+   union { float16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+@@ -11939,529 +13699,616 @@ vst4q_lane_f16 (float16_t * __a, float16x8x4_t __b, const int __c)
+ }
+ #endif
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_f32 (float32_t * __a, float32x4x4_t __b, const int __c)
+ {
+   union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev4sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_u16 (uint16_t * __a, uint16x8x4_t __b, const int __c)
+ {
+   union { uint16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_u32 (uint32_t * __a, uint32x4x4_t __b, const int __c)
+ {
+   union { uint32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev4si ((__builtin_neon_si *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vst4q_lane_p16 (poly16_t * __a, poly16x8x4_t __b, const int __c)
+ {
+   union { poly16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+   __builtin_neon_vst4_lanev8hi ((__builtin_neon_hi *) __a, __bu.__o, __c);
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vand_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vandq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a & __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorr_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorrq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a | __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veor_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ veorq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a ^ __b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbic_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vbicq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a & ~__b;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s8 (int8x8_t __a, int8x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s16 (int16x4_t __a, int16x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s32 (int32x2_t __a, int32x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u8 (uint8x8_t __a, uint8x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u16 (uint16x4_t __a, uint16x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u32 (uint32x2_t __a, uint32x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_s64 (int64x1_t __a, int64x1_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vorn_u64 (uint64x1_t __a, uint64x1_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s8 (int8x16_t __a, int8x16_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s16 (int16x8_t __a, int16x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s32 (int32x4_t __a, int32x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_s64 (int64x2_t __a, int64x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u8 (uint8x16_t __a, uint8x16_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u16 (uint16x8_t __a, uint16x8_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u32 (uint32x4_t __a, uint32x4_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vornq_u64 (uint64x2_t __a, uint64x2_t __b)
+ {
+   return __a | ~__b;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_p16 (poly16x4_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_f16 (float16x4_t __a)
+ {
+   return (poly8x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_f32 (float32x2_t __a)
+ {
+   return (poly8x8_t)__a;
+@@ -12469,76 +14316,88 @@ vreinterpret_p8_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_p64 (poly64x1_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s64 (int64x1_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u64 (uint64x1_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s8 (int8x8_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s16 (int16x4_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_s32 (int32x2_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u8 (uint8x8_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u16 (uint16x4_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p8_u32 (uint32x2_t __a)
+ {
+   return (poly8x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_p8 (poly8x8_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_f16 (float16x4_t __a)
+ {
+   return (poly16x4_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_f32 (float32x2_t __a)
+ {
+   return (poly16x4_t)__a;
+@@ -12546,63 +14405,73 @@ vreinterpret_p16_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_p64 (poly64x1_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s64 (int64x1_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u64 (uint64x1_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s8 (int8x8_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s16 (int16x4_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_s32 (int32x2_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u8 (uint8x8_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u16 (uint16x4_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p16_u32 (uint32x2_t __a)
+ {
+   return (poly16x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_p8 (poly8x8_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12610,7 +14479,8 @@ vreinterpret_f16_p8 (poly8x8_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_p16 (poly16x4_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12618,7 +14488,8 @@ vreinterpret_f16_p16 (poly16x4_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_f32 (float32x2_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12628,7 +14499,8 @@ vreinterpret_f16_f32 (float32x2_t __a)
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_p64 (poly64x1_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12637,7 +14509,8 @@ vreinterpret_f16_p64 (poly64x1_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s64 (int64x1_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12645,7 +14518,8 @@ vreinterpret_f16_s64 (int64x1_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u64 (uint64x1_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12653,7 +14527,8 @@ vreinterpret_f16_u64 (uint64x1_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s8 (int8x8_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12661,7 +14536,8 @@ vreinterpret_f16_s8 (int8x8_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s16 (int16x4_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12669,7 +14545,8 @@ vreinterpret_f16_s16 (int16x4_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_s32 (int32x2_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12677,7 +14554,8 @@ vreinterpret_f16_s32 (int32x2_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u8 (uint8x8_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12685,7 +14563,8 @@ vreinterpret_f16_u8 (uint8x8_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u16 (uint16x4_t __a)
+ {
+   return (float16x4_t) __a;
+@@ -12693,27 +14572,31 @@ vreinterpret_f16_u16 (uint16x4_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f16_u32 (uint32x2_t __a)
+ {
+   return (float16x4_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_p8 (poly8x8_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_p16 (poly16x4_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_f16 (float16x4_t __a)
+ {
+   return (float32x2_t) __a;
+@@ -12722,56 +14605,65 @@ vreinterpret_f32_f16 (float16x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_p64 (poly64x1_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s64 (int64x1_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u64 (uint64x1_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s8 (int8x8_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s16 (int16x4_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_s32 (int32x2_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u8 (uint8x8_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u16 (uint16x4_t __a)
+ {
+   return (float32x2_t)__a;
+ }
+ 
+-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_f32_u32 (uint32x2_t __a)
+ {
+   return (float32x2_t)__a;
+@@ -12779,102 +14671,118 @@ vreinterpret_f32_u32 (uint32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_p8 (poly8x8_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_p16 (poly16x4_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_f16 (float16x4_t __a)
+ {
+   return (poly64x1_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_f32 (float32x2_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_s64 (int64x1_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_u64 (uint64x1_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_s8 (int8x8_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_s16 (int16x4_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_s32 (int32x2_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_u8 (uint8x8_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_u16 (uint16x4_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_p64_u32 (uint32x2_t __a)
+ {
+   return (poly64x1_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_p8 (poly8x8_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_p16 (poly16x4_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_f16 (float16x4_t __a)
+ {
+   return (int64x1_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_f32 (float32x2_t __a)
+ {
+   return (int64x1_t)__a;
+@@ -12882,76 +14790,88 @@ vreinterpret_s64_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_p64 (poly64x1_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u64 (uint64x1_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_s8 (int8x8_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_s16 (int16x4_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_s32 (int32x2_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u8 (uint8x8_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u16 (uint16x4_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s64_u32 (uint32x2_t __a)
+ {
+   return (int64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_p8 (poly8x8_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_p16 (poly16x4_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_f16 (float16x4_t __a)
+ {
+   return (uint64x1_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_f32 (float32x2_t __a)
+ {
+   return (uint64x1_t)__a;
+@@ -12959,76 +14879,88 @@ vreinterpret_u64_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_p64 (poly64x1_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s64 (int64x1_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s8 (int8x8_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s16 (int16x4_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_s32 (int32x2_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_u8 (uint8x8_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_u16 (uint16x4_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u64_u32 (uint32x2_t __a)
+ {
+   return (uint64x1_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_p8 (poly8x8_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_p16 (poly16x4_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_f16 (float16x4_t __a)
+ {
+   return (int8x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_f32 (float32x2_t __a)
+ {
+   return (int8x8_t)__a;
+@@ -13036,76 +14968,88 @@ vreinterpret_s8_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_p64 (poly64x1_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_s64 (int64x1_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u64 (uint64x1_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_s16 (int16x4_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_s32 (int32x2_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u8 (uint8x8_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u16 (uint16x4_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s8_u32 (uint32x2_t __a)
+ {
+   return (int8x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_p8 (poly8x8_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_p16 (poly16x4_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_f16 (float16x4_t __a)
+ {
+   return (int16x4_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_f32 (float32x2_t __a)
+ {
+   return (int16x4_t)__a;
+@@ -13113,76 +15057,88 @@ vreinterpret_s16_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_p64 (poly64x1_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_s64 (int64x1_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u64 (uint64x1_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_s8 (int8x8_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_s32 (int32x2_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u8 (uint8x8_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u16 (uint16x4_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s16_u32 (uint32x2_t __a)
+ {
+   return (int16x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_p8 (poly8x8_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_p16 (poly16x4_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_f16 (float16x4_t __a)
+ {
+   return (int32x2_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_f32 (float32x2_t __a)
+ {
+   return (int32x2_t)__a;
+@@ -13190,76 +15146,88 @@ vreinterpret_s32_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_p64 (poly64x1_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_s64 (int64x1_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u64 (uint64x1_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_s8 (int8x8_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_s16 (int16x4_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u8 (uint8x8_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u16 (uint16x4_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_s32_u32 (uint32x2_t __a)
+ {
+   return (int32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_p8 (poly8x8_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_p16 (poly16x4_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_f16 (float16x4_t __a)
+ {
+   return (uint8x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_f32 (float32x2_t __a)
+ {
+   return (uint8x8_t)__a;
+@@ -13267,76 +15235,88 @@ vreinterpret_u8_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_p64 (poly64x1_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s64 (int64x1_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_u64 (uint64x1_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s8 (int8x8_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s16 (int16x4_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_s32 (int32x2_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_u16 (uint16x4_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u8_u32 (uint32x2_t __a)
+ {
+   return (uint8x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_p8 (poly8x8_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_p16 (poly16x4_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_f16 (float16x4_t __a)
+ {
+   return (uint16x4_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_f32 (float32x2_t __a)
+ {
+   return (uint16x4_t)__a;
+@@ -13344,76 +15324,88 @@ vreinterpret_u16_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_p64 (poly64x1_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s64 (int64x1_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_u64 (uint64x1_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s8 (int8x8_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s16 (int16x4_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_s32 (int32x2_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_u8 (uint8x8_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u16_u32 (uint32x2_t __a)
+ {
+   return (uint16x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_p8 (poly8x8_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_p16 (poly16x4_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_f16 (float16x4_t __a)
+ {
+   return (uint32x2_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_f32 (float32x2_t __a)
+ {
+   return (uint32x2_t)__a;
+@@ -13421,70 +15413,81 @@ vreinterpret_u32_f32 (float32x2_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_p64 (poly64x1_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s64 (int64x1_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_u64 (uint64x1_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s8 (int8x8_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s16 (int16x4_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_s32 (int32x2_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_u8 (uint8x8_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpret_u32_u16 (uint16x4_t __a)
+ {
+   return (uint32x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_p16 (poly16x8_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_f16 (float16x8_t __a)
+ {
+   return (poly8x16_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_f32 (float32x4_t __a)
+ {
+   return (poly8x16_t)__a;
+@@ -13492,83 +15495,96 @@ vreinterpretq_p8_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_p64 (poly64x2_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_p128 (poly128_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s64 (int64x2_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u64 (uint64x2_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s8 (int8x16_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s16 (int16x8_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_s32 (int32x4_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u8 (uint8x16_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u16 (uint16x8_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p8_u32 (uint32x4_t __a)
+ {
+   return (poly8x16_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_p8 (poly8x16_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_f16 (float16x8_t __a)
+ {
+   return (poly16x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_f32 (float32x4_t __a)
+ {
+   return (poly16x8_t)__a;
+@@ -13576,69 +15592,80 @@ vreinterpretq_p16_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_p64 (poly64x2_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_p128 (poly128_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s64 (int64x2_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u64 (uint64x2_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s8 (int8x16_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s16 (int16x8_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_s32 (int32x4_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u8 (uint8x16_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u16 (uint16x8_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+-__extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p16_u32 (uint32x4_t __a)
+ {
+   return (poly16x8_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_p8 (poly8x16_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13646,7 +15673,8 @@ vreinterpretq_f16_p8 (poly8x16_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_p16 (poly16x8_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13654,7 +15682,8 @@ vreinterpretq_f16_p16 (poly16x8_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_f32 (float32x4_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13665,7 +15694,8 @@ vreinterpretq_f16_f32 (float32x4_t __a)
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_p64 (poly64x2_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13673,7 +15703,8 @@ vreinterpretq_f16_p64 (poly64x2_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_p128 (poly128_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13683,7 +15714,8 @@ vreinterpretq_f16_p128 (poly128_t __a)
+ #pragma GCC pop_options
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s64 (int64x2_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13691,7 +15723,8 @@ vreinterpretq_f16_s64 (int64x2_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u64 (uint64x2_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13699,7 +15732,8 @@ vreinterpretq_f16_u64 (uint64x2_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s8 (int8x16_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13707,7 +15741,8 @@ vreinterpretq_f16_s8 (int8x16_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s16 (int16x8_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13715,7 +15750,8 @@ vreinterpretq_f16_s16 (int16x8_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_s32 (int32x4_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13723,7 +15759,8 @@ vreinterpretq_f16_s32 (int32x4_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u8 (uint8x16_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13731,7 +15768,8 @@ vreinterpretq_f16_u8 (uint8x16_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u16 (uint16x8_t __a)
+ {
+   return (float16x8_t) __a;
+@@ -13739,27 +15777,31 @@ vreinterpretq_f16_u16 (uint16x8_t __a)
+ #endif
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f16_u32 (uint32x4_t __a)
+ {
+   return (float16x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_p8 (poly8x16_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_p16 (poly16x8_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_f16 (float16x8_t __a)
+ {
+   return (float32x4_t) __a;
+@@ -13768,62 +15810,72 @@ vreinterpretq_f32_f16 (float16x8_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_p64 (poly64x2_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_p128 (poly128_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s64 (int64x2_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u64 (uint64x2_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s8 (int8x16_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s16 (int16x8_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_s32 (int32x4_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u8 (uint8x16_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u16 (uint16x8_t __a)
+ {
+   return (float32x4_t)__a;
+ }
+ 
+-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline float32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_f32_u32 (uint32x4_t __a)
+ {
+   return (float32x4_t)__a;
+@@ -13831,188 +15883,218 @@ vreinterpretq_f32_u32 (uint32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_p8 (poly8x16_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_p16 (poly16x8_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_f16 (float16x8_t __a)
+ {
+   return (poly64x2_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_f32 (float32x4_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_p128 (poly128_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_s64 (int64x2_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_u64 (uint64x2_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_s8 (int8x16_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_s16 (int16x8_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_s32 (int32x4_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_u8 (uint8x16_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_u16 (uint16x8_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p64_u32 (uint32x4_t __a)
+ {
+   return (poly64x2_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_p8 (poly8x16_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_p16 (poly16x8_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_f16 (float16x8_t __a)
+ {
+   return (poly128_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_f32 (float32x4_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_p64 (poly64x2_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_s64 (int64x2_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_u64 (uint64x2_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_s8 (int8x16_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_s16 (int16x8_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_s32 (int32x4_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_u8 (uint8x16_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_u16 (uint16x8_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_p128_u32 (uint32x4_t __a)
+ {
+   return (poly128_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_p8 (poly8x16_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_p16 (poly16x8_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_f16 (float16x8_t __a)
+ {
+   return (int64x2_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_f32 (float32x4_t __a)
+ {
+   return (int64x2_t)__a;
+@@ -14020,82 +16102,95 @@ vreinterpretq_s64_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_p64 (poly64x2_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_p128 (poly128_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u64 (uint64x2_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_s8 (int8x16_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_s16 (int16x8_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_s32 (int32x4_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u8 (uint8x16_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u16 (uint16x8_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s64_u32 (uint32x4_t __a)
+ {
+   return (int64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_p8 (poly8x16_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_p16 (poly16x8_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_f16 (float16x8_t __a)
+ {
+   return (uint64x2_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_f32 (float32x4_t __a)
+ {
+   return (uint64x2_t)__a;
+@@ -14103,82 +16198,95 @@ vreinterpretq_u64_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_p64 (poly64x2_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_p128 (poly128_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s64 (int64x2_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s8 (int8x16_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s16 (int16x8_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_s32 (int32x4_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_u8 (uint8x16_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_u16 (uint16x8_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u64_u32 (uint32x4_t __a)
+ {
+   return (uint64x2_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_p8 (poly8x16_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_p16 (poly16x8_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_f16 (float16x8_t __a)
+ {
+   return (int8x16_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_f32 (float32x4_t __a)
+ {
+   return (int8x16_t)__a;
+@@ -14186,82 +16294,95 @@ vreinterpretq_s8_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_p64 (poly64x2_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_p128 (poly128_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_s64 (int64x2_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u64 (uint64x2_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_s16 (int16x8_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_s32 (int32x4_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u8 (uint8x16_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u16 (uint16x8_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s8_u32 (uint32x4_t __a)
+ {
+   return (int8x16_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_p8 (poly8x16_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_p16 (poly16x8_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_f16 (float16x8_t __a)
+ {
+   return (int16x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_f32 (float32x4_t __a)
+ {
+   return (int16x8_t)__a;
+@@ -14269,82 +16390,95 @@ vreinterpretq_s16_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_p64 (poly64x2_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_p128 (poly128_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_s64 (int64x2_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u64 (uint64x2_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_s8 (int8x16_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_s32 (int32x4_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u8 (uint8x16_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u16 (uint16x8_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s16_u32 (uint32x4_t __a)
+ {
+   return (int16x8_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_p8 (poly8x16_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_p16 (poly16x8_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_f16 (float16x8_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ #endif
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_f32 (float32x4_t __a)
+ {
+   return (int32x4_t)__a;
+@@ -14352,82 +16486,95 @@ vreinterpretq_s32_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_p64 (poly64x2_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_p128 (poly128_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_s64 (int64x2_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u64 (uint64x2_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_s8 (int8x16_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_s16 (int16x8_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u8 (uint8x16_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u16 (uint16x8_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline int32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_s32_u32 (uint32x4_t __a)
+ {
+   return (int32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_p8 (poly8x16_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_p16 (poly16x8_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_f16 (float16x8_t __a)
+ {
+   return (uint8x16_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_f32 (float32x4_t __a)
+ {
+   return (uint8x16_t)__a;
+@@ -14435,82 +16582,95 @@ vreinterpretq_u8_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_p64 (poly64x2_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_p128 (poly128_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s64 (int64x2_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_u64 (uint64x2_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s8 (int8x16_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s16 (int16x8_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_s32 (int32x4_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_u16 (uint16x8_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u8_u32 (uint32x4_t __a)
+ {
+   return (uint8x16_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_p8 (poly8x16_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_p16 (poly16x8_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_f16 (float16x8_t __a)
+ {
+   return (uint16x8_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_f32 (float32x4_t __a)
+ {
+   return (uint16x8_t)__a;
+@@ -14518,82 +16678,95 @@ vreinterpretq_u16_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_p64 (poly64x2_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_p128 (poly128_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s64 (int64x2_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_u64 (uint64x2_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s8 (int8x16_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s16 (int16x8_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_s32 (int32x4_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_u8 (uint8x16_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u16_u32 (uint32x4_t __a)
+ {
+   return (uint16x8_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_p8 (poly8x16_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_p16 (poly16x8_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_f16 (float16x8_t __a)
+ {
+   return (uint32x4_t) __a;
+ }
+ #endif
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_f32 (float32x4_t __a)
+ {
+   return (uint32x4_t)__a;
+@@ -14601,56 +16774,65 @@ vreinterpretq_u32_f32 (float32x4_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_p64 (poly64x2_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_p128 (poly128_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+ #pragma GCC pop_options
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s64 (int64x2_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_u64 (uint64x2_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s8 (int8x16_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s16 (int16x8_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_s32 (int32x4_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_u8 (uint8x16_t __a)
+ {
+   return (uint32x4_t)__a;
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vreinterpretq_u32_u16 (uint16x8_t __a)
+ {
+   return (uint32x4_t)__a;
+@@ -14659,7 +16841,8 @@ vreinterpretq_u32_u16 (uint16x8_t __a)
+ 
+ #pragma GCC push_options
+ #pragma GCC target ("fpu=crypto-neon-fp-armv8")
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vldrq_p128 (poly128_t const * __ptr)
+ {
+ #ifdef __ARM_BIG_ENDIAN
+@@ -14672,7 +16855,8 @@ vldrq_p128 (poly128_t const * __ptr)
+ #endif
+ }
+ 
+-__extension__ static __inline void __attribute__ ((__always_inline__))
++__extension__ extern __inline void
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vstrq_p128 (poly128_t * __ptr, poly128_t __val)
+ {
+ #ifdef __ARM_BIG_ENDIAN
+@@ -14695,7 +16879,8 @@ vstrq_p128 (poly128_t * __ptr, poly128_t __val)
+    If the result is all zeroes for any half then the whole result is zeroes.
+    This is what the pairwise min reduction achieves.  */
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vceq_p64 (poly64x1_t __a, poly64x1_t __b)
+ {
+   uint32x2_t __t_a = vreinterpret_u32_p64 (__a);
+@@ -14710,7 +16895,8 @@ vceq_p64 (poly64x1_t __a, poly64x1_t __b)
+    a reduction with max since if any two corresponding bits
+    in the two poly64_t's match, then the whole result must be all ones.  */
+ 
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint64x1_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vtst_p64 (poly64x1_t __a, poly64x1_t __b)
+ {
+   uint32x2_t __t_a = vreinterpret_u32_p64 (__a);
+@@ -14720,31 +16906,36 @@ vtst_p64 (poly64x1_t __a, poly64x1_t __b)
+   return vreinterpret_u64_u32 (__m);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaeseq_u8 (uint8x16_t __data, uint8x16_t __key)
+ {
+   return __builtin_arm_crypto_aese (__data, __key);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaesdq_u8 (uint8x16_t __data, uint8x16_t __key)
+ {
+   return __builtin_arm_crypto_aesd (__data, __key);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaesmcq_u8 (uint8x16_t __data)
+ {
+   return __builtin_arm_crypto_aesmc (__data);
+ }
+ 
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint8x16_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vaesimcq_u8 (uint8x16_t __data)
+ {
+   return __builtin_arm_crypto_aesimc (__data);
+ }
+ 
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha1h_u32 (uint32_t __hash_e)
+ {
+   uint32x4_t __t = vdupq_n_u32 (0);
+@@ -14753,7 +16944,8 @@ vsha1h_u32 (uint32_t __hash_e)
+   return vgetq_lane_u32 (__t, 0);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha1cq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+ {
+   uint32x4_t __t = vdupq_n_u32 (0);
+@@ -14761,7 +16953,8 @@ vsha1cq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+   return __builtin_arm_crypto_sha1c (__hash_abcd, __t, __wk);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha1pq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+ {
+   uint32x4_t __t = vdupq_n_u32 (0);
+@@ -14769,7 +16962,8 @@ vsha1pq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+   return __builtin_arm_crypto_sha1p (__hash_abcd, __t, __wk);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha1mq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+ {
+   uint32x4_t __t = vdupq_n_u32 (0);
+@@ -14777,49 +16971,57 @@ vsha1mq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+   return __builtin_arm_crypto_sha1m (__hash_abcd, __t, __wk);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha1su0q_u32 (uint32x4_t __w0_3, uint32x4_t __w4_7, uint32x4_t __w8_11)
+ {
+   return __builtin_arm_crypto_sha1su0 (__w0_3, __w4_7, __w8_11);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha1su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w12_15)
+ {
+   return __builtin_arm_crypto_sha1su1 (__tw0_3, __w12_15);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha256hq_u32 (uint32x4_t __hash_abcd, uint32x4_t __hash_efgh, uint32x4_t __wk)
+ {
+   return __builtin_arm_crypto_sha256h (__hash_abcd, __hash_efgh, __wk);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha256h2q_u32 (uint32x4_t __hash_abcd, uint32x4_t __hash_efgh, uint32x4_t __wk)
+ {
+   return __builtin_arm_crypto_sha256h2 (__hash_abcd, __hash_efgh, __wk);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha256su0q_u32 (uint32x4_t __w0_3, uint32x4_t __w4_7)
+ {
+   return __builtin_arm_crypto_sha256su0 (__w0_3, __w4_7);
+ }
+ 
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
++__extension__ extern __inline uint32x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vsha256su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w8_11, uint32x4_t __w12_15)
+ {
+   return __builtin_arm_crypto_sha256su1 (__tw0_3, __w8_11, __w12_15);
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_p64 (poly64_t __a, poly64_t __b)
+ {
+   return (poly128_t) __builtin_arm_crypto_vmullp64 ((uint64_t) __a, (uint64_t) __b);
+ }
+ 
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
++__extension__ extern __inline poly128_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+ vmull_high_p64 (poly64x2_t __a, poly64x2_t __b)
+ {
+   poly64_t __t1 = vget_high_p64 (__a);
+@@ -14830,6 +17032,984 @@ vmull_high_p64 (poly64x2_t __a, poly64x2_t __b)
+ 
+ #pragma GCC pop_options
+ 
++  /* Intrinsics for FP16 instructions.  */
++#pragma GCC push_options
++#pragma GCC target ("fpu=neon-fp-armv8")
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vabd_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vabdv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vabdq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vabdv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vabs_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vabsv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vabsq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vabsv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vadd_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vaddv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vaddq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vaddv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcage_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcagev4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcageq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcagev8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcagt_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcagtv4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcagtq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcagtv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcale_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcalev4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcaleq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcalev8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcalt_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcaltv4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcaltq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcaltv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vceq_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vceqv4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vceqq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vceqv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vceqz_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vceqzv4hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vceqzq_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vceqzv8hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcge_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcgev4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgeq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcgev8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgez_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcgezv4hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgezq_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcgezv8hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgt_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcgtv4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcgtv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtz_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcgtzv4hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcgtzq_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcgtzv8hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcle_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vclev4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcleq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vclev8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vclez_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vclezv4hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vclezq_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vclezv8hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vclt_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return (uint16x4_t)__builtin_neon_vcltv4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcltq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return (uint16x8_t)__builtin_neon_vcltv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcltz_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcltzv4hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcltzq_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcltzv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f16_s16 (int16x4_t __a)
++{
++  return (float16x4_t)__builtin_neon_vcvtsv4hi (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_f16_u16 (uint16x4_t __a)
++{
++  return (float16x4_t)__builtin_neon_vcvtuv4hi ((int16x4_t)__a);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_s16_f16 (float16x4_t __a)
++{
++  return (int16x4_t)__builtin_neon_vcvtsv4hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_u16_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcvtuv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f16_s16 (int16x8_t __a)
++{
++  return (float16x8_t)__builtin_neon_vcvtsv8hi (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_f16_u16 (uint16x8_t __a)
++{
++  return (float16x8_t)__builtin_neon_vcvtuv8hi ((int16x8_t)__a);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_s16_f16 (float16x8_t __a)
++{
++  return (int16x8_t)__builtin_neon_vcvtsv8hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_u16_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcvtuv8hf (__a);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_s16_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vcvtasv4hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvta_u16_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcvtauv4hf (__a);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_s16_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vcvtasv8hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtaq_u16_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcvtauv8hf (__a);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_s16_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vcvtmsv4hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtm_u16_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcvtmuv4hf (__a);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_s16_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vcvtmsv8hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtmq_u16_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcvtmuv8hf (__a);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_s16_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vcvtnsv4hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtn_u16_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcvtnuv4hf (__a);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_s16_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vcvtnsv8hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtnq_u16_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcvtnuv8hf (__a);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_s16_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vcvtpsv4hf (__a);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtp_u16_f16 (float16x4_t __a)
++{
++  return (uint16x4_t)__builtin_neon_vcvtpuv4hf (__a);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_s16_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vcvtpsv8hf (__a);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtpq_u16_f16 (float16x8_t __a)
++{
++  return (uint16x8_t)__builtin_neon_vcvtpuv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f16_s16 (int16x4_t __a, const int __b)
++{
++  return __builtin_neon_vcvts_nv4hi (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_f16_u16 (uint16x4_t __a, const int __b)
++{
++  return __builtin_neon_vcvtu_nv4hi ((int16x4_t)__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f16_s16 (int16x8_t __a, const int __b)
++{
++  return __builtin_neon_vcvts_nv8hi (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_f16_u16 (uint16x8_t __a, const int __b)
++{
++  return __builtin_neon_vcvtu_nv8hi ((int16x8_t)__a, __b);
++}
++
++__extension__ extern __inline int16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_s16_f16 (float16x4_t __a, const int __b)
++{
++  return __builtin_neon_vcvts_nv4hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvt_n_u16_f16 (float16x4_t __a, const int __b)
++{
++  return (uint16x4_t)__builtin_neon_vcvtu_nv4hf (__a, __b);
++}
++
++__extension__ extern __inline int16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_s16_f16 (float16x8_t __a, const int __b)
++{
++  return __builtin_neon_vcvts_nv8hf (__a, __b);
++}
++
++__extension__ extern __inline uint16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vcvtq_n_u16_f16 (float16x8_t __a, const int __b)
++{
++  return (uint16x8_t)__builtin_neon_vcvtu_nv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vfma_f16 (float16x4_t __a, float16x4_t __b, float16x4_t __c)
++{
++  return __builtin_neon_vfmav4hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vfmaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
++{
++  return __builtin_neon_vfmav8hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vfms_f16 (float16x4_t __a, float16x4_t __b, float16x4_t __c)
++{
++  return __builtin_neon_vfmsv4hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vfmsq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
++{
++  return __builtin_neon_vfmsv8hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmax_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vmaxfv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vmaxfv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnm_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vmaxnmv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmaxnmq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vmaxnmv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmin_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vminfv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vminq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vminfv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vminnm_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vminnmv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vminnmq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vminnmv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vmulfv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_lane_f16 (float16x4_t __a, float16x4_t __b, const int __c)
++{
++  return __builtin_neon_vmul_lanev4hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmul_n_f16 (float16x4_t __a, float16_t __b)
++{
++  return __builtin_neon_vmul_nv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vmulfv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_lane_f16 (float16x8_t __a, float16x4_t __b, const int __c)
++{
++  return __builtin_neon_vmul_lanev8hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmulq_n_f16 (float16x8_t __a, float16_t __b)
++{
++  return __builtin_neon_vmul_nv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vneg_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vnegv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vnegq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vnegv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vpadd_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vpaddv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vpmax_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vpmaxfv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vpmin_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vpminfv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpe_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrecpev4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpeq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrecpev8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrnd_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrndv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrndv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrnda_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrndav4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndaq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrndav8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndm_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrndmv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndmq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrndmv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndn_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrndnv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndnq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrndnv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndp_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrndpv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndpq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrndpv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndx_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrndxv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrndxq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrndxv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrte_f16 (float16x4_t __a)
++{
++  return __builtin_neon_vrsqrtev4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrteq_f16 (float16x8_t __a)
++{
++  return __builtin_neon_vrsqrtev8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrecps_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vrecpsv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrecpsq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vrecpsv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrts_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vrsqrtsv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrsqrtsq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vrsqrtsv8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vsub_f16 (float16x4_t __a, float16x4_t __b)
++{
++  return __builtin_neon_vsubv4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vsubq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  return __builtin_neon_vsubv8hf (__a, __b);
++}
++
++#endif /* __ARM_FEATURE_VECTOR_FP16_ARITHMETIC.  */
++#pragma GCC pop_options
++
++  /* Half-precision data processing intrinsics.  */
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vbsl_f16 (uint16x4_t __a, float16x4_t __b, float16x4_t __c)
++{
++  return __builtin_neon_vbslv4hf ((int16x4_t)__a, __b, __c);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vbslq_f16 (uint16x8_t __a, float16x8_t __b, float16x8_t __c)
++{
++  return __builtin_neon_vbslv8hf ((int16x8_t)__a, __b, __c);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_n_f16 (float16_t __a)
++{
++  return __builtin_neon_vdup_nv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_n_f16 (float16_t __a)
++{
++  return __builtin_neon_vdup_nv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vdup_lane_f16 (float16x4_t __a, const int __b)
++{
++  return __builtin_neon_vdup_lanev4hf (__a, __b);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vdupq_lane_f16 (float16x4_t __a, const int __b)
++{
++  return __builtin_neon_vdup_lanev8hf (__a, __b);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vext_f16 (float16x4_t __a, float16x4_t __b, const int __c)
++{
++  return __builtin_neon_vextv4hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vextq_f16 (float16x8_t __a, float16x8_t __b, const int __c)
++{
++  return __builtin_neon_vextv8hf (__a, __b, __c);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmov_n_f16 (float16_t __a)
++{
++  return __builtin_neon_vdup_nv4hf (__a);
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vmovq_n_f16 (float16_t __a)
++{
++  return __builtin_neon_vdup_nv8hf (__a);
++}
++
++__extension__ extern __inline float16x4_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64_f16 (float16x4_t __a)
++{
++  return (float16x4_t)__builtin_shuffle (__a, (uint16x4_t){ 3, 2, 1, 0 });
++}
++
++__extension__ extern __inline float16x8_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vrev64q_f16 (float16x8_t __a)
++{
++  return
++    (float16x8_t)__builtin_shuffle (__a,
++				    (uint16x8_t){ 3, 2, 1, 0, 7, 6, 5, 4 });
++}
++
++__extension__ extern __inline float16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vtrn_f16 (float16x4_t __a, float16x4_t __b)
++{
++  float16x4x2_t __rv;
++#ifdef __ARM_BIG_ENDIAN
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x4_t){ 5, 1, 7, 3 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x4_t){ 4, 0, 6, 2 });
++#else
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x4_t){ 0, 4, 2, 6 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x4_t){ 1, 5, 3, 7 });
++#endif
++  return __rv;
++}
++
++__extension__ extern __inline float16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vtrnq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  float16x8x2_t __rv;
++#ifdef __ARM_BIG_ENDIAN
++  __rv.val[0] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 9, 1, 11, 3, 13, 5, 15, 7 });
++  __rv.val[1] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 8, 0, 10, 2, 12, 4, 14, 6 });
++#else
++  __rv.val[0] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 0, 8, 2, 10, 4, 12, 6, 14 });
++  __rv.val[1] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 1, 9, 3, 11, 5, 13, 7, 15 });
++#endif
++  return __rv;
++}
++
++__extension__ extern __inline float16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vuzp_f16 (float16x4_t __a, float16x4_t __b)
++{
++  float16x4x2_t __rv;
++#ifdef __ARM_BIG_ENDIAN
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x4_t){ 5, 7, 1, 3 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x4_t){ 4, 6, 0, 2 });
++#else
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x4_t){ 0, 2, 4, 6 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x4_t){ 1, 3, 5, 7 });
++#endif
++  return __rv;
++}
++
++__extension__ extern __inline float16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vuzpq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  float16x8x2_t __rv;
++#ifdef __ARM_BIG_ENDIAN
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
++				   { 5, 7, 1, 3, 13, 15, 9, 11 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x8_t)
++				   { 4, 6, 0, 2, 12, 14, 8, 10 });
++#else
++  __rv.val[0] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 0, 2, 4, 6, 8, 10, 12, 14 });
++  __rv.val[1] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 1, 3, 5, 7, 9, 11, 13, 15 });
++#endif
++  return __rv;
++}
++
++__extension__ extern __inline float16x4x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vzip_f16 (float16x4_t __a, float16x4_t __b)
++{
++  float16x4x2_t __rv;
++#ifdef __ARM_BIG_ENDIAN
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x4_t){ 6, 2, 7, 3 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x4_t){ 4, 0, 5, 1 });
++#else
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x4_t){ 0, 4, 1, 5 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x4_t){ 2, 6, 3, 7 });
++#endif
++  return __rv;
++}
++
++__extension__ extern __inline float16x8x2_t
++__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
++vzipq_f16 (float16x8_t __a, float16x8_t __b)
++{
++  float16x8x2_t __rv;
++#ifdef __ARM_BIG_ENDIAN
++  __rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
++				   { 10, 2, 11, 3, 8, 0, 9, 1 });
++  __rv.val[1] = __builtin_shuffle (__a, __b, (uint16x8_t)
++				   { 14, 6, 15, 7, 12, 4, 13, 5 });
++#else
++  __rv.val[0] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 0, 8, 1, 9, 2, 10, 3, 11 });
++  __rv.val[1] = __builtin_shuffle (__a, __b,
++				   (uint16x8_t){ 4, 12, 5, 13, 6, 14, 7, 15 });
++#endif
++  return __rv;
++}
++
++#endif
++
+ #ifdef __cplusplus
+ }
+ #endif
+--- a/src/gcc/config/arm/arm_neon_builtins.def
++++ b/src/gcc/config/arm/arm_neon_builtins.def
+@@ -19,6 +19,7 @@
+    <http://www.gnu.org/licenses/>.  */
+ 
+ VAR2 (BINOP, vadd, v2sf, v4sf)
++VAR2 (BINOP, vadd, v8hf, v4hf)
+ VAR3 (BINOP, vaddls, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vaddlu, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vaddws, v8qi, v4hi, v2si)
+@@ -32,12 +33,15 @@ VAR8 (BINOP, vqaddu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+ VAR3 (BINOP, vaddhn, v8hi, v4si, v2di)
+ VAR3 (BINOP, vraddhn, v8hi, v4si, v2di)
+ VAR2 (BINOP, vmulf, v2sf, v4sf)
++VAR2 (BINOP, vmulf, v8hf, v4hf)
+ VAR2 (BINOP, vmulp, v8qi, v16qi)
+ VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+ VAR3 (TERNOP, vmlals, v8qi, v4hi, v2si)
+ VAR3 (TERNOP, vmlalu, v8qi, v4hi, v2si)
+ VAR2 (TERNOP, vfma, v2sf, v4sf)
++VAR2 (TERNOP, vfma, v4hf, v8hf)
+ VAR2 (TERNOP, vfms, v2sf, v4sf)
++VAR2 (TERNOP, vfms, v4hf, v8hf)
+ VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+ VAR3 (TERNOP, vmlsls, v8qi, v4hi, v2si)
+ VAR3 (TERNOP, vmlslu, v8qi, v4hi, v2si)
+@@ -94,6 +98,7 @@ VAR8 (TERNOP_IMM, vsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+ VAR8 (TERNOP_IMM, vrsras_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+ VAR8 (TERNOP_IMM, vrsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+ VAR2 (BINOP, vsub, v2sf, v4sf)
++VAR2 (BINOP, vsub, v8hf, v4hf)
+ VAR3 (BINOP, vsubls, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vsublu, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vsubws, v8qi, v4hi, v2si)
+@@ -111,12 +116,27 @@ VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+ VAR6 (BINOP, vcgtu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR2 (BINOP, vcage, v2sf, v4sf)
+ VAR2 (BINOP, vcagt, v2sf, v4sf)
++VAR2 (BINOP, vcage, v4hf, v8hf)
++VAR2 (BINOP, vcagt, v4hf, v8hf)
++VAR2 (BINOP, vcale, v4hf, v8hf)
++VAR2 (BINOP, vcalt, v4hf, v8hf)
++VAR2 (BINOP, vceq, v4hf, v8hf)
++VAR2 (BINOP, vcge, v4hf, v8hf)
++VAR2 (BINOP, vcgt, v4hf, v8hf)
++VAR2 (BINOP, vcle, v4hf, v8hf)
++VAR2 (BINOP, vclt, v4hf, v8hf)
++VAR2 (UNOP, vceqz, v4hf, v8hf)
++VAR2 (UNOP, vcgez, v4hf, v8hf)
++VAR2 (UNOP, vcgtz, v4hf, v8hf)
++VAR2 (UNOP, vclez, v4hf, v8hf)
++VAR2 (UNOP, vcltz, v4hf, v8hf)
+ VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (BINOP, vabds, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (BINOP, vabdu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR2 (BINOP, vabdf, v2sf, v4sf)
+ VAR3 (BINOP, vabdls, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vabdlu, v8qi, v4hi, v2si)
++VAR2 (BINOP, vabd, v8hf, v4hf)
+ 
+ VAR6 (TERNOP, vabas, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (TERNOP, vabau, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+@@ -126,27 +146,38 @@ VAR3 (TERNOP, vabalu, v8qi, v4hi, v2si)
+ VAR6 (BINOP, vmaxs, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (BINOP, vmaxu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR2 (BINOP, vmaxf, v2sf, v4sf)
++VAR2 (BINOP, vmaxf, v8hf, v4hf)
++VAR4 (BINOP, vmaxnm, v2sf, v4sf, v4hf, v8hf)
+ VAR6 (BINOP, vmins, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (BINOP, vminu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR2 (BINOP, vminf, v2sf, v4sf)
++VAR2 (BINOP, vminf, v4hf, v8hf)
++VAR4 (BINOP, vminnm, v2sf, v4sf, v8hf, v4hf)
+ 
+ VAR3 (BINOP, vpmaxs, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vpmaxu, v8qi, v4hi, v2si)
+ VAR1 (BINOP, vpmaxf, v2sf)
++VAR1 (BINOP, vpmaxf, v4hf)
+ VAR3 (BINOP, vpmins, v8qi, v4hi, v2si)
+ VAR3 (BINOP, vpminu, v8qi, v4hi, v2si)
+ VAR1 (BINOP, vpminf, v2sf)
++VAR1 (BINOP, vpminf, v4hf)
+ 
+ VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf)
++VAR1 (BINOP, vpadd, v4hf)
+ VAR6 (UNOP, vpaddls, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (UNOP, vpaddlu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (BINOP, vpadals, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR6 (BINOP, vpadalu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR2 (BINOP, vrecps, v2sf, v4sf)
+ VAR2 (BINOP, vrsqrts, v2sf, v4sf)
++VAR2 (BINOP, vrecps, v4hf, v8hf)
++VAR2 (BINOP, vrsqrts, v4hf, v8hf)
+ VAR8 (TERNOP_IMM, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+ VAR8 (TERNOP_IMM, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di)
+ VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
++VAR2 (UNOP, vabs, v8hf, v4hf)
++VAR2 (UNOP, vneg, v8hf, v4hf)
+ VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+ VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+@@ -155,8 +186,16 @@ VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
+ VAR5 (BSWAP, bswap, v4hi, v8hi, v2si, v4si, v2di)
+ VAR2 (UNOP, vcnt, v8qi, v16qi)
+ VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf)
++VAR2 (UNOP, vrecpe, v8hf, v4hf)
+ VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf)
++VAR2 (UNOP, vrsqrte, v4hf, v8hf)
+ VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
++VAR2 (UNOP, vrnd, v8hf, v4hf)
++VAR2 (UNOP, vrnda, v8hf, v4hf)
++VAR2 (UNOP, vrndm, v8hf, v4hf)
++VAR2 (UNOP, vrndn, v8hf, v4hf)
++VAR2 (UNOP, vrndp, v8hf, v4hf)
++VAR2 (UNOP, vrndx, v8hf, v4hf)
+   /* FIXME: vget_lane supports more variants than this!  */
+ VAR10 (GETLANE, vget_lane,
+ 	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
+@@ -166,8 +205,10 @@ VAR10 (SETLANE, vset_lane,
+ VAR5 (UNOP, vcreate, v8qi, v4hi, v2si, v2sf, di)
+ VAR10 (UNOP, vdup_n,
+ 	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
++VAR2 (UNOP, vdup_n, v8hf, v4hf)
+ VAR10 (GETLANE, vdup_lane,
+ 	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
++VAR2 (GETLANE, vdup_lane, v8hf, v4hf)
+ VAR6 (COMBINE, vcombine, v8qi, v4hi, v4hf, v2si, v2sf, di)
+ VAR6 (UNOP, vget_high, v16qi, v8hi, v8hf, v4si, v4sf, v2di)
+ VAR6 (UNOP, vget_low, v16qi, v8hi, v8hf, v4si, v4sf, v2di)
+@@ -177,7 +218,7 @@ VAR3 (UNOP, vqmovnu, v8hi, v4si, v2di)
+ VAR3 (UNOP, vqmovun, v8hi, v4si, v2di)
+ VAR3 (UNOP, vmovls, v8qi, v4hi, v2si)
+ VAR3 (UNOP, vmovlu, v8qi, v4hi, v2si)
+-VAR6 (SETLANE, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
++VAR8 (SETLANE, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf, v4hf, v8hf)
+ VAR6 (MAC_LANE, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+ VAR2 (MAC_LANE, vmlals_lane, v4hi, v2si)
+ VAR2 (MAC_LANE, vmlalu_lane, v4hi, v2si)
+@@ -186,7 +227,7 @@ VAR6 (MAC_LANE, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+ VAR2 (MAC_LANE, vmlsls_lane, v4hi, v2si)
+ VAR2 (MAC_LANE, vmlslu_lane, v4hi, v2si)
+ VAR2 (MAC_LANE, vqdmlsl_lane, v4hi, v2si)
+-VAR6 (BINOP, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
++VAR8 (BINOP, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf, v4hf, v8hf)
+ VAR6 (MAC_N, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf)
+ VAR2 (MAC_N, vmlals_n, v4hi, v2si)
+ VAR2 (MAC_N, vmlalu_n, v4hi, v2si)
+@@ -197,17 +238,27 @@ VAR2 (MAC_N, vmlslu_n, v4hi, v2si)
+ VAR2 (MAC_N, vqdmlsl_n, v4hi, v2si)
+ VAR10 (SETLANE, vext,
+ 	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
++VAR2 (SETLANE, vext, v8hf, v4hf)
+ VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf)
+ VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi)
+ VAR2 (UNOP, vrev16, v8qi, v16qi)
+ VAR4 (UNOP, vcvts, v2si, v2sf, v4si, v4sf)
++VAR2 (UNOP, vcvts, v4hi, v8hi)
++VAR2 (UNOP, vcvts, v4hf, v8hf)
++VAR2 (UNOP, vcvtu, v4hi, v8hi)
++VAR2 (UNOP, vcvtu, v4hf, v8hf)
+ VAR4 (UNOP, vcvtu, v2si, v2sf, v4si, v4sf)
+ VAR4 (BINOP, vcvts_n, v2si, v2sf, v4si, v4sf)
+ VAR4 (BINOP, vcvtu_n, v2si, v2sf, v4si, v4sf)
++VAR2 (BINOP, vcvts_n, v4hf, v8hf)
++VAR2 (BINOP, vcvtu_n, v4hi, v8hi)
++VAR2 (BINOP, vcvts_n, v4hi, v8hi)
++VAR2 (BINOP, vcvtu_n, v4hf, v8hf)
+ VAR1 (UNOP, vcvtv4sf, v4hf)
+ VAR1 (UNOP, vcvtv4hf, v4sf)
+ VAR10 (TERNOP, vbsl,
+ 	 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
++VAR2 (TERNOP, vbsl, v8hf, v4hf)
+ VAR2 (UNOP, copysignf, v2sf, v4sf)
+ VAR2 (UNOP, vrintn, v2sf, v4sf)
+ VAR2 (UNOP, vrinta, v2sf, v4sf)
+@@ -219,6 +270,14 @@ VAR1 (UNOP, vcvtav2sf, v2si)
+ VAR1 (UNOP, vcvtav4sf, v4si)
+ VAR1 (UNOP, vcvtauv2sf, v2si)
+ VAR1 (UNOP, vcvtauv4sf, v4si)
++VAR2 (UNOP, vcvtas, v4hf, v8hf)
++VAR2 (UNOP, vcvtau, v4hf, v8hf)
++VAR2 (UNOP, vcvtms, v4hf, v8hf)
++VAR2 (UNOP, vcvtmu, v4hf, v8hf)
++VAR2 (UNOP, vcvtns, v4hf, v8hf)
++VAR2 (UNOP, vcvtnu, v4hf, v8hf)
++VAR2 (UNOP, vcvtps, v4hf, v8hf)
++VAR2 (UNOP, vcvtpu, v4hf, v8hf)
+ VAR1 (UNOP, vcvtpv2sf, v2si)
+ VAR1 (UNOP, vcvtpv4sf, v4si)
+ VAR1 (UNOP, vcvtpuv2sf, v2si)
+--- /dev/null
++++ b/src/gcc/config/arm/arm_vfp_builtins.def
+@@ -0,0 +1,51 @@
++/* VFP instruction builtin definitions.
++   Copyright (C) 2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with GCC; see the file COPYING3.  If not see
++   <http://www.gnu.org/licenses/>.  */
++
++/* This file lists the builtins that may be available when VFP is enabled but
++   not NEON is enabled.  The entries otherwise have the same requirements and
++   generate the same structures as those in the arm_neon_builtins.def.  */
++
++/* FP16 Arithmetic instructions.  */
++VAR1 (UNOP, vabs, hf)
++VAR2 (UNOP, vcvths, hf, si)
++VAR2 (UNOP, vcvthu, hf, si)
++VAR1 (UNOP, vcvtahs, si)
++VAR1 (UNOP, vcvtahu, si)
++VAR1 (UNOP, vcvtmhs, si)
++VAR1 (UNOP, vcvtmhu, si)
++VAR1 (UNOP, vcvtnhs, si)
++VAR1 (UNOP, vcvtnhu, si)
++VAR1 (UNOP, vcvtphs, si)
++VAR1 (UNOP, vcvtphu, si)
++VAR1 (UNOP, vrnd, hf)
++VAR1 (UNOP, vrnda, hf)
++VAR1 (UNOP, vrndi, hf)
++VAR1 (UNOP, vrndm, hf)
++VAR1 (UNOP, vrndn, hf)
++VAR1 (UNOP, vrndp, hf)
++VAR1 (UNOP, vrndx, hf)
++VAR1 (UNOP, vsqrt, hf)
++
++VAR2 (BINOP, vcvths_n, hf, si)
++VAR2 (BINOP, vcvthu_n, hf, si)
++VAR1 (BINOP, vmaxnm, hf)
++VAR1 (BINOP, vminnm, hf)
++
++VAR1 (TERNOP, vfma, hf)
++VAR1 (TERNOP, vfms, hf)
+--- a/src/gcc/config/arm/bpabi.h
++++ b/src/gcc/config/arm/bpabi.h
+@@ -75,6 +75,9 @@
+    |mcpu=cortex-a57.cortex-a53				\
+    |mcpu=cortex-a72					\
+    |mcpu=cortex-a72.cortex-a53				\
++   |mcpu=cortex-a73					\
++   |mcpu=cortex-a73.cortex-a35				\
++   |mcpu=cortex-a73.cortex-a53				\
+    |mcpu=exynos-m1                                      \
+    |mcpu=qdf24xx					\
+    |mcpu=xgene1                                         \
+@@ -90,6 +93,11 @@
+    |march=armv8-a+crc					\
+    |march=armv8.1-a					\
+    |march=armv8.1-a+crc					\
++   |march=armv8.2-a					\
++   |march=armv8.2-a+fp16				\
++   |march=armv8-m.base|mcpu=cortex-m23			\
++   |march=armv8-m.main					\
++   |march=armv8-m.main+dsp|mcpu=cortex-m33		\
+    :%{!r:--be8}}}"
+ #else
+ #define BE8_LINK_SPEC \
+@@ -105,6 +113,9 @@
+    |mcpu=cortex-a57.cortex-a53				\
+    |mcpu=cortex-a72					\
+    |mcpu=cortex-a72.cortex-a53				\
++   |mcpu=cortex-a73					\
++   |mcpu=cortex-a73.cortex-a35				\
++   |mcpu=cortex-a73.cortex-a53				\
+    |mcpu=exynos-m1                                      \
+    |mcpu=qdf24xx					\
+    |mcpu=xgene1                                         \
+@@ -121,6 +132,11 @@
+    |march=armv8-a+crc					\
+    |march=armv8.1-a					\
+    |march=armv8.1-a+crc					\
++   |march=armv8.2-a					\
++   |march=armv8.2-a+fp16				\
++   |march=armv8-m.base|mcpu=cortex-m23			\
++   |march=armv8-m.main					\
++   |march=armv8-m.main+dsp|mcpu=cortex-m33		\
+    :%{!r:--be8}}}"
+ #endif
+ 
+--- a/src/gcc/config/arm/constraints.md
++++ b/src/gcc/config/arm/constraints.md
+@@ -34,11 +34,13 @@
+ ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dp, Dz
+ ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
+ ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
++;; in all states: Pf
+ 
+ ;; The following memory constraints have been used:
+-;; in ARM/Thumb-2 state: Q, Uh, Ut, Uv, Uy, Un, Um, Us
++;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us
+ ;; in ARM state: Uq
+ ;; in Thumb state: Uu, Uw
++;; in all states: Q
+ 
+ 
+ (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
+@@ -66,7 +68,7 @@
+ 
+ (define_constraint "j"
+  "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
+- (and (match_test "TARGET_32BIT && arm_arch_thumb2")
++ (and (match_test "TARGET_HAVE_MOVT")
+       (ior (and (match_code "high")
+ 		(match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
+ 	   (and (match_code "const_int")
+@@ -180,6 +182,13 @@
+   (and (match_code "const_int")
+        (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
+ 
++(define_constraint "Pf"
++  "Memory models except relaxed, consume or release ones."
++  (and (match_code "const_int")
++       (match_test "!is_mm_relaxed (memmodel_from_int (ival))
++		    && !is_mm_consume (memmodel_from_int (ival))
++		    && !is_mm_release (memmodel_from_int (ival))")))
++
+ (define_constraint "Ps"
+   "@internal In Thumb-2 state a constant in the range -255 to +255"
+   (and (match_code "const_int")
+@@ -333,13 +342,13 @@
+  "@internal
+   In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
+   (and (match_code "const_double")
+-       (match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))
++       (match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))
+ 
+ (define_constraint "Dp"
+  "@internal
+   In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
+   (and (match_code "const_double")
+-       (match_test "TARGET_32BIT && TARGET_VFP
++       (match_test "TARGET_32BIT
+ 		    && vfp3_const_double_for_bits (op) > 0")))
+ 
+ (define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
+@@ -407,7 +416,7 @@
+ 
+ (define_memory_constraint "Q"
+  "@internal
+-  In ARM/Thumb-2 state an address that is a single base register."
++  An address that is a single base register."
+  (and (match_code "mem")
+       (match_test "REG_P (XEXP (op, 0))")))
+ 
+--- a/src/gcc/config/arm/cortex-a53.md
++++ b/src/gcc/config/arm/cortex-a53.md
+@@ -30,6 +30,7 @@
+ 
+ (define_cpu_unit "cortex_a53_slot0" "cortex_a53")
+ (define_cpu_unit "cortex_a53_slot1" "cortex_a53")
++(final_presence_set "cortex_a53_slot1" "cortex_a53_slot0")
+ 
+ (define_reservation "cortex_a53_slot_any"
+ 		    "cortex_a53_slot0\
+@@ -71,41 +72,43 @@
+ 
+ (define_insn_reservation "cortex_a53_shift" 2
+   (and (eq_attr "tune" "cortexa53")
+-       (eq_attr "type" "adr,shift_imm,shift_reg,mov_imm,mvn_imm"))
++       (eq_attr "type" "adr,shift_imm,mov_imm,mvn_imm,mov_shift"))
+   "cortex_a53_slot_any")
+ 
+-(define_insn_reservation "cortex_a53_alu_rotate_imm" 2
++(define_insn_reservation "cortex_a53_shift_reg" 2
+   (and (eq_attr "tune" "cortexa53")
+-       (eq_attr "type" "rotate_imm"))
+-  "(cortex_a53_slot1)
+-   | (cortex_a53_single_issue)")
++       (eq_attr "type" "shift_reg,mov_shift_reg"))
++  "cortex_a53_slot_any+cortex_a53_hazard")
+ 
+ (define_insn_reservation "cortex_a53_alu" 3
+   (and (eq_attr "tune" "cortexa53")
+        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,
+ 			alu_sreg,alus_sreg,logic_reg,logics_reg,
+ 			adc_imm,adcs_imm,adc_reg,adcs_reg,
+-			bfm,csel,clz,rbit,rev,alu_dsp_reg,
+-			mov_reg,mvn_reg,
+-			mrs,multiple,no_insn"))
++			csel,clz,rbit,rev,alu_dsp_reg,
++			mov_reg,mvn_reg,mrs,multiple,no_insn"))
+   "cortex_a53_slot_any")
+ 
+ (define_insn_reservation "cortex_a53_alu_shift" 3
+   (and (eq_attr "tune" "cortexa53")
+        (eq_attr "type" "alu_shift_imm,alus_shift_imm,
+ 			crc,logic_shift_imm,logics_shift_imm,
+-			alu_ext,alus_ext,
+-			extend,mov_shift,mvn_shift"))
++			alu_ext,alus_ext,bfm,bfx,extend,mvn_shift"))
+   "cortex_a53_slot_any")
+ 
+ (define_insn_reservation "cortex_a53_alu_shift_reg" 3
+   (and (eq_attr "tune" "cortexa53")
+        (eq_attr "type" "alu_shift_reg,alus_shift_reg,
+ 			logic_shift_reg,logics_shift_reg,
+-			mov_shift_reg,mvn_shift_reg"))
++			mvn_shift_reg"))
+   "cortex_a53_slot_any+cortex_a53_hazard")
+ 
+-(define_insn_reservation "cortex_a53_mul" 3
++(define_insn_reservation "cortex_a53_alu_extr" 3
++  (and (eq_attr "tune" "cortexa53")
++       (eq_attr "type" "rotate_imm"))
++  "cortex_a53_slot1|cortex_a53_single_issue")
++
++(define_insn_reservation "cortex_a53_mul" 4
+   (and (eq_attr "tune" "cortexa53")
+        (ior (eq_attr "mul32" "yes")
+ 	    (eq_attr "mul64" "yes")))
+@@ -189,49 +192,43 @@
+ (define_insn_reservation "cortex_a53_branch" 0
+   (and (eq_attr "tune" "cortexa53")
+        (eq_attr "type" "branch,call"))
+-  "cortex_a53_slot_any,cortex_a53_branch")
++  "cortex_a53_slot_any+cortex_a53_branch")
+ 
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ;; General-purpose register bypasses
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ 
+-;; Model bypasses for unshifted operands to ALU instructions.
++;; Model bypasses for ALU to ALU instructions.
+ 
+-(define_bypass 1 "cortex_a53_shift"
+-		 "cortex_a53_shift")
++(define_bypass 0 "cortex_a53_shift*"
++		 "cortex_a53_alu")
++
++(define_bypass 1 "cortex_a53_shift*"
++		 "cortex_a53_shift*,cortex_a53_alu_*")
+ 
+-(define_bypass 1 "cortex_a53_alu,
+-		  cortex_a53_alu_shift*,
+-		  cortex_a53_alu_rotate_imm,
+-		  cortex_a53_shift"
++(define_bypass 1 "cortex_a53_alu*"
+ 		 "cortex_a53_alu")
+ 
+-(define_bypass 2 "cortex_a53_alu,
+-		  cortex_a53_alu_shift*"
++(define_bypass 1 "cortex_a53_alu*"
+ 		 "cortex_a53_alu_shift*"
+ 		 "aarch_forward_to_shift_is_not_shifted_reg")
+ 
+-;; In our model, we allow any general-purpose register operation to
+-;; bypass to the accumulator operand of an integer MADD-like operation.
++(define_bypass 2 "cortex_a53_alu*"
++		 "cortex_a53_alu_*,cortex_a53_shift*")
++
++;; Model a bypass from MUL/MLA to MLA instructions.
+ 
+-(define_bypass 1 "cortex_a53_alu*,
+-		  cortex_a53_load*,
+-		  cortex_a53_mul"
++(define_bypass 1 "cortex_a53_mul"
+ 		 "cortex_a53_mul"
+ 		 "aarch_accumulator_forwarding")
+ 
+-;; Model a bypass from MLA/MUL to many ALU instructions.
++;; Model a bypass from MUL/MLA to ALU instructions.
+ 
+ (define_bypass 2 "cortex_a53_mul"
+-		 "cortex_a53_alu,
+-		  cortex_a53_alu_shift*")
++		 "cortex_a53_alu")
+ 
+-;; We get neater schedules by allowing an MLA/MUL to feed an
+-;; early load address dependency to a load.
+-
+-(define_bypass 2 "cortex_a53_mul"
+-		 "cortex_a53_load*"
+-		 "arm_early_load_addr_dep")
++(define_bypass 3 "cortex_a53_mul"
++		 "cortex_a53_alu_*,cortex_a53_shift*")
+ 
+ ;; Model bypasses for loads which are to be consumed by the ALU.
+ 
+@@ -239,47 +236,56 @@
+ 		 "cortex_a53_alu")
+ 
+ (define_bypass 3 "cortex_a53_load1"
+-		 "cortex_a53_alu_shift*")
++		 "cortex_a53_alu_*,cortex_a53_shift*")
++
++(define_bypass 3 "cortex_a53_load2"
++		 "cortex_a53_alu")
+ 
+ ;; Model a bypass for ALU instructions feeding stores.
+ 
+-(define_bypass 1 "cortex_a53_alu*"
+-		 "cortex_a53_store1,
+-		  cortex_a53_store2,
+-		  cortex_a53_store3plus"
++(define_bypass 0 "cortex_a53_alu*,cortex_a53_shift*"
++		 "cortex_a53_store*"
+ 		 "arm_no_early_store_addr_dep")
+ 
+ ;; Model a bypass for load and multiply instructions feeding stores.
+ 
+-(define_bypass 2 "cortex_a53_mul,
+-		  cortex_a53_load1,
+-		  cortex_a53_load2,
+-		  cortex_a53_load3plus"
+-		 "cortex_a53_store1,
+-		  cortex_a53_store2,
+-		  cortex_a53_store3plus"
++(define_bypass 1 "cortex_a53_mul,
++		  cortex_a53_load*"
++		 "cortex_a53_store*"
+ 		 "arm_no_early_store_addr_dep")
+ 
++;; Model a bypass for load to load/store address.
++
++(define_bypass 3 "cortex_a53_load1"
++		 "cortex_a53_load*"
++		 "arm_early_load_addr_dep_ptr")
++
++(define_bypass 3 "cortex_a53_load1"
++		 "cortex_a53_store*"
++		 "arm_early_store_addr_dep_ptr")
++
+ ;; Model a GP->FP register move as similar to stores.
+ 
+-(define_bypass 1 "cortex_a53_alu*"
++(define_bypass 0 "cortex_a53_alu*,cortex_a53_shift*"
+ 		 "cortex_a53_r2f")
+ 
+-(define_bypass 2 "cortex_a53_mul,
++(define_bypass 1 "cortex_a53_mul,
+ 		  cortex_a53_load1,
+-		  cortex_a53_load2,
+-		  cortex_a53_load3plus"
++		  cortex_a53_load2"
+ 		 "cortex_a53_r2f")
+ 
+-;; Shifts feeding Load/Store addresses may not be ready in time.
++(define_bypass 2 "cortex_a53_alu*"
++		 "cortex_a53_r2f_cvt")
+ 
+-(define_bypass 3 "cortex_a53_shift"
+-		 "cortex_a53_load*"
+-		 "arm_early_load_addr_dep")
++(define_bypass 3 "cortex_a53_mul,
++		  cortex_a53_load1,
++		  cortex_a53_load2"
++		 "cortex_a53_r2f_cvt")
+ 
+-(define_bypass 3 "cortex_a53_shift"
+-		 "cortex_a53_store*"
+-		 "arm_early_store_addr_dep")
++;; Model flag forwarding to branches.
++
++(define_bypass 0 "cortex_a53_alu*,cortex_a53_shift*"
++		 "cortex_a53_branch")
+ 
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ;; Floating-point/Advanced SIMD.
+@@ -535,19 +541,25 @@
+ ;; Floating-point to/from core transfers.
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ 
+-(define_insn_reservation "cortex_a53_r2f" 6
++(define_insn_reservation "cortex_a53_r2f" 2
++  (and (eq_attr "tune" "cortexa53")
++       (eq_attr "type" "f_mcr,f_mcrr"))
++  "cortex_a53_slot_any,cortex_a53_fp_alu")
++
++(define_insn_reservation "cortex_a53_f2r" 4
+   (and (eq_attr "tune" "cortexa53")
+-       (eq_attr "type" "f_mcr,f_mcrr,f_cvti2f,
+-			neon_from_gp, neon_from_gp_q"))
+-  "cortex_a53_slot_any,cortex_a53_store,
+-   nothing,cortex_a53_fp_alu")
++       (eq_attr "type" "f_mrc,f_mrrc"))
++  "cortex_a53_slot_any,cortex_a53_fp_alu")
+ 
+-(define_insn_reservation "cortex_a53_f2r" 6
++(define_insn_reservation "cortex_a53_r2f_cvt" 4
+   (and (eq_attr "tune" "cortexa53")
+-       (eq_attr "type" "f_mrc,f_mrrc,f_cvtf2i,
+-			neon_to_gp, neon_to_gp_q"))
+-  "cortex_a53_slot_any,cortex_a53_fp_alu,
+-   nothing,cortex_a53_store")
++       (eq_attr "type" "f_cvti2f, neon_from_gp, neon_from_gp_q"))
++  "cortex_a53_slot_any,cortex_a53_fp_alu")
++
++(define_insn_reservation "cortex_a53_f2r_cvt" 5
++  (and (eq_attr "tune" "cortexa53")
++       (eq_attr "type" "f_cvtf2i, neon_to_gp, neon_to_gp_q"))
++  "cortex_a53_slot_any,cortex_a53_fp_alu")
+ 
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ;; Floating-point flag transfer.
+--- a/src/gcc/config/arm/cortex-a57.md
++++ b/src/gcc/config/arm/cortex-a57.md
+@@ -297,7 +297,7 @@
+        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ 			alu_sreg,alus_sreg,logic_reg,logics_reg,\
+ 			adc_imm,adcs_imm,adc_reg,adcs_reg,\
+-			adr,bfm,clz,rbit,rev,alu_dsp_reg,\
++			adr,bfx,extend,clz,rbit,rev,alu_dsp_reg,\
+ 			rotate_imm,shift_imm,shift_reg,\
+ 			mov_imm,mov_reg,\
+ 			mvn_imm,mvn_reg,\
+@@ -307,7 +307,7 @@
+ ;; ALU ops with immediate shift
+ (define_insn_reservation "cortex_a57_alu_shift" 3
+   (and (eq_attr "tune" "cortexa57")
+-       (eq_attr "type" "extend,\
++       (eq_attr "type" "bfm,\
+ 			alu_shift_imm,alus_shift_imm,\
+ 			crc,logic_shift_imm,logics_shift_imm,\
+ 			mov_shift,mvn_shift"))
+@@ -726,7 +726,7 @@
+ 
+ (define_insn_reservation "cortex_a57_fp_cpys" 4
+   (and (eq_attr "tune" "cortexa57")
+-       (eq_attr "type" "fmov"))
++       (eq_attr "type" "fmov,fcsel"))
+   "(ca57_cx1|ca57_cx2)")
+ 
+ (define_insn_reservation "cortex_a57_fp_divs" 12
+--- a/src/gcc/config/arm/cortex-a8-neon.md
++++ b/src/gcc/config/arm/cortex-a8-neon.md
+@@ -357,30 +357,34 @@
+        (eq_attr "type" "fmuls"))
+   "cortex_a8_vfp,cortex_a8_vfplite*11")
+ 
++;; Don't model a reservation for more than 15 cycles as this explodes the
++;; state space of the automaton for little gain.  It is unlikely that the
++;; scheduler will find enough instructions to hide the full latency of the
++;; instructions.
+ (define_insn_reservation "cortex_a8_vfp_muld" 17
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "type" "fmuld"))
+-  "cortex_a8_vfp,cortex_a8_vfplite*16")
++  "cortex_a8_vfp,cortex_a8_vfplite*15")
+ 
+ (define_insn_reservation "cortex_a8_vfp_macs" 21
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "type" "fmacs,ffmas"))
+-  "cortex_a8_vfp,cortex_a8_vfplite*20")
++  "cortex_a8_vfp,cortex_a8_vfplite*15")
+ 
+ (define_insn_reservation "cortex_a8_vfp_macd" 26
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "type" "fmacd,ffmad"))
+-  "cortex_a8_vfp,cortex_a8_vfplite*25")
++  "cortex_a8_vfp,cortex_a8_vfplite*15")
+ 
+ (define_insn_reservation "cortex_a8_vfp_divs" 37
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "type" "fdivs, fsqrts"))
+-  "cortex_a8_vfp,cortex_a8_vfplite*36")
++  "cortex_a8_vfp,cortex_a8_vfplite*15")
+ 
+ (define_insn_reservation "cortex_a8_vfp_divd" 65
+   (and (eq_attr "tune" "cortexa8")
+        (eq_attr "type" "fdivd, fsqrtd"))
+-  "cortex_a8_vfp,cortex_a8_vfplite*64")
++  "cortex_a8_vfp,cortex_a8_vfplite*15")
+ 
+ ;; Comparisons can actually take 7 cycles sometimes instead of four,
+ ;; but given all the other instructions lumped into type=ffarith that
+--- a/src/gcc/config/arm/crypto.md
++++ b/src/gcc/config/arm/crypto.md
+@@ -18,14 +18,27 @@
+ ;; along with GCC; see the file COPYING3.  If not see
+ ;; <http://www.gnu.org/licenses/>.
+ 
++
++;; When AES/AESMC fusion is enabled we want the register allocation to
++;; look like:
++;;    AESE Vn, _
++;;    AESMC Vn, Vn
++;; So prefer to tie operand 1 to operand 0 when fusing.
++
+ (define_insn "crypto_<crypto_pattern>"
+-  [(set (match_operand:<crypto_mode> 0 "register_operand" "=w")
++  [(set (match_operand:<crypto_mode> 0 "register_operand" "=w,w")
+         (unspec:<crypto_mode> [(match_operand:<crypto_mode> 1
+-                       "register_operand" "w")]
++                       "register_operand" "0,w")]
+          CRYPTO_UNARY))]
+   "TARGET_CRYPTO"
+   "<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q1"
+-  [(set_attr "type" "<crypto_type>")]
++  [(set_attr "type" "<crypto_type>")
++   (set_attr_alternative "enabled"
++     [(if_then_else (match_test
++		       "arm_fusion_enabled_p (tune_params::FUSE_AES_AESMC)")
++		     (const_string "yes" )
++		     (const_string "no"))
++      (const_string "yes")])]
+ )
+ 
+ (define_insn "crypto_<crypto_pattern>"
+--- a/src/gcc/config/arm/driver-arm.c
++++ b/src/gcc/config/arm/driver-arm.c
+@@ -46,6 +46,12 @@ static struct vendor_cpu arm_cpu_table[] = {
+     {"0xc0d", "armv7ve", "cortex-a12"},
+     {"0xc0e", "armv7ve", "cortex-a17"},
+     {"0xc0f", "armv7ve", "cortex-a15"},
++    {"0xd01", "armv8-a+crc", "cortex-a32"},
++    {"0xd04", "armv8-a+crc", "cortex-a35"},
++    {"0xd03", "armv8-a+crc", "cortex-a53"},
++    {"0xd07", "armv8-a+crc", "cortex-a57"},
++    {"0xd08", "armv8-a+crc", "cortex-a72"},
++    {"0xd09", "armv8-a+crc", "cortex-a73"},
+     {"0xc14", "armv7-r", "cortex-r4"},
+     {"0xc15", "armv7-r", "cortex-r5"},
+     {"0xc20", "armv6-m", "cortex-m0"},
+--- a/src/gcc/config/arm/elf.h
++++ b/src/gcc/config/arm/elf.h
+@@ -75,16 +75,7 @@
+ 
+ /* We might need a ARM specific header to function declarations.  */
+ #undef  ASM_DECLARE_FUNCTION_NAME
+-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)		\
+-  do								\
+-    {								\
+-      ARM_DECLARE_FUNCTION_NAME (FILE, NAME, DECL);		\
+-      ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function");	\
+-      ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));		\
+-      ASM_OUTPUT_LABEL(FILE, NAME);				\
+-      ARM_OUTPUT_FN_UNWIND (FILE, TRUE);			\
+-    }								\
+-  while (0)
++#define ASM_DECLARE_FUNCTION_NAME arm_asm_declare_function_name
+ 
+ /* We might need an ARM specific trailer for function declarations.  */
+ #undef  ASM_DECLARE_FUNCTION_SIZE
+@@ -104,7 +95,8 @@
+    the code more efficient, but for Thumb-1 it's better to put them out of
+    band unless we are generating compressed tables.  */
+ #define JUMP_TABLES_IN_TEXT_SECTION					\
+-   (TARGET_32BIT || (TARGET_THUMB && (optimize_size || flag_pic)))
++   ((TARGET_32BIT || (TARGET_THUMB && (optimize_size || flag_pic))) \
++    && !target_pure_code)
+ 
+ #ifndef LINK_SPEC
+ #define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X"
+@@ -148,8 +140,9 @@
+   while (0)
+ 
+ /* Horrible hack: We want to prevent some libgcc routines being included
+-   for some multilibs.  */
+-#ifndef __ARM_ARCH_6M__
++   for some multilibs.  The condition should match the one in
++   libgcc/config/arm/lib1funcs.S.  */
++#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1
+ #undef L_fixdfsi
+ #undef L_fixunsdfsi
+ #undef L_truncdfsf2
+--- a/src/gcc/config/arm/exynos-m1.md
++++ b/src/gcc/config/arm/exynos-m1.md
+@@ -358,7 +358,7 @@
+ 	    (eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\
+ 			     alu_sreg, alus_sreg, logic_reg, logics_reg,\
+ 			     adc_imm, adcs_imm, adc_reg, adcs_reg,\
+-			     adr, bfm, clz, rbit, rev, csel, alu_dsp_reg,\
++			     adr, bfm, bfx, clz, rbit, rev, csel, alu_dsp_reg,\
+ 			     shift_imm, shift_reg, rotate_imm, extend,\
+ 			     mov_imm, mov_reg,\
+ 			     mvn_imm, mvn_reg,\
+@@ -372,7 +372,7 @@
+ 	    (eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\
+ 			     alu_sreg, alus_sreg, logic_reg, logics_reg,\
+ 			     adc_imm, adcs_imm, adc_reg, adcs_reg,\
+-			     adr, bfm, clz, rbit, rev, alu_dsp_reg,\
++			     adr, bfm, bfx, clz, rbit, rev, alu_dsp_reg,\
+ 			     shift_imm, shift_reg, rotate_imm, extend,\
+ 			     mov_imm, mov_reg,\
+ 			     mvn_imm, mvn_reg,\
+--- a/src/gcc/config/arm/iterators.md
++++ b/src/gcc/config/arm/iterators.md
+@@ -46,7 +46,7 @@
+ (define_mode_iterator SIDI [SI DI])
+ 
+ ;; A list of modes which the VFP unit can handle
+-(define_mode_iterator SDF [(SF "TARGET_VFP") (DF "TARGET_VFP_DOUBLE")])
++(define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")])
+ 
+ ;; Integer element sizes implemented by IWMMXT.
+ (define_mode_iterator VMMX [V2SI V4HI V8QI])
+@@ -119,6 +119,10 @@
+ ;; All supported vector modes (except those with 64-bit integer elements).
+ (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
+ 
++;; All supported vector modes including 16-bit float modes.
++(define_mode_iterator VDQWH [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF
++			     V8HF V4HF])
++
+ ;; Supported integer vector modes (not 64 bit elements).
+ (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
+ 
+@@ -141,6 +145,9 @@
+ ;; Vector modes form int->float conversions.
+ (define_mode_iterator VCVTI [V2SI V4SI])
+ 
++;; Vector modes for int->half conversions.
++(define_mode_iterator VCVTHI [V4HI V8HI])
++
+ ;; Vector modes for doubleword multiply-accumulate, etc. insns.
+ (define_mode_iterator VMD [V4HI V2SI V2SF])
+ 
+@@ -174,6 +181,9 @@
+ ;; Modes with 8-bit, 16-bit and 32-bit elements.
+ (define_mode_iterator VU [V16QI V8HI V4SI])
+ 
++;; Vector modes for 16-bit floating-point support.
++(define_mode_iterator VH [V8HF V4HF])
++
+ ;; Iterators used for fixed-point support.
+ (define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA])
+ 
+@@ -192,14 +202,17 @@
+ ;; Code iterators
+ ;;----------------------------------------------------------------------------
+ 
+-;; A list of condition codes used in compare instructions where 
+-;; the carry flag from the addition is used instead of doing the 
++;; A list of condition codes used in compare instructions where
++;; the carry flag from the addition is used instead of doing the
+ ;; compare a second time.
+ (define_code_iterator LTUGEU [ltu geu])
+ 
+ ;; The signed gt, ge comparisons
+ (define_code_iterator GTGE [gt ge])
+ 
++;; The signed gt, ge, lt, le comparisons
++(define_code_iterator GLTE [gt ge lt le])
++
+ ;; The unsigned gt, ge comparisons
+ (define_code_iterator GTUGEU [gtu geu])
+ 
+@@ -228,6 +241,12 @@
+ ;; Binary operators whose second operand can be shifted.
+ (define_code_iterator SHIFTABLE_OPS [plus minus ior xor and])
+ 
++;; Operations on the sign of a number.
++(define_code_iterator ABSNEG [abs neg])
++
++;; Conversions.
++(define_code_iterator FCVT [unsigned_float float])
++
+ ;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows
+ ;; a stack pointer opoerand.  The minus operation is a candidate for an rsub
+ ;; and hence only plus is supported.
+@@ -251,10 +270,14 @@
+ (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM
+                             UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA])
+ 
+-(define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE UNSPEC_VCLT UNSPEC_VCLE])
++(define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE
++				UNSPEC_VCLT UNSPEC_VCLE])
+ 
+ (define_int_iterator NEON_VACMP [UNSPEC_VCAGE UNSPEC_VCAGT])
+ 
++(define_int_iterator NEON_VAGLTE [UNSPEC_VCAGE UNSPEC_VCAGT
++				  UNSPEC_VCALE UNSPEC_VCALT])
++
+ (define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA])
+ 
+ (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM
+@@ -323,6 +346,22 @@
+ 
+ (define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N])
+ 
++(define_int_iterator VCVT_HF_US_N [UNSPEC_VCVT_HF_S_N UNSPEC_VCVT_HF_U_N])
++
++(define_int_iterator VCVT_SI_US_N [UNSPEC_VCVT_SI_S_N UNSPEC_VCVT_SI_U_N])
++
++(define_int_iterator VCVT_HF_US [UNSPEC_VCVTA_S UNSPEC_VCVTA_U
++				 UNSPEC_VCVTM_S UNSPEC_VCVTM_U
++				 UNSPEC_VCVTN_S UNSPEC_VCVTN_U
++				 UNSPEC_VCVTP_S UNSPEC_VCVTP_U])
++
++(define_int_iterator VCVTH_US [UNSPEC_VCVTH_S UNSPEC_VCVTH_U])
++
++;; Operators for FP16 instructions.
++(define_int_iterator FP16_RND [UNSPEC_VRND UNSPEC_VRNDA
++			       UNSPEC_VRNDM UNSPEC_VRNDN
++			       UNSPEC_VRNDP UNSPEC_VRNDX])
++
+ (define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U])
+ 
+ (define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U])
+@@ -366,6 +405,8 @@
+ 
+ (define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH])
+ 
++(define_int_iterator VFM_LANE_AS [UNSPEC_VFMA_LANE UNSPEC_VFMS_LANE])
++
+ ;;----------------------------------------------------------------------------
+ ;; Mode attributes
+ ;;----------------------------------------------------------------------------
+@@ -384,6 +425,10 @@
+ (define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si")
+                            (V4SI "v4sf") (V4SF "v4si")])
+ 
++;; (Opposite) mode to convert to/from for vector-half mode conversions.
++(define_mode_attr VH_CVTTO [(V4HI "V4HF") (V4HF "V4HI")
++			    (V8HI "V8HF") (V8HF "V8HI")])
++
+ ;; Define element mode for each vector mode.
+ (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
+ 			  (V4HI "HI") (V8HI "HI")
+@@ -427,12 +472,13 @@
+ 
+ ;; Register width from element mode
+ (define_mode_attr V_reg [(V8QI "P") (V16QI "q")
+-                         (V4HI "P") (V8HI  "q")
+-                         (V4HF "P") (V8HF  "q")
+-                         (V2SI "P") (V4SI  "q")
+-                         (V2SF "P") (V4SF  "q")
+-                         (DI   "P") (V2DI  "q")
+-                         (SF   "")  (DF    "P")])
++			 (V4HI "P") (V8HI  "q")
++			 (V4HF "P") (V8HF  "q")
++			 (V2SI "P") (V4SI  "q")
++			 (V2SF "P") (V4SF  "q")
++			 (DI   "P") (V2DI  "q")
++			 (SF   "")  (DF    "P")
++			 (HF   "")])
+ 
+ ;; Wider modes with the same number of elements.
+ (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])
+@@ -448,7 +494,7 @@
+ (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
+ 			  (V8HF "V4HF") (V4SI  "V2SI")
+ 			  (V4SF "V2SF") (V2DF "DF")
+-                          (V2DI "DI")])
++			  (V2DI "DI") (V4HF "HF")])
+ 
+ ;; Same, but lower-case.
+ (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
+@@ -475,9 +521,10 @@
+ ;; Used for neon_vdup_lane, where the second operand is double-sized
+ ;; even when the first one is quad.
+ (define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
+-                                        (V4SI "V2SI") (V4SF "V2SF")
+-                                        (V8QI "V8QI") (V4HI "V4HI")
+-                                        (V2SI "V2SI") (V2SF "V2SF")])
++					(V4SI "V2SI") (V4SF "V2SF")
++					(V8QI "V8QI") (V4HI "V4HI")
++					(V2SI "V2SI") (V2SF "V2SF")
++					(V8HF "V4HF") (V4HF "V4HF")])
+ 
+ ;; Mode of result of comparison operations (and bit-select operand 1).
+ (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
+@@ -496,18 +543,22 @@
+ ;; Get element type from double-width mode, for operations where we 
+ ;; don't care about signedness.
+ (define_mode_attr V_if_elem [(V8QI "i8")  (V16QI "i8")
+-                 (V4HI "i16") (V8HI  "i16")
+-                             (V2SI "i32") (V4SI  "i32")
+-                             (DI   "i64") (V2DI  "i64")
+-                 (V2SF "f32") (V4SF  "f32")
+-                 (SF "f32") (DF "f64")])
++			     (V4HI "i16") (V8HI  "i16")
++			     (V2SI "i32") (V4SI  "i32")
++			     (DI   "i64") (V2DI  "i64")
++			     (V2SF "f32") (V4SF  "f32")
++			     (SF   "f32") (DF    "f64")
++			     (HF   "f16") (V4HF  "f16")
++			     (V8HF "f16")])
+ 
+ ;; Same, but for operations which work on signed values.
+ (define_mode_attr V_s_elem [(V8QI "s8")  (V16QI "s8")
+-                (V4HI "s16") (V8HI  "s16")
+-                            (V2SI "s32") (V4SI  "s32")
+-                            (DI   "s64") (V2DI  "s64")
+-                (V2SF "f32") (V4SF  "f32")])
++			    (V4HI "s16") (V8HI  "s16")
++			    (V2SI "s32") (V4SI  "s32")
++			    (DI   "s64") (V2DI  "s64")
++			    (V2SF "f32") (V4SF  "f32")
++			    (HF   "f16") (V4HF  "f16")
++			    (V8HF "f16")])
+ 
+ ;; Same, but for operations which work on unsigned values.
+ (define_mode_attr V_u_elem [(V8QI "u8")  (V16QI "u8")
+@@ -524,17 +575,22 @@
+                              (V2SF "32") (V4SF "32")])
+ 
+ (define_mode_attr V_sz_elem [(V8QI "8")  (V16QI "8")
+-                 (V4HI "16") (V8HI  "16")
+-                             (V2SI "32") (V4SI  "32")
+-                             (DI   "64") (V2DI  "64")
++			     (V4HI "16") (V8HI  "16")
++			     (V2SI "32") (V4SI  "32")
++			     (DI   "64") (V2DI  "64")
+ 			     (V4HF "16") (V8HF "16")
+-                 (V2SF "32") (V4SF  "32")])
++			     (V2SF "32") (V4SF  "32")])
+ 
+ (define_mode_attr V_elem_ch [(V8QI "b")  (V16QI "b")
+-                             (V4HI "h") (V8HI  "h")
+-                             (V2SI "s") (V4SI  "s")
+-                             (DI   "d") (V2DI  "d")
+-                             (V2SF "s") (V4SF  "s")])
++			     (V4HI "h") (V8HI  "h")
++			     (V2SI "s") (V4SI  "s")
++			     (DI   "d") (V2DI  "d")
++			     (V2SF "s") (V4SF  "s")
++			     (V2SF "s") (V4SF  "s")])
++
++(define_mode_attr VH_elem_ch [(V4HI "s") (V8HI  "s")
++			      (V4HF "s") (V8HF  "s")
++			      (HF "s")])
+ 
+ ;; Element sizes for duplicating ARM registers to all elements of a vector.
+ (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])
+@@ -570,29 +626,30 @@
+ ;; This mode attribute is used to obtain the correct register constraints.
+ 
+ (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
+-                                         (V8HI "x") (V4SI "t") (V4SF "t")])
++					 (V8HI "x") (V4SI "t") (V4SF "t")
++					 (V8HF "x") (V4HF "x")])
+ 
+ ;; Predicates used for setting type for neon instructions
+ 
+ (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
+-                 (V4HI "false") (V8HI "false")
+-                 (V2SI "false") (V4SI "false")
+-                 (V4HF "true") (V8HF "true")
+-                 (V2SF "true") (V4SF "true")
+-                 (DI "false") (V2DI "false")])
++				 (V4HI "false") (V8HI "false")
++				 (V2SI "false") (V4SI "false")
++				 (V4HF "true") (V8HF "true")
++				 (V2SF "true") (V4SF "true")
++				 (DI "false") (V2DI "false")])
+ 
+ (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
+-                   (V4HI "true") (V8HI "true")
+-                   (V2SI "false") (V4SI "false")
+-                   (V2SF "false") (V4SF "false")
+-                   (DI "false") (V2DI "false")])
+-
++				   (V4HI "true") (V8HI "true")
++				   (V2SI "false") (V4SI "false")
++				   (V2SF "false") (V4SF "false")
++				   (DI "false") (V2DI "false")])
+ 
+ (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
+-                            (V4HI "true") (V8HI  "false")
+-                            (V2SI "true") (V4SI  "false")
+-                            (V2SF "true") (V4SF  "false")
+-                            (DI   "true") (V2DI  "false")])
++			    (V4HI "true") (V8HI  "false")
++			    (V2SI "true") (V4SI  "false")
++			    (V2SF "true") (V4SF  "false")
++			    (DI   "true") (V2DI  "false")
++			    (V4HF "true") (V8HF  "false")])
+ 
+ (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
+ 				 (V4HF "4") (V8HF "8")
+@@ -637,12 +694,14 @@
+ 
+ ;; Mode attribute used to build the "type" attribute.
+ (define_mode_attr q [(V8QI "") (V16QI "_q")
+-                     (V4HI "") (V8HI "_q")
+-                     (V2SI "") (V4SI "_q")
++		     (V4HI "") (V8HI "_q")
++		     (V2SI "") (V4SI "_q")
++		     (V4HF "") (V8HF "_q")
++		     (V2SF "") (V4SF "_q")
+ 		     (V4HF "") (V8HF "_q")
+-                     (V2SF "") (V4SF "_q")
+-                     (DI "")   (V2DI "_q")
+-                     (DF "")   (V2DF "_q")])
++		     (DI "")   (V2DI "_q")
++		     (DF "")   (V2DF "_q")
++		     (HF "")])
+ 
+ (define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")])
+ 
+@@ -679,6 +738,16 @@
+ (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")])
+ (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")])
+ 
++;; String reprentations of operations on the sign of a number.
++(define_code_attr absneg_str [(abs "abs") (neg "neg")])
++
++;; Conversions.
++(define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
++
++(define_code_attr float_sup [(unsigned_float "u") (float "s")])
++
++(define_code_attr float_SUP [(unsigned_float "U") (float "S")])
++
+ ;;----------------------------------------------------------------------------
+ ;; Int attributes
+ ;;----------------------------------------------------------------------------
+@@ -710,7 +779,13 @@
+   (UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u")
+   (UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u")
+   (UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u")
++  (UNSPEC_VCVTA_S "s") (UNSPEC_VCVTA_U "u")
++  (UNSPEC_VCVTM_S "s") (UNSPEC_VCVTM_U "u")
++  (UNSPEC_VCVTN_S "s") (UNSPEC_VCVTN_U "u")
++  (UNSPEC_VCVTP_S "s") (UNSPEC_VCVTP_U "u")
+   (UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u")
++  (UNSPEC_VCVT_HF_S_N "s") (UNSPEC_VCVT_HF_U_N "u")
++  (UNSPEC_VCVT_SI_S_N "s") (UNSPEC_VCVT_SI_U_N "u")
+   (UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u")
+   (UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u")
+   (UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u")
+@@ -725,13 +800,30 @@
+   (UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u")
+   (UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u")
+   (UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u")
+-
++  (UNSPEC_VCVTH_S "s") (UNSPEC_VCVTH_U "u")
+ ])
+ 
++(define_int_attr vcvth_op
++ [(UNSPEC_VCVTA_S "a") (UNSPEC_VCVTA_U "a")
++  (UNSPEC_VCVTM_S "m") (UNSPEC_VCVTM_U "m")
++  (UNSPEC_VCVTN_S "n") (UNSPEC_VCVTN_U "n")
++  (UNSPEC_VCVTP_S "p") (UNSPEC_VCVTP_U "p")])
++
++(define_int_attr fp16_rnd_str
++  [(UNSPEC_VRND "rnd") (UNSPEC_VRNDA "rnda")
++   (UNSPEC_VRNDM "rndm") (UNSPEC_VRNDN "rndn")
++   (UNSPEC_VRNDP "rndp") (UNSPEC_VRNDX "rndx")])
++
++(define_int_attr fp16_rnd_insn
++  [(UNSPEC_VRND "vrintz") (UNSPEC_VRNDA "vrinta")
++   (UNSPEC_VRNDM "vrintm") (UNSPEC_VRNDN "vrintn")
++   (UNSPEC_VRNDP "vrintp") (UNSPEC_VRNDX "vrintx")])
++
+ (define_int_attr cmp_op_unsp [(UNSPEC_VCEQ "eq") (UNSPEC_VCGT "gt")
+-                              (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le")
+-                              (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge")
+-                              (UNSPEC_VCAGT "gt")])
++			      (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le")
++			      (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge")
++			      (UNSPEC_VCAGT "gt") (UNSPEC_VCALE "le")
++			      (UNSPEC_VCALT "lt")])
+ 
+ (define_int_attr r [
+   (UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r")
+@@ -847,3 +939,7 @@
+ 
+ ;; Attributes for VQRDMLAH/VQRDMLSH
+ (define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")])
++
++;; Attributes for VFMA_LANE/ VFMS_LANE
++(define_int_attr neon_vfm_lane_as
++ [(UNSPEC_VFMA_LANE "a") (UNSPEC_VFMS_LANE "s")])
+--- a/src/gcc/config/arm/neon-testgen.ml
++++ b/src//dev/null
+@@ -1,324 +0,0 @@
+-(* Auto-generate ARM Neon intrinsics tests.
+-   Copyright (C) 2006-2016 Free Software Foundation, Inc.
+-   Contributed by CodeSourcery.
+-
+-   This file is part of GCC.
+-
+-   GCC is free software; you can redistribute it and/or modify it under
+-   the terms of the GNU General Public License as published by the Free
+-   Software Foundation; either version 3, or (at your option) any later
+-   version.
+-
+-   GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+-   WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-   for more details.
+-
+-   You should have received a copy of the GNU General Public License
+-   along with GCC; see the file COPYING3.  If not see
+-   <http://www.gnu.org/licenses/>.
+-
+-   This is an O'Caml program.  The O'Caml compiler is available from:
+-
+-     http://caml.inria.fr/
+-
+-   Or from your favourite OS's friendly packaging system. Tested with version
+-   3.09.2, though other versions will probably work too.
+-
+-   Compile with:
+-     ocamlc -c neon.ml
+-     ocamlc -o neon-testgen neon.cmo neon-testgen.ml
+-
+-   Run with:
+-     cd /path/to/gcc/testsuite/gcc.target/arm/neon
+-     /path/to/neon-testgen
+-*)
+-
+-open Neon
+-
+-type c_type_flags = Pointer | Const
+-
+-(* Open a test source file.  *)
+-let open_test_file dir name =
+-  try
+-    open_out (dir ^ "/" ^ name ^ ".c")
+-  with Sys_error str ->
+-    failwith ("Could not create test source file " ^ name ^ ": " ^ str)
+-
+-(* Emit prologue code to a test source file.  *)
+-let emit_prologue chan test_name effective_target compile_test_optim =
+-  Printf.fprintf chan "/* Test the `%s' ARM Neon intrinsic.  */\n" test_name;
+-  Printf.fprintf chan "/* This file was autogenerated by neon-testgen.  */\n\n";
+-  Printf.fprintf chan "/* { dg-do assemble } */\n";
+-  Printf.fprintf chan "/* { dg-require-effective-target %s_ok } */\n"
+-                 effective_target;
+-  Printf.fprintf chan "/* { dg-options \"-save-temps %s\" } */\n" compile_test_optim;
+-  Printf.fprintf chan "/* { dg-add-options %s } */\n" effective_target;
+-  Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n"
+-
+-(* Emit declarations of variables that are going to be passed
+-   to an intrinsic, together with one to take a returned value if needed.  *)
+-let emit_variables chan c_types features spaces =
+-  let emit () =
+-    ignore (
+-      List.fold_left (fun arg_number -> fun (flags, ty) ->
+-                        let pointer_bit =
+-                          if List.mem Pointer flags then "*" else ""
+-                        in
+-                          (* Const arguments to builtins are directly
+-                             written in as constants.  *)
+-                          if not (List.mem Const flags) then
+-                            Printf.fprintf chan "%s%s %sarg%d_%s;\n"
+-                                           spaces ty pointer_bit arg_number ty;
+-                        arg_number + 1)
+-                     0 (List.tl c_types))
+-  in
+-    match c_types with
+-      (_, return_ty) :: tys ->
+-        if return_ty <> "void" then begin
+-          (* The intrinsic returns a value.  We need to do explicit register
+-             allocation for vget_low tests or they fail because of copy
+-             elimination.  *)
+-          ((if List.mem Fixed_vector_reg features then
+-              Printf.fprintf chan "%sregister %s out_%s asm (\"d18\");\n"
+-                             spaces return_ty return_ty
+-            else if List.mem Fixed_core_reg features then
+-              Printf.fprintf chan "%sregister %s out_%s asm (\"r0\");\n"
+-                             spaces return_ty return_ty
+-            else
+-              Printf.fprintf chan "%s%s out_%s;\n" spaces return_ty return_ty);
+-	   emit ())
+-        end else
+-          (* The intrinsic does not return a value.  *)
+-          emit ()
+-    | _ -> assert false
+-
+-(* Emit code to call an intrinsic.  *)
+-let emit_call chan const_valuator c_types name elt_ty =
+-  (if snd (List.hd c_types) <> "void" then
+-     Printf.fprintf chan "  out_%s = " (snd (List.hd c_types))
+-   else
+-     Printf.fprintf chan "  ");
+-  Printf.fprintf chan "%s_%s (" (intrinsic_name name) (string_of_elt elt_ty);
+-  let print_arg chan arg_number (flags, ty) =
+-    (* If the argument is of const type, then directly write in the
+-       constant now.  *)
+-    if List.mem Const flags then
+-      match const_valuator with
+-        None ->
+-          if List.mem Pointer flags then
+-            Printf.fprintf chan "0"
+-          else
+-            Printf.fprintf chan "1"
+-      | Some f -> Printf.fprintf chan "%s" (string_of_int (f arg_number))
+-    else
+-      Printf.fprintf chan "arg%d_%s" arg_number ty
+-  in
+-  let rec print_args arg_number tys =
+-    match tys with
+-      [] -> ()
+-    | [ty] -> print_arg chan arg_number ty
+-    | ty::tys ->
+-      print_arg chan arg_number ty;
+-      Printf.fprintf chan ", ";
+-      print_args (arg_number + 1) tys
+-  in
+-    print_args 0 (List.tl c_types);
+-    Printf.fprintf chan ");\n"
+-
+-(* Emit epilogue code to a test source file.  *)
+-let emit_epilogue chan features regexps =
+-  let no_op = List.exists (fun feature -> feature = No_op) features in
+-    Printf.fprintf chan "}\n\n";
+-    if not no_op then
+-      List.iter (fun regexp ->
+-                  Printf.fprintf chan
+-                    "/* { dg-final { scan-assembler \"%s\" } } */\n" regexp)
+-                regexps
+-    else
+-      ()
+-    
+-
+-(* Check a list of C types to determine which ones are pointers and which
+-   ones are const.  *)
+-let check_types tys =
+-  let tys' =
+-    List.map (fun ty ->
+-                let len = String.length ty in
+-                  if len > 2 && String.get ty (len - 2) = ' '
+-                             && String.get ty (len - 1) = '*'
+-                  then ([Pointer], String.sub ty 0 (len - 2))
+-                  else ([], ty)) tys
+-  in
+-    List.map (fun (flags, ty) ->
+-                if String.length ty > 6 && String.sub ty 0 6 = "const "
+-                then (Const :: flags, String.sub ty 6 ((String.length ty) - 6))
+-                else (flags, ty)) tys'
+-
+-(* Work out what the effective target should be.  *)
+-let effective_target features =
+-  try
+-    match List.find (fun feature ->
+-                       match feature with Requires_feature _ -> true
+-                                        | Requires_arch _ -> true
+-                                        | Requires_FP_bit 1 -> true
+-                                        | _ -> false)
+-                     features with
+-      Requires_feature "FMA" -> "arm_neonv2"
+-    | Requires_feature "CRYPTO" -> "arm_crypto"
+-    | Requires_arch 8 -> "arm_v8_neon"
+-    | Requires_FP_bit 1 -> "arm_neon_fp16"
+-    | _ -> assert false
+-  with Not_found -> "arm_neon"
+-
+-(* Work out what the testcase optimization level should be, default to -O0.  *)
+-let compile_test_optim features =
+-  try
+-    match List.find (fun feature ->
+-                       match feature with Compiler_optim _ -> true
+-                                        | _ -> false)
+-                     features with
+-      Compiler_optim opt -> opt
+-    | _ -> assert false
+-  with Not_found -> "-O0"
+-
+-(* Given an intrinsic shape, produce a regexp that will match
+-   the right-hand sides of instructions generated by an intrinsic of
+-   that shape.  *)
+-let rec analyze_shape shape =
+-  let rec n_things n thing =
+-    match n with
+-      0 -> []
+-    | n -> thing :: (n_things (n - 1) thing)
+-  in
+-  let rec analyze_shape_elt elt =
+-    match elt with
+-      Dreg -> "\\[dD\\]\\[0-9\\]+"
+-    | Qreg -> "\\[qQ\\]\\[0-9\\]+"
+-    | Corereg -> "\\[rR\\]\\[0-9\\]+"
+-    | Immed -> "#\\[0-9\\]+"
+-    | VecArray (1, elt) ->
+-        let elt_regexp = analyze_shape_elt elt in
+-          "((\\\\\\{" ^ elt_regexp ^ "\\\\\\})|(" ^ elt_regexp ^ "))"
+-    | VecArray (n, elt) ->
+-      let elt_regexp = analyze_shape_elt elt in
+-      let alt1 = elt_regexp ^ "-" ^ elt_regexp in
+-      let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in
+-        "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}"
+-    | (PtrTo elt | CstPtrTo elt) ->
+-      "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\(:\\[0-9\\]+\\)?\\\\\\]"
+-    | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
+-    | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
+-    | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]"
+-    | Alternatives (elts) -> "(" ^ (String.concat "|" (List.map analyze_shape_elt elts)) ^ ")"
+-  in
+-    match shape with
+-      All (n, elt) -> commas analyze_shape_elt (n_things n elt) ""
+-    | Long -> (analyze_shape_elt Qreg) ^ ", " ^ (analyze_shape_elt Dreg) ^
+-              ", " ^ (analyze_shape_elt Dreg)
+-    | Long_noreg elt -> (analyze_shape_elt elt) ^ ", " ^ (analyze_shape_elt elt)
+-    | Wide -> (analyze_shape_elt Qreg) ^ ", " ^ (analyze_shape_elt Qreg) ^
+-              ", " ^ (analyze_shape_elt Dreg)
+-    | Wide_noreg elt -> analyze_shape (Long_noreg elt)
+-    | Narrow -> (analyze_shape_elt Dreg) ^ ", " ^ (analyze_shape_elt Qreg) ^
+-                ", " ^ (analyze_shape_elt Qreg)
+-    | Use_operands elts -> commas analyze_shape_elt (Array.to_list elts) ""
+-    | By_scalar Dreg ->
+-        analyze_shape (Use_operands [| Dreg; Dreg; Element_of_dreg |])
+-    | By_scalar Qreg ->
+-        analyze_shape (Use_operands [| Qreg; Qreg; Element_of_dreg |])
+-    | By_scalar _ -> assert false
+-    | Wide_lane ->
+-        analyze_shape (Use_operands [| Qreg; Dreg; Element_of_dreg |])
+-    | Wide_scalar ->
+-        analyze_shape (Use_operands [| Qreg; Dreg; Element_of_dreg |])
+-    | Pair_result elt ->
+-      let elt_regexp = analyze_shape_elt elt in
+-        elt_regexp ^ ", " ^ elt_regexp
+-    | Unary_scalar _ -> "FIXME Unary_scalar"
+-    | Binary_imm elt -> analyze_shape (Use_operands [| elt; elt; Immed |])
+-    | Narrow_imm -> analyze_shape (Use_operands [| Dreg; Qreg; Immed |])
+-    | Long_imm -> analyze_shape (Use_operands [| Qreg; Dreg; Immed |])
+-
+-(* Generate tests for one intrinsic.  *)
+-let test_intrinsic dir opcode features shape name munge elt_ty =
+-  (* Open the test source file.  *)
+-  let test_name = name ^ (string_of_elt elt_ty) in
+-  let chan = open_test_file dir test_name in
+-  (* Work out what argument and return types the intrinsic has.  *)
+-  let c_arity, new_elt_ty = munge shape elt_ty in
+-  let c_types = check_types (strings_of_arity c_arity) in
+-  (* Extract any constant valuator (a function specifying what constant
+-     values are to be written into the intrinsic call) from the features
+-     list.  *)
+-  let const_valuator =
+-    try
+-      match (List.find (fun feature -> match feature with
+-                                         Const_valuator _ -> true
+-				       | _ -> false) features) with
+-        Const_valuator f -> Some f
+-      | _ -> assert false
+-    with Not_found -> None
+-  in
+-  (* Work out what instruction name(s) to expect.  *)
+-  let insns = get_insn_names features name in
+-  let no_suffix = (new_elt_ty = NoElts) in
+-  let insns =
+-    if no_suffix then insns
+-                 else List.map (fun insn ->
+-                                  let suffix = string_of_elt_dots new_elt_ty in
+-                                    insn ^ "\\." ^ suffix) insns
+-  in
+-  (* Construct a regexp to match against the expected instruction name(s).  *)
+-  let insn_regexp =
+-    match insns with
+-      [] -> assert false
+-    | [insn] -> insn
+-    | _ ->
+-      let rec calc_regexp insns cur_regexp =
+-        match insns with
+-          [] -> cur_regexp
+-        | [insn] -> cur_regexp ^ "(" ^ insn ^ "))"
+-        | insn::insns -> calc_regexp insns (cur_regexp ^ "(" ^ insn ^ ")|")
+-      in calc_regexp insns "("
+-  in
+-  (* Construct regexps to match against the instructions that this
+-     intrinsic expands to.  Watch out for any writeback character and
+-     comments after the instruction.  *)
+-  let regexps = List.map (fun regexp -> insn_regexp ^ "\\[ \t\\]+" ^ regexp ^
+-			  "!?\\(\\[ \t\\]+@\\[a-zA-Z0-9 \\]+\\)?\\n")
+-                         (analyze_all_shapes features shape analyze_shape)
+-  in
+-  let effective_target = effective_target features in
+-  let compile_test_optim = compile_test_optim features
+-  in
+-    (* Emit file and function prologues.  *)
+-    emit_prologue chan test_name effective_target compile_test_optim;
+-
+-    if (compare compile_test_optim "-O0") <> 0 then
+-        (* Emit variable declarations.  *)
+-        emit_variables chan c_types features "";
+-
+-    Printf.fprintf chan "void test_%s (void)\n{\n" test_name;
+-
+-    if compare compile_test_optim "-O0" = 0 then
+-        (* Emit variable declarations.  *)
+-        emit_variables chan c_types features "  ";
+-
+-    Printf.fprintf chan "\n";
+-    (* Emit the call to the intrinsic.  *)
+-    emit_call chan const_valuator c_types name elt_ty;
+-    (* Emit the function epilogue and the DejaGNU scan-assembler directives.  *)
+-    emit_epilogue chan features regexps;
+-    (* Close the test file.  *)
+-    close_out chan
+-
+-(* Generate tests for one element of the "ops" table.  *)
+-let test_intrinsic_group dir (opcode, features, shape, name, munge, types) =
+-  List.iter (test_intrinsic dir opcode features shape name munge) types
+-
+-(* Program entry point.  *)
+-let _ =
+-  let directory = if Array.length Sys.argv <> 1 then Sys.argv.(1) else "." in
+-    List.iter (test_intrinsic_group directory) (reinterp @ reinterpq @ ops)
+-
+--- a/src/gcc/config/arm/neon.md
++++ b/src/gcc/config/arm/neon.md
+@@ -406,7 +406,7 @@
+    (match_operand:SI 2 "immediate_operand" "")]
+   "TARGET_NEON"
+ {
+-  HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
++  HOST_WIDE_INT elem = HOST_WIDE_INT_1 << INTVAL (operands[2]);
+   emit_insn (gen_vec_set<mode>_internal (operands[0], operands[1],
+ 					 GEN_INT (elem), operands[0]));
+   DONE;
+@@ -505,6 +505,20 @@
+                     (const_string "neon_add<q>")))]
+ )
+ 
++(define_insn "add<mode>3_fp16"
++  [(set
++    (match_operand:VH 0 "s_register_operand" "=w")
++    (plus:VH
++     (match_operand:VH 1 "s_register_operand" "w")
++     (match_operand:VH 2 "s_register_operand" "w")))]
++ "TARGET_NEON_FP16INST"
++ "vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set (attr "type")
++   (if_then_else (match_test "<Is_float_mode>")
++    (const_string "neon_fp_addsub_s<q>")
++    (const_string "neon_add<q>")))]
++)
++
+ (define_insn "adddi3_neon"
+   [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?w,?&r,?&r,?&r")
+         (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,w,r,0,r")
+@@ -543,6 +557,17 @@
+                     (const_string "neon_sub<q>")))]
+ )
+ 
++(define_insn "sub<mode>3_fp16"
++ [(set
++   (match_operand:VH 0 "s_register_operand" "=w")
++   (minus:VH
++    (match_operand:VH 1 "s_register_operand" "w")
++    (match_operand:VH 2 "s_register_operand" "w")))]
++ "TARGET_NEON_FP16INST"
++ "vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_sub<q>")]
++)
++
+ (define_insn "subdi3_neon"
+   [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r,?w")
+         (minus:DI (match_operand:DI 1 "s_register_operand" "w,0,r,0,w")
+@@ -591,6 +616,16 @@
+ 		    (const_string "neon_mla_<V_elem_ch><q>")))]
+ )
+ 
++(define_insn "mul<mode>3add<mode>_neon"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++	(plus:VH (mult:VH (match_operand:VH 2 "s_register_operand" "w")
++			  (match_operand:VH 3 "s_register_operand" "w"))
++		  (match_operand:VH 1 "s_register_operand" "0")))]
++  "TARGET_NEON_FP16INST && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
++  "vmla.f16\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
++  [(set_attr "type" "neon_fp_mla_s<q>")]
++)
++
+ (define_insn "mul<mode>3neg<mode>add<mode>_neon"
+   [(set (match_operand:VDQW 0 "s_register_operand" "=w")
+         (minus:VDQW (match_operand:VDQW 1 "s_register_operand" "0")
+@@ -629,6 +664,19 @@
+   [(set_attr "type" "neon_fp_mla_s<q>")]
+ )
+ 
++;; There is limited support for unsafe-math optimizations using the NEON FP16
++;; arithmetic instructions, so only the intrinsic is currently supported.
++(define_insn "fma<VH:mode>4_intrinsic"
++ [(set (match_operand:VH 0 "register_operand" "=w")
++   (fma:VH
++    (match_operand:VH 1 "register_operand" "w")
++    (match_operand:VH 2 "register_operand" "w")
++    (match_operand:VH 3 "register_operand" "0")))]
++ "TARGET_NEON_FP16INST"
++ "vfma.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_mla_s<q>")]
++)
++
+ (define_insn "*fmsub<VCVTF:mode>4"
+   [(set (match_operand:VCVTF 0 "register_operand" "=w")
+         (fma:VCVTF (neg:VCVTF (match_operand:VCVTF 1 "register_operand" "w"))
+@@ -640,13 +688,25 @@
+ )
+ 
+ (define_insn "fmsub<VCVTF:mode>4_intrinsic"
+-  [(set (match_operand:VCVTF 0 "register_operand" "=w")
+-        (fma:VCVTF (neg:VCVTF (match_operand:VCVTF 1 "register_operand" "w"))
+-		   (match_operand:VCVTF 2 "register_operand" "w")
+-		   (match_operand:VCVTF 3 "register_operand" "0")))]
+-  "TARGET_NEON && TARGET_FMA"
+-  "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+-  [(set_attr "type" "neon_fp_mla_s<q>")]
++ [(set (match_operand:VCVTF 0 "register_operand" "=w")
++   (fma:VCVTF
++    (neg:VCVTF (match_operand:VCVTF 1 "register_operand" "w"))
++    (match_operand:VCVTF 2 "register_operand" "w")
++    (match_operand:VCVTF 3 "register_operand" "0")))]
++ "TARGET_NEON && TARGET_FMA"
++ "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_mla_s<q>")]
++)
++
++(define_insn "fmsub<VH:mode>4_intrinsic"
++ [(set (match_operand:VH 0 "register_operand" "=w")
++   (fma:VH
++    (neg:VH (match_operand:VH 1 "register_operand" "w"))
++    (match_operand:VH 2 "register_operand" "w")
++    (match_operand:VH 3 "register_operand" "0")))]
++ "TARGET_NEON_FP16INST"
++ "vfms.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_mla_s<q>")]
+ )
+ 
+ (define_insn "neon_vrint<NEON_VRINT:nvrint_variant><VCVTF:mode>"
+@@ -860,6 +920,44 @@
+   ""
+ )
+ 
++(define_insn "<absneg_str><mode>2"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++    (ABSNEG:VH (match_operand:VH 1 "s_register_operand" "w")))]
++ "TARGET_NEON_FP16INST"
++ "v<absneg_str>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
++ [(set_attr "type" "neon_abs<q>")]
++)
++
++(define_expand "neon_v<absneg_str><mode>"
++ [(set
++   (match_operand:VH 0 "s_register_operand")
++   (ABSNEG:VH (match_operand:VH 1 "s_register_operand")))]
++ "TARGET_NEON_FP16INST"
++{
++  emit_insn (gen_<absneg_str><mode>2 (operands[0], operands[1]));
++  DONE;
++})
++
++(define_insn "neon_v<fp16_rnd_str><mode>"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++    (unspec:VH
++     [(match_operand:VH 1 "s_register_operand" "w")]
++     FP16_RND))]
++ "TARGET_NEON_FP16INST"
++ "<fp16_rnd_insn>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
++ [(set_attr "type" "neon_fp_round_s<q>")]
++)
++
++(define_insn "neon_vrsqrte<mode>"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++    (unspec:VH
++     [(match_operand:VH 1 "s_register_operand" "w")]
++     UNSPEC_VRSQRTE))]
++  "TARGET_NEON_FP16INST"
++  "vrsqrte.f16\t%<V_reg>0, %<V_reg>1"
++ [(set_attr "type" "neon_fp_rsqrte_s<q>")]
++)
++
+ (define_insn "*umin<mode>3_neon"
+   [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
+ 	(umin:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
+@@ -1208,16 +1306,135 @@
+ 
+ ;; Widening operations
+ 
++(define_expand "widen_ssum<mode>3"
++  [(set (match_operand:<V_double_width> 0 "s_register_operand" "")
++	(plus:<V_double_width>
++	 (sign_extend:<V_double_width>
++	  (match_operand:VQI 1 "s_register_operand" ""))
++	 (match_operand:<V_double_width> 2 "s_register_operand" "")))]
++  "TARGET_NEON"
++  {
++    machine_mode mode = GET_MODE (operands[1]);
++    rtx p1, p2;
++
++    p1  = arm_simd_vect_par_cnst_half (mode, false);
++    p2  = arm_simd_vect_par_cnst_half (mode, true);
++
++    if (operands[0] != operands[2])
++      emit_move_insn (operands[0], operands[2]);
++
++    emit_insn (gen_vec_sel_widen_ssum_lo<mode><V_half>3 (operands[0],
++							 operands[1],
++							 p1,
++							 operands[0]));
++    emit_insn (gen_vec_sel_widen_ssum_hi<mode><V_half>3 (operands[0],
++							 operands[1],
++							 p2,
++							 operands[0]));
++    DONE;
++  }
++)
++
++(define_insn "vec_sel_widen_ssum_lo<mode><V_half>3"
++  [(set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
++	(plus:<V_double_width>
++	 (sign_extend:<V_double_width>
++	  (vec_select:<V_HALF>
++	   (match_operand:VQI 1 "s_register_operand" "%w")
++	   (match_operand:VQI 2 "vect_par_constant_low" "")))
++	 (match_operand:<V_double_width> 3 "s_register_operand" "0")))]
++  "TARGET_NEON"
++{
++  return BYTES_BIG_ENDIAN ?  "vaddw.<V_s_elem>\t%q0, %q3, %f1" :
++    "vaddw.<V_s_elem>\t%q0, %q3, %e1";
++}
++  [(set_attr "type" "neon_add_widen")])
++
++(define_insn "vec_sel_widen_ssum_hi<mode><V_half>3"
++  [(set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
++	(plus:<V_double_width>
++	 (sign_extend:<V_double_width>
++	  (vec_select:<V_HALF>
++			 (match_operand:VQI 1 "s_register_operand" "%w")
++			 (match_operand:VQI 2 "vect_par_constant_high" "")))
++	 (match_operand:<V_double_width> 3 "s_register_operand" "0")))]
++  "TARGET_NEON"
++{
++  return BYTES_BIG_ENDIAN ?  "vaddw.<V_s_elem>\t%q0, %q3, %e1" :
++    "vaddw.<V_s_elem>\t%q0, %q3, %f1";
++}
++  [(set_attr "type" "neon_add_widen")])
++
+ (define_insn "widen_ssum<mode>3"
+   [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
+-	(plus:<V_widen> (sign_extend:<V_widen>
+-			  (match_operand:VW 1 "s_register_operand" "%w"))
+-		        (match_operand:<V_widen> 2 "s_register_operand" "w")))]
++	(plus:<V_widen>
++	 (sign_extend:<V_widen>
++	  (match_operand:VW 1 "s_register_operand" "%w"))
++	 (match_operand:<V_widen> 2 "s_register_operand" "w")))]
+   "TARGET_NEON"
+   "vaddw.<V_s_elem>\t%q0, %q2, %P1"
+   [(set_attr "type" "neon_add_widen")]
+ )
+ 
++(define_expand "widen_usum<mode>3"
++  [(set (match_operand:<V_double_width> 0 "s_register_operand" "")
++	(plus:<V_double_width>
++	 (zero_extend:<V_double_width>
++	  (match_operand:VQI 1 "s_register_operand" ""))
++	 (match_operand:<V_double_width> 2 "s_register_operand" "")))]
++  "TARGET_NEON"
++  {
++    machine_mode mode = GET_MODE (operands[1]);
++    rtx p1, p2;
++
++    p1  = arm_simd_vect_par_cnst_half (mode, false);
++    p2  = arm_simd_vect_par_cnst_half (mode, true);
++
++    if (operands[0] != operands[2])
++      emit_move_insn (operands[0], operands[2]);
++
++    emit_insn (gen_vec_sel_widen_usum_lo<mode><V_half>3 (operands[0],
++							 operands[1],
++							 p1,
++							 operands[0]));
++    emit_insn (gen_vec_sel_widen_usum_hi<mode><V_half>3 (operands[0],
++							 operands[1],
++							 p2,
++							 operands[0]));
++    DONE;
++  }
++)
++
++(define_insn "vec_sel_widen_usum_lo<mode><V_half>3"
++  [(set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
++	(plus:<V_double_width>
++	 (zero_extend:<V_double_width>
++	  (vec_select:<V_HALF>
++	   (match_operand:VQI 1 "s_register_operand" "%w")
++	   (match_operand:VQI 2 "vect_par_constant_low" "")))
++	 (match_operand:<V_double_width> 3 "s_register_operand" "0")))]
++  "TARGET_NEON"
++{
++  return BYTES_BIG_ENDIAN ?  "vaddw.<V_u_elem>\t%q0, %q3, %f1" :
++    "vaddw.<V_u_elem>\t%q0, %q3, %e1";
++}
++  [(set_attr "type" "neon_add_widen")])
++
++(define_insn "vec_sel_widen_usum_hi<mode><V_half>3"
++  [(set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
++	(plus:<V_double_width>
++	 (zero_extend:<V_double_width>
++	  (vec_select:<V_HALF>
++			 (match_operand:VQI 1 "s_register_operand" "%w")
++			 (match_operand:VQI 2 "vect_par_constant_high" "")))
++	 (match_operand:<V_double_width> 3 "s_register_operand" "0")))]
++  "TARGET_NEON"
++{
++ return BYTES_BIG_ENDIAN ?  "vaddw.<V_u_elem>\t%q0, %q3, %e1" :
++    "vaddw.<V_u_elem>\t%q0, %q3, %f1";
++}
++  [(set_attr "type" "neon_add_widen")])
++
+ (define_insn "widen_usum<mode>3"
+   [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
+ 	(plus:<V_widen> (zero_extend:<V_widen>
+@@ -1488,6 +1705,17 @@
+                     (const_string "neon_reduc_add<q>")))]
+ )
+ 
++(define_insn "neon_vpaddv4hf"
++ [(set
++   (match_operand:V4HF 0 "s_register_operand" "=w")
++   (unspec:V4HF [(match_operand:V4HF 1 "s_register_operand" "w")
++		 (match_operand:V4HF 2 "s_register_operand" "w")]
++    UNSPEC_VPADD))]
++ "TARGET_NEON_FP16INST"
++ "vpadd.f16\t%P0, %P1, %P2"
++ [(set_attr "type" "neon_reduc_add")]
++)
++
+ (define_insn "neon_vpsmin<mode>"
+   [(set (match_operand:VD 0 "s_register_operand" "=w")
+ 	(unspec:VD [(match_operand:VD 1 "s_register_operand" "w")
+@@ -1836,6 +2064,26 @@
+   DONE;
+ })
+ 
++(define_expand "neon_vadd<mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:VH 1 "s_register_operand")
++   (match_operand:VH 2 "s_register_operand")]
++  "TARGET_NEON_FP16INST"
++{
++  emit_insn (gen_add<mode>3_fp16 (operands[0], operands[1], operands[2]));
++  DONE;
++})
++
++(define_expand "neon_vsub<mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:VH 1 "s_register_operand")
++   (match_operand:VH 2 "s_register_operand")]
++  "TARGET_NEON_FP16INST"
++{
++  emit_insn (gen_sub<mode>3_fp16 (operands[0], operands[1], operands[2]));
++  DONE;
++})
++
+ ; Note that NEON operations don't support the full IEEE 754 standard: in
+ ; particular, denormal values are flushed to zero.  This means that GCC cannot
+ ; use those instructions for autovectorization, etc. unless
+@@ -1927,6 +2175,17 @@
+                     (const_string "neon_mul_<V_elem_ch><q>")))]
+ )
+ 
++(define_insn "neon_vmulf<mode>"
++ [(set
++   (match_operand:VH 0 "s_register_operand" "=w")
++   (mult:VH
++    (match_operand:VH 1 "s_register_operand" "w")
++    (match_operand:VH 2 "s_register_operand" "w")))]
++  "TARGET_NEON_FP16INST"
++  "vmul.f16\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_mul_<VH_elem_ch><q>")]
++)
++
+ (define_expand "neon_vmla<mode>"
+   [(match_operand:VDQW 0 "s_register_operand" "=w")
+    (match_operand:VDQW 1 "s_register_operand" "0")
+@@ -1955,6 +2214,18 @@
+   DONE;
+ })
+ 
++(define_expand "neon_vfma<VH:mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:VH 1 "s_register_operand")
++   (match_operand:VH 2 "s_register_operand")
++   (match_operand:VH 3 "s_register_operand")]
++  "TARGET_NEON_FP16INST"
++{
++  emit_insn (gen_fma<mode>4_intrinsic (operands[0], operands[2], operands[3],
++				       operands[1]));
++  DONE;
++})
++
+ (define_expand "neon_vfms<VCVTF:mode>"
+   [(match_operand:VCVTF 0 "s_register_operand")
+    (match_operand:VCVTF 1 "s_register_operand")
+@@ -1967,6 +2238,18 @@
+   DONE;
+ })
+ 
++(define_expand "neon_vfms<VH:mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:VH 1 "s_register_operand")
++   (match_operand:VH 2 "s_register_operand")
++   (match_operand:VH 3 "s_register_operand")]
++  "TARGET_NEON_FP16INST"
++{
++  emit_insn (gen_fmsub<mode>4_intrinsic (operands[0], operands[2], operands[3],
++					 operands[1]));
++  DONE;
++})
++
+ ; Used for intrinsics when flag_unsafe_math_optimizations is false.
+ 
+ (define_insn "neon_vmla<mode>_unspec"
+@@ -2267,6 +2550,72 @@
+   [(set_attr "type" "neon_fp_compare_s<q>")]
+ )
+ 
++(define_expand "neon_vc<cmp_op><mode>"
++ [(match_operand:<V_cmp_result> 0 "s_register_operand")
++  (neg:<V_cmp_result>
++   (COMPARISONS:VH
++    (match_operand:VH 1 "s_register_operand")
++    (match_operand:VH 2 "reg_or_zero_operand")))]
++ "TARGET_NEON_FP16INST"
++{
++  /* For FP comparisons use UNSPECS unless -funsafe-math-optimizations
++     are enabled.  */
++  if (GET_MODE_CLASS (<MODE>mode) == MODE_VECTOR_FLOAT
++      && !flag_unsafe_math_optimizations)
++    emit_insn
++      (gen_neon_vc<cmp_op><mode>_fp16insn_unspec
++       (operands[0], operands[1], operands[2]));
++  else
++    emit_insn
++      (gen_neon_vc<cmp_op><mode>_fp16insn
++       (operands[0], operands[1], operands[2]));
++  DONE;
++})
++
++(define_insn "neon_vc<cmp_op><mode>_fp16insn"
++ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
++   (neg:<V_cmp_result>
++    (COMPARISONS:<V_cmp_result>
++     (match_operand:VH 1 "s_register_operand" "w,w")
++     (match_operand:VH 2 "reg_or_zero_operand" "w,Dz"))))]
++ "TARGET_NEON_FP16INST
++  && !(GET_MODE_CLASS (<MODE>mode) == MODE_VECTOR_FLOAT
++  && !flag_unsafe_math_optimizations)"
++{
++  char pattern[100];
++  sprintf (pattern, "vc<cmp_op>.%s%%#<V_sz_elem>\t%%<V_reg>0,"
++	   " %%<V_reg>1, %s",
++	   GET_MODE_CLASS (<MODE>mode) == MODE_VECTOR_FLOAT
++	   ? "f" : "<cmp_type>",
++	   which_alternative == 0
++	   ? "%<V_reg>2" : "#0");
++  output_asm_insn (pattern, operands);
++  return "";
++}
++ [(set (attr "type")
++   (if_then_else (match_operand 2 "zero_operand")
++    (const_string "neon_compare_zero<q>")
++    (const_string "neon_compare<q>")))])
++
++(define_insn "neon_vc<cmp_op_unsp><mode>_fp16insn_unspec"
++ [(set
++   (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
++   (unspec:<V_cmp_result>
++    [(match_operand:VH 1 "s_register_operand" "w,w")
++     (match_operand:VH 2 "reg_or_zero_operand" "w,Dz")]
++    NEON_VCMP))]
++ "TARGET_NEON_FP16INST"
++{
++  char pattern[100];
++  sprintf (pattern, "vc<cmp_op_unsp>.f%%#<V_sz_elem>\t%%<V_reg>0,"
++	   " %%<V_reg>1, %s",
++	   which_alternative == 0
++	   ? "%<V_reg>2" : "#0");
++  output_asm_insn (pattern, operands);
++  return "";
++}
++ [(set_attr "type" "neon_fp_compare_s<q>")])
++
+ (define_insn "neon_vc<cmp_op>u<mode>"
+   [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
+         (neg:<V_cmp_result>
+@@ -2318,6 +2667,60 @@
+   [(set_attr "type" "neon_fp_compare_s<q>")]
+ )
+ 
++(define_expand "neon_vca<cmp_op><mode>"
++  [(set
++    (match_operand:<V_cmp_result> 0 "s_register_operand")
++    (neg:<V_cmp_result>
++     (GLTE:<V_cmp_result>
++      (abs:VH (match_operand:VH 1 "s_register_operand"))
++      (abs:VH (match_operand:VH 2 "s_register_operand")))))]
++ "TARGET_NEON_FP16INST"
++{
++  if (flag_unsafe_math_optimizations)
++    emit_insn (gen_neon_vca<cmp_op><mode>_fp16insn
++	       (operands[0], operands[1], operands[2]));
++  else
++    emit_insn (gen_neon_vca<cmp_op><mode>_fp16insn_unspec
++	       (operands[0], operands[1], operands[2]));
++  DONE;
++})
++
++(define_insn "neon_vca<cmp_op><mode>_fp16insn"
++  [(set
++    (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
++    (neg:<V_cmp_result>
++     (GLTE:<V_cmp_result>
++      (abs:VH (match_operand:VH 1 "s_register_operand" "w"))
++      (abs:VH (match_operand:VH 2 "s_register_operand" "w")))))]
++ "TARGET_NEON_FP16INST && flag_unsafe_math_optimizations"
++ "vac<cmp_op>.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_compare_s<q>")]
++)
++
++(define_insn "neon_vca<cmp_op_unsp><mode>_fp16insn_unspec"
++ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
++   (unspec:<V_cmp_result>
++    [(match_operand:VH 1 "s_register_operand" "w")
++     (match_operand:VH 2 "s_register_operand" "w")]
++    NEON_VAGLTE))]
++ "TARGET_NEON"
++ "vac<cmp_op_unsp>.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_compare_s<q>")]
++)
++
++(define_expand "neon_vc<cmp_op>z<mode>"
++ [(set
++   (match_operand:<V_cmp_result> 0 "s_register_operand")
++   (COMPARISONS:<V_cmp_result>
++    (match_operand:VH 1 "s_register_operand")
++    (const_int 0)))]
++ "TARGET_NEON_FP16INST"
++ {
++  emit_insn (gen_neon_vc<cmp_op><mode> (operands[0], operands[1],
++					CONST0_RTX (<MODE>mode)));
++  DONE;
++})
++
+ (define_insn "neon_vtst<mode>"
+   [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
+         (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
+@@ -2338,6 +2741,16 @@
+   [(set_attr "type" "neon_abd<q>")]
+ )
+ 
++(define_insn "neon_vabd<mode>"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++    (unspec:VH [(match_operand:VH 1 "s_register_operand" "w")
++		(match_operand:VH 2 "s_register_operand" "w")]
++     UNSPEC_VABD_F))]
++ "TARGET_NEON_FP16INST"
++ "vabd.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++  [(set_attr "type" "neon_abd<q>")]
++)
++
+ (define_insn "neon_vabdf<mode>"
+   [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
+         (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
+@@ -2400,6 +2813,51 @@
+   [(set_attr "type" "neon_fp_minmax_s<q>")]
+ )
+ 
++(define_insn "neon_v<maxmin>f<mode>"
++ [(set (match_operand:VH 0 "s_register_operand" "=w")
++   (unspec:VH
++    [(match_operand:VH 1 "s_register_operand" "w")
++     (match_operand:VH 2 "s_register_operand" "w")]
++    VMAXMINF))]
++ "TARGET_NEON_FP16INST"
++ "v<maxmin>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_minmax_s<q>")]
++)
++
++(define_insn "neon_vp<maxmin>fv4hf"
++ [(set (match_operand:V4HF 0 "s_register_operand" "=w")
++   (unspec:V4HF
++    [(match_operand:V4HF 1 "s_register_operand" "w")
++     (match_operand:V4HF 2 "s_register_operand" "w")]
++    VPMAXMINF))]
++ "TARGET_NEON_FP16INST"
++ "vp<maxmin>.f16\t%P0, %P1, %P2"
++  [(set_attr "type" "neon_reduc_minmax")]
++)
++
++(define_insn "neon_<fmaxmin_op><mode>"
++ [(set
++   (match_operand:VH 0 "s_register_operand" "=w")
++   (unspec:VH
++    [(match_operand:VH 1 "s_register_operand" "w")
++     (match_operand:VH 2 "s_register_operand" "w")]
++    VMAXMINFNM))]
++ "TARGET_NEON_FP16INST"
++ "<fmaxmin_op>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_minmax_s<q>")]
++)
++
++;; v<maxmin>nm intrinsics.
++(define_insn "neon_<fmaxmin_op><mode>"
++  [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
++	(unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
++		       (match_operand:VCVTF 2 "s_register_operand" "w")]
++		       VMAXMINFNM))]
++  "TARGET_NEON && TARGET_FPU_ARMV8"
++  "<fmaxmin_op>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++  [(set_attr "type" "neon_fp_minmax_s<q>")]
++)
++
+ ;; Vector forms for the IEEE-754 fmax()/fmin() functions
+ (define_insn "<fmaxmin><mode>3"
+   [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
+@@ -2471,6 +2929,17 @@
+   [(set_attr "type" "neon_fp_recps_s<q>")]
+ )
+ 
++(define_insn "neon_vrecps<mode>"
++  [(set
++    (match_operand:VH 0 "s_register_operand" "=w")
++    (unspec:VH [(match_operand:VH 1 "s_register_operand" "w")
++		(match_operand:VH 2 "s_register_operand" "w")]
++     UNSPEC_VRECPS))]
++  "TARGET_NEON_FP16INST"
++  "vrecps.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++  [(set_attr "type" "neon_fp_recps_s<q>")]
++)
++
+ (define_insn "neon_vrsqrts<mode>"
+   [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
+         (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
+@@ -2481,6 +2950,17 @@
+   [(set_attr "type" "neon_fp_rsqrts_s<q>")]
+ )
+ 
++(define_insn "neon_vrsqrts<mode>"
++  [(set
++    (match_operand:VH 0 "s_register_operand" "=w")
++    (unspec:VH [(match_operand:VH 1 "s_register_operand" "w")
++		 (match_operand:VH 2 "s_register_operand" "w")]
++     UNSPEC_VRSQRTS))]
++ "TARGET_NEON_FP16INST"
++ "vrsqrts.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
++ [(set_attr "type" "neon_fp_rsqrts_s<q>")]
++)
++
+ (define_expand "neon_vabs<mode>"
+   [(match_operand:VDQW 0 "s_register_operand" "")
+    (match_operand:VDQW 1 "s_register_operand" "")]
+@@ -2595,6 +3075,15 @@
+   DONE;
+ })
+ 
++(define_insn "neon_vrecpe<mode>"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++	(unspec:VH [(match_operand:VH 1 "s_register_operand" "w")]
++		   UNSPEC_VRECPE))]
++  "TARGET_NEON_FP16INST"
++  "vrecpe.f16\t%<V_reg>0, %<V_reg>1"
++  [(set_attr "type" "neon_fp_recpe_s<q>")]
++)
++
+ (define_insn "neon_vrecpe<mode>"
+   [(set (match_operand:V32 0 "s_register_operand" "=w")
+ 	(unspec:V32 [(match_operand:V32 1 "s_register_operand" "w")]
+@@ -2932,6 +3421,28 @@ if (BYTES_BIG_ENDIAN)
+   [(set_attr "type" "neon_dup<q>")]
+ )
+ 
++(define_insn "neon_vdup_lane<mode>_internal"
++ [(set (match_operand:VH 0 "s_register_operand" "=w")
++   (vec_duplicate:VH
++    (vec_select:<V_elem>
++     (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w")
++     (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
++ "TARGET_NEON && TARGET_FP16"
++{
++  if (BYTES_BIG_ENDIAN)
++    {
++      int elt = INTVAL (operands[2]);
++      elt = GET_MODE_NUNITS (<V_double_vector_mode>mode) - 1 - elt;
++      operands[2] = GEN_INT (elt);
++    }
++  if (<Is_d_reg>)
++    return "vdup.<V_sz_elem>\t%P0, %P1[%c2]";
++  else
++    return "vdup.<V_sz_elem>\t%q0, %P1[%c2]";
++}
++  [(set_attr "type" "neon_dup<q>")]
++)
++
+ (define_expand "neon_vdup_lane<mode>"
+   [(match_operand:VDQW 0 "s_register_operand" "=w")
+    (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w")
+@@ -2951,6 +3462,25 @@ if (BYTES_BIG_ENDIAN)
+     DONE;
+ })
+ 
++(define_expand "neon_vdup_lane<mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:<V_double_vector_mode> 1 "s_register_operand")
++   (match_operand:SI 2 "immediate_operand")]
++  "TARGET_NEON && TARGET_FP16"
++{
++  if (BYTES_BIG_ENDIAN)
++    {
++      unsigned int elt = INTVAL (operands[2]);
++      unsigned int reg_nelts
++	= 64 / GET_MODE_UNIT_BITSIZE (<V_double_vector_mode>mode);
++      elt ^= reg_nelts - 1;
++      operands[2] = GEN_INT (elt);
++    }
++  emit_insn (gen_neon_vdup_lane<mode>_internal (operands[0], operands[1],
++						operands[2]));
++  DONE;
++})
++
+ ; Scalar index is ignored, since only zero is valid here.
+ (define_expand "neon_vdup_lanedi"
+   [(match_operand:DI 0 "s_register_operand" "=w")
+@@ -3097,6 +3627,28 @@ if (BYTES_BIG_ENDIAN)
+   [(set_attr "type" "neon_fp_cvt_narrow_s_q")]
+ )
+ 
++(define_insn "neon_vcvt<sup><mode>"
++ [(set
++   (match_operand:<VH_CVTTO> 0 "s_register_operand" "=w")
++   (unspec:<VH_CVTTO>
++    [(match_operand:VCVTHI 1 "s_register_operand" "w")]
++    VCVT_US))]
++ "TARGET_NEON_FP16INST"
++ "vcvt.f16.<sup>%#16\t%<V_reg>0, %<V_reg>1"
++  [(set_attr "type" "neon_int_to_fp_<VH_elem_ch><q>")]
++)
++
++(define_insn "neon_vcvt<sup><mode>"
++ [(set
++   (match_operand:<VH_CVTTO> 0 "s_register_operand" "=w")
++   (unspec:<VH_CVTTO>
++    [(match_operand:VH 1 "s_register_operand" "w")]
++    VCVT_US))]
++ "TARGET_NEON_FP16INST"
++ "vcvt.<sup>%#16.f16\t%<V_reg>0, %<V_reg>1"
++  [(set_attr "type" "neon_fp_to_int_<VH_elem_ch><q>")]
++)
++
+ (define_insn "neon_vcvt<sup>_n<mode>"
+   [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
+ 	(unspec:<V_CVTTO> [(match_operand:VCVTF 1 "s_register_operand" "w")
+@@ -3110,6 +3662,20 @@ if (BYTES_BIG_ENDIAN)
+   [(set_attr "type" "neon_fp_to_int_<V_elem_ch><q>")]
+ )
+ 
++(define_insn "neon_vcvt<sup>_n<mode>"
++ [(set (match_operand:<VH_CVTTO> 0 "s_register_operand" "=w")
++   (unspec:<VH_CVTTO>
++    [(match_operand:VH 1 "s_register_operand" "w")
++     (match_operand:SI 2 "immediate_operand" "i")]
++    VCVT_US_N))]
++  "TARGET_NEON_FP16INST"
++{
++  neon_const_bounds (operands[2], 0, 17);
++  return "vcvt.<sup>%#16.f16\t%<V_reg>0, %<V_reg>1, %2";
++}
++ [(set_attr "type" "neon_fp_to_int_<VH_elem_ch><q>")]
++)
++
+ (define_insn "neon_vcvt<sup>_n<mode>"
+   [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
+ 	(unspec:<V_CVTTO> [(match_operand:VCVTI 1 "s_register_operand" "w")
+@@ -3123,6 +3689,31 @@ if (BYTES_BIG_ENDIAN)
+   [(set_attr "type" "neon_int_to_fp_<V_elem_ch><q>")]
+ )
+ 
++(define_insn "neon_vcvt<sup>_n<mode>"
++ [(set (match_operand:<VH_CVTTO> 0 "s_register_operand" "=w")
++   (unspec:<VH_CVTTO>
++    [(match_operand:VCVTHI 1 "s_register_operand" "w")
++     (match_operand:SI 2 "immediate_operand" "i")]
++    VCVT_US_N))]
++ "TARGET_NEON_FP16INST"
++{
++  neon_const_bounds (operands[2], 0, 17);
++  return "vcvt.f16.<sup>%#16\t%<V_reg>0, %<V_reg>1, %2";
++}
++ [(set_attr "type" "neon_int_to_fp_<VH_elem_ch><q>")]
++)
++
++(define_insn "neon_vcvt<vcvth_op><sup><mode>"
++ [(set
++   (match_operand:<VH_CVTTO> 0 "s_register_operand" "=w")
++   (unspec:<VH_CVTTO>
++    [(match_operand:VH 1 "s_register_operand" "w")]
++    VCVT_HF_US))]
++ "TARGET_NEON_FP16INST"
++ "vcvt<vcvth_op>.<sup>%#16.f16\t%<V_reg>0, %<V_reg>1"
++  [(set_attr "type" "neon_fp_to_int_<VH_elem_ch><q>")]
++)
++
+ (define_insn "neon_vmovn<mode>"
+   [(set (match_operand:<V_narrow> 0 "s_register_operand" "=w")
+ 	(unspec:<V_narrow> [(match_operand:VN 1 "s_register_operand" "w")]
+@@ -3193,6 +3784,18 @@ if (BYTES_BIG_ENDIAN)
+                    (const_string "neon_mul_<V_elem_ch>_scalar<q>")))]
+ )
+ 
++(define_insn "neon_vmul_lane<mode>"
++  [(set (match_operand:VH 0 "s_register_operand" "=w")
++	(unspec:VH [(match_operand:VH 1 "s_register_operand" "w")
++		    (match_operand:V4HF 2 "s_register_operand"
++		     "<scalar_mul_constraint>")
++		     (match_operand:SI 3 "immediate_operand" "i")]
++		     UNSPEC_VMUL_LANE))]
++  "TARGET_NEON_FP16INST"
++  "vmul.f16\t%<V_reg>0, %<V_reg>1, %P2[%c3]"
++  [(set_attr "type" "neon_fp_mul_s_scalar<q>")]
++)
++
+ (define_insn "neon_vmull<sup>_lane<mode>"
+   [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
+ 	(unspec:<V_widen> [(match_operand:VMDI 1 "s_register_operand" "w")
+@@ -3447,6 +4050,19 @@ if (BYTES_BIG_ENDIAN)
+   DONE;
+ })
+ 
++(define_expand "neon_vmul_n<mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:VH 1 "s_register_operand")
++   (match_operand:<V_elem> 2 "s_register_operand")]
++  "TARGET_NEON_FP16INST"
++{
++  rtx tmp = gen_reg_rtx (V4HFmode);
++  emit_insn (gen_neon_vset_lanev4hf (tmp, operands[2], tmp, const0_rtx));
++  emit_insn (gen_neon_vmul_lane<mode> (operands[0], operands[1], tmp,
++				       const0_rtx));
++  DONE;
++})
++
+ (define_expand "neon_vmulls_n<mode>"
+   [(match_operand:<V_widen> 0 "s_register_operand" "")
+    (match_operand:VMDI 1 "s_register_operand" "")
+@@ -4168,25 +4784,25 @@ if (BYTES_BIG_ENDIAN)
+ 
+ (define_expand "neon_vtrn<mode>_internal"
+   [(parallel
+-    [(set (match_operand:VDQW 0 "s_register_operand" "")
+-	  (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "")
+-			(match_operand:VDQW 2 "s_register_operand" "")]
++    [(set (match_operand:VDQWH 0 "s_register_operand")
++	  (unspec:VDQWH [(match_operand:VDQWH 1 "s_register_operand")
++			 (match_operand:VDQWH 2 "s_register_operand")]
+ 	   UNSPEC_VTRN1))
+-     (set (match_operand:VDQW 3 "s_register_operand" "")
+-          (unspec:VDQW [(match_dup 1) (match_dup 2)] UNSPEC_VTRN2))])]
++     (set (match_operand:VDQWH 3 "s_register_operand")
++	  (unspec:VDQWH [(match_dup 1) (match_dup 2)] UNSPEC_VTRN2))])]
+   "TARGET_NEON"
+   ""
+ )
+ 
+ ;; Note: Different operand numbering to handle tied registers correctly.
+ (define_insn "*neon_vtrn<mode>_insn"
+-  [(set (match_operand:VDQW 0 "s_register_operand" "=&w")
+-        (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
+-                      (match_operand:VDQW 3 "s_register_operand" "2")]
+-                     UNSPEC_VTRN1))
+-   (set (match_operand:VDQW 2 "s_register_operand" "=&w")
+-         (unspec:VDQW [(match_dup 1) (match_dup 3)]
+-                     UNSPEC_VTRN2))]
++  [(set (match_operand:VDQWH 0 "s_register_operand" "=&w")
++	(unspec:VDQWH [(match_operand:VDQWH 1 "s_register_operand" "0")
++		       (match_operand:VDQWH 3 "s_register_operand" "2")]
++	 UNSPEC_VTRN1))
++   (set (match_operand:VDQWH 2 "s_register_operand" "=&w")
++	(unspec:VDQWH [(match_dup 1) (match_dup 3)]
++	 UNSPEC_VTRN2))]
+   "TARGET_NEON"
+   "vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
+   [(set_attr "type" "neon_permute<q>")]
+@@ -4194,25 +4810,25 @@ if (BYTES_BIG_ENDIAN)
+ 
+ (define_expand "neon_vzip<mode>_internal"
+   [(parallel
+-    [(set (match_operand:VDQW 0 "s_register_operand" "")
+-	  (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "")
+-	  	        (match_operand:VDQW 2 "s_register_operand" "")]
+-		       UNSPEC_VZIP1))
+-    (set (match_operand:VDQW 3 "s_register_operand" "")
+-	 (unspec:VDQW [(match_dup 1) (match_dup 2)] UNSPEC_VZIP2))])]
++    [(set (match_operand:VDQWH 0 "s_register_operand")
++	  (unspec:VDQWH [(match_operand:VDQWH 1 "s_register_operand")
++			 (match_operand:VDQWH 2 "s_register_operand")]
++	   UNSPEC_VZIP1))
++    (set (match_operand:VDQWH 3 "s_register_operand")
++	 (unspec:VDQWH [(match_dup 1) (match_dup 2)] UNSPEC_VZIP2))])]
+   "TARGET_NEON"
+   ""
+ )
+ 
+ ;; Note: Different operand numbering to handle tied registers correctly.
+ (define_insn "*neon_vzip<mode>_insn"
+-  [(set (match_operand:VDQW 0 "s_register_operand" "=&w")
+-        (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
+-                      (match_operand:VDQW 3 "s_register_operand" "2")]
+-                     UNSPEC_VZIP1))
+-   (set (match_operand:VDQW 2 "s_register_operand" "=&w")
+-        (unspec:VDQW [(match_dup 1) (match_dup 3)]
+-                     UNSPEC_VZIP2))]
++  [(set (match_operand:VDQWH 0 "s_register_operand" "=&w")
++	(unspec:VDQWH [(match_operand:VDQWH 1 "s_register_operand" "0")
++		       (match_operand:VDQWH 3 "s_register_operand" "2")]
++	 UNSPEC_VZIP1))
++   (set (match_operand:VDQWH 2 "s_register_operand" "=&w")
++	(unspec:VDQWH [(match_dup 1) (match_dup 3)]
++	 UNSPEC_VZIP2))]
+   "TARGET_NEON"
+   "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
+   [(set_attr "type" "neon_zip<q>")]
+@@ -4220,25 +4836,25 @@ if (BYTES_BIG_ENDIAN)
+ 
+ (define_expand "neon_vuzp<mode>_internal"
+   [(parallel
+-    [(set (match_operand:VDQW 0 "s_register_operand" "")
+-	  (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "")
+-			(match_operand:VDQW 2 "s_register_operand" "")]
++    [(set (match_operand:VDQWH 0 "s_register_operand")
++	  (unspec:VDQWH [(match_operand:VDQWH 1 "s_register_operand")
++			(match_operand:VDQWH 2 "s_register_operand")]
+ 	   UNSPEC_VUZP1))
+-     (set (match_operand:VDQW 3 "s_register_operand" "")
+-	  (unspec:VDQW [(match_dup 1) (match_dup 2)] UNSPEC_VUZP2))])]
++     (set (match_operand:VDQWH 3 "s_register_operand" "")
++	  (unspec:VDQWH [(match_dup 1) (match_dup 2)] UNSPEC_VUZP2))])]
+   "TARGET_NEON"
+   ""
+ )
+ 
+ ;; Note: Different operand numbering to handle tied registers correctly.
+ (define_insn "*neon_vuzp<mode>_insn"
+-  [(set (match_operand:VDQW 0 "s_register_operand" "=&w")
+-        (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
+-                      (match_operand:VDQW 3 "s_register_operand" "2")]
+-                     UNSPEC_VUZP1))
+-   (set (match_operand:VDQW 2 "s_register_operand" "=&w")
+-        (unspec:VDQW [(match_dup 1) (match_dup 3)]
+-                     UNSPEC_VUZP2))]
++  [(set (match_operand:VDQWH 0 "s_register_operand" "=&w")
++	(unspec:VDQWH [(match_operand:VDQWH 1 "s_register_operand" "0")
++		       (match_operand:VDQWH 3 "s_register_operand" "2")]
++	 UNSPEC_VUZP1))
++   (set (match_operand:VDQWH 2 "s_register_operand" "=&w")
++	(unspec:VDQWH [(match_dup 1) (match_dup 3)]
++	 UNSPEC_VUZP2))]
+   "TARGET_NEON"
+   "vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
+   [(set_attr "type" "neon_zip<q>")]
+--- a/src/gcc/config/arm/neon.ml
++++ b/src//dev/null
+@@ -1,2357 +0,0 @@
+-(* Common code for ARM NEON header file, documentation and test case
+-   generators.
+-
+-   Copyright (C) 2006-2016 Free Software Foundation, Inc.
+-   Contributed by CodeSourcery.
+-
+-   This file is part of GCC.
+-
+-   GCC is free software; you can redistribute it and/or modify it under
+-   the terms of the GNU General Public License as published by the Free
+-   Software Foundation; either version 3, or (at your option) any later
+-   version.
+-
+-   GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+-   WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-   for more details.
+-
+-   You should have received a copy of the GNU General Public License
+-   along with GCC; see the file COPYING3.  If not see
+-   <http://www.gnu.org/licenses/>.  *)
+-
+-(* Shorthand types for vector elements.  *)
+-type elts = S8 | S16 | S32 | S64 | F16 | F32 | U8 | U16 | U32 | U64 | P8 | P16
+-          | P64 | P128 | I8 | I16 | I32 | I64 | B8 | B16 | B32 | B64 | Conv of elts * elts
+-          | Cast of elts * elts | NoElts
+-
+-type eltclass = Signed | Unsigned | Float | Poly | Int | Bits
+-	      | ConvClass of eltclass * eltclass | NoType
+-
+-(* These vector types correspond directly to C types.  *)
+-type vectype = T_int8x8    | T_int8x16
+-             | T_int16x4   | T_int16x8
+-	     | T_int32x2   | T_int32x4
+-	     | T_int64x1   | T_int64x2
+-	     | T_uint8x8   | T_uint8x16
+-	     | T_uint16x4  | T_uint16x8
+-	     | T_uint32x2  | T_uint32x4
+-	     | T_uint64x1  | T_uint64x2
+-	     | T_float16x4
+-	     | T_float32x2 | T_float32x4
+-	     | T_poly8x8   | T_poly8x16
+-	     | T_poly16x4  | T_poly16x8
+-	     | T_immediate of int * int
+-             | T_int8      | T_int16
+-             | T_int32     | T_int64
+-             | T_uint8     | T_uint16
+-             | T_uint32    | T_uint64
+-             | T_poly8     | T_poly16
+-             | T_poly64    | T_poly64x1
+-             | T_poly64x2  | T_poly128
+-             | T_float16   | T_float32
+-             | T_arrayof of int * vectype
+-             | T_ptrto of vectype | T_const of vectype
+-             | T_void      | T_intQI
+-             | T_intHI     | T_intSI
+-             | T_intDI     | T_intTI
+-             | T_floatHF   | T_floatSF
+-
+-(* The meanings of the following are:
+-     TImode : "Tetra", two registers (four words).
+-     EImode : "hExa", three registers (six words).
+-     OImode : "Octa", four registers (eight words).
+-     CImode : "dodeCa", six registers (twelve words).
+-     XImode : "heXadeca", eight registers (sixteen words).
+-*)
+-
+-type inttype = B_TImode | B_EImode | B_OImode | B_CImode | B_XImode
+-
+-type shape_elt = Dreg | Qreg | Corereg | Immed | VecArray of int * shape_elt
+-               | PtrTo of shape_elt | CstPtrTo of shape_elt
+-	       (* These next ones are used only in the test generator.  *)
+-	       | Element_of_dreg	(* Used for "lane" variants.  *)
+-	       | Element_of_qreg	(* Likewise.  *)
+-	       | All_elements_of_dreg	(* Used for "dup" variants.  *)
+-	       | Alternatives of shape_elt list (* Used for multiple valid operands *)
+-
+-type shape_form = All of int * shape_elt
+-                | Long
+-		| Long_noreg of shape_elt
+-		| Wide
+-		| Wide_noreg of shape_elt
+-		| Narrow
+-                | Long_imm
+-                | Narrow_imm
+-                | Binary_imm of shape_elt
+-                | Use_operands of shape_elt array
+-                | By_scalar of shape_elt
+-                | Unary_scalar of shape_elt
+-                | Wide_lane
+-                | Wide_scalar
+-                | Pair_result of shape_elt
+-
+-type arity = Arity0 of vectype
+-           | Arity1 of vectype * vectype
+-	   | Arity2 of vectype * vectype * vectype
+-	   | Arity3 of vectype * vectype * vectype * vectype
+-           | Arity4 of vectype * vectype * vectype * vectype * vectype
+-
+-type vecmode = V8QI | V4HI | V4HF |V2SI | V2SF | DI
+-             | V16QI | V8HI | V4SI | V4SF | V2DI | TI
+-             | QI | HI | SI | SF
+-
+-type opcode =
+-  (* Binary ops.  *)
+-    Vadd
+-  | Vmul
+-  | Vmla
+-  | Vmls
+-  | Vfma
+-  | Vfms
+-  | Vsub
+-  | Vceq
+-  | Vcge
+-  | Vcgt
+-  | Vcle
+-  | Vclt
+-  | Vcage
+-  | Vcagt
+-  | Vcale
+-  | Vcalt
+-  | Vtst
+-  | Vabd
+-  | Vaba
+-  | Vmax
+-  | Vmin
+-  | Vpadd
+-  | Vpada
+-  | Vpmax
+-  | Vpmin
+-  | Vrecps
+-  | Vrsqrts
+-  | Vshl
+-  | Vshr_n
+-  | Vshl_n
+-  | Vsra_n
+-  | Vsri
+-  | Vsli
+-  (* Logic binops.  *)
+-  | Vand
+-  | Vorr
+-  | Veor
+-  | Vbic
+-  | Vorn
+-  | Vbsl
+-  (* Ops with scalar.  *)
+-  | Vmul_lane
+-  | Vmla_lane
+-  | Vmls_lane
+-  | Vmul_n
+-  | Vmla_n
+-  | Vmls_n
+-  | Vmull_n
+-  | Vmull_lane
+-  | Vqdmull_n
+-  | Vqdmull_lane
+-  | Vqdmulh_n
+-  | Vqdmulh_lane
+-  (* Unary ops.  *)
+-  | Vrintn
+-  | Vrinta
+-  | Vrintp
+-  | Vrintm
+-  | Vrintz
+-  | Vabs
+-  | Vneg
+-  | Vcls
+-  | Vclz
+-  | Vcnt
+-  | Vrecpe
+-  | Vrsqrte
+-  | Vmvn
+-  (* Vector extract.  *)
+-  | Vext
+-  (* Reverse elements.  *)
+-  | Vrev64
+-  | Vrev32
+-  | Vrev16
+-  (* Transposition ops.  *)
+-  | Vtrn
+-  | Vzip
+-  | Vuzp
+-  (* Loads and stores (VLD1/VST1/VLD2...), elements and structures.  *)
+-  | Vldx of int
+-  | Vstx of int
+-  | Vldx_lane of int
+-  | Vldx_dup of int
+-  | Vstx_lane of int
+-  (* Set/extract lanes from a vector.  *)
+-  | Vget_lane
+-  | Vset_lane
+-  (* Initialize vector from bit pattern.  *)
+-  | Vcreate
+-  (* Set all lanes to same value.  *)
+-  | Vdup_n
+-  | Vmov_n  (* Is this the same?  *)
+-  (* Duplicate scalar to all lanes of vector.  *)
+-  | Vdup_lane
+-  (* Combine vectors.  *)
+-  | Vcombine
+-  (* Get quadword high/low parts.  *)
+-  | Vget_high
+-  | Vget_low
+-  (* Convert vectors.  *)
+-  | Vcvt
+-  | Vcvt_n
+-  (* Narrow/lengthen vectors.  *)
+-  | Vmovn
+-  | Vmovl
+-  (* Table lookup.  *)
+-  | Vtbl of int
+-  | Vtbx of int
+-  (* Reinterpret casts.  *)
+-  | Vreinterp
+-
+-let rev_elems revsize elsize nelts _ =
+-  let mask = (revsize / elsize) - 1 in
+-  let arr = Array.init nelts
+-    (fun i -> i lxor mask) in
+-  Array.to_list arr
+-
+-let permute_range i stride nelts increment =
+-  let rec build i = function
+-    0 -> []
+-  | nelts -> i :: (i + stride) :: build (i + increment) (pred nelts) in
+-  build i nelts
+-
+-(* Generate a list of integers suitable for vzip.  *)
+-let zip_range i stride nelts = permute_range i stride nelts 1
+-
+-(* Generate a list of integers suitable for vunzip.  *)
+-let uzip_range i stride nelts = permute_range i stride nelts 4
+-
+-(* Generate a list of integers suitable for trn.  *)
+-let trn_range i stride nelts = permute_range i stride nelts 2
+-
+-let zip_elems _ nelts part =
+-  match part with
+-    `lo -> zip_range 0 nelts (nelts / 2)
+-  | `hi -> zip_range (nelts / 2) nelts (nelts / 2)
+-
+-let uzip_elems _ nelts part =
+-  match part with
+-    `lo -> uzip_range 0 2 (nelts / 2)
+-  | `hi -> uzip_range 1 2 (nelts / 2)
+-
+-let trn_elems _ nelts part =
+-  match part with
+-    `lo -> trn_range 0 nelts (nelts / 2)
+-  | `hi -> trn_range 1 nelts (nelts / 2)
+-
+-(* Features used for documentation, to distinguish between some instruction
+-   variants, and to signal special requirements (e.g. swapping arguments).  *)
+-
+-type features =
+-    Halving
+-  | Rounding
+-  | Saturating
+-  | Dst_unsign
+-  | High_half
+-  | Doubling
+-  | Flipped of string  (* Builtin name to use with flipped arguments.  *)
+-  | InfoWord  (* Pass an extra word for signage/rounding etc. (always passed
+-                 for All _, Long, Wide, Narrow shape_forms.  *)
+-    (* Implement builtin as shuffle.  The parameter is a function which returns
+-       masks suitable for __builtin_shuffle: arguments are (element size,
+-       number of elements, high/low part selector).  *)
+-  | Use_shuffle of (int -> int -> [`lo|`hi] -> int list)
+-    (* A specification as to the shape of instruction expected upon
+-       disassembly, used if it differs from the shape used to build the
+-       intrinsic prototype.  Multiple entries in the constructor's argument
+-       indicate that the intrinsic expands to more than one assembly
+-       instruction, each with a corresponding shape specified here.  *)
+-  | Disassembles_as of shape_form list
+-  | Builtin_name of string  (* Override the name of the builtin.  *)
+-    (* Override the name of the instruction.  If more than one name
+-       is specified, it means that the instruction can have any of those
+-       names.  *)
+-  | Instruction_name of string list
+-    (* Mark that the intrinsic yields no instructions, or expands to yield
+-       behavior that the test generator cannot test.  *)
+-  | No_op
+-    (* Mark that the intrinsic has constant arguments that cannot be set
+-       to the defaults (zero for pointers and one otherwise) in the test
+-       cases.  The function supplied must return the integer to be written
+-       into the testcase for the argument number (0-based) supplied to it.  *)
+-  | Const_valuator of (int -> int)
+-  | Fixed_vector_reg
+-  | Fixed_core_reg
+-    (* Mark that the intrinsic requires __ARM_FEATURE_string to be defined.  *)
+-  | Requires_feature of string
+-    (* Mark that the intrinsic requires a particular architecture version.  *)
+-  | Requires_arch of int
+-    (* Mark that the intrinsic requires a particular bit in __ARM_FP to
+-    be set.   *)
+-  | Requires_FP_bit of int
+-    (* Compiler optimization level for the test.  *)
+-  | Compiler_optim of string
+-
+-exception MixedMode of elts * elts
+-
+-let rec elt_width = function
+-    S8 | U8 | P8 | I8 | B8 -> 8
+-  | S16 | U16 | P16 | I16 | B16 | F16 -> 16
+-  | S32 | F32 | U32 | I32 | B32 -> 32
+-  | S64 | U64 | P64 | I64 | B64 -> 64
+-  | P128 -> 128
+-  | Conv (a, b) ->
+-      let wa = elt_width a and wb = elt_width b in
+-      if wa = wb then wa else raise (MixedMode (a, b))
+-  | Cast (a, b) -> raise (MixedMode (a, b))
+-  | NoElts -> failwith "No elts"
+-
+-let rec elt_class = function
+-    S8 | S16 | S32 | S64 -> Signed
+-  | U8 | U16 | U32 | U64 -> Unsigned
+-  | P8 | P16 | P64 | P128 -> Poly
+-  | F16 | F32 -> Float
+-  | I8 | I16 | I32 | I64 -> Int
+-  | B8 | B16 | B32 | B64 -> Bits
+-  | Conv (a, b) | Cast (a, b) -> ConvClass (elt_class a, elt_class b)
+-  | NoElts -> NoType
+-
+-let elt_of_class_width c w =
+-  match c, w with
+-    Signed, 8 -> S8
+-  | Signed, 16 -> S16
+-  | Signed, 32 -> S32
+-  | Signed, 64 -> S64
+-  | Float, 16 -> F16
+-  | Float, 32 -> F32
+-  | Unsigned, 8 -> U8
+-  | Unsigned, 16 -> U16
+-  | Unsigned, 32 -> U32
+-  | Unsigned, 64 -> U64
+-  | Poly, 8 -> P8
+-  | Poly, 16 -> P16
+-  | Poly, 64 -> P64
+-  | Poly, 128 -> P128
+-  | Int, 8 -> I8
+-  | Int, 16 -> I16
+-  | Int, 32 -> I32
+-  | Int, 64 -> I64
+-  | Bits, 8 -> B8
+-  | Bits, 16 -> B16
+-  | Bits, 32 -> B32
+-  | Bits, 64 -> B64
+-  | _ -> failwith "Bad element type"
+-
+-(* Return unsigned integer element the same width as argument.  *)
+-let unsigned_of_elt elt =
+-  elt_of_class_width Unsigned (elt_width elt)
+-
+-let signed_of_elt elt =
+-  elt_of_class_width Signed (elt_width elt)
+-
+-(* Return untyped bits element the same width as argument.  *)
+-let bits_of_elt elt =
+-  elt_of_class_width Bits (elt_width elt)
+-
+-let non_signed_variant = function
+-    S8 -> I8
+-  | S16 -> I16
+-  | S32 -> I32
+-  | S64 -> I64
+-  | U8 -> I8
+-  | U16 -> I16
+-  | U32 -> I32
+-  | U64 -> I64
+-  | x -> x
+-
+-let poly_unsigned_variant v =
+-  let elclass = match elt_class v with
+-    Poly -> Unsigned
+-  | x -> x in
+-  elt_of_class_width elclass (elt_width v)
+-
+-let widen_elt elt =
+-  let w = elt_width elt
+-  and c = elt_class elt in
+-  elt_of_class_width c (w * 2)
+-
+-let narrow_elt elt =
+-  let w = elt_width elt
+-  and c = elt_class elt in
+-  elt_of_class_width c (w / 2)
+-
+-(* If we're trying to find a mode from a "Use_operands" instruction, use the
+-   last vector operand as the dominant mode used to invoke the correct builtin.
+-   We must stick to this rule in neon.md.  *)
+-let find_key_operand operands =
+-  let rec scan opno =
+-    match operands.(opno) with
+-      Qreg -> Qreg
+-    | Dreg -> Dreg
+-    | VecArray (_, Qreg) -> Qreg
+-    | VecArray (_, Dreg) -> Dreg
+-    | _ -> scan (opno-1)
+-  in
+-    scan ((Array.length operands) - 1)
+-
+-(* Find a vecmode from a shape_elt ELT for an instruction with shape_form
+-   SHAPE.  For a Use_operands shape, if ARGPOS is passed then return the mode
+-   for the given argument position, else determine which argument to return a
+-   mode for automatically.  *)
+-
+-let rec mode_of_elt ?argpos elt shape =
+-  let flt = match elt_class elt with
+-    Float | ConvClass(_, Float) -> true | _ -> false in
+-  let idx =
+-    match elt_width elt with
+-      8 -> 0 | 16 -> 1 | 32 -> 2 | 64 -> 3 | 128 -> 4
+-    | _ -> failwith "Bad element width"
+-  in match shape with
+-    All (_, Dreg) | By_scalar Dreg | Pair_result Dreg | Unary_scalar Dreg
+-  | Binary_imm Dreg | Long_noreg Dreg | Wide_noreg Dreg ->
+-      if flt then
+-        [| V8QI; V4HF; V2SF; DI |].(idx)
+-      else
+-        [| V8QI; V4HI; V2SI; DI |].(idx)
+-  | All (_, Qreg) | By_scalar Qreg | Pair_result Qreg | Unary_scalar Qreg
+-  | Binary_imm Qreg | Long_noreg Qreg | Wide_noreg Qreg ->
+-      [| V16QI; V8HI; if flt then V4SF else V4SI; V2DI; TI|].(idx)
+-  | All (_, (Corereg | PtrTo _ | CstPtrTo _)) ->
+-      [| QI; HI; if flt then SF else SI; DI |].(idx)
+-  | Long | Wide | Wide_lane | Wide_scalar
+-  | Long_imm ->
+-      [| V8QI; V4HI; V2SI; DI |].(idx)
+-  | Narrow | Narrow_imm -> [| V16QI; V8HI; V4SI; V2DI |].(idx)
+-  | Use_operands ops ->
+-      begin match argpos with
+-        None -> mode_of_elt ?argpos elt (All (0, (find_key_operand ops)))
+-      | Some pos -> mode_of_elt ?argpos elt (All (0, ops.(pos)))
+-      end
+-  | _ -> failwith "invalid shape"
+-
+-(* Modify an element type dependent on the shape of the instruction and the
+-   operand number.  *)
+-
+-let shapemap shape no =
+-  let ident = fun x -> x in
+-  match shape with
+-    All _ | Use_operands _ | By_scalar _ | Pair_result _ | Unary_scalar _
+-  | Binary_imm _ -> ident
+-  | Long | Long_noreg _ | Wide_scalar | Long_imm ->
+-      [| widen_elt; ident; ident |].(no)
+-  | Wide | Wide_noreg _ -> [| widen_elt; widen_elt; ident |].(no)
+-  | Wide_lane -> [| widen_elt; ident; ident; ident |].(no)
+-  | Narrow | Narrow_imm -> [| narrow_elt; ident; ident |].(no)
+-
+-(* Register type (D/Q) of an operand, based on shape and operand number.  *)
+-
+-let regmap shape no =
+-  match shape with
+-    All (_, reg) | Long_noreg reg | Wide_noreg reg -> reg
+-  | Long -> [| Qreg; Dreg; Dreg |].(no)
+-  | Wide -> [| Qreg; Qreg; Dreg |].(no)
+-  | Narrow -> [| Dreg; Qreg; Qreg |].(no)
+-  | Wide_lane -> [| Qreg; Dreg; Dreg; Immed |].(no)
+-  | Wide_scalar -> [| Qreg; Dreg; Corereg |].(no)
+-  | By_scalar reg -> [| reg; reg; Dreg; Immed |].(no)
+-  | Unary_scalar reg -> [| reg; Dreg; Immed |].(no)
+-  | Pair_result reg -> [| VecArray (2, reg); reg; reg |].(no)
+-  | Binary_imm reg -> [| reg; reg; Immed |].(no)
+-  | Long_imm -> [| Qreg; Dreg; Immed |].(no)
+-  | Narrow_imm -> [| Dreg; Qreg; Immed |].(no)
+-  | Use_operands these -> these.(no)
+-
+-let type_for_elt shape elt no =
+-  let elt = (shapemap shape no) elt in
+-  let reg = regmap shape no in
+-  let rec type_for_reg_elt reg elt =
+-    match reg with
+-      Dreg ->
+-        begin match elt with
+-          S8 -> T_int8x8
+-        | S16 -> T_int16x4
+-        | S32 -> T_int32x2
+-        | S64 -> T_int64x1
+-        | U8 -> T_uint8x8
+-        | U16 -> T_uint16x4
+-        | U32 -> T_uint32x2
+-        | U64 -> T_uint64x1
+-        | P64 -> T_poly64x1
+-        | P128 -> T_poly128
+-        | F16 -> T_float16x4
+-        | F32 -> T_float32x2
+-        | P8 -> T_poly8x8
+-        | P16 -> T_poly16x4
+-        | _ -> failwith "Bad elt type for Dreg"
+-        end
+-    | Qreg ->
+-        begin match elt with
+-          S8 -> T_int8x16
+-        | S16 -> T_int16x8
+-        | S32 -> T_int32x4
+-        | S64 -> T_int64x2
+-        | U8 -> T_uint8x16
+-        | U16 -> T_uint16x8
+-        | U32 -> T_uint32x4
+-        | U64 -> T_uint64x2
+-        | F32 -> T_float32x4
+-        | P8 -> T_poly8x16
+-        | P16 -> T_poly16x8
+-        | P64 -> T_poly64x2
+-        | P128 -> T_poly128
+-        | _ -> failwith "Bad elt type for Qreg"
+-        end
+-    | Corereg ->
+-        begin match elt with
+-          S8 -> T_int8
+-        | S16 -> T_int16
+-        | S32 -> T_int32
+-        | S64 -> T_int64
+-        | U8 -> T_uint8
+-        | U16 -> T_uint16
+-        | U32 -> T_uint32
+-        | U64 -> T_uint64
+-        | P8 -> T_poly8
+-        | P16 -> T_poly16
+-        | P64 -> T_poly64
+-        | P128 -> T_poly128
+-        | F32 -> T_float32
+-        | _ -> failwith "Bad elt type for Corereg"
+-        end
+-    | Immed ->
+-        T_immediate (0, 0)
+-    | VecArray (num, sub) ->
+-        T_arrayof (num, type_for_reg_elt sub elt)
+-    | PtrTo x ->
+-        T_ptrto (type_for_reg_elt x elt)
+-    | CstPtrTo x ->
+-        T_ptrto (T_const (type_for_reg_elt x elt))
+-    (* Anything else is solely for the use of the test generator.  *)
+-    | _ -> assert false
+-  in
+-    type_for_reg_elt reg elt
+-
+-(* Return size of a vector type, in bits.  *)
+-let vectype_size = function
+-    T_int8x8 | T_int16x4 | T_int32x2 | T_int64x1
+-  | T_uint8x8 | T_uint16x4 | T_uint32x2 | T_uint64x1
+-  | T_float32x2 | T_poly8x8 | T_poly64x1 | T_poly16x4 | T_float16x4 -> 64
+-  | T_int8x16 | T_int16x8 | T_int32x4 | T_int64x2
+-  | T_uint8x16 | T_uint16x8  | T_uint32x4  | T_uint64x2
+-  | T_float32x4 | T_poly8x16 | T_poly64x2 | T_poly16x8 -> 128
+-  | _ -> raise Not_found
+-
+-let inttype_for_array num elttype =
+-  let eltsize = vectype_size elttype in
+-  let numwords = (num * eltsize) / 32 in
+-  match numwords with
+-    4 -> B_TImode
+-  | 6 -> B_EImode
+-  | 8 -> B_OImode
+-  | 12 -> B_CImode
+-  | 16 -> B_XImode
+-  | _ -> failwith ("no int type for size " ^ string_of_int numwords)
+-
+-(* These functions return pairs of (internal, external) types, where "internal"
+-   types are those seen by GCC, and "external" are those seen by the assembler.
+-   These types aren't necessarily the same, since the intrinsics can munge more
+-   than one C type into each assembler opcode.  *)
+-
+-let make_sign_invariant func shape elt =
+-  let arity, elt' = func shape elt in
+-  arity, non_signed_variant elt'
+-
+-(* Don't restrict any types.  *)
+-
+-let elts_same make_arity shape elt =
+-  let vtype = type_for_elt shape elt in
+-  make_arity vtype, elt
+-
+-(* As sign_invar_*, but when sign matters.  *)
+-let elts_same_io_lane =
+-  elts_same (fun vtype -> Arity4 (vtype 0, vtype 0, vtype 1, vtype 2, vtype 3))
+-
+-let elts_same_io =
+-  elts_same (fun vtype -> Arity3 (vtype 0, vtype 0, vtype 1, vtype 2))
+-
+-let elts_same_2_lane =
+-  elts_same (fun vtype -> Arity3 (vtype 0, vtype 1, vtype 2, vtype 3))
+-
+-let elts_same_3 = elts_same_2_lane
+-
+-let elts_same_2 =
+-  elts_same (fun vtype -> Arity2 (vtype 0, vtype 1, vtype 2))
+-
+-let elts_same_1 =
+-  elts_same (fun vtype -> Arity1 (vtype 0, vtype 1))
+-
+-(* Use for signed/unsigned invariant operations (i.e. where the operation
+-   doesn't depend on the sign of the data.  *)
+-
+-let sign_invar_io_lane = make_sign_invariant elts_same_io_lane
+-let sign_invar_io = make_sign_invariant elts_same_io
+-let sign_invar_2_lane = make_sign_invariant elts_same_2_lane
+-let sign_invar_2 = make_sign_invariant elts_same_2
+-let sign_invar_1 = make_sign_invariant elts_same_1
+-
+-(* Sign-sensitive comparison.  *)
+-
+-let cmp_sign_matters shape elt =
+-  let vtype = type_for_elt shape elt
+-  and rtype = type_for_elt shape (unsigned_of_elt elt) 0 in
+-  Arity2 (rtype, vtype 1, vtype 2), elt
+-
+-(* Signed/unsigned invariant comparison.  *)
+-
+-let cmp_sign_invar shape elt =
+-  let shape', elt' = cmp_sign_matters shape elt in
+-  let elt'' =
+-    match non_signed_variant elt' with
+-      P8 -> I8
+-    | x -> x
+-  in
+-    shape', elt''
+-
+-(* Comparison (VTST) where only the element width matters.  *)
+-
+-let cmp_bits shape elt =
+-  let vtype = type_for_elt shape elt
+-  and rtype = type_for_elt shape (unsigned_of_elt elt) 0
+-  and bits_only = bits_of_elt elt in
+-  Arity2 (rtype, vtype 1, vtype 2), bits_only
+-
+-let reg_shift shape elt =
+-  let vtype = type_for_elt shape elt
+-  and op2type = type_for_elt shape (signed_of_elt elt) 2 in
+-  Arity2 (vtype 0, vtype 1, op2type), elt
+-
+-(* Genericised constant-shift type-generating function.  *)
+-
+-let const_shift mkimm ?arity ?result shape elt =
+-  let op2type = (shapemap shape 2) elt in
+-  let op2width = elt_width op2type in
+-  let op2 = mkimm op2width
+-  and op1 = type_for_elt shape elt 1
+-  and r_elt =
+-    match result with
+-      None -> elt
+-    | Some restriction -> restriction elt in
+-  let rtype = type_for_elt shape r_elt 0 in
+-  match arity with
+-    None -> Arity2 (rtype, op1, op2), elt
+-  | Some mkarity -> mkarity rtype op1 op2, elt
+-
+-(* Use for immediate right-shifts.  *)
+-
+-let shift_right shape elt =
+-  const_shift (fun imm -> T_immediate (1, imm)) shape elt
+-
+-let shift_right_acc shape elt =
+-  const_shift (fun imm -> T_immediate (1, imm))
+-    ~arity:(fun dst op1 op2 -> Arity3 (dst, dst, op1, op2)) shape elt
+-
+-(* Use for immediate right-shifts when the operation doesn't care about
+-   signedness.  *)
+-
+-let shift_right_sign_invar =
+-  make_sign_invariant shift_right
+-
+-(* Immediate right-shift; result is unsigned even when operand is signed.  *)
+-
+-let shift_right_to_uns shape elt =
+-  const_shift (fun imm -> T_immediate (1, imm)) ~result:unsigned_of_elt
+-    shape elt
+-
+-(* Immediate left-shift.  *)
+-
+-let shift_left shape elt =
+-  const_shift (fun imm -> T_immediate (0, imm - 1)) shape elt
+-
+-(* Immediate left-shift, unsigned result.  *)
+-
+-let shift_left_to_uns shape elt =
+-  const_shift (fun imm -> T_immediate (0, imm - 1)) ~result:unsigned_of_elt
+-    shape elt
+-
+-(* Immediate left-shift, don't care about signs.  *)
+-
+-let shift_left_sign_invar =
+-  make_sign_invariant shift_left
+-
+-(* Shift left/right and insert: only element size matters.  *)
+-
+-let shift_insert shape elt =
+-  let arity, elt =
+-    const_shift (fun imm -> T_immediate (1, imm))
+-    ~arity:(fun dst op1 op2 -> Arity3 (dst, dst, op1, op2)) shape elt in
+-  arity, bits_of_elt elt
+-
+-(* Get/set lane.  *)
+-
+-let get_lane shape elt =
+-  let vtype = type_for_elt shape elt in
+-  Arity2 (vtype 0, vtype 1, vtype 2),
+-    (match elt with P8 -> U8 | P16 -> U16 | S32 | U32 | F32 -> B32 | x -> x)
+-
+-let set_lane shape elt =
+-  let vtype = type_for_elt shape elt in
+-  Arity3 (vtype 0, vtype 1, vtype 2, vtype 3), bits_of_elt elt
+-
+-let set_lane_notype shape elt =
+-  let vtype = type_for_elt shape elt in
+-  Arity3 (vtype 0, vtype 1, vtype 2, vtype 3), NoElts
+-
+-let create_vector shape elt =
+-  let vtype = type_for_elt shape U64 1
+-  and rtype = type_for_elt shape elt 0 in
+-  Arity1 (rtype, vtype), elt
+-
+-let conv make_arity shape elt =
+-  let edest, esrc = match elt with
+-    Conv (edest, esrc) | Cast (edest, esrc) -> edest, esrc
+-  | _ -> failwith "Non-conversion element in conversion" in
+-  let vtype = type_for_elt shape esrc
+-  and rtype = type_for_elt shape edest 0 in
+-  make_arity rtype vtype, elt
+-
+-let conv_1 = conv (fun rtype vtype -> Arity1 (rtype, vtype 1))
+-let conv_2 = conv (fun rtype vtype -> Arity2 (rtype, vtype 1, vtype 2))
+-
+-(* Operation has an unsigned result even if operands are signed.  *)
+-
+-let dst_unsign make_arity shape elt =
+-  let vtype = type_for_elt shape elt
+-  and rtype = type_for_elt shape (unsigned_of_elt elt) 0 in
+-  make_arity rtype vtype, elt
+-
+-let dst_unsign_1 = dst_unsign (fun rtype vtype -> Arity1 (rtype, vtype 1))
+-
+-let make_bits_only func shape elt =
+-  let arity, elt' = func shape elt in
+-  arity, bits_of_elt elt'
+-
+-(* Extend operation.  *)
+-
+-let extend shape elt =
+-  let vtype = type_for_elt shape elt in
+-  Arity3 (vtype 0, vtype 1, vtype 2, vtype 3), bits_of_elt elt
+-
+-(* Table look-up operations. Operand 2 is signed/unsigned for signed/unsigned
+-   integer ops respectively, or unsigned for polynomial ops.  *)
+-
+-let table mkarity shape elt =
+-  let vtype = type_for_elt shape elt in
+-  let op2 = type_for_elt shape (poly_unsigned_variant elt) 2 in
+-  mkarity vtype op2, bits_of_elt elt
+-
+-let table_2 = table (fun vtype op2 -> Arity2 (vtype 0, vtype 1, op2))
+-let table_io = table (fun vtype op2 -> Arity3 (vtype 0, vtype 0, vtype 1, op2))
+-
+-(* Operations where only bits matter.  *)
+-
+-let bits_1 = make_bits_only elts_same_1
+-let bits_2 = make_bits_only elts_same_2
+-let bits_3 = make_bits_only elts_same_3
+-
+-(* Store insns.  *)
+-let store_1 shape elt =
+-  let vtype = type_for_elt shape elt in
+-  Arity2 (T_void, vtype 0, vtype 1), bits_of_elt elt
+-
+-let store_3 shape elt =
+-  let vtype = type_for_elt shape elt in
+-  Arity3 (T_void, vtype 0, vtype 1, vtype 2), bits_of_elt elt
+-
+-let make_notype func shape elt =
+-  let arity, _ = func shape elt in
+-  arity, NoElts
+-
+-let notype_1 = make_notype elts_same_1
+-let notype_2 = make_notype elts_same_2
+-let notype_3 = make_notype elts_same_3
+-
+-(* Bit-select operations (first operand is unsigned int).  *)
+-
+-let bit_select shape elt =
+-  let vtype = type_for_elt shape elt
+-  and itype = type_for_elt shape (unsigned_of_elt elt) in
+-  Arity3 (vtype 0, itype 1, vtype 2, vtype 3), NoElts
+-
+-(* Common lists of supported element types.  *)
+-
+-let s_8_32 = [S8; S16; S32]
+-let u_8_32 = [U8; U16; U32]
+-let su_8_32 = [S8; S16; S32; U8; U16; U32]
+-let su_8_64 = S64 :: U64 :: su_8_32
+-let su_16_64 = [S16; S32; S64; U16; U32; U64]
+-let pf_su_8_16 = [P8; P16; S8; S16; U8; U16]
+-let pf_su_8_32 = P8 :: P16 :: F32 :: su_8_32
+-let pf_su_8_64 = P8 :: P16 :: F32 :: su_8_64
+-let suf_32 = [S32; U32; F32]
+-
+-let ops =
+-  [
+-    (* Addition.  *)
+-    Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_32;
+-    Vadd, [No_op], All (3, Dreg), "vadd", sign_invar_2, [S64; U64];
+-    Vadd, [], All (3, Qreg), "vaddQ", sign_invar_2, F32 :: su_8_64;
+-    Vadd, [], Long, "vaddl", elts_same_2, su_8_32;
+-    Vadd, [], Wide, "vaddw", elts_same_2, su_8_32;
+-    Vadd, [Halving], All (3, Dreg), "vhadd", elts_same_2, su_8_32;
+-    Vadd, [Halving], All (3, Qreg), "vhaddQ", elts_same_2, su_8_32;
+-    Vadd, [Instruction_name ["vrhadd"]; Rounding; Halving],
+-      All (3, Dreg), "vRhadd", elts_same_2, su_8_32;
+-    Vadd, [Instruction_name ["vrhadd"]; Rounding; Halving],
+-      All (3, Qreg), "vRhaddQ", elts_same_2, su_8_32;
+-    Vadd, [Saturating], All (3, Dreg), "vqadd", elts_same_2, su_8_64;
+-    Vadd, [Saturating], All (3, Qreg), "vqaddQ", elts_same_2, su_8_64;
+-    Vadd, [High_half], Narrow, "vaddhn", sign_invar_2, su_16_64;
+-    Vadd, [Instruction_name ["vraddhn"]; Rounding; High_half],
+-      Narrow, "vRaddhn", sign_invar_2, su_16_64;
+-
+-    (* Multiplication.  *)
+-    Vmul, [], All (3, Dreg), "vmul", sign_invar_2, P8 :: F32 :: su_8_32;
+-    Vmul, [], All (3, Qreg), "vmulQ", sign_invar_2, P8 :: F32 :: su_8_32;
+-    Vmul, [Saturating; Doubling; High_half], All (3, Dreg), "vqdmulh",
+-      elts_same_2, [S16; S32];
+-    Vmul, [Saturating; Doubling; High_half], All (3, Qreg), "vqdmulhQ",
+-      elts_same_2, [S16; S32];
+-    Vmul,
+-      [Saturating; Rounding; Doubling; High_half;
+-       Instruction_name ["vqrdmulh"]],
+-      All (3, Dreg), "vqRdmulh",
+-      elts_same_2, [S16; S32];
+-    Vmul,
+-      [Saturating; Rounding; Doubling; High_half;
+-       Instruction_name ["vqrdmulh"]],
+-      All (3, Qreg), "vqRdmulhQ",
+-      elts_same_2, [S16; S32];
+-    Vmul, [], Long, "vmull", elts_same_2, P8 :: su_8_32;
+-    Vmul, [Saturating; Doubling], Long, "vqdmull", elts_same_2, [S16; S32];
+-
+-    (* Multiply-accumulate. *)
+-    Vmla, [], All (3, Dreg), "vmla", sign_invar_io, F32 :: su_8_32;
+-    Vmla, [], All (3, Qreg), "vmlaQ", sign_invar_io, F32 :: su_8_32;
+-    Vmla, [], Long, "vmlal", elts_same_io, su_8_32;
+-    Vmla, [Saturating; Doubling], Long, "vqdmlal", elts_same_io, [S16; S32];
+-
+-    (* Multiply-subtract.  *)
+-    Vmls, [], All (3, Dreg), "vmls", sign_invar_io, F32 :: su_8_32;
+-    Vmls, [], All (3, Qreg), "vmlsQ", sign_invar_io, F32 :: su_8_32;
+-    Vmls, [], Long, "vmlsl", elts_same_io, su_8_32;
+-    Vmls, [Saturating; Doubling], Long, "vqdmlsl", elts_same_io, [S16; S32];
+-
+-    (* Fused-multiply-accumulate. *)
+-    Vfma, [Requires_feature "FMA"], All (3, Dreg), "vfma", elts_same_io, [F32];
+-    Vfma, [Requires_feature "FMA"], All (3, Qreg), "vfmaQ", elts_same_io, [F32];
+-    Vfms, [Requires_feature "FMA"], All (3, Dreg), "vfms", elts_same_io, [F32];
+-    Vfms, [Requires_feature "FMA"], All (3, Qreg), "vfmsQ", elts_same_io, [F32];
+-
+-    (* Round to integral. *)
+-    Vrintn, [Builtin_name "vrintn"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
+-            "vrndn", elts_same_1, [F32];
+-    Vrintn, [Builtin_name "vrintn"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
+-            "vrndqn", elts_same_1, [F32];
+-    Vrinta, [Builtin_name "vrinta"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
+-            "vrnda", elts_same_1, [F32];
+-    Vrinta, [Builtin_name "vrinta"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
+-            "vrndqa", elts_same_1, [F32];
+-    Vrintp, [Builtin_name "vrintp"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
+-            "vrndp", elts_same_1, [F32];
+-    Vrintp, [Builtin_name "vrintp"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
+-            "vrndqp", elts_same_1, [F32];
+-    Vrintm, [Builtin_name "vrintm"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
+-            "vrndm", elts_same_1, [F32];
+-    Vrintm, [Builtin_name "vrintm"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
+-            "vrndqm", elts_same_1, [F32];
+-    Vrintz, [Builtin_name "vrintz"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
+-            "vrnd", elts_same_1, [F32];
+-    Vrintz, [Builtin_name "vrintz"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
+-            "vrndq", elts_same_1, [F32];
+-    (* Subtraction.  *)
+-    Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_32;
+-    Vsub, [No_op], All (3, Dreg), "vsub", sign_invar_2,  [S64; U64];
+-    Vsub, [], All (3, Qreg), "vsubQ", sign_invar_2, F32 :: su_8_64;
+-    Vsub, [], Long, "vsubl", elts_same_2, su_8_32;
+-    Vsub, [], Wide, "vsubw", elts_same_2, su_8_32;
+-    Vsub, [Halving], All (3, Dreg), "vhsub", elts_same_2, su_8_32;
+-    Vsub, [Halving], All (3, Qreg), "vhsubQ", elts_same_2, su_8_32;
+-    Vsub, [Saturating], All (3, Dreg), "vqsub", elts_same_2, su_8_64;
+-    Vsub, [Saturating], All (3, Qreg), "vqsubQ", elts_same_2, su_8_64;
+-    Vsub, [High_half], Narrow, "vsubhn", sign_invar_2, su_16_64;
+-    Vsub, [Instruction_name ["vrsubhn"]; Rounding; High_half],
+-      Narrow, "vRsubhn", sign_invar_2, su_16_64;
+-
+-    (* Comparison, equal.  *)
+-    Vceq, [], All (3, Dreg), "vceq", cmp_sign_invar, P8 :: F32 :: su_8_32;
+-    Vceq, [], All (3, Qreg), "vceqQ", cmp_sign_invar, P8 :: F32 :: su_8_32;
+-
+-    (* Comparison, greater-than or equal.  *)
+-    Vcge, [], All (3, Dreg), "vcge", cmp_sign_matters, F32 :: s_8_32;
+-    Vcge, [Instruction_name ["vcge"]; Builtin_name "vcgeu"],
+-      All (3, Dreg), "vcge", cmp_sign_matters,
+-      u_8_32;
+-    Vcge, [], All (3, Qreg), "vcgeQ", cmp_sign_matters, F32 :: s_8_32;
+-    Vcge, [Instruction_name ["vcge"]; Builtin_name "vcgeu"],
+-      All (3, Qreg), "vcgeQ", cmp_sign_matters,
+-      u_8_32;
+-
+-    (* Comparison, less-than or equal.  *)
+-    Vcle, [Flipped "vcge"], All (3, Dreg), "vcle", cmp_sign_matters,
+-      F32 :: s_8_32;
+-    Vcle, [Instruction_name ["vcge"]; Flipped "vcgeu"],
+-      All (3, Dreg), "vcle", cmp_sign_matters,
+-      u_8_32;
+-    Vcle, [Instruction_name ["vcge"]; Flipped "vcgeQ"],
+-      All (3, Qreg), "vcleQ", cmp_sign_matters,
+-      F32 :: s_8_32;
+-    Vcle, [Instruction_name ["vcge"]; Flipped "vcgeuQ"],
+-      All (3, Qreg), "vcleQ", cmp_sign_matters,
+-      u_8_32;
+-
+-    (* Comparison, greater-than.  *)
+-    Vcgt, [], All (3, Dreg), "vcgt", cmp_sign_matters, F32 :: s_8_32;
+-    Vcgt, [Instruction_name ["vcgt"]; Builtin_name "vcgtu"],
+-      All (3, Dreg), "vcgt", cmp_sign_matters,
+-      u_8_32;
+-    Vcgt, [], All (3, Qreg), "vcgtQ", cmp_sign_matters, F32 :: s_8_32;
+-    Vcgt, [Instruction_name ["vcgt"]; Builtin_name "vcgtu"],
+-      All (3, Qreg), "vcgtQ", cmp_sign_matters,
+-      u_8_32;
+-
+-    (* Comparison, less-than.  *)
+-    Vclt, [Flipped "vcgt"], All (3, Dreg), "vclt", cmp_sign_matters,
+-      F32 :: s_8_32;
+-    Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtu"],
+-      All (3, Dreg), "vclt", cmp_sign_matters,
+-      u_8_32;
+-    Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtQ"],
+-      All (3, Qreg), "vcltQ", cmp_sign_matters,
+-      F32 :: s_8_32;
+-    Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtuQ"],
+-      All (3, Qreg), "vcltQ", cmp_sign_matters,
+-      u_8_32;
+-
+-    (* Compare absolute greater-than or equal.  *)
+-    Vcage, [Instruction_name ["vacge"]],
+-      All (3, Dreg), "vcage", cmp_sign_matters, [F32];
+-    Vcage, [Instruction_name ["vacge"]],
+-      All (3, Qreg), "vcageQ", cmp_sign_matters, [F32];
+-
+-    (* Compare absolute less-than or equal.  *)
+-    Vcale, [Instruction_name ["vacge"]; Flipped "vcage"],
+-      All (3, Dreg), "vcale", cmp_sign_matters, [F32];
+-    Vcale, [Instruction_name ["vacge"]; Flipped "vcageQ"],
+-      All (3, Qreg), "vcaleQ", cmp_sign_matters, [F32];
+-
+-    (* Compare absolute greater-than or equal.  *)
+-    Vcagt, [Instruction_name ["vacgt"]],
+-      All (3, Dreg), "vcagt", cmp_sign_matters, [F32];
+-    Vcagt, [Instruction_name ["vacgt"]],
+-      All (3, Qreg), "vcagtQ", cmp_sign_matters, [F32];
+-
+-    (* Compare absolute less-than or equal.  *)
+-    Vcalt, [Instruction_name ["vacgt"]; Flipped "vcagt"],
+-      All (3, Dreg), "vcalt", cmp_sign_matters, [F32];
+-    Vcalt, [Instruction_name ["vacgt"]; Flipped "vcagtQ"],
+-      All (3, Qreg), "vcaltQ", cmp_sign_matters, [F32];
+-
+-    (* Test bits.  *)
+-    Vtst, [], All (3, Dreg), "vtst", cmp_bits, P8 :: su_8_32;
+-    Vtst, [], All (3, Qreg), "vtstQ", cmp_bits, P8 :: su_8_32;
+-
+-    (* Absolute difference.  *)
+-    Vabd, [], All (3, Dreg), "vabd", elts_same_2, F32 :: su_8_32;
+-    Vabd, [], All (3, Qreg), "vabdQ", elts_same_2, F32 :: su_8_32;
+-    Vabd, [], Long, "vabdl", elts_same_2, su_8_32;
+-
+-    (* Absolute difference and accumulate.  *)
+-    Vaba, [], All (3, Dreg), "vaba", elts_same_io, su_8_32;
+-    Vaba, [], All (3, Qreg), "vabaQ", elts_same_io, su_8_32;
+-    Vaba, [], Long, "vabal", elts_same_io, su_8_32;
+-
+-    (* Max.  *)
+-    Vmax, [], All (3, Dreg), "vmax", elts_same_2, F32 :: su_8_32;
+-    Vmax, [], All (3, Qreg), "vmaxQ", elts_same_2, F32 :: su_8_32;
+-
+-    (* Min.  *)
+-    Vmin, [], All (3, Dreg), "vmin", elts_same_2, F32 :: su_8_32;
+-    Vmin, [], All (3, Qreg), "vminQ", elts_same_2, F32 :: su_8_32;
+-
+-    (* Pairwise add.  *)
+-    Vpadd, [], All (3, Dreg), "vpadd", sign_invar_2, F32 :: su_8_32;
+-    Vpadd, [], Long_noreg Dreg, "vpaddl", elts_same_1, su_8_32;
+-    Vpadd, [], Long_noreg Qreg, "vpaddlQ", elts_same_1, su_8_32;
+-
+-    (* Pairwise add, widen and accumulate.  *)
+-    Vpada, [], Wide_noreg Dreg, "vpadal", elts_same_2, su_8_32;
+-    Vpada, [], Wide_noreg Qreg, "vpadalQ", elts_same_2, su_8_32;
+-
+-    (* Folding maximum, minimum.  *)
+-    Vpmax, [], All (3, Dreg), "vpmax", elts_same_2, F32 :: su_8_32;
+-    Vpmin, [], All (3, Dreg), "vpmin", elts_same_2, F32 :: su_8_32;
+-
+-    (* Reciprocal step.  *)
+-    Vrecps, [], All (3, Dreg), "vrecps", elts_same_2, [F32];
+-    Vrecps, [], All (3, Qreg), "vrecpsQ", elts_same_2, [F32];
+-    Vrsqrts, [], All (3, Dreg), "vrsqrts", elts_same_2, [F32];
+-    Vrsqrts, [], All (3, Qreg), "vrsqrtsQ", elts_same_2, [F32];
+-
+-    (* Vector shift left.  *)
+-    Vshl, [], All (3, Dreg), "vshl", reg_shift, su_8_64;
+-    Vshl, [], All (3, Qreg), "vshlQ", reg_shift, su_8_64;
+-    Vshl, [Instruction_name ["vrshl"]; Rounding],
+-      All (3, Dreg), "vRshl", reg_shift, su_8_64;
+-    Vshl, [Instruction_name ["vrshl"]; Rounding],
+-      All (3, Qreg), "vRshlQ", reg_shift, su_8_64;
+-    Vshl, [Saturating], All (3, Dreg), "vqshl", reg_shift, su_8_64;
+-    Vshl, [Saturating], All (3, Qreg), "vqshlQ", reg_shift, su_8_64;
+-    Vshl, [Instruction_name ["vqrshl"]; Saturating; Rounding],
+-      All (3, Dreg), "vqRshl", reg_shift, su_8_64;
+-    Vshl, [Instruction_name ["vqrshl"]; Saturating; Rounding],
+-      All (3, Qreg), "vqRshlQ", reg_shift, su_8_64;
+-
+-    (* Vector shift right by constant.  *)
+-    Vshr_n, [], Binary_imm Dreg, "vshr_n", shift_right, su_8_64;
+-    Vshr_n, [], Binary_imm Qreg, "vshrQ_n", shift_right, su_8_64;
+-    Vshr_n, [Instruction_name ["vrshr"]; Rounding], Binary_imm Dreg,
+-      "vRshr_n", shift_right, su_8_64;
+-    Vshr_n, [Instruction_name ["vrshr"]; Rounding], Binary_imm Qreg,
+-      "vRshrQ_n", shift_right, su_8_64;
+-    Vshr_n, [], Narrow_imm, "vshrn_n", shift_right_sign_invar, su_16_64;
+-    Vshr_n, [Instruction_name ["vrshrn"]; Rounding], Narrow_imm, "vRshrn_n",
+-      shift_right_sign_invar, su_16_64;
+-    Vshr_n, [Saturating], Narrow_imm, "vqshrn_n", shift_right, su_16_64;
+-    Vshr_n, [Instruction_name ["vqrshrn"]; Saturating; Rounding], Narrow_imm,
+-      "vqRshrn_n", shift_right, su_16_64;
+-    Vshr_n, [Saturating; Dst_unsign], Narrow_imm, "vqshrun_n",
+-      shift_right_to_uns, [S16; S32; S64];
+-    Vshr_n, [Instruction_name ["vqrshrun"]; Saturating; Dst_unsign; Rounding],
+-      Narrow_imm, "vqRshrun_n", shift_right_to_uns, [S16; S32; S64];
+-
+-    (* Vector shift left by constant.  *)
+-    Vshl_n, [], Binary_imm Dreg, "vshl_n", shift_left_sign_invar, su_8_64;
+-    Vshl_n, [], Binary_imm Qreg, "vshlQ_n", shift_left_sign_invar, su_8_64;
+-    Vshl_n, [Saturating], Binary_imm Dreg, "vqshl_n", shift_left, su_8_64;
+-    Vshl_n, [Saturating], Binary_imm Qreg, "vqshlQ_n", shift_left, su_8_64;
+-    Vshl_n, [Saturating; Dst_unsign], Binary_imm Dreg, "vqshlu_n",
+-      shift_left_to_uns, [S8; S16; S32; S64];
+-    Vshl_n, [Saturating; Dst_unsign], Binary_imm Qreg, "vqshluQ_n",
+-      shift_left_to_uns, [S8; S16; S32; S64];
+-    Vshl_n, [], Long_imm, "vshll_n", shift_left, su_8_32;
+-
+-    (* Vector shift right by constant and accumulate.  *)
+-    Vsra_n, [], Binary_imm Dreg, "vsra_n", shift_right_acc, su_8_64;
+-    Vsra_n, [], Binary_imm Qreg, "vsraQ_n", shift_right_acc, su_8_64;
+-    Vsra_n, [Instruction_name ["vrsra"]; Rounding], Binary_imm Dreg,
+-      "vRsra_n", shift_right_acc, su_8_64;
+-    Vsra_n, [Instruction_name ["vrsra"]; Rounding], Binary_imm Qreg,
+-      "vRsraQ_n", shift_right_acc, su_8_64;
+-
+-    (* Vector shift right and insert.  *)
+-    Vsri, [Requires_feature "CRYPTO"], Use_operands [| Dreg; Dreg; Immed |], "vsri_n", shift_insert,
+-      [P64];
+-    Vsri, [], Use_operands [| Dreg; Dreg; Immed |], "vsri_n", shift_insert,
+-      P8 :: P16 :: su_8_64;
+-    Vsri, [Requires_feature "CRYPTO"], Use_operands [| Qreg; Qreg; Immed |], "vsriQ_n", shift_insert,
+-      [P64];
+-    Vsri, [], Use_operands [| Qreg; Qreg; Immed |], "vsriQ_n", shift_insert,
+-      P8 :: P16 :: su_8_64;
+-
+-    (* Vector shift left and insert.  *)
+-    Vsli, [Requires_feature "CRYPTO"], Use_operands [| Dreg; Dreg; Immed |], "vsli_n", shift_insert,
+-      [P64];
+-    Vsli, [], Use_operands [| Dreg; Dreg; Immed |], "vsli_n", shift_insert,
+-      P8 :: P16 :: su_8_64;
+-    Vsli, [Requires_feature "CRYPTO"], Use_operands [| Qreg; Qreg; Immed |], "vsliQ_n", shift_insert,
+-      [P64];
+-    Vsli, [], Use_operands [| Qreg; Qreg; Immed |], "vsliQ_n", shift_insert,
+-      P8 :: P16 :: su_8_64;
+-
+-    (* Absolute value.  *)
+-    Vabs, [], All (2, Dreg), "vabs", elts_same_1, [S8; S16; S32; F32];
+-    Vabs, [], All (2, Qreg), "vabsQ", elts_same_1, [S8; S16; S32; F32];
+-    Vabs, [Saturating], All (2, Dreg), "vqabs", elts_same_1, [S8; S16; S32];
+-    Vabs, [Saturating], All (2, Qreg), "vqabsQ", elts_same_1, [S8; S16; S32];
+-
+-    (* Negate.  *)
+-    Vneg, [], All (2, Dreg), "vneg", elts_same_1, [S8; S16; S32; F32];
+-    Vneg, [], All (2, Qreg), "vnegQ", elts_same_1, [S8; S16; S32; F32];
+-    Vneg, [Saturating], All (2, Dreg), "vqneg", elts_same_1, [S8; S16; S32];
+-    Vneg, [Saturating], All (2, Qreg), "vqnegQ", elts_same_1, [S8; S16; S32];
+-
+-    (* Bitwise not.  *)
+-    Vmvn, [], All (2, Dreg), "vmvn", notype_1, P8 :: su_8_32;
+-    Vmvn, [], All (2, Qreg), "vmvnQ", notype_1, P8 :: su_8_32;
+-
+-    (* Count leading sign bits.  *)
+-    Vcls, [], All (2, Dreg), "vcls", elts_same_1, [S8; S16; S32];
+-    Vcls, [], All (2, Qreg), "vclsQ", elts_same_1, [S8; S16; S32];
+-
+-    (* Count leading zeros.  *)
+-    Vclz, [], All (2, Dreg), "vclz", sign_invar_1, su_8_32;
+-    Vclz, [], All (2, Qreg), "vclzQ", sign_invar_1, su_8_32;
+-
+-    (* Count number of set bits.  *)
+-    Vcnt, [], All (2, Dreg), "vcnt", bits_1, [P8; S8; U8];
+-    Vcnt, [], All (2, Qreg), "vcntQ", bits_1, [P8; S8; U8];
+-
+-    (* Reciprocal estimate.  *)
+-    Vrecpe, [], All (2, Dreg), "vrecpe", elts_same_1, [U32; F32];
+-    Vrecpe, [], All (2, Qreg), "vrecpeQ", elts_same_1, [U32; F32];
+-
+-    (* Reciprocal square-root estimate.  *)
+-    Vrsqrte, [], All (2, Dreg), "vrsqrte", elts_same_1, [U32; F32];
+-    Vrsqrte, [], All (2, Qreg), "vrsqrteQ", elts_same_1, [U32; F32];
+-
+-    (* Get lanes from a vector.  *)
+-    Vget_lane,
+-      [InfoWord; Disassembles_as [Use_operands [| Corereg; Element_of_dreg |]];
+-       Instruction_name ["vmov"]],
+-      Use_operands [| Corereg; Dreg; Immed |],
+-      "vget_lane", get_lane, pf_su_8_32;
+-    Vget_lane,
+-      [No_op;
+-       InfoWord;
+-       Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]];
+-       Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
+-      Use_operands [| Corereg; Dreg; Immed |],
+-      "vget_lane", notype_2, [S64; U64];
+-    Vget_lane,
+-      [InfoWord; Disassembles_as [Use_operands [| Corereg; Element_of_dreg |]];
+-       Instruction_name ["vmov"]],
+-      Use_operands [| Corereg; Qreg; Immed |],
+-      "vgetQ_lane", get_lane, pf_su_8_32;
+-    Vget_lane,
+-      [InfoWord;
+-       Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]];
+-       Instruction_name ["vmov"; "fmrrd"]; Const_valuator (fun _ -> 0);
+-       Fixed_core_reg],
+-      Use_operands [| Corereg; Qreg; Immed |],
+-      "vgetQ_lane", notype_2, [S64; U64];
+-
+-    (* Set lanes in a vector.  *)
+-    Vset_lane, [Disassembles_as [Use_operands [| Element_of_dreg; Corereg |]];
+-                Instruction_name ["vmov"]],
+-      Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane",
+-      set_lane, pf_su_8_32;
+-    Vset_lane, [No_op;
+-                Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]];
+-                Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
+-      Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane",
+-      set_lane_notype, [S64; U64];
+-    Vset_lane, [Disassembles_as [Use_operands [| Element_of_dreg; Corereg |]];
+-                Instruction_name ["vmov"]],
+-      Use_operands [| Qreg; Corereg; Qreg; Immed |], "vsetQ_lane",
+-      set_lane, pf_su_8_32;
+-    Vset_lane, [Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]];
+-                Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
+-      Use_operands [| Qreg; Corereg; Qreg; Immed |], "vsetQ_lane",
+-      set_lane_notype, [S64; U64];
+-
+-    (* Create vector from literal bit pattern.  *)
+-    Vcreate,
+-      [Requires_feature "CRYPTO"; No_op], (* Not really, but it can yield various things that are too
+-                                   hard for the test generator at this time.  *)
+-      Use_operands [| Dreg; Corereg |], "vcreate", create_vector,
+-      [P64];
+-    Vcreate,
+-      [No_op], (* Not really, but it can yield various things that are too
+-                  hard for the test generator at this time.  *)
+-      Use_operands [| Dreg; Corereg |], "vcreate", create_vector,
+-      pf_su_8_64;
+-
+-    (* Set all lanes to the same value.  *)
+-    Vdup_n,
+-      [Disassembles_as [Use_operands [| Dreg;
+-                                        Alternatives [ Corereg;
+-                                                       Element_of_dreg ] |]]],
+-      Use_operands [| Dreg; Corereg |], "vdup_n", bits_1,
+-      pf_su_8_32;
+-    Vdup_n,
+-      [No_op; Requires_feature "CRYPTO";
+-       Instruction_name ["vmov"];
+-       Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
+-      Use_operands [| Dreg; Corereg |], "vdup_n", notype_1,
+-      [P64];
+-    Vdup_n,
+-      [No_op;
+-       Instruction_name ["vmov"];
+-       Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
+-      Use_operands [| Dreg; Corereg |], "vdup_n", notype_1,
+-      [S64; U64];
+-    Vdup_n,
+-      [No_op; Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| Qreg;
+-                                        Alternatives [ Corereg;
+-                                                       Element_of_dreg ] |]]],
+-      Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1,
+-      [P64];
+-    Vdup_n,
+-      [Disassembles_as [Use_operands [| Qreg;
+-                                        Alternatives [ Corereg;
+-                                                       Element_of_dreg ] |]]],
+-      Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1,
+-      pf_su_8_32;
+-    Vdup_n,
+-      [No_op;
+-       Instruction_name ["vmov"];
+-       Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |];
+-                        Use_operands [| Dreg; Corereg; Corereg |]]],
+-      Use_operands [| Qreg; Corereg |], "vdupQ_n", notype_1,
+-      [S64; U64];
+-
+-    (* These are just aliases for the above.  *)
+-    Vmov_n,
+-      [Builtin_name "vdup_n";
+-       Disassembles_as [Use_operands [| Dreg;
+-                                        Alternatives [ Corereg;
+-                                                       Element_of_dreg ] |]]],
+-      Use_operands [| Dreg; Corereg |],
+-      "vmov_n", bits_1, pf_su_8_32;
+-    Vmov_n,
+-      [No_op;
+-       Builtin_name "vdup_n";
+-       Instruction_name ["vmov"];
+-       Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
+-      Use_operands [| Dreg; Corereg |],
+-      "vmov_n", notype_1, [S64; U64];
+-    Vmov_n,
+-      [Builtin_name "vdupQ_n";
+-       Disassembles_as [Use_operands [| Qreg;
+-                                        Alternatives [ Corereg;
+-                                                       Element_of_dreg ] |]]],
+-      Use_operands [| Qreg; Corereg |],
+-      "vmovQ_n", bits_1, pf_su_8_32;
+-    Vmov_n,
+-      [No_op;
+-       Builtin_name "vdupQ_n";
+-       Instruction_name ["vmov"];
+-       Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |];
+-                        Use_operands [| Dreg; Corereg; Corereg |]]],
+-      Use_operands [| Qreg; Corereg |],
+-      "vmovQ_n", notype_1, [S64; U64];
+-
+-    (* Duplicate, lane version.  We can't use Use_operands here because the
+-       rightmost register (always Dreg) would be picked up by find_key_operand,
+-       when we want the leftmost register to be used in this case (otherwise
+-       the modes are indistinguishable in neon.md, etc.  *)
+-    Vdup_lane,
+-      [Disassembles_as [Use_operands [| Dreg; Element_of_dreg |]]],
+-      Unary_scalar Dreg, "vdup_lane", bits_2, pf_su_8_32;
+-    Vdup_lane,
+-      [No_op; Requires_feature "CRYPTO"; Const_valuator (fun _ -> 0)],
+-      Unary_scalar Dreg, "vdup_lane", bits_2, [P64];
+-    Vdup_lane,
+-      [No_op; Const_valuator (fun _ -> 0)],
+-      Unary_scalar Dreg, "vdup_lane", bits_2, [S64; U64];
+-    Vdup_lane,
+-      [Disassembles_as [Use_operands [| Qreg; Element_of_dreg |]]],
+-      Unary_scalar Qreg, "vdupQ_lane", bits_2, pf_su_8_32;
+-    Vdup_lane,
+-      [No_op; Requires_feature "CRYPTO"; Const_valuator (fun _ -> 0)],
+-      Unary_scalar Qreg, "vdupQ_lane", bits_2, [P64];
+-    Vdup_lane,
+-      [No_op; Const_valuator (fun _ -> 0)],
+-      Unary_scalar Qreg, "vdupQ_lane", bits_2, [S64; U64];
+-
+-    (* Combining vectors.  *)
+-    Vcombine, [Requires_feature "CRYPTO"; No_op],
+-      Use_operands [| Qreg; Dreg; Dreg |], "vcombine", notype_2,
+-      [P64];
+-    Vcombine, [No_op],
+-      Use_operands [| Qreg; Dreg; Dreg |], "vcombine", notype_2,
+-      pf_su_8_64;
+-
+-    (* Splitting vectors.  *)
+-    Vget_high, [Requires_feature "CRYPTO"; No_op],
+-      Use_operands [| Dreg; Qreg |], "vget_high",
+-      notype_1, [P64];
+-    Vget_high, [No_op],
+-      Use_operands [| Dreg; Qreg |], "vget_high",
+-      notype_1, pf_su_8_64;
+-    Vget_low, [Instruction_name ["vmov"];
+-               Disassembles_as [Use_operands [| Dreg; Dreg |]];
+-	       Fixed_vector_reg],
+-      Use_operands [| Dreg; Qreg |], "vget_low",
+-      notype_1, pf_su_8_32;
+-    Vget_low, [Requires_feature "CRYPTO"; No_op],
+-      Use_operands [| Dreg; Qreg |], "vget_low",
+-      notype_1, [P64];
+-    Vget_low, [No_op],
+-      Use_operands [| Dreg; Qreg |], "vget_low",
+-      notype_1, [S64; U64];
+-
+-    (* Conversions.  *)
+-    Vcvt, [InfoWord], All (2, Dreg), "vcvt", conv_1,
+-      [Conv (S32, F32); Conv (U32, F32); Conv (F32, S32); Conv (F32, U32)];
+-    Vcvt, [InfoWord], All (2, Qreg), "vcvtQ", conv_1,
+-      [Conv (S32, F32); Conv (U32, F32); Conv (F32, S32); Conv (F32, U32)];
+-    Vcvt, [Builtin_name "vcvt" ; Requires_FP_bit 1],
+-          Use_operands [| Dreg; Qreg; |], "vcvt", conv_1, [Conv (F16, F32)];
+-    Vcvt, [Builtin_name "vcvt" ; Requires_FP_bit 1],
+-          Use_operands [| Qreg; Dreg; |], "vcvt", conv_1, [Conv (F32, F16)];
+-    Vcvt_n, [InfoWord], Use_operands [| Dreg; Dreg; Immed |], "vcvt_n", conv_2,
+-      [Conv (S32, F32); Conv (U32, F32); Conv (F32, S32); Conv (F32, U32)];
+-    Vcvt_n, [InfoWord], Use_operands [| Qreg; Qreg; Immed |], "vcvtQ_n", conv_2,
+-      [Conv (S32, F32); Conv (U32, F32); Conv (F32, S32); Conv (F32, U32)];
+-
+-    (* Move, narrowing.  *)
+-    Vmovn, [Disassembles_as [Use_operands [| Dreg; Qreg |]]],
+-      Narrow, "vmovn", sign_invar_1, su_16_64;
+-    Vmovn, [Disassembles_as [Use_operands [| Dreg; Qreg |]]; Saturating],
+-      Narrow, "vqmovn", elts_same_1, su_16_64;
+-    Vmovn,
+-      [Disassembles_as [Use_operands [| Dreg; Qreg |]]; Saturating; Dst_unsign],
+-      Narrow, "vqmovun", dst_unsign_1,
+-      [S16; S32; S64];
+-
+-    (* Move, long.  *)
+-    Vmovl, [Disassembles_as [Use_operands [| Qreg; Dreg |]]],
+-      Long, "vmovl", elts_same_1, su_8_32;
+-
+-    (* Table lookup.  *)
+-    Vtbl 1,
+-      [Instruction_name ["vtbl"];
+-       Disassembles_as [Use_operands [| Dreg; VecArray (1, Dreg); Dreg |]]],
+-      Use_operands [| Dreg; Dreg; Dreg |], "vtbl1", table_2, [U8; S8; P8];
+-    Vtbl 2, [Instruction_name ["vtbl"]],
+-      Use_operands [| Dreg; VecArray (2, Dreg); Dreg |], "vtbl2", table_2,
+-      [U8; S8; P8];
+-    Vtbl 3, [Instruction_name ["vtbl"]],
+-      Use_operands [| Dreg; VecArray (3, Dreg); Dreg |], "vtbl3", table_2,
+-      [U8; S8; P8];
+-    Vtbl 4, [Instruction_name ["vtbl"]],
+-      Use_operands [| Dreg; VecArray (4, Dreg); Dreg |], "vtbl4", table_2,
+-      [U8; S8; P8];
+-
+-    (* Extended table lookup.  *)
+-    Vtbx 1,
+-      [Instruction_name ["vtbx"];
+-       Disassembles_as [Use_operands [| Dreg; VecArray (1, Dreg); Dreg |]]],
+-      Use_operands [| Dreg; Dreg; Dreg |], "vtbx1", table_io, [U8; S8; P8];
+-    Vtbx 2, [Instruction_name ["vtbx"]],
+-      Use_operands [| Dreg; VecArray (2, Dreg); Dreg |], "vtbx2", table_io,
+-      [U8; S8; P8];
+-    Vtbx 3, [Instruction_name ["vtbx"]],
+-      Use_operands [| Dreg; VecArray (3, Dreg); Dreg |], "vtbx3", table_io,
+-      [U8; S8; P8];
+-    Vtbx 4, [Instruction_name ["vtbx"]],
+-      Use_operands [| Dreg; VecArray (4, Dreg); Dreg |], "vtbx4", table_io,
+-      [U8; S8; P8];
+-
+-    (* Multiply, lane.  (note: these were undocumented at the time of
+-       writing).  *)
+-    Vmul_lane, [], By_scalar Dreg, "vmul_lane", sign_invar_2_lane,
+-      [S16; S32; U16; U32; F32];
+-    Vmul_lane, [], By_scalar Qreg, "vmulQ_lane", sign_invar_2_lane,
+-      [S16; S32; U16; U32; F32];
+-
+-    (* Multiply-accumulate, lane.  *)
+-    Vmla_lane, [], By_scalar Dreg, "vmla_lane", sign_invar_io_lane,
+-      [S16; S32; U16; U32; F32];
+-    Vmla_lane, [], By_scalar Qreg, "vmlaQ_lane", sign_invar_io_lane,
+-      [S16; S32; U16; U32; F32];
+-    Vmla_lane, [], Wide_lane, "vmlal_lane", elts_same_io_lane,
+-      [S16; S32; U16; U32];
+-    Vmla_lane, [Saturating; Doubling], Wide_lane, "vqdmlal_lane",
+-      elts_same_io_lane, [S16; S32];
+-
+-    (* Multiply-subtract, lane.  *)
+-    Vmls_lane, [], By_scalar Dreg, "vmls_lane", sign_invar_io_lane,
+-      [S16; S32; U16; U32; F32];
+-    Vmls_lane, [], By_scalar Qreg, "vmlsQ_lane", sign_invar_io_lane,
+-      [S16; S32; U16; U32; F32];
+-    Vmls_lane, [], Wide_lane, "vmlsl_lane", elts_same_io_lane,
+-      [S16; S32; U16; U32];
+-    Vmls_lane, [Saturating; Doubling], Wide_lane, "vqdmlsl_lane",
+-      elts_same_io_lane, [S16; S32];
+-
+-    (* Long multiply, lane.  *)
+-    Vmull_lane, [],
+-      Wide_lane, "vmull_lane", elts_same_2_lane, [S16; S32; U16; U32];
+-
+-    (* Saturating doubling long multiply, lane.  *)
+-    Vqdmull_lane, [Saturating; Doubling],
+-      Wide_lane, "vqdmull_lane", elts_same_2_lane, [S16; S32];
+-
+-    (* Saturating doubling long multiply high, lane.  *)
+-    Vqdmulh_lane, [Saturating; Halving],
+-      By_scalar Qreg, "vqdmulhQ_lane", elts_same_2_lane, [S16; S32];
+-    Vqdmulh_lane, [Saturating; Halving],
+-      By_scalar Dreg, "vqdmulh_lane", elts_same_2_lane, [S16; S32];
+-    Vqdmulh_lane, [Saturating; Halving; Rounding;
+-		   Instruction_name ["vqrdmulh"]],
+-      By_scalar Qreg, "vqRdmulhQ_lane", elts_same_2_lane, [S16; S32];
+-    Vqdmulh_lane, [Saturating; Halving; Rounding;
+-		   Instruction_name ["vqrdmulh"]],
+-      By_scalar Dreg, "vqRdmulh_lane", elts_same_2_lane, [S16; S32];
+-
+-    (* Vector multiply by scalar.  *)
+-    Vmul_n, [InfoWord;
+-             Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]],
+-             Use_operands [| Dreg; Dreg; Corereg |], "vmul_n",
+-      sign_invar_2, [S16; S32; U16; U32; F32];
+-    Vmul_n, [InfoWord;
+-             Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]],
+-             Use_operands [| Qreg; Qreg; Corereg |], "vmulQ_n",
+-      sign_invar_2, [S16; S32; U16; U32; F32];
+-
+-    (* Vector long multiply by scalar.  *)
+-    Vmull_n, [Instruction_name ["vmull"];
+-              Disassembles_as [Use_operands [| Qreg; Dreg; Element_of_dreg |]]],
+-              Wide_scalar, "vmull_n",
+-      elts_same_2, [S16; S32; U16; U32];
+-
+-    (* Vector saturating doubling long multiply by scalar.  *)
+-    Vqdmull_n, [Saturating; Doubling;
+-	        Disassembles_as [Use_operands [| Qreg; Dreg;
+-						 Element_of_dreg |]]],
+-                Wide_scalar, "vqdmull_n",
+-      elts_same_2, [S16; S32];
+-
+-    (* Vector saturating doubling long multiply high by scalar.  *)
+-    Vqdmulh_n,
+-      [Saturating; Halving; InfoWord;
+-       Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]],
+-      Use_operands [| Qreg; Qreg; Corereg |],
+-      "vqdmulhQ_n", elts_same_2, [S16; S32];
+-    Vqdmulh_n,
+-      [Saturating; Halving; InfoWord;
+-       Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]],
+-      Use_operands [| Dreg; Dreg; Corereg |],
+-      "vqdmulh_n", elts_same_2, [S16; S32];
+-    Vqdmulh_n,
+-      [Saturating; Halving; Rounding; InfoWord;
+-       Instruction_name ["vqrdmulh"];
+-       Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]],
+-      Use_operands [| Qreg; Qreg; Corereg |],
+-      "vqRdmulhQ_n", elts_same_2, [S16; S32];
+-    Vqdmulh_n,
+-      [Saturating; Halving; Rounding; InfoWord;
+-       Instruction_name ["vqrdmulh"];
+-       Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]],
+-      Use_operands [| Dreg; Dreg; Corereg |],
+-      "vqRdmulh_n", elts_same_2, [S16; S32];
+-
+-    (* Vector multiply-accumulate by scalar.  *)
+-    Vmla_n, [InfoWord;
+-             Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]],
+-      Use_operands [| Dreg; Dreg; Corereg |], "vmla_n",
+-      sign_invar_io, [S16; S32; U16; U32; F32];
+-    Vmla_n, [InfoWord;
+-             Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]],
+-      Use_operands [| Qreg; Qreg; Corereg |], "vmlaQ_n",
+-      sign_invar_io, [S16; S32; U16; U32; F32];
+-    Vmla_n, [], Wide_scalar, "vmlal_n", elts_same_io, [S16; S32; U16; U32];
+-    Vmla_n, [Saturating; Doubling], Wide_scalar, "vqdmlal_n", elts_same_io,
+-      [S16; S32];
+-
+-    (* Vector multiply subtract by scalar.  *)
+-    Vmls_n, [InfoWord;
+-             Disassembles_as [Use_operands [| Dreg; Dreg; Element_of_dreg |]]],
+-      Use_operands [| Dreg; Dreg; Corereg |], "vmls_n",
+-      sign_invar_io, [S16; S32; U16; U32; F32];
+-    Vmls_n, [InfoWord;
+-             Disassembles_as [Use_operands [| Qreg; Qreg; Element_of_dreg |]]],
+-      Use_operands [| Qreg; Qreg; Corereg |], "vmlsQ_n",
+-      sign_invar_io, [S16; S32; U16; U32; F32];
+-    Vmls_n, [], Wide_scalar, "vmlsl_n", elts_same_io, [S16; S32; U16; U32];
+-    Vmls_n, [Saturating; Doubling], Wide_scalar, "vqdmlsl_n", elts_same_io,
+-      [S16; S32];
+-
+-    (* Vector extract.  *)
+-    Vext, [Requires_feature "CRYPTO"; Const_valuator (fun _ -> 0)],
+-      Use_operands [| Dreg; Dreg; Dreg; Immed |], "vext", extend,
+-      [P64];
+-    Vext, [Const_valuator (fun _ -> 0)],
+-      Use_operands [| Dreg; Dreg; Dreg; Immed |], "vext", extend,
+-      pf_su_8_64;
+-    Vext, [Requires_feature "CRYPTO"; Const_valuator (fun _ -> 0)],
+-      Use_operands [| Qreg; Qreg; Qreg; Immed |], "vextQ", extend,
+-      [P64];
+-    Vext, [Const_valuator (fun _ -> 0)],
+-      Use_operands [| Qreg; Qreg; Qreg; Immed |], "vextQ", extend,
+-      pf_su_8_64;
+-
+-    (* Reverse elements.  *)
+-    Vrev64, [Use_shuffle (rev_elems 64)], All (2, Dreg), "vrev64", bits_1,
+-      P8 :: P16 :: F32 :: su_8_32;
+-    Vrev64, [Use_shuffle (rev_elems 64)], All (2, Qreg), "vrev64Q", bits_1,
+-      P8 :: P16 :: F32 :: su_8_32;
+-    Vrev32, [Use_shuffle (rev_elems 32)], All (2, Dreg), "vrev32", bits_1,
+-      [P8; P16; S8; U8; S16; U16];
+-    Vrev32, [Use_shuffle (rev_elems 32)], All (2, Qreg), "vrev32Q", bits_1,
+-      [P8; P16; S8; U8; S16; U16];
+-    Vrev16, [Use_shuffle (rev_elems 16)], All (2, Dreg), "vrev16", bits_1,
+-      [P8; S8; U8];
+-    Vrev16, [Use_shuffle (rev_elems 16)], All (2, Qreg), "vrev16Q", bits_1,
+-      [P8; S8; U8];
+-
+-    (* Bit selection.  *)
+-    Vbsl,
+-      [Requires_feature "CRYPTO"; Instruction_name ["vbsl"; "vbit"; "vbif"];
+-       Disassembles_as [Use_operands [| Dreg; Dreg; Dreg |]]],
+-      Use_operands [| Dreg; Dreg; Dreg; Dreg |], "vbsl", bit_select,
+-      [P64];
+-    Vbsl,
+-      [Instruction_name ["vbsl"; "vbit"; "vbif"];
+-       Disassembles_as [Use_operands [| Dreg; Dreg; Dreg |]]],
+-      Use_operands [| Dreg; Dreg; Dreg; Dreg |], "vbsl", bit_select,
+-      pf_su_8_64;
+-    Vbsl,
+-      [Requires_feature "CRYPTO"; Instruction_name ["vbsl"; "vbit"; "vbif"];
+-       Disassembles_as [Use_operands [| Qreg; Qreg; Qreg |]]],
+-      Use_operands [| Qreg; Qreg; Qreg; Qreg |], "vbslQ", bit_select,
+-      [P64];
+-    Vbsl,
+-      [Instruction_name ["vbsl"; "vbit"; "vbif"];
+-       Disassembles_as [Use_operands [| Qreg; Qreg; Qreg |]]],
+-      Use_operands [| Qreg; Qreg; Qreg; Qreg |], "vbslQ", bit_select,
+-      pf_su_8_64;
+-
+-    Vtrn, [Use_shuffle trn_elems], Pair_result Dreg, "vtrn", bits_2, pf_su_8_16;
+-    Vtrn, [Use_shuffle trn_elems; Instruction_name ["vuzp"]], Pair_result Dreg, "vtrn", bits_2, suf_32;
+-    Vtrn, [Use_shuffle trn_elems], Pair_result Qreg, "vtrnQ", bits_2, pf_su_8_32;
+-    (* Zip elements.  *)
+-    Vzip, [Use_shuffle zip_elems], Pair_result Dreg, "vzip", bits_2, pf_su_8_16;
+-    Vzip, [Use_shuffle zip_elems; Instruction_name ["vuzp"]], Pair_result Dreg, "vzip", bits_2, suf_32;
+-    Vzip, [Use_shuffle zip_elems], Pair_result Qreg, "vzipQ", bits_2, pf_su_8_32; 
+-
+-    (* Unzip elements.  *)
+-    Vuzp, [Use_shuffle uzip_elems], Pair_result Dreg, "vuzp", bits_2,
+-      pf_su_8_32;
+-    Vuzp, [Use_shuffle uzip_elems], Pair_result Qreg, "vuzpQ", bits_2,
+-      pf_su_8_32;
+-
+-    (* Element/structure loads.  VLD1 variants.  *)
+-    Vldx 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Dreg; CstPtrTo Corereg |], "vld1", bits_1,
+-      [P64];
+-    Vldx 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Dreg; CstPtrTo Corereg |], "vld1", bits_1,
+-      pf_su_8_64;
+-    Vldx 1, [Requires_feature "CRYPTO";
+-             Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-					      CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg |], "vld1Q", bits_1,
+-      [P64];
+-    Vldx 1, [Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-					      CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg |], "vld1Q", bits_1,
+-      pf_su_8_64;
+-
+-    Vldx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Element_of_dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Dreg; CstPtrTo Corereg; Dreg; Immed |],
+-      "vld1_lane", bits_3, pf_su_8_32;
+-    Vldx_lane 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]];
+-       Const_valuator (fun _ -> 0)],
+-      Use_operands [| Dreg; CstPtrTo Corereg; Dreg; Immed |],
+-      "vld1_lane", bits_3, [P64];
+-    Vldx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]];
+-       Const_valuator (fun _ -> 0)],
+-      Use_operands [| Dreg; CstPtrTo Corereg; Dreg; Immed |],
+-      "vld1_lane", bits_3, [S64; U64];
+-    Vldx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Element_of_dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg; Qreg; Immed |],
+-      "vld1Q_lane", bits_3, pf_su_8_32;
+-    Vldx_lane 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg; Qreg; Immed |],
+-      "vld1Q_lane", bits_3, [P64];
+-    Vldx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg; Qreg; Immed |],
+-      "vld1Q_lane", bits_3, [S64; U64];
+-
+-    Vldx_dup 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, All_elements_of_dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Dreg; CstPtrTo Corereg |], "vld1_dup",
+-      bits_1, pf_su_8_32;
+-    Vldx_dup 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Dreg; CstPtrTo Corereg |], "vld1_dup",
+-      bits_1, [P64];
+-    Vldx_dup 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Dreg; CstPtrTo Corereg |], "vld1_dup",
+-      bits_1, [S64; U64];
+-    Vldx_dup 1,
+-      [Disassembles_as [Use_operands [| VecArray (2, All_elements_of_dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg |], "vld1Q_dup",
+-      bits_1, pf_su_8_32;
+-    (* Treated identically to vld1_dup above as we now
+-       do a single load followed by a duplicate.  *)
+-    Vldx_dup 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg |], "vld1Q_dup",
+-      bits_1, [P64];
+-    Vldx_dup 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| Qreg; CstPtrTo Corereg |], "vld1Q_dup",
+-      bits_1, [S64; U64];
+-
+-    (* VST1 variants.  *)
+-    Vstx 1, [Requires_feature "CRYPTO";
+-             Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                              PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Dreg |], "vst1",
+-      store_1, [P64];
+-    Vstx 1, [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                              PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Dreg |], "vst1",
+-      store_1, pf_su_8_64;
+-    Vstx 1, [Requires_feature "CRYPTO";
+-             Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-					      PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Qreg |], "vst1Q",
+-      store_1, [P64];
+-    Vstx 1, [Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-					      PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Qreg |], "vst1Q",
+-      store_1, pf_su_8_64;
+-
+-    Vstx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Element_of_dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Dreg; Immed |],
+-      "vst1_lane", store_3, pf_su_8_32;
+-    Vstx_lane 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]];
+-       Const_valuator (fun _ -> 0)],
+-      Use_operands [| PtrTo Corereg; Dreg; Immed |],
+-      "vst1_lane", store_3, [P64];
+-    Vstx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]];
+-       Const_valuator (fun _ -> 0)],
+-      Use_operands [| PtrTo Corereg; Dreg; Immed |],
+-      "vst1_lane", store_3, [U64; S64];
+-    Vstx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Element_of_dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Qreg; Immed |],
+-      "vst1Q_lane", store_3, pf_su_8_32;
+-    Vstx_lane 1,
+-      [Requires_feature "CRYPTO";
+-       Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Qreg; Immed |],
+-      "vst1Q_lane", store_3, [P64];
+-    Vstx_lane 1,
+-      [Disassembles_as [Use_operands [| VecArray (1, Dreg);
+-                                        CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; Qreg; Immed |],
+-      "vst1Q_lane", store_3, [U64; S64];
+-
+-    (* VLD2 variants.  *)
+-    Vldx 2, [], Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |],
+-      "vld2", bits_1, pf_su_8_32;
+-    Vldx 2, [Requires_feature "CRYPTO"; Instruction_name ["vld1"]],
+-       Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |],
+-      "vld2", bits_1, [P64];
+-    Vldx 2, [Instruction_name ["vld1"]],
+-       Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |],
+-      "vld2", bits_1, [S64; U64];
+-    Vldx 2, [Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-                                              CstPtrTo Corereg |];
+-                              Use_operands [| VecArray (2, Dreg);
+-					      CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (2, Qreg); CstPtrTo Corereg |],
+-      "vld2Q", bits_1, pf_su_8_32;
+-
+-    Vldx_lane 2,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (2, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg;
+-                      VecArray (2, Dreg); Immed |],
+-      "vld2_lane", bits_3, P8 :: P16 :: F32 :: su_8_32;
+-    Vldx_lane 2,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (2, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (2, Qreg); CstPtrTo Corereg;
+- 	              VecArray (2, Qreg); Immed |],
+-      "vld2Q_lane", bits_3, [P16; F32; U16; U32; S16; S32];
+-
+-    Vldx_dup 2,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (2, All_elements_of_dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |],
+-      "vld2_dup", bits_1, pf_su_8_32;
+-    Vldx_dup 2,
+-      [Requires_feature "CRYPTO";
+-       Instruction_name ["vld1"]; Disassembles_as [Use_operands
+-        [| VecArray (2, Dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |],
+-      "vld2_dup", bits_1, [P64];
+-    Vldx_dup 2,
+-      [Instruction_name ["vld1"]; Disassembles_as [Use_operands
+-        [| VecArray (2, Dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (2, Dreg); CstPtrTo Corereg |],
+-      "vld2_dup", bits_1, [S64; U64];
+-
+-    (* VST2 variants.  *)
+-    Vstx 2, [Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-                                              PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (2, Dreg) |], "vst2",
+-      store_1, pf_su_8_32;
+-    Vstx 2, [Requires_feature "CRYPTO";
+-             Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-                                              PtrTo Corereg |]];
+-             Instruction_name ["vst1"]],
+-      Use_operands [| PtrTo Corereg; VecArray (2, Dreg) |], "vst2",
+-      store_1, [P64];
+-    Vstx 2, [Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-                                              PtrTo Corereg |]];
+-             Instruction_name ["vst1"]],
+-      Use_operands [| PtrTo Corereg; VecArray (2, Dreg) |], "vst2",
+-      store_1, [S64; U64];
+-    Vstx 2, [Disassembles_as [Use_operands [| VecArray (2, Dreg);
+-					      PtrTo Corereg |];
+-                              Use_operands [| VecArray (2, Dreg);
+-				              PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (2, Qreg) |], "vst2Q",
+-      store_1, pf_su_8_32;
+-
+-    Vstx_lane 2,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (2, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (2, Dreg); Immed |], "vst2_lane",
+-      store_3, P8 :: P16 :: F32 :: su_8_32;
+-    Vstx_lane 2,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (2, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (2, Qreg); Immed |], "vst2Q_lane",
+-      store_3, [P16; F32; U16; U32; S16; S32];
+-
+-    (* VLD3 variants.  *)
+-    Vldx 3, [], Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |],
+-      "vld3", bits_1, pf_su_8_32;
+-    Vldx 3, [Requires_feature "CRYPTO"; Instruction_name ["vld1"]],
+-      Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |],
+-      "vld3", bits_1, [P64];
+-    Vldx 3, [Instruction_name ["vld1"]],
+-      Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |],
+-      "vld3", bits_1, [S64; U64];
+-    Vldx 3, [Disassembles_as [Use_operands [| VecArray (3, Dreg);
+-					      CstPtrTo Corereg |];
+-                              Use_operands [| VecArray (3, Dreg);
+-					      CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (3, Qreg); CstPtrTo Corereg |],
+-      "vld3Q", bits_1, P8 :: P16 :: F32 :: su_8_32;
+-
+-    Vldx_lane 3,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (3, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg;
+-                                     VecArray (3, Dreg); Immed |],
+-      "vld3_lane", bits_3, P8 :: P16 :: F32 :: su_8_32;
+-    Vldx_lane 3,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (3, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (3, Qreg); CstPtrTo Corereg;
+-				     VecArray (3, Qreg); Immed |],
+-      "vld3Q_lane", bits_3, [P16; F32; U16; U32; S16; S32];
+-
+-    Vldx_dup 3,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (3, All_elements_of_dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |],
+-      "vld3_dup", bits_1, pf_su_8_32;
+-    Vldx_dup 3,
+-      [Requires_feature "CRYPTO";
+-       Instruction_name ["vld1"]; Disassembles_as [Use_operands
+-        [| VecArray (3, Dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |],
+-      "vld3_dup", bits_1, [P64];
+-    Vldx_dup 3,
+-      [Instruction_name ["vld1"]; Disassembles_as [Use_operands
+-        [| VecArray (3, Dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (3, Dreg); CstPtrTo Corereg |],
+-      "vld3_dup", bits_1, [S64; U64];
+-
+-    (* VST3 variants.  *)
+-    Vstx 3, [Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-                                              PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (3, Dreg) |], "vst3",
+-      store_1, pf_su_8_32;
+-    Vstx 3, [Requires_feature "CRYPTO";
+-             Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-                                              PtrTo Corereg |]];
+-             Instruction_name ["vst1"]],
+-      Use_operands [| PtrTo Corereg; VecArray (3, Dreg) |], "vst3",
+-      store_1, [P64];
+-    Vstx 3, [Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-                                              PtrTo Corereg |]];
+-             Instruction_name ["vst1"]],
+-      Use_operands [| PtrTo Corereg; VecArray (3, Dreg) |], "vst3",
+-      store_1, [S64; U64];
+-    Vstx 3, [Disassembles_as [Use_operands [| VecArray (3, Dreg);
+-					      PtrTo Corereg |];
+-                              Use_operands [| VecArray (3, Dreg);
+-					      PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (3, Qreg) |], "vst3Q",
+-      store_1, pf_su_8_32;
+-
+-    Vstx_lane 3,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (3, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (3, Dreg); Immed |], "vst3_lane",
+-      store_3, P8 :: P16 :: F32 :: su_8_32;
+-    Vstx_lane 3,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (3, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (3, Qreg); Immed |], "vst3Q_lane",
+-      store_3, [P16; F32; U16; U32; S16; S32];
+-
+-    (* VLD4/VST4 variants.  *)
+-    Vldx 4, [], Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |],
+-      "vld4", bits_1, pf_su_8_32;
+-    Vldx 4, [Requires_feature "CRYPTO"; Instruction_name ["vld1"]],
+-      Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |],
+-      "vld4", bits_1, [P64];
+-    Vldx 4, [Instruction_name ["vld1"]],
+-      Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |],
+-      "vld4", bits_1, [S64; U64];
+-    Vldx 4, [Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-					      CstPtrTo Corereg |];
+-                              Use_operands [| VecArray (4, Dreg);
+-					      CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (4, Qreg); CstPtrTo Corereg |],
+-      "vld4Q", bits_1, P8 :: P16 :: F32 :: su_8_32;
+-
+-    Vldx_lane 4,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (4, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg;
+-                                     VecArray (4, Dreg); Immed |],
+-      "vld4_lane", bits_3, P8 :: P16 :: F32 :: su_8_32;
+-    Vldx_lane 4,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (4, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (4, Qreg); CstPtrTo Corereg;
+-   	              VecArray (4, Qreg); Immed |],
+-      "vld4Q_lane", bits_3, [P16; F32; U16; U32; S16; S32];
+-
+-    Vldx_dup 4,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (4, All_elements_of_dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |],
+-      "vld4_dup", bits_1, pf_su_8_32;
+-    Vldx_dup 4,
+-      [Requires_feature "CRYPTO";
+-       Instruction_name ["vld1"]; Disassembles_as [Use_operands
+-        [| VecArray (4, Dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |],
+-      "vld4_dup", bits_1, [P64];
+-    Vldx_dup 4,
+-      [Instruction_name ["vld1"]; Disassembles_as [Use_operands
+-        [| VecArray (4, Dreg); CstPtrTo Corereg |]]],
+-      Use_operands [| VecArray (4, Dreg); CstPtrTo Corereg |],
+-      "vld4_dup", bits_1, [S64; U64];
+-
+-    Vstx 4, [Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-                                              PtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (4, Dreg) |], "vst4",
+-      store_1, pf_su_8_32;
+-    Vstx 4, [Requires_feature "CRYPTO";
+-             Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-                                              PtrTo Corereg |]];
+-             Instruction_name ["vst1"]],
+-      Use_operands [| PtrTo Corereg; VecArray (4, Dreg) |], "vst4",
+-      store_1, [P64];
+-    Vstx 4, [Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-                                              PtrTo Corereg |]];
+-             Instruction_name ["vst1"]],
+-      Use_operands [| PtrTo Corereg; VecArray (4, Dreg) |], "vst4",
+-      store_1, [S64; U64];
+-    Vstx 4, [Disassembles_as [Use_operands [| VecArray (4, Dreg);
+-					      PtrTo Corereg |];
+-                              Use_operands [| VecArray (4, Dreg);
+-					      PtrTo Corereg |]]],
+-     Use_operands [| PtrTo Corereg; VecArray (4, Qreg) |], "vst4Q",
+-      store_1, pf_su_8_32;
+-
+-    Vstx_lane 4,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (4, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (4, Dreg); Immed |], "vst4_lane",
+-      store_3, P8 :: P16 :: F32 :: su_8_32;
+-    Vstx_lane 4,
+-      [Disassembles_as [Use_operands
+-        [| VecArray (4, Element_of_dreg);
+-           CstPtrTo Corereg |]]],
+-      Use_operands [| PtrTo Corereg; VecArray (4, Qreg); Immed |], "vst4Q_lane",
+-      store_3, [P16; F32; U16; U32; S16; S32];
+-
+-    (* Logical operations. And.  *)
+-    Vand, [], All (3, Dreg), "vand", notype_2, su_8_32;
+-    Vand, [No_op], All (3, Dreg), "vand", notype_2, [S64; U64];
+-    Vand, [], All (3, Qreg), "vandQ", notype_2, su_8_64;
+-
+-    (* Or.  *)
+-    Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_32;
+-    Vorr, [No_op], All (3, Dreg), "vorr", notype_2, [S64; U64];
+-    Vorr, [], All (3, Qreg), "vorrQ", notype_2, su_8_64;
+-
+-    (* Eor.  *)
+-    Veor, [], All (3, Dreg), "veor", notype_2, su_8_32;
+-    Veor, [No_op], All (3, Dreg), "veor", notype_2, [S64; U64];
+-    Veor, [], All (3, Qreg), "veorQ", notype_2, su_8_64;
+-
+-    (* Bic (And-not).  *)
+-    Vbic, [Compiler_optim "-O2"], All (3, Dreg), "vbic", notype_2, su_8_32;
+-    Vbic, [No_op; Compiler_optim "-O2"], All (3, Dreg), "vbic", notype_2, [S64; U64];
+-    Vbic, [Compiler_optim "-O2"], All (3, Qreg), "vbicQ", notype_2, su_8_64;
+-
+-    (* Or-not.  *)
+-    Vorn, [Compiler_optim "-O2"], All (3, Dreg), "vorn", notype_2, su_8_32;
+-    Vorn, [No_op; Compiler_optim "-O2"], All (3, Dreg), "vorn", notype_2, [S64; U64];
+-    Vorn, [Compiler_optim "-O2"], All (3, Qreg), "vornQ", notype_2, su_8_64;
+-  ]
+-
+-let type_in_crypto_only t
+-  = (t == P64) || (t == P128)
+-
+-let cross_product s1 s2
+-  = List.filter (fun (e, e') -> e <> e')
+-                (List.concat (List.map (fun e1 -> List.map (fun e2 -> (e1,e2)) s1) s2))
+-
+-let reinterp =
+-  let elems = P8 :: P16 :: F32 :: P64 :: su_8_64 in
+-  let casts = cross_product elems elems in
+-  List.map
+-    (fun (convto, convfrom) ->
+-       Vreinterp, (if (type_in_crypto_only convto) || (type_in_crypto_only convfrom)
+-                   then [Requires_feature "CRYPTO"] else []) @ [No_op], Use_operands [| Dreg; Dreg |],
+-                   "vreinterpret", conv_1, [Cast (convto, convfrom)])
+-    casts
+-
+-let reinterpq =
+-  let elems = P8 :: P16 :: F32 :: P64 :: P128 :: su_8_64 in
+-  let casts = cross_product elems elems in
+-  List.map
+-    (fun (convto, convfrom) ->
+-       Vreinterp, (if (type_in_crypto_only convto) || (type_in_crypto_only convfrom)
+-                   then [Requires_feature "CRYPTO"] else []) @ [No_op], Use_operands [| Qreg; Qreg |],
+-                   "vreinterpretQ", conv_1, [Cast (convto, convfrom)])
+-    casts
+-
+-(* Output routines.  *)
+-
+-let rec string_of_elt = function
+-    S8 -> "s8" | S16 -> "s16" | S32 -> "s32" | S64 -> "s64"
+-  | U8 -> "u8" | U16 -> "u16" | U32 -> "u32" | U64 -> "u64"
+-  | I8 -> "i8" | I16 -> "i16" | I32 -> "i32" | I64 -> "i64"
+-  | B8 -> "8" | B16 -> "16" | B32 -> "32" | B64 -> "64"
+-  | F16 -> "f16" | F32 -> "f32" | P8 -> "p8" | P16 -> "p16"
+-  | P64 -> "p64" | P128 -> "p128"
+-  | Conv (a, b) | Cast (a, b) -> string_of_elt a ^ "_" ^ string_of_elt b
+-  | NoElts -> failwith "No elts"
+-
+-let string_of_elt_dots elt =
+-  match elt with
+-    Conv (a, b) | Cast (a, b) -> string_of_elt a ^ "." ^ string_of_elt b
+-  | _ -> string_of_elt elt
+-
+-let string_of_vectype vt =
+-  let rec name affix = function
+-    T_int8x8 -> affix "int8x8"
+-  | T_int8x16 -> affix "int8x16"
+-  | T_int16x4 -> affix "int16x4"
+-  | T_int16x8 -> affix "int16x8"
+-  | T_int32x2 -> affix "int32x2"
+-  | T_int32x4 -> affix "int32x4"
+-  | T_int64x1 -> affix "int64x1"
+-  | T_int64x2 -> affix "int64x2"
+-  | T_uint8x8 -> affix "uint8x8"
+-  | T_uint8x16 -> affix "uint8x16"
+-  | T_uint16x4 -> affix "uint16x4"
+-  | T_uint16x8 -> affix "uint16x8"
+-  | T_uint32x2 -> affix "uint32x2"
+-  | T_uint32x4 -> affix "uint32x4"
+-  | T_uint64x1 -> affix "uint64x1"
+-  | T_uint64x2 -> affix "uint64x2"
+-  | T_float16x4 -> affix "float16x4"
+-  | T_float32x2 -> affix "float32x2"
+-  | T_float32x4 -> affix "float32x4"
+-  | T_poly8x8 -> affix "poly8x8"
+-  | T_poly8x16 -> affix "poly8x16"
+-  | T_poly16x4 -> affix "poly16x4"
+-  | T_poly16x8 -> affix "poly16x8"
+-  | T_int8 -> affix "int8"
+-  | T_int16 -> affix "int16"
+-  | T_int32 -> affix "int32"
+-  | T_int64 -> affix "int64"
+-  | T_uint8 -> affix "uint8"
+-  | T_uint16 -> affix "uint16"
+-  | T_uint32 -> affix "uint32"
+-  | T_uint64 -> affix "uint64"
+-  | T_poly8 -> affix "poly8"
+-  | T_poly16 -> affix "poly16"
+-  | T_poly64 -> affix "poly64"
+-  | T_poly64x1 -> affix "poly64x1"
+-  | T_poly64x2 -> affix "poly64x2"
+-  | T_poly128 -> affix "poly128"
+-  | T_float16 -> affix "float16"
+-  | T_float32 -> affix "float32"
+-  | T_immediate _ -> "const int"
+-  | T_void -> "void"
+-  | T_intQI -> "__builtin_neon_qi"
+-  | T_intHI -> "__builtin_neon_hi"
+-  | T_intSI -> "__builtin_neon_si"
+-  | T_intDI -> "__builtin_neon_di"
+-  | T_intTI -> "__builtin_neon_ti"
+-  | T_floatHF -> "__builtin_neon_hf"
+-  | T_floatSF -> "__builtin_neon_sf"
+-  | T_arrayof (num, base) ->
+-      let basename = name (fun x -> x) base in
+-      affix (Printf.sprintf "%sx%d" basename num)
+-  | T_ptrto x ->
+-      let basename = name affix x in
+-      Printf.sprintf "%s *" basename
+-  | T_const x ->
+-      let basename = name affix x in
+-      Printf.sprintf "const %s" basename
+-  in
+-    name (fun x -> x ^ "_t") vt
+-
+-let string_of_inttype = function
+-    B_TImode -> "__builtin_neon_ti"
+-  | B_EImode -> "__builtin_neon_ei"
+-  | B_OImode -> "__builtin_neon_oi"
+-  | B_CImode -> "__builtin_neon_ci"
+-  | B_XImode -> "__builtin_neon_xi"
+-
+-let string_of_mode = function
+-    V8QI -> "v8qi" | V4HI -> "v4hi" | V4HF  -> "v4hf"  | V2SI -> "v2si"
+-  | V2SF -> "v2sf" | DI   -> "di"   | V16QI -> "v16qi" | V8HI -> "v8hi"
+-  | V4SI -> "v4si" | V4SF -> "v4sf" | V2DI  -> "v2di"  | QI   -> "qi"
+-  | HI -> "hi" | SI -> "si" | SF -> "sf" | TI -> "ti"
+-
+-(* Use uppercase chars for letters which form part of the intrinsic name, but
+-   should be omitted from the builtin name (the info is passed in an extra
+-   argument, instead).  *)
+-let intrinsic_name name = String.lowercase name
+-
+-(* Allow the name of the builtin to be overridden by things (e.g. Flipped)
+-   found in the features list.  *)
+-let builtin_name features name =
+-  let name = List.fold_right
+-               (fun el name ->
+-                 match el with
+-                   Flipped x | Builtin_name x -> x
+-                 | _ -> name)
+-               features name in
+-  let islower x = let str = String.make 1 x in (String.lowercase str) = str
+-  and buf = Buffer.create (String.length name) in
+-  String.iter (fun c -> if islower c then Buffer.add_char buf c) name;
+-  Buffer.contents buf
+-
+-(* Transform an arity into a list of strings.  *)
+-let strings_of_arity a =
+-  match a with
+-  | Arity0 vt -> [string_of_vectype vt]
+-  | Arity1 (vt1, vt2) -> [string_of_vectype vt1; string_of_vectype vt2]
+-  | Arity2 (vt1, vt2, vt3) -> [string_of_vectype vt1;
+-			       string_of_vectype vt2;
+-                               string_of_vectype vt3]
+-  | Arity3 (vt1, vt2, vt3, vt4) -> [string_of_vectype vt1;
+-                                    string_of_vectype vt2;
+-                                    string_of_vectype vt3;
+-                                    string_of_vectype vt4]
+-  | Arity4 (vt1, vt2, vt3, vt4, vt5) -> [string_of_vectype vt1;
+-                                         string_of_vectype vt2;
+-                                         string_of_vectype vt3;
+-                                         string_of_vectype vt4;
+-                                         string_of_vectype vt5]
+-
+-(* Suffixes on the end of builtin names that are to be stripped in order
+-   to obtain the name used as an instruction.  They are only stripped if
+-   preceded immediately by an underscore.  *)
+-let suffixes_to_strip = [ "n"; "lane"; "dup" ]
+-
+-(* Get the possible names of an instruction corresponding to a "name" from the
+-   ops table.  This is done by getting the equivalent builtin name and
+-   stripping any suffixes from the list at the top of this file, unless
+-   the features list presents with an Instruction_name entry, in which
+-   case that is used; or unless the features list presents with a Flipped
+-   entry, in which case that is used.  If both such entries are present,
+-   the first in the list will be chosen.  *)
+-let get_insn_names features name =
+-  let names = try
+-  begin
+-    match List.find (fun feature -> match feature with
+-                                      Instruction_name _ -> true
+-				    | Flipped _ -> true
+-				    | _ -> false) features
+-    with
+-      Instruction_name names -> names
+-    | Flipped name -> [name]
+-    | _ -> assert false
+-  end
+-  with Not_found -> [builtin_name features name]
+-  in
+-  begin
+-    List.map (fun name' ->
+-      try
+-        let underscore = String.rindex name' '_' in
+-        let our_suffix = String.sub name' (underscore + 1)
+-                                    ((String.length name') - underscore - 1)
+-        in
+-          let rec strip remaining_suffixes =
+-            match remaining_suffixes with
+-              [] -> name'
+-            | s::ss when our_suffix = s -> String.sub name' 0 underscore
+-            | _::ss -> strip ss
+-          in
+-            strip suffixes_to_strip
+-      with (Not_found | Invalid_argument _) -> name') names
+-  end
+-
+-(* Apply a function to each element of a list and then comma-separate
+-   the resulting strings.  *)
+-let rec commas f elts acc =
+-  match elts with
+-    [] -> acc
+-  | [elt] -> acc ^ (f elt)
+-  | elt::elts ->
+-    commas f elts (acc ^ (f elt) ^ ", ")
+-
+-(* Given a list of features and the shape specified in the "ops" table, apply
+-   a function to each possible shape that the instruction may have.
+-   By default, this is the "shape" entry in "ops".  If the features list
+-   contains a Disassembles_as entry, the shapes contained in that entry are
+-   mapped to corresponding outputs and returned in a list.  If there is more
+-   than one Disassembles_as entry, only the first is used.  *)
+-let analyze_all_shapes features shape f =
+-  try
+-    match List.find (fun feature ->
+-                       match feature with Disassembles_as _ -> true
+-                                        | _ -> false)
+-                    features with
+-      Disassembles_as shapes -> List.map f shapes
+-    | _ -> assert false
+-  with Not_found -> [f shape]
+-
+-(* The crypto intrinsics have unconventional shapes and are not that
+-   numerous to be worth the trouble of encoding here.  We implement them
+-   explicitly here.  *)
+-let crypto_intrinsics =
+-"
+-#ifdef __ARM_FEATURE_CRYPTO
+-
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
+-vldrq_p128 (poly128_t const * __ptr)
+-{
+-#ifdef __ARM_BIG_ENDIAN
+-  poly64_t* __ptmp = (poly64_t*) __ptr;
+-  poly64_t __d0 = vld1_p64 (__ptmp);
+-  poly64_t __d1 = vld1_p64 (__ptmp + 1);
+-  return vreinterpretq_p128_p64 (vcombine_p64 (__d1, __d0));
+-#else
+-  return vreinterpretq_p128_p64 (vld1q_p64 ((poly64_t*) __ptr));
+-#endif
+-}
+-
+-__extension__ static __inline void __attribute__ ((__always_inline__))
+-vstrq_p128 (poly128_t * __ptr, poly128_t __val)
+-{
+-#ifdef __ARM_BIG_ENDIAN
+-  poly64x2_t __tmp = vreinterpretq_p64_p128 (__val);
+-  poly64_t __d0 = vget_high_p64 (__tmp);
+-  poly64_t __d1 = vget_low_p64 (__tmp);
+-  vst1q_p64 ((poly64_t*) __ptr, vcombine_p64 (__d0, __d1));
+-#else
+-  vst1q_p64 ((poly64_t*) __ptr, vreinterpretq_p64_p128 (__val));
+-#endif
+-}
+-
+-/* The vceq_p64 intrinsic does not map to a single instruction.
+-   Instead we emulate it by performing a 32-bit variant of the vceq
+-   and applying a pairwise min reduction to the result.
+-   vceq_u32 will produce two 32-bit halves, each of which will contain either
+-   all ones or all zeros depending on whether the corresponding 32-bit
+-   halves of the poly64_t were equal.  The whole poly64_t values are equal
+-   if and only if both halves are equal, i.e. vceq_u32 returns all ones.
+-   If the result is all zeroes for any half then the whole result is zeroes.
+-   This is what the pairwise min reduction achieves.  */
+-
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vceq_p64 (poly64x1_t __a, poly64x1_t __b)
+-{
+-  uint32x2_t __t_a = vreinterpret_u32_p64 (__a);
+-  uint32x2_t __t_b = vreinterpret_u32_p64 (__b);
+-  uint32x2_t __c = vceq_u32 (__t_a, __t_b);
+-  uint32x2_t __m = vpmin_u32 (__c, __c);
+-  return vreinterpret_u64_u32 (__m);
+-}
+-
+-/* The vtst_p64 intrinsic does not map to a single instruction.
+-   We emulate it in way similar to vceq_p64 above but here we do
+-   a reduction with max since if any two corresponding bits
+-   in the two poly64_t's match, then the whole result must be all ones.  */
+-
+-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+-vtst_p64 (poly64x1_t __a, poly64x1_t __b)
+-{
+-  uint32x2_t __t_a = vreinterpret_u32_p64 (__a);
+-  uint32x2_t __t_b = vreinterpret_u32_p64 (__b);
+-  uint32x2_t __c = vtst_u32 (__t_a, __t_b);
+-  uint32x2_t __m = vpmax_u32 (__c, __c);
+-  return vreinterpret_u64_u32 (__m);
+-}
+-
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaeseq_u8 (uint8x16_t __data, uint8x16_t __key)
+-{
+-  return __builtin_arm_crypto_aese (__data, __key);
+-}
+-
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaesdq_u8 (uint8x16_t __data, uint8x16_t __key)
+-{
+-  return __builtin_arm_crypto_aesd (__data, __key);
+-}
+-
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaesmcq_u8 (uint8x16_t __data)
+-{
+-  return __builtin_arm_crypto_aesmc (__data);
+-}
+-
+-__extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
+-vaesimcq_u8 (uint8x16_t __data)
+-{
+-  return __builtin_arm_crypto_aesimc (__data);
+-}
+-
+-__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+-vsha1h_u32 (uint32_t __hash_e)
+-{
+-  uint32x4_t __t = vdupq_n_u32 (0);
+-  __t = vsetq_lane_u32 (__hash_e, __t, 0);
+-  __t = __builtin_arm_crypto_sha1h (__t);
+-  return vgetq_lane_u32 (__t, 0);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1cq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+-{
+-  uint32x4_t __t = vdupq_n_u32 (0);
+-  __t = vsetq_lane_u32 (__hash_e, __t, 0);
+-  return __builtin_arm_crypto_sha1c (__hash_abcd, __t, __wk);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1pq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+-{
+-  uint32x4_t __t = vdupq_n_u32 (0);
+-  __t = vsetq_lane_u32 (__hash_e, __t, 0);
+-  return __builtin_arm_crypto_sha1p (__hash_abcd, __t, __wk);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1mq_u32 (uint32x4_t __hash_abcd, uint32_t __hash_e, uint32x4_t __wk)
+-{
+-  uint32x4_t __t = vdupq_n_u32 (0);
+-  __t = vsetq_lane_u32 (__hash_e, __t, 0);
+-  return __builtin_arm_crypto_sha1m (__hash_abcd, __t, __wk);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1su0q_u32 (uint32x4_t __w0_3, uint32x4_t __w4_7, uint32x4_t __w8_11)
+-{
+-  return __builtin_arm_crypto_sha1su0 (__w0_3, __w4_7, __w8_11);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha1su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w12_15)
+-{
+-  return __builtin_arm_crypto_sha1su1 (__tw0_3, __w12_15);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256hq_u32 (uint32x4_t __hash_abcd, uint32x4_t __hash_efgh, uint32x4_t __wk)
+-{
+-  return __builtin_arm_crypto_sha256h (__hash_abcd, __hash_efgh, __wk);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256h2q_u32 (uint32x4_t __hash_abcd, uint32x4_t __hash_efgh, uint32x4_t __wk)
+-{
+-  return __builtin_arm_crypto_sha256h2 (__hash_abcd, __hash_efgh, __wk);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256su0q_u32 (uint32x4_t __w0_3, uint32x4_t __w4_7)
+-{
+-  return __builtin_arm_crypto_sha256su0 (__w0_3, __w4_7);
+-}
+-
+-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+-vsha256su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w8_11, uint32x4_t __w12_15)
+-{
+-  return __builtin_arm_crypto_sha256su1 (__tw0_3, __w8_11, __w12_15);
+-}
+-
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
+-vmull_p64 (poly64_t __a, poly64_t __b)
+-{
+-  return (poly128_t) __builtin_arm_crypto_vmullp64 ((uint64_t) __a, (uint64_t) __b);
+-}
+-
+-__extension__ static __inline poly128_t __attribute__ ((__always_inline__))
+-vmull_high_p64 (poly64x2_t __a, poly64x2_t __b)
+-{
+-  poly64_t __t1 = vget_high_p64 (__a);
+-  poly64_t __t2 = vget_high_p64 (__b);
+-
+-  return (poly128_t) __builtin_arm_crypto_vmullp64 ((uint64_t) __t1, (uint64_t) __t2);
+-}
+-
+-#endif
+-"
+--- a/src/gcc/config/arm/predicates.md
++++ b/src/gcc/config/arm/predicates.md
+@@ -141,8 +141,7 @@
+        (match_test "const_ok_for_arm (~INTVAL (op))")))
+ 
+ (define_predicate "const0_operand"
+-  (and (match_code "const_int")
+-       (match_test "INTVAL (op) == 0")))
++  (match_test "op == CONST0_RTX (mode)"))
+ 
+ ;; Something valid on the RHS of an ARM data-processing instruction
+ (define_predicate "arm_rhs_operand"
+@@ -170,8 +169,7 @@
+ 
+ (define_predicate "const_neon_scalar_shift_amount_operand"
+   (and (match_code "const_int")
+-       (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode)
+-	&& ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0")))
++       (match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))")))
+ 
+ (define_predicate "ldrd_strd_offset_operand"
+   (and (match_operand 0 "const_int_operand")
+@@ -243,11 +241,6 @@
+        (and (match_code "const_double")
+ 	    (match_test "arm_const_double_rtx (op)"))))
+ 
+-(define_predicate "arm_float_compare_operand"
+-  (if_then_else (match_test "TARGET_VFP")
+-		(match_operand 0 "vfp_compare_operand")
+-		(match_operand 0 "s_register_operand")))
+-
+ ;; True for valid index operands.
+ (define_predicate "index_operand"
+   (ior (match_operand 0 "s_register_operand")
+@@ -285,19 +278,19 @@
+ 		      (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
+ 		 (and (match_code "rotate")
+ 		      (match_test "CONST_INT_P (XEXP (op, 1))
+-				   && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
++				   && (UINTVAL (XEXP (op, 1))) < 32")))
+ 	    (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
+ 		 (match_test "!CONST_INT_P (XEXP (op, 1))
+-			      || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
++			      || (UINTVAL (XEXP (op, 1))) < 32")))
+        (match_test "mode == GET_MODE (op)")))
+ 
+ (define_special_predicate "shift_nomul_operator"
+   (and (ior (and (match_code "rotate")
+ 		 (match_test "CONST_INT_P (XEXP (op, 1))
+-			      && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))
++			      && (UINTVAL (XEXP (op, 1))) < 32"))
+ 	    (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
+ 		 (match_test "!CONST_INT_P (XEXP (op, 1))
+-			      || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
++			      || (UINTVAL (XEXP (op, 1))) < 32")))
+        (match_test "mode == GET_MODE (op)")))
+ 
+ ;; True for shift operators which can be used with saturation instructions.
+@@ -306,7 +299,7 @@
+                  (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
+             (and (match_code "ashift,ashiftrt")
+                  (match_test "CONST_INT_P (XEXP (op, 1))
+-		              && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)")))
++		              && (UINTVAL (XEXP (op, 1)) < 32)")))
+        (match_test "mode == GET_MODE (op)")))
+ 
+ ;; True for MULT, to identify which variant of shift_operator is in use.
+@@ -398,6 +391,12 @@
+ 	     || mode == CC_DGTUmode));
+ })
+ 
++;; Any register, including CC
++(define_predicate "cc_register_operand"
++  (and (match_code "reg")
++       (ior (match_operand 0 "s_register_operand")
++	    (match_operand 0 "cc_register"))))
++
+ (define_special_predicate "arm_extendqisi_mem_op"
+   (and (match_operand 0 "memory_operand")
+        (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
+@@ -532,7 +531,7 @@
+   (ior (and (match_code "reg,subreg")
+ 	    (match_operand 0 "s_register_operand"))
+        (and (match_code "const_int")
+-	    (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
++	    (match_test "(UINTVAL (op)) < 256"))))
+ 
+ (define_predicate "thumb1_cmpneg_operand"
+   (and (match_code "const_int")
+@@ -612,69 +611,23 @@
+ (define_special_predicate "vect_par_constant_high" 
+   (match_code "parallel")
+ {
+-  HOST_WIDE_INT count = XVECLEN (op, 0);
+-  int i;
+-  int base = GET_MODE_NUNITS (mode);
+-
+-  if ((count < 1)
+-      || (count != base/2))
+-    return false;
+-    
+-  if (!VECTOR_MODE_P (mode))
+-    return false;
+-
+-  for (i = 0; i < count; i++)
+-   {
+-     rtx elt = XVECEXP (op, 0, i);
+-     int val;
+-
+-     if (!CONST_INT_P (elt))
+-       return false;
+-
+-     val = INTVAL (elt);
+-     if (val != (base/2) + i)
+-       return false;
+-   }
+-  return true; 
++  return arm_simd_check_vect_par_cnst_half_p (op, mode, true);
+ })
+ 
+ (define_special_predicate "vect_par_constant_low"
+   (match_code "parallel")
+ {
+-  HOST_WIDE_INT count = XVECLEN (op, 0);
+-  int i;
+-  int base = GET_MODE_NUNITS (mode);
+-
+-  if ((count < 1)
+-      || (count != base/2))
+-    return false;
+-    
+-  if (!VECTOR_MODE_P (mode))
+-    return false;
+-
+-  for (i = 0; i < count; i++)
+-   {
+-     rtx elt = XVECEXP (op, 0, i);
+-     int val;
+-
+-     if (!CONST_INT_P (elt))
+-       return false;
+-
+-     val = INTVAL (elt);
+-     if (val != i)
+-       return false;
+-   } 
+-  return true; 
++  return arm_simd_check_vect_par_cnst_half_p (op, mode, false);
+ })
+ 
+ (define_predicate "const_double_vcvt_power_of_two_reciprocal"
+   (and (match_code "const_double")
+-       (match_test "TARGET_32BIT && TARGET_VFP
+-                   && vfp3_const_double_for_fract_bits (op)")))
++       (match_test "TARGET_32BIT
++		    && vfp3_const_double_for_fract_bits (op)")))
+ 
+ (define_predicate "const_double_vcvt_power_of_two"
+   (and (match_code "const_double")
+-       (match_test "TARGET_32BIT && TARGET_VFP
++       (match_test "TARGET_32BIT
+ 		    && vfp3_const_double_for_bits (op) > 0")))
+ 
+ (define_predicate "neon_struct_operand"
+--- a/src/gcc/config/arm/sync.md
++++ b/src/gcc/config/arm/sync.md
+@@ -63,37 +63,59 @@
+    (set_attr "predicable" "no")])
+ 
+ (define_insn "atomic_load<mode>"
+-  [(set (match_operand:QHSI 0 "register_operand" "=r")
++  [(set (match_operand:QHSI 0 "register_operand" "=r,r,l")
+     (unspec_volatile:QHSI
+-      [(match_operand:QHSI 1 "arm_sync_memory_operand" "Q")
+-       (match_operand:SI 2 "const_int_operand")]		;; model
++      [(match_operand:QHSI 1 "arm_sync_memory_operand" "Q,Q,Q")
++       (match_operand:SI 2 "const_int_operand" "n,Pf,n")]	;; model
+       VUNSPEC_LDA))]
+   "TARGET_HAVE_LDACQ"
+   {
+     enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
+     if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model))
+-      return \"ldr<sync_sfx>%?\\t%0, %1\";
++      {
++	if (TARGET_THUMB1)
++	  return \"ldr<sync_sfx>\\t%0, %1\";
++	else
++	  return \"ldr<sync_sfx>%?\\t%0, %1\";
++      }
+     else
+-      return \"lda<sync_sfx>%?\\t%0, %1\";
++      {
++	if (TARGET_THUMB1)
++	  return \"lda<sync_sfx>\\t%0, %1\";
++	else
++	  return \"lda<sync_sfx>%?\\t%0, %1\";
++      }
+   }
+-  [(set_attr "predicable" "yes")
++  [(set_attr "arch" "32,v8mb,any")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ (define_insn "atomic_store<mode>"
+-  [(set (match_operand:QHSI 0 "memory_operand" "=Q")
++  [(set (match_operand:QHSI 0 "memory_operand" "=Q,Q,Q")
+     (unspec_volatile:QHSI
+-      [(match_operand:QHSI 1 "general_operand" "r")
+-       (match_operand:SI 2 "const_int_operand")]		;; model
++      [(match_operand:QHSI 1 "general_operand" "r,r,l")
++       (match_operand:SI 2 "const_int_operand" "n,Pf,n")]	;; model
+       VUNSPEC_STL))]
+   "TARGET_HAVE_LDACQ"
+   {
+     enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
+     if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))
+-      return \"str<sync_sfx>%?\t%1, %0\";
++      {
++	if (TARGET_THUMB1)
++	  return \"str<sync_sfx>\t%1, %0\";
++	else
++	  return \"str<sync_sfx>%?\t%1, %0\";
++      }
+     else
+-      return \"stl<sync_sfx>%?\t%1, %0\";
++      {
++	if (TARGET_THUMB1)
++	  return \"stl<sync_sfx>\t%1, %0\";
++	else
++	  return \"stl<sync_sfx>%?\t%1, %0\";
++      }
+   }
+-  [(set_attr "predicable" "yes")
++  [(set_attr "arch" "32,v8mb,any")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ ;; An LDRD instruction usable by the atomic_loaddi expander on LPAE targets
+@@ -117,7 +139,7 @@
+   [(match_operand:DI 0 "s_register_operand")		;; val out
+    (match_operand:DI 1 "mem_noofs_operand")		;; memory
+    (match_operand:SI 2 "const_int_operand")]		;; model
+-  "(TARGET_HAVE_LDREXD || TARGET_HAVE_LPAE || TARGET_HAVE_LDACQ)
++  "(TARGET_HAVE_LDREXD || TARGET_HAVE_LPAE || TARGET_HAVE_LDACQEXD)
+    && ARM_DOUBLEWORD_ALIGN"
+ {
+   memmodel model = memmodel_from_int (INTVAL (operands[2]));
+@@ -125,7 +147,7 @@
+   /* For ARMv8-A we can use an LDAEXD to atomically load two 32-bit registers
+      when acquire or stronger semantics are needed.  When the relaxed model is
+      used this can be relaxed to a normal LDRD.  */
+-  if (TARGET_HAVE_LDACQ)
++  if (TARGET_HAVE_LDACQEXD)
+     {
+       if (is_mm_relaxed (model))
+ 	emit_insn (gen_arm_atomic_loaddi2_ldrd (operands[0], operands[1]));
+@@ -167,21 +189,23 @@
+   DONE;
+ })
+ 
++;; Constraints of this pattern must be at least as strict as those of the
++;; cbranchsi operations in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_compare_and_swap<mode>_1"
+-  [(set (reg:CC_Z CC_REGNUM)					;; bool out
++  [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l")		;; bool out
+ 	(unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS))
+-   (set (match_operand:SI 0 "s_register_operand" "=&r")		;; val out
++   (set (match_operand:SI 1 "s_register_operand" "=&r,&l,&0,&l*h")	;; val out
+ 	(zero_extend:SI
+-	  (match_operand:NARROW 1 "mem_noofs_operand" "+Ua")))	;; memory
+-   (set (match_dup 1)
++	  (match_operand:NARROW 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua")))	;; memory
++   (set (match_dup 2)
+ 	(unspec_volatile:NARROW
+-	  [(match_operand:SI 2 "arm_add_operand" "rIL")		;; expected
+-	   (match_operand:NARROW 3 "s_register_operand" "r")	;; desired
+-	   (match_operand:SI 4 "const_int_operand")		;; is_weak
+-	   (match_operand:SI 5 "const_int_operand")		;; mod_s
+-	   (match_operand:SI 6 "const_int_operand")]		;; mod_f
++	  [(match_operand:SI 3 "arm_add_operand" "rIL,lIL*h,J,*r")	;; expected
++	   (match_operand:NARROW 4 "s_register_operand" "r,r,r,r")	;; desired
++	   (match_operand:SI 5 "const_int_operand")		;; is_weak
++	   (match_operand:SI 6 "const_int_operand")		;; mod_s
++	   (match_operand:SI 7 "const_int_operand")]		;; mod_f
+ 	  VUNSPEC_ATOMIC_CAS))
+-   (clobber (match_scratch:SI 7 "=&r"))]
++   (clobber (match_scratch:SI 8 "=&r,X,X,X"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -189,27 +213,30 @@
+   {
+     arm_split_compare_and_swap (operands);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb,v8mb,v8mb")])
+ 
+ (define_mode_attr cas_cmp_operand
+   [(SI "arm_add_operand") (DI "cmpdi_operand")])
+ (define_mode_attr cas_cmp_str
+   [(SI "rIL") (DI "rDi")])
+ 
++;; Constraints of this pattern must be at least as strict as those of the
++;; cbranchsi operations in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_compare_and_swap<mode>_1"
+-  [(set (reg:CC_Z CC_REGNUM)					;; bool out
++  [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l")		;; bool out
+ 	(unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS))
+-   (set (match_operand:SIDI 0 "s_register_operand" "=&r")	;; val out
+-	(match_operand:SIDI 1 "mem_noofs_operand" "+Ua"))	;; memory
+-   (set (match_dup 1)
++   (set (match_operand:SIDI 1 "s_register_operand" "=&r,&l,&0,&l*h")	;; val out
++	(match_operand:SIDI 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua"))	;; memory
++   (set (match_dup 2)
+ 	(unspec_volatile:SIDI
+-	  [(match_operand:SIDI 2 "<cas_cmp_operand>" "<cas_cmp_str>") ;; expect
+-	   (match_operand:SIDI 3 "s_register_operand" "r")	;; desired
+-	   (match_operand:SI 4 "const_int_operand")		;; is_weak
+-	   (match_operand:SI 5 "const_int_operand")		;; mod_s
+-	   (match_operand:SI 6 "const_int_operand")]		;; mod_f
++	  [(match_operand:SIDI 3 "<cas_cmp_operand>" "<cas_cmp_str>,lIL*h,J,*r") ;; expect
++	   (match_operand:SIDI 4 "s_register_operand" "r,r,r,r")	;; desired
++	   (match_operand:SI 5 "const_int_operand")		;; is_weak
++	   (match_operand:SI 6 "const_int_operand")		;; mod_s
++	   (match_operand:SI 7 "const_int_operand")]		;; mod_f
+ 	  VUNSPEC_ATOMIC_CAS))
+-   (clobber (match_scratch:SI 7 "=&r"))]
++   (clobber (match_scratch:SI 8 "=&r,X,X,X"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -217,18 +244,19 @@
+   {
+     arm_split_compare_and_swap (operands);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb,v8mb,v8mb")])
+ 
+ (define_insn_and_split "atomic_exchange<mode>"
+-  [(set (match_operand:QHSD 0 "s_register_operand" "=&r")	;; output
+-	(match_operand:QHSD 1 "mem_noofs_operand" "+Ua"))	;; memory
++  [(set (match_operand:QHSD 0 "s_register_operand" "=&r,&r")	;; output
++	(match_operand:QHSD 1 "mem_noofs_operand" "+Ua,Ua"))	;; memory
+    (set (match_dup 1)
+ 	(unspec_volatile:QHSD
+-	  [(match_operand:QHSD 2 "s_register_operand" "r")	;; input
++	  [(match_operand:QHSD 2 "s_register_operand" "r,r")	;; input
+ 	   (match_operand:SI 3 "const_int_operand" "")]		;; model
+ 	  VUNSPEC_ATOMIC_XCHG))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:SI 4 "=&r"))]
++   (clobber (match_scratch:SI 4 "=&r,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -237,7 +265,11 @@
+     arm_split_atomic_op (SET, operands[0], NULL, operands[1],
+ 			 operands[2], operands[3], operands[4]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb")])
++
++;; The following mode and code attribute are defined here because they are
++;; specific to atomics and are not needed anywhere else.
+ 
+ (define_mode_attr atomic_op_operand
+   [(QI "reg_or_int_operand")
+@@ -248,16 +280,24 @@
+ (define_mode_attr atomic_op_str
+   [(QI "rn") (HI "rn") (SI "rn") (DI "r")])
+ 
++(define_code_attr thumb1_atomic_op_str
++  [(ior "l,l") (xor "l,l") (and "l,l") (plus "lIJL,r") (minus "lPd,lPd")])
++
++(define_code_attr thumb1_atomic_newop_str
++  [(ior "&l,&l") (xor "&l,&l") (and "&l,&l") (plus "&l,&r") (minus "&l,&l")])
++
++;; Constraints of this pattern must be at least as strict as those of the non
++;; atomic operations in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_<sync_optab><mode>"
+-  [(set (match_operand:QHSD 0 "mem_noofs_operand" "+Ua")
++  [(set (match_operand:QHSD 0 "mem_noofs_operand" "+Ua,Ua,Ua")
+ 	(unspec_volatile:QHSD
+ 	  [(syncop:QHSD (match_dup 0)
+-	     (match_operand:QHSD 1 "<atomic_op_operand>" "<atomic_op_str>"))
++	     (match_operand:QHSD 1 "<atomic_op_operand>" "<atomic_op_str>,<thumb1_atomic_op_str>"))
+ 	   (match_operand:SI 2 "const_int_operand")]		;; model
+ 	  VUNSPEC_ATOMIC_OP))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:QHSD 3 "=&r"))
+-   (clobber (match_scratch:SI 4 "=&r"))]
++   (clobber (match_scratch:QHSD 3 "=&r,<thumb1_atomic_newop_str>"))
++   (clobber (match_scratch:SI 4 "=&r,&l,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -266,19 +306,22 @@
+     arm_split_atomic_op (<CODE>, NULL, operands[3], operands[0],
+ 			 operands[1], operands[2], operands[4]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb,v8mb")])
+ 
++;; Constraints of this pattern must be at least as strict as those of the non
++;; atomic NANDs in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_nand<mode>"
+-  [(set (match_operand:QHSD 0 "mem_noofs_operand" "+Ua")
++  [(set (match_operand:QHSD 0 "mem_noofs_operand" "+Ua,Ua")
+ 	(unspec_volatile:QHSD
+ 	  [(not:QHSD
+ 	     (and:QHSD (match_dup 0)
+-	       (match_operand:QHSD 1 "<atomic_op_operand>" "<atomic_op_str>")))
++	       (match_operand:QHSD 1 "<atomic_op_operand>" "<atomic_op_str>,l")))
+ 	   (match_operand:SI 2 "const_int_operand")]		;; model
+ 	  VUNSPEC_ATOMIC_OP))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:QHSD 3 "=&r"))
+-   (clobber (match_scratch:SI 4 "=&r"))]
++   (clobber (match_scratch:QHSD 3 "=&r,&l"))
++   (clobber (match_scratch:SI 4 "=&r,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -287,20 +330,38 @@
+     arm_split_atomic_op (NOT, NULL, operands[3], operands[0],
+ 			 operands[1], operands[2], operands[4]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb")])
++
++;; 3 alternatives are needed to represent constraints after split from
++;; thumb1_addsi3: (i) case where operand1 and destination can be in different
++;; registers, (ii) case where they are in the same low register and (iii) case
++;; when they are in the same register without restriction on the register.  We
++;; disparage slightly alternatives that require copying the old value into the
++;; register for the new value (see bind_old_new in arm_split_atomic_op).
++(define_code_attr thumb1_atomic_fetch_op_str
++  [(ior "l,l,l") (xor "l,l,l") (and "l,l,l") (plus "lL,?IJ,?r") (minus "lPd,lPd,lPd")])
++
++(define_code_attr thumb1_atomic_fetch_newop_str
++  [(ior "&l,&l,&l") (xor "&l,&l,&l") (and "&l,&l,&l") (plus "&l,&l,&r") (minus "&l,&l,&l")])
+ 
++(define_code_attr thumb1_atomic_fetch_oldop_str
++  [(ior "&r,&r,&r") (xor "&r,&r,&r") (and "&r,&r,&r") (plus "&l,&r,&r") (minus "&l,&l,&l")])
++
++;; Constraints of this pattern must be at least as strict as those of the non
++;; atomic operations in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_fetch_<sync_optab><mode>"
+-  [(set (match_operand:QHSD 0 "s_register_operand" "=&r")
+-	(match_operand:QHSD 1 "mem_noofs_operand" "+Ua"))
++  [(set (match_operand:QHSD 0 "s_register_operand" "=&r,<thumb1_atomic_fetch_oldop_str>")
++	(match_operand:QHSD 1 "mem_noofs_operand" "+Ua,Ua,Ua,Ua"))
+    (set (match_dup 1)
+ 	(unspec_volatile:QHSD
+ 	  [(syncop:QHSD (match_dup 1)
+-	     (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>"))
++	     (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>,<thumb1_atomic_fetch_op_str>"))
+ 	   (match_operand:SI 3 "const_int_operand")]		;; model
+ 	  VUNSPEC_ATOMIC_OP))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:QHSD 4 "=&r"))
+-   (clobber (match_scratch:SI 5 "=&r"))]
++   (clobber (match_scratch:QHSD 4 "=&r,<thumb1_atomic_fetch_newop_str>"))
++   (clobber (match_scratch:SI 5 "=&r,&l,&l,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -309,21 +370,24 @@
+     arm_split_atomic_op (<CODE>, operands[0], operands[4], operands[1],
+ 			 operands[2], operands[3], operands[5]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb,v8mb,v8mb")])
+ 
++;; Constraints of this pattern must be at least as strict as those of the non
++;; atomic NANDs in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_fetch_nand<mode>"
+-  [(set (match_operand:QHSD 0 "s_register_operand" "=&r")
+-	(match_operand:QHSD 1 "mem_noofs_operand" "+Ua"))
++  [(set (match_operand:QHSD 0 "s_register_operand" "=&r,&r")
++	(match_operand:QHSD 1 "mem_noofs_operand" "+Ua,Ua"))
+    (set (match_dup 1)
+ 	(unspec_volatile:QHSD
+ 	  [(not:QHSD
+ 	     (and:QHSD (match_dup 1)
+-	       (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>")))
++	       (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>,l")))
+ 	   (match_operand:SI 3 "const_int_operand")]		;; model
+ 	  VUNSPEC_ATOMIC_OP))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:QHSD 4 "=&r"))
+-   (clobber (match_scratch:SI 5 "=&r"))]
++   (clobber (match_scratch:QHSD 4 "=&r,&l"))
++   (clobber (match_scratch:SI 5 "=&r,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -332,20 +396,23 @@
+     arm_split_atomic_op (NOT, operands[0], operands[4], operands[1],
+ 			 operands[2], operands[3], operands[5]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb")])
+ 
++;; Constraints of this pattern must be at least as strict as those of the non
++;; atomic operations in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_<sync_optab>_fetch<mode>"
+-  [(set (match_operand:QHSD 0 "s_register_operand" "=&r")
++  [(set (match_operand:QHSD 0 "s_register_operand" "=&r,<thumb1_atomic_newop_str>")
+ 	(syncop:QHSD
+-	  (match_operand:QHSD 1 "mem_noofs_operand" "+Ua")
+-	  (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>")))
++	  (match_operand:QHSD 1 "mem_noofs_operand" "+Ua,Ua,Ua")
++	  (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>,<thumb1_atomic_op_str>")))
+    (set (match_dup 1)
+ 	(unspec_volatile:QHSD
+ 	  [(match_dup 1) (match_dup 2)
+ 	   (match_operand:SI 3 "const_int_operand")]		;; model
+ 	  VUNSPEC_ATOMIC_OP))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:SI 4 "=&r"))]
++   (clobber (match_scratch:SI 4 "=&r,&l,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -354,21 +421,24 @@
+     arm_split_atomic_op (<CODE>, NULL, operands[0], operands[1],
+ 			 operands[2], operands[3], operands[4]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb,v8mb")])
+ 
++;; Constraints of this pattern must be at least as strict as those of the non
++;; atomic NANDs in thumb1.md and aim to be as permissive.
+ (define_insn_and_split "atomic_nand_fetch<mode>"
+-  [(set (match_operand:QHSD 0 "s_register_operand" "=&r")
++  [(set (match_operand:QHSD 0 "s_register_operand" "=&r,&l")
+ 	(not:QHSD
+ 	  (and:QHSD
+-	    (match_operand:QHSD 1 "mem_noofs_operand" "+Ua")
+-	    (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>"))))
++	    (match_operand:QHSD 1 "mem_noofs_operand" "+Ua,Ua")
++	    (match_operand:QHSD 2 "<atomic_op_operand>" "<atomic_op_str>,l"))))
+    (set (match_dup 1)
+ 	(unspec_volatile:QHSD
+ 	  [(match_dup 1) (match_dup 2)
+ 	   (match_operand:SI 3 "const_int_operand")]		;; model
+ 	  VUNSPEC_ATOMIC_OP))
+    (clobber (reg:CC CC_REGNUM))
+-   (clobber (match_scratch:SI 4 "=&r"))]
++   (clobber (match_scratch:SI 4 "=&r,&l"))]
+   "<sync_predtab>"
+   "#"
+   "&& reload_completed"
+@@ -377,48 +447,61 @@
+     arm_split_atomic_op (NOT, NULL, operands[0], operands[1],
+ 			 operands[2], operands[3], operands[4]);
+     DONE;
+-  })
++  }
++  [(set_attr "arch" "32,v8mb")])
+ 
+ (define_insn "arm_load_exclusive<mode>"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+         (zero_extend:SI
+ 	  (unspec_volatile:NARROW
+-	    [(match_operand:NARROW 1 "mem_noofs_operand" "Ua")]
++	    [(match_operand:NARROW 1 "mem_noofs_operand" "Ua,Ua")]
+ 	    VUNSPEC_LL)))]
+   "TARGET_HAVE_LDREXBH"
+-  "ldrex<sync_sfx>%?\t%0, %C1"
+-  [(set_attr "predicable" "yes")
++  "@
++   ldrex<sync_sfx>%?\t%0, %C1
++   ldrex<sync_sfx>\t%0, %C1"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ (define_insn "arm_load_acquire_exclusive<mode>"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+         (zero_extend:SI
+ 	  (unspec_volatile:NARROW
+-	    [(match_operand:NARROW 1 "mem_noofs_operand" "Ua")]
++	    [(match_operand:NARROW 1 "mem_noofs_operand" "Ua,Ua")]
+ 	    VUNSPEC_LAX)))]
+   "TARGET_HAVE_LDACQ"
+-  "ldaex<sync_sfx>%?\\t%0, %C1"
+-  [(set_attr "predicable" "yes")
++  "@
++   ldaex<sync_sfx>%?\\t%0, %C1
++   ldaex<sync_sfx>\\t%0, %C1"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ (define_insn "arm_load_exclusivesi"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ 	(unspec_volatile:SI
+-	  [(match_operand:SI 1 "mem_noofs_operand" "Ua")]
++	  [(match_operand:SI 1 "mem_noofs_operand" "Ua,Ua")]
+ 	  VUNSPEC_LL))]
+   "TARGET_HAVE_LDREX"
+-  "ldrex%?\t%0, %C1"
+-  [(set_attr "predicable" "yes")
++  "@
++   ldrex%?\t%0, %C1
++   ldrex\t%0, %C1"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ (define_insn "arm_load_acquire_exclusivesi"
+-  [(set (match_operand:SI 0 "s_register_operand" "=r")
++  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ 	(unspec_volatile:SI
+-	  [(match_operand:SI 1 "mem_noofs_operand" "Ua")]
++	  [(match_operand:SI 1 "mem_noofs_operand" "Ua,Ua")]
+ 	  VUNSPEC_LAX))]
+   "TARGET_HAVE_LDACQ"
+-  "ldaex%?\t%0, %C1"
+-  [(set_attr "predicable" "yes")
++  "@
++   ldaex%?\t%0, %C1
++   ldaex\t%0, %C1"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ (define_insn "arm_load_exclusivedi"
+@@ -436,7 +519,7 @@
+ 	(unspec_volatile:DI
+ 	  [(match_operand:DI 1 "mem_noofs_operand" "Ua")]
+ 	  VUNSPEC_LAX))]
+-  "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN"
++  "TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN"
+   "ldaexd%?\t%0, %H0, %C1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+@@ -452,16 +535,18 @@
+   {
+     if (<MODE>mode == DImode)
+       {
+-	rtx value = operands[2];
+ 	/* The restrictions on target registers in ARM mode are that the two
+ 	   registers are consecutive and the first one is even; Thumb is
+ 	   actually more flexible, but DI should give us this anyway.
+-	   Note that the 1st register always gets the lowest word in memory.  */
+-	gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2);
+-	operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1);
+-	return "strexd%?\t%0, %2, %3, %C1";
++	   Note that the 1st register always gets the
++	   lowest word in memory.  */
++	gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
++	return "strexd%?\t%0, %2, %H2, %C1";
+       }
+-    return "strex<sync_sfx>%?\t%0, %2, %C1";
++    if (TARGET_THUMB1)
++      return "strex<sync_sfx>\t%0, %2, %C1";
++    else
++      return "strex<sync_sfx>%?\t%0, %2, %C1";
+   }
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+@@ -473,25 +558,26 @@
+ 	(unspec_volatile:DI
+ 	  [(match_operand:DI 2 "s_register_operand" "r")]
+ 	  VUNSPEC_SLX))]
+-  "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN"
++  "TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN"
+   {
+-    rtx value = operands[2];
+     /* See comment in arm_store_exclusive<mode> above.  */
+-    gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2);
+-    operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1);
+-    return "stlexd%?\t%0, %2, %3, %C1";
++    gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
++    return "stlexd%?\t%0, %2, %H2, %C1";
+   }
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+ 
+ (define_insn "arm_store_release_exclusive<mode>"
+-  [(set (match_operand:SI 0 "s_register_operand" "=&r")
++  [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
+ 	(unspec_volatile:SI [(const_int 0)] VUNSPEC_SLX))
+-   (set (match_operand:QHSI 1 "mem_noofs_operand" "=Ua")
++   (set (match_operand:QHSI 1 "mem_noofs_operand" "=Ua,Ua")
+ 	(unspec_volatile:QHSI
+-	  [(match_operand:QHSI 2 "s_register_operand" "r")]
++	  [(match_operand:QHSI 2 "s_register_operand" "r,r")]
+ 	  VUNSPEC_SLX))]
+   "TARGET_HAVE_LDACQ"
+-  "stlex<sync_sfx>%?\t%0, %2, %C1"
+-  [(set_attr "predicable" "yes")
++  "@
++   stlex<sync_sfx>%?\t%0, %2, %C1
++   stlex<sync_sfx>\t%0, %2, %C1"
++  [(set_attr "arch" "32,v8mb")
++   (set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")])
+--- a/src/gcc/config/arm/t-aprofile
++++ b/src/gcc/config/arm/t-aprofile
+@@ -49,38 +49,33 @@ MULTILIB_DIRNAMES      += fpv3 simdv1 fpv4 simdvfpv4 simdv8
+ MULTILIB_OPTIONS       += mfloat-abi=softfp/mfloat-abi=hard
+ MULTILIB_DIRNAMES      += softfp hard
+ 
+-# We don't build no-float libraries with an FPU.
+-MULTILIB_EXCEPTIONS    += *mfpu=vfpv3-d16
+-MULTILIB_EXCEPTIONS    += *mfpu=neon
+-MULTILIB_EXCEPTIONS    += *mfpu=vfpv4-d16
+-MULTILIB_EXCEPTIONS    += *mfpu=neon-vfpv4
+-MULTILIB_EXCEPTIONS    += *mfpu=neon-fp-armv8
+-
+-# We don't build libraries requiring an FPU at the CPU/Arch/ISA level.
+-MULTILIB_EXCEPTIONS    += mfloat-abi=*
+-MULTILIB_EXCEPTIONS    += mfpu=*
+-MULTILIB_EXCEPTIONS    += mthumb/mfloat-abi=*
+-MULTILIB_EXCEPTIONS    += mthumb/mfpu=*
+-MULTILIB_EXCEPTIONS    += *march=armv7-a/mfloat-abi=*
+-MULTILIB_EXCEPTIONS    += *march=armv7ve/mfloat-abi=*
+-MULTILIB_EXCEPTIONS    += *march=armv8-a/mfloat-abi=*
+-
+-# Ensure the correct FPU variants apply to the correct base architectures.
+-MULTILIB_EXCEPTIONS    += *march=armv7ve/*mfpu=vfpv3-d16*
+-MULTILIB_EXCEPTIONS    += *march=armv7ve/*mfpu=neon/*
+-MULTILIB_EXCEPTIONS    += *march=armv8-a/*mfpu=vfpv3-d16*
+-MULTILIB_EXCEPTIONS    += *march=armv8-a/*mfpu=neon/*
+-MULTILIB_EXCEPTIONS    += *march=armv7-a/*mfpu=vfpv4-d16*
+-MULTILIB_EXCEPTIONS    += *march=armv7-a/*mfpu=neon-vfpv4*
+-MULTILIB_EXCEPTIONS    += *march=armv8-a/*mfpu=vfpv4-d16*
+-MULTILIB_EXCEPTIONS    += *march=armv8-a/*mfpu=neon-vfpv4*
+-MULTILIB_EXCEPTIONS    += *march=armv7-a/*mfpu=neon-fp-armv8*
+-MULTILIB_EXCEPTIONS    += *march=armv7ve/*mfpu=neon-fp-armv8*
++
++# Option combinations to build library with
++
++# Default CPU/Arch (ARM is implicitly included because it uses the default
++# multilib)
++MULTILIB_REQUIRED      += mthumb
++
++# ARMv7-A
++MULTILIB_REQUIRED      += *march=armv7-a
++MULTILIB_REQUIRED      += *march=armv7-a/mfpu=vfpv3-d16/mfloat-abi=*
++MULTILIB_REQUIRED      += *march=armv7-a/mfpu=neon/mfloat-abi=*
++
++# ARMv7VE
++MULTILIB_REQUIRED      += *march=armv7ve
++MULTILIB_REQUIRED      += *march=armv7ve/mfpu=vfpv4-d16/mfloat-abi=*
++MULTILIB_REQUIRED      += *march=armv7ve/mfpu=neon-vfpv4/mfloat-abi=*
++
++# ARMv8-A
++MULTILIB_REQUIRED      += *march=armv8-a
++MULTILIB_REQUIRED      += *march=armv8-a/mfpu=neon-fp-armv8/mfloat-abi=*
++
+ 
+ # CPU Matches
+ MULTILIB_MATCHES       += march?armv7-a=mcpu?cortex-a8
+ MULTILIB_MATCHES       += march?armv7-a=mcpu?cortex-a9
+ MULTILIB_MATCHES       += march?armv7-a=mcpu?cortex-a5
++MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a7
+ MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a15
+ MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a12
+ MULTILIB_MATCHES       += march?armv7ve=mcpu?cortex-a17
+@@ -93,6 +88,9 @@ MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a57
+ MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a57.cortex-a53
+ MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a72
+ MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a72.cortex-a53
++MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a73
++MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a73.cortex-a35
++MULTILIB_MATCHES       += march?armv8-a=mcpu?cortex-a73.cortex-a53
+ MULTILIB_MATCHES       += march?armv8-a=mcpu?exynos-m1
+ MULTILIB_MATCHES       += march?armv8-a=mcpu?qdf24xx
+ MULTILIB_MATCHES       += march?armv8-a=mcpu?xgene1
+@@ -101,13 +99,20 @@ MULTILIB_MATCHES       += march?armv8-a=mcpu?xgene1
+ MULTILIB_MATCHES       += march?armv8-a=march?armv8-a+crc
+ MULTILIB_MATCHES       += march?armv8-a=march?armv8.1-a
+ MULTILIB_MATCHES       += march?armv8-a=march?armv8.1-a+crc
++MULTILIB_MATCHES       += march?armv8-a=march?armv8.2-a
++MULTILIB_MATCHES       += march?armv8-a=march?armv8.2-a+fp16
+ 
+ # FPU matches
+ MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3
+ MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3-fp16
+-MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3-fp16-d16
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3-d16-fp16
++MULTILIB_MATCHES       += mfpu?neon=mfpu?neon-fp16
+ MULTILIB_MATCHES       += mfpu?vfpv4-d16=mfpu?vfpv4
++MULTILIB_MATCHES       += mfpu?vfpv4-d16=mfpu?fpv5-d16
++MULTILIB_MATCHES       += mfpu?vfpv4-d16=mfpu?fp-armv8
+ MULTILIB_MATCHES       += mfpu?neon-fp-armv8=mfpu?crypto-neon-fp-armv8
++MULTILIB_MATCHES       += mfpu?vfp=mfpu?vfpv2
++MULTILIB_MATCHES       += mfpu?neon=mfpu?neon-vfpv3
+ 
+ 
+ # Map all requests for vfpv3 with a later CPU to vfpv3-d16 v7-a.
+@@ -124,10 +129,6 @@ MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv8
+ MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp
+ MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard
+ MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp
+-MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.fp-armv8/mfloat-abi.hard
+-MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.fp-armv8/mfloat-abi.softfp
+-MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.vfpv4/mfloat-abi.hard
+-MULTILIB_REUSE	      += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.vfpv4/mfloat-abi.softfp
+ 
+ 
+ MULTILIB_REUSE	      += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7ve/mfpu.neon/mfloat-abi.hard
+@@ -140,10 +141,6 @@ MULTILIB_REUSE	      += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7-a/mf
+ MULTILIB_REUSE	      += march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp
+ 
+ 
+-MULTILIB_REUSE	      += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv7ve/mfpu.fp-armv8/mfloat-abi.hard
+-MULTILIB_REUSE	      += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv7ve/mfpu.fp-armv8/mfloat-abi.softfp
+-MULTILIB_REUSE	      += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv4/mfloat-abi.hard
+-MULTILIB_REUSE	      += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv4/mfloat-abi.softfp
+ MULTILIB_REUSE	      += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard
+ MULTILIB_REUSE	      += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp
+ 
+@@ -163,10 +160,6 @@ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthu
+ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp
+ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard
+ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp
+-MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.fp-armv8/mfloat-abi.hard
+-MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.fp-armv8/mfloat-abi.softfp
+-MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.vfpv4/mfloat-abi.hard
+-MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.vfpv4/mfloat-abi.softfp
+ 
+ 
+ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv7ve/mfpu.neon/mfloat-abi.hard
+@@ -179,10 +172,6 @@ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/ma
+ MULTILIB_REUSE	      += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp
+ 
+ 
+-MULTILIB_REUSE	      += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/march.armv7ve/mfpu.fp-armv8/mfloat-abi.hard
+-MULTILIB_REUSE	      += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/march.armv7ve/mfpu.fp-armv8/mfloat-abi.softfp
+-MULTILIB_REUSE	      += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv4/mfloat-abi.hard
+-MULTILIB_REUSE	      += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv4/mfloat-abi.softfp
+ MULTILIB_REUSE	      += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard
+ MULTILIB_REUSE	      += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp
+ 
+--- a/src/gcc/config/arm/t-arm
++++ b/src/gcc/config/arm/t-arm
+@@ -95,7 +95,8 @@ arm.o: $(srcdir)/config/arm/arm.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
+   $(srcdir)/config/arm/arm-cores.def \
+   $(srcdir)/config/arm/arm-arches.def $(srcdir)/config/arm/arm-fpus.def \
+   $(srcdir)/config/arm/arm-protos.h \
+-  $(srcdir)/config/arm/arm_neon_builtins.def
++  $(srcdir)/config/arm/arm_neon_builtins.def \
++  $(srcdir)/config/arm/arm_vfp_builtins.def
+ 
+ arm-builtins.o: $(srcdir)/config/arm/arm-builtins.c $(CONFIG_H) \
+   $(SYSTEM_H) coretypes.h $(TM_H) \
+@@ -103,6 +104,7 @@ arm-builtins.o: $(srcdir)/config/arm/arm-builtins.c $(CONFIG_H) \
+   $(DIAGNOSTIC_CORE_H) $(OPTABS_H) \
+   $(srcdir)/config/arm/arm-protos.h \
+   $(srcdir)/config/arm/arm_neon_builtins.def \
++  $(srcdir)/config/arm/arm_vfp_builtins.def \
+   $(srcdir)/config/arm/arm-simd-builtin-types.def
+ 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
+ 		$(srcdir)/config/arm/arm-builtins.c
+--- /dev/null
++++ b/src/gcc/config/arm/t-rmprofile
+@@ -0,0 +1,176 @@
++# Copyright (C) 2016 Free Software Foundation, Inc.
++#
++# This file is part of GCC.
++#
++# GCC is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3, or (at your option)
++# any later version.
++#
++# GCC is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with GCC; see the file COPYING3.  If not see
++# <http://www.gnu.org/licenses/>.
++
++# This is a target makefile fragment that attempts to get
++# multilibs built for the range of CPU's, FPU's and ABI's that
++# are relevant for the ARM architecture.  It should not be used in
++# conjunction with another make file fragment and assumes --with-arch,
++# --with-cpu, --with-fpu, --with-float, --with-mode have their default
++# values during the configure step.  We enforce this during the
++# top-level configury.
++
++MULTILIB_OPTIONS     =
++MULTILIB_DIRNAMES    =
++MULTILIB_EXCEPTIONS  =
++MULTILIB_MATCHES     =
++MULTILIB_REUSE       =
++
++# We have the following hierachy:
++#   ISA: A32 (.) or T16/T32 (thumb).
++#   Architecture: ARMv6S-M (v6-m), ARMv7-M (v7-m), ARMv7E-M (v7e-m),
++#                 ARMv8-M Baseline (v8-m.base) or ARMv8-M Mainline (v8-m.main).
++#   FPU: VFPv3-D16 (fpv3), FPV4-SP-D16 (fpv4-sp), FPV5-SP-D16 (fpv5-sp),
++#        VFPv5-D16 (fpv5), or None (.).
++#   Float-abi: Soft (.), softfp (softfp), or hard (hardfp).
++
++# Options to build libraries with
++
++MULTILIB_OPTIONS       += mthumb
++MULTILIB_DIRNAMES      += thumb
++
++MULTILIB_OPTIONS       += march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7/march=armv8-m.base/march=armv8-m.main
++MULTILIB_DIRNAMES      += v6-m v7-m v7e-m v7-ar v8-m.base v8-m.main
++
++MULTILIB_OPTIONS       += mfpu=vfpv3-d16/mfpu=fpv4-sp-d16/mfpu=fpv5-sp-d16/mfpu=fpv5-d16
++MULTILIB_DIRNAMES      += fpv3 fpv4-sp fpv5-sp fpv5
++
++MULTILIB_OPTIONS       += mfloat-abi=softfp/mfloat-abi=hard
++MULTILIB_DIRNAMES      += softfp hard
++
++
++# Option combinations to build library with
++
++# Default CPU/Arch
++MULTILIB_REQUIRED      += mthumb
++MULTILIB_REQUIRED      += mfloat-abi=hard
++
++# ARMv6-M
++MULTILIB_REQUIRED      += mthumb/march=armv6s-m
++
++# ARMv8-M Baseline
++MULTILIB_REQUIRED      += mthumb/march=armv8-m.base
++
++# ARMv7-M
++MULTILIB_REQUIRED      += mthumb/march=armv7-m
++
++# ARMv7E-M
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m/mfpu=fpv4-sp-d16/mfloat-abi=softfp
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m/mfpu=fpv4-sp-d16/mfloat-abi=hard
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m/mfpu=fpv5-d16/mfloat-abi=softfp
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m/mfpu=fpv5-d16/mfloat-abi=hard
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m/mfpu=fpv5-sp-d16/mfloat-abi=softfp
++MULTILIB_REQUIRED      += mthumb/march=armv7e-m/mfpu=fpv5-sp-d16/mfloat-abi=hard
++
++# ARMv8-M Mainline
++MULTILIB_REQUIRED      += mthumb/march=armv8-m.main
++MULTILIB_REQUIRED      += mthumb/march=armv8-m.main/mfpu=fpv5-d16/mfloat-abi=softfp
++MULTILIB_REQUIRED      += mthumb/march=armv8-m.main/mfpu=fpv5-d16/mfloat-abi=hard
++MULTILIB_REQUIRED      += mthumb/march=armv8-m.main/mfpu=fpv5-sp-d16/mfloat-abi=softfp
++MULTILIB_REQUIRED      += mthumb/march=armv8-m.main/mfpu=fpv5-sp-d16/mfloat-abi=hard
++
++# ARMv7-R as well as ARMv7-A and ARMv8-A if aprofile was not specified
++MULTILIB_REQUIRED      += mthumb/march=armv7
++MULTILIB_REQUIRED      += mthumb/march=armv7/mfpu=vfpv3-d16/mfloat-abi=softfp
++MULTILIB_REQUIRED      += mthumb/march=armv7/mfpu=vfpv3-d16/mfloat-abi=hard
++
++
++# Matches
++
++# CPU Matches
++MULTILIB_MATCHES       += march?armv6s-m=mcpu?cortex-m0
++MULTILIB_MATCHES       += march?armv6s-m=mcpu?cortex-m0.small-multiply
++MULTILIB_MATCHES       += march?armv6s-m=mcpu?cortex-m0plus
++MULTILIB_MATCHES       += march?armv6s-m=mcpu?cortex-m0plus.small-multiply
++MULTILIB_MATCHES       += march?armv6s-m=mcpu?cortex-m1
++MULTILIB_MATCHES       += march?armv6s-m=mcpu?cortex-m1.small-multiply
++MULTILIB_MATCHES       += march?armv7-m=mcpu?cortex-m3
++MULTILIB_MATCHES       += march?armv7e-m=mcpu?cortex-m4
++MULTILIB_MATCHES       += march?armv7e-m=mcpu?cortex-m7
++MULTILIB_MATCHES       += march?armv8-m.base=mcpu?cortex-m23
++MULTILIB_MATCHES       += march?armv8-m.main=mcpu?cortex-m33
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-r4
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-r4f
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-r5
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-r7
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-r8
++MULTILIB_MATCHES       += march?armv7=mcpu?marvell-pj4
++MULTILIB_MATCHES       += march?armv7=mcpu?generic-armv7-a
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a8
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a9
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a5
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a7
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a15
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a12
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a17
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a15.cortex-a7
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a17.cortex-a7
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a32
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a35
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a53
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a57
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a57.cortex-a53
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a72
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a72.cortex-a53
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a73
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a73.cortex-a35
++MULTILIB_MATCHES       += march?armv7=mcpu?cortex-a73.cortex-a53
++MULTILIB_MATCHES       += march?armv7=mcpu?exynos-m1
++MULTILIB_MATCHES       += march?armv7=mcpu?qdf24xx
++MULTILIB_MATCHES       += march?armv7=mcpu?xgene1
++
++# Arch Matches
++MULTILIB_MATCHES       += march?armv6s-m=march?armv6-m
++MULTILIB_MATCHES       += march?armv8-m.main=march?armv8-m.main+dsp
++MULTILIB_MATCHES       += march?armv7=march?armv7-r
++ifeq (,$(HAS_APROFILE))
++MULTILIB_MATCHES       += march?armv7=march?armv7-a
++MULTILIB_MATCHES       += march?armv7=march?armv7ve
++MULTILIB_MATCHES       += march?armv7=march?armv8-a
++MULTILIB_MATCHES       += march?armv7=march?armv8-a+crc
++MULTILIB_MATCHES       += march?armv7=march?armv8.1-a
++MULTILIB_MATCHES       += march?armv7=march?armv8.1-a+crc
++MULTILIB_MATCHES       += march?armv7=march?armv8.2-a
++MULTILIB_MATCHES       += march?armv7=march?armv8.2-a+fp16
++endif
++
++# FPU matches
++ifeq (,$(HAS_APROFILE))
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3-fp16
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv3-d16-fp16
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?neon
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?neon-fp16
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv4
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?vfpv4-d16
++MULTILIB_MATCHES       += mfpu?vfpv3-d16=mfpu?neon-vfpv4
++MULTILIB_MATCHES       += mfpu?fpv5-d16=mfpu?fp-armv8
++MULTILIB_MATCHES       += mfpu?fpv5-d16=mfpu?neon-fp-armv8
++MULTILIB_MATCHES       += mfpu?fpv5-d16=mfpu?crypto-neon-fp-armv8
++endif
++
++
++# We map all requests for ARMv7-R or ARMv7-A in ARM mode to Thumb mode and
++# any FPU to VFPv3-d16 if possible.
++MULTILIB_REUSE         += mthumb/march.armv7=march.armv7
++MULTILIB_REUSE         += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp
++MULTILIB_REUSE         += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard
++MULTILIB_REUSE         += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7/mfpu.fpv5-d16/mfloat-abi.softfp
++MULTILIB_REUSE         += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7/mfpu.fpv5-d16/mfloat-abi.hard
++MULTILIB_REUSE         += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7/mfpu.fpv5-d16/mfloat-abi.softfp
++MULTILIB_REUSE         += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7/mfpu.fpv5-d16/mfloat-abi.hard
+--- a/src/gcc/config/arm/thumb1.md
++++ b/src/gcc/config/arm/thumb1.md
+@@ -55,6 +55,10 @@
+    (set_attr "type" "multiple")]
+ )
+ 
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic additions in sync.md and to the logic for bind_old_new in
++;; arm_split_atomic_op in arm.c.  These must be at least as strict as the
++;; constraints here and aim to be as permissive.
+ (define_insn_and_split "*thumb1_addsi3"
+   [(set (match_operand:SI          0 "register_operand" "=l,l,l,*rk,*hk,l,k,l,l,l")
+ 	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,l,*0,*0,k,k,0,l,k")
+@@ -114,8 +118,8 @@
+    (set (match_dup 0)
+ 	(plus:SI (match_dup 0) (reg:SI SP_REGNUM)))]
+   "TARGET_THUMB1
+-   && (unsigned HOST_WIDE_INT) (INTVAL (operands[1])) < 1024
+-   && (INTVAL (operands[1]) & 3) == 0"
++   && UINTVAL (operands[1]) < 1024
++   && (UINTVAL (operands[1]) & 3) == 0"
+   [(set (match_dup 0) (plus:SI (reg:SI SP_REGNUM) (match_dup 1)))]
+   ""
+ )
+@@ -131,6 +135,10 @@
+    (set_attr "type" "multiple")]
+ )
+ 
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic subtractions in sync.md and to the logic for bind_old_new in
++;; arm_split_atomic_op in arm.c.  These must be at least as strict as the
++;; constraints here and aim to be as permissive.
+ (define_insn "thumb1_subsi3_insn"
+   [(set (match_operand:SI           0 "register_operand" "=l")
+ 	(minus:SI (match_operand:SI 1 "register_operand" "l")
+@@ -142,11 +150,11 @@
+    (set_attr "type" "alus_sreg")]
+ )
+ 
+-; Unfortunately with the Thumb the '&'/'0' trick can fails when operands
+-; 1 and 2; are the same, because reload will make operand 0 match
+-; operand 1 without realizing that this conflicts with operand 2.  We fix
+-; this by adding another alternative to match this case, and then `reload'
+-; it ourselves.  This alternative must come first.
++;; Unfortunately on Thumb the '&'/'0' trick can fail when operands
++;; 1 and 2 are the same, because reload will make operand 0 match
++;; operand 1 without realizing that this conflicts with operand 2.  We fix
++;; this by adding another alternative to match this case, and then `reload'
++;; it ourselves.  This alternative must come first.
+ (define_insn "*thumb_mulsi3"
+   [(set (match_operand:SI          0 "register_operand" "=&l,&l,&l")
+ 	(mult:SI (match_operand:SI 1 "register_operand" "%l,*h,0")
+@@ -173,6 +181,10 @@
+    (set_attr "type" "muls")]
+ )
+ 
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic bitwise ANDs and NANDs in sync.md and to the logic for bind_old_new
++;; in arm_split_atomic_op in arm.c.  These must be at least as strict as the
++;; constraints here and aim to be as permissive.
+ (define_insn "*thumb1_andsi3_insn"
+   [(set (match_operand:SI         0 "register_operand" "=l")
+ 	(and:SI (match_operand:SI 1 "register_operand" "%0")
+@@ -227,6 +239,10 @@
+    (set_attr "type" "logics_reg")]
+ )
+ 
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic inclusive ORs in sync.md and to the logic for bind_old_new in
++;; arm_split_atomic_op in arm.c.  These must be at least as strict as the
++;; constraints here and aim to be as permissive.
+ (define_insn "*thumb1_iorsi3_insn"
+   [(set (match_operand:SI         0 "register_operand" "=l")
+ 	(ior:SI (match_operand:SI 1 "register_operand" "%0")
+@@ -237,6 +253,10 @@
+    (set_attr "conds" "set")
+    (set_attr "type" "logics_reg")])
+ 
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic exclusive ORs in sync.md and to the logic for bind_old_new in
++;; arm_split_atomic_op in arm.c.  These must be at least as strict as the
++;; constraints here and aim to be as permissive.
+ (define_insn "*thumb1_xorsi3_insn"
+   [(set (match_operand:SI         0 "register_operand" "=l")
+ 	(xor:SI (match_operand:SI 1 "register_operand" "%0")
+@@ -590,8 +610,8 @@
+ ;;; ??? The 'i' constraint looks funny, but it should always be replaced by
+ ;;; thumb_reorg with a memory reference.
+ (define_insn "*thumb1_movdi_insn"
+-  [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r")
+-	(match_operand:DI 1 "general_operand"      "l, I,J,>,l,mi,l,*r"))]
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,r,l,>,l, m,*r")
++	(match_operand:DI 1 "general_operand"      "l, I,J,j,>,l,mi,l,*r"))]
+   "TARGET_THUMB1
+    && (   register_operand (operands[0], DImode)
+        || register_operand (operands[1], DImode))"
+@@ -610,36 +630,41 @@
+       operands[1] = GEN_INT (- INTVAL (operands[1]));
+       return \"movs\\t%Q0, %1\;rsbs\\t%Q0, %Q0, #0\;asrs\\t%R0, %Q0, #31\";
+     case 3:
+-      return \"ldmia\\t%1, {%0, %H0}\";
++      gcc_assert (TARGET_HAVE_MOVT);
++      return \"movw\\t%Q0, %L1\;movs\\tR0, #0\";
+     case 4:
+-      return \"stmia\\t%0, {%1, %H1}\";
++      return \"ldmia\\t%1, {%0, %H0}\";
+     case 5:
+-      return thumb_load_double_from_address (operands);
++      return \"stmia\\t%0, {%1, %H1}\";
+     case 6:
++      return thumb_load_double_from_address (operands);
++    case 7:
+       operands[2] = gen_rtx_MEM (SImode,
+ 			     plus_constant (Pmode, XEXP (operands[0], 0), 4));
+       output_asm_insn (\"str\\t%1, %0\;str\\t%H1, %2\", operands);
+       return \"\";
+-    case 7:
++    case 8:
+       if (REGNO (operands[1]) == REGNO (operands[0]) + 1)
+ 	return \"mov\\t%0, %1\;mov\\t%H0, %H1\";
+       return \"mov\\t%H0, %H1\;mov\\t%0, %1\";
+     }
+   }"
+-  [(set_attr "length" "4,4,6,2,2,6,4,4")
+-   (set_attr "type" "multiple,multiple,multiple,load2,store2,load2,store2,multiple")
+-   (set_attr "pool_range" "*,*,*,*,*,1018,*,*")]
++  [(set_attr "length" "4,4,6,6,2,2,6,4,4")
++   (set_attr "type" "multiple,multiple,multiple,multiple,load2,store2,load2,store2,multiple")
++   (set_attr "arch" "t1,t1,t1,v8mb,t1,t1,t1,t1,t1")
++   (set_attr "pool_range" "*,*,*,*,*,*,1018,*,*")]
+ )
+ 
+ (define_insn "*thumb1_movsi_insn"
+-  [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*l*h*k")
+-	(match_operand:SI 1 "general_operand"      "l, I,J,K,>,l,mi,l,*l*h*k"))]
++  [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,r,l,l,l,>,l, m,*l*h*k")
++	(match_operand:SI 1 "general_operand"      "l, I,j,J,K,>,l,mi,l,*l*h*k"))]
+   "TARGET_THUMB1
+    && (   register_operand (operands[0], SImode)
+        || register_operand (operands[1], SImode))"
+   "@
+    movs	%0, %1
+    movs	%0, %1
++   movw	%0, %1
+    #
+    #
+    ldmia\\t%1, {%0}
+@@ -647,10 +672,11 @@
+    ldr\\t%0, %1
+    str\\t%1, %0
+    mov\\t%0, %1"
+-  [(set_attr "length" "2,2,4,4,2,2,2,2,2")
+-   (set_attr "type" "mov_reg,mov_imm,multiple,multiple,load1,store1,load1,store1,mov_reg")
+-   (set_attr "pool_range" "*,*,*,*,*,*,1018,*,*")
+-   (set_attr "conds" "set,clob,*,*,nocond,nocond,nocond,nocond,nocond")])
++  [(set_attr "length" "2,2,4,4,4,2,2,2,2,2")
++   (set_attr "type" "mov_reg,mov_imm,mov_imm,multiple,multiple,load1,store1,load1,store1,mov_reg")
++   (set_attr "pool_range" "*,*,*,*,*,*,*,1018,*,*")
++   (set_attr "arch" "t1,t1,v8mb,t1,t1,t1,t1,t1,t1,t1")
++   (set_attr "conds" "set,clob,nocond,*,*,nocond,nocond,nocond,nocond,nocond")])
+ 
+ ; Split the load of 64-bit constant into two loads for high and low 32-bit parts respectively
+ ; to see if we can load them in fewer instructions or fewer cycles.
+@@ -687,7 +713,8 @@
+ (define_split
+   [(set (match_operand:SI 0 "register_operand" "")
+ 	(match_operand:SI 1 "const_int_operand" ""))]
+-  "TARGET_THUMB1 && satisfies_constraint_K (operands[1])"
++  "TARGET_THUMB1 && satisfies_constraint_K (operands[1])
++   && !(TARGET_HAVE_MOVT && satisfies_constraint_j (operands[1]))"
+   [(set (match_dup 2) (match_dup 1))
+    (set (match_dup 0) (ashift:SI (match_dup 2) (match_dup 3)))]
+   "
+@@ -714,7 +741,8 @@
+ (define_split
+   [(set (match_operand:SI 0 "register_operand" "")
+ 	(match_operand:SI 1 "const_int_operand" ""))]
+-  "TARGET_THUMB1 && satisfies_constraint_Pe (operands[1])"
++  "TARGET_THUMB1 && satisfies_constraint_Pe (operands[1])
++   && !(TARGET_HAVE_MOVT && satisfies_constraint_j (operands[1]))"
+   [(set (match_dup 2) (match_dup 1))
+    (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 3)))]
+   "
+@@ -726,8 +754,8 @@
+ )
+ 
+ (define_insn "*thumb1_movhi_insn"
+-  [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,l*r,*h,l")
+-	(match_operand:HI 1 "general_operand"       "l,m,l,k*h,*r,I"))]
++  [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,l*r,*h,l,r")
++	(match_operand:HI 1 "general_operand"       "l,m,l,k*h,*r,I,n"))]
+   "TARGET_THUMB1
+    && (   register_operand (operands[0], HImode)
+        || register_operand (operands[1], HImode))"
+@@ -739,6 +767,8 @@
+     case 3: return \"mov	%0, %1\";
+     case 4: return \"mov	%0, %1\";
+     case 5: return \"movs	%0, %1\";
++    case 6: gcc_assert (TARGET_HAVE_MOVT);
++	    return \"movw	%0, %L1\";
+     default: gcc_unreachable ();
+     case 1:
+       /* The stack pointer can end up being taken as an index register.
+@@ -758,9 +788,10 @@
+ 	}
+       return \"ldrh	%0, %1\";
+     }"
+-  [(set_attr "length" "2,4,2,2,2,2")
+-   (set_attr "type" "alus_imm,load1,store1,mov_reg,mov_reg,mov_imm")
+-   (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")])
++  [(set_attr "length" "2,4,2,2,2,2,4")
++   (set_attr "type" "alus_imm,load1,store1,mov_reg,mov_reg,mov_imm,mov_imm")
++   (set_attr "arch" "t1,t1,t1,t1,t1,t1,v8mb")
++   (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob,nocond")])
+ 
+ (define_expand "thumb_movhi_clobber"
+   [(set (match_operand:HI     0 "memory_operand"   "")
+@@ -963,6 +994,94 @@
+   DONE;
+ })
+ 
++;; A pattern for the CB(N)Z instruction added in ARMv8-M Baseline profile,
++;; adapted from cbranchsi4_insn.  Modifying cbranchsi4_insn instead leads to
++;; code generation difference for ARMv6-M because the minimum length of the
++;; instruction becomes 2 even for ARMv6-M due to a limitation in genattrtab's
++;; handling of PC in the length condition.
++(define_insn "thumb1_cbz"
++  [(set (pc) (if_then_else
++	      (match_operator 0 "equality_operator"
++	       [(match_operand:SI 1 "s_register_operand" "l")
++		(const_int 0)])
++	      (label_ref (match_operand 2 "" ""))
++	      (pc)))]
++  "TARGET_THUMB1 && TARGET_HAVE_CBZ"
++{
++  if (get_attr_length (insn) == 2)
++    {
++      if (GET_CODE (operands[0]) == EQ)
++	return "cbz\t%1, %l2";
++      else
++	return "cbnz\t%1, %l2";
++    }
++  else
++    {
++      rtx t = cfun->machine->thumb1_cc_insn;
++      if (t != NULL_RTX)
++	{
++	  if (!rtx_equal_p (cfun->machine->thumb1_cc_op0, operands[1])
++	      || !rtx_equal_p (cfun->machine->thumb1_cc_op1, operands[2]))
++	    t = NULL_RTX;
++	  if (cfun->machine->thumb1_cc_mode == CC_NOOVmode)
++	    {
++	      if (!noov_comparison_operator (operands[0], VOIDmode))
++		t = NULL_RTX;
++	    }
++	  else if (cfun->machine->thumb1_cc_mode != CCmode)
++	    t = NULL_RTX;
++	}
++      if (t == NULL_RTX)
++	{
++	  output_asm_insn ("cmp\t%1, #0", operands);
++	  cfun->machine->thumb1_cc_insn = insn;
++	  cfun->machine->thumb1_cc_op0 = operands[1];
++	  cfun->machine->thumb1_cc_op1 = operands[2];
++	  cfun->machine->thumb1_cc_mode = CCmode;
++	}
++      else
++	/* Ensure we emit the right type of condition code on the jump.  */
++	XEXP (operands[0], 0) = gen_rtx_REG (cfun->machine->thumb1_cc_mode,
++					     CC_REGNUM);
++
++      switch (get_attr_length (insn))
++	{
++	case 4:  return "b%d0\t%l2";
++	case 6:  return "b%D0\t.LCB%=;b\t%l2\t%@long jump\n.LCB%=:";
++	case 8:  return "b%D0\t.LCB%=;bl\t%l2\t%@far jump\n.LCB%=:";
++	default: gcc_unreachable ();
++	}
++    }
++}
++  [(set (attr "far_jump")
++	(if_then_else
++	    (eq_attr "length" "8")
++	    (const_string "yes")
++	    (const_string "no")))
++   (set (attr "length")
++	(if_then_else
++	    (and (ge (minus (match_dup 2) (pc)) (const_int 2))
++		 (le (minus (match_dup 2) (pc)) (const_int 128)))
++	    (const_int 2)
++	    (if_then_else
++		(and (ge (minus (match_dup 2) (pc)) (const_int -250))
++		     (le (minus (match_dup 2) (pc)) (const_int 256)))
++		(const_int 4)
++		(if_then_else
++		    (and (ge (minus (match_dup 2) (pc)) (const_int -2040))
++			 (le (minus (match_dup 2) (pc)) (const_int 2048)))
++		    (const_int 6)
++		    (const_int 8)))))
++   (set (attr "type")
++	(if_then_else
++	    (eq_attr "length" "2")
++	    (const_string "branch")
++	    (const_string "multiple")))]
++)
++
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic compare_and_swap splitters in sync.md.  These must be at least as
++;; strict as the constraints here and aim to be as permissive.
+ (define_insn "cbranchsi4_insn"
+   [(set (pc) (if_then_else
+ 	      (match_operator 0 "arm_comparison_operator"
+@@ -1024,6 +1143,9 @@
+    (set_attr "type" "multiple")]
+ )
+ 
++;; Changes to the constraints of this pattern must be propagated to those of
++;; atomic compare_and_swap splitters in sync.md.  These must be at least as
++;; strict as the constraints here and aim to be as permissive.
+ (define_insn "cbranchsi4_scratch"
+   [(set (pc) (if_then_else
+ 	      (match_operator 4 "arm_comparison_operator"
+@@ -1609,6 +1731,19 @@
+    (set_attr "type" "call")]
+ )
+ 
++(define_insn "*nonsecure_call_reg_thumb1_v5"
++  [(call (unspec:SI [(mem:SI (match_operand:SI 0 "register_operand" "l*r"))]
++		    UNSPEC_NONSECURE_MEM)
++	 (match_operand 1 "" ""))
++   (use (match_operand 2 "" ""))
++   (clobber (reg:SI LR_REGNUM))
++   (clobber (match_dup 0))]
++  "TARGET_THUMB1 && use_cmse && !SIBLING_CALL_P (insn)"
++  "bl\\t__gnu_cmse_nonsecure_call"
++  [(set_attr "length" "4")
++   (set_attr "type" "call")]
++)
++
+ (define_insn "*call_reg_thumb1"
+   [(call (mem:SI (match_operand:SI 0 "register_operand" "l*r"))
+ 	 (match_operand 1 "" ""))
+@@ -1641,6 +1776,21 @@
+    (set_attr "type" "call")]
+ )
+ 
++(define_insn "*nonsecure_call_value_reg_thumb1_v5"
++  [(set (match_operand 0 "" "")
++	(call (unspec:SI
++	       [(mem:SI (match_operand:SI 1 "register_operand" "l*r"))]
++	       UNSPEC_NONSECURE_MEM)
++	      (match_operand 2 "" "")))
++   (use (match_operand 3 "" ""))
++   (clobber (reg:SI LR_REGNUM))
++   (clobber (match_dup 1))]
++  "TARGET_THUMB1 && use_cmse"
++  "bl\\t__gnu_cmse_nonsecure_call"
++  [(set_attr "length" "4")
++   (set_attr "type" "call")]
++)
++
+ (define_insn "*call_value_reg_thumb1"
+   [(set (match_operand 0 "" "")
+ 	(call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
+@@ -1747,8 +1897,13 @@
+   "*
+     return thumb1_unexpanded_epilogue ();
+   "
+-  ; Length is absolute worst case
+-  [(set_attr "length" "44")
++  ; Length is absolute worst case, when using CMSE and if this is an entry
++  ; function an extra 4 (MSR) bytes will be added.
++  [(set (attr "length")
++	(if_then_else
++	 (match_test "IS_CMSE_ENTRY (arm_current_func_type ())")
++	 (const_int 48)
++	 (const_int 44)))
+    (set_attr "type" "block")
+    ;; We don't clobber the conditions, but the potential length of this
+    ;; operation is sufficient to make conditionalizing the sequence
+--- a/src/gcc/config/arm/thumb2.md
++++ b/src/gcc/config/arm/thumb2.md
+@@ -125,32 +125,6 @@
+    (set_attr "type" "multiple")]
+ )
+ 
+-;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
+-(define_insn_and_split "*thumb2_negdi2"
+-  [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
+-	(neg:DI (match_operand:DI 1 "s_register_operand"  "?r,0")))
+-   (clobber (reg:CC CC_REGNUM))]
+-  "TARGET_THUMB2"
+-  "#" ; negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1
+-  "&& reload_completed"
+-  [(parallel [(set (reg:CC CC_REGNUM)
+-		   (compare:CC (const_int 0) (match_dup 1)))
+-	      (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
+-   (set (match_dup 2) (minus:SI (minus:SI (match_dup 3)
+-                                          (ashift:SI (match_dup 3)
+-                                                     (const_int 1)))
+-                                (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
+-  {
+-    operands[2] = gen_highpart (SImode, operands[0]);
+-    operands[0] = gen_lowpart (SImode, operands[0]);
+-    operands[3] = gen_highpart (SImode, operands[1]);
+-    operands[1] = gen_lowpart (SImode, operands[1]);
+-  }
+-  [(set_attr "conds" "clob")
+-   (set_attr "length" "8")
+-   (set_attr "type" "multiple")]
+-)
+-
+ (define_insn_and_split "*thumb2_abssi2"
+   [(set (match_operand:SI         0 "s_register_operand" "=&r,l,r")
+ 	(abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0")))
+@@ -278,8 +252,7 @@
+ (define_insn "*thumb2_movsi_insn"
+   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l ,*hk,m,*m")
+ 	(match_operand:SI 1 "general_operand"	   "rk,I,Py,K,j,mi,*mi,l,*hk"))]
+-  "TARGET_THUMB2 && ! TARGET_IWMMXT
+-   && !(TARGET_HARD_FLOAT && TARGET_VFP)
++  "TARGET_THUMB2 && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
+    && (   register_operand (operands[0], SImode)
+        || register_operand (operands[1], SImode))"
+   "@
+@@ -581,6 +554,19 @@
+   [(set_attr "type" "call")]
+ )
+ 
++(define_insn "*nonsecure_call_reg_thumb2"
++  [(call (unspec:SI [(mem:SI (match_operand:SI 0 "s_register_operand" "r"))]
++		    UNSPEC_NONSECURE_MEM)
++	 (match_operand 1 "" ""))
++   (use (match_operand 2 "" ""))
++   (clobber (reg:SI LR_REGNUM))
++   (clobber (match_dup 0))]
++  "TARGET_THUMB2 && use_cmse"
++  "bl\\t__gnu_cmse_nonsecure_call"
++  [(set_attr "length" "4")
++   (set_attr "type" "call")]
++)
++
+ (define_insn "*call_value_reg_thumb2"
+   [(set (match_operand 0 "" "")
+ 	(call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
+@@ -592,6 +578,21 @@
+   [(set_attr "type" "call")]
+ )
+ 
++(define_insn "*nonsecure_call_value_reg_thumb2"
++  [(set (match_operand 0 "" "")
++	(call
++	 (unspec:SI [(mem:SI (match_operand:SI 1 "register_operand" "l*r"))]
++		    UNSPEC_NONSECURE_MEM)
++	 (match_operand 2 "" "")))
++   (use (match_operand 3 "" ""))
++   (clobber (reg:SI LR_REGNUM))
++   (clobber (match_dup 1))]
++  "TARGET_THUMB2 && use_cmse"
++  "bl\t__gnu_cmse_nonsecure_call"
++  [(set_attr "length" "4")
++   (set_attr "type" "call")]
++)
++
+ (define_insn "*thumb2_indirect_jump"
+   [(set (pc)
+ 	(match_operand:SI 0 "register_operand" "l*r"))]
+@@ -1115,12 +1116,31 @@
+ 
+ (define_insn "*thumb2_return"
+   [(simple_return)]
+-  "TARGET_THUMB2"
++  "TARGET_THUMB2 && !IS_CMSE_ENTRY (arm_current_func_type ())"
+   "* return output_return_instruction (const_true_rtx, true, false, true);"
+   [(set_attr "type" "branch")
+    (set_attr "length" "4")]
+ )
+ 
++(define_insn "*thumb2_cmse_entry_return"
++  [(simple_return)]
++  "TARGET_THUMB2 && IS_CMSE_ENTRY (arm_current_func_type ())"
++  "* return output_return_instruction (const_true_rtx, true, false, true);"
++  [(set_attr "type" "branch")
++   ; This is a return from a cmse_nonsecure_entry function so code will be
++   ; added to clear the APSR and potentially the FPSCR if VFP is available, so
++   ; we adapt the length accordingly.
++   (set (attr "length")
++     (if_then_else (match_test "TARGET_HARD_FLOAT")
++      (const_int 12)
++      (const_int 8)))
++   ; We do not support predicate execution of returns from cmse_nonsecure_entry
++   ; functions because we need to clear the APSR.  Since predicable has to be
++   ; a constant, we had to duplicate the thumb2_return pattern for CMSE entry
++   ; functions.
++   (set_attr "predicable" "no")]
++)
++
+ (define_insn_and_split "thumb2_eh_return"
+   [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
+ 		    VUNSPEC_EH_RETURN)
+--- a/src/gcc/config/arm/types.md
++++ b/src/gcc/config/arm/types.md
+@@ -51,6 +51,7 @@
+ ; alus_shift_imm     as alu_shift_imm, setting condition flags.
+ ; alus_shift_reg     as alu_shift_reg, setting condition flags.
+ ; bfm                bitfield move operation.
++; bfx                bitfield extract operation.
+ ; block              blockage insn, this blocks all functional units.
+ ; branch             branch.
+ ; call               subroutine call.
+@@ -557,6 +558,7 @@
+   alus_shift_imm,\
+   alus_shift_reg,\
+   bfm,\
++  bfx,\
+   block,\
+   branch,\
+   call,\
+--- a/src/gcc/config/arm/unspecs.md
++++ b/src/gcc/config/arm/unspecs.md
+@@ -84,6 +84,8 @@
+   UNSPEC_VRINTA         ; Represent a float to integral float rounding
+                         ; towards nearest, ties away from zero.
+   UNSPEC_PROBE_STACK    ; Probe stack memory reference
++  UNSPEC_NONSECURE_MEM	; Represent non-secure memory in ARMv8-M with
++			; security extension
+ ])
+ 
+ (define_c_enum "unspec" [
+@@ -191,6 +193,8 @@
+   UNSPEC_VBSL
+   UNSPEC_VCAGE
+   UNSPEC_VCAGT
++  UNSPEC_VCALE
++  UNSPEC_VCALT
+   UNSPEC_VCEQ
+   UNSPEC_VCGE
+   UNSPEC_VCGEU
+@@ -203,6 +207,20 @@
+   UNSPEC_VCVT_U
+   UNSPEC_VCVT_S_N
+   UNSPEC_VCVT_U_N
++  UNSPEC_VCVT_HF_S_N
++  UNSPEC_VCVT_HF_U_N
++  UNSPEC_VCVT_SI_S_N
++  UNSPEC_VCVT_SI_U_N
++  UNSPEC_VCVTH_S
++  UNSPEC_VCVTH_U
++  UNSPEC_VCVTA_S
++  UNSPEC_VCVTA_U
++  UNSPEC_VCVTM_S
++  UNSPEC_VCVTM_U
++  UNSPEC_VCVTN_S
++  UNSPEC_VCVTN_U
++  UNSPEC_VCVTP_S
++  UNSPEC_VCVTP_U
+   UNSPEC_VEXT
+   UNSPEC_VHADD_S
+   UNSPEC_VHADD_U
+@@ -244,6 +262,8 @@
+   UNSPEC_VMLSL_S_LANE
+   UNSPEC_VMLSL_U_LANE
+   UNSPEC_VMLSL_LANE
++  UNSPEC_VFMA_LANE
++  UNSPEC_VFMS_LANE
+   UNSPEC_VMOVL_S
+   UNSPEC_VMOVL_U
+   UNSPEC_VMOVN
+@@ -365,5 +385,11 @@
+   UNSPEC_NVRINTN
+   UNSPEC_VQRDMLAH
+   UNSPEC_VQRDMLSH
++  UNSPEC_VRND
++  UNSPEC_VRNDA
++  UNSPEC_VRNDI
++  UNSPEC_VRNDM
++  UNSPEC_VRNDN
++  UNSPEC_VRNDP
++  UNSPEC_VRNDX
+ ])
+-
+--- a/src/gcc/config/arm/vec-common.md
++++ b/src/gcc/config/arm/vec-common.md
+@@ -124,6 +124,20 @@
+     FAIL;
+ })
+ 
++(define_expand "vec_perm_const<mode>"
++  [(match_operand:VH 0 "s_register_operand")
++   (match_operand:VH 1 "s_register_operand")
++   (match_operand:VH 2 "s_register_operand")
++   (match_operand:<V_cmp_result> 3)]
++  "TARGET_NEON"
++{
++  if (arm_expand_vec_perm_const (operands[0], operands[1],
++				 operands[2], operands[3]))
++    DONE;
++  else
++    FAIL;
++})
++
+ (define_expand "vec_perm<mode>"
+   [(match_operand:VE 0 "s_register_operand" "")
+    (match_operand:VE 1 "s_register_operand" "")
+--- a/src/gcc/config/arm/vfp.md
++++ b/src/gcc/config/arm/vfp.md
+@@ -18,13 +18,206 @@
+ ;; along with GCC; see the file COPYING3.  If not see
+ ;; <http://www.gnu.org/licenses/>.  */
+ 
++;; Patterns for HI moves which provide more data transfer instructions when VFP
++;; support is enabled.
++(define_insn "*arm_movhi_vfp"
++ [(set
++   (match_operand:HI 0 "nonimmediate_operand"
++    "=rk,  r, r, m, r, *t,  r, *t")
++   (match_operand:HI 1 "general_operand"
++    "rIk, K, n, r, mi, r, *t, *t"))]
++ "TARGET_ARM && TARGET_HARD_FLOAT
++  && !TARGET_VFP_FP16INST
++  && (register_operand (operands[0], HImode)
++       || register_operand (operands[1], HImode))"
++{
++  switch (which_alternative)
++    {
++    case 0:
++      return "mov%?\t%0, %1\t%@ movhi";
++    case 1:
++      return "mvn%?\t%0, #%B1\t%@ movhi";
++    case 2:
++      return "movw%?\t%0, %L1\t%@ movhi";
++    case 3:
++      return "strh%?\t%1, %0\t%@ movhi";
++    case 4:
++      return "ldrh%?\t%0, %1\t%@ movhi";
++    case 5:
++    case 6:
++      return "vmov%?\t%0, %1\t%@ int";
++    case 7:
++      return "vmov%?.f32\t%0, %1\t%@ int";
++    default:
++      gcc_unreachable ();
++    }
++}
++ [(set_attr "predicable" "yes")
++  (set_attr_alternative "type"
++   [(if_then_else
++     (match_operand 1 "const_int_operand" "")
++     (const_string "mov_imm")
++     (const_string "mov_reg"))
++    (const_string "mvn_imm")
++    (const_string "mov_imm")
++    (const_string "store1")
++    (const_string "load1")
++    (const_string "f_mcr")
++    (const_string "f_mrc")
++    (const_string "fmov")])
++  (set_attr "arch" "*, *, v6t2, *, *, *, *, *")
++  (set_attr "pool_range" "*, *, *, *, 256, *, *, *")
++  (set_attr "neg_pool_range" "*, *, *, *, 244, *, *, *")
++  (set_attr "length" "4")]
++)
++
++(define_insn "*thumb2_movhi_vfp"
++ [(set
++   (match_operand:HI 0 "nonimmediate_operand"
++    "=rk, r, l, r, m, r, *t, r, *t")
++   (match_operand:HI 1 "general_operand"
++    "rk, I, Py, n, r, m, r, *t, *t"))]
++ "TARGET_THUMB2 && TARGET_HARD_FLOAT
++  && !TARGET_VFP_FP16INST
++  && (register_operand (operands[0], HImode)
++       || register_operand (operands[1], HImode))"
++{
++  switch (which_alternative)
++    {
++    case 0:
++    case 1:
++    case 2:
++      return "mov%?\t%0, %1\t%@ movhi";
++    case 3:
++      return "movw%?\t%0, %L1\t%@ movhi";
++    case 4:
++      return "strh%?\t%1, %0\t%@ movhi";
++    case 5:
++      return "ldrh%?\t%0, %1\t%@ movhi";
++    case 6:
++    case 7:
++      return "vmov%?\t%0, %1\t%@ int";
++    case 8:
++      return "vmov%?.f32\t%0, %1\t%@ int";
++    default:
++      gcc_unreachable ();
++    }
++}
++ [(set_attr "predicable" "yes")
++  (set_attr "predicable_short_it"
++   "yes, no, yes, no, no, no, no, no, no")
++  (set_attr "type"
++   "mov_reg, mov_imm, mov_imm, mov_imm, store1, load1,\
++    f_mcr, f_mrc, fmov")
++  (set_attr "arch" "*, *, *, v6t2, *, *, *, *, *")
++  (set_attr "pool_range" "*, *, *, *, *, 4094, *, *, *")
++  (set_attr "neg_pool_range" "*, *, *, *, *, 250, *, *, *")
++  (set_attr "length" "2, 4, 2, 4, 4, 4, 4, 4, 4")]
++)
++
++;; Patterns for HI moves which provide more data transfer instructions when FP16
++;; instructions are available.
++(define_insn "*arm_movhi_fp16"
++ [(set
++   (match_operand:HI 0 "nonimmediate_operand"
++    "=r,  r, r, m, r, *t,  r, *t")
++   (match_operand:HI 1 "general_operand"
++    "rIk, K, n, r, mi, r, *t, *t"))]
++ "TARGET_ARM && TARGET_VFP_FP16INST
++  && (register_operand (operands[0], HImode)
++       || register_operand (operands[1], HImode))"
++{
++  switch (which_alternative)
++    {
++    case 0:
++      return "mov%?\t%0, %1\t%@ movhi";
++    case 1:
++      return "mvn%?\t%0, #%B1\t%@ movhi";
++    case 2:
++      return "movw%?\t%0, %L1\t%@ movhi";
++    case 3:
++      return "strh%?\t%1, %0\t%@ movhi";
++    case 4:
++      return "ldrh%?\t%0, %1\t%@ movhi";
++    case 5:
++    case 6:
++      return "vmov.f16\t%0, %1\t%@ int";
++    case 7:
++      return "vmov%?.f32\t%0, %1\t%@ int";
++    default:
++      gcc_unreachable ();
++    }
++}
++ [(set_attr "predicable" "yes, yes, yes, yes, yes, no, no, yes")
++  (set_attr_alternative "type"
++   [(if_then_else
++     (match_operand 1 "const_int_operand" "")
++     (const_string "mov_imm")
++     (const_string "mov_reg"))
++    (const_string "mvn_imm")
++    (const_string "mov_imm")
++    (const_string "store1")
++    (const_string "load1")
++    (const_string "f_mcr")
++    (const_string "f_mrc")
++    (const_string "fmov")])
++  (set_attr "arch" "*, *, v6t2, *, *, *, *, *")
++  (set_attr "pool_range" "*, *, *, *, 256, *, *, *")
++  (set_attr "neg_pool_range" "*, *, *, *, 244, *, *, *")
++  (set_attr "length" "4")]
++)
++
++(define_insn "*thumb2_movhi_fp16"
++ [(set
++   (match_operand:HI 0 "nonimmediate_operand"
++    "=rk, r, l, r, m, r, *t, r, *t")
++   (match_operand:HI 1 "general_operand"
++    "rk, I, Py, n, r, m, r, *t, *t"))]
++ "TARGET_THUMB2 && TARGET_VFP_FP16INST
++  && (register_operand (operands[0], HImode)
++       || register_operand (operands[1], HImode))"
++{
++  switch (which_alternative)
++    {
++    case 0:
++    case 1:
++    case 2:
++      return "mov%?\t%0, %1\t%@ movhi";
++    case 3:
++      return "movw%?\t%0, %L1\t%@ movhi";
++    case 4:
++      return "strh%?\t%1, %0\t%@ movhi";
++    case 5:
++      return "ldrh%?\t%0, %1\t%@ movhi";
++    case 6:
++    case 7:
++      return "vmov.f16\t%0, %1\t%@ int";
++    case 8:
++      return "vmov%?.f32\t%0, %1\t%@ int";
++    default:
++      gcc_unreachable ();
++    }
++}
++ [(set_attr "predicable"
++   "yes, yes, yes, yes, yes, yes, no, no, yes")
++  (set_attr "predicable_short_it"
++   "yes, no, yes, no, no, no, no, no, no")
++  (set_attr "type"
++   "mov_reg, mov_imm, mov_imm, mov_imm, store1, load1,\
++    f_mcr, f_mrc, fmov")
++  (set_attr "arch" "*, *, *, v6t2, *, *, *, *, *")
++  (set_attr "pool_range" "*, *, *, *, *, 4094, *, *, *")
++  (set_attr "neg_pool_range" "*, *, *, *, *, 250, *, *, *")
++  (set_attr "length" "2, 4, 2, 4, 4, 4, 4, 4, 4")]
++)
++
+ ;; SImode moves
+ ;; ??? For now do not allow loading constants into vfp regs.  This causes
+ ;; problems because small constants get converted into adds.
+ (define_insn "*arm_movsi_vfp"
+   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
+       (match_operand:SI 1 "general_operand"	   "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
+-  "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
++  "TARGET_ARM && TARGET_HARD_FLOAT
+    && (   s_register_operand (operands[0], SImode)
+        || s_register_operand (operands[1], SImode))"
+   "*
+@@ -53,7 +246,8 @@
+     }
+   "
+   [(set_attr "predicable" "yes")
+-   (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
++   (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,
++		     f_mcr,f_mrc,fmov,f_loads,f_stores")
+    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
+    (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
+ )
+@@ -66,7 +260,7 @@
+ (define_insn "*thumb2_movsi_vfp"
+   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r, l,*hk,m, *m,*t, r,*t,*t,  *Uv")
+ 	(match_operand:SI 1 "general_operand"	   "rk,I,Py,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))]
+-  "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
++  "TARGET_THUMB2 && TARGET_HARD_FLOAT
+    && (   s_register_operand (operands[0], SImode)
+        || s_register_operand (operands[1], SImode))"
+   "*
+@@ -112,7 +306,7 @@
+ (define_insn "*movdi_vfp"
+   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,r,w,w, Uv")
+        (match_operand:DI 1 "di_operand"              "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8
++  "TARGET_32BIT && TARGET_HARD_FLOAT && arm_tune != cortexa8
+    && (   register_operand (operands[0], DImode)
+        || register_operand (operands[1], DImode))
+    && !(TARGET_NEON && CONST_INT_P (operands[1])
+@@ -163,7 +357,7 @@
+ (define_insn "*movdi_vfp_cortexa8"
+   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv")
+        (match_operand:DI 1 "di_operand"              "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8
++  "TARGET_32BIT && TARGET_HARD_FLOAT && arm_tune == cortexa8
+     && (   register_operand (operands[0], DImode)
+         || register_operand (operands[1], DImode))
+     && !(TARGET_NEON && CONST_INT_P (operands[1])
+@@ -211,10 +405,87 @@
+  )
+ 
+ ;; HFmode moves
++
++(define_insn "*movhf_vfp_fp16"
++  [(set (match_operand:HF 0 "nonimmediate_operand"
++			  "= r,m,t,r,t,r,t,t,Um,r")
++	(match_operand:HF 1 "general_operand"
++			  "  m,r,t,r,r,t,Dv,Um,t,F"))]
++  "TARGET_32BIT
++   && TARGET_VFP_FP16INST
++   && (s_register_operand (operands[0], HFmode)
++       || s_register_operand (operands[1], HFmode))"
++ {
++  switch (which_alternative)
++    {
++    case 0: /* ARM register from memory.  */
++      return \"ldrh%?\\t%0, %1\\t%@ __fp16\";
++    case 1: /* Memory from ARM register.  */
++      return \"strh%?\\t%1, %0\\t%@ __fp16\";
++    case 2: /* S register from S register.  */
++      return \"vmov\\t%0, %1\t%@ __fp16\";
++    case 3: /* ARM register from ARM register.  */
++      return \"mov%?\\t%0, %1\\t%@ __fp16\";
++    case 4: /* S register from ARM register.  */
++    case 5: /* ARM register from S register.  */
++    case 6: /* S register from immediate.  */
++      return \"vmov.f16\\t%0, %1\t%@ __fp16\";
++    case 7: /* S register from memory.  */
++      return \"vld1.16\\t{%z0}, %A1\";
++    case 8: /* Memory from S register.  */
++      return \"vst1.16\\t{%z1}, %A0\";
++    case 9: /* ARM register from constant.  */
++      {
++	long bits;
++	rtx ops[4];
++
++	bits = real_to_target (NULL, CONST_DOUBLE_REAL_VALUE (operands[1]),
++			       HFmode);
++	ops[0] = operands[0];
++	ops[1] = GEN_INT (bits);
++	ops[2] = GEN_INT (bits & 0xff00);
++	ops[3] = GEN_INT (bits & 0x00ff);
++
++	if (arm_arch_thumb2)
++	  output_asm_insn (\"movw\\t%0, %1\", ops);
++	else
++	  output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
++	return \"\";
++       }
++    default:
++      gcc_unreachable ();
++    }
++ }
++  [(set_attr "predicable" "yes, yes, no, yes, no, no, no, no, no, no")
++   (set_attr "predicable_short_it" "no, no, no, yes,\
++				    no, no, no, no,\
++				    no, no")
++   (set_attr_alternative "type"
++    [(const_string "load1") (const_string "store1")
++     (const_string "fmov") (const_string "mov_reg")
++     (const_string "f_mcr") (const_string "f_mrc")
++     (const_string "fconsts") (const_string "neon_load1_1reg")
++     (const_string "neon_store1_1reg")
++     (if_then_else (match_test "arm_arch_thumb2")
++      (const_string "mov_imm")
++      (const_string "multiple"))])
++   (set_attr_alternative "length"
++    [(const_int 4) (const_int 4)
++     (const_int 4) (const_int 4)
++     (const_int 4) (const_int 4)
++     (const_int 4) (const_int 4)
++     (const_int 4)
++     (if_then_else (match_test "arm_arch_thumb2")
++      (const_int 4)
++      (const_int 8))])]
++)
++
+ (define_insn "*movhf_vfp_neon"
+   [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
+ 	(match_operand:HF 1 "general_operand"	   " Um, t,m,r,t,r,r,t,F"))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
++  "TARGET_32BIT
++   && TARGET_HARD_FLOAT && TARGET_NEON_FP16
++   && !TARGET_VFP_FP16INST
+    && (   s_register_operand (operands[0], HFmode)
+        || s_register_operand (operands[1], HFmode))"
+   "*
+@@ -268,7 +539,10 @@
+ (define_insn "*movhf_vfp"
+   [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
+ 	(match_operand:HF 1 "general_operand"	   " m,r,t,r,r,t,F"))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16
++  "TARGET_32BIT
++   && TARGET_HARD_FLOAT
++   && !TARGET_NEON_FP16
++   && !TARGET_VFP_FP16INST
+    && (   s_register_operand (operands[0], HFmode)
+        || s_register_operand (operands[1], HFmode))"
+   "*
+@@ -321,7 +595,7 @@
+ (define_insn "*movsf_vfp"
+   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t  ,Uv,r ,m,t,r")
+         (match_operand:SF 1 "general_operand"	   " ?r,t,Dv,UvE,t, mE,r,t,r"))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
++  "TARGET_ARM && TARGET_HARD_FLOAT
+    && (   s_register_operand (operands[0], SFmode)
+        || s_register_operand (operands[1], SFmode))"
+   "*
+@@ -357,7 +631,7 @@
+ (define_insn "*thumb2_movsf_vfp"
+   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t  ,Uv,r ,m,t,r")
+ 	(match_operand:SF 1 "general_operand"	   " ?r,t,Dv,UvE,t, mE,r,t,r"))]
+-  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
++  "TARGET_THUMB2 && TARGET_HARD_FLOAT
+    && (   s_register_operand (operands[0], SFmode)
+        || s_register_operand (operands[1], SFmode))"
+   "*
+@@ -394,9 +668,9 @@
+ ;; DFmode moves
+ 
+ (define_insn "*movdf_vfp"
+-  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r, m,w,r")
+-	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,UvF,w ,mF,r,w,r"))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
++  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,w  ,Uv,r, m,w,r")
++	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,G,UvF,w ,mF,r,w,r"))]
++  "TARGET_ARM && TARGET_HARD_FLOAT
+    && (   register_operand (operands[0], DFmode)
+        || register_operand (operands[1], DFmode))"
+   "*
+@@ -410,40 +684,44 @@
+       case 2:
+ 	gcc_assert (TARGET_VFP_DOUBLE);
+         return \"vmov%?.f64\\t%P0, %1\";
+-      case 3: case 4:
++      case 3:
++	gcc_assert (TARGET_VFP_DOUBLE);
++	return \"vmov.i64\\t%P0, #0\\t%@ float\";
++      case 4: case 5:
+ 	return output_move_vfp (operands);
+-      case 5: case 6:
++      case 6: case 7:
+ 	return output_move_double (operands, true, NULL);
+-      case 7:
++      case 8:
+ 	if (TARGET_VFP_SINGLE)
+ 	  return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\";
+ 	else
+ 	  return \"vmov%?.f64\\t%P0, %P1\";
+-      case 8:
++      case 9:
+         return \"#\";
+       default:
+ 	gcc_unreachable ();
+       }
+     }
+   "
+-  [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_stored,\
++  [(set_attr "type" "f_mcrr,f_mrrc,fconstd,neon_move,f_loadd,f_stored,\
+                      load2,store2,ffarithd,multiple")
+-   (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
+-			       (eq_attr "alternative" "7")
++   (set (attr "length") (cond [(eq_attr "alternative" "6,7,9") (const_int 8)
++			       (eq_attr "alternative" "8")
+ 				(if_then_else
+ 				 (match_test "TARGET_VFP_SINGLE")
+ 				 (const_int 8)
+ 				 (const_int 4))]
+ 			      (const_int 4)))
+-   (set_attr "predicable" "yes")
+-   (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
+-   (set_attr "neg_pool_range" "*,*,*,1004,*,1004,*,*,*")]
++   (set_attr "predicable" "yes,yes,yes,no,yes,yes,yes,yes,yes,yes")
++   (set_attr "pool_range" "*,*,*,*,1020,*,1020,*,*,*")
++   (set_attr "neg_pool_range" "*,*,*,*,1004,*,1004,*,*,*")
++   (set_attr "arch" "any,any,any,neon,any,any,any,any,any,any")]
+ )
+ 
+ (define_insn "*thumb2_movdf_vfp"
+-  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r ,m,w,r")
+-	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,UvF,w, mF,r, w,r"))]
+-  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
++  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,w  ,Uv,r ,m,w,r")
++	(match_operand:DF 1 "soft_df_operand"		   " ?r,w,Dy,G,UvF,w, mF,r, w,r"))]
++  "TARGET_THUMB2 && TARGET_HARD_FLOAT
+    && (   register_operand (operands[0], DFmode)
+        || register_operand (operands[1], DFmode))"
+   "*
+@@ -457,11 +735,14 @@
+       case 2:
+ 	gcc_assert (TARGET_VFP_DOUBLE);
+ 	return \"vmov%?.f64\\t%P0, %1\";
+-      case 3: case 4:
++      case 3:
++	gcc_assert (TARGET_VFP_DOUBLE);
++	return \"vmov.i64\\t%P0, #0\\t%@ float\";
++      case 4: case 5:
+ 	return output_move_vfp (operands);
+-      case 5: case 6: case 8:
++      case 6: case 7: case 9:
+ 	return output_move_double (operands, true, NULL);
+-      case 7:
++      case 8:
+ 	if (TARGET_VFP_SINGLE)
+ 	  return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\";
+ 	else
+@@ -471,17 +752,18 @@
+       }
+     }
+   "
+-  [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,\
++  [(set_attr "type" "f_mcrr,f_mrrc,fconstd,neon_move,f_loadd,\
+                      f_stored,load2,store2,ffarithd,multiple")
+-   (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
+-			       (eq_attr "alternative" "7")
++   (set (attr "length") (cond [(eq_attr "alternative" "6,7,9") (const_int 8)
++			       (eq_attr "alternative" "8")
+ 				(if_then_else
+ 				 (match_test "TARGET_VFP_SINGLE")
+ 				 (const_int 8)
+ 				 (const_int 4))]
+ 			      (const_int 4)))
+-   (set_attr "pool_range" "*,*,*,1018,*,4094,*,*,*")
+-   (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
++   (set_attr "pool_range" "*,*,*,*,1018,*,4094,*,*,*")
++   (set_attr "neg_pool_range" "*,*,*,*,1008,*,0,*,*,*")
++   (set_attr "arch" "any,any,any,neon,any,any,any,any,any,any")]
+ )
+ 
+ 
+@@ -494,7 +776,7 @@
+ 	    [(match_operand 4 "cc_register" "") (const_int 0)])
+ 	  (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
+ 	  (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
+-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_ARM && TARGET_HARD_FLOAT"
+   "@
+    vmov%D3.f32\\t%0, %2
+    vmov%d3.f32\\t%0, %1
+@@ -517,7 +799,7 @@
+ 	    [(match_operand 4 "cc_register" "") (const_int 0)])
+ 	  (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
+ 	  (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
+-  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP && !arm_restrict_it"
++  "TARGET_THUMB2 && TARGET_HARD_FLOAT && !arm_restrict_it"
+   "@
+    it\\t%D3\;vmov%D3.f32\\t%0, %2
+    it\\t%d3\;vmov%d3.f32\\t%0, %1
+@@ -585,7 +867,7 @@
+ (define_insn "*abssf2_vfp"
+   [(set (match_operand:SF	  0 "s_register_operand" "=t")
+ 	(abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vabs%?.f32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -605,7 +887,7 @@
+ (define_insn "*negsf2_vfp"
+   [(set (match_operand:SF	  0 "s_register_operand" "=t,?r")
+ 	(neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "@
+    vneg%?.f32\\t%0, %1
+    eor%?\\t%0, %1, #-2147483648"
+@@ -661,14 +943,68 @@
+    (set_attr "type" "ffarithd")]
+ )
+ 
++;; ABS and NEG for FP16.
++(define_insn "<absneg_str>hf2"
++  [(set (match_operand:HF 0 "s_register_operand" "=w")
++    (ABSNEG:HF (match_operand:HF 1 "s_register_operand" "w")))]
++ "TARGET_VFP_FP16INST"
++ "v<absneg_str>.f16\t%0, %1"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "ffariths")]
++)
++
++(define_expand "neon_vabshf"
++ [(set
++   (match_operand:HF 0 "s_register_operand")
++   (abs:HF (match_operand:HF 1 "s_register_operand")))]
++ "TARGET_VFP_FP16INST"
++{
++  emit_insn (gen_abshf2 (operands[0], operands[1]));
++  DONE;
++})
++
++;; VRND for FP16.
++(define_insn "neon_v<fp16_rnd_str>hf"
++  [(set (match_operand:HF 0 "s_register_operand" "=w")
++    (unspec:HF
++     [(match_operand:HF 1 "s_register_operand" "w")]
++     FP16_RND))]
++ "TARGET_VFP_FP16INST"
++ "<fp16_rnd_insn>.f16\t%0, %1"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "neon_fp_round_s")]
++)
++
++(define_insn "neon_vrndihf"
++  [(set (match_operand:HF 0 "s_register_operand" "=w")
++    (unspec:HF
++     [(match_operand:HF 1 "s_register_operand" "w")]
++     UNSPEC_VRNDI))]
++  "TARGET_VFP_FP16INST"
++  "vrintr.f16\t%0, %1"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "neon_fp_round_s")]
++)
+ 
+ ;; Arithmetic insns
+ 
++(define_insn "addhf3"
++  [(set
++    (match_operand:HF 0 "s_register_operand" "=w")
++    (plus:HF
++     (match_operand:HF 1 "s_register_operand" "w")
++     (match_operand:HF 2 "s_register_operand" "w")))]
++ "TARGET_VFP_FP16INST"
++ "vadd.f16\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fadds")]
++)
++
+ (define_insn "*addsf3_vfp"
+   [(set (match_operand:SF	   0 "s_register_operand" "=t")
+ 	(plus:SF (match_operand:SF 1 "s_register_operand" "t")
+ 		 (match_operand:SF 2 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vadd%?.f32\\t%0, %1, %2"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -686,12 +1022,23 @@
+    (set_attr "type" "faddd")]
+ )
+ 
++(define_insn "subhf3"
++ [(set
++   (match_operand:HF 0 "s_register_operand" "=w")
++   (minus:HF
++    (match_operand:HF 1 "s_register_operand" "w")
++    (match_operand:HF 2 "s_register_operand" "w")))]
++ "TARGET_VFP_FP16INST"
++ "vsub.f16\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fadds")]
++)
+ 
+ (define_insn "*subsf3_vfp"
+   [(set (match_operand:SF	    0 "s_register_operand" "=t")
+ 	(minus:SF (match_operand:SF 1 "s_register_operand" "t")
+ 		  (match_operand:SF 2 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vsub%?.f32\\t%0, %1, %2"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -712,6 +1059,19 @@
+ 
+ ;; Division insns
+ 
++;; FP16 Division.
++(define_insn "divhf3"
++  [(set
++    (match_operand:HF	   0 "s_register_operand" "=w")
++    (div:HF
++     (match_operand:HF 1 "s_register_operand" "w")
++     (match_operand:HF 2 "s_register_operand" "w")))]
++  "TARGET_VFP_FP16INST"
++  "vdiv.f16\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fdivs")]
++)
++
+ ; VFP9 Erratum 760019: It's potentially unsafe to overwrite the input
+ ; operands, so mark the output as early clobber for VFPv2 on ARMv5 or
+ ; earlier.
+@@ -719,7 +1079,7 @@
+   [(set (match_operand:SF	  0 "s_register_operand" "=&t,t")
+ 	(div:SF (match_operand:SF 1 "s_register_operand" "t,t")
+ 		(match_operand:SF 2 "s_register_operand" "t,t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vdiv%?.f32\\t%0, %1, %2"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -742,11 +1102,22 @@
+ 
+ ;; Multiplication insns
+ 
++(define_insn "mulhf3"
++ [(set
++   (match_operand:HF 0 "s_register_operand" "=w")
++   (mult:HF (match_operand:HF 1 "s_register_operand" "w")
++	    (match_operand:HF 2 "s_register_operand" "w")))]
++  "TARGET_VFP_FP16INST"
++  "vmul.f16\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmuls")]
++)
++
+ (define_insn "*mulsf3_vfp"
+   [(set (match_operand:SF	   0 "s_register_operand" "=t")
+ 	(mult:SF (match_operand:SF 1 "s_register_operand" "t")
+ 		 (match_operand:SF 2 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vmul%?.f32\\t%0, %1, %2"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -764,11 +1135,31 @@
+    (set_attr "type" "fmuld")]
+ )
+ 
++(define_insn "*mulsf3neghf_vfp"
++  [(set (match_operand:HF		   0 "s_register_operand" "=t")
++	(mult:HF (neg:HF (match_operand:HF 1 "s_register_operand" "t"))
++		 (match_operand:HF	   2 "s_register_operand" "t")))]
++  "TARGET_VFP_FP16INST && !flag_rounding_math"
++  "vnmul.f16\\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmuls")]
++)
++
++(define_insn "*negmulhf3_vfp"
++  [(set (match_operand:HF		   0 "s_register_operand" "=t")
++	(neg:HF (mult:HF (match_operand:HF 1 "s_register_operand" "t")
++		 (match_operand:HF	   2 "s_register_operand" "t"))))]
++  "TARGET_VFP_FP16INST"
++  "vnmul.f16\\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmuls")]
++)
++
+ (define_insn "*mulsf3negsf_vfp"
+   [(set (match_operand:SF		   0 "s_register_operand" "=t")
+ 	(mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
+ 		 (match_operand:SF	   2 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && !flag_rounding_math"
++  "TARGET_32BIT && TARGET_HARD_FLOAT && !flag_rounding_math"
+   "vnmul%?.f32\\t%0, %1, %2"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -779,7 +1170,7 @@
+   [(set (match_operand:SF		   0 "s_register_operand" "=t")
+ 	(neg:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
+ 		 (match_operand:SF	   2 "s_register_operand" "t"))))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vnmul%?.f32\\t%0, %1, %2"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -813,12 +1204,24 @@
+ ;; Multiply-accumulate insns
+ 
+ ;; 0 = 1 * 2 + 0
++(define_insn "*mulsf3addhf_vfp"
++ [(set (match_operand:HF 0 "s_register_operand" "=t")
++       (plus:HF
++	(mult:HF (match_operand:HF 2 "s_register_operand" "t")
++		 (match_operand:HF 3 "s_register_operand" "t"))
++	(match_operand:HF 1 "s_register_operand" "0")))]
++  "TARGET_VFP_FP16INST"
++  "vmla.f16\\t%0, %2, %3"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmacs")]
++)
++
+ (define_insn "*mulsf3addsf_vfp"
+   [(set (match_operand:SF		    0 "s_register_operand" "=t")
+ 	(plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
+ 			  (match_operand:SF 3 "s_register_operand" "t"))
+ 		 (match_operand:SF	    1 "s_register_operand" "0")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vmla%?.f32\\t%0, %2, %3"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -838,12 +1241,23 @@
+ )
+ 
+ ;; 0 = 1 * 2 - 0
++(define_insn "*mulhf3subhf_vfp"
++  [(set (match_operand:HF 0 "s_register_operand" "=t")
++	(minus:HF (mult:HF (match_operand:HF 2 "s_register_operand" "t")
++			   (match_operand:HF 3 "s_register_operand" "t"))
++		  (match_operand:HF 1 "s_register_operand" "0")))]
++  "TARGET_VFP_FP16INST"
++  "vnmls.f16\\t%0, %2, %3"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmacs")]
++)
++
+ (define_insn "*mulsf3subsf_vfp"
+   [(set (match_operand:SF		     0 "s_register_operand" "=t")
+ 	(minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
+ 			   (match_operand:SF 3 "s_register_operand" "t"))
+ 		  (match_operand:SF	     1 "s_register_operand" "0")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vnmls%?.f32\\t%0, %2, %3"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -863,12 +1277,23 @@
+ )
+ 
+ ;; 0 = -(1 * 2) + 0
++(define_insn "*mulhf3neghfaddhf_vfp"
++  [(set (match_operand:HF 0 "s_register_operand" "=t")
++	(minus:HF (match_operand:HF 1 "s_register_operand" "0")
++		  (mult:HF (match_operand:HF 2 "s_register_operand" "t")
++			   (match_operand:HF 3 "s_register_operand" "t"))))]
++  "TARGET_VFP_FP16INST"
++  "vmls.f16\\t%0, %2, %3"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmacs")]
++)
++
+ (define_insn "*mulsf3negsfaddsf_vfp"
+   [(set (match_operand:SF		     0 "s_register_operand" "=t")
+ 	(minus:SF (match_operand:SF	     1 "s_register_operand" "0")
+ 		  (mult:SF (match_operand:SF 2 "s_register_operand" "t")
+ 			   (match_operand:SF 3 "s_register_operand" "t"))))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vmls%?.f32\\t%0, %2, %3"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -889,13 +1314,25 @@
+ 
+ 
+ ;; 0 = -(1 * 2) - 0
++(define_insn "*mulhf3neghfsubhf_vfp"
++  [(set (match_operand:HF 0 "s_register_operand" "=t")
++	(minus:HF (mult:HF
++		   (neg:HF (match_operand:HF 2 "s_register_operand" "t"))
++		   (match_operand:HF 3 "s_register_operand" "t"))
++		  (match_operand:HF 1 "s_register_operand" "0")))]
++  "TARGET_VFP_FP16INST"
++  "vnmla.f16\\t%0, %2, %3"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fmacs")]
++)
++
+ (define_insn "*mulsf3negsfsubsf_vfp"
+   [(set (match_operand:SF		      0 "s_register_operand" "=t")
+ 	(minus:SF (mult:SF
+ 		    (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
+ 		    (match_operand:SF	      3 "s_register_operand" "t"))
+ 		  (match_operand:SF	      1 "s_register_operand" "0")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vnmla%?.f32\\t%0, %2, %3"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -917,6 +1354,30 @@
+ 
+ ;; Fused-multiply-accumulate
+ 
++(define_insn "fmahf4"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++    (fma:HF
++     (match_operand:HF 1 "register_operand" "w")
++     (match_operand:HF 2 "register_operand" "w")
++     (match_operand:HF 3 "register_operand" "0")))]
++ "TARGET_VFP_FP16INST"
++ "vfma.f16\\t%0, %1, %2"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "ffmas")]
++)
++
++(define_expand "neon_vfmahf"
++  [(match_operand:HF 0 "s_register_operand")
++   (match_operand:HF 1 "s_register_operand")
++   (match_operand:HF 2 "s_register_operand")
++   (match_operand:HF 3 "s_register_operand")]
++  "TARGET_VFP_FP16INST"
++{
++  emit_insn (gen_fmahf4 (operands[0], operands[2], operands[3],
++			 operands[1]));
++  DONE;
++})
++
+ (define_insn "fma<SDF:mode>4"
+   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+         (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
+@@ -929,6 +1390,30 @@
+    (set_attr "type" "ffma<vfp_type>")]
+ )
+ 
++(define_insn "fmsubhf4_fp16"
++ [(set (match_operand:HF 0 "register_operand" "=w")
++   (fma:HF
++    (neg:HF (match_operand:HF 1 "register_operand" "w"))
++    (match_operand:HF 2 "register_operand" "w")
++    (match_operand:HF 3 "register_operand" "0")))]
++ "TARGET_VFP_FP16INST"
++ "vfms.f16\\t%0, %1, %2"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "ffmas")]
++)
++
++(define_expand "neon_vfmshf"
++  [(match_operand:HF 0 "s_register_operand")
++   (match_operand:HF 1 "s_register_operand")
++   (match_operand:HF 2 "s_register_operand")
++   (match_operand:HF 3 "s_register_operand")]
++  "TARGET_VFP_FP16INST"
++{
++  emit_insn (gen_fmsubhf4_fp16 (operands[0], operands[2], operands[3],
++				operands[1]));
++  DONE;
++})
++
+ (define_insn "*fmsub<SDF:mode>4"
+   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+ 	(fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
+@@ -942,6 +1427,17 @@
+    (set_attr "type" "ffma<vfp_type>")]
+ )
+ 
++(define_insn "*fnmsubhf4"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++	(fma:HF (match_operand:HF 1 "register_operand" "w")
++		 (match_operand:HF 2 "register_operand" "w")
++		 (neg:HF (match_operand:HF 3 "register_operand" "0"))))]
++  "TARGET_VFP_FP16INST"
++  "vfnms.f16\\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "ffmas")]
++)
++
+ (define_insn "*fnmsub<SDF:mode>4"
+   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+ 	(fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
+@@ -954,6 +1450,17 @@
+    (set_attr "type" "ffma<vfp_type>")]
+ )
+ 
++(define_insn "*fnmaddhf4"
++  [(set (match_operand:HF 0 "register_operand" "=w")
++	(fma:HF (neg:HF (match_operand:HF 1 "register_operand" "w"))
++		 (match_operand:HF 2 "register_operand" "w")
++		 (neg:HF (match_operand:HF 3 "register_operand" "0"))))]
++  "TARGET_VFP_FP16INST"
++  "vfnma.f16\\t%0, %1, %2"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "ffmas")]
++)
++
+ (define_insn "*fnmadd<SDF:mode>4"
+   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+ 	(fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
+@@ -993,7 +1500,7 @@
+ (define_insn "extendhfsf2"
+   [(set (match_operand:SF		   0 "s_register_operand" "=t")
+ 	(float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
++  "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)"
+   "vcvtb%?.f32.f16\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1003,7 +1510,7 @@
+ (define_insn "truncsfhf2"
+   [(set (match_operand:HF		   0 "s_register_operand" "=t")
+ 	(float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
++  "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)"
+   "vcvtb%?.f16.f32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1013,7 +1520,7 @@
+ (define_insn "*truncsisf2_vfp"
+   [(set (match_operand:SI		  0 "s_register_operand" "=t")
+ 	(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vcvt%?.s32.f32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1034,7 +1541,7 @@
+ (define_insn "fixuns_truncsfsi2"
+   [(set (match_operand:SI		  0 "s_register_operand" "=t")
+ 	(unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vcvt%?.u32.f32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1055,7 +1562,7 @@
+ (define_insn "*floatsisf2_vfp"
+   [(set (match_operand:SF	    0 "s_register_operand" "=t")
+ 	(float:SF (match_operand:SI 1 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vcvt%?.f32.s32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1076,7 +1583,7 @@
+ (define_insn "floatunssisf2"
+   [(set (match_operand:SF	    0 "s_register_operand" "=t")
+ 	(unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vcvt%?.f32.u32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1096,13 +1603,34 @@
+ 
+ ;; Sqrt insns.
+ 
++(define_insn "neon_vsqrthf"
++  [(set (match_operand:HF 0 "s_register_operand" "=w")
++	(sqrt:HF (match_operand:HF 1 "s_register_operand" "w")))]
++  "TARGET_VFP_FP16INST"
++  "vsqrt.f16\t%0, %1"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "fsqrts")]
++)
++
++(define_insn "neon_vrsqrtshf"
++  [(set
++    (match_operand:HF 0 "s_register_operand" "=w")
++    (unspec:HF [(match_operand:HF 1 "s_register_operand" "w")
++		(match_operand:HF 2 "s_register_operand" "w")]
++     UNSPEC_VRSQRTS))]
++ "TARGET_VFP_FP16INST"
++ "vrsqrts.f16\t%0, %1, %2"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "fsqrts")]
++)
++
+ ; VFP9 Erratum 760019: It's potentially unsafe to overwrite the input
+ ; operands, so mark the output as early clobber for VFPv2 on ARMv5 or
+ ; earlier.
+ (define_insn "*sqrtsf2_vfp"
+   [(set (match_operand:SF	   0 "s_register_operand" "=&t,t")
+ 	(sqrt:SF (match_operand:SF 1 "s_register_operand" "t,t")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vsqrt%?.f32\\t%0, %1"
+   [(set_attr "predicable" "yes")
+    (set_attr "predicable_short_it" "no")
+@@ -1127,7 +1655,7 @@
+ (define_insn "*movcc_vfp"
+   [(set (reg CC_REGNUM)
+ 	(reg VFPCC_REGNUM))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "vmrs%?\\tAPSR_nzcv, FPSCR"
+   [(set_attr "conds" "set")
+    (set_attr "type" "f_flag")]
+@@ -1137,9 +1665,9 @@
+   [(set (reg:CCFP CC_REGNUM)
+ 	(compare:CCFP (match_operand:SF 0 "s_register_operand"  "t")
+ 		      (match_operand:SF 1 "vfp_compare_operand" "tG")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "#"
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   [(set (reg:CCFP VFPCC_REGNUM)
+ 	(compare:CCFP (match_dup 0)
+ 		      (match_dup 1)))
+@@ -1152,9 +1680,9 @@
+   [(set (reg:CCFPE CC_REGNUM)
+ 	(compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t")
+ 		       (match_operand:SF 1 "vfp_compare_operand" "tG")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "#"
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   [(set (reg:CCFPE VFPCC_REGNUM)
+ 	(compare:CCFPE (match_dup 0)
+ 		       (match_dup 1)))
+@@ -1203,7 +1731,7 @@
+   [(set (reg:CCFP VFPCC_REGNUM)
+ 	(compare:CCFP (match_operand:SF 0 "s_register_operand"  "t,t")
+ 		      (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "@
+    vcmp%?.f32\\t%0, %1
+    vcmp%?.f32\\t%0, #0"
+@@ -1216,7 +1744,7 @@
+   [(set (reg:CCFPE VFPCC_REGNUM)
+ 	(compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t,t")
+ 		       (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "@
+    vcmpe%?.f32\\t%0, %1
+    vcmpe%?.f32\\t%0, #0"
+@@ -1252,9 +1780,6 @@
+ )
+ 
+ ;; Fixed point to floating point conversions.
+-(define_code_iterator FCVT [unsigned_float float])
+-(define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
+-
+ (define_insn "*combine_vcvt_f32_<FCVTI32typename>"
+   [(set (match_operand:SF 0 "s_register_operand" "=t")
+ 	(mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0"))
+@@ -1299,13 +1824,132 @@
+    (set_attr "type" "f_cvtf2i")]
+  )
+ 
++;; FP16 conversions.
++(define_insn "neon_vcvth<sup>hf"
++ [(set (match_operand:HF 0 "s_register_operand" "=w")
++   (unspec:HF
++    [(match_operand:SI 1 "s_register_operand" "w")]
++    VCVTH_US))]
++ "TARGET_VFP_FP16INST"
++ "vcvt.f16.<sup>%#32\t%0, %1"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "f_cvti2f")]
++)
++
++(define_insn "neon_vcvth<sup>si"
++ [(set (match_operand:SI 0 "s_register_operand" "=w")
++   (unspec:SI
++    [(match_operand:HF 1 "s_register_operand" "w")]
++    VCVTH_US))]
++ "TARGET_VFP_FP16INST"
++ "vcvt.<sup>%#32.f16\t%0, %1"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "f_cvtf2i")]
++)
++
++;; The neon_vcvth<sup>_nhf patterns are used to generate the instruction for the
++;; vcvth_n_f16_<sup>32 arm_fp16 intrinsics.  They are complicated by the
++;; hardware requirement that the source and destination registers are the same
++;; despite having different machine modes.  The approach is to use a temporary
++;; register for the conversion and move that to the correct destination.
++
++;; Generate an unspec pattern for the intrinsic.
++(define_insn "neon_vcvth<sup>_nhf_unspec"
++ [(set
++   (match_operand:SI 0 "s_register_operand" "=w")
++   (unspec:SI
++    [(match_operand:SI 1 "s_register_operand" "0")
++     (match_operand:SI 2 "immediate_operand" "i")]
++    VCVT_HF_US_N))
++ (set
++  (match_operand:HF 3 "s_register_operand" "=w")
++  (float_truncate:HF (float:SF (match_dup 0))))]
++ "TARGET_VFP_FP16INST"
++{
++  neon_const_bounds (operands[2], 1, 33);
++  return "vcvt.f16.<sup>32\t%0, %0, %2\;vmov.f32\t%3, %0";
++}
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "f_cvti2f")]
++)
++
++;; Generate the instruction patterns needed for vcvth_n_f16_s32 neon intrinsics.
++(define_expand "neon_vcvth<sup>_nhf"
++ [(match_operand:HF 0 "s_register_operand")
++  (unspec:HF [(match_operand:SI 1 "s_register_operand")
++	      (match_operand:SI 2 "immediate_operand")]
++   VCVT_HF_US_N)]
++"TARGET_VFP_FP16INST"
++{
++  rtx op1 = gen_reg_rtx (SImode);
++
++  neon_const_bounds (operands[2], 1, 33);
++
++  emit_move_insn (op1, operands[1]);
++  emit_insn (gen_neon_vcvth<sup>_nhf_unspec (op1, op1, operands[2],
++					     operands[0]));
++  DONE;
++})
++
++;; The neon_vcvth<sup>_nsi patterns are used to generate the instruction for the
++;; vcvth_n_<sup>32_f16 arm_fp16 intrinsics.  They have the same restrictions and
++;; are implemented in the same way as the neon_vcvth<sup>_nhf patterns.
++
++;; Generate an unspec pattern, constraining the registers.
++(define_insn "neon_vcvth<sup>_nsi_unspec"
++ [(set (match_operand:SI 0 "s_register_operand" "=w")
++   (unspec:SI
++    [(fix:SI
++      (fix:SF
++       (float_extend:SF
++	(match_operand:HF 1 "s_register_operand" "w"))))
++     (match_operand:SI 2 "immediate_operand" "i")]
++    VCVT_SI_US_N))]
++ "TARGET_VFP_FP16INST"
++{
++  neon_const_bounds (operands[2], 1, 33);
++  return "vmov.f32\t%0, %1\;vcvt.<sup>%#32.f16\t%0, %0, %2";
++}
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "f_cvtf2i")]
++)
++
++;; Generate the instruction patterns needed for vcvth_n_f16_s32 neon intrinsics.
++(define_expand "neon_vcvth<sup>_nsi"
++ [(match_operand:SI 0 "s_register_operand")
++  (unspec:SI
++   [(match_operand:HF 1 "s_register_operand")
++    (match_operand:SI 2 "immediate_operand")]
++   VCVT_SI_US_N)]
++ "TARGET_VFP_FP16INST"
++{
++  rtx op1 = gen_reg_rtx (SImode);
++
++  neon_const_bounds (operands[2], 1, 33);
++  emit_insn (gen_neon_vcvth<sup>_nsi_unspec (op1, operands[1], operands[2]));
++  emit_move_insn (operands[0], op1);
++  DONE;
++})
++
++(define_insn "neon_vcvt<vcvth_op>h<sup>si"
++ [(set
++   (match_operand:SI 0 "s_register_operand" "=w")
++   (unspec:SI
++    [(match_operand:HF 1 "s_register_operand" "w")]
++    VCVT_HF_US))]
++ "TARGET_VFP_FP16INST"
++ "vcvt<vcvth_op>.<sup>%#32.f16\t%0, %1"
++  [(set_attr "conds" "unconditional")
++   (set_attr "type" "f_cvtf2i")]
++)
++
+ ;; Store multiple insn used in function prologue.
+ (define_insn "*push_multi_vfp"
+   [(match_parallel 2 "multi_register_push"
+     [(set (match_operand:BLK 0 "memory_operand" "=m")
+ 	  (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")]
+ 		      UNSPEC_PUSH_MULT))])]
+-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
++  "TARGET_32BIT && TARGET_HARD_FLOAT"
+   "* return vfp_output_vstmd (operands);"
+   [(set_attr "type" "f_stored")]
+ )
+@@ -1368,6 +2012,20 @@
+ )
+ 
+ ;; Scalar forms for the IEEE-754 fmax()/fmin() functions
++
++(define_insn "neon_<fmaxmin_op>hf"
++ [(set
++   (match_operand:HF 0 "s_register_operand" "=w")
++   (unspec:HF
++    [(match_operand:HF 1 "s_register_operand" "w")
++     (match_operand:HF 2 "s_register_operand" "w")]
++    VMAXMINFNM))]
++ "TARGET_VFP_FP16INST"
++ "<fmaxmin_op>.f16\t%0, %1, %2"
++ [(set_attr "conds" "unconditional")
++  (set_attr "type" "f_minmaxs")]
++)
++
+ (define_insn "<fmaxmin><mode>3"
+   [(set (match_operand:SDF 0 "s_register_operand" "=<F_constraint>")
+ 	(unspec:SDF [(match_operand:SDF 1 "s_register_operand" "<F_constraint>")
+@@ -1382,7 +2040,7 @@
+ ;; Write Floating-point Status and Control Register.
+ (define_insn "set_fpscr"
+   [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR)]
+-  "TARGET_VFP && TARGET_HARD_FLOAT"
++  "TARGET_HARD_FLOAT"
+   "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR"
+   [(set_attr "type" "mrs")])
+ 
+@@ -1390,7 +2048,7 @@
+ (define_insn "get_fpscr"
+   [(set (match_operand:SI 0 "register_operand" "=r")
+         (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))]
+-  "TARGET_VFP && TARGET_HARD_FLOAT"
++  "TARGET_HARD_FLOAT"
+   "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR"
+   [(set_attr "type" "mrs")])
+ 
+@@ -1401,3 +2059,40 @@
+ ;; fmdhr et al (VFPv1)
+ ;; Support for xD (single precision only) variants.
+ ;; fmrrs, fmsrr
++
++;; Split an immediate DF move to two immediate SI moves.
++(define_insn_and_split "no_literal_pool_df_immediate"
++  [(set (match_operand:DF 0 "s_register_operand" "")
++	(match_operand:DF 1 "const_double_operand" ""))]
++  "TARGET_THUMB2 && arm_disable_literal_pool
++  && !(TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE
++       && vfp3_const_double_rtx (operands[1]))"
++  "#"
++  "&& !reload_completed"
++  [(set (subreg:SI (match_dup 1) 0) (match_dup 2))
++   (set (subreg:SI (match_dup 1) 4) (match_dup 3))
++   (set (match_dup 0) (match_dup 1))]
++  "
++  long buf[2];
++  real_to_target (buf, CONST_DOUBLE_REAL_VALUE (operands[1]), DFmode);
++  operands[2] = GEN_INT ((int) buf[0]);
++  operands[3] = GEN_INT ((int) buf[1]);
++  operands[1] = gen_reg_rtx (DFmode);
++  ")
++
++;; Split an immediate SF move to one immediate SI move.
++(define_insn_and_split "no_literal_pool_sf_immediate"
++  [(set (match_operand:SF 0 "s_register_operand" "")
++	(match_operand:SF 1 "const_double_operand" ""))]
++  "TARGET_THUMB2 && arm_disable_literal_pool
++  && !(TARGET_HARD_FLOAT && vfp3_const_double_rtx (operands[1]))"
++  "#"
++  "&& !reload_completed"
++  [(set (subreg:SI (match_dup 1) 0) (match_dup 2))
++   (set (match_dup 0) (match_dup 1))]
++  "
++  long buf;
++  real_to_target (&buf, CONST_DOUBLE_REAL_VALUE (operands[1]), SFmode);
++  operands[2] = GEN_INT ((int) buf);
++  operands[1] = gen_reg_rtx (SFmode);
++  ")
+--- a/src/gcc/config/arm/xgene1.md
++++ b/src/gcc/config/arm/xgene1.md
+@@ -164,7 +164,7 @@
+ 
+ (define_insn_reservation "xgene1_bfm" 2
+   (and (eq_attr "tune" "xgene1")
+-       (eq_attr "type" "bfm"))
++       (eq_attr "type" "bfm,bfx"))
+   "xgene1_decode1op,xgene1_fsu")
+ 
+ (define_insn_reservation "xgene1_f_rint" 5
+--- a/src/gcc/config/i386/i386.c
++++ b/src/gcc/config/i386/i386.c
+@@ -23,6 +23,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "backend.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "cfghooks.h"
+ #include "cfgloop.h"
+--- a/src/gcc/config/ia64/ia64.c
++++ b/src/gcc/config/ia64/ia64.c
+@@ -26,6 +26,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "cfghooks.h"
+ #include "df.h"
+ #include "tm_p.h"
+--- a/src/gcc/config/linux.c
++++ b/src/gcc/config/linux.c
+@@ -26,7 +26,7 @@ along with GCC; see the file COPYING3.  If not see
+ bool
+ linux_libc_has_function (enum function_class fn_class)
+ {
+-  if (OPTION_GLIBC)
++  if (OPTION_GLIBC || OPTION_MUSL)
+     return true;
+   if (OPTION_BIONIC)
+     if (fn_class == function_c94
+--- a/src/gcc/config/mips/mips.c
++++ b/src/gcc/config/mips/mips.c
+@@ -28,6 +28,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "cfghooks.h"
+ #include "df.h"
+--- a/src/gcc/config/rs6000/rs6000.c
++++ b/src/gcc/config/rs6000/rs6000.c
+@@ -24,6 +24,7 @@
+ #include "backend.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "cfghooks.h"
+ #include "cfgloop.h"
+--- a/src/gcc/config/sparc/sparc.c
++++ b/src/gcc/config/sparc/sparc.c
+@@ -27,6 +27,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "df.h"
+ #include "tm_p.h"
+--- a/src/gcc/configure
++++ b/src/gcc/configure
+@@ -1711,7 +1711,8 @@ Optional Packages:
+   --with-stabs            arrange to use stabs instead of host debug format
+   --with-dwarf2           force the default debug format to be DWARF 2
+   --with-specs=SPECS      add SPECS to driver command-line processing
+-  --with-pkgversion=PKG   Use PKG in the version string in place of "GCC"
++  --with-pkgversion=PKG   Use PKG in the version string in place of "Linaro
++                          GCC `cat $srcdir/LINARO-VERSION`"
+   --with-bugurl=URL       Direct users to URL to report a bug
+   --with-multilib-list    select multilibs (AArch64, SH and x86-64 only)
+   --with-gnu-ld           assume the C compiler uses GNU ld default=no
+@@ -7658,7 +7659,7 @@ if test "${with_pkgversion+set}" = set; then :
+       *)   PKGVERSION="($withval) " ;;
+      esac
+ else
+-  PKGVERSION="(GCC) "
++  PKGVERSION="(Linaro GCC `cat $srcdir/LINARO-VERSION`) "
+ 
+ fi
+ 
+@@ -18460,7 +18461,7 @@ else
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 18463 "configure"
++#line 18464 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+@@ -18566,7 +18567,7 @@ else
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 18569 "configure"
++#line 18570 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -910,7 +910,7 @@ AC_ARG_WITH(specs,
+ )
+ AC_SUBST(CONFIGURE_SPECS)
+ 
+-ACX_PKGVERSION([GCC])
++ACX_PKGVERSION([Linaro GCC `cat $srcdir/LINARO-VERSION`])
+ ACX_BUGURL([http://gcc.gnu.org/bugs.html])
+ 
+ # Sanity check enable_languages in case someone does not run the toplevel
+--- a/src/gcc/cppbuiltin.c
++++ b/src/gcc/cppbuiltin.c
+@@ -52,18 +52,41 @@ parse_basever (int *major, int *minor, int *patchlevel)
+     *patchlevel = s_patchlevel;
+ }
+ 
++/* Parse a LINAROVER version string of the format "M.m-year.month[-spin][~dev]"
++   to create Linaro release number YYYYMM and spin version.  */
++static void
++parse_linarover (int *release, int *spin)
++{
++  static int s_year = -1, s_month, s_spin;
++
++  if (s_year == -1)
++    if (sscanf (LINAROVER, "%*[^-]-%d.%d-%d", &s_year, &s_month, &s_spin) != 3)
++      {
++	sscanf (LINAROVER, "%*[^-]-%d.%d", &s_year, &s_month);
++	s_spin = 0;
++      }
++
++  if (release)
++    *release = s_year * 100 + s_month;
++
++  if (spin)
++    *spin = s_spin;
++}
+ 
+ /* Define __GNUC__, __GNUC_MINOR__, __GNUC_PATCHLEVEL__ and __VERSION__.  */
+ static void
+ define__GNUC__ (cpp_reader *pfile)
+ {
+-  int major, minor, patchlevel;
++  int major, minor, patchlevel, linaro_release, linaro_spin;
+ 
+   parse_basever (&major, &minor, &patchlevel);
++  parse_linarover (&linaro_release, &linaro_spin);
+   cpp_define_formatted (pfile, "__GNUC__=%d", major);
+   cpp_define_formatted (pfile, "__GNUC_MINOR__=%d", minor);
+   cpp_define_formatted (pfile, "__GNUC_PATCHLEVEL__=%d", patchlevel);
+   cpp_define_formatted (pfile, "__VERSION__=\"%s\"", version_string);
++  cpp_define_formatted (pfile, "__LINARO_RELEASE__=%d", linaro_release);
++  cpp_define_formatted (pfile, "__LINARO_SPIN__=%d", linaro_spin);
+   cpp_define_formatted (pfile, "__ATOMIC_RELAXED=%d", MEMMODEL_RELAXED);
+   cpp_define_formatted (pfile, "__ATOMIC_SEQ_CST=%d", MEMMODEL_SEQ_CST);
+   cpp_define_formatted (pfile, "__ATOMIC_ACQUIRE=%d", MEMMODEL_ACQUIRE);
+--- a/src/gcc/defaults.h
++++ b/src/gcc/defaults.h
+@@ -971,11 +971,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+ #define REG_WORDS_BIG_ENDIAN WORDS_BIG_ENDIAN
+ #endif
+ 
+-#ifdef TARGET_FLT_EVAL_METHOD
+-#define TARGET_FLT_EVAL_METHOD_NON_DEFAULT 1
+-#else
++#ifndef TARGET_FLT_EVAL_METHOD
+ #define TARGET_FLT_EVAL_METHOD 0
+-#define TARGET_FLT_EVAL_METHOD_NON_DEFAULT 0
+ #endif
+ 
+ #ifndef TARGET_DEC_EVAL_METHOD
+--- a/src/gcc/expmed.c
++++ b/src/gcc/expmed.c
+@@ -2522,16 +2522,8 @@ expand_variable_shift (enum tree_code code, machine_mode mode, rtx shifted,
+ }
+ 
+ 
+-/* Indicates the type of fixup needed after a constant multiplication.
+-   BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
+-   the result should be negated, and ADD_VARIANT means that the
+-   multiplicand should be added to the result.  */
+-enum mult_variant {basic_variant, negate_variant, add_variant};
+-
+ static void synth_mult (struct algorithm *, unsigned HOST_WIDE_INT,
+ 			const struct mult_cost *, machine_mode mode);
+-static bool choose_mult_variant (machine_mode, HOST_WIDE_INT,
+-				 struct algorithm *, enum mult_variant *, int);
+ static rtx expand_mult_const (machine_mode, rtx, HOST_WIDE_INT, rtx,
+ 			      const struct algorithm *, enum mult_variant);
+ static unsigned HOST_WIDE_INT invert_mod2n (unsigned HOST_WIDE_INT, int);
+@@ -3021,7 +3013,7 @@ synth_mult (struct algorithm *alg_out, unsigned HOST_WIDE_INT t,
+    Return true if the cheapest of these cost less than MULT_COST,
+    describing the algorithm in *ALG and final fixup in *VARIANT.  */
+ 
+-static bool
++bool
+ choose_mult_variant (machine_mode mode, HOST_WIDE_INT val,
+ 		     struct algorithm *alg, enum mult_variant *variant,
+ 		     int mult_cost)
+--- a/src/gcc/expmed.h
++++ b/src/gcc/expmed.h
+@@ -35,6 +35,15 @@ enum alg_code {
+   alg_impossible
+ };
+ 
++/* Indicates the type of fixup needed after a constant multiplication.
++   BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
++   the result should be negated, and ADD_VARIANT means that the
++   multiplicand should be added to the result.  */
++enum mult_variant {basic_variant, negate_variant, add_variant};
++
++bool choose_mult_variant (machine_mode, HOST_WIDE_INT,
++			  struct algorithm *, enum mult_variant *, int);
++
+ /* This structure holds the "cost" of a multiply sequence.  The
+    "cost" field holds the total rtx_cost of every operator in the
+    synthetic multiplication sequence, hence cost(a op b) is defined
+--- a/src/gcc/fold-const.c
++++ b/src/gcc/fold-const.c
+@@ -7286,7 +7286,16 @@ native_encode_real (const_tree expr, unsigned char *ptr, int len, int off)
+ 	    offset += byte % UNITS_PER_WORD;
+ 	}
+       else
+-	offset = BYTES_BIG_ENDIAN ? 3 - byte : byte;
++	{
++	  offset = byte;
++	  if (BYTES_BIG_ENDIAN)
++	    {
++	      /* Reverse bytes within each long, or within the entire float
++		 if it's smaller than a long (for HFmode).  */
++	      offset = MIN (3, total_bytes - 1) - offset;
++	      gcc_assert (offset >= 0);
++	    }
++	}
+       offset = offset + ((bitpos / BITS_PER_UNIT) & ~3);
+       if (offset >= off
+ 	  && offset - off < len)
+--- a/src/gcc/fortran/options.c
++++ b/src/gcc/fortran/options.c
+@@ -208,8 +208,7 @@ gfc_post_options (const char **pfilename)
+ 
+   /* Excess precision other than "fast" requires front-end
+      support.  */
+-  if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD
+-      && TARGET_FLT_EVAL_METHOD_NON_DEFAULT)
++  if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD)
+     sorry ("-fexcess-precision=standard for Fortran");
+   flag_excess_precision_cmdline = EXCESS_PRECISION_FAST;
+ 
+--- a/src/gcc/genconditions.c
++++ b/src/gcc/genconditions.c
+@@ -94,6 +94,7 @@ write_header (void)
+ #include \"resource.h\"\n\
+ #include \"diagnostic-core.h\"\n\
+ #include \"reload.h\"\n\
++#include \"memmodel.h\"\n\
+ #include \"tm-constrs.h\"\n");
+ 
+   if (saw_eh_return)
+--- a/src/gcc/genemit.c
++++ b/src/gcc/genemit.c
+@@ -792,6 +792,7 @@ from the machine description file `md'.  */\n\n");
+   printf ("#include \"reload.h\"\n");
+   printf ("#include \"diagnostic-core.h\"\n");
+   printf ("#include \"regs.h\"\n");
++  printf ("#include \"memmodel.h\"\n");
+   printf ("#include \"tm-constrs.h\"\n");
+   printf ("#include \"ggc.h\"\n");
+   printf ("#include \"dumpfile.h\"\n");
+--- a/src/gcc/genmultilib
++++ b/src/gcc/genmultilib
+@@ -186,7 +186,8 @@ fi
+ EOF
+ chmod +x tmpmultilib
+ 
+-combinations=`initial=/ ./tmpmultilib ${options}`
++combination_space=`initial=/ ./tmpmultilib ${options}`
++combinations="$combination_space"
+ 
+ # If there exceptions, weed them out now
+ if [ -n "${exceptions}" ]; then
+@@ -472,14 +473,19 @@ for rrule in ${multilib_reuse}; do
+   # in this variable, it means no multilib will be built for current reuse
+   # rule.  Thus the reuse purpose specified by current rule is meaningless.
+   if expr "${combinations} " : ".*/${combo}/.*" > /dev/null; then
+-    combo="/${combo}/"
+-    dirout=`./tmpmultilib3 "${combo}" "${todirnames}" "${toosdirnames}" "${enable_multilib}"`
+-    copts="/${copts}/"
+-    optout=`./tmpmultilib4 "${copts}" "${options}"`
+-    # Output the line with all appropriate matches.
+-    dirout="${dirout}" optout="${optout}" ./tmpmultilib2
++    if expr "${combination_space} " : ".*/${copts}/.*" > /dev/null; then
++      combo="/${combo}/"
++      dirout=`./tmpmultilib3 "${combo}" "${todirnames}" "${toosdirnames}" "${enable_multilib}"`
++      copts="/${copts}/"
++      optout=`./tmpmultilib4 "${copts}" "${options}"`
++      # Output the line with all appropriate matches.
++      dirout="${dirout}" optout="${optout}" ./tmpmultilib2
++    else
++      echo "The rule ${rrule} contains an option absent from MULTILIB_OPTIONS." >&2
++      exit 1
++    fi
+   else
+-    echo "The rule ${rrule} is trying to reuse nonexistent multilib."
++    echo "The rule ${rrule} is trying to reuse nonexistent multilib." >&2
+     exit 1
+   fi
+ done
+--- a/src/gcc/genoutput.c
++++ b/src/gcc/genoutput.c
+@@ -231,6 +231,7 @@ output_prologue (void)
+   printf ("#include \"diagnostic-core.h\"\n");
+   printf ("#include \"output.h\"\n");
+   printf ("#include \"target.h\"\n");
++  printf ("#include \"memmodel.h\"\n");
+   printf ("#include \"tm-constrs.h\"\n");
+ }
+ 
+--- a/src/gcc/genpeep.c
++++ b/src/gcc/genpeep.c
+@@ -373,6 +373,7 @@ from the machine description file `md'.  */\n\n");
+   printf ("#include \"except.h\"\n");
+   printf ("#include \"diagnostic-core.h\"\n");
+   printf ("#include \"flags.h\"\n");
++  printf ("#include \"memmodel.h\"\n");
+   printf ("#include \"tm-constrs.h\"\n\n");
+ 
+   printf ("extern rtx peep_operand[];\n\n");
+--- a/src/gcc/genpreds.c
++++ b/src/gcc/genpreds.c
+@@ -1577,6 +1577,7 @@ write_insn_preds_c (void)
+ #include \"reload.h\"\n\
+ #include \"regs.h\"\n\
+ #include \"emit-rtl.h\"\n\
++#include \"memmodel.h\"\n\
+ #include \"tm-constrs.h\"\n");
+ 
+   FOR_ALL_PREDICATES (p)
+--- a/src/gcc/genrecog.c
++++ b/src/gcc/genrecog.c
+@@ -4172,6 +4172,7 @@ write_header (void)
+ #include \"diagnostic-core.h\"\n\
+ #include \"reload.h\"\n\
+ #include \"regs.h\"\n\
++#include \"memmodel.h\"\n\
+ #include \"tm-constrs.h\"\n\
+ \n");
+ 
+--- a/src/gcc/gimple-fold.c
++++ b/src/gcc/gimple-fold.c
+@@ -1379,6 +1379,55 @@ gimple_fold_builtin_strncpy (gimple_stmt_iterator *gsi,
+   return true;
+ }
+ 
++/* Simplify strchr (str, 0) into str + strlen (str).
++   In general strlen is significantly faster than strchr
++   due to being a simpler operation.  */
++static bool
++gimple_fold_builtin_strchr (gimple_stmt_iterator *gsi)
++{
++  gimple *stmt = gsi_stmt (*gsi);
++  tree str = gimple_call_arg (stmt, 0);
++  tree c = gimple_call_arg (stmt, 1);
++  location_t loc = gimple_location (stmt);
++
++  if (optimize_function_for_size_p (cfun))
++    return false;
++
++  if (!integer_zerop (c) || !gimple_call_lhs (stmt))
++    return false;
++
++  tree len;
++  tree strlen_fn = builtin_decl_implicit (BUILT_IN_STRLEN);
++
++  if (!strlen_fn)
++    return false;
++
++  /* Create newstr = strlen (str).  */
++  gimple_seq stmts = NULL;
++  gimple *new_stmt = gimple_build_call (strlen_fn, 1, str);
++  gimple_set_location (new_stmt, loc);
++  if (gimple_in_ssa_p (cfun))
++    len = make_ssa_name (size_type_node);
++  else
++    len = create_tmp_reg (size_type_node);
++  gimple_call_set_lhs (new_stmt, len);
++  gimple_seq_add_stmt_without_update (&stmts, new_stmt);
++
++  /* Create (str p+ strlen (str)).  */
++  new_stmt = gimple_build_assign (gimple_call_lhs (stmt),
++				  POINTER_PLUS_EXPR, str, len);
++  gimple_seq_add_stmt_without_update (&stmts, new_stmt);
++  gsi_replace_with_seq_vops (gsi, stmts);
++  /* gsi now points at the assignment to the lhs, get a
++     stmt iterator to the strlen.
++     ???  We can't use gsi_for_stmt as that doesn't work when the
++     CFG isn't built yet.  */
++  gimple_stmt_iterator gsi2 = *gsi;
++  gsi_prev (&gsi2);
++  fold_stmt (&gsi2);
++  return true;
++}
++
+ /* Simplify a call to the strcat builtin.  DST and SRC are the arguments
+    to the call.
+ 
+@@ -2820,6 +2869,11 @@ gimple_fold_builtin (gimple_stmt_iterator *gsi)
+ 					 gimple_call_arg (stmt, 1));
+     case BUILT_IN_STRNCAT:
+       return gimple_fold_builtin_strncat (gsi);
++    case BUILT_IN_STRCHR:
++      if (gimple_fold_builtin_strchr (gsi))
++	return true;
++      /* Perform additional folding in builtin.c.  */
++      break;
+     case BUILT_IN_FPUTS:
+       return gimple_fold_builtin_fputs (gsi, gimple_call_arg (stmt, 0),
+ 					gimple_call_arg (stmt, 1), false);
+--- a/src/gcc/hooks.c
++++ b/src/gcc/hooks.c
+@@ -481,3 +481,12 @@ void
+ hook_void_gcc_optionsp (struct gcc_options *opts ATTRIBUTE_UNUSED)
+ {
+ }
++
++/* Generic hook that takes an unsigned int, an unsigned int pointer and
++   returns false.  */
++
++bool
++hook_bool_uint_uintp_false (unsigned int, unsigned int *)
++{
++  return false;
++}
+--- a/src/gcc/hooks.h
++++ b/src/gcc/hooks.h
+@@ -76,6 +76,7 @@ extern void hook_void_tree (tree);
+ extern void hook_void_tree_treeptr (tree, tree *);
+ extern void hook_void_int_int (int, int);
+ extern void hook_void_gcc_optionsp (struct gcc_options *);
++extern bool hook_bool_uint_uintp_false (unsigned int, unsigned int *);
+ 
+ extern int hook_int_uint_mode_1 (unsigned int, machine_mode);
+ extern int hook_int_const_tree_0 (const_tree);
+--- a/src/gcc/ifcvt.c
++++ b/src/gcc/ifcvt.c
+@@ -813,10 +813,15 @@ struct noce_if_info
+ 
+   /* Estimated cost of the particular branch instruction.  */
+   unsigned int branch_cost;
++
++  /* The name of the noce transform that succeeded in if-converting
++     this structure.  Used for debugging.  */
++  const char *transform_name;
+ };
+ 
+ static rtx noce_emit_store_flag (struct noce_if_info *, rtx, int, int);
+ static int noce_try_move (struct noce_if_info *);
++static int noce_try_ifelse_collapse (struct noce_if_info *);
+ static int noce_try_store_flag (struct noce_if_info *);
+ static int noce_try_addcc (struct noce_if_info *);
+ static int noce_try_store_flag_constants (struct noce_if_info *);
+@@ -1115,11 +1120,45 @@ noce_try_move (struct noce_if_info *if_info)
+ 	  emit_insn_before_setloc (seq, if_info->jump,
+ 				   INSN_LOCATION (if_info->insn_a));
+ 	}
++      if_info->transform_name = "noce_try_move";
+       return TRUE;
+     }
+   return FALSE;
+ }
+ 
++/* Try forming an IF_THEN_ELSE (cond, b, a) and collapsing that
++   through simplify_rtx.  Sometimes that can eliminate the IF_THEN_ELSE.
++   If that is the case, emit the result into x.  */
++
++static int
++noce_try_ifelse_collapse (struct noce_if_info * if_info)
++{
++  if (!noce_simple_bbs (if_info))
++    return FALSE;
++
++  machine_mode mode = GET_MODE (if_info->x);
++  rtx if_then_else = simplify_gen_ternary (IF_THEN_ELSE, mode, mode,
++					    if_info->cond, if_info->b,
++					    if_info->a);
++
++  if (GET_CODE (if_then_else) == IF_THEN_ELSE)
++    return FALSE;
++
++  rtx_insn *seq;
++  start_sequence ();
++  noce_emit_move_insn (if_info->x, if_then_else);
++  seq = end_ifcvt_sequence (if_info);
++  if (!seq)
++    return FALSE;
++
++  emit_insn_before_setloc (seq, if_info->jump,
++			  INSN_LOCATION (if_info->insn_a));
++
++  if_info->transform_name = "noce_try_ifelse_collapse";
++  return TRUE;
++}
++
++
+ /* Convert "if (test) x = 1; else x = 0".
+ 
+    Only try 0 and STORE_FLAG_VALUE here.  Other combinations will be
+@@ -1163,6 +1202,7 @@ noce_try_store_flag (struct noce_if_info *if_info)
+ 
+       emit_insn_before_setloc (seq, if_info->jump,
+ 			       INSN_LOCATION (if_info->insn_a));
++      if_info->transform_name = "noce_try_store_flag";
+       return TRUE;
+     }
+   else
+@@ -1241,6 +1281,7 @@ noce_try_inverse_constants (struct noce_if_info *if_info)
+ 
+       emit_insn_before_setloc (seq, if_info->jump,
+ 			       INSN_LOCATION (if_info->insn_a));
++      if_info->transform_name = "noce_try_inverse_constants";
+       return true;
+     }
+ 
+@@ -1461,6 +1502,8 @@ noce_try_store_flag_constants (struct noce_if_info *if_info)
+ 
+       emit_insn_before_setloc (seq, if_info->jump,
+ 			       INSN_LOCATION (if_info->insn_a));
++      if_info->transform_name = "noce_try_store_flag_constants";
++
+       return TRUE;
+     }
+ 
+@@ -1513,6 +1556,8 @@ noce_try_addcc (struct noce_if_info *if_info)
+ 
+ 	      emit_insn_before_setloc (seq, if_info->jump,
+ 				       INSN_LOCATION (if_info->insn_a));
++	      if_info->transform_name = "noce_try_addcc";
++
+ 	      return TRUE;
+ 	    }
+ 	  end_sequence ();
+@@ -1553,6 +1598,7 @@ noce_try_addcc (struct noce_if_info *if_info)
+ 
+ 	      emit_insn_before_setloc (seq, if_info->jump,
+ 				       INSN_LOCATION (if_info->insn_a));
++	      if_info->transform_name = "noce_try_addcc";
+ 	      return TRUE;
+ 	    }
+ 	  end_sequence ();
+@@ -1617,6 +1663,8 @@ noce_try_store_flag_mask (struct noce_if_info *if_info)
+ 
+ 	  emit_insn_before_setloc (seq, if_info->jump,
+ 				   INSN_LOCATION (if_info->insn_a));
++	  if_info->transform_name = "noce_try_store_flag_mask";
++
+ 	  return TRUE;
+ 	}
+ 
+@@ -1767,6 +1815,8 @@ noce_try_cmove (struct noce_if_info *if_info)
+ 
+ 	  emit_insn_before_setloc (seq, if_info->jump,
+ 				   INSN_LOCATION (if_info->insn_a));
++	  if_info->transform_name = "noce_try_cmove";
++
+ 	  return TRUE;
+ 	}
+       /* If both a and b are constants try a last-ditch transformation:
+@@ -1820,6 +1870,7 @@ noce_try_cmove (struct noce_if_info *if_info)
+ 
+ 	      emit_insn_before_setloc (seq, if_info->jump,
+ 				   INSN_LOCATION (if_info->insn_a));
++	      if_info->transform_name = "noce_try_cmove";
+ 	      return TRUE;
+ 	    }
+ 	  else
+@@ -2273,6 +2324,7 @@ noce_try_cmove_arith (struct noce_if_info *if_info)
+ 
+   emit_insn_before_setloc (ifcvt_seq, if_info->jump,
+ 			   INSN_LOCATION (if_info->insn_a));
++  if_info->transform_name = "noce_try_cmove_arith";
+   return TRUE;
+ 
+  end_seq_and_fail:
+@@ -2364,28 +2416,32 @@ noce_get_alt_condition (struct noce_if_info *if_info, rtx target,
+ 	  switch (code)
+ 	    {
+ 	    case LT:
+-	      if (actual_val == desired_val + 1)
++	      if (desired_val != HOST_WIDE_INT_MAX
++		  && actual_val == desired_val + 1)
+ 		{
+ 		  code = LE;
+ 		  op_b = GEN_INT (desired_val);
+ 		}
+ 	      break;
+ 	    case LE:
+-	      if (actual_val == desired_val - 1)
++	      if (desired_val != HOST_WIDE_INT_MIN
++		  && actual_val == desired_val - 1)
+ 		{
+ 		  code = LT;
+ 		  op_b = GEN_INT (desired_val);
+ 		}
+ 	      break;
+ 	    case GT:
+-	      if (actual_val == desired_val - 1)
++	      if (desired_val != HOST_WIDE_INT_MIN
++		  && actual_val == desired_val - 1)
+ 		{
+ 		  code = GE;
+ 		  op_b = GEN_INT (desired_val);
+ 		}
+ 	      break;
+ 	    case GE:
+-	      if (actual_val == desired_val + 1)
++	      if (desired_val != HOST_WIDE_INT_MAX
++		  && actual_val == desired_val + 1)
+ 		{
+ 		  code = GT;
+ 		  op_b = GEN_INT (desired_val);
+@@ -2525,6 +2581,7 @@ noce_try_minmax (struct noce_if_info *if_info)
+   emit_insn_before_setloc (seq, if_info->jump, INSN_LOCATION (if_info->insn_a));
+   if_info->cond = cond;
+   if_info->cond_earliest = earliest;
++  if_info->transform_name = "noce_try_minmax";
+ 
+   return TRUE;
+ }
+@@ -2691,6 +2748,7 @@ noce_try_abs (struct noce_if_info *if_info)
+   emit_insn_before_setloc (seq, if_info->jump, INSN_LOCATION (if_info->insn_a));
+   if_info->cond = cond;
+   if_info->cond_earliest = earliest;
++  if_info->transform_name = "noce_try_abs";
+ 
+   return TRUE;
+ }
+@@ -2772,6 +2830,8 @@ noce_try_sign_mask (struct noce_if_info *if_info)
+     return FALSE;
+ 
+   emit_insn_before_setloc (seq, if_info->jump, INSN_LOCATION (if_info->insn_a));
++  if_info->transform_name = "noce_try_sign_mask";
++
+   return TRUE;
+ }
+ 
+@@ -2877,6 +2937,7 @@ noce_try_bitop (struct noce_if_info *if_info)
+       emit_insn_before_setloc (seq, if_info->jump,
+ 			       INSN_LOCATION (if_info->insn_a));
+     }
++  if_info->transform_name = "noce_try_bitop";
+   return TRUE;
+ }
+ 
+@@ -3167,6 +3228,41 @@ noce_convert_multiple_sets (struct noce_if_info *if_info)
+       if (if_info->then_else_reversed)
+ 	std::swap (old_val, new_val);
+ 
++
++      /* We allow simple lowpart register subreg SET sources in
++	 bb_ok_for_noce_convert_multiple_sets.  Be careful when processing
++	 sequences like:
++	 (set (reg:SI r1) (reg:SI r2))
++	 (set (reg:HI r3) (subreg:HI (r1)))
++	 For the second insn new_val or old_val (r1 in this example) will be
++	 taken from the temporaries and have the wider mode which will not
++	 match with the mode of the other source of the conditional move, so
++	 we'll end up trying to emit r4:HI = cond ? (r1:SI) : (r3:HI).
++	 Wrap the two cmove operands into subregs if appropriate to prevent
++	 that.  */
++      if (GET_MODE (new_val) != GET_MODE (temp))
++	{
++	  machine_mode src_mode = GET_MODE (new_val);
++	  machine_mode dst_mode = GET_MODE (temp);
++	  if (GET_MODE_SIZE (src_mode) <= GET_MODE_SIZE (dst_mode))
++	    {
++	      end_sequence ();
++	      return FALSE;
++	    }
++	  new_val = lowpart_subreg (dst_mode, new_val, src_mode);
++	}
++      if (GET_MODE (old_val) != GET_MODE (temp))
++	{
++	  machine_mode src_mode = GET_MODE (old_val);
++	  machine_mode dst_mode = GET_MODE (temp);
++	  if (GET_MODE_SIZE (src_mode) <= GET_MODE_SIZE (dst_mode))
++	    {
++	      end_sequence ();
++	      return FALSE;
++	    }
++	  old_val = lowpart_subreg (dst_mode, old_val, src_mode);
++	}
++
+       /* Actually emit the conditional move.  */
+       rtx temp_dest = noce_emit_cmove (if_info, temp, cond_code,
+ 				       x, y, new_val, old_val);
+@@ -3240,6 +3336,7 @@ noce_convert_multiple_sets (struct noce_if_info *if_info)
+     }
+ 
+   num_updated_if_blocks++;
++  if_info->transform_name = "noce_convert_multiple_sets";
+   return TRUE;
+ }
+ 
+@@ -3277,9 +3374,15 @@ bb_ok_for_noce_convert_multiple_sets (basic_block test_bb,
+       rtx src = SET_SRC (set);
+ 
+       /* We can possibly relax this, but for now only handle REG to REG
+-	 moves.  This avoids any issues that might come from introducing
+-	 loads/stores that might violate data-race-freedom guarantees.  */
+-      if (!(REG_P (src) && REG_P (dest)))
++	 (including subreg) moves.  This avoids any issues that might come
++	 from introducing loads/stores that might violate data-race-freedom
++	 guarantees.  */
++      if (!REG_P (dest))
++	return false;
++
++      if (!(REG_P (src)
++	   || (GET_CODE (src) == SUBREG && REG_P (SUBREG_REG (src))
++	       && subreg_lowpart_p (src))))
+ 	return false;
+ 
+       /* Destination must be appropriate for a conditional write.  */
+@@ -3336,7 +3439,12 @@ noce_process_if_block (struct noce_if_info *if_info)
+       && bb_ok_for_noce_convert_multiple_sets (then_bb, if_info))
+     {
+       if (noce_convert_multiple_sets (if_info))
+-	return TRUE;
++	{
++	  if (dump_file && if_info->transform_name)
++	    fprintf (dump_file, "if-conversion succeeded through %s\n",
++		     if_info->transform_name);
++	  return TRUE;
++	}
+     }
+ 
+   if (! bb_valid_for_noce_process_p (then_bb, cond, &if_info->then_cost,
+@@ -3493,6 +3601,8 @@ noce_process_if_block (struct noce_if_info *if_info)
+ 
+   if (noce_try_move (if_info))
+     goto success;
++  if (noce_try_ifelse_collapse (if_info))
++    goto success;
+   if (noce_try_store_flag (if_info))
+     goto success;
+   if (noce_try_bitop (if_info))
+@@ -3533,6 +3643,9 @@ noce_process_if_block (struct noce_if_info *if_info)
+   return FALSE;
+ 
+  success:
++  if (dump_file && if_info->transform_name)
++    fprintf (dump_file, "if-conversion succeeded through %s\n",
++	     if_info->transform_name);
+ 
+   /* If we used a temporary, fix it up now.  */
+   if (orig_x != x)
+--- a/src/gcc/internal-fn.c
++++ b/src/gcc/internal-fn.c
+@@ -1812,11 +1812,7 @@ expand_arith_overflow (enum tree_code code, gimple *stmt)
+       /* For sub-word operations, retry with a wider type first.  */
+       if (orig_precres == precres && precop <= BITS_PER_WORD)
+ 	{
+-#if WORD_REGISTER_OPERATIONS
+-	  int p = BITS_PER_WORD;
+-#else
+-	  int p = precop;
+-#endif
++	  int p = WORD_REGISTER_OPERATIONS ? BITS_PER_WORD : precop;
+ 	  enum machine_mode m = smallest_mode_for_size (p, MODE_INT);
+ 	  tree optype = build_nonstandard_integer_type (GET_MODE_PRECISION (m),
+ 							uns0_p && uns1_p
+--- a/src/gcc/java/lang.c
++++ b/src/gcc/java/lang.c
+@@ -569,8 +569,7 @@ java_post_options (const char **pfilename)
+ 
+   /* Excess precision other than "fast" requires front-end
+      support.  */
+-  if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD
+-      && TARGET_FLT_EVAL_METHOD_NON_DEFAULT)
++  if (flag_excess_precision_cmdline == EXCESS_PRECISION_STANDARD)
+     sorry ("-fexcess-precision=standard for Java");
+   flag_excess_precision_cmdline = EXCESS_PRECISION_FAST;
+ 
+--- a/src/gcc/lra-constraints.c
++++ b/src/gcc/lra-constraints.c
+@@ -1326,7 +1326,22 @@ process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **aft
+ 
+   subreg_p = GET_CODE (*loc) == SUBREG;
+   if (subreg_p)
+-    loc = &SUBREG_REG (*loc);
++    {
++      reg = SUBREG_REG (*loc);
++      mode = GET_MODE (reg);
++
++      /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
++	 between two registers with different classes, but there normally will
++	 be "mov" which transfers element of vector register into the general
++	 register, and this normally will be a subreg which should be reloaded
++	 as a whole.  This is particularly likely to be triggered when
++	 -fno-split-wide-types specified.  */
++      if (!REG_P (reg)
++	  || in_class_p (reg, cl, &new_class)
++	  || GET_MODE_SIZE (mode) <= GET_MODE_SIZE (ptr_mode))
++       loc = &SUBREG_REG (*loc);
++    }
++
+   reg = *loc;
+   mode = GET_MODE (reg);
+   if (! REG_P (reg))
+@@ -2475,14 +2490,29 @@ process_alt_operands (int only_alternative)
+ 	      /* We are trying to spill pseudo into memory.  It is
+ 		 usually more costly than moving to a hard register
+ 		 although it might takes the same number of
+-		 reloads.  */
+-	      if (no_regs_p && REG_P (op) && hard_regno[nop] >= 0)
++		 reloads.
++
++		 Non-pseudo spill may happen also.  Suppose a target allows both
++		 register and memory in the operand constraint alternatives,
++		 then it's typical that an eliminable register has a substition
++		 of "base + offset" which can either be reloaded by a simple
++		 "new_reg <= base + offset" which will match the register
++		 constraint, or a similar reg addition followed by further spill
++		 to and reload from memory which will match the memory
++		 constraint, but this memory spill will be much more costly
++		 usually.
++
++		 Code below increases the reject for both pseudo and non-pseudo
++		 spill.  */
++	      if (no_regs_p
++		  && !(MEM_P (op) && offmemok)
++		  && !(REG_P (op) && hard_regno[nop] < 0))
+ 		{
+ 		  if (lra_dump_file != NULL)
+ 		    fprintf
+ 		      (lra_dump_file,
+-		       "            %d Spill pseudo into memory: reject+=3\n",
+-		       nop);
++		       "            %d Spill %spseudo into memory: reject+=3\n",
++		       nop, REG_P (op) ? "" : "Non-");
+ 		  reject += 3;
+ 		  if (VECTOR_MODE_P (mode))
+ 		    {
+--- a/src/gcc/lto/lto-partition.c
++++ b/src/gcc/lto/lto-partition.c
+@@ -447,7 +447,7 @@ add_sorted_nodes (vec<symtab_node *> &next_nodes, ltrans_partition partition)
+    and in-partition calls was reached.  */
+ 
+ void
+-lto_balanced_map (int n_lto_partitions)
++lto_balanced_map (int n_lto_partitions, int max_partition_size)
+ {
+   int n_nodes = 0;
+   int n_varpool_nodes = 0, varpool_pos = 0, best_varpool_pos = 0;
+@@ -511,6 +511,9 @@ lto_balanced_map (int n_lto_partitions)
+   varpool_order.qsort (varpool_node_cmp);
+ 
+   /* Compute partition size and create the first partition.  */
++  if (PARAM_VALUE (MIN_PARTITION_SIZE) > max_partition_size)
++    fatal_error (input_location, "min partition size cannot be greater than max partition size");
++
+   partition_size = total_size / n_lto_partitions;
+   if (partition_size < PARAM_VALUE (MIN_PARTITION_SIZE))
+     partition_size = PARAM_VALUE (MIN_PARTITION_SIZE);
+@@ -720,7 +723,8 @@ lto_balanced_map (int n_lto_partitions)
+ 		 best_cost, best_internal, best_i);
+       /* Partition is too large, unwind into step when best cost was reached and
+ 	 start new partition.  */
+-      if (partition->insns > 2 * partition_size)
++      if (partition->insns > 2 * partition_size
++	  || partition->insns > max_partition_size)
+ 	{
+ 	  if (best_i != i)
+ 	    {
+--- a/src/gcc/lto/lto-partition.h
++++ b/src/gcc/lto/lto-partition.h
+@@ -35,7 +35,7 @@ extern vec<ltrans_partition> ltrans_partitions;
+ 
+ void lto_1_to_1_map (void);
+ void lto_max_map (void);
+-void lto_balanced_map (int);
++void lto_balanced_map (int, int);
+ void lto_promote_cross_file_statics (void);
+ void free_ltrans_partitions (void);
+ void lto_promote_statics_nonwpa (void);
+--- a/src/gcc/lto/lto.c
++++ b/src/gcc/lto/lto.c
+@@ -3123,9 +3123,10 @@ do_whole_program_analysis (void)
+   else if (flag_lto_partition == LTO_PARTITION_MAX)
+     lto_max_map ();
+   else if (flag_lto_partition == LTO_PARTITION_ONE)
+-    lto_balanced_map (1);
++    lto_balanced_map (1, INT_MAX);
+   else if (flag_lto_partition == LTO_PARTITION_BALANCED)
+-    lto_balanced_map (PARAM_VALUE (PARAM_LTO_PARTITIONS));
++    lto_balanced_map (PARAM_VALUE (PARAM_LTO_PARTITIONS),
++		      PARAM_VALUE (MAX_PARTITION_SIZE));
+   else
+     gcc_unreachable ();
+ 
+--- a/src/gcc/match.pd
++++ b/src/gcc/match.pd
+@@ -468,6 +468,12 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
+  (bit_and:c (convert? @0) (convert? (bit_not @0)))
+   { build_zero_cst (type); })
+ 
++/* PR71636: Transform x & ((1U << b) - 1) -> x & ~(~0U << b);  */
++(simplify
++  (bit_and:c @0 (plus:s (lshift:s integer_onep @1) integer_minus_onep))
++  (if (TYPE_UNSIGNED (type))
++    (bit_and @0 (bit_not (lshift { build_all_ones_cst (type); } @1)))))
++
+ /* Fold (A & ~B) - (A & B) into (A ^ B) - B.  */
+ (simplify
+  (minus (bit_and:cs @0 (bit_not @1)) (bit_and:cs @0 @1))
+--- /dev/null
++++ b/src/gcc/memmodel.h
+@@ -0,0 +1,86 @@
++/* Prototypes of memory model helper functions.
++   Copyright (C) 2015-2016 Free Software Foundation, Inc.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify it under
++the terms of the GNU General Public License as published by the Free
++Software Foundation; either version 3, or (at your option) any later
++version.
++
++GCC is distributed in the hope that it will be useful, but WITHOUT ANY
++WARRANTY; without even the implied warranty of MERCHANTABILITY or
++FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++#ifndef GCC_MEMMODEL_H
++#define GCC_MEMMODEL_H
++
++/* Return the memory model from a host integer.  */
++static inline enum memmodel
++memmodel_from_int (unsigned HOST_WIDE_INT val)
++{
++  return (enum memmodel) (val & MEMMODEL_MASK);
++}
++
++/* Return the base memory model from a host integer.  */
++static inline enum memmodel
++memmodel_base (unsigned HOST_WIDE_INT val)
++{
++  return (enum memmodel) (val & MEMMODEL_BASE_MASK);
++}
++
++/* Return TRUE if the memory model is RELAXED.  */
++static inline bool
++is_mm_relaxed (enum memmodel model)
++{
++  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_RELAXED;
++}
++
++/* Return TRUE if the memory model is CONSUME.  */
++static inline bool
++is_mm_consume (enum memmodel model)
++{
++  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_CONSUME;
++}
++
++/* Return TRUE if the memory model is ACQUIRE.  */
++static inline bool
++is_mm_acquire (enum memmodel model)
++{
++  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_ACQUIRE;
++}
++
++/* Return TRUE if the memory model is RELEASE.  */
++static inline bool
++is_mm_release (enum memmodel model)
++{
++  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_RELEASE;
++}
++
++/* Return TRUE if the memory model is ACQ_REL.  */
++static inline bool
++is_mm_acq_rel (enum memmodel model)
++{
++  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_ACQ_REL;
++}
++
++/* Return TRUE if the memory model is SEQ_CST.  */
++static inline bool
++is_mm_seq_cst (enum memmodel model)
++{
++  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_SEQ_CST;
++}
++
++/* Return TRUE if the memory model is a SYNC variant.  */
++static inline bool
++is_mm_sync (enum memmodel model)
++{
++  return (model & MEMMODEL_SYNC);
++}
++
++#endif  /* GCC_MEMMODEL_H  */
+--- a/src/gcc/optabs.c
++++ b/src/gcc/optabs.c
+@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "target.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "predict.h"
+ #include "tm_p.h"
+ #include "expmed.h"
+--- a/src/gcc/params.def
++++ b/src/gcc/params.def
+@@ -1027,7 +1027,12 @@ DEFPARAM (PARAM_LTO_PARTITIONS,
+ DEFPARAM (MIN_PARTITION_SIZE,
+ 	  "lto-min-partition",
+ 	  "Minimal size of a partition for LTO (in estimated instructions).",
+-	  1000, 0, 0)
++	  10000, 0, 0)
++
++DEFPARAM (MAX_PARTITION_SIZE,
++	  "lto-max-partition",
++	  "Maximal size of a partition for LTO (in estimated instructions).",
++	  1000000, 0, INT_MAX)
+ 
+ /* Diagnostic parameters.  */
+ 
+--- a/src/gcc/rtlanal.c
++++ b/src/gcc/rtlanal.c
+@@ -3663,6 +3663,16 @@ subreg_get_info (unsigned int xregno, machine_mode xmode,
+ 	  info->offset = offset / regsize_xmode;
+ 	  return;
+ 	}
++      /* It's not valid to extract a subreg of mode YMODE at OFFSET that
++	 would go outside of XMODE.  */
++      if (!rknown
++	  && GET_MODE_SIZE (ymode) + offset > GET_MODE_SIZE (xmode))
++	{
++	  info->representable_p = false;
++	  info->nregs = nregs_ymode;
++	  info->offset = offset / regsize_xmode;
++	  return;
++	}
+       /* Quick exit for the simple and common case of extracting whole
+ 	 subregisters from a multiregister value.  */
+       /* ??? It would be better to integrate this into the code below,
+@@ -4590,13 +4600,14 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
+ 	  nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
+ 					  known_x, known_mode, known_ret);
+ 
+-#if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP)
++#ifdef LOAD_EXTEND_OP
+ 	  /* If this is a typical RISC machine, we only have to worry
+ 	     about the way loads are extended.  */
+-	  if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
+-	       ? val_signbit_known_set_p (inner_mode, nonzero)
+-	       : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
+-	      || !MEM_P (SUBREG_REG (x)))
++	  if (WORD_REGISTER_OPERATIONS
++	      && ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
++		     ? val_signbit_known_set_p (inner_mode, nonzero)
++		     : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
++		   || !MEM_P (SUBREG_REG (x))))
+ #endif
+ 	    {
+ 	      /* On many CISC machines, accessing an object in a wider mode
+--- a/src/gcc/simplify-rtx.c
++++ b/src/gcc/simplify-rtx.c
+@@ -5256,6 +5256,50 @@ simplify_const_relational_operation (enum rtx_code code,
+ 
+   return 0;
+ }
++
++/* Recognize expressions of the form (X CMP 0) ? VAL : OP (X)
++   where OP is CLZ or CTZ and VAL is the value from CLZ_DEFINED_VALUE_AT_ZERO
++   or CTZ_DEFINED_VALUE_AT_ZERO respectively and return OP (X) if the expression
++   can be simplified to that or NULL_RTX if not.
++   Assume X is compared against zero with CMP_CODE and the true
++   arm is TRUE_VAL and the false arm is FALSE_VAL.  */
++
++static rtx
++simplify_cond_clz_ctz (rtx x, rtx_code cmp_code, rtx true_val, rtx false_val)
++{
++  if (cmp_code != EQ && cmp_code != NE)
++    return NULL_RTX;
++
++  /* Result on X == 0 and X !=0 respectively.  */
++  rtx on_zero, on_nonzero;
++  if (cmp_code == EQ)
++    {
++      on_zero = true_val;
++      on_nonzero = false_val;
++    }
++  else
++    {
++      on_zero = false_val;
++      on_nonzero = true_val;
++    }
++
++  rtx_code op_code = GET_CODE (on_nonzero);
++  if ((op_code != CLZ && op_code != CTZ)
++      || !rtx_equal_p (XEXP (on_nonzero, 0), x)
++      || !CONST_INT_P (on_zero))
++    return NULL_RTX;
++
++  HOST_WIDE_INT op_val;
++  if (((op_code == CLZ
++	&& CLZ_DEFINED_VALUE_AT_ZERO (GET_MODE (on_nonzero), op_val))
++      || (op_code == CTZ
++	  && CTZ_DEFINED_VALUE_AT_ZERO (GET_MODE (on_nonzero), op_val)))
++      && op_val == INTVAL (on_zero))
++    return on_nonzero;
++
++  return NULL_RTX;
++}
++
+ 
+ /* Simplify CODE, an operation with result mode MODE and three operands,
+    OP0, OP1, and OP2.  OP0_MODE was the mode of OP0 before it became
+@@ -5389,6 +5433,19 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
+ 	    }
+ 	}
+ 
++      /* Convert x == 0 ? N : clz (x) into clz (x) when
++	 CLZ_DEFINED_VALUE_AT_ZERO is defined to N for the mode of x.
++	 Similarly for ctz (x).  */
++      if (COMPARISON_P (op0) && !side_effects_p (op0)
++	  && XEXP (op0, 1) == const0_rtx)
++	{
++	  rtx simplified
++	    = simplify_cond_clz_ctz (XEXP (op0, 0), GET_CODE (op0),
++				     op1, op2);
++	  if (simplified)
++	    return simplified;
++	}
++
+       if (COMPARISON_P (op0) && ! side_effects_p (op0))
+ 	{
+ 	  machine_mode cmp_mode = (GET_MODE (XEXP (op0, 0)) == VOIDmode
+--- a/src/gcc/system.h
++++ b/src/gcc/system.h
+@@ -971,7 +971,8 @@ extern void fancy_abort (const char *, int, const char *) ATTRIBUTE_NORETURN;
+ 	EXTRA_ADDRESS_CONSTRAINT CONST_DOUBLE_OK_FOR_CONSTRAINT_P	   \
+ 	CALLER_SAVE_PROFITABLE LARGEST_EXPONENT_IS_NORMAL		   \
+ 	ROUND_TOWARDS_ZERO SF_SIZE DF_SIZE XF_SIZE TF_SIZE LIBGCC2_TF_CEXT \
+-	LIBGCC2_LONG_DOUBLE_TYPE_SIZE STRUCT_VALUE EH_FRAME_IN_DATA_SECTION
++	LIBGCC2_LONG_DOUBLE_TYPE_SIZE STRUCT_VALUE			   \
++	EH_FRAME_IN_DATA_SECTION TARGET_FLT_EVAL_METHOD_NON_DEFAULT
+ 
+ /* Hooks that are no longer used.  */
+  #pragma GCC poison LANG_HOOKS_FUNCTION_MARK LANG_HOOKS_FUNCTION_FREE	\
+--- a/src/gcc/target.def
++++ b/src/gcc/target.def
+@@ -432,6 +432,22 @@ this section is associated.",
+  void, (const char *name, unsigned int flags, tree decl),
+  default_no_named_section)
+ 
++/* Tell assembler what section attributes to assign this elf section
++   declaration, using their numerical value.  */
++DEFHOOK
++(elf_flags_numeric,
++ "This hook can be used to encode ELF section flags for which no letter\n\
++code has been defined in the assembler.  It is called by\n\
++@code{default_asm_named_section} whenever the section flags need to be\n\
++emitted in the assembler output.  If the hook returns true, then the\n\
++numerical value for ELF section flags should be calculated from\n\
++@var{flags} and saved in @var{*num}; the value is printed out instead of the\n\
++normal sequence of letter codes.  If the hook is not defined, or if it\n\
++returns false, then @var{num} is ignored and the traditional letter sequence\n\
++is emitted.",
++ bool, (unsigned int flags, unsigned int *num),
++ hook_bool_uint_uintp_false)
++
+ /* Return preferred text (sub)section for function DECL.
+    Main purpose of this function is to separate cold, normal and hot
+    functions. STARTUP is true when function is known to be used only 
+--- a/src/gcc/testsuite/c-c++-common/asan/clone-test-1.c
++++ b/src/gcc/testsuite/c-c++-common/asan/clone-test-1.c
+@@ -29,6 +29,10 @@ int main(int argc, char **argv) {
+   char *sp = child_stack + kStackSize;  /* Stack grows down. */
+   printf("Parent: %p\n", sp);
+   pid_t clone_pid = clone(Child, sp, CLONE_FILES | CLONE_VM, NULL, 0, 0, 0);
++  if (clone_pid == -1) {
++    perror("clone");
++    return 1;
++  }
+   int status;
+   pid_t wait_result = waitpid(clone_pid, &status, __WCLONE);
+   if (wait_result < 0) {
+--- a/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-3.C
++++ b/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-3.C
+@@ -1,5 +1,6 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do run { target arm*-*-* } } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ #include "arm-fp16-ops.h"
+--- a/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-4.C
++++ b/src/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-4.C
+@@ -1,5 +1,6 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do run { target arm*-*-* } } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative -ffast-math" } */
+ 
+ #include "arm-fp16-ops.h"
+--- a/src/gcc/testsuite/g++.dg/ext/arm-fp16/fp16-param-1.C
++++ b/src/gcc/testsuite/g++.dg/ext/arm-fp16/fp16-param-1.C
+@@ -1,10 +1,14 @@
+ /* { dg-do compile { target arm*-*-* } } */
+ /* { dg-options "-mfp16-format=ieee" } */
+ 
+-/* Functions cannot have parameters of type __fp16.  */
+-extern void f (__fp16);		/* { dg-error "parameters cannot have __fp16 type" } */
+-extern void (*pf) (__fp16);	/* { dg-error "parameters cannot have __fp16 type" } */
++/* Test that the ACLE macro is defined.  */
++#if __ARM_FP16_ARGS != 1
++#error Unexpected value for __ARM_FP16_ARGS
++#endif
++
++/* Test that __fp16 is supported as a parameter type.  */
++extern void f (__fp16);
++extern void (*pf) (__fp16);
+ 
+-/* These should be OK.  */
+ extern void g (__fp16 *);
+ extern void (*pg) (__fp16 *);
+--- a/src/gcc/testsuite/g++.dg/ext/arm-fp16/fp16-return-1.C
++++ b/src/gcc/testsuite/g++.dg/ext/arm-fp16/fp16-return-1.C
+@@ -1,10 +1,9 @@
+ /* { dg-do compile { target arm*-*-* } } */
+ /* { dg-options "-mfp16-format=ieee" } */
+ 
+-/* Functions cannot return type __fp16.  */
+-extern __fp16 f (void);		/* { dg-error "cannot return __fp16" } */
+-extern __fp16 (*pf) (void);	/* { dg-error "cannot return __fp16" } */
++/* Test that __fp16 is supported as a return type.  */
++extern __fp16 f (void);
++extern __fp16 (*pf) (void);
+ 
+-/* These should be OK.  */
+ extern __fp16 *g (void);
+ extern __fp16 *(*pg) (void);
+--- a/src/gcc/testsuite/g++.dg/ext/mv8.C
++++ b/src/gcc/testsuite/g++.dg/ext/mv8.C
+@@ -1,4 +1,4 @@
+-// { dg-do compile { target i?86-*-* x86_64-*-* powerpc*-*-* } }
++// { dg-do compile { target i?86-*-* x86_64-*-* powerpc*-*-* aarch64*-*-* } }
+ // { dg-options "" }
+ 
+ __attribute__((target (11,12)))
+--- a/src/gcc/testsuite/g++.dg/inherit/thunk1.C
++++ b/src/gcc/testsuite/g++.dg/inherit/thunk1.C
+@@ -1,4 +1,5 @@
+-// { dg-do run { target i?86-*-* x86_64-*-* s390*-*-* alpha*-*-* ia64-*-* sparc*-*-* } }
++// { dg-do run { target arm*-*-* aarch64*-*-* i?86-*-* x86_64-*-* s390*-*-* alpha*-*-* ia64-*-* sparc*-*-* } }
++// { dg-skip-if "" { arm_thumb1_ok } }
+ 
+ #include <stdarg.h>
+ 
+--- a/src/gcc/testsuite/g++.dg/lto/pr69589_0.C
++++ b/src/gcc/testsuite/g++.dg/lto/pr69589_0.C
+@@ -1,7 +1,8 @@
+ // { dg-lto-do link }
+-// { dg-lto-options "-O2 -rdynamic" } 
++// { dg-lto-options "-O2 -rdynamic" }
+ // { dg-extra-ld-options "-r -nostdlib" }
+ // { dg-require-effective-target rdynamic }
++
+ #pragma GCC visibility push(hidden)
+ struct A { int &operator[] (long); };
+ template <typename> struct B;
+--- /dev/null
++++ b/src/gcc/testsuite/g++.dg/opt/pr78201.C
+@@ -0,0 +1,13 @@
++// PR middle-end/78201
++// { dg-do compile }
++// { dg-options "-O2" }
++
++struct B { long d (); } *c;
++long e;
++
++void
++foo ()
++{
++  char a[e] = "";
++  c && c->d();
++}
+--- a/src/gcc/testsuite/g++.dg/other/i386-9.C
++++ b/src/gcc/testsuite/g++.dg/other/i386-9.C
+@@ -2,6 +2,7 @@
+ // Testcase by Zdenek Sojka <zsojka@seznam.cz>
+ 
+ // { dg-do run { target i?86-*-* x86_64-*-* } }
++/* { dg-require-stack-check "" } */
+ // { dg-options "-Os -mpreferred-stack-boundary=5 -fstack-check -fno-omit-frame-pointer" }
+ 
+ int main()
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr71112.c
+@@ -0,0 +1,10 @@
++/* PR target/71112.  */
++/* { dg-additional-options "-fpie" { target pie } } */
++
++extern int dbs[100];
++void f (int *);
++int nscd_init (void)
++{
++  f (dbs);
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr71295.c
+@@ -0,0 +1,12 @@
++extern void fn2 (long long);
++int a;
++
++void
++fn1 ()
++{
++  long long b[3];
++  a = 0;
++  for (; a < 3; a++)
++    b[a] = 1;
++  fn2 (b[1]);
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr71436.c
+@@ -0,0 +1,35 @@
++/* PR target/71436.  */
++
++#pragma pack(1)
++struct S0
++{
++  volatile int f0;
++  short f2;
++};
++
++void foo (struct S0 *);
++int a, d;
++static struct S0 b[5];
++static struct S0 c;
++void fn1 ();
++void
++main ()
++{
++  {
++    struct S0 e;
++    for (; d; fn1 ())
++      {
++        {
++          a = 3;
++          for (; a >= 0; a -= 1)
++            {
++              {
++                e = c;
++              }
++              b[a] = e;
++            }
++        }
++      }
++  }
++  foo (b);
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr78362.c
+@@ -0,0 +1,11 @@
++/* PR target/78362.  */
++
++long a;
++
++void
++foo (void)
++{
++  for (;; a--)
++    if ((int) a)
++      break;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr78694.c
+@@ -0,0 +1,118 @@
++/* PR target/78694.  */
++
++enum
++{
++  MEMMODEL_RELAXED,
++  MEMMODEL_ACQUIRE,
++  PRIORITY_INSERT_END
++};
++enum
++{
++  PQ_CHILDREN,
++  PQ_TASKGROUP
++};
++struct gomp_team_state
++{
++  struct gomp_team *team;
++};
++enum gomp_task_kind
++{
++  GOMP_TASK_UNDEFERRED,
++  GOMP_TASK_WAITING
++};
++struct gomp_taskwait
++{
++  _Bool in_taskwait;
++};
++struct gomp_task
++{
++  struct gomp_task *parent;
++  int children_queue;
++  struct gomp_taskgroup *taskgroup;
++  int dependers;
++  struct gomp_taskwait taskwait;
++  enum gomp_task_kind kind;
++  _Bool in_tied_task;
++} j, q, *n;
++struct gomp_taskgroup
++{
++  _Bool in_taskgroup_wait;
++  int num_children;
++} l;
++struct gomp_team
++{
++  int task_queue;
++  int task_running_count;
++};
++struct gomp_thread
++{
++  struct gomp_team_state ts;
++  struct gomp_task task;
++} extern __thread a;
++
++int b, c, d, e, f, g, h, i, k, m, o, p, r;
++
++void priority_queue_next_task (struct gomp_task *, int, int);
++int gomp_task_run_pre (struct gomp_task *, struct gomp_task, struct gomp_team);
++void priority_queue_insert (int, struct gomp_task);
++void priority_queue_insert2 (int, struct gomp_task, int, int, int);
++void priority_queue_insert3 (int, struct gomp_task, int, int, int);
++void gomp_sem_post (int);
++void free (void *);
++
++_Bool s;
++int
++GOMP_taskgroup_end ()
++{
++  struct gomp_thread *t = &a;
++  struct gomp_team u = *t->ts.team;
++  struct gomp_task *v = &t->task, *w;
++  if (__atomic_load_n (&l.num_children, MEMMODEL_ACQUIRE))
++    while (1)
++      {
++	if (l.num_children)
++	  priority_queue_next_task (v, u.task_queue, r);
++	else if (w)
++	  free (w);
++	if (n->kind == GOMP_TASK_WAITING)
++	  {
++	    s = gomp_task_run_pre (n, q, u);
++	    if (__builtin_expect (s, 0))
++	      {
++		if (w)
++		  free (w);
++		goto finish_cancelled;
++	      }
++	    n = 0;
++	    l.in_taskgroup_wait = 1;
++	  }
++	if (w)
++	  {
++	    t->task = *n;
++	    if (__builtin_expect (p, 0))
++	      if (o)
++		t->task = *v;
++	  }
++	if (n)
++	  {
++	    struct gomp_task x = x;
++	    for (; i; b++)
++	      {
++		struct gomp_task y = j;
++		if (g)
++		  continue;
++		priority_queue_insert (PQ_CHILDREN, x);
++		if (x.taskwait.in_taskwait)
++		  priority_queue_insert2 (PQ_TASKGROUP, y, e, 0, d);
++		if (h)
++		  gomp_sem_post (f);
++		priority_queue_insert3 (k, y, PRIORITY_INSERT_END, 0, d);
++		++c;
++	      }
++	  }
++      finish_cancelled:
++	w = (struct gomp_task *) (n - u.task_running_count - v);
++      }
++  v->taskgroup = (struct gomp_taskgroup *) m;
++  return 1;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/compile/stack-check-1.c
+@@ -0,0 +1,4 @@
++/* { dg-require-effective-target untyped_assembly } */
++/* { dg-require-stack-check "" } */
++/* { dg-additional-options "-fstack-check" } */
++#include "20031023-1.c"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr37780.c
+@@ -0,0 +1,49 @@
++/* PR middle-end/37780.  */
++
++#define VAL (8 * sizeof (int))
++
++int __attribute__ ((noinline, noclone))
++fooctz (int i)
++{
++  return (i == 0) ? VAL : __builtin_ctz (i);
++}
++
++int __attribute__ ((noinline, noclone))
++fooctz2 (int i)
++{
++  return (i != 0) ? __builtin_ctz (i) : VAL;
++}
++
++unsigned int __attribute__ ((noinline, noclone))
++fooctz3 (unsigned int i)
++{
++  return (i > 0) ?  __builtin_ctz (i) : VAL;
++}
++
++int __attribute__ ((noinline, noclone))
++fooclz (int i)
++{
++  return (i == 0) ? VAL : __builtin_clz (i);
++}
++
++int __attribute__ ((noinline, noclone))
++fooclz2 (int i)
++{
++  return (i != 0) ? __builtin_clz (i) : VAL;
++}
++
++unsigned int __attribute__ ((noinline, noclone))
++fooclz3 (unsigned int i)
++{
++  return (i > 0) ? __builtin_clz (i) : VAL;
++}
++
++int
++main (void)
++{
++  if (fooctz (0) != VAL || fooctz2 (0) != VAL || fooctz3 (0) != VAL
++      || fooclz (0) != VAL || fooclz2 (0) != VAL || fooclz3 (0) != VAL)
++    __builtin_abort ();
++
++  return 0;
++}
+\ No newline at end of file
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr66940.c
+@@ -0,0 +1,20 @@
++long long __attribute__ ((noinline, noclone))
++foo (long long ival)
++{
++ if (ival <= 0)
++    return -0x7fffffffffffffffL - 1;
++
++ return 0x7fffffffffffffffL;
++}
++
++int
++main (void)
++{
++  if (foo (-1) != (-0x7fffffffffffffffL - 1))
++    __builtin_abort ();
++
++  if (foo (1) != 0x7fffffffffffffffL)
++    __builtin_abort ();
++
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.dg/asr_div1.c
++++ b/src/gcc/testsuite/gcc.dg/asr_div1.c
+@@ -1,6 +1,7 @@
+ /* Test division by const int generates only one shift.  */
+ /* { dg-do run } */
+ /* { dg-options "-O2 -fdump-rtl-combine-all" } */
++/* { dg-options "-O2 -fdump-rtl-combine-all -mtune=cortex-a53" { target aarch64*-*-* } } */
+ 
+ extern void abort (void);
+ 
+--- a/src/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
++++ b/src/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
+@@ -24,7 +24,7 @@
+ 			 | FE_OVERFLOW		\
+ 			 | FE_UNDERFLOW)
+ 
+-#if defined __alpha__
++#if defined __alpha__ || defined __aarch64__
+   #define ITER_COUNT 100
+ #else
+   #define ITER_COUNT 10000
+--- a/src/gcc/testsuite/gcc.dg/cpp/trad/include.c
++++ b/src/gcc/testsuite/gcc.dg/cpp/trad/include.c
+@@ -2,11 +2,5 @@
+ 
+ /* Test that macros are not expanded in the <> quotes of #inlcude.  */
+ 
+-/* vxWorksCommon.h uses the "#" operator to construct the name of an
+-   include file, thus making the file incompatible with -traditional-cpp.
+-   Newlib uses ## when including stdlib.h as of 2007-09-07.  */
+-/* { dg-do preprocess { target { { ! vxworks_kernel } && { ! newlib } } } } */
+-
+-#define __STDC__ 1		/* Stop complaints about non-ISO compilers.  */
+-#define stdlib 1
+-#include <stdlib.h>		/* { dg-bogus "o such file or directory" } */
++#define builtins 1
++#include <builtins.h>		/* { dg-bogus "o such file or directory" } */
+--- a/src/gcc/testsuite/gcc.dg/cpp/trad/trad.exp
++++ b/src/gcc/testsuite/gcc.dg/cpp/trad/trad.exp
+@@ -29,7 +29,7 @@ load_lib gcc-dg.exp
+ # If a testcase doesn't have special options, use these.
+ global DEFAULT_TRADCPPFLAGS
+ if ![info exists DEFAULT_TRADCPPFLAGS] then {
+-    set DEFAULT_TRADCPPFLAGS " -traditional-cpp"
++    set DEFAULT_TRADCPPFLAGS " -traditional-cpp -I$srcdir/$subdir/"
+ }
+ 
+ # Initialize `dg'.
+--- a/src/gcc/testsuite/gcc.dg/cpp/warn-undef-2.c
++++ b/src/gcc/testsuite/gcc.dg/cpp/warn-undef-2.c
+@@ -1,5 +1,5 @@
+ // { dg-do preprocess }
+ // { dg-options "-std=gnu99 -fdiagnostics-show-option -Werror=undef" }
+ /* { dg-message "some warnings being treated as errors" "" {target "*-*-*"} 0 } */
+-#if x  // { dg-error "\"x\" is not defined .-Werror=undef." }
++#if x  // { dg-error "\"x\" is not defined, evaluates to 0 .-Werror=undef." }
+ #endif
+--- a/src/gcc/testsuite/gcc.dg/cpp/warn-undef.c
++++ b/src/gcc/testsuite/gcc.dg/cpp/warn-undef.c
+@@ -1,5 +1,5 @@
+ // { dg-do preprocess }
+ // { dg-options "-std=gnu99 -fdiagnostics-show-option -Wundef" }
+ 
+-#if x  // { dg-warning "\"x\" is not defined .-Wundef." }
++#if x  // { dg-warning "\"x\" is not defined, evaluates to 0 .-Wundef." }
+ #endif
+--- a/src/gcc/testsuite/gcc.dg/graphite/run-id-pr47653.c
++++ b/src/gcc/testsuite/gcc.dg/graphite/run-id-pr47653.c
+@@ -1,3 +1,4 @@
++/* { dg-require-stack-check "generic" } */
+ /* { dg-options "-O -fstack-check=generic -ftree-pre -fgraphite-identity" } */
+ /* nvptx doesn't expose a stack.  */
+ /* { dg-skip-if "" { nvptx-*-* } { "*" } { "" } } */
+--- a/src/gcc/testsuite/gcc.dg/lto/pr54709_0.c
++++ b/src/gcc/testsuite/gcc.dg/lto/pr54709_0.c
+@@ -1,6 +1,7 @@
+ /* { dg-lto-do link } */
+ /* { dg-require-visibility "hidden" } */
+ /* { dg-require-effective-target fpic } */
++/* { dg-require-effective-target shared } */
+ /* { dg-extra-ld-options { -shared } } */
+ /* { dg-lto-options { { -fPIC -fvisibility=hidden -flto } } } */
+ 
+--- a/src/gcc/testsuite/gcc.dg/lto/pr61526_0.c
++++ b/src/gcc/testsuite/gcc.dg/lto/pr61526_0.c
+@@ -1,4 +1,5 @@
+ /* { dg-require-effective-target fpic } */
++/* { dg-require-effective-target shared } */
+ /* { dg-lto-do link } */
+ /* { dg-lto-options { { -fPIC -flto -flto-partition=1to1 } } } */
+ /* { dg-extra-ld-options { -shared } } */
+--- a/src/gcc/testsuite/gcc.dg/lto/pr64415_0.c
++++ b/src/gcc/testsuite/gcc.dg/lto/pr64415_0.c
+@@ -1,5 +1,6 @@
+ /* { dg-lto-do link } */
+ /* { dg-require-effective-target fpic } */
++/* { dg-require-effective-target shared } */
+ /* { dg-lto-options { { -O -flto -fpic } } } */
+ /* { dg-extra-ld-options { -shared } } */
+ /* { dg-extra-ld-options "-Wl,-undefined,dynamic_lookup" { target *-*-darwin* } } */
+--- a/src/gcc/testsuite/gcc.dg/plugin/plugin.exp
++++ b/src/gcc/testsuite/gcc.dg/plugin/plugin.exp
+@@ -87,6 +87,12 @@ foreach plugin_test $plugin_test_list {
+     if ![runtest_file_p $runtests $plugin_src] then {
+         continue
+     }
++    # Skip tail call tests on targets that do not have sibcall_epilogue.
++    if {[regexp ".*must_tail_call_plugin.c" $plugin_src]
++	&& [istarget arm*-*-*]
++	&& [check_effective_target_arm_thumb1]} then {
++	continue
++    }
+     set plugin_input_tests [lreplace $plugin_test 0 0]
+     plugin-test-execute $plugin_src $plugin_input_tests
+ }
+--- a/src/gcc/testsuite/gcc.dg/pr47443.c
++++ b/src/gcc/testsuite/gcc.dg/pr47443.c
+@@ -1,5 +1,6 @@
+ /* PR tree-optimization/47443 */
+ /* { dg-do compile } */
++/* { dg-require-stack-check "generic" } */
+ /* { dg-options "-O -fstack-check=generic" } */
+ 
+ static inline int bar (char *c, int i)
+--- a/src/gcc/testsuite/gcc.dg/pr48134.c
++++ b/src/gcc/testsuite/gcc.dg/pr48134.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-stack-check "specific" } */
+ /* { dg-options "-O2 -fstack-check=specific -fno-tree-dse -fno-tree-fre -fno-tree-loop-optimize -g" } */
+ 
+ struct S
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/pr59833.c
+@@ -0,0 +1,18 @@
++/* { dg-do run { target { *-*-linux* *-*-gnu* } } } */
++/* { dg-options "-O0 -lm" } */
++/* { dg-require-effective-target issignaling } */
++
++#define _GNU_SOURCE
++#include <math.h>
++
++int main (void)
++{
++  float sNaN = __builtin_nansf ("");
++  double x = (double) sNaN;
++  if (issignaling(x))
++  {
++    __builtin_abort();
++  }
++
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/pr68217.c
+@@ -0,0 +1,14 @@
++
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-vrp1" } */
++
++int foo (void)
++{
++    volatile int a = -1;
++    long long b = (1LL << (sizeof (b) * 8 - 1)); // LLONG_MIN
++    long long x = (a & b); // x == 0x8000000000000000
++    if (x < 1LL) { ; } else { __builtin_abort(); }
++    return 0;
++}
++
++/* { dg-final { scan-tree-dump "\\\[-INF, 0\\\]" "vrp1" } } */
+--- a/src/gcc/testsuite/gcc.dg/pr70017.c
++++ b/src/gcc/testsuite/gcc.dg/pr70017.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-stack-check "generic" } */
+ /* { dg-options "-fstack-check=generic" } */
+ 
+ /* Check that the expected warning is issued for large frames.  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/pr71636-1.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-options "-fdump-tree-gimple" } */
++
++unsigned f(unsigned x, unsigned b)
++{
++  return x & ((1U << b) - 1);
++}
++
++/* { dg-final { scan-tree-dump-not "1 <<" "gimple" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/pr71636-2.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-forwprop-details" } */
++
++unsigned f(unsigned x, unsigned b)
++{
++  unsigned t1 = 1U << b;
++  unsigned t2 = t1 - 1;
++  unsigned t3 = x & t2;
++  return t3;
++}
++
++/* { dg-final { scan-tree-dump "_\[0-9\] = ~_\[0-9\]" "forwprop1" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-20.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-20.c
+@@ -86,9 +86,9 @@ main ()
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 2 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 4 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-21.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-21.c
+@@ -57,9 +57,9 @@ main ()
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 2 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 3 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-22.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-22.c
+@@ -31,9 +31,9 @@ main ()
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 3 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 4 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-22g.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-22g.c
+@@ -5,9 +5,9 @@
+ #define USE_GNU
+ #include "strlenopt-22.c"
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 0 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 1 "strlen" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-26.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-26.c
+@@ -21,4 +21,5 @@ main (void)
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 2 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-5.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-5.c
+@@ -48,9 +48,9 @@ main ()
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 0 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 2 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 2 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 2 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-7.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-7.c
+@@ -40,11 +40,11 @@ main ()
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 0 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 2 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 1 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "\\*r_\[0-9\]* = 0;" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "return 3;" 1 "optimized" } } */
+--- a/src/gcc/testsuite/gcc.dg/strlenopt-9.c
++++ b/src/gcc/testsuite/gcc.dg/strlenopt-9.c
+@@ -98,10 +98,10 @@ main ()
+   return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump-times "strlen \\(" 3 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strlen \\(" 5 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "memcpy \\(" 6 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */
+-/* { dg-final { scan-tree-dump-times "strchr \\(" 3 "strlen" } } */
++/* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */
+ /* { dg-final { scan-tree-dump-times "return 4;" 1 "optimized" } } */
+--- a/src/gcc/testsuite/gcc.dg/torture/arm-fp16-int-convert-alt.c
++++ b/src/gcc/testsuite/gcc.dg/torture/arm-fp16-int-convert-alt.c
+@@ -1,5 +1,6 @@
+ /* Test floating-point conversions.  Standard types and __fp16.  */
+ /* { dg-do run { target arm*-*-* } } */
++/* { dg-require-effective-target arm_fp16_alternative_ok }
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ #include "fp-int-convert.h"
+--- a/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c
++++ b/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c
+@@ -1,5 +1,6 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do run { target arm*-*-* } } */
++/* { dg-require-effective-target arm_fp16_alternative_ok }
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ #include "arm-fp16-ops.h"
+--- a/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c
++++ b/src/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c
+@@ -1,5 +1,6 @@
+ /* Test various operators on __fp16 and mixed __fp16/float operands.  */
+ /* { dg-do run { target arm*-*-* } } */
++/* { dg-require-effective-target arm_fp16_alternative_ok }
+ /* { dg-options "-mfp16-format=alternative -ffast-math" } */
+ 
+ #include "arm-fp16-ops.h"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/torture/pr71594.c
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-options "--param max-rtl-if-conversion-insns=2" } */
++
++unsigned short a;
++int b, c;
++int *d;
++void fn1() {
++  *d = 24;
++  for (; *d <= 65;) {
++    unsigned short *e = &a;
++    b = (a &= 0 <= 0) < (c ?: (*e %= *d));
++    for (; *d <= 83;)
++      ;
++  }
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr61839_1.c
+@@ -0,0 +1,44 @@
++/* PR tree-optimization/61839.  */
++/* { dg-do run } */
++/* { dg-options "-O2 -fdump-tree-vrp1 -fdump-tree-optimized" } */
++/* { dg-require-effective-target int32plus } */
++
++__attribute__ ((noinline))
++int foo ()
++{
++  int a = -1;
++  volatile unsigned b = 1U;
++  int c = 1;
++  c = (a + 972195718) >> (1LU <= b);
++  if (c == 486097858)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++__attribute__ ((noinline))
++int bar ()
++{
++  int a = -1;
++  volatile unsigned b = 1U;
++  int c = 1;
++  c = (a + 972195718) >> (b ? 2 : 3);
++  if (c == 243048929)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++int main ()
++{
++  foo ();
++  bar ();
++}
++
++/* Scan for c = 972195717) >> [0, 1] in function foo.  */
++/* { dg-final { scan-tree-dump-times "486097858 : 972195717" 1  "vrp1" } } */
++/* Scan for c = 972195717) >> [2, 3] in function bar.  */
++/* { dg-final { scan-tree-dump-times "243048929 : 121524464" 2  "vrp1" } } */
++/* { dg-final { scan-tree-dump-times "486097858" 0  "optimized" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr61839_2.c
+@@ -0,0 +1,54 @@
++/* PR tree-optimization/61839.  */
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-vrp1" } */
++/* { dg-require-effective-target int32plus } */
++
++__attribute__ ((noinline))
++int foo ()
++{
++  int a = -1;
++  volatile unsigned b = 1U;
++  int c = 1;
++  c = (a + 972195718) / (b ? 1 : 0);
++  if (c == 972195717)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++__attribute__ ((noinline))
++int bar ()
++{
++  int a = -1;
++  volatile unsigned b = 1U;
++  int c = 1;
++  c = (a + 972195718) % (b ? 1 : 0);
++  if (c == 972195717)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++__attribute__ ((noinline))
++int bar2 ()
++{
++  int a = -1;
++  volatile unsigned b = 1U;
++  int c = 1;
++  c = (a + 972195716) % (b ? 1 : 2);
++  if (c == 972195715)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++
++/* Dont optimize 972195717 / 0 in function foo.  */
++/* { dg-final { scan-tree-dump-times "972195717 / _" 1  "vrp1" } } */
++/* Dont optimize 972195717 % 0 in function bar.  */
++/* { dg-final { scan-tree-dump-times "972195717 % _" 1 "vrp1" } } */
++/* Optimize in function bar2.  */
++/* { dg-final { scan-tree-dump-times "972195715 % _" 0 "vrp1" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr61839_3.c
+@@ -0,0 +1,26 @@
++/* PR tree-optimization/61839.  */
++/* { dg-do run } */
++/* { dg-options "-O2 -fdump-tree-vrp1 -fdump-tree-optimized" } */
++
++__attribute__ ((noinline))
++int foo (int a, unsigned b)
++{
++  int c = 1;
++  b =  a ? 12 : 13;
++  c = b << 8;
++  if (c == 3072)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++int main ()
++{
++  volatile unsigned b = 1U;
++  foo (-1, b);
++}
++
++/* Scan for c [12, 13] << 8 in function foo.  */
++/* { dg-final { scan-tree-dump-times "3072 : 3328" 2  "vrp1" } } */
++/* { dg-final { scan-tree-dump-times "3072" 0  "optimized" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr61839_4.c
+@@ -0,0 +1,28 @@
++/* PR tree-optimization/61839.  */
++/* { dg-do run } */
++/* { dg-options "-O2 -fdump-tree-vrp1 -fdump-tree-optimized" } */
++/* { dg-require-effective-target int32plus } */
++
++__attribute__ ((noinline))
++int foo (int a, unsigned b)
++{
++  unsigned c = 1;
++  if (b >= 1 && b <= ((unsigned)(-1) - 1))
++    return 0;
++  c = b >> 4;
++  if (c == 268435455)
++    ;
++  else
++    __builtin_abort ();
++  return 0;
++}
++
++int main ()
++{
++  volatile unsigned b = (unsigned)(-1);
++  foo (-1, b);
++}
++
++/* Scan for ~[1, 4294967294] >> 4 in function foo.  */
++/* { dg-final { scan-tree-dump-times "0 : 268435455" 1  "vrp1" } } */
++/* { dg-final { scan-tree-dump-times "268435455" 0  "optimized" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/scev-11.c
+@@ -0,0 +1,28 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
++
++int a[128];
++extern int b[];
++
++int bar (int *);
++
++int
++foo (int n)
++{
++  int i;
++
++  for (i = 0; i < n; i++)
++    {
++      unsigned char uc = (unsigned char)i;
++      a[i] = i;
++      b[uc] = 0;
++    }
++
++  bar (a);
++  return 0;
++}
++
++/* Address of array reference to b is scev.  */
++/* { dg-final { scan-tree-dump-times "use \[0-9\]\n  address" 2 "ivopts" } } */
++
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/scev-12.c
+@@ -0,0 +1,30 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
++
++int a[128];
++extern int b[];
++
++int bar (int *);
++
++int
++foo (int x, int n)
++{
++  int i;
++
++  for (i = 0; i < n; i++)
++    {
++      unsigned char uc = (unsigned char)i;
++      if (x)
++	a[i] = i;
++      b[uc] = 0;
++    }
++
++  bar (a);
++  return 0;
++}
++
++/* Address of array reference to b is not scev.  */
++/* { dg-final { scan-tree-dump-times "use \[0-9\]\n  address" 1 "ivopts" } } */
++
++
++
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-2.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-2.c
+@@ -25,6 +25,7 @@ f1 (int i, ...)
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units and 0 FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units and 0 FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -45,6 +46,7 @@ f2 (int i, ...)
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save \[148\] GPR units and 0 FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save 8 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save 1 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save 8 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -60,6 +62,7 @@ f3 (int i, ...)
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 0 GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 0 GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 0 GPR units and 1 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 0 GPR units and 16 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 8 GPR units and 2" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save \[1-9\]\[0-9\]* GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save \[1-9\]\[0-9\]* GPR units" "stdarg" { target ia64-*-* } } } */
+@@ -78,6 +81,7 @@ f4 (int i, ...)
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -96,6 +100,7 @@ f5 (int i, ...)
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -116,6 +121,7 @@ f6 (int i, ...)
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save (3|12|24) GPR units and 0 FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save 24 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save 3 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save 24 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save (3|12|24) GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save (3|12|24) GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save (3|12|24) GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -133,6 +139,7 @@ f7 (int i, ...)
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -152,6 +159,7 @@ f8 (int i, ...)
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -169,6 +177,7 @@ f9 (int i, ...)
+ /* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f9: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -188,6 +197,7 @@ f10 (int i, ...)
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -208,6 +218,7 @@ f11 (int i, ...)
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save (3|12|24) GPR units and 0 FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save 24 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save 3 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save 24 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save (3|12|24) GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save (3|12|24) GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 0, needs to save (3|12|24) GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -228,6 +239,7 @@ f12 (int i, ...)
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save 0 GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save 24 GPR units and 2" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save 0 GPR units and 3 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save 0 GPR units and 48 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -248,6 +260,7 @@ f13 (int i, ...)
+ /* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save 0 GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save 24 GPR units and 2" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save 0 GPR units and 3 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save 0 GPR units and 48 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f13: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -268,6 +281,7 @@ f14 (int i, ...)
+ /* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save \[148\] GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save 24 GPR units and 3" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save 1 GPR units and 2 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save 8 GPR units and 32 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f14: va_list escapes 0, needs to save \[1-9]\[0-9\]* GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -291,6 +305,7 @@ f15 (int i, ...)
+ /* { dg-final { scan-tree-dump "f15: va_list escapes 0, needs to save \[148\] GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f15: va_list escapes 0, needs to save \[148\] GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f15: va_list escapes 0, needs to save 1 GPR units and 2 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f15: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ /* We may be able to improve upon this after fixing PR66010/PR66013.  */
+ /* { dg-final { scan-tree-dump "f15: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-3.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-3.c
+@@ -24,6 +24,7 @@ f1 (int i, ...)
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -39,6 +40,7 @@ f2 (int i, ...)
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -57,6 +59,7 @@ f3 (int i, ...)
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -73,6 +76,7 @@ f4 (int i, ...)
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -89,6 +93,7 @@ f5 (int i, ...)
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -107,6 +112,7 @@ f6 (int i, ...)
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -123,6 +129,7 @@ f7 (int i, ...)
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -139,6 +146,7 @@ f8 (int i, ...)
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f8: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -155,6 +163,7 @@ f10 (int i, ...)
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f10: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -171,6 +180,7 @@ f11 (int i, ...)
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f11: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -187,6 +197,7 @@ f12 (int i, ...)
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f12: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-4.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-4.c
+@@ -27,6 +27,7 @@ f1 (int i, ...)
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes \[01\], needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes \[01\], needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes \[01\], needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -44,6 +45,7 @@ f2 (int i, ...)
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save 0 GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save all GPR units and 2" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save 0 GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save 0 GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes \[01\], needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes \[01\], needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes \[01\], needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -67,6 +69,7 @@ f3 (int i, ...)
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save \[148\] GPR units and 0 FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 8 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 1 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 8 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+@@ -88,6 +91,7 @@ f4 (int i, ...)
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 0 GPR units and \[1-9\]\[0-9\]* FPR units" "stdarg" { target { powerpc*-*-linux* && { powerpc_fprs && ilp32 } } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 8 GPR units and 2" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 0 GPR units and 1 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 0 GPR units and 16 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save \[148\] GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-5.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-5.c
+@@ -25,6 +25,7 @@ f1 (int i, ...)
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save 0 GPR units and 0 FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f1: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ void
+ f2 (int i, ...)
+@@ -38,6 +39,7 @@ f2 (int i, ...)
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save all GPR units and all FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save all GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f2: va_list escapes 0, needs to save all GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ /* Here va_arg can be executed at most as many times as va_start.  */
+ void
+@@ -56,6 +58,7 @@ f3 (int i, ...)
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 0 GPR units and 0 FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 32 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 1 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f3: va_list escapes 0, needs to save 8 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ void
+ f4 (int i, ...)
+@@ -74,6 +77,7 @@ f4 (int i, ...)
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 16 GPR units and 16 FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 24 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 2 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f4: va_list escapes 0, needs to save 24 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ void
+ f5 (int i, ...)
+@@ -88,6 +92,7 @@ f5 (int i, ...)
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 0, needs to save 16 GPR units and 0 FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 0, needs to save 32 GPR units and 1" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f5: va_list escapes 0, needs to save (4|2) GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f5: va_list escapes 0, needs to save 16 GPR units and 0 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ void
+ f6 (int i, ...)
+@@ -102,6 +107,7 @@ f6 (int i, ...)
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save 8 GPR units and 32 FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save 32 GPR units and 3" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save (3|2) GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f6: va_list escapes 0, needs to save 8 GPR units and 32 FPR units" "stdarg" { target aarch64*-*-* } } } */
+ 
+ void
+ f7 (int i, ...)
+@@ -116,3 +122,4 @@ f7 (int i, ...)
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 0, needs to save 0 GPR units and 64 FPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && { ! { ia32 || llp64 } } } } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 0, needs to save 32 GPR units and 2" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "f7: va_list escapes 0, needs to save 2 GPR units and 0 FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "f7: va_list escapes 0, needs to save 0 GPR units and 64 FPR units" "stdarg" { target aarch64*-*-* } } } */
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-6.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/stdarg-6.c
+@@ -30,6 +30,7 @@ bar (int x, char const *y, ...)
+ /* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target { powerpc*-*-linux* && ilp32 } } } } */
+ /* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target alpha*-*-linux* } } } */
+ /* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target s390*-*-linux* } } } */
++/* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units and all FPR units" "stdarg" { target aarch64*-*-* } } } */
+ /* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
+ /* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
+ /* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+--- a/src/gcc/testsuite/gcc.dg/uninit-pred-8_a.c
++++ b/src/gcc/testsuite/gcc.dg/uninit-pred-8_a.c
+@@ -1,6 +1,8 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-options "-Wuninitialized -O2" } */
++/* Pick a particular tuning to pin down BRANCH_COST.  */
++/* { dg-additional-options "-mtune=cortex-a15" { target arm*-*-* } } */
+ 
+ int g;
+ void bar();
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/aligned-section-anchors-vect-70.c
+@@ -0,0 +1,33 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target section_anchors } */
++/* { dg-require-effective-target vect_int } */
++
++#define N 32
++
++/* Increase alignment of struct if an array's offset is multiple of alignment of
++   vector type corresponding to it's scalar type.
++   For the below test-case:
++   offsetof(e) == 8 bytes. 
++   i) For arm: let x = alignment of vector type corresponding to int,
++   x == 8 bytes.
++   Since offsetof(e) % x == 0, set DECL_ALIGN(a, b, c) to x.
++   ii) For aarch64, ppc: x == 16 bytes.
++   Since offsetof(e) % x != 0, don't increase alignment of a, b, c.
++*/
++
++static struct A {
++  int p1, p2;
++  int e[N];
++} a, b, c;
++
++int foo(void)
++{
++  for (int i = 0; i < N; i++)
++    a.e[i] = b.e[i] + c.e[i];
++
++   return a.e[0];
++}
++
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target aarch64*-*-* } } } */
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target powerpc64*-*-* } } } */
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 3 "increase_alignment" { target arm*-*-* } } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/aligned-section-anchors-vect-71.c
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target section_anchors } */
++/* { dg-require-effective-target vect_int } */
++
++/* Should not increase alignment of the struct because
++   sizeof (A.e) < sizeof(corresponding vector type).  */
++
++#define N 3
++
++static struct A {
++  int p1, p2;
++  int e[N];
++} a, b, c;
++
++int foo(void)
++{
++  for (int i = 0; i < N; i++)
++    a.e[i] = b.e[i] + c.e[i];
++
++   return a.e[0];
++}
++
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target aarch64*-*-* } } } */
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target powerpc64*-*-* } } } */
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target arm*-*-* } } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/aligned-section-anchors-vect-72.c
+@@ -0,0 +1,29 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target section_anchors } */
++/* { dg-require-effective-target vect_int } */
++
++#define N 32
++
++/* Clone of section-anchors-vect-70.c having nested struct.  */
++
++struct S
++{
++  int e[N];
++};
++
++static struct A {
++  int p1, p2;
++  struct S s; 
++} a, b, c;
++
++int foo(void)
++{
++  for (int i = 0; i < N; i++)
++    a.s.e[i] = b.s.e[i] + c.s.e[i];
++
++   return a.s.e[0];
++}
++
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target aarch64*-*-* } } } */
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 0 "increase_alignment" { target powerpc64*-*-* } } } */
++/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 3 "increase_alignment" { target arm*-*-* } } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/pr57206.c
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target vect_float } */
++
++void bad0(float * d, unsigned int n)
++{
++  unsigned int i;
++  for (i=n; i>0; --i) 
++    d[n-i] = 0.0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/pr65951.c
+@@ -0,0 +1,63 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 512
++
++/* These multiplications should be vectorizable with additions when
++   no vector shift is available.  */
++
++__attribute__ ((noinline)) void
++foo (int *arr)
++{
++  for (int i = 0; i < N; i++)
++    arr[i] *= 2;
++}
++
++__attribute__ ((noinline)) void
++foo2 (int *arr)
++{
++  for (int i = 0; i < N; i++)
++    arr[i] *= 4;
++}
++
++int
++main (void)
++{
++  check_vect ();
++  int data[N];
++  int i;
++
++  for (i = 0; i < N; i++)
++    {
++      data[i] = i;
++      __asm__ volatile ("");
++    }
++
++  foo (data);
++  for (i = 0; i < N; i++)
++    {
++      if (data[i] / 2 != i)
++      __builtin_abort ();
++      __asm__ volatile ("");
++    }
++
++  for (i = 0; i < N; i++)
++    {
++      data[i] = i;
++      __asm__ volatile ("");
++    }
++
++  foo2 (data);
++  for (i = 0; i < N; i++)
++    {
++      if (data[i] / 4 != i)
++      __builtin_abort ();
++      __asm__ volatile ("");
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/pr71818.c
+@@ -0,0 +1,16 @@
++/* { dg-do compile } */
++
++char a;
++short b;
++int c, d;
++void fn1() {
++  char e = 75, g;
++  unsigned char *f = &e;
++  a = 21;
++  for (; a <= 48; a++) {
++    for (; e <= 6;)
++      ;
++    g -= e -= b || g <= c;
++  }
++  d = *f;
++}
+--- a/src/gcc/testsuite/gcc.dg/vect/vect-iv-9.c
++++ b/src/gcc/testsuite/gcc.dg/vect/vect-iv-9.c
+@@ -33,5 +33,4 @@ int main (void)
+   return 0;
+ } 
+ 
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_int_mult } } } */
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {! vect_int_mult } } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/vect-load-lanes-peeling-1.c
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target vect_int } */
++/* { dg-require-effective-target vect_load_lanes } */
++
++void
++f (int *__restrict a, int *__restrict b)
++{
++  for (int i = 0; i < 96; ++i)
++    a[i] = b[i * 3] + b[i * 3 + 1] + b[i * 3 + 2];
++}
++
++/* { dg-final { scan-tree-dump-not "Data access with gaps" "vect" } } */
++/* { dg-final { scan-tree-dump-not "epilog loop required" "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-1.c
+@@ -0,0 +1,41 @@
++/* { dg-require-effective-target vect_int } */
++/* { dg-require-effective-target vect_shift } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 256
++
++__attribute__ ((noinline)) void
++foo (long long *arr)
++{
++  for (int i = 0; i < N; i++)
++    arr[i] *= 123;
++}
++
++int
++main (void)
++{
++  check_vect ();
++  long long data[N];
++  int i;
++
++  for (i = 0; i < N; i++)
++    {
++      data[i] = i;
++      __asm__ volatile ("");
++    }
++
++  foo (data);
++  for (i = 0; i < N; i++)
++    {
++      if (data[i] / 123 != i)
++      __builtin_abort ();
++      __asm__ volatile ("");
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect"  { target aarch64*-*-* } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target aarch64*-*-* } } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-2.c
+@@ -0,0 +1,40 @@
++/* { dg-require-effective-target vect_int } */
++
++#include <stdarg.h>
++#include "tree-vect.h"
++
++#define N 256
++
++__attribute__ ((noinline)) void
++foo (long long *arr)
++{
++  for (int i = 0; i < N; i++)
++    arr[i] *= -19594LL;
++}
++
++int
++main (void)
++{
++  check_vect ();
++  long long data[N];
++  int i;
++
++  for (i = 0; i < N; i++)
++    {
++      data[i] = i;
++      __asm__ volatile ("");
++    }
++
++  foo (data);
++  for (i = 0; i < N; i++)
++    {
++      if (data[i] / -19594LL != i)
++      __builtin_abort ();
++      __asm__ volatile ("");
++    }
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect"  { target aarch64*-*-* } } } */
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target aarch64*-*-* } } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp
+@@ -53,7 +53,10 @@ torture-init
+ set-torture-options $C_TORTURE_OPTIONS {{}} $LTO_TORTURE_OPTIONS
+ 
+ # Make sure Neon flags are provided, if necessary.  Use fp16 if we can.
+-if {[check_effective_target_arm_neon_fp16_ok]} then {
++# Use fp16 arithmetic operations if the hardware supports it.
++if {[check_effective_target_arm_v8_2a_fp16_neon_hw]} then {
++  set additional_flags [add_options_for_arm_v8_2a_fp16_neon ""]
++} elseif {[check_effective_target_arm_neon_fp16_ok]} then {
+   set additional_flags [add_options_for_arm_neon_fp16 ""]
+ } else {
+   set additional_flags [add_options_for_arm_neon ""]
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
+@@ -16,6 +16,14 @@ extern void *memset(void *, int, size_t);
+ extern void *memcpy(void *, const void *, size_t);
+ extern size_t strlen(const char *);
+ 
++/* Helper macro to select FP16 tests.  */
++#if (defined (__ARM_FP16_FORMAT_IEEE) \
++     || defined (__ARM_FP16_FORMAT_ALTERNATIVE))
++#define FP16_SUPPORTED (1)
++#else
++#undef FP16_SUPPORTED
++#endif
++
+ /* Various string construction helpers.  */
+ 
+ /*
+@@ -24,6 +32,13 @@ extern size_t strlen(const char *);
+    VECT_VAR(expected, int, 16, 4) -> expected_int16x4
+    VECT_VAR_DECL(expected, int, 16, 4) -> int16x4_t expected_int16x4
+ */
++/* Some instructions don't exist on ARM.
++   Use this macro to guard against them.  */
++#ifdef __aarch64__
++#define AARCH64_ONLY(X) X
++#else
++#define AARCH64_ONLY(X)
++#endif
+ 
+ #define xSTR(X) #X
+ #define STR(X) xSTR(X)
+@@ -81,7 +96,7 @@ extern size_t strlen(const char *);
+ 	  abort();							\
+ 	}								\
+       }									\
+-    fprintf(stderr, "CHECKED %s\n", MSG);				\
++    fprintf(stderr, "CHECKED %s %s\n", STR(VECT_TYPE(T, W, N)), MSG);	\
+   }
+ 
+ /* Floating-point variant.  */
+@@ -110,7 +125,36 @@ extern size_t strlen(const char *);
+ 	  abort();							\
+ 	}								\
+       }									\
+-    fprintf(stderr, "CHECKED %s\n", MSG);				\
++    fprintf(stderr, "CHECKED %s %s\n", STR(VECT_TYPE(T, W, N)), MSG);	\
++  }
++
++/* poly variant.  */
++#define CHECK_POLY(MSG,T,W,N,FMT,EXPECTED,COMMENT)			\
++  {									\
++    int i;								\
++    for(i=0; i<N ; i++)							\
++      {									\
++	union poly_operand {						\
++	  uint##W##_t i;						\
++	  poly##W##_t p;						\
++	} tmp_res, tmp_exp;						\
++	tmp_res.p = VECT_VAR(result, T, W, N)[i];			\
++	tmp_exp.i = VECT_VAR(EXPECTED, T, W, N)[i];			\
++	if (tmp_res.i != tmp_exp.i) {					\
++	  fprintf(stderr,						\
++		  "ERROR in %s (%s line %d in buffer '%s') at type %s "	\
++		  "index %d: got 0x%" FMT " != 0x%" FMT " %s\n",	\
++		  MSG, __FILE__, __LINE__,				\
++		  STR(EXPECTED),					\
++		  STR(VECT_NAME(T, W, N)),				\
++		  i,							\
++		  tmp_res.i,						\
++		  tmp_exp.i,						\
++		  strlen(COMMENT) > 0 ? COMMENT : "");			\
++	  abort();							\
++	}								\
++      }									\
++    fprintf(stderr, "CHECKED %s %s\n", STR(VECT_TYPE(T, W, N)), MSG);	\
+   }
+ 
+ /* Clean buffer with a non-zero pattern to help diagnose buffer
+@@ -133,10 +177,16 @@ static ARRAY(result, uint, 32, 2);
+ static ARRAY(result, uint, 64, 1);
+ static ARRAY(result, poly, 8, 8);
+ static ARRAY(result, poly, 16, 4);
++#if defined (__ARM_FEATURE_CRYPTO)
++static ARRAY(result, poly, 64, 1);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ static ARRAY(result, float, 16, 4);
+ #endif
+ static ARRAY(result, float, 32, 2);
++#ifdef __aarch64__
++static ARRAY(result, float, 64, 1);
++#endif
+ static ARRAY(result, int, 8, 16);
+ static ARRAY(result, int, 16, 8);
+ static ARRAY(result, int, 32, 4);
+@@ -147,6 +197,9 @@ static ARRAY(result, uint, 32, 4);
+ static ARRAY(result, uint, 64, 2);
+ static ARRAY(result, poly, 8, 16);
+ static ARRAY(result, poly, 16, 8);
++#if defined (__ARM_FEATURE_CRYPTO)
++static ARRAY(result, poly, 64, 2);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ static ARRAY(result, float, 16, 8);
+ #endif
+@@ -169,6 +222,7 @@ extern ARRAY(expected, poly, 8, 8);
+ extern ARRAY(expected, poly, 16, 4);
+ extern ARRAY(expected, hfloat, 16, 4);
+ extern ARRAY(expected, hfloat, 32, 2);
++extern ARRAY(expected, hfloat, 64, 1);
+ extern ARRAY(expected, int, 8, 16);
+ extern ARRAY(expected, int, 16, 8);
+ extern ARRAY(expected, int, 32, 4);
+@@ -193,8 +247,8 @@ extern ARRAY(expected, hfloat, 64, 2);
+     CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment);		\
+     CHECK(test_name, uint, 64, 1, PRIx64, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);	\
++    CHECK_POLY(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment);	\
+ 									\
+     CHECK(test_name, int, 8, 16, PRIx8, EXPECTED, comment);		\
+@@ -205,8 +259,8 @@ extern ARRAY(expected, hfloat, 64, 2);
+     CHECK(test_name, uint, 16, 8, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 4, PRIx32, EXPECTED, comment);		\
+     CHECK(test_name, uint, 64, 2, PRIx64, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 16, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 16, PRIx8, EXPECTED, comment);	\
++    CHECK_POLY(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment);	\
+   }									\
+ 
+@@ -335,7 +389,8 @@ extern int VECT_VAR(expected_cumulative_sat, uint, 64, 2);
+ 	      strlen(COMMENT) > 0 ? " " COMMENT : "");			\
+       abort();								\
+     }									\
+-    fprintf(stderr, "CHECKED CUMULATIVE SAT %s\n", MSG);		\
++    fprintf(stderr, "CHECKED CUMULATIVE SAT %s %s\n",			\
++	    STR(VECT_TYPE(T, W, N)), MSG);				\
+   }
+ 
+ #define CHECK_CUMULATIVE_SAT_NAMED(test_name,EXPECTED,comment)		\
+@@ -379,6 +434,9 @@ static void clean_results (void)
+   CLEAN(result, uint, 64, 1);
+   CLEAN(result, poly, 8, 8);
+   CLEAN(result, poly, 16, 4);
++#if defined (__ARM_FEATURE_CRYPTO)
++  CLEAN(result, poly, 64, 1);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+   CLEAN(result, float, 16, 4);
+ #endif
+@@ -394,6 +452,9 @@ static void clean_results (void)
+   CLEAN(result, uint, 64, 2);
+   CLEAN(result, poly, 8, 16);
+   CLEAN(result, poly, 16, 8);
++#if defined (__ARM_FEATURE_CRYPTO)
++  CLEAN(result, poly, 64, 2);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+   CLEAN(result, float, 16, 8);
+ #endif
+@@ -419,6 +480,13 @@ static void clean_results (void)
+ #define DECL_VARIABLE(VAR, T1, W, N)		\
+   VECT_TYPE(T1, W, N) VECT_VAR(VAR, T1, W, N)
+ 
++#if defined (__ARM_FEATURE_CRYPTO)
++#define DECL_VARIABLE_CRYPTO(VAR, T1, W, N) \
++  DECL_VARIABLE(VAR, T1, W, N)
++#else
++#define DECL_VARIABLE_CRYPTO(VAR, T1, W, N)
++#endif
++
+ /* Declare only 64 bits signed variants.  */
+ #define DECL_VARIABLE_64BITS_SIGNED_VARIANTS(VAR)	\
+   DECL_VARIABLE(VAR, int, 8, 8);			\
+@@ -454,6 +522,7 @@ static void clean_results (void)
+   DECL_VARIABLE_64BITS_UNSIGNED_VARIANTS(VAR);	\
+   DECL_VARIABLE(VAR, poly, 8, 8);		\
+   DECL_VARIABLE(VAR, poly, 16, 4);		\
++  DECL_VARIABLE_CRYPTO(VAR, poly, 64, 1);	\
+   DECL_VARIABLE(VAR, float, 16, 4);		\
+   DECL_VARIABLE(VAR, float, 32, 2)
+ #else
+@@ -462,6 +531,7 @@ static void clean_results (void)
+   DECL_VARIABLE_64BITS_UNSIGNED_VARIANTS(VAR);	\
+   DECL_VARIABLE(VAR, poly, 8, 8);		\
+   DECL_VARIABLE(VAR, poly, 16, 4);		\
++  DECL_VARIABLE_CRYPTO(VAR, poly, 64, 1);	\
+   DECL_VARIABLE(VAR, float, 32, 2)
+ #endif
+ 
+@@ -472,6 +542,7 @@ static void clean_results (void)
+   DECL_VARIABLE_128BITS_UNSIGNED_VARIANTS(VAR);	\
+   DECL_VARIABLE(VAR, poly, 8, 16);		\
+   DECL_VARIABLE(VAR, poly, 16, 8);		\
++  DECL_VARIABLE_CRYPTO(VAR, poly, 64, 2);	\
+   DECL_VARIABLE(VAR, float, 16, 8);		\
+   DECL_VARIABLE(VAR, float, 32, 4)
+ #else
+@@ -480,6 +551,7 @@ static void clean_results (void)
+   DECL_VARIABLE_128BITS_UNSIGNED_VARIANTS(VAR);	\
+   DECL_VARIABLE(VAR, poly, 8, 16);		\
+   DECL_VARIABLE(VAR, poly, 16, 8);		\
++  DECL_VARIABLE_CRYPTO(VAR, poly, 64, 2);	\
+   DECL_VARIABLE(VAR, float, 32, 4)
+ #endif
+ /* Declare all variants.  */
+@@ -500,15 +572,6 @@ static void clean_results (void)
+ /* Helpers to initialize vectors.  */
+ #define VDUP(VAR, Q, T1, T2, W, N, V)			\
+   VECT_VAR(VAR, T1, W, N) = vdup##Q##_n_##T2##W(V)
+-#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+-/* Work around that there is no vdup_n_f16 intrinsic.  */
+-#define vdup_n_f16(VAL)		\
+-  __extension__			\
+-    ({				\
+-      float16_t f = VAL;	\
+-      vld1_dup_f16(&f);		\
+-    })
+-#endif
+ 
+ #define VSET_LANE(VAR, Q, T1, T2, W, N, L, V)				\
+   VECT_VAR(VAR, T1, W, N) = vset##Q##_lane_##T2##W(V,			\
+@@ -521,6 +584,13 @@ static void clean_results (void)
+ 
+ /* Helpers to call macros with 1 constant and 5 variable
+    arguments.  */
++#if defined (__ARM_FEATURE_CRYPTO)
++#define MACRO_CRYPTO(MACRO, VAR1, VAR2, T1, T2, T3, W, N) \
++  MACRO(VAR1, VAR2, T1, T2, T3, W, N)
++#else
++#define MACRO_CRYPTO(MACRO, VAR1, VAR2, T1, T2, T3, W, N)
++#endif
++
+ #define TEST_MACRO_64BITS_SIGNED_VARIANTS_1_5(MACRO, VAR)	\
+   MACRO(VAR, , int, s, 8, 8);					\
+   MACRO(VAR, , int, s, 16, 4);					\
+@@ -591,13 +661,15 @@ static void clean_results (void)
+   TEST_MACRO_64BITS_SIGNED_VARIANTS_2_5(MACRO, VAR1, VAR2);	\
+   TEST_MACRO_64BITS_UNSIGNED_VARIANTS_2_5(MACRO, VAR1, VAR2);	\
+   MACRO(VAR1, VAR2, , poly, p, 8, 8);				\
+-  MACRO(VAR1, VAR2, , poly, p, 16, 4)
++  MACRO(VAR1, VAR2, , poly, p, 16, 4);				\
++  MACRO_CRYPTO(MACRO, VAR1, VAR2, , poly, p, 64, 1)
+ 
+ #define TEST_MACRO_128BITS_VARIANTS_2_5(MACRO, VAR1, VAR2)	\
+   TEST_MACRO_128BITS_SIGNED_VARIANTS_2_5(MACRO, VAR1, VAR2);	\
+   TEST_MACRO_128BITS_UNSIGNED_VARIANTS_2_5(MACRO, VAR1, VAR2);	\
+   MACRO(VAR1, VAR2, q, poly, p, 8, 16);				\
+-  MACRO(VAR1, VAR2, q, poly, p, 16, 8)
++  MACRO(VAR1, VAR2, q, poly, p, 16, 8);				\
++  MACRO_CRYPTO(MACRO, VAR1, VAR2, q, poly, p, 64, 2)
+ 
+ #define TEST_MACRO_ALL_VARIANTS_2_5(MACRO, VAR1, VAR2)	\
+   TEST_MACRO_64BITS_VARIANTS_2_5(MACRO, VAR1, VAR2);	\
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_float.inc
+@@ -0,0 +1,170 @@
++/* Floating-point only version of binary_op_no64.inc template.  Currently only
++   float16_t is used.  */
++
++#include <math.h>
++
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1(NAME)
++
++void FNNAME (INSN_NAME) (void)
++{
++  int i;
++
++  /* Basic test: z = INSN (x, y), then store the result.  */
++#define TEST_BINARY_OP1(INSN, Q, T1, T2, W, N)				\
++  VECT_VAR(vector_res, T1, W, N) =					\
++    INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N),			\
++		      VECT_VAR(vector2, T1, W, N));			\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
++
++#define TEST_BINARY_OP(INSN, Q, T1, T2, W, N)   \
++  TEST_BINARY_OP1(INSN, Q, T1, T2, W, N)	\
++
++#ifdef HAS_FLOAT16_VARIANT
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 4);
++
++  DECL_VARIABLE(vector, float, 16, 8);
++  DECL_VARIABLE(vector2, float, 16, 8);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++
++#ifdef HAS_FLOAT_VARIANT
++  DECL_VARIABLE(vector, float, 32, 2);
++  DECL_VARIABLE(vector2, float, 32, 2);
++  DECL_VARIABLE(vector_res, float, 32, 2);
++
++  DECL_VARIABLE(vector, float, 32, 4);
++  DECL_VARIABLE(vector2, float, 32, 4);
++  DECL_VARIABLE(vector_res, float, 32, 4);
++#endif
++
++  clean_results ();
++
++  /* Initialize input "vector" from "buffer".  */
++#ifdef HAS_FLOAT16_VARIANT
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
++#ifdef HAS_FLOAT_VARIANT
++  VLOAD(vector, buffer, , float, f, 32, 2);
++  VLOAD(vector, buffer, q, float, f, 32, 4);
++#endif
++
++  /* Choose init value arbitrarily, will be used as comparison value.  */
++#ifdef HAS_FLOAT16_VARIANT
++  VDUP(vector2, , float, f, 16, 4, -15.5f);
++  VDUP(vector2, q, float, f, 16, 8, -14.5f);
++#endif
++#ifdef HAS_FLOAT_VARIANT
++  VDUP(vector2, , float, f, 32, 2, -15.5f);
++  VDUP(vector2, q, float, f, 32, 4, -14.5f);
++#endif
++
++#ifdef HAS_FLOAT16_VARIANT
++#define FLOAT16_VARIANT(MACRO, VAR)			\
++  MACRO(VAR, , float, f, 16, 4);			\
++  MACRO(VAR, q, float, f, 16, 8);
++#else
++#define FLOAT16_VARIANT(MACRO, VAR)
++#endif
++
++#ifdef HAS_FLOAT_VARIANT
++#define FLOAT_VARIANT(MACRO, VAR)			\
++  MACRO(VAR, , float, f, 32, 2);			\
++  MACRO(VAR, q, float, f, 32, 4);
++#else
++#define FLOAT_VARIANT(MACRO, VAR)
++#endif
++
++#define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR)	\
++
++  /* Apply a binary operator named INSN_NAME.  */
++  FLOAT16_VARIANT(TEST_BINARY_OP, INSN_NAME);
++  FLOAT_VARIANT(TEST_BINARY_OP, INSN_NAME);
++
++#ifdef HAS_FLOAT16_VARIANT
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++
++  /* Extra FP tests with special values (NaN, ....)  */
++  VDUP(vector, q, float, f, 16, 8, 1.0f);
++  VDUP(vector2, q, float, f, 16, 8, NAN);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_nan,
++	   " FP special (NaN)");
++
++  VDUP(vector, q, float, f, 16, 8, -NAN);
++  VDUP(vector2, q, float, f, 16, 8, 1.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_mnan,
++	   " FP special (-NaN)");
++
++  VDUP(vector, q, float, f, 16, 8, 1.0f);
++  VDUP(vector2, q, float, f, 16, 8, HUGE_VALF);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_inf,
++	   " FP special (inf)");
++
++  VDUP(vector, q, float, f, 16, 8, -HUGE_VALF);
++  VDUP(vector2, q, float, f, 16, 8, 1.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_minf,
++	   " FP special (-inf)");
++
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++  VDUP(vector2, q, float, f, 16, 8, -0.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_zero1,
++	   " FP special (-0.0)");
++
++  VDUP(vector, q, float, f, 16, 8, -0.0f);
++  VDUP(vector2, q, float, f, 16, 8, 0.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_zero2,
++	   " FP special (-0.0)");
++#endif
++
++#ifdef HAS_FLOAT_VARIANT
++  CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
++
++  /* Extra FP tests with special values (NaN, ....)  */
++  VDUP(vector, q, float, f, 32, 4, 1.0f);
++  VDUP(vector2, q, float, f, 32, 4, NAN);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_nan, " FP special (NaN)");
++
++  VDUP(vector, q, float, f, 32, 4, -NAN);
++  VDUP(vector2, q, float, f, 32, 4, 1.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_mnan, " FP special (-NaN)");
++
++  VDUP(vector, q, float, f, 32, 4, 1.0f);
++  VDUP(vector2, q, float, f, 32, 4, HUGE_VALF);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_inf, " FP special (inf)");
++
++  VDUP(vector, q, float, f, 32, 4, -HUGE_VALF);
++  VDUP(vector2, q, float, f, 32, 4, 1.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_minf, " FP special (-inf)");
++
++  VDUP(vector, q, float, f, 32, 4, 0.0f);
++  VDUP(vector2, q, float, f, 32, 4, -0.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_zero1, " FP special (-0.0)");
++
++  VDUP(vector, q, float, f, 32, 4, -0.0f);
++  VDUP(vector2, q, float, f, 32, 4, 0.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
++  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_zero2, " FP special (-0.0)");
++#endif
++}
++
++int main (void)
++{
++  FNNAME (INSN_NAME) ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc
+@@ -28,6 +28,10 @@ void FNNAME (INSN_NAME) (void)
+ 
+   /* Initialize input "vector" from "buffer".  */
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#ifdef HAS_FLOAT16_VARIANT
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+ #ifdef HAS_FLOAT_VARIANT
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+@@ -46,15 +50,27 @@ void FNNAME (INSN_NAME) (void)
+   VDUP(vector2, q, uint, u, 8, 16, 0xf9);
+   VDUP(vector2, q, uint, u, 16, 8, 0xfff2);
+   VDUP(vector2, q, uint, u, 32, 4, 0xfffffff1);
++#ifdef HAS_FLOAT16_VARIANT
++  VDUP(vector2, , float, f, 16, 4, -15.5f);
++  VDUP(vector2, q, float, f, 16, 8, -14.5f);
++#endif
+ #ifdef HAS_FLOAT_VARIANT
+   VDUP(vector2, , float, f, 32, 2, -15.5f);
+   VDUP(vector2, q, float, f, 32, 4, -14.5f);
+ #endif
+ 
++#ifdef HAS_FLOAT16_VARIANT
++#define FLOAT16_VARIANT(MACRO, VAR)			\
++  MACRO(VAR, , float, f, 16, 4);			\
++  MACRO(VAR, q, float, f, 16, 8);
++#else
++#define FLOAT16_VARIANT(MACRO, VAR)
++#endif
++
+ #ifdef HAS_FLOAT_VARIANT
+ #define FLOAT_VARIANT(MACRO, VAR)			\
+   MACRO(VAR, , float, f, 32, 2);			\
+-  MACRO(VAR, q, float, f, 32, 4)
++  MACRO(VAR, q, float, f, 32, 4);
+ #else
+ #define FLOAT_VARIANT(MACRO, VAR)
+ #endif
+@@ -72,7 +88,8 @@ void FNNAME (INSN_NAME) (void)
+   MACRO(VAR, q, uint, u, 8, 16);			\
+   MACRO(VAR, q, uint, u, 16, 8);			\
+   MACRO(VAR, q, uint, u, 32, 4);			\
+-  FLOAT_VARIANT(MACRO, VAR)
++  FLOAT_VARIANT(MACRO, VAR);				\
++  FLOAT16_VARIANT(MACRO, VAR);
+ 
+   /* Apply a binary operator named INSN_NAME.  */
+   TEST_MACRO_NO64BIT_VARIANT_1_5(TEST_BINARY_OP, INSN_NAME);
+@@ -90,6 +107,42 @@ void FNNAME (INSN_NAME) (void)
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ 
++#ifdef HAS_FLOAT16_VARIANT
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++
++  /* Extra FP tests with special values (NaN, ....)  */
++  VDUP(vector, q, float, f, 16, 8, 1.0f);
++  VDUP(vector2, q, float, f, 16, 8, NAN);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_nan, " FP special (NaN)");
++
++  VDUP(vector, q, float, f, 16, 8, -NAN);
++  VDUP(vector2, q, float, f, 16, 8, 1.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_mnan, " FP special (-NaN)");
++
++  VDUP(vector, q, float, f, 16, 8, 1.0f);
++  VDUP(vector2, q, float, f, 16, 8, HUGE_VALF);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_inf, " FP special (inf)");
++
++  VDUP(vector, q, float, f, 16, 8, -HUGE_VALF);
++  VDUP(vector2, q, float, f, 16, 8, 1.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_minf, " FP special (-inf)");
++
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++  VDUP(vector2, q, float, f, 16, 8, -0.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_zero1, " FP special (-0.0)");
++
++  VDUP(vector, q, float, f, 16, 8, -0.0f);
++  VDUP(vector2, q, float, f, 16, 8, 0.0f);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_zero2, " FP special (-0.0)");
++#endif
++
+ #ifdef HAS_FLOAT_VARIANT
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc
+@@ -0,0 +1,160 @@
++/* Template file for binary scalar operator validation.
++
++   This file is meant to be included by test files for binary scalar
++   operations.  */
++
++/* Check for required settings.  */
++
++#ifndef INSN_NAME
++#error INSN_NAME (the intrinsic to test) must be defined.
++#endif
++
++#ifndef INPUT_TYPE
++#error INPUT_TYPE (basic type of an input value) must be defined.
++#endif
++
++#ifndef OUTPUT_TYPE
++#error OUTPUT_TYPE (basic type of an output value) must be defined.
++#endif
++
++#ifndef OUTPUT_TYPE_SIZE
++#error OUTPUT_TYPE_SIZE (size in bits of an output value) must be defined.
++#endif
++
++/* Optional settings:
++
++   INPUT_1: Input values for the first parameter.  Must be of type INPUT_TYPE.
++   INPUT_2: Input values for the first parameter.  Must be of type
++   INPUT_TYPE.  */
++
++#ifndef TEST_MSG
++#define TEST_MSG "unnamed test"
++#endif
++
++/* The test framework.  */
++
++#include <stdio.h>
++
++extern void abort ();
++
++#define INFF __builtin_inf ()
++
++/* Stringify a macro.  */
++#define STR0(A) #A
++#define STR(A) STR0 (A)
++
++/* Macro concatenation.  */
++#define CAT0(A, B) A##B
++#define CAT(A, B) CAT0 (A, B)
++
++/* Format strings for error reporting.  */
++#define FMT16 "0x%04x"
++#define FMT32 "0x%08x"
++#define FMT CAT (FMT,OUTPUT_TYPE_SIZE)
++
++/* Type construction: forms TS_t, where T is the base type and S the size in
++   bits.  */
++#define MK_TYPE0(T, S) T##S##_t
++#define MK_TYPE(T, S) MK_TYPE0 (T, S)
++
++/* Convenience types for input and output data.  */
++typedef MK_TYPE (uint, OUTPUT_TYPE_SIZE) output_hex_type;
++
++/* Conversion between typed values and their hexadecimal representation.  */
++typedef union
++{
++  OUTPUT_TYPE value;
++  output_hex_type hex;
++} output_conv_type;
++
++/* Default input values.  */
++
++float16_t input_1_float16_t[] =
++{
++  0.0, -0.0,
++  2.0, 3.1,
++  20.0, 0.40,
++  -2.3, 1.33,
++  -7.6, 0.31,
++  0.3353, 0.5,
++  1.0, 13.13,
++  -6.3, 20.0,
++  (float16_t)INFF, (float16_t)-INFF,
++};
++
++float16_t input_2_float16_t[] =
++{
++  1.0, 1.0,
++  -4.33, 100.0,
++  30.0, -0.02,
++  0.5, -7.231,
++  -6.3, 20.0,
++  -7.231, 2.3,
++  -7.6, 5.1,
++  0.31, 0.33353,
++  (float16_t)-INFF, (float16_t)INFF,
++};
++
++#ifndef INPUT_1
++#define INPUT_1 CAT (input_1_,INPUT_TYPE)
++#endif
++
++#ifndef INPUT_2
++#define INPUT_2 CAT (input_2_,INPUT_TYPE)
++#endif
++
++/* Support macros and routines for the test function.  */
++
++#define CHECK()						\
++  {								\
++    output_conv_type actual;					\
++    output_conv_type expect;					\
++								\
++    expect.hex = ((output_hex_type*)EXPECTED)[index];		\
++    actual.value = INSN_NAME ((INPUT_1)[index],			\
++			      (INPUT_2)[index]);		\
++								\
++    if (actual.hex != expect.hex)				\
++      {								\
++	fprintf (stderr,					\
++		 "ERROR in %s (%s line %d), buffer %s, "	\
++		 "index %d: got "				\
++		 FMT " != " FMT "\n",				\
++		 TEST_MSG, __FILE__, __LINE__,			\
++		 STR (EXPECTED), index,				\
++		 actual.hex, expect.hex);			\
++	abort ();						\
++      }								\
++    fprintf (stderr, "CHECKED %s %s\n",				\
++	     STR (EXPECTED), TEST_MSG);				\
++  }
++
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1 (NAME)
++
++/* The test function.  */
++
++void
++FNNAME (INSN_NAME) (void)
++{
++  /* Basic test: y[i] = OP (x[i]), for each INPUT[i], then compare the result
++     against EXPECTED[i].  */
++
++  const int num_tests = sizeof (INPUT_1) / sizeof (INPUT_1[0]);
++  int index;
++
++  for (index = 0; index < num_tests; index++)
++    CHECK ();
++
++#ifdef EXTRA_TESTS
++  EXTRA_TESTS ();
++#endif
++}
++
++int
++main (void)
++{
++  FNNAME (INSN_NAME) ();
++
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc
+@@ -15,6 +15,10 @@
+    each test file.  */
+ extern ARRAY(expected2, uint, 32, 2);
+ extern ARRAY(expected2, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++extern ARRAY(expected2, uint, 16, 4);
++extern ARRAY(expected2, uint, 16, 8);
++#endif
+ 
+ #define FNNAME1(NAME) exec_ ## NAME
+ #define FNNAME(NAME) FNNAME1(NAME)
+@@ -37,17 +41,33 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector2, float, 32, 4);
+   DECL_VARIABLE(vector_res, uint, 32, 2);
+   DECL_VARIABLE(vector_res, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++  DECL_VARIABLE(vector_res, uint, 16, 4);
++  DECL_VARIABLE(vector_res, uint, 16, 8);
++#endif
+ 
+   clean_results ();
+ 
+   /* Initialize input "vector" from "buffer".  */
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+ 
+   /* Choose init value arbitrarily, will be used for vector
+      comparison.  */
+   VDUP(vector2, , float, f, 32, 2, -16.0f);
+   VDUP(vector2, q, float, f, 32, 4, -14.0f);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, -16.0f);
++  VDUP(vector2, q, float, f, 16, 8, -14.0f);
++#endif
+ 
+   /* Apply operator named INSN_NAME.  */
+   TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2);
+@@ -56,15 +76,36 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VCOMP(INSN_NAME, q, float, f, uint, 32, 4);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VCOMP(INSN_NAME, , float, f, uint, 16, 4);
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
++
++  TEST_VCOMP(INSN_NAME, q, float, f, uint, 16, 8);
++  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
++#endif
++
+   /* Test again, with different input values.  */
+   VDUP(vector2, , float, f, 32, 2, -10.0f);
+   VDUP(vector2, q, float, f, 32, 4, 10.0f);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, -10.0f);
++  VDUP(vector2, q, float, f, 16, 8, 10.0f);
++#endif
++
+   TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected2, "");
+ 
+   TEST_VCOMP(INSN_NAME, q, float, f, uint, 32, 4);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected2,"");
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VCOMP(INSN_NAME, , float, f, uint, 16, 4);
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected2, "");
++
++  TEST_VCOMP(INSN_NAME, q, float, f, uint, 16, 8);
++  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected2,"");
++#endif
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc
+@@ -11,6 +11,17 @@ extern ARRAY(expected_uint, uint, 32, 2);
+ extern ARRAY(expected_q_uint, uint, 8, 16);
+ extern ARRAY(expected_q_uint, uint, 16, 8);
+ extern ARRAY(expected_q_uint, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++extern ARRAY(expected_float, uint, 16, 4);
++extern ARRAY(expected_q_float, uint, 16, 8);
++extern ARRAY(expected_nan, uint, 16, 4);
++extern ARRAY(expected_mnan, uint, 16, 4);
++extern ARRAY(expected_nan2, uint, 16, 4);
++extern ARRAY(expected_inf, uint, 16, 4);
++extern ARRAY(expected_minf, uint, 16, 4);
++extern ARRAY(expected_inf2, uint, 16, 4);
++extern ARRAY(expected_mzero, uint, 16, 4);
++#endif
+ extern ARRAY(expected_float, uint, 32, 2);
+ extern ARRAY(expected_q_float, uint, 32, 4);
+ extern ARRAY(expected_uint2, uint, 32, 2);
+@@ -48,6 +59,9 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector, uint, 8, 8);
+   DECL_VARIABLE(vector, uint, 16, 4);
+   DECL_VARIABLE(vector, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE (vector, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, int, 8, 16);
+   DECL_VARIABLE(vector, int, 16, 8);
+@@ -55,6 +69,9 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector, uint, 8, 16);
+   DECL_VARIABLE(vector, uint, 16, 8);
+   DECL_VARIABLE(vector, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE (vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
+   DECL_VARIABLE(vector2, int, 8, 8);
+@@ -63,6 +80,9 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector2, uint, 8, 8);
+   DECL_VARIABLE(vector2, uint, 16, 4);
+   DECL_VARIABLE(vector2, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE (vector2, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector2, float, 32, 2);
+   DECL_VARIABLE(vector2, int, 8, 16);
+   DECL_VARIABLE(vector2, int, 16, 8);
+@@ -70,6 +90,9 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector2, uint, 8, 16);
+   DECL_VARIABLE(vector2, uint, 16, 8);
+   DECL_VARIABLE(vector2, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE (vector2, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector2, float, 32, 4);
+ 
+   DECL_VARIABLE(vector_res, uint, 8, 8);
+@@ -88,6 +111,9 @@ void FNNAME (INSN_NAME) (void)
+   VLOAD(vector, buffer, , uint, u, 8, 8);
+   VLOAD(vector, buffer, , uint, u, 16, 4);
+   VLOAD(vector, buffer, , uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD (vector, buffer, , float, f, 16, 4);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+ 
+   VLOAD(vector, buffer, q, int, s, 8, 16);
+@@ -96,6 +122,9 @@ void FNNAME (INSN_NAME) (void)
+   VLOAD(vector, buffer, q, uint, u, 8, 16);
+   VLOAD(vector, buffer, q, uint, u, 16, 8);
+   VLOAD(vector, buffer, q, uint, u, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD (vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+   /* Choose init value arbitrarily, will be used for vector
+@@ -106,6 +135,9 @@ void FNNAME (INSN_NAME) (void)
+   VDUP(vector2, , uint, u, 8, 8, 0xF3);
+   VDUP(vector2, , uint, u, 16, 4, 0xFFF2);
+   VDUP(vector2, , uint, u, 32, 2, 0xFFFFFFF1);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP (vector2, , float, f, 16, 4, -15.0f);
++#endif
+   VDUP(vector2, , float, f, 32, 2, -15.0f);
+ 
+   VDUP(vector2, q, int, s, 8, 16, -4);
+@@ -114,6 +146,9 @@ void FNNAME (INSN_NAME) (void)
+   VDUP(vector2, q, uint, u, 8, 16, 0xF4);
+   VDUP(vector2, q, uint, u, 16, 8, 0xFFF6);
+   VDUP(vector2, q, uint, u, 32, 4, 0xFFFFFFF2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP (vector2, q, float, f, 16, 8, -14.0f);
++#endif
+   VDUP(vector2, q, float, f, 32, 4, -14.0f);
+ 
+   /* The comparison operators produce only unsigned results, which
+@@ -154,9 +189,17 @@ void FNNAME (INSN_NAME) (void)
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_q_uint, "");
+ 
+   /* The float variants.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_float, "");
++#endif
+   TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_float, "");
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VCOMP (INSN_NAME, q, float, f, uint, 16, 8);
++  CHECK (TEST_MSG, uint, 16, 8, PRIx16, expected_q_float, "");
++#endif
+   TEST_VCOMP(INSN_NAME, q, float, f, uint, 32, 4);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_q_float, "");
+ 
+@@ -176,6 +219,43 @@ void FNNAME (INSN_NAME) (void)
+ 
+ 
+   /* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP (vector, , float, f, 16, 4, 1.0);
++  VDUP (vector2, , float, f, 16, 4, NAN);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_nan, "FP special (NaN)");
++
++  VDUP (vector, , float, f, 16, 4, 1.0);
++  VDUP (vector2, , float, f, 16, 4, -NAN);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_mnan, " FP special (-NaN)");
++
++  VDUP (vector, , float, f, 16, 4, NAN);
++  VDUP (vector2, , float, f, 16, 4, 1.0);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_nan2, " FP special (NaN)");
++
++  VDUP (vector, , float, f, 16, 4, 1.0);
++  VDUP (vector2, , float, f, 16, 4, HUGE_VALF);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_inf, " FP special (inf)");
++
++  VDUP (vector, , float, f, 16, 4, 1.0);
++  VDUP (vector2, , float, f, 16, 4, -HUGE_VALF);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_minf, " FP special (-inf)");
++
++  VDUP (vector, , float, f, 16, 4, HUGE_VALF);
++  VDUP (vector2, , float, f, 16, 4, 1.0);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_inf2, " FP special (inf)");
++
++  VDUP (vector, , float, f, 16, 4, -0.0);
++  VDUP (vector2, , float, f, 16, 4, 0.0);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_mzero, " FP special (-0.0)");
++#endif
++
+   VDUP(vector, , float, f, 32, 2, 1.0);
+   VDUP(vector2, , float, f, 32, 2, NAN);
+   TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2);
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_zero_op.inc
+@@ -0,0 +1,111 @@
++/* Template file for the validation of compare against zero operators.
++
++   This file is base on cmp_op.inc.  It is meant to be included by the relevant
++   test files, which have to define the intrinsic family to test.  If a given
++   intrinsic supports variants which are not supported by all the other
++   operators, these can be tested by providing a definition for EXTRA_TESTS.  */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++#include <math.h>
++
++/* Additional expected results declaration, they are initialized in
++   each test file.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++extern ARRAY(expected_float, uint, 16, 4);
++extern ARRAY(expected_q_float, uint, 16, 8);
++extern ARRAY(expected_uint2, uint, 16, 4);
++extern ARRAY(expected_uint3, uint, 16, 4);
++extern ARRAY(expected_uint4, uint, 16, 4);
++extern ARRAY(expected_nan, uint, 16, 4);
++extern ARRAY(expected_mnan, uint, 16, 4);
++extern ARRAY(expected_inf, uint, 16, 4);
++extern ARRAY(expected_minf, uint, 16, 4);
++extern ARRAY(expected_zero, uint, 16, 4);
++extern ARRAY(expected_mzero, uint, 16, 4);
++#endif
++
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1(NAME)
++
++void FNNAME (INSN_NAME) (void)
++{
++  /* Basic test: y=vcomp(x1,x2), then store the result.  */
++#define TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N)				\
++  VECT_VAR(vector_res, T3, W, N) =					\
++    INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N));			\
++  vst1##Q##_u##W(VECT_VAR(result, T3, W, N), VECT_VAR(vector_res, T3, W, N))
++
++#define TEST_VCOMP(INSN, Q, T1, T2, T3, W, N)				\
++  TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N)
++
++  /* No need for 64 bits elements.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE (vector, float, 16, 4);
++  DECL_VARIABLE (vector, float, 16, 8);
++#endif
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, uint, 16, 4);
++  DECL_VARIABLE(vector_res, uint, 16, 8);
++#endif
++
++  clean_results ();
++
++  /* Choose init value arbitrarily, will be used for vector
++     comparison.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP (vector, , float, f, 16, 4, -15.0f);
++  VDUP (vector, q, float, f, 16, 8, 14.0f);
++#endif
++
++  /* Float variants.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  TEST_VCOMP (INSN_NAME, q, float, f, uint, 16, 8);
++#endif
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_float, "");
++  CHECK (TEST_MSG, uint, 16, 8, PRIx16, expected_q_float, "");
++#endif
++
++  /* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP (vector, , float, f, 16, 4, NAN);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_nan, "FP special (NaN)");
++
++  VDUP (vector, , float, f, 16, 4, -NAN);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_mnan, " FP special (-NaN)");
++
++  VDUP (vector, , float, f, 16, 4, HUGE_VALF);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_inf, " FP special (inf)");
++
++  VDUP (vector, , float, f, 16, 4, -HUGE_VALF);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_minf, " FP special (-inf)");
++
++  VDUP (vector, , float, f, 16, 4, 0.0);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_zero, " FP special (0.0)");
++
++  VDUP (vector, , float, f, 16, 4, 0.0);
++  TEST_VCOMP (INSN_NAME, , float, f, uint, 16, 4);
++  CHECK (TEST_MSG, uint, 16, 4, PRIx16, expected_mzero, " FP special (-0.0)");
++#endif
++
++#ifdef EXTRA_TESTS
++  EXTRA_TESTS();
++#endif
++}
++
++int main (void)
++{
++  FNNAME (INSN_NAME) ();
++
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h
+@@ -118,6 +118,10 @@ VECT_VAR_DECL_INIT(buffer, uint, 32, 2);
+ PAD(buffer_pad, uint, 32, 2);
+ VECT_VAR_DECL_INIT(buffer, uint, 64, 1);
+ PAD(buffer_pad, uint, 64, 1);
++#if defined (__ARM_FEATURE_CRYPTO)
++VECT_VAR_DECL_INIT(buffer, poly, 64, 1);
++PAD(buffer_pad, poly, 64, 1);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ VECT_VAR_DECL_INIT(buffer, float, 16, 4);
+ PAD(buffer_pad, float, 16, 4);
+@@ -144,6 +148,10 @@ VECT_VAR_DECL_INIT(buffer, poly, 8, 16);
+ PAD(buffer_pad, poly, 8, 16);
+ VECT_VAR_DECL_INIT(buffer, poly, 16, 8);
+ PAD(buffer_pad, poly, 16, 8);
++#if defined (__ARM_FEATURE_CRYPTO)
++VECT_VAR_DECL_INIT(buffer, poly, 64, 2);
++PAD(buffer_pad, poly, 64, 2);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ VECT_VAR_DECL_INIT(buffer, float, 16, 8);
+ PAD(buffer_pad, float, 16, 8);
+@@ -178,6 +186,10 @@ VECT_VAR_DECL_INIT(buffer_dup, poly, 8, 8);
+ VECT_VAR_DECL(buffer_dup_pad, poly, 8, 8);
+ VECT_VAR_DECL_INIT(buffer_dup, poly, 16, 4);
+ VECT_VAR_DECL(buffer_dup_pad, poly, 16, 4);
++#if defined (__ARM_FEATURE_CRYPTO)
++VECT_VAR_DECL_INIT4(buffer_dup, poly, 64, 1);
++VECT_VAR_DECL(buffer_dup_pad, poly, 64, 1);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ VECT_VAR_DECL_INIT4(buffer_dup, float, 16, 4);
+ VECT_VAR_DECL(buffer_dup_pad, float, 16, 4);
+@@ -205,6 +217,10 @@ VECT_VAR_DECL_INIT(buffer_dup, poly, 8, 16);
+ VECT_VAR_DECL(buffer_dup_pad, poly, 8, 16);
+ VECT_VAR_DECL_INIT(buffer_dup, poly, 16, 8);
+ VECT_VAR_DECL(buffer_dup_pad, poly, 16, 8);
++#if defined (__ARM_FEATURE_CRYPTO)
++VECT_VAR_DECL_INIT4(buffer_dup, poly, 64, 2);
++VECT_VAR_DECL(buffer_dup_pad, poly, 64, 2);
++#endif
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+ VECT_VAR_DECL_INIT(buffer_dup, float, 16, 8);
+ VECT_VAR_DECL(buffer_dup_pad, float, 16, 8);
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/p64_p128.c
+@@ -0,0 +1,1103 @@
++/* This file contains tests for all the *p64 intrinsics, except for
++   vreinterpret which have their own testcase.  */
++
++/* { dg-require-effective-target arm_crypto_ok { target { arm*-*-* } } } */
++/* { dg-add-options arm_crypto } */
++/* { dg-additional-options "-march=armv8-a+crypto" { target { aarch64*-*-* } } }*/
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results: vbsl.  */
++VECT_VAR_DECL(vbsl_expected,poly,64,1) [] = { 0xfffffff1 };
++VECT_VAR_DECL(vbsl_expected,poly,64,2) [] = { 0xfffffff1,
++					      0xfffffff1 };
++
++/* Expected results: vceq.  */
++VECT_VAR_DECL(vceq_expected,uint,64,1) [] = { 0x0 };
++
++/* Expected results: vcombine.  */
++VECT_VAR_DECL(vcombine_expected,poly,64,2) [] = { 0xfffffffffffffff0, 0x88 };
++
++/* Expected results: vcreate.  */
++VECT_VAR_DECL(vcreate_expected,poly,64,1) [] = { 0x123456789abcdef0 };
++
++/* Expected results: vdup_lane.  */
++VECT_VAR_DECL(vdup_lane_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vdup_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0xfffffffffffffff0 };
++
++/* Expected results: vdup_n.  */
++VECT_VAR_DECL(vdup_n_expected0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vdup_n_expected0,poly,64,2) [] = { 0xfffffffffffffff0,
++						 0xfffffffffffffff0 };
++VECT_VAR_DECL(vdup_n_expected1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vdup_n_expected1,poly,64,2) [] = { 0xfffffffffffffff1,
++						 0xfffffffffffffff1 };
++VECT_VAR_DECL(vdup_n_expected2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vdup_n_expected2,poly,64,2) [] = { 0xfffffffffffffff2,
++						 0xfffffffffffffff2 };
++
++/* Expected results: vext.  */
++VECT_VAR_DECL(vext_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vext_expected,poly,64,2) [] = { 0xfffffffffffffff1, 0x88 };
++
++/* Expected results: vget_low.  */
++VECT_VAR_DECL(vget_low_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
++
++/* Expected results: vget_high.  */
++VECT_VAR_DECL(vget_high_expected,poly,64,1) [] = { 0xfffffffffffffff1 };
++
++/* Expected results: vld1.  */
++VECT_VAR_DECL(vld1_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld1_expected,poly,64,2) [] = { 0xfffffffffffffff0,
++					      0xfffffffffffffff1 };
++
++/* Expected results: vld1_dup.  */
++VECT_VAR_DECL(vld1_dup_expected0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld1_dup_expected0,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0xfffffffffffffff0 };
++VECT_VAR_DECL(vld1_dup_expected1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld1_dup_expected1,poly,64,2) [] = { 0xfffffffffffffff1,
++						   0xfffffffffffffff1 };
++VECT_VAR_DECL(vld1_dup_expected2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vld1_dup_expected2,poly,64,2) [] = { 0xfffffffffffffff2,
++						   0xfffffffffffffff2 };
++
++/* Expected results: vld1_lane.  */
++VECT_VAR_DECL(vld1_lane_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld1_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0xaaaaaaaaaaaaaaaa };
++
++/* Expected results: vldX.  */
++VECT_VAR_DECL(vld2_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld2_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld3_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld3_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld3_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vld4_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld4_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld4_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vld4_expected_3,poly,64,1) [] = { 0xfffffffffffffff3 };
++
++/* Expected results: vldX_dup.  */
++VECT_VAR_DECL(vld2_dup_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld2_dup_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld3_dup_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld3_dup_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld3_dup_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vld4_dup_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vld4_dup_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vld4_dup_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vld4_dup_expected_3,poly,64,1) [] = { 0xfffffffffffffff3 };
++
++/* Expected results: vsli.  */
++VECT_VAR_DECL(vsli_expected,poly,64,1) [] = { 0x10 };
++VECT_VAR_DECL(vsli_expected,poly,64,2) [] = { 0x7ffffffffffff0,
++					      0x7ffffffffffff1 };
++VECT_VAR_DECL(vsli_expected_max_shift,poly,64,1) [] = { 0x7ffffffffffffff0 };
++VECT_VAR_DECL(vsli_expected_max_shift,poly,64,2) [] = { 0xfffffffffffffff0,
++							0xfffffffffffffff1 };
++
++/* Expected results: vsri.  */
++VECT_VAR_DECL(vsri_expected,poly,64,1) [] = { 0xe000000000000000 };
++VECT_VAR_DECL(vsri_expected,poly,64,2) [] = { 0xfffffffffffff800,
++					      0xfffffffffffff800 };
++VECT_VAR_DECL(vsri_expected_max_shift,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vsri_expected_max_shift,poly,64,2) [] = { 0xfffffffffffffff0,
++							0xfffffffffffffff1 };
++
++/* Expected results: vst1_lane.  */
++VECT_VAR_DECL(vst1_lane_expected,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vst1_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0x3333333333333333 };
++
++/* Expected results: vget_lane.  */
++VECT_VAR_DECL(vget_lane_expected,poly,64,1) = 0xfffffffffffffff0;
++VECT_VAR_DECL(vget_lane_expected,poly,64,2) = 0xfffffffffffffff0;
++
++/* Expected results: vset_lane.  */
++VECT_VAR_DECL(vset_lane_expected,poly,64,1) [] = { 0x88 };
++VECT_VAR_DECL(vset_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0, 0x11 };
++
++/* Expected results: vtst.  */
++VECT_VAR_DECL(vtst_expected,uint,64,1) [] = { 0x0 };
++
++#ifdef __aarch64__
++/* Expected results: vmov_n.  */
++VECT_VAR_DECL(vmov_n_expected0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vmov_n_expected0,poly,64,2) [] = { 0xfffffffffffffff0,
++						 0xfffffffffffffff0 };
++VECT_VAR_DECL(vmov_n_expected1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(vmov_n_expected1,poly,64,2) [] = { 0xfffffffffffffff1,
++						 0xfffffffffffffff1 };
++VECT_VAR_DECL(vmov_n_expected2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(vmov_n_expected2,poly,64,2) [] = { 0xfffffffffffffff2,
++						 0xfffffffffffffff2 };
++
++/* Expected results: vldX_lane.  */
++VECT_VAR_DECL(expected_vld_st2_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected_vld_st2_0,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0xfffffffffffffff1 };
++VECT_VAR_DECL(expected_vld_st2_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected_vld_st2_1,poly,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
++						   0xaaaaaaaaaaaaaaaa };
++VECT_VAR_DECL(expected_vld_st3_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected_vld_st3_0,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0xfffffffffffffff1 };
++VECT_VAR_DECL(expected_vld_st3_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected_vld_st3_1,poly,64,2) [] = { 0xfffffffffffffff2,
++						   0xaaaaaaaaaaaaaaaa };
++VECT_VAR_DECL(expected_vld_st3_2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(expected_vld_st3_2,poly,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
++						   0xaaaaaaaaaaaaaaaa };
++VECT_VAR_DECL(expected_vld_st4_0,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected_vld_st4_0,poly,64,2) [] = { 0xfffffffffffffff0,
++						   0xfffffffffffffff1 };
++VECT_VAR_DECL(expected_vld_st4_1,poly,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected_vld_st4_1,poly,64,2) [] = { 0xfffffffffffffff2,
++						   0xfffffffffffffff3 };
++VECT_VAR_DECL(expected_vld_st4_2,poly,64,1) [] = { 0xfffffffffffffff2 };
++VECT_VAR_DECL(expected_vld_st4_2,poly,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
++						   0xaaaaaaaaaaaaaaaa };
++VECT_VAR_DECL(expected_vld_st4_3,poly,64,1) [] = { 0xfffffffffffffff3 };
++VECT_VAR_DECL(expected_vld_st4_3,poly,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
++						   0xaaaaaaaaaaaaaaaa };
++
++/* Expected results: vtst.  */
++VECT_VAR_DECL(vtst_expected,uint,64,2) [] = { 0x0, 0xffffffffffffffff };
++#endif
++
++int main (void)
++{
++  int i;
++
++  /* vbsl_p64 tests.  */
++#define TEST_MSG "VBSL/VBSLQ"
++
++#define TEST_VBSL(T3, Q, T1, T2, W, N)					\
++  VECT_VAR(vbsl_vector_res, T1, W, N) =					\
++    vbsl##Q##_##T2##W(VECT_VAR(vbsl_vector_first, T3, W, N),		\
++		      VECT_VAR(vbsl_vector, T1, W, N),			\
++		      VECT_VAR(vbsl_vector2, T1, W, N));		\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vbsl_vector_res, T1, W, N))
++
++  DECL_VARIABLE(vbsl_vector, poly, 64, 1);
++  DECL_VARIABLE(vbsl_vector, poly, 64, 2);
++  DECL_VARIABLE(vbsl_vector2, poly, 64, 1);
++  DECL_VARIABLE(vbsl_vector2, poly, 64, 2);
++  DECL_VARIABLE(vbsl_vector_res, poly, 64, 1);
++  DECL_VARIABLE(vbsl_vector_res, poly, 64, 2);
++
++  DECL_VARIABLE(vbsl_vector_first, uint, 64, 1);
++  DECL_VARIABLE(vbsl_vector_first, uint, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vbsl_vector, buffer, , poly, p, 64, 1);
++  VLOAD(vbsl_vector, buffer, q, poly, p, 64, 2);
++
++  VDUP(vbsl_vector2, , poly, p, 64, 1, 0xFFFFFFF3);
++  VDUP(vbsl_vector2, q, poly, p, 64, 2, 0xFFFFFFF3);
++
++  VDUP(vbsl_vector_first, , uint, u, 64, 1, 0xFFFFFFF2);
++  VDUP(vbsl_vector_first, q, uint, u, 64, 2, 0xFFFFFFF2);
++
++  TEST_VBSL(uint, , poly, p, 64, 1);
++  TEST_VBSL(uint, q, poly, p, 64, 2);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vbsl_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vbsl_expected, "");
++
++  /* vceq_p64 tests. */
++#undef TEST_MSG
++#define TEST_MSG "VCEQ"
++
++#define TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N)				\
++  VECT_VAR(vceq_vector_res, T3, W, N) =					\
++    INSN##Q##_##T2##W(VECT_VAR(vceq_vector, T1, W, N),			\
++		      VECT_VAR(vceq_vector2, T1, W, N));		\
++  vst1##Q##_u##W(VECT_VAR(result, T3, W, N), VECT_VAR(vceq_vector_res, T3, W, N))
++
++#define TEST_VCOMP(INSN, Q, T1, T2, T3, W, N)				\
++  TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N)
++
++  DECL_VARIABLE(vceq_vector, poly, 64, 1);
++  DECL_VARIABLE(vceq_vector2, poly, 64, 1);
++  DECL_VARIABLE(vceq_vector_res, uint, 64, 1);
++
++  CLEAN(result, uint, 64, 1);
++
++  VLOAD(vceq_vector, buffer, , poly, p, 64, 1);
++
++  VDUP(vceq_vector2, , poly, p, 64, 1, 0x88);
++
++  TEST_VCOMP(vceq, , poly, p, uint, 64, 1);
++
++  CHECK(TEST_MSG, uint, 64, 1, PRIx64, vceq_expected, "");
++
++  /* vcombine_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VCOMBINE"
++
++#define TEST_VCOMBINE(T1, T2, W, N, N2)					\
++  VECT_VAR(vcombine_vector128, T1, W, N2) =				\
++    vcombine_##T2##W(VECT_VAR(vcombine_vector64_a, T1, W, N),		\
++		     VECT_VAR(vcombine_vector64_b, T1, W, N));		\
++  vst1q_##T2##W(VECT_VAR(result, T1, W, N2), VECT_VAR(vcombine_vector128, T1, W, N2))
++
++  DECL_VARIABLE(vcombine_vector64_a, poly, 64, 1);
++  DECL_VARIABLE(vcombine_vector64_b, poly, 64, 1);
++  DECL_VARIABLE(vcombine_vector128, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vcombine_vector64_a, buffer, , poly, p, 64, 1);
++
++  VDUP(vcombine_vector64_b, , poly, p, 64, 1, 0x88);
++
++  TEST_VCOMBINE(poly, p, 64, 1, 2);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vcombine_expected, "");
++
++  /* vcreate_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VCREATE"
++
++#define TEST_VCREATE(T1, T2, W, N)					\
++  VECT_VAR(vcreate_vector_res, T1, W, N) =				\
++    vcreate_##T2##W(VECT_VAR(vcreate_val, T1, W, N));			\
++  vst1_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vcreate_vector_res, T1, W, N))
++
++#define DECL_VAL(VAR, T1, W, N)			\
++  uint64_t VECT_VAR(VAR, T1, W, N)
++
++  DECL_VAL(vcreate_val, poly, 64, 1);
++  DECL_VARIABLE(vcreate_vector_res, poly, 64, 1);
++
++  CLEAN(result, poly, 64, 2);
++
++  VECT_VAR(vcreate_val, poly, 64, 1) = 0x123456789abcdef0ULL;
++
++  TEST_VCREATE(poly, p, 64, 1);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vcreate_expected, "");
++
++  /* vdup_lane_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VDUP_LANE/VDUP_LANEQ"
++
++#define TEST_VDUP_LANE(Q, T1, T2, W, N, N2, L)				\
++  VECT_VAR(vdup_lane_vector_res, T1, W, N) =				\
++    vdup##Q##_lane_##T2##W(VECT_VAR(vdup_lane_vector, T1, W, N2), L);	\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vdup_lane_vector_res, T1, W, N))
++
++  DECL_VARIABLE(vdup_lane_vector, poly, 64, 1);
++  DECL_VARIABLE(vdup_lane_vector, poly, 64, 2);
++  DECL_VARIABLE(vdup_lane_vector_res, poly, 64, 1);
++  DECL_VARIABLE(vdup_lane_vector_res, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vdup_lane_vector, buffer, , poly, p, 64, 1);
++
++  TEST_VDUP_LANE(, poly, p, 64, 1, 1, 0);
++  TEST_VDUP_LANE(q, poly, p, 64, 2, 1, 0);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vdup_lane_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vdup_lane_expected, "");
++
++  /* vdup_n_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VDUP/VDUPQ"
++
++#define TEST_VDUP(Q, T1, T2, W, N)					\
++  VECT_VAR(vdup_n_vector, T1, W, N) =					\
++    vdup##Q##_n_##T2##W(VECT_VAR(buffer_dup, T1, W, N)[i]);		\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vdup_n_vector, T1, W, N))
++
++  DECL_VARIABLE(vdup_n_vector, poly, 64, 1);
++  DECL_VARIABLE(vdup_n_vector, poly, 64, 2);
++
++  /* Try to read different places from the input buffer.  */
++  for (i=0; i< 3; i++) {
++    CLEAN(result, poly, 64, 1);
++    CLEAN(result, poly, 64, 2);
++
++    TEST_VDUP(, poly, p, 64, 1);
++    TEST_VDUP(q, poly, p, 64, 2);
++
++    switch (i) {
++    case 0:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vdup_n_expected0, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vdup_n_expected0, "");
++      break;
++    case 1:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vdup_n_expected1, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vdup_n_expected1, "");
++      break;
++    case 2:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vdup_n_expected2, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vdup_n_expected2, "");
++      break;
++    default:
++      abort();
++    }
++  }
++
++  /* vexit_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VEXT/VEXTQ"
++
++#define TEST_VEXT(Q, T1, T2, W, N, V)					\
++  VECT_VAR(vext_vector_res, T1, W, N) =					\
++    vext##Q##_##T2##W(VECT_VAR(vext_vector1, T1, W, N),			\
++		      VECT_VAR(vext_vector2, T1, W, N),			\
++		      V);						\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vext_vector_res, T1, W, N))
++
++  DECL_VARIABLE(vext_vector1, poly, 64, 1);
++  DECL_VARIABLE(vext_vector1, poly, 64, 2);
++  DECL_VARIABLE(vext_vector2, poly, 64, 1);
++  DECL_VARIABLE(vext_vector2, poly, 64, 2);
++  DECL_VARIABLE(vext_vector_res, poly, 64, 1);
++  DECL_VARIABLE(vext_vector_res, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vext_vector1, buffer, , poly, p, 64, 1);
++  VLOAD(vext_vector1, buffer, q, poly, p, 64, 2);
++
++  VDUP(vext_vector2, , poly, p, 64, 1, 0x88);
++  VDUP(vext_vector2, q, poly, p, 64, 2, 0x88);
++
++  TEST_VEXT(, poly, p, 64, 1, 0);
++  TEST_VEXT(q, poly, p, 64, 2, 1);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vext_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vext_expected, "");
++
++  /* vget_low_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VGET_LOW"
++
++#define TEST_VGET_LOW(T1, T2, W, N, N2)					\
++  VECT_VAR(vget_low_vector64, T1, W, N) =				\
++    vget_low_##T2##W(VECT_VAR(vget_low_vector128, T1, W, N2));		\
++  vst1_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vget_low_vector64, T1, W, N))
++
++  DECL_VARIABLE(vget_low_vector64, poly, 64, 1);
++  DECL_VARIABLE(vget_low_vector128, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++
++  VLOAD(vget_low_vector128, buffer, q, poly, p, 64, 2);
++
++  TEST_VGET_LOW(poly, p, 64, 1, 2);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vget_low_expected, "");
++
++  /* vget_high_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VGET_HIGH"
++
++#define TEST_VGET_HIGH(T1, T2, W, N, N2)					\
++  VECT_VAR(vget_high_vector64, T1, W, N) =				\
++    vget_high_##T2##W(VECT_VAR(vget_high_vector128, T1, W, N2));		\
++  vst1_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vget_high_vector64, T1, W, N))
++
++  DECL_VARIABLE(vget_high_vector64, poly, 64, 1);
++  DECL_VARIABLE(vget_high_vector128, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++
++  VLOAD(vget_high_vector128, buffer, q, poly, p, 64, 2);
++
++  TEST_VGET_HIGH(poly, p, 64, 1, 2);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vget_high_expected, "");
++
++  /* vld1_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VLD1/VLD1Q"
++
++#define TEST_VLD1(VAR, BUF, Q, T1, T2, W, N)				\
++  VECT_VAR(VAR, T1, W, N) = vld1##Q##_##T2##W(VECT_VAR(BUF, T1, W, N)); \
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(VAR, T1, W, N))
++
++  DECL_VARIABLE(vld1_vector, poly, 64, 1);
++  DECL_VARIABLE(vld1_vector, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vld1_vector, buffer, , poly, p, 64, 1);
++  VLOAD(vld1_vector, buffer, q, poly, p, 64, 2);
++
++  TEST_VLD1(vld1_vector, buffer, , poly, p, 64, 1);
++  TEST_VLD1(vld1_vector, buffer, q, poly, p, 64, 2);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld1_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vld1_expected, "");
++
++  /* vld1_dup_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VLD1_DUP/VLD1_DUPQ"
++
++#define TEST_VLD1_DUP(VAR, BUF, Q, T1, T2, W, N)			\
++  VECT_VAR(VAR, T1, W, N) =						\
++    vld1##Q##_dup_##T2##W(&VECT_VAR(BUF, T1, W, N)[i]);			\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(VAR, T1, W, N))
++
++  DECL_VARIABLE(vld1_dup_vector, poly, 64, 1);
++  DECL_VARIABLE(vld1_dup_vector, poly, 64, 2);
++
++  /* Try to read different places from the input buffer.  */
++  for (i=0; i<3; i++) {
++    CLEAN(result, poly, 64, 1);
++    CLEAN(result, poly, 64, 2);
++
++    TEST_VLD1_DUP(vld1_dup_vector, buffer_dup, , poly, p, 64, 1);
++    TEST_VLD1_DUP(vld1_dup_vector, buffer_dup, q, poly, p, 64, 2);
++
++    switch (i) {
++    case 0:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld1_dup_expected0, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vld1_dup_expected0, "");
++      break;
++    case 1:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld1_dup_expected1, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vld1_dup_expected1, "");
++      break;
++    case 2:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld1_dup_expected2, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vld1_dup_expected2, "");
++      break;
++    default:
++      abort();
++    }
++  }
++
++  /* vld1_lane_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VLD1_LANE/VLD1_LANEQ"
++
++#define TEST_VLD1_LANE(Q, T1, T2, W, N, L)				\
++  memset (VECT_VAR(vld1_lane_buffer_src, T1, W, N), 0xAA, W/8*N);	\
++  VECT_VAR(vld1_lane_vector_src, T1, W, N) =				\
++    vld1##Q##_##T2##W(VECT_VAR(vld1_lane_buffer_src, T1, W, N));	\
++  VECT_VAR(vld1_lane_vector, T1, W, N) =				\
++    vld1##Q##_lane_##T2##W(VECT_VAR(buffer, T1, W, N),			\
++			   VECT_VAR(vld1_lane_vector_src, T1, W, N), L); \
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vld1_lane_vector, T1, W, N))
++
++  DECL_VARIABLE(vld1_lane_vector, poly, 64, 1);
++  DECL_VARIABLE(vld1_lane_vector, poly, 64, 2);
++  DECL_VARIABLE(vld1_lane_vector_src, poly, 64, 1);
++  DECL_VARIABLE(vld1_lane_vector_src, poly, 64, 2);
++
++  ARRAY(vld1_lane_buffer_src, poly, 64, 1);
++  ARRAY(vld1_lane_buffer_src, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  TEST_VLD1_LANE(, poly, p, 64, 1, 0);
++  TEST_VLD1_LANE(q, poly, p, 64, 2, 0);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld1_lane_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vld1_lane_expected, "");
++
++  /* vldX_p64 tests.  */
++#define DECL_VLDX(T1, W, N, X)						\
++  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vldX_vector, T1, W, N, X); \
++  VECT_VAR_DECL(vldX_result_bis_##X, T1, W, N)[X * N]
++
++#define TEST_VLDX(Q, T1, T2, W, N, X)					\
++  VECT_ARRAY_VAR(vldX_vector, T1, W, N, X) =				\
++    /* Use dedicated init buffer, of size X */				\
++    vld##X##Q##_##T2##W(VECT_ARRAY_VAR(buffer_vld##X, T1, W, N, X));	\
++  vst##X##Q##_##T2##W(VECT_VAR(vldX_result_bis_##X, T1, W, N),		\
++		      VECT_ARRAY_VAR(vldX_vector, T1, W, N, X));	\
++  memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(vldX_result_bis_##X, T1, W, N), \
++	 sizeof(VECT_VAR(result, T1, W, N)));
++
++  /* Overwrite "result" with the contents of "result_bis"[Y].  */
++#define TEST_EXTRA_CHUNK(T1, W, N, X,Y)				\
++  memcpy(VECT_VAR(result, T1, W, N),				\
++	 &(VECT_VAR(vldX_result_bis_##X, T1, W, N)[Y*N]),	\
++	 sizeof(VECT_VAR(result, T1, W, N)));
++
++  DECL_VLDX(poly, 64, 1, 2);
++  DECL_VLDX(poly, 64, 1, 3);
++  DECL_VLDX(poly, 64, 1, 4);
++
++  VECT_ARRAY_INIT2(buffer_vld2, poly, 64, 1);
++  PAD(buffer_vld2_pad, poly, 64, 1);
++  VECT_ARRAY_INIT3(buffer_vld3, poly, 64, 1);
++  PAD(buffer_vld3_pad, poly, 64, 1);
++  VECT_ARRAY_INIT4(buffer_vld4, poly, 64, 1);
++  PAD(buffer_vld4_pad, poly, 64, 1);
++
++#undef TEST_MSG
++#define TEST_MSG "VLD2/VLD2Q"
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX(, poly, p, 64, 1, 2);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld2_expected_0, "chunk 0");
++  CLEAN(result, poly, 64, 1);
++  TEST_EXTRA_CHUNK(poly, 64, 1, 2, 1);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld2_expected_1, "chunk 1");
++
++#undef TEST_MSG
++#define TEST_MSG "VLD3/VLD3Q"
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX(, poly, p, 64, 1, 3);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld3_expected_0, "chunk 0");
++  CLEAN(result, poly, 64, 1);
++  TEST_EXTRA_CHUNK(poly, 64, 1, 3, 1);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld3_expected_1, "chunk 1");
++  CLEAN(result, poly, 64, 1);
++  TEST_EXTRA_CHUNK(poly, 64, 1, 3, 2);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld3_expected_2, "chunk 2");
++
++#undef TEST_MSG
++#define TEST_MSG "VLD4/VLD4Q"
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX(, poly, p, 64, 1, 4);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_0, "chunk 0");
++  CLEAN(result, poly, 64, 1);
++  TEST_EXTRA_CHUNK(poly, 64, 1, 4, 1);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_1, "chunk 1");
++  CLEAN(result, poly, 64, 1);
++  TEST_EXTRA_CHUNK(poly, 64, 1, 4, 2);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_2, "chunk 2");
++  CLEAN(result, poly, 64, 1);
++  TEST_EXTRA_CHUNK(poly, 64, 1, 4, 3);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_3, "chunk 3");
++
++  /* vldX_dup_p64 tests.  */
++#define DECL_VLDX_DUP(T1, W, N, X)					\
++  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vldX_dup_vector, T1, W, N, X); \
++  VECT_VAR_DECL(vldX_dup_result_bis_##X, T1, W, N)[X * N]
++
++#define TEST_VLDX_DUP(Q, T1, T2, W, N, X)				\
++  VECT_ARRAY_VAR(vldX_dup_vector, T1, W, N, X) =			\
++    vld##X##Q##_dup_##T2##W(&VECT_VAR(buffer_dup, T1, W, N)[0]);	\
++    									\
++  vst##X##Q##_##T2##W(VECT_VAR(vldX_dup_result_bis_##X, T1, W, N),	\
++		      VECT_ARRAY_VAR(vldX_dup_vector, T1, W, N, X));	\
++  memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(vldX_dup_result_bis_##X, T1, W, N), \
++	 sizeof(VECT_VAR(result, T1, W, N)));
++
++  /* Overwrite "result" with the contents of "result_bis"[Y].  */
++#define TEST_VLDX_DUP_EXTRA_CHUNK(T1, W, N, X,Y)		\
++  memcpy(VECT_VAR(result, T1, W, N),				\
++	 &(VECT_VAR(vldX_dup_result_bis_##X, T1, W, N)[Y*N]),	\
++	 sizeof(VECT_VAR(result, T1, W, N)));
++
++  DECL_VLDX_DUP(poly, 64, 1, 2);
++  DECL_VLDX_DUP(poly, 64, 1, 3);
++  DECL_VLDX_DUP(poly, 64, 1, 4);
++
++
++#undef TEST_MSG
++#define TEST_MSG "VLD2_DUP/VLD2Q_DUP"
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP(, poly, p, 64, 1, 2);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld2_dup_expected_0, "chunk 0");
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 2, 1);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld2_dup_expected_1, "chunk 1");
++
++#undef TEST_MSG
++#define TEST_MSG "VLD3_DUP/VLD3Q_DUP"
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP(, poly, p, 64, 1, 3);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld3_dup_expected_0, "chunk 0");
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 3, 1);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld3_dup_expected_1, "chunk 1");
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 3, 2);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld3_dup_expected_2, "chunk 2");
++
++#undef TEST_MSG
++#define TEST_MSG "VLD4_DUP/VLD4Q_DUP"
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP(, poly, p, 64, 1, 4);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_0, "chunk 0");
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 4, 1);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_1, "chunk 1");
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 4, 2);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_2, "chunk 2");
++  CLEAN(result, poly, 64, 1);
++  TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 4, 3);
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_3, "chunk 3");
++
++  /* vsli_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VSLI"
++
++#define TEST_VSXI1(INSN, Q, T1, T2, W, N, V)				\
++  VECT_VAR(vsXi_vector_res, T1, W, N) =					\
++    INSN##Q##_n_##T2##W(VECT_VAR(vsXi_vector, T1, W, N),		\
++		      VECT_VAR(vsXi_vector2, T1, W, N),			\
++		      V);						\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vsXi_vector_res, T1, W, N))
++
++#define TEST_VSXI(INSN, Q, T1, T2, W, N, V)	\
++  TEST_VSXI1(INSN, Q, T1, T2, W, N, V)
++
++  DECL_VARIABLE(vsXi_vector, poly, 64, 1);
++  DECL_VARIABLE(vsXi_vector, poly, 64, 2);
++  DECL_VARIABLE(vsXi_vector2, poly, 64, 1);
++  DECL_VARIABLE(vsXi_vector2, poly, 64, 2);
++  DECL_VARIABLE(vsXi_vector_res, poly, 64, 1);
++  DECL_VARIABLE(vsXi_vector_res, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vsXi_vector, buffer, , poly, p, 64, 1);
++  VLOAD(vsXi_vector, buffer, q, poly, p, 64, 2);
++
++  VDUP(vsXi_vector2, , poly, p, 64, 1, 2);
++  VDUP(vsXi_vector2, q, poly, p, 64, 2, 3);
++
++  TEST_VSXI(vsli, , poly, p, 64, 1, 3);
++  TEST_VSXI(vsli, q, poly, p, 64, 2, 53);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vsli_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vsli_expected, "");
++
++  /* Test cases with maximum shift amount.  */
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  TEST_VSXI(vsli, , poly, p, 64, 1, 63);
++  TEST_VSXI(vsli, q, poly, p, 64, 2, 63);
++
++#define COMMENT "(max shift amount)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vsli_expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vsli_expected_max_shift, COMMENT);
++
++  /* vsri_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VSRI"
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  VLOAD(vsXi_vector, buffer, , poly, p, 64, 1);
++  VLOAD(vsXi_vector, buffer, q, poly, p, 64, 2);
++
++  VDUP(vsXi_vector2, , poly, p, 64, 1, 2);
++  VDUP(vsXi_vector2, q, poly, p, 64, 2, 3);
++
++  TEST_VSXI(vsri, , poly, p, 64, 1, 3);
++  TEST_VSXI(vsri, q, poly, p, 64, 2, 53);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vsri_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vsri_expected, "");
++
++  /* Test cases with maximum shift amount.  */
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  TEST_VSXI(vsri, , poly, p, 64, 1, 64);
++  TEST_VSXI(vsri, q, poly, p, 64, 2, 64);
++
++#define COMMENT "(max shift amount)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vsri_expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vsri_expected_max_shift, COMMENT);
++
++  /* vst1_lane_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VST1_LANE/VST1_LANEQ"
++
++#define TEST_VST1_LANE(Q, T1, T2, W, N, L)				\
++  VECT_VAR(vst1_lane_vector, T1, W, N) =				\
++    vld1##Q##_##T2##W(VECT_VAR(buffer, T1, W, N));			\
++  vst1##Q##_lane_##T2##W(VECT_VAR(result, T1, W, N),			\
++			 VECT_VAR(vst1_lane_vector, T1, W, N), L);
++
++  DECL_VARIABLE(vst1_lane_vector, poly, 64, 1);
++  DECL_VARIABLE(vst1_lane_vector, poly, 64, 2);
++
++  CLEAN(result, poly, 64, 1);
++  CLEAN(result, poly, 64, 2);
++
++  TEST_VST1_LANE(, poly, p, 64, 1, 0);
++  TEST_VST1_LANE(q, poly, p, 64, 2, 0);
++
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vst1_lane_expected, "");
++  CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vst1_lane_expected, "");
++
++  /* vget_lane_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VGET_LANE/VGETQ_LANE"
++
++#define TEST_VGET_LANE(Q, T1, T2, W, N, L)				   \
++  VECT_VAR(vget_lane_vector, T1, W, N) = vget##Q##_lane_##T2##W(VECT_VAR(vget_lane_vector1, T1, W, N), L); \
++  if (VECT_VAR(vget_lane_vector, T1, W, N) != VECT_VAR(vget_lane_expected, T1, W, N)) {		\
++    fprintf(stderr,							   \
++	    "ERROR in %s (%s line %d in result '%s') at type %s "	   \
++	    "got 0x%" PRIx##W " != 0x%" PRIx##W "\n",			   \
++	    TEST_MSG, __FILE__, __LINE__,				   \
++	    STR(VECT_VAR(vget_lane_expected, T1, W, N)),		   \
++	    STR(VECT_NAME(T1, W, N)),					   \
++	    VECT_VAR(vget_lane_vector, T1, W, N),			   \
++	    VECT_VAR(vget_lane_expected, T1, W, N));			   \
++    abort ();								   \
++  }
++
++  /* Initialize input values.  */
++  DECL_VARIABLE(vget_lane_vector1, poly, 64, 1);
++  DECL_VARIABLE(vget_lane_vector1, poly, 64, 2);
++
++  VLOAD(vget_lane_vector1, buffer,  , poly, p, 64, 1);
++  VLOAD(vget_lane_vector1, buffer, q, poly, p, 64, 2);
++
++  VECT_VAR_DECL(vget_lane_vector, poly, 64, 1);
++  VECT_VAR_DECL(vget_lane_vector, poly, 64, 2);
++
++  TEST_VGET_LANE( , poly, p, 64, 1, 0);
++  TEST_VGET_LANE(q, poly, p, 64, 2, 0);
++
++
++  /* vset_lane_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VSET_LANE/VSETQ_LANE"
++
++#define TEST_VSET_LANE(Q, T1, T2, W, N, V, L)				\
++  VECT_VAR(vset_lane_vector, T1, W, N) =						\
++    vset##Q##_lane_##T2##W(V,						\
++			   VECT_VAR(vset_lane_vector, T1, W, N),			\
++			   L);						\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vset_lane_vector, T1, W, N))
++
++  /* Initialize input values.  */
++  DECL_VARIABLE(vset_lane_vector, poly, 64, 1);
++  DECL_VARIABLE(vset_lane_vector, poly, 64, 2);
++
++  CLEAN(result, uint, 64, 1);
++  CLEAN(result, uint, 64, 2);
++
++  VLOAD(vset_lane_vector, buffer, , poly, p, 64, 1);
++  VLOAD(vset_lane_vector, buffer, q, poly, p, 64, 2);
++
++  /* Choose value and lane arbitrarily.  */
++  TEST_VSET_LANE(, poly, p, 64, 1, 0x88, 0);
++  TEST_VSET_LANE(q, poly, p, 64, 2, 0x11, 1);
++
++  CHECK(TEST_MSG, poly, 64, 1, PRIx64, vset_lane_expected, "");
++  CHECK(TEST_MSG, poly, 64, 2, PRIx64, vset_lane_expected, "");
++
++
++  /* vtst_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VTST"
++  
++#define TEST_VTST1(INSN, Q, T1, T2, W, N)			\
++  VECT_VAR(vtst_vector_res, uint, W, N) =			\
++    INSN##Q##_##T2##W(VECT_VAR(vtst_vector, T1, W, N),		\
++		      VECT_VAR(vtst_vector2, T1, W, N));	\
++    vst1##Q##_u##W(VECT_VAR(result, uint, W, N),		\
++		   VECT_VAR(vtst_vector_res, uint, W, N))
++
++#define TEST_VTST(INSN, Q, T1, T2, W, N)	\
++  TEST_VTST1(INSN, Q, T1, T2, W, N)		\
++
++  /* Initialize input values.  */
++  DECL_VARIABLE(vtst_vector, poly, 64, 1);
++  DECL_VARIABLE(vtst_vector2, poly, 64, 1);
++  DECL_VARIABLE(vtst_vector_res, uint, 64, 1);
++
++  CLEAN(result, uint, 64, 1);
++
++  VLOAD(vtst_vector, buffer,  , poly, p, 64, 1);
++  VDUP(vtst_vector2, , poly, p, 64, 1, 5);
++
++  TEST_VTST(vtst, , poly, p, 64, 1);
++
++  CHECK(TEST_MSG, uint, 64, 1, PRIx64, vtst_expected, "");
++
++  /* vtstq_p64 is supported by aarch64 only.  */
++#ifdef __aarch64__
++  DECL_VARIABLE(vtst_vector, poly, 64, 2);
++  DECL_VARIABLE(vtst_vector2, poly, 64, 2);
++  DECL_VARIABLE(vtst_vector_res, uint, 64, 2);
++  CLEAN(result, uint, 64, 2);
++  VLOAD(vtst_vector, buffer, q, poly, p, 64, 2);
++  VDUP(vtst_vector2, q, poly, p, 64, 2, 5);
++  TEST_VTST(vtst, q, poly, p, 64, 2);
++  CHECK(TEST_MSG, uint, 64, 2, PRIx64, vtst_expected, "");
++
++  /* vmov_n_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VMOV/VMOVQ"
++
++#define TEST_VMOV(Q, T1, T2, W, N)					\
++  VECT_VAR(vmov_n_vector, T1, W, N) =					\
++    vmov##Q##_n_##T2##W(VECT_VAR(buffer_dup, T1, W, N)[i]);		\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vmov_n_vector, T1, W, N))
++
++  DECL_VARIABLE(vmov_n_vector, poly, 64, 1);
++  DECL_VARIABLE(vmov_n_vector, poly, 64, 2);
++
++  /* Try to read different places from the input buffer.  */
++  for (i=0; i< 3; i++) {
++    CLEAN(result, poly, 64, 1);
++    CLEAN(result, poly, 64, 2);
++
++    TEST_VMOV(, poly, p, 64, 1);
++    TEST_VMOV(q, poly, p, 64, 2);
++
++    switch (i) {
++    case 0:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vmov_n_expected0, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vmov_n_expected0, "");
++      break;
++    case 1:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vmov_n_expected1, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vmov_n_expected1, "");
++      break;
++    case 2:
++      CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, vmov_n_expected2, "");
++      CHECK_POLY(TEST_MSG, poly, 64, 2, PRIx64, vmov_n_expected2, "");
++      break;
++    default:
++      abort();
++    }
++  }
++
++  /* vldx_lane_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VLDX_LANE/VLDXQ_LANE"
++
++VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 64, 2);
++VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 64, 3);
++VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 64, 4);
++
++  /* In this case, input variables are arrays of vectors.  */
++#define DECL_VLD_STX_LANE(T1, W, N, X)					\
++  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector, T1, W, N, X);	\
++  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector_src, T1, W, N, X);	\
++  VECT_VAR_DECL(result_bis_##X, T1, W, N)[X * N]
++
++  /* We need to use a temporary result buffer (result_bis), because
++     the one used for other tests is not large enough. A subset of the
++     result data is moved from result_bis to result, and it is this
++     subset which is used to check the actual behavior. The next
++     macro enables to move another chunk of data from result_bis to
++     result.  */
++  /* We also use another extra input buffer (buffer_src), which we
++     fill with 0xAA, and which it used to load a vector from which we
++     read a given lane.  */
++
++#define TEST_VLDX_LANE(Q, T1, T2, W, N, X, L)				\
++  memset (VECT_VAR(buffer_src, T1, W, N), 0xAA,				\
++	  sizeof(VECT_VAR(buffer_src, T1, W, N)));			\
++									\
++  VECT_ARRAY_VAR(vector_src, T1, W, N, X) =				\
++    vld##X##Q##_##T2##W(VECT_VAR(buffer_src, T1, W, N));		\
++									\
++  VECT_ARRAY_VAR(vector, T1, W, N, X) =					\
++    /* Use dedicated init buffer, of size.  X */			\
++    vld##X##Q##_lane_##T2##W(VECT_VAR(buffer_vld##X##_lane, T1, W, X),	\
++			     VECT_ARRAY_VAR(vector_src, T1, W, N, X),	\
++			     L);					\
++  vst##X##Q##_##T2##W(VECT_VAR(result_bis_##X, T1, W, N),		\
++		      VECT_ARRAY_VAR(vector, T1, W, N, X));		\
++  memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis_##X, T1, W, N), \
++	 sizeof(VECT_VAR(result, T1, W, N)))
++
++  /* Overwrite "result" with the contents of "result_bis"[Y].  */
++#undef TEST_EXTRA_CHUNK
++#define TEST_EXTRA_CHUNK(T1, W, N, X, Y)		\
++  memcpy(VECT_VAR(result, T1, W, N),			\
++	 &(VECT_VAR(result_bis_##X, T1, W, N)[Y*N]),	\
++	 sizeof(VECT_VAR(result, T1, W, N)));
++
++  /* Add some padding to try to catch out of bound accesses.  */
++#define ARRAY1(V, T, W, N) VECT_VAR_DECL(V,T,W,N)[1]={42}
++#define DUMMY_ARRAY(V, T, W, N, L) \
++  VECT_VAR_DECL(V,T,W,N)[N*L]={0}; \
++  ARRAY1(V##_pad,T,W,N)
++
++#define DECL_ALL_VLD_STX_LANE(X)     \
++  DECL_VLD_STX_LANE(poly, 64, 1, X); \
++  DECL_VLD_STX_LANE(poly, 64, 2, X);
++
++#define TEST_ALL_VLDX_LANE(X)		  \
++  TEST_VLDX_LANE(, poly, p, 64, 1, X, 0); \
++  TEST_VLDX_LANE(q, poly, p, 64, 2, X, 0);
++
++#define TEST_ALL_EXTRA_CHUNKS(X,Y)	     \
++  TEST_EXTRA_CHUNK(poly, 64, 1, X, Y) \
++  TEST_EXTRA_CHUNK(poly, 64, 2, X, Y)
++
++#define CHECK_RESULTS_VLD_STX_LANE(test_name,EXPECTED,comment)		\
++  CHECK_POLY(test_name, poly, 64, 1, PRIx64, EXPECTED, comment);	\
++  CHECK_POLY(test_name, poly, 64, 2, PRIx64, EXPECTED, comment);
++
++  /* Declare the temporary buffers / variables.  */
++  DECL_ALL_VLD_STX_LANE(2);
++  DECL_ALL_VLD_STX_LANE(3);
++  DECL_ALL_VLD_STX_LANE(4);
++
++  DUMMY_ARRAY(buffer_src, poly, 64, 1, 4);
++  DUMMY_ARRAY(buffer_src, poly, 64, 2, 4);
++
++  /* Check vld2_lane/vld2q_lane.  */
++  clean_results ();
++#undef TEST_MSG
++#define TEST_MSG "VLD2_LANE/VLD2Q_LANE"
++  TEST_ALL_VLDX_LANE(2);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st2_0, " chunk 0");
++
++  TEST_ALL_EXTRA_CHUNKS(2, 1);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st2_1, " chunk 1");
++
++  /* Check vld3_lane/vld3q_lane.  */
++  clean_results ();
++#undef TEST_MSG
++#define TEST_MSG "VLD3_LANE/VLD3Q_LANE"
++  TEST_ALL_VLDX_LANE(3);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st3_0, " chunk 0");
++
++  TEST_ALL_EXTRA_CHUNKS(3, 1);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st3_1, " chunk 1");
++
++  TEST_ALL_EXTRA_CHUNKS(3, 2);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st3_2, " chunk 2");
++
++  /* Check vld4_lane/vld4q_lane.  */
++  clean_results ();
++#undef TEST_MSG
++#define TEST_MSG "VLD4_LANE/VLD4Q_LANE"
++  TEST_ALL_VLDX_LANE(4);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st4_0, " chunk 0");
++
++  TEST_ALL_EXTRA_CHUNKS(4, 1);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st4_1, " chunk 1");
++
++  TEST_ALL_EXTRA_CHUNKS(4, 2);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st4_2, " chunk 2");
++
++  TEST_ALL_EXTRA_CHUNKS(4, 3);
++  CHECK_RESULTS_VLD_STX_LANE (TEST_MSG, expected_vld_st4_3, " chunk 3");
++
++  /* In this case, input variables are arrays of vectors.  */
++#define DECL_VSTX_LANE(T1, W, N, X)					\
++  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector, T1, W, N, X);	\
++  VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector_src, T1, W, N, X);	\
++  VECT_VAR_DECL(result_bis_##X, T1, W, N)[X * N]
++
++  /* We need to use a temporary result buffer (result_bis), because
++     the one used for other tests is not large enough. A subset of the
++     result data is moved from result_bis to result, and it is this
++     subset which is used to check the actual behavior. The next
++     macro enables to move another chunk of data from result_bis to
++     result.  */
++  /* We also use another extra input buffer (buffer_src), which we
++     fill with 0xAA, and which it used to load a vector from which we
++     read a given lane.  */
++#define TEST_VSTX_LANE(Q, T1, T2, W, N, X, L)				 \
++  memset (VECT_VAR(buffer_src, T1, W, N), 0xAA,				 \
++	  sizeof(VECT_VAR(buffer_src, T1, W, N)));			 \
++  memset (VECT_VAR(result_bis_##X, T1, W, N), 0,			 \
++	  sizeof(VECT_VAR(result_bis_##X, T1, W, N)));			 \
++									 \
++  VECT_ARRAY_VAR(vector_src, T1, W, N, X) =				 \
++    vld##X##Q##_##T2##W(VECT_VAR(buffer_src, T1, W, N));		 \
++									 \
++  VECT_ARRAY_VAR(vector, T1, W, N, X) =					 \
++    /* Use dedicated init buffer, of size X.  */			 \
++    vld##X##Q##_lane_##T2##W(VECT_VAR(buffer_vld##X##_lane, T1, W, X),	 \
++			     VECT_ARRAY_VAR(vector_src, T1, W, N, X),	 \
++			     L);					 \
++  vst##X##Q##_lane_##T2##W(VECT_VAR(result_bis_##X, T1, W, N),		 \
++			   VECT_ARRAY_VAR(vector, T1, W, N, X),		 \
++			   L);						 \
++  memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis_##X, T1, W, N), \
++	 sizeof(VECT_VAR(result, T1, W, N)));
++
++#define TEST_ALL_VSTX_LANE(X)		  \
++  TEST_VSTX_LANE(, poly, p, 64, 1, X, 0); \
++  TEST_VSTX_LANE(q, poly, p, 64, 2, X, 0);
++
++  /* Check vst2_lane/vst2q_lane.  */
++  clean_results ();
++#undef TEST_MSG
++#define TEST_MSG "VST2_LANE/VST2Q_LANE"
++  TEST_ALL_VSTX_LANE(2);
++
++#define CMT " (chunk 0)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st2_0, CMT);
++
++  TEST_ALL_EXTRA_CHUNKS(2, 1);
++#undef CMT
++#define CMT " chunk 1"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st2_1, CMT);
++
++  /* Check vst3_lane/vst3q_lane.  */
++  clean_results ();
++#undef TEST_MSG
++#define TEST_MSG "VST3_LANE/VST3Q_LANE"
++  TEST_ALL_VSTX_LANE(3);
++
++#undef CMT
++#define CMT " (chunk 0)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st3_0, CMT);
++
++  TEST_ALL_EXTRA_CHUNKS(3, 1);
++
++#undef CMT
++#define CMT " (chunk 1)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st3_1, CMT);
++
++  TEST_ALL_EXTRA_CHUNKS(3, 2);
++
++#undef CMT
++#define CMT " (chunk 2)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st3_2, CMT);
++
++  /* Check vst4_lane/vst4q_lane.  */
++  clean_results ();
++#undef TEST_MSG
++#define TEST_MSG "VST4_LANE/VST4Q_LANE"
++  TEST_ALL_VSTX_LANE(4);
++
++#undef CMT
++#define CMT " (chunk 0)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st4_0, CMT);
++
++  TEST_ALL_EXTRA_CHUNKS(4, 1);
++
++#undef CMT
++#define CMT " (chunk 1)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st4_1, CMT);
++
++  TEST_ALL_EXTRA_CHUNKS(4, 2);
++
++#undef CMT
++#define CMT " (chunk 2)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st4_2, CMT);
++
++  TEST_ALL_EXTRA_CHUNKS(4, 3);
++
++#undef CMT
++#define CMT " (chunk 3)"
++  CHECK_POLY(TEST_MSG, poly, 64, 1, PRIx64, expected_vld_st4_3, CMT);
++
++#endif /* __aarch64__.  */
++
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc
+@@ -0,0 +1,206 @@
++/* Template file for ternary scalar operator validation.
++
++   This file is meant to be included by test files for binary scalar
++   operations.  */
++
++/* Check for required settings.  */
++
++#ifndef INSN_NAME
++#error INSN_NAME (the intrinsic to test) must be defined.
++#endif
++
++#ifndef INPUT_TYPE
++#error INPUT_TYPE (basic type of an input value) must be defined.
++#endif
++
++#ifndef OUTPUT_TYPE
++#error OUTPUT_TYPE (basic type of an output value) must be defined.
++#endif
++
++#ifndef OUTPUT_TYPE_SIZE
++#error OUTPUT_TYPE_SIZE (size in bits of an output value) must be defined.
++#endif
++
++/* Optional settings:
++
++   INPUT_1: Input values for the first parameter.  Must be of type INPUT_TYPE.
++   INPUT_2: Input values for the second parameter.  Must be of type INPUT_TYPE.
++   INPUT_3: Input values for the third parameter.  Must be of type
++   INPUT_TYPE.  */
++
++#ifndef TEST_MSG
++#define TEST_MSG "unnamed test"
++#endif
++
++/* The test framework.  */
++
++#include <stdio.h>
++
++extern void abort ();
++
++#define INFF __builtin_inf ()
++
++/* Stringify a macro.  */
++#define STR0(A) #A
++#define STR(A) STR0 (A)
++
++/* Macro concatenation.  */
++#define CAT0(A, B) A##B
++#define CAT(A, B) CAT0 (A, B)
++
++/* Format strings for error reporting.  */
++#define FMT16 "0x%04x"
++#define FMT32 "0x%08x"
++#define FMT CAT (FMT,OUTPUT_TYPE_SIZE)
++
++/* Type construction: forms TS_t, where T is the base type and S the size in
++   bits.  */
++#define MK_TYPE0(T, S) T##S##_t
++#define MK_TYPE(T, S) MK_TYPE0 (T, S)
++
++/* Convenience types for input and output data.  */
++typedef MK_TYPE (uint, OUTPUT_TYPE_SIZE) output_hex_type;
++
++/* Conversion between typed values and their hexadecimal representation.  */
++typedef union
++{
++  OUTPUT_TYPE value;
++  output_hex_type hex;
++} output_conv_type;
++
++/* Default input values.  */
++
++float16_t input_1_float16_t[] =
++{
++  0.0,
++  -0.0,
++  2.0,
++  3.1,
++  20.0,
++  0.40,
++  -2.3,
++  1.33,
++  -7.6,
++  0.31,
++  0.3353,
++  0.5,
++  1.0,
++  13.13,
++  -6.3,
++  20.0,
++  (float16_t)INFF,
++  (float16_t)-INFF,
++};
++
++float16_t input_2_float16_t[] =
++{
++  1.0,
++  1.0,
++  -4.33,
++  100.0,
++  30.0,
++  -0.02,
++  0.5,
++  -7.231,
++  -6.3,
++  20.0,
++  -7.231,
++  2.3,
++  -7.6,
++  5.1,
++  0.31,
++  0.33353,
++  (float16_t)-INFF,
++  (float16_t)INFF,
++};
++
++float16_t input_3_float16_t[] =
++{
++  -0.0,
++  0.0,
++  0.31,
++  -0.31,
++  1.31,
++  2.1,
++  -6.3,
++  1.0,
++  -1.5,
++  5.1,
++  0.3353,
++  9.3,
++  -9.3,
++  -7.231,
++  0.5,
++  -0.33,
++  (float16_t)INFF,
++  (float16_t)INFF,
++};
++
++#ifndef INPUT_1
++#define INPUT_1 CAT (input_1_,INPUT_TYPE)
++#endif
++
++#ifndef INPUT_2
++#define INPUT_2 CAT (input_2_,INPUT_TYPE)
++#endif
++
++#ifndef INPUT_3
++#define INPUT_3 CAT (input_3_,INPUT_TYPE)
++#endif
++
++/* Support macros and routines for the test function.  */
++
++#define CHECK()							\
++  {								\
++    output_conv_type actual;					\
++    output_conv_type expect;					\
++								\
++    expect.hex = ((output_hex_type*)EXPECTED)[index];		\
++    actual.value = INSN_NAME ((INPUT_1)[index],			\
++			      (INPUT_2)[index],			\
++			      (INPUT_3)[index]);		\
++								\
++    if (actual.hex != expect.hex)				\
++      {								\
++	fprintf (stderr,					\
++		 "ERROR in %s (%s line %d), buffer %s, "	\
++		 "index %d: got "				\
++		 FMT " != " FMT "\n",				\
++		 TEST_MSG, __FILE__, __LINE__,			\
++		 STR (EXPECTED), index,				\
++		 actual.hex, expect.hex);			\
++	abort ();						\
++      }								\
++    fprintf (stderr, "CHECKED %s %s\n",				\
++	     STR (EXPECTED), TEST_MSG);				\
++  }
++
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1 (NAME)
++
++/* The test function.  */
++
++void
++FNNAME (INSN_NAME) (void)
++{
++  /* Basic test: y[i] = OP (x[i]), for each INPUT[i], then compare the result
++     against EXPECTED[i].  */
++
++  const int num_tests = sizeof (INPUT_1) / sizeof (INPUT_1[0]);
++  int index;
++
++  for (index = 0; index < num_tests; index++)
++    CHECK ();
++
++#ifdef EXTRA_TESTS
++  EXTRA_TESTS ();
++#endif
++}
++
++int
++main (void)
++{
++  FNNAME (INSN_NAME) ();
++
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc
+@@ -61,11 +61,11 @@ void FNNAME (INSN_NAME) (void)
+   TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 32, 4, expected_cumulative_sat, "");
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, int, 16, 4, PRIx8, expected, "");
+-  CHECK(TEST_MSG, int, 32, 2, PRIx8, expected, "");
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
++  CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+-  CHECK(TEST_MSG, int, 16, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, int, 32, 4, PRIx8, expected, "");
++  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
++  CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ 
+ #ifdef EXTRA_TESTS
+   EXTRA_TESTS();
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc
+@@ -0,0 +1,200 @@
++/* Template file for unary scalar operator validation.
++
++   This file is meant to be included by test files for unary scalar
++   operations.  */
++
++/* Check for required settings.  */
++
++#ifndef INSN_NAME
++#error INSN_NAME (the intrinsic to test) must be defined.
++#endif
++
++#ifndef INPUT_TYPE
++#error INPUT_TYPE (basic type of an input value) must be defined.
++#endif
++
++#ifndef SCALAR_OPERANDS
++#ifndef EXPECTED
++#error EXPECTED (an array of expected output values) must be defined.
++#endif
++#endif
++
++#ifndef OUTPUT_TYPE
++#error OUTPUT_TYPE (basic type of an output value) must be defined.
++#endif
++
++#ifndef OUTPUT_TYPE_SIZE
++#error OUTPUT_TYPE_SIZE (size in bits of an output value) must be defined.
++#endif
++
++/* Optional settings.  */
++
++/* SCALAR_OPERANDS: Defined iff the intrinsic has a scalar operand.
++
++   SCALAR_1, SCALAR_2, .., SCALAR_4: If SCALAR_OPERANDS is defined, SCALAR_<n>
++   is the scalar and EXPECTED_<n> is array of expected values.
++
++   INPUT: Input values for the first parameter.  Must be of type INPUT_TYPE.  */
++
++/* Additional comments for the error message.  */
++#ifndef COMMENT
++#define COMMENT ""
++#endif
++
++#ifndef TEST_MSG
++#define TEST_MSG "unnamed test"
++#endif
++
++/* The test framework.  */
++
++#include <stdio.h>
++
++extern void abort ();
++
++#define INFF __builtin_inf ()
++
++/* Stringify a macro.  */
++#define STR0(A) #A
++#define STR(A) STR0 (A)
++
++/* Macro concatenation.  */
++#define CAT0(A, B) A##B
++#define CAT(A, B) CAT0 (A, B)
++
++/* Format strings for error reporting.  */
++#define FMT16 "0x%04x"
++#define FMT32 "0x%08x"
++#define FMT64 "0x%016x"
++#define FMT CAT (FMT,OUTPUT_TYPE_SIZE)
++
++/* Type construction: forms TS_t, where T is the base type and S the size in
++   bits.  */
++#define MK_TYPE0(T, S) T##S##_t
++#define MK_TYPE(T, S) MK_TYPE0 (T, S)
++
++/* Convenience types for input and output data.  */
++typedef MK_TYPE (uint, OUTPUT_TYPE_SIZE) output_hex_type;
++
++/* Conversion between typed values and their hexadecimal representation.  */
++typedef union
++{
++  OUTPUT_TYPE value;
++  output_hex_type hex;
++} output_conv_type;
++
++/* Default input values.  */
++
++float16_t input_1_float16_t[] =
++{
++  0.0, -0.0,
++  2.0, 3.1,
++  20.0, 0.40,
++  -2.3, 1.33,
++  -7.6, 0.31,
++  0.3353, 0.5,
++  1.0, 13.13,
++  -6.3, 20.0,
++  (float16_t)INFF, (float16_t)-INFF,
++};
++
++#ifndef INPUT
++#define INPUT CAT(input_1_,INPUT_TYPE)
++#endif
++
++/* Support macros and routines for the test function.  */
++
++#define CHECK()							\
++  {								\
++    output_conv_type actual;					\
++    output_conv_type expect;					\
++								\
++    expect.hex = ((output_hex_type*)EXPECTED)[index];		\
++    actual.value = INSN_NAME ((INPUT)[index]);			\
++								\
++    if (actual.hex != expect.hex)				\
++      {								\
++	fprintf (stderr,					\
++		 "ERROR in %s (%s line %d), buffer %s, "	\
++		 "index %d: got "				\
++		 FMT " != " FMT "\n",				\
++		 TEST_MSG, __FILE__, __LINE__,			\
++		 STR (EXPECTED), index,				\
++		 actual.hex, expect.hex);			\
++	abort ();						\
++      }								\
++    fprintf (stderr, "CHECKED %s %s\n",				\
++	     STR (EXPECTED), TEST_MSG);				\
++  }
++
++#define CHECK_N(SCALAR, EXPECTED)				\
++  {								\
++    output_conv_type actual;					\
++    output_conv_type expect;					\
++								\
++    expect.hex							\
++      = ((output_hex_type*)EXPECTED)[index];			\
++    actual.value = INSN_NAME ((INPUT)[index], (SCALAR));	\
++								\
++    if (actual.hex != expect.hex)				\
++      {								\
++	fprintf (stderr,					\
++		 "ERROR in %s (%s line %d), buffer %s, "	\
++		 "index %d: got "				\
++		 FMT " != " FMT "\n",				\
++		 TEST_MSG, __FILE__, __LINE__,			\
++		 STR (EXPECTED), index,				\
++		 actual.hex, expect.hex);			\
++	abort ();						\
++      }								\
++    fprintf (stderr, "CHECKED %s %s\n",				\
++	     STR (EXPECTED), TEST_MSG);				\
++  }
++
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1 (NAME)
++
++/* The test function.  */
++
++void
++FNNAME (INSN_NAME) (void)
++{
++  /* Basic test: y[i] = OP (x[i]), for each INPUT[i], then compare the result
++     against EXPECTED[i].  */
++
++  const int num_tests = sizeof (INPUT) / sizeof (INPUT[0]);
++  int index;
++
++  for (index = 0; index < num_tests; index++)
++    {
++#if defined (SCALAR_OPERANDS)
++
++#ifdef SCALAR_1
++      CHECK_N (SCALAR_1, EXPECTED_1);
++#endif
++#ifdef SCALAR_2
++      CHECK_N (SCALAR_2, EXPECTED_2);
++#endif
++#ifdef SCALAR_3
++      CHECK_N (SCALAR_3, EXPECTED_3);
++#endif
++#ifdef SCALAR_4
++      CHECK_N (SCALAR_4, EXPECTED_4);
++#endif
++
++#else /* !defined (SCALAR_OPERAND).  */
++      CHECK ();
++#endif
++    }
++
++#ifdef EXTRA_TESTS
++  EXTRA_TESTS ();
++#endif
++}
++
++int
++main (void)
++{
++  FNNAME (INSN_NAME) ();
++
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabd.c
+@@ -30,10 +30,20 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffd0, 0xffffffd1,
+ 					 0xffffffd2, 0xffffffd3 };
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x42407ae1, 0x423c7ae1,
+ 					   0x42387ae1, 0x42347ae1 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0x4e13, 0x4dd3,
++					      0x4d93, 0x4d53 };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0x5204, 0x51e4, 0x51c4, 0x51a4,
++					      0x5184, 0x5164, 0x5144, 0x5124 };
++#endif
+ 
+ /* Additional expected results for float32 variants with specially
+    chosen input values.  */
+ VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						      0x0, 0x0, 0x0, 0x0 };
++#endif
+ 
+ #define TEST_MSG "VABD/VABDQ"
+ void exec_vabd (void)
+@@ -65,6 +75,17 @@ void exec_vabd (void)
+   DECL_VABD_VAR(vector2);
+   DECL_VABD_VAR(vector_res);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector1, float, 16, 4);
++  DECL_VARIABLE(vector1, float, 16, 8);
++
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++
+   clean_results ();
+ 
+   /* Initialize input "vector1" from "buffer".  */
+@@ -82,6 +103,12 @@ void exec_vabd (void)
+   VLOAD(vector1, buffer, q, uint, u, 16, 8);
+   VLOAD(vector1, buffer, q, uint, u, 32, 4);
+   VLOAD(vector1, buffer, q, float, f, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector1, buffer, , float, f, 16, 4);
++  VLOAD(vector1, buffer, , float, f, 16, 4);
++  VLOAD(vector1, buffer, q, float, f, 16, 8);
++  VLOAD(vector1, buffer, q, float, f, 16, 8);
++#endif
+ 
+   /* Choose init value arbitrarily.  */
+   VDUP(vector2, , int, s, 8, 8, 1);
+@@ -98,6 +125,10 @@ void exec_vabd (void)
+   VDUP(vector2, q, uint, u, 16, 8, 12);
+   VDUP(vector2, q, uint, u, 32, 4, 32);
+   VDUP(vector2, q, float, f, 32, 4, 32.12f);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 8.3f);
++  VDUP(vector2, q, float, f, 16, 8, 32.12f);
++#endif
+ 
+   /* Execute the tests.  */
+   TEST_VABD(, int, s, 8, 8);
+@@ -115,6 +146,11 @@ void exec_vabd (void)
+   TEST_VABD(q, uint, u, 32, 4);
+   TEST_VABD(q, float, f, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VABD(, float, f, 16, 4);
++  TEST_VABD(q, float, f, 16, 8);
++#endif
++
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+@@ -129,7 +165,10 @@ void exec_vabd (void)
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+-
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
+ 
+   /* Extra FP tests with special values (-0.0, ....) */
+   VDUP(vector1, q, float, f, 32, 4, -0.0f);
+@@ -137,11 +176,27 @@ void exec_vabd (void)
+   TEST_VABD(q, float, f, 32, 4);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, " FP special (-0.0)");
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector1, q, float, f, 16, 8, -0.0f);
++  VDUP(vector2, q, float, f, 16, 8, 0.0);
++  TEST_VABD(q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16,
++	   " FP special (-0.0)");
++#endif
++
+   /* Extra FP tests with special values (-0.0, ....) */
+   VDUP(vector1, q, float, f, 32, 4, 0.0f);
+   VDUP(vector2, q, float, f, 32, 4, -0.0);
+   TEST_VABD(q, float, f, 32, 4);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, " FP special (-0.0)");
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector1, q, float, f, 16, 8, 0.0f);
++  VDUP(vector2, q, float, f, 16, 8, -0.0);
++  TEST_VABD(q, float, f, 16, 8);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16,
++	   " FP special (-0.0)");
++#endif
+ }
+ 
+ int main (void)
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c
+@@ -0,0 +1,44 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++#define INFF __builtin_inf ()
++
++/* Expected results.
++   Absolute difference between INPUT1 and INPUT2 in binary_scalar_op.inc.  */
++uint16_t expected[] =
++{
++  0x3C00,
++  0x3C00,
++  0x4654,
++  0x560E,
++  0x4900,
++  0x36B8,
++  0x419a,
++  0x4848,
++  0x3d34,
++  0x4cec,
++  0x4791,
++  0x3f34,
++  0x484d,
++  0x4804,
++  0x469c,
++  0x4ceb,
++  0x7c00,
++  0x7c00
++};
++
++#define TEST_MSG "VABDH_F16"
++#define INSN_NAME vabdh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabs.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabs.c
+@@ -21,24 +21,52 @@ VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd };
+ /* Expected results for float32 variants. Needs to be separated since
+    the generic test function does not test floating-point
+    versions.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_float16, hfloat, 16, 4) [] = { 0x409a, 0x409a,
++						      0x409a, 0x409a };
++VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0x42cd, 0x42cd,
++						      0x42cd, 0x42cd,
++						      0x42cd, 0x42cd,
++						      0x42cd, 0x42cd };
++#endif
+ VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0x40133333, 0x40133333 };
+ VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0x4059999a, 0x4059999a,
+ 						   0x4059999a, 0x4059999a };
+ 
+ void exec_vabs_f32(void)
+ {
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+   DECL_VARIABLE(vector_res, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, -2.3f);
++  VDUP(vector, q, float, f, 16, 8, 3.4f);
++#endif
+   VDUP(vector, , float, f, 32, 2, -2.3f);
+   VDUP(vector, q, float, f, 32, 4, 3.4f);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_UNARY_OP(INSN_NAME, , float, f, 16, 4);
++  TEST_UNARY_OP(INSN_NAME, q, float, f, 16, 8);
++#endif
+   TEST_UNARY_OP(INSN_NAME, , float, f, 32, 2);
+   TEST_UNARY_OP(INSN_NAME, q, float, f, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_float16, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, "");
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4233 /* 3.099609 */,
++  0x4d00 /* 20.000000 */,
++  0x3666 /* 0.399902 */,
++  0x409a /* 2.300781 */,
++  0x3d52 /* 1.330078 */,
++  0x479a /* 7.601562 */,
++  0x34f6 /* 0.310059 */,
++  0x355d /* 0.335205 */,
++  0x3800 /* 0.500000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a91 /* 13.132812 */,
++  0x464d /* 6.300781 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */
++};
++
++#define TEST_MSG "VABSH_F16"
++#define INSN_NAME vabsh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vadd.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vadd.c
+@@ -43,6 +43,14 @@ VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff3,
+ VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0x40d9999a, 0x40d9999a };
+ VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0x41100000, 0x41100000,
+ 						   0x41100000, 0x41100000 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_float16, hfloat, 16, 4) [] = { 0x46cd, 0x46cd,
++						      0x46cd, 0x46cd };
++VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0x4880, 0x4880,
++						      0x4880, 0x4880,
++						      0x4880, 0x4880,
++						      0x4880, 0x4880 };
++#endif
+ 
+ void exec_vadd_f32(void)
+ {
+@@ -66,4 +74,27 @@ void exec_vadd_f32(void)
+ 
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, "");
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++
++  VDUP(vector, , float, f, 16, 4, 2.3f);
++  VDUP(vector, q, float, f, 16, 8, 3.4f);
++
++  VDUP(vector2, , float, f, 16, 4, 4.5f);
++  VDUP(vector2, q, float, f, 16, 8, 5.6f);
++
++  TEST_BINARY_OP(INSN_NAME, , float, f, 16, 4);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_float16, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, "");
++#endif
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc0a8 /* -2.328125 */,
++  0x5672 /* 103.125000 */,
++  0x5240 /* 50.000000 */,
++  0x3614 /* 0.379883 */,
++  0xbf34 /* -1.800781 */,
++  0xc5e6 /* -5.898438 */,
++  0xcaf4 /* -13.906250 */,
++  0x4d14 /* 20.312500 */,
++  0xc6e5 /* -6.894531 */,
++  0x419a /* 2.800781 */,
++  0xc69a /* -6.601562 */,
++  0x4c8f /* 18.234375 */,
++  0xc5fe /* -5.992188 */,
++  0x4d15 /* 20.328125 */,
++  0x7e00 /* nan */,
++  0x7e00 /* nan */,
++};
++
++#define TEST_MSG "VADDH_F16"
++#define INSN_NAME vaddh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbsl.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbsl.c
+@@ -16,6 +16,10 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffff1 };
+ VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
+ 					0xf7, 0xf7, 0xf7, 0xf7 };
+ VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0xfff0, 0xfff2, 0xfff2 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc09, 0xcb89,
++					       0xcb09, 0xca89 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800004, 0xc1700004 };
+ VECT_VAR_DECL(expected,int,8,16) [] = { 0xf2, 0xf2, 0xf2, 0xf2,
+ 					0xf6, 0xf6, 0xf6, 0xf6,
+@@ -43,6 +47,12 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
+ 					 0xf7, 0xf7, 0xf7, 0xf7 };
+ VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff0, 0xfff2, 0xfff2,
+ 					 0xfff4, 0xfff4, 0xfff6, 0xfff6 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc09, 0xcb89,
++					       0xcb09, 0xca89,
++					       0xca09, 0xc989,
++					       0xc909, 0xc889 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800001, 0xc1700001,
+ 					   0xc1600001, 0xc1500001 };
+ 
+@@ -66,6 +76,10 @@ void exec_vbsl (void)
+   clean_results ();
+ 
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+@@ -80,6 +94,9 @@ void exec_vbsl (void)
+   VDUP(vector2, , uint, u, 16, 4, 0xFFF2);
+   VDUP(vector2, , uint, u, 32, 2, 0xFFFFFFF0);
+   VDUP(vector2, , uint, u, 64, 1, 0xFFFFFFF3);
++#if defined (FP16_SUPPORTED)
++  VDUP(vector2, , float, f, 16, 4, -2.4f);   /* -2.4f is 0xC0CD.  */
++#endif
+   VDUP(vector2, , float, f, 32, 2, -30.3f);
+   VDUP(vector2, , poly, p, 8, 8, 0xF3);
+   VDUP(vector2, , poly, p, 16, 4, 0xFFF2);
+@@ -94,6 +111,9 @@ void exec_vbsl (void)
+   VDUP(vector2, q, uint, u, 64, 2, 0xFFFFFFF3);
+   VDUP(vector2, q, poly, p, 8, 16, 0xF3);
+   VDUP(vector2, q, poly, p, 16, 8, 0xFFF2);
++#if defined (FP16_SUPPORTED)
++  VDUP(vector2, q, float, f, 16, 8, -2.4f);
++#endif
+   VDUP(vector2, q, float, f, 32, 4, -30.4f);
+ 
+   VDUP(vector_first, , uint, u, 8, 8, 0xF4);
+@@ -111,10 +131,18 @@ void exec_vbsl (void)
+   TEST_VBSL(uint, , poly, p, 16, 4);
+   TEST_VBSL(uint, q, poly, p, 8, 16);
+   TEST_VBSL(uint, q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VBSL(uint, , float, f, 16, 4);
++  TEST_VBSL(uint, q, float, f, 16, 8);
++#endif
+   TEST_VBSL(uint, , float, f, 32, 2);
+   TEST_VBSL(uint, q, float, f, 32, 4);
+ 
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS (TEST_MSG, "");
++#else
+   CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
++#endif
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c
+@@ -11,3 +11,13 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ 					  0xffffffff, 0xffffffff };
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, uint, 16, 4) [] = { 0xffff, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected, uint, 16, 8) [] = { 0xffff, 0xffff, 0xffff, 0x0,
++					     0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected2, uint, 16, 4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL (expected2, uint, 16, 8) [] = { 0xffff, 0xffff, 0xffff, 0xffff,
++					      0xffff, 0xffff, 0xffff, 0x0 };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0x0, 0x0, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
++			0xFFFF};
++
++#define TEST_MSG "VCAGEH_F16"
++#define INSN_NAME vcageh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c
+@@ -11,3 +11,13 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ 					  0xffffffff, 0xffffffff };
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected, uint, 16, 8) [] = { 0xffff, 0xffff, 0x0, 0x0,
++					     0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected2, uint, 16, 4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL (expected2, uint, 16, 8) [] = { 0xffff, 0xffff, 0xffff, 0xffff,
++					      0xffff, 0xffff, 0x0, 0x0 };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c
+@@ -0,0 +1,21 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0x0, 0x0, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0};
++
++#define TEST_MSG "VCAGTH_F16"
++#define INSN_NAME vcagth_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c
+@@ -9,3 +9,13 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0xffffffff };
+ 
+ VECT_VAR_DECL(expected2,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, uint, 16, 4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL (expected, uint, 16, 8) [] = { 0x0, 0x0, 0xffff, 0xffff,
++					     0xffff, 0xffff, 0xffff, 0xffff };
++
++VECT_VAR_DECL (expected2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected2, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++					      0x0, 0x0, 0xffff, 0xffff };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0,
++			0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0,
++			0x0, 0xFFFF, 0xFFFF};
++
++#define TEST_MSG "VCALEH_F16"
++#define INSN_NAME vcaleh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c
+@@ -9,3 +9,13 @@ VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0x0, 0xffffffff };
+ 
+ VECT_VAR_DECL(expected2,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, uint, 16, 4) [] = { 0x0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL (expected, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0xffff,
++					     0xffff, 0xffff, 0xffff, 0xffff };
++
++VECT_VAR_DECL (expected2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected2, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++					      0x0, 0x0, 0x0, 0xffff };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0,
++			0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0x0,
++			0x0, 0x0, 0x0};
++
++#define TEST_MSG "VCALTH_F16"
++#define INSN_NAME vcalth_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceq.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceq.c
+@@ -32,6 +32,12 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 						0x0, 0x0, 0xffff, 0x0 };
+ VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0x0 };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0xffff, 0x0, 0x0 };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, 0xffff, 0x0,
++						     0x0, 0x0, 0x0, 0x0, };
++#endif
++
+ VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0x0, 0xffffffff };
+ VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0x0 };
+ 
+@@ -39,6 +45,18 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0xffffffff, 0x0 };
+ VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0x0, 0xffffffff };
+ VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0xffffffff, 0x0 };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++#endif
++
+ VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 };
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c
+@@ -0,0 +1,21 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++			0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
++
++#define TEST_MSG "VCEQH_F16"
++#define INSN_NAME vceqh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqz_1.c
+@@ -0,0 +1,27 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#define INSN_NAME vceqz
++#define TEST_MSG "VCEQZ/VCEQZQ"
++
++#include "cmp_zero_op.inc"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						     0x0, 0x0, 0x0, 0x0 };
++#endif
++
++/* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c
+@@ -0,0 +1,21 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
++			0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
++
++#define TEST_MSG "VCEQZH_F16"
++#define INSN_NAME vceqzh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcge.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcge.c
+@@ -28,6 +28,14 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 						0, 0x0, 0xffff, 0xffff };
+ VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0xffffffff };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff };
++#endif
++
+ VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0x0, 0xffffffff };
+ VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0xffffffff };
+ 
+@@ -35,6 +43,20 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0x0, 0xffffffff };
+ VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++#endif
++
+ VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 };
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0x0, 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF,
++			0xFFFF, 0x0};
++
++#define TEST_MSG "VCGEH_F16"
++#define INSN_NAME vcgeh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgez_1.c
+@@ -0,0 +1,30 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#define INSN_NAME vcgez
++#define TEST_MSG "VCGEZ/VCGEZQ"
++
++#include "cmp_zero_op.inc"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0xffff, 0xffff,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff };
++#endif
++
++/* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						 0xffff, 0xffff };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0,
++			0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
++			0x0, 0xFFFF, 0xFFFF, 0x0};
++
++#define TEST_MSG "VCGEZH_F16"
++#define INSN_NAME vcgezh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgt.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgt.c
+@@ -28,6 +28,14 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 						0x0, 0x0, 0x0, 0xffff };
+ VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0x0, 0x0, 0x0, 0xffffffff };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0xffff, 0xffff };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0,
++						     0x0, 0xffff,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff };
++#endif
++
+ VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0x0, 0x0, 0x0, 0xffffffff };
+ 
+@@ -35,6 +43,19 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0x0, 0xffffffff };
+ VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0x0, 0xffffffff };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++#endif
++
+ VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 };
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0x0, 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF,
++			0xFFFF, 0x0};
++
++#define TEST_MSG "VCGTH_F16"
++#define INSN_NAME vcgth_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtz_1.c
+@@ -0,0 +1,28 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#define INSN_NAME vcgtz
++#define TEST_MSG "VCGTZ/VCGTZQ"
++
++#include "cmp_zero_op.inc"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0xffff, 0xffff,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff,
++						     0xffff, 0xffff };
++#endif
++
++/* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						 0xffff, 0xffff };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x0,
++			0xFFFF, 0xFFFF, 0x0};
++
++#define TEST_MSG "VCGTZH_F16"
++#define INSN_NAME vcgtzh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcle.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcle.c
+@@ -31,6 +31,14 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff,
+ VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ 						0xffffffff, 0x0 };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0xffff, 0xffff, 0x0, 0x0 };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0xffff, 0xffff,
++						     0xffff, 0x0,
++						     0x0, 0x0,
++						     0x0, 0x0 };
++#endif
++
+ VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ 						 0xffffffff, 0x0 };
+@@ -39,6 +47,20 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0xffffffff, 0x0 };
+ VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0xffffffff, 0x0 };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						 0xffff, 0xffff };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++#endif
++
+ VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 };
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0x0,
++			0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF, 0x0, 0x0,
++			0xFFFF};
++
++#define TEST_MSG "VCLEH_F16"
++#define INSN_NAME vcleh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclez_1.c
+@@ -0,0 +1,29 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#define INSN_NAME vclez
++#define TEST_MSG "VCLEZ/VCLEZQ"
++
++#include "cmp_zero_op.inc"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0 };
++#endif
++
++/* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c
+@@ -0,0 +1,21 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF};
++
++#define TEST_MSG "VCLEZH_F16"
++#define INSN_NAME vclezh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclt.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclt.c
+@@ -30,6 +30,14 @@ VECT_VAR_DECL(expected_q_uint,uint,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff,
+ VECT_VAR_DECL(expected_q_uint,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ 						0x0, 0x0 };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0xffff, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0xffff, 0xffff,
++						     0x0, 0x0,
++						     0x0, 0x0,
++						     0x0, 0x0 };
++#endif
++
+ VECT_VAR_DECL(expected_float,uint,32,2) [] = { 0xffffffff, 0x0 };
+ VECT_VAR_DECL(expected_q_float,uint,32,4) [] = { 0xffffffff, 0xffffffff,
+ 						 0x0, 0x0 };
+@@ -38,6 +46,19 @@ VECT_VAR_DECL(expected_uint2,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_uint3,uint,32,2) [] = { 0xffffffff, 0x0 };
+ VECT_VAR_DECL(expected_uint4,uint,32,2) [] = { 0x0, 0x0 };
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_nan2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						 0xffff, 0xffff };
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf2, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++#endif
++
+ VECT_VAR_DECL(expected_nan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_mnan,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_nan2,uint,32,2) [] = { 0x0, 0x0 };
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0x0,
++			0xFFFF, 0xFFFF, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF, 0x0, 0x0,
++			0xFFFF};
++
++#define TEST_MSG "VCLTH_F16"
++#define INSN_NAME vclth_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltz_1.c
+@@ -0,0 +1,27 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#define INSN_NAME vcltz
++#define TEST_MSG "VCLTZ/VCLTZQ"
++
++#include "cmp_zero_op.inc"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0xffff, 0xffff,
++						   0xffff, 0xffff };
++VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0 };
++#endif
++
++/* Extra FP tests with special values (NaN, ....).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
++VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++
++VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0xffff, 0xffff,
++						  0xffff, 0xffff };
++VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c
+@@ -0,0 +1,21 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0x0, 0xFFFF,
++			0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFF, 0x0, 0x0, 0xFFFF};
++
++#define TEST_MSG "VCltZH_F16"
++#define INSN_NAME vcltzh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcnt.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcnt.c
+@@ -65,10 +65,10 @@ FNNAME (INSN_NAME)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcombine.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcombine.c
+@@ -93,8 +93,8 @@ void exec_vcombine (void)
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+   CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
+ #endif
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcreate.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcreate.c
+@@ -106,8 +106,8 @@ FNNAME (INSN_NAME)
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+   CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
+ #endif
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt.c
+@@ -4,36 +4,99 @@
+ #include <math.h>
+ 
+ /* Expected results for vcvt.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_s, hfloat, 16, 4) [] =
++{ 0xcc00, 0xcb80, 0xcb00, 0xca80 };
++VECT_VAR_DECL(expected_u, hfloat, 16, 4) [] =
++{ 0x7c00, 0x7c00, 0x7c00, 0x7c00, };
++VECT_VAR_DECL(expected_s, hfloat, 16, 8) [] =
++{ 0xcc00, 0xcb80, 0xcb00, 0xca80,
++  0xca00, 0xc980, 0xc900, 0xc880 };
++VECT_VAR_DECL(expected_u, hfloat, 16, 8) [] =
++{ 0x7c00, 0x7c00, 0x7c00, 0x7c00,
++  0x7c00, 0x7c00, 0x7c00, 0x7c00, };
++#endif
+ VECT_VAR_DECL(expected_s,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected_u,hfloat,32,2) [] = { 0x4f800000, 0x4f800000 };
+ VECT_VAR_DECL(expected_s,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+-					   0xc1600000, 0xc1500000 };
++					     0xc1600000, 0xc1500000 };
+ VECT_VAR_DECL(expected_u,hfloat,32,4) [] = { 0x4f800000, 0x4f800000,
+-					   0x4f800000, 0x4f800000 };
++					     0x4f800000, 0x4f800000 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, int, 16, 4) [] = { 0xfff1, 0x5, 0xfff1, 0x5 };
++VECT_VAR_DECL(expected, uint, 16, 4) [] = { 0x0, 0x5, 0x0, 0x5 };
++VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x0, 0x0, 0xf, 0xfff1,
++					   0x0, 0x0, 0xf, 0xfff1 };
++VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0x0, 0x0, 0xf, 0x0,
++					    0x0, 0x0, 0xf, 0x0 };
++#endif
+ VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0x5 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0x0, 0x5 };
+ VECT_VAR_DECL(expected,int,32,4) [] = { 0x0, 0x0, 0xf, 0xfffffff1 };
+ VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0xf, 0x0 };
+ 
+ /* Expected results for vcvt_n.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_vcvt_n_s, hfloat, 16, 4) [] = { 0xc400, 0xc380,
++						       0xc300, 0xc280 };
++VECT_VAR_DECL(expected_vcvt_n_u, hfloat, 16, 4) [] = { 0x6000, 0x6000,
++						       0x6000, 0x6000 };
++VECT_VAR_DECL(expected_vcvt_n_s, hfloat, 16, 8) [] = { 0xb000, 0xaf80,
++						       0xaf00, 0xae80,
++						       0xae00, 0xad80,
++						       0xad00, 0xac80 };
++VECT_VAR_DECL(expected_vcvt_n_u, hfloat, 16, 8) [] = { 0x4c00, 0x4c00,
++						       0x4c00, 0x4c00,
++						       0x4c00, 0x4c00,
++						       0x4c00, 0x4c00 };
++#endif
+ VECT_VAR_DECL(expected_vcvt_n_s,hfloat,32,2) [] = { 0xc0800000, 0xc0700000 };
+ VECT_VAR_DECL(expected_vcvt_n_u,hfloat,32,2) [] = { 0x4c000000, 0x4c000000 };
+ VECT_VAR_DECL(expected_vcvt_n_s,hfloat,32,4) [] = { 0xb2800000, 0xb2700000,
+ 						  0xb2600000, 0xb2500000 };
+ VECT_VAR_DECL(expected_vcvt_n_u,hfloat,32,4) [] = { 0x49800000, 0x49800000,
+ 						  0x49800000, 0x49800000 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_vcvt_n, int, 16, 4) [] = { 0xffc3, 0x15,
++						  0xffc3, 0x15 };
++VECT_VAR_DECL(expected_vcvt_n, uint, 16, 4) [] = { 0x0, 0x2a6, 0x0, 0x2a6 };
++VECT_VAR_DECL(expected_vcvt_n, int, 16, 8) [] = { 0x0, 0x0, 0x78f, 0xf871,
++						  0x0, 0x0, 0x78f, 0xf871 };
++VECT_VAR_DECL(expected_vcvt_n, uint, 16, 8) [] = { 0x0, 0x0, 0xf1e0, 0x0,
++						   0x0, 0x0, 0xf1e0, 0x0 };
++#endif
+ VECT_VAR_DECL(expected_vcvt_n,int,32,2) [] = { 0xff0b3333, 0x54cccd };
+ VECT_VAR_DECL(expected_vcvt_n,uint,32,2) [] = { 0x0, 0x15 };
+ VECT_VAR_DECL(expected_vcvt_n,int,32,4) [] = { 0x0, 0x0, 0x1e3d7, 0xfffe1c29 };
+ VECT_VAR_DECL(expected_vcvt_n,uint,32,4) [] = { 0x0, 0x0, 0x1e, 0x0 };
+ 
+ /* Expected results for vcvt with rounding.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_rounding, int, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa };
++VECT_VAR_DECL(expected_rounding, uint, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa };
++VECT_VAR_DECL(expected_rounding, int, 16, 8) [] = { 0x7d, 0x7d, 0x7d, 0x7d,
++						    0x7d, 0x7d, 0x7d, 0x7d };
++VECT_VAR_DECL(expected_rounding, uint, 16, 8) [] = { 0x7d, 0x7d, 0x7d, 0x7d,
++						     0x7d, 0x7d, 0x7d, 0x7d };
++#endif
+ VECT_VAR_DECL(expected_rounding,int,32,2) [] = { 0xa, 0xa };
+ VECT_VAR_DECL(expected_rounding,uint,32,2) [] = { 0xa, 0xa };
+ VECT_VAR_DECL(expected_rounding,int,32,4) [] = { 0x7d, 0x7d, 0x7d, 0x7d };
+ VECT_VAR_DECL(expected_rounding,uint,32,4) [] = { 0x7d, 0x7d, 0x7d, 0x7d };
+ 
+ /* Expected results for vcvt_n with rounding.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_vcvt_n_rounding, int, 16, 4) [] =
++{ 0x533, 0x533, 0x533, 0x533 };
++VECT_VAR_DECL(expected_vcvt_n_rounding, uint, 16, 4) [] =
++{ 0x533, 0x533, 0x533, 0x533 };
++VECT_VAR_DECL(expected_vcvt_n_rounding, int, 16, 8) [] =
++{ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
++  0x7fff, 0x7fff, 0x7fff, 0x7fff };
++VECT_VAR_DECL(expected_vcvt_n_rounding, uint, 16, 8) [] =
++{ 0xffff, 0xffff, 0xffff, 0xffff,
++  0xffff, 0xffff, 0xffff, 0xffff };
++#endif
+ VECT_VAR_DECL(expected_vcvt_n_rounding,int,32,2) [] = { 0xa66666, 0xa66666 };
+ VECT_VAR_DECL(expected_vcvt_n_rounding,uint,32,2) [] = { 0xa66666, 0xa66666 };
+ VECT_VAR_DECL(expected_vcvt_n_rounding,int,32,4) [] = { 0xfbccc, 0xfbccc,
+@@ -42,11 +105,17 @@ VECT_VAR_DECL(expected_vcvt_n_rounding,uint,32,4) [] = { 0xfbccc, 0xfbccc,
+ 						0xfbccc, 0xfbccc };
+ 
+ /* Expected results for vcvt_n with saturation.  */
+-VECT_VAR_DECL(expected_vcvt_n_saturation,int,32,2) [] = { 0x7fffffff,
+-							  0x7fffffff };
+-VECT_VAR_DECL(expected_vcvt_n_saturation,int,32,4) [] = { 0x7fffffff,
+-							  0x7fffffff,
+-					       0x7fffffff, 0x7fffffff };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_vcvt_n_saturation, int, 16, 4) [] =
++{ 0x533, 0x533, 0x533, 0x533 };
++VECT_VAR_DECL(expected_vcvt_n_saturation, int, 16, 8) [] =
++{ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
++  0x7fff, 0x7fff, 0x7fff, 0x7fff };
++#endif
++VECT_VAR_DECL(expected_vcvt_n_saturation,int,32,2) [] =
++{ 0x7fffffff, 0x7fffffff };
++VECT_VAR_DECL(expected_vcvt_n_saturation,int,32,4) [] =
++{ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff };
+ 
+ #define TEST_MSG "VCVT/VCVTQ"
+ void exec_vcvt (void)
+@@ -89,11 +158,26 @@ void exec_vcvt (void)
+ 
+   /* Initialize input "vector" from "buffer".  */
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+   /* Make sure some elements have a fractional part, to exercise
+      integer conversions.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VSET_LANE(vector, , float, f, 16, 4, 0, -15.3f);
++  VSET_LANE(vector, , float, f, 16, 4, 1, 5.3f);
++  VSET_LANE(vector, , float, f, 16, 4, 2, -15.3f);
++  VSET_LANE(vector, , float, f, 16, 4, 3, 5.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 4, -15.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 5, 5.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 6, -15.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 7, 5.3f);
++#endif
++
+   VSET_LANE(vector, , float, f, 32, 2, 0, -15.3f);
+   VSET_LANE(vector, , float, f, 32, 2, 1, 5.3f);
+   VSET_LANE(vector, q, float, f, 32, 4, 2, -15.3f);
+@@ -103,23 +187,55 @@ void exec_vcvt (void)
+      before overwriting them.  */
+ #define TEST_MSG2 ""
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_f16_xx.  */
++  TEST_VCVT_FP(, float, f, 16, 4, int, s, expected_s);
++  TEST_VCVT_FP(, float, f, 16, 4, uint, u, expected_u);
++#endif
+   /* vcvt_f32_xx.  */
+   TEST_VCVT_FP(, float, f, 32, 2, int, s, expected_s);
+   TEST_VCVT_FP(, float, f, 32, 2, uint, u, expected_u);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_f16_xx.  */
++  TEST_VCVT_FP(q, float, f, 16, 8, int, s, expected_s);
++  TEST_VCVT_FP(q, float, f, 16, 8, uint, u, expected_u);
++#endif
+   /* vcvtq_f32_xx.  */
+   TEST_VCVT_FP(q, float, f, 32, 4, int, s, expected_s);
+   TEST_VCVT_FP(q, float, f, 32, 4, uint, u, expected_u);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_xx_f16.  */
++  TEST_VCVT(, int, s, 16, 4, float, f, expected);
++  TEST_VCVT(, uint, u, 16, 4, float, f, expected);
++#endif
+   /* vcvt_xx_f32.  */
+   TEST_VCVT(, int, s, 32, 2, float, f, expected);
+   TEST_VCVT(, uint, u, 32, 2, float, f, expected);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VSET_LANE(vector, q, float, f, 16, 8, 0, 0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 1, -0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 2, 15.12f);
++  VSET_LANE(vector, q, float, f, 16, 8, 3, -15.12f);
++  VSET_LANE(vector, q, float, f, 16, 8, 4, 0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 5, -0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 6, 15.12f);
++  VSET_LANE(vector, q, float, f, 16, 8, 7, -15.12f);
++#endif
++
+   VSET_LANE(vector, q, float, f, 32, 4, 0, 0.0f);
+   VSET_LANE(vector, q, float, f, 32, 4, 1, -0.0f);
+   VSET_LANE(vector, q, float, f, 32, 4, 2, 15.12f);
+   VSET_LANE(vector, q, float, f, 32, 4, 3, -15.12f);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_xx_f16.  */
++  TEST_VCVT(q, int, s, 16, 8, float, f, expected);
++  TEST_VCVT(q, uint, u, 16, 8, float, f, expected);
++#endif
++
+   /* vcvtq_xx_f32.  */
+   TEST_VCVT(q, int, s, 32, 4, float, f, expected);
+   TEST_VCVT(q, uint, u, 32, 4, float, f, expected);
+@@ -129,18 +245,38 @@ void exec_vcvt (void)
+ #undef TEST_MSG
+ #define TEST_MSG "VCVT_N/VCVTQ_N"
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_n_f16_xx.  */
++  TEST_VCVT_N_FP(, float, f, 16, 4, int, s, 2, expected_vcvt_n_s);
++  TEST_VCVT_N_FP(, float, f, 16, 4, uint, u, 7, expected_vcvt_n_u);
++#endif
+   /* vcvt_n_f32_xx.  */
+   TEST_VCVT_N_FP(, float, f, 32, 2, int, s, 2, expected_vcvt_n_s);
+   TEST_VCVT_N_FP(, float, f, 32, 2, uint, u, 7, expected_vcvt_n_u);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_n_f16_xx.  */
++  TEST_VCVT_N_FP(q, float, f, 16, 8, int, s, 7, expected_vcvt_n_s);
++  TEST_VCVT_N_FP(q, float, f, 16, 8, uint, u, 12, expected_vcvt_n_u);
++#endif
+   /* vcvtq_n_f32_xx.  */
+   TEST_VCVT_N_FP(q, float, f, 32, 4, int, s, 30, expected_vcvt_n_s);
+   TEST_VCVT_N_FP(q, float, f, 32, 4, uint, u, 12, expected_vcvt_n_u);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_n_xx_f16.  */
++  TEST_VCVT_N(, int, s, 16, 4, float, f, 2, expected_vcvt_n);
++  TEST_VCVT_N(, uint, u, 16, 4, float, f, 7, expected_vcvt_n);
++#endif
+   /* vcvt_n_xx_f32.  */
+   TEST_VCVT_N(, int, s, 32, 2, float, f, 20, expected_vcvt_n);
+   TEST_VCVT_N(, uint, u, 32, 2, float, f, 2, expected_vcvt_n);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_n_xx_f16.  */
++  TEST_VCVT_N(q, int, s, 16, 8, float, f, 7, expected_vcvt_n);
++  TEST_VCVT_N(q, uint, u, 16, 8, float, f, 12, expected_vcvt_n);
++#endif
+   /* vcvtq_n_xx_f32.  */
+   TEST_VCVT_N(q, int, s, 32, 4, float, f, 13, expected_vcvt_n);
+   TEST_VCVT_N(q, uint, u, 32, 4, float, f, 1, expected_vcvt_n);
+@@ -150,20 +286,49 @@ void exec_vcvt (void)
+ #define TEST_MSG "VCVT/VCVTQ"
+ #undef TEST_MSG2
+ #define TEST_MSG2 "(check rounding)"
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 10.4f);
++  VDUP(vector, q, float, f, 16, 8, 125.9f);
++#endif
+   VDUP(vector, , float, f, 32, 2, 10.4f);
+   VDUP(vector, q, float, f, 32, 4, 125.9f);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_xx_f16.  */
++  TEST_VCVT(, int, s, 16, 4, float, f, expected_rounding);
++  TEST_VCVT(, uint, u, 16, 4, float, f, expected_rounding);
++#endif
+   /* vcvt_xx_f32.  */
+   TEST_VCVT(, int, s, 32, 2, float, f, expected_rounding);
+   TEST_VCVT(, uint, u, 32, 2, float, f, expected_rounding);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_xx_f16.  */
++  TEST_VCVT(q, int, s, 16, 8, float, f, expected_rounding);
++  TEST_VCVT(q, uint, u, 16, 8, float, f, expected_rounding);
++#endif
+   /* vcvtq_xx_f32.  */
+   TEST_VCVT(q, int, s, 32, 4, float, f, expected_rounding);
+   TEST_VCVT(q, uint, u, 32, 4, float, f, expected_rounding);
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VCVT_N/VCVTQ_N"
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_n_xx_f16.  */
++  TEST_VCVT_N(, int, s, 16, 4, float, f, 7, expected_vcvt_n_rounding);
++  TEST_VCVT_N(, uint, u, 16, 4, float, f, 7, expected_vcvt_n_rounding);
++#endif
+   /* vcvt_n_xx_f32.  */
+   TEST_VCVT_N(, int, s, 32, 2, float, f, 20, expected_vcvt_n_rounding);
+   TEST_VCVT_N(, uint, u, 32, 2, float, f, 20, expected_vcvt_n_rounding);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_n_xx_f16.  */
++  TEST_VCVT_N(q, int, s, 16, 8, float, f, 13, expected_vcvt_n_rounding);
++  TEST_VCVT_N(q, uint, u, 16, 8, float, f, 13, expected_vcvt_n_rounding);
++#endif
+   /* vcvtq_n_xx_f32.  */
+   TEST_VCVT_N(q, int, s, 32, 4, float, f, 13, expected_vcvt_n_rounding);
+   TEST_VCVT_N(q, uint, u, 32, 4, float, f, 13, expected_vcvt_n_rounding);
+@@ -172,8 +337,18 @@ void exec_vcvt (void)
+ #define TEST_MSG "VCVT_N/VCVTQ_N"
+ #undef TEST_MSG2
+ #define TEST_MSG2 "(check saturation)"
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt_n_xx_f16.  */
++  TEST_VCVT_N(, int, s, 16, 4, float, f, 7, expected_vcvt_n_saturation);
++#endif
+   /* vcvt_n_xx_f32.  */
+   TEST_VCVT_N(, int, s, 32, 2, float, f, 31, expected_vcvt_n_saturation);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvtq_n_xx_f16.  */
++  TEST_VCVT_N(q, int, s, 16, 8, float, f, 13, expected_vcvt_n_saturation);
++#endif
+   /* vcvtq_n_xx_f32.  */
+   TEST_VCVT_N(q, int, s, 32, 4, float, f, 31, expected_vcvt_n_saturation);
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtX.inc
+@@ -0,0 +1,113 @@
++/* Template file for VCVT operator validation.
++
++   This file is meant to be included by the relevant test files, which
++   have to define the intrinsic family to test.  If a given intrinsic
++   supports variants which are not supported by all the other vcvt
++   operators, these can be tested by providing a definition for
++   EXTRA_TESTS.
++
++   This file is only used for VCVT? tests, which currently have only f16 to
++   integer variants.  It is based on vcvt.c.  */
++
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1 (NAME)
++
++void FNNAME (INSN_NAME) (void)
++{
++  int i;
++
++  /* Basic test: y=vcvt(x), then store the result.  */
++#define TEST_VCVT1(INSN, Q, T1, T2, W, N, TS1, TS2, EXP)	\
++  VECT_VAR(vector_res, T1, W, N) =				\
++    INSN##Q##_##T2##W##_##TS2##W(VECT_VAR(vector, TS1, W, N));	\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),			\
++		    VECT_VAR(vector_res, T1, W, N));		\
++  CHECK(TEST_MSG, T1, W, N, PRIx##W, EXP, TEST_MSG2);
++
++#define TEST_VCVT(INSN, Q, T1, T2, W, N, TS1, TS2, EXP)		\
++  TEST_VCVT1 (INSN, Q, T1, T2, W, N, TS1, TS2, EXP)
++
++  DECL_VARIABLE_ALL_VARIANTS(vector);
++  DECL_VARIABLE_ALL_VARIANTS(vector_res);
++
++  clean_results ();
++
++  /* Initialize input "vector" from "buffer".  */
++  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
++
++  /* Make sure some elements have a fractional part, to exercise
++     integer conversions.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VSET_LANE(vector, , float, f, 16, 4, 0, -15.3f);
++  VSET_LANE(vector, , float, f, 16, 4, 1, 5.3f);
++  VSET_LANE(vector, , float, f, 16, 4, 2, -15.3f);
++  VSET_LANE(vector, , float, f, 16, 4, 3, 5.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 4, -15.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 5, 5.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 6, -15.3f);
++  VSET_LANE(vector, q, float, f, 16, 8, 7, 5.3f);
++#endif
++
++  /* The same result buffers are used multiple times, so we check them
++     before overwriting them.  */
++#define TEST_MSG2 ""
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt?_xx_f16.  */
++  TEST_VCVT(INSN_NAME, , int, s, 16, 4, float, f, expected);
++  TEST_VCVT(INSN_NAME, , uint, u, 16, 4, float, f, expected);
++#endif
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VSET_LANE(vector, q, float, f, 16, 8, 0, 0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 1, -0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 2, 15.12f);
++  VSET_LANE(vector, q, float, f, 16, 8, 3, -15.12f);
++  VSET_LANE(vector, q, float, f, 16, 8, 4, 0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 5, -0.0f);
++  VSET_LANE(vector, q, float, f, 16, 8, 6, 15.12f);
++  VSET_LANE(vector, q, float, f, 16, 8, 7, -15.12f);
++#endif
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt?q_xx_f16.  */
++  TEST_VCVT(INSN_NAME, q, int, s, 16, 8, float, f, expected);
++  TEST_VCVT(INSN_NAME, q, uint, u, 16, 8, float, f, expected);
++#endif
++
++  /* Check rounding.  */
++#undef TEST_MSG2
++#define TEST_MSG2 "(check rounding)"
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 10.4f);
++  VDUP(vector, q, float, f, 16, 8, 125.9f);
++#endif
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt?_xx_f16.  */
++  TEST_VCVT(INSN_NAME, , int, s, 16, 4, float, f, expected_rounding);
++  TEST_VCVT(INSN_NAME, , uint, u, 16, 4, float, f, expected_rounding);
++#endif
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  /* vcvt?q_xx_f16.  */
++  TEST_VCVT(INSN_NAME, q, int, s, 16, 8, float, f, expected_rounding);
++  TEST_VCVT(INSN_NAME, q, uint, u, 16, 8, float, f, expected_rounding);
++#endif
++
++#ifdef EXTRA_TESTS
++  EXTRA_TESTS();
++#endif
++}
++
++int
++main (void)
++{
++  FNNAME (INSN_NAME) ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvta_1.c
+@@ -0,0 +1,33 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++#include <math.h>
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, int, 16, 4) [] = { 0xfff1, 0x5, 0xfff1, 0x5 };
++VECT_VAR_DECL(expected, uint, 16, 4) [] = { 0x0, 0x5, 0x0, 0x5 };
++VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x0, 0x0, 0xf, 0xfff1,
++					   0x0, 0x0, 0xf, 0xfff1 };
++VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0x0, 0x0, 0xf, 0x0,
++					    0x0, 0x0, 0xf, 0x0 };
++#endif
++
++/* Expected results with rounding.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_rounding, int, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa };
++VECT_VAR_DECL(expected_rounding, uint, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa };
++VECT_VAR_DECL(expected_rounding, int, 16, 8) [] = { 0x7e, 0x7e, 0x7e, 0x7e,
++						    0x7e, 0x7e, 0x7e, 0x7e };
++VECT_VAR_DECL(expected_rounding, uint, 16, 8) [] = { 0x7e, 0x7e, 0x7e, 0x7e,
++						     0x7e, 0x7e, 0x7e, 0x7e };
++#endif
++
++#define TEST_MSG "VCVTA/VCVTAQ"
++#define INSN_NAME vcvta
++
++#include "vcvtX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int16_t expected[] = { 124, -57, 1, 25, -64, 169, -4, 77 };
++
++#define TEST_MSG "VCVTAH_S16_F16"
++#define INSN_NAME vcvtah_s16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0xfffffdc8,
++  0xffffffdd,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0xfffffffb,
++  0x0000004d,
++  0xffffff6f,
++  0xffffffc7,
++  0xfffffff0,
++  0xfffffff1,
++  0xfffffff2,
++  0xfffffff3
++};
++
++#define TEST_MSG "VCVTAH_S32_F16"
++#define INSN_NAME vcvtah_s32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int64_t expected[] = { 124, -57, 1, 25, -64, 169, -4, 77 };
++
++#define TEST_MSG "VCVTAH_S64_F16"
++#define INSN_NAME vcvtah_s64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint16_t expected[] = { 124, 57, 1, 25, 64, 169, 4, 77 };
++
++#define TEST_MSG "VCVTAH_u16_F16"
++#define INSN_NAME vcvtah_u16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0x00000000,
++  0x00000000,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0x00000000,
++  0x0000004d,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000
++};
++
++#define TEST_MSG "VCVTAH_U32_F16"
++#define INSN_NAME vcvtah_u32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint64_t expected[] = { 124, 57, 1, 25, 64, 169, 4, 77 };
++
++#define TEST_MSG "VCVTAH_u64_F16"
++#define INSN_NAME vcvtah_u64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c
+@@ -0,0 +1,25 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++int16_t input[] = { 123, -567, 0, 1024, -63, 169, -4, 77 };
++uint16_t expected[] = { 0x57B0 /* 123.0.  */, 0xE06E /* -567.0.  */,
++			0x0000 /* 0.0.  */, 0x6400 /* 1024.  */,
++			0xD3E0 /* -63.  */, 0x5948 /* 169.  */,
++			0xC400 /* -4.  */, 0x54D0 /* 77.  */ };
++
++#define TEST_MSG "VCVTH_F16_S16"
++#define INSN_NAME vcvth_f16_s16
++
++#define EXPECTED expected
++
++#define INPUT input
++#define INPUT_TYPE int16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c
+@@ -0,0 +1,52 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++uint32_t input[] =
++{
++  0, -0,
++  123, -567,
++  -34, 1024,
++  -63, 169,
++  -4, 77,
++  -144, -56,
++  -16, -15,
++  -14, -13,
++};
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x57b0 /* 123.000000 */,
++  0xe06e /* -567.000000 */,
++  0xd040 /* -34.000000 */,
++  0x6400 /* 1024.000000 */,
++  0xd3e0 /* -63.000000 */,
++  0x5948 /* 169.000000 */,
++  0xc400 /* -4.000000 */,
++  0x54d0 /* 77.000000 */,
++  0xd880 /* -144.000000 */,
++  0xd300 /* -56.000000 */,
++  0xcc00 /* -16.000000 */,
++  0xcb80 /* -15.000000 */,
++  0xcb00 /* -14.000000 */,
++  0xca80 /* -13.000000 */
++};
++
++#define TEST_MSG "VCVTH_F16_S32"
++#define INSN_NAME vcvth_f16_s32
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE uint32_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c
+@@ -0,0 +1,25 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++int64_t input[] = { 123, -567, 0, 1024, -63, 169, -4, 77 };
++uint16_t expected[] = { 0x57B0 /* 123.0.  */, 0xE06E /* -567.0.  */,
++			0x0000 /* 0.0.  */, 0x6400 /* 1024.  */,
++			0xD3E0 /* -63.  */, 0x5948 /* 169.  */,
++			0xC400 /* -4.  */, 0x54D0 /* 77.  */ };
++
++#define TEST_MSG "VCVTH_F16_S64"
++#define INSN_NAME vcvth_f16_s64
++
++#define EXPECTED expected
++
++#define INPUT input
++#define INPUT_TYPE int64_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c
+@@ -0,0 +1,25 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint16_t input[] = { 123, 567, 0, 1024, 63, 169, 4, 77 };
++uint16_t expected[] = { 0x57B0 /* 123.0.  */, 0x606E /* 567.0.  */,
++			0x0000 /* 0.0.  */, 0x6400 /* 1024.0.  */,
++			0x53E0 /* 63.0.  */, 0x5948 /* 169.0.  */,
++			0x4400 /* 4.0.  */, 0x54D0 /* 77.0.  */ };
++
++#define TEST_MSG "VCVTH_F16_U16"
++#define INSN_NAME vcvth_f16_u16
++
++#define EXPECTED expected
++
++#define INPUT input
++#define INPUT_TYPE uint16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c
+@@ -0,0 +1,52 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++int32_t input[] =
++{
++  0, -0,
++  123, -567,
++  -34, 1024,
++  -63, 169,
++  -4, 77,
++  -144, -56,
++  -16, -15,
++  -14, -13,
++};
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x57b0 /* 123.000000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x6400 /* 1024.000000 */,
++  0x7c00 /* inf */,
++  0x5948 /* 169.000000 */,
++  0x7c00 /* inf */,
++  0x54d0 /* 77.000000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */
++};
++
++#define TEST_MSG "VCVTH_F16_U32"
++#define INSN_NAME vcvth_f16_u32
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE int32_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c
+@@ -0,0 +1,25 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++uint64_t input[] = { 123, 567, 0, 1024, 63, 169, 4, 77 };
++uint16_t expected[] = { 0x57B0 /* 123.0.  */, 0x606E /* 567.0.  */,
++			0x0000 /* 0.0.  */, 0x6400 /* 1024.0.  */,
++			0x53E0 /* 63.0.  */, 0x5948 /* 169.0.  */,
++			0x4400 /* 4.0.  */, 0x54D0 /* 77.0.  */ };
++
++#define TEST_MSG "VCVTH_F16_U64"
++#define INSN_NAME vcvth_f16_u64
++
++#define EXPECTED expected
++
++#define INPUT input
++#define INPUT_TYPE uint64_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c
+@@ -0,0 +1,46 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++int16_t input[] = { 1, 10, 48, 100, -1, -10, 7, -7 };
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected_1[] = { 0x3800 /* 0.5.  */,
++			  0x4500 /* 5.  */,
++			  0x4E00 /* 24.  */,
++			  0x5240 /* 50.  */,
++			  0xB800 /* -0.5.  */,
++			  0xC500 /* -5.  */,
++			  0x4300 /* 3.5.  */,
++			  0xC300 /* -3.5.  */ };
++
++uint16_t expected_2[] = { 0x3400 /* 0.25.  */,
++			  0x4100 /* 2.5.  */,
++			  0x4A00 /* 12.  */,
++			  0x4E40 /* 25.  */,
++			  0xB400 /* -0.25.  */,
++			  0xC100 /* -2.5.  */,
++			  0x3F00 /* 1.75.  */,
++			  0xBF00 /* -1.75.  */ };
++
++#define TEST_MSG "VCVTH_N_F16_S16"
++#define INSN_NAME vcvth_n_f16_s16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE int16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c
+@@ -0,0 +1,99 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++uint32_t input[] =
++{
++  0, -0,
++  123, -567,
++  -34, 1024,
++  -63, 169,
++  -4, 77,
++  -144, -56,
++  -16, -15,
++  -14, -13,
++};
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected_1[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x53b0 /* 61.500000 */,
++  0xdc6e /* -283.500000 */,
++  0xcc40 /* -17.000000 */,
++  0x6000 /* 512.000000 */,
++  0xcfe0 /* -31.500000 */,
++  0x5548 /* 84.500000 */,
++  0xc000 /* -2.000000 */,
++  0x50d0 /* 38.500000 */,
++  0xd480 /* -72.000000 */,
++  0xcf00 /* -28.000000 */,
++  0xc800 /* -8.000000 */,
++  0xc780 /* -7.500000 */,
++  0xc700 /* -7.000000 */,
++  0xc680 /* -6.500000 */
++};
++
++uint16_t expected_2[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x4fb0 /* 30.750000 */,
++  0xd86e /* -141.750000 */,
++  0xc840 /* -8.500000 */,
++  0x5c00 /* 256.000000 */,
++  0xcbe0 /* -15.750000 */,
++  0x5148 /* 42.250000 */,
++  0xbc00 /* -1.000000 */,
++  0x4cd0 /* 19.250000 */,
++  0xd080 /* -36.000000 */,
++  0xcb00 /* -14.000000 */,
++  0xc400 /* -4.000000 */,
++  0xc380 /* -3.750000 */,
++  0xc300 /* -3.500000 */,
++  0xc280 /* -3.250000 */
++};
++
++uint16_t expected_3[] =
++{
++ 0x0000 /* 0.000000 */,
++ 0x0000 /* 0.000000 */,
++ 0x0000 /* 0.000000 */,
++ 0x8002 /* -0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x0004 /* 0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x0001 /* 0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x0000 /* 0.000000 */,
++ 0x8001 /* -0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x8000 /* -0.000000 */,
++ 0x8000 /* -0.000000 */
++};
++
++#define TEST_MSG "VCVTH_N_F16_S32"
++#define INSN_NAME vcvth_n_f16_s32
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++#define EXPECTED_3 expected_3
++
++#define INPUT_TYPE int32_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++#define SCALAR_3 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c
+@@ -0,0 +1,46 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++int64_t input[] = { 1, 10, 48, 100, -1, -10, 7, -7 };
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected_1[] = { 0x3800 /* 0.5.  */,
++			  0x4500 /* 5.  */,
++			  0x4E00 /* 24.  */,
++			  0x5240 /* 50.  */,
++			  0xB800 /* -0.5.  */,
++			  0xC500 /* -5.  */,
++			  0x4300 /* 3.5.  */,
++			  0xC300 /* -3.5.  */ };
++
++uint16_t expected_2[] = { 0x3400 /* 0.25.  */,
++			  0x4100 /* 2.5.  */,
++			  0x4A00 /* 12.  */,
++			  0x4E40 /* 25.  */,
++			  0xB400 /* -0.25.  */,
++			  0xC100 /* -2.5.  */,
++			  0x3F00 /* 1.75.  */,
++			  0xBF00 /* -1.75.  */ };
++
++#define TEST_MSG "VCVTH_N_F16_S64"
++#define INSN_NAME vcvth_n_f16_s64
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE int64_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c
+@@ -0,0 +1,46 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++uint16_t input[] = { 1, 10, 48, 100, 1000, 0, 500, 9 };
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected_1[] = { 0x3800 /* 0.5.  */,
++			  0x4500 /* 5.  */,
++			  0x4E00 /* 24.  */,
++			  0x5240 /* 50.  */,
++			  0x5FD0 /* 500.  */,
++			  0x0000 /* 0.0.  */,
++			  0x5BD0 /* 250.  */,
++			  0x4480 /* 4.5.  */ };
++
++uint16_t expected_2[] = { 0x3400 /* 0.25.  */,
++			  0x4100 /* 2.5.  */,
++			  0x4A00 /* 12.  */,
++			  0x4E40 /* 25.  */,
++			  0x5BD0 /* 250.  */,
++			  0x0000 /* 0.0.  */,
++			  0x57D0 /* 125.  */,
++			  0x4080 /* 2.25.  */ };
++
++#define TEST_MSG "VCVTH_N_F16_U16"
++#define INSN_NAME vcvth_n_f16_u16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE uint16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c
+@@ -0,0 +1,99 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++uint32_t input[] =
++{
++  0, -0,
++  123, -567,
++  -34, 1024,
++  -63, 169,
++  -4, 77,
++  -144, -56,
++  -16, -15,
++  -14, -13,
++};
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected_1[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x53b0 /* 61.500000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x6000 /* 512.000000 */,
++  0x7c00 /* inf */,
++  0x5548 /* 84.500000 */,
++  0x7c00 /* inf */,
++  0x50d0 /* 38.500000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */
++};
++
++uint16_t expected_2[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x4fb0 /* 30.750000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x5c00 /* 256.000000 */,
++  0x7c00 /* inf */,
++  0x5148 /* 42.250000 */,
++  0x7c00 /* inf */,
++  0x4cd0 /* 19.250000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */
++};
++
++uint16_t expected_3[] =
++{
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x0004 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x0001 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */
++};
++
++#define TEST_MSG "VCVTH_N_F16_U32"
++#define INSN_NAME vcvth_n_f16_u32
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++#define EXPECTED_3 expected_3
++
++#define INPUT_TYPE uint32_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++#define SCALAR_3 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c
+@@ -0,0 +1,46 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++uint64_t input[] = { 1, 10, 48, 100, 1000, 0, 500, 9 };
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected_1[] = { 0x3800 /* 0.5.  */,
++			  0x4500 /* 5.  */,
++			  0x4E00 /* 24.  */,
++			  0x5240 /* 50.  */,
++			  0x5FD0 /* 500.  */,
++			  0x0000 /* 0.0.  */,
++			  0x5BD0 /* 250.  */,
++			  0x4480 /* 4.5.  */ };
++
++uint16_t expected_2[] = { 0x3400 /* 0.25.  */,
++			  0x4100 /* 2.5.  */,
++			  0x4A00 /* 12.  */,
++			  0x4E40 /* 25.  */,
++			  0x5BD0 /* 250.  */,
++			  0x0000 /* 0.0.  */,
++			  0x57D0 /* 125.  */,
++			  0x4080 /* 2.25.  */ };
++
++#define TEST_MSG "VCVTH_N_F16_U64"
++#define INSN_NAME vcvth_n_f16_u64
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE uint64_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c
+@@ -0,0 +1,29 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 2.5, 100, 7.1, -9.9, -5.0, 9.1, -4.8, 77 };
++int16_t expected_1[] = { 5, 200, 14, -19, -10, 18, -9, 154 };
++int16_t expected_2[] = { 10, 400, 28, -39, -20, 36, -19, 308 };
++
++#define TEST_MSG "VCVTH_N_S16_F16"
++#define INSN_NAME vcvth_n_s16_f16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c
+@@ -0,0 +1,100 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected_1[] =
++{
++  0x00000000,
++  0x00000000,
++  0x000000f6,
++  0xfffffb90,
++  0xffffffbb,
++  0x00000800,
++  0x0000052e,
++  0x00000152,
++  0xfffffff7,
++  0x0000009a,
++  0xfffffedf,
++  0xffffff8f,
++  0xffffffe0,
++  0xffffffe2,
++  0xffffffe4,
++  0xffffffe6,
++};
++
++uint32_t expected_2[] =
++{
++  0x00000000,
++  0x00000000,
++  0x000001ed,
++  0xfffff720,
++  0xffffff75,
++  0x00001000,
++  0x00000a5c,
++  0x000002a4,
++  0xffffffed,
++  0x00000134,
++  0xfffffdbe,
++  0xffffff1d,
++  0xffffffc0,
++  0xffffffc4,
++  0xffffffc8,
++  0xffffffcc,
++};
++
++uint32_t expected_3[] =
++{
++  0x00000000,
++  0x00000000,
++  0x7fffffff,
++  0x80000000,
++  0x80000000,
++  0x7fffffff,
++  0x7fffffff,
++  0x7fffffff,
++  0x80000000,
++  0x7fffffff,
++  0x80000000,
++  0x80000000,
++  0x80000000,
++  0x80000000,
++  0x80000000,
++  0x80000000,
++};
++
++#define TEST_MSG "VCVTH_N_S32_F16"
++#define INSN_NAME vcvth_n_s32_f16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++#define EXPECTED_3 expected_3
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++#define SCALAR_3 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c
+@@ -0,0 +1,29 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 2.5, 100, 7.1, -9.9, -5.0, 9.1, -4.8, 77 };
++int64_t expected_1[] = { 5, 200, 14, -19, -10, 18, -9, 154 };
++int64_t expected_2[] = { 10, 400, 28, -39, -20, 36, -19, 308 };
++
++#define TEST_MSG "VCVTH_N_S64_F16"
++#define INSN_NAME vcvth_n_s64_f16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int64_t
++#define OUTPUT_TYPE_SIZE 64
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c
+@@ -0,0 +1,29 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 2.5, 100, 7.1, 9.9, 5.0, 9.1, 4.8, 77 };
++uint16_t expected_1[] = {5, 200, 14, 19, 10, 18, 9, 154};
++uint16_t expected_2[] = {10, 400, 28, 39, 20, 36, 19, 308};
++
++#define TEST_MSG "VCVTH_N_U16_F16"
++#define INSN_NAME vcvth_n_u16_f16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c
+@@ -0,0 +1,100 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected_1[] =
++{
++  0x00000000,
++  0x00000000,
++  0x000000f6,
++  0x00000000,
++  0x00000000,
++  0x00000800,
++  0x0000052e,
++  0x00000152,
++  0x00000000,
++  0x0000009a,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++uint32_t expected_2[] =
++{
++  0x00000000,
++  0x00000000,
++  0x000001ed,
++  0x00000000,
++  0x00000000,
++  0x00001000,
++  0x00000a5c,
++  0x000002a4,
++  0x00000000,
++  0x00000134,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++uint32_t expected_3[] =
++{
++  0x00000000,
++  0x00000000,
++  0xffffffff,
++  0x00000000,
++  0x00000000,
++  0xffffffff,
++  0xffffffff,
++  0xffffffff,
++  0x00000000,
++  0xffffffff,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++#define TEST_MSG "VCVTH_N_U32_F16"
++#define INSN_NAME vcvth_n_u32_f16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++#define EXPECTED_3 expected_3
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++#define SCALAR_3 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c
+@@ -0,0 +1,29 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 2.5, 100, 7.1, 9.9, 5.0, 9.1, 4.8, 77 };
++uint64_t expected_1[] = { 5, 200, 14, 19, 10, 18, 9, 154 };
++uint64_t expected_2[] = { 10, 400, 28, 39, 20, 36, 19, 308 };
++
++#define TEST_MSG "VCVTH_N_U64_F16"
++#define INSN_NAME vcvth_n_u64_f16
++
++#define INPUT input
++#define EXPECTED_1 expected_1
++#define EXPECTED_2 expected_2
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint64_t
++#define OUTPUT_TYPE_SIZE 64
++
++#define SCALAR_OPERANDS
++#define SCALAR_1 1
++#define SCALAR_2 2
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int16_t expected[] = { 123, -56, 0, 24, -63, 169, -4, 77 };
++
++#define TEST_MSG "VCVTH_S16_F16"
++#define INSN_NAME vcvth_s16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0xfffffdc8,
++  0xffffffde,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0xfffffffc,
++  0x0000004d,
++  0xffffff70,
++  0xffffffc8,
++  0xfffffff0,
++  0xfffffff1,
++  0xfffffff2,
++  0xfffffff3,
++};
++
++#define TEST_MSG "VCVTH_S32_F16"
++#define INSN_NAME vcvth_s32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int64_t expected[] = { 123, -56, 0, 24, -63, 169, -4, 77 };
++
++#define TEST_MSG "VCVTH_S64_F16"
++#define INSN_NAME vcvth_s64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint16_t expected[] = { 123, 56, 0, 24, 63, 169, 4, 77 };
++
++#define TEST_MSG "VCVTH_u16_F16"
++#define INSN_NAME vcvth_u16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0x00000000,
++  0x00000000,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0x00000000,
++  0x0000004d,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++#define TEST_MSG "VCVTH_U32_F16"
++#define INSN_NAME vcvth_u32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint64_t expected[] = { 123, 56, 0, 24, 63, 169, 4, 77 };
++
++#define TEST_MSG "VCVTH_u64_F16"
++#define INSN_NAME vcvth_u64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtm_1.c
+@@ -0,0 +1,33 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++#include <math.h>
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, int, 16, 4) [] = { 0xfff0, 0x5, 0xfff0, 0x5 };
++VECT_VAR_DECL(expected, uint, 16, 4) [] = { 0x0, 0x5, 0x0, 0x5 };
++VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x0, 0x0, 0xf, 0xfff0, 0x0,
++					   0x0, 0xf, 0xfff0 };
++VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0x0, 0x0, 0xf, 0x0,
++					    0x0, 0x0, 0xf, 0x0 };
++#endif
++
++/* Expected results with rounding.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_rounding, int, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa };
++VECT_VAR_DECL(expected_rounding, uint, 16, 4) [] = { 0xa, 0xa, 0xa, 0xa };
++VECT_VAR_DECL(expected_rounding, int, 16, 8) [] = { 0x7d, 0x7d, 0x7d, 0x7d,
++						    0x7d, 0x7d, 0x7d, 0x7d };
++VECT_VAR_DECL(expected_rounding, uint, 16, 8) [] = { 0x7d, 0x7d, 0x7d, 0x7d,
++						     0x7d, 0x7d, 0x7d, 0x7d };
++#endif
++
++#define TEST_MSG "VCVTM/VCVTMQ"
++#define INSN_NAME vcvtm
++
++#include "vcvtX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int16_t expected[] = { 123, -57, 0, 24, -64, 169, -5, 77 };
++
++#define TEST_MSG "VCVTMH_S16_F16"
++#define INSN_NAME vcvtmh_s16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0xfffffdc8,
++  0xffffffdd,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0xfffffffb,
++  0x0000004d,
++  0xffffff6f,
++  0xffffffc7,
++  0xfffffff0,
++  0xfffffff1,
++  0xfffffff2,
++  0xfffffff3
++};
++
++#define TEST_MSG "VCVTMH_S32_F16"
++#define INSN_NAME vcvtmh_s32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int64_t expected[] = { 123, -57, 0, 24, -64, 169, -5, 77 };
++
++#define TEST_MSG "VCVTMH_S64_F16"
++#define INSN_NAME vcvtmh_s64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint16_t expected[] = { 123, 56, 0, 24, 63, 169, 4, 77 };
++
++#define TEST_MSG "VCVTMH_u16_F16"
++#define INSN_NAME vcvtmh_u16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0x00000000,
++  0x00000000,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0x00000000,
++  0x0000004d,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++#define TEST_MSG "VCVTMH_U32_F16"
++#define INSN_NAME vcvtmh_u32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint64_t expected[] = { 123, 56, 0, 24, 63, 169, 4, 77 };
++
++#define TEST_MSG "VCVTMH_u64_F16"
++#define INSN_NAME vcvtmh_u64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int16_t expected[] = { 124, -57, 1, 25, -64, 169, -4, 77 };
++
++#define TEST_MSG "VCVTNH_S16_F16"
++#define INSN_NAME vcvtnh_s16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0xfffffdc8,
++  0xffffffdd,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0xfffffffb,
++  0x0000004d,
++  0xffffff70,
++  0xffffffc7,
++  0xfffffff0,
++  0xfffffff1,
++  0xfffffff2,
++  0xfffffff3
++};
++
++#define TEST_MSG "VCVTNH_S32_F16"
++#define INSN_NAME vcvtnh_s32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int64_t expected[] = { 124, -57, 1, 25, -64, 169, -4, 77 };
++
++#define TEST_MSG "VCVTNH_S64_F16"
++#define INSN_NAME vcvtnh_s64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint16_t expected[] = { 124, 57, 1, 25, 64, 169, 4, 77 };
++
++#define TEST_MSG "VCVTNH_u16_F16"
++#define INSN_NAME vcvtnh_u16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007b,
++  0x00000000,
++  0x00000000,
++  0x00000400,
++  0x00000297,
++  0x000000a9,
++  0x00000000,
++  0x0000004d,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++#define TEST_MSG "VCVTNH_U32_F16"
++#define INSN_NAME vcvtnh_u32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint64_t expected[] = { 124, 57, 1, 25, 64, 169, 4, 77 };
++
++#define TEST_MSG "VCVTNH_u64_F16"
++#define INSN_NAME vcvtnh_u64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtp_1.c
+@@ -0,0 +1,33 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++#include <math.h>
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, int, 16, 4) [] = { 0xfff1, 0x6, 0xfff1, 0x6 };
++VECT_VAR_DECL(expected, uint, 16, 4) [] = { 0x0, 0x6, 0x0, 0x6 };
++VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x0, 0x0, 0x10, 0xfff1,
++					   0x0, 0x0, 0x10, 0xfff1 };
++VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0x0, 0x0, 0x10, 0x0,
++					    0x0, 0x0, 0x10, 0x0 };
++#endif
++
++/* Expected results with rounding.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_rounding, int, 16, 4) [] = { 0xb, 0xb, 0xb, 0xb };
++VECT_VAR_DECL(expected_rounding, uint, 16, 4) [] = { 0xb, 0xb, 0xb, 0xb };
++VECT_VAR_DECL(expected_rounding, int, 16, 8) [] = { 0x7e, 0x7e, 0x7e, 0x7e,
++						    0x7e, 0x7e, 0x7e, 0x7e };
++VECT_VAR_DECL(expected_rounding, uint, 16, 8) [] = { 0x7e, 0x7e, 0x7e, 0x7e,
++						     0x7e, 0x7e, 0x7e, 0x7e };
++#endif
++
++#define TEST_MSG "VCVTP/VCVTPQ"
++#define INSN_NAME vcvtp
++
++#include "vcvtX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int16_t expected[] = { 124, -56, 1, 25, -63, 170, -4, 77 };
++
++#define TEST_MSG "VCVTPH_S16_F16"
++#define INSN_NAME vcvtph_s16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007c,
++  0xfffffdc8,
++  0xffffffde,
++  0x00000400,
++  0x00000297,
++  0x000000aa,
++  0xfffffffc,
++  0x0000004d,
++  0xffffff70,
++  0xffffffc8,
++  0xfffffff0,
++  0xfffffff1,
++  0xfffffff2,
++  0xfffffff3
++};
++
++#define TEST_MSG "VCVTPH_S32_F16"
++#define INSN_NAME vcvtph_s32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, -56.8, 0.7, 24.6, -63.5, 169.4, -4.3, 77.0 };
++int64_t expected[] = { 124, -56, 1, 25, -63, 170, -4, 77 };
++
++#define TEST_MSG "VCVTPH_S64_F16"
++#define INSN_NAME vcvtph_s64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE int64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint16_t expected[] = { 124, 57, 1, 25, 64, 170, 5, 77 };
++
++#define TEST_MSG "VCVTPH_u16_F16"
++#define INSN_NAME vcvtph_u16_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] =
++{
++  0.0, -0.0,
++  123.4, -567.8,
++  -34.8, 1024,
++  663.1, 169.1,
++  -4.8, 77.0,
++  -144.5, -56.8,
++
++  (float16_t) -16, (float16_t) -15,
++  (float16_t) -14, (float16_t) -13,
++};
++
++/* Expected results (32-bit hexadecimal representation).  */
++uint32_t expected[] =
++{
++  0x00000000,
++  0x00000000,
++  0x0000007c,
++  0x00000000,
++  0x00000000,
++  0x00000400,
++  0x00000297,
++  0x000000aa,
++  0x00000000,
++  0x0000004d,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++  0x00000000,
++};
++
++#define TEST_MSG "VCVTPH_U32_F16"
++#define INSN_NAME vcvtph_u32_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint32_t
++#define OUTPUT_TYPE_SIZE 32
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c
+@@ -0,0 +1,23 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.9, 56.8, 0.7, 24.6, 63.5, 169.4, 4.3, 77.0 };
++uint64_t expected[] = { 124, 57, 1, 25, 64, 170, 5, 77 };
++
++#define TEST_MSG "VCVTPH_u64_F16"
++#define INSN_NAME vcvtph_u64_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE uint64_t
++#define OUTPUT_TYPE_SIZE 64
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c
+@@ -0,0 +1,86 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (-56.8)
++#define C FP16_C (-34.8)
++#define D FP16_C (12)
++#define E FP16_C (63.1)
++#define F FP16_C (19.1)
++#define G FP16_C (-4.8)
++#define H FP16_C (77)
++
++#define I FP16_C (0.7)
++#define J FP16_C (-78)
++#define K FP16_C (11.23)
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-8)
++#define O FP16_C (-1.1)
++#define P FP16_C (-9.7)
++
++/* Expected results for vdiv.  */
++VECT_VAR_DECL (expected_div_static, hfloat, 16, 4) []
++  = { 0x32CC /* A / E.  */, 0xC1F3 /* B / F.  */,
++      0x4740 /* C / G.  */, 0x30FD /* D / H.  */ };
++
++VECT_VAR_DECL (expected_div_static, hfloat, 16, 8) []
++  = { 0x32CC /* A / E.  */, 0xC1F3 /* B / F.  */,
++      0x4740 /* C / G.  */, 0x30FD /* D / H.  */,
++      0x201D /* I / M.  */, 0x48E0 /* J / N.  */,
++      0xC91B /* K / O.  */, 0xC90D /* L / P.  */ };
++
++void exec_vdiv_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VDIV (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {E, F, G, H};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vdiv_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		VECT_VAR (vsrc_2, float, 16, 4));
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_div_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VDIVQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {E, F, G, H, M, N, O, P};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vdivq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		 VECT_VAR (vsrc_2, float, 16, 8));
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_div_static, "");
++}
++
++int
++main (void)
++{
++  exec_vdiv_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++#define INFF __builtin_inf ()
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0xb765 /* -0.462158 */,
++  0x27ef /* 0.030991 */,
++  0x3955 /* 0.666504 */,
++  0xccff /* -19.984375 */,
++  0xc49a /* -4.601562 */,
++  0xb1e3 /* -0.183960 */,
++  0x3cd3 /* 1.206055 */,
++  0x23f0 /* 0.015503 */,
++  0xa9ef /* -0.046356 */,
++  0x32f4 /* 0.217285 */,
++  0xb036 /* -0.131592 */,
++  0x4126 /* 2.574219 */,
++  0xcd15 /* -20.328125 */,
++  0x537f /* 59.968750 */,
++  0x7e00 /* nan */,
++  0x7e00 /* nan */
++};
++
++#define TEST_MSG "VDIVH_F16"
++#define INSN_NAME vdivh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c
+@@ -19,6 +19,10 @@ VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 };
+ VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
+ 					 0xf0, 0xf0, 0xf0, 0xf0 };
+ VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcc00,
++						0xcc00, 0xcc00 };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 };
+ VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
+ 					 0xf0, 0xf0, 0xf0, 0xf0,
+@@ -46,6 +50,12 @@ VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
+ 					  0xf0, 0xf0, 0xf0, 0xf0 };
+ VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0,
+ 					  0xfff0, 0xfff0, 0xfff0, 0xfff0 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 8) [] = { 0xcc00, 0xcc00,
++						0xcc00, 0xcc00,
++						0xcc00, 0xcc00,
++						0xcc00, 0xcc00 };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1800000,
+ 					    0xc1800000, 0xc1800000 };
+ 
+@@ -63,6 +73,10 @@ VECT_VAR_DECL(expected1,uint,64,1) [] = { 0xfffffffffffffff1 };
+ VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf1, 0xf1, 0xf1, 0xf1,
+ 					 0xf1, 0xf1, 0xf1, 0xf1 };
+ VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 4) [] = { 0xcb80, 0xcb80,
++						0xcb80, 0xcb80 };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
+ VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf1, 0xf1, 0xf1, 0xf1,
+ 					 0xf1, 0xf1, 0xf1, 0xf1,
+@@ -90,6 +104,12 @@ VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf1, 0xf1, 0xf1, 0xf1,
+ 					  0xf1, 0xf1, 0xf1, 0xf1 };
+ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1,
+ 					  0xfff1, 0xfff1, 0xfff1, 0xfff1 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 8) [] = { 0xcb80, 0xcb80,
++						0xcb80, 0xcb80,
++						0xcb80, 0xcb80,
++						0xcb80, 0xcb80 };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1700000, 0xc1700000,
+ 					    0xc1700000, 0xc1700000 };
+ 
+@@ -107,6 +127,10 @@ VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff2 };
+ VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf2, 0xf2, 0xf2, 0xf2,
+ 					 0xf2, 0xf2, 0xf2, 0xf2 };
+ VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff2 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb00, 0xcb00,
++						0xcb00, 0xcb00 };
++#endif
+ VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1600000, 0xc1600000 };
+ VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf2, 0xf2, 0xf2, 0xf2,
+ 					 0xf2, 0xf2, 0xf2, 0xf2,
+@@ -134,6 +158,12 @@ VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf2, 0xf2, 0xf2, 0xf2,
+ 					  0xf2, 0xf2, 0xf2, 0xf2 };
+ VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff2,
+ 					  0xfff2, 0xfff2, 0xfff2, 0xfff2 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xcb00, 0xcb00,
++						0xcb00, 0xcb00,
++						0xcb00, 0xcb00,
++						0xcb00, 0xcb00 };
++#endif
+ VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1600000, 0xc1600000,
+ 					    0xc1600000, 0xc1600000 };
+ 
+@@ -171,6 +201,9 @@ void exec_vdup_vmov (void)
+     TEST_VDUP(, uint, u, 64, 1);
+     TEST_VDUP(, poly, p, 8, 8);
+     TEST_VDUP(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++    TEST_VDUP(, float, f, 16, 4);
++#endif
+     TEST_VDUP(, float, f, 32, 2);
+ 
+     TEST_VDUP(q, int, s, 8, 16);
+@@ -183,8 +216,26 @@ void exec_vdup_vmov (void)
+     TEST_VDUP(q, uint, u, 64, 2);
+     TEST_VDUP(q, poly, p, 8, 16);
+     TEST_VDUP(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++    TEST_VDUP(q, float, f, 16, 8);
++#endif
+     TEST_VDUP(q, float, f, 32, 4);
+ 
++#if defined (FP16_SUPPORTED)
++    switch (i) {
++    case 0:
++      CHECK_RESULTS_NAMED (TEST_MSG, expected0, "");
++      break;
++    case 1:
++      CHECK_RESULTS_NAMED (TEST_MSG, expected1, "");
++      break;
++    case 2:
++      CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
++      break;
++    default:
++      abort();
++    }
++#else
+     switch (i) {
+     case 0:
+       CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected0, "");
+@@ -198,6 +249,7 @@ void exec_vdup_vmov (void)
+     default:
+       abort();
+     }
++#endif
+   }
+ 
+   /* Do the same tests with vmov. Use the same expected results.  */
+@@ -216,6 +268,9 @@ void exec_vdup_vmov (void)
+     TEST_VMOV(, uint, u, 64, 1);
+     TEST_VMOV(, poly, p, 8, 8);
+     TEST_VMOV(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++    TEST_VMOV(, float, f, 16, 4);
++#endif
+     TEST_VMOV(, float, f, 32, 2);
+ 
+     TEST_VMOV(q, int, s, 8, 16);
+@@ -228,8 +283,26 @@ void exec_vdup_vmov (void)
+     TEST_VMOV(q, uint, u, 64, 2);
+     TEST_VMOV(q, poly, p, 8, 16);
+     TEST_VMOV(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++    TEST_VMOV(q, float, f, 16, 8);
++#endif
+     TEST_VMOV(q, float, f, 32, 4);
+ 
++#if defined (FP16_SUPPORTED)
++    switch (i) {
++    case 0:
++      CHECK_RESULTS_NAMED (TEST_MSG, expected0, "");
++      break;
++    case 1:
++      CHECK_RESULTS_NAMED (TEST_MSG, expected1, "");
++      break;
++    case 2:
++      CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
++      break;
++    default:
++      abort();
++    }
++#else
+     switch (i) {
+     case 0:
+       CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected0, "");
+@@ -243,6 +316,8 @@ void exec_vdup_vmov (void)
+     default:
+       abort();
+     }
++#endif
++
+   }
+ }
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c
+@@ -17,6 +17,10 @@ VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7,
+ 					0xf7, 0xf7, 0xf7, 0xf7 };
+ VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xca80, 0xca80,
++					       0xca80, 0xca80 };
++#endif
+ VECT_VAR_DECL(expected,int,8,16) [] = { 0xf2, 0xf2, 0xf2, 0xf2,
+ 					0xf2, 0xf2, 0xf2, 0xf2,
+ 					0xf2, 0xf2, 0xf2, 0xf2,
+@@ -43,10 +47,16 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf5, 0xf5, 0xf5, 0xf5,
+ 					 0xf5, 0xf5, 0xf5, 0xf5 };
+ VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1,
+ 					 0xfff1, 0xfff1, 0xfff1, 0xfff1 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xca80, 0xca80,
++					       0xca80, 0xca80,
++					       0xca80, 0xca80,
++					       0xca80, 0xca80 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1700000, 0xc1700000,
+ 					   0xc1700000, 0xc1700000 };
+ 
+-#define TEST_MSG "VDUP_LANE/VDUP_LANEQ"
++#define TEST_MSG "VDUP_LANE/VDUPQ_LANE"
+ void exec_vdup_lane (void)
+ {
+   /* Basic test: vec1=vdup_lane(vec2, lane), then store the result.  */
+@@ -63,6 +73,9 @@ void exec_vdup_lane (void)
+   clean_results ();
+ 
+   TEST_MACRO_64BITS_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+ 
+   /* Choose lane arbitrarily.  */
+@@ -76,6 +89,9 @@ void exec_vdup_lane (void)
+   TEST_VDUP_LANE(, uint, u, 64, 1, 1, 0);
+   TEST_VDUP_LANE(, poly, p, 8, 8, 8, 7);
+   TEST_VDUP_LANE(, poly, p, 16, 4, 4, 3);
++#if defined (FP16_SUPPORTED)
++  TEST_VDUP_LANE(, float, f, 16, 4, 4, 3);
++#endif
+   TEST_VDUP_LANE(, float, f, 32, 2, 2, 1);
+ 
+   TEST_VDUP_LANE(q, int, s, 8, 16, 8, 2);
+@@ -88,9 +104,133 @@ void exec_vdup_lane (void)
+   TEST_VDUP_LANE(q, uint, u, 64, 2, 1, 0);
+   TEST_VDUP_LANE(q, poly, p, 8, 16, 8, 5);
+   TEST_VDUP_LANE(q, poly, p, 16, 8, 4, 1);
++#if defined (FP16_SUPPORTED)
++  TEST_VDUP_LANE(q, float, f, 16, 8, 4, 3);
++#endif
+   TEST_VDUP_LANE(q, float, f, 32, 4, 2, 1);
+ 
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS (TEST_MSG, "");
++#else
+   CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
++#endif
++
++#if defined (__aarch64__)
++
++#undef TEST_MSG
++#define TEST_MSG "VDUP_LANEQ/VDUPQ_LANEQ"
++
++  /* Expected results for vdup*_laneq tests.  */
++VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd,
++					0xfd, 0xfd, 0xfd, 0xfd };
++VECT_VAR_DECL(expected2,int,16,4) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff2 };
++VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0xfffffff1 };
++VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff,
++					 0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected2,uint,16,4) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
++VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 };
++VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7,
++					 0xf7, 0xf7, 0xf7, 0xf7 };
++VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
++VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80,
++						0xca80, 0xca80 };
++#endif
++VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb,
++					 0xfb, 0xfb, 0xfb, 0xfb,
++					 0xfb, 0xfb, 0xfb, 0xfb,
++					 0xfb, 0xfb, 0xfb, 0xfb };
++VECT_VAR_DECL(expected2,int,16,8) [] = { 0xfff7, 0xfff7, 0xfff7, 0xfff7,
++					 0xfff7, 0xfff7, 0xfff7, 0xfff7 };
++VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1,
++					 0xfffffff1, 0xfffffff1 };
++VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0,
++					 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected2,uint,8,16) [] = { 0xf5, 0xf5, 0xf5, 0xf5,
++					  0xf5, 0xf5, 0xf5, 0xf5,
++					  0xf5, 0xf5, 0xf5, 0xf5,
++					  0xf5, 0xf5, 0xf5, 0xf5 };
++VECT_VAR_DECL(expected2,uint,16,8) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1,
++					  0xfff1, 0xfff1, 0xfff1, 0xfff1 };
++VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff0, 0xfffffff0,
++					  0xfffffff0, 0xfffffff0 };
++VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0,
++					  0xfffffffffffffff0 };
++VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf5, 0xf5, 0xf5, 0xf5,
++					  0xf5, 0xf5, 0xf5, 0xf5,
++					  0xf5, 0xf5, 0xf5, 0xf5,
++					  0xf5, 0xf5, 0xf5, 0xf5 };
++VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1,
++					  0xfff1, 0xfff1, 0xfff1, 0xfff1 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xc880, 0xc880,
++						0xc880, 0xc880,
++						0xc880, 0xc880,
++						0xc880, 0xc880 };
++#endif
++VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1700000, 0xc1700000,
++					    0xc1700000, 0xc1700000 };
++
++  /* Clean all results for vdup*_laneq tests.  */
++  clean_results ();
++  /* Basic test: vec1=vdup_lane(vec2, lane), then store the result.  */
++#define TEST_VDUP_LANEQ(Q, T1, T2, W, N, N2, L)				\
++  VECT_VAR(vector_res, T1, W, N) =					\
++    vdup##Q##_laneq_##T2##W(VECT_VAR(vector, T1, W, N2), L);		\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
++
++  /* Input vector can only have 64 bits.  */
++  DECL_VARIABLE_128BITS_VARIANTS(vector);
++
++  clean_results ();
++
++  TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD(vector, buffer, q, float, f, 32, 4);
++
++  /* Choose lane arbitrarily.  */
++  TEST_VDUP_LANEQ(, int, s, 8, 8, 16, 13);
++  TEST_VDUP_LANEQ(, int, s, 16, 4, 8, 2);
++  TEST_VDUP_LANEQ(, int, s, 32, 2, 4, 1);
++  TEST_VDUP_LANEQ(, int, s, 64, 1, 2, 0);
++  TEST_VDUP_LANEQ(, uint, u, 8, 8, 16, 15);
++  TEST_VDUP_LANEQ(, uint, u, 16, 4, 8, 3);
++  TEST_VDUP_LANEQ(, uint, u, 32, 2, 4, 1);
++  TEST_VDUP_LANEQ(, uint, u, 64, 1, 2, 0);
++  TEST_VDUP_LANEQ(, poly, p, 8, 8, 16, 7);
++  TEST_VDUP_LANEQ(, poly, p, 16, 4, 8, 3);
++#if defined (FP16_SUPPORTED)
++  TEST_VDUP_LANEQ(, float, f, 16, 4, 8, 3);
++#endif
++  TEST_VDUP_LANEQ(, float, f, 32, 2, 4, 1);
++
++  TEST_VDUP_LANEQ(q, int, s, 8, 16, 16, 11);
++  TEST_VDUP_LANEQ(q, int, s, 16, 8, 8, 7);
++  TEST_VDUP_LANEQ(q, int, s, 32, 4, 4, 1);
++  TEST_VDUP_LANEQ(q, int, s, 64, 2, 2, 0);
++  TEST_VDUP_LANEQ(q, uint, u, 8, 16, 16, 5);
++  TEST_VDUP_LANEQ(q, uint, u, 16, 8, 8, 1);
++  TEST_VDUP_LANEQ(q, uint, u, 32, 4, 4, 0);
++  TEST_VDUP_LANEQ(q, uint, u, 64, 2, 2, 0);
++  TEST_VDUP_LANEQ(q, poly, p, 8, 16, 16, 5);
++  TEST_VDUP_LANEQ(q, poly, p, 16, 8, 8, 1);
++#if defined (FP16_SUPPORTED)
++  TEST_VDUP_LANEQ(q, float, f, 16, 8, 8, 7);
++#endif
++  TEST_VDUP_LANEQ(q, float, f, 32, 4, 4, 1);
++
++  CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
++#if defined (FP16_SUPPORTED)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected2, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected2, "");
++#endif
++
++#endif /* __aarch64__.  */
+ }
+ 
+ int main (void)
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c
+@@ -0,0 +1,137 @@
++/* { dg-do run } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define A -16
++#define B -15
++#define C -14
++#define D -13
++#define E -12
++#define F -11
++#define G -10
++#define H -9
++
++#define F16_C(a) ((__fp16) a)
++#define AF F16_C (A)
++#define BF F16_C (B)
++#define CF F16_C (C)
++#define DF F16_C (D)
++#define EF F16_C (E)
++#define FF F16_C (F)
++#define GF F16_C (G)
++#define HF F16_C (H)
++
++#define S16_C(a) ((int16_t) a)
++#define AS S16_C (A)
++#define BS S16_C (B)
++#define CS S16_C (C)
++#define DS S16_C (D)
++#define ES S16_C (E)
++#define FS S16_C (F)
++#define GS S16_C (G)
++#define HS S16_C (H)
++
++#define U16_C(a) ((int16_t) a)
++#define AU U16_C (A)
++#define BU U16_C (B)
++#define CU U16_C (C)
++#define DU U16_C (D)
++#define EU U16_C (E)
++#define FU U16_C (F)
++#define GU U16_C (G)
++#define HU U16_C (H)
++
++#define P16_C(a) ((poly16_t) a)
++#define AP P16_C (A)
++#define BP P16_C (B)
++#define CP P16_C (C)
++#define DP P16_C (D)
++#define EP P16_C (E)
++#define FP P16_C (F)
++#define GP P16_C (G)
++#define HP P16_C (H)
++
++/* Expected results for vduph_lane.  */
++float16_t expected_f16 = AF;
++int16_t expected_s16 = DS;
++uint16_t expected_u16 = BU;
++poly16_t expected_p16 = CP;
++
++/* Expected results for vduph_laneq.  */
++float16_t expected_q_f16 = EF;
++int16_t expected_q_s16 = BS;
++uint16_t expected_q_u16 = GU;
++poly16_t expected_q_p16 = FP;
++
++void exec_vduph_lane_f16 (void)
++{
++  /* vduph_lane.  */
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  DECL_VARIABLE(vsrc, int, 16, 4);
++  DECL_VARIABLE(vsrc, uint, 16, 4);
++  DECL_VARIABLE(vsrc, poly, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {AF, BF, CF, DF};
++  VECT_VAR_DECL (buf_src, int, 16, 4) [] = {AS, BS, CS, DS};
++  VECT_VAR_DECL (buf_src, uint, 16, 4) [] = {AU, BU, CU, DU};
++  VECT_VAR_DECL (buf_src, poly, 16, 4) [] = {AP, BP, CP, DP};
++  VLOAD (vsrc, buf_src, , int, s, 16, 4);
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  VLOAD (vsrc, buf_src, , uint, u, 16, 4);
++  VLOAD (vsrc, buf_src, , poly, p, 16, 4);
++
++  float16_t res_f = vduph_lane_f16 (VECT_VAR (vsrc, float, 16, 4), 0);
++  if (* (unsigned short *) &res_f != * (unsigned short *) &expected_f16)
++    abort ();
++
++  int16_t res_s = vduph_lane_s16 (VECT_VAR (vsrc, int, 16, 4), 3);
++  if (* (unsigned short *) &res_s != * (unsigned short *) &expected_s16)
++    abort ();
++
++  uint16_t res_u = vduph_lane_u16 (VECT_VAR (vsrc, uint, 16, 4), 1);
++  if (* (unsigned short *) &res_u != * (unsigned short *) &expected_u16)
++    abort ();
++
++  poly16_t res_p = vduph_lane_p16 (VECT_VAR (vsrc, poly, 16, 4), 2);
++  if (* (unsigned short *) &res_p != * (unsigned short *) &expected_p16)
++    abort ();
++
++  /* vduph_laneq.  */
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  DECL_VARIABLE(vsrc, int, 16, 8);
++  DECL_VARIABLE(vsrc, uint, 16, 8);
++  DECL_VARIABLE(vsrc, poly, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {AF, BF, CF, DF, EF, FF, GF, HF};
++  VECT_VAR_DECL (buf_src, int, 16, 8) [] = {AS, BS, CS, DS, ES, FS, GS, HS};
++  VECT_VAR_DECL (buf_src, uint, 16, 8) [] = {AU, BU, CU, DU, EU, FU, GU, HU};
++  VECT_VAR_DECL (buf_src, poly, 16, 8) [] = {AP, BP, CP, DP, EP, FP, GP, HP};
++  VLOAD (vsrc, buf_src, q, int, s, 16, 8);
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  VLOAD (vsrc, buf_src, q, uint, u, 16, 8);
++  VLOAD (vsrc, buf_src, q, poly, p, 16, 8);
++
++  res_f = vduph_laneq_f16 (VECT_VAR (vsrc, float, 16, 8), 4);
++  if (* (unsigned short *) &res_f != * (unsigned short *) &expected_q_f16)
++    abort ();
++
++  res_s = vduph_laneq_s16 (VECT_VAR (vsrc, int, 16, 8), 1);
++  if (* (unsigned short *) &res_s != * (unsigned short *) &expected_q_s16)
++    abort ();
++
++  res_u = vduph_laneq_u16 (VECT_VAR (vsrc, uint, 16, 8), 6);
++  if (* (unsigned short *) &res_u != * (unsigned short *) &expected_q_u16)
++    abort ();
++
++  res_p = vduph_laneq_p16 (VECT_VAR (vsrc, poly, 16, 8), 5);
++  if (* (unsigned short *) &res_p != * (unsigned short *) &expected_q_p16)
++    abort ();
++}
++
++int
++main (void)
++{
++  exec_vduph_lane_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vext.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vext.c
+@@ -16,6 +16,10 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
+ VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf6, 0xf7, 0x55, 0x55,
+ 					0x55, 0x55, 0x55, 0x55 };
+ VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcb00, 0xca80,
++					       0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0x42066666 };
+ VECT_VAR_DECL(expected,int,8,16) [] = { 0xfe, 0xff, 0x11, 0x11,
+ 					0x11, 0x11, 0x11, 0x11,
+@@ -39,6 +43,12 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xfc, 0xfd, 0xfe, 0xff,
+ 					 0x55, 0x55, 0x55, 0x55 };
+ VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff6, 0xfff7, 0x66, 0x66,
+ 					 0x66, 0x66, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xc880, 0x4b4d,
++					       0x4b4d, 0x4b4d,
++					       0x4b4d, 0x4b4d,
++					       0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1500000, 0x4204cccd,
+ 					   0x4204cccd, 0x4204cccd };
+ 
+@@ -60,6 +70,10 @@ void exec_vext (void)
+   clean_results ();
+ 
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
++#ifdef FP16_SUPPORTED
++  VLOAD(vector1, buffer, , float, f, 16, 4);
++  VLOAD(vector1, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector1, buffer, , float, f, 32, 2);
+   VLOAD(vector1, buffer, q, float, f, 32, 4);
+ 
+@@ -74,6 +88,9 @@ void exec_vext (void)
+   VDUP(vector2, , uint, u, 64, 1, 0x88);
+   VDUP(vector2, , poly, p, 8, 8, 0x55);
+   VDUP(vector2, , poly, p, 16, 4, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, , float, f, 16, 4, 14.6f);   /* 14.6f is 0x4b4d.  */
++#endif
+   VDUP(vector2, , float, f, 32, 2, 33.6f);
+ 
+   VDUP(vector2, q, int, s, 8, 16, 0x11);
+@@ -86,6 +103,9 @@ void exec_vext (void)
+   VDUP(vector2, q, uint, u, 64, 2, 0x88);
+   VDUP(vector2, q, poly, p, 8, 16, 0x55);
+   VDUP(vector2, q, poly, p, 16, 8, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, q, float, f, 16, 8, 14.6f);
++#endif
+   VDUP(vector2, q, float, f, 32, 4, 33.2f);
+ 
+   /* Choose arbitrary extract offsets.  */
+@@ -99,6 +119,9 @@ void exec_vext (void)
+   TEST_VEXT(, uint, u, 64, 1, 0);
+   TEST_VEXT(, poly, p, 8, 8, 6);
+   TEST_VEXT(, poly, p, 16, 4, 2);
++#if defined (FP16_SUPPORTED)
++  TEST_VEXT(, float, f, 16, 4, 2);
++#endif
+   TEST_VEXT(, float, f, 32, 2, 1);
+ 
+   TEST_VEXT(q, int, s, 8, 16, 14);
+@@ -111,9 +134,16 @@ void exec_vext (void)
+   TEST_VEXT(q, uint, u, 64, 2, 1);
+   TEST_VEXT(q, poly, p, 8, 16, 12);
+   TEST_VEXT(q, poly, p, 16, 8, 6);
++#if defined (FP16_SUPPORTED)
++  TEST_VEXT(q, float, f, 16, 8, 7);
++#endif
+   TEST_VEXT(q, float, f, 32, 4, 3);
+ 
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS (TEST_MSG, "");
++#else
+   CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
++#endif
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfma.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfma.c
+@@ -3,11 +3,19 @@
+ #include "compute-ref-data.h"
+ 
+ #ifdef __ARM_FEATURE_FMA
++
+ /* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0x61c6, 0x61c8, 0x61ca, 0x61cc };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0x6435, 0x6436, 0x6437, 0x6438,
++					      0x6439, 0x643a, 0x643b, 0x643c };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x4438ca3d, 0x44390a3d };
+-VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x44869eb8, 0x4486beb8, 0x4486deb8, 0x4486feb8 };
++VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x44869eb8, 0x4486beb8,
++					   0x4486deb8, 0x4486feb8 };
+ #ifdef __aarch64__
+-VECT_VAR_DECL(expected,hfloat,64,2) [] = { 0x408906e1532b8520, 0x40890ee1532b8520 };
++VECT_VAR_DECL(expected,hfloat,64,2) [] = { 0x408906e1532b8520,
++					   0x40890ee1532b8520 };
+ #endif
+ 
+ #define TEST_MSG "VFMA/VFMAQ"
+@@ -44,6 +52,18 @@ void exec_vfma (void)
+   DECL_VARIABLE(VAR, float, 32, 4);
+ #endif
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector1, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector3, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 4);
++
++  DECL_VARIABLE(vector1, float, 16, 8);
++  DECL_VARIABLE(vector2, float, 16, 8);
++  DECL_VARIABLE(vector3, float, 16, 8);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++
+   DECL_VFMA_VAR(vector1);
+   DECL_VFMA_VAR(vector2);
+   DECL_VFMA_VAR(vector3);
+@@ -52,6 +72,10 @@ void exec_vfma (void)
+   clean_results ();
+ 
+   /* Initialize input "vector1" from "buffer".  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector1, buffer, , float, f, 16, 4);
++  VLOAD(vector1, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector1, buffer, , float, f, 32, 2);
+   VLOAD(vector1, buffer, q, float, f, 32, 4);
+ #ifdef __aarch64__
+@@ -59,13 +83,21 @@ void exec_vfma (void)
+ #endif
+ 
+   /* Choose init value arbitrarily.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 9.3f);
++  VDUP(vector2, q, float, f, 16, 8, 29.7f);
++#endif
+   VDUP(vector2, , float, f, 32, 2, 9.3f);
+   VDUP(vector2, q, float, f, 32, 4, 29.7f);
+ #ifdef __aarch64__
+   VDUP(vector2, q, float, f, 64, 2, 15.8f);
+ #endif
+-  
++
+   /* Choose init value arbitrarily.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector3, , float, f, 16, 4, 81.2f);
++  VDUP(vector3, q, float, f, 16, 8, 36.8f);
++#endif
+   VDUP(vector3, , float, f, 32, 2, 81.2f);
+   VDUP(vector3, q, float, f, 32, 4, 36.8f);
+ #ifdef __aarch64__
+@@ -73,12 +105,20 @@ void exec_vfma (void)
+ #endif
+ 
+   /* Execute the tests.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VFMA(, float, f, 16, 4);
++  TEST_VFMA(q, float, f, 16, 8);
++#endif
+   TEST_VFMA(, float, f, 32, 2);
+   TEST_VFMA(q, float, f, 32, 4);
+ #ifdef __aarch64__
+   TEST_VFMA(q, float, f, 64, 2);
+ #endif
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
+   CHECK_VFMA_RESULTS (TEST_MSG, "");
+ }
+ #endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++ 0x0000 /* 0.000000 */,
++ 0x0000 /* 0.000000 */,
++ 0x3944 /* 0.658203 */,
++ 0xcefa /* -27.906250 */,
++ 0x5369 /* 59.281250 */,
++ 0x35ba /* 0.357910 */,
++ 0xc574 /* -5.453125 */,
++ 0xc5e6 /* -5.898438 */,
++ 0x3f66 /* 1.849609 */,
++ 0x5665 /* 102.312500 */,
++ 0xc02d /* -2.087891 */,
++ 0x4d79 /* 21.890625 */,
++ 0x547b /* 71.687500 */,
++ 0xcdf0 /* -23.750000 */,
++ 0xc625 /* -6.144531 */,
++ 0x4cf9 /* 19.890625 */,
++ 0x7e00 /* nan */,
++ 0x7e00 /* nan */
++};
++
++#define TEST_MSG "VFMAH_F16"
++#define INSN_NAME vfmah_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "ternary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c
+@@ -0,0 +1,908 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (123.4)
++#define A1 FP16_C (-5.8)
++#define A2 FP16_C (-0.0)
++#define A3 FP16_C (10)
++#define A4 FP16_C (123412.43)
++#define A5 FP16_C (-5.8)
++#define A6 FP16_C (90.8)
++#define A7 FP16_C (24)
++
++#define B0 FP16_C (23.4)
++#define B1 FP16_C (-5.8)
++#define B2 FP16_C (8.9)
++#define B3 FP16_C (4.0)
++#define B4 FP16_C (3.4)
++#define B5 FP16_C (-550.8)
++#define B6 FP16_C (-31.8)
++#define B7 FP16_C (20000.0)
++
++/* Expected results for vfma_lane.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 4) []
++  = { 0x613E /* A0 + B0 * B0.  */,
++      0xD86D /* A1 + B1 * B0.  */,
++      0x5A82 /* A2 + B2 * B0.  */,
++      0x567A /* A3 + B3 * B0.  */};
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 4) []
++  = { 0xCA33 /* A0 + B0 * B1.  */,
++      0x4EF6 /* A1 + B1 * B1.  */,
++      0xD274 /* A2 + B2 * B1.  */,
++      0xCA9A /* A3 + B3 * B1.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 4) []
++  = { 0x5D2F /* A0 + B0 * B2.  */,
++      0xD32D /* A1 + B1 * B2.  */,
++      0x54F3 /* A2 + B2 * B2.  */,
++      0x51B3 /* A3 + B3 * B2.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 4) []
++  = { 0x5AC8 /* A0 + B0 * B3.  */,
++      0xCF40 /* A1 + B1 * B3.  */,
++      0x5073 /* A2 + B2 * B3.  */,
++      0x4E80 /* A3 + B3 * B3.  */ };
++
++/* Expected results for vfmaq_lane.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 8) []
++  = { 0x613E /* A0 + B0 * B0.  */,
++      0xD86D /* A1 + B1 * B0.  */,
++      0x5A82 /* A2 + B2 * B0.  */,
++      0x567A /* A3 + B3 * B0.  */,
++      0x7C00 /* A4 + B4 * B0.  */,
++      0xF24D /* A5 + B5 * B0.  */,
++      0xE11B /* A6 + B6 * B0.  */,
++      0x7C00 /* A7 + B7 * B0.  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 8) []
++  = { 0xCA33 /* A0 + B0 * B1.  */,
++      0x4EF6 /* A1 + B1 * B1.  */,
++      0xD274 /* A2 + B2 * B1.  */,
++      0xCA9A /* A3 + B3 * B1.  */,
++      0x7C00 /* A4 + B4 * B1.  */,
++      0x6A3B /* A5 + B5 * B1.  */,
++      0x5C4D /* A6 + B6 * B1.  */,
++      0xFC00 /* A7 + B7 * B1.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 8) []
++  = { 0x5D2F /* A0 + B0 * B2.  */,
++      0xD32D /* A1 + B1 * B2.  */,
++      0x54F3 /* A2 + B2 * B2.  */,
++      0x51B3 /* A3 + B3 * B2.  */,
++      0x7C00 /* A4 + B4 * B2.  */,
++      0xECCB /* A5 + B5 * B2.  */,
++      0xDA01 /* A6 + B6 * B2.  */,
++      0x7C00 /* A7 + B7 * B2.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 8) []
++  = { 0x5AC8 /* A0 + B0 * B3.  */,
++      0xCF40 /* A1 + B1 * B3.  */,
++      0x5073 /* A2 + B2 * B3.  */,
++      0x4E80 /* A3 + B3 * B3.  */,
++      0x7C00 /* A4 + B4 * B3.  */,
++      0xE851 /* A5 + B5 * B3.  */,
++      0xD08C /* A6 + B6 * B3.  */,
++      0x7C00 /* A7 + B7 * B3.  */ };
++
++/* Expected results for vfma_laneq.  */
++VECT_VAR_DECL (expected0_laneq_static, hfloat, 16, 4) []
++  = { 0x613E /* A0 + B0 * B0.  */,
++      0xD86D /* A1 + B1 * B0.  */,
++      0x5A82 /* A2 + B2 * B0.  */,
++      0x567A /* A3 + B3 * B0.  */ };
++
++VECT_VAR_DECL (expected1_laneq_static, hfloat, 16, 4) []
++  = { 0xCA33 /* A0 + B0 * B1.  */,
++      0x4EF6 /* A1 + B1 * B1.  */,
++      0xD274 /* A2 + B2 * B1.  */,
++      0xCA9A /* A3 + B3 * B1.  */ };
++
++VECT_VAR_DECL (expected2_laneq_static, hfloat, 16, 4) []
++  = { 0x5D2F /* A0 + B0 * B2.  */,
++      0xD32D /* A1 + B1 * B2.  */,
++      0x54F3 /* A2 + B2 * B2.  */,
++      0x51B3 /* A3 + B3 * B2.  */ };
++
++VECT_VAR_DECL (expected3_laneq_static, hfloat, 16, 4) []
++  = { 0x5AC8 /* A0 + B0 * B3.  */,
++      0xCF40 /* A1 + B1 * B3.  */,
++      0x5073 /* A2 + B2 * B3.  */,
++      0x4E80 /* A3 + B3 * B3.  */ };
++
++VECT_VAR_DECL (expected4_laneq_static, hfloat, 16, 4) []
++  = { 0x5A58 /* A0 + B0 * B4.  */,
++      0xCE62 /* A1 + B1 * B4.  */,
++      0x4F91 /* A2 + B2 * B4.  */,
++      0x4DE6 /* A3 + B3 * B4.  */ };
++
++VECT_VAR_DECL (expected5_laneq_static, hfloat, 16, 4) []
++  = { 0xF23D /* A0 + B0 * B5.  */,
++      0x6A3B /* A1 + B1 * B5.  */,
++      0xECCA /* A2 + B2 * B5.  */,
++      0xE849 /* A3 + B3 * B5.  */ };
++
++VECT_VAR_DECL (expected6_laneq_static, hfloat, 16, 4) []
++  = { 0xE0DA /* A0 + B0 * B6.  */,
++      0x5995 /* A1 + B1 * B6.  */,
++      0xDC6C /* A2 + B2 * B6.  */,
++      0xD753 /* A3 + B3 * B6.  */ };
++
++VECT_VAR_DECL (expected7_laneq_static, hfloat, 16, 4) []
++  = { 0x7C00 /* A0 + B0 * B7.  */,
++      0xFC00 /* A1 + B1 * B7.  */,
++      0x7C00 /* A2 + B2 * B7.  */,
++      0x7C00 /* A3 + B3 * B7.  */ };
++
++/* Expected results for vfmaq_laneq.  */
++VECT_VAR_DECL (expected0_laneq_static, hfloat, 16, 8) []
++  = { 0x613E /* A0 + B0 * B0.  */,
++      0xD86D /* A1 + B1 * B0.  */,
++      0x5A82 /* A2 + B2 * B0.  */,
++      0x567A /* A3 + B3 * B0.  */,
++      0x7C00 /* A4 + B4 * B0.  */,
++      0xF24D /* A5 + B5 * B0.  */,
++      0xE11B /* A6 + B6 * B0.  */,
++      0x7C00 /* A7 + B7 * B0.  */ };
++
++VECT_VAR_DECL (expected1_laneq_static, hfloat, 16, 8) []
++  = { 0xCA33 /* A0 + B0 * B1.  */,
++      0x4EF6 /* A1 + B1 * B1.  */,
++      0xD274 /* A2 + B2 * B1.  */,
++      0xCA9A /* A3 + B3 * B1.  */,
++      0x7C00 /* A4 + B4 * B1.  */,
++      0x6A3B /* A5 + B5 * B1.  */,
++      0x5C4D /* A6 + B6 * B1.  */,
++      0xFC00 /* A7 + B7 * B1.  */ };
++
++VECT_VAR_DECL (expected2_laneq_static, hfloat, 16, 8) []
++  = { 0x5D2F /* A0 + B0 * B2.  */,
++      0xD32D /* A1 + B1 * B2.  */,
++      0x54F3 /* A2 + B2 * B2.  */,
++      0x51B3 /* A3 + B3 * B2.  */,
++      0x7C00 /* A4 + B4 * B2.  */,
++      0xECCB /* A5 + B5 * B2.  */,
++      0xDA01 /* A6 + B6 * B2.  */,
++      0x7C00 /* A7 + B7 * B2.  */ };
++
++VECT_VAR_DECL (expected3_laneq_static, hfloat, 16, 8) []
++  = { 0x5AC8 /* A0 + B0 * B3.  */,
++      0xCF40 /* A1 + B1 * B3.  */,
++      0x5073 /* A2 + B2 * B3.  */,
++      0x4E80 /* A3 + B3 * B3.  */,
++      0x7C00 /* A4 + B4 * B3.  */,
++      0xE851 /* A5 + B5 * B3.  */,
++      0xD08C /* A6 + B6 * B3.  */,
++      0x7C00 /* A7 + B7 * B3.  */ };
++
++VECT_VAR_DECL (expected4_laneq_static, hfloat, 16, 8) []
++  = { 0x5A58 /* A0 + B0 * B4.  */,
++      0xCE62 /* A1 + B1 * B4.  */,
++      0x4F91 /* A2 + B2 * B4.  */,
++      0x4DE6 /* A3 + B3 * B4.  */,
++      0x7C00 /* A4 + B4 * B4.  */,
++      0xE757 /* A5 + B5 * B4.  */,
++      0xCC54 /* A6 + B6 * B4.  */,
++      0x7C00 /* A7 + B7 * B4.  */ };
++
++VECT_VAR_DECL (expected5_laneq_static, hfloat, 16, 8) []
++  = { 0xF23D /* A0 + B0 * B5.  */,
++      0x6A3B /* A1 + B1 * B5.  */,
++      0xECCA /* A2 + B2 * B5.  */,
++      0xE849 /* A3 + B3 * B5.  */,
++      0x7C00 /* A4 + B4 * B5.  */,
++      0x7C00 /* A5 + B5 * B5.  */,
++      0x744D /* A6 + B6 * B5.  */,
++      0xFC00 /* A7 + B7 * B5.  */ };
++
++VECT_VAR_DECL (expected6_laneq_static, hfloat, 16, 8) []
++  = { 0xE0DA /* A0 + B0 * B6.  */,
++      0x5995 /* A1 + B1 * B6.  */,
++      0xDC6C /* A2 + B2 * B6.  */,
++      0xD753 /* A3 + B3 * B6.  */,
++      0x7C00 /* A4 + B4 * B6.  */,
++      0x7447 /* A5 + B5 * B6.  */,
++      0x644E /* A6 + B6 * B6.  */,
++      0xFC00 /* A7 + B7 * B6.  */ };
++
++VECT_VAR_DECL (expected7_laneq_static, hfloat, 16, 8) []
++  = { 0x7C00 /* A0 + B0 * B7.  */,
++      0xFC00 /* A1 + B1 * B7.  */,
++      0x7C00 /* A2 + B2 * B7.  */,
++      0x7C00 /* A3 + B3 * B7.  */,
++      0x7C00 /* A4 + B4 * B7.  */,
++      0xFC00 /* A5 + B5 * B7.  */,
++      0xFC00 /* A6 + B6 * B7.  */,
++      0x7C00 /* A7 + B7 * B7.  */ };
++
++/* Expected results for vfms_lane.  */
++VECT_VAR_DECL (expected0_fms_static, hfloat, 16, 4) []
++  = { 0xDEA2 /* A0 + (-B0) * B0.  */,
++      0x5810 /* A1 + (-B1) * B0.  */,
++      0xDA82 /* A2 + (-B2) * B0.  */,
++      0xD53A /* A3 + (-B3) * B0.  */ };
++
++VECT_VAR_DECL (expected1_fms_static, hfloat, 16, 4) []
++  = { 0x5C0D /* A0 + (-B0) * B1.  */,
++      0xD0EE /* A1 + (-B1) * B1.  */,
++      0x5274 /* A2 + (-B2) * B1.  */,
++      0x5026 /* A3 + (-B3) * B1.  */ };
++
++VECT_VAR_DECL (expected2_fms_static, hfloat, 16, 4) []
++  = { 0xD54E /* A0 + (-B0) * B2.  */,
++      0x51BA /* A1 + (-B1) * B2.  */,
++      0xD4F3 /* A2 + (-B2) * B2.  */,
++      0xCE66 /* A3 + (-B3) * B2.  */ };
++
++VECT_VAR_DECL (expected3_fms_static, hfloat, 16, 4) []
++  = { 0x4F70 /* A0 + (-B0) * B3.  */,
++      0x4C5A /* A1 + (-B1) * B3.  */,
++      0xD073 /* A2 + (-B2) * B3.  */,
++      0xC600 /* A3 + (-B3) * B3.  */ };
++
++/* Expected results for vfmsq_lane.  */
++VECT_VAR_DECL (expected0_fms_static, hfloat, 16, 8) []
++  = { 0xDEA2 /* A0 + (-B0) * B0.  */,
++      0x5810 /* A1 + (-B1) * B0.  */,
++      0xDA82 /* A2 + (-B2) * B0.  */,
++      0xD53A /* A3 + (-B3) * B0.  */,
++      0x7C00 /* A4 + (-B4) * B0.  */,
++      0x724B /* A5 + (-B5) * B0.  */,
++      0x6286 /* A6 + (-B6) * B0.  */,
++      0xFC00 /* A7 + (-B7) * B0.  */ };
++
++VECT_VAR_DECL (expected1_fms_static, hfloat, 16, 8) []
++  = { 0x5C0D /* A0 + (-B0) * B1.  */,
++      0xD0EE /* A1 + (-B1) * B1.  */,
++      0x5274 /* A2 + (-B2) * B1.  */,
++      0x5026 /* A3 + (-B3) * B1.  */,
++      0x7C00 /* A4 + (-B4) * B1.  */,
++      0xEA41 /* A5 + (-B5) * B1.  */,
++      0xD5DA /* A6 + (-B6) * B1.  */,
++      0x7C00 /* A7 + (-B7) * B1.  */ };
++
++VECT_VAR_DECL (expected2_fms_static, hfloat, 16, 8) []
++  = { 0xD54E /* A0 + (-B0) * B2.  */,
++      0x51BA /* A1 + (-B1) * B2.  */,
++      0xD4F3 /* A2 + (-B2) * B2.  */,
++      0xCE66 /* A3 + (-B3) * B2.  */,
++      0x7C00 /* A4 + (-B4) * B2.  */,
++      0x6CC8 /* A5 + (-B5) * B2.  */,
++      0x5DD7 /* A6 + (-B6) * B2.  */,
++      0xFC00 /* A7 + (-B7) * B2.  */ };
++
++VECT_VAR_DECL (expected3_fms_static, hfloat, 16, 8) []
++  = { 0x4F70 /* A0 + (-B0) * B3.  */,
++      0x4C5A /* A1 + (-B1) * B3.  */,
++      0xD073 /* A2 + (-B2) * B3.  */,
++      0xC600 /* A3 + (-B3) * B3.  */,
++      0x7C00 /* A4 + (-B4) * B3.  */,
++      0x684B /* A5 + (-B5) * B3.  */,
++      0x5AD0 /* A6 + (-B6) * B3.  */,
++      0xFC00 /* A7 + (-B7) * B3.  */ };
++
++/* Expected results for vfms_laneq.  */
++VECT_VAR_DECL (expected0_fms_laneq_static, hfloat, 16, 4) []
++  = { 0xDEA2 /* A0 + (-B0) * B0.  */,
++      0x5810 /* A1 + (-B1) * B0.  */,
++      0xDA82 /* A2 + (-B2) * B0.  */,
++      0xD53A /* A3 + (-B3) * B0.  */ };
++
++VECT_VAR_DECL (expected1_fms_laneq_static, hfloat, 16, 4) []
++  = { 0x5C0D /* A0 + (-B0) * B1.  */,
++      0xD0EE /* A1 + (-B1) * B1.  */,
++      0x5274 /* A2 + (-B2) * B1.  */,
++      0x5026 /* A3 + (-B3) * B1.  */ };
++
++VECT_VAR_DECL (expected2_fms_laneq_static, hfloat, 16, 4) []
++  = { 0xD54E /* A0 + (-B0) * B2.  */,
++      0x51BA /* A1 + (-B1) * B2.  */,
++      0xD4F3 /* A2 + (-B2) * B2.  */,
++      0xCE66 /* A3 + (-B3) * B2.  */ };
++
++VECT_VAR_DECL (expected3_fms_laneq_static, hfloat, 16, 4) []
++  = { 0x4F70 /* A0 + (-B0) * B3.  */,
++      0x4C5A /* A1 + (-B1) * B3.  */,
++      0xD073 /* A2 + (-B2) * B3.  */,
++      0xC600 /* A3 + (-B3) * B3.  */ };
++
++VECT_VAR_DECL (expected4_fms_laneq_static, hfloat, 16, 4) []
++  = { 0x5179 /* A0 + (-B0) * B4.  */,
++      0x4AF6 /* A1 + (-B1) * B4.  */,
++      0xCF91 /* A2 + (-B2) * B4.  */,
++      0xC334 /* A3 + (-B3) * B4.  */ };
++
++VECT_VAR_DECL (expected5_fms_laneq_static, hfloat, 16, 4) []
++  = { 0x725C /* A0 + (-B0) * B5.  */,
++      0xEA41 /* A1 + (-B1) * B5.  */,
++      0x6CCA /* A2 + (-B2) * B5.  */,
++      0x6853 /* A3 + (-B3) * B5.  */ };
++
++VECT_VAR_DECL (expected6_fms_laneq_static, hfloat, 16, 4) []
++  = { 0x62C7 /* A0 + (-B0) * B6.  */,
++      0xD9F2 /* A1 + (-B1) * B6.  */,
++      0x5C6C /* A2 + (-B2) * B6.  */,
++      0x584A /* A3 + (-B3) * B6.  */ };
++
++VECT_VAR_DECL (expected7_fms_laneq_static, hfloat, 16, 4) []
++  = { 0xFC00 /* A0 + (-B0) * B7.  */,
++      0x7C00 /* A1 + (-B1) * B7.  */,
++      0xFC00 /* A2 + (-B2) * B7.  */,
++      0xFC00 /* A3 + (-B3) * B7.  */ };
++
++/* Expected results for vfmsq_laneq.  */
++VECT_VAR_DECL (expected0_fms_laneq_static, hfloat, 16, 8) []
++  = { 0xDEA2 /* A0 + (-B0) * B0.  */,
++      0x5810 /* A1 + (-B1) * B0.  */,
++      0xDA82 /* A2 + (-B2) * B0.  */,
++      0xD53A /* A3 + (-B3) * B0.  */,
++      0x7C00 /* A4 + (-B4) * B0.  */,
++      0x724B /* A5 + (-B5) * B0.  */,
++      0x6286 /* A6 + (-B6) * B0.  */,
++      0xFC00 /* A7 + (-B7) * B0.  */ };
++
++VECT_VAR_DECL (expected1_fms_laneq_static, hfloat, 16, 8) []
++  = { 0x5C0D /* A0 + (-B0) * B1.  */,
++      0xD0EE /* A1 + (-B1) * B1.  */,
++      0x5274 /* A2 + (-B2) * B1.  */,
++      0x5026 /* A3 + (-B3) * B1.  */,
++      0x7C00 /* A4 + (-B4) * B1.  */,
++      0xEA41 /* A5 + (-B5) * B1.  */,
++      0xD5DA /* A6 + (-B6) * B1.  */,
++      0x7C00 /* A7 + (-B7) * B1.  */ };
++
++VECT_VAR_DECL (expected2_fms_laneq_static, hfloat, 16, 8) []
++  = { 0xD54E /* A0 + (-B0) * B2.  */,
++      0x51BA /* A1 + (-B1) * B2.  */,
++      0xD4F3 /* A2 + (-B2) * B2.  */,
++      0xCE66 /* A3 + (-B3) * B2.  */,
++      0x7C00 /* A4 + (-B4) * B2.  */,
++      0x6CC8 /* A5 + (-B5) * B2.  */,
++      0x5DD7 /* A6 + (-B6) * B2.  */,
++      0xFC00 /* A7 + (-B7) * B2.  */ };
++
++VECT_VAR_DECL (expected3_fms_laneq_static, hfloat, 16, 8) []
++  = { 0x4F70 /* A0 + (-B0) * B3.  */,
++      0x4C5A /* A1 + (-B1) * B3.  */,
++      0xD073 /* A2 + (-B2) * B3.  */,
++      0xC600 /* A3 + (-B3) * B3.  */,
++      0x7C00 /* A4 + (-B4) * B3.  */,
++      0x684B /* A5 + (-B5) * B3.  */,
++      0x5AD0 /* A6 + (-B6) * B3.  */,
++      0xFC00 /* A7 + (-B7) * B3.  */ };
++
++VECT_VAR_DECL (expected4_fms_laneq_static, hfloat, 16, 8) []
++  = { 0x5179 /* A0 + (-B0) * B4.  */,
++      0x4AF6 /* A1 + (-B1) * B4.  */,
++      0xCF91 /* A2 + (-B2) * B4.  */,
++      0xC334 /* A3 + (-B3) * B4.  */,
++      0x7C00 /* A4 + (-B4) * B4.  */,
++      0x674C /* A5 + (-B5) * B4.  */,
++      0x5A37 /* A6 + (-B6) * B4.  */,
++      0xFC00 /* A7 + (-B7) * B4.  */ };
++
++VECT_VAR_DECL (expected5_fms_laneq_static, hfloat, 16, 8) []
++  = { 0x725C /* A0 + (-B0) * B5.  */,
++      0xEA41 /* A1 + (-B1) * B5.  */,
++      0x6CCA /* A2 + (-B2) * B5.  */,
++      0x6853 /* A3 + (-B3) * B5.  */,
++      0x7C00 /* A4 + (-B4) * B5.  */,
++      0xFC00 /* A5 + (-B5) * B5.  */,
++      0xF441 /* A6 + (-B6) * B5.  */,
++      0x7C00 /* A7 + (-B7) * B5.  */ };
++
++VECT_VAR_DECL (expected6_fms_laneq_static, hfloat, 16, 8) []
++  = { 0x62C7 /* A0 + (-B0) * B6.  */,
++      0xD9F2 /* A1 + (-B1) * B6.  */,
++      0x5C6C /* A2 + (-B2) * B6.  */,
++      0x584A /* A3 + (-B3) * B6.  */,
++      0x7C00 /* A4 + (-B4) * B6.  */,
++      0xF447 /* A5 + (-B5) * B6.  */,
++      0xE330 /* A6 + (-B6) * B6.  */,
++      0x7C00 /* A7 + (-B7) * B6.  */ };
++
++VECT_VAR_DECL (expected7_fms_laneq_static, hfloat, 16, 8) []
++  = { 0xFC00 /* A0 + (-B0) * B7.  */,
++      0x7C00 /* A1 + (-B1) * B7.  */,
++      0xFC00 /* A2 + (-B2) * B7.  */,
++      0xFC00 /* A3 + (-B3) * B7.  */,
++      0x7C00 /* A4 + (-B4) * B7.  */,
++      0x7C00 /* A5 + (-B5) * B7.  */,
++      0x7C00 /* A6 + (-B6) * B7.  */,
++      0xFC00 /* A7 + (-B7) * B7.  */ };
++
++void exec_vfmas_lane_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VFMA_LANE (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A0, A1, A2, A3};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {B0, B1, B2, B3};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vfma_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMAQ_LANE (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A0, A1, A2, A3, A4, A5, A6, A7};
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {B0, B1, B2, B3, B4, B5, B6, B7};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vfmaq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMA_LANEQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_3, float, 16, 8);
++  VECT_VAR_DECL (buf_src_3, float, 16, 8) [] = {B0, B1, B2, B3, B4, B5, B6, B7};
++  VLOAD (vsrc_3, buf_src_3, q, float, f, 16, 8);
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 4);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected4_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 5);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected5_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 6);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected6_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 7);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected7_laneq_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMAQ_LANEQ (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 4);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected4_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 5);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected5_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 6);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected6_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 7);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected7_laneq_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMS_LANE (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_fms_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_fms_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_fms_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_fms_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMSQ_LANE (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_fms_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_fms_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_fms_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_fms_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMS_LANEQ (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 4);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected4_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 5);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected5_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 6);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected6_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4),
++		      VECT_VAR (vsrc_3, float, 16, 8), 7);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected7_fms_laneq_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMSQ_LANEQ (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 4);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected4_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 5);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected5_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 6);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected6_fms_laneq_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8),
++		       VECT_VAR (vsrc_3, float, 16, 8), 7);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected7_fms_laneq_static, "");
++}
++
++int
++main (void)
++{
++  exec_vfmas_lane_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c
+@@ -0,0 +1,469 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (123.4)
++#define A1 FP16_C (-5.8)
++#define A2 FP16_C (-0.0)
++#define A3 FP16_C (10)
++#define A4 FP16_C (123412.43)
++#define A5 FP16_C (-5.8)
++#define A6 FP16_C (90.8)
++#define A7 FP16_C (24)
++
++#define B0 FP16_C (23.4)
++#define B1 FP16_C (-5.8)
++#define B2 FP16_C (8.9)
++#define B3 FP16_C (4.0)
++#define B4 FP16_C (3.4)
++#define B5 FP16_C (-550.8)
++#define B6 FP16_C (-31.8)
++#define B7 FP16_C (20000.0)
++
++/* Expected results for vfma_n.  */
++VECT_VAR_DECL (expected_fma0_static, hfloat, 16, 4) []
++  = { 0x613E /* A0 + B0 * B0.  */,
++      0xD86D /* A1 + B1 * B0.  */,
++      0x5A82 /* A2 + B2 * B0.  */,
++      0x567A /* A3 + B3 * B0.  */ };
++
++VECT_VAR_DECL (expected_fma1_static, hfloat, 16, 4) []
++  = { 0xCA33 /* A0 + B0 * B1.  */,
++      0x4EF6 /* A1 + B1 * B1.  */,
++      0xD274 /* A2 + B2 * B1.  */,
++      0xCA9A /* A3 + B3 * B1.  */ };
++
++VECT_VAR_DECL (expected_fma2_static, hfloat, 16, 4) []
++  = { 0x5D2F /* A0 + B0 * B2.  */,
++      0xD32D /* A1 + B1 * B2.  */,
++      0x54F3 /* A2 + B2 * B2.  */,
++      0x51B3 /* A3 + B3 * B2.  */ };
++
++VECT_VAR_DECL (expected_fma3_static, hfloat, 16, 4) []
++  = { 0x5AC8 /* A0 + B0 * B3.  */,
++      0xCF40 /* A1 + B1 * B3.  */,
++      0x5073 /* A2 + B2 * B3.  */,
++      0x4E80 /* A3 + B3 * B3.  */ };
++
++VECT_VAR_DECL (expected_fma0_static, hfloat, 16, 8) []
++  = { 0x613E /* A0 + B0 * B0.  */,
++      0xD86D /* A1 + B1 * B0.  */,
++      0x5A82 /* A2 + B2 * B0.  */,
++      0x567A /* A3 + B3 * B0.  */,
++      0x7C00 /* A4 + B4 * B0.  */,
++      0xF24D /* A5 + B5 * B0.  */,
++      0xE11B /* A6 + B6 * B0.  */,
++      0x7C00 /* A7 + B7 * B0.  */ };
++
++VECT_VAR_DECL (expected_fma1_static, hfloat, 16, 8) []
++  = { 0xCA33 /* A0 + B0 * B1.  */,
++      0x4EF6 /* A1 + B1 * B1.  */,
++      0xD274 /* A2 + B2 * B1.  */,
++      0xCA9A /* A3 + B3 * B1.  */,
++      0x7C00 /* A4 + B4 * B1.  */,
++      0x6A3B /* A5 + B5 * B1.  */,
++      0x5C4D /* A6 + B6 * B1.  */,
++      0xFC00 /* A7 + B7 * B1.  */ };
++
++VECT_VAR_DECL (expected_fma2_static, hfloat, 16, 8) []
++  = { 0x5D2F /* A0 + B0 * B2.  */,
++      0xD32D /* A1 + B1 * B2.  */,
++      0x54F3 /* A2 + B2 * B2.  */,
++      0x51B3 /* A3 + B3 * B2.  */,
++      0x7C00 /* A4 + B4 * B2.  */,
++      0xECCB /* A5 + B5 * B2.  */,
++      0xDA01 /* A6 + B6 * B2.  */,
++      0x7C00 /* A7 + B7 * B2.  */ };
++
++VECT_VAR_DECL (expected_fma3_static, hfloat, 16, 8) []
++  = { 0x5AC8 /* A0 + B0 * B3.  */,
++      0xCF40 /* A1 + B1 * B3.  */,
++      0x5073 /* A2 + B2 * B3.  */,
++      0x4E80 /* A3 + B3 * B3.  */,
++      0x7C00 /* A4 + B4 * B3.  */,
++      0xE851 /* A5 + B5 * B3.  */,
++      0xD08C /* A6 + B6 * B3.  */,
++      0x7C00 /* A7 + B7 * B3.  */ };
++
++VECT_VAR_DECL (expected_fma4_static, hfloat, 16, 8) []
++  = { 0x5A58 /* A0 + B0 * B4.  */,
++      0xCE62 /* A1 + B1 * B4.  */,
++      0x4F91 /* A2 + B2 * B4.  */,
++      0x4DE6 /* A3 + B3 * B4.  */,
++      0x7C00 /* A4 + B4 * B4.  */,
++      0xE757 /* A5 + B5 * B4.  */,
++      0xCC54 /* A6 + B6 * B4.  */,
++      0x7C00 /* A7 + B7 * B4.  */ };
++
++VECT_VAR_DECL (expected_fma5_static, hfloat, 16, 8) []
++  = { 0xF23D /* A0 + B0 * B5.  */,
++      0x6A3B /* A1 + B1 * B5.  */,
++      0xECCA /* A2 + B2 * B5.  */,
++      0xE849 /* A3 + B3 * B5.  */,
++      0x7C00 /* A4 + B4 * B5.  */,
++      0x7C00 /* A5 + B5 * B5.  */,
++      0x744D /* A6 + B6 * B5.  */,
++      0xFC00 /* A7 + B7 * B5.  */ };
++
++VECT_VAR_DECL (expected_fma6_static, hfloat, 16, 8) []
++  = { 0xE0DA /* A0 + B0 * B6.  */,
++      0x5995 /* A1 + B1 * B6.  */,
++      0xDC6C /* A2 + B2 * B6.  */,
++      0xD753 /* A3 + B3 * B6.  */,
++      0x7C00 /* A4 + B4 * B6.  */,
++      0x7447 /* A5 + B5 * B6.  */,
++      0x644E /* A6 + B6 * B6.  */,
++      0xFC00 /* A7 + B7 * B6.  */ };
++
++VECT_VAR_DECL (expected_fma7_static, hfloat, 16, 8) []
++  = { 0x7C00 /* A0 + B0 * B7.  */,
++      0xFC00 /* A1 + B1 * B7.  */,
++      0x7C00 /* A2 + B2 * B7.  */,
++      0x7C00 /* A3 + B3 * B7.  */,
++      0x7C00 /* A4 + B4 * B7.  */,
++      0xFC00 /* A5 + B5 * B7.  */,
++      0xFC00 /* A6 + B6 * B7.  */,
++      0x7C00 /* A7 + B7 * B7.  */ };
++
++/* Expected results for vfms_n.  */
++VECT_VAR_DECL (expected_fms0_static, hfloat, 16, 4) []
++  = { 0xDEA2 /* A0 + (-B0) * B0.  */,
++      0x5810 /* A1 + (-B1) * B0.  */,
++      0xDA82 /* A2 + (-B2) * B0.  */,
++      0xD53A /* A3 + (-B3) * B0.  */ };
++
++VECT_VAR_DECL (expected_fms1_static, hfloat, 16, 4) []
++  = { 0x5C0D /* A0 + (-B0) * B1.  */,
++      0xD0EE /* A1 + (-B1) * B1.  */,
++      0x5274 /* A2 + (-B2) * B1.  */,
++      0x5026 /* A3 + (-B3) * B1.  */ };
++
++VECT_VAR_DECL (expected_fms2_static, hfloat, 16, 4) []
++  = { 0xD54E /* A0 + (-B0) * B2.  */,
++      0x51BA /* A1 + (-B1) * B2.  */,
++      0xD4F3 /* A2 + (-B2) * B2.  */,
++      0xCE66 /* A3 + (-B3) * B2.  */ };
++
++VECT_VAR_DECL (expected_fms3_static, hfloat, 16, 4) []
++  = { 0x4F70 /* A0 + (-B0) * B3.  */,
++      0x4C5A /* A1 + (-B1) * B3.  */,
++      0xD073 /* A2 + (-B2) * B3.  */,
++      0xC600 /* A3 + (-B3) * B3.  */ };
++
++VECT_VAR_DECL (expected_fms0_static, hfloat, 16, 8) []
++  = { 0xDEA2 /* A0 + (-B0) * B0.  */,
++      0x5810 /* A1 + (-B1) * B0.  */,
++      0xDA82 /* A2 + (-B2) * B0.  */,
++      0xD53A /* A3 + (-B3) * B0.  */,
++      0x7C00 /* A4 + (-B4) * B0.  */,
++      0x724B /* A5 + (-B5) * B0.  */,
++      0x6286 /* A6 + (-B6) * B0.  */,
++      0xFC00 /* A7 + (-B7) * B0.  */ };
++
++VECT_VAR_DECL (expected_fms1_static, hfloat, 16, 8) []
++  = { 0x5C0D /* A0 + (-B0) * B1.  */,
++      0xD0EE /* A1 + (-B1) * B1.  */,
++      0x5274 /* A2 + (-B2) * B1.  */,
++      0x5026 /* A3 + (-B3) * B1.  */,
++      0x7C00 /* A4 + (-B4) * B1.  */,
++      0xEA41 /* A5 + (-B5) * B1.  */,
++      0xD5DA /* A6 + (-B6) * B1.  */,
++      0x7C00 /* A7 + (-B7) * B1.  */ };
++
++VECT_VAR_DECL (expected_fms2_static, hfloat, 16, 8) []
++  = { 0xD54E /* A0 + (-B0) * B2.  */,
++      0x51BA /* A1 + (-B1) * B2.  */,
++      0xD4F3 /* A2 + (-B2) * B2.  */,
++      0xCE66 /* A3 + (-B3) * B2.  */,
++      0x7C00 /* A4 + (-B4) * B2.  */,
++      0x6CC8 /* A5 + (-B5) * B2.  */,
++      0x5DD7 /* A6 + (-B6) * B2.  */,
++      0xFC00 /* A7 + (-B7) * B2.  */ };
++
++VECT_VAR_DECL (expected_fms3_static, hfloat, 16, 8) []
++  = { 0x4F70 /* A0 + (-B0) * B3.  */,
++      0x4C5A /* A1 + (-B1) * B3.  */,
++      0xD073 /* A2 + (-B2) * B3.  */,
++      0xC600 /* A3 + (-B3) * B3.  */,
++      0x7C00 /* A4 + (-B4) * B3.  */,
++      0x684B /* A5 + (-B5) * B3.  */,
++      0x5AD0 /* A6 + (-B6) * B3.  */,
++      0xFC00 /* A7 + (-B7) * B3.  */ };
++
++VECT_VAR_DECL (expected_fms4_static, hfloat, 16, 8) []
++  = { 0x5179 /* A0 + (-B0) * B4.  */,
++      0x4AF6 /* A1 + (-B1) * B4.  */,
++      0xCF91 /* A2 + (-B2) * B4.  */,
++      0xC334 /* A3 + (-B3) * B4.  */,
++      0x7C00 /* A4 + (-B4) * B4.  */,
++      0x674C /* A5 + (-B5) * B4.  */,
++      0x5A37 /* A6 + (-B6) * B4.  */,
++      0xFC00 /* A7 + (-B7) * B4.  */ };
++
++VECT_VAR_DECL (expected_fms5_static, hfloat, 16, 8) []
++  = { 0x725C /* A0 + (-B0) * B5.  */,
++      0xEA41 /* A1 + (-B1) * B5.  */,
++      0x6CCA /* A2 + (-B2) * B5.  */,
++      0x6853 /* A3 + (-B3) * B5.  */,
++      0x7C00 /* A4 + (-B4) * B5.  */,
++      0xFC00 /* A5 + (-B5) * B5.  */,
++      0xF441 /* A6 + (-B6) * B5.  */,
++      0x7C00 /* A7 + (-B7) * B5.  */ };
++
++VECT_VAR_DECL (expected_fms6_static, hfloat, 16, 8) []
++  = { 0x62C7 /* A0 + (-B0) * B6.  */,
++      0xD9F2 /* A1 + (-B1) * B6.  */,
++      0x5C6C /* A2 + (-B2) * B6.  */,
++      0x584A /* A3 + (-B3) * B6.  */,
++      0x7C00 /* A4 + (-B4) * B6.  */,
++      0xF447 /* A5 + (-B5) * B6.  */,
++      0xE330 /* A6 + (-B6) * B6.  */,
++      0x7C00 /* A7 + (-B7) * B6.  */ };
++
++VECT_VAR_DECL (expected_fms7_static, hfloat, 16, 8) []
++  = { 0xFC00 /* A0 + (-B0) * B7.  */,
++      0x7C00 /* A1 + (-B1) * B7.  */,
++      0xFC00 /* A2 + (-B2) * B7.  */,
++      0xFC00 /* A3 + (-B3) * B7.  */,
++      0x7C00 /* A4 + (-B4) * B7.  */,
++      0x7C00 /* A5 + (-B5) * B7.  */,
++      0x7C00 /* A6 + (-B6) * B7.  */,
++      0xFC00 /* A7 + (-B7) * B7.  */ };
++
++void exec_vfmas_n_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VFMA_N (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A0, A1, A2, A3};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {B0, B1, B2, B3};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vfma_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B0);
++
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fma0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fma1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fma2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfma_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fma3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMAQ_N (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A0, A1, A2, A3, A4, A5, A6, A7};
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {B0, B1, B2, B3, B4, B5, B6, B7};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma3_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B4);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma4_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B5);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma5_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B6);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma6_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmaq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B7);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fma7_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMA_N (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B0);
++
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fms0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fms1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fms2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vfms_n_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		  VECT_VAR (vsrc_2, float, 16, 4), B3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_fms3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMAQ_N (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms3_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B4);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms4_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B5);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms5_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B6);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms6_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vfmsq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		   VECT_VAR (vsrc_2, float, 16, 8), B7);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_fms7_static, "");
++}
++
++int
++main (void)
++{
++  exec_vfmas_n_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c
+@@ -0,0 +1,143 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (123.4)
++#define B0 FP16_C (-5.8)
++#define C0 FP16_C (-3.8)
++#define D0 FP16_C (10)
++
++#define A1 FP16_C (12.4)
++#define B1 FP16_C (-5.8)
++#define C1 FP16_C (90.8)
++#define D1 FP16_C (24)
++
++#define A2 FP16_C (23.4)
++#define B2 FP16_C (-5.8)
++#define C2 FP16_C (8.9)
++#define D2 FP16_C (4)
++
++#define E0 FP16_C (3.4)
++#define F0 FP16_C (-55.8)
++#define G0 FP16_C (-31.8)
++#define H0 FP16_C (2)
++
++#define E1 FP16_C (123.4)
++#define F1 FP16_C (-5.8)
++#define G1 FP16_C (-3.8)
++#define H1 FP16_C (102)
++
++#define E2 FP16_C (4.9)
++#define F2 FP16_C (-15.8)
++#define G2 FP16_C (39.8)
++#define H2 FP16_C (49)
++
++extern void abort ();
++
++float16_t src1[8] = { A0, B0, C0, D0, E0, F0, G0, H0 };
++float16_t src2[8] = { A1, B1, C1, D1, E1, F1, G1, H1 };
++VECT_VAR_DECL (src3, float, 16, 4) [] = { A2, B2, C2, D2 };
++VECT_VAR_DECL (src3, float, 16, 8) [] = { A2, B2, C2, D2, E2, F2, G2, H2 };
++
++/* Expected results for vfmah_lane_f16.  */
++uint16_t expected[4] = { 0x5E76 /* A0 + A1 * A2.  */,
++			 0x4EF6 /* B0 + B1 * B2.  */,
++			 0x6249 /* C0 + C1 * C2.  */,
++			 0x56A0 /* D0 + D1 * D2.  */ };
++
++/* Expected results for vfmah_laneq_f16.  */
++uint16_t expected_laneq[8] = { 0x5E76 /* A0 + A1 * A2.  */,
++			       0x4EF6 /* B0 + B1 * B2.  */,
++			       0x6249 /* C0 + C1 * C2.  */,
++			       0x56A0 /* D0 + D1 * D2.  */,
++			       0x60BF /* E0 + E1 * E2.  */,
++			       0x507A /* F0 + F1 * F2.  */,
++			       0xD9B9 /* G0 + G1 * G2.  */,
++			       0x6CE2 /* H0 + H1 * H2.  */ };
++
++/* Expected results for vfmsh_lane_f16.  */
++uint16_t expected_fms[4] = { 0xD937 /* A0 + -A1 * A2.  */,
++			     0xD0EE /* B0 + -B1 * B2.  */,
++			     0xE258 /* C0 + -C1 * C2.  */,
++			     0xD560 /* D0 + -D1 * D2.  */ };
++
++/* Expected results for vfmsh_laneq_f16.  */
++uint16_t expected_fms_laneq[8] = { 0xD937 /* A0 + -A1 * A2.  */,
++				   0xD0EE /* B0 + -B1 * B2.  */,
++				   0xE258 /* C0 + -C1 * C2.  */,
++				   0xD560 /* D0 + -D1 * D2.  */,
++				   0xE0B2 /* E0 + -E1 * E2.  */,
++				   0xD89C /* F0 + -F1 * F2.  */,
++				   0x5778 /* G0 + -G1 * G2.  */,
++				   0xECE1 /* H0 + -H1 * H2.  */ };
++
++void exec_vfmash_lane_f16 (void)
++{
++#define CHECK_LANE(N) \
++  ret = vfmah_lane_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 4), N);\
++  if (*(uint16_t *) &ret != expected[N])\
++    abort ();
++
++  DECL_VARIABLE(vsrc3, float, 16, 4);
++  VLOAD (vsrc3, src3, , float, f, 16, 4);
++  float16_t ret;
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++
++#undef CHECK_LANE
++#define CHECK_LANE(N) \
++  ret = vfmah_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\
++  if (*(uint16_t *) &ret != expected_laneq[N]) \
++	  abort ();
++
++  DECL_VARIABLE(vsrc3, float, 16, 8);
++  VLOAD (vsrc3, src3, q, float, f, 16, 8);
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++  CHECK_LANE(4)
++  CHECK_LANE(5)
++  CHECK_LANE(6)
++  CHECK_LANE(7)
++
++#undef CHECK_LANE
++#define CHECK_LANE(N) \
++  ret = vfmsh_lane_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 4), N);\
++  if (*(uint16_t *) &ret != expected_fms[N])\
++    abort ();
++
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++
++#undef CHECK_LANE
++#define CHECK_LANE(N) \
++  ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\
++  if (*(uint16_t *) &ret != expected_fms_laneq[N]) \
++	  abort ();
++
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++  CHECK_LANE(4)
++  CHECK_LANE(5)
++  CHECK_LANE(6)
++  CHECK_LANE(7)
++}
++
++int
++main (void)
++{
++  exec_vfmash_lane_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfms.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfms.c
+@@ -4,10 +4,17 @@
+ 
+ #ifdef __ARM_FEATURE_FMA
+ /* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xe206, 0xe204, 0xe202, 0xe200 };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xe455, 0xe454, 0xe453, 0xe452,
++					      0xe451, 0xe450, 0xe44f, 0xe44e };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc440ca3d, 0xc4408a3d };
+-VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc48a9eb8, 0xc48a7eb8, 0xc48a5eb8, 0xc48a3eb8 };
++VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc48a9eb8, 0xc48a7eb8,
++					   0xc48a5eb8, 0xc48a3eb8 };
+ #ifdef __aarch64__
+-VECT_VAR_DECL(expected,hfloat,64,2) [] = { 0xc08a06e1532b8520, 0xc089fee1532b8520 };
++VECT_VAR_DECL(expected,hfloat,64,2) [] = { 0xc08a06e1532b8520,
++					   0xc089fee1532b8520 };
+ #endif
+ 
+ #define TEST_MSG "VFMS/VFMSQ"
+@@ -44,6 +51,18 @@ void exec_vfms (void)
+   DECL_VARIABLE(VAR, float, 32, 4);
+ #endif
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector1, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector3, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 4);
++
++  DECL_VARIABLE(vector1, float, 16, 8);
++  DECL_VARIABLE(vector2, float, 16, 8);
++  DECL_VARIABLE(vector3, float, 16, 8);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++
+   DECL_VFMS_VAR(vector1);
+   DECL_VFMS_VAR(vector2);
+   DECL_VFMS_VAR(vector3);
+@@ -52,6 +71,10 @@ void exec_vfms (void)
+   clean_results ();
+ 
+   /* Initialize input "vector1" from "buffer".  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector1, buffer, , float, f, 16, 4);
++  VLOAD(vector1, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector1, buffer, , float, f, 32, 2);
+   VLOAD(vector1, buffer, q, float, f, 32, 4);
+ #ifdef __aarch64__
+@@ -59,13 +82,21 @@ void exec_vfms (void)
+ #endif
+ 
+   /* Choose init value arbitrarily.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 9.3f);
++  VDUP(vector2, q, float, f, 16, 8, 29.7f);
++#endif
+   VDUP(vector2, , float, f, 32, 2, 9.3f);
+   VDUP(vector2, q, float, f, 32, 4, 29.7f);
+ #ifdef __aarch64__
+   VDUP(vector2, q, float, f, 64, 2, 15.8f);
+ #endif
+-  
++
+   /* Choose init value arbitrarily.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector3, , float, f, 16, 4, 81.2f);
++  VDUP(vector3, q, float, f, 16, 8, 36.8f);
++#endif
+   VDUP(vector3, , float, f, 32, 2, 81.2f);
+   VDUP(vector3, q, float, f, 32, 4, 36.8f);
+ #ifdef __aarch64__
+@@ -73,12 +104,20 @@ void exec_vfms (void)
+ #endif
+ 
+   /* Execute the tests.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VFMS(, float, f, 16, 4);
++  TEST_VFMS(q, float, f, 16, 8);
++#endif
+   TEST_VFMS(, float, f, 32, 2);
+   TEST_VFMS(q, float, f, 32, 4);
+ #ifdef __aarch64__
+   TEST_VFMS(q, float, f, 64, 2);
+ #endif
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
+   CHECK_VFMS_RESULTS (TEST_MSG, "");
+ }
+ #endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfms_vfma_n.c
+@@ -0,0 +1,490 @@
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#if defined(__aarch64__) && defined(__ARM_FEATURE_FMA)
++
++#define A0 123.4f
++#define A1 -3.8f
++#define A2 -29.4f
++#define A3 (__builtin_inff ())
++#define A4 0.0f
++#define A5 24.0f
++#define A6 124.0f
++#define A7 1024.0f
++
++#define B0 -5.8f
++#define B1 -0.0f
++#define B2 -10.8f
++#define B3 10.0f
++#define B4 23.4f
++#define B5 -1234.8f
++#define B6 8.9f
++#define B7 4.0f
++
++#define E0 9.8f
++#define E1 -1024.0f
++#define E2 (-__builtin_inff ())
++#define E3 479.0f
++float32_t elem0 = E0;
++float32_t elem1 = E1;
++float32_t elem2 = E2;
++float32_t elem3 = E3;
++
++#define DA0 1231234.4
++#define DA1 -3.8
++#define DA2 -2980.4
++#define DA3 -5.8
++#define DA4 0.01123
++#define DA5 24.0
++#define DA6 124.12345
++#define DA7 1024.0
++
++#define DB0 -5.8
++#define DB1 (__builtin_inf ())
++#define DB2 -105.8
++#define DB3 10.0
++#define DB4 (-__builtin_inf ())
++#define DB5 -1234.8
++#define DB6 848.9
++#define DB7 44444.0
++
++#define DE0 9.8
++#define DE1 -1024.0
++#define DE2 105.8
++#define DE3 479.0
++float64_t delem0 = DE0;
++float64_t delem1 = DE1;
++float64_t delem2 = DE2;
++float64_t delem3 = DE3;
++
++/* Expected results for vfms_n.  */
++
++VECT_VAR_DECL(expectedfms0, float, 32, 2) [] = {A0 + -B0 * E0, A1 + -B1 * E0};
++VECT_VAR_DECL(expectedfms1, float, 32, 2) [] = {A2 + -B2 * E1, A3 + -B3 * E1};
++VECT_VAR_DECL(expectedfms2, float, 32, 2) [] = {A4 + -B4 * E2, A5 + -B5 * E2};
++VECT_VAR_DECL(expectedfms3, float, 32, 2) [] = {A6 + -B6 * E3, A7 + -B7 * E3};
++VECT_VAR_DECL(expectedfma0, float, 32, 2) [] = {A0 + B0 * E0, A1 + B1 * E0};
++VECT_VAR_DECL(expectedfma1, float, 32, 2) [] = {A2 + B2 * E1, A3 + B3 * E1};
++VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2};
++VECT_VAR_DECL(expectedfma3, float, 32, 2) [] = {A6 + B6 * E3, A7 + B7 * E3};
++
++hfloat32_t * VECT_VAR (expectedfms0_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfms0, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfms1_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfms1, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfms2_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfms2, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfms3_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfms3, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfma0_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfma0, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfma1_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfma1, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfma2_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
++hfloat32_t * VECT_VAR (expectedfma3_static, hfloat, 32, 2) =
++  (hfloat32_t *) VECT_VAR (expectedfma3, float, 32, 2);
++
++
++VECT_VAR_DECL(expectedfms0, float, 32, 4) [] = {A0 + -B0 * E0, A1 + -B1 * E0,
++						A2 + -B2 * E0, A3 + -B3 * E0};
++VECT_VAR_DECL(expectedfms1, float, 32, 4) [] = {A4 + -B4 * E1, A5 + -B5 * E1,
++						A6 + -B6 * E1, A7 + -B7 * E1};
++VECT_VAR_DECL(expectedfms2, float, 32, 4) [] = {A0 + -B0 * E2, A2 + -B2 * E2,
++						A4 + -B4 * E2, A6 + -B6 * E2};
++VECT_VAR_DECL(expectedfms3, float, 32, 4) [] = {A1 + -B1 * E3, A3 + -B3 * E3,
++						A5 + -B5 * E3, A7 + -B7 * E3};
++VECT_VAR_DECL(expectedfma0, float, 32, 4) [] = {A0 + B0 * E0, A1 + B1 * E0,
++						A2 + B2 * E0, A3 + B3 * E0};
++VECT_VAR_DECL(expectedfma1, float, 32, 4) [] = {A4 + B4 * E1, A5 + B5 * E1,
++						A6 + B6 * E1, A7 + B7 * E1};
++VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2,
++						A4 + B4 * E2, A6 + B6 * E2};
++VECT_VAR_DECL(expectedfma3, float, 32, 4) [] = {A1 + B1 * E3, A3 + B3 * E3,
++						A5 + B5 * E3, A7 + B7 * E3};
++
++hfloat32_t * VECT_VAR (expectedfms0_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfms0, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfms1_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfms1, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfms2_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfms2, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfms3_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfms3, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfma0_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfma0, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfma1_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfma1, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfma2_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
++hfloat32_t * VECT_VAR (expectedfma3_static, hfloat, 32, 4) =
++  (hfloat32_t *) VECT_VAR (expectedfma3, float, 32, 4);
++
++VECT_VAR_DECL(expectedfms0, float, 64, 2) [] = {DA0 + -DB0 * DE0,
++						DA1 + -DB1 * DE0};
++VECT_VAR_DECL(expectedfms1, float, 64, 2) [] = {DA2 + -DB2 * DE1,
++						DA3 + -DB3 * DE1};
++VECT_VAR_DECL(expectedfms2, float, 64, 2) [] = {DA4 + -DB4 * DE2,
++						DA5 + -DB5 * DE2};
++VECT_VAR_DECL(expectedfms3, float, 64, 2) [] = {DA6 + -DB6 * DE3,
++						DA7 + -DB7 * DE3};
++VECT_VAR_DECL(expectedfma0, float, 64, 2) [] = {DA0 + DB0 * DE0,
++						DA1 + DB1 * DE0};
++VECT_VAR_DECL(expectedfma1, float, 64, 2) [] = {DA2 + DB2 * DE1,
++						DA3 + DB3 * DE1};
++VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2,
++						DA5 + DB5 * DE2};
++VECT_VAR_DECL(expectedfma3, float, 64, 2) [] = {DA6 + DB6 * DE3,
++						DA7 + DB7 * DE3};
++hfloat64_t * VECT_VAR (expectedfms0_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfms0, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfms1_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfms1, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfms2_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfms2, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfms3_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfms3, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfma0_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfma0, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfma1_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfma1, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfma2_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
++hfloat64_t * VECT_VAR (expectedfma3_static, hfloat, 64, 2) =
++  (hfloat64_t *) VECT_VAR (expectedfma3, float, 64, 2);
++
++VECT_VAR_DECL(expectedfms0, float, 64, 1) [] = {DA0 + -DB0 * DE0};
++VECT_VAR_DECL(expectedfms1, float, 64, 1) [] = {DA2 + -DB2 * DE1};
++VECT_VAR_DECL(expectedfms2, float, 64, 1) [] = {DA4 + -DB4 * DE2};
++VECT_VAR_DECL(expectedfms3, float, 64, 1) [] = {DA6 + -DB6 * DE3};
++VECT_VAR_DECL(expectedfma0, float, 64, 1) [] = {DA0 + DB0 * DE0};
++VECT_VAR_DECL(expectedfma1, float, 64, 1) [] = {DA2 + DB2 * DE1};
++VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2};
++VECT_VAR_DECL(expectedfma3, float, 64, 1) [] = {DA6 + DB6 * DE3};
++
++hfloat64_t * VECT_VAR (expectedfms0_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfms0, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfms1_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfms1, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfms2_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfms2, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfms3_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfms3, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfma0_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfma0, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfma1_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfma1, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfma2_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
++hfloat64_t * VECT_VAR (expectedfma3_static, hfloat, 64, 1) =
++  (hfloat64_t *) VECT_VAR (expectedfma3, float, 64, 1);
++
++void exec_vfma_vfms_n (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VFMS_VFMA_N (FP32)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 32, 2);
++  DECL_VARIABLE(vsrc_2, float, 32, 2);
++  VECT_VAR_DECL (buf_src_1, float, 32, 2) [] = {A0, A1};
++  VECT_VAR_DECL (buf_src_2, float, 32, 2) [] = {B0, B1};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 32, 2);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 32, 2);
++  DECL_VARIABLE (vector_res, float, 32, 2) =
++    vfms_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem0);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfms0_static, "");
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfma_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem0);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfma0_static, "");
++
++  VECT_VAR_DECL (buf_src_3, float, 32, 2) [] = {A2, A3};
++  VECT_VAR_DECL (buf_src_4, float, 32, 2) [] = {B2, B3};
++  VLOAD (vsrc_1, buf_src_3, , float, f, 32, 2);
++  VLOAD (vsrc_2, buf_src_4, , float, f, 32, 2);
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfms_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem1);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfms1_static, "");
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfma_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem1);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfma1_static, "");
++
++  VECT_VAR_DECL (buf_src_5, float, 32, 2) [] = {A4, A5};
++  VECT_VAR_DECL (buf_src_6, float, 32, 2) [] = {B4, B5};
++  VLOAD (vsrc_1, buf_src_5, , float, f, 32, 2);
++  VLOAD (vsrc_2, buf_src_6, , float, f, 32, 2);
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfms_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem2);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfms2_static, "");
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfma_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem2);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfma2_static, "");
++
++  VECT_VAR_DECL (buf_src_7, float, 32, 2) [] = {A6, A7};
++  VECT_VAR_DECL (buf_src_8, float, 32, 2) [] = {B6, B7};
++  VLOAD (vsrc_1, buf_src_7, , float, f, 32, 2);
++  VLOAD (vsrc_2, buf_src_8, , float, f, 32, 2);
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfms_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem3);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfms3_static, "");
++  VECT_VAR (vector_res, float, 32, 2) =
++    vfma_n_f32 (VECT_VAR (vsrc_1, float, 32, 2),
++		VECT_VAR (vsrc_2, float, 32, 2), elem3);
++  vst1_f32 (VECT_VAR (result, float, 32, 2),
++	    VECT_VAR (vector_res, float, 32, 2));
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfma3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMSQ_VFMAQ_N (FP32)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 32, 4);
++  DECL_VARIABLE(vsrc_2, float, 32, 4);
++  VECT_VAR_DECL (buf_src_1, float, 32, 4) [] = {A0, A1, A2, A3};
++  VECT_VAR_DECL (buf_src_2, float, 32, 4) [] = {B0, B1, B2, B3};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 32, 4);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 32, 4);
++  DECL_VARIABLE (vector_res, float, 32, 4) =
++    vfmsq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem0);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfms0_static, "");
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmaq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem0);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfma0_static, "");
++
++  VECT_VAR_DECL (buf_src_3, float, 32, 4) [] = {A4, A5, A6, A7};
++  VECT_VAR_DECL (buf_src_4, float, 32, 4) [] = {B4, B5, B6, B7};
++  VLOAD (vsrc_1, buf_src_3, q, float, f, 32, 4);
++  VLOAD (vsrc_2, buf_src_4, q, float, f, 32, 4);
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmsq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem1);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfms1_static, "");
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmaq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem1);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfma1_static, "");
++
++  VECT_VAR_DECL (buf_src_5, float, 32, 4) [] = {A0, A2, A4, A6};
++  VECT_VAR_DECL (buf_src_6, float, 32, 4) [] = {B0, B2, B4, B6};
++  VLOAD (vsrc_1, buf_src_5, q, float, f, 32, 4);
++  VLOAD (vsrc_2, buf_src_6, q, float, f, 32, 4);
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmsq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem2);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfms2_static, "");
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmaq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem2);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfma2_static, "");
++
++  VECT_VAR_DECL (buf_src_7, float, 32, 4) [] = {A1, A3, A5, A7};
++  VECT_VAR_DECL (buf_src_8, float, 32, 4) [] = {B1, B3, B5, B7};
++  VLOAD (vsrc_1, buf_src_7, q, float, f, 32, 4);
++  VLOAD (vsrc_2, buf_src_8, q, float, f, 32, 4);
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmsq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem3);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfms3_static, "");
++  VECT_VAR (vector_res, float, 32, 4) =
++    vfmaq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4),
++		 VECT_VAR (vsrc_2, float, 32, 4), elem3);
++  vst1q_f32 (VECT_VAR (result, float, 32, 4),
++	     VECT_VAR (vector_res, float, 32, 4));
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfma3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMSQ_VFMAQ_N (FP64)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 64, 2);
++  DECL_VARIABLE(vsrc_2, float, 64, 2);
++  VECT_VAR_DECL (buf_src_1, float, 64, 2) [] = {DA0, DA1};
++  VECT_VAR_DECL (buf_src_2, float, 64, 2) [] = {DB0, DB1};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 64, 2);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 64, 2);
++  DECL_VARIABLE (vector_res, float, 64, 2) =
++    vfmsq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem0);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfms0_static, "");
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmaq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem0);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfma0_static, "");
++
++  VECT_VAR_DECL (buf_src_3, float, 64, 2) [] = {DA2, DA3};
++  VECT_VAR_DECL (buf_src_4, float, 64, 2) [] = {DB2, DB3};
++  VLOAD (vsrc_1, buf_src_3, q, float, f, 64, 2);
++  VLOAD (vsrc_2, buf_src_4, q, float, f, 64, 2);
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmsq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem1);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfms1_static, "");
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmaq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem1);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfma1_static, "");
++
++  VECT_VAR_DECL (buf_src_5, float, 64, 2) [] = {DA4, DA5};
++  VECT_VAR_DECL (buf_src_6, float, 64, 2) [] = {DB4, DB5};
++  VLOAD (vsrc_1, buf_src_5, q, float, f, 64, 2);
++  VLOAD (vsrc_2, buf_src_6, q, float, f, 64, 2);
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmsq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem2);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfms2_static, "");
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmaq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem2);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfma2_static, "");
++
++  VECT_VAR_DECL (buf_src_7, float, 64, 2) [] = {DA6, DA7};
++  VECT_VAR_DECL (buf_src_8, float, 64, 2) [] = {DB6, DB7};
++  VLOAD (vsrc_1, buf_src_7, q, float, f, 64, 2);
++  VLOAD (vsrc_2, buf_src_8, q, float, f, 64, 2);
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmsq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem3);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfms3_static, "");
++  VECT_VAR (vector_res, float, 64, 2) =
++    vfmaq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2),
++		 VECT_VAR (vsrc_2, float, 64, 2), delem3);
++  vst1q_f64 (VECT_VAR (result, float, 64, 2),
++	     VECT_VAR (vector_res, float, 64, 2));
++  CHECK_FP (TEST_MSG, float, 64, 2, PRIx64, expectedfma3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VFMS_VFMA_N (FP64)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 64, 1);
++  DECL_VARIABLE(vsrc_2, float, 64, 1);
++  VECT_VAR_DECL (buf_src_1, float, 64, 1) [] = {DA0};
++  VECT_VAR_DECL (buf_src_2, float, 64, 1) [] = {DB0};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 64, 1);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 64, 1);
++  DECL_VARIABLE (vector_res, float, 64, 1) =
++    vfms_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem0);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfms0_static, "");
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfma_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem0);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfma0_static, "");
++
++  VECT_VAR_DECL (buf_src_3, float, 64, 1) [] = {DA2};
++  VECT_VAR_DECL (buf_src_4, float, 64, 1) [] = {DB2};
++  VLOAD (vsrc_1, buf_src_3, , float, f, 64, 1);
++  VLOAD (vsrc_2, buf_src_4, , float, f, 64, 1);
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfms_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem1);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfms1_static, "");
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfma_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem1);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfma1_static, "");
++
++  VECT_VAR_DECL (buf_src_5, float, 64, 1) [] = {DA4};
++  VECT_VAR_DECL (buf_src_6, float, 64, 1) [] = {DB4};
++  VLOAD (vsrc_1, buf_src_5, , float, f, 64, 1);
++  VLOAD (vsrc_2, buf_src_6, , float, f, 64, 1);
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfms_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem2);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfms2_static, "");
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfma_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem2);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfma2_static, "");
++
++  VECT_VAR_DECL (buf_src_7, float, 64, 1) [] = {DA6};
++  VECT_VAR_DECL (buf_src_8, float, 64, 1) [] = {DB6};
++  VLOAD (vsrc_1, buf_src_7, , float, f, 64, 1);
++  VLOAD (vsrc_2, buf_src_8, , float, f, 64, 1);
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfms_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem3);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfms3_static, "");
++  VECT_VAR (vector_res, float, 64, 1) =
++    vfma_n_f64 (VECT_VAR (vsrc_1, float, 64, 1),
++		VECT_VAR (vsrc_2, float, 64, 1), delem3);
++  vst1_f64 (VECT_VAR (result, float, 64, 1),
++	     VECT_VAR (vector_res, float, 64, 1));
++  CHECK_FP (TEST_MSG, float, 64, 1, PRIx64, expectedfma3_static, "");
++}
++#endif
++
++int
++main (void)
++{
++#if defined(__aarch64__) && defined(__ARM_FEATURE_FMA)
++  exec_vfma_vfms_n ();
++#endif
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x42af /* 3.341797 */,
++  0x5043 /* 34.093750 */,
++  0xccd2 /* -19.281250 */,
++  0x3712 /* 0.441895 */,
++  0x3acc /* 0.849609 */,
++  0x4848 /* 8.562500 */,
++  0xcc43 /* -17.046875 */,
++  0xd65c /* -101.750000 */,
++  0x4185 /* 2.759766 */,
++  0xcd39 /* -20.890625 */,
++  0xd45b /* -69.687500 */,
++  0x5241 /* 50.031250 */,
++  0xc675 /* -6.457031 */,
++  0x4d07 /* 20.109375 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VFMSH_F16"
++#define INSN_NAME vfmsh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "ternary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_high.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_high.c
+@@ -63,8 +63,8 @@ void exec_vget_high (void)
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+ }
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c
+@@ -13,6 +13,7 @@ uint32_t   expected_u32  = 0xfffffff1;
+ uint64_t   expected_u64  = 0xfffffffffffffff0;
+ poly8_t    expected_p8   = 0xf6;
+ poly16_t   expected_p16  = 0xfff2;
++hfloat16_t expected_f16  = 0xcb80;
+ hfloat32_t expected_f32  = 0xc1700000;
+ 
+ int8_t     expectedq_s8  = 0xff;
+@@ -25,6 +26,7 @@ uint32_t   expectedq_u32 = 0xfffffff2;
+ uint64_t   expectedq_u64 = 0xfffffffffffffff1;
+ poly8_t    expectedq_p8  = 0xfe;
+ poly16_t   expectedq_p16 = 0xfff6;
++hfloat16_t expectedq_f16 = 0xca80;
+ hfloat32_t expectedq_f32 = 0xc1500000;
+ 
+ int error_found = 0;
+@@ -52,6 +54,12 @@ void exec_vget_lane (void)
+     uint32_t var_int32;
+     float32_t var_float32;
+   } var_int32_float32;
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  union {
++    uint16_t var_int16;
++    float16_t var_float16;
++  } var_int16_float16;
++#endif
+ 
+ #define TEST_VGET_LANE_FP(Q, T1, T2, W, N, L)				   \
+   VAR(var, T1, W) = vget##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), L); \
+@@ -81,10 +89,17 @@ void exec_vget_lane (void)
+   VAR_DECL(var, uint, 64);
+   VAR_DECL(var, poly, 8);
+   VAR_DECL(var, poly, 16);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  VAR_DECL(var, float, 16);
++#endif
+   VAR_DECL(var, float, 32);
+ 
+   /* Initialize input values.  */
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+@@ -99,6 +114,9 @@ void exec_vget_lane (void)
+   TEST_VGET_LANE(, uint, u, 64, 1, 0);
+   TEST_VGET_LANE(, poly, p, 8, 8, 6);
+   TEST_VGET_LANE(, poly, p, 16, 4, 2);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VGET_LANE_FP(, float, f, 16, 4, 1);
++#endif
+   TEST_VGET_LANE_FP(, float, f, 32, 2, 1);
+ 
+   TEST_VGET_LANE(q, int, s, 8, 16, 15);
+@@ -111,6 +129,9 @@ void exec_vget_lane (void)
+   TEST_VGET_LANE(q, uint, u, 64, 2, 1);
+   TEST_VGET_LANE(q, poly, p, 8, 16, 14);
+   TEST_VGET_LANE(q, poly, p, 16, 8, 6);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VGET_LANE_FP(q, float, f, 16, 8, 3);
++#endif
+   TEST_VGET_LANE_FP(q, float, f, 32, 4, 3);
+ }
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_low.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_low.c
+@@ -63,8 +63,8 @@ void exec_vget_low (void)
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+   CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
+ #endif
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ float16x4x2_t
+ f_vld2_lane_f16 (float16_t * p, float16x4x2_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ float16x8x2_t
+ f_vld2q_lane_f16 (float16_t * p, float16x8x2_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ float16x4x3_t
+ f_vld3_lane_f16 (float16_t * p, float16x4x3_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ float16x8x3_t
+ f_vld3q_lane_f16 (float16_t * p, float16x8x3_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ float16x4x4_t
+ f_vld4_lane_f16 (float16_t * p, float16x4x4_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ float16x8x4_t
+ f_vld4q_lane_f16 (float16_t * p, float16x8x4_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c
+@@ -528,8 +528,8 @@ void exec_vldX (void)
+     CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment);		\
+     CHECK(test_name, uint, 64, 1, PRIx64, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);	\
++    CHECK_POLY(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment);	\
+ 									\
+     CHECK(test_name, int, 8, 16, PRIx8, EXPECTED, comment);		\
+@@ -538,8 +538,8 @@ void exec_vldX (void)
+     CHECK(test_name, uint, 8, 16, PRIx8, EXPECTED, comment);		\
+     CHECK(test_name, uint, 16, 8, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 4, PRIx32, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 16, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 16, PRIx8, EXPECTED, comment);	\
++    CHECK_POLY(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment)
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
+@@ -270,8 +270,8 @@ void exec_vldX_dup (void)
+     CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment);		\
+     CHECK(test_name, uint, 64, 1, PRIx64, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);	\
++    CHECK_POLY(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment)
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c
+@@ -451,14 +451,14 @@ void exec_vldX_lane (void)
+     CHECK(test_name, uint, 8, 8, PRIx8, EXPECTED, comment);		\
+     CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);	\
++    CHECK_POLY(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment);	\
+     CHECK(test_name, int, 16, 8, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, int, 32, 4, PRIx32, EXPECTED, comment);		\
+     CHECK(test_name, uint, 16, 8, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 4, PRIx32, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);	\
+     CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment)
+ 
+ #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
+@@ -7,6 +7,10 @@
+ 
+ #define HAS_FLOAT_VARIANT
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++#define HAS_FLOAT16_VARIANT
++#endif
++
+ /* Expected results.  */
+ VECT_VAR_DECL(expected,int,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
+ 				       0xf4, 0xf5, 0xf6, 0xf7 };
+@@ -16,6 +20,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
+ 					0xf4, 0xf5, 0xf6, 0xf7 };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff3 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcbc0, 0xcb80, 0xcb00, 0xca80 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1780000, 0xc1700000 };
+ VECT_VAR_DECL(expected,int,8,16) [] = { 0xf4, 0xf4, 0xf4, 0xf4,
+ 					0xf4, 0xf5, 0xf6, 0xf7,
+@@ -33,10 +40,36 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff3,
+ 					 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff1, 0xfffffff1,
+ 					 0xfffffff2, 0xfffffff3 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcb40, 0xcb40, 0xcb00, 0xca80,
++					      0xca00, 0xc980, 0xc900, 0xc880 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1680000, 0xc1680000,
+ 					   0xc1600000, 0xc1500000 };
+ 
+ /* Expected results with special FP values.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_mnan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						   0x7e00, 0x7e00,
++						   0x7e00, 0x7e00,
++						   0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_inf, hfloat, 16, 8) [] = { 0x7c00, 0x7c00,
++						  0x7c00, 0x7c00,
++						  0x7c00, 0x7c00,
++						  0x7c00, 0x7c00 };
++VECT_VAR_DECL(expected_minf, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_zero1, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						    0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_zero2, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						    0x0, 0x0, 0x0, 0x0 };
++#endif
+ VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 					       0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c
+@@ -0,0 +1,34 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++#define A 123.4
++#define B -567.8
++#define C -34.8
++#define D 1024
++#define E 663.1
++#define F 169.1
++#define G -4.8
++#define H 77
++
++float16_t input_1[] = { A, B, C, D };
++float16_t input_2[] = { E, F, G, H };
++float16_t expected[] = { E, F, G, D };
++
++#define TEST_MSG "VMAXH_F16"
++#define INSN_NAME vmaxh_f16
++
++#define INPUT_1 input_1
++#define INPUT_2 input_2
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnm_1.c
+@@ -0,0 +1,47 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define INSN_NAME vmaxnm
++#define TEST_MSG "VMAXNM/VMAXNMQ"
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++#define HAS_FLOAT16_VARIANT
++#endif
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcbc0, 0xcb80, 0xcb00, 0xca80 };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcb40, 0xcb40, 0xcb00, 0xca80,
++					      0xca00, 0xc980, 0xc900, 0xc880 };
++#endif
++
++/* Expected results with special FP values.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_mnan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_inf, hfloat, 16, 8) [] = { 0x7c00, 0x7c00,
++						  0x7c00, 0x7c00,
++						  0x7c00, 0x7c00,
++						  0x7c00, 0x7c00 };
++VECT_VAR_DECL(expected_minf, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_zero1, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						    0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_zero2, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						    0x0, 0x0, 0x0, 0x0 };
++#endif
++
++#include "binary_op_float.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++#define INFF __builtin_inf ()
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4000 /* 2.000000 */,
++  0x5640 /* 100.000000 */,
++  0x4f80 /* 30.000000 */,
++  0x3666 /* 0.399902 */,
++  0x3800 /* 0.500000 */,
++  0x3d52 /* 1.330078 */,
++  0xc64d /* -6.300781 */,
++  0x4d00 /* 20.000000 */,
++  0x355d /* 0.335205 */,
++  0x409a /* 2.300781 */,
++  0x3c00 /* 1.000000 */,
++  0x4a91 /* 13.132812 */,
++  0x34f6 /* 0.310059 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0x7c00 /* inf */
++};
++
++#define TEST_MSG "VMAXNMH_F16"
++#define INSN_NAME vmaxnmh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c
+@@ -0,0 +1,131 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (34.8)
++#define B0 FP16_C (__builtin_nanf (""))
++#define C0 FP16_C (-__builtin_nanf (""))
++#define D0 FP16_C (0.0)
++
++#define A1 FP16_C (1025.8)
++#define B1 FP16_C (13.4)
++#define C1 FP16_C (__builtin_nanf (""))
++#define D1 FP16_C (10)
++#define E1 FP16_C (-0.0)
++#define F1 FP16_C (-__builtin_nanf (""))
++#define G1 FP16_C (0.0)
++#define H1 FP16_C (10)
++
++/* Expected results for vmaxnmv.  */
++uint16_t expect = 0x505A /* A0.  */;
++uint16_t expect_alt = 0x6402 /* A1.  */;
++
++void exec_vmaxnmv_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMAXNMV (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A0, B0, C0, D0};
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  float16_t vector_res = vmaxnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 4) [] = {B0, A0, C0, D0};
++  VLOAD (vsrc, buf_src1, , float, f, 16, 4);
++  vector_res = vmaxnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 4) [] = {B0, C0, A0, D0};
++  VLOAD (vsrc, buf_src2, , float, f, 16, 4);
++  vector_res = vmaxnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 4) [] = {B0, C0, D0, A0};
++  VLOAD (vsrc, buf_src3, , float, f, 16, 4);
++  vector_res = vmaxnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++#undef TEST_MSG
++#define TEST_MSG "VMAXNMVQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A1, B1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 8) [] = {B1, A1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src1, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 8) [] = {B1, C1, A1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src2, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 8) [] = {B1, C1, D1, A1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src3, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src4, float, 16, 8) [] = {B1, C1, D1, E1, A1, F1, G1, H1};
++  VLOAD (vsrc, buf_src4, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src5, float, 16, 8) [] = {B1, C1, D1, E1, F1, A1, G1, H1};
++  VLOAD (vsrc, buf_src5, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src6, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, A1, H1};
++  VLOAD (vsrc, buf_src6, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src7, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, H1, A1};
++  VLOAD (vsrc, buf_src7, q, float, f, 16, 8);
++  vector_res = vmaxnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++}
++
++int
++main (void)
++{
++  exec_vmaxnmv_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c
+@@ -0,0 +1,131 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (123.4)
++#define B0 FP16_C (-567.8)
++#define C0 FP16_C (34.8)
++#define D0 FP16_C (0.0)
++
++#define A1 FP16_C (1025.8)
++#define B1 FP16_C (13.4)
++#define C1 FP16_C (-567.8)
++#define D1 FP16_C (10)
++#define E1 FP16_C (-0.0)
++#define F1 FP16_C (567.8)
++#define G1 FP16_C (0.0)
++#define H1 FP16_C (10)
++
++/* Expected results for vmaxv.  */
++uint16_t expect = 0x57B6 /* A0.  */;
++uint16_t expect_alt = 0x6402 /* A1.  */;
++
++void exec_vmaxv_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMAXV (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A0, B0, C0, D0};
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  float16_t vector_res = vmaxv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 4) [] = {B0, A0, C0, D0};
++  VLOAD (vsrc, buf_src1, , float, f, 16, 4);
++  vector_res = vmaxv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 4) [] = {B0, C0, A0, D0};
++  VLOAD (vsrc, buf_src2, , float, f, 16, 4);
++  vector_res = vmaxv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 4) [] = {B0, C0, D0, A0};
++  VLOAD (vsrc, buf_src3, , float, f, 16, 4);
++  vector_res = vmaxv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++#undef TEST_MSG
++#define TEST_MSG "VMAXVQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A1, B1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 8) [] = {B1, A1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src1, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 8) [] = {B1, C1, A1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src2, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 8) [] = {B1, C1, D1, A1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src3, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src4, float, 16, 8) [] = {B1, C1, D1, E1, A1, F1, G1, H1};
++  VLOAD (vsrc, buf_src4, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src5, float, 16, 8) [] = {B1, C1, D1, E1, F1, A1, G1, H1};
++  VLOAD (vsrc, buf_src5, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src6, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, A1, H1};
++  VLOAD (vsrc, buf_src6, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src7, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, H1, A1};
++  VLOAD (vsrc, buf_src7, q, float, f, 16, 8);
++  vector_res = vmaxvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++}
++
++int
++main (void)
++{
++  exec_vmaxv_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
+@@ -7,6 +7,10 @@
+ 
+ #define HAS_FLOAT_VARIANT
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++#define HAS_FLOAT16_VARIANT
++#endif
++
+ /* Expected results.  */
+ VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 				       0xf3, 0xf3, 0xf3, 0xf3 };
+@@ -16,6 +20,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					0xf3, 0xf3, 0xf3, 0xf3 };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff1, 0xfff1 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcc00, 0xcbc0, 0xcbc0, 0xcbc0 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1780000 };
+ VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					0xf4, 0xf4, 0xf4, 0xf4,
+@@ -31,11 +38,41 @@ VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					 0xf9, 0xf9, 0xf9, 0xf9 };
+ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff2,
+ 					 0xfff2, 0xfff2, 0xfff2, 0xfff2 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80, 0xcb40, 0xcb40,
++					      0xcb40, 0xcb40, 0xcb40, 0xcb40 };
++#endif
+ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 					 0xfffffff1, 0xfffffff1 };
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 					   0xc1680000, 0xc1680000 };
+ /* Expected results with special FP values.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_mnan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						   0x7e00, 0x7e00,
++						   0x7e00, 0x7e00,
++						   0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_inf, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_minf, hfloat, 16, 8) [] = { 0xfc00, 0xfc00,
++						   0xfc00, 0xfc00,
++						   0xfc00, 0xfc00,
++						   0xfc00, 0xfc00 };
++VECT_VAR_DECL(expected_zero1, hfloat, 16, 8) [] = { 0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000 };
++VECT_VAR_DECL(expected_zero2, hfloat, 16, 8) [] = { 0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000 };
++#endif
+ VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 					       0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c
+@@ -0,0 +1,34 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++#define A 123.4
++#define B -567.8
++#define C -34.8
++#define D 1024
++#define E 663.1
++#define F 169.1
++#define G -4.8
++#define H 77
++
++float16_t input_1[] = { A, B, C, D };
++float16_t input_2[] = { E, F, G, H };
++float16_t expected[] = { A, B, C, H };
++
++#define TEST_MSG "VMINH_F16"
++#define INSN_NAME vminh_f16
++
++#define INPUT_1 input_1
++#define INPUT_2 input_2
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnm_1.c
+@@ -0,0 +1,51 @@
++/* This file tests an intrinsic which currently has only an f16 variant and that
++   is only available when FP16 arithmetic instructions are supported.  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define INSN_NAME vminnm
++#define TEST_MSG "VMINNM/VMINMQ"
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++#define HAS_FLOAT16_VARIANT
++#endif
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcc00, 0xcbc0, 0xcbc0, 0xcbc0 };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80, 0xcb40, 0xcb40,
++					      0xcb40, 0xcb40, 0xcb40, 0xcb40 };
++#endif
++
++/* Expected results with special FP values.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_mnan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00,
++						   0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_inf, hfloat, 16, 8) [] = { 0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00,
++						  0x3c00, 0x3c00 };
++VECT_VAR_DECL(expected_minf, hfloat, 16, 8) [] = { 0xfc00, 0xfc00,
++						   0xfc00, 0xfc00,
++						   0xfc00, 0xfc00,
++						   0xfc00, 0xfc00 };
++VECT_VAR_DECL(expected_zero1, hfloat, 16, 8) [] = { 0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000 };
++VECT_VAR_DECL(expected_zero2, hfloat, 16, 8) [] = { 0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000,
++						    0x8000, 0x8000 };
++#endif
++
++#include "binary_op_float.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++#define INFF __builtin_inf ()
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0xc454 /* -4.328125 */,
++  0x4233 /* 3.099609 */,
++  0x4d00 /* 20.000000 */,
++  0xa51f /* -0.020004 */,
++  0xc09a /* -2.300781 */,
++  0xc73b /* -7.230469 */,
++  0xc79a /* -7.601562 */,
++  0x34f6 /* 0.310059 */,
++  0xc73b /* -7.230469 */,
++  0x3800 /* 0.500000 */,
++  0xc79a /* -7.601562 */,
++  0x451a /* 5.101562 */,
++  0xc64d /* -6.300781 */,
++  0x3556 /* 0.333496 */,
++  0xfc00 /* -inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VMINNMH_F16"
++#define INSN_NAME vminnmh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c
+@@ -0,0 +1,131 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (-567.8)
++#define B0 FP16_C (__builtin_nanf (""))
++#define C0 FP16_C (34.8)
++#define D0 FP16_C (-__builtin_nanf (""))
++
++#define A1 FP16_C (-567.8)
++#define B1 FP16_C (1025.8)
++#define C1 FP16_C (-__builtin_nanf (""))
++#define D1 FP16_C (10)
++#define E1 FP16_C (-0.0)
++#define F1 FP16_C (__builtin_nanf (""))
++#define G1 FP16_C (0.0)
++#define H1 FP16_C (10)
++
++/* Expected results for vminnmv.  */
++uint16_t expect = 0xE070 /* A0.  */;
++uint16_t expect_alt = 0xE070 /* A1.  */;
++
++void exec_vminnmv_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMINNMV (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A0, B0, C0, D0};
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  float16_t vector_res = vminnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 4) [] = {B0, A0, C0, D0};
++  VLOAD (vsrc, buf_src1, , float, f, 16, 4);
++  vector_res = vminnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 4) [] = {B0, C0, A0, D0};
++  VLOAD (vsrc, buf_src2, , float, f, 16, 4);
++  vector_res = vminnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 4) [] = {B0, C0, D0, A0};
++  VLOAD (vsrc, buf_src3, , float, f, 16, 4);
++  vector_res = vminnmv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++#undef TEST_MSG
++#define TEST_MSG "VMINNMVQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A1, B1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 8) [] = {B1, A1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src1, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 8) [] = {B1, C1, A1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src2, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 8) [] = {B1, C1, D1, A1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src3, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src4, float, 16, 8) [] = {B1, C1, D1, E1, A1, F1, G1, H1};
++  VLOAD (vsrc, buf_src4, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src5, float, 16, 8) [] = {B1, C1, D1, E1, F1, A1, G1, H1};
++  VLOAD (vsrc, buf_src5, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src6, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, A1, H1};
++  VLOAD (vsrc, buf_src6, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src7, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, H1, A1};
++  VLOAD (vsrc, buf_src7, q, float, f, 16, 8);
++  vector_res = vminnmvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++}
++
++int
++main (void)
++{
++  exec_vminnmv_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c
+@@ -0,0 +1,131 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A0 FP16_C (-567.8)
++#define B0 FP16_C (123.4)
++#define C0 FP16_C (34.8)
++#define D0 FP16_C (0.0)
++
++#define A1 FP16_C (-567.8)
++#define B1 FP16_C (1025.8)
++#define C1 FP16_C (13.4)
++#define D1 FP16_C (10)
++#define E1 FP16_C (-0.0)
++#define F1 FP16_C (567.8)
++#define G1 FP16_C (0.0)
++#define H1 FP16_C (10)
++
++/* Expected results for vminv.  */
++uint16_t expect = 0xE070 /* A0.  */;
++uint16_t expect_alt = 0xE070 /* A1.  */;
++
++void exec_vminv_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMINV (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A0, B0, C0, D0};
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  float16_t vector_res = vminv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 4) [] = {B0, A0, C0, D0};
++  VLOAD (vsrc, buf_src1, , float, f, 16, 4);
++  vector_res = vminv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 4) [] = {B0, C0, A0, D0};
++  VLOAD (vsrc, buf_src2, , float, f, 16, 4);
++  vector_res = vminv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 4) [] = {B0, C0, D0, A0};
++  VLOAD (vsrc, buf_src3, , float, f, 16, 4);
++  vector_res = vminv_f16 (VECT_VAR (vsrc, float, 16, 4));
++
++  if (* (uint16_t *) &vector_res != expect)
++    abort ();
++
++#undef TEST_MSG
++#define TEST_MSG "VMINVQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A1, B1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src1, float, 16, 8) [] = {B1, A1, C1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src1, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src2, float, 16, 8) [] = {B1, C1, A1, D1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src2, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src3, float, 16, 8) [] = {B1, C1, D1, A1, E1, F1, G1, H1};
++  VLOAD (vsrc, buf_src3, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src4, float, 16, 8) [] = {B1, C1, D1, E1, A1, F1, G1, H1};
++  VLOAD (vsrc, buf_src4, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src5, float, 16, 8) [] = {B1, C1, D1, E1, F1, A1, G1, H1};
++  VLOAD (vsrc, buf_src5, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src6, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, A1, H1};
++  VLOAD (vsrc, buf_src6, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++
++  VECT_VAR_DECL (buf_src7, float, 16, 8) [] = {B1, C1, D1, E1, F1, G1, H1, A1};
++  VLOAD (vsrc, buf_src7, q, float, f, 16, 8);
++  vector_res = vminvq_f16 (VECT_VAR (vsrc, float, 16, 8));
++
++  if (* (uint16_t *) &vector_res != expect_alt)
++    abort ();
++}
++
++int
++main (void)
++{
++  exec_vminv_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn.c
+@@ -35,11 +35,11 @@ void exec_vmovn (void)
+   TEST_VMOVN(uint, u, 32, 16, 4);
+   TEST_VMOVN(uint, u, 64, 32, 2);
+ 
+-  CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
+-  CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ }
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul.c
+@@ -13,6 +13,10 @@ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfab0, 0xfb05, 0xfb5a, 0xfbaf };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffff9a0, 0xfffffa06 };
+ VECT_VAR_DECL(expected,poly,8,8) [] = { 0xc0, 0x84, 0x48, 0xc,
+ 					0xd0, 0x94, 0x58, 0x1c };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xe02a, 0xdfcf,
++					      0xdf4a, 0xdec4 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc4053333, 0xc3f9c000 };
+ VECT_VAR_DECL(expected,int,8,16) [] = { 0x90, 0x7, 0x7e, 0xf5,
+ 					0x6c, 0xe3, 0x5a, 0xd1,
+@@ -34,13 +38,15 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0x60, 0xca, 0x34, 0x9e,
+ 					 0xc8, 0x62, 0x9c, 0x36,
+ 					 0x30, 0x9a, 0x64, 0xce,
+ 					 0x98, 0x32, 0xcc, 0x66 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xe63a, 0xe5d6, 0xe573, 0xe50f,
++					      0xe4ac, 0xe448, 0xe3c8, 0xe301 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4c73333, 0xc4bac000,
+ 					   0xc4ae4ccd, 0xc4a1d999 };
+ 
+-#ifndef INSN_NAME
+ #define INSN_NAME vmul
+ #define TEST_MSG "VMUL"
+-#endif
+ 
+ #define FNNAME1(NAME) exec_ ## NAME
+ #define FNNAME(NAME) FNNAME1(NAME)
+@@ -80,6 +86,17 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VMUL(poly, 8, 16);
+   DECL_VMUL(float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector1, float, 16, 4);
++  DECL_VARIABLE(vector1, float, 16, 8);
++
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++
+   clean_results ();
+ 
+   /* Initialize input "vector1" from "buffer".  */
+@@ -99,6 +116,10 @@ void FNNAME (INSN_NAME) (void)
+   VLOAD(vector1, buffer, q, uint, u, 32, 4);
+   VLOAD(vector1, buffer, q, poly, p, 8, 16);
+   VLOAD(vector1, buffer, q, float, f, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector1, buffer, , float, f, 16, 4);
++  VLOAD(vector1, buffer, q, float, f, 16, 8);
++#endif
+ 
+   /* Choose init value arbitrarily.  */
+   VDUP(vector2, , int, s, 8, 8, 0x11);
+@@ -117,6 +138,10 @@ void FNNAME (INSN_NAME) (void)
+   VDUP(vector2, q, uint, u, 32, 4, 0xCC);
+   VDUP(vector2, q, poly, p, 8, 16, 0xAA);
+   VDUP(vector2, q, float, f, 32, 4, 99.6f);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 33.3f);
++  VDUP(vector2, q, float, f, 16, 8, 99.6f);
++#endif
+ 
+   /* Execute the tests.  */
+   TEST_VMUL(INSN_NAME, , int, s, 8, 8);
+@@ -135,6 +160,10 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VMUL(INSN_NAME, q, uint, u, 32, 4);
+   TEST_VMUL(INSN_NAME, q, poly, p, 8, 16);
+   TEST_VMUL(INSN_NAME, q, float, f, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VMUL(INSN_NAME, , float, f, 16, 4);
++  TEST_VMUL(INSN_NAME, q, float, f, 16, 8);
++#endif
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+@@ -142,7 +171,7 @@ void FNNAME (INSN_NAME) (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+@@ -150,8 +179,12 @@ void FNNAME (INSN_NAME) (void)
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c
+@@ -7,6 +7,9 @@ VECT_VAR_DECL(expected,int,16,4) [] = { 0xffc0, 0xffc4, 0xffc8, 0xffcc };
+ VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffde0, 0xfffffe02 };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xbbc0, 0xc004, 0xc448, 0xc88c };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffface0, 0xffffb212 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xddb3, 0xdd58, 0xdcfd, 0xdca1 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc3b66666, 0xc3ab0000 };
+ VECT_VAR_DECL(expected,int,16,8) [] = { 0xffc0, 0xffc4, 0xffc8, 0xffcc,
+ 					0xffd0, 0xffd4, 0xffd8, 0xffdc };
+@@ -16,6 +19,10 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xbbc0, 0xc004, 0xc448, 0xc88c,
+ 					 0xccd0, 0xd114, 0xd558, 0xd99c };
+ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffface0, 0xffffb212,
+ 					 0xffffb744, 0xffffbc76 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xddb3, 0xdd58, 0xdcfd, 0xdca1,
++					      0xdc46, 0xdbd6, 0xdb20, 0xda69 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc3b66666, 0xc3ab0000,
+ 					   0xc39f9999, 0xc3943333 };
+ 
+@@ -45,11 +52,20 @@ void exec_vmul_lane (void)
+ 
+   DECL_VMUL(vector);
+   DECL_VMUL(vector_res);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+ 
+   DECL_VARIABLE(vector2, int, 16, 4);
+   DECL_VARIABLE(vector2, int, 32, 2);
+   DECL_VARIABLE(vector2, uint, 16, 4);
+   DECL_VARIABLE(vector2, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector2, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector2, float, 32, 2);
+ 
+   clean_results ();
+@@ -59,11 +75,17 @@ void exec_vmul_lane (void)
+   VLOAD(vector, buffer, , int, s, 32, 2);
+   VLOAD(vector, buffer, , uint, u, 16, 4);
+   VLOAD(vector, buffer, , uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, int, s, 16, 8);
+   VLOAD(vector, buffer, q, int, s, 32, 4);
+   VLOAD(vector, buffer, q, uint, u, 16, 8);
+   VLOAD(vector, buffer, q, uint, u, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+   /* Initialize vector2.  */
+@@ -71,6 +93,9 @@ void exec_vmul_lane (void)
+   VDUP(vector2, , int, s, 32, 2, 0x22);
+   VDUP(vector2, , uint, u, 16, 4, 0x444);
+   VDUP(vector2, , uint, u, 32, 2, 0x532);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 22.8f);
++#endif
+   VDUP(vector2, , float, f, 32, 2, 22.8f);
+ 
+   /* Choose lane arbitrarily.  */
+@@ -78,22 +103,34 @@ void exec_vmul_lane (void)
+   TEST_VMUL_LANE(, int, s, 32, 2, 2, 1);
+   TEST_VMUL_LANE(, uint, u, 16, 4, 4, 2);
+   TEST_VMUL_LANE(, uint, u, 32, 2, 2, 1);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VMUL_LANE(, float, f, 16, 4, 4, 1);
++#endif
+   TEST_VMUL_LANE(, float, f, 32, 2, 2, 1);
+   TEST_VMUL_LANE(q, int, s, 16, 8, 4, 2);
+   TEST_VMUL_LANE(q, int, s, 32, 4, 2, 0);
+   TEST_VMUL_LANE(q, uint, u, 16, 8, 4, 2);
+   TEST_VMUL_LANE(q, uint, u, 32, 4, 2, 1);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VMUL_LANE(q, float, f, 16, 8, 4, 0);
++#endif
+   TEST_VMUL_LANE(q, float, f, 32, 4, 2, 0);
+ 
+-  CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+ }
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c
+@@ -0,0 +1,454 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (-56.8)
++#define C FP16_C (-34.8)
++#define D FP16_C (12)
++#define E FP16_C (63.1)
++#define F FP16_C (19.1)
++#define G FP16_C (-4.8)
++#define H FP16_C (77)
++
++#define I FP16_C (0.7)
++#define J FP16_C (-78)
++#define K FP16_C (11.23)
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-8)
++#define O FP16_C (-1.1)
++#define P FP16_C (-9.7)
++
++/* Expected results for vmul_lane.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 4) []
++  = { 0x629B /* A * E.  */,
++      0xEB00 /* B * E.  */,
++      0xE84A /* C * E.  */,
++      0x61EA /* D * E.  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 4) []
++  = { 0x5BFF /* A * F.  */,
++      0xE43D /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0x5B29 /* D * F.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 4) []
++  = { 0xD405 /* A * G.  */,
++      0x5C43 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0xD334 /* D * G.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 4) []
++  = { 0x6408 /* A * H.  */,
++      0xEC46 /* B * H.  */,
++      0xE93C /* C * H.  */,
++      0x6338 /* D * H.  */ };
++
++/* Expected results for vmulq_lane.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 8) []
++  = { 0x629B /* A * E.  */,
++      0xEB00 /* B * E.  */,
++      0xE84A /* C * E.  */,
++      0x61EA /* D * E.  */,
++      0x5186 /* I * E.  */,
++      0xECCE /* J * E.  */,
++      0x6189 /* K * E.  */,
++      0x6E0A /* L * E.  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 8) []
++  = { 0x5BFF /* A * F.  */,
++      0xE43D /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0x5B29 /* D * F.  */,
++      0x4AAF /* I * F.  */,
++      0xE5D1 /* J * F.  */,
++      0x5AB3 /* K * F.  */,
++      0x674F /* L * F.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 8) []
++  = { 0xD405 /* A * G.  */,
++      0x5C43 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0xD334 /* D * G.  */,
++      0xC2B9 /* I * G.  */,
++      0x5DDA /* J * G.  */,
++      0xD2BD /* K * G.  */,
++      0xDF5A /* L * G.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 8) []
++  = { 0x6408 /* A * H.  */,
++      0xEC46 /* B * H.  */,
++      0xE93C /* C * H.  */,
++      0x6338 /* D * H.  */,
++      0x52BD /* I * H.  */,
++      0xEDDE /* J * H.  */,
++      0x62C1 /* K * H.  */,
++      0x6F5E /* L * H.  */ };
++
++/* Expected results for vmul_laneq.  */
++VECT_VAR_DECL (expected_laneq0_static, hfloat, 16, 4) []
++  = { 0x629B /* A * E.  */,
++      0xEB00 /* B * E.  */,
++      0xE84A /* C * E.  */,
++      0x61EA /* D * E.  */ };
++
++VECT_VAR_DECL (expected_laneq1_static, hfloat, 16, 4) []
++  = { 0x5BFF /* A * F.  */,
++      0xE43D /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0x5B29 /* D * F.  */ };
++
++VECT_VAR_DECL (expected_laneq2_static, hfloat, 16, 4) []
++  = { 0xD405 /* A * G.  */,
++      0x5C43 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0xD334 /* D * G.  */ };
++
++VECT_VAR_DECL (expected_laneq3_static, hfloat, 16, 4) []
++  = { 0x6408 /* A * H.  */,
++      0xEC46 /* B * H.  */,
++      0xE93C /* C * H.  */,
++      0x6338 /* D * H.  */ };
++
++VECT_VAR_DECL (expected_laneq4_static, hfloat, 16, 4) []
++  = { 0x648F /* A * M.  */,
++      0xECD5 /* B * M.  */,
++      0xE9ED /* C * M.  */,
++      0x6416 /* D * M.  */ };
++
++VECT_VAR_DECL (expected_laneq5_static, hfloat, 16, 4) []
++  = { 0xD6B3 /* A * N.  */,
++      0x5F1A /* B * N.  */,
++      0x5C5A /* C * N.  */,
++      0xD600 /* D * N.  */ };
++
++VECT_VAR_DECL (expected_laneq6_static, hfloat, 16, 4) []
++  = { 0xCB5E /* A * O.  */,
++      0x53CF /* B * O.  */,
++      0x50C9 /* C * O.  */,
++      0xCA99 /* D * O.  */ };
++
++VECT_VAR_DECL (expected_laneq7_static, hfloat, 16, 4) []
++  = { 0xD810 /* A * P.  */,
++      0x604F /* B * P.  */,
++      0x5D47 /* C * P.  */,
++      0xD747 /* D * P.  */ };
++
++/* Expected results for vmulq_laneq.  */
++VECT_VAR_DECL (expected_laneq0_static, hfloat, 16, 8) []
++  = { 0x629B /* A * E.  */,
++      0xEB00 /* B * E.  */,
++      0xE84A /* C * E.  */,
++      0x61EA /* D * E.  */,
++      0x5186 /* I * E.  */,
++      0xECCE /* J * E.  */,
++      0x6189 /* K * E.  */,
++      0x6E0A /* L * E.  */ };
++
++VECT_VAR_DECL (expected_laneq1_static, hfloat, 16, 8) []
++  = { 0x5BFF /* A * F.  */,
++      0xE43D /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0x5B29 /* D * F.  */,
++      0x4AAF /* I * F.  */,
++      0xE5D1 /* J * F.  */,
++      0x5AB3 /* K * F.  */,
++      0x674F /* L * F.  */ };
++
++VECT_VAR_DECL (expected_laneq2_static, hfloat, 16, 8) []
++  = { 0xD405 /* A * G.  */,
++      0x5C43 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0xD334 /* D * G.  */,
++      0xC2B9 /* I * G.  */,
++      0x5DDA /* J * G.  */,
++      0xD2BD /* K * G.  */,
++      0xDF5A /* L * G.  */ };
++
++VECT_VAR_DECL (expected_laneq3_static, hfloat, 16, 8) []
++  = { 0x6408 /* A * H.  */,
++      0xEC46 /* B * H.  */,
++      0xE93C /* C * H.  */,
++      0x6338 /* D * H.  */,
++      0x52BD /* I * H.  */,
++      0xEDDE /* J * H.  */,
++      0x62C1 /* K * H.  */,
++      0x6F5E /* L * H.  */ };
++
++VECT_VAR_DECL (expected_laneq4_static, hfloat, 16, 8) []
++  = { 0x648F /* A * M.  */,
++      0xECD5 /* B * M.  */,
++      0xE9ED /* C * M.  */,
++      0x6416 /* D * M.  */,
++      0x53A0 /* I * M.  */,
++      0xEEA3 /* J * M.  */,
++      0x63A4 /* K * M.  */,
++      0x702B /* L * M.  */ };
++
++VECT_VAR_DECL (expected_laneq5_static, hfloat, 16, 8) []
++  = { 0xD6B3 /* A * N.  */,
++      0x5F1A /* B * N.  */,
++      0x5C5A /* C * N.  */,
++      0xD600 /* D * N.  */,
++      0xC59A /* I * N.  */,
++      0x60E0 /* J * N.  */,
++      0xD59D /* K * N.  */,
++      0xE220 /* L * N.  */ };
++
++VECT_VAR_DECL (expected_laneq6_static, hfloat, 16, 8) []
++  = { 0xCB5E /* A * O.  */,
++      0x53CF /* B * O.  */,
++      0x50C9 /* C * O.  */,
++      0xCA99 /* D * O.  */,
++      0xBA29 /* I * O.  */,
++      0x555C /* J * O.  */,
++      0xCA2C /* K * O.  */,
++      0xD6BC /* L * O.  */ };
++
++VECT_VAR_DECL (expected_laneq7_static, hfloat, 16, 8) []
++  = { 0xD810 /* A * P.  */,
++      0x604F /* B * P.  */,
++      0x5D47 /* C * P.  */,
++      0xD747 /* D * P.  */,
++      0xC6CB /* I * P.  */,
++      0x61EA /* J * P.  */,
++      0xD6CF /* K * P.  */,
++      0xE36E /* L * P.  */ };
++
++void exec_vmul_lane_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMUL_LANE (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {E, F, G, H};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vmul_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		     VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULQ_LANE (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vmulq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 0);
++
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		      VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMUL_LANEQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {E, F, G, H, M, N, O, P};
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq3_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 4);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq4_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 5);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq5_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 6);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq6_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmul_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 8), 7);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq7_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULQ_LANEQ (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq3_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 4);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq4_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 5);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq5_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 6);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq6_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 8), 7);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq7_static, "");
++}
++
++int
++main (void)
++{
++  exec_vmul_lane_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c
+@@ -7,6 +7,9 @@ VECT_VAR_DECL(expected,int,16,4) [] = { 0xfef0, 0xff01, 0xff12, 0xff23 };
+ VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffde0, 0xfffffe02 };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfcd0, 0xfd03, 0xfd36, 0xfd69 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffbc0, 0xfffffc04 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xdd93, 0xdd3a, 0xdce1, 0xdc87 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc3b26666, 0xc3a74000 };
+ VECT_VAR_DECL(expected,int,16,8) [] = { 0xfab0, 0xfb05, 0xfb5a, 0xfbaf,
+ 					0xfc04, 0xfc59, 0xfcae, 0xfd03 };
+@@ -16,6 +19,10 @@ VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf890, 0xf907, 0xf97e, 0xf9f5,
+ 					 0xfa6c, 0xfae3, 0xfb5a, 0xfbd1 };
+ VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffff780, 0xfffff808,
+ 					 0xfffff890, 0xfffff918 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xe58e, 0xe535, 0xe4dc, 0xe483,
++					      0xe42a, 0xe3a3, 0xe2f2, 0xe240 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4b1cccd, 0xc4a6b000,
+ 					   0xc49b9333, 0xc4907667 };
+ 
+@@ -50,6 +57,13 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VMUL(vector);
+   DECL_VMUL(vector_res);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++
+   clean_results ();
+ 
+   /* Initialize vector from pre-initialized values.  */
+@@ -57,11 +71,17 @@ void FNNAME (INSN_NAME) (void)
+   VLOAD(vector, buffer, , int, s, 32, 2);
+   VLOAD(vector, buffer, , uint, u, 16, 4);
+   VLOAD(vector, buffer, , uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, int, s, 16, 8);
+   VLOAD(vector, buffer, q, int, s, 32, 4);
+   VLOAD(vector, buffer, q, uint, u, 16, 8);
+   VLOAD(vector, buffer, q, uint, u, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+   /* Choose multiplier arbitrarily.  */
+@@ -69,22 +89,34 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VMUL_N(, int, s, 32, 2, 0x22);
+   TEST_VMUL_N(, uint, u, 16, 4, 0x33);
+   TEST_VMUL_N(, uint, u, 32, 2, 0x44);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VMUL_N(, float, f, 16, 4, 22.3f);
++#endif
+   TEST_VMUL_N(, float, f, 32, 2, 22.3f);
+   TEST_VMUL_N(q, int, s, 16, 8, 0x55);
+   TEST_VMUL_N(q, int, s, 32, 4, 0x66);
+   TEST_VMUL_N(q, uint, u, 16, 8, 0x77);
+   TEST_VMUL_N(q, uint, u, 32, 4, 0x88);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VMUL_N(q, float, f, 16, 8, 88.9f);
++#endif
+   TEST_VMUL_N(q, float, f, 32, 4, 88.9f);
+ 
+-  CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+ }
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++#define INFF __builtin_inf ()
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0xc854 /* -8.656250 */,
++  0x5cd8 /* 310.000000 */,
++  0x60b0 /* 600.000000 */,
++  0xa019 /* -0.008003 */,
++  0xbc9a /* -1.150391 */,
++  0xc8cf /* -9.617188 */,
++  0x51fd /* 47.906250 */,
++  0x4634 /* 6.203125 */,
++  0xc0d9 /* -2.423828 */,
++  0x3c9a /* 1.150391 */,
++  0xc79a /* -7.601562 */,
++  0x5430 /* 67.000000 */,
++  0xbfd0 /* -1.953125 */,
++  0x46ac /* 6.671875 */,
++  0xfc00 /* -inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VMULH_F16"
++#define INSN_NAME vmulh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c
+@@ -0,0 +1,90 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (-56.8)
++#define C FP16_C (-34.8)
++#define D FP16_C (12)
++#define E FP16_C (63.1)
++#define F FP16_C (19.1)
++#define G FP16_C (-4.8)
++#define H FP16_C (77)
++
++#define I FP16_C (0.7)
++#define J FP16_C (-78)
++#define K FP16_C (11.23)
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-8)
++#define O FP16_C (-1.1)
++#define P FP16_C (-9.7)
++
++extern void abort ();
++
++float16_t src1[8] = { A, B, C, D, I, J, K, L };
++VECT_VAR_DECL (src2, float, 16, 4) [] = { E, F, G, H };
++VECT_VAR_DECL (src2, float, 16, 8) [] = { E, F, G, H, M, N, O, P };
++
++/* Expected results for vmulh_lane.  */
++uint16_t expected[4] = { 0x629B /* A * E.  */, 0xE43D /* B * F.  */,
++			 0x5939 /* C * G.  */, 0x6338 /* D * H.  */ };
++
++
++/* Expected results for vmulh_lane.  */
++uint16_t expected_laneq[8] = { 0x629B /* A * E.  */,
++			       0xE43D /* B * F.  */,
++			       0x5939 /* C * G.  */,
++			       0x6338 /* D * H.  */,
++			       0x53A0 /* I * M.  */,
++			       0x60E0 /* J * N.  */,
++			       0xCA2C /* K * O.  */,
++			       0xE36E /* L * P.  */ };
++
++void exec_vmulh_lane_f16 (void)
++{
++#define CHECK_LANE(N)\
++  ret = vmulh_lane_f16 (src1[N], VECT_VAR (vsrc2, float, 16, 4), N);\
++  if (*(uint16_t *) &ret != expected[N])\
++    abort ();
++
++  DECL_VARIABLE(vsrc2, float, 16, 4);
++  VLOAD (vsrc2, src2, , float, f, 16, 4);
++  float16_t ret;
++
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++
++#undef CHECK_LANE
++#define CHECK_LANE(N)\
++  ret = vmulh_laneq_f16 (src1[N], VECT_VAR (vsrc2, float, 16, 8), N);\
++  if (*(uint16_t *) &ret != expected_laneq[N])\
++    abort ();
++
++  DECL_VARIABLE(vsrc2, float, 16, 8);
++  VLOAD (vsrc2, src2, q, float, f, 16, 8);
++
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++  CHECK_LANE(4)
++  CHECK_LANE(5)
++  CHECK_LANE(6)
++  CHECK_LANE(7)
++}
++
++int
++main (void)
++{
++  exec_vmulh_lane_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull.c
+@@ -59,13 +59,13 @@ void exec_vmull (void)
+   TEST_VMULL(uint, u, 32, 64, 2);
+   TEST_VMULL(poly, p, 8, 16, 8);
+ 
+-  CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, int, 64, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 64, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
++  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c
+@@ -54,9 +54,9 @@ void exec_vmull_lane (void)
+   TEST_VMULL_LANE(uint, u, 32, 64, 2, 1);
+ 
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, int, 64, 2, PRIx32, expected, "");
++  CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 64, 2, PRIx32, expected, "");
++  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+ }
+ 
+ int main (void)
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c
+@@ -0,0 +1,84 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (__builtin_inff ())
++#define C FP16_C (-34.8)
++#define D FP16_C (-__builtin_inff ())
++#define E FP16_C (63.1)
++#define F FP16_C (0.0)
++#define G FP16_C (-4.8)
++#define H FP16_C (0.0)
++
++#define I FP16_C (0.7)
++#define J FP16_C (-__builtin_inff ())
++#define K FP16_C (11.23)
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-0.0)
++#define O FP16_C (-1.1)
++#define P FP16_C (7)
++
++/* Expected results for vmulx.  */
++VECT_VAR_DECL (expected_static, hfloat, 16, 4) []
++  = { 0x629B /* A * E.  */, 0x4000 /* FP16_C (2.0f).  */,
++      0x5939 /* C * G.  */, 0xC000 /* FP16_C (-2.0f).  */ };
++
++VECT_VAR_DECL (expected_static, hfloat, 16, 8) []
++  = { 0x629B /* A * E.  */, 0x4000 /* FP16_C (2.0f).  */,
++      0x5939 /* C * G.  */, 0xC000 /* FP16_C (-2.0f).  */,
++      0x53A0 /* I * M.  */, 0x4000 /* FP16_C (2.0f).  */,
++      0xCA2C /* K * O.  */, 0x615C /* L * P.  */ };
++
++void exec_vmulx_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMULX (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {E, F, G, H};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vmulx_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		 VECT_VAR (vsrc_2, float, 16, 4));
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULXQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {E, F, G, H, M, N, O, P};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vmulxq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		  VECT_VAR (vsrc_2, float, 16, 8));
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_static, "");
++}
++
++int
++main (void)
++{
++  exec_vmulx_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c
+@@ -0,0 +1,452 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (__builtin_inff ())
++#define C FP16_C (-34.8)
++#define D FP16_C (-__builtin_inff ())
++#define E FP16_C (-0.0)
++#define F FP16_C (19.1)
++#define G FP16_C (-4.8)
++#define H FP16_C (0.0)
++
++#define I FP16_C (0.7)
++#define J FP16_C (-78)
++#define K FP16_C (-__builtin_inff ())
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-8)
++#define O FP16_C (-1.1)
++#define P FP16_C (-0.0)
++
++/* Expected results for vmulx_lane.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 4) []
++  = { 0x8000 /* A * E.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * E.  */,
++      0x4000 /* FP16_C (2.0f).  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 4) []
++  = { 0x5BFF /* A * F.  */,
++      0x7C00 /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0xFC00 /* D * F.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 4) []
++  = { 0xD405 /* A * G.  */,
++      0xFC00 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0x7C00 /* D * G.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 4) []
++  = { 0x0000 /* A * H.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* C * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */ };
++
++/* Expected results for vmulxq_lane.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 8) []
++  = { 0x8000 /* A * E.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * E.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* I * E.  */,
++      0x0000 /* J * E.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* L * E.  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 8) []
++  = { 0x5BFF /* A * F.  */,
++      0x7C00 /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0xFC00 /* D * F.  */,
++      0x4AAF /* I * F.  */,
++      0xE5D1 /* J * F.  */,
++      0xFC00 /* K * F.  */,
++      0x674F /* L * F.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 8) []
++  = { 0xD405 /* A * G.  */,
++      0xFC00 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0x7C00 /* D * G.  */,
++      0xC2B9 /* I * G.  */,
++      0x5DDA /* J * G.  */,
++      0x7C00 /* K * G.  */,
++      0xDF5A /* L * G.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 8) []
++  = { 0x0000 /* A * H.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* C * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* I * H.  */,
++      0x8000 /* J * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* L * H.  */};
++
++/* Expected results for vmulx_laneq.  */
++VECT_VAR_DECL (expected_laneq0_static, hfloat, 16, 4) []
++  = { 0x8000 /* A * E.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * E.  */,
++      0x4000 /* FP16_C (2.0f).  */ };
++
++VECT_VAR_DECL (expected_laneq1_static, hfloat, 16, 4) []
++  = { 0x5BFF /* A * F.  */,
++      0x7C00 /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0xFC00 /* D * F.  */ };
++
++VECT_VAR_DECL (expected_laneq2_static, hfloat, 16, 4) []
++  = { 0xD405 /* A * G.  */,
++      0xFC00 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0x7C00 /* D * G.  */ };
++
++VECT_VAR_DECL (expected_laneq3_static, hfloat, 16, 4) []
++  = { 0x0000 /* A * H.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* C * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */ };
++
++VECT_VAR_DECL (expected_laneq4_static, hfloat, 16, 4) []
++  = { 0x648F /* A * M.  */,
++      0x7C00 /* B * M.  */,
++      0xE9ED /* C * M.  */,
++      0xFC00 /* D * M.  */ };
++
++VECT_VAR_DECL (expected_laneq5_static, hfloat, 16, 4) []
++  = { 0xD6B3 /* A * N.  */,
++      0xFC00 /* B * N.  */,
++      0x5C5A /* C * N.  */,
++      0x7C00 /* D * N.  */ };
++
++VECT_VAR_DECL (expected_laneq6_static, hfloat, 16, 4) []
++  = { 0xCB5E /* A * O.  */,
++      0xFC00 /* B * O.  */,
++      0x50C9 /* C * O.  */,
++      0x7C00 /* D * O.  */ };
++
++VECT_VAR_DECL (expected_laneq7_static, hfloat, 16, 4) []
++  = { 0x8000 /* A * P.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * P.  */,
++      0x4000 /* FP16_C (2.0f).  */ };
++
++VECT_VAR_DECL (expected_laneq0_static, hfloat, 16, 8) []
++  = { 0x8000 /* A * E.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * E.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* I * E.  */,
++      0x0000 /* J * E.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* L * E.  */  };
++
++VECT_VAR_DECL (expected_laneq1_static, hfloat, 16, 8) []
++  = { 0x5BFF /* A * F.  */,
++      0x7C00 /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0xFC00 /* D * F.  */,
++      0x4AAF /* I * F.  */,
++      0xE5D1 /* J * F.  */,
++      0xFC00 /* K * F.  */,
++      0x674F /* L * F.  */ };
++
++VECT_VAR_DECL (expected_laneq2_static, hfloat, 16, 8) []
++  = { 0xD405 /* A * G.  */,
++      0xFC00 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0x7C00 /* D * G.  */,
++      0xC2B9 /* I * G.  */,
++      0x5DDA /* J * G.  */,
++      0x7C00 /* K * G.  */,
++      0xDF5A /* L * G.  */ };
++
++VECT_VAR_DECL (expected_laneq3_static, hfloat, 16, 8) []
++  = { 0x0000 /* A * H.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* C * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* I * H.  */,
++      0x8000 /* J * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* L * H.  */ };
++
++VECT_VAR_DECL (expected_laneq4_static, hfloat, 16, 8) []
++  = { 0x648F /* A * M.  */,
++      0x7C00 /* B * M.  */,
++      0xE9ED /* C * M.  */,
++      0xFC00 /* D * M.  */,
++      0x53A0 /* I * M.  */,
++      0xEEA3 /* J * M.  */,
++      0xFC00 /* K * M.  */,
++      0x702B /* L * M.  */ };
++
++VECT_VAR_DECL (expected_laneq5_static, hfloat, 16, 8) []
++  = { 0xD6B3 /* A * N.  */,
++      0xFC00 /* B * N.  */,
++      0x5C5A /* C * N.  */,
++      0x7C00 /* D * N.  */,
++      0xC59A /* I * N.  */,
++      0x60E0 /* J * N.  */,
++      0x7C00 /* K * N.  */,
++      0xE220 /* L * N.  */ };
++
++VECT_VAR_DECL (expected_laneq6_static, hfloat, 16, 8) []
++  = { 0xCB5E /* A * O.  */,
++      0xFC00 /* B * O.  */,
++      0x50C9 /* C * O.  */,
++      0x7C00 /* D * O.  */,
++      0xBA29 /* I * O.  */,
++      0x555C /* J * O.  */,
++      0x7C00 /* K * O.  */,
++      0xD6BC /* L * O.  */ };
++
++VECT_VAR_DECL (expected_laneq7_static, hfloat, 16, 8) []
++  = { 0x8000 /* A * P.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * P.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* I * P.  */,
++      0x0000 /* J * P.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* L * P.  */ };
++
++void exec_vmulx_lane_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMULX_LANE (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {E, F, G, H};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vmulx_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_lane_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		      VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULXQ_LANE (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vmulxq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 4), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 4), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 4), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_lane_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		       VECT_VAR (vsrc_2, float, 16, 4), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULX_LANEQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {E, F, G, H, M, N, O, P};
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 0);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 1);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 2);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 3);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq3_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 4);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq4_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 5);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq5_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 6);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq6_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		       VECT_VAR (vsrc_2, float, 16, 8), 7);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_laneq7_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULXQ_LANEQ (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 0);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 1);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 2);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 3);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq3_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 4);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq4_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 5);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq5_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 6);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq6_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_laneq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++			VECT_VAR (vsrc_2, float, 16, 8), 7);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_laneq7_static, "");
++}
++
++int
++main (void)
++{
++  exec_vmulx_lane_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c
+@@ -0,0 +1,177 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (__builtin_inff ())
++#define C FP16_C (-34.8)
++#define D FP16_C (-__builtin_inff ())
++#define E FP16_C (-0.0)
++#define F FP16_C (19.1)
++#define G FP16_C (-4.8)
++#define H FP16_C (0.0)
++
++float16_t elemE = E;
++float16_t elemF = F;
++float16_t elemG = G;
++float16_t elemH = H;
++
++#define I FP16_C (0.7)
++#define J FP16_C (-78)
++#define K FP16_C (11.23)
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-8)
++#define O FP16_C (-1.1)
++#define P FP16_C (-9.7)
++
++/* Expected results for vmulx_n.  */
++VECT_VAR_DECL (expected0_static, hfloat, 16, 4) []
++  = { 0x8000 /* A * E.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * E.  */,
++      0x4000 /* FP16_C (2.0f).  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 4) []
++  = { 0x5BFF /* A * F.  */,
++      0x7C00 /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0xFC00 /* D * F.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 4) []
++  = { 0xD405 /* A * G.  */,
++      0xFC00 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0x7C00 /* D * G.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 4) []
++  = { 0x0000 /* A * H.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* C * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */ };
++
++VECT_VAR_DECL (expected0_static, hfloat, 16, 8) []
++  = { 0x8000 /* A * E.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* C * E.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* I * E.  */,
++      0x0000 /* J * E.  */,
++      0x8000 /* K * E.  */,
++      0x8000 /* L * E.  */ };
++
++VECT_VAR_DECL (expected1_static, hfloat, 16, 8) []
++  = { 0x5BFF /* A * F.  */,
++      0x7C00 /* B * F.  */,
++      0xE131 /* C * F.  */,
++      0xFC00 /* D * F.  */,
++      0x4AAF /* I * F.  */,
++      0xE5D1 /* J * F.  */,
++      0x5AB3 /* K * F.  */,
++      0x674F /* L * F.  */ };
++
++VECT_VAR_DECL (expected2_static, hfloat, 16, 8) []
++  = { 0xD405 /* A * G.  */,
++      0xFC00 /* B * G.  */,
++      0x5939 /* C * G.  */,
++      0x7C00 /* D * G.  */,
++      0xC2B9 /* I * G.  */,
++      0x5DDA /* J * G.  */,
++      0xD2BD /* K * G.  */,
++      0xDF5A /* L * G.  */ };
++
++VECT_VAR_DECL (expected3_static, hfloat, 16, 8) []
++  = { 0x0000 /* A * H.  */,
++      0x4000 /* FP16_C (2.0f).  */,
++      0x8000 /* C * H.  */,
++      0xC000 /* FP16_C (-2.0f).  */,
++      0x0000 /* I * H.  */,
++      0x8000 /* J * H.  */,
++      0x0000 /* K * H.  */,
++      0x0000 /* L * H.  */ };
++
++void exec_vmulx_n_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VMULX_N (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE (vsrc_1, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemE);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemF);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemG);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vmulx_n_f16 (VECT_VAR (vsrc_1, float, 16, 4), elemH);
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected3_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VMULXQ_N (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE (vsrc_1, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemE);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected0_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemF);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected1_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemG);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected2_static, "");
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vmulxq_n_f16 (VECT_VAR (vsrc_1, float, 16, 8), elemH);
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected3_static, "");
++}
++
++int
++main (void)
++{
++  exec_vmulx_n_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c
+@@ -0,0 +1,50 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++#define A 13.4
++#define B __builtin_inff ()
++#define C -34.8
++#define D -__builtin_inff ()
++#define E 63.1
++#define F 0.0
++#define G -4.8
++#define H 0.0
++
++#define I 0.7
++#define J -__builtin_inff ()
++#define K 11.23
++#define L 98
++#define M 87.1
++#define N -0.0
++#define O -1.1
++#define P 7
++
++float16_t input_1[] = { A, B, C, D, I, J, K, L };
++float16_t input_2[] = { E, F, G, H, M, N, O, P };
++uint16_t expected[] = { 0x629B /* A * E.  */,
++			0x4000 /* FP16_C (2.0f).  */,
++			0x5939 /* C * G.  */,
++			0xC000 /* FP16_C (-2.0f).  */,
++			0x53A0 /* I * M.  */,
++			0x4000 /* FP16_C (2.0f).  */,
++			0xCA2C /* K * O.  */,
++			0x615C /* L * P.  */ };
++
++#define TEST_MSG "VMULXH_F16"
++#define INSN_NAME vmulxh_f16
++
++#define INPUT_1 input_1
++#define INPUT_2 input_2
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c
+@@ -0,0 +1,91 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (13.4)
++#define B FP16_C (__builtin_inff ())
++#define C FP16_C (-34.8)
++#define D FP16_C (-__builtin_inff ())
++#define E FP16_C (63.1)
++#define F FP16_C (0.0)
++#define G FP16_C (-4.8)
++#define H FP16_C (0.0)
++
++#define I FP16_C (0.7)
++#define J FP16_C (-__builtin_inff ())
++#define K FP16_C (11.23)
++#define L FP16_C (98)
++#define M FP16_C (87.1)
++#define N FP16_C (-0.0)
++#define O FP16_C (-1.1)
++#define P FP16_C (7)
++
++extern void abort ();
++
++float16_t src1[8] = { A, B, C, D, I, J, K, L };
++VECT_VAR_DECL (src2, float, 16, 4) [] = { E, F, G, H };
++VECT_VAR_DECL (src2, float, 16, 8) [] = { E, F, G, H, M, N, O, P };
++
++/* Expected results for vmulxh_lane.  */
++uint16_t expected[4] = { 0x629B /* A * E.  */,
++			 0x4000 /* FP16_C (2.0f).  */,
++			 0x5939 /* C * G.  */,
++			 0xC000 /* FP16_C (-2.0f).  */ };
++
++/* Expected results for vmulxh_lane.  */
++uint16_t expected_laneq[8] = { 0x629B /* A * E.  */,
++			       0x4000 /* FP16_C (2.0f).  */,
++			       0x5939 /* C * G.  */,
++			       0xC000 /* FP16_C (-2.0f).  */,
++			       0x53A0 /* I * M.  */,
++			       0x4000 /* FP16_C (2.0f).  */,
++			       0xCA2C /* K * O.  */,
++			       0x615C /* L * P.  */ };
++
++void exec_vmulxh_lane_f16 (void)
++{
++#define CHECK_LANE(N)\
++  ret = vmulxh_lane_f16 (src1[N], VECT_VAR (vsrc2, float, 16, 4), N);\
++  if (*(uint16_t *) &ret != expected[N])\
++    abort ();
++
++  DECL_VARIABLE(vsrc2, float, 16, 4);
++  VLOAD (vsrc2, src2, , float, f, 16, 4);
++  float16_t ret;
++
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++
++#undef CHECK_LANE
++#define CHECK_LANE(N)\
++  ret = vmulxh_laneq_f16 (src1[N], VECT_VAR (vsrc2, float, 16, 8), N);\
++  if (*(uint16_t *) &ret != expected_laneq[N])\
++    abort ();
++
++  DECL_VARIABLE(vsrc2, float, 16, 8);
++  VLOAD (vsrc2, src2, q, float, f, 16, 8);
++
++  CHECK_LANE(0)
++  CHECK_LANE(1)
++  CHECK_LANE(2)
++  CHECK_LANE(3)
++  CHECK_LANE(4)
++  CHECK_LANE(5)
++  CHECK_LANE(6)
++  CHECK_LANE(7)
++}
++
++int
++main (void)
++{
++  exec_vmulxh_lane_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmvn.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmvn.c
+@@ -120,14 +120,14 @@ FNNAME (INSN_NAME)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vneg.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vneg.c
+@@ -21,24 +21,53 @@ VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd };
+ /* Expected results for float32 variants. Needs to be separated since
+    the generic test function does not test floating-point
+    versions.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_float16, hfloat, 16, 4) [] = { 0xc09a, 0xc09a,
++						      0xc09a, 0xc09a };
++VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0xc2cd, 0xc2cd,
++						      0xc2cd, 0xc2cd,
++						      0xc2cd, 0xc2cd,
++						      0xc2cd, 0xc2cd };
++#endif
+ VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0xc0133333, 0xc0133333 };
+ VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0xc059999a, 0xc059999a,
+ 						   0xc059999a, 0xc059999a };
+ 
+ void exec_vneg_f32(void)
+ {
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+   DECL_VARIABLE(vector_res, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 2.3f);
++  VDUP(vector, q, float, f, 16, 8, 3.4f);
++#endif
+   VDUP(vector, , float, f, 32, 2, 2.3f);
+   VDUP(vector, q, float, f, 32, 4, 3.4f);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_UNARY_OP(INSN_NAME, , float, f, 16, 4);
++  TEST_UNARY_OP(INSN_NAME, q, float, f, 16, 8);
++#endif
+   TEST_UNARY_OP(INSN_NAME, , float, f, 32, 2);
+   TEST_UNARY_OP(INSN_NAME, q, float, f, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_float16, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, "");
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c
+@@ -0,0 +1,39 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++uint16_t expected[] =
++{
++  0x8000 /* -0.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc000 /* -2.000000 */,
++  0xc233 /* -3.099609 */,
++  0xcd00 /* -20.000000 */,
++  0xb666 /* -0.399902 */,
++  0x409a /* 2.300781 */,
++  0xbd52 /* -1.330078 */,
++  0x479a /* 7.601562 */,
++  0xb4f6 /* -0.310059 */,
++  0xb55d /* -0.335205 */,
++  0xb800 /* -0.500000 */,
++  0xbc00 /* -1.000000 */,
++  0xca91 /* -13.132812 */,
++  0x464d /* 6.300781 */,
++  0xcd00 /* -20.000000 */,
++  0xfc00 /* -inf */,
++  0x7c00 /* inf */
++};
++
++#define TEST_MSG "VNEGH_F16"
++#define INSN_NAME vnegh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
+@@ -21,6 +21,9 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector, uint, 8, 8);
+   DECL_VARIABLE(vector, uint, 16, 4);
+   DECL_VARIABLE(vector, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+ 
+   DECL_VARIABLE(vector_res, int, 8, 8);
+@@ -29,6 +32,9 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VARIABLE(vector_res, uint, 8, 8);
+   DECL_VARIABLE(vector_res, uint, 16, 4);
+   DECL_VARIABLE(vector_res, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+ 
+   clean_results ();
+@@ -40,6 +46,9 @@ void FNNAME (INSN_NAME) (void)
+   VLOAD(vector, buffer, , uint, u, 8, 8);
+   VLOAD(vector, buffer, , uint, u, 16, 4);
+   VLOAD(vector, buffer, , uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+ 
+   /* Apply a binary operator named INSN_NAME.  */
+@@ -49,14 +58,20 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VPXXX(INSN_NAME, uint, u, 8, 8);
+   TEST_VPXXX(INSN_NAME, uint, u, 16, 4);
+   TEST_VPXXX(INSN_NAME, uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VPXXX(INSN_NAME, float, f, 16, 4);
++#endif
+   TEST_VPXXX(INSN_NAME, float, f, 32, 2);
+ 
+-  CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
+-  CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
+-  CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
++  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, "");
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+ }
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
+@@ -14,6 +14,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
+ 					0xe1, 0xe5, 0xe9, 0xed };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe1, 0xffffffe1 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcfc0, 0xcec0, 0xcfc0, 0xcec0 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1f80000, 0xc1f80000 };
+ 
+ #include "vpXXX.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
+@@ -15,6 +15,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
+ 					0xf1, 0xf3, 0xf5, 0xf7 };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcb80, 0xca80, 0xcb80, 0xca80 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
+ 
+ #include "vpXXX.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
+@@ -15,6 +15,9 @@ VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
+ 					0xf0, 0xf2, 0xf4, 0xf6 };
+ VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb00, 0xcc00, 0xcb00 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 };
+ 
+ #include "vpXXX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c
+@@ -0,0 +1,114 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (123.4)
++#define B FP16_C (__builtin_nanf ("")) /* NaN */
++#define C FP16_C (-34.8)
++#define D FP16_C (1024)
++#define E FP16_C (663.1)
++#define F FP16_C (169.1)
++#define G FP16_C (-4.8)
++#define H FP16_C (-__builtin_nanf ("")) /* NaN */
++
++#define I FP16_C (0.7)
++#define J FP16_C (-78)
++#define K FP16_C (101.23)
++#define L FP16_C (-1098)
++#define M FP16_C (870.1)
++#define N FP16_C (-8781)
++#define O FP16_C (__builtin_inff ()) /* +Inf */
++#define P FP16_C (-__builtin_inff ()) /* -Inf */
++
++
++/* Expected results for vpminnm.  */
++VECT_VAR_DECL (expected_min_static, hfloat, 16, 4) []
++  = { 0x57B6 /* A.  */, 0xD05A /* C.  */, 0x5949 /* F.  */, 0xC4CD /* G.  */ };
++
++VECT_VAR_DECL (expected_min_static, hfloat, 16, 8) []
++  = { 0x57B6 /* A.  */, 0xD05A /* C.  */, 0xD4E0 /* J.  */, 0xE44A /* L.  */,
++      0x5949 /* F.  */, 0xC4CD /* G.  */, 0xF04A /* N.  */, 0xFC00 /* P.  */ };
++
++/* expected_max results for vpmaxnm.  */
++VECT_VAR_DECL (expected_max_static, hfloat, 16, 4) []
++  = { 0x57B6 /* A.  */, 0x6400 /* D.  */, 0x612E /* E.  */, 0xC4CD /* G.  */ };
++
++VECT_VAR_DECL (expected_max_static, hfloat, 16, 8) []
++  = { 0x57B6 /* A.  */, 0x6400 /* D.  */, 0x399A /* I.  */, 0x5654 /* K.  */,
++      0x612E /* E.  */, 0xC4CD /* G.  */, 0x62CC /* M.  */, 0x7C00 /* O.  */ };
++
++void exec_vpminmaxnm_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VPMINNM (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 4);
++  DECL_VARIABLE(vsrc_2, float, 16, 4);
++  VECT_VAR_DECL (buf_src_1, float, 16, 4) [] = {A, B, C, D};
++  VECT_VAR_DECL (buf_src_2, float, 16, 4) [] = {E, F, G, H};
++  VLOAD (vsrc_1, buf_src_1, , float, f, 16, 4);
++  VLOAD (vsrc_2, buf_src_2, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vpminnm_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		   VECT_VAR (vsrc_2, float, 16, 4));
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_min_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VPMINNMQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc_1, float, 16, 8);
++  DECL_VARIABLE(vsrc_2, float, 16, 8);
++  VECT_VAR_DECL (buf_src_1, float, 16, 8) [] = {A, B, C, D, I, J, K, L};
++  VECT_VAR_DECL (buf_src_2, float, 16, 8) [] = {E, F, G, H, M, N, O, P};
++  VLOAD (vsrc_1, buf_src_1, q, float, f, 16, 8);
++  VLOAD (vsrc_2, buf_src_2, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vpminnmq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		    VECT_VAR (vsrc_2, float, 16, 8));
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_min_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VPMAXNM (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 4)
++    = vpmaxnm_f16 (VECT_VAR (vsrc_1, float, 16, 4),
++		   VECT_VAR (vsrc_2, float, 16, 4));
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_max_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VPMAXNMQ (FP16)"
++  clean_results ();
++
++  VECT_VAR (vector_res, float, 16, 8)
++    = vpmaxnmq_f16 (VECT_VAR (vsrc_1, float, 16, 8),
++		    VECT_VAR (vsrc_2, float, 16, 8));
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_max_static, "");
++}
++
++int
++main (void)
++{
++  exec_vpminmaxnm_f16 ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqabs.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqabs.c
+@@ -90,9 +90,9 @@ void vqabs_extra()
+   TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 32, 4, expected_cumulative_sat_min_neg, MSG);
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 16, 4, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 32, 2, PRIx8, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_min_neg, MSG);
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 16, 8, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 32, 4, PRIx8, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_min_neg, MSG);
+ }
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull.c
+@@ -63,8 +63,8 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VQDMULL(int, s, 16, 32, 4, expected_cumulative_sat, "");
+   TEST_VQDMULL(int, s, 32, 64, 2, expected_cumulative_sat, "");
+ 
+-  CHECK (TEST_MSG, int, 32, 4, PRIx16, expected, "");
+-  CHECK (TEST_MSG, int, 64, 2, PRIx32, expected, "");
++  CHECK (TEST_MSG, int, 32, 4, PRIx32, expected, "");
++  CHECK (TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ 
+   VDUP(vector, , int, s, 16, 4, 0x8000);
+   VDUP(vector2, , int, s, 16, 4, 0x8000);
+@@ -75,8 +75,8 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VQDMULL(int, s, 16, 32, 4, expected_cumulative_sat2, TEST_MSG2);
+   TEST_VQDMULL(int, s, 32, 64, 2, expected_cumulative_sat2, TEST_MSG2);
+ 
+-  CHECK (TEST_MSG, int, 32, 4, PRIx16, expected2, TEST_MSG2);
+-  CHECK (TEST_MSG, int, 64, 2, PRIx32, expected2, TEST_MSG2);
++  CHECK (TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
++  CHECK (TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2);
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqneg.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqneg.c
+@@ -90,9 +90,9 @@ void vqneg_extra()
+   TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 32, 4, expected_cumulative_sat_min_neg, MSG);
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 16, 4, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 32, 2, PRIx8, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_min_neg, MSG);
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 16, 8, PRIx8, expected_min_neg, MSG);
+-  CHECK(TEST_MSG, int, 32, 4, PRIx8, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_min_neg, MSG);
++  CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_min_neg, MSG);
+ }
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqtbX.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqtbX.c
+@@ -318,13 +318,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbl1, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbl1, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl1, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl1, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBL1Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbl1q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbl1q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl1q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl1q, "");
+ 
+   /* Check vqtbl2.  */
+   clean_results ();
+@@ -334,13 +334,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbl2, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbl2, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl2, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl2, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBL2Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbl2q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbl2q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl2q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl2q, "");
+ 
+   /* Check vqtbl3.  */
+   clean_results ();
+@@ -350,13 +350,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbl3, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbl3, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl3, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl3, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBL3Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbl3q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbl3q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl3q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl3q, "");
+ 
+   /* Check vqtbl4.  */
+   clean_results ();
+@@ -366,13 +366,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbl4, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbl4, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl4, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbl4, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBL4Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbl4q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbl4q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl4q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbl4q, "");
+ 
+ 
+   /* Now test VQTBX.  */
+@@ -455,13 +455,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbx1, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbx1, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx1, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx1, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBX1Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbx1q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbx1q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx1q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx1q, "");
+ 
+   /* Check vqtbx2.  */
+   clean_results ();
+@@ -471,13 +471,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbx2, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbx2, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx2, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx2, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBX2Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbx2q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbx2q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx2q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx2q, "");
+ 
+   /* Check vqtbx3.  */
+   clean_results ();
+@@ -487,13 +487,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbx3, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbx3, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx3, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx3, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBX3Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbx3q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbx3q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx3q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx3q, "");
+ 
+   /* Check vqtbx4.  */
+   clean_results ();
+@@ -503,13 +503,13 @@ void exec_vqtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vqtbx4, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vqtbx4, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx4, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vqtbx4, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VQTBX4Q"
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vqtbx4q, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vqtbx4q, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx4q, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vqtbx4q, "");
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c
+@@ -7,6 +7,14 @@
+ VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000,
+ 						  0xbf000000, 0xbf000000 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834,
++						       0x3834, 0x3834 };
++VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018,
++						       0x2018, 0x2018,
++						       0x2018, 0x2018,
++						       0x2018, 0x2018 };
++#endif
+ VECT_VAR_DECL(expected_positive,hfloat,32,2) [] = { 0x3f068000, 0x3f068000 };
+ VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000,
+ 						    0x3c030000, 0x3c030000 };
+@@ -15,24 +23,56 @@ VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000,
+ VECT_VAR_DECL(expected_negative,uint,32,2) [] = { 0x80000000, 0x80000000 };
+ VECT_VAR_DECL(expected_negative,uint,32,4) [] = { 0xee800000, 0xee800000,
+ 						  0xee800000, 0xee800000 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_negative, hfloat, 16, 4) [] = { 0xae64, 0xae64,
++						       0xae64, 0xae64 };
++VECT_VAR_DECL(expected_negative, hfloat, 16, 8) [] = { 0xa018, 0xa018,
++						       0xa018, 0xa018,
++						       0xa018, 0xa018,
++						       0xa018, 0xa018 };
++#endif
+ VECT_VAR_DECL(expected_negative,hfloat,32,2) [] = { 0xbdcc8000, 0xbdcc8000 };
+ VECT_VAR_DECL(expected_negative,hfloat,32,4) [] = { 0xbc030000, 0xbc030000,
+ 						    0xbc030000, 0xbc030000 };
+ 
+ /* Expected results with FP special values (NaN, infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 4) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						  0x0, 0x0, 0x0, 0x0 };
++#endif
+ VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results with FP special values (zero, large value).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 4) [] = { 0x7c00, 0x7c00,
++						  0x7c00, 0x7c00 };
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
++						  0x0, 0x0, 0x0, 0x0 };
++#endif
+ VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0x7f800000, 0x7f800000 };
+ VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results with FP special values (-0, -infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp3, hfloat, 16, 4) [] = { 0xfc00, 0xfc00,
++						  0xfc00, 0xfc00};
++VECT_VAR_DECL(expected_fp3, hfloat, 16, 8) [] = { 0x8000, 0x8000,
++						  0x8000, 0x8000,
++						  0x8000, 0x8000,
++						  0x8000, 0x8000 };
++#endif
+ VECT_VAR_DECL(expected_fp3,hfloat,32,2) [] = { 0xff800000, 0xff800000 };
+ VECT_VAR_DECL(expected_fp3,hfloat,32,4) [] = { 0x80000000, 0x80000000,
+ 					       0x80000000, 0x80000000 };
+ 
+ /* Expected results with FP special large negative value.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp4, hfloat, 16, 4) [] = { 0x8000, 0x8000,
++						  0x8000, 0x8000 };
++#endif
+ VECT_VAR_DECL(expected_fp4,hfloat,32,2) [] = { 0x80000000, 0x80000000 };
+ 
+ #define TEST_MSG "VRECPE/VRECPEQ"
+@@ -50,11 +90,19 @@ void exec_vrecpe(void)
+   /* No need for 64 bits variants.  */
+   DECL_VARIABLE(vector, uint, 32, 2);
+   DECL_VARIABLE(vector, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
+   DECL_VARIABLE(vector_res, uint, 32, 2);
+   DECL_VARIABLE(vector_res, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+   DECL_VARIABLE(vector_res, float, 32, 4);
+ 
+@@ -62,88 +110,165 @@ void exec_vrecpe(void)
+ 
+   /* Choose init value arbitrarily, positive.  */
+   VDUP(vector, , uint, u, 32, 2, 0x12345678);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 1.9f);
++#endif
+   VDUP(vector, , float, f, 32, 2, 1.9f);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, q, float, f, 16, 8, 125.0f);
++#endif
+   VDUP(vector, q, uint, u, 32, 4, 0xABCDEF10);
+   VDUP(vector, q, float, f, 32, 4, 125.0f);
+ 
+   /* Apply the operator.  */
+   TEST_VRECPE(, uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(, float, f, 16, 4);
++#endif
+   TEST_VRECPE(, float, f, 32, 2);
+   TEST_VRECPE(q, uint, u, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(q, float, f, 16, 8);
++#endif
+   TEST_VRECPE(q, float, f, 32, 4);
+ 
+ #define CMT " (positive input)"
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_positive, CMT);
+ 
+   /* Choose init value arbitrarily,negative.  */
+   VDUP(vector, , uint, u, 32, 2, 0xFFFFFFFF);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, -10.0f);
++#endif
+   VDUP(vector, , float, f, 32, 2, -10.0f);
+   VDUP(vector, q, uint, u, 32, 4, 0x89081234);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, q, float, f, 16, 8, -125.0f);
++#endif
+   VDUP(vector, q, float, f, 32, 4, -125.0f);
+ 
+   /* Apply the operator.  */
+   TEST_VRECPE(, uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(, float, f, 16, 4);
++#endif
+   TEST_VRECPE(, float, f, 32, 2);
+   TEST_VRECPE(q, uint, u, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(q, float, f, 16, 8);
++#endif
+   TEST_VRECPE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " (negative input)"
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_negative, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_negative, CMT);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_negative, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_negative, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_negative, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_negative, CMT);
+ 
+   /* Test FP variants with special input values (NaN, infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, NAN);
++  VDUP(vector, q, float, f, 16, 8, HUGE_VALF);
++#endif
+   VDUP(vector, , float, f, 32, 2, NAN);
+   VDUP(vector, q, float, f, 32, 4, HUGE_VALF);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(, float, f, 16, 4);
++  TEST_VRECPE(q, float, f, 16, 8);
++#endif
+   TEST_VRECPE(, float, f, 32, 2);
+   TEST_VRECPE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (NaN, infinity)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp1, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT);
+ 
+   /* Test FP variants with special input values (zero, large value).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 0.0f);
++  VDUP(vector, q, float, f, 16, 8, 8.97229e37f /*9.0e37f*/);
++#endif
+   VDUP(vector, , float, f, 32, 2, 0.0f);
+   VDUP(vector, q, float, f, 32, 4, 8.97229e37f /*9.0e37f*/);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(, float, f, 16, 4);
++  TEST_VRECPE(q, float, f, 16, 8);
++#endif
+   TEST_VRECPE(, float, f, 32, 2);
+   TEST_VRECPE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (zero, large value)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp2, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp2, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT);
+ 
+   /* Test FP variants with special input values (-0, -infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, -0.0f);
++  VDUP(vector, q, float, f, 16, 8, -HUGE_VALF);
++#endif
+   VDUP(vector, , float, f, 32, 2, -0.0f);
+   VDUP(vector, q, float, f, 32, 4, -HUGE_VALF);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(, float, f, 16, 4);
++  TEST_VRECPE(q, float, f, 16, 8);
++#endif
+   TEST_VRECPE(, float, f, 32, 2);
+   TEST_VRECPE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (-0, -infinity)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp3, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp3, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp3, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp3, CMT);
+ 
+   /* Test FP variants with special input values (large negative value).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, -9.0e37f);
++#endif
+   VDUP(vector, , float, f, 32, 2, -9.0e37f);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPE(, float, f, 16, 4);
++#endif
+   TEST_VRECPE(, float, f, 32, 2);
+ 
+ #undef CMT
+ #define CMT " FP special (large negative value)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp4, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp4, CMT);
+ }
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++#define A 123.4
++#define B 567.8
++#define C 34.8
++#define D 1024
++#define E 663.1
++#define F 144.0
++#define G 4.8
++#define H 77
++
++#define RECP_A 0x2028 /* 1/A.  */
++#define RECP_B 0x1734 /* 1/B.  */
++#define RECP_C 0x275C /* 1/C.  */
++#define RECP_D 0x13FC /* 1/D.  */
++#define RECP_E 0x162C /* 1/E.  */
++#define RECP_F 0x1F18 /* 1/F.  */
++#define RECP_G 0x32A8 /* 1/G.  */
++#define RECP_H 0x22A4 /* 1/H.  */
++
++float16_t input[] = { A, B, C, D, E, F, G, H };
++uint16_t expected[] = { RECP_A, RECP_B, RECP_C, RECP_D,
++		        RECP_E, RECP_F, RECP_G, RECP_H };
++
++#define TEST_MSG "VRECPEH_F16"
++#define INSN_NAME vrecpeh_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c
+@@ -4,22 +4,51 @@
+ #include <math.h>
+ 
+ /* Expected results with positive input.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xd70c, 0xd70c, 0xd70c, 0xd70c };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcedc, 0xcedc, 0xcedc, 0xcedc,
++					      0xcedc, 0xcedc, 0xcedc, 0xcedc };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc2e19eb7, 0xc2e19eb7 };
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1db851f, 0xc1db851f,
+ 					   0xc1db851f, 0xc1db851f };
+ 
+ /* Expected results with FP special values (NaN).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 4) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++#endif
+ VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 					       0x7fc00000, 0x7fc00000 };
+ 
+ /* Expected results with FP special values (infinity, 0) and normal
+    values.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 4) [] = { 0xfc00, 0xfc00,
++						  0xfc00, 0xfc00 };
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 8) [] = { 0x4000, 0x4000,
++						  0x4000, 0x4000,
++						  0x4000, 0x4000,
++						  0x4000, 0x4000 };
++#endif
+ VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0xff800000, 0xff800000 };
+ VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x40000000, 0x40000000,
+ 					       0x40000000, 0x40000000 };
+ 
+ /* Expected results with FP special values (infinity, 0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp3, hfloat, 16, 4) [] = { 0x4000, 0x4000,
++						  0x4000, 0x4000 };
++VECT_VAR_DECL(expected_fp3, hfloat, 16, 8) [] = { 0x4000, 0x4000,
++						  0x4000, 0x4000,
++						  0x4000, 0x4000,
++						  0x4000, 0x4000 };
++#endif
+ VECT_VAR_DECL(expected_fp3,hfloat,32,2) [] = { 0x40000000, 0x40000000 };
+ VECT_VAR_DECL(expected_fp3,hfloat,32,4) [] = { 0x40000000, 0x40000000,
+ 					       0x40000000, 0x40000000 };
+@@ -38,74 +67,143 @@ void exec_vrecps(void)
+ 		    VECT_VAR(vector_res, T1, W, N))
+ 
+   /* No need for integer variants.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector2, float, 32, 2);
+   DECL_VARIABLE(vector2, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+   DECL_VARIABLE(vector_res, float, 32, 4);
+ 
+   clean_results ();
+ 
+   /* Choose init value arbitrarily.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 12.9f);
++  VDUP(vector, q, float, f, 16, 8, 9.2f);
++#endif
+   VDUP(vector, , float, f, 32, 2, 12.9f);
+   VDUP(vector, q, float, f, 32, 4, 9.2f);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 8.9f);
++  VDUP(vector2, q, float, f, 16, 8, 3.2f);
++#endif
+   VDUP(vector2, , float, f, 32, 2, 8.9f);
+   VDUP(vector2, q, float, f, 32, 4, 3.2f);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPS(, float, f, 16, 4);
++  TEST_VRECPS(q, float, f, 16, 8);
++#endif
+   TEST_VRECPS(, float, f, 32, 2);
+   TEST_VRECPS(q, float, f, 32, 4);
+ 
+ #define CMT " (positive input)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, CMT);
+ 
+ 
+   /* Test FP variants with special input values (NaN).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, NAN);
++  VDUP(vector2, q, float, f, 16, 8, NAN);
++#endif
+   VDUP(vector, , float, f, 32, 2, NAN);
+   VDUP(vector2, q, float, f, 32, 4, NAN);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPS(, float, f, 16, 4);
++  TEST_VRECPS(q, float, f, 16, 8);
++#endif
+   TEST_VRECPS(, float, f, 32, 2);
+   TEST_VRECPS(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (NaN)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp1, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT);
+ 
+ 
+   /* Test FP variants with special input values (infinity, 0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, HUGE_VALF);
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++  VDUP(vector2, q, float, f, 16, 8, 3.2f); /* Restore a normal value.  */
++#endif
+   VDUP(vector, , float, f, 32, 2, HUGE_VALF);
+   VDUP(vector, q, float, f, 32, 4, 0.0f);
+   VDUP(vector2, q, float, f, 32, 4, 3.2f); /* Restore a normal value.  */
+ 
++
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPS(, float, f, 16, 4);
++  TEST_VRECPS(q, float, f, 16, 8);
++#endif
+   TEST_VRECPS(, float, f, 32, 2);
+   TEST_VRECPS(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (infinity, 0) and normal value"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp2, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp2, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT);
+ 
+ 
+   /* Test FP variants with only special input values (infinity, 0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, HUGE_VALF);
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++  VDUP(vector2, , float, f, 16, 4, 0.0f);
++  VDUP(vector2, q, float, f, 16, 8, HUGE_VALF);
++#endif
+   VDUP(vector, , float, f, 32, 2, HUGE_VALF);
+   VDUP(vector, q, float, f, 32, 4, 0.0f);
+   VDUP(vector2, , float, f, 32, 2, 0.0f);
+   VDUP(vector2, q, float, f, 32, 4, HUGE_VALF);
+ 
++
+   /* Apply the operator */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRECPS(, float, f, 16, 4);
++  TEST_VRECPS(q, float, f, 16, 8);
++#endif
+   TEST_VRECPS(, float, f, 32, 2);
+   TEST_VRECPS(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (infinity, 0)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp3, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp3, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp3, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp3, CMT);
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c
+@@ -0,0 +1,50 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++#define A 12.4
++#define B -5.8
++#define C -3.8
++#define D 10
++#define E 66.1
++#define F 16.1
++#define G -4.8
++#define H -77
++
++#define I 0.7
++#define J -78
++#define K 10.23
++#define L 98
++#define M 87
++#define N -87.81
++#define O -1.1
++#define P 47.8
++
++float16_t input_1[] = { A, B, C, D, I, J, K, L };
++float16_t input_2[] = { E, F, G, H, M, N, O, P };
++uint16_t expected[] = { 0xE264 /* 2.0f - A * E.  */,
++			0x55F6 /* 2.0f - B * F.  */,
++			0xCC10 /* 2.0f - C * G.  */,
++			0x6208 /* 2.0f - D * H.  */,
++			0xD35D /* 2.0f - I * M.  */,
++			0xEEB0 /* 2.0f - J * N.  */,
++			0x4A9F /* 2.0f - K * O.  */,
++			0xEC93 /* 2.0f - L * P.  */ };
++
++#define TEST_MSG "VRECPSH_F16"
++#define INSN_NAME vrecpsh_f16
++
++#define INPUT_1 input_1
++#define INPUT_2 input_2
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c
+@@ -0,0 +1,32 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++
++float16_t input[] = { 123.4, 567.8, 34.8, 1024, 663.1, 144.0, 4.8, 77 };
++/*  Expected results are calculated by:
++  for (index = 0; index < 8; index++)
++    {
++      uint16_t src_cast = * (uint16_t *) &src[index];
++      * (uint16_t *) &expected[index] =
++	(src_cast & 0x8000) | (~src_cast & 0x7C00);
++    }  */
++uint16_t expected[8] = { 0x2800, 0x1C00, 0x2C00, 0x1800,
++			 0x1C00, 0x2400, 0x3800, 0x2800 };
++
++#define TEST_MSG "VRECPXH_F16"
++#define INSN_NAME vrecpxh_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
+@@ -21,6 +21,8 @@ VECT_VAR_DECL(expected_s8_8,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					    0xf4, 0xf5, 0xf6, 0xf7 };
+ VECT_VAR_DECL(expected_s8_9,int,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 					    0xf2, 0xff, 0xf3, 0xff };
++VECT_VAR_DECL(expected_s8_10,int,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
++					     0x00, 0xcb, 0x80, 0xca };
+ 
+ /* Expected results for vreinterpret_s16_xx.  */
+ VECT_VAR_DECL(expected_s16_1,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+@@ -32,6 +34,7 @@ VECT_VAR_DECL(expected_s16_6,int,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+ VECT_VAR_DECL(expected_s16_7,int,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+ VECT_VAR_DECL(expected_s16_8,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+ VECT_VAR_DECL(expected_s16_9,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
++VECT_VAR_DECL(expected_s16_10,int,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
+ 
+ /* Expected results for vreinterpret_s32_xx.  */
+ VECT_VAR_DECL(expected_s32_1,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+@@ -43,6 +46,7 @@ VECT_VAR_DECL(expected_s32_6,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+ VECT_VAR_DECL(expected_s32_7,int,32,2) [] = { 0xfffffff0, 0xffffffff };
+ VECT_VAR_DECL(expected_s32_8,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+ VECT_VAR_DECL(expected_s32_9,int,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
++VECT_VAR_DECL(expected_s32_10,int,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
+ 
+ /* Expected results for vreinterpret_s64_xx.  */
+ VECT_VAR_DECL(expected_s64_1,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+@@ -54,6 +58,7 @@ VECT_VAR_DECL(expected_s64_6,int,64,1) [] = { 0xfffffff1fffffff0 };
+ VECT_VAR_DECL(expected_s64_7,int,64,1) [] = { 0xfffffffffffffff0 };
+ VECT_VAR_DECL(expected_s64_8,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+ VECT_VAR_DECL(expected_s64_9,int,64,1) [] = { 0xfff3fff2fff1fff0 };
++VECT_VAR_DECL(expected_s64_10,int,64,1) [] = { 0xca80cb00cb80cc00 };
+ 
+ /* Expected results for vreinterpret_u8_xx.  */
+ VECT_VAR_DECL(expected_u8_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+@@ -74,6 +79,8 @@ VECT_VAR_DECL(expected_u8_8,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					     0xf4, 0xf5, 0xf6, 0xf7 };
+ VECT_VAR_DECL(expected_u8_9,uint,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 					     0xf2, 0xff, 0xf3, 0xff };
++VECT_VAR_DECL(expected_u8_10,uint,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
++					      0x00, 0xcb, 0x80, 0xca };
+ 
+ /* Expected results for vreinterpret_u16_xx.  */
+ VECT_VAR_DECL(expected_u16_1,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+@@ -85,6 +92,7 @@ VECT_VAR_DECL(expected_u16_6,uint,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+ VECT_VAR_DECL(expected_u16_7,uint,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+ VECT_VAR_DECL(expected_u16_8,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+ VECT_VAR_DECL(expected_u16_9,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
++VECT_VAR_DECL(expected_u16_10,uint,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
+ 
+ /* Expected results for vreinterpret_u32_xx.  */
+ VECT_VAR_DECL(expected_u32_1,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+@@ -96,6 +104,7 @@ VECT_VAR_DECL(expected_u32_6,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+ VECT_VAR_DECL(expected_u32_7,uint,32,2) [] = { 0xfffffff0, 0xffffffff };
+ VECT_VAR_DECL(expected_u32_8,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+ VECT_VAR_DECL(expected_u32_9,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
++VECT_VAR_DECL(expected_u32_10,uint,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
+ 
+ /* Expected results for vreinterpret_u64_xx.  */
+ VECT_VAR_DECL(expected_u64_1,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+@@ -107,6 +116,7 @@ VECT_VAR_DECL(expected_u64_6,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
+ VECT_VAR_DECL(expected_u64_7,uint,64,1) [] = { 0xfffffff1fffffff0 };
+ VECT_VAR_DECL(expected_u64_8,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
+ VECT_VAR_DECL(expected_u64_9,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
++VECT_VAR_DECL(expected_u64_10,uint,64,1) [] = { 0xca80cb00cb80cc00 };
+ 
+ /* Expected results for vreinterpret_p8_xx.  */
+ VECT_VAR_DECL(expected_p8_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+@@ -127,6 +137,8 @@ VECT_VAR_DECL(expected_p8_8,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
+ 					     0xff, 0xff, 0xff, 0xff };
+ VECT_VAR_DECL(expected_p8_9,poly,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 					     0xf2, 0xff, 0xf3, 0xff };
++VECT_VAR_DECL(expected_p8_10,poly,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
++					      0x00, 0xcb, 0x80, 0xca };
+ 
+ /* Expected results for vreinterpret_p16_xx.  */
+ VECT_VAR_DECL(expected_p16_1,poly,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
+@@ -138,6 +150,7 @@ VECT_VAR_DECL(expected_p16_6,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+ VECT_VAR_DECL(expected_p16_7,poly,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
+ VECT_VAR_DECL(expected_p16_8,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
+ VECT_VAR_DECL(expected_p16_9,poly,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
++VECT_VAR_DECL(expected_p16_10,poly,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
+ 
+ /* Expected results for vreinterpretq_s8_xx.  */
+ VECT_VAR_DECL(expected_q_s8_1,int,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+@@ -176,6 +189,10 @@ VECT_VAR_DECL(expected_q_s8_9,int,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 					       0xf2, 0xff, 0xf3, 0xff,
+ 					       0xf4, 0xff, 0xf5, 0xff,
+ 					       0xf6, 0xff, 0xf7, 0xff };
++VECT_VAR_DECL(expected_q_s8_10,int,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
++						0x00, 0xcb, 0x80, 0xca,
++						0x00, 0xca, 0x80, 0xc9,
++						0x00, 0xc9, 0x80, 0xc8 };
+ 
+ /* Expected results for vreinterpretq_s16_xx.  */
+ VECT_VAR_DECL(expected_q_s16_1,int,16,8) [] = { 0xf1f0, 0xf3f2,
+@@ -214,6 +231,10 @@ VECT_VAR_DECL(expected_q_s16_9,int,16,8) [] = { 0xfff0, 0xfff1,
+ 						0xfff2, 0xfff3,
+ 						0xfff4, 0xfff5,
+ 						0xfff6, 0xfff7 };
++VECT_VAR_DECL(expected_q_s16_10,int,16,8) [] = { 0xcc00, 0xcb80,
++						 0xcb00, 0xca80,
++						 0xca00, 0xc980,
++						 0xc900, 0xc880 };
+ 
+ /* Expected results for vreinterpretq_s32_xx.  */
+ VECT_VAR_DECL(expected_q_s32_1,int,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+@@ -234,6 +255,8 @@ VECT_VAR_DECL(expected_q_s32_8,int,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 						0xfbfaf9f8, 0xfffefdfc };
+ VECT_VAR_DECL(expected_q_s32_9,int,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 						0xfff5fff4, 0xfff7fff6 };
++VECT_VAR_DECL(expected_q_s32_10,int,32,4) [] = { 0xcb80cc00, 0xca80cb00,
++						 0xc980ca00, 0xc880c900 };
+ 
+ /* Expected results for vreinterpretq_s64_xx.  */
+ VECT_VAR_DECL(expected_q_s64_1,int,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+@@ -254,6 +277,8 @@ VECT_VAR_DECL(expected_q_s64_8,int,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+ 						0xfffefdfcfbfaf9f8 };
+ VECT_VAR_DECL(expected_q_s64_9,int,64,2) [] = { 0xfff3fff2fff1fff0,
+ 						0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(expected_q_s64_10,int,64,2) [] = { 0xca80cb00cb80cc00,
++						 0xc880c900c980ca00 };
+ 
+ /* Expected results for vreinterpretq_u8_xx.  */
+ VECT_VAR_DECL(expected_q_u8_1,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+@@ -292,6 +317,10 @@ VECT_VAR_DECL(expected_q_u8_9,uint,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
+ 						0xf2, 0xff, 0xf3, 0xff,
+ 						0xf4, 0xff, 0xf5, 0xff,
+ 						0xf6, 0xff, 0xf7, 0xff };
++VECT_VAR_DECL(expected_q_u8_10,uint,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
++						 0x00, 0xcb, 0x80, 0xca,
++						 0x00, 0xca, 0x80, 0xc9,
++						 0x00, 0xc9, 0x80, 0xc8 };
+ 
+ /* Expected results for vreinterpretq_u16_xx.  */
+ VECT_VAR_DECL(expected_q_u16_1,uint,16,8) [] = { 0xf1f0, 0xf3f2,
+@@ -330,6 +359,10 @@ VECT_VAR_DECL(expected_q_u16_9,uint,16,8) [] = { 0xfff0, 0xfff1,
+ 						 0xfff2, 0xfff3,
+ 						 0xfff4, 0xfff5,
+ 						 0xfff6, 0xfff7 };
++VECT_VAR_DECL(expected_q_u16_10,uint,16,8) [] = { 0xcc00, 0xcb80,
++						  0xcb00, 0xca80,
++						  0xca00, 0xc980,
++						  0xc900, 0xc880 };
+ 
+ /* Expected results for vreinterpretq_u32_xx.  */
+ VECT_VAR_DECL(expected_q_u32_1,uint,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+@@ -350,6 +383,8 @@ VECT_VAR_DECL(expected_q_u32_8,uint,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 						 0xfbfaf9f8, 0xfffefdfc };
+ VECT_VAR_DECL(expected_q_u32_9,uint,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 						 0xfff5fff4, 0xfff7fff6 };
++VECT_VAR_DECL(expected_q_u32_10,uint,32,4) [] = { 0xcb80cc00, 0xca80cb00,
++						  0xc980ca00, 0xc880c900 };
+ 
+ /* Expected results for vreinterpretq_u64_xx.  */
+ VECT_VAR_DECL(expected_q_u64_1,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+@@ -370,6 +405,92 @@ VECT_VAR_DECL(expected_q_u64_8,uint,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
+ 						0xfffefdfcfbfaf9f8 };
+ VECT_VAR_DECL(expected_q_u64_9,uint,64,2) [] = { 0xfff3fff2fff1fff0,
+ 						 0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(expected_q_u64_10,uint,64,2) [] = { 0xca80cb00cb80cc00,
++						  0xc880c900c980ca00 };
++
++/* Expected results for vreinterpretq_p8_xx.  */
++VECT_VAR_DECL(expected_q_p8_1,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
++						0xf4, 0xf5, 0xf6, 0xf7,
++						0xf8, 0xf9, 0xfa, 0xfb,
++						0xfc, 0xfd, 0xfe, 0xff };
++VECT_VAR_DECL(expected_q_p8_2,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
++						0xf2, 0xff, 0xf3, 0xff,
++						0xf4, 0xff, 0xf5, 0xff,
++						0xf6, 0xff, 0xf7, 0xff };
++VECT_VAR_DECL(expected_q_p8_3,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++						0xf1, 0xff, 0xff, 0xff,
++						0xf2, 0xff, 0xff, 0xff,
++						0xf3, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected_q_p8_4,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++						0xff, 0xff, 0xff, 0xff,
++						0xf1, 0xff, 0xff, 0xff,
++						0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected_q_p8_5,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
++						0xf4, 0xf5, 0xf6, 0xf7,
++						0xf8, 0xf9, 0xfa, 0xfb,
++						0xfc, 0xfd, 0xfe, 0xff };
++VECT_VAR_DECL(expected_q_p8_6,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
++						0xf2, 0xff, 0xf3, 0xff,
++						0xf4, 0xff, 0xf5, 0xff,
++						0xf6, 0xff, 0xf7, 0xff };
++VECT_VAR_DECL(expected_q_p8_7,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++						0xf1, 0xff, 0xff, 0xff,
++						0xf2, 0xff, 0xff, 0xff,
++						0xf3, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected_q_p8_8,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++						0xff, 0xff, 0xff, 0xff,
++						0xf1, 0xff, 0xff, 0xff,
++						0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected_q_p8_9,poly,8,16) [] = { 0xf0, 0xff, 0xf1, 0xff,
++						0xf2, 0xff, 0xf3, 0xff,
++						0xf4, 0xff, 0xf5, 0xff,
++						0xf6, 0xff, 0xf7, 0xff };
++VECT_VAR_DECL(expected_q_p8_10,poly,8,16) [] = { 0x00, 0xcc, 0x80, 0xcb,
++						 0x00, 0xcb, 0x80, 0xca,
++						 0x00, 0xca, 0x80, 0xc9,
++						 0x00, 0xc9, 0x80, 0xc8 };
++
++/* Expected results for vreinterpretq_p16_xx.  */
++VECT_VAR_DECL(expected_q_p16_1,poly,16,8) [] = { 0xf1f0, 0xf3f2,
++						 0xf5f4, 0xf7f6,
++						 0xf9f8, 0xfbfa,
++						 0xfdfc, 0xfffe };
++VECT_VAR_DECL(expected_q_p16_2,poly,16,8) [] = { 0xfff0, 0xfff1,
++						 0xfff2, 0xfff3,
++						 0xfff4, 0xfff5,
++						 0xfff6, 0xfff7 };
++VECT_VAR_DECL(expected_q_p16_3,poly,16,8) [] = { 0xfff0, 0xffff,
++						 0xfff1, 0xffff,
++						 0xfff2, 0xffff,
++						 0xfff3, 0xffff };
++VECT_VAR_DECL(expected_q_p16_4,poly,16,8) [] = { 0xfff0, 0xffff,
++						 0xffff, 0xffff,
++						 0xfff1, 0xffff,
++						 0xffff, 0xffff };
++VECT_VAR_DECL(expected_q_p16_5,poly,16,8) [] = { 0xf1f0, 0xf3f2,
++						 0xf5f4, 0xf7f6,
++						 0xf9f8, 0xfbfa,
++						 0xfdfc, 0xfffe };
++VECT_VAR_DECL(expected_q_p16_6,poly,16,8) [] = { 0xfff0, 0xfff1,
++						 0xfff2, 0xfff3,
++						 0xfff4, 0xfff5,
++						 0xfff6, 0xfff7 };
++VECT_VAR_DECL(expected_q_p16_7,poly,16,8) [] = { 0xfff0, 0xffff,
++						 0xfff1, 0xffff,
++						 0xfff2, 0xffff,
++						 0xfff3, 0xffff };
++VECT_VAR_DECL(expected_q_p16_8,poly,16,8) [] = { 0xfff0, 0xffff,
++						 0xffff, 0xffff,
++						 0xfff1, 0xffff,
++						 0xffff, 0xffff };
++VECT_VAR_DECL(expected_q_p16_9,poly,16,8) [] = { 0xf1f0, 0xf3f2,
++						 0xf5f4, 0xf7f6,
++						 0xf9f8, 0xfbfa,
++						 0xfdfc, 0xfffe };
++VECT_VAR_DECL(expected_q_p16_10,poly,16,8) [] = { 0xcc00, 0xcb80,
++						  0xcb00, 0xca80,
++						  0xca00, 0xc980,
++						  0xc900, 0xc880 };
+ 
+ /* Expected results for vreinterpret_f32_xx.  */
+ VECT_VAR_DECL(expected_f32_1,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+@@ -382,6 +503,7 @@ VECT_VAR_DECL(expected_f32_7,hfloat,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+ VECT_VAR_DECL(expected_f32_8,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff };
+ VECT_VAR_DECL(expected_f32_9,hfloat,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
+ VECT_VAR_DECL(expected_f32_10,hfloat,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
++VECT_VAR_DECL(expected_f32_11,hfloat,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
+ 
+ /* Expected results for vreinterpretq_f32_xx.  */
+ VECT_VAR_DECL(expected_q_f32_1,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+@@ -404,8 +526,10 @@ VECT_VAR_DECL(expected_q_f32_9,hfloat,32,4) [] = { 0xf3f2f1f0, 0xf7f6f5f4,
+ 						   0xfbfaf9f8, 0xfffefdfc };
+ VECT_VAR_DECL(expected_q_f32_10,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
+ 						    0xfff5fff4, 0xfff7fff6 };
++VECT_VAR_DECL(expected_q_f32_11,hfloat,32,4) [] = { 0xcb80cc00, 0xca80cb00,
++						    0xc980ca00, 0xc880c900 };
+ 
+-/* Expected results for vreinterpretq_xx_f32.  */
++/* Expected results for vreinterpret_xx_f32.  */
+ VECT_VAR_DECL(expected_xx_f32_1,int,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
+ 						0x0, 0x0, 0x70, 0xc1 };
+ VECT_VAR_DECL(expected_xx_f32_2,int,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
+@@ -419,6 +543,7 @@ VECT_VAR_DECL(expected_xx_f32_8,uint,64,1) [] = { 0xc1700000c1800000 };
+ VECT_VAR_DECL(expected_xx_f32_9,poly,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
+ 						 0x0, 0x0, 0x70, 0xc1 };
+ VECT_VAR_DECL(expected_xx_f32_10,poly,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
++VECT_VAR_DECL(expected_xx_f32_11,hfloat,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
+ 
+ /* Expected results for vreinterpretq_xx_f32.  */
+ VECT_VAR_DECL(expected_q_xx_f32_1,int,8,16) [] = { 0x0, 0x0, 0x80, 0xc1,
+@@ -447,6 +572,62 @@ VECT_VAR_DECL(expected_q_xx_f32_9,poly,8,16) [] = { 0x0, 0x0, 0x80, 0xc1,
+ 						    0x0, 0x0, 0x50, 0xc1 };
+ VECT_VAR_DECL(expected_q_xx_f32_10,poly,16,8) [] = { 0x0, 0xc180, 0x0, 0xc170,
+ 						     0x0, 0xc160, 0x0, 0xc150 };
++VECT_VAR_DECL(expected_q_xx_f32_11,hfloat,16,8) [] = { 0x0, 0xc180, 0x0, 0xc170,
++						      0x0, 0xc160, 0x0, 0xc150 };
++
++/* Expected results for vreinterpret_f16_xx.  */
++VECT_VAR_DECL(expected_f16_1,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
++VECT_VAR_DECL(expected_f16_2,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
++VECT_VAR_DECL(expected_f16_3,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
++VECT_VAR_DECL(expected_f16_4,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL(expected_f16_5,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
++VECT_VAR_DECL(expected_f16_6,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
++VECT_VAR_DECL(expected_f16_7,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xfff1, 0xffff };
++VECT_VAR_DECL(expected_f16_8,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL(expected_f16_9,hfloat,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
++VECT_VAR_DECL(expected_f16_10,hfloat,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
++
++/* Expected results for vreinterpretq_f16_xx.  */
++VECT_VAR_DECL(expected_q_f16_1,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
++						   0xf5f4, 0xf7f6,
++						   0xf9f8, 0xfbfa,
++						   0xfdfc, 0xfffe };
++VECT_VAR_DECL(expected_q_f16_2,hfloat,16,8) [] = { 0xfff0, 0xfff1,
++						   0xfff2, 0xfff3,
++						   0xfff4, 0xfff5,
++						   0xfff6, 0xfff7 };
++VECT_VAR_DECL(expected_q_f16_3,hfloat,16,8) [] = { 0xfff0, 0xffff,
++						   0xfff1, 0xffff,
++						   0xfff2, 0xffff,
++						   0xfff3, 0xffff };
++VECT_VAR_DECL(expected_q_f16_4,hfloat,16,8) [] = { 0xfff0, 0xffff,
++						   0xffff, 0xffff,
++						   0xfff1, 0xffff,
++						   0xffff, 0xffff };
++VECT_VAR_DECL(expected_q_f16_5,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
++						   0xf5f4, 0xf7f6,
++						   0xf9f8, 0xfbfa,
++						   0xfdfc, 0xfffe };
++VECT_VAR_DECL(expected_q_f16_6,hfloat,16,8) [] = { 0xfff0, 0xfff1,
++						   0xfff2, 0xfff3,
++						   0xfff4, 0xfff5,
++						   0xfff6, 0xfff7 };
++VECT_VAR_DECL(expected_q_f16_7,hfloat,16,8) [] = { 0xfff0, 0xffff,
++						   0xfff1, 0xffff,
++						   0xfff2, 0xffff,
++						   0xfff3, 0xffff };
++VECT_VAR_DECL(expected_q_f16_8,hfloat,16,8) [] = { 0xfff0, 0xffff,
++						   0xffff, 0xffff,
++						   0xfff1, 0xffff,
++						   0xffff, 0xffff };
++VECT_VAR_DECL(expected_q_f16_9,hfloat,16,8) [] = { 0xf1f0, 0xf3f2,
++						   0xf5f4, 0xf7f6,
++						   0xf9f8, 0xfbfa,
++						   0xfdfc, 0xfffe };
++VECT_VAR_DECL(expected_q_f16_10,hfloat,16,8) [] = { 0xfff0, 0xfff1,
++						    0xfff2, 0xfff3,
++						    0xfff4, 0xfff5,
++						    0xfff6, 0xfff7 };
+ 
+ #define TEST_MSG "VREINTERPRET/VREINTERPRETQ"
+ 
+@@ -484,6 +665,10 @@ void exec_vreinterpret (void)
+ 
+   /* Initialize input "vector" from "buffer".  */
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+@@ -497,6 +682,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, int, s, 8, 8, uint, u, 64, 1, expected_s8_7);
+   TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 8, 8, expected_s8_8);
+   TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 16, 4, expected_s8_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, int, s, 8, 8, float, f, 16, 4, expected_s8_10);
++#endif
+ 
+   /* vreinterpret_s16_xx.  */
+   TEST_VREINTERPRET(, int, s, 16, 4, int, s, 8, 8, expected_s16_1);
+@@ -508,6 +696,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, int, s, 16, 4, uint, u, 64, 1, expected_s16_7);
+   TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 8, 8, expected_s16_8);
+   TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 16, 4, expected_s16_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, int, s, 16, 4, float, f, 16, 4, expected_s16_10);
++#endif
+ 
+   /* vreinterpret_s32_xx.  */
+   TEST_VREINTERPRET(, int, s, 32, 2, int, s, 8, 8, expected_s32_1);
+@@ -519,6 +710,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, int, s, 32, 2, uint, u, 64, 1, expected_s32_7);
+   TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 8, 8, expected_s32_8);
+   TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 16, 4, expected_s32_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, int, s, 32, 2, float, f, 16, 4, expected_s32_10);
++#endif
+ 
+   /* vreinterpret_s64_xx.  */
+   TEST_VREINTERPRET(, int, s, 64, 1, int, s, 8, 8, expected_s64_1);
+@@ -530,6 +724,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, int, s, 64, 1, uint, u, 64, 1, expected_s64_7);
+   TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 8, 8, expected_s64_8);
+   TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 16, 4, expected_s64_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, int, s, 64, 1, float, f, 16, 4, expected_s64_10);
++#endif
+ 
+   /* vreinterpret_u8_xx.  */
+   TEST_VREINTERPRET(, uint, u, 8, 8, int, s, 8, 8, expected_u8_1);
+@@ -541,6 +738,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, uint, u, 8, 8, uint, u, 64, 1, expected_u8_7);
+   TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 8, 8, expected_u8_8);
+   TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 16, 4, expected_u8_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, uint, u, 8, 8, float, f, 16, 4, expected_u8_10);
++#endif
+ 
+   /* vreinterpret_u16_xx.  */
+   TEST_VREINTERPRET(, uint, u, 16, 4, int, s, 8, 8, expected_u16_1);
+@@ -552,6 +752,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, uint, u, 16, 4, uint, u, 64, 1, expected_u16_7);
+   TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 8, 8, expected_u16_8);
+   TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 16, 4, expected_u16_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, uint, u, 16, 4, float, f, 16, 4, expected_u16_10);
++#endif
+ 
+   /* vreinterpret_u32_xx.  */
+   TEST_VREINTERPRET(, uint, u, 32, 2, int, s, 8, 8, expected_u32_1);
+@@ -563,6 +766,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, uint, u, 32, 2, uint, u, 64, 1, expected_u32_7);
+   TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 8, 8, expected_u32_8);
+   TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 16, 4, expected_u32_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, uint, u, 32, 2, float, f, 16, 4, expected_u32_10);
++#endif
+ 
+   /* vreinterpret_u64_xx.  */
+   TEST_VREINTERPRET(, uint, u, 64, 1, int, s, 8, 8, expected_u64_1);
+@@ -574,6 +780,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, uint, u, 64, 1, uint, u, 32, 2, expected_u64_7);
+   TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 8, 8, expected_u64_8);
+   TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 16, 4, expected_u64_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(, uint, u, 64, 1, float, f, 16, 4, expected_u64_10);
++#endif
+ 
+   /* vreinterpret_p8_xx.  */
+   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, int, s, 8, 8, expected_p8_1);
+@@ -585,6 +794,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 32, 2, expected_p8_7);
+   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 64, 1, expected_p8_8);
+   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, poly, p, 16, 4, expected_p8_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_POLY(, poly, p, 8, 8, float, f, 16, 4, expected_p8_10);
++#endif
+ 
+   /* vreinterpret_p16_xx.  */
+   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, int, s, 8, 8, expected_p16_1);
+@@ -596,6 +808,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 32, 2, expected_p16_7);
+   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 64, 1, expected_p16_8);
+   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, poly, p, 8, 8, expected_p16_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_POLY(, poly, p, 16, 4, float, f, 16, 4, expected_p16_10);
++#endif
+ 
+   /* vreinterpretq_s8_xx.  */
+   TEST_VREINTERPRET(q, int, s, 8, 16, int, s, 16, 8, expected_q_s8_1);
+@@ -607,6 +822,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, int, s, 8, 16, uint, u, 64, 2, expected_q_s8_7);
+   TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 8, 16, expected_q_s8_8);
+   TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 16, 8, expected_q_s8_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, int, s, 8, 16, float, f, 16, 8, expected_q_s8_10);
++#endif
+ 
+   /* vreinterpretq_s16_xx.  */
+   TEST_VREINTERPRET(q, int, s, 16, 8, int, s, 8, 16, expected_q_s16_1);
+@@ -618,6 +836,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, int, s, 16, 8, uint, u, 64, 2, expected_q_s16_7);
+   TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 8, 16, expected_q_s16_8);
+   TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 16, 8, expected_q_s16_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, int, s, 16, 8, float, f, 16, 8, expected_q_s16_10);
++#endif
+ 
+   /* vreinterpretq_s32_xx.  */
+   TEST_VREINTERPRET(q, int, s, 32, 4, int, s, 8, 16, expected_q_s32_1);
+@@ -629,6 +850,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, int, s, 32, 4, uint, u, 64, 2, expected_q_s32_7);
+   TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 8, 16, expected_q_s32_8);
+   TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 16, 8, expected_q_s32_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, int, s, 32, 4, float, f, 16, 8, expected_q_s32_10);
++#endif
+ 
+   /* vreinterpretq_s64_xx.  */
+   TEST_VREINTERPRET(q, int, s, 64, 2, int, s, 8, 16, expected_q_s64_1);
+@@ -640,6 +864,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, int, s, 64, 2, uint, u, 64, 2, expected_q_s64_7);
+   TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 8, 16, expected_q_s64_8);
+   TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 16, 8, expected_q_s64_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, int, s, 64, 2, float, f, 16, 8, expected_q_s64_10);
++#endif
+ 
+   /* vreinterpretq_u8_xx.  */
+   TEST_VREINTERPRET(q, uint, u, 8, 16, int, s, 8, 16, expected_q_u8_1);
+@@ -651,6 +878,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, uint, u, 8, 16, uint, u, 64, 2, expected_q_u8_7);
+   TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 8, 16, expected_q_u8_8);
+   TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 16, 8, expected_q_u8_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, uint, u, 8, 16, float, f, 16, 8, expected_q_u8_10);
++#endif
+ 
+   /* vreinterpretq_u16_xx.  */
+   TEST_VREINTERPRET(q, uint, u, 16, 8, int, s, 8, 16, expected_q_u16_1);
+@@ -662,6 +892,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, uint, u, 16, 8, uint, u, 64, 2, expected_q_u16_7);
+   TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 8, 16, expected_q_u16_8);
+   TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 16, 8, expected_q_u16_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, uint, u, 16, 8, float, f, 16, 8, expected_q_u16_10);
++#endif
+ 
+   /* vreinterpretq_u32_xx.  */
+   TEST_VREINTERPRET(q, uint, u, 32, 4, int, s, 8, 16, expected_q_u32_1);
+@@ -673,6 +906,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, uint, u, 32, 4, uint, u, 64, 2, expected_q_u32_7);
+   TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 8, 16, expected_q_u32_8);
+   TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 16, 8, expected_q_u32_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, uint, u, 32, 4, float, f, 16, 8, expected_q_u32_10);
++#endif
+ 
+   /* vreinterpretq_u64_xx.  */
+   TEST_VREINTERPRET(q, uint, u, 64, 2, int, s, 8, 16, expected_q_u64_1);
+@@ -684,6 +920,37 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, uint, u, 64, 2, uint, u, 32, 4, expected_q_u64_7);
+   TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 8, 16, expected_q_u64_8);
+   TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 16, 8, expected_q_u64_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET(q, uint, u, 64, 2, float, f, 16, 8, expected_q_u64_10);
++#endif
++
++  /* vreinterpretq_p8_xx.  */
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 8, 16, expected_q_p8_1);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 16, 8, expected_q_p8_2);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 32, 4, expected_q_p8_3);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 64, 2, expected_q_p8_4);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 8, 16, expected_q_p8_5);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 16, 8, expected_q_p8_6);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 32, 4, expected_q_p8_7);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 64, 2, expected_q_p8_8);
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, poly, p, 16, 8, expected_q_p8_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, float, f, 16, 8, expected_q_p8_10);
++#endif
++
++  /* vreinterpretq_p16_xx.  */
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 8, 16, expected_q_p16_1);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 16, 8, expected_q_p16_2);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 32, 4, expected_q_p16_3);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 64, 2, expected_q_p16_4);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 8, 16, expected_q_p16_5);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 16, 8, expected_q_p16_6);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 32, 4, expected_q_p16_7);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 64, 2, expected_q_p16_8);
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, poly, p, 8, 16, expected_q_p16_9);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, float, f, 16, 8, expected_q_p16_10);
++#endif
+ 
+   /* vreinterpret_f32_xx.  */
+   TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 8, 8, expected_f32_1);
+@@ -696,6 +963,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET_FP(, float, f, 32, 2, uint, u, 64, 1, expected_f32_8);
+   TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 8, 8, expected_f32_9);
+   TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 16, 4, expected_f32_10);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP(, float, f, 32, 2, float, f, 16, 4, expected_f32_11);
++#endif
+ 
+   /* vreinterpretq_f32_xx.  */
+   TEST_VREINTERPRET_FP(q, float, f, 32, 4, int, s, 8, 16, expected_q_f32_1);
+@@ -708,6 +978,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET_FP(q, float, f, 32, 4, uint, u, 64, 2, expected_q_f32_8);
+   TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 8, 16, expected_q_f32_9);
+   TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 16, 8, expected_q_f32_10);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP(q, float, f, 32, 4, float, f, 16, 8, expected_q_f32_11);
++#endif
+ 
+   /* vreinterpret_xx_f32.  */
+   TEST_VREINTERPRET(, int, s, 8, 8, float, f, 32, 2, expected_xx_f32_1);
+@@ -720,6 +993,9 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(, uint, u, 64, 1, float, f, 32, 2, expected_xx_f32_8);
+   TEST_VREINTERPRET_POLY(, poly, p, 8, 8, float, f, 32, 2, expected_xx_f32_9);
+   TEST_VREINTERPRET_POLY(, poly, p, 16, 4, float, f, 32, 2, expected_xx_f32_10);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, float, f, 32, 2, expected_xx_f32_11);
++#endif
+ 
+   /* vreinterpretq_xx_f32.  */
+   TEST_VREINTERPRET(q, int, s, 8, 16, float, f, 32, 4, expected_q_xx_f32_1);
+@@ -732,6 +1008,33 @@ void exec_vreinterpret (void)
+   TEST_VREINTERPRET(q, uint, u, 64, 2, float, f, 32, 4, expected_q_xx_f32_8);
+   TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, float, f, 32, 4, expected_q_xx_f32_9);
+   TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, float, f, 32, 4, expected_q_xx_f32_10);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, float, f, 32, 4, expected_q_xx_f32_11);
++
++  /* vreinterpret_f16_xx.  */
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 8, 8, expected_f16_1);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 16, 4, expected_f16_2);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 32, 2, expected_f16_3);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, int, s, 64, 1, expected_f16_4);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 8, 8, expected_f16_5);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 16, 4, expected_f16_6);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 32, 2, expected_f16_7);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, uint, u, 64, 1, expected_f16_8);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 8, 8, expected_f16_9);
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 16, 4, expected_f16_10);
++
++  /* vreinterpretq_f16_xx.  */
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 8, 16, expected_q_f16_1);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 16, 8, expected_q_f16_2);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 32, 4, expected_q_f16_3);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, int, s, 64, 2, expected_q_f16_4);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 8, 16, expected_q_f16_5);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 16, 8, expected_q_f16_6);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 32, 4, expected_q_f16_7);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 64, 2, expected_q_f16_8);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 8, 16, expected_q_f16_9);
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 16, 8, expected_q_f16_10);
++#endif
+ }
+ 
+ int main (void)
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
+@@ -0,0 +1,165 @@
++/* This file contains tests for the vreinterpret *p128 intrinsics.  */
++
++/* { dg-require-effective-target arm_crypto_ok { target { arm*-*-* } } } */
++/* { dg-add-options arm_crypto } */
++/* { dg-additional-options "-march=armv8-a+crypto" { target { aarch64*-*-* } } }*/
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results: vreinterpretq_p128_*.  */
++VECT_VAR_DECL(vreint_expected_q_p128_s8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
++							  0xfffefdfcfbfaf9f8 };
++VECT_VAR_DECL(vreint_expected_q_p128_s16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
++							   0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(vreint_expected_q_p128_s32,poly,64,2) [] = { 0xfffffff1fffffff0,
++							   0xfffffff3fffffff2 };
++VECT_VAR_DECL(vreint_expected_q_p128_s64,poly,64,2) [] = { 0xfffffffffffffff0,
++							   0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_p128_u8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
++							  0xfffefdfcfbfaf9f8 };
++VECT_VAR_DECL(vreint_expected_q_p128_u16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
++							   0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(vreint_expected_q_p128_u32,poly,64,2) [] = { 0xfffffff1fffffff0,
++							   0xfffffff3fffffff2 };
++VECT_VAR_DECL(vreint_expected_q_p128_u64,poly,64,2) [] = { 0xfffffffffffffff0,
++							   0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_p128_p8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
++							  0xfffefdfcfbfaf9f8 };
++VECT_VAR_DECL(vreint_expected_q_p128_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
++							   0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(vreint_expected_q_p128_f32,poly,64,2) [] = { 0xc1700000c1800000,
++							   0xc1500000c1600000 };
++VECT_VAR_DECL(vreint_expected_q_p128_f16,poly,64,2) [] = { 0xca80cb00cb80cc00,
++							   0xc880c900c980ca00 };
++
++/* Expected results: vreinterpretq_*_p128.  */
++VECT_VAR_DECL(vreint_expected_q_s8_p128,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++							 0xff, 0xff, 0xff, 0xff,
++							 0xf1, 0xff, 0xff, 0xff,
++							 0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_q_s16_p128,int,16,8) [] = { 0xfff0, 0xffff,
++							  0xffff, 0xffff,
++							  0xfff1, 0xffff,
++							  0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_q_s32_p128,int,32,4) [] = { 0xfffffff0, 0xffffffff,
++							  0xfffffff1, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_q_s64_p128,int,64,2) [] = { 0xfffffffffffffff0,
++							  0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_u8_p128,uint,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++							  0xff, 0xff, 0xff, 0xff,
++							  0xf1, 0xff, 0xff, 0xff,
++							  0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_q_u16_p128,uint,16,8) [] = { 0xfff0, 0xffff,
++							   0xffff, 0xffff,
++							   0xfff1, 0xffff,
++							   0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_q_u32_p128,uint,32,4) [] = { 0xfffffff0, 0xffffffff,
++							   0xfffffff1, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_q_u64_p128,uint,64,2) [] = { 0xfffffffffffffff0,
++							   0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_p8_p128,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++							  0xff, 0xff, 0xff, 0xff,
++							  0xf1, 0xff, 0xff, 0xff,
++							  0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_q_p16_p128,poly,16,8) [] = { 0xfff0, 0xffff,
++							   0xffff, 0xffff,
++							   0xfff1, 0xffff,
++							   0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_q_p64_p128,uint,64,2) [] = { 0xfffffffffffffff0,
++							   0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_f32_p128,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
++							     0xfffffff1, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_q_f16_p128,hfloat,16,8) [] = { 0xfff0, 0xffff,
++							     0xffff, 0xffff,
++							     0xfff1, 0xffff,
++							     0xffff, 0xffff };
++
++int main (void)
++{
++  DECL_VARIABLE_128BITS_VARIANTS(vreint_vector);
++  DECL_VARIABLE_128BITS_VARIANTS(vreint_vector_res);
++
++  clean_results ();
++
++  TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vreint_vector, buffer);
++  VLOAD(vreint_vector, buffer, q, poly, p, 64, 2);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  VLOAD(vreint_vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD(vreint_vector, buffer, q, float, f, 32, 4);
++
++  /* vreinterpretq_p128_* tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VREINTERPRETQ_P128_*"
++
++  /* Since there is no way to store a poly128_t value, convert to
++     poly64x2_t before storing. This means that we are not able to
++     test vreinterpretq_p128* alone, and that errors in
++     vreinterpretq_p64_p128 could compensate for errors in
++     vreinterpretq_p128*.  */
++#define TEST_VREINTERPRET128(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
++  VECT_VAR(vreint_vector_res, poly, 64, 2) =  vreinterpretq_p64_p128(	\
++    vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS))); \
++  vst1##Q##_##T2##64(VECT_VAR(result, poly, 64, 2),			\
++                     VECT_VAR(vreint_vector_res, poly, 64, 2));		\
++  CHECK_POLY(TEST_MSG, T1, 64, 2, PRIx##64, EXPECTED, "");
++
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 8, 16, vreint_expected_q_p128_s8);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 16, 8, vreint_expected_q_p128_s16);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 32, 4, vreint_expected_q_p128_s32);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 64, 2, vreint_expected_q_p128_s64);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 8, 16, vreint_expected_q_p128_u8);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 16, 8, vreint_expected_q_p128_u16);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 32, 4, vreint_expected_q_p128_u32);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 64, 2, vreint_expected_q_p128_u64);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 8, 16, vreint_expected_q_p128_p8);
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 16, 8, vreint_expected_q_p128_p16);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 16, 8, vreint_expected_q_p128_f16);
++#endif
++  TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 32, 4, vreint_expected_q_p128_f32);
++
++  /* vreinterpretq_*_p128 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VREINTERPRETQ_*_P128"
++
++  /* Since there is no way to load a poly128_t value, load a
++     poly64x2_t and convert it to poly128_t. This means that we are
++     not able to test vreinterpretq_*_p128 alone, and that errors in
++     vreinterpretq_p128_p64 could compensate for errors in
++     vreinterpretq_*_p128*.  */
++#define TEST_VREINTERPRET_FROM_P128(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
++  VECT_VAR(vreint_vector_res, T1, W, N) =				\
++    vreinterpret##Q##_##T2##W##_##TS2##WS(				\
++  vreinterpretq_p128_p64(VECT_VAR(vreint_vector, TS1, 64, 2)));		\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
++		    VECT_VAR(vreint_vector_res, T1, W, N));		\
++  CHECK(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
++
++#define TEST_VREINTERPRET_FP_FROM_P128(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
++  VECT_VAR(vreint_vector_res, T1, W, N) =				\
++    vreinterpret##Q##_##T2##W##_##TS2##WS(				\
++  vreinterpretq_p128_p64(VECT_VAR(vreint_vector, TS1, 64, 2)));		\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
++		    VECT_VAR(vreint_vector_res, T1, W, N));		\
++  CHECK_FP(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
++
++  TEST_VREINTERPRET_FROM_P128(q, int, s, 8, 16, poly, p, 128, 1, vreint_expected_q_s8_p128);
++  TEST_VREINTERPRET_FROM_P128(q, int, s, 16, 8, poly, p, 128, 1, vreint_expected_q_s16_p128);
++  TEST_VREINTERPRET_FROM_P128(q, int, s, 32, 4, poly, p, 128, 1, vreint_expected_q_s32_p128);
++  TEST_VREINTERPRET_FROM_P128(q, int, s, 64, 2, poly, p, 128, 1, vreint_expected_q_s64_p128);
++  TEST_VREINTERPRET_FROM_P128(q, uint, u, 8, 16, poly, p, 128, 1, vreint_expected_q_u8_p128);
++  TEST_VREINTERPRET_FROM_P128(q, uint, u, 16, 8, poly, p, 128, 1, vreint_expected_q_u16_p128);
++  TEST_VREINTERPRET_FROM_P128(q, uint, u, 32, 4, poly, p, 128, 1, vreint_expected_q_u32_p128);
++  TEST_VREINTERPRET_FROM_P128(q, uint, u, 64, 2, poly, p, 128, 1, vreint_expected_q_u64_p128);
++  TEST_VREINTERPRET_FROM_P128(q, poly, p, 8, 16, poly, p, 128, 1, vreint_expected_q_p8_p128);
++  TEST_VREINTERPRET_FROM_P128(q, poly, p, 16, 8, poly, p, 128, 1, vreint_expected_q_p16_p128);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 16, 8, poly, p, 128, 1, vreint_expected_q_f16_p128);
++#endif
++  TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 32, 4, poly, p, 128, 1, vreint_expected_q_f32_p128);
++
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c
+@@ -0,0 +1,216 @@
++/* This file contains tests for the vreinterpret *p64 intrinsics.  */
++
++/* { dg-require-effective-target arm_crypto_ok { target { arm*-*-* } } } */
++/* { dg-add-options arm_crypto } */
++/* { dg-additional-options "-march=armv8-a+crypto" { target { aarch64*-*-* } } }*/
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results: vreinterpret_p64_*.  */
++VECT_VAR_DECL(vreint_expected_p64_s8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
++VECT_VAR_DECL(vreint_expected_p64_s16,poly,64,1) [] = { 0xfff3fff2fff1fff0 };
++VECT_VAR_DECL(vreint_expected_p64_s32,poly,64,1) [] = { 0xfffffff1fffffff0 };
++VECT_VAR_DECL(vreint_expected_p64_s64,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vreint_expected_p64_u8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
++VECT_VAR_DECL(vreint_expected_p64_u16,poly,64,1) [] = { 0xfff3fff2fff1fff0 };
++VECT_VAR_DECL(vreint_expected_p64_u32,poly,64,1) [] = { 0xfffffff1fffffff0 };
++VECT_VAR_DECL(vreint_expected_p64_u64,poly,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vreint_expected_p64_p8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
++VECT_VAR_DECL(vreint_expected_p64_p16,poly,64,1) [] = { 0xfff3fff2fff1fff0 };
++VECT_VAR_DECL(vreint_expected_p64_f32,poly,64,1) [] = { 0xc1700000c1800000 };
++VECT_VAR_DECL(vreint_expected_p64_f16,poly,64,1) [] = { 0xca80cb00cb80cc00 };
++
++/* Expected results: vreinterpretq_p64_*.  */
++VECT_VAR_DECL(vreint_expected_q_p64_s8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
++							 0xfffefdfcfbfaf9f8 };
++VECT_VAR_DECL(vreint_expected_q_p64_s16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
++							  0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(vreint_expected_q_p64_s32,poly,64,2) [] = { 0xfffffff1fffffff0,
++							  0xfffffff3fffffff2 };
++VECT_VAR_DECL(vreint_expected_q_p64_s64,poly,64,2) [] = { 0xfffffffffffffff0,
++							  0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_p64_u8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
++							 0xfffefdfcfbfaf9f8 };
++VECT_VAR_DECL(vreint_expected_q_p64_u16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
++							  0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(vreint_expected_q_p64_u32,poly,64,2) [] = { 0xfffffff1fffffff0,
++							  0xfffffff3fffffff2 };
++VECT_VAR_DECL(vreint_expected_q_p64_u64,poly,64,2) [] = { 0xfffffffffffffff0,
++							  0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_p64_p8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0,
++							 0xfffefdfcfbfaf9f8 };
++VECT_VAR_DECL(vreint_expected_q_p64_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0,
++							  0xfff7fff6fff5fff4 };
++VECT_VAR_DECL(vreint_expected_q_p64_f32,poly,64,2) [] = { 0xc1700000c1800000,
++							  0xc1500000c1600000 };
++VECT_VAR_DECL(vreint_expected_q_p64_f16,poly,64,2) [] = { 0xca80cb00cb80cc00,
++							  0xc880c900c980ca00 };
++
++/* Expected results: vreinterpret_*_p64.  */
++VECT_VAR_DECL(vreint_expected_s8_p64,int,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
++						     0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_s16_p64,int,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_s32_p64,int,32,2) [] = { 0xfffffff0, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_s64_p64,int,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vreint_expected_u8_p64,uint,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
++						      0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_u16_p64,uint,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_u32_p64,uint,32,2) [] = { 0xfffffff0, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_u64_p64,uint,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(vreint_expected_p8_p64,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff,
++						      0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_p16_p64,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_f32_p64,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_f16_p64,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff };
++
++/* Expected results: vreinterpretq_*_p64.  */
++VECT_VAR_DECL(vreint_expected_q_s8_p64,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++							0xff, 0xff, 0xff, 0xff,
++							0xf1, 0xff, 0xff, 0xff,
++							0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_q_s16_p64,int,16,8) [] = { 0xfff0, 0xffff,
++							 0xffff, 0xffff,
++							 0xfff1, 0xffff,
++							 0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_q_s32_p64,int,32,4) [] = { 0xfffffff0, 0xffffffff,
++							 0xfffffff1, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_q_s64_p64,int,64,2) [] = { 0xfffffffffffffff0,
++							 0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_u8_p64,uint,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++							 0xff, 0xff, 0xff, 0xff,
++							 0xf1, 0xff, 0xff, 0xff,
++							 0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_q_u16_p64,uint,16,8) [] = { 0xfff0, 0xffff,
++							  0xffff, 0xffff,
++							  0xfff1, 0xffff,
++							  0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_q_u32_p64,uint,32,4) [] = { 0xfffffff0, 0xffffffff,
++							  0xfffffff1, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_q_u64_p64,uint,64,2) [] = { 0xfffffffffffffff0,
++							  0xfffffffffffffff1 };
++VECT_VAR_DECL(vreint_expected_q_p8_p64,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
++							 0xff, 0xff, 0xff, 0xff,
++							 0xf1, 0xff, 0xff, 0xff,
++							 0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(vreint_expected_q_p16_p64,poly,16,8) [] = { 0xfff0, 0xffff,
++							  0xffff, 0xffff,
++							  0xfff1, 0xffff,
++							  0xffff, 0xffff };
++VECT_VAR_DECL(vreint_expected_q_f32_p64,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff,
++							    0xfffffff1, 0xffffffff };
++VECT_VAR_DECL(vreint_expected_q_f16_p64,hfloat,16,8) [] = { 0xfff0, 0xffff,
++							    0xffff, 0xffff,
++							    0xfff1, 0xffff,
++							    0xffff, 0xffff };
++
++int main (void)
++{
++#define TEST_VREINTERPRET(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED)	\
++  VECT_VAR(vreint_vector_res, T1, W, N) =				\
++    vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS)); \
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
++		    VECT_VAR(vreint_vector_res, T1, W, N));		\
++  CHECK(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
++
++#define TEST_VREINTERPRET_TO_POLY(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED)	\
++  VECT_VAR(vreint_vector_res, T1, W, N) =				\
++    vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS)); \
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
++		    VECT_VAR(vreint_vector_res, T1, W, N));		\
++  CHECK_POLY(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
++
++#define TEST_VREINTERPRET_FP(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \
++  VECT_VAR(vreint_vector_res, T1, W, N) =				\
++    vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS)); \
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),				\
++		    VECT_VAR(vreint_vector_res, T1, W, N));		\
++  CHECK_FP(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, "");
++
++  DECL_VARIABLE_ALL_VARIANTS(vreint_vector);
++  DECL_VARIABLE_ALL_VARIANTS(vreint_vector_res);
++
++  clean_results ();
++
++  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vreint_vector, buffer);
++  VLOAD(vreint_vector, buffer, , poly, p, 64, 1);
++  VLOAD(vreint_vector, buffer, q, poly, p, 64, 2);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  VLOAD(vreint_vector, buffer, , float, f, 16, 4);
++  VLOAD(vreint_vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD(vreint_vector, buffer, , float, f, 32, 2);
++  VLOAD(vreint_vector, buffer, q, float, f, 32, 4);
++
++  /* vreinterpret_p64_* tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VREINTERPRET_P64_*"
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, int, s, 8, 8, vreint_expected_p64_s8);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, int, s, 16, 4, vreint_expected_p64_s16);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, int, s, 32, 2, vreint_expected_p64_s32);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, int, s, 64, 1, vreint_expected_p64_s64);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, uint, u, 8, 8, vreint_expected_p64_u8);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, uint, u, 16, 4, vreint_expected_p64_u16);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, uint, u, 32, 2, vreint_expected_p64_u32);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, uint, u, 64, 1, vreint_expected_p64_u64);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, poly, p, 8, 8, vreint_expected_p64_p8);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, poly, p, 16, 4, vreint_expected_p64_p16);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, float, f, 16, 4, vreint_expected_p64_f16);
++#endif
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 64, 1, float, f, 32, 2, vreint_expected_p64_f32);
++
++  /* vreinterpretq_p64_* tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VREINTERPRETQ_P64_*"
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, int, s, 8, 16, vreint_expected_q_p64_s8);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, int, s, 16, 8, vreint_expected_q_p64_s16);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, int, s, 32, 4, vreint_expected_q_p64_s32);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, int, s, 64, 2, vreint_expected_q_p64_s64);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, uint, u, 8, 16, vreint_expected_q_p64_u8);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, uint, u, 16, 8, vreint_expected_q_p64_u16);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, uint, u, 32, 4, vreint_expected_q_p64_u32);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, uint, u, 64, 2, vreint_expected_q_p64_u64);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, poly, p, 8, 16, vreint_expected_q_p64_p8);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, poly, p, 16, 8, vreint_expected_q_p64_p16);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, float, f, 16, 8, vreint_expected_q_p64_f16);
++#endif
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 64, 2, float, f, 32, 4, vreint_expected_q_p64_f32);
++
++  /* vreinterpret_*_p64 tests.  */
++#undef TEST_MSG
++#define TEST_MSG "VREINTERPRET_*_P64"
++
++  TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 64, 1, vreint_expected_s8_p64);
++  TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 64, 1, vreint_expected_s16_p64);
++  TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 64, 1, vreint_expected_s32_p64);
++  TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 64, 1, vreint_expected_s64_p64);
++  TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 64, 1, vreint_expected_u8_p64);
++  TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 64, 1, vreint_expected_u16_p64);
++  TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 64, 1, vreint_expected_u32_p64);
++  TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 64, 1, vreint_expected_u64_p64);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 8, 8, poly, p, 64, 1, vreint_expected_p8_p64);
++  TEST_VREINTERPRET_TO_POLY(, poly, p, 16, 4, poly, p, 64, 1, vreint_expected_p16_p64);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 64, 1, vreint_expected_f16_p64);
++#endif
++  TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 64, 1, vreint_expected_f32_p64);
++  TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 64, 2, vreint_expected_q_s8_p64);
++  TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 64, 2, vreint_expected_q_s16_p64);
++  TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 64, 2, vreint_expected_q_s32_p64);
++  TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 64, 2, vreint_expected_q_s64_p64);
++  TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 64, 2, vreint_expected_q_u8_p64);
++  TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 64, 2, vreint_expected_q_u16_p64);
++  TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 64, 2, vreint_expected_q_u32_p64);
++  TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 64, 2, vreint_expected_q_u64_p64);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 8, 16, poly, p, 64, 2, vreint_expected_q_p8_p64);
++  TEST_VREINTERPRET_TO_POLY(q, poly, p, 16, 8, poly, p, 64, 2, vreint_expected_q_p16_p64);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 64, 2, vreint_expected_q_f16_p64);
++#endif
++  TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 64, 2, vreint_expected_q_f32_p64);
++
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c
+@@ -63,6 +63,10 @@ VECT_VAR_DECL(expected_vrev64,uint,32,2) [] = { 0xfffffff1, 0xfffffff0 };
+ VECT_VAR_DECL(expected_vrev64,poly,8,8) [] = { 0xf7, 0xf6, 0xf5, 0xf4,
+ 					       0xf3, 0xf2, 0xf1, 0xf0 };
+ VECT_VAR_DECL(expected_vrev64,poly,16,4) [] = { 0xfff3, 0xfff2, 0xfff1, 0xfff0 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected_vrev64, hfloat, 16, 4) [] = { 0xca80, 0xcb00,
++						      0xcb80, 0xcc00 };
++#endif
+ VECT_VAR_DECL(expected_vrev64,hfloat,32,2) [] = { 0xc1700000, 0xc1800000 };
+ VECT_VAR_DECL(expected_vrev64,int,8,16) [] = { 0xf7, 0xf6, 0xf5, 0xf4,
+ 					       0xf3, 0xf2, 0xf1, 0xf0,
+@@ -86,6 +90,12 @@ VECT_VAR_DECL(expected_vrev64,poly,8,16) [] = { 0xf7, 0xf6, 0xf5, 0xf4,
+ 						0xfb, 0xfa, 0xf9, 0xf8 };
+ VECT_VAR_DECL(expected_vrev64,poly,16,8) [] = { 0xfff3, 0xfff2, 0xfff1, 0xfff0,
+ 						0xfff7, 0xfff6, 0xfff5, 0xfff4 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected_vrev64, hfloat, 16, 8) [] = { 0xca80, 0xcb00,
++						      0xcb80, 0xcc00,
++						      0xc880, 0xc900,
++						      0xc980, 0xca00 };
++#endif
+ VECT_VAR_DECL(expected_vrev64,hfloat,32,4) [] = { 0xc1700000, 0xc1800000,
+ 						  0xc1500000, 0xc1600000 };
+ 
+@@ -104,6 +114,10 @@ void exec_vrev (void)
+ 
+   /* Initialize input "vector" from "buffer".  */
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD (vector, buffer, , float, f, 16, 4);
++  VLOAD (vector, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector, buffer, , float, f, 32, 2);
+   VLOAD(vector, buffer, q, float, f, 32, 4);
+ 
+@@ -118,10 +132,10 @@ void exec_vrev (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vrev16, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vrev16, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev16, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev16, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vrev16, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vrev16, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev16, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev16, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VREV32"
+@@ -142,14 +156,14 @@ void exec_vrev (void)
+   CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_vrev32, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vrev32, "");
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_vrev32, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev32, "");
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_vrev32, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev32, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_vrev32, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vrev32, "");
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_vrev32, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vrev32, "");
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_vrev32, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev32, "");
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_vrev32, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev32, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_vrev32, "");
+ 
+ #undef TEST_MSG
+ #define TEST_MSG "VREV64"
+@@ -176,17 +190,23 @@ void exec_vrev (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vrev64, "");
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_vrev64, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_vrev64, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev64, "");
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_vrev64, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vrev64, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_vrev64, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_vrev64, "");
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_vrev64, "");
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_vrev64, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_vrev64, "");
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_vrev64, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_vrev64, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev64, "");
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_vrev64, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_vrev64, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_vrev64, "");
+ 
++#if defined (FP16_SUPPORTED)
++  TEST_VREV (, float, f, 16, 4, 64);
++  TEST_VREV (q, float, f, 16, 8, 64);
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx32, expected_vrev64, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx32, expected_vrev64, "");
++#endif
+   TEST_VREV(, float, f, 32, 2, 64);
+   TEST_VREV(q, float, f, 32, 4, 64);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_vrev64, "");
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
+@@ -0,0 +1,24 @@
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-add-options arm_v8_neon } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80 };
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80,
++					       0xca00, 0xc980,
++					       0xc900, 0xc880 };
++#endif
++VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
++VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
++					       0xc1600000, 0xc1500000 };
++
++#define INSN vrnd
++#define TEST_MSG "VRND"
++
++#include "vrndX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
+@@ -0,0 +1,63 @@
++#define FNNAME1(NAME) exec_ ## NAME
++#define FNNAME(NAME) FNNAME1 (NAME)
++
++void FNNAME (INSN) (void)
++{
++  /* vector_res = vrndX (vector), then store the result.  */
++#define TEST_VRND2(INSN, Q, T1, T2, W, N)				\
++  VECT_VAR (vector_res, T1, W, N) =					\
++    INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N));			\
++    vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),			\
++		       VECT_VAR (vector_res, T1, W, N))
++
++  /* Two auxliary macros are necessary to expand INSN.  */
++#define TEST_VRND1(INSN, Q, T1, T2, W, N)	\
++  TEST_VRND2 (INSN, Q, T1, T2, W, N)
++
++#define TEST_VRND(Q, T1, T2, W, N)		\
++  TEST_VRND1 (INSN, Q, T1, T2, W, N)
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
++  DECL_VARIABLE (vector, float, 32, 2);
++  DECL_VARIABLE (vector, float, 32, 4);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
++  DECL_VARIABLE (vector_res, float, 32, 2);
++  DECL_VARIABLE (vector_res, float, 32, 4);
++
++  clean_results ();
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VLOAD (vector, buffer, , float, f, 16, 4);
++  VLOAD (vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD (vector, buffer, , float, f, 32, 2);
++  VLOAD (vector, buffer, q, float, f, 32, 4);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRND ( , float, f, 16, 4);
++  TEST_VRND (q, float, f, 16, 8);
++#endif
++  TEST_VRND ( , float, f, 32, 2);
++  TEST_VRND (q, float, f, 32, 4);
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected, "");
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected, "");
++#endif
++  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
++  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
++}
++
++int
++main (void)
++{
++  FNNAME (INSN) ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
+@@ -0,0 +1,25 @@
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-add-options arm_v8_neon } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80 };
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80,
++					       0xca00, 0xc980,
++					       0xc900, 0xc880 };
++#endif
++VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
++VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
++					       0xc1600000, 0xc1500000 };
++
++#define INSN vrnda
++#define TEST_MSG "VRNDA"
++
++#include "vrndX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4200 /* 3.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc000 /* -2.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc800 /* -8.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a80 /* 13.000000 */,
++  0xc600 /* -6.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDAH_F16"
++#define INSN_NAME vrndah_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4200 /* 3.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc000 /* -2.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc700 /* -7.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a80 /* 13.000000 */,
++  0xc600 /* -6.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDH_F16"
++#define INSN_NAME vrndh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c
+@@ -0,0 +1,71 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (123.4)
++#define RNDI_A 0x57B0 /* FP16_C (123).  */
++#define B FP16_C (-567.5)
++#define RNDI_B 0xE070 /* FP16_C (-568).  */
++#define C FP16_C (-34.8)
++#define RNDI_C 0xD060 /* FP16_C (-35).  */
++#define D FP16_C (1024)
++#define RNDI_D 0x6400 /* FP16_C (1024).  */
++#define E FP16_C (663.1)
++#define RNDI_E 0x612E /* FP16_C (663).  */
++#define F FP16_C (169.1)
++#define RNDI_F 0x5948 /* FP16_C (169).  */
++#define G FP16_C (-4.8)
++#define RNDI_G 0xC500 /* FP16_C (-5).  */
++#define H FP16_C (77.5)
++#define RNDI_H 0x54E0 /* FP16_C (78).  */
++
++/* Expected results for vrndi.  */
++VECT_VAR_DECL (expected_static, hfloat, 16, 4) []
++  = { RNDI_A, RNDI_B, RNDI_C, RNDI_D };
++
++VECT_VAR_DECL (expected_static, hfloat, 16, 8) []
++  = { RNDI_A, RNDI_B, RNDI_C, RNDI_D, RNDI_E, RNDI_F, RNDI_G, RNDI_H };
++
++void exec_vrndi_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VRNDI (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A, B, C, D};
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vrndi_f16 (VECT_VAR (vsrc, float, 16, 4));
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VRNDIQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A, B, C, D, E, F, G, H};
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vrndiq_f16 (VECT_VAR (vsrc, float, 16, 8));
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_static, "");
++}
++
++int
++main (void)
++{
++  exec_vrndi_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4200 /* 3.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc000 /* -2.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc800 /* -8.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a80 /* 13.000000 */,
++  0xc600 /* -6.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDIH_F16"
++#define INSN_NAME vrndih_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
+@@ -0,0 +1,25 @@
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-add-options arm_v8_neon } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80 };
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80,
++					       0xca00, 0xc980,
++					       0xc900, 0xc880 };
++#endif
++VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
++VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
++					       0xc1600000, 0xc1500000 };
++
++#define INSN vrndm
++#define TEST_MSG "VRNDM"
++
++#include "vrndX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4200 /* 3.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc200 /* -3.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc800 /* -8.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a80 /* 13.000000 */,
++  0xc700 /* -7.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDMH_F16"
++#define INSN_NAME vrndmh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c
+@@ -0,0 +1,25 @@
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-add-options arm_v8_neon } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80 };
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80,
++					       0xca00, 0xc980,
++					       0xc900, 0xc880 };
++#endif
++VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
++VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
++					       0xc1600000, 0xc1500000 };
++
++#define INSN vrndn
++#define TEST_MSG "VRNDN"
++
++#include "vrndX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4200 /* 3.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc000 /* -2.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc800 /* -8.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a80 /* 13.000000 */,
++  0xc600 /* -6.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDNH_F16"
++#define INSN_NAME vrndnh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c
+@@ -0,0 +1,24 @@
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-add-options arm_v8_neon } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80 };
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80,
++					       0xca00, 0xc980,
++					       0xc900, 0xc880 };
++#endif
++VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
++VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
++					       0xc1600000, 0xc1500000 };
++
++#define INSN vrndp
++#define TEST_MSG "VRNDP"
++
++#include "vrndX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4400 /* 4.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc000 /* -2.000000 */,
++  0x4000 /* 2.000000 */,
++  0xc700 /* -7.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4b00 /* 14.000000 */,
++  0xc600 /* -6.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDPH_F16"
++#define INSN_NAME vrndph_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c
+@@ -0,0 +1,24 @@
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-add-options arm_v8_neon } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80 };
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++					       0xcb00, 0xca80,
++					       0xca00, 0xc980,
++					       0xc900, 0xc880 };
++#endif
++VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 };
++VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000,
++					       0xc1600000, 0xc1500000 };
++
++#define INSN vrndx
++#define TEST_MSG "VRNDX"
++
++#include "vrndX.inc"
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x4000 /* 2.000000 */,
++  0x4200 /* 3.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x0000 /* 0.000000 */,
++  0xc000 /* -2.000000 */,
++  0x3c00 /* 1.000000 */,
++  0xc800 /* -8.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x0000 /* 0.000000 */,
++  0x3c00 /* 1.000000 */,
++  0x4a80 /* 13.000000 */,
++  0xc600 /* -6.000000 */,
++  0x4d00 /* 20.000000 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VRNDNH_F16"
++#define INSN_NAME vrndnh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c
+@@ -7,6 +7,11 @@
+ VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0xffffffff };
+ VECT_VAR_DECL(expected,uint,32,4) [] = { 0x9c800000, 0x9c800000,
+ 					 0x9c800000, 0x9c800000 };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0x324c, 0x324c, 0x324c, 0x324c };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0x3380, 0x3380, 0x3380, 0x3380,
++					      0x3380, 0x3380, 0x3380, 0x3380 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x3e498000, 0x3e498000 };
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x3e700000, 0x3e700000,
+ 					   0x3e700000, 0x3e700000 };
+@@ -22,17 +27,39 @@ VECT_VAR_DECL(expected_2,uint,32,4) [] = { 0xed000000, 0xed000000,
+ 					   0xed000000, 0xed000000 };
+ 
+ /* Expected results with FP special inputs values (NaNs, ...).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 4) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 8) [] = { 0x7c00, 0x7c00,
++						  0x7c00, 0x7c00,
++						  0x7c00, 0x7c00,
++						  0x7c00, 0x7c00 };
++#endif
+ VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x7f800000, 0x7f800000,
+ 					       0x7f800000, 0x7f800000 };
+ 
+ /* Expected results with FP special inputs values
+    (negative, infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 4) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0, 0x0,
++						  0x0, 0x0, 0x0 };
++#endif
+ VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results with FP special inputs values
+    (-0, -infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp3, hfloat, 16, 4) [] = { 0xfc00, 0xfc00,
++						  0xfc00, 0xfc00 };
++VECT_VAR_DECL(expected_fp3, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++#endif
+ VECT_VAR_DECL(expected_fp3,hfloat,32,2) [] = { 0xff800000, 0xff800000 };
+ VECT_VAR_DECL(expected_fp3,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 					       0x7fc00000, 0x7fc00000 };
+@@ -50,32 +77,60 @@ void exec_vrsqrte(void)
+ 		    VECT_VAR(vector_res, T1, W, N))
+ 
+   DECL_VARIABLE(vector, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
+   DECL_VARIABLE(vector_res, uint, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+   DECL_VARIABLE(vector_res, uint, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 4);
+ 
+   clean_results ();
+ 
+   /* Choose init value arbitrarily.  */
+   VDUP(vector, , uint, u, 32, 2, 0x12345678);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 25.799999f);
++#endif
+   VDUP(vector, , float, f, 32, 2, 25.799999f);
+   VDUP(vector, q, uint, u, 32, 4, 0xABCDEF10);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, q, float, f, 16, 8, 18.2f);
++#endif
+   VDUP(vector, q, float, f, 32, 4, 18.2f);
+ 
+   /* Apply the operator.  */
+   TEST_VRSQRTE(, uint, u, 32, 2);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTE(, float, f, 16, 4);
++#endif
+   TEST_VRSQRTE(, float, f, 32, 2);
+   TEST_VRSQRTE(q, uint, u, 32, 4);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTE(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTE(q, float, f, 32, 4);
+ 
+ #define CMT ""
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, CMT);
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, CMT);
+ 
+@@ -110,42 +165,78 @@ void exec_vrsqrte(void)
+ 
+ 
+   /* Test FP variants with special input values (NaNs, ...).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, NAN);
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++#endif
+   VDUP(vector, , float, f, 32, 2, NAN);
+   VDUP(vector, q, float, f, 32, 4, 0.0f);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTE(, float, f, 16, 4);
++  TEST_VRSQRTE(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTE(, float, f, 32, 2);
+   TEST_VRSQRTE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (NaN, 0)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp1, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT);
+ 
+ 
+   /* Test FP variants with special input values (negative, infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, -1.0f);
++  VDUP(vector, q, float, f, 16, 8, HUGE_VALF);
++#endif
+   VDUP(vector, , float, f, 32, 2, -1.0f);
+   VDUP(vector, q, float, f, 32, 4, HUGE_VALF);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTE(, float, f, 16, 4);
++  TEST_VRSQRTE(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTE(, float, f, 32, 2);
+   TEST_VRSQRTE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (negative, infinity)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp2, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp2, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT);
+ 
+   /* Test FP variants with special input values (-0, -infinity).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, -0.0f);
++  VDUP(vector, q, float, f, 16, 8, -HUGE_VALF);
++#endif
+   VDUP(vector, , float, f, 32, 2, -0.0f);
+   VDUP(vector, q, float, f, 32, 4, -HUGE_VALF);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTE(, float, f, 16, 4);
++  TEST_VRSQRTE(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTE(, float, f, 32, 2);
+   TEST_VRSQRTE(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (-0, -infinity)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp3, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp3, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp3, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp3, CMT);
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c
+@@ -0,0 +1,30 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++float16_t input[] = { 123.4, 67.8, 34.8, 24.0, 66.1, 144.0, 4.8, 77.0 };
++uint16_t expected[] = { 0x2DC4 /* FP16_C (1/__builtin_sqrtf (123.4)).  */,
++			0x2FC8 /* FP16_C (1/__builtin_sqrtf (67.8)).  */,
++			0x316C /* FP16_C (1/__builtin_sqrtf (34.8)).  */,
++			0x3288 /* FP16_C (1/__builtin_sqrtf (24.0)).  */,
++			0x2FDC /* FP16_C (1/__builtin_sqrtf (66.1)).  */,
++			0x2D54 /* FP16_C (1/__builtin_sqrtf (144.0)).  */,
++			0x3750 /* FP16_C (1/__builtin_sqrtf (4.8)).  */,
++			0x2F48 /* FP16_C (1/__builtin_sqrtf (77.0)).  */ };
++
++#define TEST_MSG "VRSQRTEH_F16"
++#define INSN_NAME vrsqrteh_f16
++
++#define INPUT input
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c
+@@ -4,22 +4,51 @@
+ #include <math.h>
+ 
+ /* Expected results.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xd3cb, 0xd3cb, 0xd3cb, 0xd3cb };
++VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xc726, 0xc726, 0xc726, 0xc726,
++					      0xc726, 0xc726, 0xc726, 0xc726 };
++#endif
+ VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc2796b84, 0xc2796b84 };
+ VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc0e4a3d8, 0xc0e4a3d8,
+ 					   0xc0e4a3d8, 0xc0e4a3d8 };
+ 
+ /* Expected results with input=NaN.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_nan, hfloat, 16, 4) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00,
++						  0x7e00, 0x7e00 };
++#endif
+ VECT_VAR_DECL(expected_nan,hfloat,32,2) [] = { 0x7fc00000, 0x7fc00000 };
+ VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 					       0x7fc00000, 0x7fc00000 };
+ 
+ /* Expected results with FP special inputs values (infinity, 0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 4) [] = { 0xfc00, 0xfc00,
++						  0xfc00, 0xfc00 };
++VECT_VAR_DECL(expected_fp1, hfloat, 16, 8) [] = { 0x3e00, 0x3e00,
++						  0x3e00, 0x3e00,
++						  0x3e00, 0x3e00,
++						  0x3e00, 0x3e00 };
++#endif
+ VECT_VAR_DECL(expected_fp1,hfloat,32,2) [] = { 0xff800000, 0xff800000 };
+ VECT_VAR_DECL(expected_fp1,hfloat,32,4) [] = { 0x3fc00000, 0x3fc00000,
+ 					       0x3fc00000, 0x3fc00000 };
+ 
+ /* Expected results with only FP special inputs values (infinity,
+    0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 4) [] = { 0x3e00, 0x3e00,
++						  0x3e00, 0x3e00 };
++VECT_VAR_DECL(expected_fp2, hfloat, 16, 8) [] = { 0x3e00, 0x3e00,
++						  0x3e00, 0x3e00,
++						  0x3e00, 0x3e00,
++						  0x3e00, 0x3e00 };
++#endif
+ VECT_VAR_DECL(expected_fp2,hfloat,32,2) [] = { 0x3fc00000, 0x3fc00000 };
+ VECT_VAR_DECL(expected_fp2,hfloat,32,4) [] = { 0x3fc00000, 0x3fc00000,
+ 					       0x3fc00000, 0x3fc00000 };
+@@ -38,75 +67,143 @@ void exec_vrsqrts(void)
+ 		    VECT_VAR(vector_res, T1, W, N))
+ 
+   /* No need for integer variants.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector, float, 32, 2);
+   DECL_VARIABLE(vector, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector2, float, 32, 2);
+   DECL_VARIABLE(vector2, float, 32, 4);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++#endif
+   DECL_VARIABLE(vector_res, float, 32, 2);
+   DECL_VARIABLE(vector_res, float, 32, 4);
+ 
+   clean_results ();
+ 
+   /* Choose init value arbitrarily.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, 12.9f);
++  VDUP(vector, q, float, f, 16, 8, 9.1f);
++#endif
+   VDUP(vector, , float, f, 32, 2, 12.9f);
+   VDUP(vector, q, float, f, 32, 4, 9.1f);
+ 
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector2, , float, f, 16, 4, 9.9f);
++  VDUP(vector2, q, float, f, 16, 8, 1.9f);
++#endif
+   VDUP(vector2, , float, f, 32, 2, 9.9f);
+   VDUP(vector2, q, float, f, 32, 4, 1.9f);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTS(, float, f, 16, 4);
++  TEST_VRSQRTS(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTS(, float, f, 32, 2);
+   TEST_VRSQRTS(q, float, f, 32, 4);
+ 
+ #define CMT ""
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, CMT);
+ 
+ 
+   /* Test FP variants with special input values (NaN).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, NAN);
++  VDUP(vector2, q, float, f, 16, 8, NAN);
++#endif
+   VDUP(vector, , float, f, 32, 2, NAN);
+   VDUP(vector2, q, float, f, 32, 4, NAN);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTS(, float, f, 16, 4);
++  TEST_VRSQRTS(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTS(, float, f, 32, 2);
+   TEST_VRSQRTS(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (NAN) and normal values"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_nan, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_nan, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_nan, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_nan, CMT);
+ 
+ 
+   /* Test FP variants with special input values (infinity, 0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, HUGE_VALF);
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++  /* Restore a normal value in vector2.  */
++  VDUP(vector2, q, float, f, 16, 8, 3.2f);
++#endif
+   VDUP(vector, , float, f, 32, 2, HUGE_VALF);
+   VDUP(vector, q, float, f, 32, 4, 0.0f);
+   /* Restore a normal value in vector2.  */
+   VDUP(vector2, q, float, f, 32, 4, 3.2f);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTS(, float, f, 16, 4);
++  TEST_VRSQRTS(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTS(, float, f, 32, 2);
+   TEST_VRSQRTS(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " FP special (infinity, 0) and normal values"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp1, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp1, CMT);
+ 
+ 
+   /* Test FP variants with only special input values (infinity, 0).  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  VDUP(vector, , float, f, 16, 4, HUGE_VALF);
++  VDUP(vector, q, float, f, 16, 8, 0.0f);
++  VDUP(vector2, , float, f, 16, 4, -0.0f);
++  VDUP(vector2, q, float, f, 16, 8, HUGE_VALF);
++#endif
+   VDUP(vector, , float, f, 32, 2, HUGE_VALF);
+   VDUP(vector, q, float, f, 32, 4, 0.0f);
+   VDUP(vector2, , float, f, 32, 2, -0.0f);
+   VDUP(vector2, q, float, f, 32, 4, HUGE_VALF);
+ 
+   /* Apply the operator.  */
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  TEST_VRSQRTS(, float, f, 16, 4);
++  TEST_VRSQRTS(q, float, f, 16, 8);
++#endif
+   TEST_VRSQRTS(, float, f, 32, 2);
+   TEST_VRSQRTS(q, float, f, 32, 4);
+ 
+ #undef CMT
+ #define CMT " only FP special (infinity, 0)"
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_fp2, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_fp2, CMT);
++#endif
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_fp2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_fp2, CMT);
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c
+@@ -0,0 +1,50 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_fp16.h>
++
++/* Input values.  */
++#define A 12.4
++#define B -5.8
++#define C -3.8
++#define D 10
++#define E 66.1
++#define F 16.1
++#define G -4.8
++#define H -77
++
++#define I 0.7
++#define J -78
++#define K 10.23
++#define L 98
++#define M 87
++#define N -87.81
++#define O -1.1
++#define P 47.8
++
++float16_t input_1[] = { A, B, C, D, I, J, K, L };
++float16_t input_2[] = { E, F, G, H, M, N, O, P };
++uint16_t expected[] = { 0xDE62 /* (3.0f + (-A) * E) / 2.0f.  */,
++			0x5206 /* (3.0f + (-B) * F) / 2.0f.  */,
++			0xC7A0 /* (3.0f + (-C) * G) / 2.0f.  */,
++			0x5E0A /* (3.0f + (-D) * H) / 2.0f.  */,
++			0xCF3D /* (3.0f + (-I) * M) / 2.0f.  */,
++			0xEAB0 /* (3.0f + (-J) * N) / 2.0f.  */,
++			0x471F /* (3.0f + (-K) * O) / 2.0f.  */,
++			0xE893 /* (3.0f + (-L) * P) / 2.0f.  */ };
++
++#define TEST_MSG "VRSQRTSH_F16"
++#define INSN_NAME vrsqrtsh_f16
++
++#define INPUT_1 input_1
++#define INPUT_2 input_2
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc
+@@ -76,16 +76,16 @@ void FNNAME (INSN_NAME) (void)
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
+ 
+ #ifdef EXTRA_TESTS
+   EXTRA_TESTS();
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl.c
+@@ -101,10 +101,8 @@ VECT_VAR_DECL(expected_negative_shift,uint,64,2) [] = { 0x7ffffffffffffff,
+ 							0x7ffffffffffffff };
+ 
+ 
+-#ifndef INSN_NAME
+ #define INSN_NAME vshl
+ #define TEST_MSG "VSHL/VSHLQ"
+-#endif
+ 
+ #define FNNAME1(NAME) exec_ ## NAME
+ #define FNNAME(NAME) FNNAME1(NAME)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
+@@ -53,9 +53,17 @@ void FNNAME (INSN_NAME) (void)
+   DECL_VSHUFFLE(float, 32, 4)
+ 
+   DECL_ALL_VSHUFFLE();
++#if defined (FP16_SUPPORTED)
++  DECL_VSHUFFLE (float, 16, 4);
++  DECL_VSHUFFLE (float, 16, 8);
++#endif
+ 
+   /* Initialize input "vector" from "buffer".  */
+   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD (vector1, buffer, , float, f, 16, 4);
++  VLOAD (vector1, buffer, q, float, f, 16, 8);
++#endif
+   VLOAD(vector1, buffer, , float, f, 32, 2);
+   VLOAD(vector1, buffer, q, float, f, 32, 4);
+ 
+@@ -68,6 +76,9 @@ void FNNAME (INSN_NAME) (void)
+   VDUP(vector2, , uint, u, 32, 2, 0x77);
+   VDUP(vector2, , poly, p, 8, 8, 0x55);
+   VDUP(vector2, , poly, p, 16, 4, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, , float, f, 16, 4, 14.6f);   /* 14.6f is 0x4b4d.  */
++#endif
+   VDUP(vector2, , float, f, 32, 2, 33.6f);
+ 
+   VDUP(vector2, q, int, s, 8, 16, 0x11);
+@@ -78,8 +89,11 @@ void FNNAME (INSN_NAME) (void)
+   VDUP(vector2, q, uint, u, 32, 4, 0x77);
+   VDUP(vector2, q, poly, p, 8, 16, 0x55);
+   VDUP(vector2, q, poly, p, 16, 8, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, q, float, f, 16, 8, 14.6f);
++#endif
+   VDUP(vector2, q, float, f, 32, 4, 33.8f);
+-  
++
+ #define TEST_ALL_VSHUFFLE(INSN)				\
+   TEST_VSHUFFLE(INSN, , int, s, 8, 8);			\
+   TEST_VSHUFFLE(INSN, , int, s, 16, 4);			\
+@@ -100,6 +114,10 @@ void FNNAME (INSN_NAME) (void)
+   TEST_VSHUFFLE(INSN, q, poly, p, 16, 8);		\
+   TEST_VSHUFFLE(INSN, q, float, f, 32, 4)
+ 
++#define TEST_VSHUFFLE_FP16(INSN)		\
++  TEST_VSHUFFLE(INSN, , float, f, 16, 4);	\
++  TEST_VSHUFFLE(INSN, q, float, f, 16, 8);
++
+ #define TEST_ALL_EXTRA_CHUNKS()			\
+   TEST_EXTRA_CHUNK(int, 8, 8, 1);		\
+   TEST_EXTRA_CHUNK(int, 16, 4, 1);		\
+@@ -130,8 +148,8 @@ void FNNAME (INSN_NAME) (void)
+     CHECK(test_name, uint, 8, 8, PRIx8, EXPECTED, comment);		\
+     CHECK(test_name, uint, 16, 4, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 2, PRIx32, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 8, PRIx8, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 16, 4, PRIx16, EXPECTED, comment);		\
+     CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment);	\
+ 									\
+     CHECK(test_name, int, 8, 16, PRIx8, EXPECTED, comment);		\
+@@ -140,20 +158,40 @@ void FNNAME (INSN_NAME) (void)
+     CHECK(test_name, uint, 8, 16, PRIx8, EXPECTED, comment);		\
+     CHECK(test_name, uint, 16, 8, PRIx16, EXPECTED, comment);		\
+     CHECK(test_name, uint, 32, 4, PRIx32, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 8, 16, PRIx8, EXPECTED, comment);		\
+-    CHECK(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 8, 16, PRIx8, EXPECTED, comment);		\
++    CHECK_POLY(test_name, poly, 16, 8, PRIx16, EXPECTED, comment);		\
+     CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment);	\
+-  }									\
++  }
++
++#define CHECK_RESULTS_VSHUFFLE_FP16(test_name,EXPECTED,comment)		\
++  {									\
++    CHECK_FP (test_name, float, 16, 4, PRIx16, EXPECTED, comment);	\
++    CHECK_FP (test_name, float, 16, 8, PRIx16, EXPECTED, comment);	\
++  }
+ 
+   clean_results ();
+ 
+   /* Execute the tests.  */
+   TEST_ALL_VSHUFFLE(INSN_NAME);
++#if defined (FP16_SUPPORTED)
++  TEST_VSHUFFLE_FP16 (INSN_NAME);
++#endif
+ 
+   CHECK_RESULTS_VSHUFFLE (TEST_MSG, expected0, "(chunk 0)");
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS_VSHUFFLE_FP16 (TEST_MSG, expected0, "(chunk 0)");
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS();
++#if defined (FP16_SUPPORTED)
++  TEST_EXTRA_CHUNK (float, 16, 4, 1);
++  TEST_EXTRA_CHUNK (float, 16, 8, 1);
++#endif
++
+   CHECK_RESULTS_VSHUFFLE (TEST_MSG, expected1, "(chunk 1)");
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS_VSHUFFLE_FP16 (TEST_MSG, expected1, "(chunk 1)");
++#endif
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
+@@ -161,14 +161,16 @@ void vsli_extra(void)
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_shift, COMMENT);
++  CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT);
++  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT);
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c
+@@ -0,0 +1,72 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
++/* { dg-add-options arm_v8_2a_fp16_neon } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++#define FP16_C(a) ((__fp16) a)
++#define A FP16_C (123.4)
++#define B FP16_C (567.8)
++#define C FP16_C (34.8)
++#define D FP16_C (1024)
++#define E FP16_C (663.1)
++#define F FP16_C (144.0)
++#define G FP16_C (4.8)
++#define H FP16_C (77)
++
++#define SQRT_A 0x498E /* FP16_C (__builtin_sqrtf (123.4)).  */
++#define SQRT_B 0x4DF5 /* FP16_C (__builtin_sqrtf (567.8)).  */
++#define SQRT_C 0x45E6 /* FP16_C (__builtin_sqrtf (34.8)).  */
++#define SQRT_D 0x5000 /* FP16_C (__builtin_sqrtf (1024)).  */
++#define SQRT_E 0x4E70 /* FP16_C (__builtin_sqrtf (663.1)).  */
++#define SQRT_F 0x4A00 /* FP16_C (__builtin_sqrtf (144.0)).  */
++#define SQRT_G 0x4062 /* FP16_C (__builtin_sqrtf (4.8)).  */
++#define SQRT_H 0x4863 /* FP16_C (__builtin_sqrtf (77)).  */
++
++/* Expected results for vsqrt.  */
++VECT_VAR_DECL (expected_static, hfloat, 16, 4) []
++  = { SQRT_A, SQRT_B, SQRT_C, SQRT_D };
++
++VECT_VAR_DECL (expected_static, hfloat, 16, 8) []
++  = { SQRT_A, SQRT_B, SQRT_C, SQRT_D, SQRT_E, SQRT_F, SQRT_G, SQRT_H };
++
++void exec_vsqrt_f16 (void)
++{
++#undef TEST_MSG
++#define TEST_MSG "VSQRT (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 4);
++  VECT_VAR_DECL (buf_src, float, 16, 4) [] = {A, B, C, D};
++  VLOAD (vsrc, buf_src, , float, f, 16, 4);
++  DECL_VARIABLE (vector_res, float, 16, 4)
++    = vsqrt_f16 (VECT_VAR (vsrc, float, 16, 4));
++  vst1_f16 (VECT_VAR (result, float, 16, 4),
++	    VECT_VAR (vector_res, float, 16, 4));
++
++  CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected_static, "");
++
++#undef TEST_MSG
++#define TEST_MSG "VSQRTQ (FP16)"
++  clean_results ();
++
++  DECL_VARIABLE(vsrc, float, 16, 8);
++  VECT_VAR_DECL (buf_src, float, 16, 8) [] = {A, B, C, D, E, F, G, H};
++  VLOAD (vsrc, buf_src, q, float, f, 16, 8);
++  DECL_VARIABLE (vector_res, float, 16, 8)
++    = vsqrtq_f16 (VECT_VAR (vsrc, float, 16, 8));
++  vst1q_f16 (VECT_VAR (result, float, 16, 8),
++	     VECT_VAR (vector_res, float, 16, 8));
++
++  CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_static, "");
++}
++
++int
++main (void)
++{
++  exec_vsqrt_f16 ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0x0000 /* 0.000000 */,
++  0x8000 /* -0.000000 */,
++  0x3da8 /* 1.414062 */,
++  0x3f0b /* 1.760742 */,
++  0x4479 /* 4.472656 */,
++  0x390f /* 0.632324 */,
++  0x7e00 /* nan */,
++  0x3c9d /* 1.153320 */,
++  0x7e00 /* nan */,
++  0x3874 /* 0.556641 */,
++  0x38a2 /* 0.579102 */,
++  0x39a8 /* 0.707031 */,
++  0x3c00 /* 1.000000 */,
++  0x433f /* 3.623047 */,
++  0x7e00 /* nan */,
++  0x4479 /* 4.472656 */,
++  0x7c00 /* inf */,
++  0x7e00 /* nan */
++};
++
++#define TEST_MSG "VSQRTH_F16"
++#define INSN_NAME vsqrth_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for unary scalar operations.  */
++#include "unary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c
+@@ -163,14 +163,14 @@ void vsri_extra(void)
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_max_shift, COMMENT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 8, 16, PRIx8, expected_max_shift, COMMENT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_max_shift, COMMENT);
+ }
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ void
+ f_vst2_lane_f16 (float16_t * p, float16x4x2_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ void
+ f_vst2q_lane_f16 (float16_t * p, float16x8x2_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ void
+ f_vst3_lane_f16 (float16_t * p, float16x4x3_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ void
+ f_vst3q_lane_f16 (float16_t * p, float16x8x3_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ void
+ f_vst4_lane_f16 (float16_t * p, float16x4x4_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c
+@@ -2,6 +2,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
++/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */
+ 
+ void
+ f_vst4q_lane_f16 (float16_t * p, float16x8x4_t v)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
+@@ -14,6 +14,7 @@ VECT_VAR_DECL(expected_st2_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+ VECT_VAR_DECL(expected_st2_0,poly,8,8) [] = { 0xf0, 0xf1, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st2_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected_st2_0,int,16,8) [] = { 0xfff0, 0xfff1, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -24,6 +25,8 @@ VECT_VAR_DECL(expected_st2_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 					       0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st2_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0x0, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 						 0x0, 0x0 };
+ 
+@@ -39,6 +42,7 @@ VECT_VAR_DECL(expected_st2_1,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st2_1,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_1,hfloat,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -48,6 +52,8 @@ VECT_VAR_DECL(expected_st2_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ VECT_VAR_DECL(expected_st2_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st2_1,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st2_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results for vst3, chunk 0.  */
+@@ -62,6 +68,7 @@ VECT_VAR_DECL(expected_st3_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+ VECT_VAR_DECL(expected_st3_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0 };
++VECT_VAR_DECL(expected_st3_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0x0 };
+ VECT_VAR_DECL(expected_st3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected_st3_0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -73,6 +80,8 @@ VECT_VAR_DECL(expected_st3_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 					       0xfffffff2, 0x0 };
+ VECT_VAR_DECL(expected_st3_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st3_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 						 0xc1600000, 0x0 };
+ 
+@@ -88,6 +97,7 @@ VECT_VAR_DECL(expected_st3_1,uint,32,2) [] = { 0xfffffff2, 0x0 };
+ VECT_VAR_DECL(expected_st3_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st3_1,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_1,hfloat,32,2) [] = { 0xc1600000, 0x0 };
+ VECT_VAR_DECL(expected_st3_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -97,6 +107,8 @@ VECT_VAR_DECL(expected_st3_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ VECT_VAR_DECL(expected_st3_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st3_1,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results for vst3, chunk 2.  */
+@@ -111,6 +123,7 @@ VECT_VAR_DECL(expected_st3_2,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_2,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_2,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st3_2,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_2,hfloat,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_2,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -120,6 +133,8 @@ VECT_VAR_DECL(expected_st3_2,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ VECT_VAR_DECL(expected_st3_2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_2,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st3_2,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st3_2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results for vst4, chunk 0.  */
+@@ -134,6 +149,7 @@ VECT_VAR_DECL(expected_st4_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+ VECT_VAR_DECL(expected_st4_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
++VECT_VAR_DECL(expected_st4_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 };
+ VECT_VAR_DECL(expected_st4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected_st4_0,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -145,6 +161,8 @@ VECT_VAR_DECL(expected_st4_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 					       0xfffffff2, 0xfffffff3 };
+ VECT_VAR_DECL(expected_st4_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 						 0xc1600000, 0xc1500000 };
+ 
+@@ -160,6 +178,7 @@ VECT_VAR_DECL(expected_st4_1,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 };
+ VECT_VAR_DECL(expected_st4_1,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_1,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_1,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
+ VECT_VAR_DECL(expected_st4_1,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -169,6 +188,8 @@ VECT_VAR_DECL(expected_st4_1,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ VECT_VAR_DECL(expected_st4_1,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_1,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_1,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results for vst4, chunk 2.  */
+@@ -183,6 +204,7 @@ VECT_VAR_DECL(expected_st4_2,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_2,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_2,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_2,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_2,hfloat,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_2,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -192,6 +214,8 @@ VECT_VAR_DECL(expected_st4_2,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ VECT_VAR_DECL(expected_st4_2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_2,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_2,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
++					       0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Expected results for vst4, chunk 3.  */
+@@ -206,6 +230,7 @@ VECT_VAR_DECL(expected_st4_3,uint,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_3,poly,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_3,poly,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_3,hfloat,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_3,hfloat,32,2) [] = { 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_3,int,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					      0x0, 0x0, 0x0, 0x0 };
+@@ -215,6 +240,8 @@ VECT_VAR_DECL(expected_st4_3,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ VECT_VAR_DECL(expected_st4_3,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_3,poly,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
+ 					       0x0, 0x0, 0x0, 0x0 };
++VECT_VAR_DECL(expected_st4_3,hfloat,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
++						 0x0, 0x0, 0x0, 0x0 };
+ VECT_VAR_DECL(expected_st4_3,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+ 
+ /* Declare additional input buffers as needed.  */
+@@ -229,6 +256,9 @@ VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 32, 2);
+ VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 64, 2);
+ VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 8, 2);
+ VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 16, 2);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++VECT_VAR_DECL_INIT(buffer_vld2_lane, float, 16, 2);
++#endif
+ VECT_VAR_DECL_INIT(buffer_vld2_lane, float, 32, 2);
+ 
+ /* Input buffers for vld3_lane.  */
+@@ -242,6 +272,9 @@ VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 32, 3);
+ VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 64, 3);
+ VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 8, 3);
+ VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 16, 3);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++VECT_VAR_DECL_INIT(buffer_vld3_lane, float, 16, 3);
++#endif
+ VECT_VAR_DECL_INIT(buffer_vld3_lane, float, 32, 3);
+ 
+ /* Input buffers for vld4_lane.  */
+@@ -255,6 +288,9 @@ VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 32, 4);
+ VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 64, 4);
+ VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 8, 4);
+ VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 16, 4);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++VECT_VAR_DECL_INIT(buffer_vld4_lane, float, 16, 4);
++#endif
+ VECT_VAR_DECL_INIT(buffer_vld4_lane, float, 32, 4);
+ 
+ void exec_vstX_lane (void)
+@@ -302,7 +338,7 @@ void exec_vstX_lane (void)
+ 
+   /* We need all variants in 64 bits, but there is no 64x2 variant,
+      nor 128 bits vectors of int8/uint8/poly8.  */
+-#define DECL_ALL_VSTX_LANE(X)			\
++#define DECL_ALL_VSTX_LANE_NO_FP16(X)		\
+   DECL_VSTX_LANE(int, 8, 8, X);			\
+   DECL_VSTX_LANE(int, 16, 4, X);		\
+   DECL_VSTX_LANE(int, 32, 2, X);		\
+@@ -319,11 +355,20 @@ void exec_vstX_lane (void)
+   DECL_VSTX_LANE(poly, 16, 8, X);		\
+   DECL_VSTX_LANE(float, 32, 4, X)
+ 
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++#define DECL_ALL_VSTX_LANE(X)		\
++  DECL_ALL_VSTX_LANE_NO_FP16(X);	\
++  DECL_VSTX_LANE(float, 16, 4, X);	\
++  DECL_VSTX_LANE(float, 16, 8, X)
++#else
++#define DECL_ALL_VSTX_LANE(X) DECL_ALL_VSTX_LANE_NO_FP16(X)
++#endif
++
+ #define DUMMY_ARRAY(V, T, W, N, L) VECT_VAR_DECL(V,T,W,N)[N*L]
+ 
+   /* Use the same lanes regardless of the size of the array (X), for
+      simplicity.  */
+-#define TEST_ALL_VSTX_LANE(X)			\
++#define TEST_ALL_VSTX_LANE_NO_FP16(X)		\
+   TEST_VSTX_LANE(, int, s, 8, 8, X, 7);		\
+   TEST_VSTX_LANE(, int, s, 16, 4, X, 2);	\
+   TEST_VSTX_LANE(, int, s, 32, 2, X, 0);	\
+@@ -340,7 +385,16 @@ void exec_vstX_lane (void)
+   TEST_VSTX_LANE(q, poly, p, 16, 8, X, 5);	\
+   TEST_VSTX_LANE(q, float, f, 32, 4, X, 2)
+ 
+-#define TEST_ALL_EXTRA_CHUNKS(X, Y)		\
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++#define TEST_ALL_VSTX_LANE(X)			\
++  TEST_ALL_VSTX_LANE_NO_FP16(X);		\
++  TEST_VSTX_LANE(, float, f, 16, 4, X, 2);	\
++  TEST_VSTX_LANE(q, float, f, 16, 8, X, 6)
++#else
++#define TEST_ALL_VSTX_LANE(X) TEST_ALL_VSTX_LANE_NO_FP16(X)
++#endif
++
++#define TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y)	\
+   TEST_EXTRA_CHUNK(int, 8, 8, X, Y);		\
+   TEST_EXTRA_CHUNK(int, 16, 4, X, Y);		\
+   TEST_EXTRA_CHUNK(int, 32, 2, X, Y);		\
+@@ -357,6 +411,15 @@ void exec_vstX_lane (void)
+   TEST_EXTRA_CHUNK(poly, 16, 8, X, Y);		\
+   TEST_EXTRA_CHUNK(float, 32, 4, X, Y)
+ 
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++#define TEST_ALL_EXTRA_CHUNKS(X,Y)		\
++  TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y);		\
++  TEST_EXTRA_CHUNK(float, 16, 4, X, Y);		\
++  TEST_EXTRA_CHUNK(float, 16, 8, X, Y)
++#else
++#define TEST_ALL_EXTRA_CHUNKS(X,Y) TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y)
++#endif
++
+   /* Declare the temporary buffers / variables.  */
+   DECL_ALL_VSTX_LANE(2);
+   DECL_ALL_VSTX_LANE(3);
+@@ -371,12 +434,18 @@ void exec_vstX_lane (void)
+   DUMMY_ARRAY(buffer_src, uint, 32, 2, 4);
+   DUMMY_ARRAY(buffer_src, poly, 8, 8, 4);
+   DUMMY_ARRAY(buffer_src, poly, 16, 4, 4);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  DUMMY_ARRAY(buffer_src, float, 16, 4, 4);
++#endif
+   DUMMY_ARRAY(buffer_src, float, 32, 2, 4);
+   DUMMY_ARRAY(buffer_src, int, 16, 8, 4);
+   DUMMY_ARRAY(buffer_src, int, 32, 4, 4);
+   DUMMY_ARRAY(buffer_src, uint, 16, 8, 4);
+   DUMMY_ARRAY(buffer_src, uint, 32, 4, 4);
+   DUMMY_ARRAY(buffer_src, poly, 16, 8, 4);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  DUMMY_ARRAY(buffer_src, float, 16, 8, 4);
++#endif
+   DUMMY_ARRAY(buffer_src, float, 32, 4, 4);
+ 
+   /* Check vst2_lane/vst2q_lane.  */
+@@ -391,15 +460,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st2_0, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st2_0, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st2_0, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st2_0, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st2_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st2_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st2_0, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st2_0, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st2_0, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st2_0, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st2_0, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st2_0, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_0, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st2_0, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st2_0, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st2_0, CMT);
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS(2, 1);
+ #undef CMT
+@@ -410,15 +483,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st2_1, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st2_1, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st2_1, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st2_1, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st2_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st2_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st2_1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st2_1, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st2_1, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st2_1, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st2_1, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st2_1, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st2_1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st2_1, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st2_1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st2_1, CMT);
++#endif
+ 
+ 
+   /* Check vst3_lane/vst3q_lane.  */
+@@ -435,15 +512,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st3_0, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st3_0, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st3_0, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_0, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_0, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st3_0, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st3_0, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st3_0, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st3_0, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_0, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_0, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_0, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st3_0, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st3_0, CMT);
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS(3, 1);
+ 
+@@ -455,15 +536,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st3_1, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st3_1, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st3_1, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_1, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st3_1, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st3_1, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st3_1, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st3_1, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_1, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_1, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st3_1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st3_1, CMT);
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS(3, 2);
+ 
+@@ -475,15 +560,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st3_2, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st3_2, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st3_2, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_2, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_2, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st3_2, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st3_2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st3_2, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st3_2, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st3_2, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st3_2, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st3_2, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_2, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st3_2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st3_2, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st3_2, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st3_2, CMT);
++#endif
+ 
+ 
+   /* Check vst4_lane/vst4q_lane.  */
+@@ -500,15 +589,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_0, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_0, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_0, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_0, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_0, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st4_0, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_0, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st4_0, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st4_0, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_0, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_0, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_0, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_0, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_0, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_0, CMT);
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS(4, 1);
+ 
+@@ -520,15 +613,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_1, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_1, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_1, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_1, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st4_1, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_1, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st4_1, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st4_1, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_1, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_1, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_1, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_1, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_1, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_1, CMT);
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS(4, 2);
+ 
+@@ -540,15 +637,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_2, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_2, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_2, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_2, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_2, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_2, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st4_2, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_2, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st4_2, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st4_2, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_2, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_2, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_2, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_2, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_2, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_2, CMT);
++#endif
+ 
+   TEST_ALL_EXTRA_CHUNKS(4, 3);
+ 
+@@ -560,15 +661,19 @@ void exec_vstX_lane (void)
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_st4_3, CMT);
+   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_st4_3, CMT);
+   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_st4_3, CMT);
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_3, CMT);
+-  CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_3, CMT);
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_st4_3, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 4, PRIx16, expected_st4_3, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_st4_3, CMT);
+   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_st4_3, CMT);
+   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_st4_3, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_st4_3, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_st4_3, CMT);
+-  CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_3, CMT);
++  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected_st4_3, CMT);
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_st4_3, CMT);
++#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_st4_3, CMT);
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_st4_3, CMT);
++#endif
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsub.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsub.c
+@@ -44,6 +44,14 @@ VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffffed,
+ VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0xc00ccccd, 0xc00ccccd };
+ VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0xc00ccccc, 0xc00ccccc,
+ 						   0xc00ccccc, 0xc00ccccc };
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++VECT_VAR_DECL(expected_float16, hfloat, 16, 4) [] = { 0xc066, 0xc066,
++						      0xc066, 0xc066 };
++VECT_VAR_DECL(expected_float16, hfloat, 16, 8) [] = { 0xc067, 0xc067,
++						      0xc067, 0xc067,
++						      0xc067, 0xc067,
++						      0xc067, 0xc067 };
++#endif
+ 
+ void exec_vsub_f32(void)
+ {
+@@ -67,4 +75,27 @@ void exec_vsub_f32(void)
+ 
+   CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, "");
+   CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, "");
++
++#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++  DECL_VARIABLE(vector, float, 16, 4);
++  DECL_VARIABLE(vector, float, 16, 8);
++
++  DECL_VARIABLE(vector2, float, 16, 4);
++  DECL_VARIABLE(vector2, float, 16, 8);
++
++  DECL_VARIABLE(vector_res, float, 16, 4);
++  DECL_VARIABLE(vector_res, float, 16, 8);
++
++  VDUP(vector, , float, f, 16, 4, 2.3f);
++  VDUP(vector, q, float, f, 16, 8, 3.4f);
++
++  VDUP(vector2, , float, f, 16, 4, 4.5f);
++  VDUP(vector2, q, float, f, 16, 8, 5.6f);
++
++  TEST_BINARY_OP(INSN_NAME, , float, f, 16, 4);
++  TEST_BINARY_OP(INSN_NAME, q, float, f, 16, 8);
++
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_float16, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_float16, "");
++#endif
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++#include <arm_fp16.h>
++
++#define INFF __builtin_inf ()
++
++/* Expected results (16-bit hexadecimal representation).  */
++uint16_t expected[] =
++{
++  0xbc00 /* -1.000000 */,
++  0xbc00 /* -1.000000 */,
++  0x4654 /* 6.328125 */,
++  0xd60e /* -96.875000 */,
++  0xc900 /* -10.000000 */,
++  0x36b8 /* 0.419922 */,
++  0xc19a /* -2.800781 */,
++  0x4848 /* 8.562500 */,
++  0xbd34 /* -1.300781 */,
++  0xccec /* -19.687500 */,
++  0x4791 /* 7.566406 */,
++  0xbf34 /* -1.800781 */,
++  0x484d /* 8.601562 */,
++  0x4804 /* 8.031250 */,
++  0xc69c /* -6.609375 */,
++  0x4ceb /* 19.671875 */,
++  0x7c00 /* inf */,
++  0xfc00 /* -inf */
++};
++
++#define TEST_MSG "VSUB_F16"
++#define INSN_NAME vsubh_f16
++
++#define EXPECTED expected
++
++#define INPUT_TYPE float16_t
++#define OUTPUT_TYPE float16_t
++#define OUTPUT_TYPE_SIZE 16
++
++/* Include the template for binary scalar operations.  */
++#include "binary_scalar_op.inc"
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c
+@@ -167,7 +167,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbl1, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbl1, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl1, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl1, "");
+ 
+   /* Check vtbl2.  */
+   clean_results ();
+@@ -177,7 +177,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbl2, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbl2, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl2, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl2, "");
+ 
+   /* Check vtbl3.  */
+   clean_results ();
+@@ -187,7 +187,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbl3, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbl3, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl3, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl3, "");
+ 
+   /* Check vtbl4.  */
+   clean_results ();
+@@ -197,7 +197,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbl4, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbl4, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl4, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbl4, "");
+ 
+ 
+   /* Now test VTBX.  */
+@@ -249,7 +249,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbx1, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbx1, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx1, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx1, "");
+ 
+   /* Check vtbx2.  */
+   clean_results ();
+@@ -259,7 +259,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbx2, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbx2, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx2, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx2, "");
+ 
+   /* Check vtbx3.  */
+   clean_results ();
+@@ -269,7 +269,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbx3, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbx3, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx3, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx3, "");
+ 
+   /* Check vtbx4.  */
+   clean_results ();
+@@ -279,7 +279,7 @@ void exec_vtbX (void)
+ 
+   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_vtbx4, "");
+   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_vtbx4, "");
+-  CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx4, "");
++  CHECK_POLY(TEST_MSG, poly, 8, 8, PRIx8, expected_vtbx4, "");
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c
+@@ -15,6 +15,10 @@ VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+ VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55,
+ 					 0xf2, 0xf3, 0x55, 0x55 };
+ VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11,
+ 					 0xf2, 0xf3, 0x11, 0x11,
+@@ -36,6 +40,12 @@ VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55,
+ 					  0xf6, 0xf7, 0x55, 0x55 };
+ VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff1, 0x66, 0x66,
+ 					  0xfff2, 0xfff3, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++						0x4b4d, 0x4b4d,
++						0xcb00, 0xca80,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 					    0x42073333, 0x42073333 };
+ 
+@@ -51,6 +61,10 @@ VECT_VAR_DECL(expected1,uint,32,2) [] = { 0x77, 0x77 };
+ VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf4, 0xf5, 0x55, 0x55,
+ 					 0xf6, 0xf7, 0x55, 0x55 };
+ VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 4) [] = { 0xcb00, 0xca80,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0x42066666, 0x42066666 };
+ VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf8, 0xf9, 0x11, 0x11,
+ 					 0xfa, 0xfb, 0x11, 0x11,
+@@ -72,6 +86,12 @@ VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf8, 0xf9, 0x55, 0x55,
+ 					  0xfe, 0xff, 0x55, 0x55 };
+ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff4, 0xfff5, 0x66, 0x66,
+ 					  0xfff6, 0xfff7, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 8) [] = { 0xca00, 0xc980,
++						0x4b4d, 0x4b4d,
++						0xc900, 0xc880,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1600000, 0xc1500000,
+ 					    0x42073333, 0x42073333 };
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c
+@@ -0,0 +1,263 @@
++/* { dg-do run } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0x11, 0xf2, 0x11,
++				       0xf4, 0x11, 0xf6, 0x11 };
++VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0x22, 0xfff2, 0x22 };
++VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0x33 };
++VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0x55, 0xf2, 0x55,
++					0xf4, 0x55, 0xf6, 0x55 };
++VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0x66, 0xfff2, 0x66 };
++VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0x77 };
++VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0x55, 0xf2, 0x55,
++					0xf4, 0x55, 0xf6, 0x55 };
++VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0x66, 0xfff2, 0x66 };
++VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0x42066666 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0x4b4d,
++					       0xcb00, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0x11, 0xf2, 0x11,
++					0xf4, 0x11, 0xf6, 0x11,
++					0xf8, 0x11, 0xfa, 0x11,
++					0xfc, 0x11, 0xfe, 0x11 };
++VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0x22, 0xfff2, 0x22,
++					0xfff4, 0x22, 0xfff6, 0x22 };
++VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0x33,
++					0xfffffff2, 0x33 };
++VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
++					0x44 };
++VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0x55, 0xf2, 0x55,
++					 0xf4, 0x55, 0xf6, 0x55,
++					 0xf8, 0x55, 0xfa, 0x55,
++					 0xfc, 0x55, 0xfe, 0x55 };
++VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0x66, 0xfff2, 0x66,
++					 0xfff4, 0x66, 0xfff6, 0x66 };
++VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0x77,
++					 0xfffffff2, 0x77 };
++VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
++					 0x88 };
++VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0x55, 0xf2, 0x55,
++					 0xf4, 0x55, 0xf6, 0x55,
++					 0xf8, 0x55, 0xfa, 0x55,
++					 0xfc, 0x55, 0xfe, 0x55 };
++VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0x66, 0xfff2, 0x66,
++					 0xfff4, 0x66, 0xfff6, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0x4b4d,
++					       0xcb00, 0x4b4d,
++					       0xca00, 0x4b4d,
++					       0xc900, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0x42073333,
++					   0xc1600000, 0x42073333 };
++
++#define TEST_MSG "VTRN1"
++void exec_vtrn_half (void)
++{
++#define TEST_VTRN(PART, Q, T1, T2, W, N)		\
++  VECT_VAR(vector_res, T1, W, N) =			\
++    vtrn##PART##Q##_##T2##W(VECT_VAR(vector, T1, W, N),	\
++		       VECT_VAR(vector2, T1, W, N));	\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
++
++#define TEST_VTRN1(Q, T1, T2, W, N) TEST_VTRN(1, Q, T1, T2, W, N)
++
++  /* Input vector can only have 64 bits.  */
++  DECL_VARIABLE_ALL_VARIANTS(vector);
++  DECL_VARIABLE_ALL_VARIANTS(vector2);
++  DECL_VARIABLE(vector, float, 64, 2);
++  DECL_VARIABLE(vector2, float, 64, 2);
++
++  DECL_VARIABLE_ALL_VARIANTS(vector_res);
++  DECL_VARIABLE(vector_res, float, 64, 2);
++
++  clean_results ();
++  /* We don't have vtrn1_T64x1, so set expected to the clean value.  */
++  CLEAN(expected, int, 64, 1);
++  CLEAN(expected, uint, 64, 1);
++
++  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD(vector, buffer, , float, f, 32, 2);
++  VLOAD(vector, buffer, q, float, f, 32, 4);
++  VLOAD(vector, buffer, q, float, f, 64, 2);
++
++  /* Choose arbitrary initialization values.  */
++  VDUP(vector2, , int, s, 8, 8, 0x11);
++  VDUP(vector2, , int, s, 16, 4, 0x22);
++  VDUP(vector2, , int, s, 32, 2, 0x33);
++  VDUP(vector2, , uint, u, 8, 8, 0x55);
++  VDUP(vector2, , uint, u, 16, 4, 0x66);
++  VDUP(vector2, , uint, u, 32, 2, 0x77);
++  VDUP(vector2, , poly, p, 8, 8, 0x55);
++  VDUP(vector2, , poly, p, 16, 4, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, , float, f, 16, 4, 14.6f);   /* 14.6f is 0x4b4d.  */
++#endif
++  VDUP(vector2, , float, f, 32, 2, 33.6f);
++
++  VDUP(vector2, q, int, s, 8, 16, 0x11);
++  VDUP(vector2, q, int, s, 16, 8, 0x22);
++  VDUP(vector2, q, int, s, 32, 4, 0x33);
++  VDUP(vector2, q, int, s, 64, 2, 0x44);
++  VDUP(vector2, q, uint, u, 8, 16, 0x55);
++  VDUP(vector2, q, uint, u, 16, 8, 0x66);
++  VDUP(vector2, q, uint, u, 32, 4, 0x77);
++  VDUP(vector2, q, uint, u, 64, 2, 0x88);
++  VDUP(vector2, q, poly, p, 8, 16, 0x55);
++  VDUP(vector2, q, poly, p, 16, 8, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, q, float, f, 16, 8, 14.6f);
++#endif
++  VDUP(vector2, q, float, f, 32, 4, 33.8f);
++  VDUP(vector2, q, float, f, 64, 2, 33.8f);
++
++  TEST_VTRN1(, int, s, 8, 8);
++  TEST_VTRN1(, int, s, 16, 4);
++  TEST_VTRN1(, int, s, 32, 2);
++  TEST_VTRN1(, uint, u, 8, 8);
++  TEST_VTRN1(, uint, u, 16, 4);
++  TEST_VTRN1(, uint, u, 32, 2);
++  TEST_VTRN1(, poly, p, 8, 8);
++  TEST_VTRN1(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++  TEST_VTRN1(, float, f, 16, 4);
++#endif
++  TEST_VTRN1(, float, f, 32, 2);
++
++  TEST_VTRN1(q, int, s, 8, 16);
++  TEST_VTRN1(q, int, s, 16, 8);
++  TEST_VTRN1(q, int, s, 32, 4);
++  TEST_VTRN1(q, int, s, 64, 2);
++  TEST_VTRN1(q, uint, u, 8, 16);
++  TEST_VTRN1(q, uint, u, 16, 8);
++  TEST_VTRN1(q, uint, u, 32, 4);
++  TEST_VTRN1(q, uint, u, 64, 2);
++  TEST_VTRN1(q, poly, p, 8, 16);
++  TEST_VTRN1(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VTRN1(q, float, f, 16, 8);
++#endif
++  TEST_VTRN1(q, float, f, 32, 4);
++  TEST_VTRN1(q, float, f, 64, 2);
++
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS (TEST_MSG, "");
++#else
++  CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
++#endif
++
++#undef TEST_MSG
++#define TEST_MSG "VTRN2"
++
++#define TEST_VTRN2(Q, T1, T2, W, N) TEST_VTRN(2, Q, T1, T2, W, N)
++
++/* Expected results.  */
++VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf1, 0x11, 0xf3, 0x11,
++					0xf5, 0x11, 0xf7, 0x11 };
++VECT_VAR_DECL(expected2,int,16,4) [] = { 0xfff1, 0x22, 0xfff3, 0x22 };
++VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 };
++VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xf1, 0x55, 0xf3, 0x55,
++					 0xf5, 0x55, 0xf7, 0x55 };
++VECT_VAR_DECL(expected2,uint,16,4) [] = { 0xfff1, 0x66, 0xfff3, 0x66 };
++VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 };
++VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf1, 0x55, 0xf3, 0x55,
++					 0xf5, 0x55, 0xf7, 0x55 };
++VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff1, 0x66, 0xfff3, 0x66 };
++VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1700000, 0x42066666 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb80, 0x4b4d,
++						0xca80, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf1, 0x11, 0xf3, 0x11,
++					 0xf5, 0x11, 0xf7, 0x11,
++					 0xf9, 0x11, 0xfb, 0x11,
++					 0xfd, 0x11, 0xff, 0x11 };
++VECT_VAR_DECL(expected2,int,16,8) [] = { 0xfff1, 0x22, 0xfff3, 0x22,
++					 0xfff5, 0x22, 0xfff7, 0x22 };
++VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0x33,
++					 0xfffffff3, 0x33 };
++VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1,
++					 0x44 };
++VECT_VAR_DECL(expected2,uint,8,16) [] = { 0xf1, 0x55, 0xf3, 0x55,
++					  0xf5, 0x55, 0xf7, 0x55,
++					  0xf9, 0x55, 0xfb, 0x55,
++					  0xfd, 0x55, 0xff, 0x55 };
++VECT_VAR_DECL(expected2,uint,16,8) [] = { 0xfff1, 0x66, 0xfff3, 0x66,
++					  0xfff5, 0x66, 0xfff7, 0x66 };
++VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff1, 0x77,
++					  0xfffffff3, 0x77 };
++VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1,
++					  0x88 };
++VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf1, 0x55, 0xf3, 0x55,
++					  0xf5, 0x55, 0xf7, 0x55,
++					  0xf9, 0x55, 0xfb, 0x55,
++					  0xfd, 0x55, 0xff, 0x55 };
++VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff1, 0x66, 0xfff3, 0x66,
++					  0xfff5, 0x66, 0xfff7, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xcb80, 0x4b4d,
++						0xca80, 0x4b4d,
++						0xc980, 0x4b4d,
++						0xc880, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1700000, 0x42073333,
++					    0xc1500000, 0x42073333 };
++  clean_results ();
++  CLEAN(expected2, int, 64, 1);
++  CLEAN(expected2, uint, 64, 1);
++
++  TEST_VTRN2(, int, s, 8, 8);
++  TEST_VTRN2(, int, s, 16, 4);
++  TEST_VTRN2(, int, s, 32, 2);
++  TEST_VTRN2(, uint, u, 8, 8);
++  TEST_VTRN2(, uint, u, 16, 4);
++  TEST_VTRN2(, uint, u, 32, 2);
++  TEST_VTRN2(, poly, p, 8, 8);
++  TEST_VTRN2(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++  TEST_VTRN2(, float, f, 16, 4);
++#endif
++  TEST_VTRN2(, float, f, 32, 2);
++
++  TEST_VTRN2(q, int, s, 8, 16);
++  TEST_VTRN2(q, int, s, 16, 8);
++  TEST_VTRN2(q, int, s, 32, 4);
++  TEST_VTRN2(q, int, s, 64, 2);
++  TEST_VTRN2(q, uint, u, 8, 16);
++  TEST_VTRN2(q, uint, u, 16, 8);
++  TEST_VTRN2(q, uint, u, 32, 4);
++  TEST_VTRN2(q, uint, u, 64, 2);
++  TEST_VTRN2(q, poly, p, 8, 16);
++  TEST_VTRN2(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VTRN2(q, float, f, 16, 8);
++#endif
++  TEST_VTRN2(q, float, f, 32, 4);
++  TEST_VTRN2(q, float, f, 64, 2);
++
++  CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
++#if defined (FP16_SUPPORTED)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected2, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected2, "");
++#endif
++}
++
++int main (void)
++{
++  exec_vtrn_half ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
+@@ -32,10 +32,21 @@ VECT_VAR_DECL(expected_unsigned,uint,16,8) [] = { 0x0, 0xffff,
+ VECT_VAR_DECL(expected_unsigned,uint,32,4) [] = { 0x0, 0xffffffff,
+ 						  0x0, 0xffffffff };
+ 
+-#ifndef INSN_NAME
++/* Expected results with poly input.  */
++VECT_VAR_DECL(expected_poly,uint,8,8) [] = { 0x0, 0xff, 0xff, 0xff,
++					     0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected_poly,uint,8,16) [] = { 0x0, 0xff, 0xff, 0xff,
++					      0xff, 0xff, 0xff, 0xff,
++					      0xff, 0xff, 0xff, 0xff,
++					      0xff, 0xff, 0xff, 0xff };
++VECT_VAR_DECL(expected_poly,uint,16,4) [] = { 0x0, 0xffff, 0x0, 0xffff };
++VECT_VAR_DECL(expected_poly,uint,16,8) [] = { 0x0, 0xffff,
++					      0x0, 0xffff,
++					      0xffff, 0xffff,
++					      0xffff, 0xffff };
++
+ #define INSN_NAME vtst
+ #define TEST_MSG "VTST/VTSTQ"
+-#endif
+ 
+ /* We can't use the standard ref_v_binary_op.c template because vtst
+    has no 64 bits variant, and outputs are always of uint type.  */
+@@ -73,12 +84,16 @@ FNNAME (INSN_NAME)
+   VDUP(vector2, , uint, u, 8, 8, 15);
+   VDUP(vector2, , uint, u, 16, 4, 5);
+   VDUP(vector2, , uint, u, 32, 2, 1);
++  VDUP(vector2, , poly, p, 8, 8, 15);
++  VDUP(vector2, , poly, p, 16, 4, 5);
+   VDUP(vector2, q, int, s, 8, 16, 15);
+   VDUP(vector2, q, int, s, 16, 8, 5);
+   VDUP(vector2, q, int, s, 32, 4, 1);
+   VDUP(vector2, q, uint, u, 8, 16, 15);
+   VDUP(vector2, q, uint, u, 16, 8, 5);
+   VDUP(vector2, q, uint, u, 32, 4, 1);
++  VDUP(vector2, q, poly, p, 8, 16, 15);
++  VDUP(vector2, q, poly, p, 16, 8, 5);
+ 
+ #define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR, T1, T2)	\
+   MACRO(VAR, , T1, T2, 8, 8);					\
+@@ -111,6 +126,18 @@ FNNAME (INSN_NAME)
+   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_unsigned, CMT);
+   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_unsigned, CMT);
+   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_unsigned, CMT);
++
++  /* Now, test the variants with poly8 and poly16 as input.  */
++#undef CMT
++#define CMT " (poly input)"
++  TEST_BINARY_OP(INSN_NAME, , poly, p, 8, 8);
++  TEST_BINARY_OP(INSN_NAME, , poly, p, 16, 4);
++  TEST_BINARY_OP(INSN_NAME, q, poly, p, 8, 16);
++  TEST_BINARY_OP(INSN_NAME, q, poly, p, 16, 8);
++  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_poly, CMT);
++  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_poly, CMT);
++  CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_poly, CMT);
++  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_poly, CMT);
+ }
+ 
+ int main (void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
+@@ -19,6 +19,10 @@ VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					 0xf4, 0xf5, 0xf6, 0xf7 };
+ VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1,
+ 					  0xfff2, 0xfff3 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb80,
++						0xcb00, 0xca80 };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 					 0xf4, 0xf5, 0xf6, 0xf7,
+@@ -48,6 +52,12 @@ VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff1,
+ 					  0xfff2, 0xfff3,
+ 					  0xfff4, 0xfff5,
+ 					  0xfff6, 0xfff7 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 8) [] = { 0xcc00, 0xcb80,
++						0xcb00, 0xca80,
++						0xca00, 0xc980,
++						0xc900, 0xc880 };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 					    0xc1600000, 0xc1500000 };
+ 
+@@ -63,6 +73,10 @@ VECT_VAR_DECL(expected1,uint,32,2) [] = { 0x77, 0x77 };
+ VECT_VAR_DECL(expected1,poly,8,8) [] = { 0x55, 0x55, 0x55, 0x55,
+ 					 0x55, 0x55, 0x55, 0x55 };
+ VECT_VAR_DECL(expected1,poly,16,4) [] = { 0x66, 0x66, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 4) [] = { 0x4b4d, 0x4b4d,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0x42066666, 0x42066666 };
+ VECT_VAR_DECL(expected1,int,8,16) [] = { 0x11, 0x11, 0x11, 0x11,
+ 					 0x11, 0x11, 0x11, 0x11,
+@@ -84,6 +98,12 @@ VECT_VAR_DECL(expected1,poly,8,16) [] = { 0x55, 0x55, 0x55, 0x55,
+ 					  0x55, 0x55, 0x55, 0x55 };
+ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0x66, 0x66, 0x66, 0x66,
+ 					  0x66, 0x66, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 8) [] = { 0x4b4d, 0x4b4d,
++						0x4b4d, 0x4b4d,
++						0x4b4d, 0x4b4d,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0x42073333, 0x42073333,
+ 					    0x42073333, 0x42073333 };
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c
+@@ -0,0 +1,259 @@
++/* { dg-do run } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
++				       0x11, 0x11, 0x11, 0x11 };
++VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff2, 0x22, 0x22 };
++VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0x33 };
++VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
++					0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0x66, 0x66 };
++VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0x77 };
++VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
++					0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0xfff2, 0x66, 0x66 };
++VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0x42066666 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0xcb00,
++					       0x4b4d, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
++					0xf8, 0xfa, 0xfc, 0xfe,
++					0x11, 0x11, 0x11, 0x11,
++					0x11, 0x11, 0x11, 0x11 };
++VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff2, 0xfff4, 0xfff6,
++					0x22, 0x22, 0x22, 0x22 };
++VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff2,
++					0x33, 0x33 };
++VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
++					0x44 };
++VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
++					 0xf8, 0xfa, 0xfc, 0xfe,
++					 0x55, 0x55, 0x55, 0x55,
++					 0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff2, 0xfff4, 0xfff6,
++					 0x66, 0x66, 0x66, 0x66 };
++VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff2, 0x77, 0x77 };
++VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
++					 0x88 };
++VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
++					 0xf8, 0xfa, 0xfc, 0xfe,
++					 0x55, 0x55, 0x55, 0x55,
++					 0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff2, 0xfff4, 0xfff6,
++					 0x66, 0x66, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb00, 0xca00, 0xc900,
++					       0x4b4d, 0x4b4d, 0x4b4d, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1600000,
++					   0x42073333, 0x42073333 };
++
++#define TEST_MSG "VUZP1"
++void exec_vuzp_half (void)
++{
++#define TEST_VUZP(PART, Q, T1, T2, W, N)		\
++  VECT_VAR(vector_res, T1, W, N) =			\
++    vuzp##PART##Q##_##T2##W(VECT_VAR(vector, T1, W, N),	\
++		       VECT_VAR(vector2, T1, W, N));	\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
++
++#define TEST_VUZP1(Q, T1, T2, W, N) TEST_VUZP(1, Q, T1, T2, W, N)
++
++  /* Input vector can only have 64 bits.  */
++  DECL_VARIABLE_ALL_VARIANTS(vector);
++  DECL_VARIABLE_ALL_VARIANTS(vector2);
++  DECL_VARIABLE(vector, float, 64, 2);
++  DECL_VARIABLE(vector2, float, 64, 2);
++
++  DECL_VARIABLE_ALL_VARIANTS(vector_res);
++  DECL_VARIABLE(vector_res, float, 64, 2);
++
++  clean_results ();
++  /* We don't have vuzp1_T64x1, so set expected to the clean value.  */
++  CLEAN(expected, int, 64, 1);
++  CLEAN(expected, uint, 64, 1);
++
++  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD(vector, buffer, , float, f, 32, 2);
++  VLOAD(vector, buffer, q, float, f, 32, 4);
++  VLOAD(vector, buffer, q, float, f, 64, 2);
++
++  /* Choose arbitrary initialization values.  */
++  VDUP(vector2, , int, s, 8, 8, 0x11);
++  VDUP(vector2, , int, s, 16, 4, 0x22);
++  VDUP(vector2, , int, s, 32, 2, 0x33);
++  VDUP(vector2, , uint, u, 8, 8, 0x55);
++  VDUP(vector2, , uint, u, 16, 4, 0x66);
++  VDUP(vector2, , uint, u, 32, 2, 0x77);
++  VDUP(vector2, , poly, p, 8, 8, 0x55);
++  VDUP(vector2, , poly, p, 16, 4, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, , float, f, 16, 4, 14.6f);   /* 14.6f is 0x4b4d.  */
++#endif
++  VDUP(vector2, , float, f, 32, 2, 33.6f);
++
++  VDUP(vector2, q, int, s, 8, 16, 0x11);
++  VDUP(vector2, q, int, s, 16, 8, 0x22);
++  VDUP(vector2, q, int, s, 32, 4, 0x33);
++  VDUP(vector2, q, int, s, 64, 2, 0x44);
++  VDUP(vector2, q, uint, u, 8, 16, 0x55);
++  VDUP(vector2, q, uint, u, 16, 8, 0x66);
++  VDUP(vector2, q, uint, u, 32, 4, 0x77);
++  VDUP(vector2, q, uint, u, 64, 2, 0x88);
++  VDUP(vector2, q, poly, p, 8, 16, 0x55);
++  VDUP(vector2, q, poly, p, 16, 8, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, q, float, f, 16, 8, 14.6f);
++#endif
++  VDUP(vector2, q, float, f, 32, 4, 33.8f);
++  VDUP(vector2, q, float, f, 64, 2, 33.8f);
++
++  TEST_VUZP1(, int, s, 8, 8);
++  TEST_VUZP1(, int, s, 16, 4);
++  TEST_VUZP1(, int, s, 32, 2);
++  TEST_VUZP1(, uint, u, 8, 8);
++  TEST_VUZP1(, uint, u, 16, 4);
++  TEST_VUZP1(, uint, u, 32, 2);
++  TEST_VUZP1(, poly, p, 8, 8);
++  TEST_VUZP1(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++  TEST_VUZP1(, float, f, 16, 4);
++#endif
++  TEST_VUZP1(, float, f, 32, 2);
++
++  TEST_VUZP1(q, int, s, 8, 16);
++  TEST_VUZP1(q, int, s, 16, 8);
++  TEST_VUZP1(q, int, s, 32, 4);
++  TEST_VUZP1(q, int, s, 64, 2);
++  TEST_VUZP1(q, uint, u, 8, 16);
++  TEST_VUZP1(q, uint, u, 16, 8);
++  TEST_VUZP1(q, uint, u, 32, 4);
++  TEST_VUZP1(q, uint, u, 64, 2);
++  TEST_VUZP1(q, poly, p, 8, 16);
++  TEST_VUZP1(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VUZP1(q, float, f, 16, 8);
++#endif
++  TEST_VUZP1(q, float, f, 32, 4);
++  TEST_VUZP1(q, float, f, 64, 2);
++
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS (TEST_MSG, "");
++#else
++  CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
++#endif
++
++#undef TEST_MSG
++#define TEST_MSG "VUZP2"
++
++#define TEST_VUZP2(Q, T1, T2, W, N) TEST_VUZP(2, Q, T1, T2, W, N)
++
++/* Expected results.  */
++VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
++					0x11, 0x11, 0x11, 0x11 };
++VECT_VAR_DECL(expected2,int,16,4) [] = { 0xfff1, 0xfff3, 0x22, 0x22 };
++VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 };
++VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
++					 0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected2,uint,16,4) [] = { 0xfff1, 0xfff3, 0x66, 0x66 };
++VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 };
++VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
++					 0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff1, 0xfff3, 0x66, 0x66 };
++VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1700000, 0x42066666 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb80, 0xca80,
++						0x4b4d, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
++					 0xf9, 0xfb, 0xfd, 0xff,
++					 0x11, 0x11, 0x11, 0x11,
++					 0x11, 0x11, 0x11, 0x11 };
++VECT_VAR_DECL(expected2,int,16,8) [] = { 0xfff1, 0xfff3, 0xfff5, 0xfff7,
++					 0x22, 0x22, 0x22, 0x22 };
++VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff3,
++					 0x33, 0x33 };
++VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1,
++					 0x44 };
++VECT_VAR_DECL(expected2,uint,8,16) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
++					  0xf9, 0xfb, 0xfd, 0xff,
++					  0x55, 0x55, 0x55, 0x55,
++					  0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected2,uint,16,8) [] = { 0xfff1, 0xfff3, 0xfff5, 0xfff7,
++					  0x66, 0x66, 0x66, 0x66 };
++VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff1, 0xfffffff3, 0x77, 0x77 };
++VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1,
++					  0x88 };
++VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
++					  0xf9, 0xfb, 0xfd, 0xff,
++					  0x55, 0x55, 0x55, 0x55,
++					  0x55, 0x55, 0x55, 0x55 };
++VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff1, 0xfff3, 0xfff5, 0xfff7,
++					  0x66, 0x66, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xcb80, 0xca80, 0xc980, 0xc880,
++						0x4b4d, 0x4b4d, 0x4b4d, 0x4b4d
++					      };
++#endif
++VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1700000, 0xc1500000,
++					    0x42073333, 0x42073333 };
++
++  clean_results ();
++  CLEAN(expected2, int, 64, 1);
++  CLEAN(expected2, uint, 64, 1);
++
++  TEST_VUZP2(, int, s, 8, 8);
++  TEST_VUZP2(, int, s, 16, 4);
++  TEST_VUZP2(, int, s, 32, 2);
++  TEST_VUZP2(, uint, u, 8, 8);
++  TEST_VUZP2(, uint, u, 16, 4);
++  TEST_VUZP2(, uint, u, 32, 2);
++  TEST_VUZP2(, poly, p, 8, 8);
++  TEST_VUZP2(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++  TEST_VUZP2(, float, f, 16, 4);
++#endif
++  TEST_VUZP2(, float, f, 32, 2);
++
++  TEST_VUZP2(q, int, s, 8, 16);
++  TEST_VUZP2(q, int, s, 16, 8);
++  TEST_VUZP2(q, int, s, 32, 4);
++  TEST_VUZP2(q, int, s, 64, 2);
++  TEST_VUZP2(q, uint, u, 8, 16);
++  TEST_VUZP2(q, uint, u, 16, 8);
++  TEST_VUZP2(q, uint, u, 32, 4);
++  TEST_VUZP2(q, uint, u, 64, 2);
++  TEST_VUZP2(q, poly, p, 8, 16);
++  TEST_VUZP2(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VUZP2(q, float, f, 16, 8);
++#endif
++  TEST_VUZP2(q, float, f, 32, 4);
++  TEST_VUZP2(q, float, f, 64, 2);
++
++  CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
++#if defined (FP16_SUPPORTED)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected2, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected2, "");
++#endif
++}
++
++int main (void)
++{
++  exec_vuzp_half ();
++  return 0;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
+@@ -18,6 +18,10 @@ VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55,
+ 					 0xf1, 0xf5, 0x55, 0x55 };
+ VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2,
+ 					  0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcb00,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+ VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11,
+ 					 0xf1, 0xf9, 0x11, 0x11,
+@@ -41,6 +45,12 @@ VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf8, 0x55, 0x55,
+ 					  0xf3, 0xfb, 0x55, 0x55 };
+ VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff4, 0x66, 0x66,
+ 					  0xfff1, 0xfff5, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected0, hfloat, 16, 8) [] = { 0xcc00, 0xca00,
++						0x4b4d, 0x4b4d,
++						0xcb80, 0xc980,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1600000,
+ 					    0x42073333, 0x42073333 };
+ 
+@@ -59,6 +69,10 @@ VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf2, 0xf6, 0x55, 0x55,
+ 					 0xf3, 0xf7, 0x55, 0x55 };
+ VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff1, 0xfff3,
+ 					  0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 4) [] = { 0xcb80, 0xca80,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0x42066666, 0x42066666 };
+ VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf4, 0xfc, 0x11, 0x11,
+ 					 0xf5, 0xfd, 0x11, 0x11,
+@@ -82,6 +96,12 @@ VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf4, 0xfc, 0x55, 0x55,
+ 					  0xf7, 0xff, 0x55, 0x55 };
+ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff2, 0xfff6, 0x66, 0x66,
+ 					  0xfff3, 0xfff7, 0x66, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected1, hfloat, 16, 8) [] = { 0xcb00, 0xc900,
++						0x4b4d, 0x4b4d,
++						0xca80, 0xc880,
++						0x4b4d, 0x4b4d };
++#endif
+ VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1700000, 0xc1500000,
+ 					    0x42073333, 0x42073333 };
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c
+@@ -0,0 +1,263 @@
++/* { dg-do run } */
++/* { dg-skip-if "" { arm*-*-* } } */
++
++#include <arm_neon.h>
++#include "arm-neon-ref.h"
++#include "compute-ref-data.h"
++
++/* Expected results.  */
++VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0x11, 0xf1, 0x11,
++				       0xf2, 0x11, 0xf3, 0x11 };
++VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0x22, 0xfff1, 0x22 };
++VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0x33 };
++VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0x55, 0xf1, 0x55,
++					0xf2, 0x55, 0xf3, 0x55 };
++VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0x66, 0xfff1, 0x66 };
++VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0x77 };
++VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
++VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0x55, 0xf1, 0x55,
++					0xf2, 0x55, 0xf3, 0x55 };
++VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0x66, 0xfff1, 0x66 };
++VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0x42066666 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 4) [] = { 0xcc00, 0x4b4d,
++					       0xcb80, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0x11, 0xf1, 0x11,
++					0xf2, 0x11, 0xf3, 0x11,
++					0xf4, 0x11, 0xf5, 0x11,
++					0xf6, 0x11, 0xf7, 0x11 };
++VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0x22, 0xfff1, 0x22,
++					0xfff2, 0x22, 0xfff3, 0x22 };
++VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0x33,
++					0xfffffff1, 0x33 };
++VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
++					0x44 };
++VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0x55, 0xf1, 0x55,
++					 0xf2, 0x55, 0xf3, 0x55,
++					 0xf4, 0x55, 0xf5, 0x55,
++					 0xf6, 0x55, 0xf7, 0x55 };
++VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0x66, 0xfff1, 0x66,
++					 0xfff2, 0x66, 0xfff3, 0x66 };
++VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0x77,
++					 0xfffffff1, 0x77 };
++VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
++					 0x88 };
++VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0x55, 0xf1, 0x55,
++					 0xf2, 0x55, 0xf3, 0x55,
++					 0xf4, 0x55, 0xf5, 0x55,
++					 0xf6, 0x55, 0xf7, 0x55 };
++VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0x66, 0xfff1, 0x66,
++					 0xfff2, 0x66, 0xfff3, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected, hfloat, 16, 8) [] = { 0xcc00, 0x4b4d,
++					       0xcb80, 0x4b4d,
++					       0xcb00, 0x4b4d,
++					       0xca80, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0x42073333,
++					   0xc1700000, 0x42073333 };
++
++#define TEST_MSG "VZIP1"
++void exec_vzip_half (void)
++{
++#define TEST_VZIP(PART, Q, T1, T2, W, N)		\
++  VECT_VAR(vector_res, T1, W, N) =			\
++    vzip##PART##Q##_##T2##W(VECT_VAR(vector, T1, W, N),	\
++		       VECT_VAR(vector2, T1, W, N));	\
++  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
++
++#define TEST_VZIP1(Q, T1, T2, W, N) TEST_VZIP(1, Q, T1, T2, W, N)
++
++  /* Input vector can only have 64 bits.  */
++  DECL_VARIABLE_ALL_VARIANTS(vector);
++  DECL_VARIABLE_ALL_VARIANTS(vector2);
++  DECL_VARIABLE(vector, float, 64, 2);
++  DECL_VARIABLE(vector2, float, 64, 2);
++
++  DECL_VARIABLE_ALL_VARIANTS(vector_res);
++  DECL_VARIABLE(vector_res, float, 64, 2);
++
++  clean_results ();
++  /* We don't have vzip1_T64x1, so set expected to the clean value.  */
++  CLEAN(expected, int, 64, 1);
++  CLEAN(expected, uint, 64, 1);
++
++  TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
++#if defined (FP16_SUPPORTED)
++  VLOAD(vector, buffer, , float, f, 16, 4);
++  VLOAD(vector, buffer, q, float, f, 16, 8);
++#endif
++  VLOAD(vector, buffer, , float, f, 32, 2);
++  VLOAD(vector, buffer, q, float, f, 32, 4);
++  VLOAD(vector, buffer, q, float, f, 64, 2);
++
++  /* Choose arbitrary initialization values.  */
++  VDUP(vector2, , int, s, 8, 8, 0x11);
++  VDUP(vector2, , int, s, 16, 4, 0x22);
++  VDUP(vector2, , int, s, 32, 2, 0x33);
++  VDUP(vector2, , uint, u, 8, 8, 0x55);
++  VDUP(vector2, , uint, u, 16, 4, 0x66);
++  VDUP(vector2, , uint, u, 32, 2, 0x77);
++  VDUP(vector2, , poly, p, 8, 8, 0x55);
++  VDUP(vector2, , poly, p, 16, 4, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, , float, f, 16, 4, 14.6f);   /* 14.6f is 0x4b4d.  */
++#endif
++  VDUP(vector2, , float, f, 32, 2, 33.6f);
++
++  VDUP(vector2, q, int, s, 8, 16, 0x11);
++  VDUP(vector2, q, int, s, 16, 8, 0x22);
++  VDUP(vector2, q, int, s, 32, 4, 0x33);
++  VDUP(vector2, q, int, s, 64, 2, 0x44);
++  VDUP(vector2, q, uint, u, 8, 16, 0x55);
++  VDUP(vector2, q, uint, u, 16, 8, 0x66);
++  VDUP(vector2, q, uint, u, 32, 4, 0x77);
++  VDUP(vector2, q, uint, u, 64, 2, 0x88);
++  VDUP(vector2, q, poly, p, 8, 16, 0x55);
++  VDUP(vector2, q, poly, p, 16, 8, 0x66);
++#if defined (FP16_SUPPORTED)
++  VDUP (vector2, q, float, f, 16, 8, 14.6f);
++#endif
++  VDUP(vector2, q, float, f, 32, 4, 33.8f);
++  VDUP(vector2, q, float, f, 64, 2, 33.8f);
++
++  TEST_VZIP1(, int, s, 8, 8);
++  TEST_VZIP1(, int, s, 16, 4);
++  TEST_VZIP1(, int, s, 32, 2);
++  TEST_VZIP1(, uint, u, 8, 8);
++  TEST_VZIP1(, uint, u, 16, 4);
++  TEST_VZIP1(, uint, u, 32, 2);
++  TEST_VZIP1(, poly, p, 8, 8);
++  TEST_VZIP1(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++  TEST_VZIP1(, float, f, 16, 4);
++#endif
++  TEST_VZIP1(, float, f, 32, 2);
++
++  TEST_VZIP1(q, int, s, 8, 16);
++  TEST_VZIP1(q, int, s, 16, 8);
++  TEST_VZIP1(q, int, s, 32, 4);
++  TEST_VZIP1(q, int, s, 64, 2);
++  TEST_VZIP1(q, uint, u, 8, 16);
++  TEST_VZIP1(q, uint, u, 16, 8);
++  TEST_VZIP1(q, uint, u, 32, 4);
++  TEST_VZIP1(q, uint, u, 64, 2);
++  TEST_VZIP1(q, poly, p, 8, 16);
++  TEST_VZIP1(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VZIP1(q, float, f, 16, 8);
++#endif
++  TEST_VZIP1(q, float, f, 32, 4);
++  TEST_VZIP1(q, float, f, 64, 2);
++
++#if defined (FP16_SUPPORTED)
++  CHECK_RESULTS (TEST_MSG, "");
++#else
++  CHECK_RESULTS_NO_FP16 (TEST_MSG, "");
++#endif
++
++#undef TEST_MSG
++#define TEST_MSG "VZIP2"
++
++#define TEST_VZIP2(Q, T1, T2, W, N) TEST_VZIP(2, Q, T1, T2, W, N)
++
++/* Expected results.  */
++VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf4, 0x11, 0xf5, 0x11,
++					0xf6, 0x11, 0xf7, 0x11 };
++VECT_VAR_DECL(expected2,int,16,4) [] = { 0xfff2, 0x22, 0xfff3, 0x22 };
++VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 };
++VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xf4, 0x55, 0xf5, 0x55,
++					 0xf6, 0x55, 0xf7, 0x55 };
++VECT_VAR_DECL(expected2,uint,16,4) [] = { 0xfff2, 0x66, 0xfff3, 0x66 };
++VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 };
++VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 };
++VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf4, 0x55, 0xf5, 0x55,
++					 0xf6, 0x55, 0xf7, 0x55 };
++VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff2, 0x66, 0xfff3, 0x66 };
++VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1700000, 0x42066666 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb00, 0x4b4d,
++						0xca80, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf8, 0x11, 0xf9, 0x11,
++					 0xfa, 0x11, 0xfb, 0x11,
++					 0xfc, 0x11, 0xfd, 0x11,
++					 0xfe, 0x11, 0xff, 0x11 };
++VECT_VAR_DECL(expected2,int,16,8) [] = { 0xfff4, 0x22, 0xfff5, 0x22,
++					 0xfff6, 0x22, 0xfff7, 0x22 };
++VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff2, 0x33,
++					 0xfffffff3, 0x33 };
++VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1,
++					 0x44 };
++VECT_VAR_DECL(expected2,uint,8,16) [] = { 0xf8, 0x55, 0xf9, 0x55,
++					  0xfa, 0x55, 0xfb, 0x55,
++					  0xfc, 0x55, 0xfd, 0x55,
++					  0xfe, 0x55, 0xff, 0x55 };
++VECT_VAR_DECL(expected2,uint,16,8) [] = { 0xfff4, 0x66, 0xfff5, 0x66,
++					  0xfff6, 0x66, 0xfff7, 0x66 };
++VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff2, 0x77,
++					  0xfffffff3, 0x77 };
++VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1,
++					  0x88 };
++VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf8, 0x55, 0xf9, 0x55,
++					  0xfa, 0x55, 0xfb, 0x55,
++					  0xfc, 0x55, 0xfd, 0x55,
++					  0xfe, 0x55, 0xff, 0x55 };
++VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff4, 0x66, 0xfff5, 0x66,
++					  0xfff6, 0x66, 0xfff7, 0x66 };
++#if defined (FP16_SUPPORTED)
++VECT_VAR_DECL (expected2, hfloat, 16, 8) [] = { 0xca00, 0x4b4d,
++						0xc980, 0x4b4d,
++						0xc900, 0x4b4d,
++						0xc880, 0x4b4d };
++#endif
++VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1600000, 0x42073333,
++					    0xc1500000, 0x42073333 };
++  clean_results ();
++  CLEAN(expected2, int, 64, 1);
++  CLEAN(expected2, uint, 64, 1);
++
++  TEST_VZIP2(, int, s, 8, 8);
++  TEST_VZIP2(, int, s, 16, 4);
++  TEST_VZIP2(, int, s, 32, 2);
++  TEST_VZIP2(, uint, u, 8, 8);
++  TEST_VZIP2(, uint, u, 16, 4);
++  TEST_VZIP2(, uint, u, 32, 2);
++  TEST_VZIP2(, poly, p, 8, 8);
++  TEST_VZIP2(, poly, p, 16, 4);
++#if defined (FP16_SUPPORTED)
++  TEST_VZIP2(, float, f, 16, 4);
++#endif
++  TEST_VZIP2(, float, f, 32, 2);
++
++  TEST_VZIP2(q, int, s, 8, 16);
++  TEST_VZIP2(q, int, s, 16, 8);
++  TEST_VZIP2(q, int, s, 32, 4);
++  TEST_VZIP2(q, int, s, 64, 2);
++  TEST_VZIP2(q, uint, u, 8, 16);
++  TEST_VZIP2(q, uint, u, 16, 8);
++  TEST_VZIP2(q, uint, u, 32, 4);
++  TEST_VZIP2(q, uint, u, 64, 2);
++  TEST_VZIP2(q, poly, p, 8, 16);
++  TEST_VZIP2(q, poly, p, 16, 8);
++#if defined (FP16_SUPPORTED)
++  TEST_VZIP2(q, float, f, 16, 8);
++#endif
++  TEST_VZIP2(q, float, f, 32, 4);
++  TEST_VZIP2(q, float, f, 64, 2);
++
++  CHECK_RESULTS_NAMED (TEST_MSG, expected2, "");
++#if defined (FP16_SUPPORTED)
++  CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected2, "");
++  CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected2, "");
++#endif
++}
++
++int main (void)
++{
++  exec_vzip_half ();
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/ands_3.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++int
++f9 (unsigned char x, int y)
++{
++  if (y > 1 && x == 0)
++    return 10;
++  return x;
++}
++
++/* { dg-final { scan-assembler "ands\t(x|w)\[0-9\]+,\[ \t\]*(x|w)\[0-9\]+,\[ \t\]*255" } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c
+@@ -1,4 +1,5 @@
+ /* { dg-error "unknown" "" {target "aarch64*-*-*" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "" } } */
+ /* { dg-options "-O2 -mcpu=dummy" } */
+ 
+ void f ()
+--- a/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c
+@@ -1,4 +1,5 @@
+ /* { dg-error "missing" "" {target "aarch64*-*-*" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "" } } */
+ /* { dg-options "-O2 -mcpu=cortex-a53+no" } */
+ 
+ void f ()
+--- a/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c
+@@ -1,4 +1,5 @@
+ /* { dg-error "invalid feature" "" {target "aarch64*-*-*" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "" } } */
+ /* { dg-options "-O2 -mcpu=cortex-a53+dummy" } */
+ 
+ void f ()
+--- a/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c
+@@ -1,4 +1,5 @@
+ /* { dg-error "missing" "" {target "aarch64*-*-*" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "" } } */
+ /* { dg-options "-O2 -mcpu=+dummy" } */
+ 
+ void f ()
+--- a/src/gcc/testsuite/gcc.target/aarch64/fmaxmin.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/fmaxmin.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O2 -ftree-vectorize -fno-inline -save-temps" } */
++/* { dg-options "-O2 -ftree-vectorize -fno-inline -fno-vect-cost-model -save-temps" } */
+ 
+ 
+ extern void abort (void);
+--- a/src/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
+@@ -110,6 +110,6 @@ main (int argc, char **argv)
+ /* vfmaq_lane_f64.
+    vfma_laneq_f64.
+    vfmaq_laneq_f64.  */
+-/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d\\\[\[0-9\]+\\\]" 3 } } */
++/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */
+ 
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
+@@ -111,6 +111,6 @@ main (int argc, char **argv)
+ /* vfmsq_lane_f64.
+    vfms_laneq_f64.
+    vfmsq_laneq_f64.  */
+-/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d\\\[\[0-9\]+\\\]" 3 } } */
++/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */
+ 
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/fmovd-zero-reg.c
+@@ -8,4 +8,4 @@ foo (void)
+   bar (0.0);
+ }
+ 
+-/* { dg-final { scan-assembler "fmov\\td0, xzr" } } */
++/* { dg-final { scan-assembler "movi\\td0, #0" } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/fmovf-zero-reg.c
+@@ -8,4 +8,4 @@ foo (void)
+   bar (0.0);
+ }
+ 
+-/* { dg-final { scan-assembler "fmov\\ts0, wzr" } } */
++/* { dg-final { scan-assembler "movi\\tv0\.2s, #0" } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-save-temps -O2 -ftree-vectorize -fno-inline" } */
++/* { dg-options "-save-temps -O2 -ftree-vectorize -fno-inline -fno-vect-cost-model" } */
+ 
+ #define N 1024
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_subreg_1.c
+@@ -0,0 +1,30 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-rtl-ce1" } */
++
++/* Check that the inner if is transformed into CSELs.  */
++
++int
++foo (int *x, int *z, int a)
++{
++  int b = 0;
++  int c = 0;
++  int d = 0;
++  int i;
++
++  for (i = 0; i < a; i++)
++    {
++      if (x[i] < c)
++	{
++	  b = z[i];
++	  if (c < b)
++	    {
++	      c = b;
++	      d = i;
++	    }
++	}
++    }
++
++  return c + d;
++}
++
++/* { dg-final { scan-rtl-dump "if-conversion succeeded through noce_convert_multiple_sets" "ce1" } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/ldp_stp_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/ldp_stp_1.c
+@@ -1,4 +1,4 @@
+-/* { dg-options "-O2" } */
++/* { dg-options "-O2 -mcpu=generic" } */
+ 
+ int arr[4][4];
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_1.c
+@@ -0,0 +1,20 @@
++/* { dg-options "-O2" } */
++
++/* Check that we can use a REG + IMM addressing mode when moving an unaligned
++   TImode value to and from memory.  */
++
++struct foo
++{
++  long long b;
++  __int128 a;
++} __attribute__ ((packed));
++
++void
++bar (struct foo *p, struct foo *q)
++{
++  p->a = q->a;
++}
++
++/* { dg-final { scan-assembler-not "add\tx\[0-9\]+, x\[0-9\]+" } } */
++/* { dg-final { scan-assembler-times "ldp\tx\[0-9\]+, x\[0-9\], .*8" 1 } } */
++/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\], .*8" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/popcnt.c
+@@ -0,0 +1,23 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++int
++foo (int x)
++{
++  return __builtin_popcount (x);
++}
++
++long
++foo1 (long x)
++{
++  return __builtin_popcountl (x);
++}
++
++long long
++foo2 (long long x)
++{
++  return __builtin_popcountll (x);
++}
++
++/* { dg-final { scan-assembler-not "popcount" } } */
++/* { dg-final { scan-assembler-times "cnt\t" 3 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr37780_1.c
+@@ -0,0 +1,46 @@
++/* Test that we can remove the conditional move due to CLZ
++   and CTZ being defined at zero.  */
++
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++int
++fooctz (int i)
++{
++  return (i == 0) ? 32 : __builtin_ctz (i);
++}
++
++int
++fooctz2 (int i)
++{
++  return (i != 0) ? __builtin_ctz (i) : 32;
++}
++
++unsigned int
++fooctz3 (unsigned int i)
++{
++  return (i > 0) ?  __builtin_ctz (i) : 32;
++}
++
++/* { dg-final { scan-assembler-times "rbit\t*" 3 } } */
++
++int
++fooclz (int i)
++{
++  return (i == 0) ? 32 : __builtin_clz (i);
++}
++
++int
++fooclz2 (int i)
++{
++  return (i != 0) ? __builtin_clz (i) : 32;
++}
++
++unsigned int
++fooclz3 (unsigned int i)
++{
++  return (i > 0) ? __builtin_clz (i) : 32;
++}
++
++/* { dg-final { scan-assembler-times "clz\t" 6 } } */
++/* { dg-final { scan-assembler-not "cmp\t.*0" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr63874.c
+@@ -0,0 +1,22 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++/* { dg-skip-if "Not applicable for mcmodel=large" { aarch64*-*-* }  { "-mcmodel=large" } { "" } } */
++
++extern void __attribute__((weak)) foo_weakref (void);
++void __attribute__((weak, noinline)) bar (void)
++{
++ return;
++}
++void (*f) (void);
++void (*g) (void);
++
++int
++main (void)
++{
++ f = &foo_weakref;
++ g = &bar;
++ return 0;
++}
++
++/* { dg-final { scan-assembler-not "adr*foo_weakref" } } */
++/* { dg-final { scan-assembler-not "\\.(word|xword)\tbar" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr71727.c
+@@ -0,0 +1,33 @@
++/* { dg-do compile } */
++/* { dg-options "-mstrict-align -O3" } */
++
++struct test_struct_s
++{
++  long a;
++  long b;
++  long c;
++  long d;
++  unsigned long e;
++};
++
++
++char _a;
++struct test_struct_s xarray[128];
++
++void
++_start (void)
++{
++  struct test_struct_s *new_entry;
++
++  new_entry = &xarray[0];
++  new_entry->a = 1;
++  new_entry->b = 2;
++  new_entry->c = 3;
++  new_entry->d = 4;
++  new_entry->e = 5;
++
++  return;
++}
++
++/* { dg-final { scan-assembler-times "mov\tx" 5 {target lp64} } } */
++/* { dg-final { scan-assembler-not "add\tx0, x0, :" {target lp64} } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr78382.c
+@@ -0,0 +1,10 @@
++/* { dg-require-effective-target fpic } */
++/* { dg-options "-mtls-dialect=trad -fpic" } */
++
++__thread int abc;
++void
++foo ()
++{
++  int *p;
++  p = &abc;
++}
+--- a/src/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c
+@@ -1,4 +1,4 @@
+-/* Test the `v[min|max]nm{q}_f*' AArch64 SIMD intrinsic.  */
++/* Test the `v[min|max]{nm}{q}_f*' AArch64 SIMD intrinsic.  */
+ 
+ /* { dg-do run } */
+ /* { dg-options "-O2" } */
+@@ -18,6 +18,7 @@ extern void abort ();
+ int
+ main (int argc, char **argv)
+ {
++  /* v{min|max}nm_f32 normal.  */
+   float32x2_t f32x2_input1 = vdup_n_f32 (-1.0);
+   float32x2_t f32x2_input2 = vdup_n_f32 (0.0);
+   float32x2_t f32x2_exp_minnm  = vdup_n_f32 (-1.0);
+@@ -28,6 +29,7 @@ main (int argc, char **argv)
+   CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm);
+   CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm);
+ 
++  /* v{min|max}nm_f32 NaN.  */
+   f32x2_input1 = vdup_n_f32 (__builtin_nanf (""));
+   f32x2_input2 = vdup_n_f32 (1.0);
+   f32x2_exp_minnm  = vdup_n_f32 (1.0);
+@@ -38,6 +40,7 @@ main (int argc, char **argv)
+   CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm);
+   CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm);
+ 
++  /* v{min|max}nmq_f32 normal.  */
+   float32x4_t f32x4_input1 = vdupq_n_f32 (-1024.0);
+   float32x4_t f32x4_input2 = vdupq_n_f32 (77.0);
+   float32x4_t f32x4_exp_minnm  = vdupq_n_f32 (-1024.0);
+@@ -48,6 +51,7 @@ main (int argc, char **argv)
+   CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm);
+   CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm);
+ 
++  /* v{min|max}nmq_f32 NaN.  */
+   f32x4_input1 = vdupq_n_f32 (-__builtin_nanf (""));
+   f32x4_input2 = vdupq_n_f32 (-1.0);
+   f32x4_exp_minnm  = vdupq_n_f32 (-1.0);
+@@ -58,16 +62,57 @@ main (int argc, char **argv)
+   CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm);
+   CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm);
+ 
++  /* v{min|max}nm_f64 normal.  */
++  float64x1_t f64x1_input1 = vdup_n_f64 (1.23);
++  float64x1_t f64x1_input2 = vdup_n_f64 (4.56);
++  float64x1_t f64x1_exp_minnm  = vdup_n_f64 (1.23);
++  float64x1_t f64x1_exp_maxnm  = vdup_n_f64 (4.56);
++  float64x1_t f64x1_ret_minnm  = vminnm_f64 (f64x1_input1, f64x1_input2);
++  float64x1_t f64x1_ret_maxnm  = vmaxnm_f64 (f64x1_input1, f64x1_input2);
++  CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm);
++  CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm);
++
++  /* v{min|max}_f64 normal.  */
++  float64x1_t f64x1_exp_min  = vdup_n_f64 (1.23);
++  float64x1_t f64x1_exp_max  = vdup_n_f64 (4.56);
++  float64x1_t f64x1_ret_min  = vmin_f64 (f64x1_input1, f64x1_input2);
++  float64x1_t f64x1_ret_max  = vmax_f64 (f64x1_input1, f64x1_input2);
++  CHECK (uint64_t, 1, f64x1_ret_min, f64x1_exp_min);
++  CHECK (uint64_t, 1, f64x1_ret_max, f64x1_exp_max);
++
++  /* v{min|max}nmq_f64 normal.  */
+   float64x2_t f64x2_input1 = vdupq_n_f64 (1.23);
+   float64x2_t f64x2_input2 = vdupq_n_f64 (4.56);
+   float64x2_t f64x2_exp_minnm  = vdupq_n_f64 (1.23);
+   float64x2_t f64x2_exp_maxnm  = vdupq_n_f64 (4.56);
+   float64x2_t f64x2_ret_minnm  = vminnmq_f64 (f64x2_input1, f64x2_input2);
+   float64x2_t f64x2_ret_maxnm  = vmaxnmq_f64 (f64x2_input1, f64x2_input2);
+-
+   CHECK (uint64_t, 2, f64x2_ret_minnm, f64x2_exp_minnm);
+   CHECK (uint64_t, 2, f64x2_ret_maxnm, f64x2_exp_maxnm);
+ 
++  /* v{min|max}nm_f64 NaN.  */
++  f64x1_input1 = vdup_n_f64 (-__builtin_nanf (""));
++  f64x1_input2 = vdup_n_f64 (1.0);
++  f64x1_exp_minnm  = vdup_n_f64 (1.0);
++  f64x1_exp_maxnm  = vdup_n_f64 (1.0);
++  f64x1_ret_minnm  = vminnm_f64 (f64x1_input1, f64x1_input2);
++  f64x1_ret_maxnm  = vmaxnm_f64 (f64x1_input1, f64x1_input2);
++
++  CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm);
++  CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm);
++
++  /* v{min|max}_f64 NaN.  */
++  f64x1_input1 = vdup_n_f64 (-__builtin_nanf (""));
++  f64x1_input2 = vdup_n_f64 (1.0);
++  f64x1_exp_minnm  = vdup_n_f64 (-__builtin_nanf (""));
++  f64x1_exp_maxnm  = vdup_n_f64 (-__builtin_nanf (""));
++  f64x1_ret_minnm  = vmin_f64 (f64x1_input1, f64x1_input2);
++  f64x1_ret_maxnm  = vmax_f64 (f64x1_input1, f64x1_input2);
++
++  CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm);
++  CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm);
++
++  /* v{min|max}nmq_f64 NaN.  */
+   f64x2_input1 = vdupq_n_f64 (-__builtin_nan (""));
+   f64x2_input2 = vdupq_n_f64 (1.0);
+   f64x2_exp_minnm  = vdupq_n_f64 (1.0);
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vmul_elem_1.c
+@@ -0,0 +1,541 @@
++/* Test the vmul_n_f64 AArch64 SIMD intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-options "-O2 --save-temps" } */
++
++#include "arm_neon.h"
++
++extern void abort (void);
++
++#define A (132.4f)
++#define B (-0.0f)
++#define C (-34.8f)
++#define D (289.34f)
++float32_t expected2_1[2] = {A * A, B * A};
++float32_t expected2_2[2] = {A * B, B * B};
++float32_t expected4_1[4] = {A * A, B * A, C * A, D * A};
++float32_t expected4_2[4] = {A * B, B * B, C * B, D * B};
++float32_t expected4_3[4] = {A * C, B * C, C * C, D * C};
++float32_t expected4_4[4] = {A * D, B * D, C * D, D * D};
++float32_t _elemA = A;
++float32_t _elemB = B;
++float32_t _elemC = C;
++float32_t _elemD = D;
++
++#define AD (1234.5)
++#define BD (-0.0)
++#define CD (71.3)
++#define DD (-1024.4)
++float64_t expectedd2_1[2] = {AD * CD, BD * CD};
++float64_t expectedd2_2[2] = {AD * DD, BD * DD};
++float64_t _elemdC = CD;
++float64_t _elemdD = DD;
++
++
++#define AS (1024)
++#define BS (-31)
++#define CS (0)
++#define DS (655)
++int32_t expecteds2_1[2] = {AS * AS, BS * AS};
++int32_t expecteds2_2[2] = {AS * BS, BS * BS};
++int32_t expecteds4_1[4] = {AS * AS, BS * AS, CS * AS, DS * AS};
++int32_t expecteds4_2[4] = {AS * BS, BS * BS, CS * BS, DS * BS};
++int32_t expecteds4_3[4] = {AS * CS, BS * CS, CS * CS, DS * CS};
++int32_t expecteds4_4[4] = {AS * DS, BS * DS, CS * DS, DS * DS};
++int32_t _elemsA = AS;
++int32_t _elemsB = BS;
++int32_t _elemsC = CS;
++int32_t _elemsD = DS;
++
++#define AH ((int16_t) 0)
++#define BH ((int16_t) -32)
++#define CH ((int16_t) 102)
++#define DH ((int16_t) -51)
++#define EH ((int16_t) 71)
++#define FH ((int16_t) -91)
++#define GH ((int16_t) 48)
++#define HH ((int16_t) 255)
++int16_t expectedh4_1[4] = {AH * AH, BH * AH, CH * AH, DH * AH};
++int16_t expectedh4_2[4] = {AH * BH, BH * BH, CH * BH, DH * BH};
++int16_t expectedh4_3[4] = {AH * CH, BH * CH, CH * CH, DH * CH};
++int16_t expectedh4_4[4] = {AH * DH, BH * DH, CH * DH, DH * DH};
++int16_t expectedh8_1[8] = {AH * AH, BH * AH, CH * AH, DH * AH,
++			   EH * AH, FH * AH, GH * AH, HH * AH};
++int16_t expectedh8_2[8] = {AH * BH, BH * BH, CH * BH, DH * BH,
++			   EH * BH, FH * BH, GH * BH, HH * BH};
++int16_t expectedh8_3[8] = {AH * CH, BH * CH, CH * CH, DH * CH,
++			   EH * CH, FH * CH, GH * CH, HH * CH};
++int16_t expectedh8_4[8] = {AH * DH, BH * DH, CH * DH, DH * DH,
++			   EH * DH, FH * DH, GH * DH, HH * DH};
++int16_t expectedh8_5[8] = {AH * EH, BH * EH, CH * EH, DH * EH,
++			   EH * EH, FH * EH, GH * EH, HH * EH};
++int16_t expectedh8_6[8] = {AH * FH, BH * FH, CH * FH, DH * FH,
++			   EH * FH, FH * FH, GH * FH, HH * FH};
++int16_t expectedh8_7[8] = {AH * GH, BH * GH, CH * GH, DH * GH,
++			   EH * GH, FH * GH, GH * GH, HH * GH};
++int16_t expectedh8_8[8] = {AH * HH, BH * HH, CH * HH, DH * HH,
++			   EH * HH, FH * HH, GH * HH, HH * HH};
++int16_t _elemhA = AH;
++int16_t _elemhB = BH;
++int16_t _elemhC = CH;
++int16_t _elemhD = DH;
++int16_t _elemhE = EH;
++int16_t _elemhF = FH;
++int16_t _elemhG = GH;
++int16_t _elemhH = HH;
++
++#define AUS (1024)
++#define BUS (31)
++#define CUS (0)
++#define DUS (655)
++uint32_t expectedus2_1[2] = {AUS * AUS, BUS * AUS};
++uint32_t expectedus2_2[2] = {AUS * BUS, BUS * BUS};
++uint32_t expectedus4_1[4] = {AUS * AUS, BUS * AUS, CUS * AUS, DUS * AUS};
++uint32_t expectedus4_2[4] = {AUS * BUS, BUS * BUS, CUS * BUS, DUS * BUS};
++uint32_t expectedus4_3[4] = {AUS * CUS, BUS * CUS, CUS * CUS, DUS * CUS};
++uint32_t expectedus4_4[4] = {AUS * DUS, BUS * DUS, CUS * DUS, DUS * DUS};
++uint32_t _elemusA = AUS;
++uint32_t _elemusB = BUS;
++uint32_t _elemusC = CUS;
++uint32_t _elemusD = DUS;
++
++#define AUH ((uint16_t) 0)
++#define BUH ((uint16_t) 32)
++#define CUH ((uint16_t) 102)
++#define DUH ((uint16_t) 51)
++#define EUH ((uint16_t) 71)
++#define FUH ((uint16_t) 91)
++#define GUH ((uint16_t) 48)
++#define HUH ((uint16_t) 255)
++uint16_t expecteduh4_1[4] = {AUH * AUH, BUH * AUH, CUH * AUH, DUH * AUH};
++uint16_t expecteduh4_2[4] = {AUH * BUH, BUH * BUH, CUH * BUH, DUH * BUH};
++uint16_t expecteduh4_3[4] = {AUH * CUH, BUH * CUH, CUH * CUH, DUH * CUH};
++uint16_t expecteduh4_4[4] = {AUH * DUH, BUH * DUH, CUH * DUH, DUH * DUH};
++uint16_t expecteduh8_1[8] = {AUH * AUH, BUH * AUH, CUH * AUH, DUH * AUH,
++			     EUH * AUH, FUH * AUH, GUH * AUH, HUH * AUH};
++uint16_t expecteduh8_2[8] = {AUH * BUH, BUH * BUH, CUH * BUH, DUH * BUH,
++			     EUH * BUH, FUH * BUH, GUH * BUH, HUH * BUH};
++uint16_t expecteduh8_3[8] = {AUH * CUH, BUH * CUH, CUH * CUH, DUH * CUH,
++			     EUH * CUH, FUH * CUH, GUH * CUH, HUH * CUH};
++uint16_t expecteduh8_4[8] = {AUH * DUH, BUH * DUH, CUH * DUH, DUH * DUH,
++			     EUH * DUH, FUH * DUH, GUH * DUH, HUH * DUH};
++uint16_t expecteduh8_5[8] = {AUH * EUH, BUH * EUH, CUH * EUH, DUH * EUH,
++			     EUH * EUH, FUH * EUH, GUH * EUH, HUH * EUH};
++uint16_t expecteduh8_6[8] = {AUH * FUH, BUH * FUH, CUH * FUH, DUH * FUH,
++			     EUH * FUH, FUH * FUH, GUH * FUH, HUH * FUH};
++uint16_t expecteduh8_7[8] = {AUH * GUH, BUH * GUH, CUH * GUH, DUH * GUH,
++			     EUH * GUH, FUH * GUH, GUH * GUH, HUH * GUH};
++uint16_t expecteduh8_8[8] = {AUH * HUH, BUH * HUH, CUH * HUH, DUH * HUH,
++			     EUH * HUH, FUH * HUH, GUH * HUH, HUH * HUH};
++uint16_t _elemuhA = AUH;
++uint16_t _elemuhB = BUH;
++uint16_t _elemuhC = CUH;
++uint16_t _elemuhD = DUH;
++uint16_t _elemuhE = EUH;
++uint16_t _elemuhF = FUH;
++uint16_t _elemuhG = GUH;
++uint16_t _elemuhH = HUH;
++
++void
++check_v2sf (float32_t elemA, float32_t elemB)
++{
++  int32_t indx;
++  const float32_t vec32x2_buf[2] = {A, B};
++  float32x2_t vec32x2_src = vld1_f32 (vec32x2_buf);
++  float32_t vec32x2_res[2];
++
++  vst1_f32 (vec32x2_res, vmul_n_f32 (vec32x2_src, elemA));
++
++  for (indx = 0; indx < 2; indx++)
++    if (* (uint32_t *) &vec32x2_res[indx] != * (uint32_t *) &expected2_1[indx])
++      abort ();
++
++  vst1_f32 (vec32x2_res, vmul_n_f32 (vec32x2_src, elemB));
++
++  for (indx = 0; indx < 2; indx++)
++    if (* (uint32_t *) &vec32x2_res[indx] != * (uint32_t *) &expected2_2[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "fmul\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[0\\\]" 2 } } */
++}
++
++void
++check_v4sf (float32_t elemA, float32_t elemB, float32_t elemC, float32_t elemD)
++{
++  int32_t indx;
++  const float32_t vec32x4_buf[4] = {A, B, C, D};
++  float32x4_t vec32x4_src = vld1q_f32 (vec32x4_buf);
++  float32_t vec32x4_res[4];
++
++  vst1q_f32 (vec32x4_res, vmulq_n_f32 (vec32x4_src, elemA));
++
++  for (indx = 0; indx < 4; indx++)
++    if (* (uint32_t *) &vec32x4_res[indx] != * (uint32_t *) &expected4_1[indx])
++      abort ();
++
++  vst1q_f32 (vec32x4_res, vmulq_n_f32 (vec32x4_src, elemB));
++
++  for (indx = 0; indx < 4; indx++)
++    if (* (uint32_t *) &vec32x4_res[indx] != * (uint32_t *) &expected4_2[indx])
++      abort ();
++
++  vst1q_f32 (vec32x4_res, vmulq_n_f32 (vec32x4_src, elemC));
++
++  for (indx = 0; indx < 4; indx++)
++    if (* (uint32_t *) &vec32x4_res[indx] != * (uint32_t *) &expected4_3[indx])
++      abort ();
++
++  vst1q_f32 (vec32x4_res, vmulq_n_f32 (vec32x4_src, elemD));
++
++  for (indx = 0; indx < 4; indx++)
++    if (* (uint32_t *) &vec32x4_res[indx] != * (uint32_t *) &expected4_4[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "fmul\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[0\\\]" 4 } } */
++}
++
++void
++check_v2df (float64_t elemdC, float64_t elemdD)
++{
++  int32_t indx;
++  const float64_t vec64x2_buf[2] = {AD, BD};
++  float64x2_t vec64x2_src = vld1q_f64 (vec64x2_buf);
++  float64_t vec64x2_res[2];
++
++  vst1q_f64 (vec64x2_res, vmulq_n_f64 (vec64x2_src, elemdC));
++
++  for (indx = 0; indx < 2; indx++)
++    if (* (uint64_t *) &vec64x2_res[indx] != * (uint64_t *) &expectedd2_1[indx])
++      abort ();
++
++  vst1q_f64 (vec64x2_res, vmulq_n_f64 (vec64x2_src, elemdD));
++
++  for (indx = 0; indx < 2; indx++)
++    if (* (uint64_t *) &vec64x2_res[indx] != * (uint64_t *) &expectedd2_2[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "fmul\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[0\\\]" 2 } } */
++}
++
++void
++check_v2si (int32_t elemsA, int32_t elemsB)
++{
++  int32_t indx;
++  const int32_t vecs32x2_buf[2] = {AS, BS};
++  int32x2_t vecs32x2_src = vld1_s32 (vecs32x2_buf);
++  int32_t vecs32x2_res[2];
++
++  vst1_s32 (vecs32x2_res, vmul_n_s32 (vecs32x2_src, elemsA));
++
++  for (indx = 0; indx < 2; indx++)
++    if (vecs32x2_res[indx] != expecteds2_1[indx])
++      abort ();
++
++  vst1_s32 (vecs32x2_res, vmul_n_s32 (vecs32x2_src, elemsB));
++
++  for (indx = 0; indx < 2; indx++)
++    if (vecs32x2_res[indx] != expecteds2_2[indx])
++      abort ();
++}
++
++void
++check_v2si_unsigned (uint32_t elemusA, uint32_t elemusB)
++{
++  int indx;
++  const uint32_t vecus32x2_buf[2] = {AUS, BUS};
++  uint32x2_t vecus32x2_src = vld1_u32 (vecus32x2_buf);
++  uint32_t vecus32x2_res[2];
++
++  vst1_u32 (vecus32x2_res, vmul_n_u32 (vecus32x2_src, elemusA));
++
++  for (indx = 0; indx < 2; indx++)
++    if (vecus32x2_res[indx] != expectedus2_1[indx])
++      abort ();
++
++  vst1_u32 (vecus32x2_res, vmul_n_u32 (vecus32x2_src, elemusB));
++
++  for (indx = 0; indx < 2; indx++)
++    if (vecus32x2_res[indx] != expectedus2_2[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "\tmul\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[0\\\]" 4 } } */
++}
++
++void
++check_v4si (int32_t elemsA, int32_t elemsB, int32_t elemsC, int32_t elemsD)
++{
++  int32_t indx;
++  const int32_t vecs32x4_buf[4] = {AS, BS, CS, DS};
++  int32x4_t vecs32x4_src = vld1q_s32 (vecs32x4_buf);
++  int32_t vecs32x4_res[4];
++
++  vst1q_s32 (vecs32x4_res, vmulq_n_s32 (vecs32x4_src, elemsA));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecs32x4_res[indx] != expecteds4_1[indx])
++      abort ();
++
++  vst1q_s32 (vecs32x4_res, vmulq_n_s32 (vecs32x4_src, elemsB));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecs32x4_res[indx] != expecteds4_2[indx])
++      abort ();
++
++  vst1q_s32 (vecs32x4_res, vmulq_n_s32 (vecs32x4_src, elemsC));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecs32x4_res[indx] != expecteds4_3[indx])
++      abort ();
++
++  vst1q_s32 (vecs32x4_res, vmulq_n_s32 (vecs32x4_src, elemsD));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecs32x4_res[indx] != expecteds4_4[indx])
++      abort ();
++}
++
++void
++check_v4si_unsigned (uint32_t elemusA, uint32_t elemusB, uint32_t elemusC,
++		     uint32_t elemusD)
++{
++  int indx;
++  const uint32_t vecus32x4_buf[4] = {AUS, BUS, CUS, DUS};
++  uint32x4_t vecus32x4_src = vld1q_u32 (vecus32x4_buf);
++  uint32_t vecus32x4_res[4];
++
++  vst1q_u32 (vecus32x4_res, vmulq_n_u32 (vecus32x4_src, elemusA));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecus32x4_res[indx] != expectedus4_1[indx])
++      abort ();
++
++  vst1q_u32 (vecus32x4_res, vmulq_n_u32 (vecus32x4_src, elemusB));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecus32x4_res[indx] != expectedus4_2[indx])
++      abort ();
++
++  vst1q_u32 (vecus32x4_res, vmulq_n_u32 (vecus32x4_src, elemusC));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecus32x4_res[indx] != expectedus4_3[indx])
++      abort ();
++
++  vst1q_u32 (vecus32x4_res, vmulq_n_u32 (vecus32x4_src, elemusD));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecus32x4_res[indx] != expectedus4_4[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "\tmul\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[0\\\]" 8 } } */
++}
++
++
++void
++check_v4hi (int16_t elemhA, int16_t elemhB, int16_t elemhC, int16_t elemhD)
++{
++  int32_t indx;
++  const int16_t vech16x4_buf[4] = {AH, BH, CH, DH};
++  int16x4_t vech16x4_src = vld1_s16 (vech16x4_buf);
++  int16_t vech16x4_res[4];
++
++  vst1_s16 (vech16x4_res, vmul_n_s16 (vech16x4_src, elemhA));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vech16x4_res[indx] != expectedh4_1[indx])
++      abort ();
++
++  vst1_s16 (vech16x4_res, vmul_n_s16 (vech16x4_src, elemhB));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vech16x4_res[indx] != expectedh4_2[indx])
++      abort ();
++
++  vst1_s16 (vech16x4_res, vmul_n_s16 (vech16x4_src, elemhC));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vech16x4_res[indx] != expectedh4_3[indx])
++      abort ();
++
++  vst1_s16 (vech16x4_res, vmul_n_s16 (vech16x4_src, elemhD));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vech16x4_res[indx] != expectedh4_4[indx])
++      abort ();
++}
++
++void
++check_v4hi_unsigned (uint16_t elemuhA, uint16_t elemuhB, uint16_t elemuhC,
++		     uint16_t elemuhD)
++{
++  int indx;
++  const uint16_t vecuh16x4_buf[4] = {AUH, BUH, CUH, DUH};
++  uint16x4_t vecuh16x4_src = vld1_u16 (vecuh16x4_buf);
++  uint16_t vecuh16x4_res[4];
++
++  vst1_u16 (vecuh16x4_res, vmul_n_u16 (vecuh16x4_src, elemuhA));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecuh16x4_res[indx] != expecteduh4_1[indx])
++      abort ();
++
++  vst1_u16 (vecuh16x4_res, vmul_n_u16 (vecuh16x4_src, elemuhB));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecuh16x4_res[indx] != expecteduh4_2[indx])
++      abort ();
++
++  vst1_u16 (vecuh16x4_res, vmul_n_u16 (vecuh16x4_src, elemuhC));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecuh16x4_res[indx] != expecteduh4_3[indx])
++      abort ();
++
++  vst1_u16 (vecuh16x4_res, vmul_n_u16 (vecuh16x4_src, elemuhD));
++
++  for (indx = 0; indx < 4; indx++)
++    if (vecuh16x4_res[indx] != expecteduh4_4[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "mul\tv\[0-9\]+\.4h, v\[0-9\]+\.4h, v\[0-9\]+\.h\\\[0\\\]" 8 } } */
++}
++
++void
++check_v8hi (int16_t elemhA, int16_t elemhB, int16_t elemhC, int16_t elemhD,
++	    int16_t elemhE, int16_t elemhF, int16_t elemhG, int16_t elemhH)
++{
++  int32_t indx;
++  const int16_t vech16x8_buf[8] = {AH, BH, CH, DH, EH, FH, GH, HH};
++  int16x8_t vech16x8_src = vld1q_s16 (vech16x8_buf);
++  int16_t vech16x8_res[8];
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhA));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_1[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhB));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_2[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhC));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_3[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhD));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_4[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhE));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_5[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhF));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_6[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhG));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_7[indx])
++      abort ();
++
++  vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhH));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vech16x8_res[indx] != expectedh8_8[indx])
++      abort ();
++}
++
++void
++check_v8hi_unsigned (uint16_t elemuhA, uint16_t elemuhB, uint16_t elemuhC,
++		     uint16_t elemuhD, uint16_t elemuhE, uint16_t elemuhF,
++		     uint16_t elemuhG, uint16_t elemuhH)
++{
++  int indx;
++  const uint16_t vecuh16x8_buf[8] = {AUH, BUH, CUH, DUH, EUH, FUH, GUH, HUH};
++  uint16x8_t vecuh16x8_src = vld1q_u16 (vecuh16x8_buf);
++  uint16_t vecuh16x8_res[8];
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhA));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_1[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhB));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_2[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhC));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_3[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhD));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_4[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhE));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_5[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhF));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_6[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhG));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_7[indx])
++      abort ();
++
++  vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhH));
++
++  for (indx = 0; indx < 8; indx++)
++    if (vecuh16x8_res[indx] != expecteduh8_8[indx])
++      abort ();
++
++/* { dg-final { scan-assembler-times "mul\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[0\\\]" 16 } } */
++}
++
++int
++main (void)
++{
++  check_v2sf (_elemA, _elemB);
++  check_v4sf (_elemA, _elemB, _elemC, _elemD);
++  check_v2df (_elemdC, _elemdD);
++  check_v2si (_elemsA, _elemsB);
++  check_v4si (_elemsA, _elemsB, _elemsC, _elemsD);
++  check_v4hi (_elemhA, _elemhB, _elemhC, _elemhD);
++  check_v8hi (_elemhA, _elemhB, _elemhC, _elemhD,
++	      _elemhE, _elemhF, _elemhG, _elemhH);
++  check_v2si_unsigned (_elemusA, _elemusB);
++  check_v4si_unsigned (_elemusA, _elemusB, _elemusC, _elemusD);
++  check_v4hi_unsigned (_elemuhA, _elemuhB, _elemuhC, _elemuhD);
++  check_v8hi_unsigned (_elemuhA, _elemuhB, _elemuhC, _elemuhD,
++		       _elemuhE, _elemuhF, _elemuhG, _elemuhH);
++
++  return 0;
++}
++
+--- a/src/gcc/testsuite/gcc.target/aarch64/stack-checking.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/stack-checking.c
+@@ -1,4 +1,5 @@
+ /* { dg-do run { target { *-*-linux* } } } */
++/* { dg-require-stack-check "" } */
+ /* { dg-options "-fstack-check" } */
+ 
+ int main(void)
+--- a/src/gcc/testsuite/gcc.target/aarch64/store-pair-1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/store-pair-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2" } */
++/* { dg-options "-O2 -mcpu=generic" } */
+ 
+ int f(int *a, int b)
+ {
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/store_repeating_constant_1.c
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mtune=generic" } */
++
++void
++foo (unsigned long long *a)
++{
++  a[0] = 0x0140c0da0140c0daULL;
++}
++
++/* { dg-final { scan-assembler-times "movk\\tw.*" 1 } } */
++/* { dg-final { scan-assembler-times "stp\tw\[0-9\]+, w\[0-9\]+.*" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/store_repeating_constant_2.c
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-options "-Os" } */
++
++/* Check that for -Os we synthesize only the bottom half and then
++   store it twice with an STP rather than synthesizing it twice in each
++   half of an X-reg.  */
++
++void
++foo (unsigned long long *a)
++{
++  a[0] = 0xc0da0000c0daULL;
++}
++
++/* { dg-final { scan-assembler-times "mov\\tw.*" 1 } } */
++/* { dg-final { scan-assembler-times "stp\tw\[0-9\]+, w\[0-9\]+.*" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/struct_return.c
+@@ -0,0 +1,31 @@
++/* Test the absence of a spurious move from x8 to x0 for functions
++   return structures.  */
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++struct s
++{
++  long x;
++  long y;
++  long z;
++};
++
++struct s __attribute__((noinline))
++foo (long a, long d, long c)
++{
++  struct s b;
++  b.x = a;
++  b.y = d;
++  b.z = c;
++  return b;
++}
++
++int
++main (void)
++{
++  struct s x;
++  x = foo ( 10, 20, 30);
++  return x.x + x.y + x.z;
++}
++
++/* { dg-final { scan-assembler-not "mov\tx0, x8" } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
+@@ -4,8 +4,7 @@
+      * total frame size > 512.
+        area except outgoing <= 512
+      * number of callee-saved reg >= 2.
+-     * Split stack adjustment into two subtractions.
+-       the first subtractions could be optimized into "stp !".  */
++     * Use a single stack adjustment, no writeback.  */
+ 
+ /* { dg-do run } */
+ /* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
+@@ -15,6 +14,6 @@
+ t_frame_pattern_outgoing (test10, 480, "x19", 24, a[8], a[9], a[10])
+ t_frame_run (test10)
+ 
+-/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
+-/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" 1 } } */
++/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, \[0-9\]+\\\]" 1 } } */
++/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp, \[0-9\]+\\\]" 1 } } */
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_12.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_12.c
+@@ -13,6 +13,6 @@ t_frame_run (test12)
+ 
+ /* { dg-final { scan-assembler-times "sub\tsp, sp, #\[0-9\]+" 1 } } */
+ 
+-/* Check epilogue using write-back.  */
+-/* { dg-final { scan-assembler-times "ldp\tx29, x30, \\\[sp\\\], \[0-9\]+" 3 } } */
++/* Check epilogue using no write-back.  */
++/* { dg-final { scan-assembler-times "ldp\tx29, x30, \\\[sp, \[0-9\]+\\\]" 1 } } */
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_13.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_13.c
+@@ -2,8 +2,7 @@
+      * without outgoing.
+      * total frame size > 512.
+      * number of callee-save reg >= 2.
+-     * split the stack adjustment into two substractions,
+-       the second could be optimized into "stp !".  */
++     * Use a single stack adjustment, no writeback.  */
+ 
+ /* { dg-do run } */
+ /* { dg-options "-O2 --save-temps" } */
+@@ -14,4 +13,4 @@ t_frame_pattern (test13, 700, )
+ t_frame_run (test13)
+ 
+ /* { dg-final { scan-assembler-times "sub\tsp, sp, #\[0-9\]+" 1 } } */
+-/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
++/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp\\\]" 1 } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_15.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_15.c
+@@ -3,8 +3,7 @@
+      * total frame size > 512.
+        area except outgoing <= 512
+      * number of callee-save reg >= 2.
+-     * split the stack adjustment into two substractions,
+-       the first could be optimized into "stp !".  */
++     * Use a single stack adjustment, no writeback.  */
+ 
+ /* { dg-do run } */
+ /* { dg-options "-O2 --save-temps" } */
+@@ -15,4 +14,4 @@ t_frame_pattern_outgoing (test15, 480, , 8, a[8])
+ t_frame_run (test15)
+ 
+ /* { dg-final { scan-assembler-times "sub\tsp, sp, #\[0-9\]+" 1 } } */
+-/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 3 } } */
++/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, \[0-9\]+\\\]" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_16.c
+@@ -0,0 +1,25 @@
++/* Verify:
++     * with outgoing.
++     * single int register push.
++     * varargs and callee-save size >= 256
++     * Use 2 stack adjustments.  */
++
++/* { dg-do compile } */
++/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
++
++#define REP8(X) X,X,X,X,X,X,X,X
++#define REP64(X) REP8(REP8(X))
++
++void outgoing (__builtin_va_list, ...);
++
++double vararg_outgoing (int x1, ...)
++{
++  double a1 = x1, a2 = x1 * 2, a3 = x1 * 3, a4 = x1 * 4, a5 = x1 * 5, a6 = x1 * 6;
++  __builtin_va_list vl;
++  __builtin_va_start (vl, x1);
++  outgoing (vl, a1, a2, a3, a4, a5, a6, REP64 (1));
++  __builtin_va_end (vl);
++  return a1 + a2 + a3 + a4 + a5 + a6;
++}
++
++/* { dg-final { scan-assembler-times "sub\tsp, sp, #\[0-9\]+" 2 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_17.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 --save-temps" } */
++
++/* Test reuse of stack adjustment temporaries.  */
++
++void foo ();
++
++int reuse_mov (int i)
++{
++  int arr[1025];
++  return arr[i];
++}
++
++int no_reuse_mov (int i)
++{
++  int arr[1025];
++  foo ();
++  return arr[i];
++}
++
++/* { dg-final { scan-assembler-times "mov\tx16, \[0-9\]+" 3 } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_6.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_6.c
+@@ -3,8 +3,7 @@
+      * without outgoing.
+      * total frame size > 512.
+      * number of callee-saved reg == 1.
+-     * split stack adjustment into two subtractions.
+-       the second subtraction should use "str !".  */
++     * use a single stack adjustment, no writeback.  */
+ 
+ /* { dg-do run } */
+ /* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
+@@ -14,6 +13,7 @@
+ t_frame_pattern (test6, 700, )
+ t_frame_run (test6)
+ 
+-/* { dg-final { scan-assembler-times "str\tx30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
+-/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\], \[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler-times "str\tx30, \\\[sp\\\]" 1 } } */
++/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\]" 2 } } */
++/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\]," 1 } } */
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
+@@ -3,8 +3,7 @@
+      * without outgoing.
+      * total frame size > 512.
+      * number of callee-saved reg == 2.
+-     * split stack adjustment into two subtractions.
+-       the second subtraction should use "stp !".  */
++     * use a single stack adjustment, no writeback.  */
+ 
+ /* { dg-do run } */
+ /* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */
+@@ -14,6 +13,6 @@
+ t_frame_pattern (test7, 700, "x19")
+ t_frame_run (test7)
+ 
+-/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
+-/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" 1 } } */
++/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp]" 1 } } */
++/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\]" 1 } } */
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/test_frame_8.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/test_frame_8.c
+@@ -12,6 +12,6 @@
+ t_frame_pattern_outgoing (test8, 700, , 8, a[8])
+ t_frame_run (test8)
+ 
+-/* { dg-final { scan-assembler-times "str\tx30, \\\[sp, -\[0-9\]+\\\]!" 3 } } */
+-/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\], \[0-9\]+" 3 } } */
++/* { dg-final { scan-assembler-times "str\tx30, \\\[sp, \[0-9\]+\\\]" 1 } } */
++/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp, \[0-9\]+\\\]" 1 } } */
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/thunderxloadpair.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mcpu=thunderx" } */
++
++struct ldp
++{
++  long long c;
++  int a, b;
++};
++
++
++int f(struct ldp *a)
++{
++  return a->a + a->b;
++}
++
++
++/* We know the alignement of a->a to be 8 byte aligned so it is profitable
++   to do ldp. */
++/* { dg-final { scan-assembler-times "ldp\tw\[0-9\]+, w\[0-9\]" 1 } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/thunderxnoloadpair.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mcpu=thunderx" } */
++
++struct noldp
++{
++  int a, b;
++};
++
++
++int f(struct noldp *a)
++{
++  return a->a + a->b;
++}
++
++/* We know the alignement of a->a to be 4 byte aligned so it is not profitable
++   to do ldp. */
++/* { dg-final { scan-assembler-not "ldp\tw\[0-9\]+, w\[0-9\]" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++/* Check that an X-reg UBFIZ can be simplified into a W-reg LSL.  */
++
++long long
++f2 (long long x)
++{
++  return (x << 5) & 0xffffffff;
++}
++
++/* { dg-final { scan-assembler "lsl\tw" } } */
++/* { dg-final { scan-assembler-not "ubfiz\tx" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/ubfx_lsr_1.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++/* Check that an X-reg UBFX can be simplified into a W-reg LSR.  */
++
++int
++f (unsigned long long x)
++{
++  x = (x >> 24) & 255;
++  return x + 1;
++}
++
++/* { dg-final { scan-assembler "lsr\tw" } } */
++/* { dg-final { scan-assembler-not "ubfx\tx" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/va_arg_1.c
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 --save-temps" } */
++
++int
++f (int a, ...)
++{
++  /* { dg-final { scan-assembler-not "str" } } */
++  return a;
++}
++
++/* { dg-final { cleanup-saved-temps } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/va_arg_2.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 --save-temps" } */
++
++int
++foo (char *fmt, ...)
++{
++  int d;
++  __builtin_va_list ap;
++
++  __builtin_va_start (ap, fmt);
++  d = __builtin_va_arg (ap, int);
++  __builtin_va_end (ap);
++
++  /* { dg-final { scan-assembler-not "x7" } } */
++  return d;
++}
++
++/* { dg-final { cleanup-saved-temps } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/va_arg_3.c
+@@ -0,0 +1,26 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 --save-temps" } */
++
++int d2i (double a);
++
++int
++foo (char *fmt, ...)
++{
++  int d, e;
++  double f, g;
++  __builtin_va_list ap;
++
++  __builtin_va_start (ap, fmt);
++  d = __builtin_va_arg (ap, int);
++  f = __builtin_va_arg (ap, double);
++  g = __builtin_va_arg (ap, double);
++  d += d2i (f);
++  d += d2i (g);
++  __builtin_va_end (ap);
++
++  /* { dg-final { scan-assembler-not "x7" } } */
++  /* { dg-final { scan-assembler-not "q7" } } */
++  return d;
++}
++
++/* { dg-final { cleanup-saved-temps } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c
+@@ -1,6 +1,6 @@
+ 
+ /* { dg-do compile } */
+-/* { dg-options "-O3" } */
++/* { dg-options "-O3 -fno-vect-cost-model" } */
+ 
+ #define N 16
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-clz.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-clz.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O3 -save-temps -fno-inline" } */
++/* { dg-options "-O3 -save-temps -fno-inline -fno-vect-cost-model" } */
+ 
+ extern void abort ();
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline -fno-vect-cost-model" } */
+ 
+ #define FTYPE double
+ #define ITYPE long
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline -fno-vect-cost-model" } */
+ 
+ #define FTYPE double
+ #define ITYPE long
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline -fno-vect-cost-model" } */
+ 
+ #define FTYPE double
+ #define ITYPE long
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-vect-cost-model" } */
+ 
+ #define N 32
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmovd.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmovd.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-vect-cost-model" } */
+ 
+ #define N 32
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-vect-cost-model" } */
+ 
+ #define N 32
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fmovf.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fmovf.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-vect-cost-model" } */
+ 
+ #define N 32
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c
+@@ -0,0 +1,86 @@
++/* { dg-do compile } */
++/* { dg-options "-O3" } */
++
++#include "arm_neon.h"
++
++#define BUILD_TEST(TYPE1, TYPE2, Q1, Q2, SUFFIX, INDEX1, INDEX2)	\
++TYPE1 __attribute__((noinline,noclone))					\
++test_copy##Q1##_lane##Q2##_##SUFFIX (TYPE1 a, TYPE2 b)			\
++{									\
++  return vcopy##Q1##_lane##Q2##_##SUFFIX (a, INDEX1, b, INDEX2);	\
++}
++
++/* vcopy_lane.  */
++BUILD_TEST (poly8x8_t, poly8x8_t, , , p8, 7, 6)
++BUILD_TEST (int8x8_t,  int8x8_t,  , , s8, 7, 6)
++BUILD_TEST (uint8x8_t, uint8x8_t, , , u8, 7, 6)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[7\\\], v1.b\\\[6\\\]" 3 } } */
++BUILD_TEST (poly16x4_t, poly16x4_t, , , p16, 3, 2)
++BUILD_TEST (int16x4_t,  int16x4_t,  , , s16, 3, 2)
++BUILD_TEST (uint16x4_t, uint16x4_t, , , u16, 3, 2)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[3\\\], v1.h\\\[2\\\]" 3 } } */
++BUILD_TEST (float32x2_t, float32x2_t, , , f32, 1, 0)
++BUILD_TEST (int32x2_t,   int32x2_t,   , , s32, 1, 0)
++BUILD_TEST (uint32x2_t,  uint32x2_t,  , , u32, 1, 0)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[0\\\]" 3 } } */
++BUILD_TEST (int64x1_t,   int64x1_t,   , , s64, 0, 0)
++BUILD_TEST (uint64x1_t,  uint64x1_t,  , , u64, 0, 0)
++BUILD_TEST (float64x1_t, float64x1_t, , , f64, 0, 0)
++/* { dg-final { scan-assembler-times "fmov\\td0, d1" 3 } } */
++
++/* vcopy_laneq.  */
++
++BUILD_TEST (poly8x8_t, poly8x16_t, , q, p8, 7, 15)
++BUILD_TEST (int8x8_t,  int8x16_t,  , q, s8, 7, 15)
++BUILD_TEST (uint8x8_t, uint8x16_t, , q, u8, 7, 15)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[7\\\], v1.b\\\[15\\\]" 3 } } */
++BUILD_TEST (poly16x4_t, poly16x8_t, , q, p16, 3, 7)
++BUILD_TEST (int16x4_t,  int16x8_t,  , q, s16, 3, 7)
++BUILD_TEST (uint16x4_t, uint16x8_t, , q, u16, 3, 7)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[3\\\], v1.h\\\[7\\\]" 3 } } */
++BUILD_TEST (float32x2_t, float32x4_t, , q, f32, 1, 3)
++BUILD_TEST (int32x2_t,   int32x4_t,   , q, s32, 1, 3)
++BUILD_TEST (uint32x2_t,  uint32x4_t,  , q, u32, 1, 3)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[3\\\]" 3 } } */
++BUILD_TEST (float64x1_t, float64x2_t, , q, f64, 0, 1)
++BUILD_TEST (int64x1_t,  int64x2_t,    , q, s64, 0, 1)
++BUILD_TEST (uint64x1_t, uint64x2_t,   , q, u64, 0, 1)
++/* XFAIL due to PR 71307.  */
++/* { dg-final { scan-assembler-times "dup\\td0, v1.d\\\[1\\\]" 3 { xfail *-*-* } } } */
++
++/* vcopyq_lane.  */
++BUILD_TEST (poly8x16_t, poly8x8_t, q, , p8, 15, 7)
++BUILD_TEST (int8x16_t,  int8x8_t,  q, , s8, 15, 7)
++BUILD_TEST (uint8x16_t, uint8x8_t, q, , u8, 15, 7)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[15\\\], v1.b\\\[7\\\]" 3 } } */
++BUILD_TEST (poly16x8_t, poly16x4_t, q, , p16, 7, 3)
++BUILD_TEST (int16x8_t,  int16x4_t,  q, , s16, 7, 3)
++BUILD_TEST (uint16x8_t, uint16x4_t, q, , u16, 7, 3)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[7\\\], v1.h\\\[3\\\]" 3 } } */
++BUILD_TEST (float32x4_t, float32x2_t, q, , f32, 3, 1)
++BUILD_TEST (int32x4_t,   int32x2_t,   q, , s32, 3, 1)
++BUILD_TEST (uint32x4_t,  uint32x2_t,  q, , u32, 3, 1)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[3\\\], v1.s\\\[1\\\]" 3 } } */
++BUILD_TEST (float64x2_t, float64x1_t, q, , f64, 1, 0)
++BUILD_TEST (int64x2_t,   int64x1_t,   q, , s64, 1, 0)
++BUILD_TEST (uint64x2_t,  uint64x1_t,  q, , u64, 1, 0)
++/* { dg-final { scan-assembler-times "ins\\tv0.d\\\[1\\\], v1.d\\\[0\\\]" 3 } } */
++
++/* vcopyq_laneq.  */
++
++BUILD_TEST (poly8x16_t, poly8x16_t, q, q, p8, 14, 15)
++BUILD_TEST (int8x16_t,  int8x16_t,  q, q, s8, 14, 15)
++BUILD_TEST (uint8x16_t, uint8x16_t, q, q, u8, 14, 15)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[14\\\], v1.b\\\[15\\\]" 3 } } */
++BUILD_TEST (poly16x8_t, poly16x8_t, q, q, p16, 6, 7)
++BUILD_TEST (int16x8_t,  int16x8_t,  q, q, s16, 6, 7)
++BUILD_TEST (uint16x8_t, uint16x8_t, q, q, u16, 6, 7)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[6\\\], v1.h\\\[7\\\]" 3 } } */
++BUILD_TEST (float32x4_t, float32x4_t, q, q, f32, 2, 3)
++BUILD_TEST (int32x4_t,   int32x4_t,   q, q, s32, 2, 3)
++BUILD_TEST (uint32x4_t,  uint32x4_t,  q, q, u32, 2, 3)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[2\\\], v1.s\\\[3\\\]" 3 } } */
++BUILD_TEST (float64x2_t, float64x2_t, q, q, f64, 1, 1)
++BUILD_TEST (int64x2_t,   int64x2_t,   q,  q, s64, 1, 1)
++BUILD_TEST (uint64x2_t,  uint64x2_t,  q, q, u64, 1, 1)
++/* { dg-final { scan-assembler-times "ins\\tv0.d\\\[1\\\], v1.d\\\[1\\\]" 3 } } */
+--- a/src/gcc/testsuite/gcc.target/aarch64/vect_ctz_1.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vect_ctz_1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O3 -save-temps -fno-inline" } */
++/* { dg-options "-O3 -save-temps -fno-inline -fno-vect-cost-model" } */
+ 
+ extern void abort ();
+ 
+--- a/src/gcc/testsuite/gcc.target/aarch64/vector_initialization_nostack.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vector_initialization_nostack.c
+@@ -38,14 +38,14 @@ f11 (void)
+   return sum;
+ }
+ 
+-char arr_c[100][100];
++char arr_c[100];
+ char
+ f12 (void)
+ {
+   int i;
+   char sum = 0;
+   for (i = 0; i < 100; i++)
+-    sum += arr_c[i][0] * arr_c[0][i];
++    sum += arr_c[i] * arr_c[i];
+   return sum;
+ }
+ 
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/vget_set_lane_1.c
+@@ -0,0 +1,72 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++#include "arm_neon.h"
++
++#define BUILD_TEST(TYPE1, TYPE2, Q1, Q2, SUFFIX, INDEX1, INDEX2)	\
++TYPE1 __attribute__((noinline,noclone))				\
++test_copy##Q1##_lane##Q2##_##SUFFIX (TYPE1 a, TYPE2 b)			\
++{									\
++  return vset##Q1##_lane_##SUFFIX (vget##Q2##_lane_##SUFFIX (b, INDEX2),\
++				    a, INDEX1);				\
++}
++
++BUILD_TEST (poly8x8_t, poly8x8_t, , , p8, 7, 6)
++BUILD_TEST (int8x8_t,  int8x8_t,  , , s8, 7, 6)
++BUILD_TEST (uint8x8_t, uint8x8_t, , , u8, 7, 6)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[7\\\], v1.b\\\[6\\\]" 3 } } */
++BUILD_TEST (poly16x4_t, poly16x4_t, , , p16, 3, 2)
++BUILD_TEST (int16x4_t,  int16x4_t,  , , s16, 3, 2)
++BUILD_TEST (uint16x4_t, uint16x4_t, , , u16, 3, 2)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[3\\\], v1.h\\\[2\\\]" 3 } } */
++BUILD_TEST (float32x2_t, float32x2_t, , , f32, 1, 0)
++BUILD_TEST (int32x2_t,   int32x2_t,   , , s32, 1, 0)
++BUILD_TEST (uint32x2_t,  uint32x2_t,  , , u32, 1, 0)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[0\\\]" 3 } } */
++
++BUILD_TEST (poly8x8_t, poly8x16_t, , q, p8, 7, 15)
++BUILD_TEST (int8x8_t,  int8x16_t,  , q, s8, 7, 15)
++BUILD_TEST (uint8x8_t, uint8x16_t, , q, u8, 7, 15)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[7\\\], v1.b\\\[15\\\]" 3 } } */
++BUILD_TEST (poly16x4_t, poly16x8_t, , q, p16, 3, 7)
++BUILD_TEST (int16x4_t,  int16x8_t,  , q, s16, 3, 7)
++BUILD_TEST (uint16x4_t, uint16x8_t, , q, u16, 3, 7)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[3\\\], v1.h\\\[7\\\]" 3 } } */
++BUILD_TEST (float32x2_t, float32x4_t, , q, f32, 1, 3)
++BUILD_TEST (int32x2_t,   int32x4_t,   , q, s32, 1, 3)
++BUILD_TEST (uint32x2_t,  uint32x4_t,  , q, u32, 1, 3)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[3\\\]" 3 } } */
++
++BUILD_TEST (poly8x16_t, poly8x8_t, q, , p8, 15, 7)
++BUILD_TEST (int8x16_t,  int8x8_t,  q, , s8, 15, 7)
++BUILD_TEST (uint8x16_t, uint8x8_t, q, , u8, 15, 7)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[15\\\], v1.b\\\[7\\\]" 3 } } */
++BUILD_TEST (poly16x8_t, poly16x4_t, q, , p16, 7, 3)
++BUILD_TEST (int16x8_t,  int16x4_t,  q, , s16, 7, 3)
++BUILD_TEST (uint16x8_t, uint16x4_t, q, , u16, 7, 3)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[7\\\], v1.h\\\[3\\\]" 3 } } */
++BUILD_TEST (float32x4_t, float32x2_t, q, , f32, 3, 1)
++BUILD_TEST (int32x4_t,   int32x2_t,   q, , s32, 3, 1)
++BUILD_TEST (uint32x4_t,  uint32x2_t,  q, , u32, 3, 1)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[3\\\], v1.s\\\[1\\\]" 3 } } */
++BUILD_TEST (float64x2_t, float64x1_t, q, , f64, 1, 0)
++BUILD_TEST (int64x2_t,   int64x1_t,   q, , s64, 1, 0)
++BUILD_TEST (uint64x2_t,  uint64x1_t,  q, , u64, 1, 0)
++/* { dg-final { scan-assembler-times "ins\\tv0.d\\\[1\\\], v1.d\\\[0\\\]" 3 } } */
++
++BUILD_TEST (poly8x16_t, poly8x16_t, q, q, p8, 14, 15)
++BUILD_TEST (int8x16_t,  int8x16_t,  q, q, s8, 14, 15)
++BUILD_TEST (uint8x16_t, uint8x16_t, q, q, u8, 14, 15)
++/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[14\\\], v1.b\\\[15\\\]" 3 } } */
++BUILD_TEST (poly16x8_t, poly16x8_t, q, q, p16, 6, 7)
++BUILD_TEST (int16x8_t,  int16x8_t,  q, q, s16, 6, 7)
++BUILD_TEST (uint16x8_t, uint16x8_t, q, q, u16, 6, 7)
++/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[6\\\], v1.h\\\[7\\\]" 3 } } */
++BUILD_TEST (float32x4_t, float32x4_t, q, q, f32, 2, 3)
++BUILD_TEST (int32x4_t,   int32x4_t,   q, q, s32, 2, 3)
++BUILD_TEST (uint32x4_t,  uint32x4_t,  q, q, u32, 2, 3)
++/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[2\\\], v1.s\\\[3\\\]" 3 } } */
++BUILD_TEST (float64x2_t, float64x2_t, q, q, f64, 1, 1)
++BUILD_TEST (int64x2_t,   int64x2_t,   q,  q, s64, 1, 1)
++BUILD_TEST (uint64x2_t,  uint64x2_t,  q, q, u64, 1, 1)
++/* { dg-final { scan-assembler-times "ins\\tv0.d\\\[1\\\], v1.d\\\[1\\\]" 3 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/vminmaxnm.c
+@@ -0,0 +1,37 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++#include "arm_neon.h"
++
++/* For each of these intrinsics, we map directly to an unspec in RTL.
++   We're just using the argument directly and returning the result, so we
++   can precisely specify the exact instruction pattern and register
++   allocations we expect.  */
++
++float64x1_t
++test_vmaxnm_f64 (float64x1_t a, float64x1_t b)
++{
++  /* { dg-final { scan-assembler-times "fmaxnm\td0, d0, d1" 1 } } */
++  return vmaxnm_f64 (a, b);
++}
++
++float64x1_t
++test_vminnm_f64 (float64x1_t a, float64x1_t b)
++{
++  /* { dg-final { scan-assembler-times "fminnm\td0, d0, d1" 1 } } */
++  return vminnm_f64 (a, b);
++}
++
++float64x1_t
++test_vmax_f64 (float64x1_t a, float64x1_t b)
++{
++  /* { dg-final { scan-assembler-times "fmax\td0, d0, d1" 1 } } */
++  return vmax_f64 (a, b);
++}
++
++float64x1_t
++test_vmin_f64 (float64x1_t a, float64x1_t b)
++{
++  /* { dg-final { scan-assembler-times "fmin\td0, d0, d1" 1 } } */
++  return vmin_f64 (a, b);
++}
+\ No newline at end of file
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c
+@@ -0,0 +1,32 @@
++/* Test AAPCS layout (VFP variant for Neon types) */
++
++/* { dg-do run { target arm_eabi } } */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_neon_fp16_hw } */
++/* { dg-add-options arm_neon_fp16 } */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define NEON
++#define TESTFILE "neon-vect10.c"
++#include "neon-constants.h"
++
++#include "abitest.h"
++#else
++
++ARG (int32x4_t, i32x4_constvec2, Q0) /* D0, D1.  */
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 3.0f, S4 + 2) /* D2, Q1.  */
++#else
++ARG (__fp16, 3.0f, S4) /* D2, Q1.  */
++#endif
++ARG (int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12.  */
++ARG (double, 12.0, D3) /* Backfill this particular argument.  */
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 5.0f, S5 + 2) /* Backfill in S5.  */
++#else
++ARG (__fp16, 5.0f, S5) /* Backfill in S5.  */
++#endif
++ARG (int32x4x2_t, i32x4x2_constvec2, STACK)
++LAST_ARG (int, 3, R0)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c
+@@ -0,0 +1,24 @@
++/* Test AAPCS layout (VFP variant for Neon types) */
++
++/* { dg-do run { target arm_eabi } } */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_neon_fp16_hw } */
++/* { dg-add-options arm_neon_fp16 } */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define NEON
++#define TESTFILE "neon-vect9.c"
++#include "neon-constants.h"
++
++#include "abitest.h"
++#else
++
++ARG (int32x4_t, i32x4_constvec2, Q0) /* D0, D1.  */
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 3.0f, S4 + 2) /* D2, Q1 occupied.  */
++#else
++ARG (__fp16, 3.0f, S4) /* D2, Q1 occupied.  */
++#endif
++LAST_ARG (int, 3, R0)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp18.c
+@@ -0,0 +1,28 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_ieee }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp18.c"
++#include "abitest.h"
++
++#else
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, S0 + 2)
++#else
++ARG (__fp16, 1.0f, S0)
++#endif
++ARG (float, 2.0f, S1)
++ARG (double, 4.0, D1)
++ARG (float, 2.0f, S4)
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, S5 + 2)
++#else
++ARG (__fp16, 1.0f, S5)
++#endif
++LAST_ARG (int, 3, R0)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp19.c
+@@ -0,0 +1,30 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_ieee }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp19.c"
++
++__complex__ x = 1.0+2.0i;
++
++#include "abitest.h"
++#else
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, S0 + 2)
++#else
++ARG (__fp16, 1.0f, S0)
++#endif
++ARG (float, 2.0f, S1)
++ARG (__complex__ double, x, D1)
++ARG (float, 3.0f, S6)
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 2.0f, S7 + 2)
++#else
++ARG (__fp16, 2.0f, S7)
++#endif
++LAST_ARG (int, 3, R0)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp20.c
+@@ -0,0 +1,22 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_ieee }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp20.c"
++
++#define PCSATTR __attribute__((pcs("aapcs")))
++
++#include "abitest.h"
++#else
++ARG (float, 1.0f, R0)
++ARG (double, 2.0, R2)
++ARG (float, 3.0f, STACK)
++ARG (__fp16, 2.0f, STACK+4)
++LAST_ARG (double, 4.0, STACK+8)
++#endif
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp21.c
+@@ -0,0 +1,26 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_ieee }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp21.c"
++
++#define PCSATTR __attribute__((pcs("aapcs")))
++
++#include "abitest.h"
++#else
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, R0 + 2)
++#else
++ARG (__fp16, 1.0f, R0)
++#endif
++ARG (double, 2.0, R2)
++ARG (__fp16, 3.0f, STACK)
++ARG (float, 2.0f, STACK+4)
++LAST_ARG (double, 4.0, STACK+8)
++#endif
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp22.c
+@@ -0,0 +1,28 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_alternative }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp22.c"
++#include "abitest.h"
++
++#else
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, S0 + 2)
++#else
++ARG (__fp16, 1.0f, S0)
++#endif
++ARG (float, 2.0f, S1)
++ARG (double, 4.0, D1)
++ARG (float, 2.0f, S4)
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, S5 + 2)
++#else
++ARG (__fp16, 1.0f, S5)
++#endif
++LAST_ARG (int, 3, R0)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp23.c
+@@ -0,0 +1,30 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_alternative }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp23.c"
++
++__complex__ x = 1.0+2.0i;
++
++#include "abitest.h"
++#else
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, S0 + 2)
++#else
++ARG (__fp16, 1.0f, S0)
++#endif
++ARG (float, 2.0f, S1)
++ARG (__complex__ double, x, D1)
++ARG (float, 3.0f, S6)
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 2.0f, S7 + 2)
++#else
++ARG (__fp16, 2.0f, S7)
++#endif
++LAST_ARG (int, 3, R0)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp24.c
+@@ -0,0 +1,21 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_alternative }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp24.c"
++
++#define PCSATTR __attribute__((pcs("aapcs")))
++
++#include "abitest.h"
++#else
++ARG (float, 1.0f, R0)
++ARG (double, 2.0, R2)
++ARG (float, 3.0f, STACK)
++ARG (__fp16, 2.0f, STACK+4)
++LAST_ARG (double, 4.0, STACK+8)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/aapcs/vfp25.c
+@@ -0,0 +1,25 @@
++/* Test AAPCS layout (VFP variant)  */
++
++/* { dg-do run { target arm_eabi } }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_hw }  */
++/* { dg-add-options arm_fp16_alternative }  */
++
++#ifndef IN_FRAMEWORK
++#define VFP
++#define TESTFILE "vfp25.c"
++
++#define PCSATTR __attribute__((pcs("aapcs")))
++
++#include "abitest.h"
++#else
++#if defined (__ARM_BIG_ENDIAN)
++ARG (__fp16, 1.0f, R0 + 2)
++#else
++ARG (__fp16, 1.0f, R0)
++#endif
++ARG (double, 2.0, R2)
++ARG (__fp16, 3.0f, STACK)
++ARG (float, 2.0f, STACK+4)
++LAST_ARG (double, 4.0, STACK+8)
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv5_thumb_isa.c
+@@ -0,0 +1,8 @@
++/* { dg-require-effective-target arm_arch_v5_ok } */
++/* { dg-add-options arm_arch_v5 } */
++
++#if __ARM_ARCH_ISA_THUMB
++#error "__ARM_ARCH_ISA_THUMB defined for ARMv5"
++#endif
++
++int foo;
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv8_2-fp16-arith-1.c
+@@ -0,0 +1,105 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_ok }  */
++/* { dg-options "-O2 -ffast-math" }  */
++/* { dg-add-options arm_v8_2a_fp16_neon }  */
++
++/* Test instructions generated for half-precision arithmetic.  */
++
++typedef __fp16 float16_t;
++typedef __simd64_float16_t float16x4_t;
++typedef __simd128_float16_t float16x8_t;
++
++typedef short int16x4_t __attribute__ ((vector_size (8)));
++typedef short int int16x8_t  __attribute__ ((vector_size (16)));
++
++float16_t
++fp16_abs (float16_t a)
++{
++  return (a < 0) ? -a : a;
++}
++
++#define TEST_UNOP(NAME, OPERATOR, TY)		\
++  TY test_##NAME##_##TY (TY a)			\
++  {						\
++    return OPERATOR (a);			\
++  }
++
++#define TEST_BINOP(NAME, OPERATOR, TY)		\
++  TY test_##NAME##_##TY (TY a, TY b)		\
++  {						\
++    return a OPERATOR b;			\
++  }
++
++#define TEST_CMP(NAME, OPERATOR, RTY, TY)	\
++  RTY test_##NAME##_##TY (TY a, TY b)		\
++  {						\
++    return a OPERATOR b;			\
++  }
++
++/* Scalars.  */
++
++TEST_UNOP (neg, -, float16_t)
++TEST_UNOP (abs, fp16_abs, float16_t)
++
++TEST_BINOP (add, +, float16_t)
++TEST_BINOP (sub, -, float16_t)
++TEST_BINOP (mult, *, float16_t)
++TEST_BINOP (div, /, float16_t)
++
++TEST_CMP (equal, ==, int, float16_t)
++TEST_CMP (unequal, !=, int, float16_t)
++TEST_CMP (lessthan, <, int, float16_t)
++TEST_CMP (greaterthan, >, int, float16_t)
++TEST_CMP (lessthanequal, <=, int, float16_t)
++TEST_CMP (greaterthanqual, >=, int, float16_t)
++
++/* Vectors of size 4.  */
++
++TEST_UNOP (neg, -, float16x4_t)
++
++TEST_BINOP (add, +, float16x4_t)
++TEST_BINOP (sub, -, float16x4_t)
++TEST_BINOP (mult, *, float16x4_t)
++TEST_BINOP (div, /, float16x4_t)
++
++TEST_CMP (equal, ==, int16x4_t, float16x4_t)
++TEST_CMP (unequal, !=, int16x4_t, float16x4_t)
++TEST_CMP (lessthan, <, int16x4_t, float16x4_t)
++TEST_CMP (greaterthan, >, int16x4_t, float16x4_t)
++TEST_CMP (lessthanequal, <=, int16x4_t, float16x4_t)
++TEST_CMP (greaterthanqual, >=, int16x4_t, float16x4_t)
++
++/* Vectors of size 8.  */
++
++TEST_UNOP (neg, -, float16x8_t)
++
++TEST_BINOP (add, +, float16x8_t)
++TEST_BINOP (sub, -, float16x8_t)
++TEST_BINOP (mult, *, float16x8_t)
++TEST_BINOP (div, /, float16x8_t)
++
++TEST_CMP (equal, ==, int16x8_t, float16x8_t)
++TEST_CMP (unequal, !=, int16x8_t, float16x8_t)
++TEST_CMP (lessthan, <, int16x8_t, float16x8_t)
++TEST_CMP (greaterthan, >, int16x8_t, float16x8_t)
++TEST_CMP (lessthanequal, <=, int16x8_t, float16x8_t)
++TEST_CMP (greaterthanqual, >=, int16x8_t, float16x8_t)
++
++/* { dg-final { scan-assembler-times {vneg\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++/* { dg-final { scan-assembler-times {vneg\.f16\td[0-9]+, d[0-9]+} 1 } }  */
++/* { dg-final { scan-assembler-times {vneg\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++/* { dg-final { scan-assembler-times {vabs\.f16\ts[0-9]+, s[0-9]+} 2 } }  */
++
++/* { dg-final { scan-assembler-times {vadd\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 13 } }  */
++/* { dg-final { scan-assembler-times {vsub\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 13 } }  */
++/* { dg-final { scan-assembler-times {vmul\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 13 } }  */
++/* { dg-final { scan-assembler-times {vdiv\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 13 } }  */
++/* { dg-final { scan-assembler-times {vcmp\.f32\ts[0-9]+, s[0-9]+} 26 } }  */
++/* { dg-final { scan-assembler-times {vcmpe\.f32\ts[0-9]+, s[0-9]+} 52 } }  */
++
++/* { dg-final { scan-assembler-not {vadd\.f32} } }  */
++/* { dg-final { scan-assembler-not {vsub\.f32} } }  */
++/* { dg-final { scan-assembler-not {vmul\.f32} } }  */
++/* { dg-final { scan-assembler-not {vdiv\.f32} } }  */
++/* { dg-final { scan-assembler-not {vcmp\.f16} } }  */
++/* { dg-final { scan-assembler-not {vcmpe\.f16} } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv8_2-fp16-conv-1.c
+@@ -0,0 +1,101 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok }  */
++/* { dg-options "-O2" }  */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++/* Test ARMv8.2 FP16 conversions.  */
++#include <arm_fp16.h>
++
++float
++f16_to_f32 (__fp16 a)
++{
++  return (float)a;
++}
++
++float
++f16_to_pf32 (__fp16* a)
++{
++  return (float)*a;
++}
++
++short
++f16_to_s16 (__fp16 a)
++{
++  return (short)a;
++}
++
++short
++pf16_to_s16 (__fp16* a)
++{
++  return (short)*a;
++}
++
++/* { dg-final { scan-assembler-times {vcvtb\.f32\.f16\ts[0-9]+, s[0-9]+} 4 } }  */
++
++__fp16
++f32_to_f16 (float a)
++{
++  return (__fp16)a;
++}
++
++void
++f32_to_pf16 (__fp16* x, float a)
++{
++  *x = (__fp16)a;
++}
++
++__fp16
++s16_to_f16 (short a)
++{
++  return (__fp16)a;
++}
++
++void
++s16_to_pf16 (__fp16* x, short a)
++{
++  *x = (__fp16)a;
++}
++
++/* { dg-final { scan-assembler-times {vcvtb\.f16\.f32\ts[0-9]+, s[0-9]+} 4 } }  */
++
++float
++s16_to_f32 (short a)
++{
++  return (float)a;
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.f32\.s32\ts[0-9]+, s[0-9]+} 3 } }  */
++
++short
++f32_to_s16 (float a)
++{
++  return (short)a;
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.s32\.f32\ts[0-9]+, s[0-9]+} 3 } }  */
++
++unsigned short
++f32_to_u16 (float a)
++{
++  return (unsigned short)a;
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.u32\.f32\ts[0-9]+, s[0-9]+} 1 } }  */
++
++short
++f64_to_s16 (double a)
++{
++  return (short)a;
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.s32\.f64\ts[0-9]+, d[0-9]+} 1 } }  */
++
++unsigned short
++f64_to_u16 (double a)
++{
++  return (unsigned short)a;
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.s32\.f64\ts[0-9]+, d[0-9]+} 1 } }  */
++
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c
+@@ -0,0 +1,165 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok }  */
++/* { dg-options "-O2" }  */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++__fp16
++test_load_1 (__fp16* a)
++{
++  return *a;
++}
++
++__fp16
++test_load_2 (__fp16* a, int i)
++{
++  return a[i];
++}
++
++/* { dg-final { scan-assembler-times {vld1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 2 } }  */
++
++void
++test_store_1 (__fp16* a, __fp16 b)
++{
++  *a = b;
++}
++
++void
++test_store_2 (__fp16* a, int i, __fp16 b)
++{
++  a[i] = b;
++}
++
++/* { dg-final { scan-assembler-times {vst1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 2 } }  */
++
++__fp16
++test_load_store_1 (__fp16* a, int i, __fp16* b)
++{
++  a[i] = b[i];
++}
++
++__fp16
++test_load_store_2 (__fp16* a, int i, __fp16* b)
++{
++  a[i] = b[i + 2];
++  return a[i];
++}
++/* { dg-final { scan-assembler-times {ldrh\tr[0-9]+} 2 } }  */
++/* { dg-final { scan-assembler-times {strh\tr[0-9]+} 2 } }  */
++
++__fp16
++test_select_1 (int sel, __fp16 a, __fp16 b)
++{
++  if (sel)
++    return a;
++  else
++    return b;
++}
++
++__fp16
++test_select_2 (int sel, __fp16 a, __fp16 b)
++{
++  return sel ? a : b;
++}
++
++__fp16
++test_select_3 (__fp16 a, __fp16 b, __fp16 c)
++{
++  return (a == b) ? b : c;
++}
++
++__fp16
++test_select_4 (__fp16 a, __fp16 b, __fp16 c)
++{
++  return (a != b) ? b : c;
++}
++
++__fp16
++test_select_5 (__fp16 a, __fp16 b, __fp16 c)
++{
++  return (a < b) ? b : c;
++}
++
++__fp16
++test_select_6 (__fp16 a, __fp16 b, __fp16 c)
++{
++  return (a <= b) ? b : c;
++}
++
++__fp16
++test_select_7 (__fp16 a, __fp16 b, __fp16 c)
++{
++  return (a > b) ? b : c;
++}
++
++__fp16
++test_select_8 (__fp16 a, __fp16 b, __fp16 c)
++{
++  return (a >= b) ? b : c;
++}
++
++/* { dg-final { scan-assembler-times {vseleq\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 4 } } */
++/* { dg-final { scan-assembler-times {vselgt\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++/* { dg-final { scan-assembler-times {vselge\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++/* { dg-final { scan-assembler-times {vmov\.f16\ts[0-9]+, r[0-9]+} 4 } }  */
++/* { dg-final { scan-assembler-times {vmov\.f16\tr[0-9]+, s[0-9]+} 4 } }  */
++
++int
++test_compare_1 (__fp16 a, __fp16 b)
++{
++  if (a == b)
++    return -1;
++  else
++    return 0;
++}
++
++int
++test_compare_ (__fp16 a, __fp16 b)
++{
++  if (a != b)
++    return -1;
++  else
++    return 0;
++}
++
++int
++test_compare_2 (__fp16 a, __fp16 b)
++{
++  if (a > b)
++    return -1;
++  else
++    return 0;
++}
++
++int
++test_compare_3 (__fp16 a, __fp16 b)
++{
++  if (a >= b)
++    return -1;
++  else
++    return 0;
++}
++
++int
++test_compare_4 (__fp16 a, __fp16 b)
++{
++  if (a < b)
++    return -1;
++  else
++    return 0;
++}
++
++int
++test_compare_5 (__fp16 a, __fp16 b)
++{
++  if (a <= b)
++    return -1;
++  else
++    return 0;
++}
++
++/* { dg-final { scan-assembler-not {vcmp\.f16} } }  */
++/* { dg-final { scan-assembler-not {vcmpe\.f16} } }  */
++
++/* { dg-final { scan-assembler-times {vcmp\.f32} 4 } }  */
++/* { dg-final { scan-assembler-times {vcmpe\.f32} 8 } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-1.c
+@@ -0,0 +1,490 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_ok }  */
++/* { dg-options "-O2" }  */
++/* { dg-add-options arm_v8_2a_fp16_neon }  */
++
++/* Test instructions generated for the FP16 vector intrinsics.  */
++
++#include <arm_neon.h>
++
++#define MSTRCAT(L, str)	L##str
++
++#define UNOP_TEST(insn)				\
++  float16x4_t					\
++  MSTRCAT (test_##insn, _16x4) (float16x4_t a)	\
++  {						\
++    return MSTRCAT (insn, _f16) (a);		\
++  }						\
++  float16x8_t					\
++  MSTRCAT (test_##insn, _16x8) (float16x8_t a)	\
++  {						\
++    return MSTRCAT (insn, q_f16) (a);		\
++  }
++
++#define BINOP_TEST(insn)					\
++  float16x4_t							\
++  MSTRCAT (test_##insn, _16x4) (float16x4_t a, float16x4_t b)	\
++  {								\
++    return MSTRCAT (insn, _f16) (a, b);				\
++  }								\
++  float16x8_t							\
++  MSTRCAT (test_##insn, _16x8) (float16x8_t a, float16x8_t b)	\
++  {								\
++    return MSTRCAT (insn, q_f16) (a, b);			\
++  }
++
++#define BINOP_LANE_TEST(insn, I)					\
++  float16x4_t								\
++  MSTRCAT (test_##insn##_lane, _16x4) (float16x4_t a, float16x4_t b)	\
++  {									\
++    return MSTRCAT (insn, _lane_f16) (a, b, I);				\
++  }									\
++  float16x8_t								\
++  MSTRCAT (test_##insn##_lane, _16x8) (float16x8_t a, float16x4_t b)	\
++  {									\
++    return MSTRCAT (insn, q_lane_f16) (a, b, I);			\
++  }
++
++#define BINOP_LANEQ_TEST(insn, I)					\
++  float16x4_t								\
++  MSTRCAT (test_##insn##_laneq, _16x4) (float16x4_t a, float16x8_t b)	\
++  {									\
++    return MSTRCAT (insn, _laneq_f16) (a, b, I);			\
++  }									\
++  float16x8_t								\
++  MSTRCAT (test_##insn##_laneq, _16x8) (float16x8_t a, float16x8_t b)	\
++  {									\
++    return MSTRCAT (insn, q_laneq_f16) (a, b, I);			\
++  }									\
++
++#define BINOP_N_TEST(insn)					\
++  float16x4_t							\
++  MSTRCAT (test_##insn##_n, _16x4) (float16x4_t a, float16_t b)	\
++  {								\
++    return MSTRCAT (insn, _n_f16) (a, b);			\
++  }								\
++  float16x8_t							\
++  MSTRCAT (test_##insn##_n, _16x8) (float16x8_t a, float16_t b)	\
++  {								\
++    return MSTRCAT (insn, q_n_f16) (a, b);			\
++  }
++
++#define TERNOP_TEST(insn)						\
++  float16_t								\
++  MSTRCAT (test_##insn, _16) (float16_t a, float16_t b, float16_t c)	\
++  {									\
++    return MSTRCAT (insn, h_f16) (a, b, c);				\
++  }									\
++  float16x4_t								\
++  MSTRCAT (test_##insn, _16x4) (float16x4_t a, float16x4_t b,		\
++			       float16x4_t c)				\
++  {									\
++    return MSTRCAT (insn, _f16) (a, b, c);				\
++  }									\
++  float16x8_t								\
++  MSTRCAT (test_##insn, _16x8) (float16x8_t a, float16x8_t b,		\
++			       float16x8_t c)				\
++  {									\
++    return MSTRCAT (insn, q_f16) (a, b, c);				\
++  }
++
++#define VCMP1_TEST(insn)			\
++  uint16x4_t					\
++  MSTRCAT (test_##insn, _16x4) (float16x4_t a)	\
++  {						\
++    return MSTRCAT (insn, _f16) (a);		\
++  }						\
++  uint16x8_t					\
++  MSTRCAT (test_##insn, _16x8) (float16x8_t a)	\
++  {						\
++    return MSTRCAT (insn, q_f16) (a);		\
++  }
++
++#define VCMP2_TEST(insn)					\
++  uint16x4_t							\
++  MSTRCAT (test_##insn, _16x4) (float16x4_t a, float16x4_t b)	\
++  {								\
++    return MSTRCAT (insn, _f16) (a, b);				\
++  }								\
++  uint16x8_t							\
++  MSTRCAT (test_##insn, _16x8) (float16x8_t a, float16x8_t b)	\
++  {								\
++    return MSTRCAT (insn, q_f16) (a, b);			\
++  }
++
++#define VCVT_TEST(insn, TY, TO, FR)			\
++  MSTRCAT (TO, 16x4_t)					\
++  MSTRCAT (test_##insn, TY) (MSTRCAT (FR, 16x4_t) a)	\
++  {							\
++    return MSTRCAT (insn, TY) (a);			\
++  }							\
++  MSTRCAT (TO, 16x8_t)					\
++  MSTRCAT (test_##insn##_q, TY) (MSTRCAT (FR, 16x8_t) a)	\
++  {							\
++    return MSTRCAT (insn, q##TY) (a);			\
++  }
++
++#define VCVT_N_TEST(insn, TY, TO, FR)			\
++  MSTRCAT (TO, 16x4_t)					\
++  MSTRCAT (test_##insn##_n, TY) (MSTRCAT (FR, 16x4_t) a)	\
++  {							\
++    return MSTRCAT (insn, _n##TY) (a, 1);		\
++  }							\
++  MSTRCAT (TO, 16x8_t)					\
++  MSTRCAT (test_##insn##_n_q, TY) (MSTRCAT (FR, 16x8_t) a)	\
++  {							\
++    return MSTRCAT (insn, q_n##TY) (a, 1);		\
++  }
++
++VCMP1_TEST (vceqz)
++/* { dg-final { scan-assembler-times {vceq\.f16\td[0-9]+, d[0-0]+, #0} 1 } }  */
++/* { dg-final { scan-assembler-times {vceq\.f16\tq[0-9]+, q[0-9]+, #0} 1 } }  */
++
++VCMP1_TEST (vcgtz)
++/* { dg-final { scan-assembler-times {vcgt\.f16\td[0-9]+, d[0-9]+, #0} 1 } }  */
++/* { dg-final { scan-assembler-times {vceq\.f16\tq[0-9]+, q[0-9]+, #0} 1 } }  */
++
++VCMP1_TEST (vcgez)
++/* { dg-final { scan-assembler-times {vcge\.f16\td[0-9]+, d[0-9]+, #0} 1 } }  */
++/* { dg-final { scan-assembler-times {vcge\.f16\tq[0-9]+, q[0-9]+, #0} 1 } }  */
++
++VCMP1_TEST (vcltz)
++/* { dg-final { scan-assembler-times {vclt.f16\td[0-9]+, d[0-9]+, #0} 1 } }  */
++/* { dg-final { scan-assembler-times {vclt.f16\tq[0-9]+, q[0-9]+, #0} 1 } }  */
++
++VCMP1_TEST (vclez)
++/* { dg-final { scan-assembler-times {vcle\.f16\td[0-9]+, d[0-9]+, #0} 1 } }  */
++/* { dg-final { scan-assembler-times {vcle\.f16\tq[0-9]+, q[0-9]+, #0} 1 } }  */
++
++VCVT_TEST (vcvt, _f16_s16, float, int)
++VCVT_N_TEST (vcvt, _f16_s16, float, int)
++/* { dg-final { scan-assembler-times {vcvt\.f16\.s16\td[0-9]+, d[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.f16\.s16\tq[0-9]+, q[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.f16\.s16\td[0-9]+, d[0-9]+, #1} 1 } }
++   { dg-final { scan-assembler-times {vcvt\.f16\.s16\tq[0-9]+, q[0-9]+, #1} 1 } }  */
++
++VCVT_TEST (vcvt, _f16_u16, float, uint)
++VCVT_N_TEST (vcvt, _f16_u16, float, uint)
++/* { dg-final { scan-assembler-times {vcvt\.f16\.u16\td[0-9]+, d[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.f16\.u16\tq[0-9]+, q[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.f16\.u16\td[0-9]+, d[0-9]+, #1} 1 } }
++   { dg-final { scan-assembler-times {vcvt\.f16\.u16\tq[0-9]+, q[0-9]+, #1} 1 } }  */
++
++VCVT_TEST (vcvt, _s16_f16, int, float)
++VCVT_N_TEST (vcvt, _s16_f16, int, float)
++/* { dg-final { scan-assembler-times {vcvt\.s16\.f16\td[0-9]+, d[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.s16\.f16\tq[0-9]+, q[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.s16\.f16\td[0-9]+, d[0-9]+, #1} 1 } }
++   { dg-final { scan-assembler-times {vcvt\.s16\.f16\tq[0-9]+, q[0-9]+, #1} 1 } }  */
++
++VCVT_TEST (vcvt, _u16_f16, uint, float)
++VCVT_N_TEST (vcvt, _u16_f16, uint, float)
++/* { dg-final { scan-assembler-times {vcvt\.u16\.f16\td[0-9]+, d[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.u16\.f16\tq[0-9]+, q[0-9]+} 2 } }
++   { dg-final { scan-assembler-times {vcvt\.u16\.f16\td[0-9]+, d[0-9]+, #1} 1 } }
++   { dg-final { scan-assembler-times {vcvt\.u16\.f16\tq[0-9]+, q[0-9]+, #1} 1 } }  */
++
++VCVT_TEST (vcvta, _s16_f16, int, float)
++/* { dg-final { scan-assembler-times {vcvta\.s16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvta\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvta, _u16_f16, uint, float)
++/* { dg-final { scan-assembler-times {vcvta\.u16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvta\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvtm, _s16_f16, int, float)
++/* { dg-final { scan-assembler-times {vcvtm\.s16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvtm\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvtm, _u16_f16, uint, float)
++/* { dg-final { scan-assembler-times {vcvtm\.u16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvtm\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvtn, _s16_f16, int, float)
++/* { dg-final { scan-assembler-times {vcvtn\.s16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvtn\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvtn, _u16_f16, uint, float)
++/* { dg-final { scan-assembler-times {vcvtn\.u16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvtn\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvtp, _s16_f16, int, float)
++/* { dg-final { scan-assembler-times {vcvtp\.s16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvtp\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++VCVT_TEST (vcvtp, _u16_f16, uint, float)
++/* { dg-final { scan-assembler-times {vcvtp\.u16\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcvtp\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } }
++*/
++
++UNOP_TEST (vabs)
++/* { dg-final { scan-assembler-times {vabs\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vabs\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vneg)
++/* { dg-final { scan-assembler-times {vneg\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vneg\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrecpe)
++/* { dg-final { scan-assembler-times {vrecpe\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrecpe\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrnd)
++/* { dg-final { scan-assembler-times {vrintz\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrintz\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrnda)
++/* { dg-final { scan-assembler-times {vrinta\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrinta\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndm)
++/* { dg-final { scan-assembler-times {vrintm\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrintm\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndn)
++/* { dg-final { scan-assembler-times {vrintn\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrintn\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndp)
++/* { dg-final { scan-assembler-times {vrintp\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrintp\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndx)
++/* { dg-final { scan-assembler-times {vrintx\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrintx\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++UNOP_TEST (vrsqrte)
++/* { dg-final { scan-assembler-times {vrsqrte\.f16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrsqrte\.f16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vadd)
++/* { dg-final { scan-assembler-times {vadd\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vadd\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vabd)
++/* { dg-final { scan-assembler-times {vabd\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vabd\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcage)
++/* { dg-final { scan-assembler-times {vacge\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vacge\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcagt)
++/* { dg-final { scan-assembler-times {vacgt\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vacgt\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcale)
++/* { dg-final { scan-assembler-times {vacle\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vacle\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcalt)
++/* { dg-final { scan-assembler-times {vaclt\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vaclt\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vceq)
++/* { dg-final { scan-assembler-times {vceq\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vceq\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcge)
++/* { dg-final { scan-assembler-times {vcge\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcge\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcgt)
++/* { dg-final { scan-assembler-times {vcgt\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcgt\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vcle)
++/* { dg-final { scan-assembler-times {vcle\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vcle\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++VCMP2_TEST (vclt)
++/* { dg-final { scan-assembler-times {vclt\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vclt\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vmax)
++/* { dg-final { scan-assembler-times {vmax\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vmax\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vmin)
++/* { dg-final { scan-assembler-times {vmin\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vmin\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vmaxnm)
++/* { dg-final { scan-assembler-times {vmaxnm\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++  { dg-final { scan-assembler-times {vmaxnm\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vminnm)
++/* { dg-final { scan-assembler-times {vminnm\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++  { dg-final { scan-assembler-times {vminnm\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vmul)
++/* { dg-final { scan-assembler-times {vmul\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 3 } }
++   { dg-final { scan-assembler-times {vmul\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++BINOP_LANE_TEST (vmul, 2)
++/* { dg-final { scan-assembler-times {vmul\.f16\td[0-9]+, d[0-9]+, d[0-9]+\[2\]} 1 } }
++   { dg-final { scan-assembler-times {vmul\.f16\tq[0-9]+, q[0-9]+, d[0-9]+\[2\]} 1 } }  */
++BINOP_N_TEST (vmul)
++/* { dg-final { scan-assembler-times {vmul\.f16\td[0-9]+, d[0-9]+, d[0-9]+\[0\]} 1 } }
++   { dg-final { scan-assembler-times {vmul\.f16\tq[0-9]+, q[0-9]+, d[0-9]+\[0\]} 1 } }*/
++
++float16x4_t
++test_vpadd_16x4 (float16x4_t a, float16x4_t b)
++{
++  return vpadd_f16 (a, b);
++}
++/* { dg-final { scan-assembler-times {vpadd\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } } */
++
++float16x4_t
++test_vpmax_16x4 (float16x4_t a, float16x4_t b)
++{
++  return vpmax_f16 (a, b);
++}
++/* { dg-final { scan-assembler-times {vpmax\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } } */
++
++float16x4_t
++test_vpmin_16x4 (float16x4_t a, float16x4_t b)
++{
++  return vpmin_f16 (a, b);
++}
++/* { dg-final { scan-assembler-times {vpmin\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } } */
++
++BINOP_TEST (vsub)
++/* { dg-final { scan-assembler-times {vsub\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vsub\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vrecps)
++/* { dg-final { scan-assembler-times {vrecps\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++  { dg-final { scan-assembler-times {vrecps\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++BINOP_TEST (vrsqrts)
++/* { dg-final { scan-assembler-times {vrsqrts\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++  { dg-final { scan-assembler-times {vrsqrts\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++TERNOP_TEST (vfma)
++/* { dg-final { scan-assembler-times {vfma\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++  { dg-final { scan-assembler-times {vfma\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++TERNOP_TEST (vfms)
++/* { dg-final { scan-assembler-times {vfms\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }
++  { dg-final { scan-assembler-times {vfms\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++float16x4_t
++test_vmov_n_f16 (float16_t a)
++{
++  return vmov_n_f16 (a);
++}
++
++float16x4_t
++test_vdup_n_f16 (float16_t a)
++{
++  return vdup_n_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vdup\.16\td[0-9]+, r[0-9]+} 2 } }  */
++
++float16x8_t
++test_vmovq_n_f16 (float16_t a)
++{
++  return vmovq_n_f16 (a);
++}
++
++float16x8_t
++test_vdupq_n_f16 (float16_t a)
++{
++  return vdupq_n_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vdup\.16\tq[0-9]+, r[0-9]+} 2 } }  */
++
++float16x4_t
++test_vdup_lane_f16 (float16x4_t a)
++{
++  return vdup_lane_f16 (a, 1);
++}
++/* { dg-final { scan-assembler-times {vdup\.16\td[0-9]+, d[0-9]+\[1\]} 1 } }  */
++
++float16x8_t
++test_vdupq_lane_f16 (float16x4_t a)
++{
++  return vdupq_lane_f16 (a, 1);
++}
++/* { dg-final { scan-assembler-times {vdup\.16\tq[0-9]+, d[0-9]+\[1\]} 1 } }  */
++
++float16x4_t
++test_vext_f16 (float16x4_t a, float16x4_t b)
++{
++  return vext_f16 (a, b, 1);
++}
++/* { dg-final { scan-assembler-times {vext\.16\td[0-9]+, d[0-9]+, d[0-9]+, #1} 1 } } */
++
++float16x8_t
++test_vextq_f16 (float16x8_t a, float16x8_t b)
++{
++  return vextq_f16 (a, b, 1);
++}
++/*   { dg-final { scan-assembler-times {vext\.16\tq[0-9]+, q[0-9]+, q[0-9]+, #1} 1 } }  */
++
++UNOP_TEST (vrev64)
++/* { dg-final { scan-assembler-times {vrev64\.16\td[0-9]+, d[0-9]+} 1 } }
++   { dg-final { scan-assembler-times {vrev64\.16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++float16x4_t
++test_vbsl16x4 (uint16x4_t a, float16x4_t b, float16x4_t c)
++{
++  return vbsl_f16 (a, b, c);
++}
++/* { dg-final { scan-assembler-times {vbsl\td[0-9]+, d[0-9]+, d[0-9]+} 1 } }  */
++
++float16x8_t
++test_vbslq16x8 (uint16x8_t a, float16x8_t b, float16x8_t c)
++{
++  return vbslq_f16 (a, b, c);
++}
++/*{ dg-final { scan-assembler-times {vbsl\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } }  */
++
++float16x4x2_t
++test_vzip16x4 (float16x4_t a, float16x4_t b)
++{
++  return vzip_f16 (a, b);
++}
++/* { dg-final { scan-assembler-times {vzip\.16\td[0-9]+, d[0-9]+} 1 } }  */
++
++float16x8x2_t
++test_vzipq16x8 (float16x8_t a, float16x8_t b)
++{
++  return vzipq_f16 (a, b);
++}
++/*{ dg-final { scan-assembler-times {vzip\.16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++float16x4x2_t
++test_vuzp16x4 (float16x4_t a, float16x4_t b)
++{
++  return vuzp_f16 (a, b);
++}
++/* { dg-final { scan-assembler-times {vuzp\.16\td[0-9]+, d[0-9]+} 1 } }  */
++
++float16x8x2_t
++test_vuzpq16x8 (float16x8_t a, float16x8_t b)
++{
++  return vuzpq_f16 (a, b);
++}
++/*{ dg-final { scan-assembler-times {vuzp\.16\tq[0-9]+, q[0-9]+} 1 } }  */
++
++float16x4x2_t
++test_vtrn16x4 (float16x4_t a, float16x4_t b)
++{
++  return vtrn_f16 (a, b);
++}
++/* { dg-final { scan-assembler-times {vtrn\.16\td[0-9]+, d[0-9]+} 1 } }  */
++
++float16x8x2_t
++test_vtrnq16x8 (float16x8_t a, float16x8_t b)
++{
++  return vtrnq_f16 (a, b);
++}
++/*{ dg-final { scan-assembler-times {vtrn\.16\tq[0-9]+, q[0-9]+} 1 } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv8_2-fp16-scalar-1.c
+@@ -0,0 +1,203 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok }  */
++/* { dg-options "-O2" }  */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++/* Test instructions generated for the FP16 scalar intrinsics.  */
++#include <arm_fp16.h>
++
++#define MSTRCAT(L, str)	L##str
++
++#define UNOP_TEST(insn)				\
++  float16_t					\
++  MSTRCAT (test_##insn, 16) (float16_t a)	\
++  {						\
++    return MSTRCAT (insn, h_f16) (a);		\
++  }
++
++#define BINOP_TEST(insn)				\
++  float16_t						\
++  MSTRCAT (test_##insn, 16) (float16_t a, float16_t b)	\
++  {							\
++    return MSTRCAT (insn, h_f16) (a, b);		\
++  }
++
++#define TERNOP_TEST(insn)						\
++  float16_t								\
++  MSTRCAT (test_##insn, 16) (float16_t a, float16_t b, float16_t c)	\
++  {									\
++    return MSTRCAT (insn, h_f16) (a, b, c);				\
++  }
++
++float16_t
++test_vcvth_f16_s32 (int32_t a)
++{
++  return vcvth_f16_s32 (a);
++}
++
++float16_t
++test_vcvth_n_f16_s32 (int32_t a)
++{
++  return vcvth_n_f16_s32 (a, 1);
++}
++/* { dg-final { scan-assembler-times {vcvt\.f16\.s32\ts[0-9]+, s[0-9]+} 2 } }  */
++/* { dg-final { scan-assembler-times {vcvt\.f16\.s32\ts[0-9]+, s[0-9]+, #1} 1 } }  */
++
++float16_t
++test_vcvth_f16_u32 (uint32_t a)
++{
++  return vcvth_f16_u32 (a);
++}
++
++float16_t
++test_vcvth_n_f16_u32 (uint32_t a)
++{
++  return vcvth_n_f16_u32 (a, 1);
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.f16\.u32\ts[0-9]+, s[0-9]+} 2 } }  */
++/* { dg-final { scan-assembler-times {vcvt\.f16\.u32\ts[0-9]+, s[0-9]+, #1} 1 } }  */
++
++uint32_t
++test_vcvth_u32_f16 (float16_t a)
++{
++  return vcvth_u32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvt\.u32\.f16\ts[0-9]+, s[0-9]+} 2 } }  */
++
++uint32_t
++test_vcvth_n_u32_f16 (float16_t a)
++{
++  return vcvth_n_u32_f16 (a, 1);
++}
++/* { dg-final { scan-assembler-times {vcvt\.u32\.f16\ts[0-9]+, s[0-9]+, #1} 1 } }  */
++
++int32_t
++test_vcvth_s32_f16 (float16_t a)
++{
++  return vcvth_s32_f16 (a);
++}
++
++int32_t
++test_vcvth_n_s32_f16 (float16_t a)
++{
++  return vcvth_n_s32_f16 (a, 1);
++}
++
++/* { dg-final { scan-assembler-times {vcvt\.s32\.f16\ts[0-9]+, s[0-9]+} 2 } }  */
++/* { dg-final { scan-assembler-times {vcvt\.s32\.f16\ts[0-9]+, s[0-9]+, #1} 1 } }  */
++
++int32_t
++test_vcvtah_s32_f16 (float16_t a)
++{
++  return vcvtah_s32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvta\.s32\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++uint32_t
++test_vcvtah_u32_f16 (float16_t a)
++{
++  return vcvtah_u32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvta\.u32\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++int32_t
++test_vcvtmh_s32_f16 (float16_t a)
++{
++  return vcvtmh_s32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvtm\.s32\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++uint32_t
++test_vcvtmh_u32_f16 (float16_t a)
++{
++  return vcvtmh_u32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvtm\.u32\.f16\ts[0-9]+, s[0-9]+} 1 } }
++ */
++
++int32_t
++test_vcvtnh_s32_f16 (float16_t a)
++{
++  return vcvtnh_s32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvtn\.s32\.f16\ts[0-9]+, s[0-9]+} 1 } }
++ */
++
++uint32_t
++test_vcvtnh_u32_f16 (float16_t a)
++{
++  return vcvtnh_u32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvtn\.u32\.f16\ts[0-9]+, s[0-9]+} 1 } }
++ */
++
++int32_t
++test_vcvtph_s32_f16 (float16_t a)
++{
++  return vcvtph_s32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvtp\.s32\.f16\ts[0-9]+, s[0-9]+} 1 } }
++ */
++
++uint32_t
++test_vcvtph_u32_f16 (float16_t a)
++{
++  return vcvtph_u32_f16 (a);
++}
++/* { dg-final { scan-assembler-times {vcvtp\.u32\.f16\ts[0-9]+, s[0-9]+} 1 } }
++ */
++
++UNOP_TEST (vabs)
++/* { dg-final { scan-assembler-times {vabs\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vneg)
++/* { dg-final { scan-assembler-times {vneg\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrnd)
++/* { dg-final { scan-assembler-times {vrintz\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndi)
++/* { dg-final { scan-assembler-times {vrintr\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrnda)
++/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndm)
++/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndn)
++/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndp)
++/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vrndx)
++/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++UNOP_TEST (vsqrt)
++/* { dg-final { scan-assembler-times {vsqrt\.f16\ts[0-9]+, s[0-9]+} 1 } }  */
++
++BINOP_TEST (vadd)
++/* { dg-final { scan-assembler-times {vadd\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++BINOP_TEST (vdiv)
++/* { dg-final { scan-assembler-times {vdiv\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++BINOP_TEST (vmaxnm)
++/* { dg-final { scan-assembler-times {vmaxnm\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++BINOP_TEST (vminnm)
++/* { dg-final { scan-assembler-times {vminnm\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++BINOP_TEST (vmul)
++/* { dg-final { scan-assembler-times {vmul\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++BINOP_TEST (vsub)
++/* { dg-final { scan-assembler-times {vsub\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++TERNOP_TEST (vfma)
++/* { dg-final { scan-assembler-times {vfma\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++TERNOP_TEST (vfms)
++/* { dg-final { scan-assembler-times {vfms\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/armv8_2-fp16-scalar-2.c
+@@ -0,0 +1,71 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok }  */
++/* { dg-options "-O2 -std=c11" }  */
++/* { dg-add-options arm_v8_2a_fp16_scalar }  */
++
++/* Test compiler use of FP16 instructions.  */
++#include <arm_fp16.h>
++
++float16_t
++test_mov_imm_1 (float16_t a)
++{
++  return 1.0;
++}
++
++float16_t
++test_mov_imm_2 (float16_t a)
++{
++  float16_t b = 1.0;
++  return b;
++}
++
++float16_t
++test_vmov_imm_3 (float16_t a)
++{
++  float16_t b = 1.0;
++  return vaddh_f16 (a, b);
++}
++
++float16_t
++test_vmov_imm_4 (float16_t a)
++{
++  return vaddh_f16 (a, 1.0);
++}
++
++/* { dg-final { scan-assembler-times {vmov.f16\ts[0-9]+, #1\.0e\+0} 4 } }
++   { dg-final { scan-assembler-times {vadd.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 2 } } */
++
++float16_t
++test_vmla_1 (float16_t a, float16_t b, float16_t c)
++{
++  return vaddh_f16 (vmulh_f16 (a, b), c);
++}
++/* { dg-final { scan-assembler-times {vmla\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } }  */
++
++float16_t
++test_vmla_2 (float16_t a, float16_t b, float16_t c)
++{
++  return vsubh_f16 (vmulh_f16 (vnegh_f16 (a), b), c);
++}
++/* { dg-final { scan-assembler-times {vnmla\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
++
++float16_t
++test_vmls_1 (float16_t a, float16_t b, float16_t c)
++{
++  return vsubh_f16 (c, vmulh_f16 (a, b));
++}
++
++float16_t
++test_vmls_2 (float16_t a, float16_t b, float16_t c)
++{
++  return vsubh_f16 (a, vmulh_f16 (b, c));
++}
++/* { dg-final { scan-assembler-times {vmls\.f16} 2 } } */
++
++float16_t
++test_vnmls_1 (float16_t a, float16_t b, float16_t c)
++{
++  return vsubh_f16 (vmulh_f16 (a, b), c);
++}
++/* { dg-final { scan-assembler-times {vnmls\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2 -fno-ipa-icf" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-comp-swap-release-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex" 4 } } */
++/* { dg-final { scan-assembler-times "stlex" 4 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2 -fno-ipa-icf" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-comp-swap-release-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex" 4 } } */
++/* { dg-final { scan-assembler-times "stlex" 4 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2 -fno-ipa-icf" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-comp-swap-release-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex" 4 } } */
++/* { dg-final { scan-assembler-times "stlex" 4 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2 -fno-ipa-icf" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-comp-swap-release-acquire.x"
+-
+-/* { dg-final { scan-assembler-times "ldaex" 4 } } */
+-/* { dg-final { scan-assembler-times "stlex" 4 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-acq_rel.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-acq_rel.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-acq_rel.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-acq_rel.x"
+-
+-/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-acquire.x"
+-
+-/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-char-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-char.x"
++
++/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-char-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-char.x"
++
++/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-char-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-char.x"
++
++/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-char.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-char.x"
+-
+-/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-consume-1.c
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-consume.x"
++
++/* Scan for ldaex is a PR59448 consume workaround.  */
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-consume-2.c
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-consume.x"
++
++/* Scan for ldaex is a PR59448 consume workaround.  */
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-consume.x"
++
++/* Scan for ldaex is a PR59448 consume workaround.  */
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-consume.c
++++ b/src//dev/null
+@@ -1,11 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-consume.x"
+-
+-/* Scan for ldaex is a PR59448 consume workaround.  */
+-/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-int-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-int.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-int-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-int.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-int-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-int.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-int.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-int.x"
+-
+-/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-relaxed.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-relaxed.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-relaxed.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-relaxed.x"
+-
+-/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-release-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-release.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-release-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-release.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-release-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-release.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-release.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-release.x"
+-
+-/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-seq_cst.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-seq_cst.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-seq_cst.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-seq_cst.x"
+-
+-/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-short-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-short.x"
++
++/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-short-2.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_main } */
++
++#include "../aarch64/atomic-op-short.x"
++
++/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-short-3.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8m_base } */
++
++#include "../aarch64/atomic-op-short.x"
++
++/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-short.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-short.x"
+-
+-/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/attr-fp16-arith-1.c
+@@ -0,0 +1,58 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_v8_2a_fp16_neon_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_v8_2a_fp16_scalar } */
++
++/* Reset fpu to a value compatible with the next pragmas.  */
++#pragma GCC target ("fpu=vfp")
++
++#pragma GCC push_options
++#pragma GCC target ("fpu=fp-armv8")
++
++#ifndef __ARM_FEATURE_FP16_SCALAR_ARITHMETIC
++#error __ARM_FEATURE_FP16_SCALAR_ARITHMETIC not defined.
++#endif
++
++#pragma GCC push_options
++#pragma GCC target ("fpu=neon-fp-armv8")
++
++#ifndef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
++#error __ARM_FEATURE_FP16_VECTOR_ARITHMETIC not defined.
++#endif
++
++#ifndef __ARM_NEON
++#error __ARM_NEON not defined.
++#endif
++
++#if !defined (__ARM_FP) || !(__ARM_FP & 0x2)
++#error Invalid value for __ARM_FP
++#endif
++
++#include "arm_neon.h"
++
++float16_t
++foo (float16x4_t b)
++{
++  float16x4_t a = {2.0, 3.0, 4.0, 5.0};
++  float16x4_t res = vadd_f16 (a, b);
++
++  return res[0];
++}
++
++/* { dg-final { scan-assembler "vadd\\.f16\td\[0-9\]+, d\[0-9\]+" } } */
++
++#pragma GCC pop_options
++
++/* Check that the FP version is correctly reset to mfpu=fp-armv8.  */
++
++#if !defined (__ARM_FP) || !(__ARM_FP & 0x2)
++#error __ARM_FP should record FP16 support.
++#endif
++
++#pragma GCC pop_options
++
++/* Check that the FP version is correctly reset to mfpu=vfp.  */
++
++#if !defined (__ARM_FP) || (__ARM_FP & 0x2)
++#error Unexpected value for __ARM_FP.
++#endif
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_saddl.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++long overflow_add (long x, long y)
++{
++  long r;
++
++  int ovr = __builtin_saddl_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "adds" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_saddll.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++long long overflow_add (long long x, long long y)
++{
++  long long r;
++
++  int ovr = __builtin_saddll_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "adds" } } */
++/* { dg-final { scan-assembler "adcs" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_ssubl.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++long overflow_sub (long x, long y)
++{
++  long r;
++
++  int ovr = __builtin_ssubl_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "subs" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_ssubll.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++long long overflow_sub (long long x, long long y)
++{
++  long long r;
++
++  int ovr = __builtin_ssubll_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "subs" } } */
++/* { dg-final { scan-assembler "sbcs" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_uaddl.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++unsigned long overflow_add (unsigned long x, unsigned long y)
++{
++  unsigned long r;
++
++  int ovr = __builtin_uaddl_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "adds" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_uaddll.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++unsigned long long overflow_add (unsigned long long x, unsigned long long y)
++{
++  unsigned long long r;
++
++  int ovr = __builtin_uaddll_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "adds" } } */
++/* { dg-final { scan-assembler "adcs" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_usubl.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++unsigned long overflow_sub (unsigned long x, unsigned long y)
++{
++  unsigned long r;
++
++  int ovr = __builtin_usubl_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "subs" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/builtin_usubll.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++/* { dg-require-effective-target arm32 } */
++extern void overflow_handler ();
++
++unsigned long long overflow_sub (unsigned long long x, unsigned long long y)
++{
++  unsigned long long r;
++
++  int ovr = __builtin_usubll_overflow (x, y, &r);
++  if (ovr)
++    overflow_handler ();
++
++  return r;
++}
++
++/* { dg-final { scan-assembler "subs" } } */
++/* { dg-final { scan-assembler "sbcs" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cbz.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile {target { arm_thumb2 || arm_thumb1_cbz_ok } } } */
++/* { dg-options "-O2" } */
++
++int
++foo (int a, int *b)
++{
++  if (a)
++    *b = 1;
++  return 0;
++}
++
++/* { dg-final { scan-assembler-times "cbz\\tr\\d" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-4.c
+@@ -0,0 +1,57 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char a;
++  unsigned int b:5;
++  unsigned int c:11, :0, d:8;
++  struct { unsigned int ee:2; } e;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++extern void foo (test_st st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++  r.values.v4 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr4, 255" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #255" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #3" } } */
++/* { dg-final { scan-assembler "ands\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-5.c
+@@ -0,0 +1,53 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned short  b :5;
++  unsigned char	  c;
++  unsigned short  d :11;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #8191" } } */
++/* { dg-final { scan-assembler "movt\tr4, 255" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #2047" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr2, r4" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-6.c
+@@ -0,0 +1,63 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char a;
++  unsigned int	b : 3;
++  unsigned int	c : 14;
++  unsigned int	d : 1;
++  struct {
++      unsigned int    ee  : 2;
++      unsigned short  ff  : 15;
++  } e;
++  unsigned char	g : 1;
++  unsigned char	  : 4;
++  unsigned char	h : 3;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++  r.values.v4 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr4, 1023" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #3" } } */
++/* { dg-final { scan-assembler "movt\tr4, 32767" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #255" } } */
++/* { dg-final { scan-assembler "ands\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-7.c
+@@ -0,0 +1,54 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned short  b :5;
++  unsigned char	  c;
++  unsigned short  d :11;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #8191" } } */
++/* { dg-final { scan-assembler "movt\tr4, 255" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #2047" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr2, r4" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-8.c
+@@ -0,0 +1,57 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned int	    :0;
++  unsigned int	  b :1;
++  unsigned short    :0;
++  unsigned short  c;
++  unsigned int	    :0;
++  unsigned int	  d :21;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #255" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #1" } } */
++/* { dg-final { scan-assembler "movt\tr4, 65535" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr4, 31" } } */
++/* { dg-final { scan-assembler "ands\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-9.c
+@@ -0,0 +1,56 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  char a:3;
++} test_st3;
++
++typedef struct
++{
++  char a:3;
++} test_st2;
++
++typedef struct
++{
++  test_st2 st2;
++  test_st3 st3;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #1799" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr1, r4" } } */
++/* { dg-final { scan-assembler "movs\tr2, r4" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/bitfield-and-union-1.c
+@@ -0,0 +1,96 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned short a :11;
++} test_st_4;
++
++typedef union
++{
++  char	      a;
++  test_st_4 st4;
++}test_un_2;
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned int	    :0;
++  unsigned int	  b :1;
++  unsigned short    :0;
++  unsigned short  c;
++  unsigned int	    :0;
++  unsigned int	  d :21;
++} test_st_3;
++
++typedef struct
++{
++  unsigned char	  a :3;
++  unsigned int	  b :13;
++  test_un_2	  un2;
++} test_st_2;
++
++typedef union
++{
++  test_st_2 st2;
++  test_st_3 st3;
++}test_un_1;
++
++typedef struct
++{
++  unsigned char	  a :2;
++  unsigned char	    :0;
++  unsigned short  b :5;
++  unsigned char	    :0;
++  unsigned char	  c :4;
++  test_un_1	  un1;
++} test_st_1;
++
++typedef union
++{
++  test_st_1 st1;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st_1;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st_1);
++
++int
++main (void)
++{
++  read_st_1 r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++  r.values.v4 = 0xFFFFFFFF;
++
++  f (r.st1);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #7939" } } */
++/* { dg-final { scan-assembler "movt\tr4, 15" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr4, 2047" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "movs\tr4, #1" } } */
++/* { dg-final { scan-assembler "movt\tr4, 65535" } } */
++/* { dg-final { scan-assembler "ands\tr2, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr4, 31" } } */
++/* { dg-final { scan-assembler "ands\tr3, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-11.c
+@@ -0,0 +1,22 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-add-options arm_arch_v8m_base } */
++/* { dg-options "-mcmse" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (int);
++
++int
++foo (int a)
++{
++  return bar (bar (a + 1));
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr1, r4" } } */
++/* { dg-final { scan-assembler "movs\tr2, r4" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-13.c
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-add-options arm_arch_v8m_base } */
++/* { dg-options "-mcmse" } */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (float, double);
++
++int
++foo (int a)
++{
++  return bar (1.0f, 2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler-not "movs\tr0, r4" } } */
++/* { dg-final { scan-assembler "\n\tmovs\tr1, r4" } } */
++/* { dg-final { scan-assembler-not "\n\tmovs\tr2, r4\n\tmovs\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vmov" } } */
++/* { dg-final { scan-assembler-not "vmsr" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-2.c
+@@ -0,0 +1,19 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-add-options arm_arch_v8m_base } */
++/* { dg-options "-mcmse" }  */
++
++extern float bar (void);
++
++float __attribute__ ((cmse_nonsecure_entry))
++foo (void)
++{
++  return bar ();
++}
++/* { dg-final { scan-assembler "movs\tr1, r0" } } */
++/* { dg-final { scan-assembler "movs\tr2, r0" } } */
++/* { dg-final { scan-assembler "movs\tr3, r0" } } */
++/* { dg-final { scan-assembler "mov\tip, r0" } } */
++/* { dg-final { scan-assembler "mov\tlr, r0" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq," } } */
++/* { dg-final { scan-assembler "bxns" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/cmse-6.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-add-options arm_arch_v8m_base } */
++/* { dg-options "-mcmse" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (double);
++
++int
++foo (int a)
++{
++  return bar (2.0) + a + 1;
++}
++
++/* Remember dont clear r0 and r1, because we are passing the double parameter
++ * for bar in them.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr2, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/softfp.c
+@@ -0,0 +1,29 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_base_ok } */
++/* { dg-add-options arm_arch_v8m_base } */
++/* { dg-options "-mcmse -mfloat-abi=softfp" } */
++
++double __attribute__ ((cmse_nonsecure_call)) (*bar) (float, double);
++
++double
++foo (double a)
++{
++  return bar (1.0f, 2.0) + a;
++}
++
++float __attribute__ ((cmse_nonsecure_entry))
++baz (float a, double b)
++{
++  return (float) bar (a, b);
++}
++
++/* Make sure we are not using FP instructions, since ARMv8-M Baseline does not
++   support such instructions.  */
++/* { dg-final { scan-assembler-not "vmov" } } */
++/* { dg-final { scan-assembler-not "vmsr" } } */
++/* { dg-final { scan-assembler-not "vmrs" } } */
++
++/* Just double checking that we are still doing cmse though.  */
++/* { dg-final { scan-assembler-not "vmrs" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/union-1.c
+@@ -0,0 +1,71 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a :2;
++  unsigned char	    :0;
++  unsigned short  b :5;
++  unsigned char	    :0;
++  unsigned short  c :3;
++  unsigned char	    :0;
++  unsigned int	  d :9;
++} test_st_1;
++
++typedef struct
++{
++  unsigned short  a :7;
++  unsigned char	    :0;
++  unsigned char	  b :1;
++  unsigned char	    :0;
++  unsigned short  c :6;
++} test_st_2;
++
++typedef union
++{
++  test_st_1 st_1;
++  test_st_2 st_2;
++}test_un;
++
++typedef union
++{
++  test_un un;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_un;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_un);
++
++int
++main (void)
++{
++  read_un r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++
++  f (r.un);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #8063" } } */
++/* { dg-final { scan-assembler "movt\tr4, 63" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #511" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr2, r4" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/baseline/union-2.c
+@@ -0,0 +1,86 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a :2;
++  unsigned char	    :0;
++  unsigned short  b :5;
++  unsigned char	    :0;
++  unsigned short  c :3;
++  unsigned char	    :0;
++  unsigned int	  d :9;
++} test_st_1;
++
++typedef struct
++{
++  unsigned short  a :7;
++  unsigned char	    :0;
++  unsigned char	  b :1;
++  unsigned char	    :0;
++  unsigned short  c :6;
++} test_st_2;
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned int	    :0;
++  unsigned int	  b :1;
++  unsigned short    :0;
++  unsigned short  c;
++  unsigned int	    :0;
++  unsigned int	  d :21;
++} test_st_3;
++
++typedef union
++{
++  test_st_1 st_1;
++  test_st_2 st_2;
++  test_st_3 st_3;
++}test_un;
++
++typedef union
++{
++  test_un un;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_un;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_un);
++
++int
++main (void)
++{
++  read_un r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++
++  f (r.un);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #8191" } } */
++/* { dg-final { scan-assembler "movt\tr4, 63" } } */
++/* { dg-final { scan-assembler "ands\tr0, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #511" } } */
++/* { dg-final { scan-assembler "movt\tr4, 65535" } } */
++/* { dg-final { scan-assembler "ands\tr1, r4" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr4, 31" } } */
++/* { dg-final { scan-assembler "ands\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr4, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "movs\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/bitfield-1.c
+@@ -0,0 +1,39 @@
++/* { dg-do run } */
++/* { dg-options "--save-temps -mcmse -Wl,--section-start,.gnu.sgstubs=0x20400000" } */
++
++typedef struct
++{
++  unsigned short  a : 6;
++  unsigned char	  b : 3;
++  unsigned char	  c;
++  unsigned short  d : 8;
++} test_st;
++
++test_st __attribute__ ((cmse_nonsecure_entry)) foo (void)
++{
++  test_st t;
++  t.a = 63u;
++  t.b = 7u;
++  t.c = 255u;
++  t.d = 255u;
++  return t;
++}
++
++int
++main (void)
++{
++  test_st t;
++  t = foo ();
++  if (t.a != 63u
++      || t.b != 7u
++      || t.c != 255u
++      || t.d != 255u)
++    __builtin_abort ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tr1, #1855" } } */
++/* { dg-final { scan-assembler "movt\tr1, 65535" } } */
++/* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
++/* { dg-final { scan-assembler "bxns" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/bitfield-2.c
+@@ -0,0 +1,36 @@
++/* { dg-do run } */
++/* { dg-options "--save-temps -mcmse -Wl,--section-start,.gnu.sgstubs=0x20400000" } */
++
++typedef struct
++{
++  short	      a : 7;
++  signed char b : 3;
++  short	      c : 11;
++} test_st;
++
++test_st __attribute__ ((cmse_nonsecure_entry)) foo (void)
++{
++  test_st t;
++  t.a = -64;
++  t.b = -4 ;
++  t.c = -1024;
++  return t;
++}
++
++int
++main (void)
++{
++  test_st t;
++  t = foo ();
++  if (t.a != -64
++      || t.b != -4
++      || t.c != -1024)
++    __builtin_abort ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tr1, #1919" } } */
++/* { dg-final { scan-assembler "movt\tr1, 2047" } } */
++/* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
++/* { dg-final { scan-assembler "bxns" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/bitfield-3.c
+@@ -0,0 +1,37 @@
++/* { dg-do run } */
++/* { dg-options "--save-temps -mcmse -Wl,--section-start,.gnu.sgstubs=0x20400000" } */
++
++typedef struct
++{
++  short	      a;
++  signed char b : 2;
++  short		: 1;
++  signed char c : 3;
++} test_st;
++
++test_st __attribute__ ((cmse_nonsecure_entry)) foo (void)
++{
++  test_st t;
++  t.a = -32768;
++  t.b = -2;
++  t.c = -4;
++  return t;
++}
++
++int
++main (void)
++{
++  test_st t;
++  t = foo ();
++  if (t.a != -32768
++      || t.b != -2
++      || t.c != -4)
++    __builtin_abort ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tr1, #65535" } } */
++/* { dg-final { scan-assembler "movt\tr1, 63" } } */
++/* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
++/* { dg-final { scan-assembler "bxns" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
+@@ -0,0 +1,106 @@
++/* { dg-do compile } */
++/* { dg-options "-Os -mcmse -fdump-rtl-expand" }  */
++
++#include <arm_cmse.h>
++
++extern int a;
++extern int bar (void);
++
++int foo (char * p)
++{
++  cmse_address_info_t cait;
++
++  cait = cmse_TT (&a);
++  if (cait.flags.mpu_region)
++    a++;
++
++  cait = cmse_TT_fptr (&bar);
++  if (cait.flags.mpu_region)
++    a+= bar ();
++
++  cait = cmse_TTA (&a);
++  if (cait.flags.mpu_region)
++    a++;
++
++  cait = cmse_TTA_fptr (&bar);
++  if (cait.flags.mpu_region)
++    a+= bar ();
++
++  cait = cmse_TTT (&a);
++  if (cait.flags.mpu_region)
++    a++;
++
++  cait = cmse_TTT_fptr (&bar);
++  if (cait.flags.mpu_region)
++    a+= bar ();
++
++  cait = cmse_TTAT (&a);
++  if (cait.flags.mpu_region)
++    a++;
++
++  cait = cmse_TTAT_fptr (&bar);
++  if (cait.flags.mpu_region)
++    a+= bar ();
++
++  p = (char *) cmse_check_address_range ((void *) p, sizeof (char), 0);
++  p = (char *) cmse_check_address_range ((void *) p, sizeof (char),
++					 CMSE_MPU_UNPRIV);
++  p = (char *) cmse_check_address_range ((void *) p, sizeof (char),
++					 CMSE_MPU_READWRITE);
++  p = (char *) cmse_check_address_range ((void *) p, sizeof (char),
++					 CMSE_MPU_UNPRIV | CMSE_MPU_READ);
++  p = (char *) cmse_check_address_range ((void *) p, sizeof (char),
++					 CMSE_AU_NONSECURE
++					 | CMSE_MPU_NONSECURE);
++  p = (char *) cmse_check_address_range ((void *) p, sizeof (char),
++					 CMSE_NONSECURE | CMSE_MPU_UNPRIV);
++
++  p = (char *) cmse_check_pointed_object (p, CMSE_NONSECURE | CMSE_MPU_UNPRIV);
++
++  return a;
++}
++/* { dg-final { scan-assembler-times "\ttt " 2 } } */
++/* { dg-final { scan-assembler-times "ttt " 2 } } */
++/* { dg-final { scan-assembler-times "tta " 2 } } */
++/* { dg-final { scan-assembler-times "ttat " 2 } } */
++/* { dg-final { scan-assembler-times "bl.cmse_check_address_range" 7 } } */
++/* { dg-final { scan-assembler-not "cmse_check_pointed_object" } } */
++
++int __attribute__ ((cmse_nonsecure_entry))
++baz (void)
++{
++  return cmse_nonsecure_caller ();
++}
++
++typedef int __attribute__ ((cmse_nonsecure_call)) (int_nsfunc_t) (void);
++
++int default_callback (void)
++{
++  return 0;
++}
++
++int_nsfunc_t * fp = (int_nsfunc_t *) default_callback;
++
++void __attribute__ ((cmse_nonsecure_entry))
++qux (int_nsfunc_t * callback)
++{
++  fp = cmse_nsfptr_create (callback);
++}
++
++int call_callback (void)
++{
++  if (cmse_is_nsfptr (fp))
++      return fp ();
++  else
++    return default_callback ();
++}
++/* { dg-final { scan-assembler "baz:" } } */
++/* { dg-final { scan-assembler "__acle_se_baz:" } } */
++/* { dg-final { scan-assembler "qux:" } } */
++/* { dg-final { scan-assembler "__acle_se_qux:" } } */
++/* { dg-final { scan-assembler-not "\tcmse_nonsecure_caller" } } */
++/* { dg-final { scan-rtl-dump "and.*reg.*const_int 1" expand } } */
++/* { dg-final { scan-assembler "bic" } } */
++/* { dg-final { scan-assembler "push\t\{r4, r5, r6" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq" } } */
++/* { dg-final { scan-assembler-times "bl\\s+__gnu_cmse_nonsecure_call" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-10.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" }  */
++
++void
++foo (void) {}
++
++/* { dg-final { scan-assembler-not "bxns" } } */
++/* { dg-final { scan-assembler "foo:" } } */
++/* { dg-final { scan-assembler-not "__acle_se_foo:" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-12.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" }  */
++#include <arm_cmse.h>
++
++char *
++foo (char * p)
++{
++  if (!cmse_is_nsfptr (p))
++    return cmse_nsfptr_create (p);
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler-not "cmse_is_nsfptr" } } */
++/* { dg-final { scan-assembler-not "cmse_nsfptr_create" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-14.c
+@@ -0,0 +1,13 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (void);
++
++int foo (void)
++{
++  return bar ();
++}
++
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++/* { dg-final { scan-assembler-not "b\[^ y\n\]*\\s+bar" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-15.c
+@@ -0,0 +1,72 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++int __attribute__ ((cmse_nonsecure_call)) (*ns_foo) (void);
++int (*s_bar) (void);
++int __attribute__ ((cmse_nonsecure_call)) (**ns_foo2) (void);
++int (**s_bar2) (void);
++
++typedef int __attribute__ ((cmse_nonsecure_call)) ns_foo_t (void);
++typedef int s_bar_t (void);
++typedef int __attribute__ ((cmse_nonsecure_call)) (* ns_foo_ptr) (void);
++typedef int (*s_bar_ptr) (void);
++
++int nonsecure0 (ns_foo_t * ns_foo_p)
++{
++  return ns_foo_p ();
++}
++
++int nonsecure1 (ns_foo_t ** ns_foo_p)
++{
++  return (*ns_foo_p) ();
++}
++
++int nonsecure2 (ns_foo_ptr ns_foo_p)
++{
++  return ns_foo_p ();
++}
++int nonsecure3 (ns_foo_ptr * ns_foo_p)
++{
++  return (*ns_foo_p) ();
++}
++
++int secure0 (s_bar_t * s_bar_p)
++{
++  return s_bar_p ();
++}
++
++int secure1 (s_bar_t ** s_bar_p)
++{
++  return (*s_bar_p) ();
++}
++
++int secure2 (s_bar_ptr s_bar_p)
++{
++  return s_bar_p ();
++}
++
++int secure3 (s_bar_ptr * s_bar_p)
++{
++  return (*s_bar_p) ();
++}
++
++int nonsecure4 (void)
++{
++  return ns_foo ();
++}
++
++int nonsecure5 (void)
++{
++  return (*ns_foo2) ();
++}
++
++int secure4 (void)
++{
++  return s_bar ();
++}
++
++int secure5 (void)
++{
++  return (*s_bar2) ();
++}
++/* { dg-final { scan-assembler-times "bl\\s+__gnu_cmse_nonsecure_call" 6 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-3.c
+@@ -0,0 +1,45 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" }  */
++
++struct span {
++  int a, b;
++};
++struct span2 {
++  float a, b, c, d;
++};
++
++union test_union
++{
++  long long a;
++  int b;
++  struct span2 c;
++} test_union;
++
++void __attribute__ ((cmse_nonsecure_entry))
++foo (long long a, int b, long long c) {} /* { dg-error "not available to functions with arguments passed on the stack" } */
++
++void __attribute__ ((cmse_nonsecure_entry))
++bar (long long a, int b, struct span c) {} /* { dg-error "not available to functions with arguments passed on the stack" } */
++
++void __attribute__ ((cmse_nonsecure_entry))
++baz (int a, ...) {} /* { dg-error "not available to functions with variable number of arguments" } */
++
++struct span __attribute__ ((cmse_nonsecure_entry))
++qux (void) { /* { dg-error "not available to functions that return value on the stack" } */
++  struct span ret = {0, 0};
++  return ret;
++}
++
++void __attribute__ ((cmse_nonsecure_entry))
++norf (struct span2 a) {}
++
++void __attribute__ ((cmse_nonsecure_entry))
++foo2 (long long a, int b, union test_union c) {} /* { dg-error "not available to functions with arguments passed on the stack" } */
++
++typedef void __attribute__ ((cmse_nonsecure_call)) bar2 (long long a, int b, long long c); /* { dg-error "not available to functions with arguments passed on the stack" } */
++
++typedef void __attribute__ ((cmse_nonsecure_call)) baz2 (long long a, int b, struct span c); /* { dg-error "not available to functions with arguments passed on the stack" } */
++
++typedef struct span __attribute__ ((cmse_nonsecure_call)) qux2 (void); /* { dg-error "not available to functions that return value on the stack" } */
++
++typedef void __attribute__ ((cmse_nonsecure_call)) norf2 (int a, ...); /* { dg-error "not available to functions with variable number of arguments" } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-4.c
+@@ -0,0 +1,34 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" }  */
++
++struct span {
++  int a, b;
++};
++
++extern int qux (void);
++
++void __attribute__ ((cmse_nonsecure_entry))
++foo (void) {}
++
++static void __attribute__ ((cmse_nonsecure_entry))
++bar (void) {} /* { dg-warning "has no effect on functions with static linkage" } */
++
++int __attribute__ ((cmse_nonsecure_entry))
++baz (void)
++{
++  return qux ();
++}
++
++void __attribute__ ((cmse_nonsecure_call))
++quux (void) {} /* { dg-warning "attribute only applies to base type of a function pointer" } */
++
++int __attribute__ ((cmse_nonsecure_call)) norf; /* { dg-warning "attribute only applies to base type of a function pointer" } */
++
++/* { dg-final { scan-assembler-times "bxns" 2 } } */
++/* { dg-final { scan-assembler "foo:" } } */
++/* { dg-final { scan-assembler "__acle_se_foo:" } } */
++/* { dg-final { scan-assembler-not "__acle_se_bar:" } } */
++/* { dg-final { scan-assembler "baz:" } } */
++/* { dg-final { scan-assembler "__acle_se_baz:" } } */
++/* { dg-final { scan-assembler-not "__acle_se_quux:" } } */
++/* { dg-final { scan-assembler-not "__acle_se_norf:" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse-9.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-skip-if "Testing exclusion of -mcmse" { arm-*-* } { "-mcmse" } { "" } }  */
++
++
++void __attribute__ ((cmse_nonsecure_call)) (*bar) (int); /* { dg-warning "attribute ignored without -mcmse option" } */
++typedef void __attribute__ ((cmse_nonsecure_call)) baz (int); /* { dg-warning "attribute ignored without -mcmse option" } */
++
++int __attribute__ ((cmse_nonsecure_entry))
++foo (int a, baz b)
++{ /* { dg-warning "attribute ignored without -mcmse option" } */
++  bar (a);
++  b (a);
++  return a + 1;
++}
++
++/* { dg-final { scan-assembler-not "bxns" } } */
++/* { dg-final { scan-assembler-not "blxns" } } */
++/* { dg-final { scan-assembler-not "bl\t__gnu_cmse_nonsecure_call" } } */
++/* { dg-final { scan-assembler "foo:" } } */
++/* { dg-final { scan-assembler-not "__acle_se_foo:" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/cmse.exp
+@@ -0,0 +1,72 @@
++#   Copyright (C) 1997-2016 Free Software Foundation, Inc.
++
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with GCC; see the file COPYING3.  If not see
++# <http://www.gnu.org/licenses/>.
++
++# GCC testsuite for ARMv8-M Security Extensions using the `dg.exp' driver.
++
++# Load support procs.
++load_lib gcc-dg.exp
++
++# Exit immediately if the target does not support -mcmse.
++if ![check_effective_target_arm_cmse_ok] then {
++    return
++}
++
++# If a testcase doesn't have special options, use these.
++global DEFAULT_CFLAGS
++if ![info exists DEFAULT_CFLAGS] then {
++    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
++}
++
++# Initialize `dg'.
++dg-init
++
++set saved-dg-do-what-default ${dg-do-what-default}
++set dg-do-what-default "assemble"
++
++set saved-lto_torture_options ${LTO_TORTURE_OPTIONS}
++set LTO_TORTURE_OPTIONS ""
++
++# These are for both baseline and mainline.
++gcc-dg-runtest [lsort [glob $srcdir/$subdir/*.c]] \
++	"" $DEFAULT_CFLAGS
++
++if {[check_effective_target_arm_arch_v8m_base_ok]} then {
++    # Baseline only
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/baseline/*.c]] \
++	    "" $DEFAULT_CFLAGS
++}
++
++if {[check_effective_target_arm_arch_v8m_main_ok]} then {
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/*.c]] \
++	    "" $DEFAULT_CFLAGS
++    # Mainline -mfloat-abi=soft
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/soft/*.c]] \
++	    "-mfloat-abi=soft" $DEFAULT_CFLAGS
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/softfp/*.c]] \
++	    "" $DEFAULT_CFLAGS
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/softfp-sp/*.c]] \
++	    "" $DEFAULT_CFLAGS
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/hard/*.c]] \
++	    "" $DEFAULT_CFLAGS
++    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/hard-sp/*.c]] \
++	    "" $DEFAULT_CFLAGS
++}
++
++set LTO_TORTURE_OPTIONS ${saved-lto_torture_options}
++set dg-do-what-default ${saved-dg-do-what-default}
++
++# All done.
++dg-finish
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-4.c
+@@ -0,0 +1,55 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char a;
++  unsigned int b:5;
++  unsigned int c:11, :0, d:8;
++  struct { unsigned int ee:2; } e;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++extern void foo (test_st st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++  r.values.v4 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #65535" } } */
++/* { dg-final { scan-assembler "movt\tip, 255" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "mov\tip, #255" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "mov\tip, #3" } } */
++/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-5.c
+@@ -0,0 +1,51 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned short  b :5;
++  unsigned char	  c;
++  unsigned short  d :11;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #8191" } } */
++/* { dg-final { scan-assembler "movt\tip, 255" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #2047" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-6.c
+@@ -0,0 +1,61 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char a;
++  unsigned int	b : 3;
++  unsigned int	c : 14;
++  unsigned int	d : 1;
++  struct {
++      unsigned int    ee  : 2;
++      unsigned short  ff  : 15;
++  } e;
++  unsigned char	g : 1;
++  unsigned char	  : 4;
++  unsigned char	h : 3;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++  r.values.v4 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #65535" } } */
++/* { dg-final { scan-assembler "movt\tip, 1023" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "mov\tip, #3" } } */
++/* { dg-final { scan-assembler "movt\tip, 32767" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "mov\tip, #255" } } */
++/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-7.c
+@@ -0,0 +1,52 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned short  b :5;
++  unsigned char	  c;
++  unsigned short  d :11;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++
++/* { dg-final { scan-assembler "movw\tip, #8191" } } */
++/* { dg-final { scan-assembler "movt\tip, 255" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #2047" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-8.c
+@@ -0,0 +1,55 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned int	    :0;
++  unsigned int	  b :1;
++  unsigned short    :0;
++  unsigned short  c;
++  unsigned int	    :0;
++  unsigned int	  d :21;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "mov\tip, #255" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "mov\tip, #1" } } */
++/* { dg-final { scan-assembler "movt\tip, 65535" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #65535" } } */
++/* { dg-final { scan-assembler "movt\tip, 31" } } */
++/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-9.c
+@@ -0,0 +1,54 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  char a:3;
++} test_st3;
++
++typedef struct
++{
++  char a:3;
++} test_st2;
++
++typedef struct
++{
++  test_st2 st2;
++  test_st3 st3;
++} test_st;
++
++typedef union
++{
++  test_st st;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st;
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st);
++
++int
++main (void)
++{
++  read_st r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++
++  f (r.st);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #1799" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-and-union-1.c
+@@ -0,0 +1,94 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned short a :11;
++} test_st_4;
++
++typedef union
++{
++  char	      a;
++  test_st_4 st4;
++}test_un_2;
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned int	    :0;
++  unsigned int	  b :1;
++  unsigned short    :0;
++  unsigned short  c;
++  unsigned int	    :0;
++  unsigned int	  d :21;
++} test_st_3;
++
++typedef struct
++{
++  unsigned char	  a :3;
++  unsigned int	  b :13;
++  test_un_2	  un2;
++} test_st_2;
++
++typedef union
++{
++  test_st_2 st2;
++  test_st_3 st3;
++}test_un_1;
++
++typedef struct
++{
++  unsigned char	  a :2;
++  unsigned char	    :0;
++  unsigned short  b :5;
++  unsigned char	    :0;
++  unsigned char	  c :4;
++  test_un_1	  un1;
++} test_st_1;
++
++typedef union
++{
++  test_st_1 st1;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_st_1;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_st_1);
++
++int
++main (void)
++{
++  read_st_1 r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++  r.values.v4 = 0xFFFFFFFF;
++
++  f (r.st1);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #7939" } } */
++/* { dg-final { scan-assembler "movt\tip, 15" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #65535" } } */
++/* { dg-final { scan-assembler "movt\tip, 2047" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "mov\tip, #1" } } */
++/* { dg-final { scan-assembler "movt\tip, 65535" } } */
++/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #65535" } } */
++/* { dg-final { scan-assembler "movt\tip, 31" } } */
++/* { dg-final { scan-assembler "and\tr3, r3, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c
+@@ -0,0 +1,43 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
++
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (float, double);
++
++int
++foo (int a)
++{
++  return bar (3.0f, 2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts0, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts1, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts2, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts4, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts5, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts6, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts7, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts8, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts9, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts10, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts11, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts12, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts13, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts14, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts15, .L" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c
+@@ -0,0 +1,45 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
++
++extern float bar (void);
++
++float __attribute__ ((cmse_nonsecure_entry))
++foo (void)
++{
++  return bar ();
++}
++/* { dg-final { scan-assembler "mov\tr0, lr" } } */
++/* { dg-final { scan-assembler "mov\tr1, lr" } } */
++/* { dg-final { scan-assembler "mov\tr2, lr" } } */
++/* { dg-final { scan-assembler "mov\tr3, lr" } } */
++/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { arm_arch_v8m_main_ok && { ! arm_dsp } } } } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target { arm_arch_v8m_main_ok && arm_dsp } } } } */
++/* { dg-final { scan-assembler "push\t{r4}" } } */
++/* { dg-final { scan-assembler "vmrs\tip, fpscr" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65376" } } */
++/* { dg-final { scan-assembler "movt\tr4, #4095" } } */
++/* { dg-final { scan-assembler "and\tip, r4" } } */
++/* { dg-final { scan-assembler "vmsr\tfpscr, ip" } } */
++/* { dg-final { scan-assembler "pop\t{r4}" } } */
++/* { dg-final { scan-assembler "mov\tip, lr" } } */
++/* { dg-final { scan-assembler "bxns" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c
+@@ -0,0 +1,42 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (void);
++
++int
++foo (int a)
++{
++  return bar () + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts0, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts1, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts2, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts4, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts5, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts6, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts7, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts8, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts9, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts10, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts11, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts12, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts13, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts14, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts15, .L" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c
+@@ -0,0 +1,41 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (double);
++
++int
++foo (int a)
++{
++  return bar (2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts0, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts1, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts2, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts4, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts5, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts6, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts7, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts8, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts9, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts10, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts11, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts12, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts13, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts14, .L" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts15, .L" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-13.c
+@@ -0,0 +1,38 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
++
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (float, double);
++
++int
++foo (int a)
++{
++  return bar (3.0f, 2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "vldr\.32\ts1, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.64\td0, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts0, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.64\td1, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts2, .L" } } */
++/* { dg-final { scan-assembler-not "vldr\.32\ts3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td2, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td4, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td5, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td6, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td7, .L" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-5.c
+@@ -0,0 +1,38 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
++
++extern float bar (void);
++
++float __attribute__ ((cmse_nonsecure_entry))
++foo (void)
++{
++  return bar ();
++}
++/* { dg-final { scan-assembler "mov\tr0, lr" } } */
++/* { dg-final { scan-assembler "mov\tr1, lr" } } */
++/* { dg-final { scan-assembler "mov\tr2, lr" } } */
++/* { dg-final { scan-assembler "mov\tr3, lr" } } */
++/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { arm_arch_v8m_main_ok && { ! arm_dsp } } } } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target { arm_arch_v8m_main_ok && arm_dsp } } } } */
++/* { dg-final { scan-assembler "push\t{r4}" } } */
++/* { dg-final { scan-assembler "vmrs\tip, fpscr" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65376" } } */
++/* { dg-final { scan-assembler "movt\tr4, #4095" } } */
++/* { dg-final { scan-assembler "and\tip, r4" } } */
++/* { dg-final { scan-assembler "vmsr\tfpscr, ip" } } */
++/* { dg-final { scan-assembler "pop\t{r4}" } } */
++/* { dg-final { scan-assembler "mov\tip, lr" } } */
++/* { dg-final { scan-assembler "bxns" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-7.c
+@@ -0,0 +1,34 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (void);
++
++int
++foo (int a)
++{
++  return bar () + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "vldr\.64\td0, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td1, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td2, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td4, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td5, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td6, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td7, .L" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-8.c
+@@ -0,0 +1,33 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (double);
++
++int
++foo (int a)
++{
++  return bar (2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vldr\.64\td0, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td1, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td2, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td3, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td4, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td5, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td6, .L" } } */
++/* { dg-final { scan-assembler "vldr\.64\td7, .L" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-13.c
+@@ -0,0 +1,27 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=hard" -mfloat-abi=softfp } {""} } */
++/* { dg-options "-mcmse -mfloat-abi=soft" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (float, double);
++
++int
++foo (int a)
++{
++  return bar (1.0f, 2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler-not "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler-not "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vmov" } } */
++/* { dg-final { scan-assembler-not "vmsr" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-5.c
+@@ -0,0 +1,24 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=hard" -mfloat-abi=softfp } {""} } */
++/* { dg-options "-mcmse -mfloat-abi=soft" }  */
++
++extern float bar (void);
++
++float __attribute__ ((cmse_nonsecure_entry))
++foo (void)
++{
++  return bar ();
++}
++
++/* { dg-final { scan-assembler "mov\tr1, lr" } } */
++/* { dg-final { scan-assembler "mov\tr2, lr" } } */
++/* { dg-final { scan-assembler "mov\tr3, lr" } } */
++/* { dg-final { scan-assembler "mov\tip, lr" } } */
++/* { dg-final { scan-assembler-not "vmov" } } */
++/* { dg-final { scan-assembler-not "vmsr" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { arm_arch_v8m_main_ok && { ! arm_dsp } } } } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target { arm_arch_v8m_main_ok && arm_dsp } } } } */
++/* { dg-final { scan-assembler "bxns" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-7.c
+@@ -0,0 +1,27 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=hard" -mfloat-abi=softfp } {""} } */
++/* { dg-options "-mcmse -mfloat-abi=soft" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (void);
++
++int
++foo (int a)
++{
++  return bar () + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vmov" } } */
++/* { dg-final { scan-assembler-not "vmsr" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-8.c
+@@ -0,0 +1,26 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=hard" -mfloat-abi=softfp } {""} } */
++/* { dg-options "-mcmse -mfloat-abi=soft" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (double);
++
++int
++foo (int a)
++{
++  return bar (2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler-not "vmov" } } */
++/* { dg-final { scan-assembler-not "vmsr" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c
+@@ -0,0 +1,46 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" }  */
++
++extern float bar (void);
++
++float __attribute__ ((cmse_nonsecure_entry))
++foo (void)
++{
++  return bar ();
++}
++/* { dg-final { scan-assembler "__acle_se_foo:" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, lr" } } */
++/* { dg-final { scan-assembler "mov\tr1, lr" } } */
++/* { dg-final { scan-assembler "mov\tr2, lr" } } */
++/* { dg-final { scan-assembler "mov\tr3, lr" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts0, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { arm_arch_v8m_main_ok && { ! arm_dsp } } } } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target { arm_arch_v8m_main_ok && arm_dsp } } } } */
++/* { dg-final { scan-assembler "push\t{r4}" } } */
++/* { dg-final { scan-assembler "vmrs\tip, fpscr" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65376" } } */
++/* { dg-final { scan-assembler "movt\tr4, #4095" } } */
++/* { dg-final { scan-assembler "and\tip, r4" } } */
++/* { dg-final { scan-assembler "vmsr\tfpscr, ip" } } */
++/* { dg-final { scan-assembler "pop\t{r4}" } } */
++/* { dg-final { scan-assembler "mov\tip, lr" } } */
++/* { dg-final { scan-assembler "bxns" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c
+@@ -0,0 +1,26 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (void);
++
++int
++foo (int a)
++{
++  return bar () + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (double);
++
++int
++foo (int a)
++{
++  return bar (2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-13.c
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (float, double);
++
++int
++foo (int a)
++{
++  return bar (1.0f, 2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "\n\tmov\tr1, r4" } } */
++/* { dg-final { scan-assembler-not "\n\tmov\tr2, r4\n\tmov\tr3, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-5.c
+@@ -0,0 +1,38 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
++
++extern float bar (void);
++
++float __attribute__ ((cmse_nonsecure_entry))
++foo (void)
++{
++  return bar ();
++}
++/* { dg-final { scan-assembler "__acle_se_foo:" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, lr" } } */
++/* { dg-final { scan-assembler "mov\tr1, lr" } } */
++/* { dg-final { scan-assembler "mov\tr2, lr" } } */
++/* { dg-final { scan-assembler "mov\tr3, lr" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td0, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
++/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { arm_arch_v8m_main_ok && { ! arm_dsp } } } } } */
++/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target { arm_arch_v8m_main_ok && arm_dsp } } } } */
++/* { dg-final { scan-assembler "push\t{r4}" } } */
++/* { dg-final { scan-assembler "vmrs\tip, fpscr" } } */
++/* { dg-final { scan-assembler "movw\tr4, #65376" } } */
++/* { dg-final { scan-assembler "movt\tr4, #4095" } } */
++/* { dg-final { scan-assembler "and\tip, r4" } } */
++/* { dg-final { scan-assembler "vmsr\tfpscr, ip" } } */
++/* { dg-final { scan-assembler "pop\t{r4}" } } */
++/* { dg-final { scan-assembler "mov\tip, lr" } } */
++/* { dg-final { scan-assembler "bxns" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-7.c
+@@ -0,0 +1,26 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (void);
++
++int
++foo (int a)
++{
++  return bar () + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-8.c
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8m_main_ok } */
++/* { dg-add-options arm_arch_v8m_main } */
++/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
++/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
++/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
++
++int __attribute__ ((cmse_nonsecure_call)) (*bar) (double);
++
++int
++foo (int a)
++{
++  return bar (2.0) + a + 1;
++}
++
++/* Checks for saving and clearing prior to function call.  */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
++/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++
++/* Now we check that we use the correct intrinsic to call.  */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/union-1.c
+@@ -0,0 +1,69 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a :2;
++  unsigned char	    :0;
++  unsigned short  b :5;
++  unsigned char	    :0;
++  unsigned short  c :3;
++  unsigned char	    :0;
++  unsigned int	  d :9;
++} test_st_1;
++
++typedef struct
++{
++  unsigned short  a :7;
++  unsigned char	    :0;
++  unsigned char	  b :1;
++  unsigned char	    :0;
++  unsigned short  c :6;
++} test_st_2;
++
++typedef union
++{
++  test_st_1 st_1;
++  test_st_2 st_2;
++}test_un;
++
++typedef union
++{
++  test_un un;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_un;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_un);
++
++int
++main (void)
++{
++  read_un r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++
++  f (r.un);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #8063" } } */
++/* { dg-final { scan-assembler "movt\tip, 63" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #511" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr2, r4" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/mainline/union-2.c
+@@ -0,0 +1,84 @@
++/* { dg-do compile } */
++/* { dg-options "-mcmse" } */
++
++typedef struct
++{
++  unsigned char	  a :2;
++  unsigned char	    :0;
++  unsigned short  b :5;
++  unsigned char	    :0;
++  unsigned short  c :3;
++  unsigned char	    :0;
++  unsigned int	  d :9;
++} test_st_1;
++
++typedef struct
++{
++  unsigned short  a :7;
++  unsigned char	    :0;
++  unsigned char	  b :1;
++  unsigned char	    :0;
++  unsigned short  c :6;
++} test_st_2;
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned int	    :0;
++  unsigned int	  b :1;
++  unsigned short    :0;
++  unsigned short  c;
++  unsigned int	    :0;
++  unsigned int	  d :21;
++} test_st_3;
++
++typedef union
++{
++  test_st_1 st_1;
++  test_st_2 st_2;
++  test_st_3 st_3;
++}test_un;
++
++typedef union
++{
++  test_un un;
++  struct
++    {
++      unsigned int v1;
++      unsigned int v2;
++      unsigned int v3;
++      unsigned int v4;
++    }values;
++} read_un;
++
++
++typedef void __attribute__ ((cmse_nonsecure_call)) (*foo_ns) (test_un);
++
++int
++main (void)
++{
++  read_un r;
++  foo_ns f;
++
++  f = (foo_ns) 0x200000;
++  r.values.v1 = 0xFFFFFFFF;
++  r.values.v2 = 0xFFFFFFFF;
++  r.values.v3 = 0xFFFFFFFF;
++
++  f (r.un);
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movw\tip, #8191" } } */
++/* { dg-final { scan-assembler "movt\tip, 63" } } */
++/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #511" } } */
++/* { dg-final { scan-assembler "movt\tip, 65535" } } */
++/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
++/* { dg-final { scan-assembler "movw\tip, #65535" } } */
++/* { dg-final { scan-assembler "movt\tip, 31" } } */
++/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
++/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
++/* { dg-final { scan-assembler "mov\tr3, r4" } } */
++/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/cmse/struct-1.c
+@@ -0,0 +1,33 @@
++/* { dg-do run } */
++/* { dg-options "--save-temps -mcmse -Wl,--section-start,.gnu.sgstubs=0x20400000" } */
++
++typedef struct
++{
++  unsigned char	  a;
++  unsigned short  b;
++} test_st;
++
++test_st __attribute__ ((cmse_nonsecure_entry)) foo (void)
++{
++  test_st t;
++  t.a = 255u;
++  t.b = 32767u;
++  return t;
++}
++
++int
++main (void)
++{
++  test_st t;
++  t = foo ();
++  if (t.a != 255u || t.b != 32767u)
++    __builtin_abort ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler "movs\tr1, #255" } } */
++/* { dg-final { scan-assembler "movt\tr1, 65535" } } */
++/* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
++/* { dg-final { scan-assembler "bxns" } } */
++
++
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/data-rel-1.c
+@@ -0,0 +1,12 @@
++/* { dg-options "-fPIC -mno-pic-data-is-text-relative" } */
++/* { dg-final { scan-assembler-not "j-\\(.LPIC"  } } */
++/* { dg-final { scan-assembler-not "_GLOBAL_OFFSET_TABLE_-\\(.LPIC" } } */
++/* { dg-final { scan-assembler "j\\(GOT\\)" } } */
++/* { dg-final { scan-assembler "(ldr|mov)\tr\[0-9\]+, \\\[?r9" } } */
++
++static int j;
++
++int *Foo ()
++{
++  return &j;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/data-rel-2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-fPIC -mno-pic-data-is-text-relative -mno-single-pic-base" } */
++/* { dg-final { scan-assembler-not "j-\\(.LPIC"  } } */
++/* { dg-final { scan-assembler "_GLOBAL_OFFSET_TABLE_-\\(.LPIC" } } */
++/* { dg-final { scan-assembler "j\\(GOT\\)" } } */
++
++static int j;
++
++int *Foo ()
++{
++  return &j;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/data-rel-3.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-fPIC -mpic-data-is-text-relative" } */
++/* { dg-final { scan-assembler "j-\\(.LPIC"  } } */
++/* { dg-final { scan-assembler-not "_GLOBAL_OFFSET_TABLE_-\\(.LPIC" } } */
++/* { dg-final { scan-assembler-not "j\\(GOT\\)" } } */
++
++static int j;
++
++int *Foo ()
++{
++  return &j;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_ok } */
++/* { dg-options "-O2" }  */
++/* { dg-add-options arm_fp16_ieee } */
++
++/* Test __fp16 arguments and return value in registers (hard-float).  */
++
++void
++swap (__fp16, __fp16);
++
++__fp16
++F (__fp16 a, __fp16 b, __fp16 c)
++{
++  swap (b, a);
++  return c;
++}
++
++/* { dg-final { scan-assembler {vmov(\.f16)?\tr[0-9]+, s[0-9]+} } }  */
++/* { dg-final { scan-assembler {vmov(\.f32)?\ts1, s0} } }  */
++/* { dg-final { scan-assembler {vmov(\.f16)?\ts0, r[0-9]+} } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_fp16_ok } */
++/* { dg-options "-mfloat-abi=softfp -O2" }  */
++/* { dg-add-options arm_fp16_ieee } */
++/* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } } */
++
++/* Test __fp16 arguments and return value in registers (softfp).  */
++
++void
++swap (__fp16, __fp16);
++
++__fp16
++F (__fp16 a, __fp16 b, __fp16 c)
++{
++  swap (b, a);
++  return c;
++}
++
++/* { dg-final { scan-assembler-times {mov\tr[0-9]+, r[0-2]} 3 } }  */
++/* { dg-final { scan-assembler-times {mov\tr1, r0} 1 } }  */
++/* { dg-final { scan-assembler-times {mov\tr0, r[0-9]+} 2 } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_hard_vfp_ok }  */
++/* { dg-require-effective-target arm_fp16_ok } */
++/* { dg-options "-O2" }  */
++/* { dg-add-options arm_fp16_alternative } */
++
++/* Test __fp16 arguments and return value in registers (hard-float).  */
++
++void
++swap (__fp16, __fp16);
++
++__fp16
++F (__fp16 a, __fp16 b, __fp16 c)
++{
++  swap (b, a);
++  return c;
++}
++
++/* { dg-final { scan-assembler-times {vmov\tr[0-9]+, s[0-2]} 2 } }  */
++/* { dg-final { scan-assembler-times {vmov.f32\ts1, s0} 1 } }  */
++/* { dg-final { scan-assembler-times {vmov\ts0, r[0-9]+} 2 } }  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c
+@@ -0,0 +1,21 @@
++/* { dg-do compile }  */
++/* { dg-require-effective-target arm_fp16_ok } */
++/* { dg-options "-mfloat-abi=softfp -O2" }  */
++/* { dg-add-options arm_fp16_alternative } */
++/* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } } */
++
++/* Test __fp16 arguments and return value in registers (softfp).  */
++
++void
++swap (__fp16, __fp16);
++
++__fp16
++F (__fp16 a, __fp16 b, __fp16 c)
++{
++  swap (b, a);
++  return c;
++}
++
++/* { dg-final { scan-assembler-times {mov\tr[0-9]+, r[0-2]} 3 } }  */
++/* { dg-final { scan-assembler-times {mov\tr1, r0} 1 } }  */
++/* { dg-final { scan-assembler-times {mov\tr0, r[0-9]+} 2 } }  */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ __fp16 xx = 0.0;
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative -pedantic -std=gnu99" } */
+ 
+ #include <math.h>
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative -pedantic -std=gnu99" } */
+ 
+ #include <math.h>
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ float xx __attribute__((mode(HF))) = 0.0;
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* This number is the maximum value representable in the alternative
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative -pedantic" } */
+ 
+ /* This number overflows the range of the alternative encoding.  Since this
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ /* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_none_ok } */
+ /* { dg-options "-mfp16-format=none" } */
+ 
+ /* __fp16 type name is not recognized unless you explicitly enable it
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-compile-none-2.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-compile-none-2.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-effective-target arm_fp16_none_ok } */
+ /* { dg-options "-mfp16-format=none" } */
+ 
+ /* mode(HF) attributes are not recognized unless you explicitly enable
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-param-1.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-param-1.c
+@@ -1,10 +1,14 @@
+ /* { dg-do compile } */
+ /* { dg-options "-mfp16-format=ieee" } */
+ 
+-/* Functions cannot have parameters of type __fp16.  */
+-extern void f (__fp16);		/* { dg-error "parameters cannot have __fp16 type" } */
+-extern void (*pf) (__fp16);	/* { dg-error "parameters cannot have __fp16 type" } */
++/* Test that the ACLE macro is defined.  */
++#if __ARM_FP16_ARGS != 1
++#error Unexpected value for __ARM_FP16_ARGS
++#endif
++
++/* Test that __fp16 is supported as a parameter type.  */
++extern void f (__fp16);
++extern void (*pf) (__fp16);
+ 
+-/* These should be OK.  */
+ extern void g (__fp16 *);
+ extern void (*pg) (__fp16 *);
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-return-1.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-return-1.c
+@@ -1,10 +1,9 @@
+ /* { dg-do compile } */
+ /* { dg-options "-mfp16-format=ieee" } */
+ 
+-/* Functions cannot return type __fp16.  */
+-extern __fp16 f (void);		/* { dg-error "cannot return __fp16" } */
+-extern __fp16 (*pf) (void);	/* { dg-error "cannot return __fp16" } */
++/* Test that __fp16 is supported as a return type.  */
++extern __fp16 f (void);
++extern __fp16 (*pf) (void);
+ 
+-/* These should be OK.  */
+ extern __fp16 *g (void);
+ extern __fp16 *(*pg) (void);
+--- a/src/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c
++++ b/src/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c
+@@ -3,6 +3,7 @@
+    from double to __fp16.  */
+ 
+ /* { dg-do run } */
++/* { dg-require-effective-target arm_fp16_alternative_ok } */
+ /* { dg-options "-mfp16-format=alternative" } */
+ 
+ #include <stdlib.h>
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/movdi_movw.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile { target { arm_thumb2_ok || arm_thumb1_movt_ok } } } */
++/* { dg-options "-O2" } */
++
++long long
++movdi (int a)
++{
++  return 0xF0F0;
++}
++
++/* Accept r1 because big endian targets put the low bits in the highest
++   numbered register of a pair.  */
++/* { dg-final { scan-assembler-times "movw\tr\[01\], #61680" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/movhi_movw.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile { target { arm_thumb2_ok || arm_thumb1_movt_ok } } } */
++/* { dg-options "-O2" } */
++
++short
++movsi (void)
++{
++  return (short) 0x7070;
++}
++
++/* { dg-final { scan-assembler-times "movw\tr0, #28784" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/movsi_movw.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile { target { arm_thumb2_ok || arm_thumb1_movt_ok } } } */
++/* { dg-options "-O2" } */
++
++int
++movsi (void)
++{
++  return 0xF0F0;
++}
++
++/* { dg-final { scan-assembler-times "movw\tr0, #61680" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/neon-vaddws16.c
+@@ -0,0 +1,19 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O3" } */
++/* { dg-add-options arm_neon } */
++
++
++
++int
++t6 (int len, void * dummy, short * __restrict x)
++{
++  len = len & ~31;
++  int result = 0;
++  __asm volatile ("");
++  for (int i = 0; i < len; i++)
++    result += x[i];
++  return result;
++}
++
++/* { dg-final { scan-assembler "vaddw\.s16" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/neon-vaddws32.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O3" } */
++/* { dg-add-options arm_neon } */
++
++
++int
++t6 (int len, void * dummy, int * __restrict x)
++{
++  len = len & ~31;
++  long long result = 0;
++  __asm volatile ("");
++  for (int i = 0; i < len; i++)
++    result += x[i];
++  return result;
++}
++
++/* { dg-final { scan-assembler "vaddw\.s32" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/neon-vaddwu16.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O3" } */
++/* { dg-add-options arm_neon } */
++
++
++int
++t6 (int len, void * dummy, unsigned short * __restrict x)
++{
++  len = len & ~31;
++  unsigned int result = 0;
++  __asm volatile ("");
++  for (int i = 0; i < len; i++)
++    result += x[i];
++  return result;
++}
++
++/* { dg-final { scan-assembler "vaddw.u16" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/neon-vaddwu32.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O3" } */
++/* { dg-add-options arm_neon } */
++
++
++int
++t6 (int len, void * dummy, unsigned int * __restrict x)
++{
++  len = len & ~31;
++  unsigned long long result = 0;
++  __asm volatile ("");
++  for (int i = 0; i < len; i++)
++    result += x[i];
++  return result;
++}
++
++/* { dg-final { scan-assembler "vaddw\.u32" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/neon-vaddwu8.c
+@@ -0,0 +1,19 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O3" } */
++/* { dg-add-options arm_neon } */
++
++
++
++int
++t6 (int len, void * dummy, char * __restrict x)
++{
++  len = len & ~31;
++  unsigned short result = 0;
++  __asm volatile ("");
++  for (int i = 0; i < len; i++)
++    result += x[i];
++  return result;
++}
++
++/* { dg-final { scan-assembler "vaddw\.u8" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/neon.exp
++++ b/src//dev/null
+@@ -1,35 +0,0 @@
+-# Copyright (C) 1997-2016 Free Software Foundation, Inc.
+-
+-# This program is free software; you can redistribute it and/or modify
+-# it under the terms of the GNU General Public License as published by
+-# the Free Software Foundation; either version 3 of the License, or
+-# (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with GCC; see the file COPYING3.  If not see
+-# <http://www.gnu.org/licenses/>.
+-
+-# GCC testsuite that uses the `dg.exp' driver.
+-
+-# Exit immediately if this isn't an ARM target.
+-if ![istarget arm*-*-*] then {
+-  return
+-}
+-
+-# Load support procs.
+-load_lib gcc-dg.exp
+-
+-# Initialize `dg'.
+-dg-init
+-
+-# Main loop.
+-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+-	"" ""
+-
+-# All done.
+-dg-finish
+--- a/src/gcc/testsuite/gcc.target/arm/neon/polytypes.c
++++ b/src//dev/null
+@@ -1,48 +0,0 @@
+-/* Check that NEON polynomial vector types are suitably incompatible with
+-   integer vector types of the same layout.  */
+-
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-add-options arm_neon } */
+-
+-#include <arm_neon.h>
+-
+-void s64_8 (int8x8_t a) {}
+-void u64_8 (uint8x8_t a) {}
+-void p64_8 (poly8x8_t a) {}
+-void s64_16 (int16x4_t a) {}
+-void u64_16 (uint16x4_t a) {}
+-void p64_16 (poly16x4_t a) {}
+-
+-void s128_8 (int8x16_t a) {}
+-void u128_8 (uint8x16_t a) {}
+-void p128_8 (poly8x16_t a) {}
+-void s128_16 (int16x8_t a) {}
+-void u128_16 (uint16x8_t a) {}
+-void p128_16 (poly16x8_t a) {}
+-
+-void foo ()
+-{
+-  poly8x8_t v64_8;
+-  poly16x4_t v64_16;
+-  poly8x16_t v128_8;
+-  poly16x8_t v128_16;
+-
+-  s64_8 (v64_8); /* { dg-message "use -flax-vector-conversions" } */
+-  /* { dg-error "incompatible type for argument 1 of 's64_8'" "" { target *-*-* } 31 } */
+-  u64_8 (v64_8); /* { dg-error "incompatible type for argument 1 of 'u64_8'" } */
+-  p64_8 (v64_8);
+-
+-  s64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 's64_16'" } */
+-  u64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 'u64_16'" } */
+-  p64_16 (v64_16);
+-
+-  s128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 's128_8'" } */
+-  u128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 'u128_8'" } */
+-  p128_8 (v128_8);
+-
+-  s128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 's128_16'" } */
+-  u128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 'u128_16'" } */
+-  p128_16 (v128_16);
+-}
+-/* { dg-message "note: expected '\[^'\n\]*' but argument is of type '\[^'\n\]*'" "note: expected" { target *-*-* } 0 } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/pr51534.c
++++ b/src//dev/null
+@@ -1,83 +0,0 @@
+-/* Test the vector comparison intrinsics when comparing to immediate zero.
+-   */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -mfloat-abi=hard -O3" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include <arm_neon.h>
+-
+-#define GEN_TEST(T, D, C, R) \
+-  R test_##C##_##T (T a) { return C (a, D (0)); }
+-
+-#define GEN_DOUBLE_TESTS(S, T, C) \
+-  GEN_TEST (T, vdup_n_s##S, C##_s##S, u##T) \
+-  GEN_TEST (u##T, vdup_n_u##S, C##_u##S, u##T) 
+-
+-#define GEN_QUAD_TESTS(S, T, C) \
+-  GEN_TEST (T, vdupq_n_s##S, C##q_s##S, u##T) \
+-  GEN_TEST (u##T, vdupq_n_u##S, C##q_u##S, u##T) 
+-
+-#define GEN_COND_TESTS(C) \
+-  GEN_DOUBLE_TESTS (8, int8x8_t, C) \
+-  GEN_DOUBLE_TESTS (16, int16x4_t, C) \
+-  GEN_DOUBLE_TESTS (32, int32x2_t, C) \
+-  GEN_QUAD_TESTS (8, int8x16_t, C) \
+-  GEN_QUAD_TESTS (16, int16x8_t, C) \
+-  GEN_QUAD_TESTS (32, int32x4_t, C)
+-
+-GEN_COND_TESTS(vcgt)
+-GEN_COND_TESTS(vcge)
+-GEN_COND_TESTS(vclt)
+-GEN_COND_TESTS(vcle)
+-GEN_COND_TESTS(vceq)
+-
+-/* Scan for expected outputs.  */
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vclt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
+-
+-/* And ensure we don't have unexpected output too.  */
+-/* { dg-final { scan-assembler-not "vc\[gl\]\[te\]\.u\[0-9\]+\[ 	\]+\[qQdD\]\[0-9\]+, \[qQdD\]\[0-9\]+, #0" } } */
+-
+-/* Tidy up.  */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRaddhns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRaddhns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRaddhns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRaddhns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRaddhns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRaddhns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRaddhnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRaddhnu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRaddhnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRaddhnu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRaddhnu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRaddhnu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhadds16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhadds16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhadds32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhadds32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhadds8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhadds8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRhaddu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRhaddu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshls16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshls32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshls64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshls64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshls64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshls8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRshlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshlu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshr_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshr_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrn_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrn_ns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrn_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrn_ns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrn_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrn_ns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrn_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrn_nu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrn_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrn_nu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vRshrn_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRshrn_nu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsraQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsraQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsra_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsra_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsubhns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsubhns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsubhns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsubhns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsubhns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsubhns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsubhnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsubhnu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsubhnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsubhnu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vRsubhnu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vRsubhnu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabaQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabaQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16x8_t arg2_int16x8_t;
+-
+-  out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabaQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabaQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32x4_t arg2_int32x4_t;
+-
+-  out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabaQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabaQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-  int8x16_t arg2_int8x16_t;
+-
+-  out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabaQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabaQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16x8_t arg2_uint16x8_t;
+-
+-  out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabaQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabaQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32x4_t arg2_uint32x4_t;
+-
+-  out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabaQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabaQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-  uint8x16_t arg2_uint8x16_t;
+-
+-  out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabals16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabals16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabals16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabals32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabals32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabals32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabals8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabals8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabals8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabalu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabalu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabalu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabalu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabalu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabalu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabalu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabalu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabalu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabas16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabas16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabas16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabas32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabas32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabas32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabas8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabas8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabas8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabau16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabau16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabau16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabau32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabau32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabau32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabau8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vabau8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabau8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vabdq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vabdq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vabdq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vabdq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vabdq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vabdq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vabd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vabdl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabdl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vabdl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabdl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdls8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x8_t = vabdl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabdl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdlu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vabdl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabdl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdlu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vabdl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabdl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdlu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x8_t = vabdl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabdl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabds16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabds16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabds16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vabd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabds32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabds32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabds32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vabd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabds8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabds8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabds8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vabd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vabd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vabd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabdu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vabdu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabdu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vabd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabsQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabsQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vabsq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabsQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabsQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vabsq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabsQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabsQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vabsq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabsQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabsQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vabsq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabsf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabsf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabsf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vabs_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabss16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabss16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabss16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vabs_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabss32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabss32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabss32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vabs_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vabss8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vabss8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vabss8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vabs_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vaddq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddhns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddhns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int8x8_t = vaddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddhns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddhns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int16x4_t = vaddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddhns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddhns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int32x2_t = vaddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddhnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddhnu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint8x8_t = vaddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddhnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddhnu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint16x4_t = vaddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddhnu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddhnu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint32x2_t = vaddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vaddl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vaddl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddls8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x8_t = vaddl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddlu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vaddl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddlu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vaddl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddlu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x8_t = vaddl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vadds16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vadds16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vadds16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vadds32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vadds32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vadds32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vadds64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vadds64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vadds64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vadds8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vadds8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vadds8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vaddu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddws16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddws16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddws16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vaddw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddws32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddws32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddws32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vaddw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddws8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddws8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddws8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x8_t = vaddw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddwu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddwu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vaddw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddwu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddwu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vaddw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vaddwu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vaddwu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x8_t = vaddw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vaddw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vandq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vandq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vandq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vandq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vandq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vandq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vandq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vandq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vands16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vands16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vands16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vand_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vands32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vands32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vands32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vand_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vands64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vands64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vands64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vands8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vands8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vands8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vand_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vand_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vand_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vandu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vandu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vandu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vandu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vand_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int16x8_t out_int16x8_t;
+-int16x8_t arg0_int16x8_t;
+-int16x8_t arg1_int16x8_t;
+-void test_vbicQs16 (void)
+-{
+-
+-  out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int32x4_t out_int32x4_t;
+-int32x4_t arg0_int32x4_t;
+-int32x4_t arg1_int32x4_t;
+-void test_vbicQs32 (void)
+-{
+-
+-  out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int64x2_t out_int64x2_t;
+-int64x2_t arg0_int64x2_t;
+-int64x2_t arg1_int64x2_t;
+-void test_vbicQs64 (void)
+-{
+-
+-  out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int8x16_t out_int8x16_t;
+-int8x16_t arg0_int8x16_t;
+-int8x16_t arg1_int8x16_t;
+-void test_vbicQs8 (void)
+-{
+-
+-  out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint16x8_t out_uint16x8_t;
+-uint16x8_t arg0_uint16x8_t;
+-uint16x8_t arg1_uint16x8_t;
+-void test_vbicQu16 (void)
+-{
+-
+-  out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint32x4_t out_uint32x4_t;
+-uint32x4_t arg0_uint32x4_t;
+-uint32x4_t arg1_uint32x4_t;
+-void test_vbicQu32 (void)
+-{
+-
+-  out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint64x2_t out_uint64x2_t;
+-uint64x2_t arg0_uint64x2_t;
+-uint64x2_t arg1_uint64x2_t;
+-void test_vbicQu64 (void)
+-{
+-
+-  out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint8x16_t out_uint8x16_t;
+-uint8x16_t arg0_uint8x16_t;
+-uint8x16_t arg1_uint8x16_t;
+-void test_vbicQu8 (void)
+-{
+-
+-  out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbics16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbics16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int16x4_t out_int16x4_t;
+-int16x4_t arg0_int16x4_t;
+-int16x4_t arg1_int16x4_t;
+-void test_vbics16 (void)
+-{
+-
+-  out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbics32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbics32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int32x2_t out_int32x2_t;
+-int32x2_t arg0_int32x2_t;
+-int32x2_t arg1_int32x2_t;
+-void test_vbics32 (void)
+-{
+-
+-  out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbics64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vbics64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int64x1_t out_int64x1_t;
+-int64x1_t arg0_int64x1_t;
+-int64x1_t arg1_int64x1_t;
+-void test_vbics64 (void)
+-{
+-
+-  out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbics8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbics8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int8x8_t out_int8x8_t;
+-int8x8_t arg0_int8x8_t;
+-int8x8_t arg1_int8x8_t;
+-void test_vbics8 (void)
+-{
+-
+-  out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint16x4_t out_uint16x4_t;
+-uint16x4_t arg0_uint16x4_t;
+-uint16x4_t arg1_uint16x4_t;
+-void test_vbicu16 (void)
+-{
+-
+-  out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint32x2_t out_uint32x2_t;
+-uint32x2_t arg0_uint32x2_t;
+-uint32x2_t arg1_uint32x2_t;
+-void test_vbicu32 (void)
+-{
+-
+-  out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vbicu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint64x1_t out_uint64x1_t;
+-uint64x1_t arg0_uint64x1_t;
+-uint64x1_t arg1_uint64x1_t;
+-void test_vbicu64 (void)
+-{
+-
+-  out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbicu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vbicu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint8x8_t out_uint8x8_t;
+-uint8x8_t arg0_uint8x8_t;
+-uint8x8_t arg1_uint8x8_t;
+-void test_vbicu8 (void)
+-{
+-
+-  out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x4_t arg2_float32x4_t;
+-
+-  out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQp16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-  poly16x8_t arg2_poly16x8_t;
+-
+-  out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQp64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  poly64x2_t arg1_poly64x2_t;
+-  poly64x2_t arg2_poly64x2_t;
+-
+-  out_poly64x2_t = vbslq_p64 (arg0_uint64x2_t, arg1_poly64x2_t, arg2_poly64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-  poly8x16_t arg2_poly8x16_t;
+-
+-  out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16x8_t arg2_int16x8_t;
+-
+-  out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32x4_t arg2_int32x4_t;
+-
+-  out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-  int64x2_t arg2_int64x2_t;
+-
+-  out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-  int8x16_t arg2_int8x16_t;
+-
+-  out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16x8_t arg2_uint16x8_t;
+-
+-  out_uint16x8_t = vbslq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32x4_t arg2_uint32x4_t;
+-
+-  out_uint32x4_t = vbslq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-  uint64x2_t arg2_uint64x2_t;
+-
+-  out_uint64x2_t = vbslq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, arg2_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-  uint8x16_t arg2_uint8x16_t;
+-
+-  out_uint8x16_t = vbslq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslp16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-  poly16x4_t arg2_poly16x4_t;
+-
+-  out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslp64.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslp64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  poly64x1_t arg1_poly64x1_t;
+-  poly64x1_t arg2_poly64x1_t;
+-
+-  out_poly64x1_t = vbsl_p64 (arg0_uint64x1_t, arg1_poly64x1_t, arg2_poly64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-  poly8x8_t arg2_poly8x8_t;
+-
+-  out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbsls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbsls16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbsls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbsls32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbsls64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbsls64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-  int64x1_t arg2_int64x1_t;
+-
+-  out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbsls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbsls8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x4_t = vbsl_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x2_t = vbsl_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslu64.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-  uint64x1_t arg2_uint64x1_t;
+-
+-  out_uint64x1_t = vbsl_u64 (arg0_uint64x1_t, arg1_uint64x1_t, arg2_uint64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vbslu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vbslu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vbslu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vbsl_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcageQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcageQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcageq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcagef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcagef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcagef32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcage_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcagtQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcagtQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcagtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcagtf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcagtf32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcagt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcaleQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcaleQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcaleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcalef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcalef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcalef32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcale_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcaltQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcaltQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcaltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcaltf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcaltf32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcalt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vceqq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQp8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_uint8x16_t = vceqq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQs16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vceqq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQs32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vceqq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQs8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vceqq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vceqq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vceqq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vceqq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqf32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vceq_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqp8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_uint8x8_t = vceq_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqs16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vceq_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqs32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vceq_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vceqs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vceqs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vceqs8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vceq_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcequ16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcequ16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcequ16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vceq_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcequ32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcequ32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcequ32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vceq_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcequ8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcequ8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcequ8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vceq_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcgeq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQs16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vcgeq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQs32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vcgeq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQs8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vcgeq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vcgeq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vcgeq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vcgeq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgef32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcge_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcges16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcges16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcges16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vcge_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcges32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcges32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcges32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vcge_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcges8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcges8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcges8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vcge_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vcge_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vcge_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgeu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgeu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vcge_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcgtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQs16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vcgtq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQs32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vcgtq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQs8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vcgtq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vcgtq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vcgtq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vcgtq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtf32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcgt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgts16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgts16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgts16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vcgt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgts32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgts32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgts32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vcgt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgts8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgts8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgts8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vcgt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vcgt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vcgt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcgtu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcgtu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vcgt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQs16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vcleq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQs32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vcleq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQs8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vcleq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vcleq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vcleq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vcleq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vclef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclef32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vcle_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcles16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcles16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcles16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vcle_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcles32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcles32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcles32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vcle_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcles8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcles8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcles8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vcle_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vcle_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vcle_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcleu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcleu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcleu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vcle_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclsQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclsQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vclsq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclsQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclsQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vclsq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclsQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclsQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vclsq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclss16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclss16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclss16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vcls_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclss32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclss32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclss32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vcls_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclss8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclss8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclss8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vcls_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQf32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_uint32x4_t = vcltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQs16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vcltq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQs32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vcltq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQs8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vcltq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vcltq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vcltq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vcltq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltf32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_uint32x2_t = vclt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclts16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vclts16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclts16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclts32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vclts32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclts32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vclt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclts8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vclts8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclts8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vclt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vclt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vclt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcltu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vcltu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcltu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vclt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vclzq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vclzq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vclzq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vclzq_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vclzq_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vclzq_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vclz_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vclz_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vclz_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vclz_u16 (arg0_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vclz_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vclzu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vclzu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vclzu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vclz_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcntQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcntQp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x16_t = vcntq_p8 (arg0_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcntQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcntQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vcntq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcntQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcntQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vcntq_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcntp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcntp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x8_t = vcnt_p8 (arg0_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcnts8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcnts8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcnts8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vcnt_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcntu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcntu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcntu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vcnt_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombinef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombinef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x4_t = vcombine_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombinep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombinep16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x8_t = vcombine_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombinep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombinep64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64x1_t arg0_poly64x1_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  out_poly64x2_t = vcombine_p64 (arg0_poly64x1_t, arg1_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombinep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombinep8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x16_t = vcombine_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombines16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombines16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombines16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x8_t = vcombine_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombines32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombines32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombines32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x4_t = vcombine_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombines64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombines64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombines64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x2_t = vcombine_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombines8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombines8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombines8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x16_t = vcombine_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombineu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombineu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x8_t = vcombine_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombineu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombineu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x4_t = vcombine_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombineu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombineu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x2_t = vcombine_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcombineu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcombineu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x16_t = vcombine_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreatef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreatef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_float32x2_t = vcreate_f32 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreatep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreatep16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_poly16x4_t = vcreate_p16 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreatep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreatep64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_poly64x1_t = vcreate_p64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreatep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreatep8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_poly8x8_t = vcreate_p8 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreates16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreates16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreates16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_int16x4_t = vcreate_s16 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreates32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreates32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreates32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_int32x2_t = vcreate_s32 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreates64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreates64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreates64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_int64x1_t = vcreate_s64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreates8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreates8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreates8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_int8x8_t = vcreate_s8 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreateu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreateu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint16x4_t = vcreate_u16 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreateu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreateu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint32x2_t = vcreate_u32 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreateu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreateu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint64x1_t = vcreate_u64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vcreateu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcreateu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint8x8_t = vcreate_u8 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQ_nf32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQ_nf32_s32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_float32x4_t = vcvtq_n_f32_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQ_nf32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQ_nf32_u32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_float32x4_t = vcvtq_n_f32_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQ_ns32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQ_ns32_f32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_int32x4_t = vcvtq_n_s32_f32 (arg0_float32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQ_nu32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQ_nu32_f32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_uint32x4_t = vcvtq_n_u32_f32 (arg0_float32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQf32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQf32_s32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_float32x4_t = vcvtq_f32_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQf32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQf32_u32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_float32x4_t = vcvtq_f32_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQs32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQs32_f32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_int32x4_t = vcvtq_s32_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtQu32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtQu32_f32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_uint32x4_t = vcvtq_u32_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvt_nf32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvt_nf32_s32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_float32x2_t = vcvt_n_f32_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvt_nf32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvt_nf32_u32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_float32x2_t = vcvt_n_f32_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvt_ns32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvt_ns32_f32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_int32x2_t = vcvt_n_s32_f32 (arg0_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvt_nu32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvt_nu32_f32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_uint32x2_t = vcvt_n_u32_f32 (arg0_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtf16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_fp16_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon_fp16 } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtf16_f32 (void)
+-{
+-  float16x4_t out_float16x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float16x4_t = vcvt_f16_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f16.f32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtf32_f16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_fp16_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon_fp16 } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtf32_f16 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float16x4_t arg0_float16x4_t;
+-
+-  out_float32x4_t = vcvt_f32_f16 (arg0_float16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.f16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtf32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtf32_s32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_float32x2_t = vcvt_f32_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtf32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtf32_u32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_float32x2_t = vcvt_f32_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvts32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvts32_f32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_int32x2_t = vcvt_s32_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vcvtu32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vcvtu32_f32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_uint32x2_t = vcvt_u32_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanep16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdupQ_lanep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanep64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_poly64x2_t = vdupq_lane_p64 (arg0_poly64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanep8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdupQ_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanes64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64x2_t = vdupq_lane_s64 (arg0_int64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_lanes8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_laneu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_laneu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdupQ_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_laneu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64x2_t = vdupq_lane_u64 (arg0_uint64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_laneu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_nf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32_t arg0_float32_t;
+-
+-  out_float32x4_t = vdupq_n_f32 (arg0_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_np16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16_t arg0_poly16_t;
+-
+-  out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdupQ_np64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_np64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64_t arg0_poly64_t;
+-
+-  out_poly64x2_t = vdupq_n_p64 (arg0_poly64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_np8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8_t arg0_poly8_t;
+-
+-  out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16_t arg0_int16_t;
+-
+-  out_int16x8_t = vdupq_n_s16 (arg0_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32_t arg0_int32_t;
+-
+-  out_int32x4_t = vdupq_n_s32 (arg0_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdupQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64_t arg0_int64_t;
+-
+-  out_int64x2_t = vdupq_n_s64 (arg0_int64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8_t arg0_int8_t;
+-
+-  out_int8x16_t = vdupq_n_s8 (arg0_int8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16_t arg0_uint16_t;
+-
+-  out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32_t arg0_uint32_t;
+-
+-  out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdupQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdupQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdupQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8_t arg0_uint8_t;
+-
+-  out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanep16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdup_lanep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanep64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_poly64x1_t = vdup_lane_p64 (arg0_poly64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanep8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdup_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanes64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64x1_t = vdup_lane_s64 (arg0_int64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_lanes8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_laneu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_laneu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdup_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_laneu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64x1_t = vdup_lane_u64 (arg0_uint64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_laneu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_nf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32_t arg0_float32_t;
+-
+-  out_float32x2_t = vdup_n_f32 (arg0_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_np16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16_t arg0_poly16_t;
+-
+-  out_poly16x4_t = vdup_n_p16 (arg0_poly16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdup_np64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_np64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64_t arg0_poly64_t;
+-
+-  out_poly64x1_t = vdup_n_p64 (arg0_poly64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_np8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8_t arg0_poly8_t;
+-
+-  out_poly8x8_t = vdup_n_p8 (arg0_poly8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16_t arg0_int16_t;
+-
+-  out_int16x4_t = vdup_n_s16 (arg0_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32_t arg0_int32_t;
+-
+-  out_int32x2_t = vdup_n_s32 (arg0_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdup_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64_t arg0_int64_t;
+-
+-  out_int64x1_t = vdup_n_s64 (arg0_int64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8_t arg0_int8_t;
+-
+-  out_int8x8_t = vdup_n_s8 (arg0_int8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16_t arg0_uint16_t;
+-
+-  out_uint16x4_t = vdup_n_u16 (arg0_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32_t arg0_uint32_t;
+-
+-  out_uint32x2_t = vdup_n_u32 (arg0_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vdup_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint64x1_t = vdup_n_u64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vdup_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vdup_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8_t arg0_uint8_t;
+-
+-  out_uint8x8_t = vdup_n_u8 (arg0_uint8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c
++++ b/src//dev/null
+@@ -1,27 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details -mvectorize-with-neon-double" } */
+-/* { dg-add-options arm_neon } */
+-
+-#define N 32
+-
+-int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+-float fa[N];
+-int ia[N];
+-
+-int convert()
+-{
+-  int i;
+-
+-  /* int -> float */
+-  for (i = 0; i < N; i++)
+-    fa[i] = (float) ib[i];
+-
+-  /* float -> int */
+-  for (i = 0; i < N; i++)
+-    ia[i] = (int) fa[i];
+-
+-  return 0;
+-}
+-
+-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c
++++ b/src//dev/null
+@@ -1,27 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */
+-/* { dg-add-options arm_neon } */
+-
+-#define N 32
+-
+-int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+-float fa[N];
+-int ia[N];
+-
+-int convert()
+-{
+-  int i;
+-
+-  /* int -> float */
+-  for (i = 0; i < N; i++)
+-    fa[i] = (float) ib[i];
+-
+-  /* float -> int */
+-  for (i = 0; i < N; i++)
+-    ia[i] = (int) fa[i];
+-
+-  return 0;
+-}
+-
+-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = veorq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = veorq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = veorq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = veorq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = veorq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = veorq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = veorq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veorQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veorQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = veorq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veors16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veors16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veors16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = veor_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veors32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veors32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veors32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = veor_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veors64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `veors64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veors64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veors8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veors8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veors8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = veor_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veoru16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veoru16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veoru16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = veor_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veoru32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veoru32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veoru32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = veor_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veoru64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `veoru64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veoru64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/veoru8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `veoru8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_veoru8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = veor_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vextq_f32 (arg0_float32x4_t, arg1_float32x4_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQp16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8_t = vextq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQp64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQp64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64x2_t arg0_poly64x2_t;
+-  poly64x2_t arg1_poly64x2_t;
+-
+-  out_poly64x2_t = vextq_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16_t = vextq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vextq_s16 (arg0_int16x8_t, arg1_int16x8_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vextq_s32 (arg0_int32x4_t, arg1_int32x4_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vextq_s64 (arg0_int64x2_t, arg1_int64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vextq_s8 (arg0_int8x16_t, arg1_int8x16_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vextq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vextq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vextq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vextq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vext_f32 (arg0_float32x2_t, arg1_float32x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextp16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4_t = vext_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextp64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextp64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x1_t arg0_poly64x1_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  out_poly64x1_t = vext_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8_t = vext_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vexts16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vexts16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vexts16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vext_s16 (arg0_int16x4_t, arg1_int16x4_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vexts32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vexts32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vexts32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vext_s32 (arg0_int32x2_t, arg1_int32x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vexts64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vexts64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vexts64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vext_s64 (arg0_int64x1_t, arg1_int64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vexts8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vexts8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vexts8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vext_s8 (arg0_int8x8_t, arg1_int8x8_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vext_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vext_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vext_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vextu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vextu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vextu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vext_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vfmaQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neonv2_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neonv2 } */
+-
+-#include "arm_neon.h"
+-
+-void test_vfmaQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x4_t arg2_float32x4_t;
+-
+-  out_float32x4_t = vfmaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vfma\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vfmaf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neonv2_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neonv2 } */
+-
+-#include "arm_neon.h"
+-
+-void test_vfmaf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vfma_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vfma\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vfmsQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neonv2_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neonv2 } */
+-
+-#include "arm_neon.h"
+-
+-void test_vfmsQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x4_t arg2_float32x4_t;
+-
+-  out_float32x4_t = vfmsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vfms\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vfmsf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neonv2_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neonv2 } */
+-
+-#include "arm_neon.h"
+-
+-void test_vfmsf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vfms_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vfms\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c
++++ b/src//dev/null
+@@ -1,27 +0,0 @@
+-/* Check that NEON vector shifts support immediate values == size.  /*
+-
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include <arm_neon.h>
+-
+-uint16x8_t test_vshll_n_u8 (uint8x8_t a)
+-{
+-    return vshll_n_u8(a, 8);
+-}
+-
+-uint32x4_t test_vshll_n_u16 (uint16x4_t a)
+-{   
+-    return vshll_n_u16(a, 16);
+-}
+-
+-uint64x2_t test_vshll_n_u32 (uint32x2_t a)
+-{
+-    return vshll_n_u32(a, 32);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanef32 (void)
+-{
+-  float32_t out_float32_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanep16 (void)
+-{
+-  poly16_t out_poly16_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanep8 (void)
+-{
+-  poly8_t out_poly8_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanes16 (void)
+-{
+-  int16_t out_int16_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanes32 (void)
+-{
+-  int32_t out_int32_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanes64 (void)
+-{
+-  register int64_t out_int64_t asm ("r0");
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_lanes8 (void)
+-{
+-  int8_t out_int8_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_laneu16 (void)
+-{
+-  uint16_t out_uint16_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_laneu32 (void)
+-{
+-  uint32_t out_uint32_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_laneu64 (void)
+-{
+-  register uint64_t out_uint64_t asm ("r0");
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vgetQ_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vgetQ_laneu8 (void)
+-{
+-  uint8_t out_uint8_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x2_t = vget_high_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highp16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly16x4_t = vget_high_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highp64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_poly64x1_t = vget_high_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x8_t = vget_high_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x4_t = vget_high_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x2_t = vget_high_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highs64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64x1_t = vget_high_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x8_t = vget_high_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x4_t = vget_high_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x2_t = vget_high_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64x1_t = vget_high_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_highu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_highu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x8_t = vget_high_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanef32 (void)
+-{
+-  float32_t out_float32_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanep16 (void)
+-{
+-  poly16_t out_poly16_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanep8 (void)
+-{
+-  poly8_t out_poly8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanes16 (void)
+-{
+-  int16_t out_int16_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanes32 (void)
+-{
+-  int32_t out_int32_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanes64 (void)
+-{
+-  int64_t out_int64_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lanes8 (void)
+-{
+-  int8_t out_int8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_laneu16 (void)
+-{
+-  uint16_t out_uint16_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_laneu32 (void)
+-{
+-  uint32_t out_uint32_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_laneu64 (void)
+-{
+-  uint64_t out_uint64_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_laneu8 (void)
+-{
+-  uint8_t out_uint8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lowf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowf32 (void)
+-{
+-  register float32x2_t out_float32x2_t asm ("d18");
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x2_t = vget_low_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lowp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowp16 (void)
+-{
+-  register poly16x4_t out_poly16x4_t asm ("d18");
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly16x4_t = vget_low_p16 (arg0_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_lowp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowp64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_poly64x1_t = vget_low_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lowp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowp8 (void)
+-{
+-  register poly8x8_t out_poly8x8_t asm ("d18");
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x8_t = vget_low_p8 (arg0_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lows16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lows16 (void)
+-{
+-  register int16x4_t out_int16x4_t asm ("d18");
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x4_t = vget_low_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lows32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lows32 (void)
+-{
+-  register int32x2_t out_int32x2_t asm ("d18");
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x2_t = vget_low_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_lows64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lows64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64x1_t = vget_low_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lows8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lows8 (void)
+-{
+-  register int8x8_t out_int8x8_t asm ("d18");
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x8_t = vget_low_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lowu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowu16 (void)
+-{
+-  register uint16x4_t out_uint16x4_t asm ("d18");
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x4_t = vget_low_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lowu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowu32 (void)
+-{
+-  register uint32x2_t out_uint32x2_t asm ("d18");
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x2_t = vget_low_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vget_lowu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64x1_t = vget_low_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vget_lowu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vget_lowu8 (void)
+-{
+-  register uint8x8_t out_uint8x8_t asm ("d18");
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x8_t = vget_low_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhadds16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhadds16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhadds16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhadds32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhadds32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhadds32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhadds8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhadds8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhaddu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhaddu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vhsubu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vhsubu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-
+-  out_float32x4_t = vld1q_dup_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupp16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-
+-  out_poly16x8_t = vld1q_dup_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupp64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-
+-  out_poly64x2_t = vld1q_dup_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-
+-  out_poly8x16_t = vld1q_dup_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dups16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dups16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-
+-  out_int16x8_t = vld1q_dup_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dups32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dups32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-
+-  out_int32x4_t = vld1q_dup_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dups64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dups64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-
+-  out_int64x2_t = vld1q_dup_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dups8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dups8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-
+-  out_int8x16_t = vld1q_dup_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-
+-  out_uint16x8_t = vld1q_dup_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-
+-  out_uint32x4_t = vld1q_dup_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-
+-  out_uint64x2_t = vld1q_dup_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Q_dupu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_dupu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-
+-  out_uint8x16_t = vld1q_dup_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanep16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanep64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64x2_t arg1_poly64x2_t;
+-
+-  out_poly64x2_t = vld1q_lane_p64 (0, arg1_poly64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanep8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanes64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_lanes8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_laneu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_laneu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_laneu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1Q_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Q_laneu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-
+-  out_float32x4_t = vld1q_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qp16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-
+-  out_poly16x8_t = vld1q_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qp64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-
+-  out_poly64x2_t = vld1q_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-
+-  out_poly8x16_t = vld1q_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-
+-  out_int16x8_t = vld1q_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-
+-  out_int32x4_t = vld1q_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-
+-  out_int64x2_t = vld1q_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-
+-  out_int8x16_t = vld1q_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-
+-  out_uint16x8_t = vld1q_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-
+-  out_uint32x4_t = vld1q_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-
+-  out_uint64x2_t = vld1q_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1Qu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-
+-  out_uint8x16_t = vld1q_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-
+-  out_float32x2_t = vld1_dup_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupp16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-
+-  out_poly16x4_t = vld1_dup_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupp64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-
+-  out_poly64x1_t = vld1_dup_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-
+-  out_poly8x8_t = vld1_dup_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dups16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dups16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-
+-  out_int16x4_t = vld1_dup_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dups32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dups32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-
+-  out_int32x2_t = vld1_dup_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dups64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dups64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-
+-  out_int64x1_t = vld1_dup_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dups8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dups8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-
+-  out_int8x8_t = vld1_dup_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-
+-  out_uint16x4_t = vld1_dup_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-
+-  out_uint32x2_t = vld1_dup_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-
+-  out_uint64x1_t = vld1_dup_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1_dupu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_dupu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-
+-  out_uint8x8_t = vld1_dup_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanep16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanep64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  out_poly64x1_t = vld1_lane_p64 (0, arg1_poly64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanep8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanes64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_lanes8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_laneu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_laneu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_laneu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld1_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1_laneu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1f32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-
+-  out_float32x2_t = vld1_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1p16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-
+-  out_poly16x4_t = vld1_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1p64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-
+-  out_poly64x1_t = vld1_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-
+-  out_poly8x8_t = vld1_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1s16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-
+-  out_int16x4_t = vld1_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1s32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-
+-  out_int32x2_t = vld1_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1s64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-
+-  out_int64x1_t = vld1_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-
+-  out_int8x8_t = vld1_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1u16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-
+-  out_uint16x4_t = vld1_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1u32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-
+-  out_uint32x2_t = vld1_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1u64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-
+-  out_uint64x1_t = vld1_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld1u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld1u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-
+-  out_uint8x8_t = vld1_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Q_lanef32 (void)
+-{
+-  float32x4x2_t out_float32x4x2_t;
+-  float32x4x2_t arg1_float32x4x2_t;
+-
+-  out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Q_lanep16 (void)
+-{
+-  poly16x8x2_t out_poly16x8x2_t;
+-  poly16x8x2_t arg1_poly16x8x2_t;
+-
+-  out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Q_lanes16 (void)
+-{
+-  int16x8x2_t out_int16x8x2_t;
+-  int16x8x2_t arg1_int16x8x2_t;
+-
+-  out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Q_lanes32 (void)
+-{
+-  int32x4x2_t out_int32x4x2_t;
+-  int32x4x2_t arg1_int32x4x2_t;
+-
+-  out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Q_laneu16 (void)
+-{
+-  uint16x8x2_t out_uint16x8x2_t;
+-  uint16x8x2_t arg1_uint16x8x2_t;
+-
+-  out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Q_laneu32 (void)
+-{
+-  uint32x4x2_t out_uint32x4x2_t;
+-  uint32x4x2_t arg1_uint32x4x2_t;
+-
+-  out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qf32 (void)
+-{
+-  float32x4x2_t out_float32x4x2_t;
+-
+-  out_float32x4x2_t = vld2q_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qp16 (void)
+-{
+-  poly16x8x2_t out_poly16x8x2_t;
+-
+-  out_poly16x8x2_t = vld2q_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qp8 (void)
+-{
+-  poly8x16x2_t out_poly8x16x2_t;
+-
+-  out_poly8x16x2_t = vld2q_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qs16 (void)
+-{
+-  int16x8x2_t out_int16x8x2_t;
+-
+-  out_int16x8x2_t = vld2q_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qs32 (void)
+-{
+-  int32x4x2_t out_int32x4x2_t;
+-
+-  out_int32x4x2_t = vld2q_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qs8 (void)
+-{
+-  int8x16x2_t out_int8x16x2_t;
+-
+-  out_int8x16x2_t = vld2q_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qu16 (void)
+-{
+-  uint16x8x2_t out_uint16x8x2_t;
+-
+-  out_uint16x8x2_t = vld2q_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qu32 (void)
+-{
+-  uint32x4x2_t out_uint32x4x2_t;
+-
+-  out_uint32x4x2_t = vld2q_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2Qu8 (void)
+-{
+-  uint8x16x2_t out_uint8x16x2_t;
+-
+-  out_uint8x16x2_t = vld2q_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupf32 (void)
+-{
+-  float32x2x2_t out_float32x2x2_t;
+-
+-  out_float32x2x2_t = vld2_dup_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupp16 (void)
+-{
+-  poly16x4x2_t out_poly16x4x2_t;
+-
+-  out_poly16x4x2_t = vld2_dup_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupp64 (void)
+-{
+-  poly64x1x2_t out_poly64x1x2_t;
+-
+-  out_poly64x1x2_t = vld2_dup_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupp8 (void)
+-{
+-  poly8x8x2_t out_poly8x8x2_t;
+-
+-  out_poly8x8x2_t = vld2_dup_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dups16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dups16 (void)
+-{
+-  int16x4x2_t out_int16x4x2_t;
+-
+-  out_int16x4x2_t = vld2_dup_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dups32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dups32 (void)
+-{
+-  int32x2x2_t out_int32x2x2_t;
+-
+-  out_int32x2x2_t = vld2_dup_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dups64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dups64 (void)
+-{
+-  int64x1x2_t out_int64x1x2_t;
+-
+-  out_int64x1x2_t = vld2_dup_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dups8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dups8 (void)
+-{
+-  int8x8x2_t out_int8x8x2_t;
+-
+-  out_int8x8x2_t = vld2_dup_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupu16 (void)
+-{
+-  uint16x4x2_t out_uint16x4x2_t;
+-
+-  out_uint16x4x2_t = vld2_dup_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupu32 (void)
+-{
+-  uint32x2x2_t out_uint32x2x2_t;
+-
+-  out_uint32x2x2_t = vld2_dup_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupu64 (void)
+-{
+-  uint64x1x2_t out_uint64x1x2_t;
+-
+-  out_uint64x1x2_t = vld2_dup_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2_dupu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_dupu8 (void)
+-{
+-  uint8x8x2_t out_uint8x8x2_t;
+-
+-  out_uint8x8x2_t = vld2_dup_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_lanef32 (void)
+-{
+-  float32x2x2_t out_float32x2x2_t;
+-  float32x2x2_t arg1_float32x2x2_t;
+-
+-  out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_lanep16 (void)
+-{
+-  poly16x4x2_t out_poly16x4x2_t;
+-  poly16x4x2_t arg1_poly16x4x2_t;
+-
+-  out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_lanep8 (void)
+-{
+-  poly8x8x2_t out_poly8x8x2_t;
+-  poly8x8x2_t arg1_poly8x8x2_t;
+-
+-  out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_lanes16 (void)
+-{
+-  int16x4x2_t out_int16x4x2_t;
+-  int16x4x2_t arg1_int16x4x2_t;
+-
+-  out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_lanes32 (void)
+-{
+-  int32x2x2_t out_int32x2x2_t;
+-  int32x2x2_t arg1_int32x2x2_t;
+-
+-  out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_lanes8 (void)
+-{
+-  int8x8x2_t out_int8x8x2_t;
+-  int8x8x2_t arg1_int8x8x2_t;
+-
+-  out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_laneu16 (void)
+-{
+-  uint16x4x2_t out_uint16x4x2_t;
+-  uint16x4x2_t arg1_uint16x4x2_t;
+-
+-  out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_laneu32 (void)
+-{
+-  uint32x2x2_t out_uint32x2x2_t;
+-  uint32x2x2_t arg1_uint32x2x2_t;
+-
+-  out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld2_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2_laneu8 (void)
+-{
+-  uint8x8x2_t out_uint8x8x2_t;
+-  uint8x8x2_t arg1_uint8x8x2_t;
+-
+-  out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2f32 (void)
+-{
+-  float32x2x2_t out_float32x2x2_t;
+-
+-  out_float32x2x2_t = vld2_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2p16 (void)
+-{
+-  poly16x4x2_t out_poly16x4x2_t;
+-
+-  out_poly16x4x2_t = vld2_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2p64 (void)
+-{
+-  poly64x1x2_t out_poly64x1x2_t;
+-
+-  out_poly64x1x2_t = vld2_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2p8 (void)
+-{
+-  poly8x8x2_t out_poly8x8x2_t;
+-
+-  out_poly8x8x2_t = vld2_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2s16 (void)
+-{
+-  int16x4x2_t out_int16x4x2_t;
+-
+-  out_int16x4x2_t = vld2_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2s32 (void)
+-{
+-  int32x2x2_t out_int32x2x2_t;
+-
+-  out_int32x2x2_t = vld2_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2s64 (void)
+-{
+-  int64x1x2_t out_int64x1x2_t;
+-
+-  out_int64x1x2_t = vld2_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2s8 (void)
+-{
+-  int8x8x2_t out_int8x8x2_t;
+-
+-  out_int8x8x2_t = vld2_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2u16 (void)
+-{
+-  uint16x4x2_t out_uint16x4x2_t;
+-
+-  out_uint16x4x2_t = vld2_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2u32 (void)
+-{
+-  uint32x2x2_t out_uint32x2x2_t;
+-
+-  out_uint32x2x2_t = vld2_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2u64 (void)
+-{
+-  uint64x1x2_t out_uint64x1x2_t;
+-
+-  out_uint64x1x2_t = vld2_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld2u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld2u8 (void)
+-{
+-  uint8x8x2_t out_uint8x8x2_t;
+-
+-  out_uint8x8x2_t = vld2_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Q_lanef32 (void)
+-{
+-  float32x4x3_t out_float32x4x3_t;
+-  float32x4x3_t arg1_float32x4x3_t;
+-
+-  out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Q_lanep16 (void)
+-{
+-  poly16x8x3_t out_poly16x8x3_t;
+-  poly16x8x3_t arg1_poly16x8x3_t;
+-
+-  out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Q_lanes16 (void)
+-{
+-  int16x8x3_t out_int16x8x3_t;
+-  int16x8x3_t arg1_int16x8x3_t;
+-
+-  out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Q_lanes32 (void)
+-{
+-  int32x4x3_t out_int32x4x3_t;
+-  int32x4x3_t arg1_int32x4x3_t;
+-
+-  out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Q_laneu16 (void)
+-{
+-  uint16x8x3_t out_uint16x8x3_t;
+-  uint16x8x3_t arg1_uint16x8x3_t;
+-
+-  out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Q_laneu32 (void)
+-{
+-  uint32x4x3_t out_uint32x4x3_t;
+-  uint32x4x3_t arg1_uint32x4x3_t;
+-
+-  out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qf32 (void)
+-{
+-  float32x4x3_t out_float32x4x3_t;
+-
+-  out_float32x4x3_t = vld3q_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qp16 (void)
+-{
+-  poly16x8x3_t out_poly16x8x3_t;
+-
+-  out_poly16x8x3_t = vld3q_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qp8 (void)
+-{
+-  poly8x16x3_t out_poly8x16x3_t;
+-
+-  out_poly8x16x3_t = vld3q_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qs16 (void)
+-{
+-  int16x8x3_t out_int16x8x3_t;
+-
+-  out_int16x8x3_t = vld3q_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qs32 (void)
+-{
+-  int32x4x3_t out_int32x4x3_t;
+-
+-  out_int32x4x3_t = vld3q_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qs8 (void)
+-{
+-  int8x16x3_t out_int8x16x3_t;
+-
+-  out_int8x16x3_t = vld3q_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qu16 (void)
+-{
+-  uint16x8x3_t out_uint16x8x3_t;
+-
+-  out_uint16x8x3_t = vld3q_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qu32 (void)
+-{
+-  uint32x4x3_t out_uint32x4x3_t;
+-
+-  out_uint32x4x3_t = vld3q_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3Qu8 (void)
+-{
+-  uint8x16x3_t out_uint8x16x3_t;
+-
+-  out_uint8x16x3_t = vld3q_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupf32 (void)
+-{
+-  float32x2x3_t out_float32x2x3_t;
+-
+-  out_float32x2x3_t = vld3_dup_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupp16 (void)
+-{
+-  poly16x4x3_t out_poly16x4x3_t;
+-
+-  out_poly16x4x3_t = vld3_dup_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupp64 (void)
+-{
+-  poly64x1x3_t out_poly64x1x3_t;
+-
+-  out_poly64x1x3_t = vld3_dup_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupp8 (void)
+-{
+-  poly8x8x3_t out_poly8x8x3_t;
+-
+-  out_poly8x8x3_t = vld3_dup_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dups16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dups16 (void)
+-{
+-  int16x4x3_t out_int16x4x3_t;
+-
+-  out_int16x4x3_t = vld3_dup_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dups32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dups32 (void)
+-{
+-  int32x2x3_t out_int32x2x3_t;
+-
+-  out_int32x2x3_t = vld3_dup_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dups64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dups64 (void)
+-{
+-  int64x1x3_t out_int64x1x3_t;
+-
+-  out_int64x1x3_t = vld3_dup_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dups8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dups8 (void)
+-{
+-  int8x8x3_t out_int8x8x3_t;
+-
+-  out_int8x8x3_t = vld3_dup_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupu16 (void)
+-{
+-  uint16x4x3_t out_uint16x4x3_t;
+-
+-  out_uint16x4x3_t = vld3_dup_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupu32 (void)
+-{
+-  uint32x2x3_t out_uint32x2x3_t;
+-
+-  out_uint32x2x3_t = vld3_dup_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupu64 (void)
+-{
+-  uint64x1x3_t out_uint64x1x3_t;
+-
+-  out_uint64x1x3_t = vld3_dup_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3_dupu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_dupu8 (void)
+-{
+-  uint8x8x3_t out_uint8x8x3_t;
+-
+-  out_uint8x8x3_t = vld3_dup_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_lanef32 (void)
+-{
+-  float32x2x3_t out_float32x2x3_t;
+-  float32x2x3_t arg1_float32x2x3_t;
+-
+-  out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_lanep16 (void)
+-{
+-  poly16x4x3_t out_poly16x4x3_t;
+-  poly16x4x3_t arg1_poly16x4x3_t;
+-
+-  out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_lanep8 (void)
+-{
+-  poly8x8x3_t out_poly8x8x3_t;
+-  poly8x8x3_t arg1_poly8x8x3_t;
+-
+-  out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_lanes16 (void)
+-{
+-  int16x4x3_t out_int16x4x3_t;
+-  int16x4x3_t arg1_int16x4x3_t;
+-
+-  out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_lanes32 (void)
+-{
+-  int32x2x3_t out_int32x2x3_t;
+-  int32x2x3_t arg1_int32x2x3_t;
+-
+-  out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_lanes8 (void)
+-{
+-  int8x8x3_t out_int8x8x3_t;
+-  int8x8x3_t arg1_int8x8x3_t;
+-
+-  out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_laneu16 (void)
+-{
+-  uint16x4x3_t out_uint16x4x3_t;
+-  uint16x4x3_t arg1_uint16x4x3_t;
+-
+-  out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_laneu32 (void)
+-{
+-  uint32x2x3_t out_uint32x2x3_t;
+-  uint32x2x3_t arg1_uint32x2x3_t;
+-
+-  out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld3_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3_laneu8 (void)
+-{
+-  uint8x8x3_t out_uint8x8x3_t;
+-  uint8x8x3_t arg1_uint8x8x3_t;
+-
+-  out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3f32 (void)
+-{
+-  float32x2x3_t out_float32x2x3_t;
+-
+-  out_float32x2x3_t = vld3_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3p16 (void)
+-{
+-  poly16x4x3_t out_poly16x4x3_t;
+-
+-  out_poly16x4x3_t = vld3_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3p64 (void)
+-{
+-  poly64x1x3_t out_poly64x1x3_t;
+-
+-  out_poly64x1x3_t = vld3_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3p8 (void)
+-{
+-  poly8x8x3_t out_poly8x8x3_t;
+-
+-  out_poly8x8x3_t = vld3_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3s16 (void)
+-{
+-  int16x4x3_t out_int16x4x3_t;
+-
+-  out_int16x4x3_t = vld3_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3s32 (void)
+-{
+-  int32x2x3_t out_int32x2x3_t;
+-
+-  out_int32x2x3_t = vld3_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3s64 (void)
+-{
+-  int64x1x3_t out_int64x1x3_t;
+-
+-  out_int64x1x3_t = vld3_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3s8 (void)
+-{
+-  int8x8x3_t out_int8x8x3_t;
+-
+-  out_int8x8x3_t = vld3_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3u16 (void)
+-{
+-  uint16x4x3_t out_uint16x4x3_t;
+-
+-  out_uint16x4x3_t = vld3_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3u32 (void)
+-{
+-  uint32x2x3_t out_uint32x2x3_t;
+-
+-  out_uint32x2x3_t = vld3_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3u64 (void)
+-{
+-  uint64x1x3_t out_uint64x1x3_t;
+-
+-  out_uint64x1x3_t = vld3_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld3u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld3u8 (void)
+-{
+-  uint8x8x3_t out_uint8x8x3_t;
+-
+-  out_uint8x8x3_t = vld3_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Q_lanef32 (void)
+-{
+-  float32x4x4_t out_float32x4x4_t;
+-  float32x4x4_t arg1_float32x4x4_t;
+-
+-  out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Q_lanep16 (void)
+-{
+-  poly16x8x4_t out_poly16x8x4_t;
+-  poly16x8x4_t arg1_poly16x8x4_t;
+-
+-  out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Q_lanes16 (void)
+-{
+-  int16x8x4_t out_int16x8x4_t;
+-  int16x8x4_t arg1_int16x8x4_t;
+-
+-  out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Q_lanes32 (void)
+-{
+-  int32x4x4_t out_int32x4x4_t;
+-  int32x4x4_t arg1_int32x4x4_t;
+-
+-  out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Q_laneu16 (void)
+-{
+-  uint16x8x4_t out_uint16x8x4_t;
+-  uint16x8x4_t arg1_uint16x8x4_t;
+-
+-  out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Q_laneu32 (void)
+-{
+-  uint32x4x4_t out_uint32x4x4_t;
+-  uint32x4x4_t arg1_uint32x4x4_t;
+-
+-  out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qf32 (void)
+-{
+-  float32x4x4_t out_float32x4x4_t;
+-
+-  out_float32x4x4_t = vld4q_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qp16 (void)
+-{
+-  poly16x8x4_t out_poly16x8x4_t;
+-
+-  out_poly16x8x4_t = vld4q_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qp8 (void)
+-{
+-  poly8x16x4_t out_poly8x16x4_t;
+-
+-  out_poly8x16x4_t = vld4q_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qs16 (void)
+-{
+-  int16x8x4_t out_int16x8x4_t;
+-
+-  out_int16x8x4_t = vld4q_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qs32 (void)
+-{
+-  int32x4x4_t out_int32x4x4_t;
+-
+-  out_int32x4x4_t = vld4q_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qs8 (void)
+-{
+-  int8x16x4_t out_int8x16x4_t;
+-
+-  out_int8x16x4_t = vld4q_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qu16 (void)
+-{
+-  uint16x8x4_t out_uint16x8x4_t;
+-
+-  out_uint16x8x4_t = vld4q_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qu32 (void)
+-{
+-  uint32x4x4_t out_uint32x4x4_t;
+-
+-  out_uint32x4x4_t = vld4q_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4Qu8 (void)
+-{
+-  uint8x16x4_t out_uint8x16x4_t;
+-
+-  out_uint8x16x4_t = vld4q_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupf32 (void)
+-{
+-  float32x2x4_t out_float32x2x4_t;
+-
+-  out_float32x2x4_t = vld4_dup_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupp16 (void)
+-{
+-  poly16x4x4_t out_poly16x4x4_t;
+-
+-  out_poly16x4x4_t = vld4_dup_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupp64 (void)
+-{
+-  poly64x1x4_t out_poly64x1x4_t;
+-
+-  out_poly64x1x4_t = vld4_dup_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupp8 (void)
+-{
+-  poly8x8x4_t out_poly8x8x4_t;
+-
+-  out_poly8x8x4_t = vld4_dup_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dups16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dups16 (void)
+-{
+-  int16x4x4_t out_int16x4x4_t;
+-
+-  out_int16x4x4_t = vld4_dup_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dups32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dups32 (void)
+-{
+-  int32x2x4_t out_int32x2x4_t;
+-
+-  out_int32x2x4_t = vld4_dup_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dups64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dups64 (void)
+-{
+-  int64x1x4_t out_int64x1x4_t;
+-
+-  out_int64x1x4_t = vld4_dup_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dups8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dups8 (void)
+-{
+-  int8x8x4_t out_int8x8x4_t;
+-
+-  out_int8x8x4_t = vld4_dup_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupu16 (void)
+-{
+-  uint16x4x4_t out_uint16x4x4_t;
+-
+-  out_uint16x4x4_t = vld4_dup_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupu32 (void)
+-{
+-  uint32x2x4_t out_uint32x2x4_t;
+-
+-  out_uint32x2x4_t = vld4_dup_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupu64 (void)
+-{
+-  uint64x1x4_t out_uint64x1x4_t;
+-
+-  out_uint64x1x4_t = vld4_dup_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4_dupu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_dupu8 (void)
+-{
+-  uint8x8x4_t out_uint8x8x4_t;
+-
+-  out_uint8x8x4_t = vld4_dup_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_lanef32 (void)
+-{
+-  float32x2x4_t out_float32x2x4_t;
+-  float32x2x4_t arg1_float32x2x4_t;
+-
+-  out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_lanep16 (void)
+-{
+-  poly16x4x4_t out_poly16x4x4_t;
+-  poly16x4x4_t arg1_poly16x4x4_t;
+-
+-  out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_lanep8 (void)
+-{
+-  poly8x8x4_t out_poly8x8x4_t;
+-  poly8x8x4_t arg1_poly8x8x4_t;
+-
+-  out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_lanes16 (void)
+-{
+-  int16x4x4_t out_int16x4x4_t;
+-  int16x4x4_t arg1_int16x4x4_t;
+-
+-  out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_lanes32 (void)
+-{
+-  int32x2x4_t out_int32x2x4_t;
+-  int32x2x4_t arg1_int32x2x4_t;
+-
+-  out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_lanes8 (void)
+-{
+-  int8x8x4_t out_int8x8x4_t;
+-  int8x8x4_t arg1_int8x8x4_t;
+-
+-  out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_laneu16 (void)
+-{
+-  uint16x4x4_t out_uint16x4x4_t;
+-  uint16x4x4_t arg1_uint16x4x4_t;
+-
+-  out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_laneu32 (void)
+-{
+-  uint32x2x4_t out_uint32x2x4_t;
+-  uint32x2x4_t arg1_uint32x2x4_t;
+-
+-  out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vld4_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4_laneu8 (void)
+-{
+-  uint8x8x4_t out_uint8x8x4_t;
+-  uint8x8x4_t arg1_uint8x8x4_t;
+-
+-  out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4f32 (void)
+-{
+-  float32x2x4_t out_float32x2x4_t;
+-
+-  out_float32x2x4_t = vld4_f32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4p16 (void)
+-{
+-  poly16x4x4_t out_poly16x4x4_t;
+-
+-  out_poly16x4x4_t = vld4_p16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4p64 (void)
+-{
+-  poly64x1x4_t out_poly64x1x4_t;
+-
+-  out_poly64x1x4_t = vld4_p64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4p8 (void)
+-{
+-  poly8x8x4_t out_poly8x8x4_t;
+-
+-  out_poly8x8x4_t = vld4_p8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4s16 (void)
+-{
+-  int16x4x4_t out_int16x4x4_t;
+-
+-  out_int16x4x4_t = vld4_s16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4s32 (void)
+-{
+-  int32x2x4_t out_int32x2x4_t;
+-
+-  out_int32x2x4_t = vld4_s32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4s64 (void)
+-{
+-  int64x1x4_t out_int64x1x4_t;
+-
+-  out_int64x1x4_t = vld4_s64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4s8 (void)
+-{
+-  int8x8x4_t out_int8x8x4_t;
+-
+-  out_int8x8x4_t = vld4_s8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4u16 (void)
+-{
+-  uint16x4x4_t out_uint16x4x4_t;
+-
+-  out_uint16x4x4_t = vld4_u16 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4u32 (void)
+-{
+-  uint32x2x4_t out_uint32x2x4_t;
+-
+-  out_uint32x2x4_t = vld4_u32 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4u64 (void)
+-{
+-  uint64x1x4_t out_uint64x1x4_t;
+-
+-  out_uint64x1x4_t = vld4_u64 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vld4u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vld4u8 (void)
+-{
+-  uint8x8x4_t out_uint8x8x4_t;
+-
+-  out_uint8x8x4_t = vld4_u8 (0);
+-}
+-
+-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmaxu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmaxu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmins16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmins16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmins16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmins32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmins32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmins32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmins8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmins8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmins8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vminu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vminu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vminu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_lanef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_laneu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_laneu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_nf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32_t arg2_float32_t;
+-
+-  out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16_t arg2_uint16_t;
+-
+-  out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32_t arg2_uint32_t;
+-
+-  out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x4_t arg2_float32x4_t;
+-
+-  out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16x8_t arg2_int16x8_t;
+-
+-  out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32x4_t arg2_int32x4_t;
+-
+-  out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-  int8x16_t arg2_int8x16_t;
+-
+-  out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16x8_t arg2_uint16x8_t;
+-
+-  out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32x4_t arg2_uint32x4_t;
+-
+-  out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-  uint8x16_t arg2_uint8x16_t;
+-
+-  out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_lanef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_laneu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_laneu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_nf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32_t arg2_float32_t;
+-
+-  out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16_t arg2_uint16_t;
+-
+-  out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmla_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmla_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32_t arg2_uint32_t;
+-
+-  out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlaf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlaf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_lanes16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_lanes32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_laneu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_laneu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_nu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16_t arg2_uint16_t;
+-
+-  out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlal_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlal_nu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32_t arg2_uint32_t;
+-
+-  out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlals16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlals16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlals32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlals32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlals8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlals8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlalu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlalu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlalu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlalu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlalu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlalu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlas16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlas16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlas32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlas32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlas8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlas8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlau16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlau16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlau32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlau32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlau8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlau8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_lanef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_laneu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_laneu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_nf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32_t arg2_float32_t;
+-
+-  out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16_t arg2_uint16_t;
+-
+-  out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32_t arg2_uint32_t;
+-
+-  out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-  float32x4_t arg2_float32x4_t;
+-
+-  out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-  int16x8_t arg2_int16x8_t;
+-
+-  out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-  int32x4_t arg2_int32x4_t;
+-
+-  out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-  int8x16_t arg2_int8x16_t;
+-
+-  out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-  uint16x8_t arg2_uint16x8_t;
+-
+-  out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-  uint32x4_t arg2_uint32x4_t;
+-
+-  out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-  uint8x16_t arg2_uint8x16_t;
+-
+-  out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_lanef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_laneu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_laneu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_nf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32_t arg2_float32_t;
+-
+-  out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16_t arg2_uint16_t;
+-
+-  out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmls_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmls_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32_t arg2_uint32_t;
+-
+-  out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-  float32x2_t arg2_float32x2_t;
+-
+-  out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_lanes16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_lanes32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_laneu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_laneu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_nu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16_t arg2_uint16_t;
+-
+-  out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsl_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsl_nu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32_t arg2_uint32_t;
+-
+-  out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsls8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlslu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlslu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlslu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlslu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlslu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlslu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmlsl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlss16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlss16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlss32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlss32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlss8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlss8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-  uint16x4_t arg2_uint16x4_t;
+-
+-  out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-  uint32x2_t arg2_uint32x2_t;
+-
+-  out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vmlsu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmlsu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_nf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32_t arg0_float32_t;
+-
+-  out_float32x4_t = vmovq_n_f32 (arg0_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_np16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16_t arg0_poly16_t;
+-
+-  out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_np8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8_t arg0_poly8_t;
+-
+-  out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16_t arg0_int16_t;
+-
+-  out_int16x8_t = vmovq_n_s16 (arg0_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32_t arg0_int32_t;
+-
+-  out_int32x4_t = vmovq_n_s32 (arg0_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vmovQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64_t arg0_int64_t;
+-
+-  out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8_t arg0_int8_t;
+-
+-  out_int8x16_t = vmovq_n_s8 (arg0_int8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16_t arg0_uint16_t;
+-
+-  out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32_t arg0_uint32_t;
+-
+-  out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vmovQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8_t arg0_uint8_t;
+-
+-  out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_nf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32_t arg0_float32_t;
+-
+-  out_float32x2_t = vmov_n_f32 (arg0_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_np16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16_t arg0_poly16_t;
+-
+-  out_poly16x4_t = vmov_n_p16 (arg0_poly16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_np8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8_t arg0_poly8_t;
+-
+-  out_poly8x8_t = vmov_n_p8 (arg0_poly8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16_t arg0_int16_t;
+-
+-  out_int16x4_t = vmov_n_s16 (arg0_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32_t arg0_int32_t;
+-
+-  out_int32x2_t = vmov_n_s32 (arg0_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vmov_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64_t arg0_int64_t;
+-
+-  out_int64x1_t = vmov_n_s64 (arg0_int64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8_t arg0_int8_t;
+-
+-  out_int8x8_t = vmov_n_s8 (arg0_int8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16_t arg0_uint16_t;
+-
+-  out_uint16x4_t = vmov_n_u16 (arg0_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32_t arg0_uint32_t;
+-
+-  out_uint32x2_t = vmov_n_u32 (arg0_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vmov_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64_t arg0_uint64_t;
+-
+-  out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmov_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmov_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8_t arg0_uint8_t;
+-
+-  out_uint8x8_t = vmov_n_u8 (arg0_uint8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int32x4_t = vmovl_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int64x2_t = vmovl_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovls8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int16x8_t = vmovl_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovlu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovlu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovlu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x8_t = vmovn_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x4_t = vmovn_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x2_t = vmovn_s64 (arg0_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovnu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovnu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmovnu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmovnu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_lanef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_laneu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_laneu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_nf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32_t arg1_float32_t;
+-
+-  out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16_t arg1_uint16_t;
+-
+-  out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32_t arg1_uint32_t;
+-
+-  out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_lanef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_laneu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_laneu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_nf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_nf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32_t arg1_float32_t;
+-
+-  out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16_t arg1_uint16_t;
+-
+-  out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmul_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmul_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32_t arg1_uint32_t;
+-
+-  out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_lanes16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_lanes32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_laneu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_laneu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_nu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16_t arg1_uint16_t;
+-
+-  out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmull_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmull_nu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32_t arg1_uint32_t;
+-
+-  out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmullp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmullp8 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulls8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmullu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmullu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmullu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmullu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmullu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmullu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmull\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmuls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmuls16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmuls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmuls32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmuls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmuls8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vmulu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmulu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vmvnq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vmvnq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vmvnq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnp8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vmvn_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vmvn_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vmvn_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vmvnu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vmvnu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vnegq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vnegq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vnegq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vnegq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vneg_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vneg_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vneg_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vnegs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vnegs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vneg_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int16x8_t out_int16x8_t;
+-int16x8_t arg0_int16x8_t;
+-int16x8_t arg1_int16x8_t;
+-void test_vornQs16 (void)
+-{
+-
+-  out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int32x4_t out_int32x4_t;
+-int32x4_t arg0_int32x4_t;
+-int32x4_t arg1_int32x4_t;
+-void test_vornQs32 (void)
+-{
+-
+-  out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int64x2_t out_int64x2_t;
+-int64x2_t arg0_int64x2_t;
+-int64x2_t arg1_int64x2_t;
+-void test_vornQs64 (void)
+-{
+-
+-  out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int8x16_t out_int8x16_t;
+-int8x16_t arg0_int8x16_t;
+-int8x16_t arg1_int8x16_t;
+-void test_vornQs8 (void)
+-{
+-
+-  out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint16x8_t out_uint16x8_t;
+-uint16x8_t arg0_uint16x8_t;
+-uint16x8_t arg1_uint16x8_t;
+-void test_vornQu16 (void)
+-{
+-
+-  out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint32x4_t out_uint32x4_t;
+-uint32x4_t arg0_uint32x4_t;
+-uint32x4_t arg1_uint32x4_t;
+-void test_vornQu32 (void)
+-{
+-
+-  out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint64x2_t out_uint64x2_t;
+-uint64x2_t arg0_uint64x2_t;
+-uint64x2_t arg1_uint64x2_t;
+-void test_vornQu64 (void)
+-{
+-
+-  out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint8x16_t out_uint8x16_t;
+-uint8x16_t arg0_uint8x16_t;
+-uint8x16_t arg1_uint8x16_t;
+-void test_vornQu8 (void)
+-{
+-
+-  out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int16x4_t out_int16x4_t;
+-int16x4_t arg0_int16x4_t;
+-int16x4_t arg1_int16x4_t;
+-void test_vorns16 (void)
+-{
+-
+-  out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int32x2_t out_int32x2_t;
+-int32x2_t arg0_int32x2_t;
+-int32x2_t arg1_int32x2_t;
+-void test_vorns32 (void)
+-{
+-
+-  out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vorns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int64x1_t out_int64x1_t;
+-int64x1_t arg0_int64x1_t;
+-int64x1_t arg1_int64x1_t;
+-void test_vorns64 (void)
+-{
+-
+-  out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-int8x8_t out_int8x8_t;
+-int8x8_t arg0_int8x8_t;
+-int8x8_t arg1_int8x8_t;
+-void test_vorns8 (void)
+-{
+-
+-  out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint16x4_t out_uint16x4_t;
+-uint16x4_t arg0_uint16x4_t;
+-uint16x4_t arg1_uint16x4_t;
+-void test_vornu16 (void)
+-{
+-
+-  out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint32x2_t out_uint32x2_t;
+-uint32x2_t arg0_uint32x2_t;
+-uint32x2_t arg1_uint32x2_t;
+-void test_vornu32 (void)
+-{
+-
+-  out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vornu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint64x1_t out_uint64x1_t;
+-uint64x1_t arg0_uint64x1_t;
+-uint64x1_t arg1_uint64x1_t;
+-void test_vornu64 (void)
+-{
+-
+-  out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vornu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vornu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O2" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-uint8x8_t out_uint8x8_t;
+-uint8x8_t arg0_uint8x8_t;
+-uint8x8_t arg1_uint8x8_t;
+-void test_vornu8 (void)
+-{
+-
+-  out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vorrs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrs64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorrs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorrs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorru16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorru16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorru16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorru32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorru32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorru32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorru64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vorru64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorru64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vorru8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vorru8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vorru8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalQs16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalQs32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalQs8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalQu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalQu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalQu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadals16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadals16 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadals32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadals32 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadals8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadals8 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalu16 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalu32 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadalu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadalu8 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpaddf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlQs16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlQs32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlQs8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlQu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlQu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlQu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddls16 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int32x2_t = vpaddl_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddls32 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int64x1_t = vpaddl_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddls8 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int16x4_t = vpaddl_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlu16 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlu32 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vpaddlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddlu8 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadds16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadds16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadds32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadds32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpadds8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpadds8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpaddu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpaddu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpaddu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpaddu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmaxu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmaxu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpminf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpminf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmins16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmins16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmins32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmins32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpmins8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpmins8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpminu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpminu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpminu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpminu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vpminu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vpminu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vpmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulh_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulh_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulh_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulh_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulh_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulh_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulh_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulh_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRdmulhs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRdmulhs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshls16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshls32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshls64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshls64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshls8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqRshlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshlu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrn_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrn_ns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrn_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrn_ns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrn_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrn_ns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrn_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrn_nu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrn_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrn_nu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrn_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrn_nu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrun_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrun_ns16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrun_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrun_ns32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqRshrun_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqRshrun_ns64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqrshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqabsQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqabsQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vqabsq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqabsQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqabsQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vqabsq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqabsQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqabsQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vqabsq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqabss16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqabss16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vqabs_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqabss32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqabss32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vqabs_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqabss8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqabss8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vqabs_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqadds16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqadds16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqadds32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqadds32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqadds64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqadds64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqadds8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqadds8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqaddu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqaddu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlal_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlal_lanes16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlal_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlal_lanes32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlal_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlal_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlal_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlal_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlals16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlals16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlals32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlals32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlsl_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlsl_lanes16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlsl_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlsl_lanes32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlsl_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlsl_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16_t arg2_int16_t;
+-
+-  out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlsl_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlsl_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32_t arg2_int32_t;
+-
+-  out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlsls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlsls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-  int16x4_t arg2_int16x4_t;
+-
+-  out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vqdmlsls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmlsls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-  int32x2_t arg2_int32x2_t;
+-
+-  out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulh_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulh_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulh_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulh_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulh_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulh_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulh_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulh_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulhs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulhs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmull_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmull_lanes16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmull_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmull_lanes32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmull_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmull_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16_t arg1_int16_t;
+-
+-  out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmull_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmull_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32_t arg1_int32_t;
+-
+-  out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqdmulls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqdmulls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x8_t = vqmovn_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x4_t = vqmovn_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x2_t = vqmovn_s64 (arg0_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovnu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovnu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovnu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovnu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovuns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovuns16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovuns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovuns32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqmovuns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqmovuns64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqmovun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqnegQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqnegQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vqnegq_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqnegQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqnegQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vqnegq_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqnegQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqnegQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vqnegq_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqnegs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqnegs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vqneg_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqnegs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqnegs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vqneg_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqnegs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqnegs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vqneg_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshl_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshl_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshls16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshls32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshls64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshls64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshls8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqshlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshluQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshluQ_ns16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshluQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshluQ_ns32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshluQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshluQ_ns64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshluQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshluQ_ns8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlu_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu_ns16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlu_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu_ns32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlu_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu_ns64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshlu_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshlu_ns8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrn_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrn_ns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrn_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrn_ns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrn_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrn_ns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrn_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrn_nu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrn_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrn_nu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrn_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrn_nu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrun_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrun_ns16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrun_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrun_ns32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vqshrun_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqshrun_ns64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vqshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubs64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vqsubu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vqsubu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrecpeQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrecpeQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrecpeQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrecpeQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrecpef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrecpef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrecpe_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrecpeu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrecpeu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vrecpsQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrecpsQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vrecpsf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrecpsf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_p128 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_p16 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_p64 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_p8 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_s16 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_s32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_s64 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_s8 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_u16 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_u32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_u64 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQf32_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQf32_u8 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_float32x4_t = vreinterpretq_f32_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_f32 (void)
+-{
+-  poly128_t out_poly128_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_poly128_t = vreinterpretq_p128_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_p16 (void)
+-{
+-  poly128_t out_poly128_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly128_t = vreinterpretq_p128_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_p64 (void)
+-{
+-  poly128_t out_poly128_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_poly128_t = vreinterpretq_p128_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_p8 (void)
+-{
+-  poly128_t out_poly128_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly128_t = vreinterpretq_p128_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_s16 (void)
+-{
+-  poly128_t out_poly128_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_poly128_t = vreinterpretq_p128_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_s32 (void)
+-{
+-  poly128_t out_poly128_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_poly128_t = vreinterpretq_p128_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_s64 (void)
+-{
+-  poly128_t out_poly128_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_poly128_t = vreinterpretq_p128_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_s8 (void)
+-{
+-  poly128_t out_poly128_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_poly128_t = vreinterpretq_p128_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_u16 (void)
+-{
+-  poly128_t out_poly128_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_poly128_t = vreinterpretq_p128_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_u32 (void)
+-{
+-  poly128_t out_poly128_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_poly128_t = vreinterpretq_p128_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_u64 (void)
+-{
+-  poly128_t out_poly128_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_poly128_t = vreinterpretq_p128_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp128_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp128_u8 (void)
+-{
+-  poly128_t out_poly128_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_poly128_t = vreinterpretq_p128_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_f32 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_p128 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_p64 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_p8 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_s16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_s32 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_s64 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_s8 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_u16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_u32 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_u64 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp16_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp16_u8 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_poly16x8_t = vreinterpretq_p16_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_f32 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_p128 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_p16 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_p8 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_s16 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_s32 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_s64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_s8 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_u16 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_u32 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_u64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp64_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp64_u8 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_poly64x2_t = vreinterpretq_p64_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_f32 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_p128 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_p16 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_p64 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_s16 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_s32 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_s64 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_s8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_u16 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_u32 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_u64 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQp8_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQp8_u8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_poly8x16_t = vreinterpretq_p8_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_f32 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_p128 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_p16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_p64 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_p8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_s32 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_s64 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_s8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_u16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_u32 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_u64 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs16_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs16_u8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_int16x8_t = vreinterpretq_s16_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_f32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_p128 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_p16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_p64 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_p8 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_s16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_s64 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_s8 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_u16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_u32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_u64 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs32_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs32_u8 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_int32x4_t = vreinterpretq_s32_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_f32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_p128 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_p16 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_p64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_p8 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_s16 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_s32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_s8 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_u16 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_u32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_u64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs64_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs64_u8 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_int64x2_t = vreinterpretq_s64_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_f32 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_p128 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_p16 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_p64 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_p8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_s16 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_s32 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_s64 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_u16 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_u32 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_u64 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQs8_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQs8_u8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_int8x16_t = vreinterpretq_s8_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_f32 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_p128 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_p16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_p64 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_p8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_s16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_s32 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_s64 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_s8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_u32 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_u64 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu16_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu16_u8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint16x8_t = vreinterpretq_u16_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_f32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_p128 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_p16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_p64 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_p8 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_s16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_s32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_s64 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_s8 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_u16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_u64 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu32_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu32_u8 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint32x4_t = vreinterpretq_u32_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_f32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_p128 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_p16 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_p64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_p8 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_s16 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_s32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_s64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_s8 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_u16 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_u32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu64_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu64_u8 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint64x2_t = vreinterpretq_u64_u8 (arg0_uint8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_f32 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_f32 (arg0_float32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_p128' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_p128 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  poly128_t arg0_poly128_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_p128 (arg0_poly128_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_p16 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_p16 (arg0_poly16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_p64 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  poly64x2_t arg0_poly64x2_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_p64 (arg0_poly64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_p8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_p8 (arg0_poly8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_s16 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_s16 (arg0_int16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_s32 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_s32 (arg0_int32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_s64 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_s64 (arg0_int64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_s8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_s8 (arg0_int8x16_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_u16 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_u16 (arg0_uint16x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_u32 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_u32 (arg0_uint32x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretQu8_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretQu8_u64 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint8x16_t = vreinterpretq_u8_u64 (arg0_uint64x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_p16 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_float32x2_t = vreinterpret_f32_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_p64 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_float32x2_t = vreinterpret_f32_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_p8 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_float32x2_t = vreinterpret_f32_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_s16 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_float32x2_t = vreinterpret_f32_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_s32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_float32x2_t = vreinterpret_f32_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_s64 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_float32x2_t = vreinterpret_f32_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_s8 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_float32x2_t = vreinterpret_f32_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_u16 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_float32x2_t = vreinterpret_f32_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_u32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_float32x2_t = vreinterpret_f32_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_u64 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_float32x2_t = vreinterpret_f32_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretf32_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretf32_u8 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_float32x2_t = vreinterpret_f32_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_f32 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_p64 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_p8 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_s16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_s32 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_s64 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_s8 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_u16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_u32 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_u64 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp16_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp16_u8 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_poly16x4_t = vreinterpret_p16_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_f32 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_p16 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_p8 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_s16 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_s32 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_s64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_s8 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_u16 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_u32 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_u64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp64_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp64_u8 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_poly64x1_t = vreinterpret_p64_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_f32 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_p16 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_p64 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_s16 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_s32 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_s64 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_s8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_u16 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_u32 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_u64 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretp8_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretp8_u8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_poly8x8_t = vreinterpret_p8_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_f32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_int16x4_t = vreinterpret_s16_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_p16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_int16x4_t = vreinterpret_s16_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_p64 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_int16x4_t = vreinterpret_s16_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_p8 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_int16x4_t = vreinterpret_s16_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_s32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int16x4_t = vreinterpret_s16_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_s64 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int16x4_t = vreinterpret_s16_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_s8 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int16x4_t = vreinterpret_s16_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_u16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_int16x4_t = vreinterpret_s16_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_u32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_int16x4_t = vreinterpret_s16_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_u64 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_int16x4_t = vreinterpret_s16_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets16_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets16_u8 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_int16x4_t = vreinterpret_s16_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_f32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_int32x2_t = vreinterpret_s32_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_p16 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_int32x2_t = vreinterpret_s32_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_p64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_int32x2_t = vreinterpret_s32_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_p8 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_int32x2_t = vreinterpret_s32_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_s16 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int32x2_t = vreinterpret_s32_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_s64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int32x2_t = vreinterpret_s32_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_s8 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int32x2_t = vreinterpret_s32_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_u16 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_int32x2_t = vreinterpret_s32_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_u32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_int32x2_t = vreinterpret_s32_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_u64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_int32x2_t = vreinterpret_s32_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets32_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets32_u8 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_int32x2_t = vreinterpret_s32_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_f32 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_int64x1_t = vreinterpret_s64_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_p16 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_int64x1_t = vreinterpret_s64_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_p64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_int64x1_t = vreinterpret_s64_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_p8 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_int64x1_t = vreinterpret_s64_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_s16 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int64x1_t = vreinterpret_s64_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_s32 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int64x1_t = vreinterpret_s64_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_s8 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int64x1_t = vreinterpret_s64_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_u16 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_int64x1_t = vreinterpret_s64_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_u32 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_int64x1_t = vreinterpret_s64_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_u64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_int64x1_t = vreinterpret_s64_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets64_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets64_u8 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_int64x1_t = vreinterpret_s64_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_f32 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_int8x8_t = vreinterpret_s8_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_p16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_int8x8_t = vreinterpret_s8_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_p64 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_int8x8_t = vreinterpret_s8_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_p8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_int8x8_t = vreinterpret_s8_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_s16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int8x8_t = vreinterpret_s8_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_s32 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int8x8_t = vreinterpret_s8_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_s64 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int8x8_t = vreinterpret_s8_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_u16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_int8x8_t = vreinterpret_s8_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_u32 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_int8x8_t = vreinterpret_s8_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_u64 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_int8x8_t = vreinterpret_s8_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterprets8_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterprets8_u8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_int8x8_t = vreinterpret_s8_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_f32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_p16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_p64 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_p8 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_s16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_s32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_s64 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_s8 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_u32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_u64 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu16_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu16_u8 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint16x4_t = vreinterpret_u16_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_f32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_p16 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_p64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_p8 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_s16 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_s32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_s64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_s8 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_u16 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_u64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu32_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu32_u8 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint32x2_t = vreinterpret_u32_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_f32 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_p16 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_p64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_p8 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_s16 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_s32 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_s64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_s8 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_u16 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_u32 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu64_u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu64_u8 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint64x1_t = vreinterpret_u64_u8 (arg0_uint8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_f32 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_f32 (arg0_float32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_p16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_p16 (arg0_poly16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_p64 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  poly64x1_t arg0_poly64x1_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_p64 (arg0_poly64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_p8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_p8 (arg0_poly8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_s16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_s16 (arg0_int16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_s32 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_s32 (arg0_int32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_s64 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_s64 (arg0_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_s8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_s8 (arg0_int8x8_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_u16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_u16 (arg0_uint16x4_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_u32 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_u32 (arg0_uint32x2_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
++++ b/src//dev/null
+@@ -1,18 +0,0 @@
+-/* Test the `vreinterpretu8_u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vreinterpretu8_u64 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint8x8_t = vreinterpret_u8_u64 (arg0_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev16Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev16Qp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev16Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev16Qs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vrev16q_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev16Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev16Qu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev16p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev16p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev16s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev16s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vrev16_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev16u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev16u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32Qp16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32Qp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32Qs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vrev32q_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32Qs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vrev32q_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32Qu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32Qu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32p16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32s16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vrev32_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vrev32_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32u16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev32u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev32u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrev64q_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qp16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-
+-  out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qp8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-
+-  out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vrev64q_s16 (arg0_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vrev64q_s32 (arg0_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vrev64q_s8 (arg0_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64Qu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64f32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrev64_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64p16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-
+-  out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-
+-  out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64s16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vrev64_s16 (arg0_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64s32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vrev64_s32 (arg0_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vrev64_s8 (arg0_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64u16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64u32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrev64u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrev64u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndaf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndaf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrnda_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrinta\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndaqf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndaq_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndaqf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrndaq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrinta\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrnd_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintz\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndmf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndmf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrndm_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintm\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndmqf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndmq_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndmqf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrndmq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintm\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndnf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndnf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrndn_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintn\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndnqf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndnq_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndnqf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrndnq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintn\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndpf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndpf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrndp_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintp\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndpqf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndpq_f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndpqf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrndpq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintp\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrndqf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_v8_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_v8_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrndqf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrndq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrintz\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrsqrteQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrsqrteQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-
+-  out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrsqrteQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrsqrteQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrsqrtef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrsqrtef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-
+-  out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vrsqrteu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrsqrteu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vrsqrtsQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrsqrtsQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vrsqrtsf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vrsqrtsf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanef32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32_t arg0_float32_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanep16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16_t arg0_poly16_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanep8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8_t arg0_poly8_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanes16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16_t arg0_int16_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanes32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32_t arg0_int32_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanes64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64_t arg0_int64_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_lanes8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8_t arg0_int8_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_laneu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16_t arg0_uint16_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_laneu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32_t arg0_uint32_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_laneu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64_t arg0_uint64_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsetQ_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsetQ_laneu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8_t arg0_uint8_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanef32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32_t arg0_float32_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanep16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16_t arg0_poly16_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanep8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8_t arg0_poly8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanes16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16_t arg0_int16_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanes32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32_t arg0_int32_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vset_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanes64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64_t arg0_int64_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_lanes8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8_t arg0_int8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_laneu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16_t arg0_uint16_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_laneu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32_t arg0_uint32_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vset_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_laneu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64_t arg0_uint64_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vset_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vset_laneu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8_t arg0_uint8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshlQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshl_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshl_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshll_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshll_ns16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshll_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshll_ns32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshll_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshll_ns8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshll_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshll_nu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshll_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshll_nu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshll_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshll_nu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshls16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshls32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshls64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshls64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshls64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshls8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vshlu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshlu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-
+-  out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-
+-  out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-
+-  out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-
+-  out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-
+-  out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-
+-  out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-
+-  out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-
+-  out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-
+-  out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshr_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshr_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-
+-  out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrn_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrn_ns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-
+-  out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrn_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrn_ns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-
+-  out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrn_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrn_ns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-
+-  out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrn_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrn_nu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-
+-  out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrn_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrn_nu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-
+-  out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vshrn_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vshrn_nu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-
+-  out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_np16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_np64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_np64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64x2_t arg0_poly64x2_t;
+-  poly64x2_t arg1_poly64x2_t;
+-
+-  out_poly64x2_t = vsliq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_np8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsliQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsliQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_np16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_np64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_np64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x1_t arg0_poly64x1_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  out_poly64x1_t = vsli_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_np8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsli_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsli_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsraQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsraQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsra_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsra_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_np16 (void)
+-{
+-  poly16x8_t out_poly16x8_t;
+-  poly16x8_t arg0_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_np64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_np64 (void)
+-{
+-  poly64x2_t out_poly64x2_t;
+-  poly64x2_t arg0_poly64x2_t;
+-  poly64x2_t arg1_poly64x2_t;
+-
+-  out_poly64x2_t = vsriq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_np8 (void)
+-{
+-  poly8x16_t out_poly8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_ns16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_ns32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_ns64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_ns8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_nu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_nu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_nu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsriQ_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsriQ_nu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_np16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_np16 (void)
+-{
+-  poly16x4_t out_poly16x4_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_np64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_np64 (void)
+-{
+-  poly64x1_t out_poly64x1_t;
+-  poly64x1_t arg0_poly64x1_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  out_poly64x1_t = vsri_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_np8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_np8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_ns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_ns16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_ns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_ns32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_ns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_ns64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_ns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_ns8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_nu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_nu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_nu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_nu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_nu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_nu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsri_nu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsri_nu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanep64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x2_t arg1_poly64x2_t;
+-
+-  vst1q_lane_p64 (arg0_poly64_t, arg1_poly64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanep8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanes64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_lanes8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c
++++ b/src//dev/null
+@@ -1,25 +0,0 @@
+-/* Test the `vst1Q_laneu64' ARM Neon intrinsic.  */
+-
+-/* Detect ICE in the case of unaligned memory address.  */
+-
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-unsigned char dummy_store[1000];
+-
+-void
+-foo (char* addr)
+-{
+-  uint8x16_t vdata = vld1q_u8 (addr);
+-  vst1q_lane_u64 ((uint64_t*) &dummy_store, vreinterpretq_u64_u8 (vdata), 0);
+-}
+-
+-uint64_t
+-bar (uint64x2_t vdata)
+-{
+-  vdata = vld1q_lane_u64 ((uint64_t*) &dummy_store, vdata, 0);
+-  return vgetq_lane_u64 (vdata, 0);
+-}
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_laneu64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Q_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Q_laneu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qf32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qp16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qp64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qp64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x2_t arg1_poly64x2_t;
+-
+-  vst1q_p64 (arg0_poly64_t, arg1_poly64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qp8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qs16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qs32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qs64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qs8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qu64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1Qu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanep64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanep64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  vst1_lane_p64 (arg0_poly64_t, arg1_poly64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanep8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanes64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanes64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_lanes8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_laneu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_laneu64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1_laneu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1f32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  vst1_f32 (arg0_float32_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1p16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1p64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1p64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x1_t arg1_poly64x1_t;
+-
+-  vst1_p64 (arg0_poly64_t, arg1_poly64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1p8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1s16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  vst1_s16 (arg0_int16_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1s32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  vst1_s32 (arg0_int32_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1s64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  vst1_s64 (arg0_int64_t, arg1_int64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1s8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  vst1_s8 (arg0_int8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1u16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1u32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1u64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst1u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst1u8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Q_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4x2_t arg1_float32x4x2_t;
+-
+-  vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Q_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8x2_t arg1_poly16x8x2_t;
+-
+-  vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Q_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8x2_t arg1_int16x8x2_t;
+-
+-  vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Q_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4x2_t arg1_int32x4x2_t;
+-
+-  vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Q_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8x2_t arg1_uint16x8x2_t;
+-
+-  vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Q_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4x2_t arg1_uint32x4x2_t;
+-
+-  vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qf32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4x2_t arg1_float32x4x2_t;
+-
+-  vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qp16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8x2_t arg1_poly16x8x2_t;
+-
+-  vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qp8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x16x2_t arg1_poly8x16x2_t;
+-
+-  vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qs16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8x2_t arg1_int16x8x2_t;
+-
+-  vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qs32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4x2_t arg1_int32x4x2_t;
+-
+-  vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qs8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x16x2_t arg1_int8x16x2_t;
+-
+-  vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8x2_t arg1_uint16x8x2_t;
+-
+-  vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4x2_t arg1_uint32x4x2_t;
+-
+-  vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst2Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2Qu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x16x2_t arg1_uint8x16x2_t;
+-
+-  vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2x2_t arg1_float32x2x2_t;
+-
+-  vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4x2_t arg1_poly16x4x2_t;
+-
+-  vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_lanep8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8x2_t arg1_poly8x8x2_t;
+-
+-  vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4x2_t arg1_int16x4x2_t;
+-
+-  vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2x2_t arg1_int32x2x2_t;
+-
+-  vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_lanes8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8x2_t arg1_int8x8x2_t;
+-
+-  vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4x2_t arg1_uint16x4x2_t;
+-
+-  vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2x2_t arg1_uint32x2x2_t;
+-
+-  vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2_laneu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8x2_t arg1_uint8x8x2_t;
+-
+-  vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2f32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2x2_t arg1_float32x2x2_t;
+-
+-  vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2p16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4x2_t arg1_poly16x4x2_t;
+-
+-  vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2p64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2p64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x1x2_t arg1_poly64x1x2_t;
+-
+-  vst2_p64 (arg0_poly64_t, arg1_poly64x1x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2p8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8x2_t arg1_poly8x8x2_t;
+-
+-  vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2s16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4x2_t arg1_int16x4x2_t;
+-
+-  vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2s32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2x2_t arg1_int32x2x2_t;
+-
+-  vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2s64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x1x2_t arg1_int64x1x2_t;
+-
+-  vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2s8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8x2_t arg1_int8x8x2_t;
+-
+-  vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2u16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4x2_t arg1_uint16x4x2_t;
+-
+-  vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2u32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2x2_t arg1_uint32x2x2_t;
+-
+-  vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2u64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x1x2_t arg1_uint64x1x2_t;
+-
+-  vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst2u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst2u8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8x2_t arg1_uint8x8x2_t;
+-
+-  vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Q_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4x3_t arg1_float32x4x3_t;
+-
+-  vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Q_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8x3_t arg1_poly16x8x3_t;
+-
+-  vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Q_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8x3_t arg1_int16x8x3_t;
+-
+-  vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Q_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4x3_t arg1_int32x4x3_t;
+-
+-  vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Q_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8x3_t arg1_uint16x8x3_t;
+-
+-  vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Q_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4x3_t arg1_uint32x4x3_t;
+-
+-  vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qf32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4x3_t arg1_float32x4x3_t;
+-
+-  vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qp16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8x3_t arg1_poly16x8x3_t;
+-
+-  vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qp8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x16x3_t arg1_poly8x16x3_t;
+-
+-  vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qs16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8x3_t arg1_int16x8x3_t;
+-
+-  vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qs32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4x3_t arg1_int32x4x3_t;
+-
+-  vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qs8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x16x3_t arg1_int8x16x3_t;
+-
+-  vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8x3_t arg1_uint16x8x3_t;
+-
+-  vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4x3_t arg1_uint32x4x3_t;
+-
+-  vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst3Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3Qu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x16x3_t arg1_uint8x16x3_t;
+-
+-  vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2x3_t arg1_float32x2x3_t;
+-
+-  vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4x3_t arg1_poly16x4x3_t;
+-
+-  vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_lanep8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8x3_t arg1_poly8x8x3_t;
+-
+-  vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4x3_t arg1_int16x4x3_t;
+-
+-  vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2x3_t arg1_int32x2x3_t;
+-
+-  vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_lanes8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8x3_t arg1_int8x8x3_t;
+-
+-  vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4x3_t arg1_uint16x4x3_t;
+-
+-  vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2x3_t arg1_uint32x2x3_t;
+-
+-  vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3_laneu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8x3_t arg1_uint8x8x3_t;
+-
+-  vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3f32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2x3_t arg1_float32x2x3_t;
+-
+-  vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3p16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4x3_t arg1_poly16x4x3_t;
+-
+-  vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3p64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3p64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x1x3_t arg1_poly64x1x3_t;
+-
+-  vst3_p64 (arg0_poly64_t, arg1_poly64x1x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3p8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8x3_t arg1_poly8x8x3_t;
+-
+-  vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3s16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4x3_t arg1_int16x4x3_t;
+-
+-  vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3s32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2x3_t arg1_int32x2x3_t;
+-
+-  vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3s64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x1x3_t arg1_int64x1x3_t;
+-
+-  vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3s8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8x3_t arg1_int8x8x3_t;
+-
+-  vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3u16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4x3_t arg1_uint16x4x3_t;
+-
+-  vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3u32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2x3_t arg1_uint32x2x3_t;
+-
+-  vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3u64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x1x3_t arg1_uint64x1x3_t;
+-
+-  vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst3u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst3u8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8x3_t arg1_uint8x8x3_t;
+-
+-  vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4Q_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Q_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4x4_t arg1_float32x4x4_t;
+-
+-  vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4Q_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Q_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8x4_t arg1_poly16x8x4_t;
+-
+-  vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4Q_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Q_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8x4_t arg1_int16x8x4_t;
+-
+-  vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4Q_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Q_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4x4_t arg1_int32x4x4_t;
+-
+-  vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4Q_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Q_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8x4_t arg1_uint16x8x4_t;
+-
+-  vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4Q_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Q_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4x4_t arg1_uint32x4x4_t;
+-
+-  vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qf32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x4x4_t arg1_float32x4x4_t;
+-
+-  vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qp16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x8x4_t arg1_poly16x8x4_t;
+-
+-  vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qp8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x16x4_t arg1_poly8x16x4_t;
+-
+-  vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qs16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x8x4_t arg1_int16x8x4_t;
+-
+-  vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qs32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x4x4_t arg1_int32x4x4_t;
+-
+-  vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qs8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x16x4_t arg1_int8x16x4_t;
+-
+-  vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x8x4_t arg1_uint16x8x4_t;
+-
+-  vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x4x4_t arg1_uint32x4x4_t;
+-
+-  vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vst4Qu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4Qu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x16x4_t arg1_uint8x16x4_t;
+-
+-  vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_lanef32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_lanef32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2x4_t arg1_float32x2x4_t;
+-
+-  vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_lanep16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_lanep16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4x4_t arg1_poly16x4x4_t;
+-
+-  vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_lanep8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_lanep8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8x4_t arg1_poly8x8x4_t;
+-
+-  vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_lanes16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_lanes16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4x4_t arg1_int16x4x4_t;
+-
+-  vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_lanes32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_lanes32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2x4_t arg1_int32x2x4_t;
+-
+-  vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_lanes8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_lanes8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8x4_t arg1_int8x8x4_t;
+-
+-  vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_laneu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_laneu16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4x4_t arg1_uint16x4x4_t;
+-
+-  vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_laneu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_laneu32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2x4_t arg1_uint32x2x4_t;
+-
+-  vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4_laneu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4_laneu8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8x4_t arg1_uint8x8x4_t;
+-
+-  vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4f32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4f32 (void)
+-{
+-  float32_t *arg0_float32_t;
+-  float32x2x4_t arg1_float32x2x4_t;
+-
+-  vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4p16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4p16 (void)
+-{
+-  poly16_t *arg0_poly16_t;
+-  poly16x4x4_t arg1_poly16x4x4_t;
+-
+-  vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4p64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4p64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_crypto_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_crypto } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4p64 (void)
+-{
+-  poly64_t *arg0_poly64_t;
+-  poly64x1x4_t arg1_poly64x1x4_t;
+-
+-  vst4_p64 (arg0_poly64_t, arg1_poly64x1x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4p8 (void)
+-{
+-  poly8_t *arg0_poly8_t;
+-  poly8x8x4_t arg1_poly8x8x4_t;
+-
+-  vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4s16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4s16 (void)
+-{
+-  int16_t *arg0_int16_t;
+-  int16x4x4_t arg1_int16x4x4_t;
+-
+-  vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4s32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4s32 (void)
+-{
+-  int32_t *arg0_int32_t;
+-  int32x2x4_t arg1_int32x2x4_t;
+-
+-  vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4s64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4s64 (void)
+-{
+-  int64_t *arg0_int64_t;
+-  int64x1x4_t arg1_int64x1x4_t;
+-
+-  vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4s8 (void)
+-{
+-  int8_t *arg0_int8_t;
+-  int8x8x4_t arg1_int8x8x4_t;
+-
+-  vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4u16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4u16 (void)
+-{
+-  uint16_t *arg0_uint16_t;
+-  uint16x4x4_t arg1_uint16x4x4_t;
+-
+-  vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4u32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4u32 (void)
+-{
+-  uint32_t *arg0_uint32_t;
+-  uint32x2x4_t arg1_uint32x2x4_t;
+-
+-  vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4u64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4u64 (void)
+-{
+-  uint64_t *arg0_uint64_t;
+-  uint64x1x4_t arg1_uint64x1x4_t;
+-
+-  vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vst4u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vst4u8 (void)
+-{
+-  uint8_t *arg0_uint8_t;
+-  uint8x8x4_t arg1_uint8x8x4_t;
+-
+-  vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQf32 (void)
+-{
+-  float32x4_t out_float32x4_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQs16 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQs32 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQs64 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQs8 (void)
+-{
+-  int8x16_t out_int8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQu64 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubf32 (void)
+-{
+-  float32x2_t out_float32x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubhns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubhns16 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubhns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubhns32 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubhns64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubhns64 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int64x2_t arg1_int64x2_t;
+-
+-  out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubhnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubhnu16 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubhnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubhnu32 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubhnu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubhnu64 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint64x2_t arg1_uint64x2_t;
+-
+-  out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubls16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubls16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubls32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubls32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubls8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubls8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsublu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsublu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsublu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsublu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsublu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsublu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubs16 (void)
+-{
+-  int16x4_t out_int16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubs32 (void)
+-{
+-  int32x2_t out_int32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vsubs64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubs64 (void)
+-{
+-  int64x1_t out_int64x1_t;
+-  int64x1_t arg0_int64x1_t;
+-  int64x1_t arg1_int64x1_t;
+-
+-  out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubs8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
++++ b/src//dev/null
+@@ -1,19 +0,0 @@
+-/* Test the `vsubu64' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubu64 (void)
+-{
+-  uint64x1_t out_uint64x1_t;
+-  uint64x1_t arg0_uint64x1_t;
+-  uint64x1_t arg1_uint64x1_t;
+-
+-  out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+-}
+-
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubws16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubws16 (void)
+-{
+-  int32x4_t out_int32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubws32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubws32 (void)
+-{
+-  int64x2_t out_int64x2_t;
+-  int64x2_t arg0_int64x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubws8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubws8 (void)
+-{
+-  int16x8_t out_int16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubwu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubwu16 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubwu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubwu32 (void)
+-{
+-  uint64x2_t out_uint64x2_t;
+-  uint64x2_t arg0_uint64x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vsubwu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vsubwu8 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vsubw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl1p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl1p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl1s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl1s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl1u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl1u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl2p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl2p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8x2_t arg0_poly8x8x2_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl2s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl2s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8x2_t arg0_int8x8x2_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl2u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl2u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8x2_t arg0_uint8x8x2_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl3p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl3p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8x3_t arg0_poly8x8x3_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl3s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl3s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8x3_t arg0_int8x8x3_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl3u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl3u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8x3_t arg0_uint8x8x3_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl4p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl4p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8x4_t arg0_poly8x8x4_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl4s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl4s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8x4_t arg0_int8x8x4_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtbl4u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbl4u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8x4_t arg0_uint8x8x4_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx1p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx1p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx1s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx1s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx1u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx1u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx2p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx2p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8x2_t arg1_poly8x8x2_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx2s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx2s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8x2_t arg1_int8x8x2_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx2u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx2u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8x2_t arg1_uint8x8x2_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx3p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx3p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8x3_t arg1_poly8x8x3_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx3s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx3s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8x3_t arg1_int8x8x3_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx3u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx3u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8x3_t arg1_uint8x8x3_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx4p8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx4p8 (void)
+-{
+-  poly8x8_t out_poly8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8x4_t arg1_poly8x8x4_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx4s8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx4s8 (void)
+-{
+-  int8x8_t out_int8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8x4_t arg1_int8x8x4_t;
+-  int8x8_t arg2_int8x8_t;
+-
+-  out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
++++ b/src//dev/null
+@@ -1,21 +0,0 @@
+-/* Test the `vtbx4u8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtbx4u8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8x4_t arg1_uint8x8x4_t;
+-  uint8x8_t arg2_uint8x8_t;
+-
+-  out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQf32 (void)
+-{
+-  float32x4x2_t out_float32x4x2_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQp16 (void)
+-{
+-  poly16x8x2_t out_poly16x8x2_t;
+-  poly16x8_t arg0_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQp8 (void)
+-{
+-  poly8x16x2_t out_poly8x16x2_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQs16 (void)
+-{
+-  int16x8x2_t out_int16x8x2_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQs32 (void)
+-{
+-  int32x4x2_t out_int32x4x2_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQs8 (void)
+-{
+-  int8x16x2_t out_int8x16x2_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQu16 (void)
+-{
+-  uint16x8x2_t out_uint16x8x2_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQu32 (void)
+-{
+-  uint32x4x2_t out_uint32x4x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnQu8 (void)
+-{
+-  uint8x16x2_t out_uint8x16x2_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnf32 (void)
+-{
+-  float32x2x2_t out_float32x2x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnp16 (void)
+-{
+-  poly16x4x2_t out_poly16x4x2_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnp8 (void)
+-{
+-  poly8x8x2_t out_poly8x8x2_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrns16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrns16 (void)
+-{
+-  int16x4x2_t out_int16x4x2_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrns32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrns32 (void)
+-{
+-  int32x2x2_t out_int32x2x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrns8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrns8 (void)
+-{
+-  int8x8x2_t out_int8x8x2_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnu16 (void)
+-{
+-  uint16x4x2_t out_uint16x4x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnu32 (void)
+-{
+-  uint32x2x2_t out_uint32x2x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtrnu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtrnu8 (void)
+-{
+-  uint8x8x2_t out_uint8x8x2_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQp8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQs16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQs32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQs8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQu16 (void)
+-{
+-  uint16x8_t out_uint16x8_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQu32 (void)
+-{
+-  uint32x4_t out_uint32x4_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstQu8 (void)
+-{
+-  uint8x16_t out_uint8x16_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstp8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtsts16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtsts16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtsts32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtsts32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtsts8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtsts8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstu16 (void)
+-{
+-  uint16x4_t out_uint16x4_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstu32 (void)
+-{
+-  uint32x2_t out_uint32x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vtstu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vtstu8 (void)
+-{
+-  uint8x8_t out_uint8x8_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQf32 (void)
+-{
+-  float32x4x2_t out_float32x4x2_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQp16 (void)
+-{
+-  poly16x8x2_t out_poly16x8x2_t;
+-  poly16x8_t arg0_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQp8 (void)
+-{
+-  poly8x16x2_t out_poly8x16x2_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQs16 (void)
+-{
+-  int16x8x2_t out_int16x8x2_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQs32 (void)
+-{
+-  int32x4x2_t out_int32x4x2_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQs8 (void)
+-{
+-  int8x16x2_t out_int8x16x2_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQu16 (void)
+-{
+-  uint16x8x2_t out_uint16x8x2_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQu32 (void)
+-{
+-  uint32x4x2_t out_uint32x4x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpQu8 (void)
+-{
+-  uint8x16x2_t out_uint8x16x2_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpf32 (void)
+-{
+-  float32x2x2_t out_float32x2x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpp16 (void)
+-{
+-  poly16x4x2_t out_poly16x4x2_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpp8 (void)
+-{
+-  poly8x8x2_t out_poly8x8x2_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzps16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzps16 (void)
+-{
+-  int16x4x2_t out_int16x4x2_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzps32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzps32 (void)
+-{
+-  int32x2x2_t out_int32x2x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzps8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzps8 (void)
+-{
+-  int8x8x2_t out_int8x8x2_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpu16 (void)
+-{
+-  uint16x4x2_t out_uint16x4x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpu32 (void)
+-{
+-  uint32x2x2_t out_uint32x2x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vuzpu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vuzpu8 (void)
+-{
+-  uint8x8x2_t out_uint8x8x2_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQf32 (void)
+-{
+-  float32x4x2_t out_float32x4x2_t;
+-  float32x4_t arg0_float32x4_t;
+-  float32x4_t arg1_float32x4_t;
+-
+-  out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQp16 (void)
+-{
+-  poly16x8x2_t out_poly16x8x2_t;
+-  poly16x8_t arg0_poly16x8_t;
+-  poly16x8_t arg1_poly16x8_t;
+-
+-  out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQp8 (void)
+-{
+-  poly8x16x2_t out_poly8x16x2_t;
+-  poly8x16_t arg0_poly8x16_t;
+-  poly8x16_t arg1_poly8x16_t;
+-
+-  out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQs16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQs16 (void)
+-{
+-  int16x8x2_t out_int16x8x2_t;
+-  int16x8_t arg0_int16x8_t;
+-  int16x8_t arg1_int16x8_t;
+-
+-  out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQs32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQs32 (void)
+-{
+-  int32x4x2_t out_int32x4x2_t;
+-  int32x4_t arg0_int32x4_t;
+-  int32x4_t arg1_int32x4_t;
+-
+-  out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQs8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQs8 (void)
+-{
+-  int8x16x2_t out_int8x16x2_t;
+-  int8x16_t arg0_int8x16_t;
+-  int8x16_t arg1_int8x16_t;
+-
+-  out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQu16 (void)
+-{
+-  uint16x8x2_t out_uint16x8x2_t;
+-  uint16x8_t arg0_uint16x8_t;
+-  uint16x8_t arg1_uint16x8_t;
+-
+-  out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQu32 (void)
+-{
+-  uint32x4x2_t out_uint32x4x2_t;
+-  uint32x4_t arg0_uint32x4_t;
+-  uint32x4_t arg1_uint32x4_t;
+-
+-  out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipQu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipQu8 (void)
+-{
+-  uint8x16x2_t out_uint8x16x2_t;
+-  uint8x16_t arg0_uint8x16_t;
+-  uint8x16_t arg1_uint8x16_t;
+-
+-  out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipf32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipf32 (void)
+-{
+-  float32x2x2_t out_float32x2x2_t;
+-  float32x2_t arg0_float32x2_t;
+-  float32x2_t arg1_float32x2_t;
+-
+-  out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipp16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipp16 (void)
+-{
+-  poly16x4x2_t out_poly16x4x2_t;
+-  poly16x4_t arg0_poly16x4_t;
+-  poly16x4_t arg1_poly16x4_t;
+-
+-  out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipp8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipp8 (void)
+-{
+-  poly8x8x2_t out_poly8x8x2_t;
+-  poly8x8_t arg0_poly8x8_t;
+-  poly8x8_t arg1_poly8x8_t;
+-
+-  out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzips16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzips16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzips16 (void)
+-{
+-  int16x4x2_t out_int16x4x2_t;
+-  int16x4_t arg0_int16x4_t;
+-  int16x4_t arg1_int16x4_t;
+-
+-  out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzips32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzips32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzips32 (void)
+-{
+-  int32x2x2_t out_int32x2x2_t;
+-  int32x2_t arg0_int32x2_t;
+-  int32x2_t arg1_int32x2_t;
+-
+-  out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzips8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzips8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzips8 (void)
+-{
+-  int8x8x2_t out_int8x8x2_t;
+-  int8x8_t arg0_int8x8_t;
+-  int8x8_t arg1_int8x8_t;
+-
+-  out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipu16' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipu16 (void)
+-{
+-  uint16x4x2_t out_uint16x4x2_t;
+-  uint16x4_t arg0_uint16x4_t;
+-  uint16x4_t arg1_uint16x4_t;
+-
+-  out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipu32' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipu32 (void)
+-{
+-  uint32x2x2_t out_uint32x2x2_t;
+-  uint32x2_t arg0_uint32x2_t;
+-  uint32x2_t arg1_uint32x2_t;
+-
+-  out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+-}
+-
+-/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
++++ b/src//dev/null
+@@ -1,20 +0,0 @@
+-/* Test the `vzipu8' ARM Neon intrinsic.  */
+-/* This file was autogenerated by neon-testgen.  */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -O0" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include "arm_neon.h"
+-
+-void test_vzipu8 (void)
+-{
+-  uint8x8x2_t out_uint8x8x2_t;
+-  uint8x8_t arg0_uint8x8_t;
+-  uint8x8_t arg1_uint8x8_t;
+-
+-  out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+-}
+-
+-/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/optional_thumb-1.c
+@@ -0,0 +1,7 @@
++/* { dg-do compile { target { ! default_mode } } } */
++/* { dg-skip-if "-marm/-mthumb/-march/-mcpu given" { *-*-* } { "-marm" "-mthumb" "-march=*" "-mcpu=*" } } */
++/* { dg-options "-march=armv6-m" } */
++
++/* Check that -mthumb is not needed when compiling for a Thumb-only target.  */
++
++int foo;
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/optional_thumb-2.c
+@@ -0,0 +1,7 @@
++/* { dg-do compile { target { ! default_mode } } } */
++/* { dg-skip-if "-marm/-mthumb/-march/-mcpu given" { *-*-* } { "-marm" "-mthumb" "-march=*" "-mcpu=*" } } */
++/* { dg-options "-mcpu=cortex-m4" } */
++
++/* Check that -mthumb is not needed when compiling for a Thumb-only target.  */
++
++int foo;
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/optional_thumb-3.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_cortex_m } */
++/* { dg-skip-if "-mthumb given" { *-*-* } { "-mthumb" } } */
++/* { dg-options "-marm" } */
++/* { dg-error "target CPU does not support ARM mode" "missing error with -marm on Thumb-only targets" { target *-*-* } 0 } */
++
++/* Check that -marm gives an error when compiling for a Thumb-only target.  */
++
++int foo;
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/polytypes.c
+@@ -0,0 +1,48 @@
++/* Check that NEON polynomial vector types are suitably incompatible with
++   integer vector types of the same layout.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++void s64_8 (int8x8_t a) {}
++void u64_8 (uint8x8_t a) {}
++void p64_8 (poly8x8_t a) {}
++void s64_16 (int16x4_t a) {}
++void u64_16 (uint16x4_t a) {}
++void p64_16 (poly16x4_t a) {}
++
++void s128_8 (int8x16_t a) {}
++void u128_8 (uint8x16_t a) {}
++void p128_8 (poly8x16_t a) {}
++void s128_16 (int16x8_t a) {}
++void u128_16 (uint16x8_t a) {}
++void p128_16 (poly16x8_t a) {}
++
++void foo ()
++{
++  poly8x8_t v64_8;
++  poly16x4_t v64_16;
++  poly8x16_t v128_8;
++  poly16x8_t v128_16;
++
++  s64_8 (v64_8); /* { dg-message "use -flax-vector-conversions" } */
++  /* { dg-error "incompatible type for argument 1 of 's64_8'" "" { target *-*-* } 31 } */
++  u64_8 (v64_8); /* { dg-error "incompatible type for argument 1 of 'u64_8'" } */
++  p64_8 (v64_8);
++
++  s64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 's64_16'" } */
++  u64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 'u64_16'" } */
++  p64_16 (v64_16);
++
++  s128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 's128_8'" } */
++  u128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 'u128_8'" } */
++  p128_8 (v128_8);
++
++  s128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 's128_16'" } */
++  u128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 'u128_16'" } */
++  p128_16 (v128_16);
++}
++/* { dg-message "note: expected '\[^'\n\]*' but argument is of type '\[^'\n\]*'" "note: expected" { target *-*-* } 0 } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/pr37780_1.c
+@@ -0,0 +1,48 @@
++/* Test that we can remove the conditional move due to CLZ
++   being defined at zero.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v6t2_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v6t2 } */
++
++int
++fooctz (int i)
++{
++  return (i == 0) ? 32 : __builtin_ctz (i);
++}
++
++int
++fooctz2 (int i)
++{
++  return (i != 0) ? __builtin_ctz (i) : 32;
++}
++
++unsigned int
++fooctz3 (unsigned int i)
++{
++  return (i > 0) ?  __builtin_ctz (i) : 32;
++}
++
++/* { dg-final { scan-assembler-times "rbit\t*" 3 } } */
++
++int
++fooclz (int i)
++{
++  return (i == 0) ? 32 : __builtin_clz (i);
++}
++
++int
++fooclz2 (int i)
++{
++  return (i != 0) ? __builtin_clz (i) : 32;
++}
++
++unsigned int
++fooclz3 (unsigned int i)
++{
++  return (i > 0) ? __builtin_clz (i) : 32;
++}
++
++/* { dg-final { scan-assembler-times "clz\t" 6 } } */
++/* { dg-final { scan-assembler-not "cmp\t.*0" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/pr42574.c
++++ b/src/gcc/testsuite/gcc.target/arm/pr42574.c
+@@ -1,5 +1,5 @@
++/* { dg-do compile { target { arm_thumb1_ok && { ! arm_thumb1_movt_ok } } } } */
+ /* { dg-options "-mthumb -Os -fpic" }  */
+-/* { dg-require-effective-target arm_thumb1_ok } */
+ /* { dg-require-effective-target fpic } */
+ /* Make sure the address of glob.c is calculated only once and using
+    a logical shift for the offset (200<<1).  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/pr51534.c
+@@ -0,0 +1,83 @@
++/* Test the vector comparison intrinsics when comparing to immediate zero.
++   */
++
++/* { dg-do assemble } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-save-temps -mfloat-abi=hard -O3" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++#define GEN_TEST(T, D, C, R) \
++  R test_##C##_##T (T a) { return C (a, D (0)); }
++
++#define GEN_DOUBLE_TESTS(S, T, C) \
++  GEN_TEST (T, vdup_n_s##S, C##_s##S, u##T) \
++  GEN_TEST (u##T, vdup_n_u##S, C##_u##S, u##T) 
++
++#define GEN_QUAD_TESTS(S, T, C) \
++  GEN_TEST (T, vdupq_n_s##S, C##q_s##S, u##T) \
++  GEN_TEST (u##T, vdupq_n_u##S, C##q_u##S, u##T) 
++
++#define GEN_COND_TESTS(C) \
++  GEN_DOUBLE_TESTS (8, int8x8_t, C) \
++  GEN_DOUBLE_TESTS (16, int16x4_t, C) \
++  GEN_DOUBLE_TESTS (32, int32x2_t, C) \
++  GEN_QUAD_TESTS (8, int8x16_t, C) \
++  GEN_QUAD_TESTS (16, int16x8_t, C) \
++  GEN_QUAD_TESTS (32, int32x4_t, C)
++
++GEN_COND_TESTS(vcgt)
++GEN_COND_TESTS(vcge)
++GEN_COND_TESTS(vclt)
++GEN_COND_TESTS(vcle)
++GEN_COND_TESTS(vceq)
++
++/* Scan for expected outputs.  */
++/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vclt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
++
++/* And ensure we don't have unexpected output too.  */
++/* { dg-final { scan-assembler-not "vc\[gl\]\[te\]\.u\[0-9\]+\[ 	\]+\[qQdD\]\[0-9\]+, \[qQdD\]\[0-9\]+, #0" } } */
++
++/* Tidy up.  */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/pr79145.c
+@@ -0,0 +1,16 @@
++/* { dg-do compile } */
++/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */
++/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */
++/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */
++/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */
++/* { dg-require-effective-target arm32 } */
++/* { dg-require-effective-target arm_iwmmxt_ok } */
++/* { dg-options "-mcpu=iwmmxt" } */
++
++int
++main (void)
++{
++  volatile long long t1;
++  t1 ^= 0x55;
++  return 0;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/pure-code/ffunction-sections.c
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-skip-if "" { *-*-* } { "-fpic" "-fPIC" } { "" } } */
++/* { dg-options "-ffunction-sections -mpure-code" } */
++#include <limits.h>
++
++char * foo (void)
++{
++  return "foo";
++}
++
++unsigned int bar (unsigned int b)
++{
++  return UINT_MAX - b;
++}
++
++/* { dg-final { scan-assembler {\.section\t\.text\.foo[^\n]*\"0x20000006\"} } } */
++/* { dg-final { scan-assembler {\.section\t\.text\.bar[^\n]*\"0x20000006\"} } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/pure-code/no-casesi.c
+@@ -0,0 +1,29 @@
++/* { dg-do compile } */
++/* { dg-options "-mpure-code" } */
++/* { dg-skip-if "" { *-*-* } { "-g" "-fpic" "-fPIC" } { "" } } */
++
++extern int foo (void);
++extern int bar (void);
++extern int baz (void);
++extern int fooz (void);
++
++int caller (unsigned int reg_type)
++{
++  switch (reg_type)
++    {
++    case 0x80000000:
++      return (int) foo ();
++
++    case 0x80000003:
++      return (int) bar ();
++
++    case 0x80000001:
++      return (int) baz ();
++
++    case 0x80000004:
++      return (int) fooz ();
++    }
++}
++
++/* { dg-final { scan-assembler-not "\\.(float|l\\?double|\d?byte|short|int|long|quad|word)\\s+\[^.\]" } } */
++/* { dg-final { scan-assembler "text,\"0x20000006\"" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/pure-code/no-literal-pool.c
+@@ -0,0 +1,68 @@
++/* { dg-do compile } */
++/* { dg-options "-mpure-code" } */
++/* { dg-skip-if "" { *-*-* } { "-g" "-fpic" "-fPIC" } { "" } } */
++
++float sf;
++double df;
++long long l;
++static char *p = "Hello World";
++
++float
++testsf (float *p)
++{
++  if (*p > 1.1234f)
++    return 2.1234f;
++  else
++    return 3.1234f;
++}
++
++double
++testdf (double *p)
++{
++  if (*p > 4.1234)
++    return 2.1234;
++  else
++    return 3.1234;
++}
++
++long long
++testll (long long *p)
++{
++  if (*p > 0x123456789ABCDEFll)
++    return 0x111111111ll;
++  else
++    return 0x222222222ll;
++}
++
++char *
++testchar ()
++{
++  return p + 4;
++}
++
++int
++foo (int a, int b)
++{
++  int i;
++  volatile int *labelref = &&label1;
++
++  if (a > b)
++    {
++      while (i < b)
++	{
++	  a += *labelref;
++	  i += 1;
++	}
++      goto *labelref;
++    }
++  else
++    b = b + 3;
++
++  a = a * b;
++
++label1:
++  return a + b;
++}
++
++/* { dg-final { scan-assembler-not "\\.(float|l\\?double|\d?byte|short|int|long|quad|word)\\s+\[^.\]" } } */
++/* { dg-final { scan-assembler "text,\"0x20000006\"" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp
+@@ -0,0 +1,59 @@
++#   Copyright (C) 1997-2016 Free Software Foundation, Inc.
++
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with GCC; see the file COPYING3.  If not see
++# <http://www.gnu.org/licenses/>.
++
++# GCC testsuite for ARM's -mpure-code option, using the `dg.exp' driver.
++
++# Load support procs.
++load_lib gcc-dg.exp
++
++# If a testcase doesn't have special options, use these.
++global DEFAULT_CFLAGS
++if ![info exists DEFAULT_CFLAGS] then {
++    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
++}
++
++# The -mpure-code option is only available for M-profile targets that support
++# the MOVT instruction.
++if {([check_effective_target_arm_thumb2_ok]
++     || [check_effective_target_arm_thumb1_movt_ok])
++    && [check_effective_target_arm_cortex_m]} then {
++# Initialize `dg'.
++dg-init
++
++set saved-dg-do-what-default ${dg-do-what-default}
++set dg-do-what-default "assemble"
++
++set saved-lto_torture_options ${LTO_TORTURE_OPTIONS}
++
++# Add -ffat-lto-objects option to all LTO options such that we can do assembly
++# scans.
++proc add_fat_objects { list } {
++    set res {}
++    foreach el $list {set res [lappend res [concat $el " -ffat-lto-objects"]]}
++    return $res
++};
++set LTO_TORTURE_OPTIONS [add_fat_objects ${LTO_TORTURE_OPTIONS}]
++
++gcc-dg-runtest [lsort [glob $srcdir/$subdir/*.c]] \
++	"" $DEFAULT_CFLAGS
++
++# Restore global values
++set dg-do-what-default ${saved-dg-do-what-default}
++set LTO_TORTURE_OPTIONS ${saved-lto_torture_options}
++
++# All done.
++dg-finish
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/short-vfp-1.c
+@@ -0,0 +1,45 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_vfp_ok }
++/* { dg-options "-mfpu=vfp" } */
++
++int
++test_sisf (float x)
++{
++  return (int)x;
++}
++
++short
++test_hisf (float x)
++{
++  return (short)x;
++}
++
++float
++test_sfsi (int x)
++{
++  return (float)x;
++}
++
++float
++test_sfhi (short x)
++{
++  return (float)x;
++}
++
++short
++test_hisi (int x)
++{
++  return (short)x;
++}
++
++int
++test_sihi (short x)
++{
++  return (int)x;
++}
++
++/* {dg-final { scan-assembler-times {vcvt\.s32\.f32\ts[0-9]+,s[0-9]+} 2 }} */
++/* {dg-final { scan-assembler-times {vcvt\.f32\.s32\ts[0-9]+,s[0-9]+} 2 }} */
++/* {dg-final { scan-assembler-times {vmov\tr[0-9]+,s[0-9]+} 2 }} */
++/* {dg-final { scan-assembler-times {vmov\ts[0-9]+,r[0-9]+} 2 }} */
++/* {dg-final { scan-assembler-times {sxth\tr[0-9]+,r[0-9]+} 2 }} */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/simd/vmaxnm_f32_1.c
+@@ -0,0 +1,159 @@
++/* Test the `vmaxnmf32' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-options "-save-temps -O3 -march=armv8-a" } */
++/* { dg-add-options arm_v8_neon } */
++
++#include "arm_neon.h"
++
++extern void abort ();
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__regular_input1 ()
++{
++  float32_t a1[] = {1,2};
++  float32_t b1[] = {3,4};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != b1[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__regular_input2 ()
++{
++  float32_t a1[] = {3,2};
++  float32_t b1[] = {1,4};
++  float32_t e[] = {3,4};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__quiet_NaN_one_arg ()
++{
++  /* When given a quiet NaN, vmaxnm returns the other operand.
++     In this test case we have NaNs in only one operand.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {1,2};
++  float32_t b1[] = {n,n};
++  float32_t e[] = {1,2};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__quiet_NaN_both_args ()
++{
++  /* When given a quiet NaN, vmaxnm returns the other operand.
++     In this test case we have NaNs in both operands.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,2};
++  float32_t b1[] = {1,n};
++  float32_t e[] = {1,2};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__zero_both_args ()
++{
++  /* For 0 and -0, vmaxnm returns 0.  Since 0 == -0, check sign bit.  */
++  float32_t a1[] = {0.0, 0.0};
++  float32_t b1[] = {-0.0, -0.0};
++  float32_t e[] = {0.0, 0.0};
++
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++
++  float32_t actual1[2];
++  vst1_f32 (actual1, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual1[i] != e[i] || __builtin_signbit (actual1[i]) != 0)
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__inf_both_args ()
++{
++  /* The max of inf and inf is inf.  The max of -inf and -inf is -inf.  */
++  float32_t inf = __builtin_huge_valf ();
++  float32_t a1[] = {inf, -inf};
++  float32_t b1[] = {inf, -inf};
++  float32_t e[] = {inf, -inf};
++
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++
++  float32_t actual1[2];
++  vst1_f32 (actual1, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual1[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnm_f32__two_quiet_NaNs_both_args ()
++{
++  /* When given 2 NaNs, return a NaN.  Since a NaN is not equal to anything,
++     not even another NaN, use __builtin_isnan () to check.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,n};
++  float32_t b1[] = {n,n};
++  float32_t e[] = {n,n};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vmaxnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (!__builtin_isnan (actual[i]))
++      abort ();
++}
++
++int
++main ()
++{
++  test_vmaxnm_f32__regular_input1 ();
++  test_vmaxnm_f32__regular_input2 ();
++  test_vmaxnm_f32__quiet_NaN_one_arg ();
++  test_vmaxnm_f32__quiet_NaN_both_args ();
++  test_vmaxnm_f32__zero_both_args ();
++  test_vmaxnm_f32__inf_both_args ();
++  test_vmaxnm_f32__two_quiet_NaNs_both_args ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler-times "vmaxnm\.f32\t\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" 7 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/simd/vmaxnmq_f32_1.c
+@@ -0,0 +1,160 @@
++/* Test the `vmaxnmqf32' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-options "-save-temps -O3 -march=armv8-a" } */
++/* { dg-add-options arm_v8_neon } */
++
++#include "arm_neon.h"
++
++extern void abort ();
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__regular_input1 ()
++{
++  float32_t a1[] = {1,2,5,6};
++  float32_t b1[] = {3,4,7,8};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != b1[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__regular_input2 ()
++{
++  float32_t a1[] = {3,2,7,6};
++  float32_t b1[] = {1,4,5,8};
++  float32_t e[] = {3,4,7,8};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__quiet_NaN_one_arg ()
++{
++  /* When given a quiet NaN, vmaxnmq returns the other operand.
++     In this test case we have NaNs in only one operand.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {1,2,3,4};
++  float32_t b1[] = {n,n,n,n};
++  float32_t e[] = {1,2,3,4};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__quiet_NaN_both_args ()
++{
++  /* When given a quiet NaN, vmaxnmq returns the other operand.
++     In this test case we have NaNs in both operands.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,2,n,4};
++  float32_t b1[] = {1,n,3,n};
++  float32_t e[] = {1,2,3,4};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__zero_both_args ()
++{
++  /* For 0 and -0, vmaxnmq returns 0.  Since 0 == -0, check sign bit.  */
++  float32_t a1[] = {0.0, 0.0, -0.0, -0.0};
++  float32_t b1[] = {-0.0, -0.0, 0.0, 0.0};
++  float32_t e[] = {0.0, 0.0, 0.0, 0.0};
++
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++
++  float32_t actual1[4];
++  vst1q_f32 (actual1, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual1[i] != e[i] || __builtin_signbit (actual1[i]) != 0)
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__inf_both_args ()
++{
++  /* The max of inf and inf is inf.  The max of -inf and -inf is -inf.  */
++  float32_t inf = __builtin_huge_valf ();
++  float32_t a1[] = {inf, -inf, inf, inf};
++  float32_t b1[] = {inf, -inf, -inf, -inf};
++  float32_t e[] = {inf, -inf, inf, inf};
++
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++
++  float32_t actual1[4];
++  vst1q_f32 (actual1, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual1[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vmaxnmq_f32__two_quiet_NaNs_both_args ()
++{
++  /* When given 2 NaNs, return a NaN.  Since a NaN is not equal to anything,
++     not even another NaN, use __builtin_isnan () to check.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,n,n,n};
++  float32_t b1[] = {n,n,n,n};
++  float32_t e[] = {n,n};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vmaxnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (!__builtin_isnan (actual[i]))
++      abort ();
++}
++
++int
++main ()
++{
++  test_vmaxnmq_f32__regular_input1 ();
++  test_vmaxnmq_f32__regular_input2 ();
++  test_vmaxnmq_f32__quiet_NaN_one_arg ();
++  test_vmaxnmq_f32__quiet_NaN_both_args ();
++  test_vmaxnmq_f32__zero_both_args ();
++  test_vmaxnmq_f32__inf_both_args ();
++  test_vmaxnmq_f32__two_quiet_NaNs_both_args ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler-times "vmaxnm\.f32\t\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+\n" 7 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/simd/vminnm_f32_1.c
+@@ -0,0 +1,159 @@
++/* Test the `vminnmf32' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-options "-save-temps -O3 -march=armv8-a" } */
++/* { dg-add-options arm_v8_neon } */
++
++#include "arm_neon.h"
++
++extern void abort ();
++
++void __attribute__ ((noinline))
++test_vminnm_f32__regular_input1 ()
++{
++  float32_t a1[] = {1,2};
++  float32_t b1[] = {3,4};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != a1[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnm_f32__regular_input2 ()
++{
++  float32_t a1[] = {3,2};
++  float32_t b1[] = {1,4};
++  float32_t e[] = {1,2};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnm_f32__quiet_NaN_one_arg ()
++{
++  /* When given a quiet NaN, vminnm returns the other operand.
++     In this test case we have NaNs in only one operand.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {1,2};
++  float32_t b1[] = {n,n};
++  float32_t e[] = {1,2};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnm_f32__quiet_NaN_both_args ()
++{
++  /* When given a quiet NaN, vminnm returns the other operand.
++     In this test case we have NaNs in both operands.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,2};
++  float32_t b1[] = {1,n};
++  float32_t e[] = {1,2};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnm_f32__zero_both_args ()
++{
++  /* For 0 and -0, vminnm returns -0.  Since 0 == -0, check sign bit.  */
++  float32_t a1[] = {0.0,0.0};
++  float32_t b1[] = {-0.0, -0.0};
++  float32_t e[] = {-0.0, -0.0};
++
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++
++  float32_t actual1[2];
++  vst1_f32 (actual1, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual1[i] != e[i] || __builtin_signbit (actual1[i]) == 0)
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnm_f32__inf_both_args ()
++{
++  /* The min of inf and inf is inf.  The min of -inf and -inf is -inf.  */
++  float32_t inf = __builtin_huge_valf ();
++  float32_t a1[] = {inf, -inf};
++  float32_t b1[] = {inf, -inf};
++  float32_t e[] = {inf, -inf};
++
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++
++  float32_t actual1[2];
++  vst1_f32 (actual1, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (actual1[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnm_f32__two_quiet_NaNs_both_args ()
++{
++  /* When given 2 NaNs, return a NaN.  Since a NaN is not equal to anything,
++     not even another NaN, use __builtin_isnan () to check.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,n};
++  float32_t b1[] = {n,n};
++  float32_t e[] = {n,n};
++  float32x2_t a = vld1_f32 (a1);
++  float32x2_t b = vld1_f32 (b1);
++  float32x2_t c = vminnm_f32 (a, b);
++  float32_t actual[2];
++  vst1_f32 (actual, c);
++
++  for (int i = 0; i < 2; ++i)
++    if (!__builtin_isnan (actual[i]))
++      abort ();
++}
++
++int
++main ()
++{
++  test_vminnm_f32__regular_input1 ();
++  test_vminnm_f32__regular_input2 ();
++  test_vminnm_f32__quiet_NaN_one_arg ();
++  test_vminnm_f32__quiet_NaN_both_args ();
++  test_vminnm_f32__zero_both_args ();
++  test_vminnm_f32__inf_both_args ();
++  test_vminnm_f32__two_quiet_NaNs_both_args ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler-times "vminnm\.f32\t\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" 7 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/simd/vminnmq_f32_1.c
+@@ -0,0 +1,159 @@
++/* Test the `vminnmqf32' ARM Neon intrinsic.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target arm_v8_neon_hw } */
++/* { dg-options "-save-temps -O3 -march=armv8-a" } */
++/* { dg-add-options arm_v8_neon } */
++
++#include "arm_neon.h"
++
++extern void abort ();
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__regular_input1 ()
++{
++  float32_t a1[] = {1,2,5,6};
++  float32_t b1[] = {3,4,7,8};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != a1[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__regular_input2 ()
++{
++  float32_t a1[] = {3,2,7,6};
++  float32_t b1[] = {1,4,5,8};
++  float32_t e[] = {1,2,5,6};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__quiet_NaN_one_arg ()
++{
++  /* When given a quiet NaN, vminnmq returns the other operand.
++     In this test case we have NaNs in only one operand.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {1,2,3,4};
++  float32_t b1[] = {n,n,n,n};
++  float32_t e[] = {1,2,3,4};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__quiet_NaN_both_args ()
++{
++  /* When given a quiet NaN, vminnmq returns the other operand.
++     In this test case we have NaNs in both operands.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,2,n,4};
++  float32_t b1[] = {1,n,3,n};
++  float32_t e[] = {1,2,3,4};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__zero_both_args ()
++{
++  /* For 0 and -0, vminnmq returns -0.  Since 0 == -0, check sign bit.  */
++  float32_t a1[] = {0.0, 0.0, -0.0, -0.0};
++  float32_t b1[] = {-0.0, -0.0, 0.0, 0.0};
++  float32_t e[] = {-0.0, -0.0, -0.0, -0.0};
++
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++
++  float32_t actual1[4];
++  vst1q_f32 (actual1, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual1[i] != e[i] || __builtin_signbit (actual1[i]) == 0)
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__inf_both_args ()
++{
++  /* The min of inf and inf is inf.  The min of -inf and -inf is -inf.  */
++  float32_t inf = __builtin_huge_valf ();
++  float32_t a1[] = {inf, -inf, inf, inf};
++  float32_t b1[] = {inf, -inf, -inf, -inf};
++  float32_t e[] = {inf, -inf, -inf, -inf};
++
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++
++  float32_t actual1[4];
++  vst1q_f32 (actual1, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (actual1[i] != e[i])
++      abort ();
++}
++
++void __attribute__ ((noinline))
++test_vminnmq_f32__two_quiet_NaNs_both_args ()
++{
++  /* When given 2 NaNs, return a NaN.  Since a NaN is not equal to anything,
++     not even another NaN, use __builtin_isnan () to check.  */
++  float32_t n = __builtin_nanf ("");
++  float32_t a1[] = {n,n,n,n};
++  float32_t b1[] = {n,n,n,n};
++  float32_t e[] = {n,n};
++  float32x4_t a = vld1q_f32 (a1);
++  float32x4_t b = vld1q_f32 (b1);
++  float32x4_t c = vminnmq_f32 (a, b);
++  float32_t actual[4];
++  vst1q_f32 (actual, c);
++
++  for (int i = 0; i < 4; ++i)
++    if (!__builtin_isnan (actual[i]))
++      abort ();
++}
++
++int
++main ()
++{
++  test_vminnmq_f32__regular_input1 ();
++  test_vminnmq_f32__regular_input2 ();
++  test_vminnmq_f32__quiet_NaN_one_arg ();
++  test_vminnmq_f32__quiet_NaN_both_args ();
++  test_vminnmq_f32__zero_both_args ();
++  test_vminnmq_f32__inf_both_args ();
++  test_vminnmq_f32__two_quiet_NaNs_both_args ();
++  return 0;
++}
++
++/* { dg-final { scan-assembler-times "vminnm\.f32\t\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+\n" 7 } } */
+--- a/src/gcc/testsuite/gcc.target/arm/small-multiply-m0-1.c
++++ b/src/gcc/testsuite/gcc.target/arm/small-multiply-m0-1.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target arm_thumb1_ok } */
+-/* { dg-skip-if "Test is specific to cortex-m0.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m0.small-multiply" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-m0.small-multiply" } } */
+ /* { dg-options "-mcpu=cortex-m0.small-multiply -mthumb -O2" } */
+ 
+ int
+--- a/src/gcc/testsuite/gcc.target/arm/small-multiply-m0-2.c
++++ b/src/gcc/testsuite/gcc.target/arm/small-multiply-m0-2.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target arm_thumb1_ok } */
+-/* { dg-skip-if "Test is specific to cortex-m0.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m0.small-multiply" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-m0.small-multiply" } } */
+ /* { dg-options "-mcpu=cortex-m0.small-multiply -mthumb -Os" } */
+ 
+ int
+--- a/src/gcc/testsuite/gcc.target/arm/small-multiply-m0-3.c
++++ b/src/gcc/testsuite/gcc.target/arm/small-multiply-m0-3.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target arm_thumb1_ok } */
+-/* { dg-skip-if "Test is specific to cortex-m0.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m0.small-multiply" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-m0.small-multiply" } } */
+ /* { dg-options "-mcpu=cortex-m0.small-multiply -mthumb -Os" } */
+ 
+ int
+--- a/src/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-1.c
++++ b/src/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-1.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target arm_thumb1_ok } */
+-/* { dg-skip-if "Test is specific to cortex-m0plus.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m0plus.small-multiply" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-m0plus.small-multiply" } } */
+ /* { dg-options "-mcpu=cortex-m0plus.small-multiply -mthumb -O2" } */
+ 
+ int
+--- a/src/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-2.c
++++ b/src/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-2.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target arm_thumb1_ok } */
+-/* { dg-skip-if "Test is specific to cortex-m0plus.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m0plus.small-multiply" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-m0plus.small-multiply" } } */
+ /* { dg-options "-mcpu=cortex-m0plus.small-multiply -mthumb -Os" } */
+ 
+ int
+--- a/src/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-3.c
++++ b/src/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-3.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target arm_thumb1_ok } */
+-/* { dg-skip-if "Test is specific to cortex-m0plus.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m0plus.small-multiply" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-m0plus.small-multiply" } } */
+ /* { dg-options "-mcpu=cortex-m0plus.small-multiply -mthumb -Os" } */
+ 
+ int
+--- a/src/gcc/testsuite/gcc.target/arm/small-multiply-m1-1.c
++++ b/src/gcc/testsuite/gcc.target/arm/small-multiply-m1-1.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target arm_thumb1_ok } */
+-/* { dg-skip-if "Test is specific to cortex-m1.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m1.small-multiply" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-m1.small-multiply" } } */
+ /* { dg-options "-mcpu=cortex-m1.small-multiply -mthumb -O2" } */
+ 
+ int
+--- a/src/gcc/testsuite/gcc.target/arm/small-multiply-m1-2.c
++++ b/src/gcc/testsuite/gcc.target/arm/small-multiply-m1-2.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target arm_thumb1_ok } */
+-/* { dg-skip-if "Test is specific to cortex-m1.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m1.small-multiply" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-m1.small-multiply" } } */
+ /* { dg-options "-mcpu=cortex-m1.small-multiply -mthumb -Os" } */
+ 
+ int
+--- a/src/gcc/testsuite/gcc.target/arm/small-multiply-m1-3.c
++++ b/src/gcc/testsuite/gcc.target/arm/small-multiply-m1-3.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target arm_thumb1_ok } */
+-/* { dg-skip-if "Test is specific to cortex-m1.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m1.small-multiply" } } */
++/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-m1.small-multiply" } } */
+ /* { dg-options "-mcpu=cortex-m1.small-multiply -mthumb -Os" } */
+ 
+ int
+--- a/src/gcc/testsuite/gcc.target/arm/stack-checking.c
++++ b/src/gcc/testsuite/gcc.target/arm/stack-checking.c
+@@ -1,6 +1,6 @@
+ /* { dg-do run { target { *-*-linux* } } } */
++/* { dg-require-stack-check "" } */
+ /* { dg-options "-fstack-check" } */
+-/* { dg-skip-if "" { arm_thumb1 } } */
+ 
+ int main(void)
+ {
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-1.c
+@@ -0,0 +1,73 @@
++/* The option -mslow-flash-data is just for performance tuning, it
++   doesn't totally disable the use of literal pools.  But for below
++   simple cases, the use of literal pool should be replaced by
++   movw/movt or read-only constant pool.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_cortex_m } */
++/* { dg-require-effective-target arm_thumb2_ok } */
++/* { dg-options "-O2 -mthumb -mslow-flash-data" } */
++
++float sf;
++double df;
++long long l;
++static char *p = "Hello World";
++
++float
++testsf (float *p)
++{
++  if (*p > 1.1234f)
++    return 2.1234f;
++  else
++    return 3.1234f;
++}
++
++double
++testdf (double *p)
++{
++  if (*p > 4.1234)
++    return 2.1234;
++  else
++    return 3.1234;
++}
++
++long long
++testll (long long *p)
++{
++  if (*p > 0x123456789ABCDEFll)
++    return 0x111111111ll;
++  else
++    return 0x222222222ll;
++}
++
++char *
++testchar ()
++{
++  return p + 4;
++}
++
++int
++foo (int a, int b)
++{
++  int i;
++  volatile int *labelref = &&label1;
++
++  if (a > b)
++    {
++      while (i < b)
++	{
++	  a += *labelref;
++	  i += 1;
++	}
++      goto *labelref;
++    }
++  else
++    b = b + 3;
++
++  a = a * b;
++
++label1:
++  return a + b;
++}
++
++/* { dg-final { scan-assembler-not "\\.(float|l\\?double|\d?byte|short|int|long|quad|word)\\s+\[^.\]" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c
+@@ -0,0 +1,28 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_cortex_m } */
++/* { dg-require-effective-target arm_thumb2_ok } */
++/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */
++/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
++/* { dg-options "-march=armv7e-m -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */
++
++float f (float);
++
++const float max = 0.01f;
++
++int
++g (float in)
++{
++  if (f (in) + f (in) < max)
++    return 0;
++  return 1;
++}
++
++double foo (void)
++{
++  return 0xF1EC7A5239123AF;
++}
++
++double bar (void)
++{
++  return 0.0f;
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_cortex_m } */
++/* { dg-require-effective-target arm_thumb2_ok } */
++/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */
++/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
++/* { dg-options "-march=armv7e-m -mfloat-abi=hard -mthumb -mslow-flash-data" } */
++
++/* From PR71607 */
++
++float b;
++void fn1 ();
++
++float
++fn2 ()
++{
++  return 1.1f;
++}
++
++void
++fn3 ()
++{
++  float a[2];
++  a[1] = b;
++  fn1 (a);
++}
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c
+@@ -0,0 +1,26 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_cortex_m } */
++/* { dg-require-effective-target arm_thumb2_ok } */
++/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */
++/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
++/* { dg-options "-march=armv7e-m -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */
++
++double __attribute__ ((target ("fpu=fpv5-d16")))
++foo (void)
++{
++  return 1.0f;
++}
++
++float __attribute__ ((target ("fpu=fpv5-d16")))
++bar (void)
++{
++  return 1.0f;
++}
++
++float __attribute__ ((target ("fpu=fpv5-sp-d16")))
++baz (void)
++{
++  return 1.0f;
++}
++
++/* { dg-final { scan-assembler-times "#1\\.0e\\+0" 3 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_cortex_m } */
++/* { dg-require-effective-target arm_thumb2_ok } */
++/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */
++/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
++/* { dg-options "-march=armv7e-m -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */
++
++double __attribute__ ((target ("fpu=fpv5-sp-d16")))
++foo (void)
++{
++  return 1.0f;
++}
++
++/* { dg-final { scan-assembler-not "#1\\.0e\\+0" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data.c
++++ b/src//dev/null
+@@ -1,73 +0,0 @@
+-/* The option -mslow-flash-data is just for performance tuning, it
+-   doesn't totally disable the use of literal pools.  But for below
+-   simple cases, the use of literal pool should be replaced by
+-   movw/movt or read-only constant pool.  */
+-
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_cortex_m } */
+-/* { dg-require-effective-target arm_thumb2_ok } */
+-/* { dg-options "-O2 -mthumb -mslow-flash-data" } */
+-
+-float sf;
+-double df;
+-long long l;
+-static char *p = "Hello World";
+-
+-float
+-testsf (float *p)
+-{
+-  if (*p > 1.1234f)
+-    return 2.1234f;
+-  else
+-    return 3.1234f;
+-}
+-
+-double
+-testdf (double *p)
+-{
+-  if (*p > 4.1234)
+-    return 2.1234;
+-  else
+-    return 3.1234;
+-}
+-
+-long long
+-testll (long long *p)
+-{
+-  if (*p > 0x123456789ABCDEFll)
+-    return 0x111111111ll;
+-  else
+-    return 0x222222222ll;
+-}
+-
+-char *
+-testchar ()
+-{
+-  return p + 4;
+-}
+-
+-int
+-foo (int a, int b)
+-{
+-  int i;
+-  volatile int *labelref = &&label1;
+-
+-  if (a > b)
+-    {
+-      while (i < b)
+-	{
+-	  a += *labelref;
+-	  i += 1;
+-	}
+-      goto *labelref;
+-    }
+-  else
+-    b = b + 3;
+-
+-  a = a * b;
+-
+-label1:
+-  return a + b;
+-}
+-
+-/* { dg-final { scan-assembler-not "\\.(float|l\\?double|\d?byte|short|int|long|quad|word)\\s+\[^.\]" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target tls } */
++/* { dg-require-effective-target arm_cortex_m } */
++/* { dg-require-effective-target arm_thumb2_ok } */
++/* { dg-options "-mslow-flash-data" } */
++
++__thread int x = 0;
++
++int
++bar ()
++{
++  return x;
++}
++
++/* { dg-error "accessing thread-local storage is not currently supported with -mpure-code or -mslow-flash-data" "" { target *-*-* } 12 } */
+--- a/src/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c
++++ b/src/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c
+@@ -2,13 +2,13 @@
+ /* { dg-require-effective-target arm_thumb2_ok } */
+ /* { dg-options "-O" } */
+ 
+-unsigned short foo (unsigned short x)
++unsigned short foo (unsigned short x, unsigned short c)
+ {
+   unsigned char i = 0;
+   for (i = 0; i < 8; i++)
+     {
+       x >>= 1;
+-      x &= 0x7fff;
++      x &= c;
+     }
+   return x;
+ }
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/vect-vcvt.c
+@@ -0,0 +1,27 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details -mvectorize-with-neon-double" } */
++/* { dg-add-options arm_neon } */
++
++#define N 32
++
++int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
++float fa[N];
++int ia[N];
++
++int convert()
++{
++  int i;
++
++  /* int -> float */
++  for (i = 0; i < N; i++)
++    fa[i] = (float) ib[i];
++
++  /* float -> int */
++  for (i = 0; i < N; i++)
++    ia[i] = (int) fa[i];
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/vect-vcvtq.c
+@@ -0,0 +1,27 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */
++/* { dg-add-options arm_neon } */
++
++#define N 32
++
++int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
++float fa[N];
++int ia[N];
++
++int convert()
++{
++  int i;
++
++  /* int -> float */
++  for (i = 0; i < N; i++)
++    fa[i] = (float) ib[i];
++
++  /* float -> int */
++  for (i = 0; i < N; i++)
++    ia[i] = (int) fa[i];
++
++  return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/vfp-shift-a2t2.c
+@@ -0,0 +1,27 @@
++/* Check that NEON vector shifts support immediate values == size.  /*
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-save-temps" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint16x8_t test_vshll_n_u8 (uint8x8_t a)
++{
++    return vshll_n_u8(a, 8);
++}
++
++uint32x4_t test_vshll_n_u16 (uint16x4_t a)
++{   
++    return vshll_n_u16(a, 16);
++}
++
++uint64x2_t test_vshll_n_u32 (uint32x2_t a)
++{
++    return vshll_n_u32(a, 32);
++}
++
++/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/vst1Q_laneu64-1.c
+@@ -0,0 +1,25 @@
++/* Test the `vst1Q_laneu64' ARM Neon intrinsic.  */
++
++/* Detect ICE in the case of unaligned memory address.  */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++
++unsigned char dummy_store[1000];
++
++void
++foo (unsigned char* addr)
++{
++  uint8x16_t vdata = vld1q_u8 (addr);
++  vst1q_lane_u64 ((uint64_t*) &dummy_store, vreinterpretq_u64_u8 (vdata), 0);
++}
++
++uint64_t
++bar (uint64x2_t vdata)
++{
++  vdata = vld1q_lane_u64 ((uint64_t*) &dummy_store, vdata, 0);
++  return vgetq_lane_u64 (vdata, 0);
++}
+--- a/src/gcc/testsuite/gcc.target/i386/pr48723.c
++++ b/src/gcc/testsuite/gcc.target/i386/pr48723.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-stack-check "" } */
+ /* { dg-options "-fstack-check -mavx" } */
+ 
+ struct S0
+--- a/src/gcc/testsuite/gcc.target/i386/pr55672.c
++++ b/src/gcc/testsuite/gcc.target/i386/pr55672.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-stack-check "generic" } */
+ /* { dg-options "-O -fstack-check=generic" } */
+ 
+ int main ()
+--- a/src/gcc/testsuite/gcc.target/i386/pr67265-2.c
++++ b/src/gcc/testsuite/gcc.target/i386/pr67265-2.c
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-require-stack-check "" } */
+ /* { dg-options "-O -fstack-check" } */
+ 
+ void foo (int n)
+--- a/src/gcc/testsuite/gcc.target/i386/pr67265.c
++++ b/src/gcc/testsuite/gcc.target/i386/pr67265.c
+@@ -2,6 +2,7 @@
+ /* Reduced testcase by Johannes Dewender <gnu@JonnyJD.net> */
+ 
+ /* { dg-do compile } */
++/* { dg-require-stack-check "" } */
+ /* { dg-options "-O -fstack-check -fPIC" } */
+ 
+ int a, b, c, d, e;
+--- a/src/gcc/testsuite/gnat.dg/opt49.adb
++++ b/src/gcc/testsuite/gnat.dg/opt49.adb
+@@ -1,4 +1,5 @@
+ -- { dg-do run }
++-- { dg-require-stack-check "" }
+ -- { dg-options "-O -fstack-check" }
+ 
+ procedure Opt49 is
+--- a/src/gcc/testsuite/gnat.dg/stack_check1.adb
++++ b/src/gcc/testsuite/gnat.dg/stack_check1.adb
+@@ -1,4 +1,5 @@
+ -- { dg-do run }
++-- { dg-require-stack-check "" }
+ -- { dg-options "-fstack-check" }
+ 
+ -- This test requires architecture- and OS-specific support code for unwinding
+--- a/src/gcc/testsuite/gnat.dg/stack_check2.adb
++++ b/src/gcc/testsuite/gnat.dg/stack_check2.adb
+@@ -1,4 +1,5 @@
+ -- { dg-do run }
++-- { dg-require-stack-check "" }
+ -- { dg-options "-fstack-check" }
+ 
+ -- This test requires architecture- and OS-specific support code for unwinding
+--- a/src/gcc/testsuite/gnat.dg/stack_check3.adb
++++ b/src/gcc/testsuite/gnat.dg/stack_check3.adb
+@@ -1,4 +1,5 @@
+ -- { dg-do compile }
++-- { dg-require-stack-check "" }
+ -- { dg-options "-O -fstack-check" }
+ 
+ package body Stack_Check3 is
+--- a/src/gcc/testsuite/lib/gcc-dg.exp
++++ b/src/gcc/testsuite/lib/gcc-dg.exp
+@@ -403,6 +403,7 @@ if { [info procs ${tool}_load] != [list] \
+ 	    switch [lindex $result 0] {
+ 		"pass" { set status "fail" }
+ 		"fail" { set status "pass" }
++		default { set status [lindex $result 0] }
+ 	    }
+ 	    set result [list $status [lindex $result 1]]
+ 	}
+--- a/src/gcc/testsuite/lib/target-supports-dg.exp
++++ b/src/gcc/testsuite/lib/target-supports-dg.exp
+@@ -265,6 +265,21 @@ proc dg-require-linker-plugin { args } {
+     }
+ }
+ 
++# If this target does not support the "stack-check" option, skip this
++# test.
++
++proc dg-require-stack-check { args } {
++    set stack_check_available [ check_stack_check_available [lindex $args 1 ] ]
++    if { $stack_check_available == -1 } {
++	upvar name name
++	unresolved "$name"
++    }
++    if { $stack_check_available != 1 } {
++	upvar dg-do-what dg-do-what
++	set dg-do-what [list [lindex ${dg-do-what} 0] "N" "P"]
++    }
++}
++
+ # Add any target-specific flags needed for accessing the given list
+ # of features.  This must come after all dg-options.
+ 
+--- a/src/gcc/testsuite/lib/target-supports.exp
++++ b/src/gcc/testsuite/lib/target-supports.exp
+@@ -252,6 +252,20 @@ proc check_runtime {prop args} {
+     }]
+ }
+ 
++# Return 1 if GCC was configured with $pattern.
++proc check_configured_with { pattern } {
++    global tool
++
++    set gcc_output [${tool}_target_compile "-v" "" "none" ""]
++    if { [ regexp "Configured with: \[^\n\]*$pattern" $gcc_output ] } {
++        verbose "Matched: $pattern" 2
++        return 1
++    }
++
++    verbose "Failed to match: $pattern" 2
++    return 0
++}
++
+ ###############################
+ # proc check_weak_available { }
+ ###############################
+@@ -971,6 +985,17 @@ proc check_effective_target_fstack_protector {} {
+     } "-fstack-protector"]
+ }
+ 
++# Return 1 if the target supports -fstack-check or -fstack-check=$stack_kind
++proc check_stack_check_available { stack_kind } {
++    if [string match "" $stack_kind] then {
++	set stack_opt "-fstack-check"
++    } else { set stack_opt "-fstack-check=$stack_kind" }
++
++    return [check_no_compiler_messages stack_check executable {
++	int main (void) { return 0; }
++    } "$stack_opt"]
++}
++
+ # Return 1 if compilation with -freorder-blocks-and-partition is error-free
+ # for trivial code, 0 otherwise.
+ 
+@@ -2944,6 +2969,28 @@ proc add_options_for_arm_v8_1a_neon { flags } {
+     return "$flags $et_arm_v8_1a_neon_flags -march=armv8.1-a"
+ }
+ 
++# Add the options needed for ARMv8.2 with the scalar FP16 extension.
++# Also adds the ARMv8 FP options for ARM and for AArch64.
++
++proc add_options_for_arm_v8_2a_fp16_scalar { flags } {
++    if { ! [check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
++	return "$flags"
++    }
++    global et_arm_v8_2a_fp16_scalar_flags
++    return "$flags $et_arm_v8_2a_fp16_scalar_flags"
++}
++
++# Add the options needed for ARMv8.2 with the FP16 extension.  Also adds
++# the ARMv8 NEON options for ARM and for AArch64.
++
++proc add_options_for_arm_v8_2a_fp16_neon { flags } {
++    if { ! [check_effective_target_arm_v8_2a_fp16_neon_ok] } {
++	return "$flags"
++    }
++    global et_arm_v8_2a_fp16_neon_flags
++    return "$flags $et_arm_v8_2a_fp16_neon_flags"
++}
++
+ proc add_options_for_arm_crc { flags } {
+     if { ! [check_effective_target_arm_crc_ok] } {
+         return "$flags"
+@@ -3030,23 +3077,25 @@ proc check_effective_target_arm_crc_ok { } {
+ 
+ proc check_effective_target_arm_neon_fp16_ok_nocache { } {
+     global et_arm_neon_fp16_flags
++    global et_arm_neon_flags
+     set et_arm_neon_fp16_flags ""
+-    if { [check_effective_target_arm32] } {
++    if { [check_effective_target_arm32]
++	 && [check_effective_target_arm_neon_ok] } {
+ 	foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
+ 		       "-mfpu=neon-fp16 -mfloat-abi=softfp"
+ 		       "-mfp16-format=ieee"
+ 		       "-mfloat-abi=softfp -mfp16-format=ieee"
+ 		       "-mfpu=neon-fp16 -mfp16-format=ieee"
+ 		       "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} {
+-	    if { [check_no_compiler_messages_nocache arm_neon_fp_16_ok object {
++	    if { [check_no_compiler_messages_nocache arm_neon_fp16_ok object {
+ 		#include "arm_neon.h"
+ 		float16x4_t
+ 		foo (float32x4_t arg)
+ 		{
+                   return vcvt_f16_f32 (arg);
+ 		}
+-	    } "$flags"] } {
+-		set et_arm_neon_fp16_flags $flags
++	    } "$et_arm_neon_flags $flags"] } {
++		set et_arm_neon_fp16_flags [concat $et_arm_neon_flags $flags]
+ 		return 1
+ 	    }
+ 	}
+@@ -3083,6 +3132,65 @@ proc add_options_for_arm_neon_fp16 { flags } {
+     return "$flags $et_arm_neon_fp16_flags"
+ }
+ 
++# Return 1 if this is an ARM target supporting the FP16 alternative
++# format.  Some multilibs may be incompatible with the options needed.  Also
++# set et_arm_neon_fp16_flags to the best options to add.
++
++proc check_effective_target_arm_fp16_alternative_ok_nocache { } {
++    global et_arm_neon_fp16_flags
++    set et_arm_neon_fp16_flags ""
++    if { [check_effective_target_arm32] } {
++	foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
++		       "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
++	    if { [check_no_compiler_messages_nocache \
++		      arm_fp16_alternative_ok object {
++		#if !defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++		#error __ARM_FP16_FORMAT_ALTERNATIVE not defined
++		#endif
++	    } "$flags -mfp16-format=alternative"] } {
++		set et_arm_neon_fp16_flags "$flags -mfp16-format=alternative"
++		return 1
++	    }
++	}
++    }
++
++    return 0
++}
++
++proc check_effective_target_arm_fp16_alternative_ok { } {
++    return [check_cached_effective_target arm_fp16_alternative_ok \
++		check_effective_target_arm_fp16_alternative_ok_nocache]
++}
++
++# Return 1 if this is an ARM target supports specifying the FP16 none
++# format.  Some multilibs may be incompatible with the options needed.
++
++proc check_effective_target_arm_fp16_none_ok_nocache { } {
++    if { [check_effective_target_arm32] } {
++	foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
++		       "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
++	    if { [check_no_compiler_messages_nocache \
++		      arm_fp16_none_ok object {
++		#if defined (__ARM_FP16_FORMAT_ALTERNATIVE)
++		#error __ARM_FP16_FORMAT_ALTERNATIVE defined
++		#endif
++		#if defined (__ARM_FP16_FORMAT_IEEE)
++		#error __ARM_FP16_FORMAT_IEEE defined
++		#endif
++	    } "$flags -mfp16-format=none"] } {
++		return 1
++	    }
++	}
++    }
++
++    return 0
++}
++
++proc check_effective_target_arm_fp16_none_ok { } {
++    return [check_cached_effective_target arm_fp16_none_ok \
++		check_effective_target_arm_fp16_none_ok_nocache]
++}
++
+ # Return 1 if this is an ARM target supporting -mfpu=neon-fp-armv8
+ # -mfloat-abi=softfp or equivalent options.  Some multilibs may be
+ # incompatible with these options.  Also set et_arm_v8_neon_flags to the
+@@ -3125,8 +3233,10 @@ proc check_effective_target_arm_v8_neon_ok { } {
+ 
+ proc check_effective_target_arm_neonv2_ok_nocache { } {
+     global et_arm_neonv2_flags
++    global et_arm_neon_flags
+     set et_arm_neonv2_flags ""
+-    if { [check_effective_target_arm32] } {
++    if { [check_effective_target_arm32]
++	 && [check_effective_target_arm_neon_ok] } {
+ 	foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-vfpv4" "-mfpu=neon-vfpv4 -mfloat-abi=softfp"} {
+ 	    if { [check_no_compiler_messages_nocache arm_neonv2_ok object {
+ 		#include "arm_neon.h"
+@@ -3135,8 +3245,8 @@ proc check_effective_target_arm_neonv2_ok_nocache { } {
+                 {
+                   return vfma_f32 (a, b, c);
+                 }
+-	    } "$flags"] } {
+-		set et_arm_neonv2_flags $flags
++	    } "$et_arm_neon_flags $flags"] } {
++		set et_arm_neonv2_flags [concat $et_arm_neon_flags $flags]
+ 		return 1
+ 	    }
+ 	}
+@@ -3150,9 +3260,9 @@ proc check_effective_target_arm_neonv2_ok { } {
+ 		check_effective_target_arm_neonv2_ok_nocache]
+ }
+ 
+-# Add the options needed for NEON.  We need either -mfloat-abi=softfp
+-# or -mfloat-abi=hard, but if one is already specified by the
+-# multilib, use it.
++# Add the options needed for VFP FP16 support.  We need either
++# -mfloat-abi=softfp or -mfloat-abi=hard.  If one is already specified by
++# the multilib, use it.
+ 
+ proc add_options_for_arm_fp16 { flags } {
+     if { ! [check_effective_target_arm_fp16_ok] } {
+@@ -3162,9 +3272,32 @@ proc add_options_for_arm_fp16 { flags } {
+     return "$flags $et_arm_fp16_flags"
+ }
+ 
++# Add the options needed to enable support for IEEE format
++# half-precision support.  This is valid for ARM targets.
++
++proc add_options_for_arm_fp16_ieee { flags } {
++    if { ! [check_effective_target_arm_fp16_ok] } {
++	return "$flags"
++    }
++    global et_arm_fp16_flags
++    return "$flags $et_arm_fp16_flags -mfp16-format=ieee"
++}
++
++# Add the options needed to enable support for ARM Alternative format
++# half-precision support.  This is valid for ARM targets.
++
++proc add_options_for_arm_fp16_alternative { flags } {
++    if { ! [check_effective_target_arm_fp16_ok] } {
++	return "$flags"
++    }
++    global et_arm_fp16_flags
++    return "$flags $et_arm_fp16_flags -mfp16-format=alternative"
++}
++
+ # Return 1 if this is an ARM target that can support a VFP fp16 variant.
+ # Skip multilibs that are incompatible with these options and set
+-# et_arm_fp16_flags to the best options to add.
++# et_arm_fp16_flags to the best options to add.  This test is valid for
++# ARM only.
+ 
+ proc check_effective_target_arm_fp16_ok_nocache { } {
+     global et_arm_fp16_flags
+@@ -3172,7 +3305,10 @@ proc check_effective_target_arm_fp16_ok_nocache { } {
+     if { ! [check_effective_target_arm32] } {
+ 	return 0;
+     }
+-    if [check-flags [list "" { *-*-* } { "-mfpu=*" } { "-mfpu=*fp16*" "-mfpu=*fpv[4-9]*" "-mfpu=*fpv[1-9][0-9]*" } ]] {
++    if [check-flags \
++	    [list "" { *-*-* } { "-mfpu=*" } \
++		 { "-mfpu=*fp16*" "-mfpu=*fpv[4-9]*" \
++		       "-mfpu=*fpv[1-9][0-9]*" "-mfpu=*fp-armv8*" } ]] {
+ 	# Multilib flags would override -mfpu.
+ 	return 0
+     }
+@@ -3208,6 +3344,28 @@ proc check_effective_target_arm_fp16_ok { } {
+ 		check_effective_target_arm_fp16_ok_nocache]
+ }
+ 
++# Return 1 if the target supports executing VFP FP16 instructions, 0
++# otherwise.  This test is valid for ARM only.
++
++proc check_effective_target_arm_fp16_hw { } {
++    if {! [check_effective_target_arm_fp16_ok] } {
++	return 0
++    }
++    global et_arm_fp16_flags
++    check_runtime_nocache arm_fp16_hw {
++	int
++	main (int argc, char **argv)
++	{
++	  __fp16 a = 1.0;
++	  float r;
++	  asm ("vcvtb.f32.f16 %0, %1"
++	       : "=w" (r) : "w" (a)
++	       : /* No clobbers.  */);
++	  return (r == 1.0) ? 0 : 1;
++	}
++    } "$et_arm_fp16_flags -mfp16-format=ieee"
++}
++
+ # Creates a series of routines that return 1 if the given architecture
+ # can be selected and a routine to give the flags to select that architecture
+ # Note: Extra flags may be added to disable options from newer compilers
+@@ -3217,22 +3375,26 @@ proc check_effective_target_arm_fp16_ok { } {
+ # Usage: /* { dg-require-effective-target arm_arch_v5_ok } */
+ #        /* { dg-add-options arm_arch_v5 } */
+ #	 /* { dg-require-effective-target arm_arch_v5_multilib } */
+-foreach { armfunc armflag armdef } { v4 "-march=armv4 -marm" __ARM_ARCH_4__
+-				     v4t "-march=armv4t" __ARM_ARCH_4T__
+-				     v5 "-march=armv5 -marm" __ARM_ARCH_5__
+-				     v5t "-march=armv5t" __ARM_ARCH_5T__
+-				     v5te "-march=armv5te" __ARM_ARCH_5TE__
+-				     v6 "-march=armv6" __ARM_ARCH_6__
+-				     v6k "-march=armv6k" __ARM_ARCH_6K__
+-				     v6t2 "-march=armv6t2" __ARM_ARCH_6T2__
+-				     v6z "-march=armv6z" __ARM_ARCH_6Z__
+-				     v6m "-march=armv6-m -mthumb" __ARM_ARCH_6M__
+-				     v7a "-march=armv7-a" __ARM_ARCH_7A__
+-				     v7r "-march=armv7-r" __ARM_ARCH_7R__
+-				     v7m "-march=armv7-m -mthumb" __ARM_ARCH_7M__
+-				     v7em "-march=armv7e-m -mthumb" __ARM_ARCH_7EM__
+-				     v8a "-march=armv8-a" __ARM_ARCH_8A__
+-				     v8_1a "-march=armv8.1a" __ARM_ARCH_8A__ } {
++foreach { armfunc armflag armdef } {
++	v4 "-march=armv4 -marm" __ARM_ARCH_4__
++	v4t "-march=armv4t" __ARM_ARCH_4T__
++	v5 "-march=armv5 -marm" __ARM_ARCH_5__
++	v5t "-march=armv5t" __ARM_ARCH_5T__
++	v5te "-march=armv5te" __ARM_ARCH_5TE__
++	v6 "-march=armv6" __ARM_ARCH_6__
++	v6k "-march=armv6k" __ARM_ARCH_6K__
++	v6t2 "-march=armv6t2" __ARM_ARCH_6T2__
++	v6z "-march=armv6z" __ARM_ARCH_6Z__
++	v6m "-march=armv6-m -mthumb -mfloat-abi=soft" __ARM_ARCH_6M__
++	v7a "-march=armv7-a" __ARM_ARCH_7A__
++	v7r "-march=armv7-r" __ARM_ARCH_7R__
++	v7m "-march=armv7-m -mthumb" __ARM_ARCH_7M__
++	v7em "-march=armv7e-m -mthumb" __ARM_ARCH_7EM__
++	v8a "-march=armv8-a" __ARM_ARCH_8A__
++	v8_1a "-march=armv8.1a" __ARM_ARCH_8A__
++	v8_2a "-march=armv8.2a" __ARM_ARCH_8A__
++	v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft" __ARM_ARCH_8M_BASE__
++	v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__ } {
+     eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef ] {
+ 	proc check_effective_target_arm_arch_FUNC_ok { } {
+ 	    if { [ string match "*-marm*" "FLAG" ] &&
+@@ -3282,6 +3444,12 @@ proc add_options_for_arm_arch_v7ve { flags } {
+     return "$flags -march=armv7ve"
+ }
+ 
++# Return 1 if GCC was configured with --with-mode=
++proc check_effective_target_default_mode { } {
++
++    return [check_configured_with "with-mode="]
++}
++
+ # Return 1 if this is an ARM target where -marm causes ARM to be
+ # used (not Thumb)
+ 
+@@ -3360,15 +3528,60 @@ proc check_effective_target_arm_cortex_m { } {
+ 	return 0
+     }
+     return [check_no_compiler_messages arm_cortex_m assembly {
+-	#if !defined(__ARM_ARCH_7M__) \
+-            && !defined (__ARM_ARCH_7EM__) \
+-            && !defined (__ARM_ARCH_6M__)
+-	#error !__ARM_ARCH_7M__ && !__ARM_ARCH_7EM__ && !__ARM_ARCH_6M__
++	#if defined(__ARM_ARCH_ISA_ARM)
++	#error __ARM_ARCH_ISA_ARM is defined
+ 	#endif
+ 	int i;
+     } "-mthumb"]
+ }
+ 
++# Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
++# used and MOVT/MOVW instructions to be available.
++
++proc check_effective_target_arm_thumb1_movt_ok {} {
++    if [check_effective_target_arm_thumb1_ok] {
++	return [check_no_compiler_messages arm_movt object {
++	    int
++	    foo (void)
++	    {
++	      asm ("movt r0, #42");
++	    }
++	} "-mthumb"]
++    } else {
++	return 0
++    }
++}
++
++# Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
++# used and CBZ and CBNZ instructions are available.
++
++proc check_effective_target_arm_thumb1_cbz_ok {} {
++    if [check_effective_target_arm_thumb1_ok] {
++	return [check_no_compiler_messages arm_movt object {
++	    int
++	    foo (void)
++	    {
++	      asm ("cbz r0, 2f\n2:");
++	    }
++	} "-mthumb"]
++    } else {
++	return 0
++    }
++}
++
++# Return 1 if this is an ARM target where ARMv8-M Security Extensions is
++# available.
++
++proc check_effective_target_arm_cmse_ok {} {
++    return [check_no_compiler_messages arm_cmse object {
++	int
++	foo (void)
++	{
++	  asm ("bxns r0");
++	}
++    } "-mcmse"];
++}
++
+ # Return 1 if this compilation turns on string_ops_prefer_neon on.
+ 
+ proc check_effective_target_arm_tune_string_ops_prefer_neon { } {
+@@ -3444,6 +3657,76 @@ proc check_effective_target_arm_v8_1a_neon_ok { } {
+ 		check_effective_target_arm_v8_1a_neon_ok_nocache]
+ }
+ 
++# Return 1 if the target supports ARMv8.2 scalar FP16 arithmetic
++# instructions, 0 otherwise.  The test is valid for ARM and for AArch64.
++# Record the command line options needed.
++
++proc check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache { } {
++    global et_arm_v8_2a_fp16_scalar_flags
++    set et_arm_v8_2a_fp16_scalar_flags ""
++
++    if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
++	return 0;
++    }
++
++    # Iterate through sets of options to find the compiler flags that
++    # need to be added to the -march option.
++    foreach flags {"" "-mfpu=fp-armv8" "-mfloat-abi=softfp" \
++		       "-mfpu=fp-armv8 -mfloat-abi=softfp"} {
++	if { [check_no_compiler_messages_nocache \
++		  arm_v8_2a_fp16_scalar_ok object {
++	    #if !defined (__ARM_FEATURE_FP16_SCALAR_ARITHMETIC)
++	    #error "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC not defined"
++	    #endif
++	} "$flags -march=armv8.2-a+fp16"] } {
++	    set et_arm_v8_2a_fp16_scalar_flags "$flags -march=armv8.2-a+fp16"
++	    return 1
++	}
++    }
++
++    return 0;
++}
++
++proc check_effective_target_arm_v8_2a_fp16_scalar_ok { } {
++    return [check_cached_effective_target arm_v8_2a_fp16_scalar_ok \
++		check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache]
++}
++
++# Return 1 if the target supports ARMv8.2 Adv.SIMD FP16 arithmetic
++# instructions, 0 otherwise.  The test is valid for ARM and for AArch64.
++# Record the command line options needed.
++
++proc check_effective_target_arm_v8_2a_fp16_neon_ok_nocache { } {
++    global et_arm_v8_2a_fp16_neon_flags
++    set et_arm_v8_2a_fp16_neon_flags ""
++
++    if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
++	return 0;
++    }
++
++    # Iterate through sets of options to find the compiler flags that
++    # need to be added to the -march option.
++    foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
++		       "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
++	if { [check_no_compiler_messages_nocache \
++		  arm_v8_2a_fp16_neon_ok object {
++	    #if !defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
++	    #error "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC not defined"
++	    #endif
++	} "$flags -march=armv8.2-a+fp16"] } {
++	    set et_arm_v8_2a_fp16_neon_flags "$flags -march=armv8.2-a+fp16"
++	    return 1
++	}
++    }
++
++    return 0;
++}
++
++proc check_effective_target_arm_v8_2a_fp16_neon_ok { } {
++    return [check_cached_effective_target arm_v8_2a_fp16_neon_ok \
++		check_effective_target_arm_v8_2a_fp16_neon_ok_nocache]
++}
++
+ # Return 1 if the target supports executing ARMv8 NEON instructions, 0
+ # otherwise.
+ 
+@@ -3453,11 +3736,17 @@ proc check_effective_target_arm_v8_neon_hw { } {
+ 	int
+ 	main (void)
+ 	{
+-	  float32x2_t a;
++	  float32x2_t a = { 1.0f, 2.0f };
++	  #ifdef __ARM_ARCH_ISA_A64
++	  asm ("frinta %0.2s, %1.2s"
++	      : "=w" (a)
++	      : "w" (a));
++	  #else
+ 	  asm ("vrinta.f32 %P0, %P1"
+ 	       : "=w" (a)
+ 	       : "0" (a));
+-	  return 0;
++	  #endif
++	  return a[0] == 2.0f;
+ 	}
+     } [add_options_for_arm_v8_neon ""]]
+ }
+@@ -3500,6 +3789,81 @@ proc check_effective_target_arm_v8_1a_neon_hw { } {
+     } [add_options_for_arm_v8_1a_neon ""]]
+ }
+ 
++# Return 1 if the target supports executing floating point instructions from
++# ARMv8.2 with the FP16 extension, 0 otherwise.  The test is valid for ARM and
++# for AArch64.
++
++proc check_effective_target_arm_v8_2a_fp16_scalar_hw { } {
++    if { ![check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
++	return 0;
++    }
++    return [check_runtime arm_v8_2a_fp16_scalar_hw_available {
++	int
++	main (void)
++	{
++	  __fp16 a = 1.0;
++	  __fp16 result;
++
++	  #ifdef __ARM_ARCH_ISA_A64
++
++	  asm ("fabs %h0, %h1"
++	       : "=w"(result)
++	       : "w"(a)
++	       : /* No clobbers.  */);
++
++	  #else
++
++	  asm ("vabs.f16 %0, %1"
++	       : "=w"(result)
++	       : "w"(a)
++	       : /* No clobbers.  */);
++
++	  #endif
++
++	  return (result == 1.0) ? 0 : 1;
++	}
++    } [add_options_for_arm_v8_2a_fp16_scalar ""]]
++}
++
++# Return 1 if the target supports executing Adv.SIMD instructions from ARMv8.2
++# with the FP16 extension, 0 otherwise.  The test is valid for ARM and for
++# AArch64.
++
++proc check_effective_target_arm_v8_2a_fp16_neon_hw { } {
++    if { ![check_effective_target_arm_v8_2a_fp16_neon_ok] } {
++	return 0;
++    }
++    return [check_runtime arm_v8_2a_fp16_neon_hw_available {
++	int
++	main (void)
++	{
++	  #ifdef __ARM_ARCH_ISA_A64
++
++	  __Float16x4_t a = {1.0, -1.0, 1.0, -1.0};
++	  __Float16x4_t result;
++
++	  asm ("fabs %0.4h, %1.4h"
++	       : "=w"(result)
++	       : "w"(a)
++	       : /* No clobbers.  */);
++
++	  #else
++
++	  __simd64_float16_t a = {1.0, -1.0, 1.0, -1.0};
++	  __simd64_float16_t result;
++
++	  asm ("vabs.f16 %P0, %P1"
++	       : "=w"(result)
++	       : "w"(a)
++	       : /* No clobbers.  */);
++
++	  #endif
++
++	  return (result[0] == 1.0) ? 0 : 1;
++	}
++    } [add_options_for_arm_v8_2a_fp16_neon ""]]
++}
++
+ # Return 1 if this is a ARM target with NEON enabled.
+ 
+ proc check_effective_target_arm_neon { } {
+@@ -3534,6 +3898,25 @@ proc check_effective_target_arm_neonv2 { } {
+     }
+ }
+ 
++# Return 1 if this is an ARM target with load acquire and store release
++# instructions for 8-, 16- and 32-bit types.
++
++proc check_effective_target_arm_acq_rel { } {
++    return [check_no_compiler_messages arm_acq_rel object {
++	void
++	load_acquire_store_release (void)
++	{
++	  asm ("lda r0, [r1]\n\t"
++	       "stl r0, [r1]\n\t"
++	       "ldah r0, [r1]\n\t"
++	       "stlh r0, [r1]\n\t"
++	       "ldab r0, [r1]\n\t"
++	       "stlb r0, [r1]"
++	       : : : "r0", "memory");
++	}
++    }]
++}
++
+ # Return 1 if this a Loongson-2E or -2F target using an ABI that supports
+ # the Loongson vector modes.
+ 
+@@ -4388,6 +4771,8 @@ proc check_effective_target_vect_widen_sum_hi_to_si_pattern { } {
+         set et_vect_widen_sum_hi_to_si_pattern_saved 0
+         if { [istarget powerpc*-*-*]
+              || [istarget aarch64*-*-*]
++	     || ([istarget arm*-*-*] &&
++		 [check_effective_target_arm_neon_ok])
+              || [istarget ia64-*-*] } {
+             set et_vect_widen_sum_hi_to_si_pattern_saved 1
+         }
+@@ -5763,6 +6148,8 @@ proc check_effective_target_sync_int_long { } {
+ 	     || [istarget aarch64*-*-*]
+ 	     || [istarget alpha*-*-*] 
+ 	     || [istarget arm*-*-linux-*] 
++	     || ([istarget arm*-*-*]
++		 && [check_effective_target_arm_acq_rel])
+ 	     || [istarget bfin*-*linux*]
+ 	     || [istarget hppa*-*linux*]
+ 	     || [istarget s390*-*-*] 
+@@ -5796,6 +6183,8 @@ proc check_effective_target_sync_char_short { } {
+ 	     || [istarget i?86-*-*] || [istarget x86_64-*-*]
+ 	     || [istarget alpha*-*-*] 
+ 	     || [istarget arm*-*-linux-*] 
++	     || ([istarget arm*-*-*]
++		 && [check_effective_target_arm_acq_rel])
+ 	     || [istarget hppa*-*linux*]
+ 	     || [istarget s390*-*-*] 
+ 	     || [istarget powerpc*-*-*]
+--- a/src/gcc/tree-inline.c
++++ b/src/gcc/tree-inline.c
+@@ -244,6 +244,7 @@ remap_ssa_name (tree name, copy_body_data *id)
+       /* At least IPA points-to info can be directly transferred.  */
+       if (id->src_cfun->gimple_df
+ 	  && id->src_cfun->gimple_df->ipa_pta
++	  && POINTER_TYPE_P (TREE_TYPE (name))
+ 	  && (pi = SSA_NAME_PTR_INFO (name))
+ 	  && !pi->pt.anything)
+ 	{
+@@ -276,6 +277,7 @@ remap_ssa_name (tree name, copy_body_data *id)
+       /* At least IPA points-to info can be directly transferred.  */
+       if (id->src_cfun->gimple_df
+ 	  && id->src_cfun->gimple_df->ipa_pta
++	  && POINTER_TYPE_P (TREE_TYPE (name))
+ 	  && (pi = SSA_NAME_PTR_INFO (name))
+ 	  && !pi->pt.anything)
+ 	{
+--- a/src/gcc/tree-scalar-evolution.c
++++ b/src/gcc/tree-scalar-evolution.c
+@@ -1937,6 +1937,36 @@ interpret_rhs_expr (struct loop *loop, gimple *at_stmt,
+       res = chrec_convert (type, chrec1, at_stmt);
+       break;
+ 
++    case BIT_AND_EXPR:
++      /* Given int variable A, handle A&0xffff as (int)(unsigned short)A.
++	 If A is SCEV and its value is in the range of representable set
++	 of type unsigned short, the result expression is a (no-overflow)
++	 SCEV.  */
++      res = chrec_dont_know;
++      if (tree_fits_uhwi_p (rhs2))
++	{
++	  int precision;
++	  unsigned HOST_WIDE_INT val = tree_to_uhwi (rhs2);
++
++	  val ++;
++	  /* Skip if value of rhs2 wraps in unsigned HOST_WIDE_INT or
++	     it's not the maximum value of a smaller type than rhs1.  */
++	  if (val != 0
++	      && (precision = exact_log2 (val)) > 0
++	      && (unsigned) precision < TYPE_PRECISION (TREE_TYPE (rhs1)))
++	    {
++	      tree utype = build_nonstandard_integer_type (precision, 1);
++
++	      if (TYPE_PRECISION (utype) < TYPE_PRECISION (TREE_TYPE (rhs1)))
++		{
++		  chrec1 = analyze_scalar_evolution (loop, rhs1);
++		  chrec1 = chrec_convert (utype, chrec1, at_stmt);
++		  res = chrec_convert (TREE_TYPE (rhs1), chrec1, at_stmt);
++		}
++	    }
++	}
++      break;
++
+     default:
+       res = chrec_dont_know;
+       break;
+--- a/src/gcc/tree-ssa-address.c
++++ b/src/gcc/tree-ssa-address.c
+@@ -877,6 +877,10 @@ copy_ref_info (tree new_ref, tree old_ref)
+ 	      && TREE_CODE (old_ref) == MEM_REF
+ 	      && !(TREE_CODE (new_ref) == TARGET_MEM_REF
+ 		   && (TMR_INDEX2 (new_ref)
++		       /* TODO: Below conditions can be relaxed if TMR_INDEX
++			  is an indcution variable and its initial value and
++			  step are aligned.  */
++		       || (TMR_INDEX (new_ref) && !TMR_STEP (new_ref))
+ 		       || (TMR_STEP (new_ref)
+ 			   && (TREE_INT_CST_LOW (TMR_STEP (new_ref))
+ 			       < align)))))
+--- a/src/gcc/tree-ssa-ccp.c
++++ b/src/gcc/tree-ssa-ccp.c
+@@ -229,13 +229,12 @@ debug_lattice_value (ccp_prop_value_t val)
+   fprintf (stderr, "\n");
+ }
+ 
+-/* Extend NONZERO_BITS to a full mask, with the upper bits being set.  */
++/* Extend NONZERO_BITS to a full mask, based on sgn.  */ 
+ 
+ static widest_int
+-extend_mask (const wide_int &nonzero_bits)
++extend_mask (const wide_int &nonzero_bits, signop sgn)
+ {
+-  return (wi::mask <widest_int> (wi::get_precision (nonzero_bits), true)
+-	  | widest_int::from (nonzero_bits, UNSIGNED));
++  return widest_int::from (nonzero_bits, sgn); 
+ }
+ 
+ /* Compute a default value for variable VAR and store it in the
+@@ -284,7 +283,7 @@ get_default_value (tree var)
+ 		{
+ 		  val.lattice_val = CONSTANT;
+ 		  val.value = build_zero_cst (TREE_TYPE (var));
+-		  val.mask = extend_mask (nonzero_bits);
++		  val.mask = extend_mask (nonzero_bits, TYPE_SIGN (TREE_TYPE (var)));
+ 		}
+ 	    }
+ 	}
+@@ -1947,7 +1946,7 @@ evaluate_stmt (gimple *stmt)
+ 	    {
+ 	      val.lattice_val = CONSTANT;
+ 	      val.value = build_zero_cst (TREE_TYPE (lhs));
+-	      val.mask = extend_mask (nonzero_bits);
++	      val.mask = extend_mask (nonzero_bits, TYPE_SIGN (TREE_TYPE (lhs)));
+ 	      is_constant = true;
+ 	    }
+ 	  else
+@@ -1958,7 +1957,8 @@ evaluate_stmt (gimple *stmt)
+ 	      if (nonzero_bits == 0)
+ 		val.mask = 0;
+ 	      else
+-		val.mask = val.mask & extend_mask (nonzero_bits);
++		val.mask = val.mask & extend_mask (nonzero_bits,
++						   TYPE_SIGN (TREE_TYPE (lhs)));
+ 	    }
+ 	}
+     }
+--- a/src/gcc/tree-ssa-strlen.c
++++ b/src/gcc/tree-ssa-strlen.c
+@@ -2263,7 +2263,7 @@ public:
+ };
+ 
+ /* Callback for walk_dominator_tree.  Attempt to optimize various
+-   string ops by remembering string lenths pointed by pointer SSA_NAMEs.  */
++   string ops by remembering string lengths pointed by pointer SSA_NAMEs.  */
+ 
+ edge
+ strlen_dom_walker::before_dom_children (basic_block bb)
+--- a/src/gcc/tree-vect-data-refs.c
++++ b/src/gcc/tree-vect-data-refs.c
+@@ -2256,6 +2256,7 @@ vect_analyze_group_access_1 (struct data_reference *dr)
+ 	{
+ 	  GROUP_FIRST_ELEMENT (vinfo_for_stmt (stmt)) = stmt;
+ 	  GROUP_SIZE (vinfo_for_stmt (stmt)) = groupsize;
++	  GROUP_GAP (stmt_info) = groupsize - 1;
+ 	  if (dump_enabled_p ())
+ 	    {
+ 	      dump_printf_loc (MSG_NOTE, vect_location,
+--- a/src/gcc/tree-vect-loop-manip.c
++++ b/src/gcc/tree-vect-loop-manip.c
+@@ -40,6 +40,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "cfgloop.h"
+ #include "tree-scalar-evolution.h"
+ #include "tree-vectorizer.h"
++#include "tree-ssa-loop-ivopts.h"
+ 
+ /*************************************************************************
+   Simple Loop Peeling Utilities
+@@ -1593,11 +1594,27 @@ vect_can_advance_ivs_p (loop_vec_info loop_vinfo)
+ 	  return false;
+         }
+ 
++      /* FORNOW: We do not transform initial conditions of IVs
++	 which evolution functions are not invariants in the loop.  */
++
++      if (!expr_invariant_in_loop_p (loop, evolution_part))
++	{
++	  if (dump_enabled_p ())
++	    dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
++			     "evolution not invariant in loop.\n");
++	  return false;
++	}
++
+       /* FORNOW: We do not transform initial conditions of IVs
+ 	 which evolution functions are a polynomial of degree >= 2.  */
+ 
+       if (tree_is_chrec (evolution_part))
+-	return false;
++	{
++	  if (dump_enabled_p ())
++	    dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
++			     "evolution is chrec.\n");
++	  return false;
++	}
+     }
+ 
+   return true;
+--- a/src/gcc/tree-vect-loop.c
++++ b/src/gcc/tree-vect-loop.c
+@@ -1264,9 +1264,9 @@ vect_compute_single_scalar_iteration_cost (loop_vec_info loop_vinfo)
+             continue;
+ 
+ 	  vect_cost_for_stmt kind;
+-          if (STMT_VINFO_DATA_REF (vinfo_for_stmt (stmt)))
++          if (STMT_VINFO_DATA_REF (stmt_info))
+             {
+-              if (DR_IS_READ (STMT_VINFO_DATA_REF (vinfo_for_stmt (stmt))))
++              if (DR_IS_READ (STMT_VINFO_DATA_REF (stmt_info)))
+                kind = scalar_load;
+              else
+                kind = scalar_store;
+@@ -1276,7 +1276,7 @@ vect_compute_single_scalar_iteration_cost (loop_vec_info loop_vinfo)
+ 
+ 	  scalar_single_iter_cost
+ 	    += record_stmt_cost (&LOOP_VINFO_SCALAR_ITERATION_COST (loop_vinfo),
+-				 factor, kind, NULL, 0, vect_prologue);
++				 factor, kind, stmt_info, 0, vect_prologue);
+         }
+     }
+   LOOP_VINFO_SINGLE_SCALAR_ITERATION_COST (loop_vinfo)
+@@ -3072,16 +3072,24 @@ vect_get_known_peeling_cost (loop_vec_info loop_vinfo, int peel_iters_prologue,
+   int j;
+   if (peel_iters_prologue)
+     FOR_EACH_VEC_ELT (*scalar_cost_vec, j, si)
+-      retval += record_stmt_cost (prologue_cost_vec,
+-				  si->count * peel_iters_prologue,
+-				  si->kind, NULL, si->misalign,
+-				  vect_prologue);
++	{
++	  stmt_vec_info stmt_info
++	    = si->stmt ? vinfo_for_stmt (si->stmt) : NULL;
++	  retval += record_stmt_cost (prologue_cost_vec,
++				      si->count * peel_iters_prologue,
++				      si->kind, stmt_info, si->misalign,
++				      vect_prologue);
++	}
+   if (*peel_iters_epilogue)
+     FOR_EACH_VEC_ELT (*scalar_cost_vec, j, si)
+-      retval += record_stmt_cost (epilogue_cost_vec,
+-				  si->count * *peel_iters_epilogue,
+-				  si->kind, NULL, si->misalign,
+-				  vect_epilogue);
++	{
++	  stmt_vec_info stmt_info
++	    = si->stmt ? vinfo_for_stmt (si->stmt) : NULL;
++	  retval += record_stmt_cost (epilogue_cost_vec,
++				      si->count * *peel_iters_epilogue,
++				      si->kind, stmt_info, si->misalign,
++				      vect_epilogue);
++	}
+ 
+   return retval;
+ }
+--- a/src/gcc/tree-vect-patterns.c
++++ b/src/gcc/tree-vect-patterns.c
+@@ -2136,32 +2136,313 @@ vect_recog_vector_vector_shift_pattern (vec<gimple *> *stmts,
+   return pattern_stmt;
+ }
+ 
+-/* Detect multiplication by constant which are postive or negatives of power 2,
+-   and convert them to shift patterns.
++/* Return true iff the target has a vector optab implementing the operation
++   CODE on type VECTYPE.  */
+ 
+-   Mult with constants that are postive power of two.
+-   type a_t;
+-   type b_t
+-   S1: b_t = a_t * n
++static bool
++target_has_vecop_for_code (tree_code code, tree vectype)
++{
++  optab voptab = optab_for_tree_code (code, vectype, optab_vector);
++  return voptab
++	 && optab_handler (voptab, TYPE_MODE (vectype)) != CODE_FOR_nothing;
++}
+ 
+-   or
++/* Verify that the target has optabs of VECTYPE to perform all the steps
++   needed by the multiplication-by-immediate synthesis algorithm described by
++   ALG and VAR.  If SYNTH_SHIFT_P is true ensure that vector addition is
++   present.  Return true iff the target supports all the steps.  */
++
++static bool
++target_supports_mult_synth_alg (struct algorithm *alg, mult_variant var,
++				 tree vectype, bool synth_shift_p)
++{
++  if (alg->op[0] != alg_zero && alg->op[0] != alg_m)
++    return false;
++
++  bool supports_vminus = target_has_vecop_for_code (MINUS_EXPR, vectype);
++  bool supports_vplus = target_has_vecop_for_code (PLUS_EXPR, vectype);
++
++  if (var == negate_variant
++      && !target_has_vecop_for_code (NEGATE_EXPR, vectype))
++    return false;
++
++  /* If we must synthesize shifts with additions make sure that vector
++     addition is available.  */
++  if ((var == add_variant || synth_shift_p) && !supports_vplus)
++    return false;
++
++  for (int i = 1; i < alg->ops; i++)
++    {
++      switch (alg->op[i])
++	{
++	case alg_shift:
++	  break;
++	case alg_add_t_m2:
++	case alg_add_t2_m:
++	case alg_add_factor:
++	  if (!supports_vplus)
++	    return false;
++	  break;
++	case alg_sub_t_m2:
++	case alg_sub_t2_m:
++	case alg_sub_factor:
++	  if (!supports_vminus)
++	    return false;
++	  break;
++	case alg_unknown:
++	case alg_m:
++	case alg_zero:
++	case alg_impossible:
++	  return false;
++	default:
++	  gcc_unreachable ();
++	}
++    }
++
++  return true;
++}
++
++/* Synthesize a left shift of OP by AMNT bits using a series of additions and
++   putting the final result in DEST.  Append all statements but the last into
++   VINFO.  Return the last statement.  */
++
++static gimple *
++synth_lshift_by_additions (tree dest, tree op, HOST_WIDE_INT amnt,
++			   stmt_vec_info vinfo)
++{
++  HOST_WIDE_INT i;
++  tree itype = TREE_TYPE (op);
++  tree prev_res = op;
++  gcc_assert (amnt >= 0);
++  for (i = 0; i < amnt; i++)
++    {
++      tree tmp_var = (i < amnt - 1) ? vect_recog_temp_ssa_var (itype, NULL)
++		      : dest;
++      gimple *stmt
++        = gimple_build_assign (tmp_var, PLUS_EXPR, prev_res, prev_res);
++      prev_res = tmp_var;
++      if (i < amnt - 1)
++	append_pattern_def_seq (vinfo, stmt);
++      else
++	return stmt;
++    }
++  gcc_unreachable ();
++  return NULL;
++}
++
++/* Helper for vect_synth_mult_by_constant.  Apply a binary operation
++   CODE to operands OP1 and OP2, creating a new temporary SSA var in
++   the process if necessary.  Append the resulting assignment statements
++   to the sequence in STMT_VINFO.  Return the SSA variable that holds the
++   result of the binary operation.  If SYNTH_SHIFT_P is true synthesize
++   left shifts using additions.  */
++
++static tree
++apply_binop_and_append_stmt (tree_code code, tree op1, tree op2,
++			     stmt_vec_info stmt_vinfo, bool synth_shift_p)
++{
++  if (integer_zerop (op2)
++      && (code == LSHIFT_EXPR
++	  || code == PLUS_EXPR))
++    {
++      gcc_assert (TREE_CODE (op1) == SSA_NAME);
++      return op1;
++    }
++
++  gimple *stmt;
++  tree itype = TREE_TYPE (op1);
++  tree tmp_var = vect_recog_temp_ssa_var (itype, NULL);
++
++  if (code == LSHIFT_EXPR
++      && synth_shift_p)
++    {
++      stmt = synth_lshift_by_additions (tmp_var, op1, TREE_INT_CST_LOW (op2),
++					 stmt_vinfo);
++      append_pattern_def_seq (stmt_vinfo, stmt);
++      return tmp_var;
++    }
++
++  stmt = gimple_build_assign (tmp_var, code, op1, op2);
++  append_pattern_def_seq (stmt_vinfo, stmt);
++  return tmp_var;
++}
++
++/* Synthesize a multiplication of OP by an INTEGER_CST VAL using shifts
++   and simple arithmetic operations to be vectorized.  Record the statements
++   produced in STMT_VINFO and return the last statement in the sequence or
++   NULL if it's not possible to synthesize such a multiplication.
++   This function mirrors the behavior of expand_mult_const in expmed.c but
++   works on tree-ssa form.  */
++
++static gimple *
++vect_synth_mult_by_constant (tree op, tree val,
++			     stmt_vec_info stmt_vinfo)
++{
++  tree itype = TREE_TYPE (op);
++  machine_mode mode = TYPE_MODE (itype);
++  struct algorithm alg;
++  mult_variant variant;
++  if (!tree_fits_shwi_p (val))
++    return NULL;
++
++  /* Multiplication synthesis by shifts, adds and subs can introduce
++     signed overflow where the original operation didn't.  Perform the
++     operations on an unsigned type and cast back to avoid this.
++     In the future we may want to relax this for synthesis algorithms
++     that we can prove do not cause unexpected overflow.  */
++  bool cast_to_unsigned_p = !TYPE_OVERFLOW_WRAPS (itype);
++
++  tree multtype = cast_to_unsigned_p ? unsigned_type_for (itype) : itype;
++
++  /* Targets that don't support vector shifts but support vector additions
++     can synthesize shifts that way.  */
++  bool synth_shift_p = !vect_supportable_shift (LSHIFT_EXPR, multtype);
++
++  HOST_WIDE_INT hwval = tree_to_shwi (val);
++  /* Use MAX_COST here as we don't want to limit the sequence on rtx costs.
++     The vectorizer's benefit analysis will decide whether it's beneficial
++     to do this.  */
++  bool possible = choose_mult_variant (mode, hwval, &alg,
++					&variant, MAX_COST);
++  if (!possible)
++    return NULL;
+ 
+-   Mult with constants that are negative power of two.
+-   S2: b_t = a_t * -n
++  tree vectype = get_vectype_for_scalar_type (multtype);
++
++  if (!vectype
++      || !target_supports_mult_synth_alg (&alg, variant,
++					   vectype, synth_shift_p))
++    return NULL;
++
++  tree accumulator;
++
++  /* Clear out the sequence of statements so we can populate it below.  */
++  STMT_VINFO_PATTERN_DEF_SEQ (stmt_vinfo) = NULL;
++  gimple *stmt = NULL;
++
++  if (cast_to_unsigned_p)
++    {
++      tree tmp_op = vect_recog_temp_ssa_var (multtype, NULL);
++      stmt = gimple_build_assign (tmp_op, CONVERT_EXPR, op);
++      append_pattern_def_seq (stmt_vinfo, stmt);
++      op = tmp_op;
++    }
++
++  if (alg.op[0] == alg_zero)
++    accumulator = build_int_cst (multtype, 0);
++  else
++    accumulator = op;
++
++  bool needs_fixup = (variant == negate_variant)
++		      || (variant == add_variant);
++
++  for (int i = 1; i < alg.ops; i++)
++    {
++      tree shft_log = build_int_cst (multtype, alg.log[i]);
++      tree accum_tmp = vect_recog_temp_ssa_var (multtype, NULL);
++      tree tmp_var = NULL_TREE;
++
++      switch (alg.op[i])
++	{
++	case alg_shift:
++	  if (synth_shift_p)
++	    stmt
++	      = synth_lshift_by_additions (accum_tmp, accumulator, alg.log[i],
++					    stmt_vinfo);
++	  else
++	    stmt = gimple_build_assign (accum_tmp, LSHIFT_EXPR, accumulator,
++					 shft_log);
++	  break;
++	case alg_add_t_m2:
++	  tmp_var
++	    = apply_binop_and_append_stmt (LSHIFT_EXPR, op, shft_log,
++					    stmt_vinfo, synth_shift_p);
++	  stmt = gimple_build_assign (accum_tmp, PLUS_EXPR, accumulator,
++				       tmp_var);
++	  break;
++	case alg_sub_t_m2:
++	  tmp_var = apply_binop_and_append_stmt (LSHIFT_EXPR, op,
++						  shft_log, stmt_vinfo,
++						  synth_shift_p);
++	  /* In some algorithms the first step involves zeroing the
++	     accumulator.  If subtracting from such an accumulator
++	     just emit the negation directly.  */
++	  if (integer_zerop (accumulator))
++	    stmt = gimple_build_assign (accum_tmp, NEGATE_EXPR, tmp_var);
++	  else
++	    stmt = gimple_build_assign (accum_tmp, MINUS_EXPR, accumulator,
++					tmp_var);
++	  break;
++	case alg_add_t2_m:
++	  tmp_var
++	    = apply_binop_and_append_stmt (LSHIFT_EXPR, accumulator, shft_log,
++					   stmt_vinfo, synth_shift_p);
++	  stmt = gimple_build_assign (accum_tmp, PLUS_EXPR, tmp_var, op);
++	  break;
++	case alg_sub_t2_m:
++	  tmp_var
++	    = apply_binop_and_append_stmt (LSHIFT_EXPR, accumulator, shft_log,
++					   stmt_vinfo, synth_shift_p);
++	  stmt = gimple_build_assign (accum_tmp, MINUS_EXPR, tmp_var, op);
++	  break;
++	case alg_add_factor:
++	  tmp_var
++	    = apply_binop_and_append_stmt (LSHIFT_EXPR, accumulator, shft_log,
++					    stmt_vinfo, synth_shift_p);
++	  stmt = gimple_build_assign (accum_tmp, PLUS_EXPR, accumulator,
++				       tmp_var);
++	  break;
++	case alg_sub_factor:
++	  tmp_var
++	    = apply_binop_and_append_stmt (LSHIFT_EXPR, accumulator, shft_log,
++					   stmt_vinfo, synth_shift_p);
++	  stmt = gimple_build_assign (accum_tmp, MINUS_EXPR, tmp_var,
++				      accumulator);
++	  break;
++	default:
++	  gcc_unreachable ();
++	}
++      /* We don't want to append the last stmt in the sequence to stmt_vinfo
++	 but rather return it directly.  */
++
++      if ((i < alg.ops - 1) || needs_fixup || cast_to_unsigned_p)
++	append_pattern_def_seq (stmt_vinfo, stmt);
++      accumulator = accum_tmp;
++    }
++  if (variant == negate_variant)
++    {
++      tree accum_tmp = vect_recog_temp_ssa_var (multtype, NULL);
++      stmt = gimple_build_assign (accum_tmp, NEGATE_EXPR, accumulator);
++      accumulator = accum_tmp;
++      if (cast_to_unsigned_p)
++	append_pattern_def_seq (stmt_vinfo, stmt);
++    }
++  else if (variant == add_variant)
++    {
++      tree accum_tmp = vect_recog_temp_ssa_var (multtype, NULL);
++      stmt = gimple_build_assign (accum_tmp, PLUS_EXPR, accumulator, op);
++      accumulator = accum_tmp;
++      if (cast_to_unsigned_p)
++	append_pattern_def_seq (stmt_vinfo, stmt);
++    }
++  /* Move back to a signed if needed.  */
++  if (cast_to_unsigned_p)
++    {
++      tree accum_tmp = vect_recog_temp_ssa_var (itype, NULL);
++      stmt = gimple_build_assign (accum_tmp, CONVERT_EXPR, accumulator);
++    }
++
++  return stmt;
++}
++
++/* Detect multiplication by constant and convert it into a sequence of
++   shifts and additions, subtractions, negations.  We reuse the
++   choose_mult_variant algorithms from expmed.c
+ 
+    Input/Output:
+ 
+    STMTS: Contains a stmt from which the pattern search begins,
+-   i.e. the mult stmt.  Convert the mult operation to LSHIFT if
+-   constant operand is a power of 2.
+-   type a_t, b_t
+-   S1': b_t = a_t << log2 (n)
+-
+-   Convert the mult operation to LSHIFT and followed by a NEGATE
+-   if constant operand is a negative power of 2.
+-   type a_t, b_t, res_T;
+-   S2': b_t = a_t << log2 (n)
+-   S3': res_T  = - (b_t)
++   i.e. the mult stmt.
+ 
+  Output:
+ 
+@@ -2169,8 +2450,8 @@ vect_recog_vector_vector_shift_pattern (vec<gimple *> *stmts,
+ 
+   * TYPE_OUT: The type of the output of this pattern.
+ 
+-  * Return value: A new stmt that will be used to replace the multiplication
+-    S1 or S2 stmt.  */
++  * Return value: A new stmt that will be used to replace
++    the multiplication.  */
+ 
+ static gimple *
+ vect_recog_mult_pattern (vec<gimple *> *stmts,
+@@ -2178,11 +2459,8 @@ vect_recog_mult_pattern (vec<gimple *> *stmts,
+ {
+   gimple *last_stmt = stmts->pop ();
+   tree oprnd0, oprnd1, vectype, itype;
+-  gimple *pattern_stmt, *def_stmt;
+-  optab optab;
++  gimple *pattern_stmt;
+   stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt);
+-  int power2_val, power2_neg_val;
+-  tree shift;
+ 
+   if (!is_gimple_assign (last_stmt))
+     return NULL;
+@@ -2206,52 +2484,17 @@ vect_recog_mult_pattern (vec<gimple *> *stmts,
+ 
+   /* If the target can handle vectorized multiplication natively,
+      don't attempt to optimize this.  */
+-  optab = optab_for_tree_code (MULT_EXPR, vectype, optab_default);
+-  if (optab != unknown_optab)
++  optab mul_optab = optab_for_tree_code (MULT_EXPR, vectype, optab_default);
++  if (mul_optab != unknown_optab)
+     {
+       machine_mode vec_mode = TYPE_MODE (vectype);
+-      int icode = (int) optab_handler (optab, vec_mode);
++      int icode = (int) optab_handler (mul_optab, vec_mode);
+       if (icode != CODE_FOR_nothing)
+-	return NULL;
++       return NULL;
+     }
+ 
+-  /* If target cannot handle vector left shift then we cannot
+-     optimize and bail out.  */
+-  optab = optab_for_tree_code (LSHIFT_EXPR, vectype, optab_vector);
+-  if (!optab
+-      || optab_handler (optab, TYPE_MODE (vectype)) == CODE_FOR_nothing)
+-    return NULL;
+-
+-  power2_val = wi::exact_log2 (oprnd1);
+-  power2_neg_val = wi::exact_log2 (wi::neg (oprnd1));
+-
+-  /* Handle constant operands that are postive or negative powers of 2.  */
+-  if (power2_val != -1)
+-    {
+-      shift = build_int_cst (itype, power2_val);
+-      pattern_stmt
+-	= gimple_build_assign (vect_recog_temp_ssa_var (itype, NULL),
+-			       LSHIFT_EXPR, oprnd0, shift);
+-    }
+-  else if (power2_neg_val != -1)
+-    {
+-      /* If the target cannot handle vector NEGATE then we cannot
+-	 do the optimization.  */
+-      optab = optab_for_tree_code (NEGATE_EXPR, vectype, optab_vector);
+-      if (!optab
+-	  || optab_handler (optab, TYPE_MODE (vectype)) == CODE_FOR_nothing)
+-	return NULL;
+-
+-      shift = build_int_cst (itype, power2_neg_val);
+-      def_stmt
+-	= gimple_build_assign (vect_recog_temp_ssa_var (itype, NULL),
+-			       LSHIFT_EXPR, oprnd0, shift);
+-      new_pattern_def_seq (stmt_vinfo, def_stmt);
+-      pattern_stmt
+-	 = gimple_build_assign (vect_recog_temp_ssa_var (itype, NULL),
+-				NEGATE_EXPR, gimple_assign_lhs (def_stmt));
+-    }
+-  else
++  pattern_stmt = vect_synth_mult_by_constant (oprnd0, oprnd1, stmt_vinfo);
++  if (!pattern_stmt)
+     return NULL;
+ 
+   /* Pattern detected.  */
+--- a/src/gcc/tree-vect-stmts.c
++++ b/src/gcc/tree-vect-stmts.c
+@@ -6360,12 +6360,22 @@ vectorizable_load (gimple *stmt, gimple_stmt_iterator *gsi, gimple **vec_stmt,
+       gcc_assert (!nested_in_vect_loop && !STMT_VINFO_GATHER_SCATTER_P (stmt_info));
+ 
+       first_stmt = GROUP_FIRST_ELEMENT (stmt_info);
++      group_size = GROUP_SIZE (vinfo_for_stmt (first_stmt));
++
++      if (!slp
++	  && !PURE_SLP_STMT (stmt_info)
++	  && !STMT_VINFO_STRIDED_P (stmt_info))
++	{
++	  if (vect_load_lanes_supported (vectype, group_size))
++	    load_lanes_p = true;
++	  else if (!vect_grouped_load_supported (vectype, group_size))
++	    return false;
++	}
+ 
+       /* If this is single-element interleaving with an element distance
+          that leaves unused vector loads around punt - we at least create
+ 	 very sub-optimal code in that case (and blow up memory,
+ 	 see PR65518).  */
+-      bool force_peeling = false;
+       if (first_stmt == stmt
+ 	  && !GROUP_NEXT_ELEMENT (stmt_info))
+ 	{
+@@ -6379,7 +6389,7 @@ vectorizable_load (gimple *stmt, gimple_stmt_iterator *gsi, gimple **vec_stmt,
+ 	    }
+ 
+ 	  /* Single-element interleaving requires peeling for gaps.  */
+-	  force_peeling = true;
++	  gcc_assert (GROUP_GAP (stmt_info));
+ 	}
+ 
+       /* If there is a gap in the end of the group or the group size cannot
+@@ -6387,9 +6397,8 @@ vectorizable_load (gimple *stmt, gimple_stmt_iterator *gsi, gimple **vec_stmt,
+ 	 elements in the last iteration and thus need to peel that off.  */
+       if (loop_vinfo
+ 	  && ! STMT_VINFO_STRIDED_P (stmt_info)
+-	  && (force_peeling
+-	      || GROUP_GAP (vinfo_for_stmt (first_stmt)) != 0
+-	      || (!slp && vf % GROUP_SIZE (vinfo_for_stmt (first_stmt)) != 0)))
++	  && (GROUP_GAP (vinfo_for_stmt (first_stmt)) != 0
++	      || (!slp && !load_lanes_p && vf % group_size != 0)))
+ 	{
+ 	  if (dump_enabled_p ())
+ 	    dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
+@@ -6409,8 +6418,6 @@ vectorizable_load (gimple *stmt, gimple_stmt_iterator *gsi, gimple **vec_stmt,
+       if (slp && SLP_TREE_LOAD_PERMUTATION (slp_node).exists ())
+ 	slp_perm = true;
+ 
+-      group_size = GROUP_SIZE (vinfo_for_stmt (first_stmt));
+-
+       /* ???  The following is overly pessimistic (as well as the loop
+          case above) in the case we can statically determine the excess
+ 	 elements loaded are within the bounds of a decl that is accessed.
+@@ -6423,16 +6430,6 @@ vectorizable_load (gimple *stmt, gimple_stmt_iterator *gsi, gimple **vec_stmt,
+ 	  return false;
+ 	}
+ 
+-      if (!slp
+-	  && !PURE_SLP_STMT (stmt_info)
+-	  && !STMT_VINFO_STRIDED_P (stmt_info))
+-	{
+-	  if (vect_load_lanes_supported (vectype, group_size))
+-	    load_lanes_p = true;
+-	  else if (!vect_grouped_load_supported (vectype, group_size))
+-	    return false;
+-	}
+-
+       /* Invalidate assumptions made by dependence analysis when vectorization
+ 	 on the unrolled body effectively re-orders stmts.  */
+       if (!PURE_SLP_STMT (stmt_info)
+--- a/src/gcc/tree-vectorizer.c
++++ b/src/gcc/tree-vectorizer.c
+@@ -794,38 +794,142 @@ make_pass_slp_vectorize (gcc::context *ctxt)
+      This should involve global alignment analysis and in the future also
+      array padding.  */
+ 
++static unsigned get_vec_alignment_for_type (tree);
++static hash_map<tree, unsigned> *type_align_map;
++
++/* Return alignment of array's vector type corresponding to scalar type.
++   0 if no vector type exists.  */
++static unsigned
++get_vec_alignment_for_array_type (tree type) 
++{
++  gcc_assert (TREE_CODE (type) == ARRAY_TYPE);
++
++  tree vectype = get_vectype_for_scalar_type (strip_array_types (type));
++  if (!vectype
++      || !TYPE_SIZE (type)
++      || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST
++      || tree_int_cst_lt (TYPE_SIZE (type), TYPE_SIZE (vectype)))
++    return 0;
++
++  return TYPE_ALIGN (vectype);
++}
++
++/* Return alignment of field having maximum alignment of vector type
++   corresponding to it's scalar type. For now, we only consider fields whose
++   offset is a multiple of it's vector alignment.
++   0 if no suitable field is found.  */
++static unsigned
++get_vec_alignment_for_record_type (tree type) 
++{
++  gcc_assert (TREE_CODE (type) == RECORD_TYPE);
++
++  unsigned max_align = 0, alignment;
++  HOST_WIDE_INT offset;
++  tree offset_tree;
++
++  if (TYPE_PACKED (type))
++    return 0;
++
++  unsigned *slot = type_align_map->get (type);
++  if (slot)
++    return *slot;
++
++  for (tree field = first_field (type);
++       field != NULL_TREE;
++       field = DECL_CHAIN (field))
++    {
++      /* Skip if not FIELD_DECL or if alignment is set by user.  */ 
++      if (TREE_CODE (field) != FIELD_DECL
++	  || DECL_USER_ALIGN (field)
++	  || DECL_ARTIFICIAL (field))
++	continue;
++
++      /* We don't need to process the type further if offset is variable,
++	 since the offsets of remaining members will also be variable.  */
++      if (TREE_CODE (DECL_FIELD_OFFSET (field)) != INTEGER_CST
++	  || TREE_CODE (DECL_FIELD_BIT_OFFSET (field)) != INTEGER_CST)
++	break;
++
++      /* Similarly stop processing the type if offset_tree
++	 does not fit in unsigned HOST_WIDE_INT.  */
++      offset_tree = bit_position (field);
++      if (!tree_fits_uhwi_p (offset_tree))
++	break;
++
++      offset = tree_to_uhwi (offset_tree); 
++      alignment = get_vec_alignment_for_type (TREE_TYPE (field));
++
++      /* Get maximum alignment of vectorized field/array among those members
++	 whose offset is multiple of the vector alignment.  */ 
++      if (alignment
++	  && (offset % alignment == 0)
++	  && (alignment > max_align))
++	max_align = alignment;
++    }
++
++  type_align_map->put (type, max_align);
++  return max_align;
++}
++
++/* Return alignment of vector type corresponding to decl's scalar type
++   or 0 if it doesn't exist or the vector alignment is lesser than
++   decl's alignment.  */
++static unsigned
++get_vec_alignment_for_type (tree type)
++{
++  if (type == NULL_TREE)
++    return 0;
++
++  gcc_assert (TYPE_P (type));
++
++  static unsigned alignment = 0;
++  switch (TREE_CODE (type))
++    {
++      case ARRAY_TYPE:
++	alignment = get_vec_alignment_for_array_type (type);
++	break;
++      case RECORD_TYPE:
++	alignment = get_vec_alignment_for_record_type (type);
++	break;
++      default:
++	alignment = 0;
++	break;
++    }
++
++  return (alignment > TYPE_ALIGN (type)) ? alignment : 0;
++}
++
++/* Entry point to increase_alignment pass.  */
+ static unsigned int
+ increase_alignment (void)
+ {
+   varpool_node *vnode;
+ 
+   vect_location = UNKNOWN_LOCATION;
++  type_align_map = new hash_map<tree, unsigned>;
+ 
+   /* Increase the alignment of all global arrays for vectorization.  */
+   FOR_EACH_DEFINED_VARIABLE (vnode)
+     {
+-      tree vectype, decl = vnode->decl;
+-      tree t;
++      tree decl = vnode->decl;
+       unsigned int alignment;
+ 
+-      t = TREE_TYPE (decl);
+-      if (TREE_CODE (t) != ARRAY_TYPE)
+-        continue;
+-      vectype = get_vectype_for_scalar_type (strip_array_types (t));
+-      if (!vectype)
+-        continue;
+-      alignment = TYPE_ALIGN (vectype);
+-      if (DECL_ALIGN (decl) >= alignment)
+-        continue;
+-
+-      if (vect_can_force_dr_alignment_p (decl, alignment))
++      if ((decl_in_symtab_p (decl)
++	  && !symtab_node::get (decl)->can_increase_alignment_p ())
++	  || DECL_USER_ALIGN (decl) || DECL_ARTIFICIAL (decl))
++	continue;
++
++      alignment = get_vec_alignment_for_type (TREE_TYPE (decl));
++      if (alignment && vect_can_force_dr_alignment_p (decl, alignment))
+         {
+-	  vnode->increase_alignment (TYPE_ALIGN (vectype));
++	  vnode->increase_alignment (alignment);
+           dump_printf (MSG_NOTE, "Increasing alignment of decl: ");
+           dump_generic_expr (MSG_NOTE, TDF_SLIM, decl);
+           dump_printf (MSG_NOTE, "\n");
+         }
+     }
++
++  delete type_align_map;
+   return 0;
+ }
+ 
+--- a/src/gcc/tree-vrp.c
++++ b/src/gcc/tree-vrp.c
+@@ -3191,6 +3191,24 @@ extract_range_from_binary_expr_1 (value_range *vr,
+ 	  if (int_cst_range1 && tree_int_cst_sgn (vr1.min) >= 0)
+ 	    wmax = wi::min (wmax, vr1.max, TYPE_SIGN (expr_type));
+ 	  max = wide_int_to_tree (expr_type, wmax);
++	  cmp = compare_values (min, max);
++	  /* PR68217: In case of signed & sign-bit-CST should
++	     result in [-INF, 0] instead of [-INF, INF].  */
++	  if (cmp == -2 || cmp == 1)
++	    {
++	      wide_int sign_bit
++		= wi::set_bit_in_zero (TYPE_PRECISION (expr_type) - 1,
++				       TYPE_PRECISION (expr_type));
++	      if (!TYPE_UNSIGNED (expr_type)
++		  && ((value_range_constant_singleton (&vr0)
++		       && !wi::cmps (vr0.min, sign_bit))
++		      || (value_range_constant_singleton (&vr1)
++			  && !wi::cmps (vr1.min, sign_bit))))
++		{
++		  min = TYPE_MIN_VALUE (expr_type);
++		  max = build_int_cst (expr_type, 0);
++		}
++	    }
+ 	}
+       else if (code == BIT_IOR_EXPR)
+ 	{
+@@ -3885,7 +3903,8 @@ extract_range_basic (value_range *vr, gimple *stmt)
+ 	  arg = gimple_call_arg (stmt, 0);
+ 	  if (TREE_CODE (arg) == SSA_NAME
+ 	      && SSA_NAME_IS_DEFAULT_DEF (arg)
+-	      && TREE_CODE (SSA_NAME_VAR (arg)) == PARM_DECL)
++	      && TREE_CODE (SSA_NAME_VAR (arg)) == PARM_DECL
++	      && cfun->after_inlining)
+ 	    {
+ 	      set_value_range_to_null (vr, type);
+ 	      return;
+@@ -9961,6 +9980,40 @@ simplify_internal_call_using_ranges (gimple_stmt_iterator *gsi, gimple *stmt)
+   return true;
+ }
+ 
++/* Return true if VAR is a two-valued variable.  Set a and b with the
++   two-values when it is true.  Return false otherwise.  */
++
++static bool
++two_valued_val_range_p (tree var, tree *a, tree *b)
++{
++  value_range *vr = get_value_range (var);
++  if ((vr->type != VR_RANGE
++       && vr->type != VR_ANTI_RANGE)
++      || TREE_CODE (vr->min) != INTEGER_CST
++      || TREE_CODE (vr->max) != INTEGER_CST)
++    return false;
++
++  if (vr->type == VR_RANGE
++      && wi::sub (vr->max, vr->min) == 1)
++    {
++      *a = vr->min;
++      *b = vr->max;
++      return true;
++    }
++
++  /* ~[TYPE_MIN + 1, TYPE_MAX - 1] */
++  if (vr->type == VR_ANTI_RANGE
++      && wi::sub (vr->min, vrp_val_min (TREE_TYPE (var))) == 1
++      && wi::sub (vrp_val_max (TREE_TYPE (var)), vr->max) == 1)
++    {
++      *a = vrp_val_min (TREE_TYPE (var));
++      *b = vrp_val_max (TREE_TYPE (var));
++      return true;
++    }
++
++  return false;
++}
++
+ /* Simplify STMT using ranges if possible.  */
+ 
+ static bool
+@@ -9971,6 +10024,68 @@ simplify_stmt_using_ranges (gimple_stmt_iterator *gsi)
+     {
+       enum tree_code rhs_code = gimple_assign_rhs_code (stmt);
+       tree rhs1 = gimple_assign_rhs1 (stmt);
++      tree rhs2 = gimple_assign_rhs2 (stmt);
++      tree lhs = gimple_assign_lhs (stmt);
++      tree val1 = NULL_TREE, val2 = NULL_TREE;
++      use_operand_p use_p;
++      gimple *use_stmt;
++
++      /* Convert:
++	 LHS = CST BINOP VAR
++	 Where VAR is two-valued and LHS is used in GIMPLE_COND only
++	 To:
++	 LHS = VAR == VAL1 ? (CST BINOP VAL1) : (CST BINOP VAL2)
++
++	 Also handles:
++	 LHS = VAR BINOP CST
++	 Where VAR is two-valued and LHS is used in GIMPLE_COND only
++	 To:
++	 LHS = VAR == VAL1 ? (VAL1 BINOP CST) : (VAL2 BINOP CST) */
++
++      if (TREE_CODE_CLASS (rhs_code) == tcc_binary
++	  && INTEGRAL_TYPE_P (TREE_TYPE (lhs))
++	  && ((TREE_CODE (rhs1) == INTEGER_CST
++	       && TREE_CODE (rhs2) == SSA_NAME)
++	      || (TREE_CODE (rhs2) == INTEGER_CST
++		  && TREE_CODE (rhs1) == SSA_NAME))
++	  && single_imm_use (lhs, &use_p, &use_stmt)
++	  && gimple_code (use_stmt) == GIMPLE_COND)
++
++	{
++	  tree new_rhs1 = NULL_TREE;
++	  tree new_rhs2 = NULL_TREE;
++	  tree cmp_var = NULL_TREE;
++
++	  if (TREE_CODE (rhs2) == SSA_NAME
++	      && two_valued_val_range_p (rhs2, &val1, &val2))
++	    {
++	      /* Optimize RHS1 OP [VAL1, VAL2].  */
++	      new_rhs1 = int_const_binop (rhs_code, rhs1, val1);
++	      new_rhs2 = int_const_binop (rhs_code, rhs1, val2);
++	      cmp_var = rhs2;
++	    }
++	  else if (TREE_CODE (rhs1) == SSA_NAME
++		   && two_valued_val_range_p (rhs1, &val1, &val2))
++	    {
++	      /* Optimize [VAL1, VAL2] OP RHS2.  */
++	      new_rhs1 = int_const_binop (rhs_code, val1, rhs2);
++	      new_rhs2 = int_const_binop (rhs_code, val2, rhs2);
++	      cmp_var = rhs1;
++	    }
++
++	  /* If we could not find two-vals or the optimzation is invalid as
++	     in divide by zero, new_rhs1 / new_rhs will be NULL_TREE.  */
++	  if (new_rhs1 && new_rhs2)
++	    {
++	      tree cond = build2 (EQ_EXPR, TREE_TYPE (cmp_var), cmp_var, val1);
++	      gimple_assign_set_rhs_with_ops (gsi,
++					      COND_EXPR, cond,
++					      new_rhs1,
++					      new_rhs2);
++	      update_stmt (gsi_stmt (*gsi));
++	      return true;
++	    }
++	}
+ 
+       switch (rhs_code)
+ 	{
+--- a/src/gcc/tree.h
++++ b/src/gcc/tree.h
+@@ -4628,69 +4628,6 @@ extern void warn_deprecated_use (tree, tree);
+ extern void cache_integer_cst (tree);
+ extern const char *combined_fn_name (combined_fn);
+ 
+-/* Return the memory model from a host integer.  */
+-static inline enum memmodel
+-memmodel_from_int (unsigned HOST_WIDE_INT val)
+-{
+-  return (enum memmodel) (val & MEMMODEL_MASK);
+-}
+-
+-/* Return the base memory model from a host integer.  */
+-static inline enum memmodel
+-memmodel_base (unsigned HOST_WIDE_INT val)
+-{
+-  return (enum memmodel) (val & MEMMODEL_BASE_MASK);
+-}
+-
+-/* Return TRUE if the memory model is RELAXED.  */
+-static inline bool
+-is_mm_relaxed (enum memmodel model)
+-{
+-  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_RELAXED;
+-}
+-
+-/* Return TRUE if the memory model is CONSUME.  */
+-static inline bool
+-is_mm_consume (enum memmodel model)
+-{
+-  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_CONSUME;
+-}
+-
+-/* Return TRUE if the memory model is ACQUIRE.  */
+-static inline bool
+-is_mm_acquire (enum memmodel model)
+-{
+-  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_ACQUIRE;
+-}
+-
+-/* Return TRUE if the memory model is RELEASE.  */
+-static inline bool
+-is_mm_release (enum memmodel model)
+-{
+-  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_RELEASE;
+-}
+-
+-/* Return TRUE if the memory model is ACQ_REL.  */
+-static inline bool
+-is_mm_acq_rel (enum memmodel model)
+-{
+-  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_ACQ_REL;
+-}
+-
+-/* Return TRUE if the memory model is SEQ_CST.  */
+-static inline bool
+-is_mm_seq_cst (enum memmodel model)
+-{
+-  return (model & MEMMODEL_BASE_MASK) == MEMMODEL_SEQ_CST;
+-}
+-
+-/* Return TRUE if the memory model is a SYNC variant.  */
+-static inline bool
+-is_mm_sync (enum memmodel model)
+-{
+-  return (model & MEMMODEL_SYNC);
+-}
+-
+ /* Compare and hash for any structure which begins with a canonical
+    pointer.  Assumes all pointers are interchangeable, which is sort
+    of already assumed by gcc elsewhere IIRC.  */
+--- a/src/gcc/tsan.c
++++ b/src/gcc/tsan.c
+@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3.  If not see
+ #include "backend.h"
+ #include "rtl.h"
+ #include "tree.h"
++#include "memmodel.h"
+ #include "gimple.h"
+ #include "tree-pass.h"
+ #include "ssa.h"
+--- a/src/gcc/varasm.c
++++ b/src/gcc/varasm.c
+@@ -6243,6 +6243,7 @@ default_elf_asm_named_section (const char *name, unsigned int flags,
+ 			       tree decl)
+ {
+   char flagchars[10], *f = flagchars;
++  unsigned int numeric_value = 0;
+ 
+   /* If we have already declared this section, we can use an
+      abbreviated form to switch back to it -- unless this section is
+@@ -6255,27 +6256,34 @@ default_elf_asm_named_section (const char *name, unsigned int flags,
+       return;
+     }
+ 
+-  if (!(flags & SECTION_DEBUG))
+-    *f++ = 'a';
++  /* If we have a machine specific flag, then use the numeric value to pass
++     this on to GAS.  */
++  if (targetm.asm_out.elf_flags_numeric (flags, &numeric_value))
++      snprintf (f, sizeof (flagchars), "0x%08x", numeric_value);
++  else
++    {
++      if (!(flags & SECTION_DEBUG))
++	*f++ = 'a';
+ #if defined (HAVE_GAS_SECTION_EXCLUDE) && HAVE_GAS_SECTION_EXCLUDE == 1
+-  if (flags & SECTION_EXCLUDE)
+-    *f++ = 'e';
++      if (flags & SECTION_EXCLUDE)
++	*f++ = 'e';
+ #endif
+-  if (flags & SECTION_WRITE)
+-    *f++ = 'w';
+-  if (flags & SECTION_CODE)
+-    *f++ = 'x';
+-  if (flags & SECTION_SMALL)
+-    *f++ = 's';
+-  if (flags & SECTION_MERGE)
+-    *f++ = 'M';
+-  if (flags & SECTION_STRINGS)
+-    *f++ = 'S';
+-  if (flags & SECTION_TLS)
+-    *f++ = TLS_SECTION_ASM_FLAG;
+-  if (HAVE_COMDAT_GROUP && (flags & SECTION_LINKONCE))
+-    *f++ = 'G';
+-  *f = '\0';
++      if (flags & SECTION_WRITE)
++	*f++ = 'w';
++      if (flags & SECTION_CODE)
++	*f++ = 'x';
++      if (flags & SECTION_SMALL)
++	*f++ = 's';
++      if (flags & SECTION_MERGE)
++	*f++ = 'M';
++      if (flags & SECTION_STRINGS)
++	*f++ = 'S';
++      if (flags & SECTION_TLS)
++	*f++ = TLS_SECTION_ASM_FLAG;
++      if (HAVE_COMDAT_GROUP && (flags & SECTION_LINKONCE))
++	*f++ = 'G';
++      *f = '\0';
++    }
+ 
+   fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
+ 
+@@ -6776,6 +6784,16 @@ default_use_anchors_for_symbol_p (const_rtx symbol)
+ 	 sections that should be marked as small in the section directive.  */
+       if (targetm.in_small_data_p (decl))
+ 	return false;
++
++      /* Don't use section anchors for decls that won't fit inside a single
++	 anchor range to reduce the amount of instructions required to refer
++	 to the entire declaration.  */
++      if (DECL_SIZE_UNIT (decl) == NULL_TREE
++	  || !tree_fits_uhwi_p (DECL_SIZE_UNIT (decl))
++	  || (tree_to_uhwi (DECL_SIZE_UNIT (decl))
++	      >= (unsigned HOST_WIDE_INT) targetm.max_anchor_offset))
++	return false;
++
+     }
+   return true;
+ }
+--- a/src/intl/configure
++++ b/src/intl/configure
+@@ -609,6 +609,8 @@ CATOBJEXT
+ USE_INCLUDED_LIBINTL
+ BUILD_INCLUDED_LIBINTL
+ INTLBISON
++LTLIBICONV
++LIBICONV
+ GLIBC21
+ ALLOCA
+ EGREP
+@@ -682,9 +684,9 @@ ac_subst_files=''
+ ac_user_opts='
+ enable_option_checking
+ enable_nls
+-with_libiconv_prefix
+ with_gnu_ld
+ enable_rpath
++with_libiconv_prefix
+ with_included_gettext
+ with_libintl_prefix
+ enable_maintainer_mode
+@@ -1317,9 +1319,9 @@ Optional Features:
+ Optional Packages:
+   --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
+   --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
+-  --with-libiconv-prefix=DIR
+-                          search for libiconv in DIR/include and DIR/lib
+   --with-gnu-ld           assume the C compiler uses GNU ld default=no
++  --with-libiconv-prefix[=DIR]  search for libiconv in DIR/include and DIR/lib
++  --without-libiconv-prefix     don't search for libiconv in includedir and libdir
+   --with-included-gettext use the GNU gettext library included here
+   --with-libintl-prefix[=DIR]  search for libintl in DIR/include and DIR/lib
+   --without-libintl-prefix     don't search for libintl in includedir and libdir
+@@ -4847,136 +4849,658 @@ _ACEOF
+   fi
+ 
+ 
++      if test "X$prefix" = "XNONE"; then
++    acl_final_prefix="$ac_default_prefix"
++  else
++    acl_final_prefix="$prefix"
++  fi
++  if test "X$exec_prefix" = "XNONE"; then
++    acl_final_exec_prefix='${prefix}'
++  else
++    acl_final_exec_prefix="$exec_prefix"
++  fi
++  acl_save_prefix="$prefix"
++  prefix="$acl_final_prefix"
++  eval acl_final_exec_prefix=\"$acl_final_exec_prefix\"
++  prefix="$acl_save_prefix"
+ 
+-  for ac_header in argz.h limits.h locale.h nl_types.h malloc.h stddef.h \
+-stdlib.h string.h unistd.h sys/param.h
+-do :
+-  as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+-ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default"
+-eval as_val=\$$as_ac_Header
+-   if test "x$as_val" = x""yes; then :
+-  cat >>confdefs.h <<_ACEOF
+-#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+-_ACEOF
+ 
++# Check whether --with-gnu-ld was given.
++if test "${with_gnu_ld+set}" = set; then :
++  withval=$with_gnu_ld; test "$withval" = no || with_gnu_ld=yes
++else
++  with_gnu_ld=no
+ fi
+ 
+-done
++# Prepare PATH_SEPARATOR.
++# The user is always right.
++if test "${PATH_SEPARATOR+set}" != set; then
++  echo "#! /bin/sh" >conf$$.sh
++  echo  "exit 0"   >>conf$$.sh
++  chmod +x conf$$.sh
++  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
++    PATH_SEPARATOR=';'
++  else
++    PATH_SEPARATOR=:
++  fi
++  rm -f conf$$.sh
++fi
++ac_prog=ld
++if test "$GCC" = yes; then
++  # Check if gcc -print-prog-name=ld gives a path.
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ld used by GCC" >&5
++$as_echo_n "checking for ld used by GCC... " >&6; }
++  case $host in
++  *-*-mingw*)
++    # gcc leaves a trailing carriage return which upsets mingw
++    ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\015'` ;;
++  *)
++    ac_prog=`($CC -print-prog-name=ld) 2>&5` ;;
++  esac
++  case $ac_prog in
++    # Accept absolute paths.
++    [\\/]* | [A-Za-z]:[\\/]*)
++      re_direlt='/[^/][^/]*/\.\./'
++      # Canonicalize the path of ld
++      ac_prog=`echo $ac_prog| sed 's%\\\\%/%g'`
++      while echo $ac_prog | grep "$re_direlt" > /dev/null 2>&1; do
++	ac_prog=`echo $ac_prog| sed "s%$re_direlt%/%"`
++      done
++      test -z "$LD" && LD="$ac_prog"
++      ;;
++  "")
++    # If it fails, then pretend we aren't using GCC.
++    ac_prog=ld
++    ;;
++  *)
++    # If it is relative, then search for the first ld in PATH.
++    with_gnu_ld=unknown
++    ;;
++  esac
++elif test "$with_gnu_ld" = yes; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for GNU ld" >&5
++$as_echo_n "checking for GNU ld... " >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for non-GNU ld" >&5
++$as_echo_n "checking for non-GNU ld... " >&6; }
++fi
++if test "${acl_cv_path_LD+set}" = set; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -z "$LD"; then
++  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}"
++  for ac_dir in $PATH; do
++    test -z "$ac_dir" && ac_dir=.
++    if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then
++      acl_cv_path_LD="$ac_dir/$ac_prog"
++      # Check to see if the program is GNU ld.  I'd rather use --version,
++      # but apparently some GNU ld's only accept -v.
++      # Break only if it was the GNU/non-GNU ld that we prefer.
++      if "$acl_cv_path_LD" -v 2>&1 < /dev/null | egrep '(GNU|with BFD)' > /dev/null; then
++	test "$with_gnu_ld" != no && break
++      else
++	test "$with_gnu_ld" != yes && break
++      fi
++    fi
++  done
++  IFS="$ac_save_ifs"
++else
++  acl_cv_path_LD="$LD" # Let the user override the test with a path.
++fi
++fi
+ 
+-  for ac_func in feof_unlocked fgets_unlocked getc_unlocked getcwd getegid \
+-geteuid getgid getuid mempcpy munmap putenv setenv setlocale stpcpy \
+-strcasecmp strdup strtoul tsearch __argz_count __argz_stringify __argz_next \
+-__fsetlocking
+-do :
+-  as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh`
+-ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var"
+-eval as_val=\$$as_ac_var
+-   if test "x$as_val" = x""yes; then :
+-  cat >>confdefs.h <<_ACEOF
+-#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1
+-_ACEOF
++LD="$acl_cv_path_LD"
++if test -n "$LD"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LD" >&5
++$as_echo "$LD" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
++test -z "$LD" && as_fn_error "no acceptable ld found in \$PATH" "$LINENO" 5
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if the linker ($LD) is GNU ld" >&5
++$as_echo_n "checking if the linker ($LD) is GNU ld... " >&6; }
++if test "${acl_cv_prog_gnu_ld+set}" = set; then :
++  $as_echo_n "(cached) " >&6
++else
++  # I'd rather use --version here, but apparently some GNU ld's only accept -v.
++if $LD -v 2>&1 </dev/null | egrep '(GNU|with BFD)' 1>&5; then
++  acl_cv_prog_gnu_ld=yes
++else
++  acl_cv_prog_gnu_ld=no
++fi
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $acl_cv_prog_gnu_ld" >&5
++$as_echo "$acl_cv_prog_gnu_ld" >&6; }
++with_gnu_ld=$acl_cv_prog_gnu_ld
++
++
++
++                                                { $as_echo "$as_me:${as_lineno-$LINENO}: checking for shared library run path origin" >&5
++$as_echo_n "checking for shared library run path origin... " >&6; }
++if test "${acl_cv_rpath+set}" = set; then :
++  $as_echo_n "(cached) " >&6
++else
++
++    CC="$CC" GCC="$GCC" LDFLAGS="$LDFLAGS" LD="$LD" with_gnu_ld="$with_gnu_ld" \
++    ${CONFIG_SHELL-/bin/sh} "$ac_aux_dir/config.rpath" "$host" > conftest.sh
++    . ./conftest.sh
++    rm -f ./conftest.sh
++    acl_cv_rpath=done
+ 
+ fi
+-done
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $acl_cv_rpath" >&5
++$as_echo "$acl_cv_rpath" >&6; }
++  wl="$acl_cv_wl"
++  libext="$acl_cv_libext"
++  shlibext="$acl_cv_shlibext"
++  hardcode_libdir_flag_spec="$acl_cv_hardcode_libdir_flag_spec"
++  hardcode_libdir_separator="$acl_cv_hardcode_libdir_separator"
++  hardcode_direct="$acl_cv_hardcode_direct"
++  hardcode_minus_L="$acl_cv_hardcode_minus_L"
++    # Check whether --enable-rpath was given.
++if test "${enable_rpath+set}" = set; then :
++  enableval=$enable_rpath; :
++else
++  enable_rpath=yes
++fi
++
++
+ 
+ 
+ 
+ 
+ 
++
++    use_additional=yes
++
++  acl_save_prefix="$prefix"
++  prefix="$acl_final_prefix"
++  acl_save_exec_prefix="$exec_prefix"
++  exec_prefix="$acl_final_exec_prefix"
++
++    eval additional_includedir=\"$includedir\"
++    eval additional_libdir=\"$libdir\"
++
++  exec_prefix="$acl_save_exec_prefix"
++  prefix="$acl_save_prefix"
++
++
+ # Check whether --with-libiconv-prefix was given.
+ if test "${with_libiconv_prefix+set}" = set; then :
+   withval=$with_libiconv_prefix;
+-    for dir in `echo "$withval" | tr : ' '`; do
+-      if test -d $dir/include; then LIBICONV_INCLUDE="-I$dir/include"; fi
+-      if test -d $dir/lib; then LIBICONV_LIBDIR="-L$dir/lib"; fi
+-    done
+-
+-fi
++    if test "X$withval" = "Xno"; then
++      use_additional=no
++    else
++      if test "X$withval" = "X"; then
+ 
++  acl_save_prefix="$prefix"
++  prefix="$acl_final_prefix"
++  acl_save_exec_prefix="$exec_prefix"
++  exec_prefix="$acl_final_exec_prefix"
+ 
+-  BUILD_LIBICONV_LIBDIRS="../libiconv/lib/.libs ../libiconv/lib/_libs"
+-  BUILD_LIBICONV_INCLUDE="-I../libiconv/include"
++          eval additional_includedir=\"$includedir\"
++          eval additional_libdir=\"$libdir\"
+ 
+-  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for iconv" >&5
+-$as_echo_n "checking for iconv... " >&6; }
+-if test "${am_cv_func_iconv+set}" = set; then :
+-  $as_echo_n "(cached) " >&6
+-else
++  exec_prefix="$acl_save_exec_prefix"
++  prefix="$acl_save_prefix"
+ 
+-    am_cv_func_iconv="no, consider installing GNU libiconv"
+-    am_cv_lib_iconv=no
+-    am_cv_use_build_libiconv=no
+-    am_cv_build_libiconv_path=
++      else
++        additional_includedir="$withval/include"
++        additional_libdir="$withval/lib"
++      fi
++    fi
+ 
+-    # First, try to find iconv in libc.
+-    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+-/* end confdefs.h.  */
+-#include <stdlib.h>
+-#include <iconv.h>
+-int
+-main ()
+-{
+-iconv_t cd = iconv_open("","");
+-         iconv(cd,NULL,NULL,NULL,NULL);
+-         iconv_close(cd);
+-  ;
+-  return 0;
+-}
+-_ACEOF
+-if ac_fn_c_try_link "$LINENO"; then :
+-  am_cv_func_iconv=yes
+ fi
+-rm -f core conftest.err conftest.$ac_objext \
+-    conftest$ac_exeext conftest.$ac_ext
+ 
+-    # If libiconv is part of the build tree, then try using it over
+-    # any system libiconv.
+-    if test "$am_cv_func_iconv" != yes && test -d ../libiconv; then
+-      for lib_dir in $BUILD_LIBICONV_LIBDIRS; do
+-        am_save_LIBS="$LIBS"
+-        am_save_CPPFLAGS="$CPPFLAGS"
+-        LIBS="$LIBS $lib_dir/libiconv.a"
+-        CPPFLAGS="$CPPFLAGS $BUILD_LIBICONV_INCLUDE"
+-        cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+-/* end confdefs.h.  */
+-#include <stdlib.h>
+-#include <iconv.h>
+-int
+-main ()
+-{
+-iconv_t cd = iconv_open("","");
+-           iconv(cd,NULL,NULL,NULL,NULL);
+-           iconv_close(cd);
+-  ;
+-  return 0;
+-}
+-_ACEOF
+-if ac_fn_c_try_link "$LINENO"; then :
+-  am_cv_use_build_libiconv=yes
+-          am_cv_build_libiconv_path=$lib_dir/libiconv.a
+-          am_cv_lib_iconv=yes
+-          am_cv_func_iconv=yes
++      LIBICONV=
++  LTLIBICONV=
++  INCICONV=
++  rpathdirs=
++  ltrpathdirs=
++  names_already_handled=
++  names_next_round='iconv '
++  while test -n "$names_next_round"; do
++    names_this_round="$names_next_round"
++    names_next_round=
++    for name in $names_this_round; do
++      already_handled=
++      for n in $names_already_handled; do
++        if test "$n" = "$name"; then
++          already_handled=yes
++          break
++        fi
++      done
++      if test -z "$already_handled"; then
++        names_already_handled="$names_already_handled $name"
++                        uppername=`echo "$name" | sed -e 'y|abcdefghijklmnopqrstuvwxyz./-|ABCDEFGHIJKLMNOPQRSTUVWXYZ___|'`
++        eval value=\"\$HAVE_LIB$uppername\"
++        if test -n "$value"; then
++          if test "$value" = yes; then
++            eval value=\"\$LIB$uppername\"
++            test -z "$value" || LIBICONV="${LIBICONV}${LIBICONV:+ }$value"
++            eval value=\"\$LTLIB$uppername\"
++            test -z "$value" || LTLIBICONV="${LTLIBICONV}${LTLIBICONV:+ }$value"
++          else
++                                    :
++          fi
++        else
++                              found_dir=
++          found_la=
++          found_so=
++          found_a=
++          if test $use_additional = yes; then
++            if test -n "$shlibext" && test -f "$additional_libdir/lib$name.$shlibext"; then
++              found_dir="$additional_libdir"
++              found_so="$additional_libdir/lib$name.$shlibext"
++              if test -f "$additional_libdir/lib$name.la"; then
++                found_la="$additional_libdir/lib$name.la"
++              fi
++            else
++              if test -f "$additional_libdir/lib$name.$libext"; then
++                found_dir="$additional_libdir"
++                found_a="$additional_libdir/lib$name.$libext"
++                if test -f "$additional_libdir/lib$name.la"; then
++                  found_la="$additional_libdir/lib$name.la"
++                fi
++              fi
++            fi
++          fi
++          if test "X$found_dir" = "X"; then
++            for x in $LDFLAGS $LTLIBICONV; do
++
++  acl_save_prefix="$prefix"
++  prefix="$acl_final_prefix"
++  acl_save_exec_prefix="$exec_prefix"
++  exec_prefix="$acl_final_exec_prefix"
++  eval x=\"$x\"
++  exec_prefix="$acl_save_exec_prefix"
++  prefix="$acl_save_prefix"
++
++              case "$x" in
++                -L*)
++                  dir=`echo "X$x" | sed -e 's/^X-L//'`
++                  if test -n "$shlibext" && test -f "$dir/lib$name.$shlibext"; then
++                    found_dir="$dir"
++                    found_so="$dir/lib$name.$shlibext"
++                    if test -f "$dir/lib$name.la"; then
++                      found_la="$dir/lib$name.la"
++                    fi
++                  else
++                    if test -f "$dir/lib$name.$libext"; then
++                      found_dir="$dir"
++                      found_a="$dir/lib$name.$libext"
++                      if test -f "$dir/lib$name.la"; then
++                        found_la="$dir/lib$name.la"
++                      fi
++                    fi
++                  fi
++                  ;;
++              esac
++              if test "X$found_dir" != "X"; then
++                break
++              fi
++            done
++          fi
++          if test "X$found_dir" != "X"; then
++                        LTLIBICONV="${LTLIBICONV}${LTLIBICONV:+ }-L$found_dir -l$name"
++            if test "X$found_so" != "X"; then
++                                                        if test "$enable_rpath" = no || test "X$found_dir" = "X/usr/lib"; then
++                                LIBICONV="${LIBICONV}${LIBICONV:+ }$found_so"
++              else
++                                                                                haveit=
++                for x in $ltrpathdirs; do
++                  if test "X$x" = "X$found_dir"; then
++                    haveit=yes
++                    break
++                  fi
++                done
++                if test -z "$haveit"; then
++                  ltrpathdirs="$ltrpathdirs $found_dir"
++                fi
++                                if test "$hardcode_direct" = yes; then
++                                                      LIBICONV="${LIBICONV}${LIBICONV:+ }$found_so"
++                else
++                  if test -n "$hardcode_libdir_flag_spec" && test "$hardcode_minus_L" = no; then
++                                                            LIBICONV="${LIBICONV}${LIBICONV:+ }$found_so"
++                                                            haveit=
++                    for x in $rpathdirs; do
++                      if test "X$x" = "X$found_dir"; then
++                        haveit=yes
++                        break
++                      fi
++                    done
++                    if test -z "$haveit"; then
++                      rpathdirs="$rpathdirs $found_dir"
++                    fi
++                  else
++                                                                                haveit=
++                    for x in $LDFLAGS $LIBICONV; do
++
++  acl_save_prefix="$prefix"
++  prefix="$acl_final_prefix"
++  acl_save_exec_prefix="$exec_prefix"
++  exec_prefix="$acl_final_exec_prefix"
++  eval x=\"$x\"
++  exec_prefix="$acl_save_exec_prefix"
++  prefix="$acl_save_prefix"
++
++                      if test "X$x" = "X-L$found_dir"; then
++                        haveit=yes
++                        break
++                      fi
++                    done
++                    if test -z "$haveit"; then
++                      LIBICONV="${LIBICONV}${LIBICONV:+ }-L$found_dir"
++                    fi
++                    if test "$hardcode_minus_L" != no; then
++                                                                                        LIBICONV="${LIBICONV}${LIBICONV:+ }$found_so"
++                    else
++                                                                                                                                                                                LIBICONV="${LIBICONV}${LIBICONV:+ }-l$name"
++                    fi
++                  fi
++                fi
++              fi
++            else
++              if test "X$found_a" != "X"; then
++                                LIBICONV="${LIBICONV}${LIBICONV:+ }$found_a"
++              else
++                                                LIBICONV="${LIBICONV}${LIBICONV:+ }-L$found_dir -l$name"
++              fi
++            fi
++                        additional_includedir=
++            case "$found_dir" in
++              */lib | */lib/)
++                basedir=`echo "X$found_dir" | sed -e 's,^X,,' -e 's,/lib/*$,,'`
++                additional_includedir="$basedir/include"
++                ;;
++            esac
++            if test "X$additional_includedir" != "X"; then
++                                                                                                                if test "X$additional_includedir" != "X/usr/include"; then
++                haveit=
++                if test "X$additional_includedir" = "X/usr/local/include"; then
++                  if test -n "$GCC"; then
++                    case $host_os in
++                      linux*) haveit=yes;;
++                    esac
++                  fi
++                fi
++                if test -z "$haveit"; then
++                  for x in $CPPFLAGS $INCICONV; do
++
++  acl_save_prefix="$prefix"
++  prefix="$acl_final_prefix"
++  acl_save_exec_prefix="$exec_prefix"
++  exec_prefix="$acl_final_exec_prefix"
++  eval x=\"$x\"
++  exec_prefix="$acl_save_exec_prefix"
++  prefix="$acl_save_prefix"
++
++                    if test "X$x" = "X-I$additional_includedir"; then
++                      haveit=yes
++                      break
++                    fi
++                  done
++                  if test -z "$haveit"; then
++                    if test -d "$additional_includedir"; then
++                                            INCICONV="${INCICONV}${INCICONV:+ }-I$additional_includedir"
++                    fi
++                  fi
++                fi
++              fi
++            fi
++                        if test -n "$found_la"; then
++                                                        save_libdir="$libdir"
++              case "$found_la" in
++                */* | *\\*) . "$found_la" ;;
++                *) . "./$found_la" ;;
++              esac
++              libdir="$save_libdir"
++                            for dep in $dependency_libs; do
++                case "$dep" in
++                  -L*)
++                    additional_libdir=`echo "X$dep" | sed -e 's/^X-L//'`
++                                                                                                                                                                if test "X$additional_libdir" != "X/usr/lib"; then
++                      haveit=
++                      if test "X$additional_libdir" = "X/usr/local/lib"; then
++                        if test -n "$GCC"; then
++                          case $host_os in
++                            linux*) haveit=yes;;
++                          esac
++                        fi
++                      fi
++                      if test -z "$haveit"; then
++                        haveit=
++                        for x in $LDFLAGS $LIBICONV; do
++
++  acl_save_prefix="$prefix"
++  prefix="$acl_final_prefix"
++  acl_save_exec_prefix="$exec_prefix"
++  exec_prefix="$acl_final_exec_prefix"
++  eval x=\"$x\"
++  exec_prefix="$acl_save_exec_prefix"
++  prefix="$acl_save_prefix"
++
++                          if test "X$x" = "X-L$additional_libdir"; then
++                            haveit=yes
++                            break
++                          fi
++                        done
++                        if test -z "$haveit"; then
++                          if test -d "$additional_libdir"; then
++                                                        LIBICONV="${LIBICONV}${LIBICONV:+ }-L$additional_libdir"
++                          fi
++                        fi
++                        haveit=
++                        for x in $LDFLAGS $LTLIBICONV; do
++
++  acl_save_prefix="$prefix"
++  prefix="$acl_final_prefix"
++  acl_save_exec_prefix="$exec_prefix"
++  exec_prefix="$acl_final_exec_prefix"
++  eval x=\"$x\"
++  exec_prefix="$acl_save_exec_prefix"
++  prefix="$acl_save_prefix"
++
++                          if test "X$x" = "X-L$additional_libdir"; then
++                            haveit=yes
++                            break
++                          fi
++                        done
++                        if test -z "$haveit"; then
++                          if test -d "$additional_libdir"; then
++                                                        LTLIBICONV="${LTLIBICONV}${LTLIBICONV:+ }-L$additional_libdir"
++                          fi
++                        fi
++                      fi
++                    fi
++                    ;;
++                  -R*)
++                    dir=`echo "X$dep" | sed -e 's/^X-R//'`
++                    if test "$enable_rpath" != no; then
++                                                                  haveit=
++                      for x in $rpathdirs; do
++                        if test "X$x" = "X$dir"; then
++                          haveit=yes
++                          break
++                        fi
++                      done
++                      if test -z "$haveit"; then
++                        rpathdirs="$rpathdirs $dir"
++                      fi
++                                                                  haveit=
++                      for x in $ltrpathdirs; do
++                        if test "X$x" = "X$dir"; then
++                          haveit=yes
++                          break
++                        fi
++                      done
++                      if test -z "$haveit"; then
++                        ltrpathdirs="$ltrpathdirs $dir"
++                      fi
++                    fi
++                    ;;
++                  -l*)
++                                        names_next_round="$names_next_round "`echo "X$dep" | sed -e 's/^X-l//'`
++                    ;;
++                  *.la)
++                                                                                names_next_round="$names_next_round "`echo "X$dep" | sed -e 's,^X.*/,,' -e 's,^lib,,' -e 's,\.la$,,'`
++                    ;;
++                  *)
++                                        LIBICONV="${LIBICONV}${LIBICONV:+ }$dep"
++                    LTLIBICONV="${LTLIBICONV}${LTLIBICONV:+ }$dep"
++                    ;;
++                esac
++              done
++            fi
++          else
++                                                            LIBICONV="${LIBICONV}${LIBICONV:+ }-l$name"
++            LTLIBICONV="${LTLIBICONV}${LTLIBICONV:+ }-l$name"
++          fi
++        fi
++      fi
++    done
++  done
++  if test "X$rpathdirs" != "X"; then
++    if test -n "$hardcode_libdir_separator"; then
++                        alldirs=
++      for found_dir in $rpathdirs; do
++        alldirs="${alldirs}${alldirs:+$hardcode_libdir_separator}$found_dir"
++      done
++            acl_save_libdir="$libdir"
++      libdir="$alldirs"
++      eval flag=\"$hardcode_libdir_flag_spec\"
++      libdir="$acl_save_libdir"
++      LIBICONV="${LIBICONV}${LIBICONV:+ }$flag"
++    else
++            for found_dir in $rpathdirs; do
++        acl_save_libdir="$libdir"
++        libdir="$found_dir"
++        eval flag=\"$hardcode_libdir_flag_spec\"
++        libdir="$acl_save_libdir"
++        LIBICONV="${LIBICONV}${LIBICONV:+ }$flag"
++      done
++    fi
++  fi
++  if test "X$ltrpathdirs" != "X"; then
++            for found_dir in $ltrpathdirs; do
++      LTLIBICONV="${LTLIBICONV}${LTLIBICONV:+ }-R$found_dir"
++    done
++  fi
++
++
++
++
++  for ac_header in argz.h limits.h locale.h nl_types.h malloc.h stddef.h \
++stdlib.h string.h unistd.h sys/param.h
++do :
++  as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
++ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default"
++eval as_val=\$$as_ac_Header
++   if test "x$as_val" = x""yes; then :
++  cat >>confdefs.h <<_ACEOF
++#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
++_ACEOF
++
++fi
++
++done
++
++  for ac_func in feof_unlocked fgets_unlocked getc_unlocked getcwd getegid \
++geteuid getgid getuid mempcpy munmap putenv setenv setlocale stpcpy \
++strcasecmp strdup strtoul tsearch __argz_count __argz_stringify __argz_next \
++__fsetlocking
++do :
++  as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh`
++ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var"
++eval as_val=\$$as_ac_var
++   if test "x$as_val" = x""yes; then :
++  cat >>confdefs.h <<_ACEOF
++#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1
++_ACEOF
++
++fi
++done
++
++
++
++
++
++
++
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for iconv" >&5
++$as_echo_n "checking for iconv... " >&6; }
++if test "${am_cv_func_iconv+set}" = set; then :
++  $as_echo_n "(cached) " >&6
++else
++
++    am_cv_func_iconv="no, consider installing GNU libiconv"
++    am_cv_lib_iconv=no
++                    am_save_CPPFLAGS="$CPPFLAGS"
++    CPPFLAGS="$CPPFLAGS $INCICONV"
++    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <stdlib.h>
++#include <iconv.h>
++int
++main ()
++{
++iconv_t cd = iconv_open("","");
++       iconv(cd,NULL,NULL,NULL,NULL);
++       iconv_close(cd);
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  am_cv_func_iconv=yes
++fi
++rm -f core conftest.err conftest.$ac_objext \
++    conftest$ac_exeext conftest.$ac_ext
++    CPPFLAGS="$am_save_CPPFLAGS"
++
++    if test "$am_cv_func_iconv" != yes && test -d ../libiconv; then
++      for _libs in .libs _libs; do
++        am_save_CPPFLAGS="$CPPFLAGS"
++        am_save_LIBS="$LIBS"
++        CPPFLAGS="$CPPFLAGS -I../libiconv/include"
++        LIBS="$LIBS ../libiconv/lib/$_libs/libiconv.a"
++        cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h.  */
++#include <stdlib.h>
++#include <iconv.h>
++int
++main ()
++{
++iconv_t cd = iconv_open("","");
++           iconv(cd,NULL,NULL,NULL,NULL);
++           iconv_close(cd);
++  ;
++  return 0;
++}
++_ACEOF
++if ac_fn_c_try_link "$LINENO"; then :
++  INCICONV="-I../libiconv/include"
++          LIBICONV='${top_builddir}'/../libiconv/lib/$_libs/libiconv.a
++          LTLIBICONV='${top_builddir}'/../libiconv/lib/libiconv.la
++          am_cv_lib_iconv=yes
++          am_cv_func_iconv=yes
+ fi
+ rm -f core conftest.err conftest.$ac_objext \
+     conftest$ac_exeext conftest.$ac_ext
+-        LIBS="$am_save_LIBS"
+         CPPFLAGS="$am_save_CPPFLAGS"
+-        if test "$am_cv_use_build_libiconv" = "yes"; then
++        LIBS="$am_save_LIBS"
++        if test "$am_cv_func_iconv" = "yes"; then
+           break
+         fi
+       done
+     fi
+ 
+-    # If iconv was not in libc, try -liconv.  In this case, arrange to
+-    # look in the libiconv prefix, if it was specified by the user.
+     if test "$am_cv_func_iconv" != yes; then
+       am_save_CPPFLAGS="$CPPFLAGS"
+       am_save_LIBS="$LIBS"
+-      if test -n "$LIBICONV_INCLUDE"; then
+-        CPPFLAGS="$CPPFLAGS $LIBICONV_INCLUDE"
+-        LIBS="$LIBS $LIBICONV_LIBDIR"
+-      fi
+-      LIBS="$LIBS -liconv"
++      CPPFLAGS="$LIBS $INCICONV"
++      LIBS="$LIBS $LIBICONV"
+       cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+ /* end confdefs.h.  */
+ #include <stdlib.h>
+@@ -4997,35 +5521,54 @@ if ac_fn_c_try_link "$LINENO"; then :
+ fi
+ rm -f core conftest.err conftest.$ac_objext \
+     conftest$ac_exeext conftest.$ac_ext
+-      LIBS="$am_save_LIBS"
+       CPPFLAGS="$am_save_CPPFLAGS"
++      LIBS="$am_save_LIBS"
+     fi
+ 
+ fi
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_func_iconv" >&5
+ $as_echo "$am_cv_func_iconv" >&6; }
++  if test "$am_cv_func_iconv" = yes; then
++
++$as_echo "#define HAVE_ICONV 1" >>confdefs.h
+ 
+-  # Set the various flags based on the cache variables.  We can't rely
+-  # on the flags to remain set from the above code, due to caching.
+-  LIBICONV=
++  fi
+   if test "$am_cv_lib_iconv" = yes; then
+-    LIBICONV="-liconv"
++
++  for element in $INCICONV; do
++    haveit=
++    for x in $CPPFLAGS; do
++
++  acl_save_prefix="$prefix"
++  prefix="$acl_final_prefix"
++  acl_save_exec_prefix="$exec_prefix"
++  exec_prefix="$acl_final_exec_prefix"
++  eval x=\"$x\"
++  exec_prefix="$acl_save_exec_prefix"
++  prefix="$acl_save_prefix"
++
++      if test "X$x" = "X$element"; then
++        haveit=yes
++        break
++      fi
++    done
++    if test -z "$haveit"; then
++      CPPFLAGS="${CPPFLAGS}${CPPFLAGS:+ }$element"
++    fi
++  done
++
++    { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to link with libiconv" >&5
++$as_echo_n "checking how to link with libiconv... " >&6; }
++    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LIBICONV" >&5
++$as_echo "$LIBICONV" >&6; }
+   else
+-    LIBICONV_LIBDIR=
+-    LIBICONV_INCLUDE=
++    LIBICONV=
++    LTLIBICONV=
+   fi
+-  if test "$am_cv_use_build_libiconv" = yes; then
+-    LIBICONV="$am_cv_build_libiconv_path"
+-    LIBICONV_LIBDIR=""
+-    LIBICONV_INCLUDE="$BUILD_LIBICONV_INCLUDE"
+-  fi
+-  CPPFLAGS="$CPPFLAGS $LIBICONV_INCLUDE"
+-  LIBS="$LIBS $LIBICONV_LIBDIR $LIBICONV"
+ 
+-  if test "$am_cv_func_iconv" = yes; then
+ 
+-$as_echo "#define HAVE_ICONV 1" >>confdefs.h
+ 
++  if test "$am_cv_func_iconv" = yes; then
+     { $as_echo "$as_me:${as_lineno-$LINENO}: checking for iconv declaration" >&5
+ $as_echo_n "checking for iconv declaration... " >&6; }
+     if test "${am_cv_proto_iconv+set}" = set; then :
+@@ -5208,164 +5751,6 @@ $as_echo "$ac_prog_version" >&6; }
+   fi
+ 
+ 
+-      if test "X$prefix" = "XNONE"; then
+-    acl_final_prefix="$ac_default_prefix"
+-  else
+-    acl_final_prefix="$prefix"
+-  fi
+-  if test "X$exec_prefix" = "XNONE"; then
+-    acl_final_exec_prefix='${prefix}'
+-  else
+-    acl_final_exec_prefix="$exec_prefix"
+-  fi
+-  acl_save_prefix="$prefix"
+-  prefix="$acl_final_prefix"
+-  eval acl_final_exec_prefix=\"$acl_final_exec_prefix\"
+-  prefix="$acl_save_prefix"
+-
+-
+-# Check whether --with-gnu-ld was given.
+-if test "${with_gnu_ld+set}" = set; then :
+-  withval=$with_gnu_ld; test "$withval" = no || with_gnu_ld=yes
+-else
+-  with_gnu_ld=no
+-fi
+-
+-# Prepare PATH_SEPARATOR.
+-# The user is always right.
+-if test "${PATH_SEPARATOR+set}" != set; then
+-  echo "#! /bin/sh" >conf$$.sh
+-  echo  "exit 0"   >>conf$$.sh
+-  chmod +x conf$$.sh
+-  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
+-    PATH_SEPARATOR=';'
+-  else
+-    PATH_SEPARATOR=:
+-  fi
+-  rm -f conf$$.sh
+-fi
+-ac_prog=ld
+-if test "$GCC" = yes; then
+-  # Check if gcc -print-prog-name=ld gives a path.
+-  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ld used by GCC" >&5
+-$as_echo_n "checking for ld used by GCC... " >&6; }
+-  case $host in
+-  *-*-mingw*)
+-    # gcc leaves a trailing carriage return which upsets mingw
+-    ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\015'` ;;
+-  *)
+-    ac_prog=`($CC -print-prog-name=ld) 2>&5` ;;
+-  esac
+-  case $ac_prog in
+-    # Accept absolute paths.
+-    [\\/]* | [A-Za-z]:[\\/]*)
+-      re_direlt='/[^/][^/]*/\.\./'
+-      # Canonicalize the path of ld
+-      ac_prog=`echo $ac_prog| sed 's%\\\\%/%g'`
+-      while echo $ac_prog | grep "$re_direlt" > /dev/null 2>&1; do
+-	ac_prog=`echo $ac_prog| sed "s%$re_direlt%/%"`
+-      done
+-      test -z "$LD" && LD="$ac_prog"
+-      ;;
+-  "")
+-    # If it fails, then pretend we aren't using GCC.
+-    ac_prog=ld
+-    ;;
+-  *)
+-    # If it is relative, then search for the first ld in PATH.
+-    with_gnu_ld=unknown
+-    ;;
+-  esac
+-elif test "$with_gnu_ld" = yes; then
+-  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for GNU ld" >&5
+-$as_echo_n "checking for GNU ld... " >&6; }
+-else
+-  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for non-GNU ld" >&5
+-$as_echo_n "checking for non-GNU ld... " >&6; }
+-fi
+-if test "${acl_cv_path_LD+set}" = set; then :
+-  $as_echo_n "(cached) " >&6
+-else
+-  if test -z "$LD"; then
+-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}"
+-  for ac_dir in $PATH; do
+-    test -z "$ac_dir" && ac_dir=.
+-    if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then
+-      acl_cv_path_LD="$ac_dir/$ac_prog"
+-      # Check to see if the program is GNU ld.  I'd rather use --version,
+-      # but apparently some GNU ld's only accept -v.
+-      # Break only if it was the GNU/non-GNU ld that we prefer.
+-      if "$acl_cv_path_LD" -v 2>&1 < /dev/null | egrep '(GNU|with BFD)' > /dev/null; then
+-	test "$with_gnu_ld" != no && break
+-      else
+-	test "$with_gnu_ld" != yes && break
+-      fi
+-    fi
+-  done
+-  IFS="$ac_save_ifs"
+-else
+-  acl_cv_path_LD="$LD" # Let the user override the test with a path.
+-fi
+-fi
+-
+-LD="$acl_cv_path_LD"
+-if test -n "$LD"; then
+-  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LD" >&5
+-$as_echo "$LD" >&6; }
+-else
+-  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+-$as_echo "no" >&6; }
+-fi
+-test -z "$LD" && as_fn_error "no acceptable ld found in \$PATH" "$LINENO" 5
+-{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if the linker ($LD) is GNU ld" >&5
+-$as_echo_n "checking if the linker ($LD) is GNU ld... " >&6; }
+-if test "${acl_cv_prog_gnu_ld+set}" = set; then :
+-  $as_echo_n "(cached) " >&6
+-else
+-  # I'd rather use --version here, but apparently some GNU ld's only accept -v.
+-if $LD -v 2>&1 </dev/null | egrep '(GNU|with BFD)' 1>&5; then
+-  acl_cv_prog_gnu_ld=yes
+-else
+-  acl_cv_prog_gnu_ld=no
+-fi
+-fi
+-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $acl_cv_prog_gnu_ld" >&5
+-$as_echo "$acl_cv_prog_gnu_ld" >&6; }
+-with_gnu_ld=$acl_cv_prog_gnu_ld
+-
+-
+-
+-                                                { $as_echo "$as_me:${as_lineno-$LINENO}: checking for shared library run path origin" >&5
+-$as_echo_n "checking for shared library run path origin... " >&6; }
+-if test "${acl_cv_rpath+set}" = set; then :
+-  $as_echo_n "(cached) " >&6
+-else
+-
+-    CC="$CC" GCC="$GCC" LDFLAGS="$LDFLAGS" LD="$LD" with_gnu_ld="$with_gnu_ld" \
+-    ${CONFIG_SHELL-/bin/sh} "$ac_aux_dir/config.rpath" "$host" > conftest.sh
+-    . ./conftest.sh
+-    rm -f ./conftest.sh
+-    acl_cv_rpath=done
+-
+-fi
+-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $acl_cv_rpath" >&5
+-$as_echo "$acl_cv_rpath" >&6; }
+-  wl="$acl_cv_wl"
+-  libext="$acl_cv_libext"
+-  shlibext="$acl_cv_shlibext"
+-  hardcode_libdir_flag_spec="$acl_cv_hardcode_libdir_flag_spec"
+-  hardcode_libdir_separator="$acl_cv_hardcode_libdir_separator"
+-  hardcode_direct="$acl_cv_hardcode_direct"
+-  hardcode_minus_L="$acl_cv_hardcode_minus_L"
+-    # Check whether --enable-rpath was given.
+-if test "${enable_rpath+set}" = set; then :
+-  enableval=$enable_rpath; :
+-else
+-  enable_rpath=yes
+-fi
+-
+-
+-
+ 
+ 
+ 
+--- a/src/libcpp/expr.c
++++ b/src/libcpp/expr.c
+@@ -1073,7 +1073,7 @@ eval_token (cpp_reader *pfile, const cpp_token *token,
+ 	  result.low = 0;
+ 	  if (CPP_OPTION (pfile, warn_undef) && !pfile->state.skip_eval)
+ 	    cpp_warning_with_line (pfile, CPP_W_UNDEF, virtual_location, 0,
+-				   "\"%s\" is not defined",
++				   "\"%s\" is not defined, evaluates to 0",
+ 				   NODE_NAME (token->val.node.node));
+ 	}
+       break;
+--- a/src/libcpp/lex.c
++++ b/src/libcpp/lex.c
+@@ -750,6 +750,101 @@ search_line_fast (const uchar *s, const uchar *end ATTRIBUTE_UNUSED)
+   }
+ }
+ 
++#elif defined (__ARM_NEON) && defined (__ARM_64BIT_STATE)
++#include "arm_neon.h"
++
++/* This doesn't have to be the exact page size, but no system may use
++   a size smaller than this.  ARMv8 requires a minimum page size of
++   4k.  The impact of being conservative here is a small number of
++   cases will take the slightly slower entry path into the main
++   loop.  */
++
++#define AARCH64_MIN_PAGE_SIZE 4096
++
++static const uchar *
++search_line_fast (const uchar *s, const uchar *end ATTRIBUTE_UNUSED)
++{
++  const uint8x16_t repl_nl = vdupq_n_u8 ('\n');
++  const uint8x16_t repl_cr = vdupq_n_u8 ('\r');
++  const uint8x16_t repl_bs = vdupq_n_u8 ('\\');
++  const uint8x16_t repl_qm = vdupq_n_u8 ('?');
++  const uint8x16_t xmask = (uint8x16_t) vdupq_n_u64 (0x8040201008040201ULL);
++
++#ifdef __AARCH64EB
++  const int16x8_t shift = {8, 8, 8, 8, 0, 0, 0, 0};
++#else
++  const int16x8_t shift = {0, 0, 0, 0, 8, 8, 8, 8};
++#endif
++
++  unsigned int found;
++  const uint8_t *p;
++  uint8x16_t data;
++  uint8x16_t t;
++  uint16x8_t m;
++  uint8x16_t u, v, w;
++
++  /* Align the source pointer.  */
++  p = (const uint8_t *)((uintptr_t)s & -16);
++
++  /* Assuming random string start positions, with a 4k page size we'll take
++     the slow path about 0.37% of the time.  */
++  if (__builtin_expect ((AARCH64_MIN_PAGE_SIZE
++			 - (((uintptr_t) s) & (AARCH64_MIN_PAGE_SIZE - 1)))
++			< 16, 0))
++    {
++      /* Slow path: the string starts near a possible page boundary.  */
++      uint32_t misalign, mask;
++
++      misalign = (uintptr_t)s & 15;
++      mask = (-1u << misalign) & 0xffff;
++      data = vld1q_u8 (p);
++      t = vceqq_u8 (data, repl_nl);
++      u = vceqq_u8 (data, repl_cr);
++      v = vorrq_u8 (t, vceqq_u8 (data, repl_bs));
++      w = vorrq_u8 (u, vceqq_u8 (data, repl_qm));
++      t = vorrq_u8 (v, w);
++      t = vandq_u8 (t, xmask);
++      m = vpaddlq_u8 (t);
++      m = vshlq_u16 (m, shift);
++      found = vaddvq_u16 (m);
++      found &= mask;
++      if (found)
++	return (const uchar*)p + __builtin_ctz (found);
++    }
++  else
++    {
++      data = vld1q_u8 ((const uint8_t *) s);
++      t = vceqq_u8 (data, repl_nl);
++      u = vceqq_u8 (data, repl_cr);
++      v = vorrq_u8 (t, vceqq_u8 (data, repl_bs));
++      w = vorrq_u8 (u, vceqq_u8 (data, repl_qm));
++      t = vorrq_u8 (v, w);
++      if (__builtin_expect (vpaddd_u64 ((uint64x2_t)t) != 0, 0))
++	goto done;
++    }
++
++  do
++    {
++      p += 16;
++      data = vld1q_u8 (p);
++      t = vceqq_u8 (data, repl_nl);
++      u = vceqq_u8 (data, repl_cr);
++      v = vorrq_u8 (t, vceqq_u8 (data, repl_bs));
++      w = vorrq_u8 (u, vceqq_u8 (data, repl_qm));
++      t = vorrq_u8 (v, w);
++    } while (!vpaddd_u64 ((uint64x2_t)t));
++
++done:
++  /* Now that we've found the terminating substring, work out precisely where
++     we need to stop.  */
++  t = vandq_u8 (t, xmask);
++  m = vpaddlq_u8 (t);
++  m = vshlq_u16 (m, shift);
++  found = vaddvq_u16 (m);
++  return (((((uintptr_t) p) < (uintptr_t) s) ? s : (const uchar *)p)
++	  + __builtin_ctz (found));
++}
++
+ #elif defined (__ARM_NEON)
+ #include "arm_neon.h"
+ 
+--- a/src/libgcc/Makefile.in
++++ b/src/libgcc/Makefile.in
+@@ -414,8 +414,9 @@ lib2funcs = _muldi3 _negdi2 _lshrdi3 _ashldi3 _ashrdi3 _cmpdi2 _ucmpdi2	   \
+ 	    _negvsi2 _negvdi2 _ctors _ffssi2 _ffsdi2 _clz _clzsi2 _clzdi2  \
+ 	    _ctzsi2 _ctzdi2 _popcount_tab _popcountsi2 _popcountdi2	   \
+ 	    _paritysi2 _paritydi2 _powisf2 _powidf2 _powixf2 _powitf2	   \
+-	    _mulsc3 _muldc3 _mulxc3 _multc3 _divsc3 _divdc3 _divxc3	   \
+-	    _divtc3 _bswapsi2 _bswapdi2 _clrsbsi2 _clrsbdi2
++	    _mulhc3 _mulsc3 _muldc3 _mulxc3 _multc3 _divhc3 _divsc3	   \
++	    _divdc3 _divxc3 _divtc3 _bswapsi2 _bswapdi2 _clrsbsi2	   \
++	    _clrsbdi2
+ 
+ # The floating-point conversion routines that involve a single-word integer.
+ # XX stands for the integer mode.
+--- a/src/libgcc/config.host
++++ b/src/libgcc/config.host
+@@ -1399,4 +1399,8 @@ i[34567]86-*-linux* | x86_64-*-linux*)
+ 	fi
+ 	tm_file="${tm_file} i386/value-unwind.h"
+ 	;;
++aarch64*-*-*)
++	# ILP32 needs an extra header for unwinding
++	tm_file="${tm_file} aarch64/value-unwind.h"
++	;;
+ esac
+--- /dev/null
++++ b/src/libgcc/config/aarch64/value-unwind.h
+@@ -0,0 +1,25 @@
++/* Store register values as _Unwind_Word type in DWARF2 EH unwind context.
++   Copyright (C) 2017 Free Software Foundation, Inc.
++
++   This file is part of GCC.
++
++   GCC is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published
++   by the Free Software Foundation; either version 3, or (at your
++   option) any later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++/* Define this macro if the target stores register values as _Unwind_Word
++   type in unwind context.  Only enable it for ilp32.  */
++#if defined __aarch64__ && !defined __LP64__
++# define REG_VALUE_IN_UNWIND_CONTEXT
++#endif
+--- a/src/libgcc/config/arm/bpabi-v6m.S
++++ b/src/libgcc/config/arm/bpabi-v6m.S
+@@ -1,4 +1,5 @@
+-/* Miscellaneous BPABI functions.  ARMv6M implementation
++/* Miscellaneous BPABI functions.  Thumb-1 implementation, suitable for ARMv4T,
++   ARMv6-M and ARMv8-M Baseline like ISA variants.
+ 
+    Copyright (C) 2006-2016 Free Software Foundation, Inc.
+    Contributed by CodeSourcery.
+--- /dev/null
++++ b/src/libgcc/config/arm/cmse.c
+@@ -0,0 +1,108 @@
++/* ARMv8-M Security Extensions routines.
++   Copyright (C) 2015-2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++
++   This file is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published by the
++   Free Software Foundation; either version 3, or (at your option) any
++   later version.
++
++   This file is distributed in the hope that it will be useful, but
++   WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   General Public License for more details.
++
++   Under Section 7 of GPL version 3, you are granted additional
++   permissions described in the GCC Runtime Library Exception, version
++   3.1, as published by the Free Software Foundation.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++
++#if __ARM_FEATURE_CMSE & 1
++
++#include <arm_cmse.h>
++
++/* ARM intrinsic function to perform a permission check on a given
++   address range.  See ACLE changes for ARMv8-M.  */
++
++void *
++cmse_check_address_range (void *p, size_t size, int flags)
++{
++  cmse_address_info_t permb, perme;
++  char *pb = (char *) p, *pe;
++
++  /* Check if the range wraps around.  */
++  if (UINTPTR_MAX - (uintptr_t) p < size)
++    return NULL;
++
++  /* Check if an unknown flag is present.  */
++  int known = CMSE_MPU_UNPRIV | CMSE_MPU_READWRITE | CMSE_MPU_READ;
++  int known_secure_level = CMSE_MPU_UNPRIV;
++#if __ARM_FEATURE_CMSE & 2
++  known |= CMSE_AU_NONSECURE | CMSE_MPU_NONSECURE;
++  known_secure_level |= CMSE_MPU_NONSECURE;
++#endif
++  if (flags & (~known))
++    return NULL;
++
++  /* Execute the right variant of the TT instructions.  */
++  pe = pb + size - 1;
++  const int singleCheck = (((uintptr_t) pb ^ (uintptr_t) pe) < 32);
++  switch (flags & known_secure_level)
++    {
++    case 0:
++      permb = cmse_TT (pb);
++      perme = singleCheck ? permb : cmse_TT (pe);
++      break;
++    case CMSE_MPU_UNPRIV:
++      permb = cmse_TTT (pb);
++      perme = singleCheck ? permb : cmse_TTT (pe);
++      break;
++#if __ARM_FEATURE_CMSE & 2
++    case CMSE_MPU_NONSECURE:
++      permb = cmse_TTA (pb);
++      perme = singleCheck ? permb : cmse_TTA (pe);
++      break;
++    case CMSE_MPU_UNPRIV | CMSE_MPU_NONSECURE:
++      permb = cmse_TTAT (pb);
++      perme = singleCheck ? permb : cmse_TTAT (pe);
++      break;
++#endif
++    default:
++      /* Invalid flag, eg.  CMSE_MPU_NONSECURE specified but
++	 __ARM_FEATURE_CMSE & 2 == 0.  */
++      return NULL;
++    }
++
++  /* Check that the range does not cross MPU, SAU, or IDAU boundaries.  */
++  if (permb.value != perme.value)
++    return NULL;
++
++  /* Check the permissions on the range.  */
++  switch (flags & (~known_secure_level))
++    {
++#if __ARM_FEATURE_CMSE & 2
++    case CMSE_MPU_READ | CMSE_MPU_READWRITE | CMSE_AU_NONSECURE:
++    case		 CMSE_MPU_READWRITE | CMSE_AU_NONSECURE:
++      return permb.flags.nonsecure_readwrite_ok	? p : NULL;
++    case CMSE_MPU_READ | CMSE_AU_NONSECURE:
++      return permb.flags.nonsecure_read_ok	? p : NULL;
++    case CMSE_AU_NONSECURE:
++      return permb.flags.secure			? NULL : p;
++#endif
++    case CMSE_MPU_READ | CMSE_MPU_READWRITE:
++    case		 CMSE_MPU_READWRITE:
++      return permb.flags.readwrite_ok		? p : NULL;
++    case CMSE_MPU_READ:
++      return permb.flags.read_ok		? p : NULL;
++    default:
++      return NULL;
++    }
++}
++
++
++#endif /* __ARM_FEATURE_CMSE & 1.  */
+--- /dev/null
++++ b/src/libgcc/config/arm/cmse_nonsecure_call.S
+@@ -0,0 +1,131 @@
++/* CMSE wrapper function used to save, clear and restore callee saved registers
++   for cmse_nonsecure_call's.
++
++   Copyright (C) 2016 Free Software Foundation, Inc.
++   Contributed by ARM Ltd.
++
++   This file is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published by the
++   Free Software Foundation; either version 3, or (at your option) any
++   later version.
++
++   This file is distributed in the hope that it will be useful, but
++   WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   General Public License for more details.
++
++   Under Section 7 of GPL version 3, you are granted additional
++   permissions described in the GCC Runtime Library Exception, version
++   3.1, as published by the Free Software Foundation.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++.syntax unified
++.thumb
++.global __gnu_cmse_nonsecure_call
++__gnu_cmse_nonsecure_call:
++#if defined(__ARM_ARCH_8M_MAIN__)
++push	    {r5-r11,lr}
++mov	    r7, r4
++mov	    r8, r4
++mov	    r9, r4
++mov	    r10, r4
++mov	    r11, r4
++mov	    ip, r4
++
++/* Save and clear callee-saved registers only if we are dealing with hard float
++   ABI.  The unused caller-saved registers have already been cleared by GCC
++   generated code.  */
++#ifdef __ARM_PCS_VFP
++vpush.f64   {d8-d15}
++mov	    r5, #0
++vmov	    d8, r5, r5
++#if __ARM_FP & 0x04
++vmov	    s18, s19, r5, r5
++vmov	    s20, s21, r5, r5
++vmov	    s22, s23, r5, r5
++vmov	    s24, s25, r5, r5
++vmov	    s26, s27, r5, r5
++vmov	    s28, s29, r5, r5
++vmov	    s30, s31, r5, r5
++#elif __ARM_FP & 0x08
++vmov.f64    d9, d8
++vmov.f64    d10, d8
++vmov.f64    d11, d8
++vmov.f64    d12, d8
++vmov.f64    d13, d8
++vmov.f64    d14, d8
++vmov.f64    d15, d8
++#else
++#error "Half precision implementation not supported."
++#endif
++/* Clear the cumulative exception-status bits (0-4,7) and the
++   condition code bits (28-31) of the FPSCR.  */
++vmrs	    r5, fpscr
++movw	    r6, #65376
++movt	    r6, #4095
++ands	    r5, r6
++vmsr	    fpscr, r5
++
++/* We are not dealing with hard float ABI, so we can safely use the vlstm and
++   vlldm instructions without needing to preserve the registers used for
++   argument passing.  */
++#else
++sub	    sp, sp, #0x88 /* Reserve stack space to save all floating point
++			     registers, including FPSCR.  */
++vlstm	    sp		  /* Lazy store and clearance of d0-d16 and FPSCR.  */
++#endif /* __ARM_PCS_VFP */
++
++/* Make sure to clear the 'GE' bits of the APSR register if 32-bit SIMD
++   instructions are available.  */
++#if defined(__ARM_FEATURE_SIMD32)
++msr	    APSR_nzcvqg, r4
++#else
++msr	    APSR_nzcvq, r4
++#endif
++
++mov	    r5, r4
++mov	    r6, r4
++blxns	    r4
++
++#ifdef __ARM_PCS_VFP
++vpop.f64    {d8-d15}
++#else
++vlldm	    sp		  /* Lazy restore of d0-d16 and FPSCR.  */
++add	    sp, sp, #0x88 /* Free space used to save floating point registers.  */
++#endif /* __ARM_PCS_VFP */
++
++pop	    {r5-r11, pc}
++
++#elif defined (__ARM_ARCH_8M_BASE__)
++push	    {r5-r7, lr}
++mov	    r5, r8
++mov	    r6, r9
++mov	    r7, r10
++push	    {r5-r7}
++mov	    r5, r11
++push	    {r5}
++mov	    r5, r4
++mov	    r6, r4
++mov	    r7, r4
++mov	    r8, r4
++mov	    r9, r4
++mov	    r10, r4
++mov	    r11, r4
++mov	    ip, r4
++msr	    APSR_nzcvq, r4
++blxns	    r4
++pop	    {r5}
++mov	    r11, r5
++pop	    {r5-r7}
++mov	    r10, r7
++mov	    r9, r6
++mov	    r8, r5
++pop	    {r5-r7, pc}
++
++#else
++#error "This should only be used for armv8-m base- and mainline."
++#endif
+--- a/src/libgcc/config/arm/ieee754-df.S
++++ b/src/libgcc/config/arm/ieee754-df.S
+@@ -160,8 +160,8 @@ ARM_FUNC_ALIAS aeabi_dadd adddf3
+ 	teq	r4, r5
+ 	beq	LSYM(Lad_d)
+ 
+-@ CFI note: we're lucky that the branches to Lad_* that appear after this function
+-@ have a CFI state that's exactly the same as the one we're in at this
++@ CFI note: we're lucky that the branches to Lad_* that appear after this
++@ function have a CFI state that's exactly the same as the one we're in at this
+ @ point. Otherwise the CFI would change to a different state after the branch,
+ @ which would be disastrous for backtracing.
+ LSYM(Lad_x):
+@@ -507,11 +507,15 @@ ARM_FUNC_ALIAS aeabi_f2d extendsfdf2
+ 	eorne	xh, xh, #0x38000000	@ fixup exponent otherwise.
+ 	RETc(ne)			@ and return it.
+ 
+-	teq	r2, #0			@ if actually 0
+-	do_it	ne, e
+-	teqne	r3, #0xff000000		@ or INF or NAN
++	bics	r2, r2, #0xff000000	@ isolate mantissa
++	do_it	eq			@ if 0, that is ZERO or INF,
+ 	RETc(eq)			@ we are done already.
+ 
++	teq	r3, #0xff000000		@ check for NAN
++	do_it	eq, t
++	orreq	xh, xh, #0x00080000	@ change to quiet NAN
++	RETc(eq)			@ and return it.
++
+ 	@ value was denormalized.  We can normalize it now.
+ 	do_push	{r4, r5, lr}
+ 	.cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12
+@@ -1158,8 +1162,8 @@ ARM_FUNC_ALIAS eqdf2 cmpdf2
+ 1:	str	ip, [sp, #-4]!
+ 	.cfi_adjust_cfa_offset 4        @ CFA is now sp + previousOffset + 4.
+ 	@ We're not adding CFI for ip as it's pushed into the stack
+-	@ only because @ it may be popped off later as a return value
+-	@ (i.e. we're not preserving @ it anyways).
++	@ only because it may be popped off later as a return value
++	@ (i.e. we're not preserving it anyways).
+ 
+ 	@ Trap any INF/NAN first.
+ 	mov	ip, xh, lsl #1
+@@ -1169,14 +1173,14 @@ ARM_FUNC_ALIAS eqdf2 cmpdf2
+ 	COND(mvn,s,ne)	ip, ip, asr #21
+ 	beq	3f
+ 	.cfi_remember_state
+-	@ Save the current CFI state. This is done because the branch
+-	@ is conditional, @ and if we don't take it we'll issue a
+-	@ .cfi_adjust_cfa_offset and return.  @ If we do take it,
+-	@ however, the .cfi_adjust_cfa_offset from the non-branch @ code
+-	@ will affect the branch code as well. To avoid this we'll
+-	@ restore @ the current state before executing the branch code.
+-
+-	@ Test for equality.  @ Note that 0.0 is equal to -0.0.
++	@ Save the current CFI state.  This is done because the branch
++	@ is conditional, and if we don't take it we'll issue a
++	@ .cfi_adjust_cfa_offset and return.  If we do take it,
++	@ however, the .cfi_adjust_cfa_offset from the non-branch code
++	@ will affect the branch code as well.  To avoid this we'll
++	@ restore the current state before executing the branch code.
++
++	@ Test for equality.  Note that 0.0 is equal to -0.0.
+ 2:	add	sp, sp, #4
+ 	.cfi_adjust_cfa_offset -4       @ CFA is now sp + previousOffset.
+ 
+--- a/src/libgcc/config/arm/lib1funcs.S
++++ b/src/libgcc/config/arm/lib1funcs.S
+@@ -108,7 +108,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+ # define __ARM_ARCH__ 7
+ #endif
+ 
+-#if defined(__ARM_ARCH_8A__)
++#if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \
++	|| defined(__ARM_ARCH_8M_MAIN__)
+ # define __ARM_ARCH__ 8
+ #endif
+ 
+@@ -124,10 +125,14 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+      && !defined(__thumb2__)		\
+      && (!defined(__THUMB_INTERWORK__)	\
+ 	 || defined (__OPTIMIZE_SIZE__)	\
+-	 || defined(__ARM_ARCH_6M__)))
++	 || !__ARM_ARCH_ISA_ARM))
+ # define __prefer_thumb__
+ #endif
+ 
++#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
++#define NOT_ISA_TARGET_32BIT 1
++#endif
++
+ /* How to return from a function call depends on the architecture variant.  */
+ 
+ #if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__)
+@@ -305,35 +310,14 @@ LSYM(Lend_fde):
+ 
+ #ifdef __ARM_EABI__
+ .macro THUMB_LDIV0 name signed
+-#if defined(__ARM_ARCH_6M__)
+-	.ifc \signed, unsigned
+-	cmp	r0, #0
+-	beq	1f
+-	mov	r0, #0
+-	mvn	r0, r0		@ 0xffffffff
+-1:
+-	.else
+-	cmp	r0, #0
+-	beq	2f
+-	blt	3f
++#ifdef NOT_ISA_TARGET_32BIT
++
++	push	{r0, lr}
+ 	mov	r0, #0
+-	mvn	r0, r0
+-	lsr	r0, r0, #1	@ 0x7fffffff
+-	b	2f
+-3:	mov	r0, #0x80
+-	lsl	r0, r0, #24	@ 0x80000000
+-2:
+-	.endif
+-	push	{r0, r1, r2}
+-	ldr	r0, 4f
+-	adr	r1, 4f
+-	add	r0, r1
+-	str	r0, [sp, #8]
++	bl	SYM(__aeabi_idiv0)
+ 	@ We know we are not on armv4t, so pop pc is safe.
+-	pop	{r0, r1, pc}
+-	.align	2
+-4:
+-	.word	__aeabi_idiv0 - 4b
++	pop	{r1, pc}
++
+ #elif defined(__thumb2__)
+ 	.syntax unified
+ 	.ifc \signed, unsigned
+@@ -478,7 +462,7 @@ _L__\name:
+ 
+ #else /* !(__INTERWORKING_STUBS__ || __thumb2__) */
+ 
+-#ifdef __ARM_ARCH_6M__
++#ifdef NOT_ISA_TARGET_32BIT
+ #define EQUIV .thumb_set
+ #else
+ .macro	ARM_FUNC_START name sp_section=
+@@ -510,7 +494,7 @@ SYM (__\name):
+ #endif
+ .endm
+ 
+-#ifndef __ARM_ARCH_6M__
++#ifndef NOT_ISA_TARGET_32BIT
+ .macro	ARM_FUNC_ALIAS new old
+ 	.globl	SYM (__\new)
+ 	EQUIV	SYM (__\new), SYM (__\old)
+@@ -945,7 +929,170 @@ LSYM(Lover7):
+ 	add	dividend, work
+   .endif
+ LSYM(Lgot_result):
+-.endm	
++.endm
++
++/* If performance is preferred, the following functions are provided.  */
++#if defined(__prefer_thumb__) && !defined(__OPTIMIZE_SIZE__)
++
++/* Branch to div(n), and jump to label if curbit is lo than divisior.  */
++.macro BranchToDiv n, label
++	lsr	curbit, dividend, \n
++	cmp	curbit, divisor
++	blo	\label
++.endm
++
++/* Body of div(n).  Shift the divisor in n bits and compare the divisor
++   and dividend.  Update the dividend as the substruction result.  */
++.macro DoDiv n
++	lsr	curbit, dividend, \n
++	cmp	curbit, divisor
++	bcc	1f
++	lsl	curbit, divisor, \n
++	sub	dividend, dividend, curbit
++
++1:	adc	result, result
++.endm
++
++/* The body of division with positive divisor.  Unless the divisor is very
++   big, shift it up in multiples of four bits, since this is the amount of
++   unwinding in the main division loop.  Continue shifting until the divisor
++   is larger than the dividend.  */
++.macro THUMB1_Div_Positive
++	mov	result, #0
++	BranchToDiv #1, LSYM(Lthumb1_div1)
++	BranchToDiv #4, LSYM(Lthumb1_div4)
++	BranchToDiv #8, LSYM(Lthumb1_div8)
++	BranchToDiv #12, LSYM(Lthumb1_div12)
++	BranchToDiv #16, LSYM(Lthumb1_div16)
++LSYM(Lthumb1_div_large_positive):
++	mov	result, #0xff
++	lsl	divisor, divisor, #8
++	rev	result, result
++	lsr	curbit, dividend, #16
++	cmp	curbit, divisor
++	blo	1f
++	asr	result, #8
++	lsl	divisor, divisor, #8
++	beq	LSYM(Ldivbyzero_waypoint)
++
++1:	lsr	curbit, dividend, #12
++	cmp	curbit, divisor
++	blo	LSYM(Lthumb1_div12)
++	b	LSYM(Lthumb1_div16)
++LSYM(Lthumb1_div_loop):
++	lsr	divisor, divisor, #8
++LSYM(Lthumb1_div16):
++	Dodiv	#15
++	Dodiv	#14
++	Dodiv	#13
++	Dodiv	#12
++LSYM(Lthumb1_div12):
++	Dodiv	#11
++	Dodiv	#10
++	Dodiv	#9
++	Dodiv	#8
++	bcs	LSYM(Lthumb1_div_loop)
++LSYM(Lthumb1_div8):
++	Dodiv	#7
++	Dodiv	#6
++	Dodiv	#5
++LSYM(Lthumb1_div5):
++	Dodiv	#4
++LSYM(Lthumb1_div4):
++	Dodiv	#3
++LSYM(Lthumb1_div3):
++	Dodiv	#2
++LSYM(Lthumb1_div2):
++	Dodiv	#1
++LSYM(Lthumb1_div1):
++	sub	divisor, dividend, divisor
++	bcs	1f
++	cpy	divisor, dividend
++
++1:	adc	result, result
++	cpy	dividend, result
++	RET
++
++LSYM(Ldivbyzero_waypoint):
++	b	LSYM(Ldiv0)
++.endm
++
++/* The body of division with negative divisor.  Similar with
++   THUMB1_Div_Positive except that the shift steps are in multiples
++   of six bits.  */
++.macro THUMB1_Div_Negative
++	lsr	result, divisor, #31
++	beq	1f
++	neg	divisor, divisor
++
++1:	asr	curbit, dividend, #32
++	bcc	2f
++	neg	dividend, dividend
++
++2:	eor	curbit, result
++	mov	result, #0
++	cpy	ip, curbit
++	BranchToDiv #4, LSYM(Lthumb1_div_negative4)
++	BranchToDiv #8, LSYM(Lthumb1_div_negative8)
++LSYM(Lthumb1_div_large):
++	mov	result, #0xfc
++	lsl	divisor, divisor, #6
++	rev	result, result
++	lsr	curbit, dividend, #8
++	cmp	curbit, divisor
++	blo	LSYM(Lthumb1_div_negative8)
++
++	lsl	divisor, divisor, #6
++	asr	result, result, #6
++	cmp	curbit, divisor
++	blo	LSYM(Lthumb1_div_negative8)
++
++	lsl	divisor, divisor, #6
++	asr	result, result, #6
++	cmp	curbit, divisor
++	blo	LSYM(Lthumb1_div_negative8)
++
++	lsl	divisor, divisor, #6
++	beq	LSYM(Ldivbyzero_negative)
++	asr	result, result, #6
++	b	LSYM(Lthumb1_div_negative8)
++LSYM(Lthumb1_div_negative_loop):
++	lsr	divisor, divisor, #6
++LSYM(Lthumb1_div_negative8):
++	DoDiv	#7
++	DoDiv	#6
++	DoDiv	#5
++	DoDiv	#4
++LSYM(Lthumb1_div_negative4):
++	DoDiv	#3
++	DoDiv	#2
++	bcs	LSYM(Lthumb1_div_negative_loop)
++	DoDiv	#1
++	sub	divisor, dividend, divisor
++	bcs	1f
++	cpy	divisor, dividend
++
++1:	cpy	curbit, ip
++	adc	result, result
++	asr	curbit, curbit, #1
++	cpy	dividend, result
++	bcc	2f
++	neg	dividend, dividend
++	cmp	curbit, #0
++
++2:	bpl	3f
++	neg	divisor, divisor
++
++3:	RET
++
++LSYM(Ldivbyzero_negative):
++	cpy	curbit, ip
++	asr	curbit, curbit, #1
++	bcc	LSYM(Ldiv0)
++	neg	dividend, dividend
++.endm
++#endif /* ARM Thumb version.  */
++
+ /* ------------------------------------------------------------------------ */
+ /*		Start of the Real Functions				    */
+ /* ------------------------------------------------------------------------ */
+@@ -955,6 +1102,7 @@ LSYM(Lgot_result):
+ 
+ 	FUNC_START udivsi3
+ 	FUNC_ALIAS aeabi_uidiv udivsi3
++#if defined(__OPTIMIZE_SIZE__)
+ 
+ 	cmp	divisor, #0
+ 	beq	LSYM(Ldiv0)
+@@ -972,6 +1120,14 @@ LSYM(udivsi3_skip_div0_test):
+ 	pop	{ work }
+ 	RET
+ 
++/* Implementation of aeabi_uidiv for ARMv6m.  This version is only
++   used in ARMv6-M when we need an efficient implementation.  */
++#else
++LSYM(udivsi3_skip_div0_test):
++	THUMB1_Div_Positive
++
++#endif /* __OPTIMIZE_SIZE__ */
++
+ #elif defined(__ARM_ARCH_EXT_IDIV__)
+ 
+ 	ARM_FUNC_START udivsi3
+@@ -1023,12 +1179,21 @@ LSYM(udivsi3_skip_div0_test):
+ FUNC_START aeabi_uidivmod
+ 	cmp	r1, #0
+ 	beq	LSYM(Ldiv0)
++# if defined(__OPTIMIZE_SIZE__)
+ 	push	{r0, r1, lr}
+ 	bl	LSYM(udivsi3_skip_div0_test)
+ 	POP	{r1, r2, r3}
+ 	mul	r2, r0
+ 	sub	r1, r1, r2
+ 	bx	r3
++# else
++	/* Both the quotient and remainder are calculated simultaneously
++	   in THUMB1_Div_Positive.  There is no need to calculate the
++	   remainder again here.  */
++	b	LSYM(udivsi3_skip_div0_test)
++	RET
++# endif /* __OPTIMIZE_SIZE__ */
++
+ #elif defined(__ARM_ARCH_EXT_IDIV__)
+ ARM_FUNC_START aeabi_uidivmod
+ 	cmp	r1, #0
+@@ -1054,7 +1219,7 @@ ARM_FUNC_START aeabi_uidivmod
+ /* ------------------------------------------------------------------------ */
+ #ifdef L_umodsi3
+ 
+-#ifdef __ARM_ARCH_EXT_IDIV__
++#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB != 1
+ 
+ 	ARM_FUNC_START umodsi3
+ 
+@@ -1084,7 +1249,7 @@ LSYM(Lover10):
+ 	RET
+ 	
+ #else  /* ARM version.  */
+-	
++
+ 	FUNC_START umodsi3
+ 
+ 	subs	r2, r1, #1			@ compare divisor with 1
+@@ -1109,8 +1274,9 @@ LSYM(Lover10):
+ 
+ #if defined(__prefer_thumb__)
+ 
+-	FUNC_START divsi3	
++	FUNC_START divsi3
+ 	FUNC_ALIAS aeabi_idiv divsi3
++#if defined(__OPTIMIZE_SIZE__)
+ 
+ 	cmp	divisor, #0
+ 	beq	LSYM(Ldiv0)
+@@ -1133,7 +1299,7 @@ LSYM(Lover11):
+ 	blo	LSYM(Lgot_result)
+ 
+ 	THUMB_DIV_MOD_BODY 0
+-	
++
+ 	mov	r0, result
+ 	mov	work, ip
+ 	cmp	work, #0
+@@ -1143,6 +1309,22 @@ LSYM(Lover12):
+ 	pop	{ work }
+ 	RET
+ 
++/* Implementation of aeabi_idiv for ARMv6m.  This version is only
++   used in ARMv6-M when we need an efficient implementation.  */
++#else
++LSYM(divsi3_skip_div0_test):
++	cpy	curbit, dividend
++	orr	curbit, divisor
++	bmi	LSYM(Lthumb1_div_negative)
++
++LSYM(Lthumb1_div_positive):
++	THUMB1_Div_Positive
++
++LSYM(Lthumb1_div_negative):
++	THUMB1_Div_Negative
++
++#endif /* __OPTIMIZE_SIZE__ */
++
+ #elif defined(__ARM_ARCH_EXT_IDIV__)
+ 
+ 	ARM_FUNC_START divsi3
+@@ -1154,8 +1336,8 @@ LSYM(Lover12):
+ 	RET
+ 
+ #else /* ARM/Thumb-2 version.  */
+-	
+-	ARM_FUNC_START divsi3	
++
++	ARM_FUNC_START divsi3
+ 	ARM_FUNC_ALIAS aeabi_idiv divsi3
+ 
+ 	cmp	r1, #0
+@@ -1209,12 +1391,21 @@ LSYM(divsi3_skip_div0_test):
+ FUNC_START aeabi_idivmod
+ 	cmp	r1, #0
+ 	beq	LSYM(Ldiv0)
++# if defined(__OPTIMIZE_SIZE__)
+ 	push	{r0, r1, lr}
+ 	bl	LSYM(divsi3_skip_div0_test)
+ 	POP	{r1, r2, r3}
+ 	mul	r2, r0
+ 	sub	r1, r1, r2
+ 	bx	r3
++# else
++	/* Both the quotient and remainder are calculated simultaneously
++	   in THUMB1_Div_Positive and THUMB1_Div_Negative.  There is no
++	   need to calculate the remainder again here.  */
++	b	LSYM(divsi3_skip_div0_test)
++	RET
++# endif /* __OPTIMIZE_SIZE__ */
++
+ #elif defined(__ARM_ARCH_EXT_IDIV__)
+ ARM_FUNC_START aeabi_idivmod
+ 	cmp 	r1, #0
+@@ -1240,7 +1431,7 @@ ARM_FUNC_START aeabi_idivmod
+ /* ------------------------------------------------------------------------ */
+ #ifdef L_modsi3
+ 
+-#if defined(__ARM_ARCH_EXT_IDIV__)
++#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB != 1
+ 
+ 	ARM_FUNC_START modsi3
+ 
+@@ -1508,14 +1699,15 @@ LSYM(Lover12):
+ 
+ #endif /* __symbian__ */
+ 
+-#if ((__ARM_ARCH__ > 5) && !defined(__ARM_ARCH_6M__)) \
+-    || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \
+-    || defined(__ARM_ARCH_5TEJ__)
++#if (__ARM_ARCH_ISA_THUMB == 2	\
++     || (__ARM_ARCH_ISA_ARM	\
++	 && (__ARM_ARCH__ > 5	\
++	     || (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB))))
+ #define HAVE_ARM_CLZ 1
+ #endif
+ 
+ #ifdef L_clzsi2
+-#if defined(__ARM_ARCH_6M__)
++#ifdef NOT_ISA_TARGET_32BIT
+ FUNC_START clzsi2
+ 	mov	r1, #28
+ 	mov	r3, #1
+@@ -1576,7 +1768,7 @@ ARM_FUNC_START clzsi2
+ #ifdef L_clzdi2
+ #if !defined(HAVE_ARM_CLZ)
+ 
+-# if defined(__ARM_ARCH_6M__)
++# ifdef NOT_ISA_TARGET_32BIT
+ FUNC_START clzdi2
+ 	push	{r4, lr}
+ # else
+@@ -1601,7 +1793,7 @@ ARM_FUNC_START clzdi2
+ 	bl	__clzsi2
+ # endif
+ 2:
+-# if defined(__ARM_ARCH_6M__)
++# ifdef NOT_ISA_TARGET_32BIT
+ 	pop	{r4, pc}
+ # else
+ 	RETLDM	r4
+@@ -1623,7 +1815,7 @@ ARM_FUNC_START clzdi2
+ #endif /* L_clzdi2 */
+ 
+ #ifdef L_ctzsi2
+-#if defined(__ARM_ARCH_6M__)
++#ifdef NOT_ISA_TARGET_32BIT
+ FUNC_START ctzsi2
+ 	neg	r1, r0
+ 	and	r0, r0, r1
+@@ -1738,7 +1930,7 @@ ARM_FUNC_START ctzsi2
+ 
+ /* Don't bother with the old interworking routines for Thumb-2.  */
+ /* ??? Maybe only omit these on "m" variants.  */
+-#if !defined(__thumb2__) && !defined(__ARM_ARCH_6M__)
++#if !defined(__thumb2__) && __ARM_ARCH_ISA_ARM
+ 
+ #if defined L_interwork_call_via_rX
+ 
+@@ -1983,11 +2175,12 @@ LSYM(Lchange_\register):
+ .endm
+ 
+ #ifndef __symbian__
+-#ifndef __ARM_ARCH_6M__
++/* The condition here must match the one in gcc/config/arm/elf.h.  */
++#ifndef NOT_ISA_TARGET_32BIT
+ #include "ieee754-df.S"
+ #include "ieee754-sf.S"
+ #include "bpabi.S"
+-#else /* __ARM_ARCH_6M__ */
++#else /* NOT_ISA_TARGET_32BIT */
+ #include "bpabi-v6m.S"
+-#endif /* __ARM_ARCH_6M__ */
++#endif /* NOT_ISA_TARGET_32BIT */
+ #endif /* !__symbian__ */
+--- a/src/libgcc/config/arm/libunwind.S
++++ b/src/libgcc/config/arm/libunwind.S
+@@ -58,7 +58,7 @@
+ #endif
+ #endif
+ 
+-#ifdef __ARM_ARCH_6M__
++#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
+ 
+ /* r0 points to a 16-word block.  Upload these values to the actual core
+    state.  */
+@@ -169,7 +169,7 @@ FUNC_START gnu_Unwind_Save_WMMXC
+ 	UNPREFIX \name
+ .endm
+ 
+-#else /* !__ARM_ARCH_6M__ */
++#else /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */
+ 
+ /* r0 points to a 16-word block.  Upload these values to the actual core
+    state.  */
+@@ -351,7 +351,7 @@ ARM_FUNC_START gnu_Unwind_Save_WMMXC
+ 	UNPREFIX \name
+ .endm
+ 
+-#endif /* !__ARM_ARCH_6M__ */
++#endif /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */
+ 
+ UNWIND_WRAPPER _Unwind_RaiseException 1
+ UNWIND_WRAPPER _Unwind_Resume 1
+--- a/src/libgcc/config/arm/t-arm
++++ b/src/libgcc/config/arm/t-arm
+@@ -1,3 +1,17 @@
+ LIB1ASMSRC = arm/lib1funcs.S
+ LIB1ASMFUNCS = _thumb1_case_sqi _thumb1_case_uqi _thumb1_case_shi \
+ 	_thumb1_case_uhi _thumb1_case_si
++
++HAVE_CMSE:=$(findstring __ARM_FEATURE_CMSE,$(shell $(gcc_compile_bare) -dM -E - </dev/null))
++ifneq ($(shell $(gcc_compile_bare) -E -mcmse - </dev/null 2>/dev/null),)
++CMSE_OPTS:=-mcmse
++endif
++
++ifdef HAVE_CMSE
++libgcc-objects += cmse.o cmse_nonsecure_call.o
++
++cmse.o: $(srcdir)/config/arm/cmse.c
++	$(gcc_compile) -c $(CMSE_OPTS) $<
++cmse_nonsecure_call.o: $(srcdir)/config/arm/cmse_nonsecure_call.S
++		       $(gcc_compile) -c $<
++endif
+--- a/src/libgcc/config/arm/t-softfp
++++ b/src/libgcc/config/arm/t-softfp
+@@ -1,2 +1,2 @@
+-softfp_wrap_start := '\#ifdef __ARM_ARCH_6M__'
++softfp_wrap_start := '\#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1'
+ softfp_wrap_end := '\#endif'
+--- a/src/libgcc/libgcc2.c
++++ b/src/libgcc/libgcc2.c
+@@ -1853,7 +1853,8 @@ NAME (TYPE x, int m)
+ 
+ #endif
+ 
+-#if ((defined(L_mulsc3) || defined(L_divsc3)) && LIBGCC2_HAS_SF_MODE) \
++#if((defined(L_mulhc3) || defined(L_divhc3)) && LIBGCC2_HAS_HF_MODE) \
++    || ((defined(L_mulsc3) || defined(L_divsc3)) && LIBGCC2_HAS_SF_MODE) \
+     || ((defined(L_muldc3) || defined(L_divdc3)) && LIBGCC2_HAS_DF_MODE) \
+     || ((defined(L_mulxc3) || defined(L_divxc3)) && LIBGCC2_HAS_XF_MODE) \
+     || ((defined(L_multc3) || defined(L_divtc3)) && LIBGCC2_HAS_TF_MODE)
+@@ -1862,7 +1863,13 @@ NAME (TYPE x, int m)
+ #undef double
+ #undef long
+ 
+-#if defined(L_mulsc3) || defined(L_divsc3)
++#if defined(L_mulhc3) || defined(L_divhc3)
++# define MTYPE	HFtype
++# define CTYPE	HCtype
++# define MODE	hc
++# define CEXT	__LIBGCC_HF_FUNC_EXT__
++# define NOTRUNC (!__LIBGCC_HF_EXCESS_PRECISION__)
++#elif defined(L_mulsc3) || defined(L_divsc3)
+ # define MTYPE	SFtype
+ # define CTYPE	SCtype
+ # define MODE	sc
+@@ -1923,7 +1930,7 @@ extern void *compile_type_assert[sizeof(INFINITY) == sizeof(MTYPE) ? 1 : -1];
+ # define TRUNC(x)	__asm__ ("" : "=m"(x) : "m"(x))
+ #endif
+ 
+-#if defined(L_mulsc3) || defined(L_muldc3) \
++#if defined(L_mulhc3) || defined(L_mulsc3) || defined(L_muldc3) \
+     || defined(L_mulxc3) || defined(L_multc3)
+ 
+ CTYPE
+@@ -1993,7 +2000,7 @@ CONCAT3(__mul,MODE,3) (MTYPE a, MTYPE b, MTYPE c, MTYPE d)
+ }
+ #endif /* complex multiply */
+ 
+-#if defined(L_divsc3) || defined(L_divdc3) \
++#if defined(L_divhc3) || defined(L_divsc3) || defined(L_divdc3) \
+     || defined(L_divxc3) || defined(L_divtc3)
+ 
+ CTYPE
+--- a/src/libgcc/libgcc2.h
++++ b/src/libgcc/libgcc2.h
+@@ -34,6 +34,12 @@ extern void __clear_cache (char *, char *);
+ extern void __eprintf (const char *, const char *, unsigned int, const char *)
+   __attribute__ ((__noreturn__));
+ 
++#ifdef __LIBGCC_HAS_HF_MODE__
++#define LIBGCC2_HAS_HF_MODE 1
++#else
++#define LIBGCC2_HAS_HF_MODE 0
++#endif
++
+ #ifdef __LIBGCC_HAS_SF_MODE__
+ #define LIBGCC2_HAS_SF_MODE 1
+ #else
+@@ -133,6 +139,10 @@ typedef unsigned int UTItype	__attribute__ ((mode (TI)));
+ #endif
+ #endif
+ 
++#if LIBGCC2_HAS_HF_MODE
++typedef		float HFtype	__attribute__ ((mode (HF)));
++typedef _Complex float HCtype	__attribute__ ((mode (HC)));
++#endif
+ #if LIBGCC2_HAS_SF_MODE
+ typedef 	float SFtype	__attribute__ ((mode (SF)));
+ typedef _Complex float SCtype	__attribute__ ((mode (SC)));
+@@ -424,6 +434,10 @@ extern SItype __negvsi2 (SItype);
+ #endif /* COMPAT_SIMODE_TRAPPING_ARITHMETIC */
+ 
+ #undef int
++#if LIBGCC2_HAS_HF_MODE
++extern HCtype __divhc3 (HFtype, HFtype, HFtype, HFtype);
++extern HCtype __mulhc3 (HFtype, HFtype, HFtype, HFtype);
++#endif
+ #if LIBGCC2_HAS_SF_MODE
+ extern DWtype __fixsfdi (SFtype);
+ extern SFtype __floatdisf (DWtype);
+--- a/src/libstdc++-v3/acinclude.m4
++++ b/src/libstdc++-v3/acinclude.m4
+@@ -632,10 +632,10 @@ dnl  baseline_dir
+ dnl  baseline_subdir_switch
+ dnl
+ AC_DEFUN([GLIBCXX_CONFIGURE_TESTSUITE], [
+-  if $GLIBCXX_IS_NATIVE ; then
+-    # Do checks for resource limit functions.
+-    GLIBCXX_CHECK_SETRLIMIT
++  # Do checks for resource limit functions.
++  GLIBCXX_CHECK_SETRLIMIT
+ 
++  if $GLIBCXX_IS_NATIVE ; then
+     # Look for setenv, so that extended locale tests can be performed.
+     GLIBCXX_CHECK_STDLIB_DECL_AND_LINKAGE_3(setenv)
+   fi
+--- a/src/libstdc++-v3/configure
++++ b/src/libstdc++-v3/configure
+@@ -79519,8 +79519,7 @@ $as_echo "$ac_cv_x86_rdrand" >&6; }
+ 
+ # This depends on GLIBCXX_ENABLE_SYMVERS and GLIBCXX_IS_NATIVE.
+ 
+-  if $GLIBCXX_IS_NATIVE ; then
+-    # Do checks for resource limit functions.
++  # Do checks for resource limit functions.
+ 
+   setrlimit_have_headers=yes
+   for ac_header in unistd.h sys/time.h sys/resource.h
+@@ -79749,6 +79748,7 @@ $as_echo "#define _GLIBCXX_RES_LIMITS 1" >>confdefs.h
+ $as_echo "$ac_res_limits" >&6; }
+ 
+ 
++  if $GLIBCXX_IS_NATIVE ; then
+     # Look for setenv, so that extended locale tests can be performed.
+ 
+   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for setenv declaration" >&5
+--- a/src/libstdc++-v3/testsuite/29_atomics/atomic/65913.cc
++++ b/src/libstdc++-v3/testsuite/29_atomics/atomic/65913.cc
+@@ -15,7 +15,8 @@
+ // with this library; see the file COPYING3.  If not see
+ // <http://www.gnu.org/licenses/>.
+ 
+-// { dg-do run { target x86_64-*-linux* powerpc*-*-linux* } }
++// { dg-do run }
++// { dg-require-atomic-builtins "" }
+ // { dg-options "-std=gnu++11 -O0" }
+ 
+ #include <atomic>
--- gcc-6-6.4.0.orig/debian/patches/gcc-multiarch.diff
+++ gcc-6-6.4.0/debian/patches/gcc-multiarch.diff
@@ -0,0 +1,210 @@
+# DP: - Remaining multiarch patches, not yet submitted upstream.
+# DP: - Add MULTIARCH_DIRNAME definitions for multilib configurations,
+# DP:   which are used for the non-multilib builds.
+
+2013-06-12  Matthias Klose  <doko@ubuntu.com>
+
+	* config/i386/t-linux64: Set MULTIARCH_DIRNAME.
+	* config/i386/t-kfreebsd: Set MULTIARCH_DIRNAME.
+	* config.gcc (i[34567]86-*-linux* | x86_64-*-linux*): Prepend
+	i386/t-linux to $tmake_file;
+	set default ABI to N64 for mips64el.
+	* config/mips/t-linux64: Set MULTIARCH_DIRNAME.
+	* config/rs6000/t-linux64: Set MULTIARCH_DIRNAME.
+	* config/s390/t-linux64: Set MULTIARCH_DIRNAME.
+	* config/sparc/t-linux64: Set MULTIARCH_DIRNAME.
+	* src/gcc/config/mips/mips.h: (/usr)/lib as default path.
+
+Index: b/src/gcc/config/sh/t-linux
+===================================================================
+--- a/src/gcc/config/sh/t-linux
++++ b/src/gcc/config/sh/t-linux
+@@ -1,2 +1,10 @@
+ MULTILIB_DIRNAMES= 
+ MULTILIB_MATCHES = 
++
++ifneq (,$(findstring sh4,$(target)))
++MULTILIB_OSDIRNAMES = .:sh4-linux-gnu sh4_nofpu-linux-gnu:sh4-linux-gnu
++MULTIARCH_DIRNAME = $(call if_multiarch,sh4-linux-gnu)
++else
++MULTILIB_OSDIRNAMES = .:sh3-linux-gnu sh3_nofpu-linux-gnu:sh3-linux-gnu
++MULTIARCH_DIRNAME = $(call if_multiarch,sh3-linux-gnu)
++endif
+Index: b/src/gcc/config/sparc/t-linux64
+===================================================================
+--- a/src/gcc/config/sparc/t-linux64
++++ b/src/gcc/config/sparc/t-linux64
+@@ -27,3 +27,5 @@ MULTILIB_OPTIONS = m64/m32
+ MULTILIB_DIRNAMES = 64 32
+ MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:sparc64-linux-gnu)
+ MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:sparc-linux-gnu)
++
++MULTIARCH_DIRNAME = $(call if_multiarch,sparc$(if $(findstring 64,$(target)),64)-linux-gnu)
+Index: b/src/gcc/config/s390/t-linux64
+===================================================================
+--- a/src/gcc/config/s390/t-linux64
++++ b/src/gcc/config/s390/t-linux64
+@@ -9,3 +9,5 @@ MULTILIB_OPTIONS = m64/m31
+ MULTILIB_DIRNAMES = 64 32
+ MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:s390x-linux-gnu)
+ MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:s390-linux-gnu)
++
++MULTIARCH_DIRNAME = $(call if_multiarch,s390$(if $(findstring s390x,$(target)),x)-linux-gnu)
+Index: b/src/gcc/config/rs6000/t-linux64
+===================================================================
+--- a/src/gcc/config/rs6000/t-linux64
++++ b/src/gcc/config/rs6000/t-linux64
+@@ -31,6 +31,8 @@ MULTILIB_EXTRA_OPTS :=
+ MULTILIB_OSDIRNAMES := m64=../lib64$(call if_multiarch,:powerpc64-linux-gnu)
+ MULTILIB_OSDIRNAMES += m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu)
+ 
++MULTIARCH_DIRNAME = $(call if_multiarch,powerpc$(if $(findstring 64,$(target)),64)-linux-gnu)
++
+ rs6000-linux.o: $(srcdir)/config/rs6000/rs6000-linux.c
+ 	$(COMPILE) $<
+ 	$(POSTCOMPILE)
+Index: b/src/gcc/config/i386/t-linux64
+===================================================================
+--- a/src/gcc/config/i386/t-linux64
++++ b/src/gcc/config/i386/t-linux64
+@@ -36,3 +36,13 @@ MULTILIB_DIRNAMES   = $(patsubst m%, %,
+ MULTILIB_OSDIRNAMES = m64=../lib64$(call if_multiarch,:x86_64-linux-gnu)
+ MULTILIB_OSDIRNAMES+= m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:i386-linux-gnu)
+ MULTILIB_OSDIRNAMES+= mx32=../libx32$(call if_multiarch,:x86_64-linux-gnux32)
++
++ifneq (,$(findstring x86_64,$(target)))
++  ifneq (,$(findstring biarchx32.h,$(tm_include_list)))
++  MULTIARCH_DIRNAME = $(call if_multiarch,x86_64-linux-gnux32)
++  else
++  MULTIARCH_DIRNAME = $(call if_multiarch,x86_64-linux-gnu)
++  endif
++else
++  MULTIARCH_DIRNAME = $(call if_multiarch,i386-linux-gnu)
++endif
+Index: b/src/gcc/config/i386/t-kfreebsd
+===================================================================
+--- a/src/gcc/config/i386/t-kfreebsd
++++ b/src/gcc/config/i386/t-kfreebsd
+@@ -1,5 +1,9 @@
+-MULTIARCH_DIRNAME = $(call if_multiarch,i386-kfreebsd-gnu)
++ifeq (,$(MULTIARCH_DIRNAME))
++  MULTIARCH_DIRNAME = $(call if_multiarch,i386-kfreebsd-gnu)
++endif
+ 
+ # MULTILIB_OSDIRNAMES are set in t-linux64.
+ KFREEBSD_OS = $(filter kfreebsd%, $(word 3, $(subst -, ,$(target))))
+ MULTILIB_OSDIRNAMES := $(filter-out mx32=%,$(subst linux,$(KFREEBSD_OS),$(MULTILIB_OSDIRNAMES)))
++
++MULTIARCH_DIRNAME := $(subst linux,$(KFREEBSD_OS),$(MULTIARCH_DIRNAME))
+Index: b/src/gcc/config/mips/t-linux64
+===================================================================
+--- a/src/gcc/config/mips/t-linux64
++++ b/src/gcc/config/mips/t-linux64
+@@ -18,9 +18,22 @@
+ 
+ MULTILIB_OPTIONS = mabi=n32/mabi=32/mabi=64
+ MULTILIB_DIRNAMES = n32 32 64
++MIPS_R6 = $(if $(findstring r6, $(firstword $(subst -, ,$(target)))),r6)
++MIPS_32 = $(if $(findstring r6, $(firstword $(subst -, ,$(target)))),32)
++MIPS_ISA = $(if $(findstring r6, $(firstword $(subst -, ,$(target)))),isa)
+ MIPS_EL = $(if $(filter %el, $(firstword $(subst -, ,$(target)))),el)
+ MIPS_SOFT = $(if $(strip $(filter MASK_SOFT_FLOAT_ABI, $(target_cpu_default)) $(filter soft, $(with_float))),soft)
+ MULTILIB_OSDIRNAMES = \
+ 	../lib32$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
+ 	../lib$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
+ 	../lib64$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
++
++ifneq (,$(findstring abin32,$(target)))
++MULTIARCH_DIRNAME = $(call if_multiarch,mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT))
++else
++ifneq (,$(findstring abi64,$(target)))
++MULTIARCH_DIRNAME = $(call if_multiarch,mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
++else
++MULTIARCH_DIRNAME = $(call if_multiarch,mips$(MIPS_ISA)$(MIPS_32)$(MIPS_R6)$(MIPS_EL)-linux-gnu$(MIPS_SOFT))
++endif
++endif
+Index: b/src/gcc/config.gcc
+===================================================================
+--- a/src/gcc/config.gcc
++++ b/src/gcc/config.gcc
+@@ -2090,6 +2090,11 @@ mips*-*-linux*)				# Linux MIPS, either
+ 			target_cpu_default=MASK_SOFT_FLOAT_ABI
+ 			enable_mips_multilibs="yes"
+ 			;;
++		mipsisa64r6*-*-linux-gnuabi64)
++			default_mips_abi=64
++			default_mips_arch=mips64r6
++			enable_mips_multilibs="yes"
++			;;
+ 		mipsisa64r6*-*-linux*)
+ 			default_mips_abi=n32
+ 			default_mips_arch=mips64r6
+@@ -2100,6 +2105,10 @@ mips*-*-linux*)				# Linux MIPS, either
+ 			default_mips_arch=mips64r2
+ 			enable_mips_multilibs="yes"
+ 			;;
++		mips64*-*-linux-gnuabi64 | mipsisa64*-*-linux-gnuabi64)
++			default_mips_abi=64
++			enable_mips_multilibs="yes"
++			;;
+ 		mips64*-*-linux* | mipsisa64*-*-linux*)
+ 			default_mips_abi=n32
+ 			enable_mips_multilibs="yes"
+@@ -4449,7 +4458,7 @@ case ${target} in
+ 	i[34567]86-*-darwin* | x86_64-*-darwin*)
+ 		;;
+ 	i[34567]86-*-linux* | x86_64-*-linux*)
+-		tmake_file="$tmake_file i386/t-linux"
++		tmake_file="i386/t-linux $tmake_file"
+ 		;;
+ 	i[34567]86-*-kfreebsd*-gnu | x86_64-*-kfreebsd*-gnu)
+ 		tmake_file="$tmake_file i386/t-kfreebsd"
+Index: b/src/gcc/config/aarch64/t-aarch64-linux
+===================================================================
+--- a/src/gcc/config/aarch64/t-aarch64-linux
++++ b/src/gcc/config/aarch64/t-aarch64-linux
+@@ -22,7 +22,7 @@ LIB1ASMSRC   = aarch64/lib1funcs.asm
+ LIB1ASMFUNCS = _aarch64_sync_cache_range
+ 
+ AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be)
+-MULTILIB_OSDIRNAMES = mabi.lp64=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
+-MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
++MULTILIB_OSDIRNAMES = mabi.lp64=../lib$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
++MULTILIB_OSDIRNAMES += mabi.ilp32=../libilp32$(call if_multiarch,:aarch64$(AARCH_BE)_ilp32-linux-gnu)
+ 
+-MULTILIB_OSDIRNAMES += mabi.ilp32=../libilp32
++MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
+Index: b/src/gcc/config/mips/mips.h
+===================================================================
+--- a/src/gcc/config/mips/mips.h
++++ b/src/gcc/config/mips/mips.h
+@@ -3387,16 +3387,6 @@ struct GTY(())  machine_function {
+ #define PMODE_INSN(NAME, ARGS) \
+   (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
+ 
+-/* If we are *not* using multilibs and the default ABI is not ABI_32 we
+-   need to change these from /lib and /usr/lib.  */
+-#if MIPS_ABI_DEFAULT == ABI_N32
+-#define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
+-#define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
+-#elif MIPS_ABI_DEFAULT == ABI_64
+-#define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
+-#define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
+-#endif
+-
+ /* Load store bonding is not supported by micromips and fix_24k.  The
+    performance can be degraded for those targets.  Hence, do not bond for
+    micromips or fix_24k.  */
+Index: b/src/gcc/config/tilegx/t-tilegx
+===================================================================
+--- a/src/gcc/config/tilegx/t-tilegx
++++ b/src/gcc/config/tilegx/t-tilegx
+@@ -1,6 +1,7 @@
+ MULTILIB_OPTIONS = m64/m32
+ MULTILIB_DIRNAMES = 64 32
+-MULTILIB_OSDIRNAMES = ../lib ../lib32
++MULTILIB_OSDIRNAMES = ../lib$(call if_multiarch,:tilegx-linux-gnu) ../lib32$(call if_multiarch,:tilegx32-linux-gnu)
++MULTIARCH_DIRNAME = $(call if_multiarch,tilegx-linux-gnu)
+ 
+ LIBGCC = stmp-multilib
+ INSTALL_LIBGCC = install-multilib
--- gcc-6-6.4.0.orig/debian/patches/gcc-multilib-multiarch.diff
+++ gcc-6-6.4.0/debian/patches/gcc-multilib-multiarch.diff
@@ -0,0 +1,126 @@
+# DP: Don't auto-detect multilib osdirnames.
+
+Index: b/src/gcc/config/sparc/t-linux64
+===================================================================
+--- a/src/gcc/config/sparc/t-linux64
++++ b/src/gcc/config/sparc/t-linux64
+@@ -25,7 +25,12 @@
+ 
+ MULTILIB_OPTIONS = m64/m32
+ MULTILIB_DIRNAMES = 64 32
++ifneq (,$(findstring sparc64,$(target)))
++MULTILIB_OSDIRNAMES = ../lib$(call if_multiarch,:sparc64-linux-gnu)
++MULTILIB_OSDIRNAMES += ../lib32$(call if_multiarch,:sparc-linux-gnu)
++else
+ MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:sparc64-linux-gnu)
+-MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:sparc-linux-gnu)
++MULTILIB_OSDIRNAMES += ../lib$(call if_multiarch,:sparc-linux-gnu)
++endif
+ 
+ MULTIARCH_DIRNAME = $(call if_multiarch,sparc$(if $(findstring 64,$(target)),64)-linux-gnu)
+Index: b/src/gcc/config/s390/t-linux64
+===================================================================
+--- a/src/gcc/config/s390/t-linux64
++++ b/src/gcc/config/s390/t-linux64
+@@ -7,7 +7,12 @@
+ 
+ MULTILIB_OPTIONS = m64/m31
+ MULTILIB_DIRNAMES = 64 32
++ifneq (,$(findstring s390x,$(target)))
++MULTILIB_OSDIRNAMES = ../lib$(call if_multiarch,:s390x-linux-gnu)
++MULTILIB_OSDIRNAMES += ../lib32$(call if_multiarch,:s390-linux-gnu)
++else
+ MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:s390x-linux-gnu)
+-MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:s390-linux-gnu)
++MULTILIB_OSDIRNAMES += ../lib$(call if_multiarch,:s390-linux-gnu)
++endif
+ 
+ MULTIARCH_DIRNAME = $(call if_multiarch,s390$(if $(findstring s390x,$(target)),x)-linux-gnu)
+Index: b/src/gcc/config/rs6000/t-linux64
+===================================================================
+--- a/src/gcc/config/rs6000/t-linux64
++++ b/src/gcc/config/rs6000/t-linux64
+@@ -28,8 +28,13 @@
+ MULTILIB_OPTIONS    := m64/m32
+ MULTILIB_DIRNAMES   := 64 32
+ MULTILIB_EXTRA_OPTS := 
++ifneq (,$(findstring powerpc64,$(target)))
++MULTILIB_OSDIRNAMES := m64=../lib$(call if_multiarch,:powerpc64-linux-gnu)
++MULTILIB_OSDIRNAMES += m32=../lib32$(call if_multiarch,:powerpc-linux-gnu)
++else
+ MULTILIB_OSDIRNAMES := m64=../lib64$(call if_multiarch,:powerpc64-linux-gnu)
+-MULTILIB_OSDIRNAMES += m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu)
++MULTILIB_OSDIRNAMES += m32=../lib$(call if_multiarch,:powerpc-linux-gnu)
++endif
+ 
+ MULTIARCH_DIRNAME = $(call if_multiarch,powerpc$(if $(findstring 64,$(target)),64)-linux-gnu)
+ 
+Index: b/src/gcc/config/i386/t-linux64
+===================================================================
+--- a/src/gcc/config/i386/t-linux64
++++ b/src/gcc/config/i386/t-linux64
+@@ -33,9 +33,19 @@
+ comma=,
+ MULTILIB_OPTIONS    = $(subst $(comma),/,$(TM_MULTILIB_CONFIG))
+ MULTILIB_DIRNAMES   = $(patsubst m%, %, $(subst /, ,$(MULTILIB_OPTIONS)))
++ifneq (,$(findstring gnux32,$(target)))
+ MULTILIB_OSDIRNAMES = m64=../lib64$(call if_multiarch,:x86_64-linux-gnu)
+-MULTILIB_OSDIRNAMES+= m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:i386-linux-gnu)
++MULTILIB_OSDIRNAMES+= m32=../lib32$(call if_multiarch,:i386-linux-gnu)
++MULTILIB_OSDIRNAMES+= mx32=../lib$(call if_multiarch,:x86_64-linux-gnux32)
++else ifneq (,$(findstring x86_64,$(target)))
++MULTILIB_OSDIRNAMES = m64=../lib$(call if_multiarch,:x86_64-linux-gnu)
++MULTILIB_OSDIRNAMES+= m32=../lib32$(call if_multiarch,:i386-linux-gnu)
+ MULTILIB_OSDIRNAMES+= mx32=../libx32$(call if_multiarch,:x86_64-linux-gnux32)
++else
++MULTILIB_OSDIRNAMES = m64=../lib64$(call if_multiarch,:x86_64-linux-gnu)
++MULTILIB_OSDIRNAMES+= m32=../lib$(call if_multiarch,:i386-linux-gnu)
++MULTILIB_OSDIRNAMES+= mx32=../libx32$(call if_multiarch,:x86_64-linux-gnux32)
++endif
+ 
+ ifneq (,$(findstring x86_64,$(target)))
+   ifneq (,$(findstring biarchx32.h,$(tm_include_list)))
+Index: b/src/gcc/config/mips/t-linux64
+===================================================================
+--- a/src/gcc/config/mips/t-linux64
++++ b/src/gcc/config/mips/t-linux64
+@@ -23,10 +23,23 @@ MIPS_32 = $(if $(findstring r6, $(firstw
+ MIPS_ISA = $(if $(findstring r6, $(firstword $(subst -, ,$(target)))),isa)
+ MIPS_EL = $(if $(filter %el, $(firstword $(subst -, ,$(target)))),el)
+ MIPS_SOFT = $(if $(strip $(filter MASK_SOFT_FLOAT_ABI, $(target_cpu_default)) $(filter soft, $(with_float))),soft)
++
++ifneq (,$(findstring gnuabi64,$(target)))
++MULTILIB_OSDIRNAMES = \
++        ../lib32$(call if_multiarch,:mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
++        ../libo32$(call if_multiarch,:mips$(MIPS_ISA)$(MIPS_32)$(MIPS_R6)$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
++        ../lib$(call if_multiarch,:mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
++else ifneq (,$(findstring gnuabin32,$(target)))
++MULTILIB_OSDIRNAMES = \
++        ../lib$(call if_multiarch,:mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
++        ../libo32$(call if_multiarch,:mips$(MIPS_ISA)$(MIPS_32)$(MIPS_R6)$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
++        ../lib64$(call if_multiarch,:mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
++else
+ MULTILIB_OSDIRNAMES = \
+-	../lib32$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
+-	../lib$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
+-	../lib64$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
++        ../lib32$(call if_multiarch,:mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \
++        ../lib$(call if_multiarch,:mips$(MIPS_ISA)$(MIPS_32)$(MIPS_R6)$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \
++        ../lib64$(call if_multiarch,:mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT))
++endif
+ 
+ ifneq (,$(findstring abin32,$(target)))
+ MULTIARCH_DIRNAME = $(call if_multiarch,mips$(MIPS_ISA)64$(MIPS_R6)$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT))
+Index: b/src/gcc/config/rs6000/t-linux
+===================================================================
+--- a/src/gcc/config/rs6000/t-linux
++++ b/src/gcc/config/rs6000/t-linux
+@@ -2,7 +2,7 @@
+ # or soft-float.
+ ifeq (,$(filter $(with_cpu),$(SOFT_FLOAT_CPUS))$(findstring soft,$(with_float)))
+ ifneq (,$(findstring powerpc64,$(target)))
+-MULTILIB_OSDIRNAMES := .=../lib64$(call if_multiarch,:powerpc64-linux-gnu)
++MULTILIB_OSDIRNAMES := .=../lib$(call if_multiarch,:powerpc64-linux-gnu)
+ else
+ ifneq (,$(findstring spe,$(target)))
+ MULTIARCH_DIRNAME := powerpc-linux-gnuspe$(if $(findstring 8548,$(with_cpu)),,v1)
--- gcc-6-6.4.0.orig/debian/patches/gcc-target-include-asm.diff
+++ gcc-6-6.4.0/debian/patches/gcc-target-include-asm.diff
@@ -0,0 +1,15 @@
+# DP: Search $(builddir)/sys-include for the asm header files
+
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -3243,7 +3243,7 @@ fi
+ # being built; programs in there won't even run.
+ if test "${build}" = "${host}" && test -d ${srcdir}/gcc; then
+   # Search for pre-installed headers if nothing else fits.
+-  FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -B$(build_tooldir)/bin/ -B$(build_tooldir)/lib/ -isystem $(build_tooldir)/include -isystem $(build_tooldir)/sys-include'
++  FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -B$(build_tooldir)/bin/ -B$(build_tooldir)/lib/ -isystem $(build_tooldir)/include -isystem $(build_tooldir)/sys-include -isystem $(CURDIR)/sys-include'
+ fi
+ 
+ if test "x${use_gnu_ld}" = x &&
--- gcc-6-6.4.0.orig/debian/patches/gcc-textdomain.diff
+++ gcc-6-6.4.0/debian/patches/gcc-textdomain.diff
@@ -0,0 +1,96 @@
+# DP: Set gettext's domain and textdomain to the versioned package name.
+
+Index: b/src/gcc/intl.c
+===================================================================
+--- a/src/gcc/intl.c
++++ b/src/gcc/intl.c
+@@ -55,8 +55,8 @@ gcc_init_libintl (void)
+   setlocale (LC_ALL, "");
+ #endif
+ 
+-  (void) bindtextdomain ("gcc", LOCALEDIR);
+-  (void) textdomain ("gcc");
++  (void) bindtextdomain ("gcc-6", LOCALEDIR);
++  (void) textdomain ("gcc-6");
+ 
+   /* Opening quotation mark.  */
+   open_quote = _("`");
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -4013,8 +4013,8 @@ install-po:
+ 	  dir=$(localedir)/$$lang/LC_MESSAGES; \
+ 	  echo $(mkinstalldirs) $(DESTDIR)$$dir; \
+ 	  $(mkinstalldirs) $(DESTDIR)$$dir || exit 1; \
+-	  echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc.mo; \
+-	  $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc.mo; \
++	  echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc-6.mo; \
++	  $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/gcc-6.mo; \
+ 	done
+ 
+ # Rule for regenerating the message template (gcc.pot).
+Index: b/src/libcpp/init.c
+===================================================================
+--- a/src/libcpp/init.c
++++ b/src/libcpp/init.c
+@@ -155,7 +155,7 @@ init_library (void)
+       init_trigraph_map ();
+ 
+ #ifdef ENABLE_NLS
+-       (void) bindtextdomain (PACKAGE, LOCALEDIR);
++       (void) bindtextdomain (PACKAGE PACKAGE_SUFFIX, LOCALEDIR);
+ #endif
+     }
+ }
+Index: b/src/libcpp/system.h
+===================================================================
+--- a/src/libcpp/system.h
++++ b/src/libcpp/system.h
+@@ -280,7 +280,7 @@ extern int errno;
+ #endif
+ 
+ #ifndef _
+-# define _(msgid) dgettext (PACKAGE, msgid)
++# define _(msgid) dgettext (PACKAGE PACKAGE_SUFFIX, msgid)
+ #endif
+ 
+ #ifndef N_
+Index: b/src/libcpp/Makefile.in
+===================================================================
+--- a/src/libcpp/Makefile.in
++++ b/src/libcpp/Makefile.in
+@@ -49,6 +49,7 @@ LDFLAGS = @LDFLAGS@
+ LIBICONV = @LIBICONV@
+ LIBINTL = @LIBINTL@
+ PACKAGE = @PACKAGE@
++PACKAGE_SUFFIX = -6
+ RANLIB = @RANLIB@
+ SHELL = @SHELL@
+ USED_CATALOGS = @USED_CATALOGS@
+@@ -72,10 +73,12 @@ depcomp = $(SHELL) $(srcdir)/../depcomp
+ 
+ INCLUDES = -I$(srcdir) -I. -I$(srcdir)/../include @INCINTL@ \
+ 	-I$(srcdir)/include
++DEBCPPFLAGS += -DPACKAGE_SUFFIX=\"$(strip $(PACKAGE_SUFFIX))\"
+ 
+-ALL_CFLAGS = $(CFLAGS) $(WARN_CFLAGS) $(INCLUDES) $(CPPFLAGS) $(PICFLAG)
++ALL_CFLAGS = $(CFLAGS) $(WARN_CFLAGS) $(INCLUDES) $(CPPFLAGS) $(PICFLAG) \
++	$(DEBCPPFLAGS)
+ ALL_CXXFLAGS = $(CXXFLAGS) $(WARN_CXXFLAGS) $(NOEXCEPTION_FLAGS) $(INCLUDES) \
+-	$(CPPFLAGS) $(PICFLAG)
++	$(CPPFLAGS) $(PICFLAG) $(DEBCPPFLAGS)
+ 
+ # The name of the compiler to use.
+ COMPILER = $(CXX)
+@@ -164,8 +167,8 @@ install-strip install: all installdirs
+ 	  else continue; \
+ 	  fi; \
+ 	  dir=$(localedir)/$$lang/LC_MESSAGES; \
+-	  echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/$(PACKAGE).mo; \
+-	  $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/$(PACKAGE).mo; \
++	  echo $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/$(PACKAGE)$(PACKAGE_SUFFIX).mo; \
++	  $(INSTALL_DATA) $$cat $(DESTDIR)$$dir/$(PACKAGE)$(PACKAGE_SUFFIX).mo; \
+ 	done
+ 
+ mostlyclean:
--- gcc-6-6.4.0.orig/debian/patches/gccgo-issue16780.diff
+++ gcc-6-6.4.0/debian/patches/gccgo-issue16780.diff
@@ -0,0 +1,39 @@
+# DP: gccgo: Call default_file_start from s390_asm_file_start
+
+https://gcc.gnu.org/ml/gcc-patches/2016-08/msg01655.html
+
+gcc/
+
+2016-08-23  Ian Lance Taylor  <iant@golang.org>
+
+	* config/s390/s390.c (s390_asm_file_start): Call
+	default_file_start.
+
+gcc/testsuite/
+
+2016-08-23  Ian Lance Taylor  <iant@golang.org>
+
+	* gcc.target/s390/nolrl-1.c: Don't match the file name.
+
+Index: b/src/gcc/config/s390/s390.c
+===================================================================
+--- a/src/gcc/config/s390/s390.c
++++ b/src/gcc/config/s390/s390.c
+@@ -14973,6 +14973,7 @@ s390_vector_alignment (const_tree type)
+ static void
+ s390_asm_file_start (void)
+ {
++  default_file_start ();
+   s390_asm_output_machine_for_arch (asm_out_file);
+ }
+ #endif
+Index: b/src/gcc/testsuite/gcc.target/s390/nolrl-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nolrl-1.c
++++ b/src/gcc/testsuite/gcc.target/s390/nolrl-1.c
+@@ -16,4 +16,4 @@ bar ()
+     foo (z);
+ }
+ 
+-/* { dg-final { scan-assembler-not "lrl" } } */
++/* { dg-final { scan-assembler-not "\tlrl" } } */
--- gcc-6-6.4.0.orig/debian/patches/gccgo-version.diff
+++ gcc-6-6.4.0/debian/patches/gccgo-version.diff
@@ -0,0 +1,91 @@
+# DP: Omit the subminor number from the go libdir
+
+Index: b/src/gcc/go/Make-lang.in
+===================================================================
+--- a/src/gcc/go/Make-lang.in
++++ b/src/gcc/go/Make-lang.in
+@@ -219,7 +219,9 @@ go.stageprofile: stageprofile-start
+ go.stagefeedback: stagefeedback-start
+ 	-mv go/*$(objext) stagefeedback/go
+ 
+-CFLAGS-go/go-lang.o += -DDEFAULT_TARGET_VERSION=\"$(version)\" \
++short_version := $(shell echo $(version) | sed -r 's/([0-9]+).*/\1/')
++
++CFLAGS-go/go-lang.o += -DDEFAULT_TARGET_VERSION=\"$(short_version)\" \
+ 	-DDEFAULT_TARGET_MACHINE=\"$(target_noncanonical)\"
+ 
+ GOINCLUDES = -I $(srcdir)/go -I $(srcdir)/go/gofrontend
+Index: b/src/libgo/Makefile.in
+===================================================================
+--- a/src/libgo/Makefile.in
++++ b/src/libgo/Makefile.in
+@@ -498,14 +498,15 @@ SUFFIXES = .c .go .gox .o .obj .lo .a
+ @LIBGO_IS_RTEMS_TRUE@subdirs = testsuite
+ SUBDIRS = ${subdirs}
+ gcc_version := $(shell $(GOC) -dumpversion)
++short_version := $(shell echo $(gcc_version) | sed -r 's/([0-9]+)\..*/\1/')
+ MAINT_CHARSET = latin1
+ mkinstalldirs = $(SHELL) $(toplevel_srcdir)/mkinstalldirs
+ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
+ toolexecdir = $(glibgo_toolexecdir)
+ toolexeclibdir = $(glibgo_toolexeclibdir)
+-toolexeclibgodir = $(nover_glibgo_toolexeclibdir)/go/$(gcc_version)/$(target_alias)
+-libexecsubdir = $(libexecdir)/gcc/$(target_alias)/$(gcc_version)
++toolexeclibgodir = $(nover_glibgo_toolexeclibdir)/go/$(short_version)
++libexecsubdir = $(libexecdir)/gcc/$(target_alias)/$(short_version)
+ WARN_CFLAGS = $(WARN_FLAGS) $(WERROR)
+ 
+ # -I/-D flags to pass when compiling.
+Index: b/src/libgo/Makefile.am
+===================================================================
+--- a/src/libgo/Makefile.am
++++ b/src/libgo/Makefile.am
+@@ -16,6 +16,7 @@ endif
+ SUBDIRS = ${subdirs}
+ 
+ gcc_version := $(shell $(GOC) -dumpversion)
++short_version := $(shell echo $(gcc_version) | sed -r 's/([0-9]+)\..*/\1/')
+ 
+ MAINT_CHARSET = latin1
+ 
+@@ -25,8 +26,8 @@ STAMP = echo timestamp >
+ 
+ toolexecdir = $(glibgo_toolexecdir)
+ toolexeclibdir = $(glibgo_toolexeclibdir)
+-toolexeclibgodir = $(nover_glibgo_toolexeclibdir)/go/$(gcc_version)/$(target_alias)
+-libexecsubdir = $(libexecdir)/gcc/$(target_alias)/$(gcc_version)
++toolexeclibgodir = $(nover_glibgo_toolexeclibdir)/go/$(short_version)
++libexecsubdir = $(libexecdir)/gcc/$(target_alias)/$(short_version)
+ 
+ LIBFFI = @LIBFFI@
+ LIBFFIINCS = @LIBFFIINCS@
+Index: b/src/gotools/Makefile.am
+===================================================================
+--- a/src/gotools/Makefile.am
++++ b/src/gotools/Makefile.am
+@@ -18,8 +18,9 @@
+ ACLOCAL_AMFLAGS = -I ./config -I ../config
+ 
+ gcc_version := $(shell $(GCC_FOR_TARGET) -dumpversion)
++short_version := $(shell echo $(gcc_version) | sed -r 's/([0-9]+)\..*/\1/')
+ 
+-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version)
++libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(short_version)
+ 
+ mkinstalldirs = $(SHELL) $(toplevel_srcdir)/mkinstalldirs
+ PWD_COMMAND = $${PWDCMD-pwd}
+Index: b/src/gotools/Makefile.in
+===================================================================
+--- a/src/gotools/Makefile.in
++++ b/src/gotools/Makefile.in
+@@ -247,7 +247,8 @@ top_builddir = @top_builddir@
+ top_srcdir = @top_srcdir@
+ ACLOCAL_AMFLAGS = -I ./config -I ../config
+ gcc_version := $(shell $(GCC_FOR_TARGET) -dumpversion)
+-libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version)
++short_version := $(shell echo $(gcc_version) | sed -r 's/([0-9]+)\..*/\1/')
++libexecsubdir = $(libexecdir)/gcc/$(target_noncanonical)/$(short_version)
+ mkinstalldirs = $(SHELL) $(toplevel_srcdir)/mkinstalldirs
+ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
--- gcc-6-6.4.0.orig/debian/patches/gcj-arm-mode.diff
+++ gcc-6-6.4.0/debian/patches/gcj-arm-mode.diff
@@ -0,0 +1,33 @@
+# DP: For armhf, force arm mode instead of thumb mode
+
+--- a/src/libjava/configure.host
++++ b/src/libjava/configure.host
+@@ -66,6 +66,9 @@
+     ;;
+ esac
+ 
++# on armhf force arm mode
++libgcj_flags="${libgcj_flags} -marm"
++
+ AM_RUNTESTFLAGS= 
+ 
+ # Set any host dependent compiler flags.
+--- a/src/gcc/java/lang-specs.h
++++ b/src/gcc/java/lang-specs.h
+@@ -47,7 +47,7 @@
+     %{.class|.zip|.jar|!fsyntax-only:jc1				\
+       %{.java|fsaw-java-file:%U.jar -fsource-filename=%i %<ffilelist-file} \
+       %{.class|.zip|.jar|ffilelist-file|fcompile-resource*:%i}		\
+-      %(jc1) %(cc1_options) %{I*} %{!findirect-dispatch:-faux-classpath %U.zip} \
++      %(jc1) %(cc1_options) -marm %{I*} %{!findirect-dispatch:-faux-classpath %U.zip} \
+       %{MD:-MD_} %{MMD:-MMD_} %{M} %{MM} %{MA} %{MT*} %{MF*}\
+       %(invoke_as)}",
+       0, 0, 0},
+--- a/src/libjava/libgcj.spec.in
++++ b/src/libjava/libgcj.spec.in
+@@ -9,4 +9,4 @@
+ %rename lib liborig
+ *lib: @LD_START_STATIC_SPEC@ @LIBGCJ_SPEC@ @LD_FINISH_STATIC_SPEC@ @LIBMATHSPEC@ @LDLIBICONV@ @GCSPEC@ @THREADSPEC@ @ZLIBSPEC@ @SYSTEMSPEC@ %(libgcc) @LIBSTDCXXSPEC@ %(liborig)
+ 
+-*jc1: @HASH_SYNC_SPEC@ @DIVIDESPEC@ @CHECKREFSPEC@ @JC1GCSPEC@ @EXCEPTIONSPEC@ @BACKTRACESPEC@ @IEEESPEC@ @ATOMICSPEC@ @LIBGCJ_BC_SPEC@ -fkeep-inline-functions
++*jc1: @HASH_SYNC_SPEC@ @DIVIDESPEC@ @CHECKREFSPEC@ @JC1GCSPEC@ @EXCEPTIONSPEC@ @BACKTRACESPEC@ @IEEESPEC@ @ATOMICSPEC@ @LIBGCJ_BC_SPEC@ -fkeep-inline-functions -marm
--- gcc-6-6.4.0.orig/debian/patches/gdc-6-doc.diff
+++ gcc-6-6.4.0/debian/patches/gdc-6-doc.diff
@@ -0,0 +1,96 @@
+# DP: This implements D language support in the GCC back end, and adds
+# DP: relevant documentation about the GDC front end (documentation part).
+
+--- a/src/gcc/doc/frontends.texi
++++ b/src/gcc/doc/frontends.texi
+@@ -9,6 +9,7 @@
+ @cindex GNU Compiler Collection
+ @cindex GNU C Compiler
+ @cindex Ada
++@cindex D
+ @cindex Fortran
+ @cindex Go
+ @cindex Java
+@@ -17,7 +18,7 @@
+ GCC stands for ``GNU Compiler Collection''.  GCC is an integrated
+ distribution of compilers for several major programming languages.  These
+ languages currently include C, C++, Objective-C, Objective-C++, Java,
+-Fortran, Ada, and Go.
++Fortran, Ada, D and Go.
+ 
+ The abbreviation @dfn{GCC} has multiple meanings in common use.  The
+ current official meaning is ``GNU Compiler Collection'', which refers
+--- a/src/gcc/doc/install.texi
++++ b/src/gcc/doc/install.texi
+@@ -1547,12 +1547,12 @@ their runtime libraries should be built.  For a list of valid values for
+ grep ^language= */config-lang.in
+ @end smallexample
+ Currently, you can use any of the following:
+-@code{all}, @code{ada}, @code{c}, @code{c++}, @code{fortran},
++@code{all}, @code{ada}, @code{c}, @code{c++}, @code{d}, @code{fortran},
+ @code{go}, @code{java}, @code{jit}, @code{lto}, @code{objc}, @code{obj-c++}.
+ Building the Ada compiler has special requirements, see below.
+ If you do not pass this flag, or specify the option @code{all}, then all
+ default languages available in the @file{gcc} sub-tree will be configured.
+-Ada, Go, Jit, and Objective-C++ are not default languages.  LTO is not a
++Ada, D, Go, Jit, and Objective-C++ are not default languages.  LTO is not a
+ default language, but is built by default because @option{--enable-lto} is
+ enabled by default.  The other languages are default languages.
+ 
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -1269,6 +1269,15 @@ called @dfn{specs}.
+ Ada source code file containing a library unit body (a subprogram or
+ package body).  Such files are also called @dfn{bodies}.
+ 
++@item @var{file}.d
++D source code file.
++
++@item @var{file}.di
++D interface code file.
++
++@item @var{file}.dd
++D documentation code file.
++
+ @c GCC also knows about some suffixes for languages not yet included:
+ @c Pascal:
+ @c @var{file}.p
+@@ -1304,6 +1313,7 @@ objective-c  objective-c-header  objective-c-cpp-output
+ objective-c++ objective-c++-header objective-c++-cpp-output
+ assembler  assembler-with-cpp
+ ada
++d
+ f77  f77-cpp-input f95  f95-cpp-input
+ go
+ java
+--- a/src/gcc/doc/sourcebuild.texi
++++ b/src/gcc/doc/sourcebuild.texi
+@@ -109,6 +109,9 @@ The Objective-C and Objective-C++ runtime library.
+ @item libquadmath
+ The runtime support library for quad-precision math operations.
+ 
++@item libphobos
++The D standard runtime library.
++
+ @item libssp
+ The Stack protector runtime library.
+ 
+--- a/src/gcc/doc/standards.texi
++++ b/src/gcc/doc/standards.texi
+@@ -280,6 +280,16 @@ available online, see @uref{http://gcc.gnu.org/readings.html}
+ As of the GCC 4.7.1 release, GCC supports the Go 1 language standard,
+ described at @uref{http://golang.org/doc/go1.html}.
+ 
++@section D language
++
++The D language is under development as of this writing; see the
++@uref{http://dlang.org/@/language-reference.html, current language
++reference}.  At present the current major version of D is 2.0, and
++there is no way to describe the language supported by GCC in terms of
++a specific minor version.  In general GCC follows the D frontend
++releases closely, and any given GCC release will support the current
++language as of the date that the release was frozen.
++
+ @section References for Other Languages
+ 
+ @xref{Top, GNAT Reference Manual, About This Guide, gnat_rm,
--- gcc-6-6.4.0.orig/debian/patches/gdc-6.diff
+++ gcc-6-6.4.0/debian/patches/gdc-6.diff
@@ -0,0 +1,139 @@
+# DP: This implements D language support in the GCC back end, and adds
+# DP: relevant documentation about the GDC front end (code part).
+
+Index: b/src/gcc/config/darwin.h
+===================================================================
+--- a/src/gcc/config/darwin.h
++++ b/src/gcc/config/darwin.h
+@@ -49,6 +49,10 @@ see the files COPYING3 and COPYING.RUNTI
+ /* Suppress g++ attempt to link in the math library automatically. */
+ #define MATH_LIBRARY ""
+ 
++/* Suppress gdc attempt to link in the thread and time library automatically. */
++#define THREAD_LIBRARY ""
++#define TIME_LIBRARY ""
++
+ /* We have atexit.  */
+ 
+ #define HAVE_ATEXIT
+Index: b/src/gcc/config/i386/cygming.h
+===================================================================
+--- a/src/gcc/config/i386/cygming.h
++++ b/src/gcc/config/i386/cygming.h
+@@ -175,6 +175,10 @@ along with GCC; see the file COPYING3.
+ 
+ #undef MATH_LIBRARY
+ #define MATH_LIBRARY ""
++#undef THREAD_LIBRARY
++#define THREAD_LIBRARY ""
++#undef TIME_LIBRARY
++#define TIME_LIBRARY ""
+ 
+ #undef TARGET_LIBC_HAS_FUNCTION
+ #define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function
+Index: b/src/gcc/config/linux-android.h
+===================================================================
+--- a/src/gcc/config/linux-android.h
++++ b/src/gcc/config/linux-android.h
+@@ -57,3 +57,9 @@
+ 
+ #define ANDROID_ENDFILE_SPEC \
+   "%{shared: crtend_so%O%s;: crtend_android%O%s}"
++
++/* Suppress gdc attempt to link in the thread and time library automatically. */
++#if ANDROID_DEFAULT
++# define THREAD_LIBRARY ""
++# define TIME_LIBRARY ""
++#endif
+Index: b/src/gcc/config/rs6000/rs6000.c
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.c
++++ b/src/gcc/config/rs6000/rs6000.c
+@@ -28685,7 +28685,8 @@ rs6000_output_function_epilogue (FILE *f
+       if (lang_GNU_C ()
+ 	  || ! strcmp (language_string, "GNU GIMPLE")
+ 	  || ! strcmp (language_string, "GNU Go")
+-	  || ! strcmp (language_string, "libgccjit"))
++	  || ! strcmp (language_string, "libgccjit")
++	  || ! strcmp (language_string, "GNU D"))
+ 	i = 0;
+       else if (! strcmp (language_string, "GNU F77")
+ 	       || lang_GNU_Fortran ())
+Index: b/src/gcc/dwarf2out.c
+===================================================================
+--- a/src/gcc/dwarf2out.c
++++ b/src/gcc/dwarf2out.c
+@@ -4846,6 +4846,16 @@ is_ada (void)
+   return lang == DW_LANG_Ada95 || lang == DW_LANG_Ada83;
+ }
+ 
++/* Return TRUE if the language is D.  */
++
++static inline bool
++is_dlang (void)
++{
++  unsigned int lang = get_AT_unsigned (comp_unit_die (), DW_AT_language);
++
++  return lang == DW_LANG_D;
++}
++
+ /* Remove the specified attribute if present.  Return TRUE if removal
+    was successful.  */
+ 
+@@ -21956,6 +21966,8 @@ gen_compile_unit_die (const char *filena
+ 	language = DW_LANG_ObjC;
+       else if (strcmp (language_string, "GNU Objective-C++") == 0)
+ 	language = DW_LANG_ObjC_plus_plus;
++      else if (strcmp (language_string, "GNU D") == 0)
++	language = DW_LANG_D;
+       else if (dwarf_version >= 5 || !dwarf_strict)
+ 	{
+ 	  if (strcmp (language_string, "GNU Go") == 0)
+@@ -23416,7 +23428,7 @@ declare_in_namespace (tree thing, dw_die
+ 
+   if (ns_context != context_die)
+     {
+-      if (is_fortran ())
++      if (is_fortran () || is_dlang ())
+ 	return ns_context;
+       if (DECL_P (thing))
+ 	gen_decl_die (thing, NULL, NULL, ns_context);
+@@ -23439,7 +23451,7 @@ gen_namespace_die (tree decl, dw_die_ref
+     {
+       /* Output a real namespace or module.  */
+       context_die = setup_namespace_context (decl, comp_unit_die ());
+-      namespace_die = new_die (is_fortran ()
++      namespace_die = new_die (is_fortran () || is_dlang ()
+ 			       ? DW_TAG_module : DW_TAG_namespace,
+ 			       context_die, decl);
+       /* For Fortran modules defined in different CU don't add src coords.  */
+@@ -23506,7 +23518,7 @@ gen_decl_die (tree decl, tree origin, st
+       break;
+ 
+     case CONST_DECL:
+-      if (!is_fortran () && !is_ada ())
++      if (!is_fortran () && !is_ada () && !is_dlang ())
+ 	{
+ 	  /* The individual enumerators of an enum type get output when we output
+ 	     the Dwarf representation of the relevant enum type itself.  */
+@@ -24036,7 +24048,7 @@ dwarf2out_decl (tree decl)
+     case CONST_DECL:
+       if (debug_info_level <= DINFO_LEVEL_TERSE)
+ 	return;
+-      if (!is_fortran () && !is_ada ())
++      if (!is_fortran () && !is_ada () && !is_dlang ())
+ 	return;
+       if (TREE_STATIC (decl) && decl_function_context (decl))
+ 	context_die = lookup_decl_die (DECL_CONTEXT (decl));
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -1288,6 +1288,7 @@ static const struct compiler default_com
+   {".java", "#Java", 0, 0, 0}, {".class", "#Java", 0, 0, 0},
+   {".zip", "#Java", 0, 0, 0}, {".jar", "#Java", 0, 0, 0},
+   {".go", "#Go", 0, 1, 0},
++  {".d", "#D", 0, 1, 0}, {".dd", "#D", 0, 1, 0}, {".di", "#D", 0, 1, 0},
+   /* Next come the entries for C.  */
+   {".c", "@c", 0, 0, 1},
+   {"@c",
--- gcc-6-6.4.0.orig/debian/patches/gdc-base-version.diff
+++ gcc-6-6.4.0/debian/patches/gdc-base-version.diff
@@ -0,0 +1,27 @@
+# DP: Use the GCC base version for the D include dir name
+
+Index: b/src/libphobos/m4/druntime.m4
+===================================================================
+--- a/src/libphobos/m4/druntime.m4
++++ b/src/libphobos/m4/druntime.m4
+@@ -43,7 +43,7 @@ AC_DEFUN([DRUNTIME_INSTALL_DIRECTORIES],
+   AC_REQUIRE([AC_PROG_GDC])
+ 
+   AC_MSG_CHECKING([D GCC version])
+-  d_gcc_ver=`$GDC -dumpversion`
++  d_gcc_ver=`$GDC -dumpversion | sed 's/^\(@<:@0-9@:>@*\).*/\1/'`
+   AC_MSG_RESULT($d_gcc_ver)
+   AC_ARG_WITH([cross-host],
+     AC_HELP_STRING([--with-cross-host=HOST],
+Index: b/src/libphobos/configure.ac
+===================================================================
+--- a/src/libphobos/configure.ac
++++ b/src/libphobos/configure.ac
+@@ -53,6 +53,7 @@ m4_rename([_AC_ARG_VAR_PRECIOUS],[glibd_
+ m4_define([_AC_ARG_VAR_PRECIOUS],[])
+ AM_PROG_AS
+ AC_PROG_CC
++dnl dummy change to run autoreconf in this directory
+ AC_PROG_GDC
+ WITH_LOCAL_DRUNTIME([GDC_CHECK_COMPILE], [])
+ 
--- gcc-6-6.4.0.orig/debian/patches/gdc-config-ml.diff
+++ gcc-6-6.4.0/debian/patches/gdc-config-ml.diff
@@ -0,0 +1,55 @@
+# DP: config-ml.in: Add D support.
+
+2015-04-30  Matthias Klose  <doko@ubuntu.com>
+
+        * config-ml.in: Add D support: treat GDC and GDCFLAGS like other
+        compiler/flag environment variables.
+
+Index: b/src/config-ml.in
+===================================================================
+--- a/src/config-ml.in
++++ b/src/config-ml.in
+@@ -525,6 +525,7 @@ multi-do:
+ 				GCJFLAGS="$(GCJFLAGS) $${flags}" \
+ 				GOCFLAGS="$(GOCFLAGS) $${flags}" \
+ 				CXXFLAGS="$(CXXFLAGS) $${flags}" \
++				DFLAGS="$(DFLAGS) $${flags}" \
+ 				LIBCFLAGS="$(LIBCFLAGS) $${flags}" \
+ 				LIBCXXFLAGS="$(LIBCXXFLAGS) $${flags}" \
+ 				LDFLAGS="$(LDFLAGS) $${flags}" \
+@@ -757,7 +758,7 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+         break
+       fi
+     done
+-    ml_config_env='CC="${CC_}$flags" CXX="${CXX_}$flags" F77="${F77_}$flags" GCJ="${GCJ_}$flags" GFORTRAN="${GFORTRAN_}$flags" GOC="${GOC_}$flags"'
++    ml_config_env='CC="${CC_}$flags" CXX="${CXX_}$flags" F77="${F77_}$flags" GCJ="${GCJ_}$flags" GFORTRAN="${GFORTRAN_}$flags" GOC="${GOC_}$flags" GDC="${GDC_}$flags"'
+ 
+     if [ "${with_target_subdir}" = "." ]; then
+ 	CC_=$CC' '
+@@ -766,6 +767,7 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	GCJ_=$GCJ' '
+ 	GFORTRAN_=$GFORTRAN' '
+ 	GOC_=$GOC' '
++	GDC_=$GDC' '
+     else
+ 	# Create a regular expression that matches any string as long
+ 	# as ML_POPDIR.
+@@ -842,6 +844,18 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  esac
+ 	done
+ 
++	GDC_=
++	for arg in ${GDC}; do
++	  case $arg in
++	  -[BIL]"${ML_POPDIR}"/*)
++	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  "${ML_POPDIR}"/*)
++	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  *)
++	    GDC_="${GDC_}${arg} " ;;
++	  esac
++	done
++
+ 	if test "x${LD_LIBRARY_PATH+set}" = xset; then
+ 	  LD_LIBRARY_PATH_=
+ 	  for arg in `echo "$LD_LIBRARY_PATH" | tr ':' ' '`; do
--- gcc-6-6.4.0.orig/debian/patches/gdc-cross-biarch.diff
+++ gcc-6-6.4.0/debian/patches/gdc-cross-biarch.diff
@@ -0,0 +1,13 @@
+# DP: Fix the location of target's libs in cross-build for biarch
+
+--- a/src/config-ml.in
++++ b/src/config-ml.in
+@@ -891,6 +915,8 @@
+ 	  case $arg in
+ 	  -[BIL]"${ML_POPDIR}"/*)
+ 	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  -B*/lib/)
++	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "$FILTER_"`' ' ;;
+ 	  "${ML_POPDIR}"/*)
+ 	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
+ 	  *)
--- gcc-6-6.4.0.orig/debian/patches/gdc-cross-install-location.diff
+++ gcc-6-6.4.0/debian/patches/gdc-cross-install-location.diff
@@ -0,0 +1,22 @@
+--- a/src/libphobos/configure.ac
++++ b/src/libphobos/configure.ac
+@@ -119,6 +119,8 @@
+ AC_SUBST([DRUNTIME_SOVERSION])
+ AC_SUBST([PHOBOS_SOVERSION])
+ 
++# trigger rebuild of the configure file
++
+ # Set default flags (after DRUNTIME_WERROR!)
+ if test -z "$DFLAGS"; then
+     DFLAGS="-Wall $WERROR_FLAG -g -frelease -O2"
+--- a/src/libphobos/m4/druntime.m4
++++ b/src/libphobos/m4/druntime.m4
+@@ -78,7 +78,7 @@ AC_DEFUN([DRUNTIME_INSTALL_DIRECTORIES],
+   AC_SUBST(toolexeclibdir)
+ 
+   # Default case for install directory for D sources files.
+-  gdc_include_dir='${libdir}/gcc/${target_alias}'/${d_gcc_ver}/include/d
++  gdc_include_dir='${libdir}/gcc-cross/${target_alias}'/${d_gcc_ver}/include/d
+   AC_SUBST(gdc_include_dir)
+ ])
+ 
--- gcc-6-6.4.0.orig/debian/patches/gdc-driver-nophobos.diff
+++ gcc-6-6.4.0/debian/patches/gdc-driver-nophobos.diff
@@ -0,0 +1,28 @@
+# DP: Modify gdc driver to have no libphobos by default.
+
+Index: b/src/gcc/d/d-lang.cc
+===================================================================
+--- a/src/gcc/d/d-lang.cc
++++ b/src/gcc/d/d-lang.cc
+@@ -198,7 +198,7 @@ static void
+ d_init_options_struct(gcc_options *opts)
+ {
+   // GCC options
+-  opts->x_flag_exceptions = 1;
++  opts->x_flag_exceptions = 0;
+ 
+   // Avoid range issues for complex multiply and divide.
+   opts->x_flag_complex_method = 2;
+Index: b/src/gcc/d/d-spec.c
+===================================================================
+--- a/src/gcc/d/d-spec.c
++++ b/src/gcc/d/d-spec.c
+@@ -62,7 +62,7 @@ static int library = 0;
+ 
+ /* If true, use the standard D runtime library when linking with
+    standard libraries. */
+-static bool need_phobos = true;
++static bool need_phobos = false;
+ 
+ void
+ lang_specific_driver (cl_decoded_option **in_decoded_options,
--- gcc-6-6.4.0.orig/debian/patches/gdc-frontend-posix.diff
+++ gcc-6-6.4.0/debian/patches/gdc-frontend-posix.diff
@@ -0,0 +1,15 @@
+# DP: Fix build of the D frontend on the Hurd and KFreeBSD.
+
+Index: b/src/gcc/d/dfrontend/object.h
+===================================================================
+--- a/src/gcc/d/dfrontend/object.h
++++ b/src/gcc/d/dfrontend/object.h
+@@ -10,7 +10,7 @@
+ #ifndef OBJECT_H
+ #define OBJECT_H
+ 
+-#define POSIX (__linux__ || __APPLE__ || __FreeBSD__ || __OpenBSD__ || __sun)
++#define POSIX (__linux__ || __GLIBC__ || __gnu_hurd__ || __APPLE__ || __FreeBSD__ || __OpenBSD__ || __sun)
+ 
+ #if __DMC__
+ #pragma once
--- gcc-6-6.4.0.orig/debian/patches/gdc-libphobos-build.diff
+++ gcc-6-6.4.0/debian/patches/gdc-libphobos-build.diff
@@ -0,0 +1,1301 @@
+# DP: This implements building of libphobos library in GCC.
+
+Index: b/src/config-ml.in
+===================================================================
+--- a/src/config-ml.in
++++ b/src/config-ml.in
+@@ -513,6 +513,7 @@ multi-do:
+ 				exec_prefix="$(exec_prefix)" \
+ 				GCJFLAGS="$(GCJFLAGS) $${flags}" \
+ 				GOCFLAGS="$(GOCFLAGS) $${flags}" \
++				GDCFLAGS="$(GDCFLAGS) $${flags}" \
+ 				CXXFLAGS="$(CXXFLAGS) $${flags}" \
+ 				LIBCFLAGS="$(LIBCFLAGS) $${flags}" \
+ 				LIBCXXFLAGS="$(LIBCXXFLAGS) $${flags}" \
+@@ -746,7 +747,7 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+         break
+       fi
+     done
+-    ml_config_env='CC="${CC_}$flags" CXX="${CXX_}$flags" F77="${F77_}$flags" GCJ="${GCJ_}$flags" GFORTRAN="${GFORTRAN_}$flags" GOC="${GOC_}$flags"'
++    ml_config_env='CC="${CC_}$flags" CXX="${CXX_}$flags" F77="${F77_}$flags" GCJ="${GCJ_}$flags" GFORTRAN="${GFORTRAN_}$flags" GOC="${GOC_}$flags" GDC="${GDC_}$flags"'
+ 
+     if [ "${with_target_subdir}" = "." ]; then
+ 	CC_=$CC' '
+@@ -755,6 +756,7 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	GCJ_=$GCJ' '
+ 	GFORTRAN_=$GFORTRAN' '
+ 	GOC_=$GOC' '
++	GDC_=$GDC' '
+     else
+ 	# Create a regular expression that matches any string as long
+ 	# as ML_POPDIR.
+@@ -831,6 +833,18 @@ if [ -n "${multidirs}" ] && [ -z "${ml_n
+ 	  esac
+ 	done
+ 
++	GDC_=
++	for arg in ${GDC}; do
++	  case $arg in
++	  -[BIL]"${ML_POPDIR}"/*)
++	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "s/X\\(-[BIL]${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X-[BIL]${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  "${ML_POPDIR}"/*)
++	    GDC_="${GDC_}"`echo "X${arg}" | sed -n "s/X\\(${popdir_rx}\\).*/\\1/p"`/${ml_dir}`echo "X${arg}" | sed -n "s/X${popdir_rx}\\(.*\\)/\\1/p"`' ' ;;
++	  *)
++	    GDC_="${GDC_}${arg} " ;;
++	  esac
++	done
++
+ 	if test "x${LD_LIBRARY_PATH+set}" = xset; then
+ 	  LD_LIBRARY_PATH_=
+ 	  for arg in `echo "$LD_LIBRARY_PATH" | tr ':' ' '`; do
+Index: b/src/config/multi.m4
+===================================================================
+--- a/src/config/multi.m4
++++ b/src/config/multi.m4
+@@ -65,4 +65,5 @@ CONFIG_SHELL=${CONFIG_SHELL-/bin/sh}
+ CC="$CC"
+ CXX="$CXX"
+ GFORTRAN="$GFORTRAN"
+-GCJ="$GCJ"])])dnl
++GCJ="$GCJ"
++GDC="$GDC"])])dnl
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -172,6 +172,8 @@ target_libraries="target-libgcc \
+ 		target-libssp \
+ 		target-libquadmath \
+ 		target-libgfortran \
++		target-zlib \
++		target-libphobos \
+ 		target-boehm-gc \
+ 		${libgcj} \
+ 		target-libobjc \
+@@ -1375,6 +1377,7 @@ if test "${build}" != "${host}" ; then
+   GCJ_FOR_BUILD=${GCJ_FOR_BUILD-gcj}
+   GFORTRAN_FOR_BUILD=${GFORTRAN_FOR_BUILD-gfortran}
+   GOC_FOR_BUILD=${GOC_FOR_BUILD-gccgo}
++  GDC_FOR_BUILD=${GDC_FOR_BUILD-gdc}
+   DLLTOOL_FOR_BUILD=${DLLTOOL_FOR_BUILD-dlltool}
+   LD_FOR_BUILD=${LD_FOR_BUILD-ld}
+   NM_FOR_BUILD=${NM_FOR_BUILD-nm}
+@@ -1389,6 +1392,7 @@ else
+   GCJ_FOR_BUILD="\$(GCJ)"
+   GFORTRAN_FOR_BUILD="\$(GFORTRAN)"
+   GOC_FOR_BUILD="\$(GOC)"
++  GDC_FOR_BUILD="\$(GDC)"
+   DLLTOOL_FOR_BUILD="\$(DLLTOOL)"
+   LD_FOR_BUILD="\$(LD)"
+   NM_FOR_BUILD="\$(NM)"
+@@ -3321,6 +3325,7 @@ AC_SUBST(DLLTOOL_FOR_BUILD)
+ AC_SUBST(GCJ_FOR_BUILD)
+ AC_SUBST(GFORTRAN_FOR_BUILD)
+ AC_SUBST(GOC_FOR_BUILD)
++AC_SUBST(GDC_FOR_BUILD)
+ AC_SUBST(LDFLAGS_FOR_BUILD)
+ AC_SUBST(LD_FOR_BUILD)
+ AC_SUBST(NM_FOR_BUILD)
+@@ -3431,6 +3436,7 @@ NCN_STRICT_CHECK_TARGET_TOOLS(GCC_FOR_TA
+ NCN_STRICT_CHECK_TARGET_TOOLS(GCJ_FOR_TARGET, gcj)
+ NCN_STRICT_CHECK_TARGET_TOOLS(GFORTRAN_FOR_TARGET, gfortran)
+ NCN_STRICT_CHECK_TARGET_TOOLS(GOC_FOR_TARGET, gccgo)
++NCN_STRICT_CHECK_TARGET_TOOLS(GDC_FOR_TARGET, gdc)
+ 
+ ACX_CHECK_INSTALLED_TARGET_TOOL(AR_FOR_TARGET, ar)
+ ACX_CHECK_INSTALLED_TARGET_TOOL(AS_FOR_TARGET, as)
+@@ -3466,6 +3472,8 @@ GCC_TARGET_TOOL(gfortran, GFORTRAN_FOR_T
+ 		[gcc/gfortran -B$$r/$(HOST_SUBDIR)/gcc/], fortran)
+ GCC_TARGET_TOOL(gccgo, GOC_FOR_TARGET, GOC,
+ 		[gcc/gccgo -B$$r/$(HOST_SUBDIR)/gcc/], go)
++GCC_TARGET_TOOL(gdc, GDC_FOR_TARGET, GDC,
++		[gcc/gdc -B$$r/$(HOST_SUBDIR)/gcc/], d)
+ GCC_TARGET_TOOL(ld, LD_FOR_TARGET, LD, [ld/ld-new])
+ GCC_TARGET_TOOL(lipo, LIPO_FOR_TARGET, LIPO)
+ GCC_TARGET_TOOL(nm, NM_FOR_TARGET, NM, [binutils/nm-new])
+Index: b/src/Makefile.def
+===================================================================
+--- a/src/Makefile.def
++++ b/src/Makefile.def
+@@ -162,6 +162,7 @@ target_modules = { module= libquadmath;
+ target_modules = { module= libgfortran; };
+ target_modules = { module= libobjc; };
+ target_modules = { module= libgo; };
++target_modules = { module= libphobos; };
+ target_modules = { module= libtermcap; no_check=true;
+                    missing=mostlyclean;
+                    missing=clean;
+@@ -319,6 +320,7 @@ flags_to_pass = { flag= GCJ_FOR_TARGET ;
+ flags_to_pass = { flag= GFORTRAN_FOR_TARGET ; };
+ flags_to_pass = { flag= GOC_FOR_TARGET ; };
+ flags_to_pass = { flag= GOCFLAGS_FOR_TARGET ; };
++flags_to_pass = { flag= GDC_FOR_TARGET ; };
+ flags_to_pass = { flag= LD_FOR_TARGET ; };
+ flags_to_pass = { flag= LIPO_FOR_TARGET ; };
+ flags_to_pass = { flag= LDFLAGS_FOR_TARGET ; };
+@@ -596,6 +598,8 @@ dependencies = { module=configure-target
+ dependencies = { module=all-target-libgo; on=all-target-libbacktrace; };
+ dependencies = { module=all-target-libgo; on=all-target-libffi; };
+ dependencies = { module=all-target-libgo; on=all-target-libatomic; };
++dependencies = { module=configure-target-libphobos; on=configure-target-zlib; };
++dependencies = { module=all-target-libphobos; on=all-target-zlib; };
+ dependencies = { module=configure-target-libjava; on=configure-target-zlib; };
+ dependencies = { module=configure-target-libjava; on=configure-target-boehm-gc; };
+ dependencies = { module=configure-target-libjava; on=configure-target-libffi; };
+@@ -660,6 +664,8 @@ languages = { language=objc;	gcc-check-t
+ languages = { language=obj-c++;	gcc-check-target=check-obj-c++; };
+ languages = { language=go;	gcc-check-target=check-go;
+ 				lib-check-target=check-target-libgo; };
++languages = { language=d;	gcc-check-target=check-d;
++				lib-check-target=check-target-libphobos; };
+ 
+ // Toplevel bootstrap
+ bootstrap_stage = { id=1 ; };
+Index: b/src/Makefile.tpl
+===================================================================
+--- a/src/Makefile.tpl
++++ b/src/Makefile.tpl
+@@ -160,6 +160,7 @@ BUILD_EXPORTS = \
+ 	GFORTRAN="$(GFORTRAN_FOR_BUILD)"; export GFORTRAN; \
+ 	GOC="$(GOC_FOR_BUILD)"; export GOC; \
+ 	GOCFLAGS="$(GOCFLAGS_FOR_BUILD)"; export GOCFLAGS; \
++	GDC="$(GDC_FOR_BUILD)"; export GDC; \
+ 	DLLTOOL="$(DLLTOOL_FOR_BUILD)"; export DLLTOOL; \
+ 	LD="$(LD_FOR_BUILD)"; export LD; \
+ 	LDFLAGS="$(LDFLAGS_FOR_BUILD)"; export LDFLAGS; \
+@@ -197,6 +198,7 @@ HOST_EXPORTS = \
+ 	GCJ="$(GCJ)"; export GCJ; \
+ 	GFORTRAN="$(GFORTRAN)"; export GFORTRAN; \
+ 	GOC="$(GOC)"; export GOC; \
++	GDC="$(GDC)"; export GDC; \
+ 	AR="$(AR)"; export AR; \
+ 	AS="$(AS)"; export AS; \
+ 	CC_FOR_BUILD="$(CC_FOR_BUILD)"; export CC_FOR_BUILD; \
+@@ -285,6 +287,7 @@ BASE_TARGET_EXPORTS = \
+ 	GCJ="$(GCJ_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GCJ; \
+ 	GFORTRAN="$(GFORTRAN_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GFORTRAN; \
+ 	GOC="$(GOC_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GOC; \
++	GDC="$(GDC_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GDC; \
+ 	DLLTOOL="$(DLLTOOL_FOR_TARGET)"; export DLLTOOL; \
+ 	LD="$(COMPILER_LD_FOR_TARGET)"; export LD; \
+ 	LDFLAGS="$(LDFLAGS_FOR_TARGET)"; export LDFLAGS; \
+@@ -353,6 +356,7 @@ DLLTOOL_FOR_BUILD = @DLLTOOL_FOR_BUILD@
+ GCJ_FOR_BUILD = @GCJ_FOR_BUILD@
+ GFORTRAN_FOR_BUILD = @GFORTRAN_FOR_BUILD@
+ GOC_FOR_BUILD = @GOC_FOR_BUILD@
++GDC_FOR_BUILD = @GDC_FOR_BUILD@
+ LDFLAGS_FOR_BUILD = @LDFLAGS_FOR_BUILD@
+ LD_FOR_BUILD = @LD_FOR_BUILD@
+ NM_FOR_BUILD = @NM_FOR_BUILD@
+@@ -483,6 +487,7 @@ RAW_CXX_FOR_TARGET=$(STAGE_CC_WRAPPER) @
+ GCJ_FOR_TARGET=$(STAGE_CC_WRAPPER) @GCJ_FOR_TARGET@
+ GFORTRAN_FOR_TARGET=$(STAGE_CC_WRAPPER) @GFORTRAN_FOR_TARGET@
+ GOC_FOR_TARGET=$(STAGE_CC_WRAPPER) @GOC_FOR_TARGET@
++GDC_FOR_TARGET=$(STAGE_CC_WRAPPER) @GDC_FOR_TARGET@
+ DLLTOOL_FOR_TARGET=@DLLTOOL_FOR_TARGET@
+ LD_FOR_TARGET=@LD_FOR_TARGET@
+ 
+@@ -609,6 +614,7 @@ EXTRA_HOST_FLAGS = \
+ 	'GCJ=$(GCJ)' \
+ 	'GFORTRAN=$(GFORTRAN)' \
+ 	'GOC=$(GOC)' \
++	'GDC=$(GDC)' \
+ 	'LD=$(LD)' \
+ 	'LIPO=$(LIPO)' \
+ 	'NM=$(NM)' \
+@@ -665,6 +671,7 @@ EXTRA_TARGET_FLAGS = \
+ 	'GFORTRAN=$$(GFORTRAN_FOR_TARGET) $$(XGCC_FLAGS_FOR_TARGET) $$(TFLAGS)' \
+ 	'GOC=$$(GOC_FOR_TARGET) $$(XGCC_FLAGS_FOR_TARGET) $$(TFLAGS)' \
+ 	'GOCFLAGS=$$(GOCFLAGS_FOR_TARGET)' \
++	'GDC=$$(GDC_FOR_TARGET) $$(XGCC_FLAGS_FOR_TARGET) $$(TFLAGS)' \
+ 	'LD=$(COMPILER_LD_FOR_TARGET)' \
+ 	'LDFLAGS=$$(LDFLAGS_FOR_TARGET)' \
+ 	'LIBCFLAGS=$$(LIBCFLAGS_FOR_TARGET)' \
+Index: b/src/Makefile.in
+===================================================================
+--- a/src/Makefile.in
++++ b/src/Makefile.in
+@@ -157,6 +157,7 @@ BUILD_EXPORTS = \
+ 	GFORTRAN="$(GFORTRAN_FOR_BUILD)"; export GFORTRAN; \
+ 	GOC="$(GOC_FOR_BUILD)"; export GOC; \
+ 	GOCFLAGS="$(GOCFLAGS_FOR_BUILD)"; export GOCFLAGS; \
++	GDC="$(GDC_FOR_BUILD)"; export GDC; \
+ 	DLLTOOL="$(DLLTOOL_FOR_BUILD)"; export DLLTOOL; \
+ 	LD="$(LD_FOR_BUILD)"; export LD; \
+ 	LDFLAGS="$(LDFLAGS_FOR_BUILD)"; export LDFLAGS; \
+@@ -194,6 +195,7 @@ HOST_EXPORTS = \
+ 	GCJ="$(GCJ)"; export GCJ; \
+ 	GFORTRAN="$(GFORTRAN)"; export GFORTRAN; \
+ 	GOC="$(GOC)"; export GOC; \
++	GDC="$(GDC)"; export GDC; \
+ 	AR="$(AR)"; export AR; \
+ 	AS="$(AS)"; export AS; \
+ 	CC_FOR_BUILD="$(CC_FOR_BUILD)"; export CC_FOR_BUILD; \
+@@ -282,6 +284,7 @@ BASE_TARGET_EXPORTS = \
+ 	GCJ="$(GCJ_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GCJ; \
+ 	GFORTRAN="$(GFORTRAN_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GFORTRAN; \
+ 	GOC="$(GOC_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GOC; \
++	GDC="$(GDC_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export GDC; \
+ 	DLLTOOL="$(DLLTOOL_FOR_TARGET)"; export DLLTOOL; \
+ 	LD="$(COMPILER_LD_FOR_TARGET)"; export LD; \
+ 	LDFLAGS="$(LDFLAGS_FOR_TARGET)"; export LDFLAGS; \
+@@ -350,6 +353,7 @@ DLLTOOL_FOR_BUILD = @DLLTOOL_FOR_BUILD@
+ GCJ_FOR_BUILD = @GCJ_FOR_BUILD@
+ GFORTRAN_FOR_BUILD = @GFORTRAN_FOR_BUILD@
+ GOC_FOR_BUILD = @GOC_FOR_BUILD@
++GDC_FOR_BUILD = @GDC_FOR_BUILD@
+ LDFLAGS_FOR_BUILD = @LDFLAGS_FOR_BUILD@
+ LD_FOR_BUILD = @LD_FOR_BUILD@
+ NM_FOR_BUILD = @NM_FOR_BUILD@
+@@ -530,6 +534,7 @@ RAW_CXX_FOR_TARGET=$(STAGE_CC_WRAPPER) @
+ GCJ_FOR_TARGET=$(STAGE_CC_WRAPPER) @GCJ_FOR_TARGET@
+ GFORTRAN_FOR_TARGET=$(STAGE_CC_WRAPPER) @GFORTRAN_FOR_TARGET@
+ GOC_FOR_TARGET=$(STAGE_CC_WRAPPER) @GOC_FOR_TARGET@
++GDC_FOR_TARGET=$(STAGE_CC_WRAPPER) @GDC_FOR_TARGET@
+ DLLTOOL_FOR_TARGET=@DLLTOOL_FOR_TARGET@
+ LD_FOR_TARGET=@LD_FOR_TARGET@
+ 
+@@ -754,6 +759,7 @@ BASE_FLAGS_TO_PASS = \
+ 	"GFORTRAN_FOR_TARGET=$(GFORTRAN_FOR_TARGET)" \
+ 	"GOC_FOR_TARGET=$(GOC_FOR_TARGET)" \
+ 	"GOCFLAGS_FOR_TARGET=$(GOCFLAGS_FOR_TARGET)" \
++	"GDC_FOR_TARGET=$(GDC_FOR_TARGET)" \
+ 	"LD_FOR_TARGET=$(LD_FOR_TARGET)" \
+ 	"LIPO_FOR_TARGET=$(LIPO_FOR_TARGET)" \
+ 	"LDFLAGS_FOR_TARGET=$(LDFLAGS_FOR_TARGET)" \
+@@ -808,6 +814,7 @@ EXTRA_HOST_FLAGS = \
+ 	'GCJ=$(GCJ)' \
+ 	'GFORTRAN=$(GFORTRAN)' \
+ 	'GOC=$(GOC)' \
++	'GDC=$(GDC)' \
+ 	'LD=$(LD)' \
+ 	'LIPO=$(LIPO)' \
+ 	'NM=$(NM)' \
+@@ -864,6 +871,7 @@ EXTRA_TARGET_FLAGS = \
+ 	'GFORTRAN=$$(GFORTRAN_FOR_TARGET) $$(XGCC_FLAGS_FOR_TARGET) $$(TFLAGS)' \
+ 	'GOC=$$(GOC_FOR_TARGET) $$(XGCC_FLAGS_FOR_TARGET) $$(TFLAGS)' \
+ 	'GOCFLAGS=$$(GOCFLAGS_FOR_TARGET)' \
++	'GDC=$$(GDC_FOR_TARGET) $$(XGCC_FLAGS_FOR_TARGET) $$(TFLAGS)' \
+ 	'LD=$(COMPILER_LD_FOR_TARGET)' \
+ 	'LDFLAGS=$$(LDFLAGS_FOR_TARGET)' \
+ 	'LIBCFLAGS=$$(LIBCFLAGS_FOR_TARGET)' \
+@@ -966,6 +974,7 @@ configure-target:  \
+     maybe-configure-target-libgfortran \
+     maybe-configure-target-libobjc \
+     maybe-configure-target-libgo \
++    maybe-configure-target-libphobos \
+     maybe-configure-target-libtermcap \
+     maybe-configure-target-winsup \
+     maybe-configure-target-libgloss \
+@@ -1137,6 +1146,7 @@ all-target: maybe-all-target-libquadmath
+ all-target: maybe-all-target-libgfortran
+ all-target: maybe-all-target-libobjc
+ all-target: maybe-all-target-libgo
++all-target: maybe-all-target-libphobos
+ all-target: maybe-all-target-libtermcap
+ all-target: maybe-all-target-winsup
+ all-target: maybe-all-target-libgloss
+@@ -1235,6 +1245,7 @@ info-target: maybe-info-target-libquadma
+ info-target: maybe-info-target-libgfortran
+ info-target: maybe-info-target-libobjc
+ info-target: maybe-info-target-libgo
++info-target: maybe-info-target-libphobos
+ info-target: maybe-info-target-libtermcap
+ info-target: maybe-info-target-winsup
+ info-target: maybe-info-target-libgloss
+@@ -1326,6 +1337,7 @@ dvi-target: maybe-dvi-target-libquadmath
+ dvi-target: maybe-dvi-target-libgfortran
+ dvi-target: maybe-dvi-target-libobjc
+ dvi-target: maybe-dvi-target-libgo
++dvi-target: maybe-dvi-target-libphobos
+ dvi-target: maybe-dvi-target-libtermcap
+ dvi-target: maybe-dvi-target-winsup
+ dvi-target: maybe-dvi-target-libgloss
+@@ -1417,6 +1429,7 @@ pdf-target: maybe-pdf-target-libquadmath
+ pdf-target: maybe-pdf-target-libgfortran
+ pdf-target: maybe-pdf-target-libobjc
+ pdf-target: maybe-pdf-target-libgo
++pdf-target: maybe-pdf-target-libphobos
+ pdf-target: maybe-pdf-target-libtermcap
+ pdf-target: maybe-pdf-target-winsup
+ pdf-target: maybe-pdf-target-libgloss
+@@ -1508,6 +1521,7 @@ html-target: maybe-html-target-libquadma
+ html-target: maybe-html-target-libgfortran
+ html-target: maybe-html-target-libobjc
+ html-target: maybe-html-target-libgo
++html-target: maybe-html-target-libphobos
+ html-target: maybe-html-target-libtermcap
+ html-target: maybe-html-target-winsup
+ html-target: maybe-html-target-libgloss
+@@ -1599,6 +1613,7 @@ TAGS-target: maybe-TAGS-target-libquadma
+ TAGS-target: maybe-TAGS-target-libgfortran
+ TAGS-target: maybe-TAGS-target-libobjc
+ TAGS-target: maybe-TAGS-target-libgo
++TAGS-target: maybe-TAGS-target-libphobos
+ TAGS-target: maybe-TAGS-target-libtermcap
+ TAGS-target: maybe-TAGS-target-winsup
+ TAGS-target: maybe-TAGS-target-libgloss
+@@ -1690,6 +1705,7 @@ install-info-target: maybe-install-info-
+ install-info-target: maybe-install-info-target-libgfortran
+ install-info-target: maybe-install-info-target-libobjc
+ install-info-target: maybe-install-info-target-libgo
++install-info-target: maybe-install-info-target-libphobos
+ install-info-target: maybe-install-info-target-libtermcap
+ install-info-target: maybe-install-info-target-winsup
+ install-info-target: maybe-install-info-target-libgloss
+@@ -1781,6 +1797,7 @@ install-pdf-target: maybe-install-pdf-ta
+ install-pdf-target: maybe-install-pdf-target-libgfortran
+ install-pdf-target: maybe-install-pdf-target-libobjc
+ install-pdf-target: maybe-install-pdf-target-libgo
++install-pdf-target: maybe-install-pdf-target-libphobos
+ install-pdf-target: maybe-install-pdf-target-libtermcap
+ install-pdf-target: maybe-install-pdf-target-winsup
+ install-pdf-target: maybe-install-pdf-target-libgloss
+@@ -1872,6 +1889,7 @@ install-html-target: maybe-install-html-
+ install-html-target: maybe-install-html-target-libgfortran
+ install-html-target: maybe-install-html-target-libobjc
+ install-html-target: maybe-install-html-target-libgo
++install-html-target: maybe-install-html-target-libphobos
+ install-html-target: maybe-install-html-target-libtermcap
+ install-html-target: maybe-install-html-target-winsup
+ install-html-target: maybe-install-html-target-libgloss
+@@ -1963,6 +1981,7 @@ installcheck-target: maybe-installcheck-
+ installcheck-target: maybe-installcheck-target-libgfortran
+ installcheck-target: maybe-installcheck-target-libobjc
+ installcheck-target: maybe-installcheck-target-libgo
++installcheck-target: maybe-installcheck-target-libphobos
+ installcheck-target: maybe-installcheck-target-libtermcap
+ installcheck-target: maybe-installcheck-target-winsup
+ installcheck-target: maybe-installcheck-target-libgloss
+@@ -2054,6 +2073,7 @@ mostlyclean-target: maybe-mostlyclean-ta
+ mostlyclean-target: maybe-mostlyclean-target-libgfortran
+ mostlyclean-target: maybe-mostlyclean-target-libobjc
+ mostlyclean-target: maybe-mostlyclean-target-libgo
++mostlyclean-target: maybe-mostlyclean-target-libphobos
+ mostlyclean-target: maybe-mostlyclean-target-libtermcap
+ mostlyclean-target: maybe-mostlyclean-target-winsup
+ mostlyclean-target: maybe-mostlyclean-target-libgloss
+@@ -2145,6 +2165,7 @@ clean-target: maybe-clean-target-libquad
+ clean-target: maybe-clean-target-libgfortran
+ clean-target: maybe-clean-target-libobjc
+ clean-target: maybe-clean-target-libgo
++clean-target: maybe-clean-target-libphobos
+ clean-target: maybe-clean-target-libtermcap
+ clean-target: maybe-clean-target-winsup
+ clean-target: maybe-clean-target-libgloss
+@@ -2236,6 +2257,7 @@ distclean-target: maybe-distclean-target
+ distclean-target: maybe-distclean-target-libgfortran
+ distclean-target: maybe-distclean-target-libobjc
+ distclean-target: maybe-distclean-target-libgo
++distclean-target: maybe-distclean-target-libphobos
+ distclean-target: maybe-distclean-target-libtermcap
+ distclean-target: maybe-distclean-target-winsup
+ distclean-target: maybe-distclean-target-libgloss
+@@ -2327,6 +2349,7 @@ maintainer-clean-target: maybe-maintaine
+ maintainer-clean-target: maybe-maintainer-clean-target-libgfortran
+ maintainer-clean-target: maybe-maintainer-clean-target-libobjc
+ maintainer-clean-target: maybe-maintainer-clean-target-libgo
++maintainer-clean-target: maybe-maintainer-clean-target-libphobos
+ maintainer-clean-target: maybe-maintainer-clean-target-libtermcap
+ maintainer-clean-target: maybe-maintainer-clean-target-winsup
+ maintainer-clean-target: maybe-maintainer-clean-target-libgloss
+@@ -2474,6 +2497,7 @@ check-target:  \
+     maybe-check-target-libgfortran \
+     maybe-check-target-libobjc \
+     maybe-check-target-libgo \
++    maybe-check-target-libphobos \
+     maybe-check-target-libtermcap \
+     maybe-check-target-winsup \
+     maybe-check-target-libgloss \
+@@ -2661,6 +2685,7 @@ install-target:  \
+     maybe-install-target-libgfortran \
+     maybe-install-target-libobjc \
+     maybe-install-target-libgo \
++    maybe-install-target-libphobos \
+     maybe-install-target-libtermcap \
+     maybe-install-target-winsup \
+     maybe-install-target-libgloss \
+@@ -2772,6 +2797,7 @@ install-strip-target:  \
+     maybe-install-strip-target-libgfortran \
+     maybe-install-strip-target-libobjc \
+     maybe-install-strip-target-libgo \
++    maybe-install-strip-target-libphobos \
+     maybe-install-strip-target-libtermcap \
+     maybe-install-strip-target-winsup \
+     maybe-install-strip-target-libgloss \
+@@ -41722,6 +41748,464 @@ maintainer-clean-target-libgo:
+ 
+ 
+ 
++.PHONY: configure-target-libphobos maybe-configure-target-libphobos
++maybe-configure-target-libphobos:
++@if gcc-bootstrap
++configure-target-libphobos: stage_current
++@endif gcc-bootstrap
++@if target-libphobos
++maybe-configure-target-libphobos: configure-target-libphobos
++configure-target-libphobos: 
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	echo "Checking multilib configuration for libphobos..."; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libphobos; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libphobos/multilib.tmp 2> /dev/null; \
++	if test -r $(TARGET_SUBDIR)/libphobos/multilib.out; then \
++	  if cmp -s $(TARGET_SUBDIR)/libphobos/multilib.tmp $(TARGET_SUBDIR)/libphobos/multilib.out; then \
++	    rm -f $(TARGET_SUBDIR)/libphobos/multilib.tmp; \
++	  else \
++	    rm -f $(TARGET_SUBDIR)/libphobos/Makefile; \
++	    mv $(TARGET_SUBDIR)/libphobos/multilib.tmp $(TARGET_SUBDIR)/libphobos/multilib.out; \
++	  fi; \
++	else \
++	  mv $(TARGET_SUBDIR)/libphobos/multilib.tmp $(TARGET_SUBDIR)/libphobos/multilib.out; \
++	fi; \
++	test ! -f $(TARGET_SUBDIR)/libphobos/Makefile || exit 0; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libphobos; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	echo Configuring in $(TARGET_SUBDIR)/libphobos; \
++	cd "$(TARGET_SUBDIR)/libphobos" || exit 1; \
++	case $(srcdir) in \
++	  /* | [A-Za-z]:[\\/]*) topdir=$(srcdir) ;; \
++	  *) topdir=`echo $(TARGET_SUBDIR)/libphobos/ | \
++		sed -e 's,\./,,g' -e 's,[^/]*/,../,g' `$(srcdir) ;; \
++	esac; \
++	module_srcdir=libphobos; \
++	rm -f no-such-file || : ; \
++	CONFIG_SITE=no-such-file $(SHELL) \
++	  $$s/$$module_srcdir/configure \
++	  --srcdir=$${topdir}/$$module_srcdir \
++	  $(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
++	  --target=${target_alias}  \
++	  || exit 1
++@endif target-libphobos
++
++
++
++
++
++.PHONY: all-target-libphobos maybe-all-target-libphobos
++maybe-all-target-libphobos:
++@if gcc-bootstrap
++all-target-libphobos: stage_current
++@endif gcc-bootstrap
++@if target-libphobos
++TARGET-target-libphobos=all
++maybe-all-target-libphobos: all-target-libphobos
++all-target-libphobos: configure-target-libphobos
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS)  \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) $(EXTRA_TARGET_FLAGS)   \
++		$(TARGET-target-libphobos))
++@endif target-libphobos
++
++
++
++
++
++.PHONY: check-target-libphobos maybe-check-target-libphobos
++maybe-check-target-libphobos:
++@if target-libphobos
++maybe-check-target-libphobos: check-target-libphobos
++
++check-target-libphobos:
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)   check)
++
++@endif target-libphobos
++
++.PHONY: install-target-libphobos maybe-install-target-libphobos
++maybe-install-target-libphobos:
++@if target-libphobos
++maybe-install-target-libphobos: install-target-libphobos
++
++install-target-libphobos: installdirs
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install)
++
++@endif target-libphobos
++
++.PHONY: install-strip-target-libphobos maybe-install-strip-target-libphobos
++maybe-install-strip-target-libphobos:
++@if target-libphobos
++maybe-install-strip-target-libphobos: install-strip-target-libphobos
++
++install-strip-target-libphobos: installdirs
++	@: $(MAKE); $(unstage)
++	@r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(TARGET_FLAGS_TO_PASS)  install-strip)
++
++@endif target-libphobos
++
++# Other targets (info, dvi, pdf, etc.)
++
++.PHONY: maybe-info-target-libphobos info-target-libphobos
++maybe-info-target-libphobos:
++@if target-libphobos
++maybe-info-target-libphobos: info-target-libphobos
++
++info-target-libphobos: \
++    configure-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing info in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           info) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-dvi-target-libphobos dvi-target-libphobos
++maybe-dvi-target-libphobos:
++@if target-libphobos
++maybe-dvi-target-libphobos: dvi-target-libphobos
++
++dvi-target-libphobos: \
++    configure-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing dvi in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           dvi) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-pdf-target-libphobos pdf-target-libphobos
++maybe-pdf-target-libphobos:
++@if target-libphobos
++maybe-pdf-target-libphobos: pdf-target-libphobos
++
++pdf-target-libphobos: \
++    configure-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           pdf) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-html-target-libphobos html-target-libphobos
++maybe-html-target-libphobos:
++@if target-libphobos
++maybe-html-target-libphobos: html-target-libphobos
++
++html-target-libphobos: \
++    configure-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing html in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           html) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-TAGS-target-libphobos TAGS-target-libphobos
++maybe-TAGS-target-libphobos:
++@if target-libphobos
++maybe-TAGS-target-libphobos: TAGS-target-libphobos
++
++TAGS-target-libphobos: \
++    configure-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing TAGS in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           TAGS) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-install-info-target-libphobos install-info-target-libphobos
++maybe-install-info-target-libphobos:
++@if target-libphobos
++maybe-install-info-target-libphobos: install-info-target-libphobos
++
++install-info-target-libphobos: \
++    configure-target-libphobos \
++    info-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-info in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-info) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-install-pdf-target-libphobos install-pdf-target-libphobos
++maybe-install-pdf-target-libphobos:
++@if target-libphobos
++maybe-install-pdf-target-libphobos: install-pdf-target-libphobos
++
++install-pdf-target-libphobos: \
++    configure-target-libphobos \
++    pdf-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-pdf) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-install-html-target-libphobos install-html-target-libphobos
++maybe-install-html-target-libphobos:
++@if target-libphobos
++maybe-install-html-target-libphobos: install-html-target-libphobos
++
++install-html-target-libphobos: \
++    configure-target-libphobos \
++    html-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           install-html) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-installcheck-target-libphobos installcheck-target-libphobos
++maybe-installcheck-target-libphobos:
++@if target-libphobos
++maybe-installcheck-target-libphobos: installcheck-target-libphobos
++
++installcheck-target-libphobos: \
++    configure-target-libphobos 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing installcheck in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           installcheck) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-mostlyclean-target-libphobos mostlyclean-target-libphobos
++maybe-mostlyclean-target-libphobos:
++@if target-libphobos
++maybe-mostlyclean-target-libphobos: mostlyclean-target-libphobos
++
++mostlyclean-target-libphobos: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           mostlyclean) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-clean-target-libphobos clean-target-libphobos
++maybe-clean-target-libphobos:
++@if target-libphobos
++maybe-clean-target-libphobos: clean-target-libphobos
++
++clean-target-libphobos: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing clean in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           clean) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-distclean-target-libphobos distclean-target-libphobos
++maybe-distclean-target-libphobos:
++@if target-libphobos
++maybe-distclean-target-libphobos: distclean-target-libphobos
++
++distclean-target-libphobos: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           distclean) \
++	  || exit 1
++
++@endif target-libphobos
++
++.PHONY: maybe-maintainer-clean-target-libphobos maintainer-clean-target-libphobos
++maybe-maintainer-clean-target-libphobos:
++@if target-libphobos
++maybe-maintainer-clean-target-libphobos: maintainer-clean-target-libphobos
++
++maintainer-clean-target-libphobos: 
++	@: $(MAKE); $(unstage)
++	@[ -f $(TARGET_SUBDIR)/libphobos/Makefile ] || exit 0; \
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(NORMAL_TARGET_EXPORTS) \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libphobos"; \
++	for flag in $(EXTRA_TARGET_FLAGS); do \
++	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
++	done; \
++	(cd $(TARGET_SUBDIR)/libphobos && \
++	  $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \
++	          "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \
++	          "RANLIB=$${RANLIB}" \
++	          "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" "WINDMC=$${WINDMC}" \
++	           maintainer-clean) \
++	  || exit 1
++
++@endif target-libphobos
++
++
++
++
++
+ .PHONY: configure-target-libtermcap maybe-configure-target-libtermcap
+ maybe-configure-target-libtermcap:
+ @if gcc-bootstrap
+@@ -46107,8 +46591,8 @@ configure-target-libada-sjlj:
+ 	@r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	echo "Checking multilib configuration for libada-sjlj..."; \
+-	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libada-sjlj ; \
+-	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp 2> /dev/null ; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libada-sjlj; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp 2> /dev/null; \
+ 	if test -r $(TARGET_SUBDIR)/libada-sjlj/multilib.out; then \
+ 	  if cmp -s $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp $(TARGET_SUBDIR)/libada-sjlj/multilib.out; then \
+ 	    rm -f $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp; \
+@@ -46120,7 +46604,7 @@ configure-target-libada-sjlj:
+ 	  mv $(TARGET_SUBDIR)/libada-sjlj/multilib.tmp $(TARGET_SUBDIR)/libada-sjlj/multilib.out; \
+ 	fi; \
+ 	test ! -f $(TARGET_SUBDIR)/libada-sjlj/Makefile || exit 0; \
+-	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libada-sjlj ; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libada-sjlj; \
+ 	$(NORMAL_TARGET_EXPORTS)  \
+ 	echo Configuring in $(TARGET_SUBDIR)/libada-sjlj; \
+ 	cd "$(TARGET_SUBDIR)/libada-sjlj" || exit 1; \
+@@ -46225,11 +46709,11 @@ maybe-pdf-target-libada-sjlj: pdf-target
+ pdf-target-libada-sjlj: \
+     configure-target-libada-sjlj 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing pdf in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46282,11 +46766,11 @@ install-pdf-target-libada-sjlj: \
+     configure-target-libada-sjlj \
+     pdf-target-libada-sjlj 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-pdf in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46309,11 +46793,11 @@ install-html-target-libada-sjlj: \
+     configure-target-libada-sjlj \
+     html-target-libada-sjlj 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-html in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46344,11 +46828,11 @@ maybe-mostlyclean-target-libada-sjlj: mo
+ 
+ mostlyclean-target-libada-sjlj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46369,11 +46853,11 @@ maybe-clean-target-libada-sjlj: clean-ta
+ 
+ clean-target-libada-sjlj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing clean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing clean in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46394,11 +46878,11 @@ maybe-distclean-target-libada-sjlj: dist
+ 
+ distclean-target-libada-sjlj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing distclean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46419,11 +46903,11 @@ maybe-maintainer-clean-target-libada-sjl
+ 
+ maintainer-clean-target-libada-sjlj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libada-sjlj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libada-sjlj" ; \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libada-sjlj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46453,8 +46937,8 @@ configure-target-libgnatvsn:
+ 	@r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	echo "Checking multilib configuration for libgnatvsn..."; \
+-	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatvsn ; \
+-	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp 2> /dev/null ; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatvsn; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp 2> /dev/null; \
+ 	if test -r $(TARGET_SUBDIR)/libgnatvsn/multilib.out; then \
+ 	  if cmp -s $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp $(TARGET_SUBDIR)/libgnatvsn/multilib.out; then \
+ 	    rm -f $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp; \
+@@ -46466,7 +46950,7 @@ configure-target-libgnatvsn:
+ 	  mv $(TARGET_SUBDIR)/libgnatvsn/multilib.tmp $(TARGET_SUBDIR)/libgnatvsn/multilib.out; \
+ 	fi; \
+ 	test ! -f $(TARGET_SUBDIR)/libgnatvsn/Makefile || exit 0; \
+-	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatvsn ; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatvsn; \
+ 	$(NORMAL_TARGET_EXPORTS)  \
+ 	echo Configuring in $(TARGET_SUBDIR)/libgnatvsn; \
+ 	cd "$(TARGET_SUBDIR)/libgnatvsn" || exit 1; \
+@@ -46581,11 +47065,11 @@ maybe-pdf-target-libgnatvsn: pdf-target-
+ pdf-target-libgnatvsn: \
+     configure-target-libgnatvsn 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing pdf in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46638,11 +47122,11 @@ install-pdf-target-libgnatvsn: \
+     configure-target-libgnatvsn \
+     pdf-target-libgnatvsn 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-pdf in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46665,11 +47149,11 @@ install-html-target-libgnatvsn: \
+     configure-target-libgnatvsn \
+     html-target-libgnatvsn 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-html in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46700,11 +47184,11 @@ maybe-mostlyclean-target-libgnatvsn: mos
+ 
+ mostlyclean-target-libgnatvsn: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46725,11 +47209,11 @@ maybe-clean-target-libgnatvsn: clean-tar
+ 
+ clean-target-libgnatvsn: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing clean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing clean in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46750,11 +47234,11 @@ maybe-distclean-target-libgnatvsn: distc
+ 
+ distclean-target-libgnatvsn: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing distclean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46775,11 +47259,11 @@ maybe-maintainer-clean-target-libgnatvsn
+ 
+ maintainer-clean-target-libgnatvsn: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatvsn/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libgnatvsn" ; \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libgnatvsn"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46809,8 +47293,8 @@ configure-target-libgnatprj:
+ 	@r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	echo "Checking multilib configuration for libgnatprj..."; \
+-	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatprj ; \
+-	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libgnatprj/multilib.tmp 2> /dev/null ; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatprj; \
++	$(CC_FOR_TARGET) --print-multi-lib > $(TARGET_SUBDIR)/libgnatprj/multilib.tmp 2> /dev/null; \
+ 	if test -r $(TARGET_SUBDIR)/libgnatprj/multilib.out; then \
+ 	  if cmp -s $(TARGET_SUBDIR)/libgnatprj/multilib.tmp $(TARGET_SUBDIR)/libgnatprj/multilib.out; then \
+ 	    rm -f $(TARGET_SUBDIR)/libgnatprj/multilib.tmp; \
+@@ -46822,7 +47306,7 @@ configure-target-libgnatprj:
+ 	  mv $(TARGET_SUBDIR)/libgnatprj/multilib.tmp $(TARGET_SUBDIR)/libgnatprj/multilib.out; \
+ 	fi; \
+ 	test ! -f $(TARGET_SUBDIR)/libgnatprj/Makefile || exit 0; \
+-	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatprj ; \
++	$(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libgnatprj; \
+ 	$(NORMAL_TARGET_EXPORTS)  \
+ 	echo Configuring in $(TARGET_SUBDIR)/libgnatprj; \
+ 	cd "$(TARGET_SUBDIR)/libgnatprj" || exit 1; \
+@@ -46937,11 +47421,11 @@ maybe-pdf-target-libgnatprj: pdf-target-
+ pdf-target-libgnatprj: \
+     configure-target-libgnatprj 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing pdf in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing pdf in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -46994,11 +47478,11 @@ install-pdf-target-libgnatprj: \
+     configure-target-libgnatprj \
+     pdf-target-libgnatprj 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-pdf in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing install-pdf in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -47021,11 +47505,11 @@ install-html-target-libgnatprj: \
+     configure-target-libgnatprj \
+     html-target-libgnatprj 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing install-html in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing install-html in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -47056,11 +47540,11 @@ maybe-mostlyclean-target-libgnatprj: mos
+ 
+ mostlyclean-target-libgnatprj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing mostlyclean in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -47081,11 +47565,11 @@ maybe-clean-target-libgnatprj: clean-tar
+ 
+ clean-target-libgnatprj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing clean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing clean in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -47106,11 +47590,11 @@ maybe-distclean-target-libgnatprj: distc
+ 
+ distclean-target-libgnatprj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing distclean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing distclean in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -47131,11 +47615,11 @@ maybe-maintainer-clean-target-libgnatprj
+ 
+ maintainer-clean-target-libgnatprj: 
+ 	@: $(MAKE); $(unstage)
+-	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0 ; \
++	@[ -f $(TARGET_SUBDIR)/libgnatprj/Makefile ] || exit 0; \
+ 	r=`${PWD_COMMAND}`; export r; \
+ 	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+ 	$(NORMAL_TARGET_EXPORTS) \
+-	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libgnatprj" ; \
++	echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libgnatprj"; \
+ 	for flag in $(EXTRA_TARGET_FLAGS); do \
+ 	  eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \
+ 	done; \
+@@ -49141,6 +49625,14 @@ check-gcc-go:
+ 	(cd gcc && $(MAKE) $(GCC_FLAGS_TO_PASS) check-go);
+ check-go: check-gcc-go check-target-libgo
+ 
++.PHONY: check-gcc-d check-d
++check-gcc-d:
++	r=`${PWD_COMMAND}`; export r; \
++	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
++	$(HOST_EXPORTS) \
++	(cd gcc && $(MAKE) $(GCC_FLAGS_TO_PASS) check-d);
++check-d: check-gcc-d check-target-libphobos
++
+ 
+ # The gcc part of install-no-fixedincludes, which relies on an intimate
+ # knowledge of how a number of gcc internal targets (inter)operate.  Delegate.
+@@ -51347,6 +51839,7 @@ configure-target-libquadmath: stage_last
+ configure-target-libgfortran: stage_last
+ configure-target-libobjc: stage_last
+ configure-target-libgo: stage_last
++configure-target-libphobos: stage_last
+ configure-target-libtermcap: stage_last
+ configure-target-winsup: stage_last
+ configure-target-libgloss: stage_last
+@@ -51385,6 +51878,7 @@ configure-target-libquadmath: maybe-all-
+ configure-target-libgfortran: maybe-all-gcc
+ configure-target-libobjc: maybe-all-gcc
+ configure-target-libgo: maybe-all-gcc
++configure-target-libphobos: maybe-all-gcc
+ configure-target-libtermcap: maybe-all-gcc
+ configure-target-winsup: maybe-all-gcc
+ configure-target-libgloss: maybe-all-gcc
+@@ -52246,6 +52740,8 @@ configure-target-libgo: maybe-all-target
+ all-target-libgo: maybe-all-target-libbacktrace
+ all-target-libgo: maybe-all-target-libffi
+ all-target-libgo: maybe-all-target-libatomic
++configure-target-libphobos: maybe-configure-target-zlib
++all-target-libphobos: maybe-all-target-zlib
+ configure-target-libjava: maybe-configure-target-zlib
+ configure-target-libjava: maybe-configure-target-boehm-gc
+ configure-target-libjava: maybe-configure-target-libffi
+@@ -52364,6 +52860,7 @@ configure-target-libquadmath: maybe-all-
+ configure-target-libgfortran: maybe-all-target-libgcc
+ configure-target-libobjc: maybe-all-target-libgcc
+ configure-target-libgo: maybe-all-target-libgcc
++configure-target-libphobos: maybe-all-target-libgcc
+ configure-target-libtermcap: maybe-all-target-libgcc
+ configure-target-winsup: maybe-all-target-libgcc
+ configure-target-libgloss: maybe-all-target-libgcc
+@@ -52411,6 +52908,8 @@ configure-target-libobjc: maybe-all-targ
+ 
+ configure-target-libgo: maybe-all-target-newlib maybe-all-target-libgloss
+ 
++configure-target-libphobos: maybe-all-target-newlib maybe-all-target-libgloss
++
+ configure-target-libtermcap: maybe-all-target-newlib maybe-all-target-libgloss
+ 
+ configure-target-winsup: maybe-all-target-newlib maybe-all-target-libgloss
--- gcc-6-6.4.0.orig/debian/patches/gdc-multiarch.diff
+++ gcc-6-6.4.0/debian/patches/gdc-multiarch.diff
@@ -0,0 +1,17 @@
+# DP: Set the D target include directory to a multiarch location.
+
+--- a/src/gcc/d/Make-lang.in
++++ b/src/gcc/d/Make-lang.in
+@@ -61,7 +61,11 @@
+ 	$(D_DMD_H)
+ 
+ 
+-gcc_d_target_include_dir=$(gcc_d_include_dir)/$(target_noncanonical)
++ifneq (,$(MULTIARCH_DIRNAME))
++  gcc_d_target_include_dir = /usr/include/$(MULTIARCH_DIRNAME)/d/$(version)
++else
++  gcc_d_target_include_dir=$(gcc_d_include_dir)/$(target_noncanonical)
++endif
+ 
+ # Name of phobos library
+ D_LIBPHOBOS = -DLIBPHOBOS=\"gphobos2\"
--- gcc-6-6.4.0.orig/debian/patches/gdc-profiledbuild.diff
+++ gcc-6-6.4.0/debian/patches/gdc-profiledbuild.diff
@@ -0,0 +1,19 @@
+# DP: Don't build gdc build tools idgen and impcnvgen with profiling flags
+
+--- a/src/gcc/d/Make-lang.in
++++ b/src/gcc/d/Make-lang.in
+@@ -97,6 +97,14 @@
+ d/impcvgen: d/impcnvgen.dmdgen.o
+ 	+$(LINKER_FOR_BUILD) $(BUILD_LINKER_FLAGS) $(BUILD_LDFLAGS) -o $@ $^
+ 
++d/idgen.dmdgen.o: d/dfrontend/idgen.c
++	$(filter-out -fprofile-%,$(DMD_COMPILE)) $(D_INCLUDES) $<
++	$(POSTCOMPILE)
++
++d/impcnvgen.dmdgen.o: $(srcdir)/d/dfrontend/impcnvgen.c
++	$(filter-out -fprofile-%,$(DMDGEN_COMPILE)) $(D_INCLUDES) $<
++	$(POSTCOMPILE)
++
+ # Generated sources.
+ d/id.c: d/idgen
+ 	cd d && ./idgen
--- gcc-6-6.4.0.orig/debian/patches/gdc-texinfo.diff
+++ gcc-6-6.4.0/debian/patches/gdc-texinfo.diff
@@ -0,0 +1,55 @@
+# DP: Add macros for the gdc texinfo documentation.
+
+Index: b/src/gcc/d/gdc.texi
+===================================================================
+--- a/src/gcc/d/gdc.texi
++++ b/src/gcc/d/gdc.texi
+@@ -43,6 +43,22 @@ man page gfdl(7).
+ @insertcopying
+ @end ifinfo
+ 
++@macro versionsubtitle
++@ifclear DEVELOPMENT
++@subtitle For @sc{gcc} version @value{version-GCC}
++@end ifclear
++@ifset DEVELOPMENT
++@subtitle For @sc{gcc} version @value{version-GCC} (pre-release)
++@end ifset
++@ifset VERSION_PACKAGE
++@sp 1
++@subtitle @value{VERSION_PACKAGE}
++@end ifset
++@c Even if there are no authors, the second titlepage line should be
++@c forced to the bottom of the page.
++@vskip 0pt plus 1filll
++@end macro
++
+ @titlepage
+ @title The GNU D Compiler
+ @versionsubtitle
+@@ -138,6 +154,25 @@ remainder.
+ 
+ @c man end
+ 
++@macro gcctabopt{body}
++@code{\body\}
++@end macro
++@macro gccoptlist{body}
++@smallexample
++\body\
++@end smallexample
++@end macro
++@c Makeinfo handles the above macro OK, TeX needs manual line breaks;
++@c they get lost at some point in handling the macro.  But if @macro is
++@c used here rather than @alias, it produces double line breaks.
++@iftex
++@alias gol = *
++@end iftex
++@ifnottex
++@macro gol
++@end macro
++@end ifnottex
++
+ @c man begin OPTIONS gdc
+ 
+ @table @gcctabopt
--- gcc-6-6.4.0.orig/debian/patches/gdc-updates.diff
+++ gcc-6-6.4.0/debian/patches/gdc-updates.diff
@@ -0,0 +1,26 @@
+# DP: gdc updates up to 20160115.
+
+	* Make-lang.in (d-warn): Filter out -Wmissing-format-attribute.
+
+--- a/src/gcc/d/Make-lang.in
++++ b/src/gcc/d/Make-lang.in
+@@ -51,7 +51,7 @@
+ 	cp gdc$(exeext) gdc-cross$(exeext)
+ 
+ # Filter out pedantic and virtual overload warnings.
+-d-warn = $(filter-out -pedantic -Woverloaded-virtual, $(STRICT_WARN))
++d-warn = $(filter-out -pedantic -Woverloaded-virtual -Wmissing-format-attribute, $(STRICT_WARN))
+ 
+ # D Frontend has slightly relaxed warnings compared to rest of GDC.
+ DMD_WARN_CXXFLAGS = -Wno-deprecated -Wstrict-aliasing -Wuninitialized
+--- a/src/libphobos/src/std/internal/math/gammafunction.d
++++ b/src/libphobos/src/std/internal/math/gammafunction.d
+@@ -420,7 +420,7 @@
+         if ( p == q )
+             return real.infinity;
+         int intpart = cast(int)(p);
+-        real sgngam = 1;
++        real sgngam = 1.0L;
+         if ( (intpart & 1) == 0 )
+             sgngam = -1;
+         z = q - p;
--- gcc-6-6.4.0.orig/debian/patches/gdc-versym-cpu.diff
+++ gcc-6-6.4.0/debian/patches/gdc-versym-cpu.diff
@@ -0,0 +1,382 @@
+# DP: Implements D CPU version conditions.
+
+This implements the following versions:
+* D_HardFloat
+* D_SoftFloat
+
+for all supported architectures. And these where appropriate:
+* ARM
+** ARM_Thumb
+** ARM_HardFloat
+** ARM_SoftFloat
+** ARM_SoftFP
+* AArch64
+* Alpha
+** Alpha_SoftFloat
+** Alpha_HardFloat
+* X86
+* X86_64
+** D_X32
+* IA64
+* MIPS32
+* MIPS64
+** MIPS_O32
+** MIPS_O64
+** MIPS_N32
+** MIPS_N64
+** MIPS_EABI
+** MIPS_HardFloat
+** MIPS_SoftFloat
+* HPPA
+* HPPA64
+* PPC
+* PPC64
+** PPC_HardFloat
+** PPC_SoftFloat
+* S390
+* S390X
+* SH
+* SH64
+* SPARC
+* SPARC64
+* SPARC_V8Plus
+** SPARC_HardFloat
+** SPARC_SoftFloat
+
+Index: b/src/gcc/config/aarch64/aarch64.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.h
++++ b/src/gcc/config/aarch64/aarch64.h
+@@ -26,6 +26,14 @@
+ #define TARGET_CPU_CPP_BUILTINS()	\
+   aarch64_cpu_cpp_builtins (pfile)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()				\
++  do							\
++    {							\
++      builtin_define ("AArch64");			\
++      builtin_define ("D_HardFloat");			\
++    } while (0)
++
+ 
+ 
+ #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas ()
+Index: b/src/gcc/config/alpha/alpha.h
+===================================================================
+--- a/src/gcc/config/alpha/alpha.h
++++ b/src/gcc/config/alpha/alpha.h
+@@ -72,6 +72,23 @@ along with GCC; see the file COPYING3.
+ 	SUBTARGET_LANGUAGE_CPP_BUILTINS();		\
+ } while (0)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()				\
++  do							\
++    {							\
++	builtin_define ("Alpha");			\
++	if (TARGET_SOFT_FP)				\
++	  {						\
++	    builtin_define ("D_SoftFloat");		\
++	    builtin_define ("Alpha_SoftFloat");		\
++	  }						\
++	else						\
++	  {						\
++	    builtin_define ("D_HardFloat");		\
++	    builtin_define ("Alpha_HardFloat");		\
++	  }						\
++} while (0)
++
+ #ifndef SUBTARGET_LANGUAGE_CPP_BUILTINS
+ #define SUBTARGET_LANGUAGE_CPP_BUILTINS()		\
+   do							\
+Index: b/src/gcc/config/arm/arm.h
+===================================================================
+--- a/src/gcc/config/arm/arm.h
++++ b/src/gcc/config/arm/arm.h
+@@ -47,6 +47,31 @@ extern char arm_arch_name[];
+ /* Target CPU builtins.  */
+ #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()				\
++  do							\
++    {							\
++	builtin_define ("ARM");				\
++							\
++	if (TARGET_THUMB || TARGET_THUMB2)		\
++	  builtin_define ("ARM_Thumb");			\
++							\
++	if (TARGET_HARD_FLOAT_ABI)			\
++	  builtin_define ("ARM_HardFloat");		\
++	else						\
++	  {						\
++	    if(TARGET_SOFT_FLOAT)			\
++	      builtin_define ("ARM_SoftFloat");		\
++	    else if(TARGET_HARD_FLOAT)			\
++	      builtin_define ("ARM_SoftFP");		\
++	  }						\
++							\
++	if(TARGET_SOFT_FLOAT)				\
++	  builtin_define ("D_SoftFloat");		\
++	else if(TARGET_HARD_FLOAT)			\
++	  builtin_define ("D_HardFloat");		\
++    } while (0)
++
+ #include "config/arm/arm-opts.h"
+ 
+ enum target_cpus
+Index: b/src/gcc/config/i386/i386.h
+===================================================================
+--- a/src/gcc/config/i386/i386.h
++++ b/src/gcc/config/i386/i386.h
+@@ -662,6 +662,24 @@ extern const char *host_detect_local_cpu
+ /* Target CPU builtins.  */
+ #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()			\
++  do {						\
++    if (TARGET_64BIT)				\
++    {						\
++      builtin_define("X86_64");			\
++      if (TARGET_X32)				\
++        builtin_define("D_X32");		\
++    }						\
++    else					\
++      builtin_define("X86");			\
++						\
++    if (TARGET_80387)				\
++      builtin_define("D_HardFloat");		\
++    else					\
++      builtin_define("D_SoftFloat");		\
++  } while (0)
++
+ /* Target Pragmas.  */
+ #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
+ 
+Index: b/src/gcc/config/ia64/ia64.h
+===================================================================
+--- a/src/gcc/config/ia64/ia64.h
++++ b/src/gcc/config/ia64/ia64.h
+@@ -40,6 +40,13 @@ do {						\
+ 	  builtin_define("__BIG_ENDIAN__");	\
+ } while (0)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()			\
++do {						\
++	builtin_define ("IA64");		\
++	builtin_define ("D_HardFloat");		\
++} while (0)
++
+ #ifndef SUBTARGET_EXTRA_SPECS
+ #define SUBTARGET_EXTRA_SPECS
+ #endif
+Index: b/src/gcc/config/mips/mips.h
+===================================================================
+--- a/src/gcc/config/mips/mips.h
++++ b/src/gcc/config/mips/mips.h
+@@ -626,6 +626,54 @@ struct mips_cpu_info {
+     }									\
+   while (0)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()						\
++  do									\
++  {									\
++    if (TARGET_64BIT)							\
++      builtin_define("MIPS64");						\
++    else								\
++      builtin_define("MIPS32");						\
++									\
++    switch (mips_abi)							\
++    {									\
++      case ABI_32:							\
++	builtin_define("MIPS_O32");					\
++	break;								\
++									\
++      case ABI_O64:							\
++	builtin_define("MIPS_O64");					\
++	break;								\
++									\
++      case ABI_N32:							\
++	builtin_define("MIPS_N32");					\
++	break;								\
++									\
++      case ABI_64:							\
++	builtin_define("MIPS_N64");					\
++	break;								\
++									\
++      case ABI_EABI:							\
++	builtin_define("MIPS_EABI");					\
++	break;								\
++									\
++      default:								\
++	gcc_unreachable();						\
++    }									\
++									\
++    if (TARGET_HARD_FLOAT_ABI)						\
++    {									\
++      builtin_define("MIPS_HardFloat");					\
++      builtin_define("D_HardFloat");					\
++    }									\
++    else if (TARGET_SOFT_FLOAT_ABI)					\
++    {									\
++      builtin_define("MIPS_SoftFloat");					\
++      builtin_define("D_SoftFloat");					\
++    }									\
++  }									\
++  while (0)
++
+ /* Default target_flags if no switches are specified  */
+ 
+ #ifndef TARGET_DEFAULT
+Index: b/src/gcc/config/pa/pa.h
+===================================================================
+--- a/src/gcc/config/pa/pa.h
++++ b/src/gcc/config/pa/pa.h
+@@ -185,6 +185,20 @@ do {								\
+        builtin_define("_PA_RISC1_0");				\
+ } while (0)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()					\
++do {								\
++     if(TARGET_64BIT)						\
++       builtin_define("HPPA64");				\
++     else							\
++       builtin_define("HPPA");					\
++								\
++     if(TARGET_SOFT_FLOAT)					\
++       builtin_define ("D_SoftFloat");				\
++     else							\
++       builtin_define ("D_HardFloat");				\
++} while (0)
++
+ /* An old set of OS defines for various BSD-like systems.  */
+ #define TARGET_OS_CPP_BUILTINS()				\
+   do								\
+Index: b/src/gcc/config/rs6000/rs6000.h
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.h
++++ b/src/gcc/config/rs6000/rs6000.h
+@@ -804,6 +804,28 @@ extern unsigned char rs6000_recip_bits[]
+ #define TARGET_CPU_CPP_BUILTINS() \
+   rs6000_cpu_cpp_builtins (pfile)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()			\
++  do						\
++    {						\
++      if (TARGET_64BIT)				\
++	builtin_define ("PPC64");		\
++      else					\
++	builtin_define ("PPC");			\
++						\
++      if (TARGET_HARD_FLOAT)			\
++	{					\
++	  builtin_define ("PPC_HardFloat");	\
++	  builtin_define ("D_HardFloat");	\
++	}					\
++      else if (TARGET_SOFT_FLOAT)		\
++	{					\
++	  builtin_define ("PPC_SoftFloat");	\
++	  builtin_define ("D_SoftFloat");	\
++	}					\
++    }						\
++  while (0)
++
+ /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
+    we're compiling for.  Some configurations may need to override it.  */
+ #define RS6000_CPU_CPP_ENDIAN_BUILTINS()	\
+Index: b/src/gcc/config/s390/s390.h
+===================================================================
+--- a/src/gcc/config/s390/s390.h
++++ b/src/gcc/config/s390/s390.h
+@@ -177,6 +177,22 @@ enum processor_flags
+ /* Target CPU builtins.  */
+ #define TARGET_CPU_CPP_BUILTINS() s390_cpu_cpp_builtins (pfile)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()				\
++  do							\
++    {							\
++      if (TARGET_64BIT)					\
++        builtin_define ("S390X");			\
++      else						\
++        builtin_define ("S390");			\
++							\
++      if(TARGET_SOFT_FLOAT)				\
++        builtin_define ("D_SoftFloat");			\
++      else if(TARGET_HARD_FLOAT)			\
++        builtin_define ("D_HardFloat");			\
++    }							\
++  while (0)
++
+ #ifdef DEFAULT_TARGET_64BIT
+ #define TARGET_DEFAULT     (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP	\
+                             | MASK_OPT_HTM | MASK_OPT_VX)
+Index: b/src/gcc/config/sh/sh.h
+===================================================================
+--- a/src/gcc/config/sh/sh.h
++++ b/src/gcc/config/sh/sh.h
+@@ -31,6 +31,22 @@ extern int code_for_indirect_jump_scratc
+ 
+ #define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile)
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()			\
++  do						\
++    {						\
++      if (TARGET_SHMEDIA64)			\
++	builtin_define ("SH64");		\
++      else					\
++	builtin_define ("SH");			\
++						\
++      if (TARGET_FPU_ANY)			\
++	builtin_define ("D_HardFloat");		\
++      else					\
++	builtin_define ("D_SoftFloat");		\
++    }						\
++  while (0)
++
+ /* Value should be nonzero if functions must have frame pointers.
+    Zero means the frame pointer need not be set up (and parms may be accessed
+    via the stack pointer) in functions that seem suitable.  */
+Index: b/src/gcc/config/sparc/sparc.h
+===================================================================
+--- a/src/gcc/config/sparc/sparc.h
++++ b/src/gcc/config/sparc/sparc.h
+@@ -27,6 +27,31 @@ along with GCC; see the file COPYING3.
+ 
+ #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros ()
+ 
++/* Target CPU builtins for D.  */
++#define TARGET_CPU_D_BUILTINS()			\
++do						\
++    {						\
++      if (TARGET_64BIT)				\
++	builtin_define ("SPARC64");		\
++      else					\
++	builtin_define ("SPARC");		\
++						\
++      if(TARGET_V8PLUS)				\
++	builtin_define ("SPARC_V8Plus");	\
++						\
++      if(TARGET_FPU)				\
++	{					\
++	  builtin_define ("D_HardFloat");	\
++	  builtin_define ("SPARC_HardFloat");	\
++	}					\
++      else					\
++	{					\
++	  builtin_define ("D_SoftFloat");	\
++	  builtin_define ("SPARC_SoftFloat");	\
++	}					\
++    }						\
++  while (0)
++
+ /* Specify this in a cover file to provide bi-architecture (32/64) support.  */
+ /* #define SPARC_BI_ARCH */
+ 
--- gcc-6-6.4.0.orig/debian/patches/gdc-versym-os.diff
+++ gcc-6-6.4.0/debian/patches/gdc-versym-os.diff
@@ -0,0 +1,430 @@
+# DP: Implements D OS version conditions.
+
+This implements the following official versions:
+* Windows
+** Win32
+** Win64
+** Cygwin
+** MinGW
+* linux
+* OSX
+* FreeBSD
+* OpenBSD
+* NetBSD
+* Solaris
+* Posix
+* AIX
+* SysV4
+* Hurd
+* Android
+
+These gdc specific versions are also implemented:
+* GNU_MinGW64 (for mingw-w64)
+* GNU_OpenSolaris (for opensolaris)
+* GNU_GLibc (implemented for linux & bsd & opensolaris)
+* GNU_UCLibc (implemented for linux)
+* GNU_Bionic (implemented for linux)
+
+These official OS versions are not implemented:
+* DragonFlyBSD
+* BSD (other BSDs)
+* Haiku
+* SkyOS
+* SysV3
+
+Index: b/src/gcc/config/alpha/linux.h
+===================================================================
+--- a/src/gcc/config/alpha/linux.h
++++ b/src/gcc/config/alpha/linux.h
+@@ -33,6 +33,16 @@ along with GCC; see the file COPYING3.
+ 	  builtin_define ("_GNU_SOURCE");			\
+     } while (0)
+ 
++#undef TARGET_OS_D_BUILTINS 
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++	if (OPTION_GLIBC)					\
++	  builtin_define ("GNU_GLibc");				\
++								\
++	builtin_define ("linux");				\
++	builtin_define ("Posix");				\
++    } while (0)
++
+ #undef LIB_SPEC
+ #define LIB_SPEC \
+   "%{pthread:-lpthread} \
+Index: b/src/gcc/config/arm/linux-eabi.h
+===================================================================
+--- a/src/gcc/config/arm/linux-eabi.h
++++ b/src/gcc/config/arm/linux-eabi.h
+@@ -30,6 +30,15 @@
+     }						\
+   while (false)
+ 
++#undef  TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS() 			\
++  do 						\
++    {						\
++      TARGET_GENERIC_LINUX_OS_D_BUILTINS();	\
++      ANDROID_TARGET_OS_D_BUILTINS();		\
++    }						\
++  while (false)
++
+ /* We default to a soft-float ABI so that binaries can run on all
+    target hardware.  If you override this to use the hard-float ABI then
+    change the setting of GLIBC_DYNAMIC_LINKER_DEFAULT as well.  */
+Index: b/src/gcc/config/darwin.h
+===================================================================
+--- a/src/gcc/config/darwin.h
++++ b/src/gcc/config/darwin.h
+@@ -977,4 +977,10 @@ extern void darwin_driver_init (unsigned
+ #define DEF_LD64 LD64_VERSION
+ #endif
+ 
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++	builtin_define ("OSX");					\
++	builtin_define ("Posix");				\
++    } while (0)
++
+ #endif /* CONFIG_DARWIN_H */
+Index: b/src/gcc/config/freebsd.h
+===================================================================
+--- a/src/gcc/config/freebsd.h
++++ b/src/gcc/config/freebsd.h
+@@ -32,6 +32,13 @@ along with GCC; see the file COPYING3.
+ #undef  TARGET_OS_CPP_BUILTINS
+ #define TARGET_OS_CPP_BUILTINS() FBSD_TARGET_OS_CPP_BUILTINS()
+ 
++#undef TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++	builtin_define ("FreeBSD");				\
++	builtin_define ("Posix");				\
++    } while (0)
++
+ #undef  CPP_SPEC
+ #define CPP_SPEC FBSD_CPP_SPEC
+ 
+Index: b/src/gcc/config/gnu.h
+===================================================================
+--- a/src/gcc/config/gnu.h
++++ b/src/gcc/config/gnu.h
+@@ -31,3 +31,11 @@ along with GCC.  If not, see <http://www
+ 	builtin_assert ("system=unix");		\
+ 	builtin_assert ("system=posix");	\
+     } while (0)
++
++#undef TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++								\
++	builtin_define ("Hurd");				\
++	builtin_define ("Posix");				\
++    } while (0)
+Index: b/src/gcc/config/i386/cygwin.h
+===================================================================
+--- a/src/gcc/config/i386/cygwin.h
++++ b/src/gcc/config/i386/cygwin.h
+@@ -29,6 +29,13 @@ along with GCC; see the file COPYING3.
+     }								\
+   while (0)
+ 
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++      builtin_define ("Windows");				\
++      builtin_define ("Cygwin");				\
++      builtin_define ("Posix");					\
++    } while (0)
++
+ #undef CPP_SPEC
+ #define CPP_SPEC "%(cpp_cpu) %{posix:-D_POSIX_SOURCE} \
+   %{!ansi:-Dunix} \
+Index: b/src/gcc/config/i386/linux-common.h
+===================================================================
+--- a/src/gcc/config/i386/linux-common.h
++++ b/src/gcc/config/i386/linux-common.h
+@@ -27,6 +27,15 @@ along with GCC; see the file COPYING3.
+     }                                          \
+   while (0)
+ 
++#undef  TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS() 			\
++  do 						\
++    {						\
++      TARGET_GENERIC_LINUX_OS_D_BUILTINS();	\
++      ANDROID_TARGET_OS_D_BUILTINS();		\
++    }						\
++  while (0)
++
+ #undef CC1_SPEC
+ #define CC1_SPEC \
+   LINUX_OR_ANDROID_CC (GNU_USER_TARGET_CC1_SPEC, \
+Index: b/src/gcc/config/i386/mingw-w64.h
+===================================================================
+--- a/src/gcc/config/i386/mingw-w64.h
++++ b/src/gcc/config/i386/mingw-w64.h
+@@ -89,3 +89,10 @@ along with GCC; see the file COPYING3.
+   %{static:-Bstatic} %{!static:-Bdynamic} \
+   %{shared|mdll: " SUB_LINK_ENTRY " --enable-auto-image-base} \
+   %(shared_libgcc_undefs)"
++
++#undef TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++      TARGET_GENERIC_MINGW_OS_D_BUILTINS();			\
++      builtin_define ("GNU_MinGW64");				\
++    } while (0)
+Index: b/src/gcc/config/i386/mingw32.h
+===================================================================
+--- a/src/gcc/config/i386/mingw32.h
++++ b/src/gcc/config/i386/mingw32.h
+@@ -53,6 +53,18 @@ along with GCC; see the file COPYING3.
+     }								\
+   while (0)
+ 
++#define TARGET_OS_D_BUILTINS() TARGET_GENERIC_MINGW_OS_D_BUILTINS()
++#define TARGET_GENERIC_MINGW_OS_D_BUILTINS()			\
++    do {							\
++      builtin_define ("Windows");				\
++      builtin_define ("MinGW");					\
++								\
++      if (TARGET_64BIT && ix86_abi == MS_ABI)			\
++	  builtin_define ("Win64");				\
++      else if (!TARGET_64BIT)					\
++        builtin_define ("Win32");				\
++    } while (0)
++
+ #ifndef TARGET_USE_PTHREAD_BY_DEFAULT
+ #define SPEC_PTHREAD1 "pthread"
+ #define SPEC_PTHREAD2 "!no-pthread"
+Index: b/src/gcc/config/kfreebsd-gnu.h
+===================================================================
+--- a/src/gcc/config/kfreebsd-gnu.h
++++ b/src/gcc/config/kfreebsd-gnu.h
+@@ -29,6 +29,14 @@ along with GCC; see the file COPYING3.
+     }						\
+   while (0)
+ 
++#undef TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++	builtin_define ("FreeBSD");				\
++	builtin_define ("Posix");				\
++	builtin_define ("GNU_GLibc");				\
++    } while (0)
++
+ #define GNU_USER_DYNAMIC_LINKER        GLIBC_DYNAMIC_LINKER
+ #define GNU_USER_DYNAMIC_LINKER32      GLIBC_DYNAMIC_LINKER32
+ #define GNU_USER_DYNAMIC_LINKER64      GLIBC_DYNAMIC_LINKER64
+Index: b/src/gcc/config/knetbsd-gnu.h
+===================================================================
+--- a/src/gcc/config/knetbsd-gnu.h
++++ b/src/gcc/config/knetbsd-gnu.h
+@@ -30,6 +30,16 @@ along with GCC; see the file COPYING3.
+     }						\
+   while (0)
+ 
++#undef TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()			\
++  do						\
++    {						\
++      builtin_define ("NetBSD");		\
++      builtin_define ("Posix");			\
++      builtin_define ("GNU_GLibc");		\
++    }						\
++  while (0)
++
+ 
+ #undef GNU_USER_DYNAMIC_LINKER
+ #define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
+Index: b/src/gcc/config/kopensolaris-gnu.h
+===================================================================
+--- a/src/gcc/config/kopensolaris-gnu.h
++++ b/src/gcc/config/kopensolaris-gnu.h
+@@ -30,5 +30,15 @@ along with GCC; see the file COPYING3.
+     }						\
+   while (0)
+ 
++#define TARGET_OS_D_BUILTINS()				\
++  do							\
++    {							\
++	builtin_define ("Solaris");			\
++	builtin_define ("Posix");			\
++	builtin_define ("GNU_OpenSolaris");		\
++	builtin_define ("GNU_GLibc");			\
++    }							\
++  while (0)
++
+ #undef GNU_USER_DYNAMIC_LINKER
+ #define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
+Index: b/src/gcc/config/linux-android.h
+===================================================================
+--- a/src/gcc/config/linux-android.h
++++ b/src/gcc/config/linux-android.h
+@@ -25,6 +25,12 @@
+ 	  builtin_define ("__ANDROID__");			\
+     } while (0)
+ 
++#define ANDROID_TARGET_OS_D_BUILTINS()				\
++    do {							\
++	if (TARGET_ANDROID)					\
++	  builtin_define ("Android");				\
++    } while (0)
++
+ #if ANDROID_DEFAULT
+ # define NOANDROID "mno-android"
+ #else
+Index: b/src/gcc/config/linux.h
+===================================================================
+--- a/src/gcc/config/linux.h
++++ b/src/gcc/config/linux.h
+@@ -53,6 +53,28 @@ see the files COPYING3 and COPYING.RUNTI
+ 	builtin_assert ("system=posix");			\
+     } while (0)
+ 
++#define TARGET_OS_D_BUILTINS() TARGET_GENERIC_LINUX_OS_D_BUILTINS()
++#define TARGET_GENERIC_LINUX_OS_D_BUILTINS()			\
++    do {							\
++	if (OPTION_GLIBC)					\
++	  {							\
++	    builtin_define ("GNU_GLibc");			\
++	    builtin_define ("CRuntime_Glibc");			\
++	  }							\
++	else if (OPTION_UCLIBC)					\
++	  {							\
++	    builtin_define ("GNU_UCLibc");			\
++	  }							\
++	else if (OPTION_BIONIC)					\
++	  {							\
++	    builtin_define ("GNU_Bionic");			\
++	    builtin_define ("CRuntime_Bionic");			\
++	  }							\
++								\
++	builtin_define ("linux");				\
++	builtin_define ("Posix");				\
++    } while (0)
++
+ /* Determine which dynamic linker to use depending on whether GLIBC or
+    uClibc or Bionic or musl is the default C library and whether
+    -muclibc or -mglibc or -mbionic or -mmusl has been passed to change
+Index: b/src/gcc/config/mips/linux-common.h
+===================================================================
+--- a/src/gcc/config/mips/linux-common.h
++++ b/src/gcc/config/mips/linux-common.h
+@@ -27,6 +27,15 @@ along with GCC; see the file COPYING3.
+     ANDROID_TARGET_OS_CPP_BUILTINS();				\
+   } while (0)
+ 
++#undef  TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS() 			\
++  do 						\
++    {						\
++      TARGET_GENERIC_LINUX_OS_D_BUILTINS();	\
++      ANDROID_TARGET_OS_D_BUILTINS();		\
++    }						\
++  while (0)
++
+ #undef  LINK_SPEC
+ #define LINK_SPEC							\
+   LINUX_OR_ANDROID_LD (GNU_USER_TARGET_LINK_SPEC,			\
+Index: b/src/gcc/config/netbsd.h
+===================================================================
+--- a/src/gcc/config/netbsd.h
++++ b/src/gcc/config/netbsd.h
+@@ -29,6 +29,14 @@ along with GCC; see the file COPYING3.
+     }						\
+   while (0)
+ 
++#define TARGET_OS_D_BUILTINS()			\
++  do						\
++    {						\
++      builtin_define ("NetBSD");		\
++      builtin_define ("Posix");			\
++    }						\
++  while (0)
++
+ /* CPP_SPEC parts common to all NetBSD targets.  */
+ #define NETBSD_CPP_SPEC				\
+   "%{posix:-D_POSIX_SOURCE} \
+Index: b/src/gcc/config/openbsd.h
+===================================================================
+--- a/src/gcc/config/openbsd.h
++++ b/src/gcc/config/openbsd.h
+@@ -84,6 +84,14 @@ along with GCC; see the file COPYING3.
+     }						\
+   while (0)
+ 
++#define TARGET_OS_D_BUILTINS()			\
++  do						\
++    {						\
++      builtin_define ("OpenBSD");		\
++      builtin_define ("Posix");			\
++    }						\
++  while (0)
++
+ /* TARGET_OS_CPP_BUILTINS() common to all OpenBSD ELF targets.  */
+ #define OPENBSD_OS_CPP_BUILTINS_ELF()		\
+   do						\
+Index: b/src/gcc/config/rs6000/aix.h
+===================================================================
+--- a/src/gcc/config/rs6000/aix.h
++++ b/src/gcc/config/rs6000/aix.h
+@@ -129,6 +129,13 @@
+     }						\
+   while (0)
+ 
++#define TARGET_OS_D_BUILTINS()					\
++    do {							\
++								\
++	builtin_define ("AIX");					\
++	builtin_define ("Posix");				\
++    } while (0)
++
+ /* Define appropriate architecture macros for preprocessor depending on
+    target switches.  */
+ 
+Index: b/src/gcc/config/rs6000/linux.h
+===================================================================
+--- a/src/gcc/config/rs6000/linux.h
++++ b/src/gcc/config/rs6000/linux.h
+@@ -57,6 +57,17 @@
+     }						\
+   while (0)
+ 
++#undef  TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()			\
++  do						\
++    {						\
++      builtin_define ("linux");			\
++      builtin_define ("Posix");			\
++      if (OPTION_GLIBC)				\
++	builtin_define ("GNU_GLibc");		\
++    }						\
++  while (0)
++
+ #undef	CPP_OS_DEFAULT_SPEC
+ #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)"
+ 
+Index: b/src/gcc/config/rs6000/linux64.h
+===================================================================
+--- a/src/gcc/config/rs6000/linux64.h
++++ b/src/gcc/config/rs6000/linux64.h
+@@ -391,6 +391,17 @@ extern int dot_symbols;
+     }							\
+   while (0)
+ 
++#undef  TARGET_OS_D_BUILTINS
++#define TARGET_OS_D_BUILTINS()				\
++  do							\
++    {							\
++      builtin_define ("linux");				\
++      builtin_define ("Posix");				\
++      if (OPTION_GLIBC)					\
++	builtin_define ("GNU_GLibc");			\
++    }							\
++  while (0)
++
+ #undef  CPP_OS_DEFAULT_SPEC
+ #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux) %(include_extra)"
+ 
--- gcc-6-6.4.0.orig/debian/patches/go-testsuite.diff
+++ gcc-6-6.4.0/debian/patches/go-testsuite.diff
@@ -0,0 +1,21 @@
+# DP: Skip Go testcase on AArch64 which hangs on the buildds.
+
+Index: b/src/gcc/testsuite/go.test/go-test.exp
+===================================================================
+--- a/src/gcc/testsuite/go.test/go-test.exp
++++ b/src/gcc/testsuite/go.test/go-test.exp
+@@ -404,6 +404,14 @@ proc go-gc-tests { } {
+ 	    continue
+ 	}
+ 
++	# Hangs on the buildds
++	if { [istarget "aarch64*-*-*"] } {
++	    if { [string match "*go.test/test/chan/select5.go" $test] } {
++		untested $test
++		continue
++	    }
++	}
++
+ 	if { [file tail $test] == "init1.go" } {
+ 	    # This tests whether GC runs during init, which for gccgo
+ 	    # it currently does not.
--- gcc-6-6.4.0.orig/debian/patches/gotools-configury.diff
+++ gcc-6-6.4.0/debian/patches/gotools-configury.diff
@@ -0,0 +1,19 @@
+# DP: Fix gotools cross build.
+
+	* Makefile.am: Use GOC configured in configure.ac for cross builds.
+	* configure.ac: Fix NATIVE conditional.
+	* Makefile.in, configure: Regenerate.
+
+Index: b/src/gotools/configure.ac
+===================================================================
+--- a/src/gotools/configure.ac
++++ b/src/gotools/configure.ac
+@@ -46,7 +46,7 @@ AC_PROG_INSTALL
+ AC_PROG_CC
+ AC_PROG_GO
+ 
+-AM_CONDITIONAL(NATIVE, test "$cross_compiling" = no)
++AM_CONDITIONAL(NATIVE, test "$host" = "$target")
+ 
+ dnl Test for -lsocket and -lnsl.  Copied from libjava/configure.ac.
+ AC_CACHE_CHECK([for socket libraries], gotools_cv_lib_sockets,
--- gcc-6-6.4.0.orig/debian/patches/hurd-changes.diff
+++ gcc-6-6.4.0/debian/patches/hurd-changes.diff
@@ -0,0 +1,20 @@
+# DP: Traditional GNU systems don't have a /usr directory.  However, Debian
+# DP: systems do, and we support both having a /usr -> . symlink, and having a
+# DP: /usr directory like the other ports.  So this patch should NOT go
+# DP: upstream.
+
+---
+ config.gcc |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/src/gcc/config.gcc	(révision 182461)
++++ b/src/gcc/config.gcc	(copie de travail)
+@@ -583,7 +583,7 @@
+     *-*-linux* | frv-*-*linux* | *-*-kfreebsd*-gnu | *-*-knetbsd*-gnu | *-*-kopensolaris*-gnu)
+       :;;
+     *-*-gnu*)
+-      native_system_header_dir=/include
++      # native_system_header_dir=/include
+       ;;
+   esac
+   # glibc / uclibc / bionic switch.
--- gcc-6-6.4.0.orig/debian/patches/ignore-pie-specs-when-not-enabled.diff
+++ gcc-6-6.4.0/debian/patches/ignore-pie-specs-when-not-enabled.diff
@@ -0,0 +1,56 @@
+# DP: Ignore dpkg's pie specs when pie is not enabled.
+
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -3715,6 +3715,36 @@ handle_foffload_option (const char *arg)
+     }
+ }
+ 
++static bool ignore_pie_specs_when_not_enabled(const char *envvar,
++					      const char *specname)
++{
++  const char *envval = secure_getenv(envvar);
++  char *hardening;
++  bool ignore;
++
++  if (strstr (specname, "/pie-compile.specs") == NULL
++      && strstr (specname, "/pie-link.specs") == NULL)
++    return false;
++  if (envval == NULL || strstr (envval, "hardening=") == NULL)
++    return true;
++  ignore = true;
++  hardening = (char *) xmalloc (strlen(envval) + 1);
++  strcpy (hardening, strstr (envval, "hardening="));
++  if (strchr (hardening, ' '))
++    *strchr (hardening, ' ') = '\0';
++  if (strstr(hardening, "+all"))
++    {
++      if (strstr(hardening, "-pie") == NULL)
++	ignore = false;
++    }
++  else if (strstr(hardening, "+pie"))
++    {
++      ignore = false;
++    }
++  free (hardening);
++  return ignore;
++}
++
+ /* Handle a driver option; arguments and return value as for
+    handle_option.  */
+ 
+@@ -3989,6 +4019,12 @@ driver_handle_option (struct gcc_options
+       break;
+ 
+     case OPT_specs_:
++      if (ignore_pie_specs_when_not_enabled("DEB_BUILD_MAINT_OPTIONS", arg)
++	  && ignore_pie_specs_when_not_enabled("DEB_BUILD_OPTIONS", arg))
++	{
++	  inform (0, "pie specs %s ignored when pie is not enabled", arg);
++	  return true;
++	}
+       {
+ 	struct user_specs *user = XNEW (struct user_specs);
+ 
--- gcc-6-6.4.0.orig/debian/patches/kfreebsd-unwind.diff
+++ gcc-6-6.4.0/debian/patches/kfreebsd-unwind.diff
@@ -0,0 +1,55 @@
+# DP: DWARF2 EH unwinding support for AMD x86-64 and x86 KFreeBSD.
+
+Index: b/src/libgcc/config.host
+===================================================================
+--- a/src/libgcc/config.host
++++ b/src/libgcc/config.host
+@@ -625,7 +625,13 @@ i[34567]86-*-linux*)
+ 	tm_file="${tm_file} i386/elf-lib.h"
+ 	md_unwind_header=i386/linux-unwind.h
+ 	;;
+-i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i[34567]86-*-gnu* | i[34567]86-*-kopensolaris*-gnu)
++i[34567]86-*-kfreebsd*-gnu)
++	extra_parts="$extra_parts crtprec32.o crtprec64.o crtprec80.o crtfastmath.o"
++	tmake_file="${tmake_file} i386/t-crtpc t-crtfm i386/t-crtstuff t-dfprules"
++	tm_file="${tm_file} i386/elf-lib.h"
++	md_unwind_header=i386/freebsd-unwind.h
++	;;
++i[34567]86-*-knetbsd*-gnu | i[34567]86-*-gnu* | i[34567]86-*-kopensolaris*-gnu)
+ 	extra_parts="$extra_parts crtprec32.o crtprec64.o crtprec80.o crtfastmath.o"
+ 	tmake_file="${tmake_file} i386/t-crtpc t-crtfm i386/t-crtstuff t-dfprules"
+ 	tm_file="${tm_file} i386/elf-lib.h"
+@@ -636,7 +642,13 @@ x86_64-*-linux*)
+ 	tm_file="${tm_file} i386/elf-lib.h"
+ 	md_unwind_header=i386/linux-unwind.h
+ 	;;
+-x86_64-*-kfreebsd*-gnu | x86_64-*-knetbsd*-gnu)
++x86_64-*-kfreebsd*-gnu)
++	extra_parts="$extra_parts crtprec32.o crtprec64.o crtprec80.o crtfastmath.o"
++	tmake_file="${tmake_file} i386/t-crtpc t-crtfm i386/t-crtstuff t-dfprules"
++	tm_file="${tm_file} i386/elf-lib.h"
++	md_unwind_header=i386/freebsd-unwind.h
++	;;
++x86_64-*-knetbsd*-gnu)
+ 	extra_parts="$extra_parts crtprec32.o crtprec64.o crtprec80.o crtfastmath.o"
+ 	tmake_file="${tmake_file} i386/t-crtpc t-crtfm i386/t-crtstuff t-dfprules"
+ 	tm_file="${tm_file} i386/elf-lib.h"
+Index: b/src/libgcc/config/i386/freebsd-unwind.h
+===================================================================
+--- a/src/libgcc/config/i386/freebsd-unwind.h
++++ b/src/libgcc/config/i386/freebsd-unwind.h
+@@ -26,6 +26,8 @@ see the files COPYING3 and COPYING.RUNTI
+ /* Do code reading to identify a signal frame, and set the frame
+    state data appropriately.  See unwind-dw2.c for the structs. */
+ 
++#ifndef inhibit_libc
++
+ #include <sys/types.h>
+ #include <signal.h>
+ #include <sys/ucontext.h>
+@@ -171,3 +173,5 @@ x86_freebsd_fallback_frame_state
+   return _URC_NO_REASON;
+ }
+ #endif /* ifdef __x86_64__  */
++
++#endif /* ifndef inhibit_libc */
--- gcc-6-6.4.0.orig/debian/patches/libasan-sparc.diff
+++ gcc-6-6.4.0/debian/patches/libasan-sparc.diff
@@ -0,0 +1,163 @@
+# DP: Re-apply sanitizer patch for sparc, dropped upstream
+
+# don't remove, this is regularly overwritten, see PR sanitizer/63958.
+
+libsanitizer/
+
+2014-10-14  David S. Miller  <davem@davemloft.net>
+
+	* sanitizer_common/sanitizer_platform_limits_linux.cc (time_t):
+	Define at __kernel_time_t, as needed for sparc.
+	(struct __old_kernel_stat): Don't check if __sparc__ is defined.
+	* libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
+	(__sanitizer): Define struct___old_kernel_stat_sz,
+	struct_kernel_stat_sz, and struct_kernel_stat64_sz for sparc.
+	(__sanitizer_ipc_perm): Adjust for sparc targets.
+	(__sanitizer_shmid_ds): Likewsie.
+	(__sanitizer_sigaction): Likewsie.
+	(IOC_SIZE): Likewsie.
+
+Index: libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
+===================================================================
+--- a/src/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h	(revision 216223)
++++ a/src/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h	(revision 216224)
+@@ -72,6 +72,14 @@
+   const unsigned struct_kernel_stat_sz = 144;
+   #endif
+   const unsigned struct_kernel_stat64_sz = 104;
++#elif defined(__sparc__) && defined(__arch64__)
++  const unsigned struct___old_kernel_stat_sz = 0;
++  const unsigned struct_kernel_stat_sz = 104;
++  const unsigned struct_kernel_stat64_sz = 144;
++#elif defined(__sparc__) && !defined(__arch64__)
++  const unsigned struct___old_kernel_stat_sz = 0;
++  const unsigned struct_kernel_stat_sz = 64;
++  const unsigned struct_kernel_stat64_sz = 104;
+ #endif
+   struct __sanitizer_perf_event_attr {
+     unsigned type;
+@@ -94,7 +102,7 @@
+ 
+ #if defined(__powerpc64__)
+   const unsigned struct___old_kernel_stat_sz = 0;
+-#else
++#elif !defined(__sparc__)
+   const unsigned struct___old_kernel_stat_sz = 32;
+ #endif
+ 
+@@ -173,6 +181,18 @@
+     unsigned short __pad1;
+     unsigned long __unused1;
+     unsigned long __unused2;
++#elif defined(__sparc__)
++# if defined(__arch64__)
++    unsigned mode;
++    unsigned short __pad1;
++# else
++    unsigned short __pad1;
++    unsigned short mode;
++    unsigned short __pad2;
++# endif
++    unsigned short __seq;
++    unsigned long long __unused1;
++    unsigned long long __unused2;
+ #else
+     unsigned short mode;
+     unsigned short __pad1;
+@@ -190,6 +210,26 @@
+ 
+   struct __sanitizer_shmid_ds {
+     __sanitizer_ipc_perm shm_perm;
++  #if defined(__sparc__)
++  # if !defined(__arch64__)
++    u32 __pad1;
++  # endif
++    long shm_atime;
++  # if !defined(__arch64__)
++    u32 __pad2;
++  # endif
++    long shm_dtime;
++  # if !defined(__arch64__)
++    u32 __pad3;
++  # endif
++    long shm_ctime;
++    uptr shm_segsz;
++    int shm_cpid;
++    int shm_lpid;
++    unsigned long shm_nattch;
++    unsigned long __glibc_reserved1;
++    unsigned long __glibc_reserved2;
++  #else    
+   #ifndef __powerpc__
+     uptr shm_segsz;
+   #elif !defined(__powerpc64__)
+@@ -227,6 +267,7 @@
+     uptr __unused4;
+     uptr __unused5;
+   #endif
++#endif
+   };
+ #elif SANITIZER_FREEBSD
+   struct __sanitizer_ipc_perm {
+@@ -523,9 +564,13 @@
+ #else
+     __sanitizer_sigset_t sa_mask;
+ #ifndef __mips__
++#if defined(__sparc__)
++    unsigned long sa_flags;
++#else
+     int sa_flags;
+ #endif
+ #endif
++#endif
+ #if SANITIZER_LINUX
+     void (*sa_restorer)();
+ #endif
+@@ -745,7 +790,7 @@
+ 
+ #define IOC_NRBITS 8
+ #define IOC_TYPEBITS 8
+-#if defined(__powerpc__) || defined(__powerpc64__) || defined(__mips__)
++#if defined(__powerpc__) || defined(__powerpc64__) || defined(__mips__) || defined(__sparc__)
+ #define IOC_SIZEBITS 13
+ #define IOC_DIRBITS 3
+ #define IOC_NONE 1U
+@@ -775,7 +820,17 @@
+ #define IOC_DIR(nr) (((nr) >> IOC_DIRSHIFT) & IOC_DIRMASK)
+ #define IOC_TYPE(nr) (((nr) >> IOC_TYPESHIFT) & IOC_TYPEMASK)
+ #define IOC_NR(nr) (((nr) >> IOC_NRSHIFT) & IOC_NRMASK)
++
++#if defined(__sparc__)
++// In sparc the 14 bits SIZE field overlaps with the
++// least significant bit of DIR, so either IOC_READ or
++// IOC_WRITE shall be 1 in order to get a non-zero SIZE.
++# define IOC_SIZE(nr)                       \
++  ((((((nr) >> 29) & 0x7) & (4U|2U)) == 0)? \
++   0 : (((nr) >> 16) & 0x3fff))
++#else
+ #define IOC_SIZE(nr) (((nr) >> IOC_SIZESHIFT) & IOC_SIZEMASK)
++#endif
+ 
+   extern unsigned struct_arpreq_sz;
+   extern unsigned struct_ifreq_sz;
+Index: libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
+===================================================================
+--- a/src/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc	(revision 216223)
++++ a/src/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc	(revision 216224)
+@@ -36,6 +36,7 @@
+ #define uid_t __kernel_uid_t
+ #define gid_t __kernel_gid_t
+ #define off_t __kernel_off_t
++#define time_t __kernel_time_t
+ // This header seems to contain the definitions of _kernel_ stat* structs.
+ #include <asm/stat.h>
+ #undef ino_t
+@@ -60,7 +61,7 @@
+ }  // namespace __sanitizer
+ 
+ #if !defined(__powerpc64__) && !defined(__x86_64__) && !defined(__aarch64__)\
+-                            && !defined(__mips__)
++                            && !defined(__mips__) && !defined(__sparc__)
+ COMPILER_CHECK(struct___old_kernel_stat_sz == sizeof(struct __old_kernel_stat));
+ #endif
+ 
--- gcc-6-6.4.0.orig/debian/patches/libcc1-compiler-name.diff
+++ gcc-6-6.4.0/debian/patches/libcc1-compiler-name.diff
@@ -0,0 +1,24 @@
+# DP: Don't add the configured prefix to libcc1's compiler name.
+
+--- a/src/libcc1/Makefile.am
++++ b/src/libcc1/Makefile.am
+@@ -49,7 +49,7 @@
+ # Put this in a header so we don't run sed for each compilation.  This
+ # is also simpler to debug as one can easily see the constant.
+ compiler-name.h: Makefile
+-	echo "#define COMPILER_NAME \"`echo gcc | sed '$(transform)'`\"" > $@
++	echo "#define COMPILER_NAME \"`echo gcc-6`\"" > $@
+ 
+ 
+ shared_source = callbacks.cc callbacks.hh connection.cc connection.hh \
+--- a/src/libcc1/Makefile.in
++++ b/src/libcc1/Makefile.in
+@@ -674,7 +674,7 @@
+ # Put this in a header so we don't run sed for each compilation.  This
+ # is also simpler to debug as one can easily see the constant.
+ compiler-name.h: Makefile
+-	echo "#define COMPILER_NAME \"`echo gcc | sed '$(transform)'`\"" > $@
++	echo "#define COMPILER_NAME \"`echo gcc-6`\"" > $@
+ 
+ # Tell versions [3.59,3.63) of GNU make to not export all variables.
+ # Otherwise a system limit (for SysV at least) may be exceeded.
--- gcc-6-6.4.0.orig/debian/patches/libcilkrts-targets.diff
+++ gcc-6-6.4.0/debian/patches/libcilkrts-targets.diff
@@ -0,0 +1,21 @@
+# DP: Disable libcilkrts on KFreeBSD and the Hurd. See #734973.
+
+Index: b/src/libcilkrts/configure.tgt
+===================================================================
+--- a/src/libcilkrts/configure.tgt
++++ b/src/libcilkrts/configure.tgt
+@@ -44,3 +44,14 @@ esac
+ 
+ # Disable libcilkrts on non POSIX hosted systems.
+ . ${srcdir}/../config/target-posix
++
++# Disable libcilkrts on KFreeBSD and the Hurd.
++if test x$enable_libcilkrts = x ; then
++    case "${target}" in
++    *-*-linux*)
++        ;;
++    *-*-gnu* | *-*-k*bsd*-gnu)
++        UNSUPPORTED=1
++        ;;
++    esac
++fi
--- gcc-6-6.4.0.orig/debian/patches/libffi-mips.diff
+++ gcc-6-6.4.0/debian/patches/libffi-mips.diff
@@ -0,0 +1,703 @@
+# DP: Backport Mips go closure support, taken from libffi issue #197.
+
+--- a/src/libffi/src/mips/ffi.c
++++ b/src/libffi/src/mips/ffi.c
+@@ -581,14 +581,15 @@ ffi_status ffi_prep_cif_machdep(ffi_cif *cif)
+ /* Low level routine for calling O32 functions */
+ extern int ffi_call_O32(void (*)(char *, extended_cif *, int, int), 
+ 			extended_cif *, unsigned, 
+-			unsigned, unsigned *, void (*)(void));
++			unsigned, unsigned *, void (*)(void), void *closure);
+ 
+ /* Low level routine for calling N32 functions */
+ extern int ffi_call_N32(void (*)(char *, extended_cif *, int, int), 
+ 			extended_cif *, unsigned, 
+-			unsigned, void *, void (*)(void));
++			unsigned, void *, void (*)(void), void *closure);
+ 
+-void ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue)
++void ffi_call_int(ffi_cif *cif, void (*fn)(void), void *rvalue, 
++	      void **avalue, void *closure)
+ {
+   extended_cif ecif;
+ 
+@@ -610,7 +611,7 @@ void ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue)
+     case FFI_O32:
+     case FFI_O32_SOFT_FLOAT:
+       ffi_call_O32(ffi_prep_args, &ecif, cif->bytes, 
+-		   cif->flags, ecif.rvalue, fn);
++		   cif->flags, ecif.rvalue, fn, closure);
+       break;
+ #endif
+ 
+@@ -642,7 +643,7 @@ void ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue)
+ #endif
+ 	  }
+         ffi_call_N32(ffi_prep_args, &ecif, cif->bytes,
+-                     cif->flags, rvalue_copy, fn);
++                     cif->flags, rvalue_copy, fn, closure);
+         if (copy_rvalue)
+           memcpy(ecif.rvalue, rvalue_copy + copy_offset, cif->rtype->size);
+       }
+@@ -655,11 +656,27 @@ void ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue)
+     }
+ }
+ 
++void
++ffi_call(ffi_cif *cif, void (*fn)(void), void *rvalue, void **avalue)
++{
++  ffi_call_int (cif, fn, rvalue, avalue, NULL);
++}
++
++void
++ffi_call_go (ffi_cif *cif, void (*fn)(void), void *rvalue,
++	     void **avalue, void *closure)
++{
++  ffi_call_int (cif, fn, rvalue, avalue, closure);
++}
++
++
+ #if FFI_CLOSURES
+ #if defined(FFI_MIPS_O32)
+ extern void ffi_closure_O32(void);
++extern void ffi_go_closure_O32(void);
+ #else
+ extern void ffi_closure_N32(void);
++extern void ffi_go_closure_N32(void);
+ #endif /* FFI_MIPS_O32 */
+ 
+ ffi_status
+@@ -762,17 +779,17 @@ ffi_prep_closure_loc (ffi_closure *closure,
+  * Based on the similar routine for sparc.
+  */
+ int
+-ffi_closure_mips_inner_O32 (ffi_closure *closure,
++ffi_closure_mips_inner_O32 (ffi_cif *cif,
++                            void (*fun)(ffi_cif*, void*, void**, void*),
++			    void *user_data,
+ 			    void *rvalue, ffi_arg *ar,
+ 			    double *fpr)
+ {
+-  ffi_cif *cif;
+   void **avaluep;
+   ffi_arg *avalue;
+   ffi_type **arg_types;
+   int i, avn, argn, seen_int;
+ 
+-  cif = closure->cif;
+   avalue = alloca (cif->nargs * sizeof (ffi_arg));
+   avaluep = alloca (cif->nargs * sizeof (ffi_arg));
+ 
+@@ -840,7 +857,7 @@ ffi_closure_mips_inner_O32 (ffi_closure *closure,
+     }
+ 
+   /* Invoke the closure. */
+-  (closure->fun) (cif, rvalue, avaluep, closure->user_data);
++  fun(cif, rvalue, avaluep, user_data);
+ 
+   if (cif->abi == FFI_O32_SOFT_FLOAT)
+     {
+@@ -916,11 +933,12 @@ copy_struct_N32(char *target, unsigned offset, ffi_abi abi, ffi_type *type,
+  *
+  */
+ int
+-ffi_closure_mips_inner_N32 (ffi_closure *closure,
++ffi_closure_mips_inner_N32 (ffi_cif *cif, 
++			    void (*fun)(ffi_cif*, void*, void**, void*),
++                            void *user_data,
+ 			    void *rvalue, ffi_arg *ar,
+ 			    ffi_arg *fpr)
+ {
+-  ffi_cif *cif;
+   void **avaluep;
+   ffi_arg *avalue;
+   ffi_type **arg_types;
+@@ -928,7 +946,6 @@ ffi_closure_mips_inner_N32 (ffi_closure *closure,
+   int soft_float;
+   ffi_arg *argp;
+ 
+-  cif = closure->cif;
+   soft_float = cif->abi == FFI_N64_SOFT_FLOAT
+     || cif->abi == FFI_N32_SOFT_FLOAT;
+   avalue = alloca (cif->nargs * sizeof (ffi_arg));
+@@ -1040,11 +1057,49 @@ ffi_closure_mips_inner_N32 (ffi_closure *closure,
+     }
+ 
+   /* Invoke the closure. */
+-  (closure->fun) (cif, rvalue, avaluep, closure->user_data);
++  fun (cif, rvalue, avaluep, user_data);
+ 
+   return cif->flags >> (FFI_FLAG_BITS * 8);
+ }
+ 
+ #endif /* FFI_MIPS_N32 */
+ 
++#if defined(FFI_MIPS_O32)
++extern void ffi_closure_O32(void);
++extern void ffi_go_closure_O32(void);
++#else
++extern void ffi_closure_N32(void);
++extern void ffi_go_closure_N32(void);
++#endif /* FFI_MIPS_O32 */
++
++ffi_status
++ffi_prep_go_closure (ffi_go_closure* closure, ffi_cif* cif,
++		     void (*fun)(ffi_cif*,void*,void**,void*))
++{
++  void * fn;
++
++#if defined(FFI_MIPS_O32)
++  if (cif->abi != FFI_O32 && cif->abi != FFI_O32_SOFT_FLOAT)
++    return FFI_BAD_ABI;
++  fn = ffi_go_closure_O32;
++#else
++#if _MIPS_SIM ==_ABIN32
++  if (cif->abi != FFI_N32
++      && cif->abi != FFI_N32_SOFT_FLOAT)
++    return FFI_BAD_ABI;
++#else
++  if (cif->abi != FFI_N64
++      && cif->abi != FFI_N64_SOFT_FLOAT)
++    return FFI_BAD_ABI;
++#endif
++  fn = ffi_go_closure_N32;
++#endif /* FFI_MIPS_O32 */
++
++  closure->tramp = (void *)fn;
++  closure->cif = cif;
++  closure->fun = fun;
++
++  return FFI_OK;
++}
++
+ #endif /* FFI_CLOSURES */
+--- a/src/libffi/src/mips/ffitarget.h
++++ b/src/libffi/src/mips/ffitarget.h
+@@ -231,12 +231,14 @@ typedef enum ffi_abi {
+ 
+ #if defined(FFI_MIPS_O32)
+ #define FFI_CLOSURES 1
++#define FFI_GO_CLOSURES 1
+ #define FFI_TRAMPOLINE_SIZE 20
+ #else
+ /* N32/N64. */
+ # define FFI_CLOSURES 1
++#define FFI_GO_CLOSURES 1
+ #if _MIPS_SIM==_ABI64
+-#define FFI_TRAMPOLINE_SIZE 52
++#define FFI_TRAMPOLINE_SIZE 56
+ #else
+ #define FFI_TRAMPOLINE_SIZE 20
+ #endif
+--- a/src/libffi/src/mips/n32.S
++++ b/src/libffi/src/mips/n32.S
+@@ -37,8 +37,12 @@
+ #define flags	 a3
+ #define raddr    a4
+ #define fn       a5
++#define closure  a6
+ 
+-#define SIZEOF_FRAME	( 8 * FFI_SIZEOF_ARG )
++/* Note: to keep stack 16 byte aligned we need even number slots 
++   used 9 slots here
++*/
++#define SIZEOF_FRAME	( 10 * FFI_SIZEOF_ARG )
+ 
+ #ifdef __GNUC__
+ 	.abicalls
+@@ -49,24 +53,25 @@
+ 	.globl	ffi_call_N32
+ 	.ent	ffi_call_N32
+ ffi_call_N32:	
+-.LFB3:
++.LFB0:
+ 	.frame	$fp, SIZEOF_FRAME, ra
+ 	.mask	0xc0000000,-FFI_SIZEOF_ARG
+ 	.fmask	0x00000000,0
+ 
+ 	# Prologue
+ 	SUBU	$sp, SIZEOF_FRAME			# Frame size
+-.LCFI0:
++.LCFI00:
+ 	REG_S	$fp, SIZEOF_FRAME - 2*FFI_SIZEOF_ARG($sp)	# Save frame pointer
+ 	REG_S	ra, SIZEOF_FRAME - 1*FFI_SIZEOF_ARG($sp)	# Save return address
+-.LCFI1:
++.LCFI01:
+ 	move	$fp, $sp
+-.LCFI3:
++.LCFI02:
+ 	move	t9, callback	# callback function pointer
+ 	REG_S	bytes, 2*FFI_SIZEOF_ARG($fp) # bytes
+ 	REG_S	flags, 3*FFI_SIZEOF_ARG($fp) # flags
+ 	REG_S	raddr, 4*FFI_SIZEOF_ARG($fp) # raddr
+ 	REG_S	fn,    5*FFI_SIZEOF_ARG($fp) # fn
++	REG_S	closure, 6*FFI_SIZEOF_ARG($fp) # closure
+ 
+ 	# Allocate at least 4 words in the argstack
+ 	move	v0, bytes
+@@ -198,6 +203,9 @@ callit:
+ 	# Load the function pointer
+ 	REG_L	t9, 5*FFI_SIZEOF_ARG($fp)
+ 
++	# install the static chain(t7=$15)
++	REG_L	t7, 6*FFI_SIZEOF_ARG($fp)
++
+ 	# If the return value pointer is NULL, assume no return value.
+ 	REG_L	t5, 4*FFI_SIZEOF_ARG($fp)
+ 	beqz	t5, noretval
+@@ -346,7 +354,7 @@ epilogue:
+ 	ADDU	$sp, SIZEOF_FRAME		      # Fix stack pointer
+ 	j	ra
+ 
+-.LFE3:
++.LFE0:
+ 	.end	ffi_call_N32
+ 
+ /* ffi_closure_N32. Expects address of the passed-in ffi_closure in t0
+@@ -406,6 +414,41 @@ epilogue:
+ #define GP_OFF2		(0  * FFI_SIZEOF_ARG)
+ 
+ 	.align	2
++	.globl	ffi_go_closure_N32
++	.ent	ffi_go_closure_N32
++ffi_go_closure_N32:
++.LFB1:
++	.frame	$sp, SIZEOF_FRAME2, ra
++	.mask	0x90000000,-(SIZEOF_FRAME2 - RA_OFF2)
++	.fmask	0x00000000,0
++	SUBU	$sp, SIZEOF_FRAME2
++.LCFI10:
++	.cpsetup t9, GP_OFF2, ffi_go_closure_N32
++	REG_S	ra, RA_OFF2($sp)	# Save return address
++.LCFI11:
++
++	REG_S	a0, A0_OFF2($sp)
++	REG_S	a1, A1_OFF2($sp)
++	REG_S	a2, A2_OFF2($sp)
++	REG_S	a3, A3_OFF2($sp)
++	REG_S	a4, A4_OFF2($sp)
++	REG_S	a5, A5_OFF2($sp)
++
++	# Call ffi_closure_mips_inner_N32 to do the real work.
++	LA	t9, ffi_closure_mips_inner_N32
++	REG_L	a0, 8($15)   # cif
++	REG_L	a1, 16($15) # fun
++	move	a2, t7                     # userdata=closure
++	ADDU	a3, $sp, V0_OFF2           # rvalue
++	ADDU	a4, $sp, A0_OFF2           # ar
++	ADDU	a5, $sp, F12_OFF2          # fpr
++
++	b	$do_closure
++
++.LFE1:	
++	.end	ffi_go_closure_N32
++
++	.align	2
+ 	.globl	ffi_closure_N32
+ 	.ent	ffi_closure_N32
+ ffi_closure_N32:
+@@ -414,18 +457,29 @@ ffi_closure_N32:
+ 	.mask	0x90000000,-(SIZEOF_FRAME2 - RA_OFF2)
+ 	.fmask	0x00000000,0
+ 	SUBU	$sp, SIZEOF_FRAME2
+-.LCFI5:
++.LCFI20:
+ 	.cpsetup t9, GP_OFF2, ffi_closure_N32
+ 	REG_S	ra, RA_OFF2($sp)	# Save return address
+-.LCFI6:
+-	# Store all possible argument registers. If there are more than
+-	# fit in registers, then they were stored on the stack.
++.LCFI21:
+ 	REG_S	a0, A0_OFF2($sp)
+ 	REG_S	a1, A1_OFF2($sp)
+ 	REG_S	a2, A2_OFF2($sp)
+ 	REG_S	a3, A3_OFF2($sp)
+ 	REG_S	a4, A4_OFF2($sp)
+ 	REG_S	a5, A5_OFF2($sp)
++
++	# Call ffi_closure_mips_inner_N32 to do the real work.
++	LA	t9, ffi_closure_mips_inner_N32
++	REG_L	a0, 56($12)   # cif
++	REG_L	a1, 64($12)   # fun
++	REG_L	a2, 72($12) # user_data
++	ADDU	a3, $sp, V0_OFF2
++	ADDU	a4, $sp, A0_OFF2
++	ADDU	a5, $sp, F12_OFF2
++
++$do_closure:
++	# Store all possible argument registers. If there are more than
++	# fit in registers, then they were stored on the stack.
+ 	REG_S	a6, A6_OFF2($sp)
+ 	REG_S	a7, A7_OFF2($sp)
+ 
+@@ -439,12 +493,6 @@ ffi_closure_N32:
+ 	s.d	$f18, F18_OFF2($sp)
+ 	s.d	$f19, F19_OFF2($sp)
+ 
+-	# Call ffi_closure_mips_inner_N32 to do the real work.
+-	LA	t9, ffi_closure_mips_inner_N32
+-	move	a0, $12	 # Pointer to the ffi_closure
+-	ADDU	a1, $sp, V0_OFF2
+-	ADDU	a2, $sp, A0_OFF2
+-	ADDU	a3, $sp, F12_OFF2
+ 	jalr	t9
+ 
+ 	# Return flags are in v0
+@@ -531,46 +579,66 @@ cls_epilogue:
+         .align  EH_FRAME_ALIGN
+ .LECIE1:
+ 
+-.LSFDE1:
+-        .4byte  .LEFDE1-.LASFDE1	# length.
+-.LASFDE1:
+-        .4byte  .LASFDE1-.Lframe1	# CIE_pointer.
+-        FDE_ADDR_BYTES  .LFB3		# initial_location.
+-        FDE_ADDR_BYTES  .LFE3-.LFB3	# address_range.
++.LSFDE0:
++        .4byte  .LEFDE0-.LASFDE0	# length.
++.LASFDE0:
++        .4byte  .LASFDE0-.Lframe1	# CIE_pointer.
++        FDE_ADDR_BYTES  .LFB0		# initial_location.
++        FDE_ADDR_BYTES  .LFE0-.LFB0	# address_range.
+         .byte   0x4			# DW_CFA_advance_loc4
+-        .4byte  .LCFI0-.LFB3		# to .LCFI0
++        .4byte  .LCFI00-.LFB0		# to .LCFI00
+         .byte   0xe			# DW_CFA_def_cfa_offset
+         .uleb128 SIZEOF_FRAME		# adjust stack.by SIZEOF_FRAME
+         .byte   0x4			# DW_CFA_advance_loc4
+-        .4byte  .LCFI1-.LCFI0		# to .LCFI1
++        .4byte  .LCFI01-.LCFI00		# to .LCFI01
+         .byte   0x9e			# DW_CFA_offset of $fp
+         .uleb128 2*FFI_SIZEOF_ARG/4	# 
+         .byte   0x9f			# DW_CFA_offset of ra
+         .uleb128 1*FFI_SIZEOF_ARG/4	# 
+         .byte   0x4			# DW_CFA_advance_loc4
+-        .4byte  .LCFI3-.LCFI1		# to .LCFI3
++        .4byte  .LCFI02-.LCFI01		# to .LCFI02
+         .byte   0xd			# DW_CFA_def_cfa_register
+         .uleb128 0x1e			# in $fp
+         .align  EH_FRAME_ALIGN
++.LEFDE0:
++
++.LSFDE1:
++	.4byte	.LEFDE1-.LASFDE1	# length
++.LASFDE1:
++	.4byte	.LASFDE1-.Lframe1	# CIE_pointer.
++	FDE_ADDR_BYTES	.LFB1		# initial_location.
++	FDE_ADDR_BYTES	.LFE1-.LFB1	# address_range.
++	.byte	0x4			# DW_CFA_advance_loc4
++	.4byte	.LCFI10-.LFB1		# to .LCFI10
++	.byte	0xe			# DW_CFA_def_cfa_offset
++	.uleb128 SIZEOF_FRAME2		# adjust stack.by SIZEOF_FRAME
++	.byte	0x4			# DW_CFA_advance_loc4
++	.4byte	.LCFI11-.LCFI10		# to .LCFI11
++	.byte	0x9c			# DW_CFA_offset of $gp ($28)
++	.uleb128 (SIZEOF_FRAME2 - GP_OFF2)/4
++	.byte	0x9f			# DW_CFA_offset of ra ($31)
++	.uleb128 (SIZEOF_FRAME2 - RA_OFF2)/4
++	.align	EH_FRAME_ALIGN
+ .LEFDE1:
+-.LSFDE3:
+-	.4byte	.LEFDE3-.LASFDE3	# length
+-.LASFDE3:
+-	.4byte	.LASFDE3-.Lframe1	# CIE_pointer.
++
++.LSFDE2:
++	.4byte	.LEFDE2-.LASFDE2	# length
++.LASFDE2:
++	.4byte	.LASFDE2-.Lframe1	# CIE_pointer.
+ 	FDE_ADDR_BYTES	.LFB2		# initial_location.
+ 	FDE_ADDR_BYTES	.LFE2-.LFB2	# address_range.
+ 	.byte	0x4			# DW_CFA_advance_loc4
+-	.4byte	.LCFI5-.LFB2		# to .LCFI5
++	.4byte	.LCFI20-.LFB2		# to .LCFI20
+ 	.byte	0xe			# DW_CFA_def_cfa_offset
+ 	.uleb128 SIZEOF_FRAME2		# adjust stack.by SIZEOF_FRAME
+ 	.byte	0x4			# DW_CFA_advance_loc4
+-	.4byte	.LCFI6-.LCFI5		# to .LCFI6
++	.4byte	.LCFI21-.LCFI20		# to .LCFI21
+ 	.byte	0x9c			# DW_CFA_offset of $gp ($28)
+ 	.uleb128 (SIZEOF_FRAME2 - GP_OFF2)/4
+ 	.byte	0x9f			# DW_CFA_offset of ra ($31)
+ 	.uleb128 (SIZEOF_FRAME2 - RA_OFF2)/4
+ 	.align	EH_FRAME_ALIGN
+-.LEFDE3:
++.LEFDE2:
+ #endif /* __GNUC__ */	
+ 	
+ #endif
+--- a/src/libffi/src/mips/o32.S
++++ b/src/libffi/src/mips/o32.S
+@@ -50,14 +50,14 @@ ffi_call_O32:
+ $LFB0:
+ 	# Prologue
+ 	SUBU	$sp, SIZEOF_FRAME	# Frame size
+-$LCFI0:
++$LCFI00:
+ 	REG_S	$fp, FP_OFF($sp)	# Save frame pointer
+-$LCFI1:
++$LCFI01:
+ 	REG_S	ra, RA_OFF($sp)		# Save return address
+-$LCFI2:
++$LCFI02:
+ 	move	$fp, $sp
+ 
+-$LCFI3:
++$LCFI03:
+ 	move	t9, callback		# callback function pointer
+ 	REG_S	flags, A3_OFF($fp)	# flags
+ 
+@@ -132,6 +132,9 @@ pass_f_d:
+ 	l.d	$f14, 2*FFI_SIZEOF_ARG($sp)	# passing double and float
+ 
+ call_it:	
++	# Load the static chain pointer
++	REG_L	t7, SIZEOF_FRAME + 6*FFI_SIZEOF_ARG($fp)
++
+ 	# Load the function pointer
+ 	REG_L	t9, SIZEOF_FRAME + 5*FFI_SIZEOF_ARG($fp)
+ 
+@@ -204,13 +207,15 @@ $LFE0:
+ 	-8 - f14 (le low, be high)
+ 	-9 - f12 (le high, be low)
+        -10 - f12 (le low, be high)
+-       -11 - Called function a3 save
+-       -12 - Called function a2 save
+-       -13 - Called function a1 save
+-       -14 - Called function a0 save, our sp and fp point here
++       -11 - Called function a5 save
++       -12 - Called function a4 save
++       -13 - Called function a3 save
++       -14 - Called function a2 save
++       -15 - Called function a1 save
++       -16 - Called function a0 save, our sp and fp point here
+ 	 */
+ 	
+-#define SIZEOF_FRAME2	(14 * FFI_SIZEOF_ARG)
++#define SIZEOF_FRAME2	(16 * FFI_SIZEOF_ARG)
+ #define A3_OFF2		(SIZEOF_FRAME2 + 3 * FFI_SIZEOF_ARG)
+ #define A2_OFF2		(SIZEOF_FRAME2 + 2 * FFI_SIZEOF_ARG)
+ #define A1_OFF2		(SIZEOF_FRAME2 + 1 * FFI_SIZEOF_ARG)
+@@ -225,13 +230,71 @@ $LFE0:
+ #define FA_1_0_OFF2	(SIZEOF_FRAME2 - 8 * FFI_SIZEOF_ARG)
+ #define FA_0_1_OFF2	(SIZEOF_FRAME2 - 9 * FFI_SIZEOF_ARG)
+ #define FA_0_0_OFF2	(SIZEOF_FRAME2 - 10 * FFI_SIZEOF_ARG)
++#define CALLED_A5_OFF2  (SIZEOF_FRAME2 - 11 * FFI_SIZEOF_ARG)
++#define CALLED_A4_OFF2  (SIZEOF_FRAME2 - 12 * FFI_SIZEOF_ARG)
+ 
+ 	.text
++
++	.align	2
++	.globl	ffi_go_closure_O32
++	.ent	ffi_go_closure_O32
++ffi_go_closure_O32:
++$LFB1:
++	# Prologue
++	.frame	$fp, SIZEOF_FRAME2, ra
++	.set	noreorder
++	.cpload	t9
++	.set	reorder
++	SUBU	$sp, SIZEOF_FRAME2
++	.cprestore GP_OFF2
++$LCFI10:
++
++	REG_S	$16, S0_OFF2($sp)	 # Save s0
++	REG_S	$fp, FP_OFF2($sp)	 # Save frame pointer
++	REG_S	ra, RA_OFF2($sp)	 # Save return address
++$LCFI11:
++
++	move	$fp, $sp
++$LCFI12:
++
++	REG_S	a0, A0_OFF2($fp)
++	REG_S	a1, A1_OFF2($fp)
++	REG_S	a2, A2_OFF2($fp)
++	REG_S	a3, A3_OFF2($fp)
++
++	# Load ABI enum to s0
++	REG_L	$16, 4($15)	# cif 
++	REG_L	$16, 0($16)	# abi is first member.
++
++	li	$13, 1		# FFI_O32
++	bne	$16, $13, 1f	# Skip fp save if FFI_O32_SOFT_FLOAT
++	
++	# Store all possible float/double registers.
++	s.d	$f12, FA_0_0_OFF2($fp)
++	s.d	$f14, FA_1_0_OFF2($fp)
++1:
++	# prepare arguments for ffi_closure_mips_inner_O32
++	REG_L	a0, 4($15)	 # cif 
++	REG_L	a1, 8($15)	 # fun
++	move	a2, $15		 # user_data = go closure
++	addu	a3, $fp, V0_OFF2 # rvalue
++
++	addu	t9, $fp, A0_OFF2 # ar
++	REG_S   t9, CALLED_A4_OFF2($fp)
++
++	addu	t9, $fp, FA_0_0_OFF2 #fpr
++	REG_S   t9, CALLED_A5_OFF2($fp)
++
++	b $do_closure
++
++$LFE1:
++	.end ffi_go_closure_O32
++
+ 	.align	2
+ 	.globl	ffi_closure_O32
+ 	.ent	ffi_closure_O32
+ ffi_closure_O32:
+-$LFB1:
++$LFB2:
+ 	# Prologue
+ 	.frame	$fp, SIZEOF_FRAME2, ra
+ 	.set	noreorder
+@@ -239,14 +302,14 @@ $LFB1:
+ 	.set	reorder
+ 	SUBU	$sp, SIZEOF_FRAME2
+ 	.cprestore GP_OFF2
+-$LCFI4:
++$LCFI20:
+ 	REG_S	$16, S0_OFF2($sp)	 # Save s0
+ 	REG_S	$fp, FP_OFF2($sp)	 # Save frame pointer
+ 	REG_S	ra, RA_OFF2($sp)	 # Save return address
+-$LCFI6:
++$LCFI21:
+ 	move	$fp, $sp
+ 
+-$LCFI7:
++$LCFI22:
+ 	# Store all possible argument registers. If there are more than
+ 	# four arguments, then they are stored above where we put a3.
+ 	REG_S	a0, A0_OFF2($fp)
+@@ -265,12 +328,21 @@ $LCFI7:
+ 	s.d	$f12, FA_0_0_OFF2($fp)
+ 	s.d	$f14, FA_1_0_OFF2($fp)
+ 1:	
+-	# Call ffi_closure_mips_inner_O32 to do the work.
++	# prepare arguments for ffi_closure_mips_inner_O32
++	REG_L	a0, 20($12)	 # cif pointer follows tramp.
++	REG_L	a1, 24($12)	 # fun
++	REG_L	a2, 28($12)	 # user_data
++	addu	a3, $fp, V0_OFF2 # rvalue
++
++	addu	t9, $fp, A0_OFF2 # ar
++	REG_S   t9, CALLED_A4_OFF2($fp)
++
++	addu	t9, $fp, FA_0_0_OFF2 #fpr
++	REG_S   t9, CALLED_A5_OFF2($fp)
++
++$do_closure:
+ 	la	t9, ffi_closure_mips_inner_O32
+-	move	a0, $12	 # Pointer to the ffi_closure
+-	addu	a1, $fp, V0_OFF2
+-	addu	a2, $fp, A0_OFF2
+-	addu	a3, $fp, FA_0_0_OFF2
++	# Call ffi_closure_mips_inner_O32 to do the work.
+ 	jalr	t9
+ 
+ 	# Load the return value into the appropriate register.
+@@ -300,7 +372,7 @@ closure_done:
+ 	REG_L	ra,  RA_OFF2($sp)	 # Restore return address
+ 	ADDU	$sp, SIZEOF_FRAME2
+ 	j	ra
+-$LFE1:
++$LFE2:
+ 	.end	ffi_closure_O32
+ 
+ /* DWARF-2 unwind info. */
+@@ -322,6 +394,7 @@ $LSCIE0:
+ 	.uleb128 0x0
+ 	.align	2
+ $LECIE0:
++
+ $LSFDE0:
+ 	.4byte	$LEFDE0-$LASFDE0	 # FDE Length
+ $LASFDE0:
+@@ -330,11 +403,11 @@ $LASFDE0:
+ 	.4byte	$LFE0-$LFB0	 # FDE address range
+ 	.uleb128 0x0	 # Augmentation size
+ 	.byte	0x4	 # DW_CFA_advance_loc4
+-	.4byte	$LCFI0-$LFB0
++	.4byte	$LCFI00-$LFB0
+ 	.byte	0xe	 # DW_CFA_def_cfa_offset
+ 	.uleb128 0x18
+ 	.byte	0x4	 # DW_CFA_advance_loc4
+-	.4byte	$LCFI2-$LCFI0
++	.4byte	$LCFI01-$LCFI00
+ 	.byte	0x11	 # DW_CFA_offset_extended_sf
+ 	.uleb128 0x1e	 # $fp
+ 	.sleb128 -2	 # SIZEOF_FRAME2 - 2*FFI_SIZEOF_ARG($sp)
+@@ -342,12 +415,13 @@ $LASFDE0:
+ 	.uleb128 0x1f	 # $ra
+ 	.sleb128 -1	 # SIZEOF_FRAME2 - 1*FFI_SIZEOF_ARG($sp)
+ 	.byte	0x4	 # DW_CFA_advance_loc4
+-	.4byte	$LCFI3-$LCFI2
++	.4byte	$LCFI02-$LCFI01
+ 	.byte	0xc	 # DW_CFA_def_cfa
+ 	.uleb128 0x1e
+ 	.uleb128 0x18
+ 	.align	2
+ $LEFDE0:
++
+ $LSFDE1:
+ 	.4byte	$LEFDE1-$LASFDE1	 # FDE Length
+ $LASFDE1:
+@@ -356,11 +430,11 @@ $LASFDE1:
+ 	.4byte	$LFE1-$LFB1	 # FDE address range
+ 	.uleb128 0x0	 # Augmentation size
+ 	.byte	0x4	 # DW_CFA_advance_loc4
+-	.4byte	$LCFI4-$LFB1
++	.4byte	$LCFI10-$LFB1
+ 	.byte	0xe	 # DW_CFA_def_cfa_offset
+-	.uleb128 0x38
++	.uleb128 SIZEOF_FRAME2
+ 	.byte	0x4	 # DW_CFA_advance_loc4
+-	.4byte	$LCFI6-$LCFI4
++	.4byte	$LCFI11-$LCFI10
+ 	.byte	0x11	 # DW_CFA_offset_extended_sf
+ 	.uleb128 0x10	 # $16
+ 	.sleb128 -3	 # SIZEOF_FRAME2 - 3*FFI_SIZEOF_ARG($sp)
+@@ -371,11 +445,41 @@ $LASFDE1:
+ 	.uleb128 0x1f	 # $ra
+ 	.sleb128 -1	 # SIZEOF_FRAME2 - 1*FFI_SIZEOF_ARG($sp)
+ 	.byte	0x4	 # DW_CFA_advance_loc4
+-	.4byte	$LCFI7-$LCFI6
++	.4byte	$LCFI12-$LCFI11
+ 	.byte	0xc	 # DW_CFA_def_cfa
+ 	.uleb128 0x1e
+-	.uleb128 0x38
++	.uleb128 SIZEOF_FRAME2
+ 	.align	2
+ $LEFDE1:
+ 
++$LSFDE2:
++	.4byte	$LEFDE2-$LASFDE2	 # FDE Length
++$LASFDE2:
++	.4byte	$LASFDE2-$Lframe0	 # FDE CIE offset
++	.4byte	$LFB2	 # FDE initial location
++	.4byte	$LFE2-$LFB2	 # FDE address range
++	.uleb128 0x0	 # Augmentation size
++	.byte	0x4	 # DW_CFA_advance_loc4
++	.4byte	$LCFI20-$LFB2
++	.byte	0xe	 # DW_CFA_def_cfa_offset
++	.uleb128 SIZEOF_FRAME2
++	.byte	0x4	 # DW_CFA_advance_loc4
++	.4byte	$LCFI21-$LCFI20
++	.byte	0x11	 # DW_CFA_offset_extended_sf
++	.uleb128 0x10	 # $16
++	.sleb128 -3	 # SIZEOF_FRAME2 - 3*FFI_SIZEOF_ARG($sp)
++	.byte	0x11	 # DW_CFA_offset_extended_sf
++	.uleb128 0x1e	 # $fp
++	.sleb128 -2	 # SIZEOF_FRAME2 - 2*FFI_SIZEOF_ARG($sp)
++	.byte	0x11	 # DW_CFA_offset_extended_sf
++	.uleb128 0x1f	 # $ra
++	.sleb128 -1	 # SIZEOF_FRAME2 - 1*FFI_SIZEOF_ARG($sp)
++	.byte	0x4	 # DW_CFA_advance_loc4
++	.4byte	$LCFI22-$LCFI21
++	.byte	0xc	 # DW_CFA_def_cfa
++	.uleb128 0x1e
++	.uleb128 SIZEOF_FRAME2
++	.align	2
++$LEFDE2:
++
+ #endif
--- gcc-6-6.4.0.orig/debian/patches/libffi-mipsen-r6.diff
+++ gcc-6-6.4.0/debian/patches/libffi-mipsen-r6.diff
@@ -0,0 +1,14 @@
+# DP: libffi: mips/n32.S: disable .set mips4 on mips r6
+
+--- a/src/libffi/src/mips/n32.S
++++ b/src/libffi/src/mips/n32.S
+@@ -47,7 +47,9 @@
+ #ifdef __GNUC__
+ 	.abicalls
+ #endif
++#if !defined(__mips_isa_rev) || (__mips_isa_rev<6)
+ 	.set mips4
++#endif
+ 	.text
+ 	.align	2
+ 	.globl	ffi_call_N32
--- gcc-6-6.4.0.orig/debian/patches/libffi-pax.diff
+++ gcc-6-6.4.0/debian/patches/libffi-pax.diff
@@ -0,0 +1,161 @@
+From 757876336c183f5b20b6620d674cc9817fd0d280 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Stefan=20B=C3=BChler?= <buehler@cert.uni-stuttgart.de>
+Date: Wed, 7 Sep 2016 15:50:54 +0200
+Subject: [PATCH 2/2] always check for PaX MPROTECT on linux, make EMUTRAMP
+ experimental
+
+- ffi_prep_closure_loc doesn't necessarily generate trampolines recognized by
+  PaX EMUTRAMP handler; there is no way to check before, and it isn't working
+on x86-64 right now -> experimental
+- if MPROTECT is enabled use the same workaround as is used for SELinux (double
+  mmap())
+---
+ configure.ac   | 11 +++++++---
+ src/closures.c | 68 +++++++++++++++++++++++++++++++++++++++-------------------
+ 2 files changed, 54 insertions(+), 25 deletions(-)
+
+--- a/src/libffi/configure.ac
++++ b/src/libffi/configure.ac
+@@ -177,12 +177,17 @@
+     ;;
+ esac
+ 
+-# On PaX enable kernels that have MPROTECT enable we can't use PROT_EXEC.
++# On PaX enable kernels that have MPROTECT enable we can't use PROT_EXEC;
++# if EMUTRAMP is active too ffi could try mapping without PROT_EXEC,
++# but the kernel needs to recognize the trampoline generated by ffi.
++# Otherwise fallback to double mmap trick.
+ AC_ARG_ENABLE(pax_emutramp,
+-  [  --enable-pax_emutramp       enable pax emulated trampolines, for we can't use PROT_EXEC],
++  [  --enable-pax_emutramp       enable pax emulated trampolines (experimental)],
+   if test "$enable_pax_emutramp" = "yes"; then
++    AC_MSG_WARN([EMUTRAMP is experimental only.  Use --enable-pax_emutramp=experimental to enforce.])
++  elif test "$enable_pax_emutramp" = "experimental"; then
+     AC_DEFINE(FFI_MMAP_EXEC_EMUTRAMP_PAX, 1,
+-      [Define this if you want to enable pax emulated trampolines])
++      [Define this if you want to enable pax emulated trampolines (experimental)])
+   fi)
+ 
+ FFI_EXEC_TRAMPOLINE_TABLE=0
+--- a/src/libffi/src/closures.c
++++ b/src/libffi/src/closures.c
+@@ -53,14 +53,18 @@
+ # endif
+ #endif
+ 
+-#if FFI_MMAP_EXEC_WRIT && !defined FFI_MMAP_EXEC_SELINUX
+-# ifdef __linux__
++#if FFI_MMAP_EXEC_WRIT && defined __linux__
++# if !defined FFI_MMAP_EXEC_SELINUX
+ /* When defined to 1 check for SELinux and if SELinux is active,
+    don't attempt PROT_EXEC|PROT_WRITE mapping at all, as that
+    might cause audit messages.  */
+ #  define FFI_MMAP_EXEC_SELINUX 1
+-# endif
+-#endif
++# endif /* !defined FFI_MMAP_EXEC_SELINUX */
++# if !defined FFI_MMAP_PAX
++/* Also check for PaX MPROTECT */
++#  define FFI_MMAP_PAX 1
++# endif /* !defined FFI_MMAP_PAX */
++#endif /* FFI_MMAP_EXEC_WRIT && defined __linux__ */
+ 
+ #if FFI_CLOSURES
+ 
+@@ -172,14 +176,18 @@
+ 
+ #endif /* !FFI_MMAP_EXEC_SELINUX */
+ 
+-/* On PaX enable kernels that have MPROTECT enable we can't use PROT_EXEC. */
+-#ifdef FFI_MMAP_EXEC_EMUTRAMP_PAX
++/* On PaX enable kernels that have MPROTECT enabled we can't use PROT_EXEC. */
++#if defined FFI_MMAP_PAX
+ #include <stdlib.h>
+ 
+-static int emutramp_enabled = -1;
++enum {
++  PAX_MPROTECT = (1 << 0),
++  PAX_EMUTRAMP = (1 << 1),
++};
++static int cached_pax_flags = -1;
+ 
+ static int
+-emutramp_enabled_check (void)
++pax_flags_check (void)
+ {
+   char *buf = NULL;
+   size_t len = 0;
+@@ -193,9 +201,10 @@
+   while (getline (&buf, &len, f) != -1)
+     if (!strncmp (buf, "PaX:", 4))
+       {
+-        char emutramp;
+-        if (sscanf (buf, "%*s %*c%c", &emutramp) == 1)
+-          ret = (emutramp == 'E');
++        if (NULL != strchr (buf + 4, 'M'))
++          ret |= PAX_MPROTECT;
++        if (NULL != strchr (buf + 4, 'E'))
++          ret |= PAX_EMUTRAMP;
+         break;
+       }
+   free (buf);
+@@ -203,9 +212,13 @@
+   return ret;
+ }
+ 
+-#define is_emutramp_enabled() (emutramp_enabled >= 0 ? emutramp_enabled \
+-                               : (emutramp_enabled = emutramp_enabled_check ()))
+-#endif /* FFI_MMAP_EXEC_EMUTRAMP_PAX */
++#define get_pax_flags() (cached_pax_flags >= 0 ? cached_pax_flags \
++                               : (cached_pax_flags = pax_flags_check ()))
++#define has_pax_flags(flags) ((flags) == ((flags) & get_pax_flags ()))
++#define is_mprotect_enabled() (has_pax_flags (PAX_MPROTECT))
++#define is_emutramp_enabled() (has_pax_flags (PAX_EMUTRAMP))
++
++#endif /* defined FFI_MMAP_PAX */
+ 
+ #elif defined (__CYGWIN__) || defined(__INTERIX)
+ 
+@@ -216,9 +229,10 @@
+ 
+ #endif /* !defined(X86_WIN32) && !defined(X86_WIN64) */
+ 
+-#ifndef FFI_MMAP_EXEC_EMUTRAMP_PAX
+-#define is_emutramp_enabled() 0
+-#endif /* FFI_MMAP_EXEC_EMUTRAMP_PAX */
++#if !defined FFI_MMAP_PAX
++# define is_mprotect_enabled() 0
++# define is_emutramp_enabled() 0
++#endif /* !defined FFI_MMAP_PAX */
+ 
+ /* Declare all functions defined in dlmalloc.c as static.  */
+ static void *dlmalloc(size_t);
+@@ -525,13 +539,23 @@
+   printf ("mapping in %zi\n", length);
+ #endif
+ 
+-  if (execfd == -1 && is_emutramp_enabled ())
++  /* -1 != execfd hints that we already decided to use dlmmap_locked
++     last time.  */
++  if (execfd == -1 && is_mprotect_enabled ())
+     {
+-      ptr = mmap (start, length, prot & ~PROT_EXEC, flags, fd, offset);
+-      return ptr;
++#ifdef FFI_MMAP_EXEC_EMUTRAMP_PAX
++      if (is_emutramp_enabled ())
++        {
++          /* emutramp requires the kernel recognizing the trampoline pattern
++             generated by ffi_prep_closure_loc; there is no way to test
++             in advance whether this will work, so this is experimental.  */
++          ptr = mmap (start, length, prot & ~PROT_EXEC, flags, fd, offset);
++          return ptr;
++        }
++#endif
++      /* fallback to dlmmap_locked.  */
+     }
+-
+-  if (execfd == -1 && !is_selinux_enabled ())
++  else if (execfd == -1 && !is_selinux_enabled ())
+     {
+       ptr = mmap (start, length, prot | PROT_EXEC, flags, fd, offset);
+ 
--- gcc-6-6.4.0.orig/debian/patches/libffi-race-condition.diff
+++ gcc-6-6.4.0/debian/patches/libffi-race-condition.diff
@@ -0,0 +1,33 @@
+From 48d2e46528fb6e621d95a7fa194069fd136b712d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Stefan=20B=C3=BChler?= <buehler@cert.uni-stuttgart.de>
+Date: Wed, 7 Sep 2016 15:49:48 +0200
+Subject: [PATCH 1/2] dlmmap_locked always needs locking as it always modifies
+ execsize
+
+---
+ src/closures.c | 13 ++++---------
+ 1 file changed, 4 insertions(+), 9 deletions(-)
+
+--- a/src/libffi/src/closures.c
++++ b/src/libffi/src/closures.c
+@@ -568,16 +568,11 @@
+ 	 MREMAP_DUP and prot at this point.  */
+     }
+ 
+-  if (execsize == 0 || execfd == -1)
+-    {
+-      pthread_mutex_lock (&open_temp_exec_file_mutex);
+-      ptr = dlmmap_locked (start, length, prot, flags, offset);
+-      pthread_mutex_unlock (&open_temp_exec_file_mutex);
++  pthread_mutex_lock (&open_temp_exec_file_mutex);
++  ptr = dlmmap_locked (start, length, prot, flags, offset);
++  pthread_mutex_unlock (&open_temp_exec_file_mutex);
+ 
+-      return ptr;
+-    }
+-
+-  return dlmmap_locked (start, length, prot, flags, offset);
++  return ptr;
+ }
+ 
+ /* Release memory at the given address, as well as the corresponding
--- gcc-6-6.4.0.orig/debian/patches/libffi-ro-eh_frame_sect.diff
+++ gcc-6-6.4.0/debian/patches/libffi-ro-eh_frame_sect.diff
@@ -0,0 +1,15 @@
+# DP: PR libffi/47248, force a read only eh frame section.
+
+Index: b/src/libffi/configure.ac
+===================================================================
+--- a/src/libffi/configure.ac
++++ b/src/libffi/configure.ac
+@@ -275,6 +275,8 @@ if test "x$GCC" = "xyes"; then
+   		libffi_cv_hidden_visibility_attribute=yes
+   	    fi
+   	fi
++	# FIXME: see PR libffi/47248
++	libffi_cv_ro_eh_frame=yes
+   	rm -f conftest.*
+       ])
+   if test $libffi_cv_hidden_visibility_attribute = yes; then
--- gcc-6-6.4.0.orig/debian/patches/libgnatprj-cross-hack.diff
+++ gcc-6-6.4.0/debian/patches/libgnatprj-cross-hack.diff
@@ -0,0 +1,66 @@
+This is a gross hack to cross build libgnatprj without having the
+gmp.h header for the target architecture.  Are libgnatvsn and libgnatprj
+really target libraries, or host libraries? The odd thing is that
+the gnat cross build tools are not linked against these two libraries.
+
+Index: b/src/gcc/wide-int.h
+===================================================================
+--- a/src/gcc/wide-int.h
++++ b/src/gcc/wide-int.h
+@@ -3106,8 +3106,10 @@ namespace wi
+   wide_int from_buffer (const unsigned char *, unsigned int);
+ 
+ #ifndef GENERATOR_FILE
++#ifndef LIBGNATPRJ_CROSS_HACK
+   void to_mpz (const wide_int_ref &, mpz_t, signop);
+ #endif
++#endif
+ 
+   wide_int mask (unsigned int, bool, unsigned int);
+   wide_int shifted_mask (unsigned int, unsigned int, bool, unsigned int);
+Index: b/src/gcc/system.h
+===================================================================
+--- a/src/gcc/system.h
++++ b/src/gcc/system.h
+@@ -678,8 +678,10 @@ extern int vsnprintf (char *, size_t, co
+ 
+ /* Do not introduce a gmp.h dependency on the build system.  */
+ #ifndef GENERATOR_FILE
++#ifndef LIBGNATPRJ_CROSS_HACK
+ #include <gmp.h>
+ #endif
++#endif
+ 
+ /* Get libiberty declarations.  */
+ #include "libiberty.h"
+Index: b/src/libgnatprj/Makefile.in
+===================================================================
+--- a/src/libgnatprj/Makefile.in
++++ b/src/libgnatprj/Makefile.in
+@@ -37,7 +37,7 @@ TOOLS_TARGET_PAIRS := @TOOLS_TARGET_PAIR
+ LN_S := @LN_S@
+ 
+ ifneq (@build@,@host@)
+-   CFLAGS += -b @host@
++   override CFLAGS += -DLIBGNATPRJ_CROSS_HACK
+ endif
+ 
+ .PHONY: libgnatprj install
+Index: b/src/gcc/double-int.h
+===================================================================
+--- a/src/gcc/double-int.h
++++ b/src/gcc/double-int.h
+@@ -429,11 +429,13 @@ double_int::popcount () const
+ 
+ 
+ #ifndef GENERATOR_FILE
++#ifndef LIBGNATPRJ_CROSS_HACK
+ /* Conversion to and from GMP integer representations.  */
+ 
+ void mpz_set_double_int (mpz_t, double_int, bool);
+ double_int mpz_get_double_int (const_tree, mpz_t, bool);
+ #endif
++#endif
+ 
+ namespace wi
+ {
--- gcc-6-6.4.0.orig/debian/patches/libgnatprj-link.diff
+++ gcc-6-6.4.0/debian/patches/libgnatprj-link.diff
@@ -0,0 +1,21 @@
+# DP: Don't link libgnatprj using --no-allow-shlib-undefined on older releases.
+
+in precise:
+/lib/x86_64-linux-gnu/libc.so.6: undefined reference to `_rtld_global@GLIBC_PRIVATE'
+/lib/x86_64-linux-gnu/libc.so.6: undefined reference to `_dl_argv@GLIBC_PRIVATE'
+/lib/x86_64-linux-gnu/libc.so.6: undefined reference to `_rtld_global_ro@GLIBC_PRIVATE'
+/lib/x86_64-linux-gnu/libc.so.6: undefined reference to `__libc_enable_secure@GLIBC_PRIVATE'
+/lib/x86_64-linux-gnu/libc.so.6: undefined reference to `__tls_get_addr@GLIBC_2.3'
+collect2: error: ld returned 1 exit status
+
+--- a/src/libgnatprj/Makefile.in
++++ b/src/libgnatprj/Makefile.in
+@@ -74,7 +74,7 @@
+ 
+ libgnatprj.so.$(LIB_VERSION): $(addprefix obj-shared/,$(OBJECTS))
+ 	: # Make libgnatprj.so
+-	$(GCC) -o $@ -shared -fPIC -Wl,--soname,$@ -Wl,--no-allow-shlib-undefined \
++	$(GCC) -o $@ -shared -fPIC -Wl,--soname,$@ \
+ 	   $^ $(addprefix ../libiberty/pic/,$(LIBIBERTY_OBJECTS)) \
+ 	   -L../gcc/ada/rts -lgnat-$(LIB_VERSION) \
+ 	   -L../libgnatvsn -lgnatvsn
--- gcc-6-6.4.0.orig/debian/patches/libgo-add-getrandom-mips-sparc.diff
+++ gcc-6-6.4.0/debian/patches/libgo-add-getrandom-mips-sparc.diff
@@ -0,0 +1,67 @@
+# DP: Backport r240457 from trunk
+
+internal/syscall/unix: add getrandom syscall for MIPS and SPARC
+
+Reviewed-on: https://go-review.googlesource.com/29678
+
+Index: b/src/libgo/go/internal/syscall/unix/getrandom_linux_mipso32.go
+===================================================================
+--- a/src/libgo/go/internal/syscall/unix/getrandom_linux_mipso32.go	(nonexistent)
++++ b/src/libgo/go/internal/syscall/unix/getrandom_linux_mipso32.go	(revision 240457)
+@@ -0,0 +1,11 @@
++// Copyright 2016 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build mipso32
++
++package unix
++
++// Linux getrandom system call number.
++// See GetRandom in getrandom_linux.go.
++const randomTrap uintptr = 4353
+Index: b/src/libgo/go/internal/syscall/unix/getrandom_linux_sparc.go
+===================================================================
+--- a/src/libgo/go/internal/syscall/unix/getrandom_linux_sparc.go	(nonexistent)
++++ b/src/libgo/go/internal/syscall/unix/getrandom_linux_sparc.go	(revision 240457)
+@@ -0,0 +1,11 @@
++// Copyright 2016 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build sparc sparc64
++
++package unix
++
++// Linux getrandom system call number.
++// See GetRandom in getrandom_linux.go.
++const randomTrap uintptr = 347
+Index: b/src/libgo/go/internal/syscall/unix/getrandom_linux_mips64x.go
+===================================================================
+--- a/src/libgo/go/internal/syscall/unix/getrandom_linux_mips64x.go	(revision 240456)
++++ b/src/libgo/go/internal/syscall/unix/getrandom_linux_mips64x.go	(revision 240457)
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build mips64 mips64le
++// +build mips64 mips64le mipsn64 mipso64
+ 
+ package unix
+ 
+Index: b/src/libgo/go/internal/syscall/unix/getrandom_linux_mipsn32.go
+===================================================================
+--- a/src/libgo/go/internal/syscall/unix/getrandom_linux_mipsn32.go	(nonexistent)
++++ b/src/libgo/go/internal/syscall/unix/getrandom_linux_mipsn32.go	(revision 240457)
+@@ -0,0 +1,11 @@
++// Copyright 2016 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build mipsn32
++
++package unix
++
++// Linux getrandom system call number.
++// See GetRandom in getrandom_linux.go.
++const randomTrap uintptr = 6317
--- gcc-6-6.4.0.orig/debian/patches/libgo-elf-relocations-sparc64.diff
+++ gcc-6-6.4.0/debian/patches/libgo-elf-relocations-sparc64.diff
@@ -0,0 +1,106 @@
+# DP: Backport r241051 from trunk
+# DP: src/libgo/go/debug/elf/testdata/go-relocation-test-gcc620-sparc64.obj is
+# DP: encoded in debian/go-relocation-test-gcc620-sparc64.obj.uue and is
+# DP: decoded at patch time.
+
+debug/elf: add sparc64 relocations
+
+This is a backport of https://go-review.googlesource.com/30870.
+
+Reviewed-on: https://go-review.googlesource.com/30916
+
+Index: b/src/libgo/go/debug/elf/file_test.go
+===================================================================
+--- a/src/libgo/go/debug/elf/file_test.go
++++ b/src/libgo/go/debug/elf/file_test.go
+@@ -473,6 +473,25 @@ var relocationTests = []relocationTest{
+ 		},
+ 	},
+ 	{
++		"testdata/go-relocation-test-gcc620-sparc64.obj",
++		[]relocationTestEntry{
++			{0, &dwarf.Entry{
++				Offset:   0xb,
++				Tag:      dwarf.TagCompileUnit,
++				Children: true,
++				Field: []dwarf.Field{
++					{Attr: dwarf.AttrProducer, Val: "GNU C11 6.2.0 20160914 -mcpu=v9 -g -fstack-protector-strong", Class: dwarf.ClassString},
++					{Attr: dwarf.AttrLanguage, Val: int64(12), Class: dwarf.ClassConstant},
++					{Attr: dwarf.AttrName, Val: "hello.c", Class: dwarf.ClassString},
++					{Attr: dwarf.AttrCompDir, Val: "/tmp", Class: dwarf.ClassString},
++					{Attr: dwarf.AttrLowpc, Val: uint64(0x0), Class: dwarf.ClassAddress},
++					{Attr: dwarf.AttrHighpc, Val: int64(0x2c), Class: dwarf.ClassConstant},
++					{Attr: dwarf.AttrStmtList, Val: int64(0), Class: dwarf.ClassLinePtr},
++				},
++			}},
++		},
++	},
++	{
+ 		"testdata/go-relocation-test-gcc493-mips64le.obj",
+ 		[]relocationTestEntry{
+ 			{0, &dwarf.Entry{
+Index: b/src/libgo/go/debug/elf/file.go
+===================================================================
+--- a/src/libgo/go/debug/elf/file.go
++++ b/src/libgo/go/debug/elf/file.go
+@@ -598,6 +598,8 @@ func (f *File) applyRelocations(dst []by
+ 		return f.applyRelocationsMIPS64(dst, rels)
+ 	case f.Class == ELFCLASS64 && f.Machine == EM_S390:
+ 		return f.applyRelocationsS390x(dst, rels)
++	case f.Class == ELFCLASS64 && f.Machine == EM_SPARCV9:
++		return f.applyRelocationsSPARC64(dst, rels)
+ 	default:
+ 		return errors.New("applyRelocations: not implemented")
+ 	}
+@@ -951,6 +953,51 @@ func (f *File) applyRelocationsS390x(dst
+ 		}
+ 	}
+ 
++	return nil
++}
++
++func (f *File) applyRelocationsSPARC64(dst []byte, rels []byte) error {
++	// 24 is the size of Rela64.
++	if len(rels)%24 != 0 {
++		return errors.New("length of relocation section is not a multiple of 24")
++	}
++
++	symbols, _, err := f.getSymbols(SHT_SYMTAB)
++	if err != nil {
++		return err
++	}
++
++	b := bytes.NewReader(rels)
++	var rela Rela64
++
++	for b.Len() > 0 {
++		binary.Read(b, f.ByteOrder, &rela)
++		symNo := rela.Info >> 32
++		t := R_SPARC(rela.Info & 0xffff)
++
++		if symNo == 0 || symNo > uint64(len(symbols)) {
++			continue
++		}
++		sym := &symbols[symNo-1]
++		if SymType(sym.Info&0xf) != STT_SECTION {
++			// We don't handle non-section relocations for now.
++			continue
++		}
++
++		switch t {
++		case R_SPARC_64, R_SPARC_UA64:
++			if rela.Off+8 >= uint64(len(dst)) || rela.Addend < 0 {
++				continue
++			}
++			f.ByteOrder.PutUint64(dst[rela.Off:rela.Off+8], uint64(rela.Addend))
++		case R_SPARC_32, R_SPARC_UA32:
++			if rela.Off+4 >= uint64(len(dst)) || rela.Addend < 0 {
++				continue
++			}
++			f.ByteOrder.PutUint32(dst[rela.Off:rela.Off+4], uint32(rela.Addend))
++		}
++	}
++
+ 	return nil
+ }
+ 
--- gcc-6-6.4.0.orig/debian/patches/libgo-fix-getrandom-clone-sparc64.diff
+++ gcc-6-6.4.0/debian/patches/libgo-fix-getrandom-clone-sparc64.diff
@@ -0,0 +1,343 @@
+# DP: Backport r241072 from trunk
+
+syscall, internal/syscall/unix: Fix getrandom, clone on sparc64
+
+Since sparc is a valid architecture, the name of
+getrandom_linux_sparc.go means that it will be ignored on sparc64,
+even though it's whitelisted with a +build line.
+
+On SPARC, clone has a unique return value convention which requires
+some inline assembly to convert it to the normal convention.
+
+Reviewed-on: https://go-review.googlesource.com/30873
+
+Index: b/src/libgo/mksysinfo.sh
+===================================================================
+--- a/src/libgo/mksysinfo.sh
++++ b/src/libgo/mksysinfo.sh
+@@ -603,8 +603,10 @@ fi
+ sizeof_long=`grep '^const ___SIZEOF_LONG__ = ' gen-sysinfo.go | sed -e 's/.*= //'`
+ if test "$sizeof_long" = "4"; then
+   echo "type _C_long int32" >> ${OUT}
++  echo "type _C_ulong uint32" >> ${OUT}
+ elif test "$sizeof_long" = "8"; then
+   echo "type _C_long int64" >> ${OUT}
++  echo "type _C_ulong uint64" >> ${OUT}
+ else
+   echo 1>&2 "mksysinfo.sh: could not determine size of long (got $sizeof_long)"
+   exit 1
+Index: b/src/libgo/go/internal/syscall/unix/getrandom_linux_sparc.go
+===================================================================
+--- a/src/libgo/go/internal/syscall/unix/getrandom_linux_sparc.go
++++ b/src/libgo/go/internal/syscall/unix/getrandom_linux_sparc.go
+@@ -1,11 +0,0 @@
+-// Copyright 2016 The Go Authors. All rights reserved.
+-// Use of this source code is governed by a BSD-style
+-// license that can be found in the LICENSE file.
+-
+-// +build sparc sparc64
+-
+-package unix
+-
+-// Linux getrandom system call number.
+-// See GetRandom in getrandom_linux.go.
+-const randomTrap uintptr = 347
+Index: b/src/libgo/go/internal/syscall/unix/getrandom_linux_sparcx.go
+===================================================================
+--- /dev/null
++++ b/src/libgo/go/internal/syscall/unix/getrandom_linux_sparcx.go
+@@ -0,0 +1,11 @@
++// Copyright 2016 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build sparc sparc64
++
++package unix
++
++// Linux getrandom system call number.
++// See GetRandom in getrandom_linux.go.
++const randomTrap uintptr = 347
+Index: b/src/libgo/go/syscall/clone_linux.c
+===================================================================
+--- /dev/null
++++ b/src/libgo/go/syscall/clone_linux.c
+@@ -0,0 +1,100 @@
++/* clone_linux.c -- consistent wrapper around Linux clone syscall
++
++   Copyright 2016 The Go Authors. All rights reserved.
++   Use of this source code is governed by a BSD-style
++   license that can be found in the LICENSE file.  */
++
++#include <errno.h>
++#include <asm/ptrace.h>
++#include <sys/syscall.h>
++
++#include "runtime.h"
++
++long rawClone (unsigned long flags, void *child_stack, void *ptid, void *ctid, struct pt_regs *regs) __asm__ (GOSYM_PREFIX "syscall.rawClone");
++
++long
++rawClone (unsigned long flags, void *child_stack, void *ptid, void *ctid, struct pt_regs *regs)
++{
++#if defined(__arc__) || defined(__aarch64__) || defined(__arm__) || defined(__mips__) || defined(__hppa__) || defined(__powerpc__) || defined(__score__) || defined(__i386__) || defined(__xtensa__)
++  // CLONE_BACKWARDS
++  return syscall(__NR_clone, flags, child_stack, ptid, regs, ctid);
++#elif defined(__s390__) || defined(__cris__)
++  // CLONE_BACKWARDS2
++  return syscall(__NR_clone, child_stack, flags, ptid, ctid, regs);
++#elif defined(__microblaze__)
++  // CLONE_BACKWARDS3
++  return syscall(__NR_clone, flags, child_stack, 0, ptid, ctid, regs);
++#elif defined(__sparc__)
++
++  /* SPARC has a unique return value convention:
++
++     Parent -->  %o0 == child's  pid, %o1 == 0
++     Child  -->  %o0 == parent's pid, %o1 == 1
++
++     Translate this to look like a normal clone.  */
++
++# if defined(__arch64__)
++
++#  define SYSCALL_STRING						\
++	"ta	0x6d;"							\
++	"bcc,pt	%%xcc, 1f;"						\
++	" mov	0, %%g1;"						\
++	"sub	%%g0, %%o0, %%o0;"					\
++	"mov	1, %%g1;"						\
++	"1:"
++
++#  define SYSCALL_CLOBBERS						\
++	"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",			\
++	"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",		\
++	"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",		\
++	"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",		\
++	"f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",		\
++	"f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",		\
++	"cc", "memory"
++
++# else /* __arch64__ */
++
++#  define SYSCALL_STRING						\
++	"ta	0x10;"							\
++	"bcc	1f;"							\
++	" mov	0, %%g1;"						\
++	"sub	%%g0, %%o0, %%o0;"					\
++	"mov	1, %%g1;"						\
++	"1:"
++
++#  define SYSCALL_CLOBBERS						\
++	"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",			\
++	"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",		\
++	"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",		\
++	"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",		\
++	"cc", "memory"
++
++# endif /* __arch64__ */
++
++  register long o0 __asm__ ("o0") = (long)flags;
++  register long o1 __asm__ ("o1") = (long)child_stack;
++  register long o2 __asm__ ("o2") = (long)ptid;
++  register long o3 __asm__ ("o3") = (long)ctid;
++  register long o4 __asm__ ("o4") = (long)regs;
++  register long g1 __asm__ ("g1") = __NR_clone;
++
++  __asm __volatile (SYSCALL_STRING :
++		    "=r" (g1), "=r" (o0), "=r" (o1) :
++		    "0" (g1), "1" (o0), "2" (o1),
++		    "r" (o2), "r" (o3), "r" (o4) :
++		    SYSCALL_CLOBBERS);
++
++  if (__builtin_expect(g1 != 0, 0))
++    {
++      errno = -o0;
++      o0 = -1L;
++    }
++  else
++    o0 &= (o1 - 1);
++
++  return o0;
++
++#else
++  return syscall(__NR_clone, flags, child_stack, ptid, ctid, regs);
++#endif
++}
+Index: b/src/libgo/go/syscall/exec_linux.go
+===================================================================
+--- a/src/libgo/go/syscall/exec_linux.go
++++ b/src/libgo/go/syscall/exec_linux.go
+@@ -7,7 +7,6 @@
+ package syscall
+ 
+ import (
+-	"runtime"
+ 	"unsafe"
+ )
+ 
+@@ -48,6 +47,9 @@ type SysProcAttr struct {
+ func runtime_BeforeFork()
+ func runtime_AfterFork()
+ 
++// Implemented in clone_linux.c
++func rawClone(flags _C_ulong, child_stack *byte, ptid *Pid_t, ctid *Pid_t, regs unsafe.Pointer) _C_long
++
+ // Fork, dup fd onto 0..len(fd), and exec(argv0, argvv, envv) in child.
+ // If a dup or exec fails, write the errno error to pipe.
+ // (Pipe is close-on-exec so if exec succeeds, it will be closed.)
+@@ -63,6 +65,7 @@ func forkAndExecInChild(argv0 *byte, arg
+ 	// declarations require heap allocation (e.g., err1).
+ 	var (
+ 		r1     uintptr
++		r2     _C_long
+ 		err1   Errno
+ 		err2   Errno
+ 		nextfd int
+@@ -97,20 +100,16 @@ func forkAndExecInChild(argv0 *byte, arg
+ 	// About to call fork.
+ 	// No more allocation or calls of non-assembly functions.
+ 	runtime_BeforeFork()
+-	if runtime.GOARCH == "s390x" || runtime.GOARCH == "s390" {
+-		r1, _, err1 = RawSyscall6(SYS_CLONE, 0, uintptr(SIGCHLD)|sys.Cloneflags, 0, 0, 0, 0)
+-	} else {
+-		r1, _, err1 = RawSyscall6(SYS_CLONE, uintptr(SIGCHLD)|sys.Cloneflags, 0, 0, 0, 0, 0)
+-	}
+-	if err1 != 0 {
++	r2 = rawClone(_C_ulong(uintptr(SIGCHLD)|sys.Cloneflags), nil, nil, nil, unsafe.Pointer(nil))
++	if r2 < 0 {
+ 		runtime_AfterFork()
+-		return 0, err1
++		return 0, GetErrno()
+ 	}
+ 
+-	if r1 != 0 {
++	if r2 != 0 {
+ 		// parent; return PID
+ 		runtime_AfterFork()
+-		pid = int(r1)
++		pid = int(r2)
+ 
+ 		if sys.UidMappings != nil || sys.GidMappings != nil {
+ 			Close(p[0])
+Index: b/src/libgo/Makefile.am
+===================================================================
+--- a/src/libgo/Makefile.am
++++ b/src/libgo/Makefile.am
+@@ -2145,6 +2145,12 @@ else
+ os_lib_inotify_lo =
+ endif
+ 
++if LIBGO_IS_LINUX
++syscall_lib_clone_lo = syscall/clone_linux.lo
++else
++syscall_lib_clone_lo =
++endif
++
+ libgo_go_objs = \
+ 	bufio.lo \
+ 	bytes.lo \
+@@ -2175,6 +2181,7 @@ libgo_go_objs = \
+ 	strings/index.lo \
+ 	sync.lo \
+ 	syscall.lo \
++	$(syscall_lib_clone_lo) \
+ 	syscall/errno.lo \
+ 	syscall/signame.lo \
+ 	syscall/wait.lo \
+@@ -3820,6 +3827,9 @@ syscall.lo.dep: $(go_syscall_files)
+ 	$(BUILDDEPS)
+ syscall.lo: $(go_syscall_files)
+ 	$(BUILDPACKAGE)
++syscall/clone_linux.lo: go/syscall/clone_linux.c
++	@$(MKDIR_P) syscall
++	$(LTCOMPILE) -c -o $@ $<
+ syscall/errno.lo: go/syscall/errno.c
+ 	@$(MKDIR_P) syscall
+ 	$(LTCOMPILE) -c -o $@ $<
+Index: b/src/libgo/Makefile.in
+===================================================================
+--- a/src/libgo/Makefile.in
++++ b/src/libgo/Makefile.in
+@@ -173,15 +173,16 @@ am__objects_3 = $(am__objects_2)
+ am_libnetgo_a_OBJECTS = $(am__objects_3)
+ libnetgo_a_OBJECTS = $(am_libnetgo_a_OBJECTS)
+ LTLIBRARIES = $(toolexeclib_LTLIBRARIES)
+-am__DEPENDENCIES_1 =
+-am__DEPENDENCIES_2 = bufio.lo bytes.lo bytes/index.lo crypto.lo \
++@LIBGO_IS_LINUX_TRUE@am__DEPENDENCIES_1 = syscall/clone_linux.lo
++am__DEPENDENCIES_2 =
++am__DEPENDENCIES_3 = bufio.lo bytes.lo bytes/index.lo crypto.lo \
+ 	encoding.lo errors.lo expvar.lo flag.lo fmt.lo hash.lo html.lo \
+ 	image.lo io.lo log.lo math.lo mime.lo net.lo os.lo path.lo \
+ 	reflect-go.lo reflect/makefunc_ffi_c.lo regexp.lo \
+ 	runtime-go.lo sort.lo strconv.lo strings.lo strings/index.lo \
+-	sync.lo syscall.lo syscall/errno.lo syscall/signame.lo \
+-	syscall/wait.lo testing.lo time-go.lo unicode.lo \
+-	archive/tar.lo archive/zip.lo compress/bzip2.lo \
++	sync.lo syscall.lo $(am__DEPENDENCIES_1) syscall/errno.lo \
++	syscall/signame.lo syscall/wait.lo testing.lo time-go.lo \
++	unicode.lo archive/tar.lo archive/zip.lo compress/bzip2.lo \
+ 	compress/flate.lo compress/gzip.lo compress/lzw.lo \
+ 	compress/zlib.lo container/heap.lo container/list.lo \
+ 	container/ring.lo crypto/aes.lo crypto/cipher.lo crypto/des.lo \
+@@ -213,18 +214,18 @@ am__DEPENDENCIES_2 = bufio.lo bytes.lo b
+ 	math/rand.lo mime/multipart.lo mime/quotedprintable.lo \
+ 	net/http.lo net/internal/socktest.lo net/mail.lo net/rpc.lo \
+ 	net/smtp.lo net/textproto.lo net/url.lo old/regexp.lo \
+-	old/template.lo os/exec.lo $(am__DEPENDENCIES_1) os/signal.lo \
++	old/template.lo os/exec.lo $(am__DEPENDENCIES_2) os/signal.lo \
+ 	os/user.lo path/filepath.lo regexp/syntax.lo \
+ 	net/rpc/jsonrpc.lo runtime/debug.lo runtime/pprof.lo \
+ 	sync/atomic.lo sync/atomic_c.lo text/scanner.lo \
+ 	text/tabwriter.lo text/template.lo text/template/parse.lo \
+ 	testing/iotest.lo testing/quick.lo unicode/utf16.lo \
+ 	unicode/utf8.lo
+-am__DEPENDENCIES_3 = $(am__DEPENDENCIES_2) \
+-	../libbacktrace/libbacktrace.la $(am__DEPENDENCIES_1) \
+-	$(am__DEPENDENCIES_1) $(am__DEPENDENCIES_1) \
+-	$(am__DEPENDENCIES_1) $(am__DEPENDENCIES_1)
+-libgo_llgo_la_DEPENDENCIES = $(am__DEPENDENCIES_3)
++am__DEPENDENCIES_4 = $(am__DEPENDENCIES_3) \
++	../libbacktrace/libbacktrace.la $(am__DEPENDENCIES_2) \
++	$(am__DEPENDENCIES_2) $(am__DEPENDENCIES_2) \
++	$(am__DEPENDENCIES_2) $(am__DEPENDENCIES_2)
++libgo_llgo_la_DEPENDENCIES = $(am__DEPENDENCIES_4)
+ @LIBGO_IS_LINUX_FALSE@am__objects_4 = lock_sema.lo thread-sema.lo
+ @LIBGO_IS_LINUX_TRUE@am__objects_4 = lock_futex.lo thread-linux.lo
+ @HAVE_SYS_MMAN_H_FALSE@am__objects_5 = mem_posix_memalign.lo
+@@ -276,7 +277,7 @@ libgo_llgo_la_LINK = $(LIBTOOL) --tag=CC
+ 	$(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
+ 	$(libgo_llgo_la_LDFLAGS) $(LDFLAGS) -o $@
+ @GOC_IS_LLGO_TRUE@am_libgo_llgo_la_rpath = -rpath $(toolexeclibdir)
+-libgo_la_DEPENDENCIES = $(am__DEPENDENCIES_3)
++libgo_la_DEPENDENCIES = $(am__DEPENDENCIES_4)
+ am_libgo_la_OBJECTS = $(am__objects_9)
+ libgo_la_OBJECTS = $(am_libgo_la_OBJECTS)
+ libgo_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \
+@@ -2156,6 +2157,8 @@ go_syscall_test_files = \
+ 
+ # os_lib_inotify_lo = os/inotify.lo
+ @LIBGO_IS_LINUX_TRUE@os_lib_inotify_lo = 
++@LIBGO_IS_LINUX_FALSE@syscall_lib_clone_lo = 
++@LIBGO_IS_LINUX_TRUE@syscall_lib_clone_lo = syscall/clone_linux.lo
+ libgo_go_objs = \
+ 	bufio.lo \
+ 	bytes.lo \
+@@ -2186,6 +2189,7 @@ libgo_go_objs = \
+ 	strings/index.lo \
+ 	sync.lo \
+ 	syscall.lo \
++	$(syscall_lib_clone_lo) \
+ 	syscall/errno.lo \
+ 	syscall/signame.lo \
+ 	syscall/wait.lo \
+@@ -6197,6 +6201,9 @@ syscall.lo.dep: $(go_syscall_files)
+ 	$(BUILDDEPS)
+ syscall.lo: $(go_syscall_files)
+ 	$(BUILDPACKAGE)
++syscall/clone_linux.lo: go/syscall/clone_linux.c
++	@$(MKDIR_P) syscall
++	$(LTCOMPILE) -c -o $@ $<
+ syscall/errno.lo: go/syscall/errno.c
+ 	@$(MKDIR_P) syscall
+ 	$(LTCOMPILE) -c -o $@ $<
--- gcc-6-6.4.0.orig/debian/patches/libgo-rawClone-no-pt_regs.diff
+++ gcc-6-6.4.0/debian/patches/libgo-rawClone-no-pt_regs.diff
@@ -0,0 +1,33 @@
+# DP: Backport r241084 from trunk
+
+syscall: don't use pt_regs in clone_linux.c
+
+It's unnecessary and it reportedly breaks the build on arm64 GNU/Linux.
+
+Reviewed-on: https://go-review.googlesource.com/30978
+
+Index: b/src/libgo/go/syscall/clone_linux.c
+===================================================================
+--- a/src/libgo/go/syscall/clone_linux.c	(revision 241083)
++++ b/src/libgo/go/syscall/clone_linux.c	(revision 241084)
+@@ -5,18 +5,17 @@
+    license that can be found in the LICENSE file.  */
+ 
+ #include <errno.h>
+-#include <asm/ptrace.h>
+ #include <sys/syscall.h>
+ 
+ #include "runtime.h"
+ 
+ long rawClone (unsigned long flags, void *child_stack, void *ptid,
+-	       void *ctid, struct pt_regs *regs)
++	       void *ctid, void *regs)
+   __asm__ (GOSYM_PREFIX "syscall.rawClone")
+   __attribute__ ((no_split_stack));
+ 
+ long
+-rawClone (unsigned long flags, void *child_stack, void *ptid, void *ctid, struct pt_regs *regs)
++rawClone (unsigned long flags, void *child_stack, void *ptid, void *ctid, void *regs)
+ {
+ #if defined(__arc__) || defined(__aarch64__) || defined(__arm__) || defined(__mips__) || defined(__hppa__) || defined(__powerpc__) || defined(__score__) || defined(__i386__) || defined(__xtensa__)
+   // CLONE_BACKWARDS
--- gcc-6-6.4.0.orig/debian/patches/libgo-rawClone-no_split_stack.diff
+++ gcc-6-6.4.0/debian/patches/libgo-rawClone-no_split_stack.diff
@@ -0,0 +1,22 @@
+# DP: Backport r241171 from trunk
+
+syscall: mark rawClone as no_split_stack
+
+Reviewed-on: https://go-review.googlesource.com/30955
+
+Index: b/src/libgo/go/syscall/clone_linux.c
+===================================================================
+--- a/src/libgo/go/syscall/clone_linux.c	(revision 241071)
++++ b/src/libgo/go/syscall/clone_linux.c	(revision 241072)
+@@ -10,7 +10,10 @@
+ 
+ #include "runtime.h"
+ 
+-long rawClone (unsigned long flags, void *child_stack, void *ptid, void *ctid, struct pt_regs *regs) __asm__ (GOSYM_PREFIX "syscall.rawClone");
++long rawClone (unsigned long flags, void *child_stack, void *ptid,
++	       void *ctid, struct pt_regs *regs)
++  __asm__ (GOSYM_PREFIX "syscall.rawClone")
++  __attribute__ ((no_split_stack));
+ 
+ long
+ rawClone (unsigned long flags, void *child_stack, void *ptid, void *ctid, struct pt_regs *regs)
--- gcc-6-6.4.0.orig/debian/patches/libgo-revert-timeout-exp.diff
+++ gcc-6-6.4.0/debian/patches/libgo-revert-timeout-exp.diff
@@ -0,0 +1,12 @@
+Index: b/src/libgo/testsuite/lib/libgo.exp
+===================================================================
+--- a/src/libgo/testsuite/lib/libgo.exp
++++ b/src/libgo/testsuite/lib/libgo.exp
+@@ -46,7 +46,6 @@ load_gcc_lib wrapper.exp
+ load_gcc_lib target-supports.exp
+ load_gcc_lib target-utils.exp
+ load_gcc_lib gcc-defs.exp
+-load_gcc_lib timeout.exp
+ load_gcc_lib go.exp
+ 
+ proc libgo_init { args } {
--- gcc-6-6.4.0.orig/debian/patches/libgo-setcontext-config.diff
+++ gcc-6-6.4.0/debian/patches/libgo-setcontext-config.diff
@@ -0,0 +1,21 @@
+# DP: libgo: Overwrite the setcontext_clobbers_tls check on mips*
+
+Index: b/src/libgo/configure.ac
+===================================================================
+--- a/src/libgo/configure.ac
++++ b/src/libgo/configure.ac
+@@ -785,6 +785,14 @@ main ()
+ CFLAGS="$CFLAGS_hold"
+ LIBS="$LIBS_hold"
+ ])
++dnl overwrite for the mips* 64bit multilibs, fails on some buildds
++if test "$libgo_cv_lib_setcontext_clobbers_tls" = "yes"; then
++  case "$target" in
++  mips*-linux-*)
++    AC_MSG_WARN([FIXME: overwrite setcontext_clobbers_tls for $target:$ptr_type_size])
++    libgo_cv_lib_setcontext_clobbers_tls=no ;;
++  esac
++fi
+ if test "$libgo_cv_lib_setcontext_clobbers_tls" = "yes"; then
+   AC_DEFINE(SETCONTEXT_CLOBBERS_TLS, 1,
+ 	    [Define if setcontext clobbers TLS variables])
--- gcc-6-6.4.0.orig/debian/patches/libgo-testsuite.diff
+++ gcc-6-6.4.0/debian/patches/libgo-testsuite.diff
@@ -0,0 +1,52 @@
+# DP: Only run the libgo testsuite for flags configured in RUNTESTFLAGS
+
+Index: b/src/libgo/Makefile.am
+===================================================================
+--- a/src/libgo/Makefile.am
++++ b/src/libgo/Makefile.am
+@@ -2387,6 +2387,12 @@ CHECK = \
+ 	export LD_LIBRARY_PATH; \
+ 	$(MKDIR_P) $(@D); \
+ 	rm -f $@-testsum $@-testlog; \
++	run_check=yes; \
++	MULTILIBDIR="$(MULTILIBDIR)"; \
++	case "$$MULTILIBDIR" in /64|/x32) \
++	  echo "$$RUNTESTFLAGS" | grep -q "$${MULTILIBDIR\#/*}" || run_check=; \
++	esac; \
++	if test "$$run_check" = "yes"; then \
+ 	if test "$(USE_DEJAGNU)" = "yes"; then \
+ 	  $(SHELL) $(srcdir)/testsuite/gotest --goarch=$(GOARCH) --goos=$(GOOS) --dejagnu=yes --basedir=$(srcdir) --srcdir=$(srcdir)/go/$(@D) --pkgpath="$(@D)" --pkgfiles="$(go_$(subst /,_,$(@D))_files)" --testname="$(@D)" $(GOTESTFLAGS) $(go_$(subst /,_,$(@D))_test_files); \
+ 	elif test "$(GOBENCH)" != ""; then \
+@@ -2402,6 +2408,7 @@ CHECK = \
+ 	    echo "FAIL: $(@D)" > $@-testsum; \
+ 	    exit 1; \
+ 	  fi; \
++	fi; \
+ 	fi
+ 
+ # Build all packages before checking any.
+Index: b/src/libgo/Makefile.in
+===================================================================
+--- a/src/libgo/Makefile.in
++++ b/src/libgo/Makefile.in
+@@ -2394,6 +2394,12 @@ CHECK = \
+ 	export LD_LIBRARY_PATH; \
+ 	$(MKDIR_P) $(@D); \
+ 	rm -f $@-testsum $@-testlog; \
++	run_check=yes; \
++	MULTILIBDIR="$(MULTILIBDIR)"; \
++	case "$$MULTILIBDIR" in /64|/x32) \
++	  echo "$$RUNTESTFLAGS" | grep -q "$${MULTILIBDIR\#/*}" || run_check=; \
++	esac; \
++	if test "$$run_check" = "yes"; then \
+ 	if test "$(USE_DEJAGNU)" = "yes"; then \
+ 	  $(SHELL) $(srcdir)/testsuite/gotest --goarch=$(GOARCH) --goos=$(GOOS) --dejagnu=yes --basedir=$(srcdir) --srcdir=$(srcdir)/go/$(@D) --pkgpath="$(@D)" --pkgfiles="$(go_$(subst /,_,$(@D))_files)" --testname="$(@D)" $(GOTESTFLAGS) $(go_$(subst /,_,$(@D))_test_files); \
+ 	elif test "$(GOBENCH)" != ""; then \
+@@ -2409,6 +2415,7 @@ CHECK = \
+ 	    echo "FAIL: $(@D)" > $@-testsum; \
+ 	    exit 1; \
+ 	  fi; \
++	fi; \
+ 	fi
+ 
+ 
--- gcc-6-6.4.0.orig/debian/patches/libgomp-kfreebsd-testsuite.diff
+++ gcc-6-6.4.0/debian/patches/libgomp-kfreebsd-testsuite.diff
@@ -0,0 +1,16 @@
+# DP: Disable lock-2.c test on kfreebsd-*
+
+Index: b/src/libgomp/testsuite/libgomp.c/lock-2.c
+===================================================================
+--- a/src/libgomp/testsuite/libgomp.c/lock-2.c
++++ b/src/libgomp/testsuite/libgomp.c/lock-2.c
+@@ -4,6 +4,9 @@
+ int
+ main (void)
+ {
++#ifdef __FreeBSD_kernel__
++  return 1;
++#endif
+   int l = 0;
+   omp_nest_lock_t lock;
+   omp_init_nest_lock (&lock);
--- gcc-6-6.4.0.orig/debian/patches/libgomp-omp_h-multilib.diff
+++ gcc-6-6.4.0/debian/patches/libgomp-omp_h-multilib.diff
@@ -0,0 +1,28 @@
+# DP: Fix up omp.h for multilibs.
+
+2008-06-09  Jakub Jelinek  <jakub@redhat.com>
+
+	* omp.h.in (omp_nest_lock_t): Fix up for Linux multilibs.
+
+2015-03-25  Matthias Klose  <doko@ubuntu.com>
+
+	* omp.h.in (omp_nest_lock_t): Limit the fix Linux.
+
+Index: b/src/libgomp/omp.h.in
+===================================================================
+--- a/src/libgomp/omp.h.in
++++ b/src/libgomp/omp.h.in
+@@ -40,8 +40,13 @@ typedef struct
+ 
+ typedef struct
+ {
++#if defined(__linux__)
++  unsigned char _x[8 + sizeof (void *)] 
++    __attribute__((__aligned__(sizeof (void *))));
++#else
+   unsigned char _x[@OMP_NEST_LOCK_SIZE@] 
+     __attribute__((__aligned__(@OMP_NEST_LOCK_ALIGN@)));
++#endif
+ } omp_nest_lock_t;
+ #endif
+ 
--- gcc-6-6.4.0.orig/debian/patches/libiberty-updates.diff
+++ gcc-6-6.4.0/debian/patches/libiberty-updates.diff
@@ -0,0 +1,2647 @@
+# DP: libiberty updates, taken from the trunk 20161108
+
+2016-11-30  David Malcolm  <dmalcolm@redhat.com>
+
+	PR c/78498
+	* strndup.c (strlen): Delete decl.
+	(strnlen): Add decl.
+	(strndup): Call strnlen rather than strlen.
+	* xstrndup.c (xstrndup): Likewise.
+
+2016-11-29  Nathan Sidwell  <nathan@acm.org>
+
+	* cp-demangle.c (d_print_comp_inner): Fix parameter indentation.
+
+2016-11-03  David Tolnay <dtolnay@gmail.com>
+	    Mark Wielaard  <mark@klomp.org>
+
+	* Makefile.in (CFILES): Add rust-demangle.c.
+	(REQUIRED_OFILES): Add rust-demangle.o.
+	* cplus-dem.c (libiberty_demanglers): Add rust_demangling case.
+	(cplus_demangle): Handle RUST_DEMANGLING.
+	(rust_demangle): New function.
+	* rust-demangle.c: New file.
+	* testsuite/Makefile.in (really-check): Add check-rust-demangle.
+	(check-rust-demangle): New rule.
+	* testsuite/rust-demangle-expected: New file.
+
+2016-11-15  Mark Wielaard  <mark@klomp.org>
+
+	* cp-demangle.c (d_expression_1): Make sure third expression
+	exists for ?: and fold expressions.
+	* testsuite/demangle-expected: Add examples of strings that could
+	crash the demangler because of missing expression.
+
+2016-11-14  Mark Wielaard  <mark@klomp.org>
+
+	* cplus-dem.c (demangle_signature): After 'H', template function,
+	no success and don't advance position if end of string reached.
+	(demangle_template): After 'z', template name, return zero on
+	premature end of string.
+	(gnu_special): Guard strchr against searching for zero characters.
+	(do_type): If member, only advance mangled string when 'F' found.
+	* testsuite/demangle-expected: Add examples of strings that could
+	crash the demangler by reading past end of input.
+
+2016-11-06  Mark Wielaard  <mark@klomp.org>
+
+	* configure.ac (ac_libiberty_warn_cflags): Add -Wshadow=local.
+	* configure: Regenerated.
+
+2016-11-07  Jason Merrill  <jason@redhat.com>
+
+	* cp-demangle.c (is_fnqual_component_type): New.
+	(d_encoding, d_print_comp_inner, d_print_mod_list): Use it.
+	(FNQUAL_COMPONENT_CASE): New.
+	(d_make_comp, has_return_type, d_print_comp_inner)
+	(d_print_function_type): Use it.
+	(next_is_type_qual): New.
+	(d_cv_qualifiers, d_print_mod): Handle noexcept and throw-spec.
+
+2016-11-02  Mark Wielaard  <mjw@redhat.com>
+
+	* cplus-dem.c (demangle_signature): Move fall through comment.
+	(demangle_fund_type): Add fall through comment between 'G' and 'I'.
+	* hashtab.c (iterative_hash): Add fall through comments.
+	* regex.c (regex_compile): Add Fall through comment after '+'/'?'.
+	(byte_re_match_2_internal): Add Fall through comment after jump_n.
+	Change "Note fall through" to "Fall through".
+	(common_op_match_null_string_p): Return false after set_number_at
+	instead of fall through.
+
+2016-11-01  Jason Merrill  <jason@redhat.com>
+
+	* cp-demangle.c (d_ctor_dtor_name): Handle inheriting constructor.
+
+2016-10-31  Mark Wielaard  <mjw@redhat.com>
+
+	* cplus-dem.c (ada_demangle): Initialize demangled to NULL and
+	XDELETEVEC demangled when unknown.
+
+2016-09-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	* pex-win32.c (argv_to_cmdline): Quote zero-length parameters.
+	* testsuite/test-pexecute.c (main): Insert check for zero-length parameters.
+
+2016-09-10  Mark Wielaard  <mjw@redhat.com>
+
+	* cp-demangle.c (d_substitution): Change struct demangle_component
+	variable name from c to dc.
+
+2016-08-12  Marek Polacek  <polacek@redhat.com>
+
+	PR c/7652
+	* cp-demangle.c (d_print_mod): Add FALLTHRU.
+
+2016-08-04  Marcel Böhme  <boehme.marcel@gmail.com>
+
+	PR c++/71696
+	* cplus-dem.c: Prevent infinite recursion when there is a cycle
+	in the referencing of remembered mangled types.
+	(work_stuff): New stack to keep track of the remembered mangled
+	types that are currently being processed.
+	(push_processed_type): New method to push currently processed
+	remembered type onto the stack.
+	(pop_processed_type): New method to pop currently processed
+	remembered type from the stack.
+	(work_stuff_copy_to_from): Copy values of new variables.
+	(delete_non_B_K_work_stuff): Free stack memory.
+	(demangle_args): Push/Pop currently processed remembered type.
+	(do_type): Do not demangle a cyclic reference and push/pop
+	referenced remembered type.
+
+2016-07-29  Aldy Hernandez  <aldyh@redhat.com>
+
+	* make-relative-prefix.c (make_relative_prefix_1): Fall back to
+	malloc if alloca argument is greater than MAX_ALLOCA_SIZE.
+
+2016-07-15  Jason Merrill  <jason@redhat.com>
+
+	* cp-demangle.c (cplus_demangle_operators): Add f[lrLR].
+	(d_expression_1): Handle them.
+	(d_maybe_print_fold_expression): New.
+	(d_print_comp_inner): Use it.
+	(d_index_template_argument): Handle negative index.
+
+	* cp-demangle.c (cplus_demangle_operators): Add sP and sZ.
+	(d_print_comp_inner): Handle them.
+	(d_template_args_1): Split out from d_template_args.
+	(d_args_length): New.
+
+2016-07-13  Marcel Böhme  <boehme.marcel@gmail.com>
+
+	PR c++/70926
+	* cplus-dem.c: Handle large values and overflow when demangling
+	length variables.
+	(demangle_template_value_parm): Read only until end of mangled string.
+	(do_hpacc_template_literal): Likewise.
+	(do_type): Handle overflow when demangling array indices.
+
+2016-06-12  Brooks Moses  <bmoses@google.com>
+
+	* cp-demangle.c (cplus_demangle_print_callback): Avoid zero-length
+	  VLAs.
+
+2016-05-31  Alan Modra  <amodra@gmail.com>
+
+	* xmemdup.c (xmemdup): Use xmalloc rather than xcalloc.
+
+2016-05-19  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/70498
+	* cp-demangle.c (d_expression_1): Formatting fix.
+
+2016-05-18  Artemiy Volkov  <artemiyv@acm.org>
+
+	* cplus-dem.c (enum type_kind_t): Add tk_rvalue_reference
+	constant.
+	(demangle_template_value_parm): Handle tk_rvalue_reference
+	type kind.
+	(do_type): Support 'O' type id (rvalue references).
+
+	* testsuite/demangle-expected: Add tests.
+
+Index: b/src/libiberty/argv.c
+===================================================================
+--- a/src/libiberty/argv.c
++++ b/src/libiberty/argv.c
+@@ -35,6 +35,13 @@ Boston, MA 02110-1301, USA.  */
+ #include <string.h>
+ #include <stdlib.h>
+ #include <stdio.h>
++#include <sys/types.h>
++#ifdef HAVE_UNISTD_H
++#include <unistd.h>
++#endif
++#if HAVE_SYS_STAT_H
++#include <sys/stat.h>
++#endif
+ 
+ #ifndef NULL
+ #define NULL 0
+@@ -387,6 +394,9 @@ expandargv (int *argcp, char ***argvp)
+       char **file_argv;
+       /* The number of options read from the response file, if any.  */
+       size_t file_argc;
++#ifdef S_ISDIR
++      struct stat sb;
++#endif
+       /* We are only interested in options of the form "@file".  */
+       filename = (*argvp)[i];
+       if (filename[0] != '@')
+@@ -397,6 +407,15 @@ expandargv (int *argcp, char ***argvp)
+ 	  fprintf (stderr, "%s: error: too many @-files encountered\n", (*argvp)[0]);
+ 	  xexit (1);
+ 	}
++#ifdef S_ISDIR
++      if (stat (filename+1, &sb) < 0)
++	continue;
++      if (S_ISDIR(sb.st_mode))
++	{
++	  fprintf (stderr, "%s: error: @-file refers to a directory\n", (*argvp)[0]);
++	  xexit (1);
++	}
++#endif
+       /* Read the contents of the file.  */
+       f = fopen (++filename, "r");
+       if (!f)
+Index: b/src/libiberty/ChangeLog
+===================================================================
+--- a/src/libiberty/ChangeLog
++++ b/src/libiberty/ChangeLog
+@@ -26,11 +26,126 @@
+ 	printing.
+ 	* testsuite/demangle-expected: Add lambda auto mangling cases. 
+ 
+-2016-08-22  Release Manager
++2016-12-06  DJ Delorie  <dj@redhat.com>
+ 
+-	* GCC 6.2.0 released.
++	* argv.c (expandargv): Check for directories passed as @-files.
+ 
+-2016-07-21  Jason Merrill  <jason@redhat.com>
++2016-11-30  David Malcolm  <dmalcolm@redhat.com>
++
++	PR c/78498
++	* strndup.c (strlen): Delete decl.
++	(strnlen): Add decl.
++	(strndup): Call strnlen rather than strlen.
++	* xstrndup.c (xstrndup): Likewise.
++
++2016-11-29  Nathan Sidwell  <nathan@acm.org>
++
++	* cp-demangle.c (d_print_comp_inner): Fix parameter indentation.
++
++2016-11-03  David Tolnay <dtolnay@gmail.com>
++	    Mark Wielaard  <mark@klomp.org>
++
++	* Makefile.in (CFILES): Add rust-demangle.c.
++	(REQUIRED_OFILES): Add rust-demangle.o.
++	* cplus-dem.c (libiberty_demanglers): Add rust_demangling case.
++	(cplus_demangle): Handle RUST_DEMANGLING.
++	(rust_demangle): New function.
++	* rust-demangle.c: New file.
++	* testsuite/Makefile.in (really-check): Add check-rust-demangle.
++	(check-rust-demangle): New rule.
++	* testsuite/rust-demangle-expected: New file.
++
++2016-11-15  Mark Wielaard  <mark@klomp.org>
++
++	* cp-demangle.c (d_expression_1): Make sure third expression
++	exists for ?: and fold expressions.
++	* testsuite/demangle-expected: Add examples of strings that could
++	crash the demangler because of missing expression.
++
++2016-11-14  Mark Wielaard  <mark@klomp.org>
++
++	* cplus-dem.c (demangle_signature): After 'H', template function,
++	no success and don't advance position if end of string reached.
++	(demangle_template): After 'z', template name, return zero on
++	premature end of string.
++	(gnu_special): Guard strchr against searching for zero characters.
++	(do_type): If member, only advance mangled string when 'F' found.
++	* testsuite/demangle-expected: Add examples of strings that could
++	crash the demangler by reading past end of input.
++
++2016-11-06  Mark Wielaard  <mark@klomp.org>
++
++	* configure.ac (ac_libiberty_warn_cflags): Add -Wshadow=local.
++	* configure: Regenerated.
++
++2016-11-07  Jason Merrill  <jason@redhat.com>
++
++	* cp-demangle.c (is_fnqual_component_type): New.
++	(d_encoding, d_print_comp_inner, d_print_mod_list): Use it.
++	(FNQUAL_COMPONENT_CASE): New.
++	(d_make_comp, has_return_type, d_print_comp_inner)
++	(d_print_function_type): Use it.
++	(next_is_type_qual): New.
++	(d_cv_qualifiers, d_print_mod): Handle noexcept and throw-spec.
++
++2016-11-02  Mark Wielaard  <mjw@redhat.com>
++
++	* cplus-dem.c (demangle_signature): Move fall through comment.
++	(demangle_fund_type): Add fall through comment between 'G' and 'I'.
++	* hashtab.c (iterative_hash): Add fall through comments.
++	* regex.c (regex_compile): Add Fall through comment after '+'/'?'.
++	(byte_re_match_2_internal): Add Fall through comment after jump_n.
++	Change "Note fall through" to "Fall through".
++	(common_op_match_null_string_p): Return false after set_number_at
++	instead of fall through.
++
++2016-11-01  Jason Merrill  <jason@redhat.com>
++
++	* cp-demangle.c (d_ctor_dtor_name): Handle inheriting constructor.
++
++2016-10-31  Mark Wielaard  <mjw@redhat.com>
++
++	* cplus-dem.c (ada_demangle): Initialize demangled to NULL and
++	XDELETEVEC demangled when unknown.
++
++2016-09-19  Andrew Stubbs  <ams@codesourcery.com>
++
++	* pex-win32.c (argv_to_cmdline): Quote zero-length parameters.
++	* testsuite/test-pexecute.c (main): Insert check for zero-length parameters.
++
++2016-09-10  Mark Wielaard  <mjw@redhat.com>
++
++	* cp-demangle.c (d_substitution): Change struct demangle_component
++	variable name from c to dc.
++
++2016-08-12  Marek Polacek  <polacek@redhat.com>
++
++	PR c/7652
++	* cp-demangle.c (d_print_mod): Add FALLTHRU.
++
++2016-08-04  Marcel Böhme  <boehme.marcel@gmail.com>
++
++	PR c++/71696
++	* cplus-dem.c: Prevent infinite recursion when there is a cycle
++	in the referencing of remembered mangled types.
++	(work_stuff): New stack to keep track of the remembered mangled
++	types that are currently being processed.
++	(push_processed_type): New method to push currently processed
++	remembered type onto the stack.
++	(pop_processed_type): New method to pop currently processed
++	remembered type from the stack.
++	(work_stuff_copy_to_from): Copy values of new variables.
++	(delete_non_B_K_work_stuff): Free stack memory.
++	(demangle_args): Push/Pop currently processed remembered type.
++	(do_type): Do not demangle a cyclic reference and push/pop
++	referenced remembered type.
++
++2016-07-29  Aldy Hernandez  <aldyh@redhat.com>
++
++	* make-relative-prefix.c (make_relative_prefix_1): Fall back to
++	malloc if alloca argument is greater than MAX_ALLOCA_SIZE.
++
++2016-07-15  Jason Merrill  <jason@redhat.com>
+ 
+ 	* cp-demangle.c (cplus_demangle_operators): Add f[lrLR].
+ 	(d_expression_1): Handle them.
+@@ -43,15 +158,40 @@
+ 	(d_template_args_1): Split out from d_template_args.
+ 	(d_args_length): New.
+ 
+-2016-05-19  Jakub Jelinek  <jakub@redhat.com>
++2016-07-13  Marcel Böhme  <boehme.marcel@gmail.com>
++
++	PR c++/70926
++	* cplus-dem.c: Handle large values and overflow when demangling
++	length variables.
++	(demangle_template_value_parm): Read only until end of mangled string.
++	(do_hpacc_template_literal): Likewise.
++	(do_type): Handle overflow when demangling array indices.
++
++2016-06-12  Brooks Moses  <bmoses@google.com>
++
++	* cp-demangle.c (cplus_demangle_print_callback): Avoid zero-length
++	  VLAs.
+ 
+-	Backported from mainline
+-	2016-05-19  Jakub Jelinek  <jakub@redhat.com>
++2016-05-31  Alan Modra  <amodra@gmail.com>
++
++	* xmemdup.c (xmemdup): Use xmalloc rather than xcalloc.
++
++2016-05-19  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR c++/70498
+ 	* cp-demangle.c (d_expression_1): Formatting fix.
+ 
+-	2016-05-02  Marcel Böhme  <boehme.marcel@gmail.com>
++2016-05-18  Artemiy Volkov  <artemiyv@acm.org>
++
++	* cplus-dem.c (enum type_kind_t): Add tk_rvalue_reference
++	constant.
++	(demangle_template_value_parm): Handle tk_rvalue_reference
++	type kind.
++	(do_type): Support 'O' type id (rvalue references).
++
++	* testsuite/demangle-expected: Add tests.
++
++2016-05-02  Marcel Böhme  <boehme.marcel@gmail.com>
+ 
+ 	PR c++/70498
+ 	* cp-demangle.c: Parse numbers as integer instead of long to avoid
+@@ -70,9 +210,9 @@
+ 	(d_unnamed_type): Likewise.
+ 	* testsuite/demangle-expected: Add regression test cases.
+ 
+-2016-04-27  Release Manager
++2016-04-30  Oleg Endo  <olegendo@gcc.gnu.org>
+ 
+-	* GCC 6.1.0 released.
++	* configure: Remove SH5 support.
+ 
+ 2016-04-08  Marcel Böhme  <boehme.marcel@gmail.com>
+ 
+@@ -145,8 +285,6 @@
+ 
+ 	PR other/61321
+ 	PR other/61233
+-	* demangle.h (enum demangle_component_type)
+-	<DEMANGLE_COMPONENT_CONVERSION>: New value.
+ 	* cp-demangle.c (d_demangle_callback, d_make_comp): Handle
+ 	DEMANGLE_COMPONENT_CONVERSION.
+ 	(is_ctor_dtor_or_conversion): Handle DEMANGLE_COMPONENT_CONVERSION
+@@ -733,11 +871,11 @@
+ 2013-05-31  Matt Burgess <matthew@linuxfromscratch.org>
+ 
+ 	PR other/56780
+-	* libiberty/configure.ac: Move test for --enable-install-libiberty
++	* configure.ac: Move test for --enable-install-libiberty
+ 	outside of the 'with_target_subdir' test so that it actually gets
+ 	run.  Add output messages to show the test result.
+-	* libiberty/configure: Regenerate.
+-	* libiberty/Makefile.in (install_to_libdir): Place the
++	* configure: Regenerate.
++	* Makefile.in (install_to_libdir): Place the
+ 	installation of the libiberty library in the same guard as that
+ 	used for the headers to prevent it being installed unless
+ 	requested via --enable-install-libiberty.
+@@ -1537,7 +1675,6 @@
+ 	Daniel Jacobowitz  <dan@codesourcery.com>
+ 	Pedro Alves  <pedro@codesourcery.com>
+ 
+-	libiberty/
+ 	* argv.c (consume_whitespace): New function.
+ 	(only_whitespace): New function.
+ 	(buildargv): Always use ISSPACE by calling consume_whitespace.
+@@ -1738,8 +1875,8 @@
+ 
+ 2009-04-07  Arnaud Patard <apatard@mandriva.com>
+ 
+-	* libiberty/configure.ac: Fix Linux/MIPS matching rule.
+-	* libiberty/configure: Regenerate.
++	* configure.ac: Fix Linux/MIPS matching rule.
++	* configure: Regenerate.
+ 
+ 2009-03-27  Ian Lance Taylor  <iant@google.com>
+ 
+@@ -1902,8 +2039,8 @@
+ 
+ 2008-04-21  Aurelien Jarno  <aurelien@aurel32.net>
+ 
+-	* libiberty/configure.ac: use -fPIC on Linux/MIPS hosts.
+-	* libiberty/configure: Regenerate.
++	* configure.ac: use -fPIC on Linux/MIPS hosts.
++	* configure: Regenerate.
+ 
+ 2008-04-18  Kris Van Hees <kris.van.hees@oracle.com>
+ 
+@@ -3681,7 +3818,7 @@
+ 
+ 2003-12-15  Brendan Kehoe  <brendan@zen.org>
+ 
+-	* libiberty/Makefile.in (floatformat.o): Add dependency on
++	* Makefile.in (floatformat.o): Add dependency on
+ 	config.h to accompany change of 2003-12-03.
+ 
+ 2003-12-15  Ian Lance Taylor  <ian@wasabisystems.com>
+@@ -4377,7 +4514,7 @@
+ 
+ 2002-10-06  Andreas Jaeger  <aj@suse.de>
+ 
+-	* libiberty/cplus-dem.c (ada_demangle): Get rid of unneeded
++	* cplus-dem.c (ada_demangle): Get rid of unneeded
+ 	variable and of strict-aliasing warning.
+ 	(grow_vect): Use char as first parameter.
+ 
+@@ -4645,7 +4782,7 @@
+ 
+ 2002-01-31  Adam Megacz  <adam@xwt.org>
+ 
+-	* gcc/libiberty/configure.in: Treat mingw the same as cywin
++	* configure.in: Treat mingw the same as cywin
+ 	wrt HAVE_SYS_ERRLIST.
+ 
+ 2002-01-30  Phil Edwards  <pme@gcc.gnu.org>
+@@ -5153,8 +5290,8 @@ Tue Aug 21 12:35:04 2001  Christopher Fa
+ 2001-03-10  Neil Booth  <neil@daikokuya.demon.co.uk>
+ 	    John David Anglin  <dave@hiauly1.hia.nrc.ca>
+ 
+-	* libiberty/lbasename.c: New file.
+-	* libiberty/Makefile.in: Update for lbasename.
++	* lbasename.c: New file.
++	* Makefile.in: Update for lbasename.
+ 
+ 2001-03-06  Zack Weinberg  <zackw@stanford.edu>
+ 
+@@ -5527,13 +5664,13 @@ Tue Aug 21 12:35:04 2001  Christopher Fa
+ 
+ 2000-08-24  Greg McGary  <greg@mcgary.org>
+ 
+-	* libiberty/random.c (end_ptr): Revert previous change.
++	* random.c (end_ptr): Revert previous change.
+ 
+ 2000-08-24  Greg McGary  <greg@mcgary.org>
+ 
+-	* libiberty/cplus-dem.c (cplus_demangle_opname, cplus_mangle_opname,
++	* cplus-dem.c (cplus_demangle_opname, cplus_mangle_opname,
+ 	demangle_expression, demangle_function_name): Use ARRAY_SIZE.
+-	* libiberty/random.c (end_ptr): Likewise.
++	* random.c (end_ptr): Likewise.
+ 
+ 2000-08-23  Alex Samuel  <samuel@codesourcery.com>
+ 
+Index: b/src/libiberty/configure
+===================================================================
+--- a/src/libiberty/configure
++++ b/src/libiberty/configure
+@@ -4398,7 +4398,8 @@ ac_compiler_gnu=$ac_cv_c_compiler_gnu
+ ac_libiberty_warn_cflags=
+ save_CFLAGS="$CFLAGS"
+ for real_option in -W -Wall -Wwrite-strings -Wc++-compat \
+-			  -Wstrict-prototypes; do
++			  -Wstrict-prototypes \
++			  -Wshadow=local; do
+   # Do the check with the no- prefix removed since gcc silently
+   # accepts any -Wno-* option on purpose
+   case $real_option in
+@@ -5145,8 +5146,7 @@ case "${host}" in
+ 	PICFLAG=-fpic
+ 	;;
+     # FIXME: Simplify to sh*-*-netbsd*?
+-    sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
+-      sh64-*-netbsd* | sh64l*-*-netbsd*)
++    sh-*-netbsdelf* | shl*-*-netbsdelf*)
+ 	PICFLAG=-fpic
+ 	;;
+     # Default to -fPIC unless specified otherwise.
+Index: b/src/libiberty/configure.ac
+===================================================================
+--- a/src/libiberty/configure.ac
++++ b/src/libiberty/configure.ac
+@@ -160,7 +160,8 @@ AC_SYS_LARGEFILE
+ AC_PROG_CPP_WERROR
+ 
+ ACX_PROG_CC_WARNING_OPTS([-W -Wall -Wwrite-strings -Wc++-compat \
+-			  -Wstrict-prototypes], [ac_libiberty_warn_cflags])
++			  -Wstrict-prototypes \
++			  -Wshadow=local], [ac_libiberty_warn_cflags])
+ ACX_PROG_CC_WARNING_ALMOST_PEDANTIC([], [ac_libiberty_warn_cflags])
+ 
+ AC_PROG_CC_C_O
+Index: b/src/libiberty/cp-demangle.c
+===================================================================
+--- a/src/libiberty/cp-demangle.c
++++ b/src/libiberty/cp-demangle.c
+@@ -439,6 +439,8 @@ static struct demangle_component *d_oper
+ 
+ static struct demangle_component *d_special_name (struct d_info *);
+ 
++static struct demangle_component *d_parmlist (struct d_info *);
++
+ static int d_call_offset (struct d_info *, int);
+ 
+ static struct demangle_component *d_ctor_dtor_name (struct d_info *);
+@@ -562,6 +564,32 @@ static int d_demangle_callback (const ch
+                                 demangle_callbackref, void *);
+ static char *d_demangle (const char *, int, size_t *);
+ 
++/* True iff TYPE is a demangling component representing a
++   function-type-qualifier.  */
++
++static int
++is_fnqual_component_type (enum demangle_component_type type)
++{
++  return (type == DEMANGLE_COMPONENT_RESTRICT_THIS
++	  || type == DEMANGLE_COMPONENT_VOLATILE_THIS
++	  || type == DEMANGLE_COMPONENT_CONST_THIS
++	  || type == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS
++	  || type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
++	  || type == DEMANGLE_COMPONENT_NOEXCEPT
++	  || type == DEMANGLE_COMPONENT_THROW_SPEC
++	  || type == DEMANGLE_COMPONENT_REFERENCE_THIS);
++}
++
++#define FNQUAL_COMPONENT_CASE				\
++    case DEMANGLE_COMPONENT_RESTRICT_THIS:		\
++    case DEMANGLE_COMPONENT_VOLATILE_THIS:		\
++    case DEMANGLE_COMPONENT_CONST_THIS:			\
++    case DEMANGLE_COMPONENT_REFERENCE_THIS:		\
++    case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:	\
++    case DEMANGLE_COMPONENT_TRANSACTION_SAFE:		\
++    case DEMANGLE_COMPONENT_NOEXCEPT:			\
++    case DEMANGLE_COMPONENT_THROW_SPEC
++
+ #ifdef CP_DEMANGLE_DEBUG
+ 
+ static void
+@@ -987,14 +1015,9 @@ d_make_comp (struct d_info *di, enum dem
+     case DEMANGLE_COMPONENT_RESTRICT:
+     case DEMANGLE_COMPONENT_VOLATILE:
+     case DEMANGLE_COMPONENT_CONST:
+-    case DEMANGLE_COMPONENT_RESTRICT_THIS:
+-    case DEMANGLE_COMPONENT_VOLATILE_THIS:
+-    case DEMANGLE_COMPONENT_CONST_THIS:
+-    case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
+-    case DEMANGLE_COMPONENT_REFERENCE_THIS:
+-    case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+     case DEMANGLE_COMPONENT_ARGLIST:
+     case DEMANGLE_COMPONENT_TEMPLATE_ARGLIST:
++    FNQUAL_COMPONENT_CASE:
+       break;
+ 
+       /* Other types should not be seen here.  */
+@@ -1228,12 +1251,7 @@ has_return_type (struct demangle_compone
+       return 0;
+     case DEMANGLE_COMPONENT_TEMPLATE:
+       return ! is_ctor_dtor_or_conversion (d_left (dc));
+-    case DEMANGLE_COMPONENT_RESTRICT_THIS:
+-    case DEMANGLE_COMPONENT_VOLATILE_THIS:
+-    case DEMANGLE_COMPONENT_CONST_THIS:
+-    case DEMANGLE_COMPONENT_REFERENCE_THIS:
+-    case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+-    case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
++    FNQUAL_COMPONENT_CASE:
+       return has_return_type (d_left (dc));
+     }
+ }
+@@ -1290,13 +1308,12 @@ d_encoding (struct d_info *di, int top_l
+ 	  while (dc->type == DEMANGLE_COMPONENT_RESTRICT_THIS
+ 		 || dc->type == DEMANGLE_COMPONENT_VOLATILE_THIS
+ 		 || dc->type == DEMANGLE_COMPONENT_CONST_THIS
+-		 || dc->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
+ 		 || dc->type == DEMANGLE_COMPONENT_REFERENCE_THIS
+ 		 || dc->type == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS)
+ 	    dc = d_left (dc);
+ 
+ 	  /* If the top level is a DEMANGLE_COMPONENT_LOCAL_NAME, then
+-	     there may be CV-qualifiers on its right argument which
++	     there may be function-qualifiers on its right argument which
+ 	     really apply here; this happens when parsing a class
+ 	     which is local to a function.  */
+ 	  if (dc->type == DEMANGLE_COMPONENT_LOCAL_NAME)
+@@ -1304,12 +1321,7 @@ d_encoding (struct d_info *di, int top_l
+ 	      struct demangle_component *dcr;
+ 
+ 	      dcr = d_right (dc);
+-	      while (dcr->type == DEMANGLE_COMPONENT_RESTRICT_THIS
+-		     || dcr->type == DEMANGLE_COMPONENT_VOLATILE_THIS
+-		     || dcr->type == DEMANGLE_COMPONENT_CONST_THIS
+-		     || dcr->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
+-		     || dcr->type == DEMANGLE_COMPONENT_REFERENCE_THIS
+-		     || dcr->type == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS)
++	      while (is_fnqual_component_type (dcr->type))
+ 		dcr = d_left (dcr);
+ 	      dc->u.s_binary.right = dcr;
+ 	    }
+@@ -2171,6 +2183,13 @@ d_ctor_dtor_name (struct d_info *di)
+     case 'C':
+       {
+ 	enum gnu_v3_ctor_kinds kind;
++	int inheriting = 0;
++
++	if (d_peek_next_char (di) == 'I')
++	  {
++	    inheriting = 1;
++	    d_advance (di, 1);
++	  }
+ 
+ 	switch (d_peek_next_char (di))
+ 	  {
+@@ -2192,7 +2211,12 @@ d_ctor_dtor_name (struct d_info *di)
+ 	  default:
+ 	    return NULL;
+ 	  }
++
+ 	d_advance (di, 2);
++
++	if (inheriting)
++	  cplus_demangle_type (di);
++
+ 	return d_make_ctor (di, kind, di->last_name);
+       }
+ 
+@@ -2230,6 +2254,24 @@ d_ctor_dtor_name (struct d_info *di)
+     }
+ }
+ 
++/* True iff we're looking at an order-insensitive type-qualifier, including
++   function-type-qualifiers.  */
++
++static int
++next_is_type_qual (struct d_info *di)
++{
++  char peek = d_peek_char (di);
++  if (peek == 'r' || peek == 'V' || peek == 'K')
++    return 1;
++  if (peek == 'D')
++    {
++      peek = d_peek_next_char (di);
++      if (peek == 'x' || peek == 'o' || peek == 'O' || peek == 'w')
++	return 1;
++    }
++  return 0;
++}
++
+ /* <type> ::= <builtin-type>
+           ::= <function-type>
+           ::= <class-enum-type>
+@@ -2315,9 +2357,7 @@ cplus_demangle_type (struct d_info *di)
+      __vector, and it treats it as order-sensitive when mangling
+      names.  */
+ 
+-  peek = d_peek_char (di);
+-  if (peek == 'r' || peek == 'V' || peek == 'K'
+-      || (peek == 'D' && d_peek_next_char (di) == 'x'))
++  if (next_is_type_qual (di))
+     {
+       struct demangle_component **pret;
+ 
+@@ -2352,6 +2392,7 @@ cplus_demangle_type (struct d_info *di)
+ 
+   can_subst = 1;
+ 
++  peek = d_peek_char (di);
+   switch (peek)
+     {
+     case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'g':
+@@ -2643,10 +2684,10 @@ d_cv_qualifiers (struct d_info *di,
+ 
+   pstart = pret;
+   peek = d_peek_char (di);
+-  while (peek == 'r' || peek == 'V' || peek == 'K'
+-	 || (peek == 'D' && d_peek_next_char (di) == 'x'))
++  while (next_is_type_qual (di))
+     {
+       enum demangle_component_type t;
++      struct demangle_component *right = NULL;
+ 
+       d_advance (di, 1);
+       if (peek == 'r')
+@@ -2672,12 +2713,41 @@ d_cv_qualifiers (struct d_info *di,
+ 	}
+       else
+ 	{
+-	  t = DEMANGLE_COMPONENT_TRANSACTION_SAFE;
+-	  di->expansion += sizeof "transaction_safe";
+-	  d_advance (di, 1);
++	  peek = d_next_char (di);
++	  if (peek == 'x')
++	    {
++	      t = DEMANGLE_COMPONENT_TRANSACTION_SAFE;
++	      di->expansion += sizeof "transaction_safe";
++	    }
++	  else if (peek == 'o'
++		   || peek == 'O')
++	    {
++	      t = DEMANGLE_COMPONENT_NOEXCEPT;
++	      di->expansion += sizeof "noexcept";
++	      if (peek == 'O')
++		{
++		  right = d_expression (di);
++		  if (right == NULL)
++		    return NULL;
++		  if (! d_check_char (di, 'E'))
++		    return NULL;
++		}
++	    }
++	  else if (peek == 'w')
++	    {
++	      t = DEMANGLE_COMPONENT_THROW_SPEC;
++	      di->expansion += sizeof "throw";
++	      right = d_parmlist (di);
++	      if (right == NULL)
++		return NULL;
++	      if (! d_check_char (di, 'E'))
++		return NULL;
++	    }
++	  else
++	    return NULL;
+ 	}
+ 
+-      *pret = d_make_comp (di, t, NULL, NULL);
++      *pret = d_make_comp (di, t, NULL, right);
+       if (*pret == NULL)
+ 	return NULL;
+       pret = &d_left (*pret);
+@@ -3352,6 +3422,8 @@ d_expression_1 (struct d_info *di)
+ 		first = d_expression_1 (di);
+ 		second = d_expression_1 (di);
+ 		third = d_expression_1 (di);
++		if (third == NULL)
++		  return NULL;
+ 	      }
+ 	    else if (code[0] == 'f')
+ 	      {
+@@ -3359,6 +3431,8 @@ d_expression_1 (struct d_info *di)
+ 		first = d_operator_name (di);
+ 		second = d_expression_1 (di);
+ 		third = d_expression_1 (di);
++		if (third == NULL)
++		  return NULL;
+ 	      }
+ 	    else if (code[0] == 'n')
+ 	      {
+@@ -3776,7 +3850,7 @@ d_substitution (struct d_info *di, int p
+ 	    {
+ 	      const char *s;
+ 	      int len;
+-	      struct demangle_component *c;
++	      struct demangle_component *dc;
+ 
+ 	      if (p->set_last_name != NULL)
+ 		di->last_name = d_make_sub (di, p->set_last_name,
+@@ -3792,15 +3866,15 @@ d_substitution (struct d_info *di, int p
+ 		  len = p->simple_len;
+ 		}
+ 	      di->expansion += len;
+-	      c = d_make_sub (di, s, len);
++	      dc = d_make_sub (di, s, len);
+ 	      if (d_peek_char (di) == 'B')
+ 		{
+ 		  /* If there are ABI tags on the abbreviation, it becomes
+ 		     a substitution candidate.  */
+-		  c = d_abi_tags (di, c);
+-		  d_add_substitution (di, c);
++		  dc = d_abi_tags (di, dc);
++		  d_add_substitution (di, dc);
+ 		}
+-	      return c;
++	      return dc;
+ 	    }
+ 	}
+ 
+@@ -3968,6 +4042,8 @@ d_count_templates_scopes (int *num_templ
+     case DEMANGLE_COMPONENT_REFERENCE_THIS:
+     case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+     case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
++    case DEMANGLE_COMPONENT_NOEXCEPT:
++    case DEMANGLE_COMPONENT_THROW_SPEC:
+     case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL:
+     case DEMANGLE_COMPONENT_POINTER:
+     case DEMANGLE_COMPONENT_COMPLEX:
+@@ -4163,8 +4239,12 @@ cplus_demangle_print_callback (int optio
+ 
+   {
+ #ifdef CP_DYNAMIC_ARRAYS
+-    __extension__ struct d_saved_scope scopes[dpi.num_saved_scopes];
+-    __extension__ struct d_print_template temps[dpi.num_copy_templates];
++    /* Avoid zero-length VLAs, which are prohibited by the C99 standard
++       and flagged as errors by Address Sanitizer.  */
++    __extension__ struct d_saved_scope scopes[(dpi.num_saved_scopes > 0)
++                                              ? dpi.num_saved_scopes : 1];
++    __extension__ struct d_print_template temps[(dpi.num_copy_templates > 0)
++                                                ? dpi.num_copy_templates : 1];
+ 
+     dpi.saved_scopes = scopes;
+     dpi.copy_templates = temps;
+@@ -4492,7 +4572,7 @@ d_maybe_print_fold_expression (struct d_
+ 
+ static void
+ d_print_comp_inner (struct d_print_info *dpi, int options,
+-		  const struct demangle_component *dc)
++		    const struct demangle_component *dc)
+ {
+   /* Magic variable to let reference smashing skip over the next modifier
+      without needing to modify *dc.  */
+@@ -4579,12 +4659,7 @@ d_print_comp_inner (struct d_print_info
+ 	    adpm[i].templates = dpi->templates;
+ 	    ++i;
+ 
+-	    if (typed_name->type != DEMANGLE_COMPONENT_RESTRICT_THIS
+-		&& typed_name->type != DEMANGLE_COMPONENT_VOLATILE_THIS
+-		&& typed_name->type != DEMANGLE_COMPONENT_CONST_THIS
+-		&& typed_name->type != DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS
+-		&& typed_name->type != DEMANGLE_COMPONENT_TRANSACTION_SAFE
+-		&& typed_name->type != DEMANGLE_COMPONENT_REFERENCE_THIS)
++	    if (!is_fnqual_component_type (typed_name->type))
+ 	      break;
+ 
+ 	    typed_name = d_left (typed_name);
+@@ -4621,13 +4696,7 @@ d_print_comp_inner (struct d_print_info
+ 		d_print_error (dpi);
+ 		return;
+ 	      }
+-	    while (local_name->type == DEMANGLE_COMPONENT_RESTRICT_THIS
+-		   || local_name->type == DEMANGLE_COMPONENT_VOLATILE_THIS
+-		   || local_name->type == DEMANGLE_COMPONENT_CONST_THIS
+-		   || local_name->type == DEMANGLE_COMPONENT_REFERENCE_THIS
+-		   || local_name->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
+-		   || (local_name->type
+-		       == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS))
++	    while (is_fnqual_component_type (local_name->type))
+ 	      {
+ 		if (i >= sizeof adpm / sizeof adpm[0])
+ 		  {
+@@ -4961,16 +5030,11 @@ d_print_comp_inner (struct d_print_info
+       }
+       /* Fall through.  */
+ 
+-    case DEMANGLE_COMPONENT_RESTRICT_THIS:
+-    case DEMANGLE_COMPONENT_VOLATILE_THIS:
+-    case DEMANGLE_COMPONENT_CONST_THIS:
+-    case DEMANGLE_COMPONENT_REFERENCE_THIS:
+-    case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+     case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL:
+     case DEMANGLE_COMPONENT_POINTER:
+     case DEMANGLE_COMPONENT_COMPLEX:
+     case DEMANGLE_COMPONENT_IMAGINARY:
+-    case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
++    FNQUAL_COMPONENT_CASE:
+     modifier:
+       {
+ 	/* We keep a list of modifiers on the stack.  */
+@@ -5679,13 +5743,7 @@ d_print_mod_list (struct d_print_info *d
+ 
+   if (mods->printed
+       || (! suffix
+-	  && (mods->mod->type == DEMANGLE_COMPONENT_RESTRICT_THIS
+-	      || mods->mod->type == DEMANGLE_COMPONENT_VOLATILE_THIS
+-	      || mods->mod->type == DEMANGLE_COMPONENT_CONST_THIS
+-	      || mods->mod->type == DEMANGLE_COMPONENT_REFERENCE_THIS
+-	      || mods->mod->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
+-	      || (mods->mod->type
+-		  == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS))))
++	  && (is_fnqual_component_type (mods->mod->type))))
+     {
+       d_print_mod_list (dpi, options, mods->next, suffix);
+       return;
+@@ -5738,12 +5796,7 @@ d_print_mod_list (struct d_print_info *d
+ 	  dc = dc->u.s_unary_num.sub;
+ 	}
+ 
+-      while (dc->type == DEMANGLE_COMPONENT_RESTRICT_THIS
+-	     || dc->type == DEMANGLE_COMPONENT_VOLATILE_THIS
+-	     || dc->type == DEMANGLE_COMPONENT_CONST_THIS
+-	     || dc->type == DEMANGLE_COMPONENT_REFERENCE_THIS
+-	     || dc->type == DEMANGLE_COMPONENT_TRANSACTION_SAFE
+-	     || dc->type == DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS)
++      while (is_fnqual_component_type (dc->type))
+ 	dc = d_left (dc);
+ 
+       d_print_comp (dpi, options, dc);
+@@ -5782,6 +5835,24 @@ d_print_mod (struct d_print_info *dpi, i
+     case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
+       d_append_string (dpi, " transaction_safe");
+       return;
++    case DEMANGLE_COMPONENT_NOEXCEPT:
++      d_append_string (dpi, " noexcept");
++      if (d_right (mod))
++	{
++	  d_append_char (dpi, '(');
++	  d_print_comp (dpi, options, d_right (mod));
++	  d_append_char (dpi, ')');
++	}
++      return;
++    case DEMANGLE_COMPONENT_THROW_SPEC:
++      d_append_string (dpi, " throw");
++      if (d_right (mod))
++	{
++	  d_append_char (dpi, '(');
++	  d_print_comp (dpi, options, d_right (mod));
++	  d_append_char (dpi, ')');
++	}
++      return;
+     case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL:
+       d_append_char (dpi, ' ');
+       d_print_comp (dpi, options, d_right (mod));
+@@ -5794,11 +5865,13 @@ d_print_mod (struct d_print_info *dpi, i
+     case DEMANGLE_COMPONENT_REFERENCE_THIS:
+       /* For the ref-qualifier, put a space before the &.  */
+       d_append_char (dpi, ' ');
++      /* FALLTHRU */
+     case DEMANGLE_COMPONENT_REFERENCE:
+       d_append_char (dpi, '&');
+       return;
+     case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+       d_append_char (dpi, ' ');
++      /* FALLTHRU */
+     case DEMANGLE_COMPONENT_RVALUE_REFERENCE:
+       d_append_string (dpi, "&&");
+       return;
+@@ -5867,12 +5940,7 @@ d_print_function_type (struct d_print_in
+ 	  need_space = 1;
+ 	  need_paren = 1;
+ 	  break;
+-	case DEMANGLE_COMPONENT_RESTRICT_THIS:
+-	case DEMANGLE_COMPONENT_VOLATILE_THIS:
+-	case DEMANGLE_COMPONENT_CONST_THIS:
+-	case DEMANGLE_COMPONENT_REFERENCE_THIS:
+-	case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+-	case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
++	FNQUAL_COMPONENT_CASE:
+ 	  break;
+ 	default:
+ 	  break;
+@@ -6414,7 +6482,6 @@ is_ctor_or_dtor (const char *mangled,
+ 	  case DEMANGLE_COMPONENT_CONST_THIS:
+ 	  case DEMANGLE_COMPONENT_REFERENCE_THIS:
+ 	  case DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS:
+-	  case DEMANGLE_COMPONENT_TRANSACTION_SAFE:
+ 	  default:
+ 	    dc = NULL;
+ 	    break;
+Index: b/src/libiberty/cplus-dem.c
+===================================================================
+--- a/src/libiberty/cplus-dem.c
++++ b/src/libiberty/cplus-dem.c
+@@ -144,6 +144,9 @@ struct work_stuff
+   string* previous_argument; /* The last function argument demangled.  */
+   int nrepeats;         /* The number of times to repeat the previous
+ 			   argument.  */
++  int *proctypevec;     /* Indices of currently processed remembered typevecs.  */
++  int proctypevec_size;
++  int nproctypes;
+ };
+ 
+ #define PRINT_ANSI_QUALIFIERS (work -> options & DMGL_ANSI)
+@@ -244,6 +247,7 @@ typedef enum type_kind_t
+   tk_none,
+   tk_pointer,
+   tk_reference,
++  tk_rvalue_reference,
+   tk_integral,
+   tk_bool,
+   tk_char,
+@@ -319,6 +323,12 @@ const struct demangler_engine libiberty_
+   }
+   ,
+   {
++    RUST_DEMANGLING_STYLE_STRING,
++    rust_demangling,
++    "Rust style demangling"
++  }
++  ,
++  {
+     NULL, unknown_demangling, NULL
+   }
+ };
+@@ -435,6 +445,10 @@ iterate_demangle_function (struct work_s
+ 
+ static void remember_type (struct work_stuff *, const char *, int);
+ 
++static void push_processed_type (struct work_stuff *, int);
++
++static void pop_processed_type (struct work_stuff *);
++
+ static void remember_Btype (struct work_stuff *, const char *, int, int);
+ 
+ static int register_Btype (struct work_stuff *);
+@@ -866,10 +880,26 @@ cplus_demangle (const char *mangled, int
+     work->options |= (int) current_demangling_style & DMGL_STYLE_MASK;
+ 
+   /* The V3 ABI demangling is implemented elsewhere.  */
+-  if (GNU_V3_DEMANGLING || AUTO_DEMANGLING)
++  if (GNU_V3_DEMANGLING || RUST_DEMANGLING || AUTO_DEMANGLING)
+     {
+       ret = cplus_demangle_v3 (mangled, work->options);
+-      if (ret || GNU_V3_DEMANGLING)
++      if (GNU_V3_DEMANGLING)
++	return ret;
++
++      if (ret)
++	{
++	  /* Rust symbols are GNU_V3 mangled plus some extra subtitutions.
++	     The subtitutions are always smaller, so do in place changes.  */
++	  if (rust_is_mangled (ret))
++	    rust_demangle_sym (ret);
++	  else if (RUST_DEMANGLING)
++	    {
++	      free (ret);
++	      ret = NULL;
++	    }
++	}
++
++      if (ret || RUST_DEMANGLING)
+ 	return ret;
+     }
+ 
+@@ -895,6 +925,27 @@ cplus_demangle (const char *mangled, int
+   return (ret);
+ }
+ 
++char *
++rust_demangle (const char *mangled, int options)
++{
++  /* Rust symbols are GNU_V3 mangled plus some extra subtitutions.  */
++  char *ret = cplus_demangle_v3 (mangled, options);
++
++  /* The Rust subtitutions are always smaller, so do in place changes.  */
++  if (ret != NULL)
++    {
++      if (rust_is_mangled (ret))
++	rust_demangle_sym (ret);
++      else
++	{
++	  free (ret);
++	  ret = NULL;
++	}
++    }
++
++  return ret;
++}
++
+ /* Demangle ada names.  The encoding is documented in gcc/ada/exp_dbug.ads.  */
+ 
+ char *
+@@ -903,7 +954,7 @@ ada_demangle (const char *mangled, int o
+   int len0;
+   const char* p;
+   char *d;
+-  char *demangled;
++  char *demangled = NULL;
+   
+   /* Discard leading _ada_, which is used for library level subprograms.  */
+   if (strncmp (mangled, "_ada_", 5) == 0)
+@@ -1148,6 +1199,7 @@ ada_demangle (const char *mangled, int o
+   return demangled;
+ 
+  unknown:
++  XDELETEVEC (demangled);
+   len0 = strlen (mangled);
+   demangled = XNEWVEC (char, len0 + 3);
+ 
+@@ -1301,6 +1353,10 @@ work_stuff_copy_to_from (struct work_stu
+       memcpy (to->btypevec[i], from->btypevec[i], len);
+     }
+ 
++  if (from->proctypevec)
++    to->proctypevec =
++      XDUPVEC (int, from->proctypevec, from->proctypevec_size);
++
+   if (from->ntmpl_args)
+     to->tmpl_argvec = XNEWVEC (char *, from->ntmpl_args);
+ 
+@@ -1329,11 +1385,17 @@ delete_non_B_K_work_stuff (struct work_s
+   /* Discard the remembered types, if any.  */
+ 
+   forget_types (work);
+-  if (work -> typevec != NULL)
++  if (work->typevec != NULL)
++    {
++      free ((char *) work->typevec);
++      work->typevec = NULL;
++      work->typevec_size = 0;
++    }
++  if (work->proctypevec != NULL)
+     {
+-      free ((char *) work -> typevec);
+-      work -> typevec = NULL;
+-      work -> typevec_size = 0;
++      free (work->proctypevec);
++      work->proctypevec = NULL;
++      work->proctypevec_size = 0;
+     }
+   if (work->tmpl_argvec)
+     {
+@@ -1635,12 +1697,13 @@ demangle_signature (struct work_stuff *w
+ 					   0);
+ 	      if (!(work->constructor & 1))
+ 		expect_return_type = 1;
+-	      (*mangled)++;
++	      if (!**mangled)
++		success = 0;
++	      else
++	        (*mangled)++;
+ 	      break;
+ 	    }
+-	  else
+-	    /* fall through */
+-	    {;}
++	  /* fall through */
+ 
+ 	default:
+ 	  if (AUTO_DEMANGLING || GNU_DEMANGLING)
+@@ -2042,7 +2105,8 @@ demangle_template_value_parm (struct wor
+     }
+   else if (tk == tk_real)
+     success = demangle_real_value (work, mangled, s);
+-  else if (tk == tk_pointer || tk == tk_reference)
++  else if (tk == tk_pointer || tk == tk_reference
++	   || tk == tk_rvalue_reference)
+     {
+       if (**mangled == 'Q')
+ 	success = demangle_qualified (work, mangled, s,
+@@ -2051,7 +2115,8 @@ demangle_template_value_parm (struct wor
+       else
+ 	{
+ 	  int symbol_len  = consume_count (mangled);
+-	  if (symbol_len == -1)
++	  if (symbol_len == -1
++	      || symbol_len > (long) strlen (*mangled))
+ 	    return -1;
+ 	  if (symbol_len == 0)
+ 	    string_appendn (s, "0", 1);
+@@ -2114,6 +2179,8 @@ demangle_template (struct work_stuff *wo
+ 	{
+ 	  int idx;
+ 	  (*mangled)++;
++	  if (**mangled == '\0')
++	    return (0);
+ 	  (*mangled)++;
+ 
+ 	  idx = consume_count_with_underscores (mangled);
+@@ -2958,7 +3025,7 @@ gnu_special (struct work_stuff *work, co
+   int success = 1;
+   const char *p;
+ 
+-  if ((*mangled)[0] == '_'
++  if ((*mangled)[0] == '_' && (*mangled)[1] != '\0'
+       && strchr (cplus_markers, (*mangled)[1]) != NULL
+       && (*mangled)[2] == '_')
+     {
+@@ -2972,7 +3039,7 @@ gnu_special (struct work_stuff *work, co
+ 		&& (*mangled)[3] == 't'
+ 		&& (*mangled)[4] == '_')
+ 	       || ((*mangled)[1] == 'v'
+-		   && (*mangled)[2] == 't'
++		   && (*mangled)[2] == 't' && (*mangled)[3] != '\0'
+ 		   && strchr (cplus_markers, (*mangled)[3]) != NULL)))
+     {
+       /* Found a GNU style virtual table, get past "_vt<CPLUS_MARKER>"
+@@ -3552,6 +3619,8 @@ static int
+ do_type (struct work_stuff *work, const char **mangled, string *result)
+ {
+   int n;
++  int i;
++  int is_proctypevec;
+   int done;
+   int success;
+   string decl;
+@@ -3564,6 +3633,7 @@ do_type (struct work_stuff *work, const
+ 
+   done = 0;
+   success = 1;
++  is_proctypevec = 0;
+   while (success && !done)
+     {
+       int member;
+@@ -3588,6 +3658,14 @@ do_type (struct work_stuff *work, const
+ 	    tk = tk_reference;
+ 	  break;
+ 
++	  /* An rvalue reference type */
++	case 'O':
++	  (*mangled)++;
++	  string_prepend (&decl, "&&");
++	  if (tk == tk_none)
++	    tk = tk_rvalue_reference;
++	  break;
++
+ 	  /* An array */
+ 	case 'A':
+ 	  {
+@@ -3611,13 +3689,20 @@ do_type (struct work_stuff *work, const
+ 	/* A back reference to a previously seen type */
+ 	case 'T':
+ 	  (*mangled)++;
+-	  if (!get_count (mangled, &n) || n >= work -> ntypes)
++	  if (!get_count (mangled, &n) || n < 0 || n >= work -> ntypes)
+ 	    {
+ 	      success = 0;
+ 	    }
+ 	  else
+-	    {
+-	      remembered_type = work -> typevec[n];
++	    for (i = 0; i < work->nproctypes; i++)
++	      if (work -> proctypevec [i] == n)
++	        success = 0;
++
++	  if (success)
++	    {    
++	      is_proctypevec = 1;
++	      push_processed_type (work, n);
++	      remembered_type = work->typevec[n];
+ 	      mangled = &remembered_type;
+ 	    }
+ 	  break;
+@@ -3645,7 +3730,6 @@ do_type (struct work_stuff *work, const
+ 	  break;
+ 
+ 	case 'M':
+-	case 'O':
+ 	  {
+ 	    type_quals = TYPE_UNQUALIFIED;
+ 
+@@ -3725,11 +3809,12 @@ do_type (struct work_stuff *work, const
+ 		    break;
+ 		  }
+ 
+-		if (*(*mangled)++ != 'F')
++		if (*(*mangled) != 'F')
+ 		  {
+ 		    success = 0;
+ 		    break;
+ 		  }
++		(*mangled)++;
+ 	      }
+ 	    if ((member && !demangle_nested_args (work, mangled, &decl))
+ 		|| **mangled != '_')
+@@ -3789,7 +3874,7 @@ do_type (struct work_stuff *work, const
+     /* A back reference to a previously seen squangled type */
+     case 'B':
+       (*mangled)++;
+-      if (!get_count (mangled, &n) || n >= work -> numb)
++      if (!get_count (mangled, &n) || n < 0 || n >= work -> numb)
+ 	success = 0;
+       else
+ 	string_append (result, work->btypevec[n]);
+@@ -3840,6 +3925,9 @@ do_type (struct work_stuff *work, const
+     string_delete (result);
+   string_delete (&decl);
+ 
++  if (is_proctypevec)
++    pop_processed_type (work); 
++
+   if (success)
+     /* Assume an integral type, if we're not sure.  */
+     return (int) ((tk == tk_none) ? tk_integral : tk);
+@@ -3983,6 +4071,7 @@ demangle_fund_type (struct work_stuff *w
+ 	  success = 0;
+ 	  break;
+ 	}
++      /* fall through */
+     case 'I':
+       (*mangled)++;
+       if (**mangled == '_')
+@@ -4130,7 +4219,8 @@ do_hpacc_template_literal (struct work_s
+ 
+   literal_len = consume_count (mangled);
+ 
+-  if (literal_len <= 0)
++  if (literal_len <= 0
++      || literal_len > (long) strlen (*mangled))
+     return 0;
+ 
+   /* Literal parameters are names of arrays, functions, etc.  and the
+@@ -4252,6 +4342,41 @@ do_arg (struct work_stuff *work, const c
+ }
+ 
+ static void
++push_processed_type (struct work_stuff *work, int typevec_index)
++{
++  if (work->nproctypes >= work->proctypevec_size)
++    {
++      if (!work->proctypevec_size)
++	{
++	  work->proctypevec_size = 4;
++	  work->proctypevec = XNEWVEC (int, work->proctypevec_size);
++	}
++      else 
++	{
++	  if (work->proctypevec_size < 16)
++	    /* Double when small.  */
++	    work->proctypevec_size *= 2;
++	  else
++	    {
++	      /* Grow slower when large.  */
++	      if (work->proctypevec_size > (INT_MAX / 3) * 2)
++                xmalloc_failed (INT_MAX);
++              work->proctypevec_size = (work->proctypevec_size * 3 / 2);
++	    }   
++          work->proctypevec
++            = XRESIZEVEC (int, work->proctypevec, work->proctypevec_size);
++	}
++    }
++    work->proctypevec [work->nproctypes++] = typevec_index;
++}
++
++static void
++pop_processed_type (struct work_stuff *work)
++{
++  work->nproctypes--;
++}
++
++static void
+ remember_type (struct work_stuff *work, const char *start, int len)
+ {
+   char *tem;
+@@ -4515,10 +4640,13 @@ demangle_args (struct work_stuff *work,
+ 		{
+ 		  string_append (declp, ", ");
+ 		}
++	      push_processed_type (work, t);  
+ 	      if (!do_arg (work, &tem, &arg))
+ 		{
++		  pop_processed_type (work);
+ 		  return (0);
+ 		}
++	      pop_processed_type (work);
+ 	      if (PRINT_ARG_TYPES)
+ 		{
+ 		  string_appends (declp, &arg);
+Index: b/src/libiberty/hashtab.c
+===================================================================
+--- a/src/libiberty/hashtab.c
++++ b/src/libiberty/hashtab.c
+@@ -962,17 +962,17 @@ iterative_hash (const PTR k_in /* the ke
+   c += length;
+   switch(len)              /* all the case statements fall through */
+     {
+-    case 11: c+=((hashval_t)k[10]<<24);
+-    case 10: c+=((hashval_t)k[9]<<16);
+-    case 9 : c+=((hashval_t)k[8]<<8);
++    case 11: c+=((hashval_t)k[10]<<24);	/* fall through */
++    case 10: c+=((hashval_t)k[9]<<16);	/* fall through */
++    case 9 : c+=((hashval_t)k[8]<<8);	/* fall through */
+       /* the first byte of c is reserved for the length */
+-    case 8 : b+=((hashval_t)k[7]<<24);
+-    case 7 : b+=((hashval_t)k[6]<<16);
+-    case 6 : b+=((hashval_t)k[5]<<8);
+-    case 5 : b+=k[4];
+-    case 4 : a+=((hashval_t)k[3]<<24);
+-    case 3 : a+=((hashval_t)k[2]<<16);
+-    case 2 : a+=((hashval_t)k[1]<<8);
++    case 8 : b+=((hashval_t)k[7]<<24);	/* fall through */
++    case 7 : b+=((hashval_t)k[6]<<16);	/* fall through */
++    case 6 : b+=((hashval_t)k[5]<<8);	/* fall through */
++    case 5 : b+=k[4];			/* fall through */
++    case 4 : a+=((hashval_t)k[3]<<24);	/* fall through */
++    case 3 : a+=((hashval_t)k[2]<<16);	/* fall through */
++    case 2 : a+=((hashval_t)k[1]<<8);	/* fall through */
+     case 1 : a+=k[0];
+       /* case 0: nothing left to add */
+     }
+Index: b/src/libiberty/Makefile.in
+===================================================================
+--- a/src/libiberty/Makefile.in
++++ b/src/libiberty/Makefile.in
+@@ -146,6 +146,7 @@ CFILES = alloca.c argv.c asprintf.c atex
+ 	 pex-unix.c pex-win32.c						\
+          physmem.c putenv.c						\
+ 	random.c regex.c rename.c rindex.c				\
++	rust-demangle.c							\
+ 	safe-ctype.c setenv.c setproctitle.c sha1.c sigsetmask.c        \
+ 	 simple-object.c simple-object-coff.c simple-object-elf.c	\
+ 	 simple-object-mach-o.c simple-object-xcoff.c			\
+@@ -183,6 +184,7 @@ REQUIRED_OFILES =							\
+ 	./partition.$(objext) ./pexecute.$(objext) ./physmem.$(objext)	\
+ 	./pex-common.$(objext) ./pex-one.$(objext)			\
+ 	./@pexecute@.$(objext) ./vprintf-support.$(objext)		\
++	./rust-demangle.$(objext)					\
+ 	./safe-ctype.$(objext)						\
+ 	./simple-object.$(objext) ./simple-object-coff.$(objext)	\
+ 	./simple-object-elf.$(objext) ./simple-object-mach-o.$(objext)	\
+@@ -1188,6 +1190,17 @@ $(CONFIGURED_OFILES): stamp-picdir stamp
+ 	else true; fi
+ 	$(COMPILE.c) $(srcdir)/rindex.c $(OUTPUT_OPTION)
+ 
++./rust-demangle.$(objext): $(srcdir)/rust-demangle.c config.h \
++	$(INCDIR)/ansidecl.h $(INCDIR)/demangle.h $(INCDIR)/libiberty.h \
++	$(INCDIR)/safe-ctype.h
++	if [ x"$(PICFLAG)" != x ]; then \
++	  $(COMPILE.c) $(PICFLAG) $(srcdir)/rust-demangle.c -o pic/$@; \
++	else true; fi
++	if [ x"$(NOASANFLAG)" != x ]; then \
++	  $(COMPILE.c) $(PICFLAG) $(NOASANFLAG) $(srcdir)/rust-demangle.c -o noasan/$@; \
++	else true; fi
++	$(COMPILE.c) $(srcdir)/rust-demangle.c $(OUTPUT_OPTION)
++
+ ./safe-ctype.$(objext): $(srcdir)/safe-ctype.c $(INCDIR)/ansidecl.h \
+ 	$(INCDIR)/safe-ctype.h
+ 	if [ x"$(PICFLAG)" != x ]; then \
+Index: b/src/libiberty/make-relative-prefix.c
+===================================================================
+--- a/src/libiberty/make-relative-prefix.c
++++ b/src/libiberty/make-relative-prefix.c
+@@ -233,6 +233,7 @@ make_relative_prefix_1 (const char *prog
+   int i, n, common;
+   int needed_len;
+   char *ret = NULL, *ptr, *full_progname;
++  char *alloc_ptr = NULL;
+ 
+   if (progname == NULL || bin_prefix == NULL || prefix == NULL)
+     return NULL;
+@@ -256,7 +257,10 @@ make_relative_prefix_1 (const char *prog
+ #ifdef HAVE_HOST_EXECUTABLE_SUFFIX
+ 	  len += strlen (HOST_EXECUTABLE_SUFFIX);
+ #endif
+-	  nstore = (char *) alloca (len);
++	  if (len < MAX_ALLOCA_SIZE)
++	    nstore = (char *) alloca (len);
++	  else
++	    alloc_ptr = nstore = (char *) malloc (len);
+ 
+ 	  startp = endp = temp;
+ 	  while (1)
+@@ -312,12 +316,12 @@ make_relative_prefix_1 (const char *prog
+   else
+     full_progname = strdup (progname);
+   if (full_progname == NULL)
+-    return NULL;
++    goto bailout;
+ 
+   prog_dirs = split_directories (full_progname, &prog_num);
+   free (full_progname);
+   if (prog_dirs == NULL)
+-    return NULL;
++    goto bailout;
+ 
+   bin_dirs = split_directories (bin_prefix, &bin_num);
+   if (bin_dirs == NULL)
+@@ -395,6 +399,7 @@ make_relative_prefix_1 (const char *prog
+   free_split_directories (prog_dirs);
+   free_split_directories (bin_dirs);
+   free_split_directories (prefix_dirs);
++  free (alloc_ptr);
+ 
+   return ret;
+ }
+Index: b/src/libiberty/pex-win32.c
+===================================================================
+--- a/src/libiberty/pex-win32.c
++++ b/src/libiberty/pex-win32.c
+@@ -370,6 +370,8 @@ argv_to_cmdline (char *const *argv)
+ 	      cmdline_len++;
+ 	    }
+ 	}
++      if (j == 0)
++	needs_quotes = 1;
+       /* Trailing backslashes also need to be escaped because they will be
+          followed by the terminating quote.  */
+       if (needs_quotes)
+@@ -394,6 +396,8 @@ argv_to_cmdline (char *const *argv)
+               break;
+             }
+         }
++      if (j == 0)
++	needs_quotes = 1;
+ 
+       if (needs_quotes)
+         {
+Index: b/src/libiberty/regex.c
+===================================================================
+--- a/src/libiberty/regex.c
++++ b/src/libiberty/regex.c
+@@ -2493,6 +2493,7 @@ PREFIX(regex_compile) (const char *ARG_P
+           if ((syntax & RE_BK_PLUS_QM)
+               || (syntax & RE_LIMITED_OPS))
+             goto normal_char;
++	  /* Fall through.  */
+         handle_plus:
+         case '*':
+           /* If there is no previous pattern... */
+@@ -6697,6 +6698,7 @@ byte_re_match_2_internal (struct re_patt
+                 {
+                   case jump_n:
+ 		    is_a_jump_n = true;
++		    /* Fall through.  */
+                   case pop_failure_jump:
+ 		  case maybe_pop_jump:
+ 		  case jump:
+@@ -7125,7 +7127,7 @@ byte_re_match_2_internal (struct re_patt
+               DEBUG_PRINT1 ("  Match => jump.\n");
+ 	      goto unconditional_jump;
+ 	    }
+-        /* Note fall through.  */
++        /* Fall through.  */
+ 
+ 
+ 	/* The end of a simple repeat has a pop_failure_jump back to
+@@ -7150,7 +7152,7 @@ byte_re_match_2_internal (struct re_patt
+                                dummy_low_reg, dummy_high_reg,
+                                reg_dummy, reg_dummy, reg_info_dummy);
+           }
+-	  /* Note fall through.  */
++	  /* Fall through.  */
+ 
+ 	unconditional_jump:
+ #ifdef _LIBC
+@@ -7453,6 +7455,7 @@ byte_re_match_2_internal (struct re_patt
+                 {
+                 case jump_n:
+                   is_a_jump_n = true;
++		  /* Fall through.  */
+                 case maybe_pop_jump:
+                 case pop_failure_jump:
+                 case jump:
+@@ -7718,6 +7721,7 @@ PREFIX(common_op_match_null_string_p) (U
+ 
+     case set_number_at:
+       p1 += 2 * OFFSET_ADDRESS_SIZE;
++      return false;
+ 
+     default:
+       /* All other opcodes mean we cannot match the empty string.  */
+Index: b/src/libiberty/rust-demangle.c
+===================================================================
+--- /dev/null
++++ b/src/libiberty/rust-demangle.c
+@@ -0,0 +1,348 @@
++/* Demangler for the Rust programming language
++   Copyright 2016 Free Software Foundation, Inc.
++   Written by David Tolnay (dtolnay@gmail.com).
++
++This file is part of the libiberty library.
++Libiberty is free software; you can redistribute it and/or
++modify it under the terms of the GNU Library General Public
++License as published by the Free Software Foundation; either
++version 2 of the License, or (at your option) any later version.
++
++In addition to the permissions in the GNU Library General Public
++License, the Free Software Foundation gives you unlimited permission
++to link the compiled version of this file into combinations with other
++programs, and to distribute those combinations without any restriction
++coming from the use of this file.  (The Library Public License
++restrictions do apply in other respects; for example, they cover
++modification of the file, and distribution when not linked into a
++combined executable.)
++
++Libiberty is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++Library General Public License for more details.
++
++You should have received a copy of the GNU Library General Public
++License along with libiberty; see the file COPYING.LIB.
++If not, see <http://www.gnu.org/licenses/>.  */
++
++
++#ifdef HAVE_CONFIG_H
++#include "config.h"
++#endif
++
++#include "safe-ctype.h"
++
++#include <sys/types.h>
++#include <string.h>
++#include <stdio.h>
++
++#ifdef HAVE_STRING_H
++#include <string.h>
++#else
++extern size_t strlen(const char *s);
++extern int strncmp(const char *s1, const char *s2, size_t n);
++extern void *memset(void *s, int c, size_t n);
++#endif
++
++#include <demangle.h>
++#include "libiberty.h"
++
++
++/* Mangled Rust symbols look like this:
++     _$LT$std..sys..fd..FileDesc$u20$as$u20$core..ops..Drop$GT$::drop::hc68340e1baa4987a
++
++   The original symbol is:
++     <std::sys::fd::FileDesc as core::ops::Drop>::drop
++
++   The last component of the path is a 64-bit hash in lowercase hex,
++   prefixed with "h". Rust does not have a global namespace between
++   crates, an illusion which Rust maintains by using the hash to
++   distinguish things that would otherwise have the same symbol.
++
++   Any path component not starting with a XID_Start character is
++   prefixed with "_".
++
++   The following escape sequences are used:
++
++   ","  =>  $C$
++   "@"  =>  $SP$
++   "*"  =>  $BP$
++   "&"  =>  $RF$
++   "<"  =>  $LT$
++   ">"  =>  $GT$
++   "("  =>  $LP$
++   ")"  =>  $RP$
++   " "  =>  $u20$
++   "\"" =>  $u22$
++   "'"  =>  $u27$
++   "+"  =>  $u2b$
++   ";"  =>  $u3b$
++   "["  =>  $u5b$
++   "]"  =>  $u5d$
++   "{"  =>  $u7b$
++   "}"  =>  $u7d$
++   "~"  =>  $u7e$
++
++   A double ".." means "::" and a single "." means "-".
++
++   The only characters allowed in the mangled symbol are a-zA-Z0-9 and _.:$  */
++
++static const char *hash_prefix = "::h";
++static const size_t hash_prefix_len = 3;
++static const size_t hash_len = 16;
++
++static int is_prefixed_hash (const char *start);
++static int looks_like_rust (const char *sym, size_t len);
++static int unescape (const char **in, char **out, const char *seq, char value);
++
++/* INPUT: sym: symbol that has been through C++ (gnu v3) demangling
++
++   This function looks for the following indicators:
++
++   1. The hash must consist of "h" followed by 16 lowercase hex digits.
++
++   2. As a sanity check, the hash must use between 5 and 15 of the 16
++      possible hex digits. This is true of 99.9998% of hashes so once
++      in your life you may see a false negative. The point is to
++      notice path components that could be Rust hashes but are
++      probably not, like "haaaaaaaaaaaaaaaa". In this case a false
++      positive (non-Rust symbol has an important path component
++      removed because it looks like a Rust hash) is worse than a false
++      negative (the rare Rust symbol is not demangled) so this sets
++      the balance in favor of false negatives.
++
++   3. There must be no characters other than a-zA-Z0-9 and _.:$
++
++   4. There must be no unrecognized $-sign sequences.
++
++   5. There must be no sequence of three or more dots in a row ("...").  */
++
++int
++rust_is_mangled (const char *sym)
++{
++  size_t len, len_without_hash;
++
++  if (!sym)
++    return 0;
++
++  len = strlen (sym);
++  if (len <= hash_prefix_len + hash_len)
++    /* Not long enough to contain "::h" + hash + something else */
++    return 0;
++
++  len_without_hash = len - (hash_prefix_len + hash_len);
++  if (!is_prefixed_hash (sym + len_without_hash))
++    return 0;
++
++  return looks_like_rust (sym, len_without_hash);
++}
++
++/* A hash is the prefix "::h" followed by 16 lowercase hex digits. The
++   hex digits must comprise between 5 and 15 (inclusive) distinct
++   digits.  */
++
++static int
++is_prefixed_hash (const char *str)
++{
++  const char *end;
++  char seen[16];
++  size_t i;
++  int count;
++
++  if (strncmp (str, hash_prefix, hash_prefix_len))
++    return 0;
++  str += hash_prefix_len;
++
++  memset (seen, 0, sizeof(seen));
++  for (end = str + hash_len; str < end; str++)
++    if (*str >= '0' && *str <= '9')
++      seen[*str - '0'] = 1;
++    else if (*str >= 'a' && *str <= 'f')
++      seen[*str - 'a' + 10] = 1;
++    else
++      return 0;
++
++  /* Count how many distinct digits seen */
++  count = 0;
++  for (i = 0; i < 16; i++)
++    if (seen[i])
++      count++;
++
++  return count >= 5 && count <= 15;
++}
++
++static int
++looks_like_rust (const char *str, size_t len)
++{
++  const char *end = str + len;
++
++  while (str < end)
++    switch (*str)
++      {
++      case '$':
++	if (!strncmp (str, "$C$", 3))
++	  str += 3;
++	else if (!strncmp (str, "$SP$", 4)
++		 || !strncmp (str, "$BP$", 4)
++		 || !strncmp (str, "$RF$", 4)
++		 || !strncmp (str, "$LT$", 4)
++		 || !strncmp (str, "$GT$", 4)
++		 || !strncmp (str, "$LP$", 4)
++		 || !strncmp (str, "$RP$", 4))
++	  str += 4;
++	else if (!strncmp (str, "$u20$", 5)
++		 || !strncmp (str, "$u22$", 5)
++		 || !strncmp (str, "$u27$", 5)
++		 || !strncmp (str, "$u2b$", 5)
++		 || !strncmp (str, "$u3b$", 5)
++		 || !strncmp (str, "$u5b$", 5)
++		 || !strncmp (str, "$u5d$", 5)
++		 || !strncmp (str, "$u7b$", 5)
++		 || !strncmp (str, "$u7d$", 5)
++		 || !strncmp (str, "$u7e$", 5))
++	  str += 5;
++	else
++	  return 0;
++	break;
++      case '.':
++	/* Do not allow three or more consecutive dots */
++	if (!strncmp (str, "...", 3))
++	  return 0;
++	/* Fall through */
++      case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
++      case 'g': case 'h': case 'i': case 'j': case 'k': case 'l':
++      case 'm': case 'n': case 'o': case 'p': case 'q': case 'r':
++      case 's': case 't': case 'u': case 'v': case 'w': case 'x':
++      case 'y': case 'z':
++      case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
++      case 'G': case 'H': case 'I': case 'J': case 'K': case 'L':
++      case 'M': case 'N': case 'O': case 'P': case 'Q': case 'R':
++      case 'S': case 'T': case 'U': case 'V': case 'W': case 'X':
++      case 'Y': case 'Z':
++      case '0': case '1': case '2': case '3': case '4': case '5':
++      case '6': case '7': case '8': case '9':
++      case '_':
++      case ':':
++	str++;
++	break;
++      default:
++	return 0;
++      }
++
++  return 1;
++}
++
++/*
++  INPUT: sym: symbol for which rust_is_mangled(sym) returned 1.
++
++  The input is demangled in-place because the mangled name is always
++  longer than the demangled one.  */
++
++void
++rust_demangle_sym (char *sym)
++{
++  const char *in;
++  char *out;
++  const char *end;
++
++  if (!sym)
++    return;
++
++  in = sym;
++  out = sym;
++  end = sym + strlen (sym) - (hash_prefix_len + hash_len);
++
++  while (in < end)
++    switch (*in)
++      {
++      case '$':
++	if (!(unescape (&in, &out, "$C$", ',')
++	      || unescape (&in, &out, "$SP$", '@')
++	      || unescape (&in, &out, "$BP$", '*')
++	      || unescape (&in, &out, "$RF$", '&')
++	      || unescape (&in, &out, "$LT$", '<')
++	      || unescape (&in, &out, "$GT$", '>')
++	      || unescape (&in, &out, "$LP$", '(')
++	      || unescape (&in, &out, "$RP$", ')')
++	      || unescape (&in, &out, "$u20$", ' ')
++	      || unescape (&in, &out, "$u22$", '\"')
++	      || unescape (&in, &out, "$u27$", '\'')
++	      || unescape (&in, &out, "$u2b$", '+')
++	      || unescape (&in, &out, "$u3b$", ';')
++	      || unescape (&in, &out, "$u5b$", '[')
++	      || unescape (&in, &out, "$u5d$", ']')
++	      || unescape (&in, &out, "$u7b$", '{')
++	      || unescape (&in, &out, "$u7d$", '}')
++	      || unescape (&in, &out, "$u7e$", '~'))) {
++	  /* unexpected escape sequence, not looks_like_rust. */
++	  goto fail;
++	}
++	break;
++      case '_':
++	/* If this is the start of a path component and the next
++	   character is an escape sequence, ignore the underscore. The
++	   mangler inserts an underscore to make sure the path
++	   component begins with a XID_Start character. */
++	if ((in == sym || in[-1] == ':') && in[1] == '$')
++	  in++;
++	else
++	  *out++ = *in++;
++	break;
++      case '.':
++	if (in[1] == '.')
++	  {
++	    /* ".." becomes "::" */
++	    *out++ = ':';
++	    *out++ = ':';
++	    in += 2;
++	  }
++	else
++	  {
++	    /* "." becomes "-" */
++	    *out++ = '-';
++	    in++;
++	  }
++	break;
++      case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
++      case 'g': case 'h': case 'i': case 'j': case 'k': case 'l':
++      case 'm': case 'n': case 'o': case 'p': case 'q': case 'r':
++      case 's': case 't': case 'u': case 'v': case 'w': case 'x':
++      case 'y': case 'z':
++      case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
++      case 'G': case 'H': case 'I': case 'J': case 'K': case 'L':
++      case 'M': case 'N': case 'O': case 'P': case 'Q': case 'R':
++      case 'S': case 'T': case 'U': case 'V': case 'W': case 'X':
++      case 'Y': case 'Z':
++      case '0': case '1': case '2': case '3': case '4': case '5':
++      case '6': case '7': case '8': case '9':
++      case ':':
++	*out++ = *in++;
++	break;
++      default:
++	/* unexpected character in symbol, not looks_like_rust.  */
++	goto fail;
++      }
++  goto done;
++
++fail:
++  *out++ = '?'; /* This is pretty lame, but it's hard to do better. */
++done:
++  *out = '\0';
++}
++
++static int
++unescape (const char **in, char **out, const char *seq, char value)
++{
++  size_t len = strlen (seq);
++
++  if (strncmp (*in, seq, len))
++    return 0;
++
++  **out = value;
++
++  *in += len;
++  *out += 1;
++
++  return 1;
++}
+Index: b/src/libiberty/strndup.c
+===================================================================
+--- a/src/libiberty/strndup.c
++++ b/src/libiberty/strndup.c
+@@ -33,7 +33,7 @@ memory was available.  The result is alw
+ #include "ansidecl.h"
+ #include <stddef.h>
+ 
+-extern size_t	strlen (const char*);
++extern size_t	strnlen (const char *s, size_t maxlen);
+ extern PTR	malloc (size_t);
+ extern PTR	memcpy (PTR, const PTR, size_t);
+ 
+@@ -41,10 +41,7 @@ char *
+ strndup (const char *s, size_t n)
+ {
+   char *result;
+-  size_t len = strlen (s);
+-
+-  if (n < len)
+-    len = n;
++  size_t len = strnlen (s, n);
+ 
+   result = (char *) malloc (len + 1);
+   if (!result)
+Index: b/src/libiberty/testsuite/demangle-expected
+===================================================================
+--- a/src/libiberty/testsuite/demangle-expected
++++ b/src/libiberty/testsuite/demangle-expected
+@@ -31,6 +31,11 @@ ArrowLine::ArrowheadIntersects(Arrowhead
+ ArrowLine::ArrowheadIntersects
+ #
+ --format=gnu --no-params
++ArrowheadIntersects__9ArrowLineP9ArrowheadO6BoxObjP7Graphic
++ArrowLine::ArrowheadIntersects(Arrowhead *, BoxObj &&, Graphic *)
++ArrowLine::ArrowheadIntersects
++#
++--format=gnu --no-params
+ AtEnd__13ivRubberGroup
+ ivRubberGroup::AtEnd(void)
+ ivRubberGroup::AtEnd
+@@ -51,6 +56,11 @@ TextCode::CoreConstDecls(ostream &)
+ TextCode::CoreConstDecls
+ #
+ --format=gnu --no-params
++CoreConstDecls__8TextCodeO7ostream
++TextCode::CoreConstDecls(ostream &&)
++TextCode::CoreConstDecls
++#
++--format=gnu --no-params
+ Detach__8StateVarP12StateVarView
+ StateVar::Detach(StateVarView *)
+ StateVar::Detach
+@@ -66,21 +76,41 @@ RelateManip::Effect(ivEvent &)
+ RelateManip::Effect
+ #
+ --format=gnu --no-params
++Effect__11RelateManipO7ivEvent
++RelateManip::Effect(ivEvent &&)
++RelateManip::Effect
++#
++--format=gnu --no-params
+ FindFixed__FRP4CNetP4CNet
+ FindFixed(CNet *&, CNet *)
+ FindFixed
+ #
+ --format=gnu --no-params
++FindFixed__FOP4CNetP4CNet
++FindFixed(CNet *&&, CNet *)
++FindFixed
++#
++--format=gnu --no-params
+ Fix48_abort__FR8twolongs
+ Fix48_abort(twolongs &)
+ Fix48_abort
+ #
+ --format=gnu --no-params
++Fix48_abort__FO8twolongs
++Fix48_abort(twolongs &&)
++Fix48_abort
++#
++--format=gnu --no-params
+ GetBarInfo__15iv2_6_VScrollerP13ivPerspectiveRiT2
+ iv2_6_VScroller::GetBarInfo(ivPerspective *, int &, int &)
+ iv2_6_VScroller::GetBarInfo
+ #
+ --format=gnu --no-params
++GetBarInfo__15iv2_6_VScrollerP13ivPerspectiveOiT2
++iv2_6_VScroller::GetBarInfo(ivPerspective *, int &&, int &&)
++iv2_6_VScroller::GetBarInfo
++#
++--format=gnu --no-params
+ GetBgColor__C9ivPainter
+ ivPainter::GetBgColor(void) const
+ ivPainter::GetBgColor
+@@ -986,11 +1016,21 @@ List<VHDLEntity>::Pix::Pix(List<VHDLEnti
+ List<VHDLEntity>::Pix::Pix
+ #
+ --format=gnu --no-params
++__Q2t4List1Z10VHDLEntity3PixOCQ2t4List1Z10VHDLEntity3Pix
++List<VHDLEntity>::Pix::Pix(List<VHDLEntity>::Pix const &&)
++List<VHDLEntity>::Pix::Pix
++#
++--format=gnu --no-params
+ __Q2t4List1Z10VHDLEntity7elementRC10VHDLEntityPT0
+ List<VHDLEntity>::element::element(VHDLEntity const &, List<VHDLEntity>::element *)
+ List<VHDLEntity>::element::element
+ #
+ --format=gnu --no-params
++__Q2t4List1Z10VHDLEntity7elementOC10VHDLEntityPT0
++List<VHDLEntity>::element::element(VHDLEntity const &&, List<VHDLEntity>::element *)
++List<VHDLEntity>::element::element
++#
++--format=gnu --no-params
+ __Q2t4List1Z10VHDLEntity7elementRCQ2t4List1Z10VHDLEntity7element
+ List<VHDLEntity>::element::element(List<VHDLEntity>::element const &)
+ List<VHDLEntity>::element::element
+@@ -1036,6 +1076,11 @@ PixX<VHDLLibrary, VHDLLibraryRep, List<V
+ PixX<VHDLLibrary, VHDLLibraryRep, List<VHDLEntity> >::PixX
+ #
+ --format=gnu --no-params
++__t4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntityOCt4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity
++PixX<VHDLLibrary, VHDLLibraryRep, List<VHDLEntity> >::PixX(PixX<VHDLLibrary, VHDLLibraryRep, List<VHDLEntity> > const &&)
++PixX<VHDLLibrary, VHDLLibraryRep, List<VHDLEntity> >::PixX
++#
++--format=gnu --no-params
+ nextE__C11VHDLLibraryRt4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity
+ VHDLLibrary::nextE(PixX<VHDLLibrary, VHDLLibraryRep, List<VHDLEntity> > &) const
+ VHDLLibrary::nextE
+@@ -1261,6 +1306,11 @@ smanip_int::smanip_int(ios &(*)(ios &, i
+ smanip_int::smanip_int
+ #
+ --format=lucid --no-params
++__ct__10smanip_intFPFO3iosi_O3iosi
++smanip_int::smanip_int(ios &&(*)(ios &&, int), int)
++smanip_int::smanip_int
++#
++--format=lucid --no-params
+ __ct__11fstreambaseFi
+ fstreambase::fstreambase(int)
+ fstreambase::fstreambase
+@@ -1281,6 +1331,11 @@ smanip_long::smanip_long(ios &(*)(ios &,
+ smanip_long::smanip_long
+ #
+ --format=lucid --no-params
++__ct__11smanip_longFPFO3iosl_O3iosl
++smanip_long::smanip_long(ios &&(*)(ios &&, long), long)
++smanip_long::smanip_long
++#
++--format=lucid --no-params
+ __ct__11stdiostreamFP4FILE
+ stdiostream::stdiostream(FILE *)
+ stdiostream::stdiostream
+@@ -1321,6 +1376,11 @@ foo::foo(foo &)
+ foo::foo
+ #
+ --format=lucid --no-params
++__ct__3fooFO3foo
++foo::foo(foo &&)
++foo::foo
++#
++--format=lucid --no-params
+ __ct__3fooFi
+ foo::foo(int)
+ foo::foo
+@@ -1336,6 +1396,11 @@ foo::foo(int, foo &, int, foo &, int, fo
+ foo::foo
+ #
+ --format=lucid --no-params
++__ct__3fooFiO3fooT1T2T1T2
++foo::foo(int, foo &&, int, foo &&, int, foo &&)
++foo::foo
++#
++--format=lucid --no-params
+ __ct__3iosFP9streambuf
+ ios::ios(streambuf *)
+ ios::ios
+@@ -1811,6 +1876,11 @@ foo(int, foo &, int, foo &, int, foo &)
+ foo
+ #
+ --format=lucid --no-params
++foo__FiO3fooT1T2T1T2
++foo(int, foo &&, int, foo &&, int, foo &&)
++foo
++#
++--format=lucid --no-params
+ foo___3barFl
+ bar::foo_(long)
+ bar::foo_
+@@ -2561,6 +2631,11 @@ DListNode<RLabel &>::DListNode(RLabel &,
+ DListNode<RLabel &>::DListNode
+ #
+ --format=arm --no-params
++__ct__25DListNode__pt__9_O6RLabelFO6RLabelP25DListNode__pt__9_O6RLabelT2
++DListNode<RLabel &&>::DListNode(RLabel &&, DListNode<RLabel &&> *, DListNode<RLabel &&> *)
++DListNode<RLabel &&>::DListNode
++#
++--format=arm --no-params
+ bar__3fooFiT16FooBar
+ foo::bar(int, int, FooBar)
+ foo::bar
+@@ -2991,6 +3066,11 @@ DListNode<RLabel &>::DListNode(RLabel &,
+ DListNode<RLabel &>::DListNode
+ #
+ --format=hp --no-params
++__ct__9DListNodeXTO6RLabel__FO6RLabelP9DListNodeXTO6RLabel_T2
++DListNode<RLabel &&>::DListNode(RLabel &&, DListNode<RLabel &&> *, DListNode<RLabel &&> *)
++DListNode<RLabel &&>::DListNode
++#
++--format=hp --no-params
+ elem__6vectorXTiUP34__Fi
+ vector<int,34U>::elem(int)
+ vector<int,34U>::elem
+@@ -3021,16 +3101,31 @@ vector<int,-67,4000U,short &>::elem(int)
+ vector<int,-67,4000U,short &>::elem
+ #
+ --format=hp --no-params
++elem__6vectorXTiSN67UP4000TOs__Fi
++vector<int,-67,4000U,short &&>::elem(int)
++vector<int,-67,4000U,short &&>::elem
++#
++--format=hp --no-params
+ elem__6vectorXTiSN67TRdTFPv_i__Fi
+ vector<int,-67,double &,int (void *)>::elem(int)
+ vector<int,-67,double &,int (void *)>::elem
+ #
+ --format=hp --no-params
++elem__6vectorXTiSN67TOdTFPv_i__Fi
++vector<int,-67,double &&,int (void *)>::elem(int)
++vector<int,-67,double &&,int (void *)>::elem
++#
++--format=hp --no-params
+ X__6vectorXTiSN67TdTPvUP5TRs
+ vector<int,-67,double,void *,5U,short &>::X
+ vector<int,-67,double,void *,5U,short &>::X
+ #
+ --format=hp --no-params
++X__6vectorXTiSN67TdTPvUP5TOs
++vector<int,-67,double,void *,5U,short &&>::X
++vector<int,-67,double,void *,5U,short &&>::X
++#
++--format=hp --no-params
+ elem__6vectorXTiA3foo__Fi
+ vector<int,&foo>::elem(int)
+ vector<int,&foo>::elem
+@@ -3071,6 +3166,11 @@ Spec<int,int &,int>::spec(int *)
+ Spec<int,int &,int>::spec
+ #
+ --format=hp --no-params
++spec__17Spec<#1,#1.&&,#1>XTiTOiTi_FPi
++Spec<int,int &&,int>::spec(int *)
++Spec<int,int &&,int>::spec
++#
++--format=hp --no-params
+ add__XTc_FcT1
+ add<char>(char, char)
+ add<char>
+@@ -3101,6 +3201,11 @@ C<Test, Test::output> call<Test>(Test &)
+ C<Test, Test::output> call<Test>
+ #
+ --format=gnu --no-params
++call__H1Z4Test_OX01_t1C2ZX01PMX01FPX01i_vQ2X016output
++C<Test, Test::output> call<Test>(Test &&)
++C<Test, Test::output> call<Test>
++#
++--format=gnu --no-params
+ fn__FPQ21n1cPMQ21n1cFPQ21n1c_i
+ fn(n::c *, int (n::c::*)(n::c *))
+ fn
+@@ -3126,6 +3231,11 @@ int foo<TA<int const &, NA<9> > >(TA<int
+ int foo<TA<int const &, NA<9> > >
+ #
+ --format=gnu --no-params
++foo__H1Zt2TA2ZOCiZt2NA1Ui9_X01_i
++int foo<TA<int const &&, NA<9> > >(TA<int const &&, NA<9> >)
++int foo<TA<int const &&, NA<9> > >
++#
++--format=gnu --no-params
+ foo__H1Zt2TA2ZcZt2NA1Ui20_X01_i
+ int foo<TA<char, NA<20> > >(TA<char, NA<20> >)
+ int foo<TA<char, NA<20> > >
+@@ -3402,6 +3512,11 @@ int* const volatile restrict _far
+ _Z3fooILi2EEvRAplT_Li1E_i
+ void foo<2>(int (&) [(2)+(1)])
+ foo<2>
++#
++--format=gnu-v3 --no-params
++_Z3fooILi2EEvOAplT_Li1E_i
++void foo<2>(int (&&) [(2)+(1)])
++foo<2>
+ # 
+ --format=gnu-v3 --no-params
+ _Z1fM1AKFvvE
+@@ -4462,6 +4577,66 @@ __vt_90000000000cafebabe
+ 
+ _Z80800000000000000000000
+ _Z80800000000000000000000
++#
++# Tests write access violation PR70926
++
++0__Ot2m02R5T0000500000
++0__Ot2m02R5T0000500000
++#
++
++0__GT50000000000_
++0__GT50000000000_
++#
++
++__t2m05B500000000000000000_
++__t2m05B500000000000000000_
++#
++# Tests stack overflow PR71696
++
++__10%0__S4_0T0T0
++%0<>::%0(%0<>)
++
++# Inheriting constructor
++_ZN1DCI11BEi
++D::B(int)
++
++# exception-specification (C++17)
++_Z1fIvJiELb0EEvPDOT1_EFT_DpT0_E
++void f<void, int, false>(void (*)(int) noexcept(false))
++
++_Z1fIvJiELb0EEvPDoFT_DpT0_E
++void f<void, int, false>(void (*)(int) noexcept)
++
++_Z1fIvJiELb0EEvPDwiEFT_DpT0_E
++void f<void, int, false>(void (*)(int) throw(int))
++
++# Could crash
++_
++_
++
++# Could crash
++_vt
++_vt
++
++# Could crash
++_$_1Acitz
++_$_1Acitz
++
++# Could crash
++_$_H1R
++_$_H1R
++
++# Could crash
++_Q8ccQ4M2e.
++_Q8ccQ4M2e.
++
++# fold-expression with missing third component could crash.
++_Z12binary_rightIJLi1ELi2ELi3EEEv1AIXfRplT_LiEEE
++_Z12binary_rightIJLi1ELi2ELi3EEEv1AIXfRplT_LiEEE
++
++# ?: expression with missing third component could crash.
++AquT_quT_4mxautouT_4mxxx
++AquT_quT_4mxautouT_4mxxx
+ 
+ # pr c++/78252 generic lambda mangling uses template parms, and leads
+ # to unbounded recursion if not dealt with properly
+Index: b/src/libiberty/testsuite/Makefile.in
+===================================================================
+--- a/src/libiberty/testsuite/Makefile.in
++++ b/src/libiberty/testsuite/Makefile.in
+@@ -45,8 +45,8 @@ all:
+ # CHECK is set to "really_check" or the empty string by configure.
+ check: @CHECK@
+ 
+-really-check: check-cplus-dem check-d-demangle check-pexecute check-expandargv \
+-		check-strtol
++really-check: check-cplus-dem check-d-demangle check-rust-demangle \
++		check-pexecute check-expandargv check-strtol
+ 
+ # Run some tests of the demangler.
+ check-cplus-dem: test-demangle $(srcdir)/demangle-expected
+@@ -55,6 +55,9 @@ check-cplus-dem: test-demangle $(srcdir)
+ check-d-demangle: test-demangle $(srcdir)/d-demangle-expected
+ 	./test-demangle < $(srcdir)/d-demangle-expected
+ 
++check-rust-demangle: test-demangle $(srcdir)/rust-demangle-expected
++	./test-demangle < $(srcdir)/rust-demangle-expected
++
+ # Check the pexecute code.
+ check-pexecute: test-pexecute
+ 	./test-pexecute
+Index: b/src/libiberty/testsuite/rust-demangle-expected
+===================================================================
+--- /dev/null
++++ b/src/libiberty/testsuite/rust-demangle-expected
+@@ -0,0 +1,161 @@
++# This file holds test cases for the Rust demangler.
++# Each test case looks like this:
++#  options
++#  input to be demangled
++#  expected output
++#
++# See demangle-expected for documentation of supported options.
++#
++# A line starting with `#' is ignored.
++# However, blank lines in this file are NOT ignored.
++#
++############
++#
++# Coverage Tests
++#
++#
++# Demangles as rust symbol.
++--format=rust
++_ZN4main4main17he714a2e23ed7db23E
++main::main
++# Also demangles as c++ gnu v3 mangled symbol. But with extra Rust hash.
++--format=gnu-v3
++_ZN4main4main17he714a2e23ed7db23E
++main::main::he714a2e23ed7db23
++# But auto should demangle fully gnu-v3 -> rust -> demangled, not partially.
++--format=auto
++_ZN4main4main17he714a2e23ed7db23E
++main::main
++# Hash is exactly 16 hex chars. Not more.
++--format=auto
++_ZN4main4main18h1e714a2e23ed7db23E
++main::main::h1e714a2e23ed7db23
++# Not less.
++--format=auto
++_ZN4main4main16h714a2e23ed7db23E
++main::main::h714a2e23ed7db23
++# And not non-hex.
++--format=auto
++_ZN4main4main17he714a2e23ed7db2gE
++main::main::he714a2e23ed7db2g
++# $XX$ substitutions should not contain just numbers.
++--format=auto
++_ZN4main4$99$17he714a2e23ed7db23E
++main::$99$::he714a2e23ed7db23
++# _ at start of path should be removed.
++# ".." translates to "::" "$GT$" to ">" and "$LT$" to "<".
++--format=rust
++_ZN71_$LT$Test$u20$$u2b$$u20$$u27$static$u20$as$u20$foo..Bar$LT$Test$GT$$GT$3bar17h930b740aa94f1d3aE
++<Test + 'static as foo::Bar<Test>>::bar
++#
++--format=rust
++_ZN54_$LT$I$u20$as$u20$core..iter..traits..IntoIterator$GT$9into_iter17h8581507801fb8615E
++<I as core::iter::traits::IntoIterator>::into_iter
++#
++--format=rust
++_ZN10parse_tsan4main17hdbbfdf1c6a7e27d9E
++parse_tsan::main
++#
++--format=rust
++_ZN65_$LT$std..env..Args$u20$as$u20$core..iter..iterator..Iterator$GT$4next17h420a7c8d0c7eef40E
++<std::env::Args as core::iter::iterator::Iterator>::next
++#
++--format=rust
++_ZN4core3str9from_utf817hdcea28871313776dE
++core::str::from_utf8
++#
++--format=rust
++_ZN4core3mem7size_of17h18bde9bb8c22e2cfE
++core::mem::size_of
++#
++--format=rust
++_ZN5alloc4heap8allocate17hd55c03e6cb81d924E
++alloc::heap::allocate
++#
++--format=rust
++_ZN4core3ptr8null_mut17h736cce09ca0ac11aE
++core::ptr::null_mut
++#
++--format=rust
++_ZN4core3ptr31_$LT$impl$u20$$BP$mut$u20$T$GT$7is_null17h7f9de798bc3f0879E
++core::ptr::<impl *mut T>::is_null
++#
++--format=rust
++_ZN40_$LT$alloc..raw_vec..RawVec$LT$T$GT$$GT$6double17h4166e2b47539e1ffE
++<alloc::raw_vec::RawVec<T>>::double
++#
++--format=rust
++_ZN39_$LT$collections..vec..Vec$LT$T$GT$$GT$4push17hd4b6b23c1b88141aE
++<collections::vec::Vec<T>>::push
++#
++--format=rust
++_ZN70_$LT$collections..vec..Vec$LT$T$GT$$u20$as$u20$core..ops..DerefMut$GT$9deref_mut17hf299b860dc5a831cE
++<collections::vec::Vec<T> as core::ops::DerefMut>::deref_mut
++#
++--format=rust
++_ZN63_$LT$core..ptr..Unique$LT$T$GT$$u20$as$u20$core..ops..Deref$GT$5deref17hc784b4a166cb5e5cE
++<core::ptr::Unique<T> as core::ops::Deref>::deref
++#
++--format=rust
++_ZN40_$LT$alloc..raw_vec..RawVec$LT$T$GT$$GT$3ptr17h7570b6e9070b693bE
++<alloc::raw_vec::RawVec<T>>::ptr
++#
++--format=rust
++_ZN4core3ptr31_$LT$impl$u20$$BP$mut$u20$T$GT$7is_null17h0f3228f343444ac8E
++core::ptr::<impl *mut T>::is_null
++#
++--format=rust
++_ZN53_$LT$$u5b$T$u5d$$u20$as$u20$core..slice..SliceExt$GT$10as_mut_ptr17h153241df1c7d1666E
++<[T] as core::slice::SliceExt>::as_mut_ptr
++#
++--format=rust
++_ZN11collections5slice29_$LT$impl$u20$$u5b$T$u5d$$GT$10as_mut_ptr17hf12a6d0409938c96E
++collections::slice::<impl [T]>::as_mut_ptr
++#
++--format=rust
++_ZN4core3ptr5write17h651fe53ec860e780E
++core::ptr::write
++#
++--format=rust
++_ZN65_$LT$std..env..Args$u20$as$u20$core..iter..iterator..Iterator$GT$4next17h420a7c8d0c7eef40E
++<std::env::Args as core::iter::iterator::Iterator>::next
++#
++--format=rust
++_ZN54_$LT$I$u20$as$u20$core..iter..traits..IntoIterator$GT$9into_iter17he06cb713aae5b465E
++<I as core::iter::traits::IntoIterator>::into_iter
++#
++--format=rust
++_ZN71_$LT$collections..vec..IntoIter$LT$T$GT$$u20$as$u20$core..ops..Drop$GT$4drop17hf7f23304ebe62eedE
++<collections::vec::IntoIter<T> as core::ops::Drop>::drop
++#
++--format=rust
++_ZN86_$LT$collections..vec..IntoIter$LT$T$GT$$u20$as$u20$core..iter..iterator..Iterator$GT$4next17h04b3fbf148c39713E
++<collections::vec::IntoIter<T> as core::iter::iterator::Iterator>::next
++#
++--format=rust
++_ZN75_$LT$$RF$$u27$a$u20$mut$u20$I$u20$as$u20$core..iter..iterator..Iterator$GT$4next17ha050492063e0fd20E
++<&'a mut I as core::iter::iterator::Iterator>::next
++# Different hashes are OK, they are just stripped.
++--format=rust
++_ZN13drop_contents17hfe3c0a68c8ad1c74E
++drop_contents
++#
++--format=rust
++_ZN13drop_contents17h48cb59bef15bb555E
++drop_contents
++#
++--format=rust
++_ZN4core3mem7size_of17h900b33157bf58f26E
++core::mem::size_of
++#
++--format=rust
++_ZN67_$LT$alloc..raw_vec..RawVec$LT$T$GT$$u20$as$u20$core..ops..Drop$GT$4drop17h96a5cf6e94807905E
++<alloc::raw_vec::RawVec<T> as core::ops::Drop>::drop
++#
++--format=rust
++_ZN68_$LT$core..nonzero..NonZero$LT$T$GT$$u20$as$u20$core..ops..Deref$GT$5deref17hc49056f882aa46dbE
++<core::nonzero::NonZero<T> as core::ops::Deref>::deref
++#
++--format=rust
++_ZN63_$LT$core..ptr..Unique$LT$T$GT$$u20$as$u20$core..ops..Deref$GT$5deref17h19f2ad4920655e85E
++<core::ptr::Unique<T> as core::ops::Deref>::deref
+Index: b/src/libiberty/testsuite/test-pexecute.c
+===================================================================
+--- a/src/libiberty/testsuite/test-pexecute.c
++++ b/src/libiberty/testsuite/test-pexecute.c
+@@ -285,6 +285,20 @@ main (int argc, char **argv)
+     ERROR ("echo exit status failed");
+   pex_free (pex1);
+ 
++  /* Check empty parameters don't get lost.  */
++  pex1 = TEST_PEX_INIT (PEX_USE_PIPES, "temp");
++  subargv[1] = "echo";
++  subargv[2] = "foo";
++  subargv[3] = "";
++  subargv[4] = "bar";
++  subargv[5] = NULL;
++  TEST_PEX_RUN (pex1, 0, "./test-pexecute", subargv, NULL, NULL);
++  e = TEST_PEX_READ_OUTPUT (pex1);
++  CHECK_LINE (e, "foo  bar");  /* Two spaces!  */
++  if (TEST_PEX_GET_STATUS_1 (pex1) != 0)
++    ERROR ("echo exit status failed");
++  pex_free (pex1);
++
+   pex1 = TEST_PEX_INIT (PEX_USE_PIPES, "temp");
+   subargv[1] = "echo";
+   subargv[2] = "bar";
+Index: b/src/libiberty/xmemdup.c
+===================================================================
+--- a/src/libiberty/xmemdup.c
++++ b/src/libiberty/xmemdup.c
+@@ -1,4 +1,4 @@
+-/* xmemdup.c -- Duplicate a memory buffer, using xcalloc.
++/* xmemdup.c -- Duplicate a memory buffer, using xmalloc.
+    This trivial function is in the public domain.
+    Jeff Garzik, September 1999.  */
+ 
+@@ -34,6 +34,8 @@ allocated, the remaining memory is zeroe
+ PTR
+ xmemdup (const PTR input, size_t copy_size, size_t alloc_size)
+ {
+-  PTR output = xcalloc (1, alloc_size);
++  PTR output = xmalloc (alloc_size);
++  if (alloc_size > copy_size)
++    memset ((char *) output + copy_size, 0, alloc_size - copy_size);
+   return (PTR) memcpy (output, input, copy_size);
+ }
+Index: b/src/libiberty/xstrndup.c
+===================================================================
+--- a/src/libiberty/xstrndup.c
++++ b/src/libiberty/xstrndup.c
+@@ -48,10 +48,7 @@ char *
+ xstrndup (const char *s, size_t n)
+ {
+   char *result;
+-  size_t len = strlen (s);
+-
+-  if (n < len)
+-    len = n;
++  size_t len = strnlen (s, n);
+ 
+   result = XNEWVEC (char, len + 1);
+ 
+Index: b/src/include/libiberty.h
+===================================================================
+--- a/src/include/libiberty.h
++++ b/src/include/libiberty.h
+@@ -397,6 +397,17 @@ extern void hex_init (void);
+ /* Save files used for communication between processes.  */
+ #define PEX_SAVE_TEMPS		0x4
+ 
++/* Max number of alloca bytes per call before we must switch to malloc.
++
++   ?? Swiped from gnulib's regex_internal.h header.  Is this actually
++   the case?  This number seems arbitrary, though sane.
++
++   The OS usually guarantees only one guard page at the bottom of the stack,
++   and a page size can be as small as 4096 bytes.  So we cannot safely
++   allocate anything larger than 4096 bytes.  Also care for the possibility
++   of a few compiler-allocated temporary stack slots.  */
++#define MAX_ALLOCA_SIZE	4032
++
+ /* Prepare to execute one or more programs, with standard output of
+    each program fed to standard input of the next.
+    FLAGS	As above.
+Index: b/src/include/demangle.h
+===================================================================
+--- a/src/include/demangle.h
++++ b/src/include/demangle.h
+@@ -63,9 +63,10 @@ extern "C" {
+ #define DMGL_GNU_V3	 (1 << 14)
+ #define DMGL_GNAT	 (1 << 15)
+ #define DMGL_DLANG	 (1 << 16)
++#define DMGL_RUST	 (1 << 17)	/* Rust wraps GNU_V3 style mangling.  */
+ 
+ /* If none of these are set, use 'current_demangling_style' as the default. */
+-#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG|DMGL_GNU_V3|DMGL_JAVA|DMGL_GNAT|DMGL_DLANG)
++#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG|DMGL_GNU_V3|DMGL_JAVA|DMGL_GNAT|DMGL_DLANG|DMGL_RUST)
+ 
+ /* Enumeration of possible demangling styles.
+ 
+@@ -88,7 +89,8 @@ extern enum demangling_styles
+   gnu_v3_demangling = DMGL_GNU_V3,
+   java_demangling = DMGL_JAVA,
+   gnat_demangling = DMGL_GNAT,
+-  dlang_demangling = DMGL_DLANG
++  dlang_demangling = DMGL_DLANG,
++  rust_demangling = DMGL_RUST
+ } current_demangling_style;
+ 
+ /* Define string names for the various demangling styles. */
+@@ -104,6 +106,7 @@ extern enum demangling_styles
+ #define JAVA_DEMANGLING_STYLE_STRING          "java"
+ #define GNAT_DEMANGLING_STYLE_STRING          "gnat"
+ #define DLANG_DEMANGLING_STYLE_STRING         "dlang"
++#define RUST_DEMANGLING_STYLE_STRING          "rust"
+ 
+ /* Some macros to test what demangling style is active. */
+ 
+@@ -118,6 +121,7 @@ extern enum demangling_styles
+ #define JAVA_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_JAVA)
+ #define GNAT_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNAT)
+ #define DLANG_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_DLANG)
++#define RUST_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_RUST)
+ 
+ /* Provide information about the available demangle styles. This code is
+    pulled from gdb into libiberty because it is useful to binutils also.  */
+@@ -175,6 +179,27 @@ ada_demangle (const char *mangled, int o
+ extern char *
+ dlang_demangle (const char *mangled, int options);
+ 
++/* Returns non-zero iff MANGLED is a rust mangled symbol.  MANGLED must
++   already have been demangled through cplus_demangle_v3.  If this function
++   returns non-zero then MANGLED can be demangled (in-place) using
++   RUST_DEMANGLE_SYM.  */
++extern int
++rust_is_mangled (const char *mangled);
++
++/* Demangles SYM (in-place) if RUST_IS_MANGLED returned non-zero for SYM.
++   If RUST_IS_MANGLED returned zero for SYM then RUST_DEMANGLE_SYM might
++   replace characters that cannot be demangled with '?' and might truncate
++   SYM.  After calling RUST_DEMANGLE_SYM SYM might be shorter, but never
++   larger.  */
++extern void
++rust_demangle_sym (char *sym);
++
++/* Demangles MANGLED if it was GNU_V3 and then RUST mangled, otherwise
++   returns NULL. Uses CPLUS_DEMANGLE_V3, RUST_IS_MANGLED and
++   RUST_DEMANGLE_SYM.  Returns a new string that is owned by the caller.  */
++extern char *
++rust_demangle (const char *mangled, int options);
++
+ enum gnu_v3_ctor_kinds {
+   gnu_v3_complete_object_ctor = 1,
+   gnu_v3_base_object_ctor,
+@@ -449,7 +474,9 @@ enum demangle_component_type
+   /* A transaction-safe function type.  */
+   DEMANGLE_COMPONENT_TRANSACTION_SAFE,
+   /* A cloned function.  */
+-  DEMANGLE_COMPONENT_CLONE
++  DEMANGLE_COMPONENT_CLONE,
++  DEMANGLE_COMPONENT_NOEXCEPT,
++  DEMANGLE_COMPONENT_THROW_SPEC
+ };
+ 
+ /* Types which are only used internally.  */
--- gcc-6-6.4.0.orig/debian/patches/libitm-no-fortify-source.diff
+++ gcc-6-6.4.0/debian/patches/libitm-no-fortify-source.diff
@@ -0,0 +1,19 @@
+# DP: Build libitm with -U_FORTIFY_SOURCE on x86 and x86_64.
+
+Index: b/src/libitm/configure.tgt
+===================================================================
+--- a/src/libitm/configure.tgt
++++ b/src/libitm/configure.tgt
+@@ -119,6 +119,12 @@ case "${target_cpu}" in
+ 	;;
+ esac
+ 
++# FIXME: ftbfs with -D_FORTIFY_SOURCE (error: invalid use of '__builtin_va_arg_pack ())
++case "${target}" in
++  *-*-linux*)
++	XCFLAGS="${XCFLAGS} -U_FORTIFY_SOURCE"
++esac
++
+ # For the benefit of top-level configure, determine if the cpu is supported.
+ test -d ${srcdir}/config/$ARCH || UNSUPPORTED=1
+ 
--- gcc-6-6.4.0.orig/debian/patches/libjava-armel-unwind.diff
+++ gcc-6-6.4.0/debian/patches/libjava-armel-unwind.diff
@@ -0,0 +1,19 @@
+# DP: On armel, apply kludge to fix unwinder infinitely looping 'til it runs out
+# DP: of memory (http://gcc.gnu.org/ml/java/2008-06/msg00010.html).
+
+---
+ libjava/stacktrace.cc |    3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+--- a/src/libjava/stacktrace.cc
++++ b/src/libjava/stacktrace.cc
+@@ -115,6 +115,9 @@ _Jv_StackTrace::UnwindTraceFn (struct _Unwind_Context *context, void *state_ptr)
+   // Check if the trace buffer needs to be extended.
+   if (pos == state->length)
+     {
++      // http://gcc.gnu.org/ml/java/2008-06/msg00010.html
++      return _URC_END_OF_STACK;
++
+       int newLength = state->length * 2;
+       void *newFrames = _Jv_AllocBytes (newLength * sizeof(_Jv_StackFrame));
+       memcpy (newFrames, state->frames, state->length * sizeof(_Jv_StackFrame));      
--- gcc-6-6.4.0.orig/debian/patches/libjava-disable-plugin.diff
+++ gcc-6-6.4.0/debian/patches/libjava-disable-plugin.diff
@@ -0,0 +1,15 @@
+# DP: Don't build the gcjwebplugin, even when configured with --enable-plugin
+
+Index: b/src/libjava/configure.ac
+===================================================================
+--- a/src/libjava/configure.ac
++++ b/src/libjava/configure.ac
+@@ -70,6 +70,8 @@ AC_ARG_ENABLE(browser-plugin,
+      esac],
+     [browser_plugin_enabled=no]
+ )
++# FIXME: don't build the plugin, this option collides with GCC plugin support
++plugin_enabled=no
+ 
+ AC_ARG_ENABLE(gconf-peer,
+   AS_HELP_STRING([--enable-gconf-peer],
--- gcc-6-6.4.0.orig/debian/patches/libjava-fixed-symlinks.diff
+++ gcc-6-6.4.0/debian/patches/libjava-fixed-symlinks.diff
@@ -0,0 +1,28 @@
+# DP: Remove unneed '..' elements from symlinks in JAVA_HOME
+
+Index: b/src/libjava/Makefile.am
+===================================================================
+--- a/src/libjava/Makefile.am
++++ b/src/libjava/Makefile.am
+@@ -836,7 +836,7 @@ if CREATE_JAVA_HOME
+ 	$(mkinstalldirs) $(DESTDIR)$(SDK_INCLUDE_DIR)/$(OS)
+ 	relative() { \
+ 	  $(PERL) -e 'use File::Spec; \
+-	    print File::Spec->abs2rel($$ARGV[0], $$ARGV[1])' $$1 $$2; \
++	    print File::Spec->abs2rel($$ARGV[0], $$ARGV[1])' $$1 $$2 | sed -r 's,(bin|lib)[^/]*/\.\./,,'; \
+ 	}; \
+ 	RELATIVE=$$(relative $(DESTDIR)$(bindir) $(DESTDIR)$(SDK_BIN_DIR)); \
+ 	ln -sf $$RELATIVE/`echo gij | sed 's,^.*/,,;$(transform);s/$$/$(EXEEXT)/'` \
+Index: b/src/libjava/Makefile.in
+===================================================================
+--- a/src/libjava/Makefile.in
++++ b/src/libjava/Makefile.in
+@@ -12552,7 +12552,7 @@ install-data-local:
+ @CREATE_JAVA_HOME_TRUE@	$(mkinstalldirs) $(DESTDIR)$(SDK_INCLUDE_DIR)/$(OS)
+ @CREATE_JAVA_HOME_TRUE@	relative() { \
+ @CREATE_JAVA_HOME_TRUE@	  $(PERL) -e 'use File::Spec; \
+-@CREATE_JAVA_HOME_TRUE@	    print File::Spec->abs2rel($$ARGV[0], $$ARGV[1])' $$1 $$2; \
++@CREATE_JAVA_HOME_TRUE@	    print File::Spec->abs2rel($$ARGV[0], $$ARGV[1])' $$1 $$2 | sed -r 's,(bin|lib)[^/]*/\.\./,,'; \
+ @CREATE_JAVA_HOME_TRUE@	}; \
+ @CREATE_JAVA_HOME_TRUE@	RELATIVE=$$(relative $(DESTDIR)$(bindir) $(DESTDIR)$(SDK_BIN_DIR)); \
+ @CREATE_JAVA_HOME_TRUE@	ln -sf $$RELATIVE/`echo gij | sed 's,^.*/,,;$(transform);s/$$/$(EXEEXT)/'` \
--- gcc-6-6.4.0.orig/debian/patches/libjava-jnipath.diff
+++ gcc-6-6.4.0/debian/patches/libjava-jnipath.diff
@@ -0,0 +1,129 @@
+# DP: - Add /usr/lib/jni and /usr/lib/<multiarch>/jni to java.library.path.
+# DP: - When running the i386 binaries on amd64, look in
+# DP: - /usr/lib32/gcj-x.y and /usr/lib32/jni instead.
+
+Index: b/src/libjava/configure.ac
+===================================================================
+--- a/src/libjava/configure.ac
++++ b/src/libjava/configure.ac
+@@ -1475,6 +1475,9 @@ AC_CHECK_SIZEOF(void *)
+ 
+ AC_C_BIGENDIAN
+ 
++MULTIARCH_DIR=$(dpkg-architecture -qDEB_HOST_MULTIARCH 2>/dev/null || true)
++AC_SUBST(MULTIARCH_DIR)
++
+ ZLIBS=
+ SYS_ZLIBS=
+ ZINCS=
+Index: b/src/libjava/Makefile.am
+===================================================================
+--- a/src/libjava/Makefile.am
++++ b/src/libjava/Makefile.am
+@@ -364,6 +364,7 @@ AM_CXXFLAGS = \
+ 	$(WARNINGS) \
+ 	-D_GNU_SOURCE \
+ 	-DPREFIX="\"$(prefix)\"" \
++	-DMULTIARCH_DIR="\"$(MULTIARCH_DIR)\"" \
+ 	-DTOOLEXECLIBDIR="\"$(toolexeclibdir)\"" \
+         -DJAVA_HOME="\"$(JAVA_HOME_DIR)\"" \
+         -DBOOT_CLASS_PATH="\"$(BOOT_CLASS_PATH_DIR)\"" \
+Index: b/src/libjava/Makefile.in
+===================================================================
+--- a/src/libjava/Makefile.in
++++ b/src/libjava/Makefile.in
+@@ -667,6 +667,7 @@ MAINT = @MAINT@
+ MAKE = @MAKE@
+ MAKEINFO = @MAKEINFO@
+ MKDIR_P = @MKDIR_P@
++MULTIARCH_DIR = @MULTIARCH_DIR@
+ NM = nm
+ NMEDIT = @NMEDIT@
+ OBJDUMP = @OBJDUMP@
+@@ -1050,6 +1051,7 @@ AM_CXXFLAGS = \
+ 	$(WARNINGS) \
+ 	-D_GNU_SOURCE \
+ 	-DPREFIX="\"$(prefix)\"" \
++	-DMULTIARCH_DIR="\"$(MULTIARCH_DIR)\"" \
+ 	-DTOOLEXECLIBDIR="\"$(toolexeclibdir)\"" \
+         -DJAVA_HOME="\"$(JAVA_HOME_DIR)\"" \
+         -DBOOT_CLASS_PATH="\"$(BOOT_CLASS_PATH_DIR)\"" \
+Index: b/src/libjava/gnu/classpath/natSystemProperties.cc
+===================================================================
+--- a/src/libjava/gnu/classpath/natSystemProperties.cc
++++ b/src/libjava/gnu/classpath/natSystemProperties.cc
+@@ -141,6 +141,44 @@ PrependVersionedLibdir (::java::lang::St
+   return retval;
+ }
+ 
++static char*
++AppendJniLibdir (char *path, struct utsname *u)
++{
++  char* retval;
++  const char* jnilibdir = "/usr/lib/jni";
++#ifdef MULTIARCH_DIR
++  const char* jnilibdir2 = "/usr/lib/" MULTIARCH_DIR "/jni";
++  jsize len2 = strlen (jnilibdir2) + 2;
++#else
++  jsize len2 = 0;
++#endif
++
++#if defined(__linux__) && defined (__i386__)
++  if (! strcmp ("x86_64", u->machine))
++    jnilibdir = "/usr/lib32/jni";
++#endif
++
++  if (path)
++    {
++      jsize total = strlen (path)
++	+ (sizeof (PATH_SEPARATOR) - 1) + strlen (jnilibdir) +len2 + 1;
++      retval = (char*) _Jv_Malloc (total);
++      strcpy (retval, path);
++      strcat (retval, PATH_SEPARATOR);
++      strcat (retval, jnilibdir);
++    }
++  else
++    {
++      retval = (char*) _Jv_Malloc (strlen (jnilibdir) + len2 + 1);
++      strcpy (retval, jnilibdir);
++    }
++#ifdef MULTIARCH_DIR
++  strcat (retval, PATH_SEPARATOR);
++  strcat (retval, jnilibdir2);
++#endif
++  return retval;
++}
++
+ void
+ gnu::classpath::SystemProperties::insertSystemProperties (::java::util::Properties *newprops)
+ {
+@@ -373,8 +411,13 @@ gnu::classpath::SystemProperties::insert
+       // Prepend GCJ_VERSIONED_LIBDIR to the module load path so that
+       // libgcj will find its own JNI libraries, like libgtkpeer.so.
+       char* val = PrependVersionedLibdir (path);
+-      _Jv_SetDLLSearchPath (val);
++
++      // Append jnilibdir
++      char* val2 = AppendJniLibdir (val, &u);
++
++      _Jv_SetDLLSearchPath (val2);
+       _Jv_Free (val);
++      _Jv_Free (val2);
+     }
+   else
+     {
+@@ -382,9 +425,12 @@ gnu::classpath::SystemProperties::insert
+ #ifdef USE_LTDL
+       char *libpath = getenv (LTDL_SHLIBPATH_VAR);
+       char* val = _Jv_PrependVersionedLibdir (libpath);
+-      SET ("java.library.path", val);
+-      _Jv_SetDLLSearchPath (val);
++      // Append jnilibdir
++      char* val2 = AppendJniLibdir (val, &u);
++      SET ("java.library.path", val2);
++      _Jv_SetDLLSearchPath (val2);
+       _Jv_Free (val);
++      _Jv_Free (val2);
+ #else
+       SET ("java.library.path", "");
+ #endif
--- gcc-6-6.4.0.orig/debian/patches/libjava-mips64el.diff
+++ gcc-6-6.4.0/debian/patches/libjava-mips64el.diff
@@ -0,0 +1,58 @@
+2016-07-13  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* java/lang/reflect/natVMProxy.cc (unbox): Use ffi_arg for
+	integer return types smaller than a word.
+
+2016-07-13  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* interpret-run.cc: Use ffi_arg for FFI integer return types.
+
+--- a/src/libjava/interpret-run.cc
++++ b/src/libjava/interpret-run.cc
+@@ -1838,7 +1838,7 @@ details.  */
+       return;
+ 
+     insn_ireturn:
+-      *(jint *) retp = POPI ();
++      *(ffi_arg *) retp = POPI ();
+       return;
+ 
+     insn_return:
+--- a/src/libjava/java/lang/reflect/natVMProxy.cc
++++ b/src/libjava/java/lang/reflect/natVMProxy.cc
+@@ -272,17 +272,17 @@ unbox (jobject o, jclass klass, void *rvalue, FFI_TYPE type)
+   if (klass == JvPrimClass (byte))
+     {
+       _Jv_CheckCast (&Byte::class$, o);
+-      *(jbyte*)rvalue = ((Byte*)o)->byteValue();
++      *(ffi_arg*)rvalue = ((Byte*)o)->byteValue();
+     }
+   else if (klass == JvPrimClass (short))
+     {
+       _Jv_CheckCast (&Short::class$, o);
+-      *(jshort*)rvalue = ((Short*)o)->shortValue();
++      *(ffi_arg*)rvalue = ((Short*)o)->shortValue();
+     }
+   else if (klass == JvPrimClass (int))
+     {
+       _Jv_CheckCast (&Integer::class$, o);
+-      *(jint*)rvalue = ((Integer*)o)->intValue();
++      *(ffi_arg*)rvalue = ((Integer*)o)->intValue();
+     }
+   else if (klass == JvPrimClass (long))
+     {
+@@ -302,12 +302,12 @@ unbox (jobject o, jclass klass, void *rvalue, FFI_TYPE type)
+   else if (klass == JvPrimClass (boolean))
+     {
+       _Jv_CheckCast (&Boolean::class$, o);
+-      *(jboolean*)rvalue = ((Boolean*)o)->booleanValue();
++      *(ffi_arg*)rvalue = ((Boolean*)o)->booleanValue();
+     }
+   else if (klass == JvPrimClass (char))
+     {
+       _Jv_CheckCast (&Character::class$, o);
+-      *(jchar*)rvalue = ((Character*)o)->charValue();
++      *(ffi_arg*)rvalue = ((Character*)o)->charValue();
+     }
+   else
+     JvFail ("Bad ffi type in proxy");
--- gcc-6-6.4.0.orig/debian/patches/libjava-multiarch.diff
+++ gcc-6-6.4.0/debian/patches/libjava-multiarch.diff
@@ -0,0 +1,82 @@
+# DP: Install libjava libraries to multiarch location
+
+Index: b/src/libjava/configure.ac
+===================================================================
+--- a/src/libjava/configure.ac
++++ b/src/libjava/configure.ac
+@@ -1535,6 +1535,10 @@ case ${version_specific_libs} in
+       .) toolexeclibdir=$toolexecmainlibdir ;; # Avoid trailing /.
+       *) toolexeclibdir=$toolexecmainlibdir/$multi_os_directory ;;
+     esac
++    multiarch=`$CC -print-multiarch`
++    if test -n "$multiarch"; then
++        toolexeclibdir=$toolexecmainlibdir/$multiarch
++    fi
+     ;;
+ esac
+ AC_SUBST(toolexecdir)
+@@ -1552,6 +1556,10 @@ AC_DEFINE_UNQUOTED(GCJVERSION, "$GCJVERS
+ # libraries are found.
+ gcjsubdir=gcj-$gcjversion-$libgcj_soversion
+ dbexecdir='$(toolexeclibdir)/'$gcjsubdir
++multiarch=`$CC -print-multiarch`
++if test -n "$multiarch"; then
++    dbexecdir='$(libdir)/'$multiarch/$gcjsubdir
++fi
+ AC_SUBST(dbexecdir)
+ AC_SUBST(gcjsubdir)
+ 
+Index: b/src/libjava/Makefile.am
+===================================================================
+--- a/src/libjava/Makefile.am
++++ b/src/libjava/Makefile.am
+@@ -373,7 +373,7 @@ AM_CXXFLAGS = \
+ 	-DGCJ_VERSIONED_LIBDIR="\"$(dbexecdir)\"" \
+ 	-DPATH_SEPARATOR="\"$(CLASSPATH_SEPARATOR)\"" \
+ 	-DECJ_JAR_FILE="\"$(ECJ_JAR)\"" \
+-	-DLIBGCJ_DEFAULT_DATABASE="\"$(dbexecdir)/$(db_name)\"" \
++	-DLIBGCJ_DEFAULT_DATABASE="\"/var/lib/$(MULTIARCH_DIR)/gcj-6/$(db_name)\"" \
+ 	-DLIBGCJ_DEFAULT_DATABASE_PATH_TAIL="\"$(db_pathtail)\""
+ 
+ AM_GCJFLAGS = \
+Index: b/src/libjava/Makefile.in
+===================================================================
+--- a/src/libjava/Makefile.in
++++ b/src/libjava/Makefile.in
+@@ -1060,7 +1060,7 @@ AM_CXXFLAGS = \
+ 	-DGCJ_VERSIONED_LIBDIR="\"$(dbexecdir)\"" \
+ 	-DPATH_SEPARATOR="\"$(CLASSPATH_SEPARATOR)\"" \
+ 	-DECJ_JAR_FILE="\"$(ECJ_JAR)\"" \
+-	-DLIBGCJ_DEFAULT_DATABASE="\"$(dbexecdir)/$(db_name)\"" \
++	-DLIBGCJ_DEFAULT_DATABASE="\"/var/lib/$(MULTIARCH_DIR)/gcj-6/$(db_name)\"" \
+ 	-DLIBGCJ_DEFAULT_DATABASE_PATH_TAIL="\"$(db_pathtail)\""
+ 
+ AM_GCJFLAGS = \
+Index: b/src/libjava/classpath/m4/acinclude.m4
+===================================================================
+--- a/src/libjava/classpath/m4/acinclude.m4
++++ b/src/libjava/classpath/m4/acinclude.m4
+@@ -276,6 +276,10 @@ AC_DEFUN([CLASSPATH_TOOLEXECLIBDIR],
+       esac
+       ;;
+   esac
++  multiarch=`$CC -print-multiarch`
++  if test -n "$multiarch"; then
++    toolexeclibdir=${libdir}/${multiarch}
++  fi
+   AC_SUBST(toolexecdir)
+   AC_SUBST(toolexecmainlibdir)
+   AC_SUBST(toolexeclibdir)
+Index: b/src/libjava/classpath/configure.ac
+===================================================================
+--- a/src/libjava/classpath/configure.ac
++++ b/src/libjava/classpath/configure.ac
+@@ -16,6 +16,8 @@ dnl END GCJ LOCAL
+ 
+ AC_CANONICAL_TARGET
+ 
++dnl dummy change to run autoconf
++
+ dnl GCJ LOCAL
+ AC_ARG_ENABLE(java-maintainer-mode,
+ 	AS_HELP_STRING([--enable-java-maintainer-mode],
--- gcc-6-6.4.0.orig/debian/patches/libjava-nobiarch-check.diff
+++ gcc-6-6.4.0/debian/patches/libjava-nobiarch-check.diff
@@ -0,0 +1,27 @@
+# DP: For biarch builds, disable the testsuite for the non-default architecture
+# DP: for runtime libraries, which are not built by default (libjava).
+
+---
+ libjava/testsuite/Makefile.in |    4 +++-
+ 2 files changed, 25 insertions(+), 1 deletions(-)
+
+Index: b/src/libjava/testsuite/Makefile.in
+===================================================================
+--- a/src/libjava/testsuite/Makefile.in
++++ b/src/libjava/testsuite/Makefile.in
+@@ -406,12 +406,14 @@ CTAGS:
+ 
+ 
+ check-DEJAGNU: site.exp
++	runtestflags="`echo '$(RUNTESTFLAGS)' | sed -r 's/,-m(32|64|x32)//g;s/,-mabi=(n32|64)//g'`"; \
++	case "$$runtestflags" in *\\{\\}) runtestflags=; esac; \
+ 	srcdir='$(srcdir)'; export srcdir; \
+ 	EXPECT=$(EXPECT); export EXPECT; \
+ 	runtest=$(RUNTEST); \
+ 	if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
+ 	  exit_status=0; l='$(DEJATOOL)'; for tool in $$l; do \
+-	    if $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) $(RUNTESTFLAGS); \
++	    if $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) $$runtestflags; \
+ 	    then :; else exit_status=1; fi; \
+ 	  done; \
+ 	else echo "WARNING: could not find \`runtest'" 1>&2; :;\
--- gcc-6-6.4.0.orig/debian/patches/libjava-rpath.diff
+++ gcc-6-6.4.0/debian/patches/libjava-rpath.diff
@@ -0,0 +1,29 @@
+# DP: - Link ecjx with -rpath $(dbexecdir)
+
+---
+ libjava/Makefile.am |    2 +-
+ libjava/Makefile.in |    2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/src/libjava/Makefile.am
++++ b/src/libjava/Makefile.am
+@@ -888,7 +888,7 @@ else !ENABLE_SHARED
+ ecjx_LDFLAGS = $(ECJX_BASE_FLAGS) $(ECJ_BUILD_JAR) -fbootclasspath=$(BOOTCLASSPATH)
+ endif !ENABLE_SHARED
+ 
+-ecjx_LDADD = -L$(here)/.libs $(extra_ldflags)
++ecjx_LDADD = -L$(here)/.libs $(extra_ldflags) -rpath $(dbexecdir)
+ ecjx_DEPENDENCIES = libgcj.la libgcj.spec
+ if USE_LIBGCJ_BC
+ ecjx_DEPENDENCIES += libgcj_bc.la
+--- a/src/libjava/Makefile.in
++++ b/src/libjava/Makefile.in
+@@ -8360,7 +8360,7 @@ ECJX_BASE_FLAGS = -findirect-dispatch \
+ @NATIVE_FALSE@ecjx_LDFLAGS = $(ECJX_BASE_FLAGS) $(ECJ_BUILD_JAR)
+ @NATIVE_FALSE@ecjx_LDADD = 
+ @NATIVE_TRUE@ecjx_LDADD = -L$(here)/.libs $(extra_ldflags) \
+-@NATIVE_TRUE@	$(am__append_21)
++@NATIVE_TRUE@	$(am__append_21) -rpath $(dbexecdir)
+ @NATIVE_FALSE@ecjx_DEPENDENCIES = 
+ @NATIVE_TRUE@ecjx_DEPENDENCIES = libgcj.la libgcj.spec \
+ @NATIVE_TRUE@	$(am__append_20)
--- gcc-6-6.4.0.orig/debian/patches/libjava-sjlj.diff
+++ gcc-6-6.4.0/debian/patches/libjava-sjlj.diff
@@ -0,0 +1,40 @@
+# DP: Don't try to use _Unwind_Backtrace on SJLJ targets.
+# DP: See bug #387875, #388505, GCC PR 29206.
+
+---
+ libjava/sysdep/generic/backtrace.h |   17 +++++++++++++++++
+ 1 files changed, 17 insertions(+), 0 deletions(-)
+
+Index: b/src/libjava/sysdep/generic/backtrace.h
+===================================================================
+--- a/src/libjava/sysdep/generic/backtrace.h
++++ b/src/libjava/sysdep/generic/backtrace.h
+@@ -13,6 +13,20 @@ details.  */
+ 
+ #include <java-stack.h>
+ 
++#ifdef SJLJ_EXCEPTIONS
++
++#undef _Unwind_GetIPInfo
++#define _Unwind_GetIPInfo(ctx,ip_before_insn) \
++  (abort (), (void) (ctx), *ip_before_insn = 1, 0)
++
++#undef _Unwind_GetRegionStart
++#define _Unwind_GetRegionStart(ctx) \
++  (abort (), (void) (ctx), 0)
++
++#undef _Unwind_Backtrace
++#define _Unwind_Backtrace(trace_fn,state_ptr) \
++  (fallback_backtrace (trace_fn, state_ptr))
++
+ /* Unwind through the call stack calling TRACE_FN with STATE for every stack
+    frame.  Returns the reason why the unwinding was stopped.  */
+ _Unwind_Reason_Code
+@@ -20,4 +34,7 @@ fallback_backtrace (_Unwind_Trace_Fn, _J
+ {
+   return _URC_NO_REASON;
+ }
++
++#endif /* SJLJ_EXCEPTIONS */
++
+ #endif
--- gcc-6-6.4.0.orig/debian/patches/libjava-stacktrace.diff
+++ gcc-6-6.4.0/debian/patches/libjava-stacktrace.diff
@@ -0,0 +1,52 @@
+# DP: libgcj: Lookup source file name and line number in separated
+# DP: debug files found in /usr/lib/debug
+
+---
+ libjava/stacktrace.cc |   27 +++++++++++++++++++++++++++
+ 1 files changed, 27 insertions(+), 0 deletions(-)
+
+Index: b/src/libjava/stacktrace.cc
+===================================================================
+--- a/src/libjava/stacktrace.cc
++++ b/src/libjava/stacktrace.cc
+@@ -17,6 +17,11 @@ details.  */
+ #include <java-stack.h>
+ 
+ #include <stdio.h>
++#include <stdlib.h>
++#include <string.h>
++#ifdef HAVE_UNISTD_H
++#include <unistd.h>
++#endif
+ 
+ #include <java/lang/Boolean.h>
+ #include <java/lang/Class.h>
+@@ -260,6 +265,28 @@ _Jv_StackTrace::getLineNumberForFrame(_J
+       finder->lookup (binaryName, (jlong) offset);
+       *sourceFileName = finder->getSourceFile();
+       *lineNum = finder->getLineNum();
++      if (*lineNum == -1 && info.file_name[0] == '/')
++	{
++	  const char *debugPrefix = "/usr/lib/debug";
++	  char *debugPath = (char *) malloc (strlen(debugPrefix)
++					     + strlen(info.file_name)
++					     + 2);
++
++	  if (debugPath)
++	    {
++	      strcpy (debugPath, debugPrefix);
++	      strcat (debugPath, info.file_name);
++	      //printf ("%s: 0x%x\n", debugPath, offset);
++	      if (!access (debugPath, R_OK))
++		{
++		  binaryName = JvNewStringUTF (debugPath);
++		  finder->lookup (binaryName, (jlong) offset);
++		  *sourceFileName = finder->getSourceFile();
++		  *lineNum = finder->getLineNum();
++		}
++	      free (debugPath);
++	    }
++	}
+       if (*lineNum == -1 && NameFinder::showRaw())
+         {
+           gnu::gcj::runtime::StringBuffer *t =
--- gcc-6-6.4.0.orig/debian/patches/libjit-ldflags.diff
+++ gcc-6-6.4.0/debian/patches/libjit-ldflags.diff
@@ -0,0 +1,13 @@
+Index: b/src/gcc/jit/Make-lang.in
+===================================================================
+--- a/src/gcc/jit/Make-lang.in
++++ b/src/gcc/jit/Make-lang.in
+@@ -86,7 +86,7 @@ $(LIBGCCJIT_FILENAME): $(jit_OBJS) \
+ 	     $(CPPLIB) $(LIBDECNUMBER) $(LIBS) $(BACKENDLIBS) \
+ 	     $(EXTRA_GCC_OBJS) \
+ 	     -Wl,--version-script=$(srcdir)/jit/libgccjit.map \
+-	     -Wl,-soname,$(LIBGCCJIT_SONAME)
++	     -Wl,-soname,$(LIBGCCJIT_SONAME) $(LDFLAGS)
+ 
+ $(LIBGCCJIT_SONAME_SYMLINK): $(LIBGCCJIT_FILENAME)
+ 	ln -sf $(LIBGCCJIT_FILENAME) $(LIBGCCJIT_SONAME_SYMLINK)
--- gcc-6-6.4.0.orig/debian/patches/libobjc-system-gc.diff
+++ gcc-6-6.4.0/debian/patches/libobjc-system-gc.diff
@@ -0,0 +1,822 @@
+# DP: Build the GC enabled libobjc using the system libgc when available
+
+<toplevel>
+
+2016-11-19  Matthias Klose  <doko@ubuntu.com>
+
+	* configure.ac: Include pkg.m4, check for bdw-gc pkg-config module.
+	* configure: Regenerate.
+
+config/
+
+2016-11-19  Matthias Klose  <doko@ubuntu.com>
+
+	* pkg.m4: New file.
+
+libobjc/
+
+2016-11-19  Matthias Klose  <doko@ubuntu.com>
+
+	* configure.ac (--enable-objc-gc): Allow to configure with a
+	system provided boehm-gc.
+	* configure: Regenerate.
+	* Makefile.in (OBJC_BOEHM_GC_LIBS): Get value from configure.
+	* gc.c: Optionally include system boehm-gc headers.
+	* memory.c: Likewise
+	* objects.c: Likewise
+
+Index: b/src/config/pkg.m4
+===================================================================
+--- /dev/null
++++ b/src/config/pkg.m4
+@@ -0,0 +1,550 @@
++dnl pkg.m4 - Macros to locate and utilise pkg-config.   -*- Autoconf -*-
++dnl serial 11 (pkg-config-0.29)
++dnl
++dnl Copyright © 2004 Scott James Remnant <scott@netsplit.com>.
++dnl Copyright © 2012-2015 Dan Nicholson <dbn.lists@gmail.com>
++dnl
++dnl This program is free software; you can redistribute it and/or modify
++dnl it under the terms of the GNU General Public License as published by
++dnl the Free Software Foundation; either version 2 of the License, or
++dnl (at your option) any later version.
++dnl
++dnl This program is distributed in the hope that it will be useful, but
++dnl WITHOUT ANY WARRANTY; without even the implied warranty of
++dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++dnl General Public License for more details.
++dnl
++dnl You should have received a copy of the GNU General Public License
++dnl along with this program; if not, write to the Free Software
++dnl Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
++dnl 02111-1307, USA.
++dnl
++dnl As a special exception to the GNU General Public License, if you
++dnl distribute this file as part of a program that contains a
++dnl configuration script generated by Autoconf, you may include it under
++dnl the same distribution terms that you use for the rest of that
++dnl program.
++
++dnl PKG_PREREQ(MIN-VERSION)
++dnl -----------------------
++dnl Since: 0.29
++dnl
++dnl Verify that the version of the pkg-config macros are at least
++dnl MIN-VERSION. Unlike PKG_PROG_PKG_CONFIG, which checks the user's
++dnl installed version of pkg-config, this checks the developer's version
++dnl of pkg.m4 when generating configure.
++dnl
++dnl To ensure that this macro is defined, also add:
++dnl m4_ifndef([PKG_PREREQ],
++dnl     [m4_fatal([must install pkg-config 0.29 or later before running autoconf/autogen])])
++dnl
++dnl See the "Since" comment for each macro you use to see what version
++dnl of the macros you require.
++m4_defun([PKG_PREREQ],
++[m4_define([PKG_MACROS_VERSION], [0.29])
++m4_if(m4_version_compare(PKG_MACROS_VERSION, [$1]), -1,
++    [m4_fatal([pkg.m4 version $1 or higher is required but ]PKG_MACROS_VERSION[ found])])
++])dnl PKG_PREREQ
++
++dnl PKG_PROG_PKG_CONFIG([MIN-VERSION])
++dnl ----------------------------------
++dnl Since: 0.16
++dnl
++dnl Search for the pkg-config tool and set the PKG_CONFIG variable to
++dnl first found in the path. Checks that the version of pkg-config found
++dnl is at least MIN-VERSION. If MIN-VERSION is not specified, 0.9.0 is
++dnl used since that's the first version where most current features of
++dnl pkg-config existed.
++AC_DEFUN([PKG_PROG_PKG_CONFIG],
++[m4_pattern_forbid([^_?PKG_[A-Z_]+$])
++m4_pattern_allow([^PKG_CONFIG(_(PATH|LIBDIR|SYSROOT_DIR|ALLOW_SYSTEM_(CFLAGS|LIBS)))?$])
++m4_pattern_allow([^PKG_CONFIG_(DISABLE_UNINSTALLED|TOP_BUILD_DIR|DEBUG_SPEW)$])
++AC_ARG_VAR([PKG_CONFIG], [path to pkg-config utility])
++AC_ARG_VAR([PKG_CONFIG_PATH], [directories to add to pkg-config's search path])
++AC_ARG_VAR([PKG_CONFIG_LIBDIR], [path overriding pkg-config's built-in search path])
++
++if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then
++	AC_PATH_TOOL([PKG_CONFIG], [pkg-config])
++fi
++if test -n "$PKG_CONFIG"; then
++	_pkg_min_version=m4_default([$1], [0.9.0])
++	AC_MSG_CHECKING([pkg-config is at least version $_pkg_min_version])
++	if $PKG_CONFIG --atleast-pkgconfig-version $_pkg_min_version; then
++		AC_MSG_RESULT([yes])
++	else
++		AC_MSG_RESULT([no])
++		PKG_CONFIG=""
++	fi
++fi[]dnl
++])dnl PKG_PROG_PKG_CONFIG
++
++dnl PKG_CHECK_EXISTS(MODULES, [ACTION-IF-FOUND], [ACTION-IF-NOT-FOUND])
++dnl -------------------------------------------------------------------
++dnl Since: 0.18
++dnl
++dnl Check to see whether a particular set of modules exists. Similar to
++dnl PKG_CHECK_MODULES(), but does not set variables or print errors.
++dnl
++dnl Please remember that m4 expands AC_REQUIRE([PKG_PROG_PKG_CONFIG])
++dnl only at the first occurence in configure.ac, so if the first place
++dnl it's called might be skipped (such as if it is within an "if", you
++dnl have to call PKG_CHECK_EXISTS manually
++AC_DEFUN([PKG_CHECK_EXISTS],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++if test -n "$PKG_CONFIG" && \
++    AC_RUN_LOG([$PKG_CONFIG --exists --print-errors "$1"]); then
++  m4_default([$2], [:])
++m4_ifvaln([$3], [else
++  $3])dnl
++fi])
++
++dnl _PKG_CONFIG([VARIABLE], [COMMAND], [MODULES])
++dnl ---------------------------------------------
++dnl Internal wrapper calling pkg-config via PKG_CONFIG and setting
++dnl pkg_failed based on the result.
++m4_define([_PKG_CONFIG],
++[if test -n "$$1"; then
++    pkg_cv_[]$1="$$1"
++ elif test -n "$PKG_CONFIG"; then
++    PKG_CHECK_EXISTS([$3],
++                     [pkg_cv_[]$1=`$PKG_CONFIG --[]$2 "$3" 2>/dev/null`
++		      test "x$?" != "x0" && pkg_failed=yes ],
++		     [pkg_failed=yes])
++ else
++    pkg_failed=untried
++fi[]dnl
++])dnl _PKG_CONFIG
++
++dnl _PKG_SHORT_ERRORS_SUPPORTED
++dnl ---------------------------
++dnl Internal check to see if pkg-config supports short errors.
++AC_DEFUN([_PKG_SHORT_ERRORS_SUPPORTED],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])
++if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then
++        _pkg_short_errors_supported=yes
++else
++        _pkg_short_errors_supported=no
++fi[]dnl
++])dnl _PKG_SHORT_ERRORS_SUPPORTED
++
++
++dnl PKG_CHECK_MODULES(VARIABLE-PREFIX, MODULES, [ACTION-IF-FOUND],
++dnl   [ACTION-IF-NOT-FOUND])
++dnl --------------------------------------------------------------
++dnl Since: 0.4.0
++dnl
++dnl Note that if there is a possibility the first call to
++dnl PKG_CHECK_MODULES might not happen, you should be sure to include an
++dnl explicit call to PKG_PROG_PKG_CONFIG in your configure.ac
++AC_DEFUN([PKG_CHECK_MODULES],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++AC_ARG_VAR([$1][_CFLAGS], [C compiler flags for $1, overriding pkg-config])dnl
++AC_ARG_VAR([$1][_LIBS], [linker flags for $1, overriding pkg-config])dnl
++
++pkg_failed=no
++AC_MSG_CHECKING([for $1])
++
++_PKG_CONFIG([$1][_CFLAGS], [cflags], [$2])
++_PKG_CONFIG([$1][_LIBS], [libs], [$2])
++
++m4_define([_PKG_TEXT], [Alternatively, you may set the environment variables $1[]_CFLAGS
++and $1[]_LIBS to avoid the need to call pkg-config.
++See the pkg-config man page for more details.])
++
++if test $pkg_failed = yes; then
++   	AC_MSG_RESULT([no])
++        _PKG_SHORT_ERRORS_SUPPORTED
++        if test $_pkg_short_errors_supported = yes; then
++	        $1[]_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "$2" 2>&1`
++        else 
++	        $1[]_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "$2" 2>&1`
++        fi
++	# Put the nasty error message in config.log where it belongs
++	echo "$$1[]_PKG_ERRORS" >&AS_MESSAGE_LOG_FD
++
++	m4_default([$4], [AC_MSG_ERROR(
++[Package requirements ($2) were not met:
++
++$$1_PKG_ERRORS
++
++Consider adjusting the PKG_CONFIG_PATH environment variable if you
++installed software in a non-standard prefix.
++
++_PKG_TEXT])[]dnl
++        ])
++elif test $pkg_failed = untried; then
++     	AC_MSG_RESULT([no])
++	m4_default([$4], [AC_MSG_FAILURE(
++[The pkg-config script could not be found or is too old.  Make sure it
++is in your PATH or set the PKG_CONFIG environment variable to the full
++path to pkg-config.
++
++_PKG_TEXT
++
++To get pkg-config, see <http://pkg-config.freedesktop.org/>.])[]dnl
++        ])
++else
++	$1[]_CFLAGS=$pkg_cv_[]$1[]_CFLAGS
++	$1[]_LIBS=$pkg_cv_[]$1[]_LIBS
++        AC_MSG_RESULT([yes])
++	$3
++fi[]dnl
++])dnl PKG_CHECK_MODULES
++
++
++dnl PKG_CHECK_MODULES_STATIC(VARIABLE-PREFIX, MODULES, [ACTION-IF-FOUND],
++dnl   [ACTION-IF-NOT-FOUND])
++dnl ---------------------------------------------------------------------
++dnl Since: 0.29
++dnl
++dnl Checks for existence of MODULES and gathers its build flags with
++dnl static libraries enabled. Sets VARIABLE-PREFIX_CFLAGS from --cflags
++dnl and VARIABLE-PREFIX_LIBS from --libs.
++dnl
++dnl Note that if there is a possibility the first call to
++dnl PKG_CHECK_MODULES_STATIC might not happen, you should be sure to
++dnl include an explicit call to PKG_PROG_PKG_CONFIG in your
++dnl configure.ac.
++AC_DEFUN([PKG_CHECK_MODULES_STATIC],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++_save_PKG_CONFIG=$PKG_CONFIG
++PKG_CONFIG="$PKG_CONFIG --static"
++PKG_CHECK_MODULES($@)
++PKG_CONFIG=$_save_PKG_CONFIG[]dnl
++])dnl PKG_CHECK_MODULES_STATIC
++
++
++dnl PKG_INSTALLDIR([DIRECTORY])
++dnl -------------------------
++dnl Since: 0.27
++dnl
++dnl Substitutes the variable pkgconfigdir as the location where a module
++dnl should install pkg-config .pc files. By default the directory is
++dnl $libdir/pkgconfig, but the default can be changed by passing
++dnl DIRECTORY. The user can override through the --with-pkgconfigdir
++dnl parameter.
++AC_DEFUN([PKG_INSTALLDIR],
++[m4_pushdef([pkg_default], [m4_default([$1], ['${libdir}/pkgconfig'])])
++m4_pushdef([pkg_description],
++    [pkg-config installation directory @<:@]pkg_default[@:>@])
++AC_ARG_WITH([pkgconfigdir],
++    [AS_HELP_STRING([--with-pkgconfigdir], pkg_description)],,
++    [with_pkgconfigdir=]pkg_default)
++AC_SUBST([pkgconfigdir], [$with_pkgconfigdir])
++m4_popdef([pkg_default])
++m4_popdef([pkg_description])
++])dnl PKG_INSTALLDIR
++
++
++dnl PKG_NOARCH_INSTALLDIR([DIRECTORY])
++dnl --------------------------------
++dnl Since: 0.27
++dnl
++dnl Substitutes the variable noarch_pkgconfigdir as the location where a
++dnl module should install arch-independent pkg-config .pc files. By
++dnl default the directory is $datadir/pkgconfig, but the default can be
++dnl changed by passing DIRECTORY. The user can override through the
++dnl --with-noarch-pkgconfigdir parameter.
++AC_DEFUN([PKG_NOARCH_INSTALLDIR],
++[m4_pushdef([pkg_default], [m4_default([$1], ['${datadir}/pkgconfig'])])
++m4_pushdef([pkg_description],
++    [pkg-config arch-independent installation directory @<:@]pkg_default[@:>@])
++AC_ARG_WITH([noarch-pkgconfigdir],
++    [AS_HELP_STRING([--with-noarch-pkgconfigdir], pkg_description)],,
++    [with_noarch_pkgconfigdir=]pkg_default)
++AC_SUBST([noarch_pkgconfigdir], [$with_noarch_pkgconfigdir])
++m4_popdef([pkg_default])
++m4_popdef([pkg_description])
++])dnl PKG_NOARCH_INSTALLDIR
++
++
++dnl PKG_CHECK_VAR(VARIABLE, MODULE, CONFIG-VARIABLE,
++dnl [ACTION-IF-FOUND], [ACTION-IF-NOT-FOUND])
++dnl -------------------------------------------
++dnl Since: 0.28
++dnl
++dnl Retrieves the value of the pkg-config variable for the given module.
++AC_DEFUN([PKG_CHECK_VAR],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++AC_ARG_VAR([$1], [value of $3 for $2, overriding pkg-config])dnl
++
++_PKG_CONFIG([$1], [variable="][$3]["], [$2])
++AS_VAR_COPY([$1], [pkg_cv_][$1])
++
++AS_VAR_IF([$1], [""], [$5], [$4])dnl
++])dnl PKG_CHECK_VAR
++dnl pkg.m4 - Macros to locate and utilise pkg-config.   -*- Autoconf -*-
++dnl serial 11 (pkg-config-0.29)
++dnl
++dnl Copyright © 2004 Scott James Remnant <scott@netsplit.com>.
++dnl Copyright © 2012-2015 Dan Nicholson <dbn.lists@gmail.com>
++dnl
++dnl This program is free software; you can redistribute it and/or modify
++dnl it under the terms of the GNU General Public License as published by
++dnl the Free Software Foundation; either version 2 of the License, or
++dnl (at your option) any later version.
++dnl
++dnl This program is distributed in the hope that it will be useful, but
++dnl WITHOUT ANY WARRANTY; without even the implied warranty of
++dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++dnl General Public License for more details.
++dnl
++dnl You should have received a copy of the GNU General Public License
++dnl along with this program; if not, write to the Free Software
++dnl Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
++dnl 02111-1307, USA.
++dnl
++dnl As a special exception to the GNU General Public License, if you
++dnl distribute this file as part of a program that contains a
++dnl configuration script generated by Autoconf, you may include it under
++dnl the same distribution terms that you use for the rest of that
++dnl program.
++
++dnl PKG_PREREQ(MIN-VERSION)
++dnl -----------------------
++dnl Since: 0.29
++dnl
++dnl Verify that the version of the pkg-config macros are at least
++dnl MIN-VERSION. Unlike PKG_PROG_PKG_CONFIG, which checks the user's
++dnl installed version of pkg-config, this checks the developer's version
++dnl of pkg.m4 when generating configure.
++dnl
++dnl To ensure that this macro is defined, also add:
++dnl m4_ifndef([PKG_PREREQ],
++dnl     [m4_fatal([must install pkg-config 0.29 or later before running autoconf/autogen])])
++dnl
++dnl See the "Since" comment for each macro you use to see what version
++dnl of the macros you require.
++m4_defun([PKG_PREREQ],
++[m4_define([PKG_MACROS_VERSION], [0.29])
++m4_if(m4_version_compare(PKG_MACROS_VERSION, [$1]), -1,
++    [m4_fatal([pkg.m4 version $1 or higher is required but ]PKG_MACROS_VERSION[ found])])
++])dnl PKG_PREREQ
++
++dnl PKG_PROG_PKG_CONFIG([MIN-VERSION])
++dnl ----------------------------------
++dnl Since: 0.16
++dnl
++dnl Search for the pkg-config tool and set the PKG_CONFIG variable to
++dnl first found in the path. Checks that the version of pkg-config found
++dnl is at least MIN-VERSION. If MIN-VERSION is not specified, 0.9.0 is
++dnl used since that's the first version where most current features of
++dnl pkg-config existed.
++AC_DEFUN([PKG_PROG_PKG_CONFIG],
++[m4_pattern_forbid([^_?PKG_[A-Z_]+$])
++m4_pattern_allow([^PKG_CONFIG(_(PATH|LIBDIR|SYSROOT_DIR|ALLOW_SYSTEM_(CFLAGS|LIBS)))?$])
++m4_pattern_allow([^PKG_CONFIG_(DISABLE_UNINSTALLED|TOP_BUILD_DIR|DEBUG_SPEW)$])
++AC_ARG_VAR([PKG_CONFIG], [path to pkg-config utility])
++AC_ARG_VAR([PKG_CONFIG_PATH], [directories to add to pkg-config's search path])
++AC_ARG_VAR([PKG_CONFIG_LIBDIR], [path overriding pkg-config's built-in search path])
++
++if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then
++	AC_PATH_TOOL([PKG_CONFIG], [pkg-config])
++fi
++if test -n "$PKG_CONFIG"; then
++	_pkg_min_version=m4_default([$1], [0.9.0])
++	AC_MSG_CHECKING([pkg-config is at least version $_pkg_min_version])
++	if $PKG_CONFIG --atleast-pkgconfig-version $_pkg_min_version; then
++		AC_MSG_RESULT([yes])
++	else
++		AC_MSG_RESULT([no])
++		PKG_CONFIG=""
++	fi
++fi[]dnl
++])dnl PKG_PROG_PKG_CONFIG
++
++dnl PKG_CHECK_EXISTS(MODULES, [ACTION-IF-FOUND], [ACTION-IF-NOT-FOUND])
++dnl -------------------------------------------------------------------
++dnl Since: 0.18
++dnl
++dnl Check to see whether a particular set of modules exists. Similar to
++dnl PKG_CHECK_MODULES(), but does not set variables or print errors.
++dnl
++dnl Please remember that m4 expands AC_REQUIRE([PKG_PROG_PKG_CONFIG])
++dnl only at the first occurence in configure.ac, so if the first place
++dnl it's called might be skipped (such as if it is within an "if", you
++dnl have to call PKG_CHECK_EXISTS manually
++AC_DEFUN([PKG_CHECK_EXISTS],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++if test -n "$PKG_CONFIG" && \
++    AC_RUN_LOG([$PKG_CONFIG --exists --print-errors "$1"]); then
++  m4_default([$2], [:])
++m4_ifvaln([$3], [else
++  $3])dnl
++fi])
++
++dnl _PKG_CONFIG([VARIABLE], [COMMAND], [MODULES])
++dnl ---------------------------------------------
++dnl Internal wrapper calling pkg-config via PKG_CONFIG and setting
++dnl pkg_failed based on the result.
++m4_define([_PKG_CONFIG],
++[if test -n "$$1"; then
++    pkg_cv_[]$1="$$1"
++ elif test -n "$PKG_CONFIG"; then
++    PKG_CHECK_EXISTS([$3],
++                     [pkg_cv_[]$1=`$PKG_CONFIG --[]$2 "$3" 2>/dev/null`
++		      test "x$?" != "x0" && pkg_failed=yes ],
++		     [pkg_failed=yes])
++ else
++    pkg_failed=untried
++fi[]dnl
++])dnl _PKG_CONFIG
++
++dnl _PKG_SHORT_ERRORS_SUPPORTED
++dnl ---------------------------
++dnl Internal check to see if pkg-config supports short errors.
++AC_DEFUN([_PKG_SHORT_ERRORS_SUPPORTED],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])
++if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then
++        _pkg_short_errors_supported=yes
++else
++        _pkg_short_errors_supported=no
++fi[]dnl
++])dnl _PKG_SHORT_ERRORS_SUPPORTED
++
++
++dnl PKG_CHECK_MODULES(VARIABLE-PREFIX, MODULES, [ACTION-IF-FOUND],
++dnl   [ACTION-IF-NOT-FOUND])
++dnl --------------------------------------------------------------
++dnl Since: 0.4.0
++dnl
++dnl Note that if there is a possibility the first call to
++dnl PKG_CHECK_MODULES might not happen, you should be sure to include an
++dnl explicit call to PKG_PROG_PKG_CONFIG in your configure.ac
++AC_DEFUN([PKG_CHECK_MODULES],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++AC_ARG_VAR([$1][_CFLAGS], [C compiler flags for $1, overriding pkg-config])dnl
++AC_ARG_VAR([$1][_LIBS], [linker flags for $1, overriding pkg-config])dnl
++
++pkg_failed=no
++AC_MSG_CHECKING([for $1])
++
++_PKG_CONFIG([$1][_CFLAGS], [cflags], [$2])
++_PKG_CONFIG([$1][_LIBS], [libs], [$2])
++
++m4_define([_PKG_TEXT], [Alternatively, you may set the environment variables $1[]_CFLAGS
++and $1[]_LIBS to avoid the need to call pkg-config.
++See the pkg-config man page for more details.])
++
++if test $pkg_failed = yes; then
++   	AC_MSG_RESULT([no])
++        _PKG_SHORT_ERRORS_SUPPORTED
++        if test $_pkg_short_errors_supported = yes; then
++	        $1[]_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "$2" 2>&1`
++        else 
++	        $1[]_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "$2" 2>&1`
++        fi
++	# Put the nasty error message in config.log where it belongs
++	echo "$$1[]_PKG_ERRORS" >&AS_MESSAGE_LOG_FD
++
++	m4_default([$4], [AC_MSG_ERROR(
++[Package requirements ($2) were not met:
++
++$$1_PKG_ERRORS
++
++Consider adjusting the PKG_CONFIG_PATH environment variable if you
++installed software in a non-standard prefix.
++
++_PKG_TEXT])[]dnl
++        ])
++elif test $pkg_failed = untried; then
++     	AC_MSG_RESULT([no])
++	m4_default([$4], [AC_MSG_FAILURE(
++[The pkg-config script could not be found or is too old.  Make sure it
++is in your PATH or set the PKG_CONFIG environment variable to the full
++path to pkg-config.
++
++_PKG_TEXT
++
++To get pkg-config, see <http://pkg-config.freedesktop.org/>.])[]dnl
++        ])
++else
++	$1[]_CFLAGS=$pkg_cv_[]$1[]_CFLAGS
++	$1[]_LIBS=$pkg_cv_[]$1[]_LIBS
++        AC_MSG_RESULT([yes])
++	$3
++fi[]dnl
++])dnl PKG_CHECK_MODULES
++
++
++dnl PKG_CHECK_MODULES_STATIC(VARIABLE-PREFIX, MODULES, [ACTION-IF-FOUND],
++dnl   [ACTION-IF-NOT-FOUND])
++dnl ---------------------------------------------------------------------
++dnl Since: 0.29
++dnl
++dnl Checks for existence of MODULES and gathers its build flags with
++dnl static libraries enabled. Sets VARIABLE-PREFIX_CFLAGS from --cflags
++dnl and VARIABLE-PREFIX_LIBS from --libs.
++dnl
++dnl Note that if there is a possibility the first call to
++dnl PKG_CHECK_MODULES_STATIC might not happen, you should be sure to
++dnl include an explicit call to PKG_PROG_PKG_CONFIG in your
++dnl configure.ac.
++AC_DEFUN([PKG_CHECK_MODULES_STATIC],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++_save_PKG_CONFIG=$PKG_CONFIG
++PKG_CONFIG="$PKG_CONFIG --static"
++PKG_CHECK_MODULES($@)
++PKG_CONFIG=$_save_PKG_CONFIG[]dnl
++])dnl PKG_CHECK_MODULES_STATIC
++
++
++dnl PKG_INSTALLDIR([DIRECTORY])
++dnl -------------------------
++dnl Since: 0.27
++dnl
++dnl Substitutes the variable pkgconfigdir as the location where a module
++dnl should install pkg-config .pc files. By default the directory is
++dnl $libdir/pkgconfig, but the default can be changed by passing
++dnl DIRECTORY. The user can override through the --with-pkgconfigdir
++dnl parameter.
++AC_DEFUN([PKG_INSTALLDIR],
++[m4_pushdef([pkg_default], [m4_default([$1], ['${libdir}/pkgconfig'])])
++m4_pushdef([pkg_description],
++    [pkg-config installation directory @<:@]pkg_default[@:>@])
++AC_ARG_WITH([pkgconfigdir],
++    [AS_HELP_STRING([--with-pkgconfigdir], pkg_description)],,
++    [with_pkgconfigdir=]pkg_default)
++AC_SUBST([pkgconfigdir], [$with_pkgconfigdir])
++m4_popdef([pkg_default])
++m4_popdef([pkg_description])
++])dnl PKG_INSTALLDIR
++
++
++dnl PKG_NOARCH_INSTALLDIR([DIRECTORY])
++dnl --------------------------------
++dnl Since: 0.27
++dnl
++dnl Substitutes the variable noarch_pkgconfigdir as the location where a
++dnl module should install arch-independent pkg-config .pc files. By
++dnl default the directory is $datadir/pkgconfig, but the default can be
++dnl changed by passing DIRECTORY. The user can override through the
++dnl --with-noarch-pkgconfigdir parameter.
++AC_DEFUN([PKG_NOARCH_INSTALLDIR],
++[m4_pushdef([pkg_default], [m4_default([$1], ['${datadir}/pkgconfig'])])
++m4_pushdef([pkg_description],
++    [pkg-config arch-independent installation directory @<:@]pkg_default[@:>@])
++AC_ARG_WITH([noarch-pkgconfigdir],
++    [AS_HELP_STRING([--with-noarch-pkgconfigdir], pkg_description)],,
++    [with_noarch_pkgconfigdir=]pkg_default)
++AC_SUBST([noarch_pkgconfigdir], [$with_noarch_pkgconfigdir])
++m4_popdef([pkg_default])
++m4_popdef([pkg_description])
++])dnl PKG_NOARCH_INSTALLDIR
++
++
++dnl PKG_CHECK_VAR(VARIABLE, MODULE, CONFIG-VARIABLE,
++dnl [ACTION-IF-FOUND], [ACTION-IF-NOT-FOUND])
++dnl -------------------------------------------
++dnl Since: 0.28
++dnl
++dnl Retrieves the value of the pkg-config variable for the given module.
++AC_DEFUN([PKG_CHECK_VAR],
++[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
++AC_ARG_VAR([$1], [value of $3 for $2, overriding pkg-config])dnl
++
++_PKG_CONFIG([$1], [variable="][$3]["], [$2])
++AS_VAR_COPY([$1], [pkg_cv_][$1])
++
++AS_VAR_IF([$1], [""], [$5], [$4])dnl
++])dnl PKG_CHECK_VAR
+Index: b/src/configure.ac
+===================================================================
+--- a/src/configure.ac
++++ b/src/configure.ac
+@@ -29,6 +29,7 @@ m4_include([ltsugar.m4])
+ m4_include([ltversion.m4])
+ m4_include([lt~obsolete.m4])
+ m4_include([config/isl.m4])
++m4_include([config/pkg.m4])
+ 
+ AC_INIT(move-if-change)
+ AC_PREREQ(2.64)
+@@ -2172,14 +2173,20 @@ AC_ARG_ENABLE(objc-gc,
+ 		[enable use of Boehm's garbage collector with the
+ 		 GNU Objective-C runtime])],
+ [case ,${enable_languages},:${enable_objc_gc}:${noconfigdirs} in
+-  *,objc,*:*:yes:*target-boehm-gc*)
++  *,objc,*:*:yes:*target-boehm-gc*|*,objc,*:*:auto:*target-boehm-gc*|*,objc,*:*:system:*target-boehm-gc*)
+     AC_MSG_ERROR([Boehm's garbage collector was requested yet not supported in this configuration])
++esac
++case ,${enable_languages},:${enable_objc_gc} in
++  *,objc,*:auto|*,objc,*:system)
++    PKG_CHECK_EXISTS(bdw-gc,
++      AC_MSG_RESULT([found]),
++      AC_MSG_ERROR([bdw-gc pkg-config module not found]))
+     ;;
+ esac])
+ 
+ # Make sure we only build Boehm's garbage collector if required.
+ case ,${enable_languages},:${enable_objc_gc} in
+-  *,objc,*:yes)
++  *,objc,*:yes|*,objc,*:auto)
+     # Keep target-boehm-gc if requested for Objective-C.
+     ;;
+   *)
+Index: b/src/libobjc/Makefile.in
+===================================================================
+--- a/src/libobjc/Makefile.in
++++ b/src/libobjc/Makefile.in
+@@ -95,7 +95,7 @@ LIBTOOL_CLEAN   = $(LIBTOOL) --mode=clea
+ OBJC_GCFLAGS=@OBJC_GCFLAGS@
+ OBJC_BOEHM_GC=@OBJC_BOEHM_GC@
+ OBJC_BOEHM_GC_INCLUDES=@OBJC_BOEHM_GC_INCLUDES@
+-OBJC_BOEHM_GC_LIBS=../boehm-gc/libgcjgc_convenience.la $(thread_libs_and_flags)
++OBJC_BOEHM_GC_LIBS=@OBJC_BOEHM_GC_LIBS@
+ 
+ INCLUDES = -I$(srcdir)/$(MULTISRCTOP)../gcc \
+   -I$(srcdir)/$(MULTISRCTOP)../gcc/config \
+Index: b/src/libobjc/configure.ac
+===================================================================
+--- a/src/libobjc/configure.ac
++++ b/src/libobjc/configure.ac
+@@ -18,6 +18,8 @@
+ #along with GCC; see the file COPYING3.  If not see
+ #<http://www.gnu.org/licenses/>.
+ 
++m4_include([../config/pkg.m4])
++
+ AC_PREREQ(2.64)
+ AC_INIT(package-unused, version-unused,, libobjc)
+ AC_CONFIG_SRCDIR([objc/objc.h])
+@@ -57,26 +59,6 @@ AC_ARG_ENABLE(version-specific-runtime-l
+ [version_specific_libs=no])
+ AC_MSG_RESULT($version_specific_libs)
+ 
+-AC_ARG_ENABLE(objc-gc,
+-[  --enable-objc-gc       enable the use of Boehm's garbage collector with
+-                          the GNU Objective-C runtime.],
+-[case $enable_objc_gc in
+-  no)
+-    OBJC_GCFLAGS=''
+-    OBJC_BOEHM_GC=''
+-    OBJC_BOEHM_GC_INCLUDES=''
+-    ;;
+-  *)
+-    OBJC_GCFLAGS='-DOBJC_WITH_GC=1'
+-    OBJC_BOEHM_GC='libobjc_gc$(libsuffix).la'
+-    OBJC_BOEHM_GC_INCLUDES='-I$(top_srcdir)/../boehm-gc/include -I../boehm-gc/include'
+-    ;;
+-esac],
+-[OBJC_GCFLAGS=''; OBJC_BOEHM_GC=''; OBJC_BOEHM_GC_INCLUDES=''])
+-AC_SUBST(OBJC_GCFLAGS)
+-AC_SUBST(OBJC_BOEHM_GC)
+-AC_SUBST(OBJC_BOEHM_GC_INCLUDES)
+-
+ # -----------
+ # Directories
+ # -----------
+@@ -214,6 +196,87 @@ GCC_CHECK_TLS
+ 
+ gt_BITFIELD_TYPE_MATTERS
+ 
++# -----------
++# boehm-gc
++# -----------
++
++AC_ARG_ENABLE(objc-gc,
++[  --enable-objc-gc       enable the use of Boehm's garbage collector with
++                          the GNU Objective-C runtime. Valid values are
++                          yes, no, system or auto],
++[case $enable_objc_gc in
++  no)
++    use_boehm_gc=no
++    ;;
++  auto|system)
++    PKG_CHECK_MODULES(BDW_GC, bdw-gc >= 7)
++    AC_MSG_CHECKING([for system boehm-gc])
++    save_CFLAGS=$CFLAGS
++    save_LIBS=$LIBS
++    CFLAGS="$CFLAGS $BDW_GC_CFLAGS"
++    LIBS="$LIBS $BDW_GC_LIBS"
++    dnl the link test is not good enough for ARM32 multilib detection,
++    dnl first check to link, then to run
++    AC_LINK_IFELSE(
++      [AC_LANG_PROGRAM([#include <gc/gc.h>],[GC_init()])],
++      [
++        AC_RUN_IFELSE([AC_LANG_SOURCE([[
++          #include <gc/gc.h>
++          int main() {
++            GC_init();
++            return 0;
++          }
++          ]])],
++          [system_boehm_gc_found=yes],
++          [system_boehm_gc_found=no],
++          dnl assume no system boehm-gc for cross builds ...
++          [system_boehm_gc_found=no]
++        )
++      ],
++      [system_boehm_gc_found=no])
++    CFLAGS=$save_CFLAGS
++    LIBS=$save_LIBS
++    if test x$enable_objc_gc = xsystem && test x$system_boehm_gc_found = xno; then
++      AC_MSG_ERROR([system boehm-gc required but not found])
++    elif test x$system_boehm_gc_found = xno; then
++      use_boehm_gc=internal
++      AC_MSG_RESULT([not found, falling back to internal boehm-gc])
++    else
++      use_boehm_gc=system
++      AC_MSG_RESULT([found])
++    fi
++    ;;
++  *)
++    use_boehm_gc=internal
++    ;;
++esac],
++[use_boehm_gc=no])
++
++case "$use_boehm_gc" in
++  internal)
++    OBJC_GCFLAGS='-DOBJC_WITH_GC=1'
++    OBJC_BOEHM_GC='libobjc_gc$(libsuffix).la'
++    OBJC_BOEHM_GC_INCLUDES='-I$(top_srcdir)/../boehm-gc/include -I../boehm-gc/include'
++    OBJC_BOEHM_GC_LIBS='../boehm-gc/libgcjgc_convenience.la $(thread_libs_and_flags)'
++    ;;
++  system)
++    OBJC_GCFLAGS='-DOBJC_WITH_GC=1 -DSYSTEM_BOEHM_GC=1'
++    OBJC_BOEHM_GC='libobjc_gc$(libsuffix).la'
++    OBJC_BOEHM_GC_INCLUDES=$BDW_GC_CFLAGS
++    OBJC_BOEHM_GC_LIBS=$BDW_GC_LIBS
++    ;;
++  *)
++    OBJC_GCFLAGS=''
++    OBJC_BOEHM_GC=''
++    OBJC_BOEHM_GC_INCLUDES=''
++    OBJC_BOEHM_GC_LIBS=''
++    ;;
++esac
++AC_SUBST(OBJC_GCFLAGS)
++AC_SUBST(OBJC_BOEHM_GC)
++AC_SUBST(OBJC_BOEHM_GC_INCLUDES)
++AC_SUBST(OBJC_BOEHM_GC_LIBS)
++
+ # ------
+ # Output
+ # ------
+Index: b/src/libobjc/gc.c
+===================================================================
+--- a/src/libobjc/gc.c
++++ b/src/libobjc/gc.c
+@@ -36,7 +36,11 @@ see the files COPYING3 and COPYING.RUNTI
+ #include "objc/runtime.h"
+ #include "objc-private/module-abi-8.h"
+ 
++#if SYSTEM_BOEHM_GC
++#include <gc/gc.h>
++#else
+ #include <gc.h>
++#endif
+ #include <limits.h>
+ 
+ /* gc_typed.h uses the following but doesn't declare them */
+@@ -44,7 +48,11 @@ typedef GC_word word;
+ typedef GC_signed_word signed_word;
+ #define BITS_PER_WORD (CHAR_BIT * sizeof (word))
+ 
++#if SYSTEM_BOEHM_GC
++#include <gc/gc_typed.h>
++#else
+ #include <gc_typed.h>
++#endif
+ 
+ /* The following functions set up in `mask` the corresponding pointers.
+    The offset is incremented with the size of the type.  */
+Index: b/src/libobjc/memory.c
+===================================================================
+--- a/src/libobjc/memory.c
++++ b/src/libobjc/memory.c
+@@ -41,7 +41,11 @@ see the files COPYING3 and COPYING.RUNTI
+ #include "objc/runtime.h"
+ 
+ #if OBJC_WITH_GC
++#if SYSTEM_BOEHM_GC
++#include <gc/gc.h>
++#else
+ #include <gc.h>
++#endif
+ 
+ void *
+ objc_malloc (size_t size)
+Index: b/src/libobjc/objects.c
+===================================================================
+--- a/src/libobjc/objects.c
++++ b/src/libobjc/objects.c
+@@ -31,8 +31,13 @@ see the files COPYING3 and COPYING.RUNTI
+ #include <string.h>                     /* For memcpy()  */
+ 
+ #if OBJC_WITH_GC
+-# include <gc.h>
+-# include <gc_typed.h>
++# if SYSTEM_BOEHM_GC
++#  include <gc/gc.h>
++#  include <gc/gc_typed.h>
++# else
++#  include <gc.h>
++#  include <gc_typed.h>
++# endif
+ #endif
+ 
+ /* FIXME: The semantics of extraBytes are not really clear.  */
--- gcc-6-6.4.0.orig/debian/patches/libphobos-zlib.diff
+++ gcc-6-6.4.0/debian/patches/libphobos-zlib.diff
@@ -0,0 +1,74 @@
+# DP: Build zlib in any case to have a fall back for missing libz multilibs
+
+Index: b/src/libphobos/configure.ac
+===================================================================
+--- a/src/libphobos/configure.ac
++++ b/src/libphobos/configure.ac
+@@ -104,6 +104,7 @@ WITH_LOCAL_DRUNTIME([
+ 
+ DRUNTIME_LIBBACKTRACE_SETUP
+ DRUNTIME_INSTALL_DIRECTORIES
++dnl fake change to regenerate the configure file
+ 
+ # Add dependencies for libgphobos.spec file
+ LIBS="$LIBS $LIBADD_DLOPEN"
+Index: b/src/libphobos/m4/druntime/libraries.m4
+===================================================================
+--- a/src/libphobos/m4/druntime/libraries.m4
++++ b/src/libphobos/m4/druntime/libraries.m4
+@@ -39,18 +39,44 @@ AC_DEFUN([DRUNTIME_LIBRARIES_ZLIB],
+ [
+   AC_ARG_WITH(target-system-zlib,
+     AS_HELP_STRING([--with-target-system-zlib],
+-                   [use installed libz (default: no)]))
++                   [use installed libz (default: no)]),
++     [system_zlib=yes],[system_zlib=no])
+ 
+-  system_zlib=false
+-  AS_IF([test "x$with_target_system_zlib" = "xyes"], [
+-    AC_CHECK_LIB([z], [deflate], [
+-      system_zlib=yes
+-      ], [
+-      AC_MSG_ERROR([System zlib not found])])
+-  ], [
+-    AC_MSG_CHECKING([for zlib])
+-    AC_MSG_RESULT([just compiled])
+-  ])
++  AC_MSG_CHECKING([for system zlib])
++  save_LIBS=$LIBS
++  LIBS="$LIBS -lz"
++  dnl the link test is not good enough for ARM32 multilib detection,
++  dnl first check to link, then to run
++  AC_LANG_PUSH(C)
++  AC_LINK_IFELSE(
++    [AC_LANG_PROGRAM([#include <zlib.h>],[gzopen("none", "rb")])],
++    [
++      AC_RUN_IFELSE([AC_LANG_SOURCE([[
++        #include <zlib.h>
++        int main() {
++          gzFile file = gzopen("none", "rb");
++          return 0;
++        }
++        ]])],
++        [system_zlib_found=yes],
++        [system_zlib_found=no],
++        dnl no system zlib for cross builds ...
++        [system_zlib_found=no]
++      )
++    ],
++    [system_zlib_found=no])
++  LIBS=$save_LIBS
++  if test x$system_zlib = xyes; then
++    if test x$system_zlib_found = xyes; then
++      AC_MSG_RESULT([found])
++    else
++      AC_MSG_RESULT([not found, disabled])
++      system_zlib=no
++    fi
++  else
++    AC_MSG_RESULT([not enabled])
++  fi
++  AC_LANG_POP
+ 
+   AM_CONDITIONAL([DRUNTIME_ZLIB_SYSTEM], [test "$with_target_system_zlib" = yes])
+ ])
--- gcc-6-6.4.0.orig/debian/patches/libstdc++-doclink.diff
+++ gcc-6-6.4.0/debian/patches/libstdc++-doclink.diff
@@ -0,0 +1,74 @@
+# DP: adjust hrefs to point to the local documentation
+
+---
+ libstdc++-v3/doc/doxygen/mainpage.html |   10 +++++-----
+ 1 files changed, 5 insertions(+), 5 deletions(-)
+
+Index: b/src/libstdc++-v3/doc/doxygen/mainpage.html
+===================================================================
+--- a/src/libstdc++-v3/doc/doxygen/mainpage.html
++++ b/src/libstdc++-v3/doc/doxygen/mainpage.html
+@@ -27,10 +27,10 @@
+ <p class="smallertext">Generated on @DATE@.</p>
+ 
+ <p>There are two types of documentation for libstdc++.  One is the
+-   distribution documentation, which can be read online
+-   <a href="https://gcc.gnu.org/onlinedocs/libstdc++/index.html">here</a>
+-   or offline from the file doc/html/index.html in the library source
+-   directory.
++   distribution documentation, which can be read
++   <a href="../index.html">offline in the documentation directory</a>
++   or
++   <a href="https://gcc.gnu.org/onlinedocs/libstdc++/index.html">online</a>.
+ </p>
+ 
+ <p>The other type is the source documentation, of which this is the first page.
+@@ -82,8 +82,11 @@
+ 
+ <h2>License, Copyright, and Other Lawyerly Verbosity</h2>
+ <p>The libstdc++ documentation is released under
++   these terms
++   (<a href="../manual/appendix_gpl.html">read offline</a> or
+    <a href="https://gcc.gnu.org/onlinedocs/libstdc++/manual/appendix_gpl.html">
+-   these terms</a>.
++   read online</a>.
++   ).
+ </p>
+ <p>Part of the generated documentation involved comments and notes from
+    SGI, who says we gotta say this:
+Index: b/src/libstdc++-v3/doc/html/api.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/api.html
++++ b/src/libstdc++-v3/doc/html/api.html
+@@ -20,6 +20,8 @@
+   member functions for the library classes, finding out what is in a
+   particular include file, looking at inheritance diagrams, etc.
+ </p><p>
++<a class="link" href="user/index.html">The API documentation, rendered into HTML, can be viewed offline.</a>
++</p><p>
+   The API documentation, rendered into HTML, can be viewed online
+   <a class="link" href="http://gcc.gnu.org/onlinedocs/" target="_top">for each GCC release</a>
+   and
+@@ -38,4 +40,4 @@
+ </p><p>
+   In addition, a rendered set of man pages are available in the same
+   location specified above. Start with C++Intro(3).
+-</p></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="bk02.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="bk02.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="bk03.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top"> </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> </td></tr></table></div></body></html>
+\ No newline at end of file
++</p></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="bk02.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="bk02.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="bk03.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top"> </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> </td></tr></table></div></body></html>
+Index: b/src/libstdc++-v3/doc/xml/api.xml
+===================================================================
+--- a/src/libstdc++-v3/doc/xml/api.xml
++++ b/src/libstdc++-v3/doc/xml/api.xml
+@@ -40,6 +40,11 @@
+ </para>
+ 
+ <para>
++  <ulink url="user/index.html">The source-level documentation for this release can be viewed offline.
++  </ulink>
++</para>
++
++<para>
+   The API documentation, rendered into HTML, can be viewed online
+   <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://gcc.gnu.org/onlinedocs/">for each GCC release</link>
+   and
--- gcc-6-6.4.0.orig/debian/patches/libstdc++-man-3cxx.diff
+++ gcc-6-6.4.0/debian/patches/libstdc++-man-3cxx.diff
@@ -0,0 +1,67 @@
+# DP: Install libstdc++ man pages with suffix .3cxx instead of .3
+
+Index: b/src/libstdc++-v3/doc/doxygen/user.cfg.in
+===================================================================
+--- a/src/libstdc++-v3/doc/doxygen/user.cfg.in
++++ b/src/libstdc++-v3/doc/doxygen/user.cfg.in
+@@ -1968,7 +1968,7 @@ MAN_OUTPUT             = man
+ # The default value is: .3.
+ # This tag requires that the tag GENERATE_MAN is set to YES.
+ 
+-MAN_EXTENSION          = .3
++MAN_EXTENSION          = .3cxx
+ 
+ # If the MAN_LINKS tag is set to YES and doxygen generates man output, then it
+ # will generate one additional man file for each entity documented in the real
+Index: b/src/libstdc++-v3/scripts/run_doxygen
+===================================================================
+--- a/src/libstdc++-v3/scripts/run_doxygen
++++ b/src/libstdc++-v3/scripts/run_doxygen
+@@ -243,6 +243,9 @@ fi
+ if $do_man; then
+ echo ::
+ echo :: Fixing up the man pages...
++mkdir -p $outdir/man/man3
++mv $outdir/man/man3cxx/* $outdir/man/man3/
++rmdir $outdir/man/man3cxx
+ cd $outdir/man/man3
+ 
+ # File names with embedded spaces (EVIL!) need to be....?  renamed or removed?
+@@ -264,7 +267,7 @@ rm -f *.h.3 *.hpp.3 *config* *.cc.3 *.tc
+ # and I'm off getting coffee then anyhow, so I didn't care enough to make
+ # this super-fast.
+ g++ ${srcdir}/doc/doxygen/stdheader.cc -o ./stdheader
+-problematic=`egrep -l '#include <.*_.*>' [a-z]*.3`
++problematic=`egrep -l '#include <.*_.*>' [a-z]*.3 [a-z]*.3cxx`
+ for f in $problematic; do
+     # this is also slow, but safe and easy to debug
+     oldh=`sed -n '/fC#include </s/.*<\(.*\)>.*/\1/p' $f`
+@@ -277,7 +280,7 @@ rm stdheader
+ # Some of the pages for generated modules have text that confuses certain
+ # implementations of man(1), e.g. on GNU/Linux.  We need to have another
+ # top-level *roff tag to /stop/ the .SH NAME entry.
+-problematic=`egrep --files-without-match '^\.SH SYNOPSIS' [A-Z]*.3`
++problematic=`egrep --files-without-match '^\.SH SYNOPSIS' [A-Z]*.3cxx`
+ #problematic='Containers.3 Sequences.3 Assoc_containers.3 Iterator_types.3'
+ 
+ for f in $problematic; do
+@@ -291,7 +294,7 @@ a\
+ done
+ 
+ # Also, break this (generated) line up.  It's ugly as sin.
+-problematic=`grep -l '[^^]Definition at line' *.3`
++problematic=`grep -l '[^^]Definition at line' *.3 *.3cxx`
+ for f in $problematic; do
+     sed 's/Definition at line/\
+ .PP\
+@@ -408,8 +411,8 @@ for f in ios streambuf istream ostream i
+ 	 istringstream ostringstream stringstream filebuf ifstream \
+ 	 ofstream fstream string;
+ do
+-    echo ".so man3/std::basic_${f}.3" > std::${f}.3
+-    echo ".so man3/std::basic_${f}.3" > std::w${f}.3
++    echo ".so man3/std::basic_${f}.3cxx" > std::${f}.3cxx
++    echo ".so man3/std::basic_${f}.3cxx" > std::w${f}.3cxx
+ done
+ 
+ echo ::
--- gcc-6-6.4.0.orig/debian/patches/libstdc++-no-testsuite.diff
+++ gcc-6-6.4.0/debian/patches/libstdc++-no-testsuite.diff
@@ -0,0 +1,12 @@
+# DP: Don't run the libstdc++ testsuite on arm, hppa and mipsel (timeouts on the buildds)
+
+--- a/src/libstdc++-v3/testsuite/Makefile.in
++++ b/src/libstdc++-v3/testsuite/Makefile.in
+@@ -567,6 +567,7 @@
+ 
+ # Run the testsuite in normal mode.
+ check-DEJAGNU $(check_DEJAGNU_normal_targets): check-DEJAGNU%: site.exp
++	case "$(target)" in arm*|hppa*|mipsel*) exit 0;; esac; \
+ 	$(if $*,@)AR="$(AR)"; export AR; \
+ 	RANLIB="$(RANLIB)"; export RANLIB; \
+ 	if [ -z "$*" ] && [ "$(filter -j, $(MFLAGS))" = "-j" ]; then \
--- gcc-6-6.4.0.orig/debian/patches/libstdc++-nothumb-check.diff
+++ gcc-6-6.4.0/debian/patches/libstdc++-nothumb-check.diff
@@ -0,0 +1,38 @@
+# DP: Don't run the libstdc++-v3 testsuite in thumb mode on armel
+
+Index: testsuite/Makefile.in
+===================================================================
+--- a/src/libstdc++-v3/testsuite/Makefile.in	(revision 156820)
++++ b/src/libstdc++-v3/testsuite/Makefile.in	(working copy)
+@@ -583,6 +583,8 @@
+ 	srcdir=`$(am__cd) $(srcdir) && pwd`; export srcdir; \
+ 	EXPECT=$(EXPECT); export EXPECT; \
+ 	runtest=$(RUNTEST); \
++	runtestflags="`echo '$(RUNTESTFLAGS)' | sed 's/,-marm/-marm/'`"; \
++	case "$$runtestflags" in *\\{\\}) runtestflags=; esac; \
+ 	if [ -z "$$runtest" ]; then runtest=runtest; fi; \
+ 	tool=libstdc++; \
+ 	dirs=; \
+@@ -590,7 +592,7 @@
+ 	  normal0) \
+ 	    if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
+ 	      $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \
+-			$(RUNTESTFLAGS) abi.exp; \
++			$$runtestflags abi.exp; \
+ 	    else echo "WARNING: could not find \`runtest'" 1>&2; :;\
+ 	    fi; \
+ 	    dirs="`cd $$srcdir; echo [013-9][0-9]_*/* [abep]*/*`";; \
+@@ -605,11 +607,11 @@
+ 	if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
+ 	  if [ -n "$$dirs" ]; then \
+ 	    $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \
+-		    $(RUNTESTFLAGS) \
++		    $$runtestflags \
+ 		    "conformance.exp=`echo $$dirs | sed 's/ /* /g;s/$$/*/'`"; \
+ 	  else \
+ 	    $$runtest $(AM_RUNTESTFLAGS) $(RUNTESTDEFAULTFLAGS) \
+-		    $(RUNTESTFLAGS); \
++		    $$runtestflags; \
+ 	  fi; \
+ 	else echo "WARNING: could not find \`runtest'" 1>&2; :;\
+ 	fi
--- gcc-6-6.4.0.orig/debian/patches/libstdc++-pic.diff
+++ gcc-6-6.4.0/debian/patches/libstdc++-pic.diff
@@ -0,0 +1,95 @@
+# DP: Build and install libstdc++_pic.a library.
+
+Index: b/src/libstdc++-v3/src/Makefile.am
+===================================================================
+--- a/src/libstdc++-v3/src/Makefile.am
++++ b/src/libstdc++-v3/src/Makefile.am
+@@ -311,10 +311,12 @@ if GLIBCXX_BUILD_DEBUG
+ STAMP_DEBUG = build-debug
+ STAMP_INSTALL_DEBUG = install-debug
+ CLEAN_DEBUG = debug
++STAMP_INSTALL_PIC = install-pic
+ else
+ STAMP_DEBUG =
+ STAMP_INSTALL_DEBUG =
+ CLEAN_DEBUG =
++STAMP_INSTALL_PIC =
+ endif
+ 
+ # Build a debug variant.
+@@ -349,6 +351,7 @@ build-debug: stamp-debug
+ 	  mv Makefile Makefile.tmp; \
+ 	  sed -e 's,all-local: all-once,all-local:,' \
+ 	      -e 's,install-data-local: install-data-once,install-data-local:,' \
++	      -e 's,install-exec-local:.*,install-exec-local:,' \
+ 	      -e '/vpath/!s,src/c,src/debug/c,' \
+ 	  < Makefile.tmp > Makefile ; \
+ 	  rm -f Makefile.tmp ; \
+@@ -359,3 +362,8 @@ build-debug: stamp-debug
+ install-debug: build-debug
+ 	(cd ${debugdir} && $(MAKE) CXXFLAGS='$(DEBUG_FLAGS)' \
+ 	toolexeclibdir=$(glibcxx_toolexeclibdir)/debug install) ;
++
++install-exec-local: $(STAMP_INSTALL_PIC)
++$(STAMP_INSTALL_PIC):
++	$(MKDIR_P) $(DESTDIR)$(toolexeclibdir)
++	$(INSTALL_DATA) .libs/libstdc++convenience.a $(DESTDIR)$(toolexeclibdir)/libstdc++_pic.a
+Index: b/src/libstdc++-v3/src/Makefile.in
+===================================================================
+--- a/src/libstdc++-v3/src/Makefile.in
++++ b/src/libstdc++-v3/src/Makefile.in
+@@ -531,6 +531,8 @@ CXXLINK = \
+ @GLIBCXX_BUILD_DEBUG_TRUE@STAMP_INSTALL_DEBUG = install-debug
+ @GLIBCXX_BUILD_DEBUG_FALSE@CLEAN_DEBUG = 
+ @GLIBCXX_BUILD_DEBUG_TRUE@CLEAN_DEBUG = debug
++@GLIBCXX_BUILD_DEBUG_FALSE@STAMP_INSTALL_PIC = 
++@GLIBCXX_BUILD_DEBUG_TRUE@STAMP_INSTALL_PIC = install-pic
+ 
+ # Build a debug variant.
+ # Take care to fix all possibly-relative paths.
+@@ -829,7 +831,7 @@ install-dvi: install-dvi-recursive
+ 
+ install-dvi-am:
+ 
+-install-exec-am: install-toolexeclibLTLIBRARIES
++install-exec-am: install-exec-local install-toolexeclibLTLIBRARIES
+ 
+ install-html: install-html-recursive
+ 
+@@ -880,11 +882,11 @@ uninstall-am: uninstall-toolexeclibLTLIB
+ 	distclean-libtool distclean-tags dvi dvi-am html html-am info \
+ 	info-am install install-am install-data install-data-am \
+ 	install-data-local install-dvi install-dvi-am install-exec \
+-	install-exec-am install-html install-html-am install-info \
+-	install-info-am install-man install-pdf install-pdf-am \
+-	install-ps install-ps-am install-strip \
+-	install-toolexeclibLTLIBRARIES installcheck installcheck-am \
+-	installdirs installdirs-am maintainer-clean \
++	install-exec-am install-exec-local install-html \
++	install-html-am install-info install-info-am install-man \
++	install-pdf install-pdf-am install-ps install-ps-am \
++	install-strip install-toolexeclibLTLIBRARIES installcheck \
++	installcheck-am installdirs installdirs-am maintainer-clean \
+ 	maintainer-clean-generic mostlyclean mostlyclean-compile \
+ 	mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \
+ 	tags tags-recursive uninstall uninstall-am \
+@@ -1017,6 +1019,7 @@ build-debug: stamp-debug
+ 	  mv Makefile Makefile.tmp; \
+ 	  sed -e 's,all-local: all-once,all-local:,' \
+ 	      -e 's,install-data-local: install-data-once,install-data-local:,' \
++	      -e 's,install-exec-local:.*,install-exec-local:,' \
+ 	      -e '/vpath/!s,src/c,src/debug/c,' \
+ 	  < Makefile.tmp > Makefile ; \
+ 	  rm -f Makefile.tmp ; \
+@@ -1028,6 +1031,11 @@ install-debug: build-debug
+ 	(cd ${debugdir} && $(MAKE) CXXFLAGS='$(DEBUG_FLAGS)' \
+ 	toolexeclibdir=$(glibcxx_toolexeclibdir)/debug install) ;
+ 
++install-exec-local: $(STAMP_INSTALL_PIC)
++$(STAMP_INSTALL_PIC):
++	$(MKDIR_P) $(DESTDIR)$(toolexeclibdir)
++	$(INSTALL_DATA) .libs/libstdc++convenience.a $(DESTDIR)$(toolexeclibdir)/libstdc++_pic.a
++
+ # Tell versions [3.59,3.63) of GNU make to not export all variables.
+ # Otherwise a system limit (for SysV at least) may be exceeded.
+ .NOEXPORT:
--- gcc-6-6.4.0.orig/debian/patches/libstdc++-test-installed.diff
+++ gcc-6-6.4.0/debian/patches/libstdc++-test-installed.diff
@@ -0,0 +1,78 @@
+# DP: Add support to run the libstdc++-v3 testsuite using the
+# DP: installed shared libraries.
+
+Index: b/src/libstdc++-v3/testsuite/lib/libstdc++.exp
+===================================================================
+--- a/src/libstdc++-v3/testsuite/lib/libstdc++.exp
++++ b/src/libstdc++-v3/testsuite/lib/libstdc++.exp
+@@ -37,6 +37,12 @@
+ # the last thing before testing begins.  This can be defined in, e.g.,
+ # ~/.dejagnurc or $DEJAGNU.
+ 
++set test_installed 0
++if [info exists env(TEST_INSTALLED)] {
++    verbose -log "test installed libstdc++-v3"
++    set test_installed 1
++}
++
+ proc load_gcc_lib { filename } {
+     global srcdir loaded_libs
+ 
+@@ -101,6 +107,7 @@ proc libstdc++_init { testfile } {
+     global tool_timeout
+     global DEFAULT_CXXFLAGS
+     global STATIC_LIBCXXFLAGS
++    global test_installed
+ 
+     # We set LC_ALL and LANG to C so that we get the same error
+     # messages as expected.
+@@ -120,6 +127,9 @@ proc libstdc++_init { testfile } {
+ 
+     set blddir [lookfor_file [get_multilibs] libstdc++-v3]
+     set flags_file "${blddir}/scripts/testsuite_flags"
++    if {$test_installed} {
++      set flags_file "${blddir}/scripts/testsuite_flags.installed"
++    }
+     set shlib_ext [get_shlib_extension]
+     v3track flags_file 2
+ 
+@@ -151,7 +161,11 @@ proc libstdc++_init { testfile } {
+ 
+     # Locate libgcc.a so we don't need to account for different values of
+     # SHLIB_EXT on different platforms
+-    set gccdir [lookfor_file $tool_root_dir gcc/libgcc.a]
++    if {$test_installed} {
++	set gccdir ""
++    } else {
++	set gccdir [lookfor_file $tool_root_dir gcc/libgcc.a]
++    }
+     if {$gccdir != ""} {
+         set gccdir [file dirname $gccdir]
+ 	append ld_library_path_tmp ":${gccdir}"
+@@ -160,7 +174,11 @@ proc libstdc++_init { testfile } {
+ 
+     # Locate libgomp. This is only required for parallel mode.
+     set v3-libgomp 0
+-    set libgompdir [lookfor_file $blddir/../libgomp .libs/libgomp.$shlib_ext]
++    if {$test_installed} {
++	set libgompdir ""
++    } else {
++	set libgompdir [lookfor_file $blddir/../libgomp .libs/libgomp.$shlib_ext]
++    }
+     if {$libgompdir != ""} {
+ 	set v3-libgomp 1
+         set libgompdir [file dirname $libgompdir]
+@@ -182,7 +200,12 @@ proc libstdc++_init { testfile } {
+ 
+     # Locate libstdc++ shared library. (ie libstdc++.so.)
+     set v3-sharedlib 0
+-    set sharedlibdir [lookfor_file $blddir src/.libs/libstdc++.$shlib_ext]
++    if {$test_installed} {
++	set sharedlibdir ""
++	set v3-sharedlib 1
++    } else {
++	set sharedlibdir [lookfor_file $blddir src/.libs/libstdc++.$shlib_ext]
++    }
+     if {$sharedlibdir != ""} {
+ 	if { ([string match "*-*-linux*" $target_triplet]
+ 	      || [string match "*-*-gnu*" $target_triplet])
--- gcc-6-6.4.0.orig/debian/patches/link-libs.diff
+++ gcc-6-6.4.0/debian/patches/link-libs.diff
@@ -0,0 +1,170 @@
+#DP: Link libraries with -01.
+
+---
+ gcc/config/t-slibgcc-elf-ver |    1 +
+ libffi/Makefile.am           |    2 +-
+ libffi/Makefile.in           |    2 +-
+ libgfortran/Makefile.am      |    2 +-
+ libgfortran/Makefile.in      |    2 +-
+ libjava/Makefile.am          |    2 +-
+ libjava/Makefile.in          |    2 +-
+ libmudflap/Makefile.am       |    4 ++--
+ libmudflap/Makefile.in       |    4 ++--
+ libobjc/Makefile.in          |    2 ++
+ libstdc++-v3/src/Makefile.am |    1 +
+ libstdc++-v3/src/Makefile.in |    1 +
+ 12 files changed, 15 insertions(+), 10 deletions(-)
+
+--- a/src/gcc/config/t-slibgcc-elf-ver.orig	2009-09-10
++++ b/src/gcc/config/t-slibgcc-elf-ver	2009-12-22
+@@ -35,6 +35,7 @@
+ SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \
+ 	-Wl,--soname=$(SHLIB_SONAME) \
+ 	-Wl,--version-script=$(SHLIB_MAP) \
++	-Wl,-O1 \
+ 	-o $(SHLIB_DIR)/$(SHLIB_SONAME).tmp @multilib_flags@ \
+ 	$(SHLIB_OBJS) $(SHLIB_LC) && \
+ 	rm -f $(SHLIB_DIR)/$(SHLIB_SOLINK) && \
+--- a/src/libffi/Makefile.am.orig	2009-08-23
++++ b/src/libffi/Makefile.am	2009-12-22
+@@ -164,7 +164,7 @@
+ 
+ LTLDFLAGS = $(shell $(SHELL) $(top_srcdir)/../libtool-ldflags $(LDFLAGS))
+ 
+-libffi_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS)
++libffi_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -Wl,-O1
+ 
+ AM_CPPFLAGS = -I. -I$(top_srcdir)/include -Iinclude -I$(top_srcdir)/src
+ AM_CCASFLAGS = $(AM_CPPFLAGS)
+--- a/src/libffi/Makefile.in.orig	2009-12-07
++++ b/src/libffi/Makefile.in	2009-12-22
+@@ -468,7 +468,7 @@
+ nodist_libffi_convenience_la_SOURCES = $(nodist_libffi_la_SOURCES)
+ AM_CFLAGS = -Wall -g -fexceptions
+ LTLDFLAGS = $(shell $(SHELL) $(top_srcdir)/../libtool-ldflags $(LDFLAGS))
+-libffi_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS)
++libffi_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -Wl,-O1
+ AM_CPPFLAGS = -I. -I$(top_srcdir)/include -Iinclude -I$(top_srcdir)/src
+ AM_CCASFLAGS = $(AM_CPPFLAGS)
+ all: fficonfig.h
+--- a/src/libgfortran/Makefile.am.orig	2009-12-01
++++ b/src/libgfortran/Makefile.am	2009-12-22
+@@ -18,7 +18,7 @@
+ 
+ toolexeclib_LTLIBRARIES = libgfortran.la
+ libgfortran_la_LINK = $(LINK) $(libgfortran_la_LDFLAGS)
+-libgfortran_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -lm $(extra_ldflags_libgfortran) $(version_arg)
++libgfortran_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -lm $(extra_ldflags_libgfortran) $(version_arg) -Wl,-O1
+ 
+ myexeclib_LTLIBRARIES = libgfortranbegin.la
+ myexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR)
+--- a/src/libgfortran/Makefile.in.orig	2009-12-07
++++ b/src/libgfortran/Makefile.in	2009-12-22
+@@ -976,7 +976,7 @@
+ 
+ toolexeclib_LTLIBRARIES = libgfortran.la
+ libgfortran_la_LINK = $(LINK) $(libgfortran_la_LDFLAGS)
+-libgfortran_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -lm $(extra_ldflags_libgfortran) $(version_arg)
++libgfortran_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` $(LTLDFLAGS) -lm $(extra_ldflags_libgfortran) $(version_arg) -Wl,-O1
+ myexeclib_LTLIBRARIES = libgfortranbegin.la
+ myexeclibdir = $(libdir)/gcc/$(target_alias)/$(gcc_version)$(MULTISUBDIR)
+ libgfortranbegin_la_SOURCES = fmain.c
+--- a/src/libjava/Makefile.am.orig	2009-12-21
++++ b/src/libjava/Makefile.am	2009-12-22
+@@ -299,7 +299,7 @@
+ GCJ_FOR_ECJX = @GCJ_FOR_ECJX@
+ GCJ_FOR_ECJX_LINK = $(GCJ_FOR_ECJX) -o $@
+ LIBLINK = $(LIBTOOL) --tag=CXX $(LIBTOOLFLAGS) --mode=link $(CXX) -L$(here) \
+-	  $(JC1FLAGS) $(LTLDFLAGS) $(extra_ldflags_libjava) $(extra_ldflags) -o $@
++	  $(JC1FLAGS) $(LTLDFLAGS) $(extra_ldflags_libjava) $(extra_ldflags) -Wl,-O1 -o $@
+ CXXLINK = $(LIBTOOL) --tag=CXX $(LIBTOOLFLAGS) --mode=link $(CXXLD) \
+ 	  $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LTLDFLAGS) -o $@
+ 
+--- a/src/libjava/Makefile.in.orig	2009-12-21
++++ b/src/libjava/Makefile.in	2009-12-22
+@@ -1073,7 +1073,7 @@
+ 
+ GCJ_FOR_ECJX_LINK = $(GCJ_FOR_ECJX) -o $@
+ LIBLINK = $(LIBTOOL) --tag=CXX $(LIBTOOLFLAGS) --mode=link $(CXX) -L$(here) \
+-	  $(JC1FLAGS) $(LTLDFLAGS) $(extra_ldflags_libjava) $(extra_ldflags) -o $@
++	  $(JC1FLAGS) $(LTLDFLAGS) $(extra_ldflags_libjava) $(extra_ldflags) -Wl,-O1 -o $@
+ 
+ CXXLINK = $(LIBTOOL) --tag=CXX $(LIBTOOLFLAGS) --mode=link $(CXXLD) \
+ 	  $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LTLDFLAGS) -o $@
+--- a/src/libmudflap/Makefile.am.orig	2009-08-23
++++ b/src/libmudflap/Makefile.am	2009-12-22
+@@ -34,7 +34,7 @@
+ 	mf-hooks2.c
+ libmudflap_la_LIBADD = 
+ libmudflap_la_DEPENDENCIES = $(libmudflap_la_LIBADD)
+-libmudflap_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version`
++libmudflap_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` -Wl,-O1
+ 
+ 
+ libmudflapth_la_SOURCES = \
+@@ -46,7 +46,7 @@
+ libmudflapth_la_CFLAGS = -DLIBMUDFLAPTH
+ libmudflapth_la_LIBADD =
+ libmudflapth_la_DEPENDENCIES = $(libmudflapth_la_LIBADD)
+-libmudflapth_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version`
++libmudflapth_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` -Wl,-O1
+ 
+ 
+ # XXX hack alert
+--- a/src/libmudflap/Makefile.in.orig	2009-12-07
++++ b/src/libmudflap/Makefile.in	2009-12-22
+@@ -320,7 +320,7 @@
+ 
+ libmudflap_la_LIBADD = 
+ libmudflap_la_DEPENDENCIES = $(libmudflap_la_LIBADD)
+-libmudflap_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version`
++libmudflap_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` -Wl,-O1
+ libmudflapth_la_SOURCES = \
+ 	mf-runtime.c \
+ 	mf-heuristics.c \
+@@ -331,7 +331,7 @@
+ libmudflapth_la_CFLAGS = -DLIBMUDFLAPTH
+ libmudflapth_la_LIBADD = 
+ libmudflapth_la_DEPENDENCIES = $(libmudflapth_la_LIBADD)
+-libmudflapth_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version`
++libmudflapth_la_LDFLAGS = -version-info `grep -v '^\#' $(srcdir)/libtool-version` -Wl,-O1
+ 
+ # XXX hack alert
+ # From libffi/Makefile.am
+--- a/src/libobjc/Makefile.in.orig	2009-08-23
++++ b/src/libobjc/Makefile.in	2009-12-22
+@@ -282,12 +282,14 @@
+ libobjc$(libsuffix).la: $(OBJS)
+ 	$(LIBTOOL_LINK) $(CC) -o $@ $(OBJS) \
+ 		-rpath $(toolexeclibdir) \
++		-Wl,-O1 \
+ 		-version-info $(LIBOBJC_VERSION) $(extra_ldflags_libobjc) \
+ 		$(LTLDFLAGS)
+ 
+ libobjc_gc$(libsuffix).la: $(OBJS_GC)
+ 	$(LIBTOOL_LINK) $(CC) -o $@ $(OBJS_GC) $(OBJC_BOEHM_GC_LIBS) \
+ 		-rpath $(toolexeclibdir) \
++		-Wl,-O1 \
+ 		-version-info $(LIBOBJC_GC_VERSION) $(extra_ldflags_libobjc) \
+ 		$(LTLDFLAGS)
+ 
+--- a/src/libstdc++-v3/src/Makefile.am.orig	2009-12-21
++++ b/src/libstdc++-v3/src/Makefile.am	2009-12-22
+@@ -207,6 +207,7 @@
+ 	$(top_builddir)/libsupc++/libsupc++convenience.la
+ 
+ libstdc___la_LDFLAGS = \
++	-Wl,-O1 \
+ 	-version-info $(libtool_VERSION) ${version_arg} -lm 
+ 
+ libstdc___la_LINK = $(CXXLINK) $(libstdc___la_LDFLAGS)
+--- a/src/libstdc++-v3/src/Makefile.in.orig	2009-12-21
++++ b/src/libstdc++-v3/src/Makefile.in	2009-12-22
+@@ -444,6 +444,7 @@
+ 	$(top_builddir)/libsupc++/libsupc++convenience.la
+ 
+ libstdc___la_LDFLAGS = \
++	-Wl,-O1 \
+ 	-version-info $(libtool_VERSION) ${version_arg} -lm 
+ 
+ libstdc___la_LINK = $(CXXLINK) $(libstdc___la_LDFLAGS)
--- gcc-6-6.4.0.orig/debian/patches/m68k-revert-pr45144.diff
+++ gcc-6-6.4.0/debian/patches/m68k-revert-pr45144.diff
@@ -0,0 +1,20 @@
+[revert the minor PR45144 missed-optimization fix because it
+ results in miscompilation of gnat on m68k with gcc-4.6 and 4.5;
+ with gcc-4.7 other changes mask the issue <mikpe@it.uu.se>]
+
+	PR ada/48835
+
+Index: b/src/gcc/tree-sra.c
+===================================================================
+--- a/src/gcc/tree-sra.c
++++ b/src/gcc/tree-sra.c
+@@ -927,9 +927,6 @@ scalarizable_type_p (tree type)
+ 	{
+ 	  tree ft = TREE_TYPE (fld);
+ 
+-	  if (DECL_BIT_FIELD (fld))
+-	    return false;
+-
+ 	  if (!is_gimple_reg_type (ft)
+ 	      && !scalarizable_type_p (ft))
+ 	    return false;
--- gcc-6-6.4.0.orig/debian/patches/mips-loongson3a-use-fused-madd.d.diff
+++ gcc-6-6.4.0/debian/patches/mips-loongson3a-use-fused-madd.d.diff
@@ -0,0 +1,36 @@
+From 04877b8f39eff7bc35ff4d3bcdd8196ec1449c43 Mon Sep 17 00:00:00 2001
+From: mpf <mpf@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Thu, 19 Jan 2017 16:26:32 +0000
+Subject: [PATCH] MIPS: Make loongson3a use fused madd.d
+
+gcc/
+	* config/mips/mips.h (ISA_HAS_FUSED_MADD4): Enable for
+	TARGET_LOONGSON_3A.
+	(ISA_HAS_UNFUSED_MADD4): Exclude TARGET_LOONGSON_3A.
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244641 138bc75d-0d04-0410-961f-82ee72b054a4
+---
+ gcc/ChangeLog          | 6 ++++++
+ gcc/config/mips/mips.h | 6 ++++--
+ 2 files changed, 10 insertions(+), 2 deletions(-)
+
+Index: b/src/gcc/config/mips/mips.h
+===================================================================
+--- a/src/gcc/config/mips/mips.h
++++ b/src/gcc/config/mips/mips.h
+@@ -1041,11 +1041,13 @@ struct mips_cpu_info {
+ 
+ /* ISA has 4 operand fused madd instructions of the form
+    'd = [+-] (a * b [+-] c)'.  */
+-#define ISA_HAS_FUSED_MADD4	TARGET_MIPS8000
++#define ISA_HAS_FUSED_MADD4	(TARGET_MIPS8000 || TARGET_LOONGSON_3A)
+ 
+ /* ISA has 4 operand unfused madd instructions of the form
+    'd = [+-] (a * b [+-] c)'.  */
+-#define ISA_HAS_UNFUSED_MADD4	(ISA_HAS_FP4 && !TARGET_MIPS8000)
++#define ISA_HAS_UNFUSED_MADD4	(ISA_HAS_FP4				\
++				 && !TARGET_MIPS8000			\
++				 && !TARGET_LOONGSON_3A)
+ 
+ /* ISA has 3 operand r6 fused madd instructions of the form
+    'c = c [+-] (a * b)'.  */
--- gcc-6-6.4.0.orig/debian/patches/mips-madd4.diff
+++ gcc-6-6.4.0/debian/patches/mips-madd4.diff
@@ -0,0 +1,307 @@
+From eb5c0cb6c16d435f6797cd934ceaac73ac7db52c Mon Sep 17 00:00:00 2001
+From: clm <clm@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Fri, 20 Jan 2017 01:05:25 +0000
+Subject: [PATCH] gcc/ 2017-01-19  Matthew Fortune 
+ <matthew.fortune@imgtec.com> 	    Yunqiang Su  <yunqiang.su@imgtec.com>
+
+	* config.gcc (supported_defaults): Add madd4.
+	(with_madd4): Add validation.
+	(all_defaults): Add madd4.
+	* config/mips/mips.opt (mmadd4): New option.
+	* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
+	mmadd4.
+	(TARGET_CPU_CPP_BUILTINS): Add builtin_define for
+	__mips_no_madd4.
+	(ISA_HAS_UNFUSED_MADD4): Gate with mips_madd4.
+	(ISA_HAS_FUSED_MADD4): Likewise.
+	* gcc/doc/invoke.texi (-mmadd4): Document the new option.
+	* gcc/doc/install.texi (--with-madd4): Document the new option.
+
+gcc/testsuite/
+2017-01-19  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* gcc.target/mips/madd4-1.c: New file.
+	* gcc.target/mips/madd4-2.c: Likewise.
+	* gcc.target/mips/mips.exp (mips_option_groups): Add ghost option
+	HAS_MADD4.
+	(mips_option_groups): Add -m[no-]madd4.
+	(mips-dg-init): Detect default -mno-madd4.
+	(mips-dg-options): Handle HAS_MADD4 arch upgrade/downgrade.
+	* gcc.target/mips/mips-ps-type.c: Add -mmadd4 test option.
+	* gcc.target/mips/mips-ps-type-2.c: Likewise.
+	* gcc.target/mips/nmadd-1.c: Likewise.
+	* gcc.target/mips/nmadd-2.c: Likewise.
+	* gcc.target/mips/nmadd-3.c: Likewise.
+
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244676 138bc75d-0d04-0410-961f-82ee72b054a4
+---
+ gcc/ChangeLog                                  | 16 ++++++++++++++++
+ gcc/config.gcc                                 | 19 +++++++++++++++++--
+ gcc/config/mips/mips.h                         | 12 +++++++++---
+ gcc/config/mips/mips.opt                       |  4 ++++
+ gcc/doc/install.texi                           | 14 ++++++++++++++
+ gcc/doc/invoke.texi                            |  8 +++++++-
+ gcc/testsuite/ChangeLog                        | 15 +++++++++++++++
+ gcc/testsuite/gcc.target/mips/madd4-1.c        | 14 ++++++++++++++
+ gcc/testsuite/gcc.target/mips/madd4-2.c        | 14 ++++++++++++++
+ gcc/testsuite/gcc.target/mips/mips-ps-type-2.c |  2 +-
+ gcc/testsuite/gcc.target/mips/mips-ps-type.c   |  2 +-
+ gcc/testsuite/gcc.target/mips/mips.exp         | 12 +++++++++++-
+ gcc/testsuite/gcc.target/mips/nmadd-1.c        |  2 +-
+ gcc/testsuite/gcc.target/mips/nmadd-2.c        |  2 +-
+ gcc/testsuite/gcc.target/mips/nmadd-3.c        |  2 +-
+ 15 files changed, 126 insertions(+), 12 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/mips/madd4-1.c
+ create mode 100644 gcc/testsuite/gcc.target/mips/madd4-2.c
+
+Index: b/src/gcc/config.gcc
+===================================================================
+--- a/src/gcc/config.gcc
++++ b/src/gcc/config.gcc
+@@ -3976,7 +3976,7 @@ case "${target}" in
+ 		;;
+ 
+ 	mips*-*-*)
+-		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1"
++		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 madd4"
+ 
+ 		case ${with_float} in
+ 		"" | soft | hard)
+@@ -4114,6 +4114,21 @@ case "${target}" in
+ 			exit 1
+ 			;;
+ 		esac
++
++		case ${with_madd4} in
++		yes)
++			with_madd4=madd4
++			;;
++		no)
++			with_madd4=no-madd4
++			;;
++		"")
++			;;
++		*)
++			echo "Unknown madd4 type used in --with-madd4" 1>&2
++			exit 1
++			;;
++		esac
+ 		;;
+ 
+ 	nds32*-*-*)
+@@ -4547,7 +4562,7 @@ case ${target} in
+ esac
+ 
+ t=
+-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1"
++all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4"
+ for option in $all_defaults
+ do
+ 	eval "val=\$with_"`echo $option | sed s/-/_/g`
+Index: b/src/gcc/config/mips/mips.h
+===================================================================
+--- a/src/gcc/config/mips/mips.h
++++ b/src/gcc/config/mips/mips.h
+@@ -621,6 +621,8 @@ struct mips_cpu_info {
+ 	builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE");		\
+       if (!ISA_HAS_LXC1_SXC1)						\
+ 	builtin_define ("__mips_no_lxc1_sxc1");				\
++      if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4)		\
++	builtin_define ("__mips_no_madd4");				\
+     }									\
+   while (0)
+ 
+@@ -850,7 +852,8 @@ struct mips_cpu_info {
+   {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
+   {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
+   {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" },			\
+-  {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" } \
++  {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \
++  {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" } \
+ 
+ /* A spec that infers the:
+    -mnan=2008 setting from a -mips argument,
+@@ -1041,11 +1044,14 @@ struct mips_cpu_info {
+ 
+ /* ISA has 4 operand fused madd instructions of the form
+    'd = [+-] (a * b [+-] c)'.  */
+-#define ISA_HAS_FUSED_MADD4	(TARGET_MIPS8000 || TARGET_LOONGSON_3A)
++#define ISA_HAS_FUSED_MADD4	(mips_madd4				\
++				 && (TARGET_MIPS8000			\
++				     || TARGET_LOONGSON_3A))
+ 
+ /* ISA has 4 operand unfused madd instructions of the form
+    'd = [+-] (a * b [+-] c)'.  */
+-#define ISA_HAS_UNFUSED_MADD4	(ISA_HAS_FP4				\
++#define ISA_HAS_UNFUSED_MADD4	(mips_madd4				\
++				 && ISA_HAS_FP4				\
+ 				 && !TARGET_MIPS8000			\
+ 				 && !TARGET_LOONGSON_3A)
+ 
+Index: b/src/gcc/config/mips/mips.opt
+===================================================================
+--- a/src/gcc/config/mips/mips.opt
++++ b/src/gcc/config/mips/mips.opt
+@@ -388,6 +388,10 @@ mlxc1-sxc1
+ Target Report Var(mips_lxc1_sxc1) Init(1)
+ Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable.
+ 
++mmadd4
++Target Report Var(mips_madd4) Init(1)
++Use 4-operand madd.s/madd.d and related instructions where applicable.
++
+ mtune=
+ Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value)
+ -mtune=PROCESSOR	Optimize the output for PROCESSOR.
+Index: b/src/gcc/testsuite/gcc.target/mips/madd4-1.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/mips/madd4-1.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-ffast-math -mno-madd4 (HAS_MADD4) -mhard-float" } */
++/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
++/* { dg-final { scan-assembler-not "\tmadd.s\t" } } */
++
++#ifndef __mips_no_madd4
++#error missing definition of __mips_no_madd4
++#endif
++
++NOMIPS16 float
++madd4 (float f, float g, float h)
++{
++  return (f * g) + h;
++}
+Index: b/src/gcc/testsuite/gcc.target/mips/madd4-2.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/mips/madd4-2.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-ffast-math -mmadd4 (HAS_MADD4) -mhard-float" } */
++/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
++/* { dg-final { scan-assembler "\tmadd.s\t" } } */
++
++#ifdef __mips_no_madd4
++#error unexpected definition of __mips_no_madd4
++#endif
++
++NOMIPS16 float
++madd4 (float f, float g, float h)
++{
++  return (f * g) + h;
++}
+Index: b/src/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c
++++ b/src/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c
+@@ -1,7 +1,7 @@
+ /* Test v2sf calculations.  The nmadd and nmsub patterns need
+    -ffinite-math-only.  */
+ /* { dg-do compile } */
+-/* { dg-options "(HAS_MADDPS) -mgp32 -mpaired-single -ffinite-math-only forbid_cpu=octeon.*" } */
++/* { dg-options "(HAS_MADDPS) -mmadd4 -mgp32 -mpaired-single -ffinite-math-only forbid_cpu=octeon.*" } */
+ /* { dg-skip-if "nmadd and nmsub need combine" { *-*-* } { "-O0" } { "" } } */
+ /* { dg-final { scan-assembler "\tcvt.ps.s\t" } } */
+ /* { dg-final { scan-assembler "\tmov.ps\t" } } */
+Index: b/src/gcc/testsuite/gcc.target/mips/mips-ps-type.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/mips-ps-type.c
++++ b/src/gcc/testsuite/gcc.target/mips/mips-ps-type.c
+@@ -1,7 +1,7 @@
+ /* Test v2sf calculations.  The nmadd and nmsub patterns need
+    -ffinite-math-only.  */
+ /* { dg-do compile } */ 
+-/* { dg-options "-mpaired-single -mgp64 -ffinite-math-only forbid_cpu=octeon.*" } */
++/* { dg-options "-mpaired-single -mmadd4 -mgp64 -ffinite-math-only forbid_cpu=octeon.*" } */
+ /* { dg-skip-if "nmadd and nmsub need combine" { *-*-* } { "-O0" } { "" } } */
+ /* { dg-final { scan-assembler "\tcvt.ps.s\t" } } */
+ /* { dg-final { scan-assembler "\tmov.ps\t" } } */
+Index: b/src/gcc/testsuite/gcc.target/mips/mips.exp
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/mips.exp
++++ b/src/gcc/testsuite/gcc.target/mips/mips.exp
+@@ -256,6 +256,7 @@ set mips_option_groups {
+     ldc "HAS_LDC"
+     movn "HAS_MOVN"
+     madd "HAS_MADD"
++    madd4_ghost "HAS_MADD4"
+     maddps "HAS_MADDPS"
+     lsa "(|!)HAS_LSA"
+     lxc1 "HAS_LXC1"
+@@ -283,6 +284,7 @@ foreach option {
+     local-sdata
+     long-calls
+     lxc1-sxc1
++    madd4
+     paired-single
+     plt
+     shared
+@@ -822,6 +824,12 @@ proc mips-dg-init {} {
+ 	    "-mlxc1-sxc1"
+ 	    #endif
+ 
++	    #ifdef __mips_no_madd4
++	    "-mno-madd4"
++	    #else
++	    "-mmadd4"
++	    #endif
++
+ 	    #ifdef __mips_synci
+ 	    "-msynci",
+ 	    #else
+@@ -1132,6 +1140,7 @@ proc mips-dg-options { args } {
+ 	#
+ 	} elseif { $isa < 4
+ +		   && ([mips_have_test_option_p options "HAS_LXC1"]
+++		       || [mips_have_test_option_p options "HAS_MADD4"]
+ +		       || [mips_have_test_option_p options "HAS_MOVN"]) } {
+ 	    mips_make_test_option options "-mips4"
+         # We need MIPS III or higher for:
+@@ -1174,8 +1183,9 @@ proc mips-dg-options { args } {
+ 		       || [mips_have_test_option_p options "-mfix-r10000"]
+ 		       || [mips_have_test_option_p options "NOT_HAS_DMUL"]
+ 		       || [mips_have_test_option_p options "HAS_LXC1"]
+-		       || [mips_have_test_option_p options "HAS_MOVN"]
+ 		       || [mips_have_test_option_p options "HAS_MADD"]
++		       || [mips_have_test_option_p options "HAS_MADD4"]
++		       || [mips_have_test_option_p options "HAS_MOVN"]
+ 		       || [mips_have_test_option_p options "-mpaired-single"]
+ 		       || [mips_have_test_option_p options "-mnan=legacy"]
+ 		       || [mips_have_test_option_p options "-mabs=legacy"]
+Index: b/src/gcc/testsuite/gcc.target/mips/nmadd-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/nmadd-1.c
++++ b/src/gcc/testsuite/gcc.target/mips/nmadd-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-ffast-math isa=4 -mhard-float" } */
++/* { dg-options "-ffast-math -mmadd4 isa=4 -mhard-float" } */
+ /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+ /* { dg-final { scan-assembler "\tnmadd.s\t" } } */
+ /* { dg-final { scan-assembler "\tnmadd.d\t" } } */
+Index: b/src/gcc/testsuite/gcc.target/mips/nmadd-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/nmadd-2.c
++++ b/src/gcc/testsuite/gcc.target/mips/nmadd-2.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-fno-fast-math -ffinite-math-only isa=4 -mhard-float" } */
++/* { dg-options "-fno-fast-math -ffinite-math-only -mmadd4 isa=4 -mhard-float" } */
+ /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+ /* { dg-final { scan-assembler "\tnmadd.s\t" } } */
+ /* { dg-final { scan-assembler "\tnmadd.d\t" } } */
+Index: b/src/gcc/testsuite/gcc.target/mips/nmadd-3.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/nmadd-3.c
++++ b/src/gcc/testsuite/gcc.target/mips/nmadd-3.c
+@@ -1,7 +1,7 @@
+ /* The same code as nmadd-2.c, but compiled with -fno-finite-math-only.
+    We can't use nmadd and nmsub in that case.  */
+ /* { dg-do compile } */
+-/* { dg-options "-fno-fast-math -fno-finite-math-only isa=4 -mhard-float" } */
++/* { dg-options "-fno-fast-math -fno-finite-math-only -mmadd4 isa=4 -mhard-float" } */
+ /* { dg-final { scan-assembler-not "\tnmadd" } } */
+ /* { dg-final { scan-assembler-not "\tnmsub" } } */
+ 
--- gcc-6-6.4.0.orig/debian/patches/mips-pr78176-add-mlxc1-sxc1.diff
+++ gcc-6-6.4.0/debian/patches/mips-pr78176-add-mlxc1-sxc1.diff
@@ -0,0 +1,321 @@
+From fccc4b5408942b92bc00bc053f4da9af2109557c Mon Sep 17 00:00:00 2001
+From: mpf <mpf@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Thu, 19 Jan 2017 16:05:59 +0000
+Subject: [PATCH] MIPS: PR target/78176 add -mlxc1-sxc1.
+
+gcc/
+
+	PR target/78176
+	* config.gcc (supported_defaults): Add lxc1-sxc1.
+	(with_lxc1_sxc1): Add validation.
+	(all_defaults): Add lxc1-sxc1.
+	* config/mips/mips.opt (mlxc1-sxc1): New option.
+	* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
+	mlxc1-sxc1.
+	(TARGET_CPU_CPP_BUILTINS): Add builtin_define for
+	__mips_no_lxc1_sxc1.
+	(ISA_HAS_LXC1_SXC1): Gate with mips_lxc1_sxc1.
+	* gcc/doc/invoke.texi (-mlxc1-sxc1): Document the new option.
+	* doc/install.texi (--with-lxc1-sxc1): Document the new option.
+
+gcc/testsuite/
+
+	* gcc.target/mips/lxc1-sxc1-1.c: New file.
+	* gcc.target/mips/lxc1-sxc1-2.c: Likewise.
+	* gcc.target/mips/mips.exp (mips_option_groups): Add ghost option
+	HAS_LXC1.
+	(mips_option_groups): Add -m[no-]lxc1-sxc1.
+	(mips-dg-init): Detect default -mno-lxc1-sxc1.
+	(mips-dg-options): Handle HAS_LXC1 arch upgrade/downgrade.
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244640 138bc75d-0d04-0410-961f-82ee72b054a4
+---
+ gcc/ChangeLog                               | 15 ++++++++
+ gcc/config.gcc                              | 19 ++++++++-
+ gcc/config/mips/mips.h                      |  8 +++-
+ gcc/config/mips/mips.opt                    |  4 ++
+ gcc/doc/install.texi                        | 19 +++++++++
+ gcc/doc/invoke.texi                         |  6 +++
+ gcc/testsuite/ChangeLog                     | 11 ++++++
+ gcc/testsuite/gcc.target/mips/lxc1-sxc1-1.c | 60 +++++++++++++++++++++++++++++
+ gcc/testsuite/gcc.target/mips/lxc1-sxc1-2.c | 60 +++++++++++++++++++++++++++++
+ gcc/testsuite/gcc.target/mips/mips.exp      | 12 +++++-
+ 10 files changed, 209 insertions(+), 5 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/mips/lxc1-sxc1-1.c
+ create mode 100644 gcc/testsuite/gcc.target/mips/lxc1-sxc1-2.c
+
+Index: b/src/gcc/config.gcc
+===================================================================
+--- a/src/gcc/config.gcc
++++ b/src/gcc/config.gcc
+@@ -3976,7 +3976,7 @@ case "${target}" in
+ 		;;
+ 
+ 	mips*-*-*)
+-		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci"
++		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1"
+ 
+ 		case ${with_float} in
+ 		"" | soft | hard)
+@@ -4099,6 +4099,21 @@ case "${target}" in
+ 			exit 1
+ 			;;
+ 		esac
++
++		case ${with_lxc1_sxc1} in
++		yes)
++			with_lxc1_sxc1=lxc1-sxc1
++			;;
++		no)
++			with_lxc1_sxc1=no-lxc1-sxc1
++			;;
++		"")
++			;;
++		*)
++			echo "Unknown lxc1-sxc1 type used in --with-lxc1-sxc1" 1>&2
++			exit 1
++			;;
++		esac
+ 		;;
+ 
+ 	nds32*-*-*)
+@@ -4532,7 +4547,7 @@ case ${target} in
+ esac
+ 
+ t=
+-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls"
++all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1"
+ for option in $all_defaults
+ do
+ 	eval "val=\$with_"`echo $option | sed s/-/_/g`
+Index: b/src/gcc/config/mips/mips.h
+===================================================================
+--- a/src/gcc/config/mips/mips.h
++++ b/src/gcc/config/mips/mips.h
+@@ -619,6 +619,8 @@ struct mips_cpu_info {
+ 									\
+       if (TARGET_CACHE_BUILTIN)						\
+ 	builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE");		\
++      if (!ISA_HAS_LXC1_SXC1)						\
++	builtin_define ("__mips_no_lxc1_sxc1");				\
+     }									\
+   while (0)
+ 
+@@ -847,7 +849,8 @@ struct mips_cpu_info {
+   {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
+   {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
+   {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
+-  {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
++  {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" },			\
++  {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" } \
+ 
+ /* A spec that infers the:
+    -mnan=2008 setting from a -mips argument,
+@@ -1011,7 +1014,8 @@ struct mips_cpu_info {
+ 
+ /* ISA has floating-point indexed load and store instructions
+    (LWXC1, LDXC1, SWXC1 and SDXC1).  */
+-#define ISA_HAS_LXC1_SXC1	ISA_HAS_FP4
++#define ISA_HAS_LXC1_SXC1	(ISA_HAS_FP4				\
++				 && mips_lxc1_sxc1)
+ 
+ /* ISA has paired-single instructions.  */
+ #define ISA_HAS_PAIRED_SINGLE	((ISA_MIPS64				\
+Index: b/src/gcc/config/mips/mips.opt
+===================================================================
+--- a/src/gcc/config/mips/mips.opt
++++ b/src/gcc/config/mips/mips.opt
+@@ -384,6 +384,10 @@ mlra
+ Target Report Var(mips_lra_flag) Init(1) Save
+ Use LRA instead of reload.
+ 
++mlxc1-sxc1
++Target Report Var(mips_lxc1_sxc1) Init(1)
++Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable.
++
+ mtune=
+ Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value)
+ -mtune=PROCESSOR	Optimize the output for PROCESSOR.
+Index: b/src/gcc/testsuite/gcc.target/mips/lxc1-sxc1-1.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/mips/lxc1-sxc1-1.c
+@@ -0,0 +1,60 @@
++/* { dg-options "(HAS_LXC1) -mno-lxc1-sxc1" } */
++/* { dg-final { scan-assembler-not "\tldxc1\t" } } */
++/* { dg-final { scan-assembler-not "\tsdxc1\t" } } */
++
++#ifndef __mips_no_lxc1_sxc1
++#error missing definition of __mips_no_lxc1_sxc1
++#endif
++
++double ldexp(double x, int exp);
++
++typedef struct
++{
++  double** rows;
++} d_mat_struct;
++
++typedef d_mat_struct d_mat_t[1];
++
++#define d_mat_entry(mat,i,j) (*((mat)->rows[i] + (j)))
++
++double __attribute__((noinline))
++ldxc1_test (int kappa, int zeros, double ctt, int* expo, d_mat_t r, double* s)
++{
++  int kappa2 = kappa;
++  double tmp = 0.0;
++
++  do
++    {
++      kappa--;
++      if (kappa > zeros + 1)
++	{
++	  tmp = d_mat_entry(r, kappa - 1, kappa - 1) * ctt;
++	  tmp = ldexp(tmp, (expo[kappa - 1] - expo[kappa2]));
++	}
++    }
++  while ((kappa >= zeros + 2) && (s[kappa - 1] <= tmp));
++
++  return tmp;
++}
++
++#define SIZE 20
++
++int main(void)
++{
++  int kappa = SIZE - 1;
++  int zeros = 1;
++  double ctt = 2;
++
++  int expo[SIZE] = {0};
++  double s[SIZE] = {0};
++  double rows_data[SIZE][SIZE] = {0};
++  double* rows[SIZE];
++
++  for (int i = 0; i < SIZE; i++)
++    rows[i] = rows_data[i];
++
++  d_mat_t r = { rows };
++
++  ldxc1_test(kappa, zeros, ctt, expo, r, s);
++  return 0;
++}
+Index: b/src/gcc/testsuite/gcc.target/mips/lxc1-sxc1-2.c
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/mips/lxc1-sxc1-2.c
+@@ -0,0 +1,60 @@
++/* { dg-options "(HAS_LXC1) -mlxc1-sxc1" } */
++/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
++/* { dg-final { scan-assembler "\tldxc1\t" } } */
++
++#ifdef __mips_no_lxc1_sxc1
++#error unexpected definition of __mips_no_lxc1_sxc1
++#endif
++
++double ldexp(double x, int exp);
++
++typedef struct
++{
++  double** rows;
++} d_mat_struct;
++
++typedef d_mat_struct d_mat_t[1];
++
++#define d_mat_entry(mat,i,j) (*((mat)->rows[i] + (j)))
++
++double __attribute__((noinline))
++ldxc1_test (int kappa, int zeros, double ctt, int* expo, d_mat_t r, double* s)
++{
++  int kappa2 = kappa;
++  double tmp = 0.0;
++
++  do
++    {
++      kappa--;
++      if (kappa > zeros + 1)
++	{
++	  tmp = d_mat_entry(r, kappa - 1, kappa - 1) * ctt;
++	  tmp = ldexp(tmp, (expo[kappa - 1] - expo[kappa2]));
++	}
++    }
++  while ((kappa >= zeros + 2) && (s[kappa - 1] <= tmp));
++
++  return tmp;
++}
++
++#define SIZE 20
++
++int main(void)
++{
++  int kappa = SIZE - 1;
++  int zeros = 1;
++  double ctt = 2;
++
++  int expo[SIZE] = {0};
++  double s[SIZE] = {0};
++  double rows_data[SIZE][SIZE] = {0};
++  double* rows[SIZE];
++
++  for (int i = 0; i < SIZE; i++)
++    rows[i] = rows_data[i];
++
++  d_mat_t r = { rows };
++
++  ldxc1_test(kappa, zeros, ctt, expo, r, s);
++  return 0;
++}
+Index: b/src/gcc/testsuite/gcc.target/mips/mips.exp
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/mips/mips.exp
++++ b/src/gcc/testsuite/gcc.target/mips/mips.exp
+@@ -258,6 +258,7 @@ set mips_option_groups {
+     madd "HAS_MADD"
+     maddps "HAS_MADDPS"
+     lsa "(|!)HAS_LSA"
++    lxc1 "HAS_LXC1"
+     section_start "-Wl,--section-start=.*"
+     frame-header "-mframe-header-opt|-mno-frame-header-opt"
+     stack-protector "-fstack-protector"
+@@ -281,6 +282,7 @@ foreach option {
+     gpopt
+     local-sdata
+     long-calls
++    lxc1-sxc1
+     paired-single
+     plt
+     shared
+@@ -814,6 +816,12 @@ proc mips-dg-init {} {
+ 	    "-mno-smartmips",
+ 	    #endif
+ 
++	    #ifdef __mips_no_lxc1_sxc1
++	    "-mno-lxc1-sxc1",
++	    #else
++	    "-mlxc1-sxc1"
++	    #endif
++
+ 	    #ifdef __mips_synci
+ 	    "-msynci",
+ 	    #else
+@@ -1122,8 +1130,9 @@ proc mips-dg-options { args } {
+         # We need MIPS IV or higher for:
+ 	#
+ 	#
+-	} elseif { $isa < 3
+-		   && [mips_have_test_option_p options "HAS_MOVN"] } {
++	} elseif { $isa < 4
+++		   && ([mips_have_test_option_p options "HAS_LXC1"]
+++		       || [mips_have_test_option_p options "HAS_MOVN"]) } {
+ 	    mips_make_test_option options "-mips4"
+         # We need MIPS III or higher for:
+ 	#
+@@ -1164,6 +1173,7 @@ proc mips-dg-options { args } {
+ 		       || [mips_have_test_option_p options "-mfp32"]
+ 		       || [mips_have_test_option_p options "-mfix-r10000"]
+ 		       || [mips_have_test_option_p options "NOT_HAS_DMUL"]
++		       || [mips_have_test_option_p options "HAS_LXC1"]
+ 		       || [mips_have_test_option_p options "HAS_MOVN"]
+ 		       || [mips_have_test_option_p options "HAS_MADD"]
+ 		       || [mips_have_test_option_p options "-mpaired-single"]
--- gcc-6-6.4.0.orig/debian/patches/note-gnu-stack.diff
+++ gcc-6-6.4.0/debian/patches/note-gnu-stack.diff
@@ -0,0 +1,186 @@
+# DP: Add .note.GNU-stack sections for gcc's crt files, libffi and boehm-gc
+# DP: Taken from FC.
+
+gcc/
+
+2004-09-20  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/rs6000/ppc-asm.h: Add .note.GNU-stack section also
+	on ppc64-linux.
+
+	* config/ia64/lib1funcs.asm: Add .note.GNU-stack section on
+	ia64-linux.
+	* config/ia64/crtbegin.asm: Likewise.
+	* config/ia64/crtend.asm: Likewise.
+	* config/ia64/crti.asm: Likewise.
+	* config/ia64/crtn.asm: Likewise.
+
+2004-05-14  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/ia64/linux.h (TARGET_ASM_FILE_END): Define.
+
+boehm-gc/
+
+2005-02-08  Jakub Jelinek  <jakub@redhat.com>
+
+	* ia64_save_regs_in_stack.s: Moved to...
+	* ia64_save_regs_in_stack.S: ... this.  Add .note.GNU-stack
+	on Linux.
+
+libffi/
+
+2007-05-11  Daniel Jacobowitz  <dan@debian.org>
+
+	* src/arm/sysv.S: Fix ARM comment marker.
+
+2005-02-08  Jakub Jelinek  <jakub@redhat.com>
+
+	* src/alpha/osf.S: Add .note.GNU-stack on Linux.
+	* src/s390/sysv.S: Likewise.
+	* src/powerpc/linux64.S: Likewise.
+	* src/powerpc/linux64_closure.S: Likewise.
+	* src/powerpc/ppc_closure.S: Likewise.
+	* src/powerpc/sysv.S: Likewise.
+	* src/x86/unix64.S: Likewise.
+	* src/x86/sysv.S: Likewise.
+	* src/sparc/v8.S: Likewise.
+	* src/sparc/v9.S: Likewise.
+	* src/m68k/sysv.S: Likewise.
+	* src/ia64/unix.S: Likewise.
+	* src/arm/sysv.S: Likewise.
+
+---
+ boehm-gc/ia64_save_regs_in_stack.S   |   15 +++++++++++++++
+ boehm-gc/ia64_save_regs_in_stack.s   |   12 ------------
+ gcc/config/ia64/linux.h              |    3 +++
+ gcc/config/rs6000/ppc-asm.h          |    2 +-
+ libgcc/config/ia64/crtbegin.S        |    4 ++++
+ libgcc/config/ia64/crtend.S          |    4 ++++
+ libgcc/config/ia64/crti.S            |    4 ++++
+ libgcc/config/ia64/crtn.S            |    4 ++++
+ libgcc/config/ia64/lib1funcs.S       |    4 ++++
+ 9 files changed, 39 insertions(+), 13 deletions(-)
+
+Index: b/src/boehm-gc/ia64_save_regs_in_stack.s
+===================================================================
+--- a/src/boehm-gc/ia64_save_regs_in_stack.s
++++ /dev/null
+@@ -1,12 +0,0 @@
+-        .text
+-        .align 16
+-        .global GC_save_regs_in_stack
+-        .proc GC_save_regs_in_stack
+-GC_save_regs_in_stack:
+-        .body
+-        flushrs
+-        ;;
+-        mov r8=ar.bsp
+-        br.ret.sptk.few rp
+-        .endp GC_save_regs_in_stack
+-
+Index: b/src/boehm-gc/ia64_save_regs_in_stack.S
+===================================================================
+--- /dev/null
++++ b/src/boehm-gc/ia64_save_regs_in_stack.S
+@@ -0,0 +1,15 @@
++        .text
++        .align 16
++        .global GC_save_regs_in_stack
++        .proc GC_save_regs_in_stack
++GC_save_regs_in_stack:
++        .body
++        flushrs
++        ;;
++        mov r8=ar.bsp
++        br.ret.sptk.few rp
++        .endp GC_save_regs_in_stack
++
++#ifdef __linux__
++	.section .note.GNU-stack,"",@progbits
++#endif
+Index: b/src/libgcc/config/ia64/crtbegin.S
+===================================================================
+--- a/src/libgcc/config/ia64/crtbegin.S
++++ b/src/libgcc/config/ia64/crtbegin.S
+@@ -252,3 +252,7 @@ __do_jv_register_classes:
+ .weak __cxa_finalize
+ #endif
+ .weak _Jv_RegisterClasses
++
++#ifdef __linux__
++.section .note.GNU-stack; .previous
++#endif
+Index: b/src/libgcc/config/ia64/crtend.S
+===================================================================
+--- a/src/libgcc/config/ia64/crtend.S
++++ b/src/libgcc/config/ia64/crtend.S
+@@ -119,3 +119,7 @@ __do_global_ctors_aux:
+ 
+ 	br.ret.sptk.many rp
+ 	.endp __do_global_ctors_aux
++
++#ifdef __linux__
++.section .note.GNU-stack; .previous
++#endif
+Index: b/src/libgcc/config/ia64/crti.S
+===================================================================
+--- a/src/libgcc/config/ia64/crti.S
++++ b/src/libgcc/config/ia64/crti.S
+@@ -51,3 +51,7 @@ _fini:
+ 	.body
+ 
+ # end of crti.S
++
++#ifdef __linux__
++.section .note.GNU-stack; .previous
++#endif
+Index: b/src/libgcc/config/ia64/crtn.S
+===================================================================
+--- a/src/libgcc/config/ia64/crtn.S
++++ b/src/libgcc/config/ia64/crtn.S
+@@ -41,3 +41,7 @@
+ 	br.ret.sptk.many b0
+ 
+ # end of crtn.S
++
++#ifdef __linux__
++.section .note.GNU-stack; .previous
++#endif
+Index: b/src/libgcc/config/ia64/lib1funcs.S
+===================================================================
+--- a/src/libgcc/config/ia64/lib1funcs.S
++++ b/src/libgcc/config/ia64/lib1funcs.S
+@@ -793,3 +793,7 @@ __floattitf:
+ 	.endp __floattitf
+ #endif
+ #endif
++
++#ifdef __linux__
++.section .note.GNU-stack; .previous
++#endif
+Index: b/src/gcc/config/ia64/linux.h
+===================================================================
+--- a/src/gcc/config/ia64/linux.h
++++ b/src/gcc/config/ia64/linux.h
+@@ -79,5 +79,8 @@ do {						\
+ #undef TARGET_INIT_LIBFUNCS
+ #define TARGET_INIT_LIBFUNCS ia64_soft_fp_init_libfuncs
+ 
++#undef TARGET_ASM_FILE_END
++#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
++
+ /* Define this to be nonzero if static stack checking is supported.  */
+ #define STACK_CHECK_STATIC_BUILTIN 1
+Index: b/src/gcc/config/rs6000/ppc-asm.h
+===================================================================
+--- a/src/gcc/config/rs6000/ppc-asm.h
++++ b/src/gcc/config/rs6000/ppc-asm.h
+@@ -375,7 +375,7 @@ GLUE(.L,name): \
+ #endif
+ #endif
+ 
+-#if defined __linux__ && !defined __powerpc64__
++#if defined __linux__
+ 	.section .note.GNU-stack
+ 	.previous
+ #endif
--- gcc-6-6.4.0.orig/debian/patches/powerpc_nofprs.diff
+++ gcc-6-6.4.0/debian/patches/powerpc_nofprs.diff
@@ -0,0 +1,75 @@
+--- a/src/libgcc/config/rs6000/crtsavfpr.S
++++ b/src/libgcc/config/rs6000/crtsavfpr.S
+@@ -33,6 +33,7 @@
+ 
+ /* On PowerPC64 Linux, these functions are provided by the linker.  */
+ #ifndef __powerpc64__
++#ifndef __NO_FPRS__
+ 
+ /* Routines for saving floating point registers, called by the compiler.  */
+ /* Called with r11 pointing to the stack header word of the caller of the */
+@@ -79,3 +80,4 @@
+ CFI_ENDPROC
+ 
+ #endif
++#endif
+--- a/src/libgcc/config/rs6000/crtresfpr.S
++++ b/src/libgcc/config/rs6000/crtresfpr.S
+@@ -33,6 +33,7 @@
+ 
+ /* On PowerPC64 Linux, these functions are provided by the linker.  */
+ #ifndef __powerpc64__
++#ifndef __NO_FPRS__
+ 
+ /* Routines for restoring floating point registers, called by the compiler.  */
+ /* Called with r11 pointing to the stack header word of the caller of the */
+@@ -79,3 +80,4 @@
+ CFI_ENDPROC
+ 
+ #endif
++#endif
+--- a/src/libgcc/config/rs6000/crtresxfpr.S
++++ b/src/libgcc/config/rs6000/crtresxfpr.S
+@@ -33,6 +33,7 @@
+ 
+ /* On PowerPC64 Linux, these functions are provided by the linker.  */
+ #ifndef __powerpc64__
++#ifndef __NO_FPRS__
+ 
+ /* Routines for restoring floating point registers, called by the compiler.  */
+ /* Called with r11 pointing to the stack header word of the caller of the */
+@@ -124,3 +125,4 @@
+ CFI_ENDPROC
+ 
+ #endif
++#endif
+--- a/src/libgcc/config/rs6000/crtsavevr.S	2013-03-13 22:25:25.802681336 +0000
++++ b/src/libgcc/config/rs6000/crtsavevr.S	2013-03-13 22:26:21.054695066 +0000
+@@ -24,6 +24,7 @@
+ 
+ /* On PowerPC64 Linux, these functions are provided by the linker.  */
+ #ifndef __powerpc64__
++#ifndef __NO_FPRS__
+ 
+ #undef __ALTIVEC__
+ #define __ALTIVEC__ 1
+@@ -85,3 +86,4 @@
+ CFI_ENDPROC
+ 
+ #endif
++#endif
+--- a/src/libgcc/config/rs6000/crtrestvr.S	2013-03-13 22:25:28.394681980 +0000
++++ b/src/libgcc/config/rs6000/crtrestvr.S	2013-03-13 22:26:21.058695067 +0000
+@@ -24,6 +24,7 @@
+ 
+ /* On PowerPC64 Linux, these functions are provided by the linker.  */
+ #ifndef __powerpc64__
++#ifndef __NO_FPRS__
+ 
+ #undef __ALTIVEC__
+ #define __ALTIVEC__ 1
+@@ -85,3 +86,4 @@
+ CFI_ENDPROC
+ 
+ #endif
++#endif
--- gcc-6-6.4.0.orig/debian/patches/powerpc_remove_many.diff
+++ gcc-6-6.4.0/debian/patches/powerpc_remove_many.diff
@@ -0,0 +1,32 @@
+# DP: Subject: [PATCH] remove -many on __SPE__ target
+# DP: this helps to to detect opcodes which are not part of the current
+# DP: CPU because without -many gas won't touch them. This currently could
+# DP: break the kernel build as the 603 on steroids cpus use performance
+# DP: counter opcodes which are not available on the steroid less 603 core.
+
+--- a/src/gcc/config/rs6000/rs6000.h
++++ b/src/gcc/config/rs6000/rs6000.h
+@@ -98,6 +98,12 @@
+ #define ASM_CPU_476_SPEC "-mpower4"
+ #endif
+ 
++#ifndef __SPE__
++#define ASM_CPU_SPU_MANY_NOT_SPE "-many"
++#else
++#define ASM_CPU_SPU_MANY_NOT_SPE
++#endif
++
+ /* Common ASM definitions used by ASM_SPEC among the various targets for
+    handling -mcpu=xxx switches.  There is a parallel list in driver-rs6000.c to
+    provide the default assembler options if the user uses -mcpu=native, so if
+@@ -170,7 +176,8 @@
+ %{mcpu=e500mc64: -me500mc64} \
+ %{maltivec: -maltivec} \
+ %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
+ %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \
+--many"
++" \
++ASM_CPU_SPU_MANY_NOT_SPE
+ 
+ #define CPP_DEFAULT_SPEC ""
+ 
--- gcc-6-6.4.0.orig/debian/patches/pr39491.diff
+++ gcc-6-6.4.0/debian/patches/pr39491.diff
@@ -0,0 +1,132 @@
+# DP: Proposed patch for PR libstdc++/39491.
+
+2009-04-16  Benjamin Kosnik  <bkoz@redhat.com>
+
+	* src/math_stubs_long_double.cc (__signbitl): Add for hppa linux only.
+
+Index: a/src/libstdc++-v3/src/math_stubs_long_double.cc
+===================================================================
+--- a/src/libstdc++-v3/src/math_stubs_long_double.cc	(revision 146216)
++++ b/src/libstdc++-v3/src/math_stubs_long_double.cc	(working copy)
+@@ -213,4 +221,111 @@
+     return tanh((double) x);
+   }
+ #endif
++
++  // From libmath/signbitl.c
++  // XXX ABI mistakenly exported
++#if defined (__hppa__) && defined (__linux__)
++# include <endian.h>
++# include <float.h>
++
++typedef unsigned int U_int32_t __attribute ((mode (SI)));
++typedef int Int32_t __attribute ((mode (SI)));
++typedef unsigned int U_int64_t __attribute ((mode (DI)));
++typedef int Int64_t __attribute ((mode (DI)));
++
++#if BYTE_ORDER == BIG_ENDIAN
++typedef union
++{
++  long double value;
++  struct
++  {
++    unsigned int sign_exponent:16;
++    unsigned int empty:16;
++    U_int32_t msw;
++    U_int32_t lsw;
++  } parts;
++} ieee_long_double_shape_type;
++#endif
++#if BYTE_ORDER == LITTLE_ENDIAN
++typedef union
++{
++  long double value;
++  struct
++  {
++    U_int32_t lsw;
++    U_int32_t msw;
++    unsigned int sign_exponent:16;
++    unsigned int empty:16;
++  } parts;
++} ieee_long_double_shape_type;
++#endif
++
++/* Get int from the exponent of a long double.  */
++#define GET_LDOUBLE_EXP(exp,d)                                  \
++do {                                                            \
++  ieee_long_double_shape_type ge_u;                             \
++  ge_u.value = (d);                                             \
++  (exp) = ge_u.parts.sign_exponent;                             \
++} while (0)
++
++#if BYTE_ORDER == BIG_ENDIAN
++typedef union
++{
++  long double value;
++  struct
++  {
++    U_int64_t msw;
++    U_int64_t lsw;
++  } parts64;
++  struct
++  {
++    U_int32_t w0, w1, w2, w3;
++  } parts32;
++} ieee_quad_double_shape_type;
++#endif
++
++#if BYTE_ORDER == LITTLE_ENDIAN
++typedef union
++{
++  long double value;
++  struct
++  {
++    U_int64_t lsw;
++    U_int64_t msw;
++  } parts64;
++  struct
++  {
++    U_int32_t w3, w2, w1, w0;
++  } parts32;
++} ieee_quad_double_shape_type;
++#endif
++
++/* Get most significant 64 bit int from a quad long double.  */
++#define GET_LDOUBLE_MSW64(msw,d)				\
++do {								\
++  ieee_quad_double_shape_type qw_u;				\
++  qw_u.value = (d);						\
++  (msw) = qw_u.parts64.msw;					\
++} while (0)
++
++int
++__signbitl (long double x)
++{
++#if LDBL_MANT_DIG == 113
++  Int64_t msw;
++
++  GET_LDOUBLE_MSW64 (msw, x);
++  return msw < 0;
++#else
++  Int32_t e;
++
++  GET_LDOUBLE_EXP (e, x);
++  return e & 0x8000;
++#endif
++}
++#endif
++
++#ifndef _GLIBCXX_HAVE___SIGNBITL
++
++#endif
+ } // extern "C"
+--- a/src/libstdc++-v3/config/abi/pre/gnu.ver~	2009-04-10 01:23:07.000000000 +0200
++++ b/src/libstdc++-v3/config/abi/pre/gnu.ver	2009-04-21 16:24:24.000000000 +0200
+@@ -635,6 +635,7 @@
+     sqrtf;
+     sqrtl;
+     copysignf;
++    __signbitl;
+ 
+    # GLIBCXX_ABI compatibility only.
+     # std::string
--- gcc-6-6.4.0.orig/debian/patches/pr47818.diff
+++ gcc-6-6.4.0/debian/patches/pr47818.diff
@@ -0,0 +1,24 @@
+# DP: Fix PR ada/47818: Pragma Assert is rejected with No_Implementation_Pragmas restriction.
+
+Index: b/src/gcc/ada/sem_prag.adb
+===================================================================
+--- a/src/gcc/ada/sem_prag.adb
++++ b/src/gcc/ada/sem_prag.adb
+@@ -16306,7 +16306,16 @@ package body Sem_Prag is
+             Type_Id : Node_Id;
+ 
+          begin
+-            GNAT_Pragma;
++            --  This could be a rewritten pragma Assert. If it is the case
++            --  then don't check restrictions, because they are different for
++            --  pragma Assert and were already checked.
++
++            if Nkind (Original_Node (N)) /= N_Pragma
++              or else Pragma_Name (Original_Node (N)) /= Name_Assert
++            then
++               GNAT_Pragma;
++            end if;
++
+             Check_At_Least_N_Arguments (2);
+             Check_At_Most_N_Arguments  (3);
+             Check_Optional_Identifier (Arg1, Name_Entity);
--- gcc-6-6.4.0.orig/debian/patches/pr64735-headers.diff
+++ gcc-6-6.4.0/debian/patches/pr64735-headers.diff
@@ -0,0 +1,60 @@
+--- a/src/libstdc++-v3/include/std/future
++++ b/src/libstdc++-v3/include/std/future
+@@ -183,7 +183,7 @@
+     async(_Fn&& __fn, _Args&&... __args);
+ 
+ #if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1) \
+-  && (ATOMIC_INT_LOCK_FREE > 1)
++  && ((ATOMIC_INT_LOCK_FREE > 1) || (defined(__ARM_EABI__) && !defined(__ARM_PCS_VFP)))
+ 
+   /// Base class and enclosing scope.
+   struct __future_base
+--- a/src/libstdc++-v3/libsupc++/exception_ptr.h
++++ b/src/libstdc++-v3/libsupc++/exception_ptr.h
+@@ -36,9 +36,11 @@
+ #include <bits/c++config.h>
+ #include <bits/exception_defines.h>
+ 
++#if !(defined(__ARM_EABI__) && !defined(__ARM_PCS_VFP))
+ #if ATOMIC_INT_LOCK_FREE < 2
+ #  error This platform does not support exception propagation.
+ #endif
++#endif
+ 
+ extern "C++" {
+ 
+--- a/src/libstdc++-v3/libsupc++/nested_exception.h
++++ b/src/libstdc++-v3/libsupc++/nested_exception.h
+@@ -39,9 +39,11 @@
+ #include <bits/c++config.h>
+ #include <bits/move.h>
+ 
++#if !(defined(__ARM_EABI__) && !defined(__ARM_PCS_VFP))
+ #if ATOMIC_INT_LOCK_FREE < 2
+ #  error This platform does not support exception propagation.
+ #endif
++#endif
+ 
+ extern "C++" {
+ 
+--- a/src/libstdc++-v3/libsupc++/exception
++++ b/src/libstdc++-v3/libsupc++/exception
+@@ -35,7 +35,9 @@
+ #pragma GCC visibility push(default)
+ 
+ #include <bits/c++config.h>
++#if !(defined(__ARM_EABI__) && !defined(__ARM_PCS_VFP))
+ #include <bits/atomic_lockfree_defines.h>
++#endif
+ 
+ extern "C++" {
+ 
+@@ -166,7 +168,7 @@
+ 
+ #pragma GCC visibility pop
+ 
+-#if (__cplusplus >= 201103L) && (ATOMIC_INT_LOCK_FREE > 1)
++#if (__cplusplus >= 201103L) && ((ATOMIC_INT_LOCK_FREE > 1) || (defined(__ARM_EABI__) && !defined(__ARM_PCS_VFP)))
+ #include <bits/exception_ptr.h>
+ #include <bits/nested_exception.h>
+ #endif
--- gcc-6-6.4.0.orig/debian/patches/pr64735.diff
+++ gcc-6-6.4.0/debian/patches/pr64735.diff
@@ -0,0 +1,1610 @@
+# DP: Proposed patch for PR libstdc++/64735
+
+commit e81e908deb699886e65cb4d614f6a0a1cf54662f
+Author: Jonathan Wakely <jwakely@redhat.com>
+Date:   Fri Dec 16 15:22:21 2016 +0000
+
+    PR64735 support exception propagation without atomics
+    
+    2016-11-09  Pauli Nieminen  <suokkos@gmail.com>
+    	    Jonathan Wakely  <jwakely@redhat.com>
+    
+    	PR libstdc++/64735
+    	* include/std/future: Remove check for ATOMIC_INT_LOCK_FREE
+    	* libsupc++/eh_atomics.h: New file for internal use only.
+    	(__eh_atomic_inc, __eh_atomic_dec): New.
+    	* libsupc++/eh_ptr.cc (exception_ptr::_M_addref)
+    	(exception_ptr::_M_release) (__gxx_dependent_exception_cleanup)
+    	(rethrow_exception): Use eh_atomics.h reference counting helpers.
+    	* libsupc++/eh_throw.cc (__gxx_exception_cleanup): Likewise.
+    	* libsupc++/eh_tm.cc (free_any_cxa_exception): Likewise.
+    	* libsupc++/exception: Remove check for ATOMIC_INT_LOCK_FREE.
+    	* libsupc++/exception_ptr.h: Likewise.
+    	* libsupc++/guard.cc: Include header for ATOMIC_INT_LOCK_FREE macro.
+    	* libsupc++/nested_exception.cc: Remove check for
+    	ATOMIC_INT_LOCK_FREE.
+    	* libsupc++/nested_exception.h: Likewise.
+    	* src/c++11/future.cc: Likewise.
+    	* testsuite/18_support/exception_ptr/*: Remove atomic builtins checks.
+    	* testsuite/18_support/nested_exception/*: Likewise.
+    	* testsuite/30_threads/async/*: Likewise.
+    	* testsuite/30_threads/future/*: Likewise.
+    	* testsuite/30_threads/headers/future/types_std_c++0x.cc: Likewise.
+    	* testsuite/30_threads/packaged_task/*: Likewise.
+    	* testsuite/30_threads/promise/*: Likewise.
+    	* testsuite/30_threads/shared_future/*: Likewise.
+
+#Index: b/src/libstdc++-v3/include/std/future
+#===================================================================
+#--- a/src/libstdc++-v3/include/std/future
+#+++ b/src/libstdc++-v3/include/std/future
+#@@ -182,8 +182,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
+#     future<__async_result_of<_Fn, _Args...>>
+#     async(_Fn&& __fn, _Args&&... __args);
+# 
+#-#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1) \
+#-  && (ATOMIC_INT_LOCK_FREE > 1)
+#+#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1)
+# 
+#   /// Base class and enclosing scope.
+#   struct __future_base
+#@@ -1745,7 +1744,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
+# 
+# #endif // _GLIBCXX_ASYNC_ABI_COMPAT
+# #endif // _GLIBCXX_HAS_GTHREADS && _GLIBCXX_USE_C99_STDINT_TR1
+#-       // && ATOMIC_INT_LOCK_FREE
+# 
+#   // @} group futures
+# _GLIBCXX_END_NAMESPACE_VERSION
+Index: b/src/libstdc++-v3/libsupc++/eh_atomics.h
+===================================================================
+--- /dev/null
++++ b/src/libstdc++-v3/libsupc++/eh_atomics.h
+@@ -0,0 +1,84 @@
++// Exception Handling support header for -*- C++ -*-
++
++// Copyright (C) 2016 Free Software Foundation, Inc.
++//
++// This file is part of GCC.
++//
++// GCC is free software; you can redistribute it and/or modify
++// it under the terms of the GNU General Public License as published by
++// the Free Software Foundation; either version 3, or (at your option)
++// any later version.
++//
++// GCC is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++//
++// Under Section 7 of GPL version 3, you are granted additional
++// permissions described in the GCC Runtime Library Exception, version
++// 3.1, as published by the Free Software Foundation.
++
++// You should have received a copy of the GNU General Public License and
++// a copy of the GCC Runtime Library Exception along with this program;
++// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++// <http://www.gnu.org/licenses/>.
++
++/** @file eh_atomics.h
++ *  This is an internal header file, included by library source files.
++ *  Do not attempt to use it directly.
++ */
++
++#ifndef _EH_ATOMICS_H
++#define _EH_ATOMICS_H 1
++
++#include <bits/c++config.h>
++#include <bits/atomic_word.h>
++#include <bits/atomic_lockfree_defines.h>
++#if ATOMIC_INT_LOCK_FREE <= 1
++# include <ext/atomicity.h>
++#endif
++
++#pragma GCC visibility push(default)
++extern "C++" {
++namespace __gnu_cxx
++{
++  void
++  __eh_atomic_inc (_Atomic_word* __count) __attribute__((always_inline));
++
++  bool
++  __eh_atomic_dec (_Atomic_word* __count) __attribute__((always_inline));
++
++  // Increments the count.
++  inline void
++  __eh_atomic_inc (_Atomic_word* __count)
++  {
++#if ATOMIC_INT_LOCK_FREE > 1
++    __atomic_add_fetch (__count, 1, __ATOMIC_ACQ_REL);
++#else
++    _GLIBCXX_SYNCHRONIZATION_HAPPENS_BEFORE (__count);
++    __gnu_cxx::__atomic_add_dispatch (__count, 1);
++    _GLIBCXX_SYNCHRONIZATION_HAPPENS_AFTER (__count);
++#endif
++  }
++
++  // Decrements the count and returns true if it reached zero.
++  inline bool
++  __eh_atomic_dec (_Atomic_word* __count)
++  {
++#if ATOMIC_INT_LOCK_FREE > 1
++    return __atomic_sub_fetch (__count, 1, __ATOMIC_ACQ_REL) == 0;
++#else
++    _GLIBCXX_SYNCHRONIZATION_HAPPENS_BEFORE (__count);
++    if (__gnu_cxx::__exchange_and_add_dispatch (__count, -1) == 1)
++      {
++	_GLIBCXX_SYNCHRONIZATION_HAPPENS_AFTER (__count);
++	return true;
++      }
++    return false;
++#endif
++  }
++} // namespace __gnu_cxx
++}
++#pragma GCC visibility pop
++
++#endif // _EH_ATOMICS_H
+Index: b/src/libstdc++-v3/libsupc++/eh_ptr.cc
+===================================================================
+--- a/src/libstdc++-v3/libsupc++/eh_ptr.cc
++++ b/src/libstdc++-v3/libsupc++/eh_ptr.cc
+@@ -23,9 +23,7 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include <bits/c++config.h>
+-#include <bits/atomic_lockfree_defines.h>
+-
+-#if ATOMIC_INT_LOCK_FREE > 1
++#include "eh_atomics.h"
+ 
+ #define _GLIBCXX_EH_PTR_COMPAT
+ 
+@@ -103,7 +101,7 @@ std::__exception_ptr::exception_ptr::_M_
+     {
+       __cxa_refcounted_exception *eh =
+ 	__get_refcounted_exception_header_from_obj (_M_exception_object);
+-      __atomic_add_fetch (&eh->referenceCount, 1, __ATOMIC_ACQ_REL);
++      __gnu_cxx::__eh_atomic_inc (&eh->referenceCount);
+     }
+ }
+ 
+@@ -115,7 +113,7 @@ std::__exception_ptr::exception_ptr::_M_
+     {
+       __cxa_refcounted_exception *eh =
+ 	__get_refcounted_exception_header_from_obj (_M_exception_object);
+-      if (__atomic_sub_fetch (&eh->referenceCount, 1, __ATOMIC_ACQ_REL) == 0)
++      if (__gnu_cxx::__eh_atomic_dec (&eh->referenceCount))
+         {
+ 	  if (eh->exc.exceptionDestructor)
+ 	    eh->exc.exceptionDestructor (_M_exception_object);
+@@ -219,7 +217,7 @@ __gxx_dependent_exception_cleanup(_Unwin
+ 
+   __cxa_free_dependent_exception (dep);
+ 
+-  if (__atomic_sub_fetch (&header->referenceCount, 1, __ATOMIC_ACQ_REL) == 0)
++  if (__gnu_cxx::__eh_atomic_dec (&header->referenceCount))
+     {
+       if (header->exc.exceptionDestructor)
+ 	header->exc.exceptionDestructor (header + 1);
+@@ -238,7 +236,7 @@ std::rethrow_exception(std::exception_pt
+ 
+   __cxa_dependent_exception *dep = __cxa_allocate_dependent_exception ();
+   dep->primaryException = obj;
+-  __atomic_add_fetch (&eh->referenceCount, 1,  __ATOMIC_ACQ_REL);
++  __gnu_cxx::__eh_atomic_inc (&eh->referenceCount);
+ 
+   dep->unexpectedHandler = get_unexpected ();
+   dep->terminateHandler = get_terminate ();
+@@ -260,5 +258,3 @@ std::rethrow_exception(std::exception_pt
+ }
+ 
+ #undef _GLIBCXX_EH_PTR_COMPAT
+-
+-#endif
+Index: b/src/libstdc++-v3/libsupc++/eh_throw.cc
+===================================================================
+--- a/src/libstdc++-v3/libsupc++/eh_throw.cc
++++ b/src/libstdc++-v3/libsupc++/eh_throw.cc
+@@ -24,6 +24,7 @@
+ 
+ #include <bits/c++config.h>
+ #include "unwind-cxx.h"
++#include "eh_atomics.h"
+ 
+ using namespace __cxxabiv1;
+ 
+@@ -42,17 +43,13 @@ __gxx_exception_cleanup (_Unwind_Reason_
+   if (code != _URC_FOREIGN_EXCEPTION_CAUGHT && code != _URC_NO_REASON)
+     __terminate (header->exc.terminateHandler);
+ 
+-#if ATOMIC_INT_LOCK_FREE > 1
+-  if (__atomic_sub_fetch (&header->referenceCount, 1, __ATOMIC_ACQ_REL) == 0)
++  if (__gnu_cxx::__eh_atomic_dec (&header->referenceCount))
+     {
+-#endif
+       if (header->exc.exceptionDestructor)
+ 	header->exc.exceptionDestructor (header + 1);
+ 
+       __cxa_free_exception (header + 1);
+-#if ATOMIC_INT_LOCK_FREE > 1
+     }
+-#endif
+ }
+ 
+ 
+Index: b/src/libstdc++-v3/libsupc++/eh_tm.cc
+===================================================================
+--- a/src/libstdc++-v3/libsupc++/eh_tm.cc
++++ b/src/libstdc++-v3/libsupc++/eh_tm.cc
+@@ -24,6 +24,7 @@
+ 
+ #include <cstdlib>
+ #include "unwind-cxx.h"
++#include "eh_atomics.h"
+ 
+ using namespace __cxxabiv1;
+ 
+@@ -45,9 +46,7 @@ free_any_cxa_exception (_Unwind_Exceptio
+       __cxa_free_dependent_exception (dep);
+     }
+ 
+-#if __GCC_ATOMIC_INT_LOCK_FREE > 1
+-  if (__atomic_sub_fetch (&h->referenceCount, 1, __ATOMIC_ACQ_REL) == 0)
+-#endif
++  if (__gnu_cxx::__eh_atomic_dec (&h->referenceCount))
+     __cxa_free_exception (h + 1);
+ }
+ 
+#Index: b/src/libstdc++-v3/libsupc++/exception
+#===================================================================
+#--- a/src/libstdc++-v3/libsupc++/exception
+#+++ b/src/libstdc++-v3/libsupc++/exception
+#@@ -35,7 +35,6 @@
+# #pragma GCC visibility push(default)
+# 
+# #include <bits/c++config.h>
+#-#include <bits/atomic_lockfree_defines.h>
+# 
+# extern "C++" {
+# 
+#@@ -166,7 +165,7 @@ _GLIBCXX_END_NAMESPACE_VERSION
+# 
+# #pragma GCC visibility pop
+# 
+#-#if (__cplusplus >= 201103L) && (ATOMIC_INT_LOCK_FREE > 1)
+#+#if (__cplusplus >= 201103L)
+# #include <bits/exception_ptr.h>
+# #include <bits/nested_exception.h>
+# #endif
+#Index: b/src/libstdc++-v3/libsupc++/exception_ptr.h
+#===================================================================
+#--- a/src/libstdc++-v3/libsupc++/exception_ptr.h
+#+++ b/src/libstdc++-v3/libsupc++/exception_ptr.h
+#@@ -36,10 +36,6 @@
+# #include <bits/c++config.h>
+# #include <bits/exception_defines.h>
+# 
+#-#if ATOMIC_INT_LOCK_FREE < 2
+#-#  error This platform does not support exception propagation.
+#-#endif
+#-
+# extern "C++" {
+# 
+# namespace std 
+Index: b/src/libstdc++-v3/libsupc++/guard.cc
+===================================================================
+--- a/src/libstdc++-v3/libsupc++/guard.cc
++++ b/src/libstdc++-v3/libsupc++/guard.cc
+@@ -30,6 +30,7 @@
+ #include <new>
+ #include <ext/atomicity.h>
+ #include <ext/concurrence.h>
++#include <bits/atomic_lockfree_defines.h>
+ #if defined(__GTHREADS) && defined(__GTHREAD_HAS_COND) \
+   && (ATOMIC_INT_LOCK_FREE > 1) && defined(_GLIBCXX_HAVE_LINUX_FUTEX)
+ # include <climits>
+Index: b/src/libstdc++-v3/libsupc++/nested_exception.cc
+===================================================================
+--- a/src/libstdc++-v3/libsupc++/nested_exception.cc
++++ b/src/libstdc++-v3/libsupc++/nested_exception.cc
+@@ -25,7 +25,5 @@
+ 
+ namespace std 
+ {
+-#if ATOMIC_INT_LOCK_FREE > 1
+   nested_exception::~nested_exception() noexcept = default;
+-#endif
+ } // namespace std
+#Index: b/src/libstdc++-v3/libsupc++/nested_exception.h
+#===================================================================
+#--- a/src/libstdc++-v3/libsupc++/nested_exception.h
+#+++ b/src/libstdc++-v3/libsupc++/nested_exception.h
+#@@ -39,10 +39,6 @@
+# #include <bits/c++config.h>
+# #include <bits/move.h>
+# 
+#-#if ATOMIC_INT_LOCK_FREE < 2
+#-#  error This platform does not support exception propagation.
+#-#endif
+#-
+# extern "C++" {
+# 
+# namespace std
+Index: b/src/libstdc++-v3/src/c++11/future.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/future.cc
++++ b/src/libstdc++-v3/src/c++11/future.cc
+@@ -78,8 +78,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
+   const char*
+   future_error::what() const noexcept { return logic_error::what(); }
+ 
+-#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1) \
+-  && (ATOMIC_INT_LOCK_FREE > 1)
++#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1)
+   __future_base::_Result_base::_Result_base() = default;
+ 
+   __future_base::_Result_base::~_Result_base() = default;
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/40296.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/40296.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/40296.cc
+@@ -1,6 +1,5 @@
+ // { dg-do compile }
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/60612-terminate.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/60612-terminate.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/60612-terminate.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/60612-unexpected.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/60612-unexpected.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/60612-unexpected.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/62258.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/62258.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/62258.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2015-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/64241.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/64241.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/64241.cc
+@@ -16,7 +16,6 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ // { dg-options "-std=gnu++11 -fno-exceptions -O0" }
+-// { dg-require-atomic-builtins "" }
+ 
+ #include <exception>
+ #include <testsuite_hooks.h>
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/current_exception.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/current_exception.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/current_exception.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // 2008-05-25  Sebastian Redl  <sebastian.redl@getdesigned.at>
+ 
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/lifespan.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/lifespan.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/lifespan.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // 2008-05-25  Sebastian Redl  <sebastian.redl@getdesigned.at>
+ 
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/make_exception_ptr.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/make_exception_ptr.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/make_exception_ptr.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/move.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/move.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/requirements.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/requirements.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/requirements.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/requirements_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/requirements_neg.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/requirements_neg.cc
+@@ -1,6 +1,5 @@
+ // { dg-do compile }
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/exception_ptr/rethrow_exception.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/exception_ptr/rethrow_exception.cc
++++ b/src/libstdc++-v3/testsuite/18_support/exception_ptr/rethrow_exception.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // 2008-05-25  Sebastian Redl  <sebastian.redl@getdesigned.at>
+ 
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/51438.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/51438.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/51438.cc
+@@ -1,6 +1,5 @@
+ // { dg-do compile }
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/62154.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/62154.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/62154.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/cons.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/cons.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/cons.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/nested_ptr.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/nested_ptr.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/nested_ptr.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/rethrow_if_nested.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/rethrow_if_nested.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/rethrow_if_nested.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/rethrow_nested.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/rethrow_nested.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/rethrow_nested.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/18_support/nested_exception/throw_with_nested.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/18_support/nested_exception/throw_with_nested.cc
++++ b/src/libstdc++-v3/testsuite/18_support/nested_exception/throw_with_nested.cc
+@@ -1,5 +1,4 @@
+ // { dg-options "-std=gnu++11" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/42819.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/42819.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/42819.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/49668.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/49668.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/49668.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/54297.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/54297.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/54297.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ // { dg-require-sleep "" }
+ 
+ // Copyright (C) 2012-2016 Free Software Foundation, Inc.
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/any.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/any.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/any.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/async.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/async.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/async.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/except.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/except.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/except.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/forced_unwind.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/forced_unwind.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/forced_unwind.cc
+@@ -2,7 +2,6 @@
+ // { dg-options " -std=gnu++11 -pthread" { target *-*-linux* *-*-gnu* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/launch.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/launch.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/launch.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/lwg2021.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/lwg2021.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/lwg2021.cc
+@@ -21,7 +21,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // LWG 2021. Further incorrect usages of result_of
+ // Arguments to result_of should use decay.
+Index: b/src/libstdc++-v3/testsuite/30_threads/async/sync.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/async/sync.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/async/sync.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/cons/assign_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/cons/assign_neg.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/cons/assign_neg.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/cons/constexpr.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/cons/constexpr.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/cons/constexpr.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11 -fno-inline -g0" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ // { dg-final { scan-assembler-not "_ZNSt6futureIvEC2Ev" } }
+ // { dg-final { scan-assembler-not "_ZNSt6futureIiEC2Ev" } }
+ 
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/cons/copy_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/cons/copy_neg.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/cons/copy_neg.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/cons/default.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/cons/default.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/cons/default.cc
+@@ -1,7 +1,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/cons/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/cons/move.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/cons/move.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/cons/move_assign.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/cons/move_assign.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/cons/move_assign.cc
+@@ -1,7 +1,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/45133.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/45133.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/45133.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/get.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/get.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/get.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/get2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/get2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/get2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/share.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/share.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/share.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/valid.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/valid.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/valid.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/wait.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/wait.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/wait.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/wait_for.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/wait_for.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/wait_for.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/members/wait_until.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/members/wait_until.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/wait_until.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/future/requirements/explicit_instantiation.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/future/requirements/explicit_instantiation.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/future/requirements/explicit_instantiation.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/headers/future/types_std_c++0x.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/headers/future/types_std_c++0x.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/headers/future/types_std_c++0x.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" } 
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/49668.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/49668.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/49668.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/1.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/1.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/1.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/3.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/3.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/3.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/56492.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/56492.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/56492.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2013-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc2.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc_min.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc_min.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc_min.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/assign_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/assign_neg.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/assign_neg.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/copy_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/copy_neg.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/copy_neg.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/move.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/move.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/move_assign.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/move_assign.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/move_assign.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/forced_unwind.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/forced_unwind.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/forced_unwind.cc
+@@ -2,7 +2,6 @@
+ // { dg-options " -std=gnu++11 -pthread" { target *-*-linux* *-*-gnu* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/at_thread_exit.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/at_thread_exit.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/at_thread_exit.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke3.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke3.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke3.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke4.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke4.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke4.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke5.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke5.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke5.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/swap.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/swap.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/swap.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/valid.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/valid.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/valid.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/requirements/explicit_instantiation.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/requirements/explicit_instantiation.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/requirements/explicit_instantiation.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/packaged_task/uses_allocator.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/uses_allocator.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/uses_allocator.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/60966.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/60966.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/60966.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/69106.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/69106.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/69106.cc
+@@ -19,7 +19,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ #include <future>
+ 
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/1.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/1.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/1.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc2.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc_min.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc_min.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc_min.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/assign_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/assign_neg.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/assign_neg.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/copy_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/copy_neg.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/copy_neg.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/move.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/move.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/cons/move_assign.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/move_assign.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/move_assign.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/at_thread_exit.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/at_thread_exit.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/at_thread_exit.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2014-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value3.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value3.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value3.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/members/swap.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/swap.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/swap.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/requirements/explicit_instantiation.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/requirements/explicit_instantiation.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/requirements/explicit_instantiation.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/promise/uses_allocator.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/uses_allocator.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/uses_allocator.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2011-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/assign.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/assign.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/assign.cc
+@@ -1,7 +1,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/constexpr.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/constexpr.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/constexpr.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11 -fno-inline -g0" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ // { dg-final { scan-assembler-not "_ZNSt13shared_futureIvEC2Ev" } }
+ // { dg-final { scan-assembler-not "_ZNSt13shared_futureIiEC2Ev" } }
+ 
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/copy.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/copy.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/copy.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/default.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/default.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/default.cc
+@@ -1,7 +1,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/move.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/move.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/move_assign.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/move_assign.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/cons/move_assign.cc
+@@ -1,7 +1,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/45133.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/45133.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/45133.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get2.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get2.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/valid.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/valid.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/valid.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2010-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_for.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_for.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_for.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_until.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_until.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_until.cc
+@@ -4,7 +4,6 @@
+ // { dg-options " -std=gnu++11 " { target *-*-cygwin *-*-rtems* *-*-darwin* } }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
+Index: b/src/libstdc++-v3/testsuite/30_threads/shared_future/requirements/explicit_instantiation.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/requirements/explicit_instantiation.cc
++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/requirements/explicit_instantiation.cc
+@@ -2,7 +2,6 @@
+ // { dg-options "-std=gnu++11" }
+ // { dg-require-cstdint "" }
+ // { dg-require-gthreads "" }
+-// { dg-require-atomic-builtins "" }
+ 
+ // Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ //
--- gcc-6-6.4.0.orig/debian/patches/pr65618.diff
+++ gcc-6-6.4.0/debian/patches/pr65618.diff
@@ -0,0 +1,16 @@
+# DP: Proposed patch for PR rtl-optimization/65618
+
+--- a/src/gcc/emit-rtl.c	
++++ a/src/gcc/emit-rtl.c	
+@@ -3742,6 +3742,11 @@ try_split (rtx pat, rtx_insn *trial, int last)
+ 		   next = NEXT_INSN (next))
+ 		if (NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)
+ 		  {
++		    /* Advance after to the next instruction if it is about to
++		       be removed */
++		    if (after == next)
++		      after = NEXT_INSN(after);
++
+ 		    remove_insn (next);
+ 		    add_insn_after (next, insn, NULL);
+ 		    break;
--- gcc-6-6.4.0.orig/debian/patches/pr66368.diff
+++ gcc-6-6.4.0/debian/patches/pr66368.diff
@@ -0,0 +1,26 @@
+# DP: PR go/66368, build libgo with -fno-stack-protector
+
+Index: b/src/libgo/Makefile.am
+===================================================================
+--- a/src/libgo/Makefile.am
++++ b/src/libgo/Makefile.am
+@@ -42,6 +42,7 @@ AM_CPPFLAGS = -I $(srcdir)/runtime $(LIB
+ ACLOCAL_AMFLAGS = -I ./config -I ../config
+ 
+ AM_CFLAGS = -fexceptions -fnon-call-exceptions -fplan9-extensions \
++	-fno-stack-protector \
+ 	$(SPLIT_STACK) $(WARN_CFLAGS) \
+ 	$(STRINGOPS_FLAG) $(OSCFLAGS) \
+ 	-I $(srcdir)/../libgcc -I $(srcdir)/../libbacktrace \
+Index: b/src/libgo/Makefile.in
+===================================================================
+--- a/src/libgo/Makefile.in
++++ b/src/libgo/Makefile.in
+@@ -513,6 +513,7 @@ WARN_CFLAGS = $(WARN_FLAGS) $(WERROR)
+ AM_CPPFLAGS = -I $(srcdir)/runtime $(LIBFFIINCS) $(PTHREAD_CFLAGS)
+ ACLOCAL_AMFLAGS = -I ./config -I ../config
+ AM_CFLAGS = -fexceptions -fnon-call-exceptions -fplan9-extensions \
++	-fno-stack-protector \
+ 	$(SPLIT_STACK) $(WARN_CFLAGS) \
+ 	$(STRINGOPS_FLAG) $(OSCFLAGS) \
+ 	-I $(srcdir)/../libgcc -I $(srcdir)/../libbacktrace \
--- gcc-6-6.4.0.orig/debian/patches/pr67590.diff
+++ gcc-6-6.4.0/debian/patches/pr67590.diff
@@ -0,0 +1,38 @@
+# DP: Fix PR67590, setting objdump macro.
+
+Index: b/src/libcc1/configure.ac
+===================================================================
+--- a/src/libcc1/configure.ac
++++ b/src/libcc1/configure.ac
+@@ -64,6 +64,31 @@ if test "$GXX" = yes; then
+ fi
+ AC_SUBST(libsuffix)
+ 
++# Figure out what objdump we will be using.
++AS_VAR_SET_IF(gcc_cv_objdump,, [
++if test -f $gcc_cv_binutils_srcdir/configure.ac \
++     && test -f ../binutils/Makefile \
++     && test x$build = x$host; then
++	# Single tree build which includes binutils.
++	gcc_cv_objdump=../binutils/objdump$build_exeext
++elif test -x objdump$build_exeext; then
++	gcc_cv_objdump=./objdump$build_exeext
++elif ( set dummy $OBJDUMP_FOR_TARGET; test -x $[2] ); then
++        gcc_cv_objdump="$OBJDUMP_FOR_TARGET"
++else
++        AC_PATH_PROG(gcc_cv_objdump, $OBJDUMP_FOR_TARGET)
++fi])
++
++AC_MSG_CHECKING(what objdump to use)
++if test "$gcc_cv_objdump" = ../binutils/objdump$build_exeext; then
++	# Single tree build which includes binutils.
++	AC_MSG_RESULT(newly built objdump)
++elif test x$gcc_cv_objdump = x; then
++	AC_MSG_RESULT(not found)
++else
++	AC_MSG_RESULT($gcc_cv_objdump)
++fi
++
+ dnl Test for -lsocket and -lnsl.  Copied from libgo/configure.ac.
+ AC_CACHE_CHECK([for socket libraries], libcc1_cv_lib_sockets,
+   [libcc1_cv_lib_sockets=
--- gcc-6-6.4.0.orig/debian/patches/pr70909.diff
+++ gcc-6-6.4.0/debian/patches/pr70909.diff
@@ -0,0 +1,345 @@
+# DP: Fix PR demangler/70909, libiberty Demangler segfaults. CVE-2016-4491.
+
+2017-03-08  Mark Wielaard  <mark@klomp.org>
+
+	PR demangler/70909
+	PR demangler/67264
+	* include/demangle.h: Add d_printing to struct demangle_component
+	and pass struct demangle_component as non const.
+
+libiberty/
+
+2017-03-08  Mark Wielaard  <mark@klomp.org>
+
+	PR demangler/70909
+	PR demangler/67264
+	* cp-demangle.c: Fix endless recursion. Pass
+	struct demangle_component as non const.
+	(d_make_empty): Initialize variable.
+	(d_print_comp_inner): Limit recursion.
+	(d_print_comp): Decrement variable.
+	* cp-demint.c (cplus_demangle_fill_component): Initialize
+	variable.
+	(cplus_demangle_fill_builtin_type): Likewise.
+	(cplus_demangle_fill_operator): Likewise.
+	* testsuite/demangle-expected: Add tests.
+
+ 
+Index: b/src/include/demangle.h
+===================================================================
+--- a/src/include/demangle.h
++++ b/src/include/demangle.h
+@@ -494,6 +494,11 @@ struct demangle_component
+   /* The type of this component.  */
+   enum demangle_component_type type;
+ 
++  /* Guard against recursive component printing.
++     Initialize to zero.  Private to d_print_comp.
++     All other fields are final after initialization.  */
++  int d_printing;
++
+   union
+   {
+     /* For DEMANGLE_COMPONENT_NAME.  */
+@@ -688,7 +693,7 @@ cplus_demangle_v3_components (const char
+ 
+ extern char *
+ cplus_demangle_print (int options,
+-                      const struct demangle_component *tree,
++                      struct demangle_component *tree,
+                       int estimated_length,
+                       size_t *p_allocated_size);
+ 
+@@ -708,7 +713,7 @@ cplus_demangle_print (int options,
+ 
+ extern int
+ cplus_demangle_print_callback (int options,
+-                               const struct demangle_component *tree,
++                               struct demangle_component *tree,
+                                demangle_callbackref callback, void *opaque);
+ 
+ #ifdef __cplusplus
+Index: b/src/libiberty/testsuite/demangle-expected
+===================================================================
+--- a/src/libiberty/testsuite/demangle-expected
++++ b/src/libiberty/testsuite/demangle-expected
+@@ -4666,3 +4666,34 @@ void eat<int*, Foo()::{lambda(auto:1*, a
+ 
+ _Z3eatIPiZ3BarIsEvvEUlPsPT_PT0_E0_EvRS3_RS5_
+ void eat<int*, void Bar<short>()::{lambda(short*, auto:1*, auto:2*)#2}>(int*&, void Bar<short>()::{lambda(short*, auto:1*, auto:2*)#2}&)
++
++#
++# Test recursion PR67264
++_Z1KIStcvT_E
++_Z1KIStcvT_E
++
++_ZcvT_IIS0_EE
++_ZcvT_IIS0_EE
++
++_ZcvT_IZcvT_E1fE
++_ZcvT_IZcvT_E1fE
++
++_Z1gINcvT_EE
++_Z1gINcvT_EE
++
++_ZcvT_ILZcvDTT_EEE
++_ZcvT_ILZcvDTT_EEE
++
++_Z1gIJOOT_EEOT_c
++_Z1gIJOOT_EEOT_c
++
++_Z1KMMMMMMMMMMMMMMMA_xooooooooooooooo
++_Z1KMMMMMMMMMMMMMMMA_xooooooooooooooo
++
++_ZdvMMMMMMMMMMMMMrrrrA_DTdvfp_fp_Eededilfdfdfdfd
++_ZdvMMMMMMMMMMMMMrrrrA_DTdvfp_fp_Eededilfdfdfdfd
++#
++# Test for Infinite Recursion PR70909
++
++_Z1MA_aMMMMA_MMA_MMMMMMMMSt1MS_o11T0000000000t2M0oooozoooo
++_Z1MA_aMMMMA_MMA_MMMMMMMMSt1MS_o11T0000000000t2M0oooozoooo
+Index: b/src/libiberty/cp-demint.c
+===================================================================
+--- a/src/libiberty/cp-demint.c
++++ b/src/libiberty/cp-demint.c
+@@ -123,6 +123,7 @@ cplus_demangle_fill_component (struct de
+   p->type = type;
+   p->u.s_binary.left = left;
+   p->u.s_binary.right = right;
++  p->d_printing = 0;
+ 
+   return 1;
+ }
+@@ -146,6 +147,7 @@ cplus_demangle_fill_builtin_type (struct
+ 	{
+ 	  p->type = DEMANGLE_COMPONENT_BUILTIN_TYPE;
+ 	  p->u.s_builtin.type = &cplus_demangle_builtin_types[i];
++	  p->d_printing = 0;
+ 	  return 1;
+ 	}
+     }
+@@ -172,6 +174,7 @@ cplus_demangle_fill_operator (struct dem
+ 	{
+ 	  p->type = DEMANGLE_COMPONENT_OPERATOR;
+ 	  p->u.s_operator.op = &cplus_demangle_operators[i];
++	  p->d_printing = 0;
+ 	  return 1;
+ 	}
+     }
+Index: b/src/libiberty/cp-demangle.c
+===================================================================
+--- a/src/libiberty/cp-demangle.c
++++ b/src/libiberty/cp-demangle.c
+@@ -173,10 +173,10 @@ static struct demangle_component *d_mang
+ static struct demangle_component *d_type (struct d_info *);
+ 
+ #define cplus_demangle_print d_print
+-static char *d_print (int, const struct demangle_component *, int, size_t *);
++static char *d_print (int, struct demangle_component *, int, size_t *);
+ 
+ #define cplus_demangle_print_callback d_print_callback
+-static int d_print_callback (int, const struct demangle_component *,
++static int d_print_callback (int, struct demangle_component *,
+                              demangle_callbackref, void *);
+ 
+ #define cplus_demangle_init_info d_init_info
+@@ -265,7 +265,7 @@ struct d_print_mod
+      in which they appeared in the mangled string.  */
+   struct d_print_mod *next;
+   /* The modifier.  */
+-  const struct demangle_component *mod;
++  struct demangle_component *mod;
+   /* Whether this modifier was printed.  */
+   int printed;
+   /* The list of templates which applies to this modifier.  */
+@@ -531,7 +531,7 @@ static inline void d_append_string (stru
+ static inline char d_last_char (struct d_print_info *);
+ 
+ static void
+-d_print_comp (struct d_print_info *, int, const struct demangle_component *);
++d_print_comp (struct d_print_info *, int, struct demangle_component *);
+ 
+ static void
+ d_print_java_identifier (struct d_print_info *, const char *, int);
+@@ -540,25 +540,25 @@ static void
+ d_print_mod_list (struct d_print_info *, int, struct d_print_mod *, int);
+ 
+ static void
+-d_print_mod (struct d_print_info *, int, const struct demangle_component *);
++d_print_mod (struct d_print_info *, int, struct demangle_component *);
+ 
+ static void
+ d_print_function_type (struct d_print_info *, int,
+-                       const struct demangle_component *,
++                       struct demangle_component *,
+                        struct d_print_mod *);
+ 
+ static void
+ d_print_array_type (struct d_print_info *, int,
+-                    const struct demangle_component *,
++                    struct demangle_component *,
+                     struct d_print_mod *);
+ 
+ static void
+-d_print_expr_op (struct d_print_info *, int, const struct demangle_component *);
++d_print_expr_op (struct d_print_info *, int, struct demangle_component *);
+ 
+ static void d_print_cast (struct d_print_info *, int,
+-			  const struct demangle_component *);
++			  struct demangle_component *);
+ static void d_print_conversion (struct d_print_info *, int,
+-				const struct demangle_component *);
++				struct demangle_component *);
+ 
+ static int d_demangle_callback (const char *, int,
+                                 demangle_callbackref, void *);
+@@ -924,6 +924,7 @@ d_make_empty (struct d_info *di)
+   if (di->next_comp >= di->num_comps)
+     return NULL;
+   p = &di->comps[di->next_comp];
++  p->d_printing = 0;
+   ++di->next_comp;
+   return p;
+ }
+@@ -4230,7 +4231,7 @@ d_last_char (struct d_print_info *dpi)
+ CP_STATIC_IF_GLIBCPP_V3
+ int
+ cplus_demangle_print_callback (int options,
+-                               const struct demangle_component *dc,
++                               struct demangle_component *dc,
+                                demangle_callbackref callback, void *opaque)
+ {
+   struct d_print_info dpi;
+@@ -4273,7 +4274,7 @@ cplus_demangle_print_callback (int optio
+ 
+ CP_STATIC_IF_GLIBCPP_V3
+ char *
+-cplus_demangle_print (int options, const struct demangle_component *dc,
++cplus_demangle_print (int options, struct demangle_component *dc,
+                       int estimate, size_t *palc)
+ {
+   struct d_growable_string dgs;
+@@ -4433,7 +4434,7 @@ d_args_length (struct d_print_info *dpi,
+ 
+ static void
+ d_print_subexpr (struct d_print_info *dpi, int options,
+-		 const struct demangle_component *dc)
++		 struct demangle_component *dc)
+ {
+   int simple = 0;
+   if (dc->type == DEMANGLE_COMPONENT_NAME
+@@ -4509,9 +4510,9 @@ d_get_saved_scope (struct d_print_info *
+ 
+ static int
+ d_maybe_print_fold_expression (struct d_print_info *dpi, int options,
+-			       const struct demangle_component *dc)
++			       struct demangle_component *dc)
+ {
+-  const struct demangle_component *ops, *operator_, *op1, *op2;
++  struct demangle_component *ops, *operator_, *op1, *op2;
+   int save_idx;
+ 
+   const char *fold_code = d_left (dc)->u.s_operator.op->code;
+@@ -4572,11 +4573,11 @@ d_maybe_print_fold_expression (struct d_
+ 
+ static void
+ d_print_comp_inner (struct d_print_info *dpi, int options,
+-		    const struct demangle_component *dc)
++		    struct demangle_component *dc)
+ {
+   /* Magic variable to let reference smashing skip over the next modifier
+      without needing to modify *dc.  */
+-  const struct demangle_component *mod_inner = NULL;
++  struct demangle_component *mod_inner = NULL;
+ 
+   /* Variable used to store the current templates while a previously
+      captured scope is used.  */
+@@ -4961,7 +4962,7 @@ d_print_comp_inner (struct d_print_info
+     case DEMANGLE_COMPONENT_RVALUE_REFERENCE:
+       {
+ 	/* Handle reference smashing: & + && = &.  */
+-	const struct demangle_component *sub = d_left (dc);
++	struct demangle_component *sub = d_left (dc);
+ 	if (!dpi->is_lambda_arg
+ 	    && sub->type == DEMANGLE_COMPONENT_TEMPLATE_PARAM)
+ 	  {
+@@ -5664,9 +5665,16 @@ d_print_comp_inner (struct d_print_info
+ 
+ static void
+ d_print_comp (struct d_print_info *dpi, int options,
+-	      const struct demangle_component *dc)
++	      struct demangle_component *dc)
+ {
+   struct d_component_stack self;
++  if (dc == NULL || dc->d_printing > 1)
++    {
++      d_print_error (dpi);
++      return;
++    }
++  else
++    dc->d_printing++;
+ 
+   self.dc = dc;
+   self.parent = dpi->component_stack;
+@@ -5675,6 +5683,7 @@ d_print_comp (struct d_print_info *dpi,
+   d_print_comp_inner (dpi, options, dc);
+ 
+   dpi->component_stack = self.parent;
++  dc->d_printing--;
+ }
+ 
+ /* Print a Java dentifier.  For Java we try to handle encoded extended
+@@ -5816,7 +5825,7 @@ d_print_mod_list (struct d_print_info *d
+ 
+ static void
+ d_print_mod (struct d_print_info *dpi, int options,
+-             const struct demangle_component *mod)
++             struct demangle_component *mod)
+ {
+   switch (mod->type)
+     {
+@@ -5908,7 +5917,7 @@ d_print_mod (struct d_print_info *dpi, i
+ 
+ static void
+ d_print_function_type (struct d_print_info *dpi, int options,
+-                       const struct demangle_component *dc,
++                       struct demangle_component *dc,
+                        struct d_print_mod *mods)
+ {
+   int need_paren;
+@@ -5986,7 +5995,7 @@ d_print_function_type (struct d_print_in
+ 
+ static void
+ d_print_array_type (struct d_print_info *dpi, int options,
+-                    const struct demangle_component *dc,
++                    struct demangle_component *dc,
+                     struct d_print_mod *mods)
+ {
+   int need_space;
+@@ -6040,7 +6049,7 @@ d_print_array_type (struct d_print_info
+ 
+ static void
+ d_print_expr_op (struct d_print_info *dpi, int options,
+-                 const struct demangle_component *dc)
++                 struct demangle_component *dc)
+ {
+   if (dc->type == DEMANGLE_COMPONENT_OPERATOR)
+     d_append_buffer (dpi, dc->u.s_operator.op->name,
+@@ -6053,7 +6062,7 @@ d_print_expr_op (struct d_print_info *dp
+ 
+ static void
+ d_print_cast (struct d_print_info *dpi, int options,
+-		    const struct demangle_component *dc)
++	      struct demangle_component *dc)
+ {
+   d_print_comp (dpi, options, d_left (dc));
+ }
+@@ -6062,7 +6071,7 @@ d_print_cast (struct d_print_info *dpi,
+ 
+ static void
+ d_print_conversion (struct d_print_info *dpi, int options,
+-		    const struct demangle_component *dc)
++		    struct demangle_component *dc)
+ {
+   struct d_print_template dpt;
+ 
--- gcc-6-6.4.0.orig/debian/patches/pr72813.diff
+++ gcc-6-6.4.0/debian/patches/pr72813.diff
@@ -0,0 +1,66 @@
+# DP: Fix PR c++/72813, taken from the trunk.
+
+gcc/c/
+
+2017-01-11  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/72813
+	* c-decl.c (pop_file_scope): Set flag_syntax_only to 1 after writing
+	PCH file.
+
+gcc/
+
+2017-01-11  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/72813
+	* gcc.c (default_compilers): Don't add -o %g.s for -S -save-temps
+	of c-header.
+
+gcc/cp/
+
+2017-01-11  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/72813
+	* decl2.c (c_parse_final_cleanups): Set flag_syntax_only to 1 after
+	writing PCH file.
+
+ 
+Index: b/src/gcc/c/c-decl.c
+===================================================================
+--- a/src/gcc/c/c-decl.c
++++ b/src/gcc/c/c-decl.c
+@@ -1418,6 +1418,8 @@ pop_file_scope (void)
+   if (pch_file)
+     {
+       c_common_write_pch ();
++      /* Ensure even the callers don't try to finalize the CU.  */
++      flag_syntax_only = 1;
+       return;
+     }
+ 
+Index: b/src/gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c
++++ b/src/gcc/gcc.c
+@@ -1317,7 +1317,7 @@ static const struct compiler default_com
+ 		%(cpp_options) -o %{save-temps*:%b.i} %{!save-temps*:%g.i} \n\
+ 		    cc1 -fpreprocessed %{save-temps*:%b.i} %{!save-temps*:%g.i} \
+ 			%(cc1_options)\
+-			%{!fsyntax-only:-o %g.s \
++			%{!fsyntax-only:%{!S:-o %g.s} \
+ 			    %{!fdump-ada-spec*:%{!o*:--output-pch=%i.gch}\
+ 					       %W{o*:--output-pch=%*}}%V}}\
+ 	  %{!save-temps*:%{!traditional-cpp:%{!no-integrated-cpp:\
+Index: b/src/gcc/cp/decl2.c
+===================================================================
+--- a/src/gcc/cp/decl2.c
++++ b/src/gcc/cp/decl2.c
+@@ -4558,6 +4558,8 @@ c_parse_final_cleanups (void)
+ 	  DECL_ASSEMBLER_NAME (node->decl);
+       c_common_write_pch ();
+       dump_tu ();
++      /* Ensure even the callers don't try to finalize the CU.  */
++      flag_syntax_only = 1;
+       return;
+     }
+ 
--- gcc-6-6.4.0.orig/debian/patches/pr77267.diff
+++ gcc-6-6.4.0/debian/patches/pr77267.diff
@@ -0,0 +1,109 @@
+# DP: Fix PR target/77267 (x86), taken from the trunk.
+
+gcc/
+
+2016-09-10  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+
+	PR target/77267
+	* config.in: Regenerate.
+	* config/i386/linux-common.h (MPX_LD_AS_NEEDED_GUARD_PUSH):
+	New macro.
+	(MPX_LD_AS_NEEDED_GUARD_PUSH): Ditto.
+	(LIBMPXWRAPPERS_SPEC): Remove "--no-whole-archive" from
+	static-libmpxwrappers case.
+	(LIBMPX_SPEC): Add guards with MPX_LD_AS_NEEDED_GUARD_PUSH and
+	MPX_LD_AS_NEEDED_GUARD_POP.
+	* configure: Regenerate.
+	* configure.ac (HAVE_LD_PUSHPOPSTATE_SUPPORT): New variable.
+	defined if linker support "--push-state"/"--pop-state".
+
+ 
+Index: b/src/gcc/config.in
+===================================================================
+--- a/src/gcc/config.in
++++ b/src/gcc/config.in
+@@ -1525,6 +1525,12 @@
+ #endif
+ 
+ 
++/* Define if your linker supports --push-state/--pop-state */
++#ifndef USED_FOR_TARGET
++#undef HAVE_LD_PUSHPOPSTATE_SUPPORT
++#endif
++
++
+ /* Define if your linker links a mix of read-only and read-write sections into
+    a read-write section. */
+ #ifndef USED_FOR_TARGET
+Index: b/src/gcc/configure.ac
+===================================================================
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -6219,6 +6219,27 @@ if test x"$ld_bndplt_support" = xyes; th
+ fi
+ AC_MSG_RESULT($ld_bndplt_support)
+ 
++# Check linker supports '--push-state'/'--pop-state'
++ld_pushpopstate_support=no
++AC_MSG_CHECKING(linker --push-state/--pop-state options)
++if test x"$ld_is_gold" = xno; then
++  if test $in_tree_ld = yes ; then
++    if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 25 -o "$gcc_cv_gld_major_version" -gt 2; then
++      ld_pushpopstate_support=yes
++    fi
++  elif test x$gcc_cv_ld != x; then
++    # Check if linker supports --push-state/--pop-state options
++    if $gcc_cv_ld --help 2>/dev/null | grep -- '--push-state' > /dev/null; then
++      ld_pushpopstate_support=yes
++    fi
++  fi
++fi
++if test x"$ld_pushpopstate_support" = xyes; then
++  AC_DEFINE(HAVE_LD_PUSHPOPSTATE_SUPPORT, 1,
++	[Define if your linker supports --push-state/--pop-state])
++fi
++AC_MSG_RESULT($ld_pushpopstate_support)
++
+ # Configure the subdirectories
+ # AC_CONFIG_SUBDIRS($subdirs)
+ 
+Index: b/src/gcc/config/i386/linux-common.h
+===================================================================
+--- a/src/gcc/config/i386/linux-common.h
++++ b/src/gcc/config/i386/linux-common.h
+@@ -79,13 +79,23 @@ along with GCC; see the file COPYING3.
+ #endif
+ #endif
+ 
++#ifdef HAVE_LD_PUSHPOPSTATE_SUPPORT
++#define MPX_LD_AS_NEEDED_GUARD_PUSH "--push-state --no-as-needed"
++#define MPX_LD_AS_NEEDED_GUARD_POP "--pop-state"
++#else
++#define MPX_LD_AS_NEEDED_GUARD_PUSH ""
++#define MPX_LD_AS_NEEDED_GUARD_POP ""
++#endif
++
+ #ifndef LIBMPX_SPEC
+ #if defined(HAVE_LD_STATIC_DYNAMIC)
+ #define LIBMPX_SPEC "\
+ %{mmpx:%{fcheck-pointer-bounds:\
+     %{static:--whole-archive -lmpx --no-whole-archive" LIBMPX_LIBS "}\
+     %{!static:%{static-libmpx:" LD_STATIC_OPTION " --whole-archive}\
+-    -lmpx %{static-libmpx:--no-whole-archive " LD_DYNAMIC_OPTION \
++    %{!static-libmpx:" MPX_LD_AS_NEEDED_GUARD_PUSH "} -lmpx \
++    %{!static-libmpx:" MPX_LD_AS_NEEDED_GUARD_POP "} \
++    %{static-libmpx:--no-whole-archive " LD_DYNAMIC_OPTION \
+     LIBMPX_LIBS "}}}}"
+ #else
+ #define LIBMPX_SPEC "\
+@@ -98,8 +108,8 @@ along with GCC; see the file COPYING3.
+ #define LIBMPXWRAPPERS_SPEC "\
+ %{mmpx:%{fcheck-pointer-bounds:%{!fno-chkp-use-wrappers:\
+     %{static:-lmpxwrappers}\
+-    %{!static:%{static-libmpxwrappers:" LD_STATIC_OPTION " --whole-archive}\
+-    -lmpxwrappers %{static-libmpxwrappers:--no-whole-archive "\
++    %{!static:%{static-libmpxwrappers:" LD_STATIC_OPTION "}\
++    -lmpxwrappers %{static-libmpxwrappers: "\
+     LD_DYNAMIC_OPTION "}}}}}"
+ #else
+ #define LIBMPXWRAPPERS_SPEC "\
--- gcc-6-6.4.0.orig/debian/patches/pr77857.diff
+++ gcc-6-6.4.0/debian/patches/pr77857.diff
@@ -0,0 +1,77 @@
+# DP: Fix PR go/77857, gccgo vendoring. Taken from the trunk.
+
+Index: b/src/libgo/go/cmd/go/build.go
+===================================================================
+--- a/src/libgo/go/cmd/go/build.go
++++ b/src/libgo/go/cmd/go/build.go
+@@ -2307,14 +2307,6 @@ func (gcToolchain) gc(b *builder, p *Pac
+ 		}
+ 	}
+ 
+-	for _, path := range p.Imports {
+-		if i := strings.LastIndex(path, "/vendor/"); i >= 0 {
+-			gcargs = append(gcargs, "-importmap", path[i+len("/vendor/"):]+"="+path)
+-		} else if strings.HasPrefix(path, "vendor/") {
+-			gcargs = append(gcargs, "-importmap", path[len("vendor/"):]+"="+path)
+-		}
+-	}
+-
+ 	args := []interface{}{buildToolExec, tool("compile"), "-o", ofile, "-trimpath", b.work, buildGcflags, gcargs, "-D", p.localPrefix, importArgs}
+ 	if ofile == archive {
+ 		args = append(args, "-pack")
+@@ -2594,6 +2586,55 @@ func (tools gccgoToolchain) gc(b *builde
+ 	if p.localPrefix != "" {
+ 		gcargs = append(gcargs, "-fgo-relative-import-path="+p.localPrefix)
+ 	}
++	savedirs := []string{}
++	for _, incdir := range importArgs {
++		if incdir != "-I" {
++			savedirs = append(savedirs, incdir)
++		}
++	}
++
++	for _, path := range p.Imports {
++		// If this is a new vendor path, add it to the list of importArgs
++		if i := strings.LastIndex(path, "/vendor"); i >= 0 {
++			for _, dir := range savedirs {
++				// Check if the vendor path is already included in dir
++				if strings.HasSuffix(dir, path[:i+len("/vendor")]) {
++					continue
++				}
++				// Make sure this vendor path is not already in the list for importArgs
++				vendorPath := dir + "/" + path[:i+len("/vendor")]
++				for _, imp := range importArgs {
++					if imp == "-I" {
++						continue
++					}
++					// This vendorPath is already in the list
++					if imp == vendorPath {
++						goto nextSuffixPath
++					}
++				}
++				// New vendorPath not yet in the importArgs list, so add it
++				importArgs = append(importArgs, "-I", vendorPath)
++			nextSuffixPath:
++			}
++		} else if strings.HasPrefix(path, "vendor/") {
++			for _, dir := range savedirs {
++				// Make sure this vendor path is not already in the list for importArgs
++				vendorPath := dir + "/" + path[len("/vendor"):]
++				for _, imp := range importArgs {
++					if imp == "-I" {
++						continue
++					}
++					if imp == vendorPath {
++						goto nextPrefixPath
++					}
++				}
++				// This vendor path is needed and not already in the list, so add it
++				importArgs = append(importArgs, "-I", vendorPath)
++			nextPrefixPath:
++			}
++		}
++	}
++
+ 	args := stringList(tools.compiler(), importArgs, "-c", gcargs, "-o", ofile, buildGccgoflags)
+ 	for _, f := range gofiles {
+ 		args = append(args, mkAbs(p.Dir, f))
--- gcc-6-6.4.0.orig/debian/patches/pr78774.diff
+++ gcc-6-6.4.0/debian/patches/pr78774.diff
@@ -0,0 +1,48 @@
+# DP: Fix PR c++/78774, proposed for the gcc-6-branch
+
+PR c++/78774 - [6/7 Regression] ICE in constexpr string literals and templates
+
+gcc/cp/ChangeLog:
+
+	PR c++/78774
+	* pt.c (convert_template_argument): Avoid assuming operand type
+	is non-null since that of SCOPE_REF is not.
+
+gcc/testsuite/ChangeLog:
+
+	PR c++/78774
+	* g++.dg/cpp1y/pr78774.C: New test.
+
+Index: b/src/gcc/cp/pt.c
+===================================================================
+--- a/src/gcc/cp/pt.c
++++ b/src/gcc/cp/pt.c
+@@ -7285,9 +7285,11 @@ convert_template_argument (tree parm,
+           /* Reject template arguments that are references to built-in
+              functions with no library fallbacks.  */
+           const_tree inner = TREE_OPERAND (val, 0);
+-          if (TREE_CODE (TREE_TYPE (inner)) == REFERENCE_TYPE
+-              && TREE_CODE (TREE_TYPE (TREE_TYPE (inner))) == FUNCTION_TYPE
+-              && TREE_CODE (TREE_TYPE (inner)) == REFERENCE_TYPE
++	  const_tree innertype = TREE_TYPE (inner);
++          if (innertype
++	      && TREE_CODE (innertype) == REFERENCE_TYPE
++              && TREE_CODE (TREE_TYPE (innertype)) == FUNCTION_TYPE
++              && TREE_CODE (innertype) == REFERENCE_TYPE
+               && 0 < TREE_OPERAND_LENGTH (inner)
+               && reject_gcc_builtin (TREE_OPERAND (inner, 0)))
+               return error_mark_node;
+Index: b/src/gcc/testsuite/g++.dg/cpp1y/pr78774.C
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/g++.dg/cpp1y/pr78774.C
+@@ -0,0 +1,9 @@
++// PR c++/78774 - [6/7 Regression] ICE in constexpr string literals and
++// templates
++// { dg-do compile { target c++14 } }
++
++template <int> struct ops {
++  template <int> struct A;
++  template <int *Ptr> using explode = typename A<*Ptr>::join;
++};
++template <typename Ts> typename ops<'\0'>::explode<Ts::join>::type a;
--- gcc-6-6.4.0.orig/debian/patches/pr79041-linaro.diff
+++ gcc-6-6.4.0/debian/patches/pr79041-linaro.diff
@@ -0,0 +1,15 @@
+# DP: Fix PR target/79041, aarch64 backend emitting R_AARCH64_ADR_PREL_PG_HI21
+# DP: relocation despite -mpc-relative-literal-loads option being used
+
+--- a/src/gcc/config/aarch64/aarch64.c	2017-06-20 17:22:23.967114886 +0200
++++ b/src/gcc/config/aarch64/aarch64.c	2017-06-20 17:31:37.023190332 +0200
+@@ -9556,7 +9556,8 @@
+ 	  /* This is alright even in PIC code as the constant
+ 	     pool reference is always PC relative and within
+ 	     the same translation unit.  */
+-	  if (CONSTANT_POOL_ADDRESS_P (x))
++	  if (!aarch64_pcrelative_literal_loads
++	      && CONSTANT_POOL_ADDRESS_P (x))
+ 	    return SYMBOL_SMALL_ABSOLUTE;
+ 	  else
+ 	    return SYMBOL_FORCE_TO_MEM;
--- gcc-6-6.4.0.orig/debian/patches/pr79041.diff
+++ gcc-6-6.4.0/debian/patches/pr79041.diff
@@ -0,0 +1,177 @@
+# DP: Fix PR target/79041.
+
+--- a/src/gcc/config/aarch64/aarch64-protos.h
++++ b/src/gcc/config/aarch64/aarch64-protos.h
+@@ -436,7 +436,6 @@ int aarch64_ccmp_mode_to_code (enum machine_mode mode);
+ bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);
+ bool aarch64_operands_ok_for_ldpstp (rtx *, bool, enum machine_mode);
+ bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, enum machine_mode);
+-extern bool aarch64_nopcrelative_literal_loads;
+ 
+ extern void aarch64_asm_output_pool_epilogue (FILE *, const char *,
+ 					      tree, HOST_WIDE_INT);
+--- a/src/gcc/config/aarch64/aarch64.c
++++ b/src/gcc/config/aarch64/aarch64.c
+@@ -152,7 +152,7 @@ enum aarch64_processor aarch64_tune = cortexa53;
+ unsigned long aarch64_tune_flags = 0;
+ 
+ /* Global flag for PC relative loads.  */
+-bool aarch64_nopcrelative_literal_loads;
++bool aarch64_pcrelative_literal_loads;
+ 
+ /* Support for command line parsing of boolean flags in the tuning
+    structures.  */
+@@ -1703,7 +1703,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
+ 	     we need to expand the literal pool access carefully.
+ 	     This is something that needs to be done in a number
+ 	     of places, so could well live as a separate function.  */
+-	  if (aarch64_nopcrelative_literal_loads)
++	  if (!aarch64_pcrelative_literal_loads)
+ 	    {
+ 	      gcc_assert (can_create_pseudo_p ());
+ 	      base = gen_reg_rtx (ptr_mode);
+@@ -4028,7 +4028,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
+ 	  return ((GET_CODE (sym) == LABEL_REF
+ 		   || (GET_CODE (sym) == SYMBOL_REF
+ 		       && CONSTANT_POOL_ADDRESS_P (sym)
+-		       && !aarch64_nopcrelative_literal_loads)));
++		       && aarch64_pcrelative_literal_loads)));
+ 	}
+       return false;
+ 
+@@ -5183,7 +5183,7 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
+   if (MEM_P (x) && GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)
+       && (SCALAR_FLOAT_MODE_P (GET_MODE (x))
+ 	  || targetm.vector_mode_supported_p (GET_MODE (x)))
+-      && aarch64_nopcrelative_literal_loads)
++      && !aarch64_pcrelative_literal_loads)
+     {
+       sri->icode = aarch64_constant_pool_reload_icode (mode);
+       return NO_REGS;
+@@ -5517,7 +5517,7 @@ aarch64_uxt_size (int shift, HOST_WIDE_INT mask)
+ static inline bool
+ aarch64_can_use_per_function_literal_pools_p (void)
+ {
+-  return (!aarch64_nopcrelative_literal_loads
++  return (aarch64_pcrelative_literal_loads
+ 	  || aarch64_cmodel == AARCH64_CMODEL_LARGE);
+ }
+ 
+@@ -8043,32 +8043,31 @@ aarch64_override_options_after_change_1 (struct gcc_options *opts)
+ 	opts->x_align_functions = aarch64_tune_params.function_align;
+     }
+ 
+-  /* If nopcrelative_literal_loads is set on the command line, this
++  /* We default to no pc-relative literal loads.  */
++
++  aarch64_pcrelative_literal_loads = false;
++
++  /* If -mpc-relative-literal-loads is set on the command line, this
+      implies that the user asked for PC relative literal loads.  */
+-  if (opts->x_nopcrelative_literal_loads == 1)
+-    aarch64_nopcrelative_literal_loads = false;
++  if (opts->x_pcrelative_literal_loads == 1)
++    aarch64_pcrelative_literal_loads = true;
+ 
+-  /* If it is not set on the command line, we default to no pc
+-     relative literal loads, unless the workaround for Cortex-A53
+-     erratum 843419 is in effect.  */
+   /* This is PR70113. When building the Linux kernel with
+      CONFIG_ARM64_ERRATUM_843419, support for relocations
+      R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
+      removed from the kernel to avoid loading objects with possibly
+-     offending sequences. With nopcrelative_literal_loads, we would
++     offending sequences.  Without -mpc-relative-literal-loads we would
+      generate such relocations, preventing the kernel build from
+      succeeding.  */
+-  if (opts->x_nopcrelative_literal_loads == 2
+-      && !TARGET_FIX_ERR_A53_843419)
+-    aarch64_nopcrelative_literal_loads = true;
++  if (opts->x_pcrelative_literal_loads == 2
++      && TARGET_FIX_ERR_A53_843419)
++    aarch64_pcrelative_literal_loads = true;
+ 
+-  /* In the tiny memory model it makes no sense
+-     to disallow non PC relative literal pool loads
+-     as many other things will break anyway.  */
+-  if (opts->x_nopcrelative_literal_loads
+-      && (aarch64_cmodel == AARCH64_CMODEL_TINY
+-	  || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC))
+-    aarch64_nopcrelative_literal_loads = false;
++  /* In the tiny memory model it makes no sense to disallow PC relative
++     literal pool loads.  */
++  if (aarch64_cmodel == AARCH64_CMODEL_TINY
++      || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
++    aarch64_pcrelative_literal_loads = true;
+ }
+ 
+ /* 'Unpack' up the internal tuning structs and update the options
+@@ -9314,7 +9313,7 @@ aarch64_classify_symbol (rtx x, rtx offset)
+ 	  /* This is alright even in PIC code as the constant
+ 	     pool reference is always PC relative and within
+ 	     the same translation unit.  */
+-	  if (nopcrelative_literal_loads
++	  if (!aarch64_pcrelative_literal_loads
+ 	      && CONSTANT_POOL_ADDRESS_P (x))
+ 	    return SYMBOL_SMALL_ABSOLUTE;
+ 	  else
+--- a/src/gcc/config/aarch64/aarch64.md
++++ b/src/gcc/config/aarch64/aarch64.md
+@@ -4775,7 +4775,7 @@
+  [(set (match_operand:GPF_TF 0 "register_operand" "=w")
+        (mem:GPF_TF (match_operand 1 "aarch64_constant_pool_symref" "S")))
+   (clobber (match_operand:P 2 "register_operand" "=&r"))]
+- "TARGET_FLOAT && aarch64_nopcrelative_literal_loads"
++ "TARGET_FLOAT"
+  {
+    aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
+    emit_move_insn (operands[0], gen_rtx_MEM (<GPF_TF:MODE>mode, operands[2]));
+@@ -4788,7 +4788,7 @@
+  [(set (match_operand:VALL 0 "register_operand" "=w")
+        (mem:VALL (match_operand 1 "aarch64_constant_pool_symref" "S")))
+   (clobber (match_operand:P 2 "register_operand" "=&r"))]
+- "TARGET_FLOAT && aarch64_nopcrelative_literal_loads"
++ "TARGET_FLOAT"
+  {
+    aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
+    emit_move_insn (operands[0], gen_rtx_MEM (<VALL:MODE>mode, operands[2]));
+--- a/src/gcc/config/aarch64/aarch64.opt
++++ b/src/gcc/config/aarch64/aarch64.opt
+@@ -146,7 +146,7 @@ EnumValue
+ Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64)
+ 
+ mpc-relative-literal-loads
+-Target Report Save Var(nopcrelative_literal_loads) Init(2) Save
++Target Report Save Var(pcrelative_literal_loads) Init(2) Save
+ PC relative literal loads.
+ 
+ mlow-precision-recip-sqrt
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr79041.c
+@@ -0,0 +1,26 @@
++/* PR target/79041.  Check that we don't generate the LO12 relocations
++   for -mpc-relative-literal-loads.  */
++/* { dg-do compile } */
++/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads" } */
++
++extern int strcmp(const char *, const char *);
++extern char * strcpy(char *,const char *);
++
++static struct {
++    char *b;
++    char *c;
++} d[] = {
++      { "0", "000000000000000" },
++      { "1", "111111111111111" },
++};
++
++void
++e (const char *b, char *c)
++{
++    int i;
++    for (i = 0; i < 1; ++i)
++      if (!strcmp(d[i].b, b))
++	strcpy(c, d[i].c);
++}
++
++/* { dg-final { scan-assembler-not ":lo12:" } } */
--- gcc-6-6.4.0.orig/debian/patches/pr80533.diff
+++ gcc-6-6.4.0/debian/patches/pr80533.diff
@@ -0,0 +1,27 @@
+# DP: Fix PR middle-end/80533, taken from the trunk.
+
+gcc/
+
+2017-04-27  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/80533
+	* emit-rtl.c (set_mem_attributes_minus_bitpos): When
+	stripping ARRAY_REFs from MEM_EXPR make sure we're not
+	keeping a reference to a trailing array.
+
+Index: b/src/gcc/emit-rtl.c
+===================================================================
+--- a/src/gcc/emit-rtl.c
++++ b/src/gcc/emit-rtl.c
+@@ -1930,7 +1930,10 @@ set_mem_attributes_minus_bitpos (rtx ref
+ 	  while (TREE_CODE (t2) == ARRAY_REF);
+ 
+ 	  if (DECL_P (t2)
+-	      || TREE_CODE (t2) == COMPONENT_REF)
++	      || (TREE_CODE (t2) == COMPONENT_REF
++		  /* For trailing arrays t2 doesn't have a size that
++		     covers all valid accesses.  */
++		  && ! array_at_struct_end_p (t)))
+ 	    {
+ 	      attrs.expr = t2;
+ 	      attrs.offset_known_p = false;
--- gcc-6-6.4.0.orig/debian/patches/rename-info-files.diff
+++ gcc-6-6.4.0/debian/patches/rename-info-files.diff
@@ -0,0 +1,839 @@
+# DP: Allow transformations on info file names. Reference the
+# DP: transformed info file names in the texinfo files.
+
+
+2004-02-17  Matthias Klose  <doko@debian.org>
+
+gcc/ChangeLog:
+	* Makefile.in: Allow transformations on info file names.
+	Define MAKEINFODEFS, macros to pass transformated info file
+	names to makeinfo.
+	* doc/cpp.texi: Use macros defined in MAKEINFODEFS for references.
+	* doc/cppinternals.texi: Likewise.
+	* doc/extend.texi: Likewise.
+	* doc/gcc.texi: Likewise.
+	* doc/gccint.texi: Likewise.
+	* doc/invoke.texi: Likewise.
+	* doc/libgcc.texi: Likewise.
+	* doc/makefile.texi: Likewise.
+	* doc/passes.texi: Likewise.
+	* doc/sourcebuild.texi: Likewise.
+	* doc/standards.texi: Likewise.
+	* doc/trouble.texi: Likewise.
+
+gcc/fortran/ChangeLog:
+	* Make-lang.in: Allow transformations on info file names.
+	Pass macros of transformated info file defined in MAKEINFODEFS
+	names to makeinfo.
+	* gfortran.texi: Use macros defined in MAKEINFODEFS for references.
+
+gcc/java/ChangeLog:
+	* Make-lang.in: Allow transformations on info file names.
+	Pass macros of transformated info file defined in MAKEINFODEFS
+
+Index: b/src/gcc/fortran/gfortran.texi
+===================================================================
+--- a/src/gcc/fortran/gfortran.texi
++++ b/src/gcc/fortran/gfortran.texi
+@@ -101,7 +101,7 @@ Texts being (a) (see below), and with th
+ @ifinfo
+ @dircategory Software development
+ @direntry
+-* gfortran: (gfortran).                  The GNU Fortran Compiler.
++* @value{fngfortran}: (@value{fngfortran}).                  The GNU Fortran Compiler.
+ @end direntry
+ This file documents the use and the internals of
+ the GNU Fortran compiler, (@command{gfortran}).
+Index: b/src/gcc/fortran/Make-lang.in
+===================================================================
+--- a/src/gcc/fortran/Make-lang.in
++++ b/src/gcc/fortran/Make-lang.in
+@@ -114,7 +114,8 @@ fortran.tags: force
+ 	cd $(srcdir)/fortran; etags -o TAGS.sub *.c *.h; \
+ 	etags --include TAGS.sub --include ../TAGS.sub
+ 
+-fortran.info: doc/gfortran.info doc/gfc-internals.info
++INFO_FORTRAN_NAME = $(shell echo gfortran|sed '$(program_transform_name)')
++fortran.info: doc/$(INFO_FORTRAN_NAME).info
+ fortran.dvi: doc/gfortran.dvi doc/gfc-internals.dvi
+ 
+ F95_HTMLFILES = $(build_htmldir)/gfortran
+@@ -181,10 +182,10 @@ GFORTRAN_TEXI = \
+   $(srcdir)/doc/include/gcc-common.texi \
+   gcc-vers.texi
+ 
+-doc/gfortran.info: $(GFORTRAN_TEXI)
++doc/$(INFO_FORTRAN_NAME).info: $(GFORTRAN_TEXI)
+ 	if [ x$(BUILD_INFO) = xinfo ]; then \
+ 	  rm -f doc/gfortran.info-*; \
+-	  $(MAKEINFO) -I $(srcdir)/doc/include -I $(srcdir)/fortran \
++	  $(MAKEINFO) $(MAKEINFODEFS) -I $(srcdir)/doc/include -I $(srcdir)/fortran \
+ 	    -o $@ $<; \
+ 	else true; fi
+ 
+@@ -249,7 +250,7 @@ fortran.install-common: install-finclude
+ 
+ fortran.install-plugin:
+ 
+-fortran.install-info: $(DESTDIR)$(infodir)/gfortran.info
++fortran.install-info: $(DESTDIR)$(infodir)/$(INFO_FORTRAN_NAME).info
+ 
+ fortran.install-man: $(DESTDIR)$(man1dir)/$(GFORTRAN_INSTALL_NAME)$(man1ext)
+ 
+@@ -267,7 +268,7 @@ fortran.uninstall:
+ 	rm -rf $(DESTDIR)$(bindir)/$(GFORTRAN_INSTALL_NAME)$(exeext); \
+ 	rm -rf $(DESTDIR)$(man1dir)/$(GFORTRAN_INSTALL_NAME)$(man1ext); \
+ 	rm -rf $(DESTDIR)$(bindir)/$(GFORTRAN_TARGET_INSTALL_NAME)$(exeext); \
+-	rm -rf $(DESTDIR)$(infodir)/gfortran.info*
++	rm -rf $(DESTDIR)$(infodir)/$(INFO_FORTRAN_NAME).info*
+ 
+ #
+ # Clean hooks:
+Index: b/src/gcc/Makefile.in
+===================================================================
+--- a/src/gcc/Makefile.in
++++ b/src/gcc/Makefile.in
+@@ -2961,8 +2961,33 @@ install-no-fixedincludes:
+ 
+ doc: $(BUILD_INFO) $(GENERATED_MANPAGES)
+ 
+-INFOFILES = doc/cpp.info doc/gcc.info doc/gccint.info \
+-            doc/gccinstall.info doc/cppinternals.info
++INFO_CPP_NAME = $(shell echo cpp|sed '$(program_transform_name)')
++INFO_GCC_NAME = $(shell echo gcc|sed '$(program_transform_name)')
++INFO_GXX_NAME = $(shell echo g++|sed '$(program_transform_name)')
++INFO_GCCINT_NAME = $(shell echo gccint|sed '$(program_transform_name)')
++INFO_GCCINSTALL_NAME = $(shell echo gccinstall|sed '$(program_transform_name)')
++INFO_CPPINT_NAME = $(shell echo cppinternals|sed '$(program_transform_name)')
++
++INFO_FORTRAN_NAME = $(shell echo gfortran|sed '$(program_transform_name)')
++INFO_GCJ_NAME = $(shell echo gcj|sed '$(program_transform_name)')
++INFO_GCCGO_NAME = $(shell echo gccgo|sed '$(program_transform_name)')
++
++INFOFILES = doc/$(INFO_CPP_NAME).info doc/$(INFO_GCC_NAME).info \
++            doc/$(INFO_GCCINT_NAME).info \
++            doc/$(INFO_GCCINSTALL_NAME).info doc/$(INFO_CPPINT_NAME).info
++
++MAKEINFODEFS = -D 'fncpp $(INFO_CPP_NAME)' \
++               -D 'fngcc $(INFO_GCC_NAME)' \
++               -D 'fngcov $(INFO_GCC_NAME)' \
++               -D 'fngcovtool $(INFO_GCC_NAME)' \
++               -D 'fngcovdump $(INFO_GCC_NAME)' \
++               -D 'fngxx $(INFO_GXX_NAME)' \
++               -D 'fngccint $(INFO_GCCINT_NAME)' \
++               -D 'fngccinstall $(INFO_GCCINSTALL_NAME)' \
++               -D 'fncppint $(INFO_CPPINT_NAME)' \
++               -D 'fngfortran $(INFO_FORTRAN_NAME)' \
++               -D 'fngcj $(INFO_GCJ_NAME)' \
++               -D 'fngccgo $(INFO_GCCGO_NAME)'
+ 
+ info: $(INFOFILES) lang.info @GENINSRC@ srcinfo lang.srcinfo
+ 
+@@ -3009,7 +3034,21 @@ gcc-vers.texi: $(BASEVER) $(DEVPHASE)
+ 	if [ -n "$(PKGVERSION)" ]; then \
+ 	  echo "@set VERSION_PACKAGE $(PKGVERSION)" >> $@T; \
+ 	fi
+-	echo "@set BUGURL $(BUGURL_TEXI)" >> $@T; \
++	echo "@set BUGURL $(BUGURL_TEXI)" >> $@T
++	( \
++	  echo '@set fncpp $(INFO_CPP_NAME)'; \
++	  echo '@set fngcc $(INFO_GCC_NAME)'; \
++	  echo '@set fngcov $(INFO_GCC_NAME)'; \
++	  echo '@set fngcovtool $(INFO_GCC_NAME)'; \
++	  echo '@set fngcovdump $(INFO_GCC_NAME)'; \
++	  echo '@set fngxx $(INFO_GXX_NAME)'; \
++	  echo '@set fngccint $(INFO_GCCINT_NAME)'; \
++	  echo '@set fngccinstall $(INFO_GCCINSTALL_NAME)'; \
++	  echo '@set fncppint $(INFO_CPPINT_NAME)'; \
++	  echo '@set fngfortran $(INFO_FORTRAN_NAME)'; \
++	  echo '@set fngcj $(INFO_GCJ_NAME)'; \
++	  echo '@set fngccgo $(INFO_GCCGO_NAME)'; \
++	) >> $@T
+ 	mv -f $@T $@
+ 
+ 
+@@ -3017,21 +3056,41 @@ gcc-vers.texi: $(BASEVER) $(DEVPHASE)
+ # patterns.  To use them, put each of the specific targets with its
+ # specific dependencies but no build commands.
+ 
+-doc/cpp.info: $(TEXI_CPP_FILES)
+-doc/gcc.info: $(TEXI_GCC_FILES)
+-doc/gccint.info: $(TEXI_GCCINT_FILES)
+-doc/cppinternals.info: $(TEXI_CPPINT_FILES)
+-
++# Generic entry to handle info files, which are not renamed (currently Ada)
+ doc/%.info: %.texi
+ 	if [ x$(BUILD_INFO) = xinfo ]; then \
+ 		$(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \
+ 			-I $(gcc_docdir)/include -o $@ $<; \
+ 	fi
+ 
++doc/$(INFO_CPP_NAME).info: $(TEXI_CPP_FILES)
++	if [ x$(BUILD_INFO) = xinfo ]; then \
++		$(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
++			-I $(gcc_docdir)/include -o $@ $<; \
++	fi
++
++doc/$(INFO_GCC_NAME).info: $(TEXI_GCC_FILES)
++	if [ x$(BUILD_INFO) = xinfo ]; then \
++		$(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
++			-I $(gcc_docdir)/include -o $@ $<; \
++	fi
++
++doc/$(INFO_GCCINT_NAME).info: $(TEXI_GCCINT_FILES)
++	if [ x$(BUILD_INFO) = xinfo ]; then \
++		$(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
++			-I $(gcc_docdir)/include -o $@ $<; \
++	fi
++
++doc/$(INFO_CPPINT_NAME).info: $(TEXI_CPPINT_FILES)
++	if [ x$(BUILD_INFO) = xinfo ]; then \
++		$(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
++			-I $(gcc_docdir)/include -o $@ $<; \
++	fi
++
+ # Duplicate entry to handle renaming of gccinstall.info
+-doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES)
++doc/$(INFO_GCCINSTALL_NAME).info: $(TEXI_GCCINSTALL_FILES)
+ 	if [ x$(BUILD_INFO) = xinfo ]; then \
+-		$(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \
++		$(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
+ 			-I $(gcc_docdir)/include -o $@ $<; \
+ 	fi
+ 
+@@ -3443,11 +3502,11 @@ install-driver: installdirs xgcc$(exeext
+ # $(INSTALL_DATA) might be a relative pathname, so we can't cd into srcdir
+ # to do the install.
+ install-info:: doc installdirs \
+-	$(DESTDIR)$(infodir)/cpp.info \
+-	$(DESTDIR)$(infodir)/gcc.info \
+-	$(DESTDIR)$(infodir)/cppinternals.info \
+-	$(DESTDIR)$(infodir)/gccinstall.info \
+-	$(DESTDIR)$(infodir)/gccint.info \
++	$(DESTDIR)$(infodir)/$(INFO_CPP_NAME).info \
++	$(DESTDIR)$(infodir)/$(INFO_GCC_NAME).info \
++	$(DESTDIR)$(infodir)/$(INFO_CPPINT_NAME).info \
++	$(DESTDIR)$(infodir)/$(INFO_GCCINSTALL_NAME).info \
++	$(DESTDIR)$(infodir)/$(INFO_GCCINT_NAME).info \
+ 	lang.install-info
+ 
+ $(DESTDIR)$(infodir)/%.info: doc/%.info installdirs
+@@ -3668,8 +3727,11 @@ uninstall: lang.uninstall
+ 	-rm -rf $(DESTDIR)$(bindir)/$(GCOV_INSTALL_NAME)$(exeext)
+ 	-rm -rf $(DESTDIR)$(man1dir)/$(GCC_INSTALL_NAME)$(man1ext)
+ 	-rm -rf $(DESTDIR)$(man1dir)/cpp$(man1ext)
+-	-rm -f $(DESTDIR)$(infodir)/cpp.info* $(DESTDIR)$(infodir)/gcc.info*
+-	-rm -f $(DESTDIR)$(infodir)/cppinternals.info* $(DESTDIR)$(infodir)/gccint.info*
++	-rm -f $(DESTDIR)$(infodir)/$(INFO_CPP_NAME).info*
++	-rm -f $(DESTDIR)$(infodir)/$(INFO_GCC_NAME).info*
++	-rm -f $(DESTDIR)$(infodir)/$(INFO_CPPINT_NAME).info*
++	-rm -f $(DESTDIR)$(infodir)/$(INFO_GCCINT_NAME).info*
++	-rm -f $(DESTDIR)$(infodir)/$(INFO_GCCINSTALL_NAME).info*
+ 	for i in ar nm ranlib ; do \
+ 	  install_name=`echo gcc-$$i|sed '$(program_transform_name)'`$(exeext) ;\
+ 	  target_install_name=$(target_noncanonical)-`echo gcc-$$i|sed '$(program_transform_name)'`$(exeext) ; \
+Index: b/src/gcc/java/gcj.texi
+===================================================================
+--- a/src/gcc/java/gcj.texi
++++ b/src/gcc/java/gcj.texi
+@@ -55,25 +55,25 @@ man page gfdl(7).
+ @format
+ @dircategory Software development
+ @direntry
+-* Gcj: (gcj).               Ahead-of-time compiler for the Java language
++* @value{fngcj}: (@value{fngcj}).               Ahead-of-time compiler for the Java language
+ @end direntry
+ 
+ @dircategory Individual utilities
+ @direntry
+-* jcf-dump: (gcj)Invoking jcf-dump.
++* jcf-dump: (@value{fngcj}) Invoking jcf-dump.
+                             Print information about Java class files
+-* gij: (gcj)Invoking gij.   GNU interpreter for Java bytecode
+-* gcj-dbtool: (gcj)Invoking gcj-dbtool.
++* gij: (@value{fngcj}) Invoking gij.   GNU interpreter for Java bytecode
++* gcj-dbtool: (@value{fngcj}) Invoking gcj-dbtool.
+                             Tool for manipulating class file databases.
+-* jv-convert: (gcj)Invoking jv-convert.
++* jv-convert: (@value{fngcj}) Invoking jv-convert.
+                             Convert file from one encoding to another
+-* grmic: (gcj)Invoking grmic.
++* grmic: (@value{fngcj}) Invoking grmic.
+                             Generate stubs for Remote Method Invocation.
+-* gc-analyze: (gcj)Invoking gc-analyze.
++* gc-analyze: (@value{fngcj}) Invoking gc-analyze.
+                             Analyze Garbage Collector (GC) memory dumps.
+-* aot-compile: (gcj)Invoking aot-compile.
++* aot-compile: (@value{fngcj})Invoking aot-compile.
+                             Compile bytecode to native and generate databases.
+-* rebuild-gcj-db: (gcj)Invoking rebuild-gcj-db.
++* rebuild-gcj-db: (@value{fngcj})Invoking rebuild-gcj-db.
+                             Merge the per-solib databases made by aot-compile
+                             into one system-wide database.
+ @end direntry
+@@ -159,7 +159,7 @@ and the Info entries for @file{gcj} and
+ 
+ As @command{gcj} is just another front end to @command{gcc}, it supports many
+ of the same options as gcc.  @xref{Option Summary, , Option Summary,
+-gcc, Using the GNU Compiler Collection (GCC)}.  This manual only documents the
++@value{fngcc}, Using the GNU Compiler Collection (GCC)}.  This manual only documents the
+ options specific to @command{gcj}.
+ 
+ @c man end
+Index: b/src/gcc/java/Make-lang.in
+===================================================================
+--- a/src/gcc/java/Make-lang.in
++++ b/src/gcc/java/Make-lang.in
+@@ -122,9 +122,10 @@ java.tags: force
+ 	etags --include TAGS.sub --include ../TAGS.sub
+ 
+ 
+-java.info: doc/gcj.info
++INFO_GCJ_NAME = $(shell echo gcj|sed '$(program_transform_name)')
++java.info: doc/$(INFO_GCJ_NAME).info
+ 
+-java.srcinfo: doc/gcj.info
++java.srcinfo: doc/$(INFO_GCJ_NAME).info
+ 	-cp -p $^ $(srcdir)/doc
+ 
+ java.dvi: doc/gcj.dvi
+@@ -190,7 +191,7 @@ java.uninstall:
+ 	-rm -rf $(DESTDIR)$(man1dir)/aot-compile$(man1ext)
+ 	-rm -rf $(DESTDIR)$(man1dir)/rebuild-gcj-db$(man1ext)
+ 
+-java.install-info: $(DESTDIR)$(infodir)/gcj.info
++java.install-info: $(DESTDIR)$(infodir)/$(INFO_GCJ_NAME).info
+ 
+ java.install-pdf: $(JAVA_PDFFILES)
+ 	@$(NORMAL_INSTALL)
+@@ -273,10 +274,10 @@ TEXI_JAVA_FILES = java/gcj.texi $(gcc_do
+ 	 gcc-vers.texi
+ 
+ # Documentation
+-doc/gcj.info: $(TEXI_JAVA_FILES)
++doc/$(INFO_GCJ_NAME).info: $(TEXI_JAVA_FILES)
+ 	if test "x$(BUILD_INFO)" = xinfo; then \
+-	  rm -f doc/gcj.info*; \
+-	  $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \
++	  rm -f doc/$(INFO_GCJ_NAME).info*; \
++	  $(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
+ 		-I $(gcc_docdir)/include -o $@ $<; \
+ 	else true; fi
+ 
+Index: b/src/gcc/ada/gnat-style.texi
+===================================================================
+--- a/src/gcc/ada/gnat-style.texi
++++ b/src/gcc/ada/gnat-style.texi
+@@ -31,7 +31,7 @@ Texts.  A copy of the license is include
+ 
+ @dircategory Software development
+ @direntry
+-* gnat-style: (gnat-style).      GNAT Coding Style
++* gnat-style: (gnat-style-6).      GNAT Coding Style
+ @end direntry
+ 
+ @macro syntax{element}
+Index: b/src/gcc/ada/gnat_rm.texi
+===================================================================
+--- a/src/gcc/ada/gnat_rm.texi
++++ b/src/gcc/ada/gnat_rm.texi
+@@ -12,7 +12,7 @@
+ @finalout
+ @dircategory GNU Ada Tools 
+ @direntry
+-* gnat_rm: (gnat_rm.info). gnat_rm
++* GNAT Reference Manual: (gnat_rm-6).  Reference Manual for GNU Ada tools.
+ @end direntry
+ 
+ @definfoenclose strong,`,'
+Index: b/src/gcc/doc/invoke.texi
+===================================================================
+--- a/src/gcc/doc/invoke.texi
++++ b/src/gcc/doc/invoke.texi
+@@ -10585,7 +10585,7 @@ One of the standard libraries bypassed b
+ @option{-nodefaultlibs} is @file{libgcc.a}, a library of internal subroutines
+ which GCC uses to overcome shortcomings of particular machines, or special
+ needs for some languages.
+-(@xref{Interface,,Interfacing to GCC Output,gccint,GNU Compiler
++(@xref{Interface,,Interfacing to GCC Output,@value{fngccint},GNU Compiler
+ Collection (GCC) Internals},
+ for more discussion of @file{libgcc.a}.)
+ In most cases, you need @file{libgcc.a} even when you want to avoid
+@@ -10594,7 +10594,7 @@ or @option{-nodefaultlibs} you should us
+ This ensures that you have no unresolved references to internal GCC
+ library subroutines.
+ (An example of such an internal subroutine is @code{__main}, used to ensure C++
+-constructors are called; @pxref{Collect2,,@code{collect2}, gccint,
++constructors are called; @pxref{Collect2,,@code{collect2}, @value{fngccint},
+ GNU Compiler Collection (GCC) Internals}.)
+ 
+ @item -pie
+@@ -25102,7 +25102,7 @@ Note that you can also specify places to
+ @option{-B}, @option{-I} and @option{-L} (@pxref{Directory Options}).  These
+ take precedence over places specified using environment variables, which
+ in turn take precedence over those specified by the configuration of GCC@.
+-@xref{Driver,, Controlling the Compilation Driver @file{gcc}, gccint,
++@xref{Driver,, Controlling the Compilation Driver @file{gcc}, @value{fngccint},
+ GNU Compiler Collection (GCC) Internals}.
+ 
+ @table @env
+@@ -25262,7 +25262,7 @@ the headers it contains change.
+ 
+ A precompiled header file is searched for when @code{#include} is
+ seen in the compilation.  As it searches for the included file
+-(@pxref{Search Path,,Search Path,cpp,The C Preprocessor}) the
++(@pxref{Search Path,,Search Path,@value{fncpp},The C Preprocessor}) the
+ compiler looks for a precompiled header in each directory just before it
+ looks for the include file in that directory.  The name searched for is
+ the name specified in the @code{#include} with @samp{.gch} appended.  If
+Index: b/src/gcc/doc/extend.texi
+===================================================================
+--- a/src/gcc/doc/extend.texi
++++ b/src/gcc/doc/extend.texi
+@@ -20136,7 +20136,7 @@ want to write code that checks whether t
+ test for the GNU compiler the same way as for C programs: check for a
+ predefined macro @code{__GNUC__}.  You can also use @code{__GNUG__} to
+ test specifically for GNU C++ (@pxref{Common Predefined Macros,,
+-Predefined Macros,cpp,The GNU C Preprocessor}).
++Predefined Macros,@value{fncpp},The GNU C Preprocessor}).
+ 
+ @menu
+ * C++ Volatiles::       What constitutes an access to a volatile object.
+Index: b/src/gcc/doc/standards.texi
+===================================================================
+--- a/src/gcc/doc/standards.texi
++++ b/src/gcc/doc/standards.texi
+@@ -313,8 +313,8 @@ described at @uref{http://golang.org/doc
+ GNAT Reference Manual}, for information on standard
+ conformance and compatibility of the Ada compiler.
+ 
+-@xref{Standards,,Standards, gfortran, The GNU Fortran Compiler}, for details
++@xref{Standards,,Standards, @value{fngfortran}, The GNU Fortran Compiler}, for details
+ of standards supported by GNU Fortran.
+ 
+-@xref{Compatibility,,Compatibility with the Java Platform, gcj, GNU gcj},
++@xref{Compatibility,,Compatibility with the Java Platform, @value{fngcj}, GNU gcj},
+ for details of compatibility between @command{gcj} and the Java Platform.
+Index: b/src/gcc/doc/libgcc.texi
+===================================================================
+--- a/src/gcc/doc/libgcc.texi
++++ b/src/gcc/doc/libgcc.texi
+@@ -24,7 +24,7 @@ that needs them.
+ GCC will also generate calls to C library routines, such as
+ @code{memcpy} and @code{memset}, in some cases.  The set of routines
+ that GCC may possibly use is documented in @ref{Other
+-Builtins,,,gcc, Using the GNU Compiler Collection (GCC)}.
++Builtins,,,@value{fngcc}, Using the GNU Compiler Collection (GCC)}.
+ 
+ These routines take arguments and return values of a specific machine
+ mode, not a specific C type.  @xref{Machine Modes}, for an explanation
+Index: b/src/gcc/doc/gccint.texi
+===================================================================
+--- a/src/gcc/doc/gccint.texi
++++ b/src/gcc/doc/gccint.texi
+@@ -49,7 +49,7 @@ Texts being (a) (see below), and with th
+ @ifnottex
+ @dircategory Software development
+ @direntry
+-* gccint: (gccint).            Internals of the GNU Compiler Collection.
++* @value{fngccint}: (@value{fngccint}).            Internals of the GNU Compiler Collection.
+ @end direntry
+ This file documents the internals of the GNU compilers.
+ @sp 1
+@@ -81,7 +81,7 @@ write front ends for new languages.  It
+ @value{VERSION_PACKAGE}
+ @end ifset
+ version @value{version-GCC}.  The use of the GNU compilers is documented in a
+-separate manual.  @xref{Top,, Introduction, gcc, Using the GNU
++separate manual.  @xref{Top,, Introduction, @value{fngcc}, Using the GNU
+ Compiler Collection (GCC)}.
+ 
+ This manual is mainly a reference manual rather than a tutorial.  It
+Index: b/src/gcc/doc/cpp.texi
+===================================================================
+--- a/src/gcc/doc/cpp.texi
++++ b/src/gcc/doc/cpp.texi
+@@ -50,7 +50,7 @@ This manual contains no Invariant Sectio
+ @ifinfo
+ @dircategory Software development
+ @direntry
+-* Cpp: (cpp).                  The GNU C preprocessor.
++* @value{fncpp}: (@value{fncpp}).                  The GNU C preprocessor.
+ @end direntry
+ @end ifinfo
+ 
+Index: b/src/gcc/doc/gcc.texi
+===================================================================
+--- a/src/gcc/doc/gcc.texi
++++ b/src/gcc/doc/gcc.texi
+@@ -63,11 +63,11 @@ Texts being (a) (see below), and with th
+ @ifnottex
+ @dircategory Software development
+ @direntry
+-* gcc: (gcc).                  The GNU Compiler Collection.
+-* g++: (gcc).                  The GNU C++ compiler.
+-* gcov: (gcc) Gcov.            @command{gcov}---a test coverage program.
+-* gcov-tool: (gcc) Gcov-tool.  @command{gcov-tool}---an offline gcda profile processing program.
+-* gcov-dump: (gcc) Gcov-dump.  @command{gcov-dump}---an offline gcda and gcno profile dump tool.
++* @value{fngcc}: (@value{fngcc}).                  The GNU Compiler Collection.
++* @value{fngxx}: (@value{fngcc}).                  The GNU C++ compiler.
++* @value{fngcov}: (@value{fngcc}) Gcov.            @command{gcov}---a test coverage program.
++* @value{fngcovtool}: (@value{fngcc}) Gcov.            @command{gcov-tool}---an offline gcda profile processing program.
++* @value{fngcovdump}: (@value{fngcc}) Gcov.            @command{gcov-dump}---an offline gcda and gcno profile dump tool.
+ @end direntry
+ This file documents the use of the GNU compilers.
+ @sp 1
+@@ -127,7 +127,7 @@ version @value{version-GCC}.
+ The internals of the GNU compilers, including how to port them to new
+ targets and some information about how to write front ends for new
+ languages, are documented in a separate manual.  @xref{Top,,
+-Introduction, gccint, GNU Compiler Collection (GCC) Internals}.
++Introduction, @value{fngccint}, GNU Compiler Collection (GCC) Internals}.
+ 
+ @menu
+ * G++ and GCC::     You can compile C or C++ programs.
+Index: b/src/gcc/doc/makefile.texi
+===================================================================
+--- a/src/gcc/doc/makefile.texi
++++ b/src/gcc/doc/makefile.texi
+@@ -139,7 +139,7 @@ regardless of how it itself was compiled
+ Builds a compiler with profiling feedback information.  In this case,
+ the second and third stages are named @samp{profile} and @samp{feedback},
+ respectively.  For more information, see
+-@ref{Building,,Building with profile feedback,gccinstall,Installing GCC}.
++@ref{Building,,Building with profile feedback,@value{fngccinstall},Installing GCC}.
+ 
+ @item restrap
+ Restart a bootstrap, so that everything that was not built with
+Index: b/src/gcc/doc/install.texi
+===================================================================
+--- a/src/gcc/doc/install.texi
++++ b/src/gcc/doc/install.texi
+@@ -94,7 +94,7 @@ Free Documentation License}''.
+ @end ifinfo
+ @dircategory Software development
+ @direntry
+-* gccinstall: (gccinstall).    Installing the GNU Compiler Collection.
++* @value{fngccinstall}: (@value{fngccinstall}).    Installing the GNU Compiler Collection.
+ @end direntry
+ 
+ @c Part 3 Titlepage and Copyright
+Index: b/src/gcc/doc/cppinternals.texi
+===================================================================
+--- a/src/gcc/doc/cppinternals.texi
++++ b/src/gcc/doc/cppinternals.texi
+@@ -7,7 +7,7 @@
+ @ifinfo
+ @dircategory Software development
+ @direntry
+-* Cpplib: (cppinternals).      Cpplib internals.
++* @value{fncppint}: (@value{fncppint}).      Cpplib internals.
+ @end direntry
+ @end ifinfo
+ 
+Index: b/src/libgomp/libgomp.texi
+===================================================================
+--- a/src/libgomp/libgomp.texi
++++ b/src/libgomp/libgomp.texi
+@@ -31,7 +31,7 @@ texts being (a) (see below), and with th
+ @ifinfo
+ @dircategory GNU Libraries
+ @direntry
+-* libgomp: (libgomp).          GNU Offloading and Multi Processing Runtime Library.
++* @value{fnlibgomp}: (@value{fnlibgomp}).          GNU Offloading and Multi Processing Runtime Library.
+ @end direntry
+ 
+ This manual documents libgomp, the GNU Offloading and Multi Processing
+Index: b/src/libgomp/Makefile.in
+===================================================================
+--- a/src/libgomp/Makefile.in
++++ b/src/libgomp/Makefile.in
+@@ -484,7 +484,8 @@ info_TEXINFOS = libgomp.texi
+ 
+ # AM_CONDITIONAL on configure check ACX_CHECK_PROG_VER([MAKEINFO])
+ @BUILD_INFO_TRUE@STAMP_BUILD_INFO = stamp-build-info
+-CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) libgomp.info
++INFO_LIBGOMP_NAME = $(shell echo libgomp|sed '$(program_transform_name)')
++CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) $(INFO_LIBGOMP_NAME).info
+ MAINTAINERCLEANFILES = $(srcdir)/libgomp.info
+ all: config.h
+ 	$(MAKE) $(AM_MAKEFLAGS) all-recursive
+@@ -1296,15 +1297,16 @@ env.lo: libgomp_f.h
+ env.o: libgomp_f.h
+ 
+ all-local: $(STAMP_GENINSRC)
+-
+-stamp-geninsrc: libgomp.info
+-	cp -p $(top_builddir)/libgomp.info $(srcdir)/libgomp.info
++stamp-geninsrc: $(INFO_LIBGOMP_NAME).info
++	cp -p $(top_builddir)/$(INFO_LIBGOMP_NAME).info $(srcdir)/libgomp.info
+ 	@touch $@
+ 
+-libgomp.info: $(STAMP_BUILD_INFO)
++libgomp.info: $(INFO_LIBGOMP_NAME).info
++	[ "$(INFO_LIBGOMP_NAME).info" = libgomp.info ] || cp $(INFO_LIBGOMP_NAME).info libgomp.info
++$(INFO_LIBGOMP_NAME).info: $(STAMP_BUILD_INFO)
+ 
+ stamp-build-info: libgomp.texi
+-	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libgomp.info $(srcdir)/libgomp.texi
++	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -D 'fnlibgomp $(INFO_LIBGOMP_NAME)' -I $(srcdir) -o $(INFO_LIBGOMP_NAME).info $(srcdir)/libgomp.texi
+ 	@touch $@
+ 
+ # Tell versions [3.59,3.63) of GNU make to not export all variables.
+Index: b/src/libgomp/Makefile.am
+===================================================================
+--- a/src/libgomp/Makefile.am
++++ b/src/libgomp/Makefile.am
+@@ -125,16 +125,19 @@ endif
+ 
+ all-local: $(STAMP_GENINSRC)
+ 
+-stamp-geninsrc: libgomp.info
+-	cp -p $(top_builddir)/libgomp.info $(srcdir)/libgomp.info
++INFO_LIBGOMP_NAME = $(shell echo libgomp|sed '$(program_transform_name)')
++stamp-geninsrc: $(INFO_LIBGOMP_NAME).info
++	cp -p $(top_builddir)/$(INFO_LIBGOMP_NAME).info $(srcdir)/libgomp.info
+ 	@touch $@
+ 
+-libgomp.info: $(STAMP_BUILD_INFO)
++libgomp.info: $(INFO_LIBGOMP_NAME).info
++	cp $(INFO_LIBGOMP_NAME).info libgomp.info
++$(INFO_LIBGOMP_NAME).info: $(STAMP_BUILD_INFO)
+ 
+ stamp-build-info: libgomp.texi
+-	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libgomp.info $(srcdir)/libgomp.texi
++	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -D 'fnlibgomp $(INFO_LIBGOMP_NAME)' -I $(srcdir) -o $(INFO_LIBGOMP_NAME).info $(srcdir)/libgomp.texi
+ 	@touch $@
+ 
+ 
+-CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) libgomp.info
++CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) $(INFO_LIBGOMP_NAME).info
+ MAINTAINERCLEANFILES = $(srcdir)/libgomp.info
+Index: b/src/libitm/libitm.texi
+===================================================================
+--- a/src/libitm/libitm.texi
++++ b/src/libitm/libitm.texi
+@@ -20,7 +20,7 @@ Free Documentation License''.
+ @ifinfo
+ @dircategory GNU Libraries
+ @direntry
+-* libitm: (libitm).                    GNU Transactional Memory Library
++* @value{fnlibitm}: (@value{fnlibitm}).                    GNU Transactional Memory Library
+ @end direntry
+ 
+ This manual documents the GNU Transactional Memory Library.
+Index: b/src/libitm/Makefile.am
+===================================================================
+--- a/src/libitm/Makefile.am
++++ b/src/libitm/Makefile.am
+@@ -107,14 +107,17 @@ endif
+ 
+ all-local: $(STAMP_GENINSRC)
+ 
+-stamp-geninsrc: libitm.info
+-	cp -p $(top_builddir)/libitm.info $(srcdir)/libitm.info
++INFO_LIBITM_NAME = $(shell echo libitm|sed '$(program_transform_name)')
++stamp-geninsrc: $(INFO_LIBITM_NAME).info
++	cp -p $(top_builddir)/$(INFO_LIBITM_NAME).info $(srcdir)/libitm.info
+ 	@touch $@
+ 
+-libitm.info: $(STAMP_BUILD_INFO)
++libitm.info: $(INFO_LIBITM_NAME).info
++       cp $(INFO_LIBITM_NAME).info libitm.info
++$(INFO_LIBITM_NAME).info: $(STAMP_BUILD_INFO)
+ 
+ stamp-build-info: libitm.texi
+-	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libitm.info $(srcdir)/libitm.texi
++	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -D 'fnlibitm $(INFO_LIBITM_NAME)'-o $(INFO_LIBITM_NAME).info $(srcdir)/libitm.texi
+ 	@touch $@
+ 
+ 
+Index: b/src/libitm/Makefile.in
+===================================================================
+--- a/src/libitm/Makefile.in
++++ b/src/libitm/Makefile.in
+@@ -1103,14 +1103,17 @@ vpath % $(strip $(search_path))
+ 
+ all-local: $(STAMP_GENINSRC)
+ 
+-stamp-geninsrc: libitm.info
+-	cp -p $(top_builddir)/libitm.info $(srcdir)/libitm.info
++INFO_LIBITM_NAME = $(shell echo libitm|sed '$(program_transform_name)')
++stamp-geninsrc: $(INFO_LIBITM_NAME).info
++	cp -p $(top_builddir)/$(INFO_LIBITM_NAME).info $(srcdir)/libitm.info
+ 	@touch $@
+ 
+-libitm.info: $(STAMP_BUILD_INFO)
++libitm.info: $(INFO_LIBITM_NAME).info
++	cp $(INFO_LIBITM_NAME).info libitm.info
++$(INFO_LIBITM_NAME).info: $(STAMP_BUILD_INFO)
+ 
+ stamp-build-info: libitm.texi
+-	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libitm.info $(srcdir)/libitm.texi
++	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -D 'fnlibitm $(INFO_LIBITM_NAME)' -o $(INFO_LIBITM_NAME).info $(srcdir)/libitm.texi
+ 	@touch $@
+ 
+ # Tell versions [3.59,3.63) of GNU make to not export all variables.
+Index: b/src/gcc/go/Make-lang.in
+===================================================================
+--- a/src/gcc/go/Make-lang.in
++++ b/src/gcc/go/Make-lang.in
+@@ -86,10 +86,11 @@ GO_TEXI_FILES = \
+ 	$(gcc_docdir)/include/gcc-common.texi \
+ 	gcc-vers.texi
+ 
+-doc/gccgo.info: $(GO_TEXI_FILES)
++INFO_GCCGO_NAME = $(shell echo gccgo|sed '$(program_transform_name)')
++doc/$(INFO_GCCGO_NAME).info: $(GO_TEXI_FILES)
+ 	if test "x$(BUILD_INFO)" = xinfo; then \
+-	  rm -f doc/gccgo.info*; \
+-	  $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \
++	  rm -f doc/$(INFO_GCCGO_NAME).info*; \
++	  $(MAKEINFO) $(MAKEINFOFLAGS) $(MAKEINFODEFS) -I $(gcc_docdir) \
+ 		-I $(gcc_docdir)/include -o $@ $<; \
+ 	else true; fi
+ 
+@@ -115,7 +116,7 @@ gccgo.pod: go/gccgo.texi
+ go.all.cross: gccgo-cross$(exeext)
+ go.start.encap: gccgo$(exeext)
+ go.rest.encap:
+-go.info: doc/gccgo.info
++go.info: doc/$(INFO_GCCGO_NAME).info
+ go.dvi: doc/gccgo.dvi
+ go.pdf: doc/gccgo.pdf
+ go.html: $(build_htmldir)/go/index.html
+@@ -151,7 +152,7 @@ go.install-common: installdirs
+ 
+ go.install-plugin:
+ 
+-go.install-info: $(DESTDIR)$(infodir)/gccgo.info
++go.install-info: $(DESTDIR)$(infodir)/$(INFO_GCCGO_NAME).info
+ 
+ go.install-pdf: doc/gccgo.pdf
+ 	@$(NORMAL_INSTALL)
+@@ -191,7 +192,7 @@ go.uninstall:
+ 	rm -rf $(DESTDIR)$(bindir)/$(GCCGO_INSTALL_NAME)$(exeext)
+ 	rm -rf $(DESTDIR)$(man1dir)/$(GCCGO_INSTALL_NAME)$(man1ext)
+ 	rm -rf $(DESTDIR)$(bindir)/$(GCCGO_TARGET_INSTALL_NAME)$(exeext)
+-	rm -rf $(DESTDIR)$(infodir)/gccgo.info*
++	rm -rf $(DESTDIR)$(infodir)/$(INFO_GCCGO_NAME).info*
+ 
+ # Clean hooks.
+ 
+Index: b/src/gcc/go/gccgo.texi
+===================================================================
+--- a/src/gcc/go/gccgo.texi
++++ b/src/gcc/go/gccgo.texi
+@@ -50,7 +50,7 @@ man page gfdl(7).
+ @format
+ @dircategory Software development
+ @direntry
+-* Gccgo: (gccgo).           A GCC-based compiler for the Go language
++* @value{fngccgo}: (@value{fngccgo}).           A GCC-based compiler for the Go language
+ @end direntry
+ @end format
+ 
+@@ -123,7 +123,7 @@ and the Info entries for @file{gccgo} an
+ 
+ The @command{gccgo} command is a frontend to @command{gcc} and
+ supports many of the same options.  @xref{Option Summary, , Option
+-Summary, gcc, Using the GNU Compiler Collection (GCC)}.  This manual
++Summary, @value{fngcc}, Using the GNU Compiler Collection (GCC)}.  This manual
+ only documents the options specific to @command{gccgo}.
+ 
+ The @command{gccgo} command may be used to compile Go source code into
+Index: b/src/libquadmath/libquadmath.texi
+===================================================================
+--- a/src/libquadmath/libquadmath.texi
++++ b/src/libquadmath/libquadmath.texi
+@@ -25,7 +25,7 @@ copy and modify this GNU manual.
+ @ifinfo
+ @dircategory GNU Libraries
+ @direntry
+-* libquadmath: (libquadmath).                  GCC Quad-Precision Math Library
++* @value{fnlibquadmath}: (@value{fnlibquadmath}).                  GCC Quad-Precision Math Library
+ @end direntry
+ 
+ This manual documents the GCC Quad-Precision Math Library API.
+Index: b/src/libquadmath/Makefile.am
+===================================================================
+--- a/src/libquadmath/Makefile.am
++++ b/src/libquadmath/Makefile.am
+@@ -133,22 +133,24 @@ endif
+ 
+ all-local: $(STAMP_GENINSRC)
+ 
+-stamp-geninsrc: libquadmath.info
+-	cp -p $(top_builddir)/libquadmath.info $(srcdir)/libquadmath.info
++INFO_LIBQMATH_NAME = $(shell echo libquadmath|sed '$(program_transform_name)')
++
++stamp-geninsrc: $(INFO_LIBQMATH_NAME).info
++	cp -p $(top_builddir)/$(INFO_LIBQMATH_NAME).info $(srcdir)/libquadmath.info
+ 	@touch $@
+ 
+ stamp-build-info: libquadmath.texi $(libquadmath_TEXINFOS)
+-	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libquadmath.info $(srcdir)/libquadmath.texi
++	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o $(INFO_LIBQMATH_NAME).info $(srcdir)/libquadmath.texi
+ 	@touch $@
+ 
+-CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) libquadmath.info
+-MAINTAINERCLEANFILES = $(srcdir)/libquadmath.info
++CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) $(INFO_LIBQMATH_NAME).info
++MAINTAINERCLEANFILES = $(srcdir)/$(INFO_LIBQMATH_NAME).info
+ 
+ endif BUILD_LIBQUADMATH
+ 
+ # Unconditionally override this target, so that automake's definition
+ # does not wrongly interfere.
+-libquadmath.info: $(STAMP_BUILD_INFO)
++$(INFO_LIBQMATH_NAME).info: $(STAMP_BUILD_INFO)
+ 
+ 
+ # Automake Documentation:
+Index: b/src/libquadmath/Makefile.in
+===================================================================
+--- a/src/libquadmath/Makefile.in
++++ b/src/libquadmath/Makefile.in
+@@ -193,7 +193,8 @@ MULTIDIRS =
+ MULTISUBDIR = 
+ MULTIDO = true
+ MULTICLEAN = true
+-INFO_DEPS = libquadmath.info
++INFO_LIBQMATH_NAME = $(shell echo libquadmath|sed '$(program_transform_name)')
++INFO_DEPS = $(INFO_LIBQMATH_NAME).info
+ am__TEXINFO_TEX_DIR = $(srcdir)/../gcc/doc/include
+ DVIS = libquadmath.dvi
+ PDFS = libquadmath.pdf
+@@ -435,8 +436,8 @@ AUTOMAKE_OPTIONS = 1.8 foreign
+ 
+ # AM_CONDITIONAL on configure check ACX_CHECK_PROG_VER([MAKEINFO])
+ @BUILD_INFO_TRUE@@BUILD_LIBQUADMATH_TRUE@STAMP_BUILD_INFO = stamp-build-info
+-@BUILD_LIBQUADMATH_TRUE@CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) libquadmath.info
+-@BUILD_LIBQUADMATH_TRUE@MAINTAINERCLEANFILES = $(srcdir)/libquadmath.info
++@BUILD_LIBQUADMATH_TRUE@CLEANFILES = $(STAMP_GENINSRC) $(STAMP_BUILD_INFO) $(INFO_LIBQMATH_NAME).info
++@BUILD_LIBQUADMATH_TRUE@MAINTAINERCLEANFILES = $(srcdir)/$(INFO_LIBQMATH_NAME).info
+ 
+ # Automake Documentation:
+ # If your package has Texinfo files in many directories, you can use the
+@@ -1517,17 +1518,17 @@ uninstall-am: uninstall-dvi-am uninstall
+ 
+ @BUILD_LIBQUADMATH_TRUE@all-local: $(STAMP_GENINSRC)
+ 
+-@BUILD_LIBQUADMATH_TRUE@stamp-geninsrc: libquadmath.info
+-@BUILD_LIBQUADMATH_TRUE@	cp -p $(top_builddir)/libquadmath.info $(srcdir)/libquadmath.info
++@BUILD_LIBQUADMATH_TRUE@stamp-geninsrc: $(INFO_LIBQMATH_NAME).info
++@BUILD_LIBQUADMATH_TRUE@	cp -p $(top_builddir)/$(INFO_LIBQMATH_NAME).info $(srcdir)/$(INFO_LIBQMATH_NAME).info
+ @BUILD_LIBQUADMATH_TRUE@	@touch $@
+ 
+ @BUILD_LIBQUADMATH_TRUE@stamp-build-info: libquadmath.texi $(libquadmath_TEXINFOS)
+-@BUILD_LIBQUADMATH_TRUE@	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o libquadmath.info $(srcdir)/libquadmath.texi
++@BUILD_LIBQUADMATH_TRUE@	$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) -o $(INFO_LIBQMATH_NAME).info $(srcdir)/libquadmath.texi
+ @BUILD_LIBQUADMATH_TRUE@	@touch $@
+ 
+ # Unconditionally override this target, so that automake's definition
+ # does not wrongly interfere.
+-libquadmath.info: $(STAMP_BUILD_INFO)
++$(INFO_LIBQMATH_NAME).info: $(STAMP_BUILD_INFO)
+ 
+ libquadmath-vers.texi:
+ 	echo "@set BUGURL $(REPORT_BUGS_TEXI)" > $@
--- gcc-6-6.4.0.orig/debian/patches/sanitizer-Fix-a-crash-in-SizeClassAllocator32-with-a.diff
+++ gcc-6-6.4.0/debian/patches/sanitizer-Fix-a-crash-in-SizeClassAllocator32-with-a.diff
@@ -0,0 +1,22 @@
+Description: [sanitizer] Fix a crash in SizeClassAllocator32 with an out-of-range pointer
+ .
+ This happens on a 64-bit platform that uses SizeClassAllocator32 (e.g. ASan on AArch64). When querying a large invalid pointer, `__sanitizer_get_allocated_size(0xdeadbeefdeadbeef)`, an assertion will fail.  This patch changes PointerIsMine to return false if the pointer is outside of [kSpaceBeg, kSpaceBeg + kSpaceSize).
+ .
+ Differential Revision: http://reviews.llvm.org/D15008
+Author: Kuba Brecka <kuba.brecka@gmail.com>
+Origin: http://llvm.org/svn/llvm-project/compiler-rt/trunk@268243
+Bug-Ubuntu: https://bugs.launchpad.net/bugs/1709727
+Applied-Upstream: svn://gcc.gnu.org/svn/gcc/trunk@241977
+
+--- a/src/libsanitizer/sanitizer_common/sanitizer_allocator.h	2015-10-21 01:32:45.340398000 -0600
++++ b/src/libsanitizer/sanitizer_common/sanitizer_allocator.h	2017-08-09 11:58:12.564883000 -0600
+@@ -747,6 +747,9 @@
+   }
+ 
+   bool PointerIsMine(const void *p) {
++    uptr mem = reinterpret_cast<uptr>(p);
++    if (mem < kSpaceBeg || mem >= kSpaceBeg + kSpaceSize)
++      return false;
+     return GetSizeClass(p) != 0;
+   }
+ 
--- gcc-6-6.4.0.orig/debian/patches/skip-bootstrap-multilib.diff
+++ gcc-6-6.4.0/debian/patches/skip-bootstrap-multilib.diff
@@ -0,0 +1,49 @@
+# DP: Skip non-default multilib and libstdc++-v3 debug builds in bootstrap builds
+
+Index: b/src/config-ml.in
+===================================================================
+--- a/src/config-ml.in
++++ b/src/config-ml.in
+@@ -479,6 +479,17 @@ esac
+ # Tests like `if [ -n "$multidirs" ]' require it.
+ multidirs=`echo "$multidirs" | sed -e 's/^[ ][ ]*//' -e 's/[ ][ ]*$//' -e 's/[ ][ ]*/ /g'`
+ 
++# stage1 and stage2 builds of the non-default multilib configurations
++# are not needed; skip these to save some build time.
++if [ -f ../../stage_final ] && [ -f ../../stage_current ]; then
++    stage_final=`cat ../../stage_final`
++    stage_current=`cat ../../stage_current`
++    if [ "$stage_current" != "$stage_final" ]; then
++	echo "Skip `basename $ml_realsrcdir` non-default multilibs for bootstrap stage $stage_current"
++	multidirs=
++    fi
++fi
++
+ # Add code to library's top level makefile to handle building the multilib
+ # subdirs.
+ 
+Index: b/src/libstdc++-v3/acinclude.m4
+===================================================================
+--- a/src/libstdc++-v3/acinclude.m4
++++ b/src/libstdc++-v3/acinclude.m4
+@@ -2902,7 +2902,20 @@ dnl
+ AC_DEFUN([GLIBCXX_ENABLE_DEBUG], [
+   AC_MSG_CHECKING([for additional debug build])
+   GLIBCXX_ENABLE(libstdcxx-debug,$1,,[build extra debug library])
++  if test x$enable_libstdcxx_debug = xyes; then
++    if test -f $toplevel_builddir/../stage_final && test -f $toplevel_builddir/../stage_current; then
++      stage_final=`cat $toplevel_builddir/../stage_final`
++      stage_current=`cat $toplevel_builddir/../stage_current`
++      if test x$stage_current != x$stage_final ; then
++	skip_debug_build=yes
++	enable_libstdcxx_debug=no
++      fi
++    fi
++  fi
+   AC_MSG_RESULT($enable_libstdcxx_debug)
++  if test x$skip_debug_build = xyes ; then
++    AC_MSG_NOTICE([Skip libstdc++-v3 debug build for bootstrap stage $stage_current])
++  fi
+   GLIBCXX_CONDITIONAL(GLIBCXX_BUILD_DEBUG, test $enable_libstdcxx_debug = yes)
+ ])
+ 
--- gcc-6-6.4.0.orig/debian/patches/sparc64-biarch-long-double-128.diff
+++ gcc-6-6.4.0/debian/patches/sparc64-biarch-long-double-128.diff
@@ -0,0 +1,35 @@
+# DP: Fix --with-long-double-128 for sparc32 when defaulting to 64-bit.
+
+On sparc, the --with-long-double-128 option doesn't change anything for
+a 64-bit compiler, as it always default to 128-bit long doubles. For
+a 32/64-bit compiler defaulting to 32-bit this correctly control the
+size of long double of the 32-bit compiler, however for a 32/64-bit
+compiler defaulting to 64-bit, the built-in specs force the 
+-mlong-double-64 option. This makes the option useless in this case.
+
+The patch below fixes that by removing the -mlong-double-64 from the
+built-in spec, using the default instead.
+
+Changelog gcc/
+
+2013-12-04  Aurelien Jarno  <aurelien@aurel32.net>
+
+	* config/sparc/linux64.h (CC1_SPEC): When defaulting to 64-bit,
+	don't force -mlong-double-64 when -m32 or -mv8plus is given.
+
+Index: b/src/gcc/config/sparc/linux64.h
+===================================================================
+--- a/src/gcc/config/sparc/linux64.h
++++ b/src/gcc/config/sparc/linux64.h
+@@ -154,9 +154,9 @@ extern const char *host_detect_local_cpu
+ #else
+ #define CC1_SPEC "%{profile:-p} \
+ %{m32:%{m64:%emay not use both -m32 and -m64}} \
+-%{m32:-mptr32 -mno-stack-bias %{!mlong-double-128:-mlong-double-64} \
++%{m32:-mptr32 -mno-stack-bias \
+   %{!mcpu*:-mcpu=cypress}} \
+-%{mv8plus:-mptr32 -mno-stack-bias %{!mlong-double-128:-mlong-double-64} \
++%{mv8plus:-mptr32 -mno-stack-bias \
+   %{!mcpu*:-mcpu=v9}} \
+ %{!m32:%{!mcpu*:-mcpu=ultrasparc}} \
+ %{!mno-vis:%{!m32:%{!mcpu=v9:-mvis}}} \
--- gcc-6-6.4.0.orig/debian/patches/src_gcc_config_i386_gnu.h.diff
+++ gcc-6-6.4.0/debian/patches/src_gcc_config_i386_gnu.h.diff
@@ -0,0 +1,25 @@
+Index: gcc-6-6.2.1-4.1/src/gcc/config/i386/gnu.h
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/gcc/config/i386/gnu.h
++++ gcc-6-6.2.1-4.1/src/gcc/config/i386/gnu.h
+@@ -37,11 +37,14 @@ along with GCC.  If not, see <http://www
+ 
+ #ifdef TARGET_LIBC_PROVIDES_SSP
+ 
+-/* Not supported yet.  */
+-# undef TARGET_THREAD_SSP_OFFSET
+-
+-/* Not supported yet.  */
+-# undef TARGET_CAN_SPLIT_STACK
+-# undef TARGET_THREAD_SPLIT_STACK_OFFSET
++/* i386 glibc provides __stack_chk_guard in %gs:0x14.  */
++#define TARGET_THREAD_SSP_OFFSET        0x14
+ 
++/* We only build the -fsplit-stack support in libgcc if the
++   assembler has full support for the CFI directives.  */
++#if HAVE_GAS_CFI_PERSONALITY_DIRECTIVE
++#define TARGET_CAN_SPLIT_STACK
++#endif
++/* We steal the last transactional memory word.  */
++#define TARGET_THREAD_SPLIT_STACK_OFFSET 0x30
+ #endif
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_Makefile.am.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_Makefile.am.diff
@@ -0,0 +1,281 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/Makefile.am
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/Makefile.am
++++ gcc-6-6.2.1-4.1/src/libgo/Makefile.am
+@@ -419,6 +419,9 @@ else
+ if LIBGO_IS_NETBSD
+ runtime_getncpu_file = runtime/getncpu-bsd.c
+ else
++if LIBGO_IS_GNU
++runtime_getncpu_file = runtime/getncpu-gnu.c
++else
+ runtime_getncpu_file = runtime/getncpu-none.c
+ endif
+ endif
+@@ -426,6 +429,7 @@ endif
+ endif
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_LINUX
+ runtime_netpoll_files = runtime/netpoll_epoll.c
+@@ -433,9 +437,13 @@ else
+ if LIBGO_IS_SOLARIS
+ runtime_netpoll_files = runtime/netpoll_select.c
+ else
++if LIBGO_IS_GNU
++runtime_netpoll_files = runtime/netpoll_select.c
++else
+ runtime_netpoll_files = runtime/netpoll_kqueue.c
+ endif
+ endif
++endif
+ 
+ runtime_files = \
+ 	runtime/go-append.c \
+@@ -744,6 +752,14 @@ go_net_sockoptip_file = go/net/sockoptip
+ go_net_cgo_sock_file = go/net/cgo_sockold.go
+ go_net_cgo_res_file = go/net/cgo_resnew.go
+ else
++if LIBGO_IS_GNU
++go_net_cgo_file = go/net/cgo_linux.go
++go_net_sock_file = go/net/sock_gnu.go
++go_net_sockopt_file = go/net/sockopt_gnu.go
++go_net_sockoptip_file = go/net/sockoptip_gnu.go go/net/sockoptip_posix.go
++go_net_cgo_sock_file = go/net/cgo_socknew.go
++go_net_cgo_res_file = go/net/cgo_resnew.go
++else
+ go_net_cgo_file = go/net/cgo_bsd.go
+ go_net_sock_file = go/net/sock_bsd.go
+ go_net_sockopt_file = go/net/sockopt_bsd.go
+@@ -755,6 +771,7 @@ endif
+ endif
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_LINUX
+ go_net_sendfile_file = go/net/sendfile_linux.go
+@@ -768,11 +785,15 @@ else
+ if LIBGO_IS_SOLARIS
+ go_net_sendfile_file = go/net/sendfile_solaris.go
+ else
++if LIBGO_IS_GNU
++go_net_sendfile_file = go/net/sendfile_gnu.go
++else
+ go_net_sendfile_file = go/net/sendfile_stub.go
+ endif
+ endif
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_LINUX
+ go_net_interface_file = go/net/interface_linux.go
+@@ -794,9 +815,13 @@ else
+ if LIBGO_IS_FREEBSD
+ go_net_cloexec_file = go/net/sock_cloexec.go go/net/hook_cloexec.go
+ else
++if LIBGO_IS_GNU
++go_net_cloexec_file = go/net/sock_cloexec.go go/net/hook_cloexec.go
++else
+ go_net_cloexec_file = go/net/sys_cloexec.go
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_OPENBSD
+ go_net_tcpsockopt_file = go/net/tcpsockopt_openbsd.go
+@@ -889,9 +914,13 @@ else
+ if LIBGO_IS_LINUX
+ go_os_dir_file = go/os/dir_largefile.go
+ else
++if LIBGO_IS_GNU
++go_os_dir_file = go/os/dir_largefile.go
++else
+ go_os_dir_file = go/os/dir_regfile.go
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_DARWIN
+ go_os_getwd_file = go/os/getwd_darwin.go
+@@ -911,11 +940,15 @@ else
+ if LIBGO_IS_RTEMS
+ go_os_sys_file = go/os/sys_uname.go
+ else
++if LIBGO_IS_GNU
++go_os_sys_file = go/os/sys_uname.go
++else
+ go_os_sys_file = go/os/sys_bsd.go
+ endif
+ endif
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_FREEBSD
+ go_os_cloexec_file = go/os/sys_freebsd.go
+@@ -937,6 +970,9 @@ else
+ if LIBGO_IS_LINUX
+ go_os_stat_file = go/os/stat_atim.go
+ else
++if LIBGO_IS_GNU
++go_os_stat_file = go/os/stat_atim.go
++else
+ if LIBGO_IS_OPENBSD
+ go_os_stat_file = go/os/stat_atim.go
+ else
+@@ -960,12 +996,17 @@ endif
+ endif
+ endif
+ endif
++endif
+ 
+ if LIBGO_IS_LINUX
+ go_os_pipe_file = go/os/pipe_linux.go
+ else
++if LIBGO_IS_GNU
++go_os_pipe_file = go/os/pipe_linux.go
++else
+ go_os_pipe_file = go/os/pipe_bsd.go
+ endif
++endif
+ 
+ if LIBGO_IS_DARWIN
+ go_os_sticky_file = go/os/sticky_bsd.go
+@@ -1158,6 +1199,9 @@ go_unicode_files = \
+ if LIBGO_IS_LINUX
+ archive_tar_atim_file = go/archive/tar/stat_atim.go
+ endif
++if LIBGO_IS_GNU
++archive_tar_atim_file = go/archive/tar/stat_atim.go
++endif
+ if LIBGO_IS_OPENBSD
+ archive_tar_atim_file = go/archive/tar/stat_atim.go
+ endif
+@@ -1322,6 +1366,9 @@ else
+ if LIBGO_IS_DARWIN
+ go_crypto_x509_root_file = go/crypto/x509/root_darwin.go
+ else
++if LIBGO_IS_GNU
++go_crypto_x509_root_file = go/crypto/x509/root_linux.go
++else
+ go_crypto_x509_root_file =
+ endif
+ endif
+@@ -1330,6 +1377,7 @@ endif
+ endif
+ endif
+ endif
++endif
+ 
+ go_crypto_x509_files = \
+ 	go/crypto/x509/cert_pool.go \
+@@ -1857,10 +1905,15 @@ if LIBGO_IS_LINUX
+ syscall_exec_file = go/syscall/exec_unix.go
+ syscall_exec_os_file = go/syscall/exec_linux.go
+ else
++if LIBGO_IS_GNU
++syscall_exec_file = go/syscall/exec_unix.go
++syscall_exec_os_file = go/syscall/exec_bsd.go
++else
+ syscall_exec_file = go/syscall/exec_unix.go
+ syscall_exec_os_file = go/syscall/exec_bsd.go
+ endif
+ endif
++endif
+ 
+ # Define Wait4.
+ if LIBGO_IS_RTEMS
+@@ -1894,6 +1947,9 @@ else
+ if LIBGO_IS_RTEMS
+ syscall_errstr_file = go/syscall/errstr_linux.go
+ else
++if LIBGO_IS_GNU
++syscall_errstr_file = go/syscall/errstr_linux.go
++else
+ if HAVE_STRERROR_R
+ syscall_errstr_file = go/syscall/errstr.go
+ else
+@@ -1901,12 +1957,16 @@ syscall_errstr_file = go/syscall/errstr_
+ endif
+ endif
+ endif
++endif
+ 
+ # Declare libc functions that vary for largefile systems.
+ if LIBGO_IS_LINUX
+ # Always use lseek64 on GNU/Linux.
+ syscall_size_file = go/syscall/libcall_posix_largefile.go
+ else # !LIBGO_IS_LINUX
++if LIBGO_IS_GNU
++syscall_size_file = go/syscall/libcall_posix_largefile.go
++else # !LIBGO_IS_LINUX && !LIBGO_IS_GNU
+ if LIBGO_IS_SOLARIS
+ if LIBGO_IS_386
+ # Use lseek64 on 32-bit Solaris/x86.
+@@ -1924,6 +1984,7 @@ else # !LIBGO_IS_LINUX && !LIBGO_IS_SOLA
+ # Use lseek by default.
+ syscall_size_file = go/syscall/libcall_posix_regfile.go
+ endif # !LIBGO_IS_SOLARIS
++endif # !LIBGO_IS_LINUX && !LIBGO_IS_GNU
+ endif # !LIBGO_IS_LINUX
+ 
+ # Define socket sizes and types.
+@@ -1946,10 +2007,14 @@ else
+ if LIBGO_IS_IRIX
+ syscall_socket_file = go/syscall/socket_irix.go
+ else
++if LIBGO_IS_GNU
++syscall_socket_file = go/syscall/socket_gnu.go
++else
+ syscall_socket_file = go/syscall/socket_bsd.go
+ endif
+ endif
+ endif
++endif
+ 
+ # Define socket functions.
+ if LIBGO_IS_SOLARIS
+@@ -2028,11 +2093,20 @@ else
+ syscall_os_file = go/syscall/libcall_bsd.go
+ endif
+ 
++# GNU/Hurd specific library calls support.
++if LIBGO_IS_GNU
++syscall_libcall_file = go/syscall/libcall_posix-1.go
++syscall_os_test_file = go/syscall/syscall_gnu_test.go
++else
++syscall_libcall_file = go/syscall/libcall_posix.go
++syscall_os_test_file = go/syscall/syscall_unix_test.go
++endif
++
+ go_base_syscall_files = \
+ 	go/syscall/env_unix.go \
+ 	go/syscall/syscall_errno.go \
+ 	go/syscall/libcall_support.go \
+-	go/syscall/libcall_posix.go \
++	$(syscall_libcall_file) \
+ 	go/syscall/msan0.go \
+ 	go/syscall/socket.go \
+ 	go/syscall/sockcmsg_unix.go \
+@@ -2078,7 +2152,7 @@ go_syscall_test_files = \
+ 	go/syscall/export_unix_test.go \
+ 	go/syscall/mmap_unix_test.go \
+ 	go/syscall/syscall_test.go \
+-	go/syscall/syscall_unix_test.go
++	$(syscall_os_test_file)
+ 
+ libcalls.go: s-libcalls; @true
+ s-libcalls: libcalls-list go/syscall/mksyscall.awk $(go_base_syscall_files)
+@@ -4431,7 +4505,7 @@ mostlyclean-local:
+ 	find . -name '*-testsum' -print | xargs rm -f
+ 	find . -name '*-testlog' -print | xargs rm -f
+ 
+-CLEANFILES = *.go *.gox goc2c *.c s-version libgo.sum libgo.log
++CLEANFILES = *.go *.gox goc2c *.c s-* libgo.sum libgo.log
+ 
+ clean-local:
+ 	find . -name '*.la' -print | xargs $(LIBTOOL) --mode=clean rm -f
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_Makefile.in.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_Makefile.in.diff
@@ -0,0 +1,475 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/Makefile.in
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/Makefile.in
++++ gcc-6-6.2.1-4.1/src/libgo/Makefile.in
+@@ -230,11 +230,13 @@ libgo_llgo_la_DEPENDENCIES = $(am__DEPEN
+ @LIBGO_IS_LINUX_TRUE@am__objects_4 = lock_futex.lo thread-linux.lo
+ @HAVE_SYS_MMAN_H_FALSE@am__objects_5 = mem_posix_memalign.lo
+ @HAVE_SYS_MMAN_H_TRUE@am__objects_5 = mem.lo
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_6 = netpoll_kqueue.lo
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_6 = netpoll_kqueue.lo
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_6 = netpoll_select.lo
+ @LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@am__objects_6 = netpoll_select.lo
+ @LIBGO_IS_LINUX_TRUE@am__objects_6 = netpoll_epoll.lo
+ @LIBGO_IS_RTEMS_TRUE@am__objects_7 = rtems-task-variable-add.lo
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_8 = getncpu-none.lo
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_8 = getncpu-none.lo
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_8 = getncpu-gnu.lo
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@am__objects_8 = getncpu-bsd.lo
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@am__objects_8 = getncpu-bsd.lo
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@am__objects_8 = getncpu-solaris.lo
+@@ -300,10 +302,10 @@ LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLF
+ SOURCES = $(libgobegin_llgo_a_SOURCES) $(libgobegin_a_SOURCES) \
+ 	$(libgolibbegin_a_SOURCES) $(libnetgo_a_SOURCES) \
+ 	$(libgo_llgo_la_SOURCES) $(libgo_la_SOURCES)
+-MULTISRCTOP = 
+-MULTIBUILDTOP = 
+-MULTIDIRS = 
+-MULTISUBDIR = 
++MULTISRCTOP =
++MULTIBUILDTOP =
++MULTIDIRS =
++MULTISUBDIR =
+ MULTIDO = true
+ MULTICLEAN = true
+ RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
+@@ -523,7 +525,7 @@ AM_CFLAGS = -fexceptions -fnon-call-exce
+ @USING_SPLIT_STACK_TRUE@AM_LDFLAGS = -XCClinker $(SPLIT_STACK)
+ 
+ # Multilib support.
+-MAKEOVERRIDES = 
++MAKEOVERRIDES =
+ 
+ # Work around what appears to be a GNU make  handling MAKEFLAGS
+ # values defined in terms of make variables, as is the case for CC and
+@@ -818,18 +820,20 @@ toolexeclibgounicode_DATA = \
+ 
+ @HAVE_SYS_MMAN_H_FALSE@runtime_mem_file = runtime/mem_posix_memalign.c
+ @HAVE_SYS_MMAN_H_TRUE@runtime_mem_file = runtime/mem.c
+-@LIBGO_IS_RTEMS_FALSE@rtems_task_variable_add_file = 
++@LIBGO_IS_RTEMS_FALSE@rtems_task_variable_add_file =
+ @LIBGO_IS_RTEMS_TRUE@rtems_task_variable_add_file = runtime/rtems-task-variable-add.c
+ @LIBGO_IS_LINUX_FALSE@runtime_lock_files = runtime/lock_sema.c runtime/thread-sema.c
+ @LIBGO_IS_LINUX_TRUE@runtime_lock_files = runtime/lock_futex.c runtime/thread-linux.c
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_getncpu_file = runtime/getncpu-none.c
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_getncpu_file = runtime/getncpu-none.c
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_getncpu_file = runtime/getncpu-gnu.c
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@runtime_getncpu_file = runtime/getncpu-bsd.c
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_getncpu_file = runtime/getncpu-bsd.c
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@runtime_getncpu_file = runtime/getncpu-solaris.c
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@runtime_getncpu_file = runtime/getncpu-irix.c
+ @LIBGO_IS_DARWIN_TRUE@@LIBGO_IS_LINUX_FALSE@runtime_getncpu_file = runtime/getncpu-bsd.c
+ @LIBGO_IS_LINUX_TRUE@runtime_getncpu_file = runtime/getncpu-linux.c
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_netpoll_files = runtime/netpoll_kqueue.c
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_netpoll_files = runtime/netpoll_kqueue.c
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@runtime_netpoll_files = runtime/netpoll_select.c
+ @LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@runtime_netpoll_files = runtime/netpoll_select.c
+ @LIBGO_IS_LINUX_TRUE@runtime_netpoll_files = runtime/netpoll_epoll.c
+ runtime_files = \
+@@ -1036,7 +1040,7 @@ go_math_files = \
+ 	go/math/tanh.go \
+ 	go/math/unsafe.go
+ 
+-@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@go_mime_type_file = 
++@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@go_mime_type_file =
+ @LIBGO_IS_DRAGONFLY_TRUE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@go_mime_type_file = go/mime/type_dragonfly.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_OPENBSD_FALSE@go_mime_type_file = go/mime/type_freebsd.go
+ @LIBGO_IS_OPENBSD_TRUE@go_mime_type_file = go/mime/type_openbsd.go
+@@ -1048,43 +1052,50 @@ go_mime_files = \
+ 	go/mime/type_unix.go \
+ 	$(go_mime_type_file)
+ 
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_file = go/net/cgo_bsd.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_file = go/net/cgo_bsd.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_file = go/net/cgo_linux.go
+ @LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_file = go/net/cgo_netbsd.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_file = go/net/cgo_bsd.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_cgo_file = go/net/cgo_solaris.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_cgo_file = go/net/cgo_linux.go
+ @LIBGO_IS_LINUX_TRUE@go_net_cgo_file = go/net/cgo_linux.go
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sock_file = go/net/sock_bsd.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sock_file = go/net/sock_bsd.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sock_file = go/net/sock_gnu.go
+ @LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_net_sock_file = go/net/sock_bsd.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sock_file = go/net/sock_bsd.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_sock_file = go/net/sock_stub.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_sock_file = go/net/sock_linux.go
+ @LIBGO_IS_LINUX_TRUE@go_net_sock_file = go/net/sock_linux.go
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockopt_file = go/net/sockopt_bsd.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockopt_file = go/net/sockopt_bsd.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockopt_file = go/net/sockopt_gnu.go
+ @LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockopt_file = go/net/sockopt_bsd.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockopt_file = go/net/sockopt_bsd.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_sockopt_file = go/net/sockopt_solaris.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_sockopt_file = go/net/sockopt_linux.go
+ @LIBGO_IS_LINUX_TRUE@go_net_sockopt_file = go/net/sockopt_linux.go
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockoptip_file = go/net/sockoptip_bsd.go go/net/sockoptip_posix.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockoptip_file = go/net/sockoptip_bsd.go go/net/sockoptip_posix.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockoptip_file = go/net/sockoptip_gnu.go go/net/sockoptip_posix.go
+ @LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockoptip_file = go/net/sockoptip_bsd.go go/net/sockoptip_posix.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sockoptip_file = go/net/sockoptip_bsd.go go/net/sockoptip_posix.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_sockoptip_file = go/net/sockoptip_stub.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_sockoptip_file = go/net/sockoptip_linux.go go/net/sockoptip_posix.go
+ @LIBGO_IS_LINUX_TRUE@go_net_sockoptip_file = go/net/sockoptip_linux.go go/net/sockoptip_posix.go
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_sock_file = go/net/cgo_sockold.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_sock_file = go/net/cgo_sockold.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_sock_file = go/net/cgo_socknew.go
+ @LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_sock_file = go/net/cgo_sockold.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_sock_file = go/net/cgo_sockold.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_cgo_sock_file = go/net/cgo_socknew.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_cgo_sock_file = go/net/cgo_socknew.go
+ @LIBGO_IS_LINUX_TRUE@go_net_cgo_sock_file = go/net/cgo_socknew.go
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_res_file = go/net/cgo_resold.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_res_file = go/net/cgo_resold.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_res_file = go/net/cgo_resnew.go
+ @LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_res_file = go/net/cgo_resnew.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_cgo_res_file = go/net/cgo_resold.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_cgo_res_file = go/net/cgo_resnew.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_cgo_res_file = go/net/cgo_resnew.go
+ @LIBGO_IS_LINUX_TRUE@go_net_cgo_res_file = go/net/cgo_resnew.go
+-@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sendfile_file = go/net/sendfile_stub.go
++@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sendfile_file = go/net/sendfile_stub.go
++@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_sendfile_file = go/net/sendfile_gnu.go
+ @LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_net_sendfile_file = go/net/sendfile_solaris.go
+ @LIBGO_IS_DRAGONFLY_TRUE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@go_net_sendfile_file = go/net/sendfile_dragonfly.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_sendfile_file = go/net/sendfile_freebsd.go
+@@ -1093,7 +1104,8 @@ go_mime_files = \
+ @LIBGO_IS_DRAGONFLY_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@go_net_interface_file = go/net/interface_dragonfly.go
+ @LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@go_net_interface_file = go/net/interface_netbsd.go
+ @LIBGO_IS_LINUX_TRUE@go_net_interface_file = go/net/interface_linux.go
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@go_net_cloexec_file = go/net/sys_cloexec.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@go_net_cloexec_file = go/net/sys_cloexec.go
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_cloexec_file = go/net/sock_cloexec.go go/net/hook_cloexec.go
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_cloexec_file = go/net/sock_cloexec.go go/net/hook_cloexec.go
+ @LIBGO_IS_LINUX_TRUE@go_net_cloexec_file = go/net/sock_cloexec.go go/net/hook_cloexec.go
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_net_tcpsockopt_file = go/net/tcpsockopt_unix.go
+@@ -1163,11 +1175,13 @@ go_netgo_files = \
+ @LIBGO_IS_386_FALSE@@LIBGO_IS_SOLARIS_TRUE@@LIBGO_IS_SPARC_FALSE@go_os_dir_file = go/os/dir_regfile.go
+ @LIBGO_IS_386_FALSE@@LIBGO_IS_SOLARIS_TRUE@@LIBGO_IS_SPARC_TRUE@go_os_dir_file = go/os/dir_largefile.go
+ @LIBGO_IS_386_TRUE@@LIBGO_IS_SOLARIS_TRUE@go_os_dir_file = go/os/dir_largefile.go
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_dir_file = go/os/dir_regfile.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_dir_file = go/os/dir_regfile.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_dir_file = go/os/dir_largefile.go
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_os_dir_file = go/os/dir_largefile.go
+-@LIBGO_IS_DARWIN_FALSE@go_os_getwd_file = 
++@LIBGO_IS_DARWIN_FALSE@go_os_getwd_file =
+ @LIBGO_IS_DARWIN_TRUE@go_os_getwd_file = go/os/getwd_darwin.go
+-@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_sys_file = go/os/sys_bsd.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_sys_file = go/os/sys_bsd.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_sys_file = go/os/sys_uname.go
+ @LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_os_sys_file = go/os/sys_uname.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_sys_file = go/os/sys_uname.go
+ @LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_os_sys_file = go/os/sys_uname.go
+@@ -1177,14 +1191,16 @@ go_netgo_files = \
+ @LIBGO_IS_FREEBSD_TRUE@go_os_cloexec_file = go/os/sys_freebsd.go
+ @HAVE_STAT_TIMESPEC_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_os_stat_file = go/os/stat_solaris.go
+ @HAVE_STAT_TIMESPEC_TRUE@@LIBGO_IS_SOLARIS_TRUE@go_os_stat_file = go/os/stat_atim.go
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat.go
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_TRUE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_dragonfly.go
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atimespec.go
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atimespec.go
+-@LIBGO_IS_DARWIN_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atimespec.go
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_OPENBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atim.go
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat.go
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_TRUE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_dragonfly.go
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atimespec.go
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atimespec.go
++@LIBGO_IS_DARWIN_TRUE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atimespec.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_OPENBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atim.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atim.go
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_os_stat_file = go/os/stat_atim.go
+-@LIBGO_IS_LINUX_FALSE@go_os_pipe_file = go/os/pipe_bsd.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@go_os_pipe_file = go/os/pipe_bsd.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@go_os_pipe_file = go/os/pipe_linux.go
+ @LIBGO_IS_LINUX_TRUE@go_os_pipe_file = go/os/pipe_linux.go
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_os_sticky_file = go/os/sticky_notbsd.go
+ @LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_TRUE@go_os_sticky_file = go/os/sticky_bsd.go
+@@ -1328,6 +1344,7 @@ go_unicode_files = \
+ 
+ @LIBGO_IS_DARWIN_TRUE@archive_tar_atim_file = go/archive/tar/stat_atimespec.go
+ @LIBGO_IS_FREEBSD_TRUE@archive_tar_atim_file = go/archive/tar/stat_atimespec.go
++@LIBGO_IS_GNU_TRUE@archive_tar_atim_file = go/archive/tar/stat_atim.go
+ @LIBGO_IS_LINUX_TRUE@archive_tar_atim_file = go/archive/tar/stat_atim.go
+ @LIBGO_IS_NETBSD_TRUE@archive_tar_atim_file = go/archive/tar/stat_atimespec.go
+ @LIBGO_IS_OPENBSD_TRUE@archive_tar_atim_file = go/archive/tar/stat_atim.go
+@@ -1421,7 +1438,7 @@ go_crypto_md5_files = \
+ 	go/crypto/md5/md5block.go \
+ 	go/crypto/md5/md5block_generic.go
+ 
+-@LIBGO_IS_LINUX_FALSE@crypto_rand_file = 
++@LIBGO_IS_LINUX_FALSE@crypto_rand_file =
+ @LIBGO_IS_LINUX_TRUE@crypto_rand_file = go/crypto/rand/rand_linux.go
+ go_crypto_rand_files = \
+ 	go/crypto/rand/eagain.go \
+@@ -1468,7 +1485,8 @@ go_crypto_tls_files = \
+ 	go/crypto/tls/ticket.go \
+ 	go/crypto/tls/tls.go
+ 
+-@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_crypto_x509_root_file = 
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_crypto_x509_root_file =
++@LIBGO_IS_DARWIN_FALSE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_crypto_x509_root_file = go/crypto/x509/root_linux.go
+ @LIBGO_IS_DARWIN_TRUE@@LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_FALSE@@LIBGO_IS_SOLARIS_FALSE@go_crypto_x509_root_file = go/crypto/x509/root_darwin.go
+ @LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_FALSE@@LIBGO_IS_OPENBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_crypto_x509_root_file = go/crypto/x509/root_bsd.go
+ @LIBGO_IS_DRAGONFLY_FALSE@@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_NETBSD_TRUE@@LIBGO_IS_SOLARIS_FALSE@go_crypto_x509_root_file = go/crypto/x509/root_bsd.go
+@@ -1772,7 +1790,7 @@ go_internal_singleflight_files = \
+ @LIBGO_IS_386_FALSE@@LIBGO_IS_ARM_TRUE@@LIBGO_IS_LINUX_TRUE@@LIBGO_IS_X86_64_FALSE@internal_syscall_unix_getrandom_files = go/internal/syscall/unix/getrandom_linux.go go/internal/syscall/unix/getrandom_linux_arm.go
+ @LIBGO_IS_386_FALSE@@LIBGO_IS_LINUX_TRUE@@LIBGO_IS_X86_64_TRUE@internal_syscall_unix_getrandom_files = go/internal/syscall/unix/getrandom_linux.go go/internal/syscall/unix/getrandom_linux_amd64.go
+ @LIBGO_IS_386_TRUE@@LIBGO_IS_LINUX_TRUE@internal_syscall_unix_getrandom_files = go/internal/syscall/unix/getrandom_linux.go go/internal/syscall/unix/getrandom_linux_386.go
+-@LIBGO_IS_LINUX_FALSE@internal_syscall_unix_getrandom_files = 
++@LIBGO_IS_LINUX_FALSE@internal_syscall_unix_getrandom_files =
+ go_internal_syscall_unix_files = \
+ 	go/internal/syscall/unix/dummy.go \
+ 	$(internal_syscall_unix_getrandom_files)
+@@ -1904,7 +1922,7 @@ go_net_http_internal_files = \
+ 	go/net/http/internal/chunked.go \
+ 	go/net/http/internal/testcert.go
+ 
+-@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@go_net_internal_socktest_sys = 
++@LIBGO_IS_FREEBSD_FALSE@@LIBGO_IS_LINUX_FALSE@go_net_internal_socktest_sys =
+ @LIBGO_IS_FREEBSD_TRUE@@LIBGO_IS_LINUX_FALSE@go_net_internal_socktest_sys = go/net/internal/socktest/sys_cloexec.go
+ @LIBGO_IS_LINUX_TRUE@go_net_internal_socktest_sys = go/net/internal/socktest/sys_cloexec.go
+ go_net_internal_socktest_files = \
+@@ -2012,52 +2030,57 @@ go_unicode_utf8_files = \
+ 
+ # Define Syscall and Syscall6.
+ @LIBGO_IS_RTEMS_TRUE@syscall_syscall_file = go/syscall/syscall_stubs.go
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_file = go/syscall/exec_unix.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_file = go/syscall/exec_unix.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_file = go/syscall/exec_unix.go
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_file = go/syscall/exec_unix.go
+ 
+ # Define ForkExec and Exec.
+ @LIBGO_IS_RTEMS_TRUE@syscall_exec_file = go/syscall/exec_stubs.go
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_os_file = go/syscall/exec_bsd.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_os_file = go/syscall/exec_bsd.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_os_file = go/syscall/exec_bsd.go
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_RTEMS_FALSE@syscall_exec_os_file = go/syscall/exec_linux.go
+-@LIBGO_IS_RTEMS_TRUE@syscall_exec_os_file = 
++@LIBGO_IS_RTEMS_TRUE@syscall_exec_os_file =
+ @HAVE_WAIT4_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_wait_file = go/syscall/libcall_waitpid.go
+ @HAVE_WAIT4_TRUE@@LIBGO_IS_RTEMS_FALSE@syscall_wait_file = go/syscall/libcall_wait4.go
+ 
+ # Define Wait4.
+-@LIBGO_IS_RTEMS_TRUE@syscall_wait_file = 
++@LIBGO_IS_RTEMS_TRUE@syscall_wait_file =
+ @LIBGO_IS_RTEMS_FALSE@syscall_wait_c_file = go/syscall/wait.c
+ 
+ # Support for pulling apart wait status.
+-@LIBGO_IS_RTEMS_TRUE@syscall_wait_c_file = 
++@LIBGO_IS_RTEMS_TRUE@syscall_wait_c_file =
+ @LIBGO_IS_RTEMS_FALSE@syscall_sleep_file = go/syscall/sleep_select.go
+ 
+ # Define Sleep.
+ @LIBGO_IS_RTEMS_TRUE@syscall_sleep_file = go/syscall/sleep_rtems.go
+-@HAVE_STRERROR_R_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_errstr_file = go/syscall/errstr_nor.go
+-@HAVE_STRERROR_R_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_errstr_file = go/syscall/errstr.go
++@HAVE_STRERROR_R_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_errstr_file = go/syscall/errstr_nor.go
++@HAVE_STRERROR_R_TRUE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_errstr_file = go/syscall/errstr.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_FALSE@syscall_errstr_file = go/syscall/errstr_linux.go
+ @LIBGO_IS_LINUX_FALSE@@LIBGO_IS_RTEMS_TRUE@syscall_errstr_file = go/syscall/errstr_linux.go
+ 
+ # Define Errstr.
+ @LIBGO_IS_LINUX_TRUE@syscall_errstr_file = go/syscall/errstr_linux.go
+ # Use lseek on 64-bit Solaris.
+-@LIBGO_IS_386_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@@LIBGO_IS_SPARC_FALSE@syscall_size_file = go/syscall/libcall_posix_regfile.go
++@LIBGO_IS_386_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@@LIBGO_IS_SPARC_FALSE@syscall_size_file = go/syscall/libcall_posix_regfile.go
+ # Use lseek64 on 32-bit Solaris/SPARC.
+-@LIBGO_IS_386_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@@LIBGO_IS_SPARC_TRUE@syscall_size_file = go/syscall/libcall_posix_largefile.go
++@LIBGO_IS_386_FALSE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@@LIBGO_IS_SPARC_TRUE@syscall_size_file = go/syscall/libcall_posix_largefile.go
+ # Use lseek64 on 32-bit Solaris/x86.
+-@LIBGO_IS_386_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@syscall_size_file = go/syscall/libcall_posix_largefile.go
++@LIBGO_IS_386_TRUE@@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@syscall_size_file = go/syscall/libcall_posix_largefile.go
+ # Use lseek by default.
+-@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@syscall_size_file = go/syscall/libcall_posix_regfile.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@syscall_size_file = go/syscall/libcall_posix_regfile.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_LINUX_FALSE@syscall_size_file = go/syscall/libcall_posix_largefile.go
+ 
+ # Declare libc functions that vary for largefile systems.
+ # Always use lseek64 on GNU/Linux.
+ @LIBGO_IS_LINUX_TRUE@syscall_size_file = go/syscall/libcall_posix_largefile.go
+-@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@syscall_socket_file = go/syscall/socket_bsd.go
++@LIBGO_IS_GNU_FALSE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@syscall_socket_file = go/syscall/socket_bsd.go
++@LIBGO_IS_GNU_TRUE@@LIBGO_IS_IRIX_FALSE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@syscall_socket_file = go/syscall/socket_gnu.go
+ @LIBGO_IS_IRIX_TRUE@@LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_FALSE@syscall_socket_file = go/syscall/socket_irix.go
+ @LIBGO_IS_LINUX_FALSE@@LIBGO_IS_SOLARIS_TRUE@syscall_socket_file = go/syscall/socket_solaris.go
+ 
+ # Define socket sizes and types.
+ @LIBGO_IS_LINUX_TRUE@syscall_socket_file = go/syscall/socket_linux.go epoll.go
+-@LIBGO_IS_LINUX_FALSE@syscall_socket_type_file = 
++@LIBGO_IS_LINUX_FALSE@syscall_socket_type_file =
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_PPC64LE_FALSE@@LIBGO_IS_PPC64_FALSE@syscall_socket_type_file = go/syscall/socket_linux_type.go
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_PPC64LE_FALSE@@LIBGO_IS_PPC64_TRUE@syscall_socket_type_file = go/syscall/socket_linux_ppc64x_type.go
+ @LIBGO_IS_LINUX_TRUE@@LIBGO_IS_PPC64LE_TRUE@syscall_socket_type_file = go/syscall/socket_linux_ppc64x_type.go
+@@ -2069,42 +2092,48 @@ go_unicode_utf8_files = \
+ 
+ # Support for uname.
+ # 32-bit Solaris 2/x86 needs _nuname, handled in libcall_solaris_386.go.
+-@LIBGO_IS_386_TRUE@@LIBGO_IS_SOLARIS_TRUE@syscall_uname_file = 
++@LIBGO_IS_386_TRUE@@LIBGO_IS_SOLARIS_TRUE@syscall_uname_file =
+ @LIBGO_IS_SOLARIS_FALSE@syscall_uname_file = go/syscall/libcall_uname.go
+-@LIBGO_IS_LINUX_FALSE@syscall_sockcmsg_file = 
++@LIBGO_IS_LINUX_FALSE@syscall_sockcmsg_file =
+ 
+ # GNU/Linux specific socket control messages.
+ @LIBGO_IS_LINUX_TRUE@syscall_sockcmsg_file = go/syscall/sockcmsg_linux.go
+-@LIBGO_IS_LINUX_FALSE@syscall_netlink_file = 
++@LIBGO_IS_LINUX_FALSE@syscall_netlink_file =
+ 
+ # Support for netlink sockets and messages.
+ @LIBGO_IS_LINUX_TRUE@syscall_netlink_file = go/syscall/netlink_linux.go
+-@LIBGO_IS_LINUX_FALSE@syscall_lsf_file = 
++@LIBGO_IS_LINUX_FALSE@syscall_lsf_file =
+ 
+ # GNU/Linux specific socket filters.
+ @LIBGO_IS_LINUX_TRUE@syscall_lsf_file = go/syscall/lsf_linux.go
+ @LIBGO_IS_ARM64_FALSE@@LIBGO_IS_LINUX_TRUE@syscall_ustat_file = go/syscall/libcall_linux_ustat.go
+ 
+ # GNU/Linux specific ustat support.
+-@LIBGO_IS_ARM64_TRUE@@LIBGO_IS_LINUX_TRUE@syscall_ustat_file = 
+-@LIBGO_IS_LINUX_FALSE@syscall_ustat_file = 
++@LIBGO_IS_ARM64_TRUE@@LIBGO_IS_LINUX_TRUE@syscall_ustat_file =
++@LIBGO_IS_LINUX_FALSE@syscall_ustat_file =
+ @LIBGO_IS_LINUX_FALSE@syscall_utimesnano_file = go/syscall/libcall_posix_utimesnano.go
+ 
+ # GNU/Linux specific utimesnano support.
+ @LIBGO_IS_LINUX_TRUE@syscall_utimesnano_file = go/syscall/libcall_linux_utimesnano.go
+-@LIBGO_IS_LINUX_FALSE@syscall_creds_test_file = 
++@LIBGO_IS_LINUX_FALSE@syscall_creds_test_file =
+ 
+ # Test files.
+ @LIBGO_IS_LINUX_TRUE@syscall_creds_test_file = go/syscall/creds_test.go
+-@LIBGO_IS_LINUX_FALSE@syscall_exec_test_file = 
++@LIBGO_IS_LINUX_FALSE@syscall_exec_test_file =
+ @LIBGO_IS_LINUX_TRUE@syscall_exec_test_file = go/syscall/exec_linux_test.go go/syscall/syscall_linux_test.go
+ @LIBGO_IS_LINUX_FALSE@syscall_os_file = go/syscall/libcall_bsd.go
+-@LIBGO_IS_LINUX_TRUE@syscall_os_file = 
++@LIBGO_IS_LINUX_TRUE@syscall_os_file =
++@LIBGO_IS_GNU_FALSE@syscall_libcall_file = go/syscall/libcall_posix.go
++
++# GNU/Hurd specific library calls support.
++@LIBGO_IS_GNU_TRUE@syscall_libcall_file = go/syscall/libcall_posix-1.go
++@LIBGO_IS_GNU_FALSE@syscall_os_test_file = go/syscall/syscall_unix_test.go
++@LIBGO_IS_GNU_TRUE@syscall_os_test_file = go/syscall/syscall_gnu_test.go
+ go_base_syscall_files = \
+ 	go/syscall/env_unix.go \
+ 	go/syscall/syscall_errno.go \
+ 	go/syscall/libcall_support.go \
+-	go/syscall/libcall_posix.go \
++	$(syscall_libcall_file) \
+ 	go/syscall/msan0.go \
+ 	go/syscall/socket.go \
+ 	go/syscall/sockcmsg_unix.go \
+@@ -2151,13 +2180,13 @@ go_syscall_test_files = \
+ 	go/syscall/export_unix_test.go \
+ 	go/syscall/mmap_unix_test.go \
+ 	go/syscall/syscall_test.go \
+-	go/syscall/syscall_unix_test.go
++	$(syscall_os_test_file)
+ 
+-@LIBGO_IS_LINUX_FALSE@os_lib_inotify_lo = 
++@LIBGO_IS_LINUX_FALSE@os_lib_inotify_lo =
+ 
+ # os_lib_inotify_lo = os/inotify.lo
+-@LIBGO_IS_LINUX_TRUE@os_lib_inotify_lo = 
+-@LIBGO_IS_LINUX_FALSE@syscall_lib_clone_lo = 
++@LIBGO_IS_LINUX_TRUE@os_lib_inotify_lo =
++@LIBGO_IS_LINUX_FALSE@syscall_lib_clone_lo =
+ @LIBGO_IS_LINUX_TRUE@syscall_lib_clone_lo = syscall/clone_linux.lo
+ libgo_go_objs = \
+ 	bufio.lo \
+@@ -2380,8 +2409,8 @@ BUILDNETGO = \
+ 	files=`echo $^ | sed -e 's/[^ ]*\.gox//g'`; \
+ 	$(GOCOMPILE) -I . -c -fPIC -fgo-pkgpath=net -o $@ $$files
+ 
+-GOTESTFLAGS = 
+-GOBENCH = 
++GOTESTFLAGS =
++GOBENCH =
+ 
+ # Check a package.
+ CHECK = \
+@@ -2586,7 +2615,7 @@ TEST_PACKAGES = \
+ 	unicode/utf8/check
+ 
+ MOSTLYCLEAN_FILES = libgo.head libgo.sum.sep libgo.log.sep
+-CLEANFILES = *.go *.gox goc2c *.c s-version libgo.sum libgo.log
++CLEANFILES = *.go *.gox goc2c *.c s-* libgo.sum libgo.log
+ all: config.h
+ 	$(MAKE) $(AM_MAKEFLAGS) all-recursive
+ 
+@@ -2634,7 +2663,7 @@ config.h: stamp-h1
+ stamp-h1: $(srcdir)/config.h.in $(top_builddir)/config.status
+ 	@rm -f stamp-h1
+ 	cd $(top_builddir) && $(SHELL) ./config.status config.h
+-$(srcdir)/config.h.in: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) 
++$(srcdir)/config.h.in: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ 	($(am__cd) $(top_srcdir) && $(AUTOHEADER))
+ 	rm -f stamp-h1
+ 	touch $@
+@@ -2672,19 +2701,19 @@ uninstall-toolexeclibLIBRARIES:
+ 
+ clean-toolexeclibLIBRARIES:
+ 	-test -z "$(toolexeclib_LIBRARIES)" || rm -f $(toolexeclib_LIBRARIES)
+-libgobegin-llgo.a: $(libgobegin_llgo_a_OBJECTS) $(libgobegin_llgo_a_DEPENDENCIES) $(EXTRA_libgobegin_llgo_a_DEPENDENCIES) 
++libgobegin-llgo.a: $(libgobegin_llgo_a_OBJECTS) $(libgobegin_llgo_a_DEPENDENCIES) $(EXTRA_libgobegin_llgo_a_DEPENDENCIES)
+ 	-rm -f libgobegin-llgo.a
+ 	$(libgobegin_llgo_a_AR) libgobegin-llgo.a $(libgobegin_llgo_a_OBJECTS) $(libgobegin_llgo_a_LIBADD)
+ 	$(RANLIB) libgobegin-llgo.a
+-libgobegin.a: $(libgobegin_a_OBJECTS) $(libgobegin_a_DEPENDENCIES) $(EXTRA_libgobegin_a_DEPENDENCIES) 
++libgobegin.a: $(libgobegin_a_OBJECTS) $(libgobegin_a_DEPENDENCIES) $(EXTRA_libgobegin_a_DEPENDENCIES)
+ 	-rm -f libgobegin.a
+ 	$(libgobegin_a_AR) libgobegin.a $(libgobegin_a_OBJECTS) $(libgobegin_a_LIBADD)
+ 	$(RANLIB) libgobegin.a
+-libgolibbegin.a: $(libgolibbegin_a_OBJECTS) $(libgolibbegin_a_DEPENDENCIES) $(EXTRA_libgolibbegin_a_DEPENDENCIES) 
++libgolibbegin.a: $(libgolibbegin_a_OBJECTS) $(libgolibbegin_a_DEPENDENCIES) $(EXTRA_libgolibbegin_a_DEPENDENCIES)
+ 	-rm -f libgolibbegin.a
+ 	$(libgolibbegin_a_AR) libgolibbegin.a $(libgolibbegin_a_OBJECTS) $(libgolibbegin_a_LIBADD)
+ 	$(RANLIB) libgolibbegin.a
+-libnetgo.a: $(libnetgo_a_OBJECTS) $(libnetgo_a_DEPENDENCIES) $(EXTRA_libnetgo_a_DEPENDENCIES) 
++libnetgo.a: $(libnetgo_a_OBJECTS) $(libnetgo_a_DEPENDENCIES) $(EXTRA_libnetgo_a_DEPENDENCIES)
+ 	-rm -f libnetgo.a
+ 	$(libnetgo_a_AR) libnetgo.a $(libnetgo_a_OBJECTS) $(libnetgo_a_LIBADD)
+ 	$(RANLIB) libnetgo.a
+@@ -2720,9 +2749,9 @@ clean-toolexeclibLTLIBRARIES:
+ 	  echo "rm -f \"$${dir}/so_locations\""; \
+ 	  rm -f "$${dir}/so_locations"; \
+ 	done
+-libgo-llgo.la: $(libgo_llgo_la_OBJECTS) $(libgo_llgo_la_DEPENDENCIES) $(EXTRA_libgo_llgo_la_DEPENDENCIES) 
++libgo-llgo.la: $(libgo_llgo_la_OBJECTS) $(libgo_llgo_la_DEPENDENCIES) $(EXTRA_libgo_llgo_la_DEPENDENCIES)
+ 	$(libgo_llgo_la_LINK) $(am_libgo_llgo_la_rpath) $(libgo_llgo_la_OBJECTS) $(libgo_llgo_la_LIBADD) $(LIBS)
+-libgo.la: $(libgo_la_OBJECTS) $(libgo_la_DEPENDENCIES) $(EXTRA_libgo_la_DEPENDENCIES) 
++libgo.la: $(libgo_la_OBJECTS) $(libgo_la_DEPENDENCIES) $(EXTRA_libgo_la_DEPENDENCIES)
+ 	$(libgo_la_LINK) $(am_libgo_la_rpath) $(libgo_la_OBJECTS) $(libgo_la_LIBADD) $(LIBS)
+ 
+ mostlyclean-compile:
+@@ -2735,6 +2764,7 @@ distclean-compile:
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpuprof.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/env_posix.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/getncpu-bsd.Plo@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/getncpu-gnu.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/getncpu-irix.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/getncpu-linux.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/getncpu-none.Plo@am__quote@
+@@ -3561,6 +3591,13 @@ getncpu-none.lo: runtime/getncpu-none.c
+ @AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ @am__fastdepCC_FALSE@	$(LIBTOOL)  --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o getncpu-none.lo `test -f 'runtime/getncpu-none.c' || echo '$(srcdir)/'`runtime/getncpu-none.c
+ 
++getncpu-gnu.lo: runtime/getncpu-gnu.c
++@am__fastdepCC_TRUE@	$(LIBTOOL)  --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT getncpu-gnu.lo -MD -MP -MF $(DEPDIR)/getncpu-gnu.Tpo -c -o getncpu-gnu.lo `test -f 'runtime/getncpu-gnu.c' || echo '$(srcdir)/'`runtime/getncpu-gnu.c
++@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/getncpu-gnu.Tpo $(DEPDIR)/getncpu-gnu.Plo
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='runtime/getncpu-gnu.c' object='getncpu-gnu.lo' libtool=yes @AMDEPBACKSLASH@
++@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
++@am__fastdepCC_FALSE@	$(LIBTOOL)  --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o getncpu-gnu.lo `test -f 'runtime/getncpu-gnu.c' || echo '$(srcdir)/'`runtime/getncpu-gnu.c
++
+ getncpu-bsd.lo: runtime/getncpu-bsd.c
+ @am__fastdepCC_TRUE@	$(LIBTOOL)  --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT getncpu-bsd.lo -MD -MP -MF $(DEPDIR)/getncpu-bsd.Tpo -c -o getncpu-bsd.lo `test -f 'runtime/getncpu-bsd.c' || echo '$(srcdir)/'`runtime/getncpu-bsd.c
+ @am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/getncpu-bsd.Tpo $(DEPDIR)/getncpu-bsd.Plo
+@@ -6307,7 +6344,7 @@ crypto/des.gox: crypto/des.lo
+ 	$(BUILDGOX)
+ crypto/dsa.gox: crypto/dsa.lo
+ 	$(BUILDGOX)
+-crypto/ecdsa.gox: crypto/ecdsa.lo	
++crypto/ecdsa.gox: crypto/ecdsa.lo
+ 	$(BUILDGOX)
+ crypto/elliptic.gox: crypto/elliptic.lo
+ 	$(BUILDGOX)
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_configure.ac.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_configure.ac.diff
@@ -0,0 +1,28 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/configure.ac
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/configure.ac
++++ gcc-6-6.2.1-4.1/src/libgo/configure.ac
+@@ -151,6 +151,7 @@ is_openbsd=no
+ is_dragonfly=no
+ is_rtems=no
+ is_solaris=no
++is_gnu=no
+ GOOS=unknown
+ case ${host} in
+   *-*-darwin*)   is_darwin=yes;  GOOS=darwin ;;
+@@ -162,6 +163,7 @@ case ${host} in
+   *-*-dragonfly*) is_dragonfly=yes; GOOS=dragonfly ;;
+   *-*-rtems*)    is_rtems=yes;   GOOS=rtems ;;
+   *-*-solaris2*) is_solaris=yes; GOOS=solaris ;;
++  *-*-gnu*)      is_gnu=yes;     GOOS=gnu ;;
+ esac
+ AM_CONDITIONAL(LIBGO_IS_DARWIN, test $is_darwin = yes)
+ AM_CONDITIONAL(LIBGO_IS_FREEBSD, test $is_freebsd = yes)
+@@ -172,6 +174,7 @@ AM_CONDITIONAL(LIBGO_IS_OPENBSD, test $i
+ AM_CONDITIONAL(LIBGO_IS_DRAGONFLY, test $is_dragonfly = yes)
+ AM_CONDITIONAL(LIBGO_IS_RTEMS, test $is_rtems = yes)
+ AM_CONDITIONAL(LIBGO_IS_SOLARIS, test $is_solaris = yes)
++AM_CONDITIONAL(LIBGO_IS_GNU, test $is_gnu = yes)
+ AC_SUBST(GOOS)
+ 
+ dnl Test whether we need to use DejaGNU or whether we can use the
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_go_net_sendfile_gnu.go.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_go_net_sendfile_gnu.go.diff
@@ -0,0 +1,84 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sendfile_gnu.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sendfile_gnu.go
+@@ -0,0 +1,79 @@
++// Copyright 2011 The Go Authors.  All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++package net
++
++import (
++	"io"
++	"os"
++	"syscall"
++)
++
++// maxSendfileSize is the largest chunk size we ask the kernel to copy
++// at a time.
++const maxSendfileSize int = 4 << 20
++
++// sendFile copies the contents of r to c using the sendfile
++// system call to minimize copies.
++//
++// if handled == true, sendFile returns the number of bytes copied and any
++// non-EOF error.
++//
++// if handled == false, sendFile performed no work.
++func sendFile(c *netFD, r io.Reader) (written int64, err error, handled bool) {
++	var remain int64 = 1 << 62 // by default, copy until EOF
++
++	lr, ok := r.(*io.LimitedReader)
++	if ok {
++		remain, r = lr.N, lr.R
++		if remain <= 0 {
++			return 0, nil, true
++		}
++	}
++	f, ok := r.(*os.File)
++	if !ok {
++		return 0, nil, false
++	}
++
++	if err := c.writeLock(); err != nil {
++		return 0, err, true
++	}
++	defer c.writeUnlock()
++
++	dst := c.sysfd
++	src := int(f.Fd())
++	for remain > 0 {
++		n := maxSendfileSize
++		if int64(n) > remain {
++			n = int(remain)
++		}
++		n, err1 := syscall.Sendfile(dst, src, nil, n)
++		if n > 0 {
++			written += int64(n)
++			remain -= int64(n)
++		}
++		if n == 0 && err1 == nil {
++			break
++		}
++		if err1 == syscall.EAGAIN {
++			if err1 = c.pd.WaitWrite(); err1 == nil {
++				continue
++			}
++		}
++		if err1 != nil {
++			// This includes syscall.ENOSYS (no kernel
++			// support) and syscall.EINVAL (fd types which
++			// don't implement sendfile)
++			err = err1
++			break
++		}
++	}
++	if lr != nil {
++		lr.N = remain
++	}
++	if err != nil {
++		err = os.NewSyscallError("sendfile", err)
++	}
++	return written, err, written > 0
++}
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_go_net_sock_gnu.go.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_go_net_sock_gnu.go.diff
@@ -0,0 +1,19 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sock_gnu.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sock_gnu.go
+@@ -0,0 +1,14 @@
++// Copyright 2014 The Go Authors.  All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build gnu
++
++package net
++
++import "syscall"
++
++func maxListenerBacklog() int {
++       // From /usr/include/i386-gnu/bits/socket.h
++       return syscall.SOMAXCONN
++}
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_go_net_sockopt_gnu.go.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_go_net_sockopt_gnu.go.diff
@@ -0,0 +1,50 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sockopt_gnu.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sockopt_gnu.go
+@@ -0,0 +1,45 @@
++// Copyright 2011 The Go Authors.  All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build gnu
++
++package net
++
++import (
++	"os"
++	"syscall"
++)
++
++func setDefaultSockopts(s, family, sotype int, ipv6only bool) error {
++	if family == syscall.AF_INET6 && sotype != syscall.SOCK_RAW {
++		// Allow both IP versions even if the OS default
++		// is otherwise.  Note that some operating systems
++		// never admit this option.
++		syscall.SetsockoptInt(s, syscall.IPPROTO_IPV6, syscall.IPV6_V6ONLY, boolint(ipv6only))
++	}
++	// Allow broadcast.
++	return os.NewSyscallError("setsockopt", syscall.SetsockoptInt(s, syscall.SOL_SOCKET, syscall.SO_BROADCAST, 1))
++}
++
++func setDefaultListenerSockopts(s int) error {
++	// Allow reuse of recently-used addresses.
++	return os.NewSyscallError("setsockopt", syscall.SetsockoptInt(s, syscall.SOL_SOCKET, syscall.SO_REUSEADDR, 1))
++}
++
++func setDefaultMulticastSockopts(s int) error {
++	// Allow multicast UDP and raw IP datagram sockets to listen
++	// concurrently across multiple listeners.
++	if err := syscall.SetsockoptInt(s, syscall.SOL_SOCKET, syscall.SO_REUSEADDR, 1); err != nil {
++		return os.NewSyscallError("setsockopt", err)
++	}
++	// Allow reuse of recently-used ports.
++	// This option is supported only in descendants of 4.4BSD,
++	// to make an effective multicast application that requires
++	// quick draw possible.
++	// Not supported on GNU/Hurd
++	//if syscall.SO_REUSEPORT != 0 {
++	//	return os.NewSyscallError("setsockopt", syscall.SetsockoptInt(s, syscall.SOL_SOCKET, syscall.SO_REUSEPORT, 1))
++	//}
++	return nil
++}
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_go_net_sockoptip_gnu.go.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_go_net_sockoptip_gnu.go.diff
@@ -0,0 +1,35 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/net/sockoptip_gnu.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/net/sockoptip_gnu.go
+@@ -0,0 +1,30 @@
++// Copyright 2011 The Go Authors.  All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build gnu
++
++package net
++
++import (
++	"os"
++	"syscall"
++)
++
++func setIPv4MulticastInterface(fd *netFD, ifi *Interface) error {
++	ip, err := interfaceToIPv4Addr(ifi)
++	if err != nil {
++		return os.NewSyscallError("setsockopt", err)
++	}
++	var a [4]byte
++	copy(a[:], ip.To4())
++	if err := fd.incref(); err != nil {
++		return err
++	}
++	defer fd.decref()
++	return os.NewSyscallError("setsockopt", syscall.SetsockoptInet4Addr(fd.sysfd, syscall.IPPROTO_IP, syscall.IP_MULTICAST_IF, a))
++}
++
++func setIPv4MulticastLoopback(fd *netFD, v bool) error {
++	return syscall.ENOPROTOOPT
++}
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_go_os_os_test.go.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_go_os_os_test.go.diff
@@ -0,0 +1,15 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/os/os_test.go
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/os/os_test.go
++++ gcc-6-6.2.1-4.1/src/libgo/go/os/os_test.go
+@@ -1192,8 +1192,9 @@ func TestSeek(t *testing.T) {
+ 	for i, tt := range tests {
+ 		off, err := f.Seek(tt.in, tt.whence)
+ 		if off != tt.out || err != nil {
+-			if e, ok := err.(*PathError); ok && e.Err == syscall.EINVAL && tt.out > 1<<32 {
++			if e, ok := err.(*PathError); ok && e.Err == syscall.EINVAL || e.Err == syscall.EFBIG && tt.out > 1<<32 {
+ 				// Reiserfs rejects the big seeks.
++				// GNU rejects the big seeks, returns EFBIG
+ 				// https://golang.org/issue/91
+ 				break
+ 			}
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_go_syscall_libcall_gnu.go.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_go_syscall_libcall_gnu.go.diff
@@ -0,0 +1,190 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/libcall_gnu.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/libcall_gnu.go
+@@ -0,0 +1,185 @@
++// Copyright 2014 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// GNU/Hurd library calls.
++
++package syscall
++
++import "unsafe"
++
++//sys   Openat(dirfd int, path string, flags int, mode uint32) (fd int, err error)
++//__go_openat(dirfd _C_int, path *byte, flags _C_int, mode Mode_t) _C_int
++
++//sys   futimesat(dirfd int, path *byte, times *[2]Timeval) (err error)
++//futimesat(dirfd _C_int, path *byte, times *[2]Timeval) _C_int
++func Futimesat(dirfd int, path string, tv []Timeval) (err error) {
++	if len(tv) != 2 {
++		return EINVAL
++	}
++	return futimesat(dirfd, StringBytePtr(path), (*[2]Timeval)(unsafe.Pointer(&tv[0])))
++}
++
++func Futimes(fd int, tv []Timeval) (err error) {
++	// Believe it or not, this is the best we can do on GNU/Linux
++	// (and is what glibc does).
++	return Utimes("/proc/self/fd/"+itoa(fd), tv)
++}
++
++//sys   ptrace(request int, pid int, addr uintptr, data uintptr) (err error)
++//ptrace(request _C_int, pid Pid_t, addr *byte, data *byte) _C_long
++
++// Dummy function
++func raw_ptrace(request int, pid int, addr *byte, data *byte) Errno {
++	return ENOSYS
++}
++
++//sys   accept4(fd int, sa *RawSockaddrAny, len *Socklen_t, flags int) (nfd int, err error)
++//accept4(fd _C_int, sa *RawSockaddrAny, len *Socklen_t, flags _C_int) _C_int
++
++func Accept4(fd int, flags int) (nfd int, sa Sockaddr, err error) {
++	var rsa RawSockaddrAny
++	var len Socklen_t = SizeofSockaddrAny
++	nfd, err = accept4(fd, &rsa, &len, flags)
++	if err != nil {
++		return -1, nil, err
++	}
++	sa, err = anyToSockaddr(&rsa)
++	if err != nil {
++		Close(nfd)
++		return -1, nil, err
++	}
++	return nfd, sa, nil
++}
++
++///INCLUDE?
++///sys   Acct(path string) (err error)
++///acct(path *byte) _C_int
++
++//sysnb Dup3(oldfd int, newfd int, flags int) (err error)
++//dup3(oldfd _C_int, newfd _C_int, flags _C_int) _C_int
++
++//sys   Faccessat(dirfd int, path string, mode uint32, flags int) (err error)
++//faccessat(dirfd _C_int, pathname *byte, mode _C_int, flags _C_int) _C_int
++
++//sys   Fallocate(fd int, mode uint32, off int64, len int64) (err error)
++//fallocate(fd _C_int, mode _C_int, offset Offset_t, len Offset_t) _C_int
++
++//sys   Fchmodat(dirfd int, path string, mode uint32, flags int) (err error)
++//fchmodat(dirfd _C_int, pathname *byte, mode Mode_t, flags _C_int) _C_int
++
++//sys   Fchownat(dirfd int, path string, uid int, gid int, flags int) (err error)
++//fchownat(dirfd _C_int, path *byte, owner Uid_t, group Gid_t, flags _C_int) _C_int
++
++//sys   Flock(fd int, how int) (err error)
++//flock(fd _C_int, how _C_int) _C_int
++
++//sys   Fstatfs(fd int, buf *Statfs_t) (err error)
++//fstatfs(fd _C_int, buf *Statfs_t) _C_int
++
++func Getdents(fd int, buf []byte) (n int, err error) {
++	var p *byte
++	if len(buf) > 0 {
++		p = &buf[0]
++	} else {
++		p = (*byte)(unsafe.Pointer(&_zero))
++	}
++	s := SYS_GETDENTS64
++	if s == 0 {
++		s = SYS_GETDENTS
++	}
++	r1, _, errno := Syscall(uintptr(s), uintptr(fd), uintptr(unsafe.Pointer(p)), uintptr(len(buf)))
++	n = int(r1)
++	if n < 0 {
++		err = errno
++	}
++	return
++}
++
++func clen(n []byte) int {
++	for i := 0; i < len(n); i++ {
++		if n[i] == 0 {
++			return i
++		}
++	}
++	return len(n)
++}
++
++func ReadDirent(fd int, buf []byte) (n int, err error) {
++	return Getdents(fd, buf)
++}
++
++func ParseDirent(buf []byte, max int, names []string) (consumed int, count int, newnames []string) {
++	origlen := len(buf)
++	count = 0
++	for max != 0 && len(buf) > 0 {
++		dirent := (*Dirent)(unsafe.Pointer(&buf[0]))
++		buf = buf[dirent.Reclen:]
++		if dirent.Ino == 0 { // File absent in directory.
++			continue
++		}
++		bytes := (*[10000]byte)(unsafe.Pointer(&dirent.Name[0]))
++		var name = string(bytes[0:clen(bytes[:])])
++		if name == "." || name == ".." { // Useless names
++			continue
++		}
++		max--
++		count++
++		names = append(names, name)
++	}
++	return origlen - len(buf), count, names
++}
++
++///INCLUDE??
++///sys   Getxattr(path string, attr string, dest []byte) (sz int, err error)
++///getxattr(path *byte, attr *byte, buf *byte, count Size_t) Ssize_t
++
++///INCLUDE??
++///sys   Listxattr(path string, dest []byte) (sz int, err error)
++///listxattr(path *byte, list *byte, size Size_t) Ssize_t
++
++//sys   Mkdirat(dirfd int, path string, mode uint32) (err error)
++//mkdirat(dirfd _C_int, path *byte, mode Mode_t) _C_int
++
++//sys   Mknodat(dirfd int, path string, mode uint32, dev int) (err error)
++//mknodat(dirfd _C_int, path *byte, mode Mode_t, dev _dev_t) _C_int
++
++//sysnb pipe2(p *[2]_C_int, flags int) (err error)
++//pipe2(p *[2]_C_int, flags _C_int) _C_int
++func Pipe2(p []int, flags int) (err error) {
++	if len(p) != 2 {
++		return EINVAL
++	}
++	var pp [2]_C_int
++	err = pipe2(&pp, flags)
++	p[0] = int(pp[0])
++	p[1] = int(pp[1])
++	return
++}
++
++///INCLUDE??
++///sys   Removexattr(path string, attr string) (err error)
++///removexattr(path *byte, name *byte) _C_int
++
++///INCLUDE??
++///sys   Renameat(olddirfd int, oldpath string, newdirfd int, newpath string) (err error)
++///renameat(olddirfd _C_int, oldpath *byte, newdirfd _C_int, newpath *byte) _C_int
++
++//INCLUDE??
++///sys   Setxattr(path string, attr string, data []byte, flags int) (err error)
++///setxattr(path *byte, name *byte, value *byte, size Size_t, flags _C_int) _C_int
++
++//sys   SyncFileRange(fd int, off int64, n int64, flags int) (err error)
++//sync_file_range(fd _C_int, off Offset_t, n Offset_t, flags _C_uint) _C_int
++
++//INCLUDE??
++///sysnb Sysinfo(info *Sysinfo_t) (err error)
++///sysinfo(info *Sysinfo_t) _C_int
++
++//func Unlinkat(dirfd int, path string) (err error) {
++//	return unlinkat(dirfd, path, 0)
++//}
++
++///INCLUDE??
++///sys   Ustat(dev int, ubuf *Ustat_t) (err error)
++///ustat(dev _dev_t, ubuf *Ustat_t) _C_int
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_go_syscall_libcall_gnu_386.go.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_go_syscall_libcall_gnu_386.go.diff
@@ -0,0 +1,15 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/libcall_gnu_386.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/libcall_gnu_386.go
+@@ -0,0 +1,10 @@
++// Copyright 2012 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// GNU/Hurd library calls 386 specific.
++
++package syscall
++
++//sys	Ioperm(from int, num int, on int) (err error)
++//ioperm(from _C_long, num _C_long, on _C_int) _C_int
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_go_syscall_libcall_posix-1.go.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_go_syscall_libcall_posix-1.go.diff
@@ -0,0 +1,398 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/libcall_posix-1.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/libcall_posix-1.go
+@@ -0,0 +1,393 @@
++// Copyright 2011 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// POSIX library calls.
++// Removed the mount call for GNU/Hurd, it exists but use translators.
++// Functionality is not the same as descibed in Linux <sys/mount.h>
++// Removed the mlockall/munlockall calls for GNU/Hurd, not yet implemented.
++// Removed the madvise call for GNU/Hurd, not yet implemented.
++// This file is compiled as ordinary Go code,
++// but it is also input to mksyscall,
++// which parses the //sys lines and generates library call stubs.
++// Note that sometimes we use a lowercase //sys name and
++// wrap it in our own nicer implementation.
++
++package syscall
++
++import "unsafe"
++
++/*
++ * Wrapped
++ */
++
++//sysnb	pipe(p *[2]_C_int) (err error)
++//pipe(p *[2]_C_int) _C_int
++func Pipe(p []int) (err error) {
++	if len(p) != 2 {
++		return EINVAL
++	}
++	var pp [2]_C_int
++	err = pipe(&pp)
++	p[0] = int(pp[0])
++	p[1] = int(pp[1])
++	return
++}
++
++//sys	utimes(path string, times *[2]Timeval) (err error)
++//utimes(path *byte, times *[2]Timeval) _C_int
++func Utimes(path string, tv []Timeval) (err error) {
++	if len(tv) != 2 {
++		return EINVAL
++	}
++	return utimes(path, (*[2]Timeval)(unsafe.Pointer(&tv[0])))
++}
++
++//sys	getcwd(buf *byte, size Size_t) (err error)
++//getcwd(buf *byte, size Size_t) *byte
++
++const ImplementsGetwd = true
++
++func Getwd() (ret string, err error) {
++	for len := Size_t(4096); ; len *= 2 {
++		b := make([]byte, len)
++		err := getcwd(&b[0], len)
++		if err == nil {
++			i := 0
++			for b[i] != 0 {
++				i++
++			}
++			return string(b[0:i]), nil
++		}
++		if err != ERANGE {
++			return "", err
++		}
++	}
++}
++
++func Getcwd(buf []byte) (n int, err error) {
++	err = getcwd(&buf[0], Size_t(len(buf)))
++	if err == nil {
++		i := 0
++		for buf[i] != 0 {
++			i++
++		}
++		n = i + 1
++	}
++	return
++}
++
++//sysnb	getgroups(size int, list *Gid_t) (nn int, err error)
++//getgroups(size _C_int, list *Gid_t) _C_int
++
++func Getgroups() (gids []int, err error) {
++	n, err := getgroups(0, nil)
++	if err != nil {
++		return nil, err
++	}
++	if n == 0 {
++		return nil, nil
++	}
++
++	// Sanity check group count.  Max is 1<<16 on GNU/Linux.
++	if n < 0 || n > 1<<20 {
++		return nil, EINVAL
++	}
++
++	a := make([]Gid_t, n)
++	n, err = getgroups(n, &a[0])
++	if err != nil {
++		return nil, err
++	}
++	gids = make([]int, n)
++	for i, v := range a[0:n] {
++		gids[i] = int(v)
++	}
++	return
++}
++
++//sysnb	setgroups(n int, list *Gid_t) (err error)
++//setgroups(n Size_t, list *Gid_t) _C_int
++
++func Setgroups(gids []int) (err error) {
++	if len(gids) == 0 {
++		return setgroups(0, nil)
++	}
++
++	a := make([]Gid_t, len(gids))
++	for i, v := range gids {
++		a[i] = Gid_t(v)
++	}
++	return setgroups(len(a), &a[0])
++}
++
++type WaitStatus uint32
++
++// The WaitStatus methods are implemented in C, to pick up the macros
++// #defines in <sys/wait.h>.
++
++func (w WaitStatus) Exited() bool
++func (w WaitStatus) Signaled() bool
++func (w WaitStatus) Stopped() bool
++func (w WaitStatus) Continued() bool
++func (w WaitStatus) CoreDump() bool
++func (w WaitStatus) ExitStatus() int
++func (w WaitStatus) Signal() Signal
++func (w WaitStatus) StopSignal() Signal
++func (w WaitStatus) TrapCause() int
++
++//sys	Mkfifo(path string, mode uint32) (err error)
++//mkfifo(path *byte, mode Mode_t) _C_int
++
++//sys	Select(nfd int, r *FdSet, w *FdSet, e *FdSet, timeout *Timeval) (n int, err error)
++//select(nfd _C_int, r *FdSet, w *FdSet, e *FdSet, timeout *Timeval) _C_int
++
++const nfdbits = int(unsafe.Sizeof(fds_bits_type(0)) * 8)
++
++type FdSet struct {
++	Bits [(FD_SETSIZE + nfdbits - 1) / nfdbits]fds_bits_type
++}
++
++func FDSet(fd int, set *FdSet) {
++	set.Bits[fd/nfdbits] |= (1 << (uint)(fd%nfdbits))
++}
++
++func FDClr(fd int, set *FdSet) {
++	set.Bits[fd/nfdbits] &^= (1 << (uint)(fd%nfdbits))
++}
++
++func FDIsSet(fd int, set *FdSet) bool {
++	if set.Bits[fd/nfdbits]&(1<<(uint)(fd%nfdbits)) != 0 {
++		return true
++	} else {
++		return false
++	}
++}
++
++func FDZero(set *FdSet) {
++	for i := range set.Bits {
++		set.Bits[i] = 0
++	}
++}
++
++//sys	Access(path string, mode uint32) (err error)
++//access(path *byte, mode _C_int) _C_int
++
++//sys	Chdir(path string) (err error)
++//chdir(path *byte) _C_int
++
++//sys	Chmod(path string, mode uint32) (err error)
++//chmod(path *byte, mode Mode_t) _C_int
++
++//sys	Chown(path string, uid int, gid int) (err error)
++//chown(path *byte, uid Uid_t, gid Gid_t) _C_int
++
++//sys	Chroot(path string) (err error)
++//chroot(path *byte) _C_int
++
++//sys	Close(fd int) (err error)
++//close(fd _C_int) _C_int
++
++//sys	Creat(path string, mode uint32) (fd int, err error)
++//creat(path *byte, mode Mode_t) _C_int
++
++//sysnb	Dup(oldfd int) (fd int, err error)
++//dup(oldfd _C_int) _C_int
++
++//sysnb	Dup2(oldfd int, newfd int) (err error)
++//dup2(oldfd _C_int, newfd _C_int) _C_int
++
++//sys	Exit(code int)
++//exit(code _C_int)
++
++//sys	Fchdir(fd int) (err error)
++//fchdir(fd _C_int) _C_int
++
++//sys	Fchmod(fd int, mode uint32) (err error)
++//fchmod(fd _C_int, mode Mode_t) _C_int
++
++//sys	Fchown(fd int, uid int, gid int) (err error)
++//fchown(fd _C_int, uid Uid_t, gid Gid_t) _C_int
++
++//sys	fcntl(fd int, cmd int, arg int) (val int, err error)
++//__go_fcntl(fd _C_int, cmd _C_int, arg _C_int) _C_int
++
++//sys	FcntlFlock(fd uintptr, cmd int, lk *Flock_t) (err error)
++//__go_fcntl_flock(fd _C_int, cmd _C_int, arg *Flock_t) _C_int
++
++//sys	Fdatasync(fd int) (err error)
++//fdatasync(fd _C_int) _C_int
++
++//sys	Fsync(fd int) (err error)
++//fsync(fd _C_int) _C_int
++
++//sysnb Getegid() (egid int)
++//getegid() Gid_t
++
++//sysnb Geteuid() (euid int)
++//geteuid() Uid_t
++
++//sysnb Getgid() (gid int)
++//getgid() Gid_t
++
++//sysnb	Getpagesize() (pagesize int)
++//getpagesize() _C_int
++
++//sysnb	Getpgid(pid int) (pgid int, err error)
++//getpgid(pid Pid_t) Pid_t
++
++//sysnb	Getpgrp() (pid int)
++//getpgrp() Pid_t
++
++//sysnb	Getpid() (pid int)
++//getpid() Pid_t
++
++//sysnb	Getppid() (ppid int)
++//getppid() Pid_t
++
++//sys Getpriority(which int, who int) (prio int, err error)
++//getpriority(which _C_int, who _C_int) _C_int
++
++//sysnb	Getrusage(who int, rusage *Rusage) (err error)
++//getrusage(who _C_int, rusage *Rusage) _C_int
++
++//sysnb	gettimeofday(tv *Timeval, tz *byte) (err error)
++//gettimeofday(tv *Timeval, tz *byte) _C_int
++func Gettimeofday(tv *Timeval) (err error) {
++	return gettimeofday(tv, nil)
++}
++
++//sysnb Getuid() (uid int)
++//getuid() Uid_t
++
++//sysnb	Kill(pid int, sig Signal) (err error)
++//kill(pid Pid_t, sig _C_int) _C_int
++
++//sys	Lchown(path string, uid int, gid int) (err error)
++//lchown(path *byte, uid Uid_t, gid Gid_t) _C_int
++
++//sys	Link(oldpath string, newpath string) (err error)
++//link(oldpath *byte, newpath *byte) _C_int
++
++//sys	Mkdir(path string, mode uint32) (err error)
++//mkdir(path *byte, mode Mode_t) _C_int
++
++//sys	Mknod(path string, mode uint32, dev int) (err error)
++//mknod(path *byte, mode Mode_t, dev _dev_t) _C_int
++
++//sys	Nanosleep(time *Timespec, leftover *Timespec) (err error)
++//nanosleep(time *Timespec, leftover *Timespec) _C_int
++
++//sys	Pause() (err error)
++//pause() _C_int
++
++//sys	read(fd int, p []byte) (n int, err error)
++//read(fd _C_int, buf *byte, count Size_t) Ssize_t
++
++//sys	readlen(fd int, p *byte, np int) (n int, err error)
++//read(fd _C_int, buf *byte, count Size_t) Ssize_t
++
++//sys	Readlink(path string, buf []byte) (n int, err error)
++//readlink(path *byte, buf *byte, bufsiz Size_t) Ssize_t
++
++//sys	Rename(oldpath string, newpath string) (err error)
++//rename(oldpath *byte, newpath *byte) _C_int
++
++//sys	Rmdir(path string) (err error)
++//rmdir(path *byte) _C_int
++
++//sys	Setdomainname(p []byte) (err error)
++//setdomainname(name *byte, len Size_t) _C_int
++
++//sys	Sethostname(p []byte) (err error)
++//sethostname(name *byte, len Size_t) _C_int
++
++//sysnb	Setgid(gid int) (err error)
++//setgid(gid Gid_t) _C_int
++
++//sysnb Setregid(rgid int, egid int) (err error)
++//setregid(rgid Gid_t, egid Gid_t) _C_int
++
++//sysnb	Setpgid(pid int, pgid int) (err error)
++//setpgid(pid Pid_t, pgid Pid_t) _C_int
++
++//sys Setpriority(which int, who int, prio int) (err error)
++//setpriority(which _C_int, who _C_int, prio _C_int) _C_int
++
++//sysnb	Setreuid(ruid int, euid int) (err error)
++//setreuid(ruid Uid_t, euid Uid_t) _C_int
++
++//sysnb	Setsid() (pid int, err error)
++//setsid() Pid_t
++
++//sysnb	settimeofday(tv *Timeval, tz *byte) (err error)
++//settimeofday(tv *Timeval, tz *byte) _C_int
++
++func Settimeofday(tv *Timeval) (err error) {
++	return settimeofday(tv, nil)
++}
++
++//sysnb	Setuid(uid int) (err error)
++//setuid(uid Uid_t) _C_int
++
++//sys	Symlink(oldpath string, newpath string) (err error)
++//symlink(oldpath *byte, newpath *byte) _C_int
++
++//sys	Sync()
++//sync()
++
++//sysnb	Time(t *Time_t) (tt Time_t, err error)
++//time(t *Time_t) Time_t
++
++//sysnb	Times(tms *Tms) (ticks uintptr, err error)
++//times(tms *Tms) _clock_t
++
++//sysnb	Umask(mask int) (oldmask int)
++//umask(mask Mode_t) Mode_t
++
++//sys	Unlink(path string) (err error)
++//unlink(path *byte) _C_int
++
++//sys	Utime(path string, buf *Utimbuf) (err error)
++//utime(path *byte, buf *Utimbuf) _C_int
++
++//sys	write(fd int, p []byte) (n int, err error)
++//write(fd _C_int, buf *byte, count Size_t) Ssize_t
++
++//sys	writelen(fd int, p *byte, np int) (n int, err error)
++//write(fd _C_int, buf *byte, count Size_t) Ssize_t
++
++//sys	munmap(addr uintptr, length uintptr) (err error)
++//munmap(addr *byte, length Size_t) _C_int
++
++//sys	Mprotect(b []byte, prot int) (err error)
++//mprotect(addr *byte, len Size_t, prot _C_int) _C_int
++
++//sys	Mlock(b []byte) (err error)
++//mlock(addr *byte, len Size_t) _C_int
++
++//sys	Munlock(b []byte) (err error)
++//munlock(addr *byte, len Size_t) _C_int
++
++func TimespecToNsec(ts Timespec) int64 { return int64(ts.Sec)*1e9 + int64(ts.Nsec) }
++
++func NsecToTimespec(nsec int64) (ts Timespec) {
++	ts.Sec = Timespec_sec_t(nsec / 1e9)
++	ts.Nsec = Timespec_nsec_t(nsec % 1e9)
++	return
++}
++
++func TimevalToNsec(tv Timeval) int64 { return int64(tv.Sec)*1e9 + int64(tv.Usec)*1e3 }
++
++func NsecToTimeval(nsec int64) (tv Timeval) {
++	nsec += 999 // round up to microsecond
++	tv.Sec = Timeval_sec_t(nsec / 1e9)
++	tv.Usec = Timeval_usec_t(nsec % 1e9 / 1e3)
++	return
++}
++
++//sysnb	Tcgetattr(fd int, p *Termios) (err error)
++//tcgetattr(fd _C_int, p *Termios) _C_int
++
++//sys	Tcsetattr(fd int, actions int, p *Termios) (err error)
++//tcsetattr(fd _C_int, actions _C_int, p *Termios) _C_int
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_go_syscall_socket_gnu.go.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_go_syscall_socket_gnu.go.diff
@@ -0,0 +1,93 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/socket_gnu.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/socket_gnu.go
+@@ -0,0 +1,88 @@
++// socket_gnu.go -- Socket handling specific to GNU/Hurd.
++
++// Copyright 2010 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++package syscall
++
++import "unsafe"
++
++const SizeofSockaddrInet4 = 16
++const SizeofSockaddrInet6 = 28
++const SizeofSockaddrUnix = 110
++
++type RawSockaddrInet4 struct {
++	Len    uint8
++	Family uint8
++	Port   uint16
++	Addr   [4]byte /* in_addr */
++	Zero   [8]uint8
++}
++
++func (sa *RawSockaddrInet4) setLen() Socklen_t {
++	sa.Len = SizeofSockaddrInet4
++	return SizeofSockaddrInet4
++}
++
++type RawSockaddrInet6 struct {
++	Len      uint8
++	Family   uint8
++	Port     uint16
++	Flowinfo uint32
++	Addr     [16]byte /* in6_addr */
++	Scope_id uint32
++}
++
++func (sa *RawSockaddrInet6) setLen() Socklen_t {
++	sa.Len = SizeofSockaddrInet6
++	return SizeofSockaddrInet6
++}
++
++type RawSockaddrUnix struct {
++	Len    uint8
++	Family uint8
++	Path   [108]int8
++}
++
++func (sa *RawSockaddrUnix) setLen(n int) {
++	sa.Len = uint8(3 + n) // 2 for Family, Len; 1 for NUL.
++}
++
++func (sa *RawSockaddrUnix) getLen() (int, error) {
++	if sa.Len < 3 || sa.Len > SizeofSockaddrUnix {
++		return 0, EINVAL
++	}
++	// Assume path ends at NUL.
++	n := 0
++	for n < len(sa.Path) && sa.Path[n] != 0 {
++		n++
++	}
++	return n, nil
++}
++
++func (sa *RawSockaddrUnix) adjustAbstract(sl Socklen_t) Socklen_t {
++	return sl
++}
++
++type RawSockaddr struct {
++	Len    uint8
++	Family uint8
++	Data   [14]int8
++}
++
++// BindToDevice binds the socket associated with fd to device.
++func BindToDevice(fd int, device string) (err error) {
++	return ENOSYS
++}
++
++func anyToSockaddrOS(rsa *RawSockaddrAny) (Sockaddr, error) {
++	return nil, EAFNOSUPPORT
++}
++
++func GetsockoptIPv6MTUInfo(fd, level, opt int) (*IPv6MTUInfo, error) {
++	var value IPv6MTUInfo
++	vallen := Socklen_t(SizeofIPv6MTUInfo)
++	err := getsockopt(fd, level, opt, unsafe.Pointer(&value), &vallen)
++	return &value, err
++}
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_go_syscall_syscall_gnu_test.go.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_go_syscall_syscall_gnu_test.go.diff
@@ -0,0 +1,361 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/syscall_gnu_test.go
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/syscall_gnu_test.go
+@@ -0,0 +1,356 @@
++// Copyright 2013 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++// +build gnu
++
++package syscall_test
++
++import (
++	"flag"
++	"fmt"
++	"internal/testenv"
++	"io/ioutil"
++	"net"
++	"os"
++	"os/exec"
++	"path/filepath"
++	"runtime"
++	"syscall"
++	"testing"
++	"time"
++)
++
++// Tests that below functions, structures and constants are consistent
++// on all Unix-like systems.
++func _() {
++	// program scheduling priority functions and constants
++	var (
++		_ func(int, int, int) error   = syscall.Setpriority
++		_ func(int, int) (int, error) = syscall.Getpriority
++	)
++	const (
++		_ int = syscall.PRIO_USER
++		_ int = syscall.PRIO_PROCESS
++		_ int = syscall.PRIO_PGRP
++	)
++
++	// termios constants
++	const (
++		_ int = syscall.TCIFLUSH
++		_ int = syscall.TCIOFLUSH
++		_ int = syscall.TCOFLUSH
++	)
++
++	// fcntl file locking structure and constants
++	var (
++		_ = syscall.Flock_t{
++			Type:   int32(0),
++			Whence: int32(0),
++			Start:  int64(0),
++			Len:    int64(0),
++			Pid:    int32(0),
++		}
++	)
++	const (
++		_ = syscall.F_GETLK
++		_ = syscall.F_SETLK
++		_ = syscall.F_SETLKW
++	)
++}
++
++// TestFcntlFlock tests whether the file locking structure matches
++// the calling convention of each kernel.
++// On some Linux systems, glibc uses another set of values for the
++// commands and translates them to the correct value that the kernel
++// expects just before the actual fcntl syscall. As Go uses raw
++// syscalls directly, it must use the real value, not the glibc value.
++// Thus this test also verifies that the Flock_t structure can be
++// roundtripped with F_SETLK and F_GETLK.
++func TestFcntlFlock(t *testing.T) {
++	if runtime.GOOS == "darwin" && (runtime.GOARCH == "arm" || runtime.GOARCH == "arm64") {
++		t.Skip("skipping; no child processes allowed on iOS")
++	}
++	flock := syscall.Flock_t{
++		Type:  syscall.F_WRLCK,
++		Start: 31415, Len: 271828, Whence: 1,
++	}
++	if os.Getenv("GO_WANT_HELPER_PROCESS") == "" {
++		// parent
++		name := filepath.Join(os.TempDir(), "TestFcntlFlock")
++		fd, err := syscall.Open(name, syscall.O_CREAT|syscall.O_RDWR|syscall.O_CLOEXEC, 0)
++		if err != nil {
++			t.Fatalf("Open failed: %v", err)
++		}
++		defer syscall.Unlink(name)
++		defer syscall.Close(fd)
++		if err := syscall.Ftruncate(fd, 1<<20); err != nil {
++			t.Fatalf("Ftruncate(1<<20) failed: %v", err)
++		}
++		if err := syscall.FcntlFlock(uintptr(fd), syscall.F_SETLK, &flock); err != nil {
++			t.Fatalf("FcntlFlock(F_SETLK) failed: %v", err)
++		}
++		cmd := exec.Command(os.Args[0], "-test.run=^TestFcntlFlock$")
++		cmd.Env = append(os.Environ(), "GO_WANT_HELPER_PROCESS=1")
++		cmd.ExtraFiles = []*os.File{os.NewFile(uintptr(fd), name)}
++		out, err := cmd.CombinedOutput()
++		if len(out) > 0 || err != nil {
++			t.Fatalf("child process: %q, %v", out, err)
++		}
++	} else {
++		// child
++		got := flock
++		// make sure the child lock is conflicting with the parent lock
++		got.Start--
++		got.Len++
++		if err := syscall.FcntlFlock(3, syscall.F_GETLK, &got); err != nil {
++			t.Fatalf("FcntlFlock(F_GETLK) failed: %v", err)
++		}
++		flock.Pid = int32(syscall.Getppid())
++		// Linux kernel always set Whence to 0
++		flock.Whence = 0
++		if got.Type == flock.Type && got.Start == flock.Start && got.Len == flock.Len && got.Pid == flock.Pid && got.Whence == flock.Whence {
++			os.Exit(0)
++		}
++		t.Fatalf("FcntlFlock got %v, want %v", got, flock)
++	}
++}
++
++// TestPassFD tests passing a file descriptor over a Unix socket.
++//
++// This test involved both a parent and child process. The parent
++// process is invoked as a normal test, with "go test", which then
++// runs the child process by running the current test binary with args
++// "-test.run=^TestPassFD$" and an environment variable used to signal
++// that the test should become the child process instead.
++func TestPassFD(t *testing.T) {
++	switch runtime.GOOS {
++	case "dragonfly":
++		// TODO(jsing): Figure out why sendmsg is returning EINVAL.
++		t.Skip("skipping test on dragonfly")
++	case "solaris":
++		// TODO(aram): Figure out why ReadMsgUnix is returning empty message.
++		t.Skip("skipping test on solaris, see issue 7402")
++	}
++
++	testenv.MustHaveExec(t)
++
++	if os.Getenv("GO_WANT_HELPER_PROCESS") == "1" {
++		passFDChild()
++		return
++	}
++
++	tempDir, err := ioutil.TempDir("", "TestPassFD")
++	if err != nil {
++		t.Fatal(err)
++	}
++	defer os.RemoveAll(tempDir)
++
++	fds, err := syscall.Socketpair(syscall.AF_LOCAL, syscall.SOCK_STREAM, 0)
++	if err != nil {
++		t.Fatalf("Socketpair: %v", err)
++	}
++	defer syscall.Close(fds[0])
++	defer syscall.Close(fds[1])
++	writeFile := os.NewFile(uintptr(fds[0]), "child-writes")
++	readFile := os.NewFile(uintptr(fds[1]), "parent-reads")
++	defer writeFile.Close()
++	defer readFile.Close()
++
++	cmd := exec.Command(os.Args[0], "-test.run=^TestPassFD$", "--", tempDir)
++	cmd.Env = append(os.Environ(), "GO_WANT_HELPER_PROCESS=1")
++	cmd.ExtraFiles = []*os.File{writeFile}
++
++	out, err := cmd.CombinedOutput()
++	if len(out) > 0 || err != nil {
++		t.Fatalf("child process: %q, %v", out, err)
++	}
++
++	c, err := net.FileConn(readFile)
++	if err != nil {
++		t.Fatalf("FileConn: %v", err)
++	}
++	defer c.Close()
++
++	uc, ok := c.(*net.UnixConn)
++	if !ok {
++		t.Fatalf("unexpected FileConn type; expected UnixConn, got %T", c)
++	}
++
++	buf := make([]byte, 32) // expect 1 byte
++	oob := make([]byte, 32) // expect 24 bytes
++	closeUnix := time.AfterFunc(5*time.Second, func() {
++		t.Logf("timeout reading from unix socket")
++		uc.Close()
++	})
++	_, oobn, _, _, err := uc.ReadMsgUnix(buf, oob)
++	closeUnix.Stop()
++
++	scms, err := syscall.ParseSocketControlMessage(oob[:oobn])
++	if err != nil {
++		t.Fatalf("ParseSocketControlMessage: %v", err)
++	}
++	if len(scms) != 1 {
++		t.Fatalf("expected 1 SocketControlMessage; got scms = %#v", scms)
++	}
++	scm := scms[0]
++	gotFds, err := syscall.ParseUnixRights(&scm)
++	if err != nil {
++		t.Fatalf("syscall.ParseUnixRights: %v", err)
++	}
++	if len(gotFds) != 1 {
++		t.Fatalf("wanted 1 fd; got %#v", gotFds)
++	}
++
++	f := os.NewFile(uintptr(gotFds[0]), "fd-from-child")
++	defer f.Close()
++
++	got, err := ioutil.ReadAll(f)
++	want := "Hello from child process!\n"
++	if string(got) != want {
++		t.Errorf("child process ReadAll: %q, %v; want %q", got, err, want)
++	}
++}
++
++// passFDChild is the child process used by TestPassFD.
++func passFDChild() {
++	defer os.Exit(0)
++
++	// Look for our fd. It should be fd 3, but we work around an fd leak
++	// bug here (https://golang.org/issue/2603) to let it be elsewhere.
++	var uc *net.UnixConn
++	for fd := uintptr(3); fd <= 10; fd++ {
++		f := os.NewFile(fd, "unix-conn")
++		var ok bool
++		netc, _ := net.FileConn(f)
++		uc, ok = netc.(*net.UnixConn)
++		if ok {
++			break
++		}
++	}
++	if uc == nil {
++		fmt.Println("failed to find unix fd")
++		return
++	}
++
++	// Make a file f to send to our parent process on uc.
++	// We make it in tempDir, which our parent will clean up.
++	flag.Parse()
++	tempDir := flag.Arg(0)
++	f, err := ioutil.TempFile(tempDir, "")
++	if err != nil {
++		fmt.Printf("TempFile: %v", err)
++		return
++	}
++
++	f.Write([]byte("Hello from child process!\n"))
++	f.Seek(0, 0)
++
++	rights := syscall.UnixRights(int(f.Fd()))
++	dummyByte := []byte("x")
++	n, oobn, err := uc.WriteMsgUnix(dummyByte, rights, nil)
++	if err != nil {
++		fmt.Printf("WriteMsgUnix: %v", err)
++		return
++	}
++	if n != 1 || oobn != len(rights) {
++		fmt.Printf("WriteMsgUnix = %d, %d; want 1, %d", n, oobn, len(rights))
++		return
++	}
++}
++
++// TestUnixRightsRoundtrip tests that UnixRights, ParseSocketControlMessage,
++// and ParseUnixRights are able to successfully round-trip lists of file descriptors.
++func TestUnixRightsRoundtrip(t *testing.T) {
++	testCases := [...][][]int{
++		{{42}},
++		{{1, 2}},
++		{{3, 4, 5}},
++		{{}},
++		{{1, 2}, {3, 4, 5}, {}, {7}},
++	}
++	for _, testCase := range testCases {
++		b := []byte{}
++		var n int
++		for _, fds := range testCase {
++			// Last assignment to n wins
++			n = len(b) + syscall.CmsgLen(4*len(fds))
++			b = append(b, syscall.UnixRights(fds...)...)
++		}
++		// Truncate b
++		b = b[:n]
++
++		scms, err := syscall.ParseSocketControlMessage(b)
++		if err != nil {
++			t.Fatalf("ParseSocketControlMessage: %v", err)
++		}
++		if len(scms) != len(testCase) {
++			t.Fatalf("expected %v SocketControlMessage; got scms = %#v", len(testCase), scms)
++		}
++		for i, scm := range scms {
++			gotFds, err := syscall.ParseUnixRights(&scm)
++			if err != nil {
++				t.Fatalf("ParseUnixRights: %v", err)
++			}
++			wantFds := testCase[i]
++			if len(gotFds) != len(wantFds) {
++				t.Fatalf("expected %v fds, got %#v", len(wantFds), gotFds)
++			}
++			for j, fd := range gotFds {
++				if fd != wantFds[j] {
++					t.Fatalf("expected fd %v, got %v", wantFds[j], fd)
++				}
++			}
++		}
++	}
++}
++
++func TestRlimit(t *testing.T) {
++	var rlimit, zero syscall.Rlimit
++	err := syscall.Getrlimit(syscall.RLIMIT_NOFILE, &rlimit)
++	if err != nil {
++		t.Fatalf("Getrlimit: save failed: %v", err)
++	}
++	if zero == rlimit {
++		t.Fatalf("Getrlimit: save failed: got zero value %#v", rlimit)
++	}
++	set := rlimit
++	set.Cur = set.Max - 1
++	err = syscall.Setrlimit(syscall.RLIMIT_NOFILE, &set)
++	if err != nil {
++		t.Fatalf("Setrlimit: set failed: %#v %v", set, err)
++	}
++	var get syscall.Rlimit
++	err = syscall.Getrlimit(syscall.RLIMIT_NOFILE, &get)
++	if err != nil {
++		t.Fatalf("Getrlimit: get failed: %v", err)
++	}
++	set = rlimit
++	set.Cur = set.Max - 1
++	if set != get {
++		// Seems like Darwin requires some privilege to
++		// increase the soft limit of rlimit sandbox, though
++		// Setrlimit never reports an error.
++		switch runtime.GOOS {
++		case "darwin":
++		default:
++			t.Fatalf("Rlimit: change failed: wanted %#v got %#v", set, get)
++		}
++	}
++	err = syscall.Setrlimit(syscall.RLIMIT_NOFILE, &rlimit)
++	if err != nil {
++		t.Fatalf("Setrlimit: restore failed: %#v %v", rlimit, err)
++	}
++}
++
++func TestSeekFailure(t *testing.T) {
++	_, err := syscall.Seek(-1, 0, 0)
++	if err == nil {
++		t.Fatalf("Seek(-1, 0, 0) did not fail")
++	}
++	str := err.Error() // used to crash on Linux
++	t.Logf("Seek: %v", str)
++	if str == "" {
++		t.Fatalf("Seek(-1, 0, 0) return error with empty message")
++	}
++}
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_go_syscall_wait.c.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_go_syscall_wait.c.diff
@@ -0,0 +1,14 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/go/syscall/wait.c
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/go/syscall/wait.c
++++ gcc-6-6.2.1-4.1/src/libgo/go/syscall/wait.c
+@@ -8,6 +8,9 @@
+    OS-independent.  */
+ 
+ #include <stdint.h>
++#ifndef WCONTINUED
++#define WCONTINUED 0
++#endif
+ #include <sys/wait.h>
+ 
+ #include "runtime.h"
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_mksysinfo.sh.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_mksysinfo.sh.diff
@@ -0,0 +1,42 @@
+Index: gcc-6-6.4.0/src/libgo/mksysinfo.sh
+===================================================================
+--- gcc-6-6.4.0.orig/src/libgo/mksysinfo.sh
++++ gcc-6-6.4.0/src/libgo/mksysinfo.sh
+@@ -304,6 +304,13 @@ echo '#include <errno.h>' | ${CC} -x c -
+   egrep '#define E[A-Z0-9_]+ ' | \
+   sed -e 's/^#define \(E[A-Z0-9_]*\) .*$/const \1 = Errno(_\1)/' >> ${OUT}
+ 
++# Special treatment of EWOULDBLOCK for GNU/Hurd
++# /usr/include/bits/errno.h: #define EWOULDBLOCK EAGAIN
++if egrep 'define EWOULDBLOCK EAGAIN' gen-sysinfo.go > /dev/null 2>&1; then
++  egrep '^const EWOULDBLOCK = Errno(_EWOULDBLOCK)' ${OUT} | \
++    sed -i -e 's/_EWOULDBLOCK/_EAGAIN/' ${OUT}
++fi
++
+ # The O_xxx flags.
+ egrep '^const _(O|F|FD)_' gen-sysinfo.go | \
+   sed -e 's/^\(const \)_\([^= ]*\)\(.*\)$/\1\2 = _\2/' >> ${OUT}
+@@ -362,6 +369,11 @@ grep '^const _SYS_' gen-sysinfo.go | \
+     echo "const $sup = _$sys" >> ${OUT}
+   done
+ 
++# Special treatment of SYS_IOCTL for GNU/Hurd
++if ! grep '^const SYS_IOCTL' ${OUT} > /dev/null 2>&1; then
++  echo "const SYS_IOCTL = 0" >> ${OUT}
++fi
++
+ # The GNU/Linux support wants to use SYS_GETDENTS64 if available.
+ if ! grep '^const SYS_GETDENTS ' ${OUT} >/dev/null 2>&1; then
+   echo "const SYS_GETDENTS = 0" >> ${OUT}
+@@ -676,6 +688,11 @@ grep '^type _tms ' gen-sysinfo.go | \
+ 
+ # The stat type.
+ # Prefer largefile variant if available.
++# Special treatment of st_dev for GNU/Hurd
++# /usr/include/i386-gnu/bits/stat.h: #define st_dev st_fsid
++if grep 'define st_dev st_fsid' gen-sysinfo.go > /dev/null 2>&1; then
++  sed -i -e 's/; st_fsid/; st_dev/' gen-sysinfo.go
++fi
+ stat=`grep '^type _stat64 ' gen-sysinfo.go || true`
+ if test "$stat" != ""; then
+   grep '^type _stat64 ' gen-sysinfo.go
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_runtime_getncpu-gnu.c.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_runtime_getncpu-gnu.c.diff
@@ -0,0 +1,21 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/runtime/getncpu-gnu.c
+===================================================================
+--- /dev/null
++++ gcc-6-6.2.1-4.1/src/libgo/runtime/getncpu-gnu.c
+@@ -0,0 +1,16 @@
++// Copyright 2012 The Go Authors. All rights reserved.
++// Use of this source code is governed by a BSD-style
++// license that can be found in the LICENSE file.
++
++#include <unistd.h>
++
++#include "runtime.h"
++#include "defs.h"
++
++int32
++getproccount(void)
++{
++	int32 n;
++	n = (int32)sysconf(_SC_NPROCESSORS_ONLN);
++	return n > 1 ? n : 1;
++}
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_runtime_go-caller.c.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_runtime_go-caller.c.diff
@@ -0,0 +1,14 @@
+Index: gcc/src/libgo/runtime/go-caller.c
+===================================================================
+--- gcc/src/libgo/runtime/go-caller.c	(révision 235086)
++++ gcc/src/libgo/runtime/go-caller.c	(copie de travail)
+@@ -93,7 +93,7 @@
+ 	 argv[0] (http://gcc.gnu.org/PR61895).  It would be nice to
+ 	 have a better check for whether this file is the real
+ 	 executable.  */
+-      if (stat (filename, &s) < 0 || s.st_size < 1024)
++      if (filename != NULL && (stat (filename, &s) < 0 || s.st_size < 1024))
+ 	filename = NULL;
+ 
+       back_state = backtrace_create_state (filename, 1, error_callback, NULL);
+
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_runtime_netpoll.goc.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_runtime_netpoll.goc.diff
@@ -0,0 +1,31 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/runtime/netpoll.goc
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/runtime/netpoll.goc
++++ gcc-6-6.2.1-4.1/src/libgo/runtime/netpoll.goc
+@@ -2,7 +2,7 @@
+ // Use of this source code is governed by a BSD-style
+ // license that can be found in the LICENSE file.
+ 
+-// +build darwin dragonfly freebsd linux nacl netbsd openbsd solaris windows
++// +build darwin dragonfly freebsd gnu linux nacl netbsd openbsd solaris windows
+ 
+ package net
+ 
+@@ -98,7 +98,7 @@ func runtime_pollServerInit() {
+ 	runtime_netpollinit();
+ }
+ 
+-func runtime_pollOpen(fd uintptr) (pd *PollDesc, errno int) {
++func runtime_pollOpen(fd uintptr) (pd *PollDesc, errno1 int) {
+ 	pd = allocPollDesc();
+ 	runtime_lock(pd);
+ 	if(pd->wg != nil && pd->wg != READY)
+@@ -114,7 +114,7 @@ func runtime_pollOpen(fd uintptr) (pd *P
+ 	pd->wd = 0;
+ 	runtime_unlock(pd);
+ 
+-	errno = runtime_netpollopen(fd, pd);
++	errno1 = runtime_netpollopen(fd, pd);
+ }
+ 
+ func runtime_pollClose(pd *PollDesc) {
--- gcc-6-6.4.0.orig/debian/patches/src_libgo_testsuite_gotest.diff
+++ gcc-6-6.4.0/debian/patches/src_libgo_testsuite_gotest.diff
@@ -0,0 +1,17 @@
+Index: gcc-6-6.2.1-4.1/src/libgo/testsuite/gotest
+===================================================================
+--- gcc-6-6.2.1-4.1.orig/src/libgo/testsuite/gotest
++++ gcc-6-6.2.1-4.1/src/libgo/testsuite/gotest
+@@ -618,7 +618,11 @@ xno)
+ 		wait $pid
+ 		status=$?
+ 		if ! test -f gotest-timeout; then
+-		    sleeppid=`ps -o pid,ppid,comm | grep " $alarmpid " | grep sleep | sed -e 's/ *\([0-9]*\) .*$/\1/'`
++		    if test "$goos" = "gnu"; then
++			sleeppid=`ps -o pid,ppid | grep " $alarmpid " | grep sleep | sed -e 's/ *\([0-9]*\) .*$/\1/'`
++		    else
++			sleeppid=`ps -o pid,ppid,comm | grep " $alarmpid " | grep sleep | sed -e 's/ *\([0-9]*\) .*$/\1/'`
++		    fi
+ 		    kill $alarmpid
+ 		    wait $alarmpid
+ 		    if test "$sleeppid" != ""; then
--- gcc-6-6.4.0.orig/debian/patches/svn-class-updates.diff
+++ gcc-6-6.4.0/debian/patches/svn-class-updates.diff
@@ -0,0 +1,27 @@
+# DP: updated class files from the 4.8 branch upto yyyymmdd.
+
+dir=gcc-4_8-branch
+dir=/scratch/packages/gcc/svn/gcc-4_8-branch
+tag=gcc_4_8_0_release
+branch=gcc-4_8-branch
+
+tmplist=files$$
+
+svn diff --summarize \
+        svn://gcc.gnu.org/svn/gcc/tags/$tag \
+        svn://gcc.gnu.org/svn/gcc/branches/$branch \
+    | grep '\.class$' > $tmplist
+
+sed -n '/^[AM].*\.class$/s,.*/'$tag'/\(.*\),\1,p' $tmplist \
+    > neworchanged.list
+sed -n '/^[D].*\.class$/s,.*/'$tag'/\(.*\),\1,p' $tmplist \
+    > removed.list
+sed -n '/^[^ADM].*\.class$/s,.*/'$tag'/\(.*\),\1,p' $tmplist \
+    > unknown.list
+
+echo "new or changed: $(wc -l neworchanged.list | cut '-d ' -f1), removed $(wc -l removed.list | cut '-d ' -f1): , unknown: $(wc -l unknown.list | cut '-d ' -f1)"
+tar -c -J -f java-class-files.tar.xz -C $dir -T neworchanged.list
+uuencode java-class-files.tar.xz java-class-files.tar.xz > java-class-files.tar.xz.uue
+
+rm -f $tmplist neworchanged.list removed.list unknown.list
+
--- gcc-6-6.4.0.orig/debian/patches/svn-doc-updates.diff
+++ gcc-6-6.4.0/debian/patches/svn-doc-updates.diff
@@ -0,0 +1,6 @@
+# DP: updates from the 6 branch upto 20170406 (documentation).
+
+svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_6_4_0_release svn://gcc.gnu.org/svn/gcc/branches/gcc-6-branch \
+	| sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \
+	| awk '/^Index:.*\.texi/ {skip=0; print; next} /^Index:/ {skip=1; next} skip==0'
+
--- gcc-6-6.4.0.orig/debian/patches/svn-updates.diff
+++ gcc-6-6.4.0/debian/patches/svn-updates.diff
@@ -0,0 +1,27372 @@
+# DP: updates from the 6 branch upto 20180312 (r258446).
+
+last_update()
+{
+	cat > ${dir}LAST_UPDATED <EOF
+Mon Mar 12 13:39:37 CET 2018
+Mon Mar 12 12:39:37 UTC 2018 (revision 258446)
+EOF
+}
+
+LANG=C svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_6_4_0_release svn://gcc.gnu.org/svn/gcc/branches/gcc-6-branch \
+	| sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \
+	| awk '/^Index:.*\.(class|texi)/ {skip=1; next} /^Index:/ { skip=0 } skip==0'
+
+Index: libgomp/ChangeLog
+===================================================================
+--- a/src/libgomp/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/libgomp/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,31 @@
++2017-12-10  Tom de Vries  <tom@codesourcery.com>
++
++	backport from trunk:
++	PR c/81875
++	2017-09-16  Tom de Vries  <tom@codesourcery.com>
++
++	* testsuite/libgomp.c/pr81875.c: New test.
++
++2017-09-15  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-09-14  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c++/81314
++	* testsuite/libgomp.c++/pr81314.C: New test.
++
++	2017-08-09  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c/81687
++	* testsuite/libgomp.c/pr81687-1.c: New test.
++	* testsuite/libgomp.c/pr81687-2.c: New test.
++
++	2017-07-27  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c/45784
++	* testsuite/libgomp.c/pr45784.c: New test.
++	* testsuite/libgomp.c++/pr45784.C: New test.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: libgomp/testsuite/libgomp.c++/pr81314.C
+===================================================================
+--- a/src/libgomp/testsuite/libgomp.c++/pr81314.C	(.../tags/gcc_6_4_0_release)
++++ b/src/libgomp/testsuite/libgomp.c++/pr81314.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,38 @@
++// PR c++/81314
++// { dg-do link }
++
++template <int N>
++struct S {
++  S () { s = 0; }
++  S (const S &x) { s = x.s; }
++  ~S () {}
++  int s;
++};
++
++void
++foo (S<2> &x)
++{
++  #pragma omp taskloop
++  for (int i = 0; i < 100; ++i)
++    x.s++;
++}
++
++void
++bar (S<3> &x)
++{
++  #pragma omp task
++  x.s++;
++}
++
++int
++main ()
++{
++  S<2> s;
++  S<3> t;
++  #pragma omp parallel
++  #pragma omp master
++  {
++    foo (s);
++    bar (t);
++  }
++}
+Index: libgomp/testsuite/libgomp.c++/pr45784.C
+===================================================================
+--- a/src/libgomp/testsuite/libgomp.c++/pr45784.C	(.../tags/gcc_6_4_0_release)
++++ b/src/libgomp/testsuite/libgomp.c++/pr45784.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,5 @@
++// PR c/45784
++// { dg-do run }
++
++#include "../libgomp.c/pr45784.c"
++
+Index: libgomp/testsuite/libgomp.c/pr81687-2.c
+===================================================================
+--- a/src/libgomp/testsuite/libgomp.c/pr81687-2.c	(.../tags/gcc_6_4_0_release)
++++ b/src/libgomp/testsuite/libgomp.c/pr81687-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,27 @@
++/* PR c/81687 */
++/* { dg-do link } */
++/* { dg-additional-options "-O2" } */
++
++int
++main ()
++{
++  __label__ lab4, lab5, lab6;
++  volatile int l = 0;
++  int m = l;
++  void foo (int x) { if (x == 1) goto lab4; }
++  void bar (int x) { if (x == 2) goto lab5; }
++  void baz (int x) { if (x == 3) goto lab6; }
++  #pragma omp parallel
++  {
++    foo (m + 1);
++   lab4:;
++  }
++  #pragma omp task
++  {
++    bar (m + 2);
++   lab5:;
++  }
++  baz (m + 3);
++ lab6:;
++  return 0;
++}
+Index: libgomp/testsuite/libgomp.c/pr81875.c
+===================================================================
+--- a/src/libgomp/testsuite/libgomp.c/pr81875.c	(.../tags/gcc_6_4_0_release)
++++ b/src/libgomp/testsuite/libgomp.c/pr81875.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,46 @@
++/* { dg-do run } */
++
++extern
++#ifdef __cplusplus
++"C"
++#endif
++void abort (void);
++
++#define N 32ULL
++int a[N];
++
++const unsigned long long c = 0x7fffffffffffffffULL;
++
++void
++f2_tpf_static32 (void)
++{
++  unsigned long long i;
++  #pragma omp for
++  for (i = c + N; i > c; i -= 1ULL)
++    a[i - 1ULL - c] -= 4;
++}
++
++__attribute__((noinline, noclone)) int
++test_tpf_static32 (void)
++{
++  int i, j, k;
++  for (i = 0; i < N; i++)
++    a[i] = i - 25;
++
++  f2_tpf_static32 ();
++
++  for (i = 0; i < N; i++)
++    if (a[i] != i - 29)
++      return 1;
++
++  return 0;
++}
++
++int
++main ()
++{
++  if (test_tpf_static32 ())
++    abort ();
++
++  return 0;
++}
+Index: libgomp/testsuite/libgomp.c/pr45784.c
+===================================================================
+--- a/src/libgomp/testsuite/libgomp.c/pr45784.c	(.../tags/gcc_6_4_0_release)
++++ b/src/libgomp/testsuite/libgomp.c/pr45784.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,41 @@
++/* PR c/45784 */
++/* { dg-do run } */
++
++void
++foo (int n)
++{
++  char *p, vla[2 * n];
++  int i;
++  #pragma omp parallel for
++  for (p = vla; p < vla + (sizeof (vla) / sizeof (vla[0])); p++)
++    *p = ' ';
++  #pragma omp parallel for
++  for (i = 0; i < 2 * n; i++)
++    if (vla[i] != ' ')
++      __builtin_abort ();
++}
++
++void
++bar (int n)
++{
++  char *p, vla1[n], vla2[n * 2], vla3[n * 3], vla4[n * 4];
++  int i;
++  __builtin_memset (vla4, ' ', n * 4);
++  #pragma omp parallel for
++  for (p = vla4 + sizeof (vla1); p < vla4 + sizeof (vla3) - sizeof (vla2) + sizeof (vla1); p += sizeof (vla4) / sizeof (vla4))
++    p[0] = '!';
++  #pragma omp parallel for
++  for (i = 0; i < n * 4; i++)
++    if (vla4[i] != ((i >= n && i < 2 * n) ? '!' : ' '))
++      __builtin_abort ();
++}
++
++int
++main ()
++{
++  volatile int n;
++  n = 128;
++  foo (n);
++  bar (n);
++  return 0;
++}
+Index: libgomp/testsuite/libgomp.c/pr81687-1.c
+===================================================================
+--- a/src/libgomp/testsuite/libgomp.c/pr81687-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/libgomp/testsuite/libgomp.c/pr81687-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,23 @@
++/* PR c/81687 */
++/* { dg-do link } */
++/* { dg-additional-options "-O2" } */
++
++extern int printf (const char *, ...);
++
++int
++main ()
++{
++  #pragma omp parallel
++  {
++   lab1:
++    printf ("lab1=%p\n", (void *)(&&lab1));
++  }
++ lab2:
++  #pragma omp parallel
++  {
++   lab3:
++    printf ("lab2=%p\n", (void *)(&&lab2));
++  }
++  printf ("lab3=%p\n", (void *)(&&lab3));
++  return 0;
++}
+Index: libquadmath/ChangeLog
+===================================================================
+--- a/src/libquadmath/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/libquadmath/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,8 @@
++2017-09-15  Jakub Jelinek  <jakub@redhat.com>
++
++	PR libquadmath/65757
++	* math/roundq.c: Cherry-pick upstream glibc 2015-04-28 change.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: libquadmath/math/roundq.c
+===================================================================
+--- a/src/libquadmath/math/roundq.c	(.../tags/gcc_6_4_0_release)
++++ b/src/libquadmath/math/roundq.c	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ /* Round __float128 to integer away from zero.
+-   Copyright (C) 1997, 1999 Free Software Foundation, Inc.
++   Copyright (C) 1997-2017 Free Software Foundation, Inc.
+    This file is part of the GNU C Library.
+    Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997 and
+ 		  Jakub Jelinek <jj@ultra.linux.cz>, 1999.
+@@ -32,7 +32,7 @@
+ 
+   GET_FLT128_WORDS64 (i0, i1, x);
+   j0 = ((i0 >> 48) & 0x7fff) - 0x3fff;
+-  if (j0 < 31)
++  if (j0 < 48)
+     {
+       if (j0 < 0)
+ 	{
+Index: libsanitizer/sanitizer_common/sanitizer_linux.cc
+===================================================================
+--- a/src/libsanitizer/sanitizer_common/sanitizer_linux.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libsanitizer/sanitizer_common/sanitizer_linux.cc	(.../branches/gcc-6-branch)
+@@ -546,8 +546,7 @@
+ }
+ #endif
+ 
+-uptr internal_sigaltstack(const struct sigaltstack *ss,
+-                         struct sigaltstack *oss) {
++uptr internal_sigaltstack(const void *ss, void *oss) {
+   return internal_syscall(SYSCALL(sigaltstack), (uptr)ss, (uptr)oss);
+ }
+ 
+Index: libsanitizer/sanitizer_common/sanitizer_linux.h
+===================================================================
+--- a/src/libsanitizer/sanitizer_common/sanitizer_linux.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libsanitizer/sanitizer_common/sanitizer_linux.h	(.../branches/gcc-6-branch)
+@@ -19,7 +19,6 @@
+ #include "sanitizer_platform_limits_posix.h"
+ 
+ struct link_map;  // Opaque type returned by dlopen().
+-struct sigaltstack;
+ 
+ namespace __sanitizer {
+ // Dirent structure for getdents(). Note that this structure is different from
+@@ -28,8 +27,7 @@
+ 
+ // Syscall wrappers.
+ uptr internal_getdents(fd_t fd, struct linux_dirent *dirp, unsigned int count);
+-uptr internal_sigaltstack(const struct sigaltstack* ss,
+-                          struct sigaltstack* oss);
++uptr internal_sigaltstack(const void* ss, void* oss);
+ uptr internal_sigprocmask(int how, __sanitizer_sigset_t *set,
+     __sanitizer_sigset_t *oldset);
+ void internal_sigfillset(__sanitizer_sigset_t *set);
+Index: libsanitizer/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc
+===================================================================
+--- a/src/libsanitizer/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libsanitizer/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc	(.../branches/gcc-6-branch)
+@@ -267,7 +267,7 @@
+ 
+   // Alternate stack for signal handling.
+   InternalScopedBuffer<char> handler_stack_memory(kHandlerStackSize);
+-  struct sigaltstack handler_stack;
++  stack_t handler_stack;
+   internal_memset(&handler_stack, 0, sizeof(handler_stack));
+   handler_stack.ss_sp = handler_stack_memory.data();
+   handler_stack.ss_size = kHandlerStackSize;
+Index: libsanitizer/ChangeLog
+===================================================================
+--- a/src/libsanitizer/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/libsanitizer/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,14 @@
++2017-09-07  Matthias Klose  <doko@ubuntu.com>
++
++	Backported from mainline
++	2017-07-14  Jakub Jelinek  <jakub@redhat.com>
++
++	PR sanitizer/81066
++	* sanitizer_common/sanitizer_linux.h: Cherry-pick upstream r307969.
++	* sanitizer_common/sanitizer_linux.cc: Likewise.
++	* sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc: Likewise.
++	* tsan/tsan_platform_linux.cc: Likewise.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: libsanitizer/tsan/tsan_platform_linux.cc
+===================================================================
+--- a/src/libsanitizer/tsan/tsan_platform_linux.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libsanitizer/tsan/tsan_platform_linux.cc	(.../branches/gcc-6-branch)
+@@ -291,7 +291,7 @@
+ int ExtractResolvFDs(void *state, int *fds, int nfd) {
+ #if SANITIZER_LINUX
+   int cnt = 0;
+-  __res_state *statp = (__res_state*)state;
++  struct __res_state *statp = (struct __res_state*)state;
+   for (int i = 0; i < MAXNS && cnt < nfd; i++) {
+     if (statp->_u._ext.nsaddrs[i] && statp->_u._ext.nssocks[i] != -1)
+       fds[cnt++] = statp->_u._ext.nssocks[i];
+Index: libstdc++-v3/configure
+===================================================================
+--- a/src/libstdc++-v3/configure	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/configure	(.../branches/gcc-6-branch)
+@@ -619,6 +619,8 @@
+ ATOMIC_FLAGS
+ ATOMIC_WORD_SRCDIR
+ ATOMICITY_SRCDIR
++INCLUDE_DIR_NOTPARALLEL_FALSE
++INCLUDE_DIR_NOTPARALLEL_TRUE
+ BUILD_PDF_FALSE
+ BUILD_PDF_TRUE
+ PDFLATEX
+@@ -11596,7 +11598,7 @@
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 11599 "configure"
++#line 11601 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+@@ -11702,7 +11704,7 @@
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 11705 "configure"
++#line 11707 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+@@ -15388,7 +15390,7 @@
+   # Fake what AC_TRY_COMPILE does.
+ 
+     cat > conftest.$ac_ext << EOF
+-#line 15391 "configure"
++#line 15393 "configure"
+ int main()
+ {
+   typedef bool atomic_type;
+@@ -15423,7 +15425,7 @@
+     rm -f conftest*
+ 
+     cat > conftest.$ac_ext << EOF
+-#line 15426 "configure"
++#line 15428 "configure"
+ int main()
+ {
+   typedef short atomic_type;
+@@ -15458,7 +15460,7 @@
+     rm -f conftest*
+ 
+     cat > conftest.$ac_ext << EOF
+-#line 15461 "configure"
++#line 15463 "configure"
+ int main()
+ {
+   // NB: _Atomic_word not necessarily int.
+@@ -15494,7 +15496,7 @@
+     rm -f conftest*
+ 
+     cat > conftest.$ac_ext << EOF
+-#line 15497 "configure"
++#line 15499 "configure"
+ int main()
+ {
+   typedef long long atomic_type;
+@@ -15575,7 +15577,7 @@
+   # unnecessary for this test.
+ 
+     cat > conftest.$ac_ext << EOF
+-#line 15578 "configure"
++#line 15580 "configure"
+ int main()
+ {
+   _Decimal32 d1;
+@@ -15617,7 +15619,7 @@
+   # unnecessary for this test.
+ 
+     cat > conftest.$ac_ext << EOF
+-#line 15620 "configure"
++#line 15622 "configure"
+ template<typename T1, typename T2>
+   struct same
+   { typedef T2 type; };
+@@ -15651,7 +15653,7 @@
+     rm -f conftest*
+ 
+     cat > conftest.$ac_ext << EOF
+-#line 15654 "configure"
++#line 15656 "configure"
+ template<typename T1, typename T2>
+   struct same
+   { typedef T2 type; };
+@@ -81017,7 +81019,19 @@
+ fi
+ 
+ 
++case "$build" in
++ *-*-darwin* ) glibcxx_include_dir_notparallel=yes ;;
++ * ) glibcxx_include_dir_notparallel=no ;;
++esac
++ if test $glibcxx_include_dir_notparallel = "yes"; then
++  INCLUDE_DIR_NOTPARALLEL_TRUE=
++  INCLUDE_DIR_NOTPARALLEL_FALSE='#'
++else
++  INCLUDE_DIR_NOTPARALLEL_TRUE='#'
++  INCLUDE_DIR_NOTPARALLEL_FALSE=
++fi
+ 
++
+ # Propagate the target-specific source directories through the build chain.
+ ATOMICITY_SRCDIR=config/${atomicity_dir}
+ ATOMIC_WORD_SRCDIR=config/${atomic_word_dir}
+@@ -81696,6 +81710,10 @@
+   as_fn_error "conditional \"BUILD_PDF\" was never defined.
+ Usually this means the macro was only invoked conditionally." "$LINENO" 5
+ fi
++if test -z "${INCLUDE_DIR_NOTPARALLEL_TRUE}" && test -z "${INCLUDE_DIR_NOTPARALLEL_FALSE}"; then
++  as_fn_error "conditional \"INCLUDE_DIR_NOTPARALLEL\" was never defined.
++Usually this means the macro was only invoked conditionally." "$LINENO" 5
++fi
+ 
+ : ${CONFIG_STATUS=./config.status}
+ ac_write_fail=0
+Index: libstdc++-v3/python/libstdcxx/v6/printers.py
+===================================================================
+--- a/src/libstdc++-v3/python/libstdcxx/v6/printers.py	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/python/libstdcxx/v6/printers.py	(.../branches/gcc-6-branch)
+@@ -1154,7 +1154,7 @@
+     Recognizes type names that match a regular expression.
+     Replaces them with a formatted string which can use replacement field
+     {N} to refer to the \N subgroup of the regex match.
+-    Type printers are recusively applied to the subgroups.
++    Type printers are recursively applied to the subgroups.
+ 
+     This allows recognizing e.g. "std::vector<(.*), std::allocator<\\1> >"
+     and replacing it with "std::vector<{1}>", omitting the template argument
+@@ -1335,10 +1335,10 @@
+     # strip the "fundamentals_v1" inline namespace from these types
+     add_one_template_type_printer(obj, 'optional<T>',
+             'experimental::fundamentals_v1::optional<(.*)>',
+-            'experimental::optional<\\1>')
++            'experimental::optional<{1}>')
+     add_one_template_type_printer(obj, 'basic_string_view<C>',
+             'experimental::fundamentals_v1::basic_string_view<(.*), std::char_traits<\\1> >',
+-            'experimental::basic_string_view<\\1>')
++            'experimental::basic_string_view<{1}>')
+ 
+ def register_libstdcxx_printers (obj):
+     "Register libstdc++ pretty-printers with objfile Obj."
+Index: libstdc++-v3/src/filesystem/ops.cc
+===================================================================
+--- a/src/libstdc++-v3/src/filesystem/ops.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/filesystem/ops.cc	(.../branches/gcc-6-branch)
+@@ -443,48 +443,68 @@
+ 	return false;
+       }
+ 
++    size_t count = from_st->st_size;
+ #ifdef _GLIBCXX_USE_SENDFILE
+     off_t offset = 0;
+-    const auto n = ::sendfile(out.fd, in.fd, &offset, from_st->st_size);
+-    if (n < 0 && (errno == ENOSYS || errno == EINVAL))
++    ssize_t n = ::sendfile(out.fd, in.fd, &offset, count);
++    if (n < 0 && errno != ENOSYS && errno != EINVAL)
+       {
+-#endif
+-	__gnu_cxx::stdio_filebuf<char> sbin(in.fd, std::ios::in);
+-	__gnu_cxx::stdio_filebuf<char> sbout(out.fd, std::ios::out);
+-	if (sbin.is_open())
+-	  in.fd = -1;
+-	if (sbout.is_open())
+-	  out.fd = -1;
+-	if (from_st->st_size && !(std::ostream(&sbout) << &sbin))
++	ec.assign(errno, std::generic_category());
++	return false;
++      }
++    if ((size_t)n == count)
++      {
++	if (!out.close() || !in.close())
+ 	  {
+-	    ec = std::make_error_code(std::errc::io_error);
+-	    return false;
+-	  }
+-	if (!sbout.close() || !sbin.close())
+-	  {
+ 	    ec.assign(errno, std::generic_category());
+ 	    return false;
+ 	  }
+-
+ 	ec.clear();
+ 	return true;
++      }
++    else if (n > 0)
++      count -= n;
++#endif // _GLIBCXX_USE_SENDFILE
+ 
++    using std::ios;
++    __gnu_cxx::stdio_filebuf<char> sbin(in.fd, ios::in|ios::binary);
++    __gnu_cxx::stdio_filebuf<char> sbout(out.fd, ios::out|ios::binary);
++
++    if (sbin.is_open())
++      in.fd = -1;
++    if (sbout.is_open())
++      out.fd = -1;
++
+ #ifdef _GLIBCXX_USE_SENDFILE
++    if (n != 0)
++      {
++	if (n < 0)
++	  n = 0;
++
++	const auto p1 = sbin.pubseekoff(n, ios::beg, ios::in);
++	const auto p2 = sbout.pubseekoff(n, ios::beg, ios::out);
++
++	const std::streampos errpos(std::streamoff(-1));
++	if (p1 == errpos || p2 == errpos)
++	  {
++	    ec = std::make_error_code(std::errc::io_error);
++	    return false;
++	  }
+       }
+-    if (n != from_st->st_size)
++#endif
++
++    if (count && !(std::ostream(&sbout) << &sbin))
+       {
+-	ec.assign(errno, std::generic_category());
++	ec = std::make_error_code(std::errc::io_error);
+ 	return false;
+       }
+-    if (!out.close() || !in.close())
++    if (!sbout.close() || !sbin.close())
+       {
+ 	ec.assign(errno, std::generic_category());
+ 	return false;
+       }
+-
+     ec.clear();
+     return true;
+-#endif
+   }
+ }
+ #endif
+@@ -1199,26 +1219,45 @@
+ 
+ fs::path fs::read_symlink(const path& p, error_code& ec)
+ {
++  path result;
+ #ifdef _GLIBCXX_HAVE_SYS_STAT_H
+   stat_type st;
+   if (::lstat(p.c_str(), &st))
+     {
+       ec.assign(errno, std::generic_category());
+-      return {};
++      return result;
+     }
+-  std::string buf(st.st_size, '\0');
+-  ssize_t len = ::readlink(p.c_str(), &buf.front(), buf.size());
+-  if (len == -1)
++  std::string buf(st.st_size ? st.st_size + 1 : 128, '\0');
++  do
+     {
+-      ec.assign(errno, std::generic_category());
+-      return {};
++      ssize_t len = ::readlink(p.c_str(), &buf.front(), buf.size());
++      if (len == -1)
++	{
++	  ec.assign(errno, std::generic_category());
++	  return result;
++	}
++      else if (len == (ssize_t)buf.size())
++	{
++	  if (buf.size() > 4096)
++	    {
++	      ec.assign(ENAMETOOLONG, std::generic_category());
++	      return result;
++	    }
++	  buf.resize(buf.size() * 2);
++	}
++      else
++	{
++	  buf.resize(len);
++	  result.assign(buf);
++	  ec.clear();
++	  break;
++	}
+     }
+-  ec.clear();
+-  return path{buf.data(), buf.data()+len};
++  while (true);
+ #else
+   ec = std::make_error_code(std::errc::not_supported);
+-  return {};
+ #endif
++  return result;
+ }
+ 
+ 
+@@ -1235,16 +1274,15 @@
+ bool
+ fs::remove(const path& p, error_code& ec) noexcept
+ {
+-  if (exists(symlink_status(p, ec)))
++    if (::remove(p.c_str()) == 0)
+     {
+-      if (::remove(p.c_str()) == 0)
+-	{
+-	  ec.clear();
+-	  return true;
+-	}
+-      else
+-	ec.assign(errno, std::generic_category());
++      ec.clear();
++      return true;
+     }
++  else if (errno == ENOENT)
++    ec.clear();
++  else
++    ec.assign(errno, std::generic_category());
+   return false;
+ }
+ 
+@@ -1253,7 +1291,7 @@
+ fs::remove_all(const path& p)
+ {
+   error_code ec;
+-  bool result = remove_all(p, ec);
++  const auto result = remove_all(p, ec);
+   if (ec.value())
+     _GLIBCXX_THROW_OR_ABORT(filesystem_error("cannot remove all", p, ec));
+   return result;
+@@ -1262,14 +1300,28 @@
+ std::uintmax_t
+ fs::remove_all(const path& p, error_code& ec) noexcept
+ {
+-  auto fs = symlink_status(p, ec);
++    const auto s = symlink_status(p, ec);
++  if (!status_known(s))
++    return -1;
++
++  ec.clear();
++  if (s.type() == file_type::not_found)
++    return 0;
++
+   uintmax_t count = 0;
+-  if (ec.value() == 0 && fs.type() == file_type::directory)
+-    for (directory_iterator d(p, ec), end; ec.value() == 0 && d != end; ++d)
+-      count += fs::remove_all(d->path(), ec);
+-  if (ec.value())
+-    return -1;
+-  return fs::remove(p, ec) ? ++count : -1;  // fs:remove() calls ec.clear()
++  if (s.type() == file_type::directory)
++    {
++      for (directory_iterator d(p, ec), end; !ec && d != end; d.increment(ec))
++	count += fs::remove_all(d->path(), ec);
++      if (ec.value() == ENOENT)
++	ec.clear();
++      else if (ec)
++	return -1;
++    }
++
++  if (fs::remove(p, ec))
++    ++count;
++  return ec ? -1 : count;
+ }
+ 
+ void
+Index: libstdc++-v3/src/c++98/misc-inst.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++98/misc-inst.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++98/misc-inst.cc	(.../branches/gcc-6-branch)
+@@ -36,34 +36,6 @@
+ {
+ _GLIBCXX_BEGIN_NAMESPACE_VERSION
+ 
+-  // string related to iostreams
+-  template 
+-    basic_istream<char>& 
+-    operator>>(basic_istream<char>&, string&);
+-  template 
+-    basic_ostream<char>& 
+-    operator<<(basic_ostream<char>&, const string&);
+-  template 
+-    basic_istream<char>& 
+-    getline(basic_istream<char>&, string&, char);
+-  template 
+-    basic_istream<char>& 
+-    getline(basic_istream<char>&, string&);
+-#ifdef _GLIBCXX_USE_WCHAR_T
+-  template 
+-    basic_istream<wchar_t>& 
+-    operator>>(basic_istream<wchar_t>&, wstring&);
+-  template 
+-    basic_ostream<wchar_t>& 
+-    operator<<(basic_ostream<wchar_t>&, const wstring&);
+-  template 
+-    basic_istream<wchar_t>& 
+-    getline(basic_istream<wchar_t>&, wstring&, wchar_t);
+-  template 
+-    basic_istream<wchar_t>& 
+-    getline(basic_istream<wchar_t>&, wstring&);
+-#endif
+-
+ #if _GLIBCXX_USE_CXX11_ABI
+   // C++98 members that are not instantiated by src/c++11/string-inst.cc
+   // because they changed in C++11 to take const_iterator parameters.
+Index: libstdc++-v3/src/c++11/cow-wstring-inst.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/cow-wstring-inst.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/cow-wstring-inst.cc	(.../branches/gcc-6-branch)
+@@ -33,32 +33,8 @@
+ #define C wchar_t
+ #include "string-inst.cc"
+ 
+-#include <ostream>
+-#include <istream>
+-
+ #if ! _GLIBCXX_USE_DUAL_ABI
+ # error This file should not be compiled for this configuration.
+ #endif
+ 
+-namespace std _GLIBCXX_VISIBILITY(default)
+-{
+-_GLIBCXX_BEGIN_NAMESPACE_VERSION
+-
+-  // XXX these came from c++98/misc-inst.cc, repeat them for COW string
+-  // string related to iostreams
+-  template 
+-    basic_istream<wchar_t>& 
+-    operator>>(basic_istream<wchar_t>&, wstring&);
+-  template 
+-    basic_ostream<wchar_t>& 
+-    operator<<(basic_ostream<wchar_t>&, const wstring&);
+-  template 
+-    basic_istream<wchar_t>& 
+-    getline(basic_istream<wchar_t>&, wstring&, wchar_t);
+-  template 
+-    basic_istream<wchar_t>& 
+-    getline(basic_istream<wchar_t>&, wstring&);
+-
+-_GLIBCXX_END_NAMESPACE_VERSION
+-} // namespace
+ #endif
+Index: libstdc++-v3/src/c++11/Makefile.in
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/Makefile.in	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/Makefile.in	(.../branches/gcc-6-branch)
+@@ -97,8 +97,11 @@
+ 	system_error.lo thread.lo $(am__objects_1) $(am__objects_2)
+ @ENABLE_DUAL_ABI_TRUE@am__objects_4 = cow-fstream-inst.lo \
+ @ENABLE_DUAL_ABI_TRUE@	cow-sstream-inst.lo cow-string-inst.lo \
+-@ENABLE_DUAL_ABI_TRUE@	cow-wstring-inst.lo cxx11-locale-inst.lo \
+-@ENABLE_DUAL_ABI_TRUE@	cxx11-wlocale-inst.lo
++@ENABLE_DUAL_ABI_TRUE@	cow-string-io-inst.lo \
++@ENABLE_DUAL_ABI_TRUE@	cow-wstring-inst.lo \
++@ENABLE_DUAL_ABI_TRUE@	cow-wstring-io-inst.lo \
++@ENABLE_DUAL_ABI_TRUE@	cxx11-locale-inst.lo \
++@ENABLE_DUAL_ABI_TRUE@	cxx11-wlocale-inst.lo sso_string.lo
+ @ENABLE_EXTERN_TEMPLATE_TRUE@am__objects_5 = $(am__objects_4) \
+ @ENABLE_EXTERN_TEMPLATE_TRUE@	ext11-inst.lo fstream-inst.lo \
+ @ENABLE_EXTERN_TEMPLATE_TRUE@	ios-inst.lo iostream-inst.lo \
+@@ -105,7 +108,9 @@
+ @ENABLE_EXTERN_TEMPLATE_TRUE@	istream-inst.lo locale-inst.lo \
+ @ENABLE_EXTERN_TEMPLATE_TRUE@	ostream-inst.lo sstream-inst.lo \
+ @ENABLE_EXTERN_TEMPLATE_TRUE@	streambuf-inst.lo string-inst.lo \
+-@ENABLE_EXTERN_TEMPLATE_TRUE@	wlocale-inst.lo wstring-inst.lo
++@ENABLE_EXTERN_TEMPLATE_TRUE@	string-io-inst.lo wlocale-inst.lo \
++@ENABLE_EXTERN_TEMPLATE_TRUE@	wstring-inst.lo \
++@ENABLE_EXTERN_TEMPLATE_TRUE@	wstring-io-inst.lo
+ am_libc__11convenience_la_OBJECTS = $(am__objects_3) $(am__objects_5)
+ libc__11convenience_la_OBJECTS = $(am_libc__11convenience_la_OBJECTS)
+ DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+@@ -395,9 +400,12 @@
+ @ENABLE_DUAL_ABI_TRUE@	cow-fstream-inst.cc \
+ @ENABLE_DUAL_ABI_TRUE@	cow-sstream-inst.cc \
+ @ENABLE_DUAL_ABI_TRUE@	cow-string-inst.cc \
++@ENABLE_DUAL_ABI_TRUE@	cow-string-io-inst.cc \
+ @ENABLE_DUAL_ABI_TRUE@	cow-wstring-inst.cc \
++@ENABLE_DUAL_ABI_TRUE@	cow-wstring-io-inst.cc \
+ @ENABLE_DUAL_ABI_TRUE@	cxx11-locale-inst.cc \
+-@ENABLE_DUAL_ABI_TRUE@	cxx11-wlocale-inst.cc
++@ENABLE_DUAL_ABI_TRUE@	cxx11-wlocale-inst.cc \
++@ENABLE_DUAL_ABI_TRUE@	sso_string.cc
+ 
+ # XTEMPLATE_FLAGS =
+ @ENABLE_EXTERN_TEMPLATE_FALSE@inst_sources = 
+@@ -415,8 +423,10 @@
+ @ENABLE_EXTERN_TEMPLATE_TRUE@	sstream-inst.cc \
+ @ENABLE_EXTERN_TEMPLATE_TRUE@	streambuf-inst.cc \
+ @ENABLE_EXTERN_TEMPLATE_TRUE@	string-inst.cc \
++@ENABLE_EXTERN_TEMPLATE_TRUE@	string-io-inst.cc \
+ @ENABLE_EXTERN_TEMPLATE_TRUE@	wlocale-inst.cc \
+-@ENABLE_EXTERN_TEMPLATE_TRUE@	wstring-inst.cc
++@ENABLE_EXTERN_TEMPLATE_TRUE@	wstring-inst.cc \
++@ENABLE_EXTERN_TEMPLATE_TRUE@	wstring-io-inst.cc
+ 
+ libc__11convenience_la_SOURCES = $(sources)  $(inst_sources)
+ 
+Index: libstdc++-v3/src/c++11/cow-string-inst.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/cow-string-inst.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/cow-string-inst.cc	(.../branches/gcc-6-branch)
+@@ -29,35 +29,10 @@
+ #define _GLIBCXX_USE_CXX11_ABI 0
+ #include "string-inst.cc"
+ 
+-#include <istream>
+-#include <ostream>
+-
+ #if ! _GLIBCXX_USE_DUAL_ABI
+ # error This file should not be compiled for this configuration.
+ #endif
+ 
+-namespace std _GLIBCXX_VISIBILITY(default)
+-{
+-_GLIBCXX_BEGIN_NAMESPACE_VERSION
+-
+-  // These came from c++98/misc-inst.cc, repeat them for COW string
+-  // string related to iostreams.
+-  template 
+-    basic_istream<char>& 
+-    operator>>(basic_istream<char>&, string&);
+-  template 
+-    basic_ostream<char>& 
+-    operator<<(basic_ostream<char>&, const string&);
+-  template 
+-    basic_istream<char>& 
+-    getline(basic_istream<char>&, string&, char);
+-  template 
+-    basic_istream<char>& 
+-    getline(basic_istream<char>&, string&);
+-
+-_GLIBCXX_END_NAMESPACE_VERSION
+-} // namespace
+-
+ #ifdef  _GLIBCXX_USE_C99_STDINT_TR1
+ #include <random>
+ #if defined __i386__ || defined __x86_64__
+Index: libstdc++-v3/src/c++11/regex.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/regex.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/regex.cc	(.../branches/gcc-6-branch)
+@@ -24,11 +24,17 @@
+ 
+ #include <stdexcept>
+ #include <bits/regex_error.h>
++#include <bits/functexcept.h>
+ 
+ namespace std _GLIBCXX_VISIBILITY(default)
+ {
+ _GLIBCXX_BEGIN_NAMESPACE_VERSION
+ 
++  void
++  __throw_regex_error(regex_constants::error_type __ecode
++		      __attribute__((unused)))
++  { _GLIBCXX_THROW_OR_ABORT(regex_error(__ecode)); }
++
+   regex_error::regex_error(regex_constants::error_type __ecode)
+   : std::runtime_error("regex_error"), _M_code(__ecode)
+   { }
+Index: libstdc++-v3/src/c++11/future.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/future.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/future.cc	(.../branches/gcc-6-branch)
+@@ -23,6 +23,7 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include <future>
++#include <bits/functexcept.h>
+ 
+ namespace
+ {
+@@ -70,6 +71,10 @@
+ {
+ _GLIBCXX_BEGIN_NAMESPACE_VERSION
+ 
++  void
++  __throw_future_error(int __i __attribute__((unused)))
++  { _GLIBCXX_THROW_OR_ABORT(future_error(make_error_code(future_errc(__i)))); }
++
+   const error_category& future_category() noexcept
+   { return __future_category_instance(); }
+ 
+Index: libstdc++-v3/src/c++11/cow-string-io-inst.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/cow-string-io-inst.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/cow-string-io-inst.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,59 @@
++// Reference-counted COW string instantiations for I/O -*- C++ -*-
++
++// Copyright (C) 2014-2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// Under Section 7 of GPL version 3, you are granted additional
++// permissions described in the GCC Runtime Library Exception, version
++// 3.1, as published by the Free Software Foundation.
++
++// You should have received a copy of the GNU General Public License and
++// a copy of the GCC Runtime Library Exception along with this program;
++// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++// <http://www.gnu.org/licenses/>.
++
++//
++// ISO C++ 14882: 21  Strings library
++//
++
++#define _GLIBCXX_USE_CXX11_ABI 0
++#include <istream>
++#include <ostream>
++
++#if ! _GLIBCXX_USE_DUAL_ABI
++# error This file should not be compiled for this configuration.
++#endif
++
++namespace std _GLIBCXX_VISIBILITY(default)
++{
++_GLIBCXX_BEGIN_NAMESPACE_VERSION
++
++  // The equivalent SSO string instantiations are in c++98/misc-inst.cc,
++  // repeat them for COW string
++
++  // string related to iostreams.
++  template
++    basic_istream<char>&
++    operator>>(basic_istream<char>&, string&);
++  template
++    basic_ostream<char>&
++    operator<<(basic_ostream<char>&, const string&);
++  template
++    basic_istream<char>&
++    getline(basic_istream<char>&, string&, char);
++  template
++    basic_istream<char>&
++    getline(basic_istream<char>&, string&);
++
++_GLIBCXX_END_NAMESPACE_VERSION
++} // namespace
+Index: libstdc++-v3/src/c++11/string-io-inst.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/string-io-inst.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/string-io-inst.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,53 @@
++// SSO string instantiations for I/O -*- C++ -*-
++
++// Copyright (C) 1997-2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// Under Section 7 of GPL version 3, you are granted additional
++// permissions described in the GCC Runtime Library Exception, version
++// 3.1, as published by the Free Software Foundation.
++
++// You should have received a copy of the GNU General Public License and
++// a copy of the GCC Runtime Library Exception along with this program;
++// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++// <http://www.gnu.org/licenses/>.
++
++//
++// ISO C++ 14882:
++//
++
++#define _GLIBCXX_USE_CXX11_ABI 1
++#include <string>
++#include <istream>
++#include <ostream>
++
++namespace std _GLIBCXX_VISIBILITY(default)
++{
++_GLIBCXX_BEGIN_NAMESPACE_VERSION
++
++  // string related to iostreams
++  template
++    basic_istream<char>&
++    operator>>(basic_istream<char>&, string&);
++  template
++    basic_ostream<char>&
++    operator<<(basic_ostream<char>&, const string&);
++  template
++    basic_istream<char>&
++    getline(basic_istream<char>&, string&, char);
++  template
++    basic_istream<char>&
++    getline(basic_istream<char>&, string&);
++
++_GLIBCXX_END_NAMESPACE_VERSION
++} // namespace
+Index: libstdc++-v3/src/c++11/functexcept.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/functexcept.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/functexcept.cc	(.../branches/gcc-6-branch)
+@@ -20,9 +20,6 @@
+ // see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+ // <http://www.gnu.org/licenses/>.
+ 
+-// We don't want to change the type thrown by __throw_ios_failure (yet?)
+-#define _GLIBCXX_USE_CXX11_ABI 0
+-
+ #include <bits/functexcept.h>
+ #include <cstdlib>
+ #include <exception>
+@@ -29,11 +26,6 @@
+ #include <stdexcept>
+ #include <new>
+ #include <typeinfo>
+-#include <ios>
+-#include <system_error>
+-#include <future>
+-#include <functional>
+-#include <bits/regex_error.h>
+ #include <stdarg.h>
+ 
+ #ifdef _GLIBCXX_USE_NLS
+@@ -121,27 +113,5 @@
+   __throw_underflow_error(const char* __s __attribute__((unused)))
+   { _GLIBCXX_THROW_OR_ABORT(underflow_error(_(__s))); }
+ 
+-  void
+-  __throw_ios_failure(const char* __s __attribute__((unused)))
+-  { _GLIBCXX_THROW_OR_ABORT(ios_base::failure(_(__s))); }
+-
+-  void
+-  __throw_system_error(int __i __attribute__((unused)))
+-  { _GLIBCXX_THROW_OR_ABORT(system_error(error_code(__i,
+-						    generic_category()))); }
+-
+-  void
+-  __throw_future_error(int __i __attribute__((unused)))
+-  { _GLIBCXX_THROW_OR_ABORT(future_error(make_error_code(future_errc(__i)))); }
+-
+-  void
+-  __throw_bad_function_call()
+-  { _GLIBCXX_THROW_OR_ABORT(bad_function_call()); }
+-
+-  void
+-  __throw_regex_error(regex_constants::error_type __ecode
+-		      __attribute__((unused)))
+-  { _GLIBCXX_THROW_OR_ABORT(regex_error(__ecode)); }
+-
+ _GLIBCXX_END_NAMESPACE_VERSION
+ } // namespace
+Index: libstdc++-v3/src/c++11/ios.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/ios.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/ios.cc	(.../branches/gcc-6-branch)
+@@ -26,13 +26,29 @@
+ // ISO C++ 14882: 27.4  Iostreams base classes
+ //
+ 
++// Determines the version of ios_base::failure thrown by __throw_ios_failure.
++// If !_GLIBCXX_USE_DUAL_ABI this will get undefined automatically.
++#define _GLIBCXX_USE_CXX11_ABI 0
++
+ #include <ios>
+ #include <limits>
++#include <bits/functexcept.h>
+ 
++#ifdef _GLIBCXX_USE_NLS
++# include <libintl.h>
++# define _(msgid)   gettext (msgid)
++#else
++# define _(msgid)   (msgid)
++#endif
++
+ namespace std _GLIBCXX_VISIBILITY(default)
+ {
+ _GLIBCXX_BEGIN_NAMESPACE_VERSION
+ 
++  void
++  __throw_ios_failure(const char* __s __attribute__((unused)))
++  { _GLIBCXX_THROW_OR_ABORT(ios_base::failure(_(__s))); }
++
+   // Definitions for static const members of ios_base.
+   const ios_base::fmtflags ios_base::boolalpha;
+   const ios_base::fmtflags ios_base::dec;
+Index: libstdc++-v3/src/c++11/sso_string.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/sso_string.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/sso_string.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,107 @@
++// Helper for accessing __cxx11::string from the ABI -*- C++ -*-
++
++// Copyright (C) 2014-2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// Under Section 7 of GPL version 3, you are granted additional
++// permissions described in the GCC Runtime Library Exception, version
++// 3.1, as published by the Free Software Foundation.
++
++// You should have received a copy of the GNU General Public License and
++// a copy of the GCC Runtime Library Exception along with this program;
++// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++// <http://www.gnu.org/licenses/>.
++
++
++#define _GLIBCXX_USE_CXX11_ABI 1
++#define __sso_string __sso_stringxxx
++#include <string>
++#include <stdexcept>
++#undef __sso_string
++
++#if ! _GLIBCXX_USE_DUAL_ABI
++# error This file should not be compiled for this configuration.
++#endif
++
++namespace std _GLIBCXX_VISIBILITY(default)
++{
++_GLIBCXX_BEGIN_NAMESPACE_VERSION
++
++#pragma GCC diagnostic push
++#pragma GCC diagnostic ignored "-Wabi-tag"
++  // Redefine __sso_string so that we can define and export its members
++  // in terms of the SSO std::string.
++  struct __sso_string
++  {
++    struct __str
++    {
++      const char* _M_p;
++      size_t _M_string_length;
++      char _M_local_buf[16];
++    };
++
++    union {
++      __str _M_s;
++      char _M_bytes[sizeof(_M_s)];
++      std::string _M_str;
++    };
++
++    __sso_string();
++    __sso_string(const std::string& s);
++    __sso_string(const char*, size_t n);
++    __sso_string(const __sso_string&) noexcept;
++    __sso_string& operator=(const __sso_string&) noexcept;
++    ~__sso_string();
++    __sso_string(__sso_string&&) noexcept;
++    __sso_string& operator=(__sso_string&&) noexcept;
++  };
++#pragma GCC diagnostic pop
++
++  __sso_string::__sso_string() : _M_str() { }
++
++#if _GLIBCXX_USE_CXX11_ABI
++  static_assert(sizeof(__sso_string) == sizeof(std::string),
++                "sizeof(std::string) has changed");
++  static_assert(alignof(__sso_string) == alignof(std::string),
++                "alignof(std::string) has changed");
++
++  // This constructor is defined in src/c++11/cow-stdexcept.cc for COW strings
++  __sso_string::__sso_string(const std::string& s) : _M_str(s) { }
++#endif
++
++  __sso_string::__sso_string(const char* s, size_t n) : _M_str(s, n) { }
++
++  __sso_string::__sso_string(const __sso_string& s) noexcept
++  : _M_str(s._M_str) { }
++
++  __sso_string&
++  __sso_string::operator=(const __sso_string& s) noexcept
++  {
++    _M_str = s._M_str;
++    return *this;
++  }
++
++  __sso_string::~__sso_string() { _M_str.~basic_string(); }
++
++  __sso_string::__sso_string(__sso_string&& s) noexcept
++  : _M_str(std::move(s._M_str)) { }
++
++  __sso_string&
++  __sso_string::operator=(__sso_string&& s) noexcept
++  {
++    _M_str = std::move(s._M_str);
++    return *this;
++  }
++
++_GLIBCXX_END_NAMESPACE_VERSION
++} // namespace
+Index: libstdc++-v3/src/c++11/system_error.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/system_error.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/system_error.cc	(.../branches/gcc-6-branch)
+@@ -75,6 +75,12 @@
+ {
+ _GLIBCXX_BEGIN_NAMESPACE_VERSION
+ 
++  void
++  __throw_system_error(int __i __attribute__((unused)))
++  {
++    _GLIBCXX_THROW_OR_ABORT(system_error(error_code(__i, generic_category())));
++  }
++
+   error_category::~error_category() noexcept = default;
+ 
+   const error_category& 
+@@ -112,73 +118,5 @@
+   }
+ #endif
+ 
+-#if _GLIBCXX_USE_DUAL_ABI
+-#pragma GCC diagnostic push
+-#pragma GCC diagnostic ignored "-Wabi-tag"
+-  // Redefine __sso_string so that we can define and export its members
+-  // in terms of the SSO std::string.
+-  struct __sso_string
+-  {
+-    struct __str
+-    {
+-      const char* _M_p;
+-      size_t _M_string_length;
+-      char _M_local_buf[16];
+-    };
+-
+-    union {
+-      __str _M_s;
+-      char _M_bytes[sizeof(_M_s)];
+-      std::string _M_str;
+-    };
+-
+-    __sso_string();
+-    __sso_string(const std::string& s);
+-    __sso_string(const char*, size_t n);
+-    __sso_string(const __sso_string&) noexcept;
+-    __sso_string& operator=(const __sso_string&) noexcept;
+-    ~__sso_string();
+-    __sso_string(__sso_string&&) noexcept;
+-    __sso_string& operator=(__sso_string&&) noexcept;
+-  };
+-#pragma GCC diagnostic pop
+-
+-  __sso_string::__sso_string() : _M_str() { }
+-
+-#if _GLIBCXX_USE_CXX11_ABI
+-  static_assert(sizeof(__sso_string) == sizeof(std::string),
+-                "sizeof(std::string) has changed");
+-  static_assert(alignof(__sso_string) == alignof(std::string),
+-                "alignof(std::string) has changed");
+-
+-  // This constructor is defined in src/c++11/cow-stdexcept.cc for COW strings
+-  __sso_string::__sso_string(const std::string& s) : _M_str(s) { }
+-#endif
+-
+-  __sso_string::__sso_string(const char* s, size_t n) : _M_str(s, n) { }
+-
+-  __sso_string::__sso_string(const __sso_string& s) noexcept
+-  : _M_str(s._M_str) { }
+-
+-  __sso_string&
+-  __sso_string::operator=(const __sso_string& s) noexcept
+-  {
+-    _M_str = s._M_str;
+-    return *this;
+-  }
+-
+-  __sso_string::~__sso_string() { _M_str.~basic_string(); }
+-
+-  __sso_string::__sso_string(__sso_string&& s) noexcept
+-  : _M_str(std::move(s._M_str)) { }
+-
+-  __sso_string&
+-  __sso_string::operator=(__sso_string&& s) noexcept
+-  {
+-    _M_str = std::move(s._M_str);
+-    return *this;
+-  }
+-#endif // _GLIBCXX_USE_DUAL_ABI
+-
+ _GLIBCXX_END_NAMESPACE_VERSION
+ } // namespace
+Index: libstdc++-v3/src/c++11/functional.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/functional.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/functional.cc	(.../branches/gcc-6-branch)
+@@ -23,11 +23,16 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include <functional>
++#include <bits/functexcept.h>
+ 
+ namespace std _GLIBCXX_VISIBILITY(default)
+ {
+ _GLIBCXX_BEGIN_NAMESPACE_VERSION
+ 
++  void
++  __throw_bad_function_call()
++  { _GLIBCXX_THROW_OR_ABORT(bad_function_call()); }
++
+   bad_function_call::~bad_function_call() noexcept = default;
+ 
+   const char*
+Index: libstdc++-v3/src/c++11/cow-wstring-io-inst.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/cow-wstring-io-inst.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/cow-wstring-io-inst.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,63 @@
++// Reference-counted COW wide string instantiations for I/O -*- C++ -*-
++
++// Copyright (C) 2014-2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// Under Section 7 of GPL version 3, you are granted additional
++// permissions described in the GCC Runtime Library Exception, version
++// 3.1, as published by the Free Software Foundation.
++
++// You should have received a copy of the GNU General Public License and
++// a copy of the GCC Runtime Library Exception along with this program;
++// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++// <http://www.gnu.org/licenses/>.
++
++//
++// ISO C++ 14882: 21  Strings library
++//
++
++#define _GLIBCXX_USE_CXX11_ABI 0
++#include <bits/c++config.h>
++
++#ifdef _GLIBCXX_USE_WCHAR_T
++#include <ostream>
++#include <istream>
++
++#if ! _GLIBCXX_USE_DUAL_ABI
++# error This file should not be compiled for this configuration.
++#endif
++
++namespace std _GLIBCXX_VISIBILITY(default)
++{
++_GLIBCXX_BEGIN_NAMESPACE_VERSION
++
++  // The equivalent SSO wstring instantiations are in c++98/misc-inst.cc,
++  // repeat them for COW wstring
++
++  // string related to iostreams
++  template
++    basic_istream<wchar_t>&
++    operator>>(basic_istream<wchar_t>&, wstring&);
++  template
++    basic_ostream<wchar_t>&
++    operator<<(basic_ostream<wchar_t>&, const wstring&);
++  template
++    basic_istream<wchar_t>&
++    getline(basic_istream<wchar_t>&, wstring&, wchar_t);
++  template
++    basic_istream<wchar_t>&
++    getline(basic_istream<wchar_t>&, wstring&);
++
++_GLIBCXX_END_NAMESPACE_VERSION
++} // namespace
++#endif
+Index: libstdc++-v3/src/c++11/wstring-io-inst.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/wstring-io-inst.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/wstring-io-inst.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,55 @@
++// SSO string instantiations for I/O -*- C++ -*-
++
++// Copyright (C) 1997-2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// Under Section 7 of GPL version 3, you are granted additional
++// permissions described in the GCC Runtime Library Exception, version
++// 3.1, as published by the Free Software Foundation.
++
++// You should have received a copy of the GNU General Public License and
++// a copy of the GCC Runtime Library Exception along with this program;
++// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++// <http://www.gnu.org/licenses/>.
++
++//
++// ISO C++ 14882:
++//
++
++#define _GLIBCXX_USE_CXX11_ABI 1
++#include <string>
++#include <istream>
++#include <ostream>
++
++namespace std _GLIBCXX_VISIBILITY(default)
++{
++_GLIBCXX_BEGIN_NAMESPACE_VERSION
++
++  // string related to iostreams
++#ifdef _GLIBCXX_USE_WCHAR_T
++  template
++    basic_istream<wchar_t>&
++    operator>>(basic_istream<wchar_t>&, wstring&);
++  template
++    basic_ostream<wchar_t>&
++    operator<<(basic_ostream<wchar_t>&, const wstring&);
++  template
++    basic_istream<wchar_t>&
++    getline(basic_istream<wchar_t>&, wstring&, wchar_t);
++  template
++    basic_istream<wchar_t>&
++    getline(basic_istream<wchar_t>&, wstring&);
++#endif
++
++_GLIBCXX_END_NAMESPACE_VERSION
++} // namespace
+Index: libstdc++-v3/src/c++11/snprintf_lite.cc
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/snprintf_lite.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/snprintf_lite.cc	(.../branches/gcc-6-branch)
+@@ -52,7 +52,7 @@
+     const size_t __len = __bufend - __buf + 1;
+ 
+     const char __err[] = "not enough space for format expansion "
+-      "(Please submit full bug report at http://gcc.gnu.org/bugs.html):\n    ";
++      "(Please submit full bug report at https://gcc.gnu.org/bugs/):\n    ";
+     const size_t __errlen = sizeof(__err) - 1;
+ 
+     char *const __e
+@@ -71,19 +71,17 @@
+   // Returns number of characters appended, or -1 if BUFSIZE is too small.
+   int __concat_size_t(char *__buf, size_t __bufsize, size_t __val)
+   {
+-    // __int_to_char is explicitly instantiated and available only for
+-    // some, but not all, types. See locale-inst.cc.
+-#ifdef _GLIBCXX_USE_LONG_LONG
+-    unsigned long long __val2 = __val;
+-#else
+-    unsigned long __val2 = __val;
+-#endif
+     // Long enough for decimal representation.
+-    int __ilen = 3 * sizeof(__val2);
++    int __ilen = 3 * sizeof(__val);
+     char *__cs = static_cast<char*>(__builtin_alloca(__ilen));
+-    size_t __len = std::__int_to_char(__cs + __ilen, __val2,
+-				      std::__num_base::_S_atoms_out,
+-				      std::ios_base::dec, true);
++    char* __out = __cs + __ilen;
++    do
++      {
++	*--__out = "0123456789"[__val % 10];
++	__val /= 10;
++      }
++    while (__val != 0);
++    size_t __len = __cs + __ilen - __out;
+     if (__bufsize < __len)
+       return -1;
+ 
+Index: libstdc++-v3/src/c++11/Makefile.am
+===================================================================
+--- a/src/libstdc++-v3/src/c++11/Makefile.am	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/src/c++11/Makefile.am	(.../branches/gcc-6-branch)
+@@ -82,9 +82,12 @@
+ 	cow-fstream-inst.cc \
+ 	cow-sstream-inst.cc \
+ 	cow-string-inst.cc \
++	cow-string-io-inst.cc \
+ 	cow-wstring-inst.cc \
++	cow-wstring-io-inst.cc \
+ 	cxx11-locale-inst.cc \
+-	cxx11-wlocale-inst.cc
++	cxx11-wlocale-inst.cc \
++	sso_string.cc
+ else
+ extra_string_inst_sources =
+ endif
+@@ -103,8 +106,10 @@
+ 	sstream-inst.cc \
+ 	streambuf-inst.cc \
+ 	string-inst.cc \
++	string-io-inst.cc \
+ 	wlocale-inst.cc \
+-	wstring-inst.cc
++	wstring-inst.cc \
++	wstring-io-inst.cc
+ else
+ # XTEMPLATE_FLAGS =
+ inst_sources =
+Index: libstdc++-v3/configure.ac
+===================================================================
+--- a/src/libstdc++-v3/configure.ac	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/configure.ac	(.../branches/gcc-6-branch)
+@@ -456,6 +456,12 @@
+ 	       test $ac_cv_prog_DBLATEX = "yes" &&
+ 	       test $ac_cv_prog_PDFLATEX = "yes")
+ 
++case "$build" in
++ *-*-darwin* ) glibcxx_include_dir_notparallel=yes ;;
++ * ) glibcxx_include_dir_notparallel=no ;;
++esac
++AM_CONDITIONAL(INCLUDE_DIR_NOTPARALLEL,
++               test $glibcxx_include_dir_notparallel = "yes")
+ 
+ # Propagate the target-specific source directories through the build chain.
+ ATOMICITY_SRCDIR=config/${atomicity_dir}
+Index: libstdc++-v3/doc/xml/manual/status_cxxtr1.xml
+===================================================================
+--- a/src/libstdc++-v3/doc/xml/manual/status_cxxtr1.xml	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/xml/manual/status_cxxtr1.xml	(.../branches/gcc-6-branch)
+@@ -22,8 +22,7 @@
+ </para>
+ 
+ <para>
+-This page describes the TR1 support in mainline GCC SVN, not in any particular
+-release.
++This page describes the TR1 support in the GCC 6 series.
+ </para>
+ 
+ <!-- Status is Yes or No, Broken/Partial-->
+Index: libstdc++-v3/doc/xml/manual/status_cxx1998.xml
+===================================================================
+--- a/src/libstdc++-v3/doc/xml/manual/status_cxx1998.xml	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/xml/manual/status_cxx1998.xml	(.../branches/gcc-6-branch)
+@@ -18,8 +18,7 @@
+ </para>
+ 
+ <para>
+-This page describes the C++ support in mainline GCC SVN, not in any
+-particular release.
++This page describes the C++ support in the GCC 6 series.
+ </para>
+ 
+ <!-- Status is Yes or No, Broken/Partial-->
+Index: libstdc++-v3/doc/xml/manual/extensions.xml
+===================================================================
+--- a/src/libstdc++-v3/doc/xml/manual/extensions.xml	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/xml/manual/extensions.xml	(.../branches/gcc-6-branch)
+@@ -502,7 +502,7 @@
+     <quote>demangling.</quote>
+   </para>
+   <para>
+-    If you have read the <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://gcc.gnu.org/onlinedocs/libstdc++/latest-doxygen/a01115.html">source
++    If you have read the <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://gcc.gnu.org/onlinedocs/libstdc++/latest-doxygen/namespaces.html">source
+     documentation for <code>namespace abi</code></link> then you are
+     aware of the cross-vendor C++ ABI in use by GCC.  One of the
+     exposed functions is used for demangling,
+Index: libstdc++-v3/doc/xml/manual/status_cxxtr24733.xml
+===================================================================
+--- a/src/libstdc++-v3/doc/xml/manual/status_cxxtr24733.xml	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/xml/manual/status_cxxtr24733.xml	(.../branches/gcc-6-branch)
+@@ -16,8 +16,7 @@
+ </para>
+ 
+ <para>
+-This page describes the TR 24733 support in mainline GCC SVN, not in any
+-particular release.
++This page describes the TR 24733 support in the GCC 6 series.
+ </para>
+ 
+ <!-- Status is Yes or No, Broken/Partial-->
+Index: libstdc++-v3/doc/html/bk02.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/bk02.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/bk02.html	(.../branches/gcc-6-branch)
+@@ -1,2 +1,2 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library" /><link rel="prev" href="manual/backwards.html" title="Backwards Compatibility" /><link rel="next" href="api.html" title="The GNU C++ Library API Reference" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="manual/backwards.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="api.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="article"><a href="api.html">The GNU C++ Library API Reference</a></span></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="manual/backwards.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="api.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Backwards Compatibility </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> The GNU C++ Library API Reference</td></tr></table></div></body></html>
+\ No newline at end of file
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library" /><link rel="prev" href="manual/backwards.html" title="Backwards Compatibility" /><link rel="next" href="api.html" title="The GNU C++ Library API Reference" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="manual/backwards.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="api.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="article"><a href="api.html">The GNU C++ Library API Reference</a></span></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="manual/backwards.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="api.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Backwards Compatibility </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> The GNU C++ Library API Reference</td></tr></table></div></body></html>
+\ No newline at end of file
+Index: libstdc++-v3/doc/html/bk03.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/bk03.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/bk03.html	(.../branches/gcc-6-branch)
+@@ -1,2 +1,2 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library" /><link rel="prev" href="api.html" title="The GNU C++ Library API Reference" /><link rel="next" href="faq.html" title="Frequently Asked Questions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="faq.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="article"><a href="faq.html">Frequently Asked Questions</a></span></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="faq.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library API Reference </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> Frequently Asked Questions</td></tr></table></div></body></html>
+\ No newline at end of file
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library" /><link rel="prev" href="api.html" title="The GNU C++ Library API Reference" /><link rel="next" href="faq.html" title="Frequently Asked Questions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="faq.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="article"><a href="faq.html">Frequently Asked Questions</a></span></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="faq.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library API Reference </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> Frequently Asked Questions</td></tr></table></div></body></html>
+\ No newline at end of file
+Index: libstdc++-v3/doc/html/faq.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/faq.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/faq.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Frequently Asked Questions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="bk03.html" title="" /><link rel="prev" href="bk03.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Frequently Asked Questions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bk03.html">Prev</a> </td><th width="60%" align="center"></th><td width="20%" align="right"> </td></tr></table><hr /></div><div class="article"><div class="titlepage"><div><div><h1 class="title"><a id="faq"></a>Frequently Asked Questions</h1></div><div><p class="copyright">Copyright © 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Frequently Asked Questions</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="bk03.html" title="" /><link rel="prev" href="bk03.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Frequently Asked Questions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bk03.html">Prev</a> </td><th width="60%" align="center"></th><td width="20%" align="right"> </td></tr></table><hr /></div><div class="article"><div class="titlepage"><div><div><h1 class="title"><a id="faq"></a>Frequently Asked Questions</h1></div><div><p class="copyright">Copyright © 
+       2008-2014
+      
+       <a class="link" href="http://www.fsf.org" target="_top">FSF</a>
+Index: libstdc++-v3/doc/html/index.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/index.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/index.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="description" content="Short Contents Copyright (C) 2008-2016 FSF Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. This is the top level of the libstdc++ documentation set. The documentation is divided into the following three sections. Manual Frequently Asked Questions API and Source Documentation" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="next" href="manual/index.html" title="The GNU C++ Library Manual" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library</th></tr><tr><td width="20%" align="left"> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="manual/index.html">Next</a></td></tr></table><hr /></div><div class="set" lang="en" xml:lang="en"><div class="titlepage"><div><div><h1 class="title"><a id="set-index"></a>The GNU C++ Library</h1></div><div><div class="abstract"><a id="contents"></a><p class="title"><strong>Short Contents</strong></p><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="description" content="Short Contents Copyright (C) 2008-2016 FSF Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. This is the top level of the libstdc++ documentation set. The documentation is divided into the following three sections. Manual Frequently Asked Questions API and Source Documentation" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="next" href="manual/index.html" title="The GNU C++ Library Manual" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library</th></tr><tr><td width="20%" align="left"> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="manual/index.html">Next</a></td></tr></table><hr /></div><div class="set" lang="en" xml:lang="en"><div class="titlepage"><div><div><h1 class="title"><a id="set-index"></a>The GNU C++ Library</h1></div><div><div class="abstract"><a id="contents"></a><p class="title"><strong>Short Contents</strong></p><p>
+       Copyright (C) 2008-2016
+       <a class="link" href="http://www.fsf.org/" target="_top">FSF
+       </a>
+Index: libstdc++-v3/doc/html/api.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/api.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/api.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library API Reference</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="bk02.html" title="" /><link rel="prev" href="bk02.html" title="" /><link rel="next" href="bk03.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library API Reference</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bk02.html">Prev</a> </td><th width="60%" align="center"></th><td width="20%" align="right"> <a accesskey="n" href="bk03.html">Next</a></td></tr></table><hr /></div><div class="article"><div class="titlepage"><div><div><h1 class="title"><a id="api"></a>The GNU C++ Library API Reference</h1></div><div><p class="copyright">Copyright © 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library API Reference</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="index.html" title="The GNU C++ Library" /><link rel="up" href="bk02.html" title="" /><link rel="prev" href="bk02.html" title="" /><link rel="next" href="bk03.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library API Reference</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bk02.html">Prev</a> </td><th width="60%" align="center"></th><td width="20%" align="right"> <a accesskey="n" href="bk03.html">Next</a></td></tr></table><hr /></div><div class="article"><div class="titlepage"><div><div><h1 class="title"><a id="api"></a>The GNU C++ Library API Reference</h1></div><div><p class="copyright">Copyright © 
+       2008
+     , 
+       2010
+Index: libstdc++-v3/doc/html/manual/dynamic_memory.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/dynamic_memory.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/dynamic_memory.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Dynamic Memory</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="support.html" title="Chapter 4.  Support" /><link rel="prev" href="support.html" title="Chapter 4.  Support" /><link rel="next" href="termination.html" title="Termination" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Dynamic Memory</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="support.html">Prev</a> </td><th width="60%" align="center">Chapter 4. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Dynamic Memory</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="support.html" title="Chapter 4.  Support" /><link rel="prev" href="support.html" title="Chapter 4.  Support" /><link rel="next" href="termination.html" title="Termination" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Dynamic Memory</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="support.html">Prev</a> </td><th width="60%" align="center">Chapter 4. 
+   Support
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="termination.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.support.memory"></a>Dynamic Memory</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/iterators.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/iterators.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/iterators.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 10.  Iterators</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="containers_and_c.html" title="Interacting with C" /><link rel="next" href="algorithms.html" title="Chapter 11.  Algorithms" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 10. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 10.  Iterators</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="containers_and_c.html" title="Interacting with C" /><link rel="next" href="algorithms.html" title="Chapter 11.  Algorithms" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 10. 
+   Iterators
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="containers_and_c.html">Prev</a> </td><th width="60%" align="center">Part II. 
+Index: libstdc++-v3/doc/html/manual/mt_allocator_ex_single.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/mt_allocator_ex_single.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/mt_allocator_ex_single.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Single Thread Example</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_impl.html" title="Implementation" /><link rel="next" href="mt_allocator_ex_multi.html" title="Multiple Thread Example" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Single Thread Example</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_ex_multi.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.example_single"></a>Single Thread Example</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Single Thread Example</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_impl.html" title="Implementation" /><link rel="next" href="mt_allocator_ex_multi.html" title="Multiple Thread Example" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Single Thread Example</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_ex_multi.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.example_single"></a>Single Thread Example</h2></div></div></div><p>
+ Let's start by describing how the data on a freelist is laid out in memory.
+ This is the first two blocks in freelist for thread id 3 in bin 3 (8 bytes):
+ </p><pre class="programlisting">
+Index: libstdc++-v3/doc/html/manual/generalized_numeric_operations.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/generalized_numeric_operations.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/generalized_numeric_operations.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Generalized Operations</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="numerics.html" title="Chapter 12.  Numerics" /><link rel="prev" href="numerics.html" title="Chapter 12.  Numerics" /><link rel="next" href="numerics_and_c.html" title="Interacting with C" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Generalized Operations</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="numerics.html">Prev</a> </td><th width="60%" align="center">Chapter 12. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Generalized Operations</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="numerics.html" title="Chapter 12.  Numerics" /><link rel="prev" href="numerics.html" title="Chapter 12.  Numerics" /><link rel="next" href="numerics_and_c.html" title="Interacting with C" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Generalized Operations</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="numerics.html">Prev</a> </td><th width="60%" align="center">Chapter 12. 
+   Numerics
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="numerics_and_c.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.numerics.generalized_ops"></a>Generalized Operations</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/mt_allocator.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/mt_allocator.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/mt_allocator.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 20. The mt_allocator</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="profile_mode_diagnostics.html" title="Diagnostics" /><link rel="next" href="mt_allocator_design.html" title="Design Issues" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 20. The mt_allocator</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_diagnostics.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 20. The mt_allocator</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="profile_mode_diagnostics.html" title="Diagnostics" /><link rel="next" href="mt_allocator_design.html" title="Design Issues" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 20. The mt_allocator</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_diagnostics.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_design.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.allocator.mt"></a>Chapter 20. The mt_allocator</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="mt_allocator.html#allocator.mt.intro">Intro</a></span></dt><dt><span class="section"><a href="mt_allocator_design.html">Design Issues</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator_design.html#allocator.mt.overview">Overview</a></span></dt></dl></dd><dt><span class="section"><a href="mt_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.tune">Tunable Parameters</a></span></dt><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.init">Initialization</a></span></dt><dt><span class="section"><a href="mt_allocator_impl.html#allocator.mt.deallocation">Deallocation Notes</a></span></dt></dl></dd><dt><span class="section"><a href="mt_allocator_ex_single.html">Single Thread Example</a></span></dt><dt><span class="section"><a href="mt_allocator_ex_multi.html">Multiple Thread Example</a></span></dt></dl></div><p>
+Index: libstdc++-v3/doc/html/manual/unordered_associative.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/unordered_associative.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/unordered_associative.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Unordered Associative</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9.  Containers" /><link rel="prev" href="associative.html" title="Associative" /><link rel="next" href="containers_and_c.html" title="Interacting with C" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Unordered Associative</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="associative.html">Prev</a> </td><th width="60%" align="center">Chapter 9. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Unordered Associative</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9.  Containers" /><link rel="prev" href="associative.html" title="Associative" /><link rel="next" href="containers_and_c.html" title="Interacting with C" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Unordered Associative</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="associative.html">Prev</a> </td><th width="60%" align="center">Chapter 9. 
+   Containers
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="containers_and_c.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.unordered"></a>Unordered Associative</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.unordered.insert_hints"></a>Insertion Hints</h3></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/configure.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/configure.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/configure.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Configure</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, configure, options" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="setup.html" title="Chapter 2. Setup" /><link rel="prev" href="setup.html" title="Chapter 2. Setup" /><link rel="next" href="make.html" title="Make" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Configure</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="setup.html">Prev</a> </td><th width="60%" align="center">Chapter 2. Setup</th><td width="20%" align="right"> <a accesskey="n" href="make.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.configure"></a>Configure</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Configure</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, configure, options" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="setup.html" title="Chapter 2. Setup" /><link rel="prev" href="setup.html" title="Chapter 2. Setup" /><link rel="next" href="make.html" title="Make" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Configure</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="setup.html">Prev</a> </td><th width="60%" align="center">Chapter 2. Setup</th><td width="20%" align="right"> <a accesskey="n" href="make.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.configure"></a>Configure</h2></div></div></div><p>
+   When configuring libstdc++, you'll have to configure the entire
+   <span class="emphasis"><em>gccsrcdir</em></span> directory. Consider using the
+   toplevel gcc configuration option
+Index: libstdc++-v3/doc/html/manual/status.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/status.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/status.html	(.../branches/gcc-6-branch)
+@@ -1,13 +1,12 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 1. Status</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I.  Introduction" /><link rel="prev" href="intro.html" title="Part I.  Introduction" /><link rel="next" href="license.html" title="License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 1. Status</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="intro.html">Prev</a> </td><th width="60%" align="center">Part I. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 1. Status</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I.  Introduction" /><link rel="prev" href="intro.html" title="Part I.  Introduction" /><link rel="next" href="license.html" title="License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 1. Status</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="intro.html">Prev</a> </td><th width="60%" align="center">Part I. 
+   Introduction
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="license.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.status"></a>Chapter 1. Status</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="status.html#manual.intro.status.iso">Implementation Status</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#status.iso.1998">C++ 1998/2003</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.1998.status">Implementation Status</a></span></dt><dt><span class="section"><a href="status.html#iso.1998.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2011">C++ 2011</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.2011.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.2014">C++ 2014</a></span></dt><dt><span class="section"><a href="status.html#status.iso.201z">C++ 201z</a></span></dt><dt><span class="section"><a href="status.html#status.iso.tr1">C++ TR1</a></span></dt><dd><dl><dt><span class="section"><a href="status.html#iso.tr1.specific">Implementation Specific Behavior</a></span></dt></dl></dd><dt><span class="section"><a href="status.html#status.iso.tr24733">C++ TR 24733</a></span></dt></dl></dd><dt><span class="section"><a href="license.html">License</a></span></dt><dd><dl><dt><span class="section"><a href="license.html#manual.intro.status.license.gpl">The Code: GPL</a></span></dt><dt><span class="section"><a href="license.html#manual.intro.status.license.fdl">The Documentation: GPL, FDL</a></span></dt></dl></dd><dt><span class="section"><a href="bugs.html">Bugs</a></span></dt><dd><dl><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.impl">Implementation Bugs</a></span></dt><dt><span class="section"><a href="bugs.html#manual.intro.status.bugs.iso">Standard Bugs</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.iso"></a>Implementation Status</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="status.iso.1998"></a>C++ 1998/2003</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="iso.1998.status"></a>Implementation Status</h4></div></div></div><p>
+ This status table is based on the table of contents of ISO/IEC 14882:2003.
+ </p><p>
+-This page describes the C++ support in mainline GCC SVN, not in any
+-particular release.
+-</p><div class="table"><a id="table.cxx98_status"></a><p class="title"><strong>Table 1.1. C++ 1998/2003 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 1998/2003 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
++This page describes the C++ support in the GCC 6 series.
++</p><div class="table"><a id="table.cxx98_status"></a><p class="title"><strong>Table 1.1. C++ 1998/2003 Implementation Status</strong></p><div class="table-contents"><table class="table" summary="C++ 1998/2003 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
+ 	<span class="emphasis"><em>18</em></span>
+       </td><td colspan="3" align="left">
+ 	<span class="emphasis"><em>Language support</em></span>
+@@ -157,7 +156,7 @@
+ presence of the required flag.
+ </p><p>
+ This page describes the C++11 support in the GCC 6 series.
+-</p><div class="table"><a id="table.cxx11_status"></a><p class="title"><strong>Table 1.2. C++ 2011 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 2011 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
++</p><div class="table"><a id="table.cxx11_status"></a><p class="title"><strong>Table 1.2. C++ 2011 Implementation Status</strong></p><div class="table-contents"><table class="table" summary="C++ 2011 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
+ 	<span class="emphasis"><em>18</em></span>
+       </td><td colspan="3" align="left">
+ 	<span class="emphasis"><em>Language support</em></span>
+@@ -333,7 +332,7 @@
+ presence of the required flag.
+ </p><p>
+ This page describes the C++14 and library TS support in the GCC 6 series.
+-</p><div class="table"><a id="table.cxx14_status"></a><p class="title"><strong>Table 1.3. C++ 2014 Implementation Status</strong></p><div class="table-contents"><table summary="C++ 2014 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Paper</th><th align="left">Title</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
++</p><div class="table"><a id="table.cxx14_status"></a><p class="title"><strong>Table 1.3. C++ 2014 Implementation Status</strong></p><div class="table-contents"><table class="table" summary="C++ 2014 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Paper</th><th align="left">Title</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
+ 	<a class="link" href="http://www.open-std.org/JTC1/sc22/WG21/docs/papers/2013/n3669.pdf" target="_top">
+ 	  N3669
+ 	</a>
+@@ -405,7 +404,7 @@
+ 	<a class="link" href="http://www.open-std.org/JTC1/sc22/WG21/docs/papers/2013/n3644.pdf" target="_top">
+ 	  N3644
+ 	</a>
+-      </td><td align="left">Null Forward Iterators</td><td align="left">Partial</td><td align="left">Only affects Debug Mode</td></tr></tbody></table></div></div><br class="table-break" /><div class="table"><a id="table.ts_status"></a><p class="title"><strong>Table 1.4. C++ Technical Specifications Implementation Status</strong></p><div class="table-contents"><table summary="C++ Technical Specifications Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Paper</th><th align="left">Title</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr bgcolor="#C8B0B0"><td align="left">
++      </td><td align="left">Null Forward Iterators</td><td align="left">Partial</td><td align="left">Only affects Debug Mode</td></tr></tbody></table></div></div><br class="table-break" /><div class="table"><a id="table.ts_status"></a><p class="title"><strong>Table 1.4. C++ Technical Specifications Implementation Status</strong></p><div class="table-contents"><table class="table" summary="C++ Technical Specifications Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Paper</th><th align="left">Title</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr bgcolor="#C8B0B0"><td align="left">
+ 	<a class="link" href="http://www.open-std.org/JTC1/sc22/WG21/docs/papers/2013/n3662.html" target="_top">
+ 	  N3662
+ 	</a>
+@@ -467,7 +466,7 @@
+ presence of the required flag.
+ </p><p>
+ This page describes the C++1z and library TS support in the GCC 6 series.
+-</p><div class="table"><a id="table.cxx1z_status"></a><p class="title"><strong>Table 1.5. C++ 201z Implementation Status</strong></p><div class="table-contents"><table summary="C++ 201z Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Paper</th><th align="left">Title</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
++</p><div class="table"><a id="table.cxx1z_status"></a><p class="title"><strong>Table 1.5. C++ 201z Implementation Status</strong></p><div class="table-contents"><table class="table" summary="C++ 201z Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Paper</th><th align="left">Title</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
+ 	<a class="link" href="http://www.open-std.org/JTC1/sc22/WG21/docs/papers/2014/n4259.pdf" target="_top">
+ 	  N4259
+ 	</a>
+@@ -540,7 +539,7 @@
+ 	</a>
+       </td><td align="left">
+         Logical Operator Type Traits (revision 1)
+-      </td><td align="left">Y</td><td align="left"> </td></tr></tbody></table></div></div><br class="table-break" /><div class="table"><a id="table.cxx1z_ts_status"></a><p class="title"><strong>Table 1.6. C++ Technical Specifications Implementation Status</strong></p><div class="table-contents"><table summary="C++ Technical Specifications Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Paper</th><th align="left">Title</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
++      </td><td align="left">Y</td><td align="left"> </td></tr></tbody></table></div></div><br class="table-break" /><div class="table"><a id="table.cxx1z_ts_status"></a><p class="title"><strong>Table 1.6. C++ Technical Specifications Implementation Status</strong></p><div class="table-contents"><table class="table" summary="C++ Technical Specifications Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Paper</th><th align="left">Title</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
+ 	<a class="link" href="http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2014/n4076.html" target="_top">
+ 	  N4076
+ 	</a>
+@@ -593,9 +592,8 @@
+ <code class="code">tr1/</code>, for instance <code class="code">&lt;tr1/functional&gt;</code>,
+ <code class="code">&lt;tr1/memory&gt;</code>, and so on.
+ </p><p>
+-This page describes the TR1 support in mainline GCC SVN, not in any particular
+-release.
+-</p><div class="table"><a id="table.tr1_status"></a><p class="title"><strong>Table 1.7. C++ TR1 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR1 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left"><span class="emphasis"><em>2</em></span></td><td colspan="3" align="left"><span class="emphasis"><em>General Utilities</em></span></td></tr><tr><td align="left">2.1</td><td align="left">Reference wrappers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.1</td><td align="left">Additions to header <code class="code">&lt;functional&gt;</code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2</td><td align="left">Class template <code class="code">reference_wrapper</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.2.1</td><td align="left"><code class="code">reference_wrapper</code> construct/copy/destroy</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.2</td><td align="left"><code class="code">reference_wrapper</code> assignment</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.3</td><td align="left"><code class="code">reference_wrapper</code> access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.4</td><td align="left"><code class="code">reference_wrapper</code> invocation</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.5</td><td align="left"><code class="code">reference_wrapper</code> helper functions</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2</td><td align="left">Smart pointers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.2.1</td><td align="left">Additions to header <code class="code">&lt;memory&gt;</code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.2</td><td align="left">Class <code class="code">bad_weak_ptr</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.3</td><td align="left">Class template <code class="code">shared_ptr</code></td><td align="left"> </td><td align="left">
++This page describes the TR1 support in the GCC 6 series.
++</p><div class="table"><a id="table.tr1_status"></a><p class="title"><strong>Table 1.7. C++ TR1 Implementation Status</strong></p><div class="table-contents"><table class="table" summary="C++ TR1 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left"><span class="emphasis"><em>2</em></span></td><td colspan="3" align="left"><span class="emphasis"><em>General Utilities</em></span></td></tr><tr><td align="left">2.1</td><td align="left">Reference wrappers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.1</td><td align="left">Additions to header <code class="code">&lt;functional&gt;</code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2</td><td align="left">Class template <code class="code">reference_wrapper</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.1.2.1</td><td align="left"><code class="code">reference_wrapper</code> construct/copy/destroy</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.2</td><td align="left"><code class="code">reference_wrapper</code> assignment</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.3</td><td align="left"><code class="code">reference_wrapper</code> access</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.4</td><td align="left"><code class="code">reference_wrapper</code> invocation</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.1.2.5</td><td align="left"><code class="code">reference_wrapper</code> helper functions</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2</td><td align="left">Smart pointers</td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left">2.2.1</td><td align="left">Additions to header <code class="code">&lt;memory&gt;</code> synopsis</td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.2</td><td align="left">Class <code class="code">bad_weak_ptr</code></td><td align="left">Y</td><td align="left"> </td></tr><tr><td align="left">2.2.3</td><td align="left">Class template <code class="code">shared_ptr</code></td><td align="left"> </td><td align="left">
+ 	<p>
+ 	  Uses code from
+ 	  <a class="link" href="http://www.boost.org/libs/smart_ptr/shared_ptr.htm" target="_top">boost::shared_ptr</a>.
+@@ -614,9 +612,8 @@
+ Extension for the programming language C++ to support
+ decimal floating-point arithmetic
+ </p><p>
+-This page describes the TR 24733 support in mainline GCC SVN, not in any
+-particular release.
+-</p><div class="table"><a id="table.decfp_status"></a><p class="title"><strong>Table 1.8. C++ TR 24733 Implementation Status</strong></p><div class="table-contents"><table summary="C++ TR 24733 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
++This page describes the TR 24733 support in the GCC 6 series.
++</p><div class="table"><a id="table.decfp_status"></a><p class="title"><strong>Table 1.8. C++ TR 24733 Implementation Status</strong></p><div class="table-contents"><table class="table" summary="C++ TR 24733 Implementation Status" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Section</th><th align="left">Description</th><th align="left">Status</th><th align="left">Comments</th></tr></thead><tbody><tr><td align="left">
+ 	<span class="emphasis"><em>0</em></span>
+       </td><td colspan="3" align="left">
+ 	<span class="emphasis"><em>Introduction</em></span>
+Index: libstdc++-v3/doc/html/manual/profile_mode_devel.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/profile_mode_devel.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/profile_mode_devel.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Developer Information</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_impl.html" title="Implementation Issues" /><link rel="next" href="profile_mode_diagnostics.html" title="Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Developer Information</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_diagnostics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.developer"></a>Developer Information</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.developer.bigpic"></a>Big Picture</h3></div></div></div><p>The profile mode headers are included with
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Developer Information</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_impl.html" title="Implementation Issues" /><link rel="next" href="profile_mode_diagnostics.html" title="Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Developer Information</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_diagnostics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.developer"></a>Developer Information</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.developer.bigpic"></a>Big Picture</h3></div></div></div><p>The profile mode headers are included with
+    <code class="code">-D_GLIBCXX_PROFILE</code> through preprocessor directives in
+    <code class="code">include/std/*</code>.
+   </p><p>Instrumented implementations are provided in
+Index: libstdc++-v3/doc/html/manual/debug_mode_design.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/debug_mode_design.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/debug_mode_design.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_using.html" title="Using" /><link rel="next" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.design"></a>Design</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_using.html" title="Using" /><link rel="next" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.design"></a>Design</h2></div></div></div><p>
+   </p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="debug_mode.design.goals"></a>Goals</h3></div></div></div><p>
+     </p><p> The libstdc++ debug mode replaces unsafe (but efficient) standard
+   containers and iterators with semantically equivalent safe standard
+Index: libstdc++-v3/doc/html/manual/policy_data_structures_design.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/policy_data_structures_design.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/policy_data_structures_design.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_using.html" title="Using" /><link rel="next" href="policy_based_data_structures_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_using.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_based_data_structures_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.design"></a>Design</h2></div></div></div><p></p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.design.concepts"></a>Concepts</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.design.concepts.null_type"></a>Null Policy Classes</h4></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_using.html" title="Using" /><link rel="next" href="policy_based_data_structures_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_using.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_based_data_structures_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.design"></a>Design</h2></div></div></div><p></p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.design.concepts"></a>Concepts</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="pbds.design.concepts.null_type"></a>Null Policy Classes</h4></div></div></div><p>
+ 	Associative containers are typically parametrized by various
+ 	policies. For example, a hash-based associative container is
+ 	parametrized by a hash-functor, transforming each key into an
+Index: libstdc++-v3/doc/html/manual/using.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/using.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/using.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 3. Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I.  Introduction" /><link rel="prev" href="make.html" title="Make" /><link rel="next" href="using_headers.html" title="Headers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 3. Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="make.html">Prev</a> </td><th width="60%" align="center">Part I. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 3. Using</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I.  Introduction" /><link rel="prev" href="make.html" title="Make" /><link rel="next" href="using_headers.html" title="Headers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 3. Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="make.html">Prev</a> </td><th width="60%" align="center">Part I. 
+   Introduction
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="using_headers.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.using"></a>Chapter 3. Using</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="using.html#manual.intro.using.flags">Command Options</a></span></dt><dt><span class="section"><a href="using_headers.html">Headers</a></span></dt><dd><dl><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.all">Header Files</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.mixing">Mixing Headers</a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.cheaders">The C Headers and <code class="code">namespace std</code></a></span></dt><dt><span class="section"><a href="using_headers.html#manual.intro.using.headers.pre">Precompiled Headers</a></span></dt></dl></dd><dt><span class="section"><a href="using_macros.html">Macros</a></span></dt><dt><span class="section"><a href="using_dual_abi.html">Dual ABI</a></span></dt><dd><dl><dt><span class="section"><a href="using_dual_abi.html#manual.intro.using.abi.trouble">Troubleshooting</a></span></dt></dl></dd><dt><span class="section"><a href="using_namespaces.html">Namespaces</a></span></dt><dd><dl><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.all">Available Namespaces</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.std">namespace std</a></span></dt><dt><span class="section"><a href="using_namespaces.html#manual.intro.using.namespaces.comp">Using Namespace Composition</a></span></dt></dl></dd><dt><span class="section"><a href="using_dynamic_or_shared.html">Linking</a></span></dt><dd><dl><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.freestanding">Almost Nothing</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.dynamic">Finding Dynamic or Shared Libraries</a></span></dt><dt><span class="section"><a href="using_dynamic_or_shared.html#manual.intro.using.linkage.experimental">Experimental Library Extensions</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html">Concurrency</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.thread_safety">Thread Safety</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.atomics">Atomics</a></span></dt><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.io">IO</a></span></dt><dd><dl><dt><span class="section"><a href="using_concurrency.html#concurrency.io.structure">Structure</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.defaults">Defaults</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.future">Future</a></span></dt><dt><span class="section"><a href="using_concurrency.html#concurrency.io.alt">Alternatives</a></span></dt></dl></dd><dt><span class="section"><a href="using_concurrency.html#manual.intro.using.concurrency.containers">Containers</a></span></dt></dl></dd><dt><span class="section"><a href="using_exceptions.html">Exceptions</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.safety">Exception Safety</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.propagating">Exception Neutrality</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.no">Doing without</a></span></dt><dt><span class="section"><a href="using_exceptions.html#intro.using.exception.compat">Compatibility</a></span></dt><dd><dl><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.c">With <code class="literal">C</code></a></span></dt><dt><span class="section"><a href="using_exceptions.html#using.exception.compat.posix">With <code class="literal">POSIX</code> thread cancellation</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="debug.html">Debugging Support</a></span></dt><dd><dl><dt><span class="section"><a href="debug.html#debug.compiler">Using <span class="command"><strong>g++</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.req">Debug Versions of Library Binary Files</a></span></dt><dt><span class="section"><a href="debug.html#debug.memory">Memory Leak Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.races">Data Race Hunting</a></span></dt><dt><span class="section"><a href="debug.html#debug.gdb">Using <span class="command"><strong>gdb</strong></span></a></span></dt><dt><span class="section"><a href="debug.html#debug.exceptions">Tracking uncaught exceptions</a></span></dt><dt><span class="section"><a href="debug.html#debug.debug_mode">Debug Mode</a></span></dt><dt><span class="section"><a href="debug.html#debug.compile_time_checks">Compile Time Checking</a></span></dt><dt><span class="section"><a href="debug.html#debug.profile_mode">Profile-based Performance Analysis</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.flags"></a>Command Options</h2></div></div></div><p>
+@@ -13,7 +13,7 @@
+       By default, <span class="command"><strong>g++</strong></span> is equivalent to
+       <span class="command"><strong>g++ -std=gnu++14</strong></span> since GCC 6, and
+       <span class="command"><strong>g++ -std=gnu++98</strong></span> for older releases.
+-    </p><div class="table"><a id="table.cmd_options"></a><p class="title"><strong>Table 3.1. C++ Command Options</strong></p><div class="table-contents"><table summary="C++ Command Options" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Option Flags</th><th align="left">Description</th></tr></thead><tbody><tr><td align="left"><code class="literal">-std=c++98</code> or <code class="literal">-std=c++03</code>
++    </p><div class="table"><a id="table.cmd_options"></a><p class="title"><strong>Table 3.1. C++ Command Options</strong></p><div class="table-contents"><table class="table" summary="C++ Command Options" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Option Flags</th><th align="left">Description</th></tr></thead><tbody><tr><td align="left"><code class="literal">-std=c++98</code> or <code class="literal">-std=c++03</code>
+       </td><td align="left">Use the 1998 ISO C++ standard plus amendments.</td></tr><tr><td align="left"><code class="literal">-std=gnu++98</code> or <code class="literal">-std=gnu++03</code>
+       </td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-std=c++11</code></td><td align="left">Use the 2011 ISO C++ standard.</td></tr><tr><td align="left"><code class="literal">-std=gnu++11</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-std=c++14</code></td><td align="left">Use the 2014 ISO C++ standard.</td></tr><tr><td align="left"><code class="literal">-std=gnu++14</code></td><td align="left">As directly above, with GNU extensions.</td></tr><tr><td align="left"><code class="literal">-fexceptions</code></td><td align="left">See <a class="link" href="using_exceptions.html#intro.using.exception.no" title="Doing without">exception-free dialect</a></td></tr><tr><td align="left"><code class="literal">-frtti</code></td><td align="left">As above, but RTTI-free dialect.</td></tr><tr><td align="left"><code class="literal">-pthread</code> or <code class="literal">-pthreads</code></td><td align="left">For ISO C++11
+         <code class="filename">&lt;thread&gt;</code>,
+Index: libstdc++-v3/doc/html/manual/profile_mode_impl.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/profile_mode_impl.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/profile_mode_impl.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation Issues</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_cost_model.html" title="Empirical Cost Model" /><link rel="next" href="profile_mode_devel.html" title="Developer Information" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_cost_model.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_devel.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.implementation"></a>Implementation Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.implementation.stack"></a>Stack Traces</h3></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation Issues</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_cost_model.html" title="Empirical Cost Model" /><link rel="next" href="profile_mode_devel.html" title="Developer Information" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_cost_model.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_devel.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.implementation"></a>Implementation Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.implementation.stack"></a>Stack Traces</h3></div></div></div><p>
+   Accurate stack traces are needed during profiling since we group events by
+   call context and dynamic instance.  Without accurate traces, diagnostics
+   may be hard to interpret.  For instance, when giving advice to the user
+Index: libstdc++-v3/doc/html/manual/ext_containers.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/ext_containers.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/ext_containers.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 23. HP/SGI Extensions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="policy_data_structures_ack.html" title="Acknowledgments" /><link rel="next" href="ext_sgi.html" title="Deprecated" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 23. HP/SGI Extensions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_ack.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 23. HP/SGI Extensions</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="policy_data_structures_ack.html" title="Acknowledgments" /><link rel="next" href="ext_sgi.html" title="Deprecated" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 23. HP/SGI Extensions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_ack.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="ext_sgi.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers"></a>Chapter 23. HP/SGI Extensions</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="ext_containers.html#manual.ext.containers.sgi">Backwards Compatibility</a></span></dt><dt><span class="section"><a href="ext_sgi.html">Deprecated</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.sgi"></a>Backwards Compatibility</h2></div></div></div><p>A few extensions and nods to backwards-compatibility have
+Index: libstdc++-v3/doc/html/manual/ext_concurrency_use.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/ext_concurrency_use.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/ext_concurrency_use.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Use</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency_impl.html" title="Implementation" /><link rel="next" href="appendix.html" title="Part IV.  Appendices" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Use</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="appendix.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.use"></a>Use</h2></div></div></div><p>Typical usage of the last two constructs is demonstrated as follows:
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Use</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency_impl.html" title="Implementation" /><link rel="next" href="appendix.html" title="Part IV.  Appendices" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Use</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency_impl.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="appendix.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.use"></a>Use</h2></div></div></div><p>Typical usage of the last two constructs is demonstrated as follows:
+ </p><pre class="programlisting">
+ #include &lt;ext/concurrence.h&gt;
+ 
+Index: libstdc++-v3/doc/html/manual/ext_io.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/ext_io.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/ext_io.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 28. Input and Output</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_iterators.html" title="Chapter 27. Iterators" /><link rel="next" href="ext_demangling.html" title="Chapter 29. Demangling" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 28. Input and Output</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_iterators.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 28. Input and Output</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_iterators.html" title="Chapter 27. Iterators" /><link rel="next" href="ext_demangling.html" title="Chapter 29. Demangling" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 28. Input and Output</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_iterators.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="ext_demangling.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.io"></a>Chapter 28. Input and Output</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="ext_io.html#manual.ext.io.filebuf_derived">Derived filebufs</a></span></dt></dl></div><p>
+Index: libstdc++-v3/doc/html/manual/termination.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/termination.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/termination.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Termination</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="support.html" title="Chapter 4.  Support" /><link rel="prev" href="dynamic_memory.html" title="Dynamic Memory" /><link rel="next" href="diagnostics.html" title="Chapter 5.  Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Termination</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="dynamic_memory.html">Prev</a> </td><th width="60%" align="center">Chapter 4. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Termination</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="support.html" title="Chapter 4.  Support" /><link rel="prev" href="dynamic_memory.html" title="Dynamic Memory" /><link rel="next" href="diagnostics.html" title="Chapter 5.  Diagnostics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Termination</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="dynamic_memory.html">Prev</a> </td><th width="60%" align="center">Chapter 4. 
+   Support
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="diagnostics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.support.termination"></a>Termination</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="support.termination.handlers"></a>Termination Handlers</h3></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/using_macros.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/using_macros.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/using_macros.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Macros</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_headers.html" title="Headers" /><link rel="next" href="using_dual_abi.html" title="Dual ABI" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Macros</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_headers.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_dual_abi.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.macros"></a>Macros</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Macros</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_headers.html" title="Headers" /><link rel="next" href="using_dual_abi.html" title="Dual ABI" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Macros</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_headers.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_dual_abi.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.macros"></a>Macros</h2></div></div></div><p>
+      All library macros begin with <code class="code">_GLIBCXX_</code>.
+    </p><p>
+      Furthermore, all pre-processor macros, switches, and
+Index: libstdc++-v3/doc/html/manual/concurrency.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/concurrency.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/concurrency.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 15.  Concurrency</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library, mutex, thread, future, condition_variable" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="atomics.html" title="Chapter 14.  Atomics" /><link rel="next" href="extensions.html" title="Part III.  Extensions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 15. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 15.  Concurrency</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library, mutex, thread, future, condition_variable" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="atomics.html" title="Chapter 14.  Atomics" /><link rel="next" href="extensions.html" title="Part III.  Extensions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 15. 
+   Concurrency
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="atomics.html">Prev</a> </td><th width="60%" align="center">Part II. 
+Index: libstdc++-v3/doc/html/manual/ext_utilities.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/ext_utilities.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/ext_utilities.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 24. Utilities</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_sgi.html" title="Deprecated" /><link rel="next" href="ext_algorithms.html" title="Chapter 25. Algorithms" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 24. Utilities</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_sgi.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 24. Utilities</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_sgi.html" title="Deprecated" /><link rel="next" href="ext_algorithms.html" title="Chapter 25. Algorithms" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 24. Utilities</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_sgi.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="ext_algorithms.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.util"></a>Chapter 24. Utilities</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/policy_data_structures.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/policy_data_structures.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/policy_data_structures.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 22. Policy-Based Data Structures</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="bitmap_allocator_impl.html" title="Implementation" /><link rel="next" href="policy_data_structures_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 22. Policy-Based Data Structures</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bitmap_allocator_impl.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 22. Policy-Based Data Structures</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="bitmap_allocator_impl.html" title="Implementation" /><link rel="next" href="policy_data_structures_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 22. Policy-Based Data Structures</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bitmap_allocator_impl.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_using.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.containers.pbds"></a>Chapter 22. Policy-Based Data Structures</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="policy_data_structures.html#pbds.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues">Performance Issues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.associative">Associative</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.issues.priority_queue">Priority Que</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation">Goals</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.associative">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.iterators">Iterators</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.associative.functions">Functional</a></span></dt></dl></dd><dt><span class="section"><a href="policy_data_structures.html#pbds.intro.motivation.priority_queue">Priority Queues</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.policy">Policy Choices</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.underlying">Underlying Data Structures</a></span></dt><dt><span class="section"><a href="policy_data_structures.html#motivation.priority_queue.binary_heap">Binary Heaps</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="section"><a href="policy_data_structures_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.organization">Organization</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial">Tutorial</a></span></dt><dd><dl><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.basic">Basic Use</a></span></dt><dt><span class="section"><a href="policy_data_structures_using.html#pbds.using.tutorial.configuring">
+Index: libstdc++-v3/doc/html/manual/ext_iterators.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/ext_iterators.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/ext_iterators.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 27. Iterators</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_numerics.html" title="Chapter 26. Numerics" /><link rel="next" href="ext_io.html" title="Chapter 28. Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 27. Iterators</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_numerics.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 27. Iterators</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_numerics.html" title="Chapter 26. Numerics" /><link rel="next" href="ext_io.html" title="Chapter 28. Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 27. Iterators</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_numerics.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="ext_io.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.iterators"></a>Chapter 27. Iterators</h2></div></div></div><p>24.3.2 describes <code class="code">struct iterator</code>, which didn't exist in the
+Index: libstdc++-v3/doc/html/manual/bitmap_allocator_impl.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/bitmap_allocator_impl.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/bitmap_allocator_impl.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /><link rel="prev" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /><link rel="next" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bitmap_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 21. The bitmap_allocator</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.bitmap.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="bitmap.impl.free_list_store"></a>Free List Store</h3></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /><link rel="prev" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /><link rel="next" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bitmap_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 21. The bitmap_allocator</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.bitmap.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="bitmap.impl.free_list_store"></a>Free List Store</h3></div></div></div><p>
+     The Free List Store (referred to as FLS for the remaining part of this
+     document) is the Global memory pool that is shared by all instances of
+     the bitmapped allocator instantiated for any type. This maintains a
+@@ -75,7 +75,7 @@
+   </p><p>
+     Consider a block of size 64 ints. In memory, it would look like this:
+     (assume a 32-bit system where, size_t is a 32-bit entity).
+-  </p><div class="table"><a id="table.bitmap_alloc"></a><p class="title"><strong>Table 21.1. Bitmap Allocator Memory Map</strong></p><div class="table-contents"><table summary="Bitmap Allocator Memory Map" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left">268</td><td align="left">0</td><td align="left">4294967295</td><td align="left">4294967295</td><td align="left">Data -&gt; Space for 64 ints</td></tr></tbody></table></div></div><br class="table-break" /><p>
++  </p><div class="table"><a id="table.bitmap_alloc"></a><p class="title"><strong>Table 21.1. Bitmap Allocator Memory Map</strong></p><div class="table-contents"><table class="table" summary="Bitmap Allocator Memory Map" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left">268</td><td align="left">0</td><td align="left">4294967295</td><td align="left">4294967295</td><td align="left">Data -&gt; Space for 64 ints</td></tr></tbody></table></div></div><br class="table-break" /><p>
+     The first Column(268) represents the size of the Block in bytes as
+     seen by the Bitmap Allocator. Internally, a global free list is
+     used to keep track of the free blocks used and given back by the
+Index: libstdc++-v3/doc/html/manual/appendix_contributing.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/appendix_contributing.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/appendix_contributing.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix A.  Contributing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="appendix.html" title="Part IV.  Appendices" /><link rel="next" href="source_organization.html" title="Directory Layout and Source Conventions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix A. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix A.  Contributing</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="appendix.html" title="Part IV.  Appendices" /><link rel="next" href="source_organization.html" title="Directory Layout and Source Conventions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix A. 
+   Contributing
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix.html">Prev</a> </td><th width="60%" align="center">Part IV. 
+Index: libstdc++-v3/doc/html/manual/parallel_mode_test.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/parallel_mode_test.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/parallel_mode_test.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_design.html" title="Design" /><link rel="next" href="profile_mode.html" title="Chapter 19. Profile Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_design.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.test"></a>Testing</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_design.html" title="Design" /><link rel="next" href="profile_mode.html" title="Chapter 19. Profile Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_design.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.test"></a>Testing</h2></div></div></div><p>
+     Both the normal conformance and regression tests and the
+     supplemental performance tests work.
+   </p><p>
+Index: libstdc++-v3/doc/html/manual/profile_mode.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/profile_mode.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/profile_mode.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 19. Profile Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="parallel_mode_test.html" title="Testing" /><link rel="next" href="profile_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 19. Profile Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_test.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 19. Profile Mode</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="parallel_mode_test.html" title="Testing" /><link rel="next" href="profile_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 19. Profile Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_test.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_design.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.profile_mode"></a>Chapter 19. Profile Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.intro">Intro</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.using">Using the Profile Mode</a></span></dt><dt><span class="section"><a href="profile_mode.html#manual.ext.profile_mode.tuning">Tuning the Profile Mode</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.wrapper">Wrapper Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.instrumentation">Instrumentation</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.rtlib">Run Time Behavior</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.analysis">Analysis and Diagnostics</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.cost-model">Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.reports">Reports</a></span></dt><dt><span class="section"><a href="profile_mode_design.html#manual.ext.profile_mode.design.testing">Testing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_api.html">Extensions for Custom Containers</a></span></dt><dt><span class="section"><a href="profile_mode_cost_model.html">Empirical Cost Model</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html">Implementation Issues</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stack">Stack Traces</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.symbols">Symbolization of Instruction Addresses</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.concurrency">Concurrency</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.stdlib-in-proflib">Using the Standard Library in the Instrumentation Implementation</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.malloc-hooks">Malloc Hooks</a></span></dt><dt><span class="section"><a href="profile_mode_impl.html#manual.ext.profile_mode.implementation.construction-destruction">Construction and Destruction of Global Objects</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_devel.html">Developer Information</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.bigpic">Big Picture</a></span></dt><dt><span class="section"><a href="profile_mode_devel.html#manual.ext.profile_mode.developer.howto">How To Add A Diagnostic</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html">Diagnostics</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.template">Diagnostic Template</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers">Containers</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small">Hashtable Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large">Hashtable Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash">Inefficient Hash</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_small">Vector Too Small</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_too_large">Vector Too Large</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_hashtable">Vector to Hashtable</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_to_vector">Hashtable to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.vector_to_list">Vector to List</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_vector">List to Vector</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.list_to_slist">List to Forward List (Slist)</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.assoc_ord_to_unord">Ordered to Unordered Associative Container</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms">Algorithms</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.algorithms.sort">Sort Algorithm Performance</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality">Data Locality</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.sw_prefetch">Need Software Prefetch</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.locality.linked">Linked Structure Locality</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread">Multithreaded Data Access</a></span></dt><dd><dl><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.ddtest">Data Dependence Violations at Container Level</a></span></dt><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.mthread.false_share">False Sharing</a></span></dt></dl></dd><dt><span class="section"><a href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.statistics">Statistics</a></span></dt></dl></dd><dt><span class="bibliography"><a href="profile_mode.html#profile_mode.biblio">Bibliography</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.intro"></a>Intro</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/stringstreams.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/stringstreams.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/stringstreams.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory Based Streams</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="streambufs.html" title="Stream Buffers" /><link rel="next" href="fstreams.html" title="File Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory Based Streams</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="streambufs.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory Based Streams</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="streambufs.html" title="Stream Buffers" /><link rel="next" href="fstreams.html" title="File Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory Based Streams</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="streambufs.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
+   Input and Output
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="fstreams.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.memstreams"></a>Memory Based Streams</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.io.memstreams.compat"></a>Compatibility With strstream</h3></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/traits.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/traits.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/traits.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Traits</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="prev" href="memory.html" title="Memory" /><link rel="next" href="strings.html" title="Chapter 7.  Strings" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Traits</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="memory.html">Prev</a> </td><th width="60%" align="center">Chapter 6. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Traits</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="prev" href="memory.html" title="Memory" /><link rel="next" href="strings.html" title="Chapter 7.  Strings" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Traits</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="memory.html">Prev</a> </td><th width="60%" align="center">Chapter 6. 
+   Utilities
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="strings.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.traits"></a>Traits</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/policy_data_structures_ack.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/policy_data_structures_ack.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/policy_data_structures_ack.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Acknowledgments</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_based_data_structures_test.html" title="Testing" /><link rel="next" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Acknowledgments</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_based_data_structures_test.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="ext_containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.ack"></a>Acknowledgments</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Acknowledgments</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_based_data_structures_test.html" title="Testing" /><link rel="next" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Acknowledgments</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_based_data_structures_test.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="ext_containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.ack"></a>Acknowledgments</h2></div></div></div><p>
+       Written by Ami Tavory and Vladimir Dreizin (IBM Haifa Research
+       Laboratories), and Benjamin Kosnik (Red Hat).
+     </p><p>
+Index: libstdc++-v3/doc/html/manual/associative.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/associative.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/associative.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Associative</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9.  Containers" /><link rel="prev" href="containers.html" title="Chapter 9.  Containers" /><link rel="next" href="unordered_associative.html" title="Unordered Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Associative</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="containers.html">Prev</a> </td><th width="60%" align="center">Chapter 9. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Associative</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9.  Containers" /><link rel="prev" href="containers.html" title="Chapter 9.  Containers" /><link rel="next" href="unordered_associative.html" title="Unordered Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Associative</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="containers.html">Prev</a> </td><th width="60%" align="center">Chapter 9. 
+   Containers
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="unordered_associative.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.associative"></a>Associative</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.associative.insert_hints"></a>Insertion Hints</h3></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/ext_concurrency.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/ext_concurrency.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/ext_concurrency.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 30. Concurrency</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_demangling.html" title="Chapter 29. Demangling" /><link rel="next" href="ext_concurrency_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 30. Concurrency</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_demangling.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 30. Concurrency</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_demangling.html" title="Chapter 29. Demangling" /><link rel="next" href="ext_concurrency_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 30. Concurrency</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_demangling.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency_impl.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.concurrency"></a>Chapter 30. Concurrency</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="ext_concurrency.html#manual.ext.concurrency.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="ext_concurrency.html#manual.ext.concurrency.design.threads">Interface to Locks and Mutexes</a></span></dt><dt><span class="section"><a href="ext_concurrency.html#manual.ext.concurrency.design.atomics">Interface to Atomic Functions</a></span></dt></dl></dd><dt><span class="section"><a href="ext_concurrency_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="ext_concurrency_impl.html#manual.ext.concurrency.impl.atomic_fallbacks">Using Built-in Atomic Functions</a></span></dt><dt><span class="section"><a href="ext_concurrency_impl.html#manual.ext.concurrency.impl.thread">Thread Abstraction</a></span></dt></dl></dd><dt><span class="section"><a href="ext_concurrency_use.html">Use</a></span></dt></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.design"></a>Design</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.concurrency.design.threads"></a>Interface to Locks and Mutexes</h3></div></div></div><p>The file <code class="filename">&lt;ext/concurrence.h&gt;</code>
+Index: libstdc++-v3/doc/html/manual/support.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/support.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/support.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 4.  Support</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="next" href="dynamic_memory.html" title="Dynamic Memory" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 4. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 4.  Support</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="next" href="dynamic_memory.html" title="Dynamic Memory" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 4. 
+   Support
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="std_contents.html">Prev</a> </td><th width="60%" align="center">Part II. 
+Index: libstdc++-v3/doc/html/manual/bitmap_allocator.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/bitmap_allocator.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/bitmap_allocator.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 21. The bitmap_allocator</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="mt_allocator_ex_multi.html" title="Multiple Thread Example" /><link rel="next" href="bitmap_allocator_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 21. The bitmap_allocator</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_ex_multi.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 21. The bitmap_allocator</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="mt_allocator_ex_multi.html" title="Multiple Thread Example" /><link rel="next" href="bitmap_allocator_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 21. The bitmap_allocator</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_ex_multi.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="bitmap_allocator_impl.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.allocator.bitmap"></a>Chapter 21. The bitmap_allocator</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="bitmap_allocator.html#allocator.bitmap.design">Design</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.free_list_store">Free List Store</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block">Super Block</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.super_block_data">Super Block Data Layout</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.max_wasted">Maximum Wasted Percentage</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.allocate"><code class="function">allocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.deallocate"><code class="function">deallocate</code></a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.questions">Questions</a></span></dt><dd><dl><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.1">1</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.2">2</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.question.3">3</a></span></dt></dl></dd><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.locality">Locality</a></span></dt><dt><span class="section"><a href="bitmap_allocator_impl.html#bitmap.impl.grow_policy">Overhead and Grow Policy</a></span></dt></dl></dd></dl></div><p>
+Index: libstdc++-v3/doc/html/manual/license.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/license.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/license.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>License</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="status.html" title="Chapter 1. Status" /><link rel="prev" href="status.html" title="Chapter 1. Status" /><link rel="next" href="bugs.html" title="Bugs" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">License</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="status.html">Prev</a> </td><th width="60%" align="center">Chapter 1. Status</th><td width="20%" align="right"> <a accesskey="n" href="bugs.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.license"></a>License</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>License</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="status.html" title="Chapter 1. Status" /><link rel="prev" href="status.html" title="Chapter 1. Status" /><link rel="next" href="bugs.html" title="Bugs" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">License</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="status.html">Prev</a> </td><th width="60%" align="center">Chapter 1. Status</th><td width="20%" align="right"> <a accesskey="n" href="bugs.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.license"></a>License</h2></div></div></div><p>
+     There are two licenses affecting GNU libstdc++: one for the code,
+     and one for the documentation.
+     </p><p>
+Index: libstdc++-v3/doc/html/manual/numerics.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/numerics.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/numerics.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 12.  Numerics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="algorithms.html" title="Chapter 11.  Algorithms" /><link rel="next" href="generalized_numeric_operations.html" title="Generalized Operations" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 12. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 12.  Numerics</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="algorithms.html" title="Chapter 11.  Algorithms" /><link rel="next" href="generalized_numeric_operations.html" title="Generalized Operations" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 12. 
+   Numerics
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="algorithms.html">Prev</a> </td><th width="60%" align="center">Part II. 
+Index: libstdc++-v3/doc/html/manual/using_exceptions.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/using_exceptions.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/using_exceptions.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Exceptions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, exception, error, exception neutrality, exception safety, exception propagation, -fno-exceptions" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_concurrency.html" title="Concurrency" /><link rel="next" href="debug.html" title="Debugging Support" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Exceptions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="debug.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.exceptions"></a>Exceptions</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Exceptions</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, exception, error, exception neutrality, exception safety, exception propagation, -fno-exceptions" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_concurrency.html" title="Concurrency" /><link rel="next" href="debug.html" title="Debugging Support" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Exceptions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="debug.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.exceptions"></a>Exceptions</h2></div></div></div><p>
+ The C++ language provides language support for stack unwinding
+ with <code class="literal">try</code> and <code class="literal">catch</code> blocks and
+ the <code class="literal">throw</code> keyword.
+Index: libstdc++-v3/doc/html/manual/policy_based_data_structures_test.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/policy_based_data_structures_test.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/policy_based_data_structures_test.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_design.html" title="Design" /><link rel="next" href="policy_data_structures_ack.html" title="Acknowledgments" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_design.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_ack.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.test"></a>Testing</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.test.regression"></a>Regression</h3></div></div></div><p>The library contains a single comprehensive regression test.
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Testing</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures_design.html" title="Design" /><link rel="next" href="policy_data_structures_ack.html" title="Acknowledgments" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Testing</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures_design.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_ack.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="pbds.test"></a>Testing</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.test.regression"></a>Regression</h3></div></div></div><p>The library contains a single comprehensive regression test.
+     For a given container type in this library, the test creates
+     an object of the container type and an object of the
+     corresponding standard type (e.g., <code class="classname">std::set</code>). It
+@@ -49,7 +49,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_hash_text_find.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
+ 		    n_hash_map_ncah
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_map</code>
+@@ -182,7 +182,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_cc_hash_int_find.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
+ 		    n_hash_map_ncah
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_map</code>
+@@ -284,7 +284,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_gp_hash_int_find.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
+ 		    n_hash_map_ncah
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_map</code>
+@@ -384,7 +384,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_cc_hash_int_subscript_find.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
+ 		    n_hash_map_ncah
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_map</code>
+@@ -484,7 +484,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_gp_hash_int_subscript_find.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
+ 		    n_hash_map_ncah
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_map</code>
+@@ -571,7 +571,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_cc_hash_int_subscript_insert.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
+ 		    n_hash_map_ncah
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_map</code>
+@@ -671,7 +671,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_gp_hash_int_subscript_insert.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
+ 		    n_hash_map_ncah
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_map</code>
+@@ -779,7 +779,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_hash_zlob_int_find.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
+ 		    n_hash_map_ncah
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_map</code>
+@@ -899,7 +899,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_hash_int_erase_mem.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="5" align="left">
+ 		    n_hash_map_ncah
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_map</code>
+@@ -1007,7 +1007,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_tree_text_insert_node.png" align="middle" /></div><p>
+ 	      The abbreviated names in the legend of the graphic above are
+ 	      instantiated with the types in the following table.
+-	    </p></div><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	    </p></div><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_map
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::map</code>
+@@ -1040,7 +1040,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_tree_text_insert_vector.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_map
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::map</code>
+@@ -1061,7 +1061,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_tree_text_insert_trie.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_map
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::map</code>
+@@ -1117,7 +1117,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_tree_text_find.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_map
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::map</code>
+@@ -1225,7 +1225,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_tree_text_lor_find.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_map
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::map</code>
+@@ -1313,7 +1313,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_tree_split_join.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_set
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::set</code>
+@@ -1416,7 +1416,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_tree_order_statistics.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_set
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::set</code>
+@@ -1489,7 +1489,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_multimap_text_find_small_s2p_tree.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
+ 		    n_mmap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::multimap</code>
+@@ -1551,7 +1551,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_multimap_text_find_small_s2p_hash.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
+ 		    n_hash_mmap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_multimap</code>
+@@ -1660,7 +1660,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_multimap_text_find_large_s2p_tree.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
+ 		    n_mmap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::multimap</code>
+@@ -1722,7 +1722,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_multimap_text_find_large_s2p_hash.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
+ 		    n_hash_mmap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_multimap</code>
+@@ -1834,7 +1834,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_multimap_text_insert_small_s2p_tree.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
+ 		    n_mmap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::multimap</code>
+@@ -1896,7 +1896,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_multimap_text_find_small_s2p_hash.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
+ 		    n_hash_mmap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_multimap</code>
+@@ -2008,7 +2008,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_multimap_text_insert_large_s2p_tree.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
+ 		    n_mmap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::multimap</code>
+@@ -2070,7 +2070,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_multimap_text_find_large_s2p_hash.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
+ 		    n_hash_mmap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_multimap</code>
+@@ -2177,7 +2177,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_multimap_text_insert_mem_small_s2p_tree.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
+ 		    n_mmap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::multimap</code>
+@@ -2239,7 +2239,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_multimap_text_find_large_s2p_hash.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
+ 		    n_hash_mmap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_multimap</code>
+@@ -2346,7 +2346,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_multimap_text_insert_mem_large_s2p_tree.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
+ 		    n_mmap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::multimap</code>
+@@ -2408,7 +2408,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_multimap_text_find_large_s2p_hash.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="7" align="left">
+ 		    n_hash_mmap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::tr1::unordered_multimap</code>
+@@ -2514,7 +2514,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_text_push.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_pq_vector
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::priority_queue</code>
+@@ -2576,7 +2576,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_pairing_priority_queue_text_push.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_pq_vector
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::priority_queue</code>
+@@ -2650,7 +2650,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_text_push_pop.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_pq_vector
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::priority_queue</code>
+@@ -2712,7 +2712,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_pairing_priority_queue_text_push_pop.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_pq_vector
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::priority_queue</code> adapting <code class="classname">std::vector</code>
+@@ -2779,7 +2779,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_int_push.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_pq_vector
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::priority_queue</code>
+@@ -2841,7 +2841,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_binary_priority_queue_int_push.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_pq_vector
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::priority_queue</code> adapting <code class="classname">std::vector</code>
+@@ -2896,7 +2896,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_int_push_pop.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_pq_vector
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::priority_queue</code>
+@@ -2996,7 +2996,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_text_pop_mem.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_pq_vector
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::priority_queue</code>
+@@ -3089,7 +3089,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_text_join.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_pq_vector
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::priority_queue</code>
+@@ -3188,7 +3188,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_text_modify_up.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_pq_vector
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::priority_queue</code>
+@@ -3250,7 +3250,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_pairing_priority_queue_text_modify_up_thin.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    thin_heap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">priority_queue</code>
+@@ -3321,7 +3321,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_priority_queue_text_modify_down.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    n_pq_vector
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">std::priority_queue</code>
+@@ -3383,7 +3383,7 @@
+ 	  </p><div class="informalfigure"><div class="mediaobject" align="center"><img src="../images/pbds_pairing_priority_queue_text_modify_down_thin.png" align="middle" /></div></div><p>
+ 	    The abbreviated names in the legend of the graphic above are
+ 	    instantiated with the types in the following table.
+-	  </p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
++	  </p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left"><span class="emphasis"><em>Name/Instantiating Type</em></span></th><th align="left"><span class="emphasis"><em>Parameter</em></span></th><th align="left"><span class="emphasis"><em>Details</em></span></th></tr></thead><tbody><tr bgcolor="#B0B0B0"><td colspan="3" align="left">
+ 		    thin_heap
+ 		  </td></tr><tr><td align="left">
+ 		    <code class="classname">priority_queue</code>
+@@ -3588,7 +3588,7 @@
+ 	  underlying data structures in terms of orders of growth. It is
+ 	  interesting to note that this table implies something about the
+ 	  constants of the operations as well (see Amortized <code class="function">push</code>
+-	  and <code class="function">pop</code> operations).</p><div class="informaltable"><table border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /></colgroup><thead><tr><th align="left"> </th><th align="left"><span class="emphasis"><em><code class="function">push</code></em></span></th><th align="left"><span class="emphasis"><em><code class="function">pop</code></em></span></th><th align="left"><span class="emphasis"><em><code class="function">modify</code></em></span></th><th align="left"><span class="emphasis"><em><code class="function">erase</code></em></span></th><th align="left"><span class="emphasis"><em><code class="function">join</code></em></span></th></tr></thead><tbody><tr><td align="left">
++	  and <code class="function">pop</code> operations).</p><div class="informaltable"><table class="informaltable" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /></colgroup><thead><tr><th align="left"> </th><th align="left"><span class="emphasis"><em><code class="function">push</code></em></span></th><th align="left"><span class="emphasis"><em><code class="function">pop</code></em></span></th><th align="left"><span class="emphasis"><em><code class="function">modify</code></em></span></th><th align="left"><span class="emphasis"><em><code class="function">erase</code></em></span></th><th align="left"><span class="emphasis"><em><code class="function">join</code></em></span></th></tr></thead><tbody><tr><td align="left">
+ 		    <code class="classname">std::priority_queue</code>
+ 		  </td><td align="left">
+ 		    Θ(n) worst
+Index: libstdc++-v3/doc/html/manual/parallel_mode_design.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/parallel_mode_design.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/parallel_mode_design.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_using.html" title="Using" /><link rel="next" href="parallel_mode_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.design"></a>Design</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_using.html" title="Using" /><link rel="next" href="parallel_mode_test.html" title="Testing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_using.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.design"></a>Design</h2></div></div></div><p>
+   </p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="parallel_mode.design.intro"></a>Interface Basics</h3></div></div></div><p>
+ All parallel algorithms are intended to have signatures that are
+ equivalent to the ISO C++ algorithms replaced. For instance, the
+Index: libstdc++-v3/doc/html/manual/abi.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/abi.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/abi.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>ABI Policy and Guidelines</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, ABI, version, dynamic, shared, compatibility" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="test.html" title="Test" /><link rel="next" href="api.html" title="API Evolution and Deprecation History" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">ABI Policy and Guidelines</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="test.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>ABI Policy and Guidelines</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, ABI, version, dynamic, shared, compatibility" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="test.html" title="Test" /><link rel="next" href="api.html" title="API Evolution and Deprecation History" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">ABI Policy and Guidelines</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="test.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
+   Porting and Maintenance
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="api.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.abi"></a>ABI Policy and Guidelines</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/intro.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/intro.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/intro.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part I.  Introduction</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="index.html" title="The GNU C++ Library Manual" /><link rel="next" href="status.html" title="Chapter 1. Status" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part I. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part I.  Introduction</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="index.html" title="The GNU C++ Library Manual" /><link rel="next" href="status.html" title="Chapter 1. Status" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part I. 
+   Introduction
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="index.html">Prev</a> </td><th width="60%" align="center">The GNU C++ Library Manual</th><td width="20%" align="right"> <a accesskey="n" href="status.html">Next</a></td></tr></table><hr /></div><div class="part"><div class="titlepage"><div><div><h1 class="title"><a id="manual.intro"></a>Part I. 
+Index: libstdc++-v3/doc/html/manual/profile_mode_api.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/profile_mode_api.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/profile_mode_api.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Extensions for Custom Containers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_design.html" title="Design" /><link rel="next" href="profile_mode_cost_model.html" title="Empirical Cost Model" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Extensions for Custom Containers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_design.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_cost_model.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.api"></a>Extensions for Custom Containers</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Extensions for Custom Containers</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_design.html" title="Design" /><link rel="next" href="profile_mode_cost_model.html" title="Empirical Cost Model" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Extensions for Custom Containers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_design.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_cost_model.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.api"></a>Extensions for Custom Containers</h2></div></div></div><p>
+   Many large projects use their own data structures instead of the ones in the
+   standard library.  If these data structures are similar in functionality
+   to the standard library, they can be instrumented with the same hooks
+Index: libstdc++-v3/doc/html/manual/atomics.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/atomics.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/atomics.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 14.  Atomics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library, atomic" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="io_and_c.html" title="Interacting with C" /><link rel="next" href="concurrency.html" title="Chapter 15.  Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 14. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 14.  Atomics</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library, atomic" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="io_and_c.html" title="Interacting with C" /><link rel="next" href="concurrency.html" title="Chapter 15.  Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 14. 
+   Atomics
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io_and_c.html">Prev</a> </td><th width="60%" align="center">Part II. 
+Index: libstdc++-v3/doc/html/manual/internals.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/internals.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/internals.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Porting to New Hardware or Operating Systems</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, internals" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="documentation_hacking.html" title="Writing and Generating Documentation" /><link rel="next" href="test.html" title="Test" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Porting to New Hardware or Operating Systems</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="documentation_hacking.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Porting to New Hardware or Operating Systems</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, internals" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="documentation_hacking.html" title="Writing and Generating Documentation" /><link rel="next" href="test.html" title="Test" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Porting to New Hardware or Operating Systems</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="documentation_hacking.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
+   Porting and Maintenance
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="test.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.internals"></a>Porting to New Hardware or Operating Systems</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/policy_data_structures_using.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/policy_data_structures_using.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/policy_data_structures_using.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="next" href="policy_data_structures_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.prereq"></a>Prerequisites</h3></div></div></div><p>The library contains only header files, and does not require any
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, policy, container, data, structure, associated, tree, trie, hash, metaprogramming" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="prev" href="policy_data_structures.html" title="Chapter 22. Policy-Based Data Structures" /><link rel="next" href="policy_data_structures_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="policy_data_structures.html">Prev</a> </td><th width="60%" align="center">Chapter 22. Policy-Based Data Structures</th><td width="20%" align="right"> <a accesskey="n" href="policy_data_structures_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="containers.pbds.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="pbds.using.prereq"></a>Prerequisites</h3></div></div></div><p>The library contains only header files, and does not require any
+       other libraries except the standard C++ library . All classes are
+       defined in namespace <code class="code">__gnu_pbds</code>. The library internally
+       uses macros beginning with <code class="code">PB_DS</code>, but
+Index: libstdc++-v3/doc/html/manual/bugs.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/bugs.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/bugs.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Bugs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="status.html" title="Chapter 1. Status" /><link rel="prev" href="license.html" title="License" /><link rel="next" href="setup.html" title="Chapter 2. Setup" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Bugs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="license.html">Prev</a> </td><th width="60%" align="center">Chapter 1. Status</th><td width="20%" align="right"> <a accesskey="n" href="setup.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.bugs"></a>Bugs</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.status.bugs.impl"></a>Implementation Bugs</h3></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Bugs</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="status.html" title="Chapter 1. Status" /><link rel="prev" href="license.html" title="License" /><link rel="next" href="setup.html" title="Chapter 2. Setup" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Bugs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="license.html">Prev</a> </td><th width="60%" align="center">Chapter 1. Status</th><td width="20%" align="right"> <a accesskey="n" href="setup.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.status.bugs"></a>Bugs</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.status.bugs.impl"></a>Implementation Bugs</h3></div></div></div><p>
+       Information on known bugs, details on efforts to fix them, and
+       fixed bugs are all available as part of the <a class="link" href="http://gcc.gnu.org/bugs/" target="_top">GCC bug tracking system</a>,
+       with the category set to <code class="literal">libstdc++</code>.
+Index: libstdc++-v3/doc/html/manual/parallel_mode_using.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/parallel_mode_using.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/parallel_mode_using.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_semantics.html" title="Semantics" /><link rel="next" href="parallel_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="parallel_mode.using.prereq_flags"></a>Prerequisite Compiler Flags</h3></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode_semantics.html" title="Semantics" /><link rel="next" href="parallel_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.using"></a>Using</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="parallel_mode.using.prereq_flags"></a>Prerequisite Compiler Flags</h3></div></div></div><p>
+   Any use of parallel functionality requires additional compiler
+   and runtime support, in particular support for OpenMP. Adding this support is
+   not difficult: just compile your application with the compiler
+@@ -63,4 +63,4 @@
+ flags for atomic operations.)
+ </p><p> The following table provides the names and headers of all the
+   parallel algorithms that can be used in a similar manner:
+-</p><div class="table"><a id="table.parallel_algos"></a><p class="title"><strong>Table 18.1. Parallel Algorithms</strong></p><div class="table-contents"><table summary="Parallel Algorithms" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Algorithm</th><th align="left">Header</th><th align="left">Parallel algorithm</th><th align="left">Parallel header</th></tr></thead><tbody><tr><td align="left"><code class="function">std::accumulate</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::accumulate</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_difference</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_difference</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::inner_product</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::inner_product</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::partial_sum</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::partial_sum</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::equal</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::equal</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_first_of</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_first_of</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::for_each</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::for_each</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::lexicographical_compare</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::lexicographical_compare</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::mismatch</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::mismatch</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::transform</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::transform</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::max_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::max_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::merge</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::merge</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::min_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::min_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::nth_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::nth_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partial_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partial_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partition</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partition</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::random_shuffle</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::random_shuffle</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_union</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_union</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_intersection</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_intersection</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_symmetric_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_symmetric_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::stable_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::stable_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::unique_copy</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::unique_copy</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="parallel_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>
+\ No newline at end of file
++</p><div class="table"><a id="table.parallel_algos"></a><p class="title"><strong>Table 18.1. Parallel Algorithms</strong></p><div class="table-contents"><table class="table" summary="Parallel Algorithms" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Algorithm</th><th align="left">Header</th><th align="left">Parallel algorithm</th><th align="left">Parallel header</th></tr></thead><tbody><tr><td align="left"><code class="function">std::accumulate</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::accumulate</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_difference</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_difference</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::inner_product</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::inner_product</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::partial_sum</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="function">__gnu_parallel::partial_sum</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr><tr><td align="left"><code class="function">std::adjacent_find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::adjacent_find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::count_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::count_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::equal</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::equal</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::find_first_of</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::find_first_of</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::for_each</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::for_each</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::generate_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::generate_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::lexicographical_compare</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::lexicographical_compare</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::mismatch</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::mismatch</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::search_n</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::search_n</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::transform</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::transform</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::replace_if</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::replace_if</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::max_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::max_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::merge</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::merge</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::min_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::min_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::nth_element</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::nth_element</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partial_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partial_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::partition</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::partition</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::random_shuffle</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::random_shuffle</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_union</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_union</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_intersection</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_intersection</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_symmetric_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_symmetric_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::set_difference</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::set_difference</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::stable_sort</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::stable_sort</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr><tr><td align="left"><code class="function">std::unique_copy</code></td><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="function">__gnu_parallel::unique_copy</code></td><td align="left"><code class="filename">parallel/algorithm</code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="parallel_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="parallel_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="parallel_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>
+\ No newline at end of file
+Index: libstdc++-v3/doc/html/manual/ext_numerics.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/ext_numerics.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/ext_numerics.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 26. Numerics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_algorithms.html" title="Chapter 25. Algorithms" /><link rel="next" href="ext_iterators.html" title="Chapter 27. Iterators" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 26. Numerics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_algorithms.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 26. Numerics</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_algorithms.html" title="Chapter 25. Algorithms" /><link rel="next" href="ext_iterators.html" title="Chapter 27. Iterators" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 26. Numerics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_algorithms.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="ext_iterators.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.numerics"></a>Chapter 26. Numerics</h2></div></div></div><p>26.4, the generalized numeric operations such as <code class="code">accumulate</code>,
+Index: libstdc++-v3/doc/html/manual/parallel_mode_semantics.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/parallel_mode_semantics.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/parallel_mode_semantics.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Semantics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="next" href="parallel_mode_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Semantics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.semantics"></a>Semantics</h2></div></div></div><p> The parallel mode STL algorithms are currently not exception-safe,
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Semantics</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="prev" href="parallel_mode.html" title="Chapter 18. Parallel Mode" /><link rel="next" href="parallel_mode_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Semantics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="parallel_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 18. Parallel Mode</th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.parallel_mode.semantics"></a>Semantics</h2></div></div></div><p> The parallel mode STL algorithms are currently not exception-safe,
+ i.e. user-defined functors must not throw exceptions.
+ Also, the order of execution is not guaranteed for some functions, of course.
+ Therefore, user-defined functors should not have any concurrent side effects.
+Index: libstdc++-v3/doc/html/manual/std_contents.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/std_contents.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/std_contents.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part II.  Standard Contents</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="debug.html" title="Debugging Support" /><link rel="next" href="support.html" title="Chapter 4.  Support" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part II. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part II.  Standard Contents</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="debug.html" title="Debugging Support" /><link rel="next" href="support.html" title="Chapter 4.  Support" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part II. 
+     Standard Contents
+   </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug.html">Prev</a> </td><th width="60%" align="center">The GNU C++ Library Manual</th><td width="20%" align="right"> <a accesskey="n" href="support.html">Next</a></td></tr></table><hr /></div><div class="part"><div class="titlepage"><div><div><h1 class="title"><a id="manual.std"></a>Part II. 
+     Standard Contents
+Index: libstdc++-v3/doc/html/manual/appendix.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/appendix.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/appendix.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part IV.  Appendices</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="ext_concurrency_use.html" title="Use" /><link rel="next" href="appendix_contributing.html" title="Appendix A.  Contributing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part IV. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part IV.  Appendices</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="ext_concurrency_use.html" title="Use" /><link rel="next" href="appendix_contributing.html" title="Appendix A.  Contributing" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part IV. 
+   Appendices
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency_use.html">Prev</a> </td><th width="60%" align="center">The GNU C++ Library Manual</th><td width="20%" align="right"> <a accesskey="n" href="appendix_contributing.html">Next</a></td></tr></table><hr /></div><div class="part"><div class="titlepage"><div><div><h1 class="title"><a id="appendix"></a>Part IV. 
+   Appendices
+Index: libstdc++-v3/doc/html/manual/memory.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/memory.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/memory.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="prev" href="pairs.html" title="Pairs" /><link rel="next" href="traits.html" title="Traits" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="pairs.html">Prev</a> </td><th width="60%" align="center">Chapter 6. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Memory</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="prev" href="pairs.html" title="Pairs" /><link rel="next" href="traits.html" title="Traits" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Memory</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="pairs.html">Prev</a> </td><th width="60%" align="center">Chapter 6. 
+   Utilities
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="traits.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.memory"></a>Memory</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/api.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/api.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/api.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>API Evolution and Deprecation History</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, api, evolution, deprecation, history" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="abi.html" title="ABI Policy and Guidelines" /><link rel="next" href="backwards.html" title="Backwards Compatibility" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">API Evolution and Deprecation History</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="abi.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>API Evolution and Deprecation History</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, api, evolution, deprecation, history" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="abi.html" title="ABI Policy and Guidelines" /><link rel="next" href="backwards.html" title="Backwards Compatibility" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">API Evolution and Deprecation History</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="abi.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
+   Porting and Maintenance
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="backwards.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.api"></a>API Evolution and Deprecation History</h2></div></div></div><p>
+@@ -77,11 +77,11 @@
+    <span class="type">__alloc</span> to select an underlying allocator that
+    satisfied memory allocation requests. The selection of this
+    underlying allocator was not user-configurable.
+-   </p><div class="table"><a id="table.extension_allocators"></a><p class="title"><strong>Table B.6. Extension Allocators</strong></p><div class="table-contents"><table summary="Extension Allocators" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Allocator (3.4)</th><th align="left">Header (3.4)</th><th align="left">Allocator (3.[0-3])</th><th align="left">Header (3.[0-3])</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::new_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="classname">std::__new_alloc</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::malloc_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="classname">std::__malloc_alloc_template&lt;int&gt;</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::debug_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="classname">std::debug_alloc&lt;T&gt;</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__pool_alloc&lt;T&gt;</code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="classname">std::__default_alloc_template&lt;bool,int&gt;</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__mt_alloc&lt;T&gt;</code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left"><code class="classname">__gnu_cxx::bitmap_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr></tbody></table></div></div><br class="table-break" /><p> Releases after gcc-3.4 have continued to add to the collection
++   </p><div class="table"><a id="table.extension_allocators"></a><p class="title"><strong>Table B.6. Extension Allocators</strong></p><div class="table-contents"><table class="table" summary="Extension Allocators" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Allocator (3.4)</th><th align="left">Header (3.4)</th><th align="left">Allocator (3.[0-3])</th><th align="left">Header (3.[0-3])</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::new_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="classname">std::__new_alloc</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::malloc_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="classname">std::__malloc_alloc_template&lt;int&gt;</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::debug_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="classname">std::debug_alloc&lt;T&gt;</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__pool_alloc&lt;T&gt;</code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="classname">std::__default_alloc_template&lt;bool,int&gt;</code></td><td align="left"><code class="filename">memory</code></td></tr><tr><td align="left"><code class="classname">__gnu_cxx::__mt_alloc&lt;T&gt;</code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr><tr><td align="left"><code class="classname">__gnu_cxx::bitmap_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"> </td><td align="left"> </td></tr></tbody></table></div></div><br class="table-break" /><p> Releases after gcc-3.4 have continued to add to the collection
+    of available allocators. All of these new allocators are
+    standard-style. The following table includes details, along with
+    the first released version of GCC that included the extension allocator.
+-   </p><div class="table"><a id="table.extension_allocators2"></a><p class="title"><strong>Table B.7. Extension Allocators Continued</strong></p><div class="table-contents"><table summary="Extension Allocators Continued" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left">Allocator</th><th align="left">Include</th><th align="left">Version</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::array_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left">4.0.0</td></tr><tr><td align="left"><code class="classname">__gnu_cxx::throw_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left">4.2.0</td></tr></tbody></table></div></div><br class="table-break" /><p>
++   </p><div class="table"><a id="table.extension_allocators2"></a><p class="title"><strong>Table B.7. Extension Allocators Continued</strong></p><div class="table-contents"><table class="table" summary="Extension Allocators Continued" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /></colgroup><thead><tr><th align="left">Allocator</th><th align="left">Include</th><th align="left">Version</th></tr></thead><tbody><tr><td align="left"><code class="classname">__gnu_cxx::array_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left">4.0.0</td></tr><tr><td align="left"><code class="classname">__gnu_cxx::throw_allocator&lt;T&gt;</code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left">4.2.0</td></tr></tbody></table></div></div><br class="table-break" /><p>
+ Debug mode first appears.
+ </p><p>
+ Precompiled header support <acronym class="acronym">PCH</acronym> support.
+Index: libstdc++-v3/doc/html/manual/source_organization.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/source_organization.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/source_organization.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Directory Layout and Source Conventions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="prev" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="next" href="source_code_style.html" title="Coding Style" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Directory Layout and Source Conventions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_contributing.html">Prev</a> </td><th width="60%" align="center">Appendix A. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Directory Layout and Source Conventions</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="prev" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="next" href="source_code_style.html" title="Coding Style" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Directory Layout and Source Conventions</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_contributing.html">Prev</a> </td><th width="60%" align="center">Appendix A. 
+   Contributing
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="source_code_style.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="contrib.organization"></a>Directory Layout and Source Conventions</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/fstreams.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/fstreams.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/fstreams.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>File Based Streams</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="stringstreams.html" title="Memory Based Streams" /><link rel="next" href="io_and_c.html" title="Interacting with C" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">File Based Streams</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="stringstreams.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>File Based Streams</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="stringstreams.html" title="Memory Based Streams" /><link rel="next" href="io_and_c.html" title="Interacting with C" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">File Based Streams</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="stringstreams.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
+   Input and Output
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="io_and_c.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.filestreams"></a>File Based Streams</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.io.filestreams.copying_a_file"></a>Copying a File</h3></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/ext_demangling.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/ext_demangling.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/ext_demangling.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 29. Demangling</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_io.html" title="Chapter 28. Input and Output" /><link rel="next" href="ext_concurrency.html" title="Chapter 30. Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 29. Demangling</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_io.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 29. Demangling</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_io.html" title="Chapter 28. Input and Output" /><link rel="next" href="ext_concurrency.html" title="Chapter 30. Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 29. Demangling</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_io.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.demangle"></a>Chapter 29. Demangling</h2></div></div></div><p>
+@@ -7,7 +7,7 @@
+     original C++ source identifiers is called
+     <span class="quote">“<span class="quote">demangling.</span>�</span>
+   </p><p>
+-    If you have read the <a class="link" href="http://gcc.gnu.org/onlinedocs/libstdc++/latest-doxygen/a01115.html" target="_top">source
++    If you have read the <a class="link" href="http://gcc.gnu.org/onlinedocs/libstdc++/latest-doxygen/namespaces.html" target="_top">source
+     documentation for <code class="code">namespace abi</code></a> then you are
+     aware of the cross-vendor C++ ABI in use by GCC.  One of the
+     exposed functions is used for demangling,
+Index: libstdc++-v3/doc/html/manual/ext_preface.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/ext_preface.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/ext_preface.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="extensions.html" title="Part III.  Extensions" /><link rel="next" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="extensions.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title></title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="extensions.html" title="Part III.  Extensions" /><link rel="next" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="extensions.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="ext_compile_checks.html">Next</a></td></tr></table><hr /></div><div class="preface"><div class="titlepage"><div><div><h1 class="title"><a id="manual.ext.preface"></a></h1></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/concept_checking.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/concept_checking.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/concept_checking.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Concept Checking</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="diagnostics.html" title="Chapter 5.  Diagnostics" /><link rel="prev" href="errno.html" title="Use of errno by the library" /><link rel="next" href="utilities.html" title="Chapter 6.  Utilities" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Concept Checking</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="errno.html">Prev</a> </td><th width="60%" align="center">Chapter 5. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Concept Checking</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="diagnostics.html" title="Chapter 5.  Diagnostics" /><link rel="prev" href="errno.html" title="Use of errno by the library" /><link rel="next" href="utilities.html" title="Chapter 6.  Utilities" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Concept Checking</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="errno.html">Prev</a> </td><th width="60%" align="center">Chapter 5. 
+   Diagnostics
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="utilities.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.diagnostics.concept_checking"></a>Concept Checking</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/mt_allocator_ex_multi.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/mt_allocator_ex_multi.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/mt_allocator_ex_multi.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Multiple Thread Example</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_ex_single.html" title="Single Thread Example" /><link rel="next" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Multiple Thread Example</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_ex_single.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="bitmap_allocator.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.example_multi"></a>Multiple Thread Example</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Multiple Thread Example</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_ex_single.html" title="Single Thread Example" /><link rel="next" href="bitmap_allocator.html" title="Chapter 21. The bitmap_allocator" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Multiple Thread Example</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_ex_single.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="bitmap_allocator.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.example_multi"></a>Multiple Thread Example</h2></div></div></div><p>
+ In the ST example we never used the thread_id variable present in each block.
+ Let's start by explaining the purpose of this in a MT application.
+ </p><p>
+Index: libstdc++-v3/doc/html/manual/ext_compile_checks.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/ext_compile_checks.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/ext_compile_checks.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 16. Compile Time Checks</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_preface.html" title="" /><link rel="next" href="debug_mode.html" title="Chapter 17. Debug Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 16. Compile Time Checks</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_preface.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 16. Compile Time Checks</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_preface.html" title="" /><link rel="next" href="debug_mode.html" title="Chapter 17. Debug Mode" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 16. Compile Time Checks</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_preface.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="debug_mode.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.compile_checks"></a>Chapter 16. Compile Time Checks</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/strings.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/strings.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/strings.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 7.  Strings</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="traits.html" title="Traits" /><link rel="next" href="localization.html" title="Chapter 8.  Localization" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 7. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 7.  Strings</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="traits.html" title="Traits" /><link rel="next" href="localization.html" title="Chapter 8.  Localization" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 7. 
+   Strings
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="traits.html">Prev</a> </td><th width="60%" align="center">Part II. 
+Index: libstdc++-v3/doc/html/manual/containers_and_c.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/containers_and_c.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/containers_and_c.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9.  Containers" /><link rel="prev" href="unordered_associative.html" title="Unordered Associative" /><link rel="next" href="iterators.html" title="Chapter 10.  Iterators" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="unordered_associative.html">Prev</a> </td><th width="60%" align="center">Chapter 9. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="containers.html" title="Chapter 9.  Containers" /><link rel="prev" href="unordered_associative.html" title="Unordered Associative" /><link rel="next" href="iterators.html" title="Chapter 10.  Iterators" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="unordered_associative.html">Prev</a> </td><th width="60%" align="center">Chapter 9. 
+   Containers
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="iterators.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.c"></a>Interacting with C</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.c.vs_array"></a>Containers vs. Arrays</h3></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/profile_mode_diagnostics.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/profile_mode_diagnostics.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/profile_mode_diagnostics.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_devel.html" title="Developer Information" /><link rel="next" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Diagnostics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_devel.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.diagnostics"></a>Diagnostics</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Diagnostics</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_devel.html" title="Developer Information" /><link rel="next" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Diagnostics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_devel.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.diagnostics"></a>Diagnostics</h2></div></div></div><p>
+   The table below presents all the diagnostics we intend to implement.
+   Each diagnostic has a corresponding compile time switch
+   <code class="code">-D_GLIBCXX_PROFILE_&lt;diagnostic&gt;</code>.
+@@ -17,7 +17,7 @@
+   A high accuracy means that the diagnostic is unlikely to be wrong.
+   These grades are not perfect.  They are just meant to guide users with
+   specific needs or time budgets.
+-  </p><div class="table"><a id="table.profile_diagnostics"></a><p class="title"><strong>Table 19.2. Profile Diagnostics</strong></p><div class="table-contents"><table summary="Profile Diagnostics" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left">Group</th><th align="left">Flag</th><th align="left">Benefit</th><th align="left">Cost</th><th align="left">Freq.</th><th align="left">Implemented</th><td class="auto-generated"> </td></tr></thead><tbody><tr><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers" title="Containers">
++  </p><div class="table"><a id="table.profile_diagnostics"></a><p class="title"><strong>Table 19.2. Profile Diagnostics</strong></p><div class="table-contents"><table class="table" summary="Profile Diagnostics" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /><col align="left" class="c6" /><col align="left" class="c7" /></colgroup><thead><tr><th align="left">Group</th><th align="left">Flag</th><th align="left">Benefit</th><th align="left">Cost</th><th align="left">Freq.</th><th align="left">Implemented</th><td class="auto-generated"> </td></tr></thead><tbody><tr><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.containers" title="Containers">
+     CONTAINERS</a></td><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_small" title="Hashtable Too Small">
+     HASHTABLE_TOO_SMALL</a></td><td align="left">10</td><td align="left">1</td><td align="left"> </td><td align="left">10</td><td align="left">yes</td></tr><tr><td align="left"> </td><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.hashtable_too_large" title="Hashtable Too Large">
+     HASHTABLE_TOO_LARGE</a></td><td align="left">5</td><td align="left">1</td><td align="left"> </td><td align="left">10</td><td align="left">yes</td></tr><tr><td align="left"> </td><td align="left"><a class="link" href="profile_mode_diagnostics.html#manual.ext.profile_mode.analysis.inefficient_hash" title="Inefficient Hash">
+Index: libstdc++-v3/doc/html/manual/ext_concurrency_impl.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="next" href="ext_concurrency_use.html" title="Use" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency_use.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.concurrency.impl.atomic_fallbacks"></a>Using Built-in Atomic Functions</h3></div></div></div><p>The functions for atomic operations described above are either
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="prev" href="ext_concurrency.html" title="Chapter 30. Concurrency" /><link rel="next" href="ext_concurrency_use.html" title="Use" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_concurrency.html">Prev</a> </td><th width="60%" align="center">Chapter 30. Concurrency</th><td width="20%" align="right"> <a accesskey="n" href="ext_concurrency_use.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.concurrency.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.concurrency.impl.atomic_fallbacks"></a>Using Built-in Atomic Functions</h3></div></div></div><p>The functions for atomic operations described above are either
+ implemented via compiler intrinsics (if the underlying host is
+ capable) or by library fallbacks.</p><p>Compiler intrinsics (builtins) are always preferred.  However, as
+ the compiler builtins for atomics are not universally implemented,
+Index: libstdc++-v3/doc/html/manual/io_and_c.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/io_and_c.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/io_and_c.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="fstreams.html" title="File Based Streams" /><link rel="next" href="atomics.html" title="Chapter 14.  Atomics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="fstreams.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="fstreams.html" title="File Based Streams" /><link rel="next" href="atomics.html" title="Chapter 14.  Atomics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="fstreams.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
+   Input and Output
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="atomics.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.c"></a>Interacting with C</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.io.c.FILE"></a>Using FILE* and file descriptors</h3></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/documentation_hacking.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/documentation_hacking.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/documentation_hacking.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Writing and Generating Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, documentation, style, docbook, doxygen" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="next" href="internals.html" title="Porting to New Hardware or Operating Systems" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Writing and Generating Documentation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_porting.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Writing and Generating Documentation</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, documentation, style, docbook, doxygen" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="next" href="internals.html" title="Porting to New Hardware or Operating Systems" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Writing and Generating Documentation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_porting.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
+   Porting and Maintenance
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="internals.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="appendix.porting.doc"></a>Writing and Generating Documentation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.intro"></a>Introduction</h3></div></div></div><p>
+@@ -112,7 +112,7 @@
+       supported, and are always aliased to dummy rules. These
+       unsupported formats are: <span class="emphasis"><em>info</em></span>,
+       <span class="emphasis"><em>ps</em></span>, and <span class="emphasis"><em>dvi</em></span>.
+-    </p></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.doxygen"></a>Doxygen</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="doxygen.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="table.doxygen_prereq"></a><p class="title"><strong>Table B.1. Doxygen Prerequisites</strong></p><div class="table-contents"><table summary="Doxygen Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">coreutils</td><td align="center">8.5</td><td align="center">all</td></tr><tr><td align="center">bash</td><td align="center">4.1</td><td align="center">all</td></tr><tr><td align="center">doxygen</td><td align="center">1.7.6.1</td><td align="center">all</td></tr><tr><td align="center">graphviz</td><td align="center">2.26</td><td align="center">graphical hierarchies</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr></tbody></table></div></div><br class="table-break" /><p>
++    </p></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.doxygen"></a>Doxygen</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="doxygen.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="table.doxygen_prereq"></a><p class="title"><strong>Table B.1. Doxygen Prerequisites</strong></p><div class="table-contents"><table class="table" summary="Doxygen Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">coreutils</td><td align="center">8.5</td><td align="center">all</td></tr><tr><td align="center">bash</td><td align="center">4.1</td><td align="center">all</td></tr><tr><td align="center">doxygen</td><td align="center">1.7.6.1</td><td align="center">all</td></tr><tr><td align="center">graphviz</td><td align="center">2.26</td><td align="center">graphical hierarchies</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr></tbody></table></div></div><br class="table-break" /><p>
+ 	Prerequisite tools are Bash 2.0 or later,
+ 	<a class="link" href="http://www.doxygen.org/" target="_top">Doxygen</a>, and
+ 	the <a class="link" href="http://www.gnu.org/software/coreutils/" target="_top">GNU
+@@ -322,7 +322,7 @@
+ 	writing Doxygen comments. Single and double quotes, and
+ 	separators in filenames are two common trouble spots. When in
+ 	doubt, consult the following table.
+-      </p><div class="table"><a id="table.doxygen_cmp"></a><p class="title"><strong>Table B.2. HTML to Doxygen Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Doxygen Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Doxygen</th></tr></thead><tbody><tr><td align="left">\</td><td align="left">\\</td></tr><tr><td align="left">"</td><td align="left">\"</td></tr><tr><td align="left">'</td><td align="left">\'</td></tr><tr><td align="left">&lt;i&gt;</td><td align="left">@a word</td></tr><tr><td align="left">&lt;b&gt;</td><td align="left">@b word</td></tr><tr><td align="left">&lt;code&gt;</td><td align="left">@c word</td></tr><tr><td align="left">&lt;em&gt;</td><td align="left">@a word</td></tr><tr><td align="left">&lt;em&gt;</td><td align="left">&lt;em&gt;two words or more&lt;/em&gt;</td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.docbook"></a>Docbook</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="docbook.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="table.docbook_prereq"></a><p class="title"><strong>Table B.3. Docbook Prerequisites</strong></p><div class="table-contents"><table summary="Docbook Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">docbook5-style-xsl</td><td align="center">1.76.1</td><td align="center">all</td></tr><tr><td align="center">xsltproc</td><td align="center">1.1.26</td><td align="center">all</td></tr><tr><td align="center">xmllint</td><td align="center">2.7.7</td><td align="center">validation</td></tr><tr><td align="center">dblatex</td><td align="center">0.3</td><td align="center">pdf output</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr><tr><td align="center">docbook2X</td><td align="center">0.8.8</td><td align="center">info output</td></tr><tr><td align="center">epub3 stylesheets</td><td align="center">b3</td><td align="center">epub output</td></tr></tbody></table></div></div><br class="table-break" /><p>
++      </p><div class="table"><a id="table.doxygen_cmp"></a><p class="title"><strong>Table B.2. HTML to Doxygen Markup Comparison</strong></p><div class="table-contents"><table class="table" summary="HTML to Doxygen Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Doxygen</th></tr></thead><tbody><tr><td align="left">\</td><td align="left">\\</td></tr><tr><td align="left">"</td><td align="left">\"</td></tr><tr><td align="left">'</td><td align="left">\'</td></tr><tr><td align="left">&lt;i&gt;</td><td align="left">@a word</td></tr><tr><td align="left">&lt;b&gt;</td><td align="left">@b word</td></tr><tr><td align="left">&lt;code&gt;</td><td align="left">@c word</td></tr><tr><td align="left">&lt;em&gt;</td><td align="left">@a word</td></tr><tr><td align="left">&lt;em&gt;</td><td align="left">&lt;em&gt;two words or more&lt;/em&gt;</td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="doc.docbook"></a>Docbook</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="docbook.prereq"></a>Prerequisites</h4></div></div></div><div class="table"><a id="table.docbook_prereq"></a><p class="title"><strong>Table B.3. Docbook Prerequisites</strong></p><div class="table-contents"><table class="table" summary="Docbook Prerequisites" border="1"><colgroup><col align="center" class="c1" /><col align="center" class="c2" /><col align="center" class="c3" /></colgroup><thead><tr><th align="center">Tool</th><th align="center">Version</th><th align="center">Required By</th></tr></thead><tbody><tr><td align="center">docbook5-style-xsl</td><td align="center">1.76.1</td><td align="center">all</td></tr><tr><td align="center">xsltproc</td><td align="center">1.1.26</td><td align="center">all</td></tr><tr><td align="center">xmllint</td><td align="center">2.7.7</td><td align="center">validation</td></tr><tr><td align="center">dblatex</td><td align="center">0.3</td><td align="center">pdf output</td></tr><tr><td align="center">pdflatex</td><td align="center">2007-59</td><td align="center">pdf output</td></tr><tr><td align="center">docbook2X</td><td align="center">0.8.8</td><td align="center">info output</td></tr><tr><td align="center">epub3 stylesheets</td><td align="center">b3</td><td align="center">epub output</td></tr></tbody></table></div></div><br class="table-break" /><p>
+ 	Editing the DocBook sources requires an XML editor. Many
+ 	exist: some notable options
+ 	include <span class="command"><strong>emacs</strong></span>, <span class="application">Kate</span>,
+@@ -532,11 +532,11 @@
+ 	<a class="link" href="http://www.docbook.org/tdg/en/html/part2.html" target="_top">online</a>.
+ 	An incomplete reference for HTML to Docbook conversion is
+ 	detailed in the table below.
+-      </p><div class="table"><a id="table.docbook_cmp"></a><p class="title"><strong>Table B.4. HTML to Docbook XML Markup Comparison</strong></p><div class="table-contents"><table summary="HTML to Docbook XML Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Docbook</th></tr></thead><tbody><tr><td align="left">&lt;p&gt;</td><td align="left">&lt;para&gt;</td></tr><tr><td align="left">&lt;pre&gt;</td><td align="left">&lt;computeroutput&gt;, &lt;programlisting&gt;,
++      </p><div class="table"><a id="table.docbook_cmp"></a><p class="title"><strong>Table B.4. HTML to Docbook XML Markup Comparison</strong></p><div class="table-contents"><table class="table" summary="HTML to Docbook XML Markup Comparison" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">HTML</th><th align="left">Docbook</th></tr></thead><tbody><tr><td align="left">&lt;p&gt;</td><td align="left">&lt;para&gt;</td></tr><tr><td align="left">&lt;pre&gt;</td><td align="left">&lt;computeroutput&gt;, &lt;programlisting&gt;,
+ 	&lt;literallayout&gt;</td></tr><tr><td align="left">&lt;ul&gt;</td><td align="left">&lt;itemizedlist&gt;</td></tr><tr><td align="left">&lt;ol&gt;</td><td align="left">&lt;orderedlist&gt;</td></tr><tr><td align="left">&lt;il&gt;</td><td align="left">&lt;listitem&gt;</td></tr><tr><td align="left">&lt;dl&gt;</td><td align="left">&lt;variablelist&gt;</td></tr><tr><td align="left">&lt;dt&gt;</td><td align="left">&lt;term&gt;</td></tr><tr><td align="left">&lt;dd&gt;</td><td align="left">&lt;listitem&gt;</td></tr><tr><td align="left">&lt;a href=""&gt;</td><td align="left">&lt;ulink url=""&gt;</td></tr><tr><td align="left">&lt;code&gt;</td><td align="left">&lt;literal&gt;, &lt;programlisting&gt;</td></tr><tr><td align="left">&lt;strong&gt;</td><td align="left">&lt;emphasis&gt;</td></tr><tr><td align="left">&lt;em&gt;</td><td align="left">&lt;emphasis&gt;</td></tr><tr><td align="left">"</td><td align="left">&lt;quote&gt;</td></tr></tbody></table></div></div><br class="table-break" /><p>
+   And examples of detailed markup for which there are no real HTML
+   equivalents are listed in the table below.
+-</p><div class="table"><a id="table.docbook_elem"></a><p class="title"><strong>Table B.5. Docbook XML Element Use</strong></p><div class="table-contents"><table summary="Docbook XML Element Use" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Element</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left">&lt;structname&gt;</td><td align="left">&lt;structname&gt;char_traits&lt;/structname&gt;</td></tr><tr><td align="left">&lt;classname&gt;</td><td align="left">&lt;classname&gt;string&lt;/classname&gt;</td></tr><tr><td align="left">&lt;function&gt;</td><td align="left">
++</p><div class="table"><a id="table.docbook_elem"></a><p class="title"><strong>Table B.5. Docbook XML Element Use</strong></p><div class="table-contents"><table class="table" summary="Docbook XML Element Use" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Element</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left">&lt;structname&gt;</td><td align="left">&lt;structname&gt;char_traits&lt;/structname&gt;</td></tr><tr><td align="left">&lt;classname&gt;</td><td align="left">&lt;classname&gt;string&lt;/classname&gt;</td></tr><tr><td align="left">&lt;function&gt;</td><td align="left">
+ 	<p>&lt;function&gt;clear()&lt;/function&gt;</p>
+ 	<p>&lt;function&gt;fs.clear()&lt;/function&gt;</p>
+       </td></tr><tr><td align="left">&lt;type&gt;</td><td align="left">&lt;type&gt;long long&lt;/type&gt;</td></tr><tr><td align="left">&lt;varname&gt;</td><td align="left">&lt;varname&gt;fs&lt;/varname&gt;</td></tr><tr><td align="left">&lt;literal&gt;</td><td align="left">
+Index: libstdc++-v3/doc/html/manual/extensions.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/extensions.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/extensions.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part III.  Extensions</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="io_and_c.html" title="Interacting with C" /><link rel="next" href="ext_preface.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Part III.  Extensions</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="index.html" title="The GNU C++ Library Manual" /><link rel="prev" href="io_and_c.html" title="Interacting with C" /><link rel="next" href="ext_preface.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Part III. 
+   Extensions
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io_and_c.html">Prev</a> </td><th width="60%" align="center">The GNU C++ Library Manual</th><td width="20%" align="right"> <a accesskey="n" href="ext_preface.html">Next</a></td></tr></table><hr /></div><div class="part"><div class="titlepage"><div><div><h1 class="title"><a id="manual.ext"></a>Part III. 
+Index: libstdc++-v3/doc/html/manual/debug_mode_using.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/debug_mode_using.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/debug_mode_using.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_semantics.html" title="Semantics" /><link rel="next" href="debug_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.using"></a>Using</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Using</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode_semantics.html" title="Semantics" /><link rel="next" href="debug_mode_design.html" title="Design" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Using</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.using"></a>Using</h2></div></div></div><p>
+   </p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="debug_mode.using.mode"></a>Using the Debug Mode</h3></div></div></div><p>To use the libstdc++ debug mode, compile your application with the
+   compiler flag <code class="code">-D_GLIBCXX_DEBUG</code>. Note that this flag
+   changes the sizes and behavior of standard class templates such
+@@ -18,6 +18,6 @@
+   mode or with debug mode. The
+   following table provides the names and headers of the debugging
+   containers:
+-</p><div class="table"><a id="table.debug_mode_containers"></a><p class="title"><strong>Table 17.1. Debugging Containers</strong></p><div class="table-contents"><table summary="Debugging Containers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::bitset</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="classname">__gnu_debug::bitset</code></td><td align="left"><code class="filename">&lt;debug/bitset&gt;</code></td></tr><tr><td align="left"><code class="classname">std::deque</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="classname">__gnu_debug::deque</code></td><td align="left"><code class="filename">&lt;debug/deque&gt;</code></td></tr><tr><td align="left"><code class="classname">std::list</code></td><td align="left"><code class="filename">list</code></td><td align="left"><code class="classname">__gnu_debug::list</code></td><td align="left"><code class="filename">&lt;debug/list&gt;</code></td></tr><tr><td align="left"><code class="classname">std::map</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::map</code></td><td align="left"><code class="filename">&lt;debug/map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::multimap</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::multimap</code></td><td align="left"><code class="filename">&lt;debug/map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::multiset</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::multiset</code></td><td align="left"><code class="filename">&lt;debug/set&gt;</code></td></tr><tr><td align="left"><code class="classname">std::set</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::set</code></td><td align="left"><code class="filename">&lt;debug/set&gt;</code></td></tr><tr><td align="left"><code class="classname">std::string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::string</code></td><td align="left"><code class="filename">&lt;debug/string&gt;</code></td></tr><tr><td align="left"><code class="classname">std::wstring</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::wstring</code></td><td align="left"><code class="filename">&lt;debug/string&gt;</code></td></tr><tr><td align="left"><code class="classname">std::basic_string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::basic_string</code></td><td align="left"><code class="filename">&lt;debug/string&gt;</code></td></tr><tr><td align="left"><code class="classname">std::vector</code></td><td align="left"><code class="filename">vector</code></td><td align="left"><code class="classname">__gnu_debug::vector</code></td><td align="left"><code class="filename">&lt;debug/vector&gt;</code></td></tr></tbody></table></div></div><br class="table-break" /><p>In addition, when compiling in C++11 mode, these additional
++</p><div class="table"><a id="table.debug_mode_containers"></a><p class="title"><strong>Table 17.1. Debugging Containers</strong></p><div class="table-contents"><table class="table" summary="Debugging Containers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::bitset</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="classname">__gnu_debug::bitset</code></td><td align="left"><code class="filename">&lt;debug/bitset&gt;</code></td></tr><tr><td align="left"><code class="classname">std::deque</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="classname">__gnu_debug::deque</code></td><td align="left"><code class="filename">&lt;debug/deque&gt;</code></td></tr><tr><td align="left"><code class="classname">std::list</code></td><td align="left"><code class="filename">list</code></td><td align="left"><code class="classname">__gnu_debug::list</code></td><td align="left"><code class="filename">&lt;debug/list&gt;</code></td></tr><tr><td align="left"><code class="classname">std::map</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::map</code></td><td align="left"><code class="filename">&lt;debug/map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::multimap</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="classname">__gnu_debug::multimap</code></td><td align="left"><code class="filename">&lt;debug/map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::multiset</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::multiset</code></td><td align="left"><code class="filename">&lt;debug/set&gt;</code></td></tr><tr><td align="left"><code class="classname">std::set</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="classname">__gnu_debug::set</code></td><td align="left"><code class="filename">&lt;debug/set&gt;</code></td></tr><tr><td align="left"><code class="classname">std::string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::string</code></td><td align="left"><code class="filename">&lt;debug/string&gt;</code></td></tr><tr><td align="left"><code class="classname">std::wstring</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::wstring</code></td><td align="left"><code class="filename">&lt;debug/string&gt;</code></td></tr><tr><td align="left"><code class="classname">std::basic_string</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="classname">__gnu_debug::basic_string</code></td><td align="left"><code class="filename">&lt;debug/string&gt;</code></td></tr><tr><td align="left"><code class="classname">std::vector</code></td><td align="left"><code class="filename">vector</code></td><td align="left"><code class="classname">__gnu_debug::vector</code></td><td align="left"><code class="filename">&lt;debug/vector&gt;</code></td></tr></tbody></table></div></div><br class="table-break" /><p>In addition, when compiling in C++11 mode, these additional
+ containers have additional debug capability.
+-</p><div class="table"><a id="table.debug_mode_containers_cxx11"></a><p class="title"><strong>Table 17.2. Debugging Containers C++11</strong></p><div class="table-contents"><table summary="Debugging Containers C++11" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::unordered_map</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_map</code></td><td align="left"><code class="filename">&lt;debug/unordered_map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::unordered_multimap</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multimap</code></td><td align="left"><code class="filename">&lt;debug/unordered_map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::unordered_set</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_set</code></td><td align="left"><code class="filename">&lt;debug/unordered_set&gt;</code></td></tr><tr><td align="left"><code class="classname">std::unordered_multiset</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multiset</code></td><td align="left"><code class="filename">&lt;debug/unordered_set&gt;</code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="debug_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>
+\ No newline at end of file
++</p><div class="table"><a id="table.debug_mode_containers_cxx11"></a><p class="title"><strong>Table 17.2. Debugging Containers C++11</strong></p><div class="table-contents"><table class="table" summary="Debugging Containers C++11" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><thead><tr><th align="left">Container</th><th align="left">Header</th><th align="left">Debug container</th><th align="left">Debug header</th></tr></thead><tbody><tr><td align="left"><code class="classname">std::unordered_map</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_map</code></td><td align="left"><code class="filename">&lt;debug/unordered_map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::unordered_multimap</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multimap</code></td><td align="left"><code class="filename">&lt;debug/unordered_map&gt;</code></td></tr><tr><td align="left"><code class="classname">std::unordered_set</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_set</code></td><td align="left"><code class="filename">&lt;debug/unordered_set&gt;</code></td></tr><tr><td align="left"><code class="classname">std::unordered_multiset</code></td><td align="left"><code class="filename">unordered_set</code></td><td align="left"><code class="classname">__gnu_debug::unordered_multiset</code></td><td align="left"><code class="filename">&lt;debug/unordered_set&gt;</code></td></tr></tbody></table></div></div><br class="table-break" /></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="debug_mode_semantics.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="debug_mode.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="debug_mode_design.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Semantics </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Design</td></tr></table></div></body></html>
+\ No newline at end of file
+Index: libstdc++-v3/doc/html/manual/debug_mode_semantics.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/debug_mode_semantics.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/debug_mode_semantics.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Semantics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="next" href="debug_mode_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Semantics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.semantics"></a>Semantics</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Semantics</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="prev" href="debug_mode.html" title="Chapter 17. Debug Mode" /><link rel="next" href="debug_mode_using.html" title="Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Semantics</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 17. Debug Mode</th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.debug_mode.semantics"></a>Semantics</h2></div></div></div><p>
+   </p><p>A program that uses the C++ standard library correctly
+   will maintain the same semantics under debug mode as it had with
+   the normal (release) library. All functional and exception-handling
+Index: libstdc++-v3/doc/html/manual/parallel_mode.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/parallel_mode.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/parallel_mode.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 18. Parallel Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="debug_mode_design.html" title="Design" /><link rel="next" href="parallel_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 18. Parallel Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_design.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 18. Parallel Mode</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, parallel" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="debug_mode_design.html" title="Design" /><link rel="next" href="parallel_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 18. Parallel Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="debug_mode_design.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="parallel_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.parallel_mode"></a>Chapter 18. Parallel Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="parallel_mode.html#manual.ext.parallel_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="parallel_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.prereq_flags">Prerequisite Compiler Flags</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.parallel_mode">Using Parallel Mode</a></span></dt><dt><span class="section"><a href="parallel_mode_using.html#parallel_mode.using.specific">Using Specific Parallel Components</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.intro">Interface Basics</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning">Configuration and Tuning</a></span></dt><dd><dl><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.omp">Setting up the OpenMP Environment</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.compile">Compile Time Switches</a></span></dt><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.tuning.settings">Run Time Settings and Defaults</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_design.html#parallel_mode.design.impl">Implementation Namespaces</a></span></dt></dl></dd><dt><span class="section"><a href="parallel_mode_test.html">Testing</a></span></dt><dt><span class="bibliography"><a href="parallel_mode.html#parallel_mode.biblio">Bibliography</a></span></dt></dl></div><p> The libstdc++ parallel mode is an experimental parallel
+Index: libstdc++-v3/doc/html/manual/setup.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/setup.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/setup.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 2. Setup</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I.  Introduction" /><link rel="prev" href="bugs.html" title="Bugs" /><link rel="next" href="configure.html" title="Configure" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 2. Setup</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bugs.html">Prev</a> </td><th width="60%" align="center">Part I. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 2. Setup</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="intro.html" title="Part I.  Introduction" /><link rel="prev" href="bugs.html" title="Bugs" /><link rel="next" href="configure.html" title="Configure" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 2. Setup</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="bugs.html">Prev</a> </td><th width="60%" align="center">Part I. 
+   Introduction
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="configure.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.intro.setup"></a>Chapter 2. Setup</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="setup.html#manual.intro.setup.prereq">Prerequisites</a></span></dt><dt><span class="section"><a href="configure.html">Configure</a></span></dt><dt><span class="section"><a href="make.html">Make</a></span></dt></dl></div><p>To transform libstdc++ sources into installed include files
+Index: libstdc++-v3/doc/html/manual/backwards.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/backwards.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/backwards.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Backwards Compatibility</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, backwards" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="api.html" title="API Evolution and Deprecation History" /><link rel="next" href="appendix_free.html" title="Appendix C.  Free Software Needs Free Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Backwards Compatibility</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Backwards Compatibility</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, backwards" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="api.html" title="API Evolution and Deprecation History" /><link rel="next" href="appendix_free.html" title="Appendix C.  Free Software Needs Free Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Backwards Compatibility</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="api.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
+   Porting and Maintenance
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="appendix_free.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.appendix.porting.backwards"></a>Backwards Compatibility</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="backwards.first"></a>First</h3></div></div></div><p>The first generation GNU C++ library was called libg++.  It was a
+Index: libstdc++-v3/doc/html/manual/source_design_notes.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/source_design_notes.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/source_design_notes.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Notes</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="prev" href="source_code_style.html" title="Coding Style" /><link rel="next" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Notes</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_code_style.html">Prev</a> </td><th width="60%" align="center">Appendix A. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Notes</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="prev" href="source_code_style.html" title="Coding Style" /><link rel="next" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Notes</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_code_style.html">Prev</a> </td><th width="60%" align="center">Appendix A. 
+   Contributing
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="appendix_porting.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="contrib.design_notes"></a>Design Notes</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/ext_sgi.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/ext_sgi.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/ext_sgi.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Deprecated</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="prev" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="next" href="ext_utilities.html" title="Chapter 24. Utilities" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Deprecated</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_containers.html">Prev</a> </td><th width="60%" align="center">Chapter 23. HP/SGI Extensions</th><td width="20%" align="right"> <a accesskey="n" href="ext_utilities.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.deprecated_sgi"></a>Deprecated</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Deprecated</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="prev" href="ext_containers.html" title="Chapter 23. HP/SGI Extensions" /><link rel="next" href="ext_utilities.html" title="Chapter 24. Utilities" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Deprecated</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_containers.html">Prev</a> </td><th width="60%" align="center">Chapter 23. HP/SGI Extensions</th><td width="20%" align="right"> <a accesskey="n" href="ext_utilities.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.containers.deprecated_sgi"></a>Deprecated</h2></div></div></div><p>
+      The SGI hashing classes <code class="classname">hash_set</code> and
+      <code class="classname">hash_set</code> have been deprecated by the
+      unordered_set, unordered_multiset, unordered_map,
+Index: libstdc++-v3/doc/html/manual/facets.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/facets.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/facets.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Facets</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="localization.html" title="Chapter 8.  Localization" /><link rel="prev" href="localization.html" title="Chapter 8.  Localization" /><link rel="next" href="containers.html" title="Chapter 9.  Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Facets</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="localization.html">Prev</a> </td><th width="60%" align="center">Chapter 8. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Facets</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="localization.html" title="Chapter 8.  Localization" /><link rel="prev" href="localization.html" title="Chapter 8.  Localization" /><link rel="next" href="containers.html" title="Chapter 9.  Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Facets</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="localization.html">Prev</a> </td><th width="60%" align="center">Chapter 8. 
+   Localization
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="containers.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.localization.facet"></a>Facets</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="std.localization.facet.ctype"></a>ctype</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="facet.ctype.impl"></a>Implementation</h4></div></div></div><div class="section"><div class="titlepage"><div><div><h5 class="title"><a id="facet.ctype.impl.spec"></a>Specializations</h5></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/using_dual_abi.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/using_dual_abi.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/using_dual_abi.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Dual ABI</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_macros.html" title="Macros" /><link rel="next" href="using_namespaces.html" title="Namespaces" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Dual ABI</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_macros.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_namespaces.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.abi"></a>Dual ABI</h2></div></div></div><p> In the GCC 5.1 release libstdc++ introduced a new library ABI that
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Dual ABI</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_macros.html" title="Macros" /><link rel="next" href="using_namespaces.html" title="Namespaces" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Dual ABI</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_macros.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_namespaces.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.abi"></a>Dual ABI</h2></div></div></div><p> In the GCC 5.1 release libstdc++ introduced a new library ABI that
+   includes new implementations of <code class="classname">std::string</code> and
+   <code class="classname">std::list</code>. These changes were necessary to conform
+   to the 2011 C++ standard which forbids Copy-On-Write strings and requires
+Index: libstdc++-v3/doc/html/manual/diagnostics.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/diagnostics.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/diagnostics.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 5.  Diagnostics</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="termination.html" title="Termination" /><link rel="next" href="errno.html" title="Use of errno by the library" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 5. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 5.  Diagnostics</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="termination.html" title="Termination" /><link rel="next" href="errno.html" title="Use of errno by the library" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 5. 
+   Diagnostics
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="termination.html">Prev</a> </td><th width="60%" align="center">Part II. 
+Index: libstdc++-v3/doc/html/manual/mt_allocator_design.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/mt_allocator_design.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/mt_allocator_design.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Issues</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="next" href="mt_allocator_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.design_issues"></a>Design Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.overview"></a>Overview</h3></div></div></div><p> There are three general components to the allocator: a datum
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design Issues</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="next" href="mt_allocator_impl.html" title="Implementation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design Issues</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.design_issues"></a>Design Issues</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.overview"></a>Overview</h3></div></div></div><p> There are three general components to the allocator: a datum
+ describing the characteristics of the memory pool, a policy class
+ containing this pool that links instantiation types to common or
+ individual pools, and a class inheriting from the policy class that is
+Index: libstdc++-v3/doc/html/manual/appendix_free.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/appendix_free.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/appendix_free.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix C.  Free Software Needs Free Documentation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="backwards.html" title="Backwards Compatibility" /><link rel="next" href="appendix_gpl.html" title="Appendix D.  GNU General Public License version 3" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix C. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix C.  Free Software Needs Free Documentation</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="backwards.html" title="Backwards Compatibility" /><link rel="next" href="appendix_gpl.html" title="Appendix D.  GNU General Public License version 3" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix C. 
+   Free Software Needs Free Documentation
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="backwards.html">Prev</a> </td><th width="60%" align="center">Part IV. 
+Index: libstdc++-v3/doc/html/manual/algorithms.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/algorithms.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/algorithms.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 11.  Algorithms</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library, algorithm" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="iterators.html" title="Chapter 10.  Iterators" /><link rel="next" href="numerics.html" title="Chapter 12.  Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 11. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 11.  Algorithms</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library, algorithm" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="iterators.html" title="Chapter 10.  Iterators" /><link rel="next" href="numerics.html" title="Chapter 12.  Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 11. 
+   Algorithms
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="iterators.html">Prev</a> </td><th width="60%" align="center">Part II. 
+Index: libstdc++-v3/doc/html/manual/appendix_porting.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/appendix_porting.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/appendix_porting.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix B.  Porting and Maintenance</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="source_design_notes.html" title="Design Notes" /><link rel="next" href="documentation_hacking.html" title="Writing and Generating Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix B. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix B.  Porting and Maintenance</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="source_design_notes.html" title="Design Notes" /><link rel="next" href="documentation_hacking.html" title="Writing and Generating Documentation" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix B. 
+   Porting and Maintenance
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_design_notes.html">Prev</a> </td><th width="60%" align="center">Part IV. 
+Index: libstdc++-v3/doc/html/manual/profile_mode_cost_model.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/profile_mode_cost_model.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/profile_mode_cost_model.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Empirical Cost Model</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_api.html" title="Extensions for Custom Containers" /><link rel="next" href="profile_mode_impl.html" title="Implementation Issues" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Empirical Cost Model</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_api.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.cost_model"></a>Empirical Cost Model</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Empirical Cost Model</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode_api.html" title="Extensions for Custom Containers" /><link rel="next" href="profile_mode_impl.html" title="Implementation Issues" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Empirical Cost Model</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode_api.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_impl.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.cost_model"></a>Empirical Cost Model</h2></div></div></div><p>
+   Currently, the cost model uses formulas with predefined relative weights
+   for alternative containers or container implementations.  For instance,
+   iterating through a vector is X times faster than iterating through a list.
+Index: libstdc++-v3/doc/html/manual/make.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/make.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/make.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Make</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="setup.html" title="Chapter 2. Setup" /><link rel="prev" href="configure.html" title="Configure" /><link rel="next" href="using.html" title="Chapter 3. Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Make</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="configure.html">Prev</a> </td><th width="60%" align="center">Chapter 2. Setup</th><td width="20%" align="right"> <a accesskey="n" href="using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.make"></a>Make</h2></div></div></div><p>If you have never done this before, you should read the basic
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Make</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="setup.html" title="Chapter 2. Setup" /><link rel="prev" href="configure.html" title="Configure" /><link rel="next" href="using.html" title="Chapter 3. Using" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Make</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="configure.html">Prev</a> </td><th width="60%" align="center">Chapter 2. Setup</th><td width="20%" align="right"> <a accesskey="n" href="using.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.make"></a>Make</h2></div></div></div><p>If you have never done this before, you should read the basic
+       <a class="link" href="http://gcc.gnu.org/install/" target="_top">GCC Installation
+       Instructions</a> first.  Read <span class="emphasis"><em>all of them</em></span>.
+       <span class="emphasis"><em>Twice.</em></span>
+Index: libstdc++-v3/doc/html/manual/pairs.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/pairs.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/pairs.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Pairs</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="prev" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="next" href="memory.html" title="Memory" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Pairs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="utilities.html">Prev</a> </td><th width="60%" align="center">Chapter 6. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Pairs</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="prev" href="utilities.html" title="Chapter 6.  Utilities" /><link rel="next" href="memory.html" title="Memory" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Pairs</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="utilities.html">Prev</a> </td><th width="60%" align="center">Chapter 6. 
+   Utilities
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="memory.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.util.pairs"></a>Pairs</h2></div></div></div><p>The <code class="code">pair&lt;T1,T2&gt;</code> is a simple and handy way to
+Index: libstdc++-v3/doc/html/manual/test.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/test.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/test.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Test</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, test, testsuite, performance, conformance, ABI, exception safety" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="internals.html" title="Porting to New Hardware or Operating Systems" /><link rel="next" href="abi.html" title="ABI Policy and Guidelines" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Test</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="internals.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Test</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, test, testsuite, performance, conformance, ABI, exception safety" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_porting.html" title="Appendix B.  Porting and Maintenance" /><link rel="prev" href="internals.html" title="Porting to New Hardware or Operating Systems" /><link rel="next" href="abi.html" title="ABI Policy and Guidelines" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Test</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="internals.html">Prev</a> </td><th width="60%" align="center">Appendix B. 
+   Porting and Maintenance
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="abi.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.setup.test"></a>Test</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/using_dynamic_or_shared.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/using_dynamic_or_shared.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/using_dynamic_or_shared.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Linking</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_namespaces.html" title="Namespaces" /><link rel="next" href="using_concurrency.html" title="Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Linking</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_namespaces.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_concurrency.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.linkage"></a>Linking</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.linkage.freestanding"></a>Almost Nothing</h3></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Linking</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_namespaces.html" title="Namespaces" /><link rel="next" href="using_concurrency.html" title="Concurrency" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Linking</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_namespaces.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_concurrency.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.linkage"></a>Linking</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.linkage.freestanding"></a>Almost Nothing</h3></div></div></div><p>
+ 	Or as close as it gets: freestanding. This is a minimal
+ 	configuration, with only partial support for the standard
+ 	library. Assume only the following header files can be used:
+Index: libstdc++-v3/doc/html/manual/using_headers.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/using_headers.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/using_headers.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Headers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using.html" title="Chapter 3. Using" /><link rel="next" href="using_macros.html" title="Macros" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Headers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_macros.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.headers"></a>Headers</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.all"></a>Header Files</h3></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Headers</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using.html" title="Chapter 3. Using" /><link rel="next" href="using_macros.html" title="Macros" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Headers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_macros.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.headers"></a>Headers</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.all"></a>Header Files</h3></div></div></div><p>
+      The C++ standard specifies the entire set of header files that
+      must be available to all hosted implementations.  Actually, the
+      word "files" is a misnomer, since the contents of the
+@@ -18,19 +18,19 @@
+      the 1998 standard as updated for 2003, and the current 2011 standard.
+    </p><p>
+      C++98/03 include files. These are available in the default compilation mode, i.e. <code class="code">-std=c++98</code> or <code class="code">-std=gnu++98</code>.
+-   </p><div class="table"><a id="table.cxx98_headers"></a><p class="title"><strong>Table 3.2. C++ 1998 Library Headers</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">complex</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td></tr><tr><td align="left"><code class="filename">fstream</code></td><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td><td align="left"><code class="filename">iosfwd</code></td></tr><tr><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td><td align="left"><code class="filename">list</code></td></tr><tr><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td></tr><tr><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">typeinfo</code></td></tr><tr><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="table.cxx98_cheaders"></a><p class="title"><strong>Table 3.3. C++ 1998 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 1998 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">ciso646</code></td></tr><tr><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td></tr><tr><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p>
++   </p><div class="table"><a id="table.cxx98_headers"></a><p class="title"><strong>Table 3.2. C++ 1998 Library Headers</strong></p><div class="table-contents"><table class="table" summary="C++ 1998 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">complex</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td></tr><tr><td align="left"><code class="filename">fstream</code></td><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td><td align="left"><code class="filename">iosfwd</code></td></tr><tr><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td><td align="left"><code class="filename">list</code></td></tr><tr><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td></tr><tr><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">typeinfo</code></td></tr><tr><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="table.cxx98_cheaders"></a><p class="title"><strong>Table 3.3. C++ 1998 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table class="table" summary="C++ 1998 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">ciso646</code></td></tr><tr><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td></tr><tr><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p>
+ C++11 include files. These are only available in C++11 compilation
+ mode, i.e. <code class="literal">-std=c++11</code> or <code class="literal">-std=gnu++11</code>.
+-</p><p></p><div class="table"><a id="table.cxx11_headers"></a><p class="title"><strong>Table 3.4. C++ 2011 Library Headers</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">array</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">chrono</code></td><td align="left"><code class="filename">complex</code></td></tr><tr><td align="left"><code class="filename">condition_variable</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td><td align="left"><code class="filename">forward_list</code></td><td align="left"><code class="filename">fstream</code></td></tr><tr><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">future</code></td><td align="left"><code class="filename">initalizer_list</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td></tr><tr><td align="left"><code class="filename">iosfwd</code></td><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td></tr><tr><td align="left"><code class="filename">list</code></td><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">mutex</code></td></tr><tr><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">random</code></td></tr><tr><td align="left"><code class="filename">ratio</code></td><td align="left"><code class="filename">regex</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">system_error</code></td><td align="left"><code class="filename">thread</code></td></tr><tr><td align="left"><code class="filename">tuple</code></td><td align="left"><code class="filename">type_traits</code></td><td align="left"><code class="filename">typeinfo</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="filename">unordered_set</code></td></tr><tr><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="table.cxx11_cheaders"></a><p class="title"><strong>Table 3.5. C++ 2011 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ 2011 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">ccomplex</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cfenv</code></td></tr><tr><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">cinttypes</code></td><td align="left"><code class="filename">ciso646</code></td><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td></tr><tr><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstdbool</code></td></tr><tr><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdint</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctgmath</code></td><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cuchar</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>
++</p><p></p><div class="table"><a id="table.cxx11_headers"></a><p class="title"><strong>Table 3.4. C++ 2011 Library Headers</strong></p><div class="table-contents"><table class="table" summary="C++ 2011 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">algorithm</code></td><td align="left"><code class="filename">array</code></td><td align="left"><code class="filename">bitset</code></td><td align="left"><code class="filename">chrono</code></td><td align="left"><code class="filename">complex</code></td></tr><tr><td align="left"><code class="filename">condition_variable</code></td><td align="left"><code class="filename">deque</code></td><td align="left"><code class="filename">exception</code></td><td align="left"><code class="filename">forward_list</code></td><td align="left"><code class="filename">fstream</code></td></tr><tr><td align="left"><code class="filename">functional</code></td><td align="left"><code class="filename">future</code></td><td align="left"><code class="filename">initalizer_list</code></td><td align="left"><code class="filename">iomanip</code></td><td align="left"><code class="filename">ios</code></td></tr><tr><td align="left"><code class="filename">iosfwd</code></td><td align="left"><code class="filename">iostream</code></td><td align="left"><code class="filename">istream</code></td><td align="left"><code class="filename">iterator</code></td><td align="left"><code class="filename">limits</code></td></tr><tr><td align="left"><code class="filename">list</code></td><td align="left"><code class="filename">locale</code></td><td align="left"><code class="filename">map</code></td><td align="left"><code class="filename">memory</code></td><td align="left"><code class="filename">mutex</code></td></tr><tr><td align="left"><code class="filename">new</code></td><td align="left"><code class="filename">numeric</code></td><td align="left"><code class="filename">ostream</code></td><td align="left"><code class="filename">queue</code></td><td align="left"><code class="filename">random</code></td></tr><tr><td align="left"><code class="filename">ratio</code></td><td align="left"><code class="filename">regex</code></td><td align="left"><code class="filename">set</code></td><td align="left"><code class="filename">sstream</code></td><td align="left"><code class="filename">stack</code></td></tr><tr><td align="left"><code class="filename">stdexcept</code></td><td align="left"><code class="filename">streambuf</code></td><td align="left"><code class="filename">string</code></td><td align="left"><code class="filename">system_error</code></td><td align="left"><code class="filename">thread</code></td></tr><tr><td align="left"><code class="filename">tuple</code></td><td align="left"><code class="filename">type_traits</code></td><td align="left"><code class="filename">typeinfo</code></td><td align="left"><code class="filename">unordered_map</code></td><td align="left"><code class="filename">unordered_set</code></td></tr><tr><td align="left"><code class="filename">utility</code></td><td align="left"><code class="filename">valarray</code></td><td align="left"><code class="filename">vector</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="table.cxx11_cheaders"></a><p class="title"><strong>Table 3.5. C++ 2011 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table class="table" summary="C++ 2011 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">cassert</code></td><td align="left"><code class="filename">ccomplex</code></td><td align="left"><code class="filename">cctype</code></td><td align="left"><code class="filename">cerrno</code></td><td align="left"><code class="filename">cfenv</code></td></tr><tr><td align="left"><code class="filename">cfloat</code></td><td align="left"><code class="filename">cinttypes</code></td><td align="left"><code class="filename">ciso646</code></td><td align="left"><code class="filename">climits</code></td><td align="left"><code class="filename">clocale</code></td></tr><tr><td align="left"><code class="filename">cmath</code></td><td align="left"><code class="filename">csetjmp</code></td><td align="left"><code class="filename">csignal</code></td><td align="left"><code class="filename">cstdarg</code></td><td align="left"><code class="filename">cstdbool</code></td></tr><tr><td align="left"><code class="filename">cstddef</code></td><td align="left"><code class="filename">cstdint</code></td><td align="left"><code class="filename">cstdlib</code></td><td align="left"><code class="filename">cstdio</code></td><td align="left"><code class="filename">cstring</code></td></tr><tr><td align="left"><code class="filename">ctgmath</code></td><td align="left"><code class="filename">ctime</code></td><td align="left"><code class="filename">cuchar</code></td><td align="left"><code class="filename">cwchar</code></td><td align="left"><code class="filename">cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>
+   In addition, TR1 includes as:
+-</p><div class="table"><a id="table.tr1_headers"></a><p class="title"><strong>Table 3.6. C++ TR 1 Library Headers</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/array</code></td><td align="left"><code class="filename">tr1/complex</code></td><td align="left"><code class="filename">tr1/memory</code></td><td align="left"><code class="filename">tr1/functional</code></td><td align="left"><code class="filename">tr1/random</code></td></tr><tr><td align="left"><code class="filename">tr1/regex</code></td><td align="left"><code class="filename">tr1/tuple</code></td><td align="left"><code class="filename">tr1/type_traits</code></td><td align="left"><code class="filename">tr1/unordered_map</code></td><td align="left"><code class="filename">tr1/unordered_set</code></td></tr><tr><td align="left"><code class="filename">tr1/utility</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="table.tr1_cheaders"></a><p class="title"><strong>Table 3.7. C++ TR 1 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table summary="C++ TR 1 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/ccomplex</code></td><td align="left"><code class="filename">tr1/cfenv</code></td><td align="left"><code class="filename">tr1/cfloat</code></td><td align="left"><code class="filename">tr1/cmath</code></td><td align="left"><code class="filename">tr1/cinttypes</code></td></tr><tr><td align="left"><code class="filename">tr1/climits</code></td><td align="left"><code class="filename">tr1/cstdarg</code></td><td align="left"><code class="filename">tr1/cstdbool</code></td><td align="left"><code class="filename">tr1/cstdint</code></td><td align="left"><code class="filename">tr1/cstdio</code></td></tr><tr><td align="left"><code class="filename">tr1/cstdlib</code></td><td align="left"><code class="filename">tr1/ctgmath</code></td><td align="left"><code class="filename">tr1/ctime</code></td><td align="left"><code class="filename">tr1/cwchar</code></td><td align="left"><code class="filename">tr1/cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>Decimal floating-point arithmetic is available if the C++
++</p><div class="table"><a id="table.tr1_headers"></a><p class="title"><strong>Table 3.6. C++ TR 1 Library Headers</strong></p><div class="table-contents"><table class="table" summary="C++ TR 1 Library Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/array</code></td><td align="left"><code class="filename">tr1/complex</code></td><td align="left"><code class="filename">tr1/memory</code></td><td align="left"><code class="filename">tr1/functional</code></td><td align="left"><code class="filename">tr1/random</code></td></tr><tr><td align="left"><code class="filename">tr1/regex</code></td><td align="left"><code class="filename">tr1/tuple</code></td><td align="left"><code class="filename">tr1/type_traits</code></td><td align="left"><code class="filename">tr1/unordered_map</code></td><td align="left"><code class="filename">tr1/unordered_set</code></td></tr><tr><td align="left"><code class="filename">tr1/utility</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="table.tr1_cheaders"></a><p class="title"><strong>Table 3.7. C++ TR 1 Library Headers for C Library Facilities</strong></p><div class="table-contents"><table class="table" summary="C++ TR 1 Library Headers for C Library Facilities" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">tr1/ccomplex</code></td><td align="left"><code class="filename">tr1/cfenv</code></td><td align="left"><code class="filename">tr1/cfloat</code></td><td align="left"><code class="filename">tr1/cmath</code></td><td align="left"><code class="filename">tr1/cinttypes</code></td></tr><tr><td align="left"><code class="filename">tr1/climits</code></td><td align="left"><code class="filename">tr1/cstdarg</code></td><td align="left"><code class="filename">tr1/cstdbool</code></td><td align="left"><code class="filename">tr1/cstdint</code></td><td align="left"><code class="filename">tr1/cstdio</code></td></tr><tr><td align="left"><code class="filename">tr1/cstdlib</code></td><td align="left"><code class="filename">tr1/ctgmath</code></td><td align="left"><code class="filename">tr1/ctime</code></td><td align="left"><code class="filename">tr1/cwchar</code></td><td align="left"><code class="filename">tr1/cwctype</code></td></tr></tbody></table></div></div><br class="table-break" /><p>Decimal floating-point arithmetic is available if the C++
+ compiler supports scalar decimal floating-point types defined via
+ <code class="code">__attribute__((mode(SD|DD|LD)))</code>.
+-</p><div class="table"><a id="table.decfp_headers"></a><p class="title"><strong>Table 3.8. C++ TR 24733 Decimal Floating-Point Header</strong></p><div class="table-contents"><table summary="C++ TR 24733 Decimal Floating-Point Header" border="1"><colgroup><col align="left" class="c1" /></colgroup><tbody><tr><td align="left"><code class="filename">decimal/decimal</code></td></tr></tbody></table></div></div><br class="table-break" /><p>
++</p><div class="table"><a id="table.decfp_headers"></a><p class="title"><strong>Table 3.8. C++ TR 24733 Decimal Floating-Point Header</strong></p><div class="table-contents"><table class="table" summary="C++ TR 24733 Decimal Floating-Point Header" border="1"><colgroup><col align="left" class="c1" /></colgroup><tbody><tr><td align="left"><code class="filename">decimal/decimal</code></td></tr></tbody></table></div></div><br class="table-break" /><p>
+   Also included are files for the C++ ABI interface:
+-</p><div class="table"><a id="table.abi_headers"></a><p class="title"><strong>Table 3.9. C++ ABI Headers</strong></p><div class="table-contents"><table summary="C++ ABI Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">cxxabi.h</code></td><td align="left"><code class="filename">cxxabi_forced.h</code></td></tr></tbody></table></div></div><br class="table-break" /><p>
++</p><div class="table"><a id="table.abi_headers"></a><p class="title"><strong>Table 3.9. C++ ABI Headers</strong></p><div class="table-contents"><table class="table" summary="C++ ABI Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">cxxabi.h</code></td><td align="left"><code class="filename">cxxabi_forced.h</code></td></tr></tbody></table></div></div><br class="table-break" /><p>
+   And a large variety of extensions.
+-</p><div class="table"><a id="table.ext_headers"></a><p class="title"><strong>Table 3.10. Extension Headers</strong></p><div class="table-contents"><table summary="Extension Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">ext/algorithm</code></td><td align="left"><code class="filename">ext/atomicity.h</code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"><code class="filename">ext/cast.h</code></td></tr><tr><td align="left"><code class="filename">ext/codecvt_specializations.h</code></td><td align="left"><code class="filename">ext/concurrence.h</code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="filename">ext/enc_filebuf.h</code></td><td align="left"><code class="filename">ext/extptr_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/functional</code></td><td align="left"><code class="filename">ext/iterator</code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="filename">ext/memory</code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="filename">ext/numeric</code></td><td align="left"><code class="filename">ext/numeric_traits.h</code></td><td align="left"><code class="filename">ext/pb_ds/assoc_container.h</code></td><td align="left"><code class="filename">ext/pb_ds/priority_queue.h</code></td></tr><tr><td align="left"><code class="filename">ext/pod_char_traits.h</code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="filename">ext/rb_tree</code></td><td align="left"><code class="filename">ext/rope</code></td><td align="left"><code class="filename">ext/slist</code></td></tr><tr><td align="left"><code class="filename">ext/stdio_filebuf.h</code></td><td align="left"><code class="filename">ext/stdio_sync_filebuf.h</code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left"><code class="filename">ext/typelist.h</code></td><td align="left"><code class="filename">ext/type_traits.h</code></td></tr><tr><td align="left"><code class="filename">ext/vstring.h</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="table.debug_headers"></a><p class="title"><strong>Table 3.11. Extension Debug Headers</strong></p><div class="table-contents"><table summary="Extension Debug Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">debug/bitset</code></td><td align="left"><code class="filename">debug/deque</code></td><td align="left"><code class="filename">debug/list</code></td><td align="left"><code class="filename">debug/map</code></td><td align="left"><code class="filename">debug/set</code></td></tr><tr><td align="left"><code class="filename">debug/string</code></td><td align="left"><code class="filename">debug/unordered_map</code></td><td align="left"><code class="filename">debug/unordered_set</code></td><td align="left"><code class="filename">debug/vector</code></td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="table.profile_headers"></a><p class="title"><strong>Table 3.12. Extension Profile Headers</strong></p><div class="table-contents"><table summary="Extension Profile Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><tbody><tr><td align="left"><code class="filename">profile/bitset</code></td><td align="left"><code class="filename">profile/deque</code></td><td align="left"><code class="filename">profile/list</code></td><td align="left"><code class="filename">profile/map</code></td></tr><tr><td align="left"><code class="filename">profile/set</code></td><td align="left"><code class="filename">profile/unordered_map</code></td><td align="left"><code class="filename">profile/unordered_set</code></td><td align="left"><code class="filename">profile/vector</code></td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="table.parallel_headers"></a><p class="title"><strong>Table 3.13. Extension Parallel Headers</strong></p><div class="table-contents"><table summary="Extension Parallel Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">parallel/algorithm</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr></tbody></table></div></div><br class="table-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.mixing"></a>Mixing Headers</h3></div></div></div><p> A few simple rules.
++</p><div class="table"><a id="table.ext_headers"></a><p class="title"><strong>Table 3.10. Extension Headers</strong></p><div class="table-contents"><table class="table" summary="Extension Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">ext/algorithm</code></td><td align="left"><code class="filename">ext/atomicity.h</code></td><td align="left"><code class="filename">ext/array_allocator.h</code></td><td align="left"><code class="filename">ext/bitmap_allocator.h</code></td><td align="left"><code class="filename">ext/cast.h</code></td></tr><tr><td align="left"><code class="filename">ext/codecvt_specializations.h</code></td><td align="left"><code class="filename">ext/concurrence.h</code></td><td align="left"><code class="filename">ext/debug_allocator.h</code></td><td align="left"><code class="filename">ext/enc_filebuf.h</code></td><td align="left"><code class="filename">ext/extptr_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/functional</code></td><td align="left"><code class="filename">ext/iterator</code></td><td align="left"><code class="filename">ext/malloc_allocator.h</code></td><td align="left"><code class="filename">ext/memory</code></td><td align="left"><code class="filename">ext/mt_allocator.h</code></td></tr><tr><td align="left"><code class="filename">ext/new_allocator.h</code></td><td align="left"><code class="filename">ext/numeric</code></td><td align="left"><code class="filename">ext/numeric_traits.h</code></td><td align="left"><code class="filename">ext/pb_ds/assoc_container.h</code></td><td align="left"><code class="filename">ext/pb_ds/priority_queue.h</code></td></tr><tr><td align="left"><code class="filename">ext/pod_char_traits.h</code></td><td align="left"><code class="filename">ext/pool_allocator.h</code></td><td align="left"><code class="filename">ext/rb_tree</code></td><td align="left"><code class="filename">ext/rope</code></td><td align="left"><code class="filename">ext/slist</code></td></tr><tr><td align="left"><code class="filename">ext/stdio_filebuf.h</code></td><td align="left"><code class="filename">ext/stdio_sync_filebuf.h</code></td><td align="left"><code class="filename">ext/throw_allocator.h</code></td><td align="left"><code class="filename">ext/typelist.h</code></td><td align="left"><code class="filename">ext/type_traits.h</code></td></tr><tr><td align="left"><code class="filename">ext/vstring.h</code></td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="table.debug_headers"></a><p class="title"><strong>Table 3.11. Extension Debug Headers</strong></p><div class="table-contents"><table class="table" summary="Extension Debug Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /><col align="left" class="c5" /></colgroup><tbody><tr><td align="left"><code class="filename">debug/bitset</code></td><td align="left"><code class="filename">debug/deque</code></td><td align="left"><code class="filename">debug/list</code></td><td align="left"><code class="filename">debug/map</code></td><td align="left"><code class="filename">debug/set</code></td></tr><tr><td align="left"><code class="filename">debug/string</code></td><td align="left"><code class="filename">debug/unordered_map</code></td><td align="left"><code class="filename">debug/unordered_set</code></td><td align="left"><code class="filename">debug/vector</code></td><td class="auto-generated"> </td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="table.profile_headers"></a><p class="title"><strong>Table 3.12. Extension Profile Headers</strong></p><div class="table-contents"><table class="table" summary="Extension Profile Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /><col align="left" class="c3" /><col align="left" class="c4" /></colgroup><tbody><tr><td align="left"><code class="filename">profile/bitset</code></td><td align="left"><code class="filename">profile/deque</code></td><td align="left"><code class="filename">profile/list</code></td><td align="left"><code class="filename">profile/map</code></td></tr><tr><td align="left"><code class="filename">profile/set</code></td><td align="left"><code class="filename">profile/unordered_map</code></td><td align="left"><code class="filename">profile/unordered_set</code></td><td align="left"><code class="filename">profile/vector</code></td></tr></tbody></table></div></div><br class="table-break" /><p></p><div class="table"><a id="table.parallel_headers"></a><p class="title"><strong>Table 3.13. Extension Parallel Headers</strong></p><div class="table-contents"><table class="table" summary="Extension Parallel Headers" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><tbody><tr><td align="left"><code class="filename">parallel/algorithm</code></td><td align="left"><code class="filename">parallel/numeric</code></td></tr></tbody></table></div></div><br class="table-break" /></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.headers.mixing"></a>Mixing Headers</h3></div></div></div><p> A few simple rules.
+ </p><p>First, mixing different dialects of the standard headers is not
+ possible. It's an all-or-nothing affair. Thus, code like
+ </p><pre class="programlisting">
+Index: libstdc++-v3/doc/html/manual/using_namespaces.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/using_namespaces.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/using_namespaces.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Namespaces</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_dual_abi.html" title="Dual ABI" /><link rel="next" href="using_dynamic_or_shared.html" title="Linking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Namespaces</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_dual_abi.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_dynamic_or_shared.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.namespaces"></a>Namespaces</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.namespaces.all"></a>Available Namespaces</h3></div></div></div><p> There are three main namespaces.
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Namespaces</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_dual_abi.html" title="Dual ABI" /><link rel="next" href="using_dynamic_or_shared.html" title="Linking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Namespaces</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_dual_abi.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_dynamic_or_shared.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.namespaces"></a>Namespaces</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.intro.using.namespaces.all"></a>Available Namespaces</h3></div></div></div><p> There are three main namespaces.
+ </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>std</p><p>The ISO C++ standards specify that "all library entities are defined
+ within namespace std." This includes namespaces nested
+ within namespace <code class="code">std</code>, such as namespace
+Index: libstdc++-v3/doc/html/manual/errno.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/errno.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/errno.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Use of errno by the library</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="diagnostics.html" title="Chapter 5.  Diagnostics" /><link rel="prev" href="diagnostics.html" title="Chapter 5.  Diagnostics" /><link rel="next" href="concept_checking.html" title="Concept Checking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Use of errno by the library</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="diagnostics.html">Prev</a> </td><th width="60%" align="center">Chapter 5. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Use of errno by the library</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="diagnostics.html" title="Chapter 5.  Diagnostics" /><link rel="prev" href="diagnostics.html" title="Chapter 5.  Diagnostics" /><link rel="next" href="concept_checking.html" title="Concept Checking" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Use of errno by the library</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="diagnostics.html">Prev</a> </td><th width="60%" align="center">Chapter 5. 
+   Diagnostics
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="concept_checking.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.diagnostics.errno"></a>Use of errno by the library</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/debug.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/debug.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/debug.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Debugging Support</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_exceptions.html" title="Exceptions" /><link rel="next" href="std_contents.html" title="Part II.  Standard Contents" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Debugging Support</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_exceptions.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="std_contents.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.debug"></a>Debugging Support</h2></div></div></div><p>
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Debugging Support</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_exceptions.html" title="Exceptions" /><link rel="next" href="std_contents.html" title="Part II.  Standard Contents" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Debugging Support</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_exceptions.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="std_contents.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.debug"></a>Debugging Support</h2></div></div></div><p>
+   There are numerous things that can be done to improve the ease with
+   which C++ binaries are debugged when using the GNU tool chain. Here
+   are some of them.
+Index: libstdc++-v3/doc/html/manual/localization.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/localization.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/localization.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 8.  Localization</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="strings.html" title="Chapter 7.  Strings" /><link rel="next" href="facets.html" title="Facets" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 8. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 8.  Localization</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="strings.html" title="Chapter 7.  Strings" /><link rel="next" href="facets.html" title="Facets" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 8. 
+   Localization
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="strings.html">Prev</a> </td><th width="60%" align="center">Part II. 
+Index: libstdc++-v3/doc/html/manual/ext_algorithms.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/ext_algorithms.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/ext_algorithms.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 25. Algorithms</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_utilities.html" title="Chapter 24. Utilities" /><link rel="next" href="ext_numerics.html" title="Chapter 26. Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 25. Algorithms</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_utilities.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 25. Algorithms</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_utilities.html" title="Chapter 24. Utilities" /><link rel="next" href="ext_numerics.html" title="Chapter 26. Numerics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 25. Algorithms</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_utilities.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="ext_numerics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.algorithms"></a>Chapter 25. Algorithms</h2></div></div></div><p>25.1.6 (count, count_if) is extended with two more versions of count
+Index: libstdc++-v3/doc/html/manual/debug_mode.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/debug_mode.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/debug_mode.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 17. Debug Mode</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /><link rel="next" href="debug_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 17. Debug Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_compile_checks.html">Prev</a> </td><th width="60%" align="center">Part III. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 17. Debug Mode</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, debug" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="extensions.html" title="Part III.  Extensions" /><link rel="prev" href="ext_compile_checks.html" title="Chapter 16. Compile Time Checks" /><link rel="next" href="debug_mode_semantics.html" title="Semantics" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 17. Debug Mode</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="ext_compile_checks.html">Prev</a> </td><th width="60%" align="center">Part III. 
+   Extensions
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="debug_mode_semantics.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="manual.ext.debug_mode"></a>Chapter 17. Debug Mode</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="debug_mode.html#manual.ext.debug_mode.intro">Intro</a></span></dt><dt><span class="section"><a href="debug_mode_semantics.html">Semantics</a></span></dt><dt><span class="section"><a href="debug_mode_using.html">Using</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.mode">Using the Debug Mode</a></span></dt><dt><span class="section"><a href="debug_mode_using.html#debug_mode.using.specific">Using a Specific Debug Container</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html">Design</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.goals">Goals</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods">Methods</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.wrappers">The Wrapper Model</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_iter">Safe Iterators</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.safe_seq">Safe Sequences (Containers)</a></span></dt></dl></dd><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.precond">Precondition Checking</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#debug_mode.design.methods.coexistence">Release- and debug-mode coexistence</a></span></dt><dd><dl><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.compile">Compile-time coexistence of release- and debug-mode components</a></span></dt><dt><span class="section"><a href="debug_mode_design.html#methods.coexistence.link">Link- and run-time coexistence of release- and
+Index: libstdc++-v3/doc/html/manual/profile_mode_design.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/profile_mode_design.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/profile_mode_design.html	(.../branches/gcc-6-branch)
+@@ -1,6 +1,6 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="next" href="profile_mode_api.html" title="Extensions for Custom Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_api.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.design"></a>Design</h2></div></div></div><p>
+-</p><div class="table"><a id="table.profile_code_loc"></a><p class="title"><strong>Table 19.1. Profile Code Location</strong></p><div class="table-contents"><table summary="Profile Code Location" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Code Location</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left"><code class="code">libstdc++-v3/include/std/*</code></td><td align="left">Preprocessor code to redirect to profile extension headers.</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/*</code></td><td align="left">Profile extension public headers (map, vector, ...).</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/impl/*</code></td><td align="left">Profile extension internals.  Implementation files are
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Design</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="C++, library, profile" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="prev" href="profile_mode.html" title="Chapter 19. Profile Mode" /><link rel="next" href="profile_mode_api.html" title="Extensions for Custom Containers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Design</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="profile_mode.html">Prev</a> </td><th width="60%" align="center">Chapter 19. Profile Mode</th><td width="20%" align="right"> <a accesskey="n" href="profile_mode_api.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.ext.profile_mode.design"></a>Design</h2></div></div></div><p>
++</p><div class="table"><a id="table.profile_code_loc"></a><p class="title"><strong>Table 19.1. Profile Code Location</strong></p><div class="table-contents"><table class="table" summary="Profile Code Location" border="1"><colgroup><col align="left" class="c1" /><col align="left" class="c2" /></colgroup><thead><tr><th align="left">Code Location</th><th align="left">Use</th></tr></thead><tbody><tr><td align="left"><code class="code">libstdc++-v3/include/std/*</code></td><td align="left">Preprocessor code to redirect to profile extension headers.</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/*</code></td><td align="left">Profile extension public headers (map, vector, ...).</td></tr><tr><td align="left"><code class="code">libstdc++-v3/include/profile/impl/*</code></td><td align="left">Profile extension internals.  Implementation files are
+      only included from <code class="code">impl/profiler.h</code>, which is the only
+      file included from the public headers.</td></tr></tbody></table></div></div><br class="table-break" /><p>
+ </p><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="manual.ext.profile_mode.design.wrapper"></a>Wrapper Model</h3></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/using_concurrency.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/using_concurrency.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/using_concurrency.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Concurrency</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_dynamic_or_shared.html" title="Linking" /><link rel="next" href="using_exceptions.html" title="Exceptions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Concurrency</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_dynamic_or_shared.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_exceptions.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.concurrency"></a>Concurrency</h2></div></div></div><p>This section discusses issues surrounding the proper compilation
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Concurrency</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="using.html" title="Chapter 3. Using" /><link rel="prev" href="using_dynamic_or_shared.html" title="Linking" /><link rel="next" href="using_exceptions.html" title="Exceptions" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Concurrency</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="using_dynamic_or_shared.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Using</th><td width="20%" align="right"> <a accesskey="n" href="using_exceptions.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="manual.intro.using.concurrency"></a>Concurrency</h2></div></div></div><p>This section discusses issues surrounding the proper compilation
+       of multithreaded applications which use the Standard C++
+       library.  This information is GCC-specific since the C++
+       standard does not address matters of multithreaded applications.
+Index: libstdc++-v3/doc/html/manual/mt_allocator_impl.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/mt_allocator_impl.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/mt_allocator_impl.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_design.html" title="Design Issues" /><link rel="next" href="mt_allocator_ex_single.html" title="Single Thread Example" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_design.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_ex_single.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.tune"></a>Tunable Parameters</h3></div></div></div><p>Certain allocation parameters can be modified, or tuned. There
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Implementation</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, allocator" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="mt_allocator.html" title="Chapter 20. The mt_allocator" /><link rel="prev" href="mt_allocator_design.html" title="Design Issues" /><link rel="next" href="mt_allocator_ex_single.html" title="Single Thread Example" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Implementation</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mt_allocator_design.html">Prev</a> </td><th width="60%" align="center">Chapter 20. The mt_allocator</th><td width="20%" align="right"> <a accesskey="n" href="mt_allocator_ex_single.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="allocator.mt.impl"></a>Implementation</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="allocator.mt.tune"></a>Tunable Parameters</h3></div></div></div><p>Certain allocation parameters can be modified, or tuned. There
+ exists a nested <code class="code">struct __pool_base::_Tune</code> that contains all
+ these parameters, which include settings for
+ </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>Alignment</p></li><li class="listitem"><p>Maximum bytes before calling <code class="code">::operator new</code> directly</p></li><li class="listitem"><p>Minimum bytes</p></li><li class="listitem"><p>Size of underlying global allocations</p></li><li class="listitem"><p>Maximum number of supported threads</p></li><li class="listitem"><p>Migration of deallocations to the global free list</p></li><li class="listitem"><p>Shunt for global <code class="code">new</code> and <code class="code">delete</code></p></li></ul></div><p>Adjusting parameters for a given instance of an allocator can only
+Index: libstdc++-v3/doc/html/manual/appendix_gfdl.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/appendix_gfdl.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/appendix_gfdl.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix E. GNU Free Documentation License</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="appendix_gpl.html" title="Appendix D.  GNU General Public License version 3" /><link rel="next" href="../bk02.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix E. GNU Free Documentation License</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_gpl.html">Prev</a> </td><th width="60%" align="center">Part IV. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix E. GNU Free Documentation License</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="appendix_gpl.html" title="Appendix D.  GNU General Public License version 3" /><link rel="next" href="../bk02.html" title="" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix E. GNU Free Documentation License</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_gpl.html">Prev</a> </td><th width="60%" align="center">Part IV. 
+   Appendices
+ </th><td width="20%" align="right"> <a accesskey="n" href="../bk02.html">Next</a></td></tr></table><hr /></div><div class="appendix"><div class="titlepage"><div><div><h1 class="title"><a id="appendix.gfdl-1.3"></a>GNU Free Documentation License</h1></div></div></div><p>Version 1.3, 3 November 2008</p><p>
+     Copyright © 2000, 2001, 2002, 2007, 2008
+Index: libstdc++-v3/doc/html/manual/containers.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/containers.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/containers.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 9.  Containers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="facets.html" title="Facets" /><link rel="next" href="associative.html" title="Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 9. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 9.  Containers</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="facets.html" title="Facets" /><link rel="next" href="associative.html" title="Associative" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 9. 
+   Containers
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="facets.html">Prev</a> </td><th width="60%" align="center">Part II. 
+Index: libstdc++-v3/doc/html/manual/io.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/io.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/io.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 13.  Input and Output</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="numerics_and_c.html" title="Interacting with C" /><link rel="next" href="streambufs.html" title="Stream Buffers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 13. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 13.  Input and Output</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="numerics_and_c.html" title="Interacting with C" /><link rel="next" href="streambufs.html" title="Stream Buffers" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 13. 
+   Input and Output
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="numerics_and_c.html">Prev</a> </td><th width="60%" align="center">Part II. 
+Index: libstdc++-v3/doc/html/manual/index.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/index.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/index.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library Manual</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="../index.html" title="The GNU C++ Library" /><link rel="prev" href="../index.html" title="The GNU C++ Library" /><link rel="next" href="intro.html" title="Part I.  Introduction" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library Manual</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="../index.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="intro.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><div><div><h1 class="title"><a id="manual"></a>The GNU C++ Library Manual</h1></div><div><div class="authorgroup"><div class="author"><h3 class="author"><span class="firstname"></span> <span class="surname"></span></h3></div><div class="author"><h3 class="author"><span class="firstname">Paolo</span> <span class="surname">Carlini</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Phil</span> <span class="surname">Edwards</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Doug</span> <span class="surname">Gregor</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Dhruv</span> <span class="surname">Matani</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jason</span> <span class="surname">Merrill</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Mark</span> <span class="surname">Mitchell</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Nathan</span> <span class="surname">Myers</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Felix</span> <span class="surname">Natter</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Stefan</span> <span class="surname">Olsson</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Silvius</span> <span class="surname">Rus</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Ami</span> <span class="surname">Tavory</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jonathan</span> <span class="surname">Wakely</span></h3></div></div></div><div><p class="copyright">Copyright © 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>The GNU C++ Library Manual</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="../index.html" title="The GNU C++ Library" /><link rel="prev" href="../index.html" title="The GNU C++ Library" /><link rel="next" href="intro.html" title="Part I.  Introduction" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">The GNU C++ Library Manual</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="../index.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="intro.html">Next</a></td></tr></table><hr /></div><div class="book"><div class="titlepage"><div><div><h1 class="title"><a id="manual"></a>The GNU C++ Library Manual</h1></div><div><div class="authorgroup"><div class="author"><h3 class="author"><span class="firstname"></span> <span class="surname"></span></h3></div><div class="author"><h3 class="author"><span class="firstname">Paolo</span> <span class="surname">Carlini</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Phil</span> <span class="surname">Edwards</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Doug</span> <span class="surname">Gregor</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Benjamin</span> <span class="surname">Kosnik</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Dhruv</span> <span class="surname">Matani</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jason</span> <span class="surname">Merrill</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Mark</span> <span class="surname">Mitchell</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Nathan</span> <span class="surname">Myers</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Felix</span> <span class="surname">Natter</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Stefan</span> <span class="surname">Olsson</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Silvius</span> <span class="surname">Rus</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Johannes</span> <span class="surname">Singler</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Ami</span> <span class="surname">Tavory</span></h3></div><div class="author"><h3 class="author"><span class="firstname">Jonathan</span> <span class="surname">Wakely</span></h3></div></div></div><div><p class="copyright">Copyright © 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016 
+       <a class="link" href="http://www.fsf.org" target="_top">FSF</a>
+     </p></div></div><hr /></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="part"><a href="intro.html">I. 
+   Introduction
+Index: libstdc++-v3/doc/html/manual/numerics_and_c.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/numerics_and_c.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/numerics_and_c.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="numerics.html" title="Chapter 12.  Numerics" /><link rel="prev" href="generalized_numeric_operations.html" title="Generalized Operations" /><link rel="next" href="io.html" title="Chapter 13.  Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="generalized_numeric_operations.html">Prev</a> </td><th width="60%" align="center">Chapter 12. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Interacting with C</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="numerics.html" title="Chapter 12.  Numerics" /><link rel="prev" href="generalized_numeric_operations.html" title="Generalized Operations" /><link rel="next" href="io.html" title="Chapter 13.  Input and Output" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Interacting with C</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="generalized_numeric_operations.html">Prev</a> </td><th width="60%" align="center">Chapter 12. 
+   Numerics
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="io.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.numerics.c"></a>Interacting with C</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="numerics.c.array"></a>Numerics vs. Arrays</h3></div></div></div><p>One of the major reasons why FORTRAN can chew through numbers so well
+Index: libstdc++-v3/doc/html/manual/appendix_gpl.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/appendix_gpl.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/appendix_gpl.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix D.  GNU General Public License version 3</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="appendix_free.html" title="Appendix C.  Free Software Needs Free Documentation" /><link rel="next" href="appendix_gfdl.html" title="Appendix E. GNU Free Documentation License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix D. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Appendix D.  GNU General Public License version 3</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix.html" title="Part IV.  Appendices" /><link rel="prev" href="appendix_free.html" title="Appendix C.  Free Software Needs Free Documentation" /><link rel="next" href="appendix_gfdl.html" title="Appendix E. GNU Free Documentation License" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Appendix D. 
+     <acronym class="acronym">GNU</acronym> General Public License version 3
+   </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="appendix_free.html">Prev</a> </td><th width="60%" align="center">Part IV. 
+   Appendices
+Index: libstdc++-v3/doc/html/manual/source_code_style.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/source_code_style.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/source_code_style.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Coding Style</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="prev" href="source_organization.html" title="Directory Layout and Source Conventions" /><link rel="next" href="source_design_notes.html" title="Design Notes" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Coding Style</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_organization.html">Prev</a> </td><th width="60%" align="center">Appendix A. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Coding Style</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="appendix_contributing.html" title="Appendix A.  Contributing" /><link rel="prev" href="source_organization.html" title="Directory Layout and Source Conventions" /><link rel="next" href="source_design_notes.html" title="Design Notes" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Coding Style</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="source_organization.html">Prev</a> </td><th width="60%" align="center">Appendix A. 
+   Contributing
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="source_design_notes.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="contrib.coding_style"></a>Coding Style</h2></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/streambufs.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/streambufs.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/streambufs.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Stream Buffers</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="io.html" title="Chapter 13.  Input and Output" /><link rel="next" href="stringstreams.html" title="Memory Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Stream Buffers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Stream Buffers</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="io.html" title="Chapter 13.  Input and Output" /><link rel="prev" href="io.html" title="Chapter 13.  Input and Output" /><link rel="next" href="stringstreams.html" title="Memory Based Streams" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Stream Buffers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="io.html">Prev</a> </td><th width="60%" align="center">Chapter 13. 
+   Input and Output
+   
+ </th><td width="20%" align="right"> <a accesskey="n" href="stringstreams.html">Next</a></td></tr></table><hr /></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.io.streambufs"></a>Stream Buffers</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="io.streambuf.derived"></a>Derived streambuf Classes</h3></div></div></div><p>
+Index: libstdc++-v3/doc/html/manual/utilities.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/utilities.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/utilities.html	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
+-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 6.  Utilities</title><meta name="generator" content="DocBook XSL-NS Stylesheets V1.78.1" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="concept_checking.html" title="Concept Checking" /><link rel="next" href="pairs.html" title="Pairs" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 6. 
++<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /><title>Chapter 6.  Utilities</title><meta name="generator" content="DocBook XSL Stylesheets Vsnapshot" /><meta name="keywords" content="ISO C++, library" /><meta name="keywords" content="ISO C++, runtime, library" /><link rel="home" href="../index.html" title="The GNU C++ Library" /><link rel="up" href="std_contents.html" title="Part II.  Standard Contents" /><link rel="prev" href="concept_checking.html" title="Concept Checking" /><link rel="next" href="pairs.html" title="Pairs" /></head><body><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 6. 
+   Utilities
+   
+ </th></tr><tr><td width="20%" align="left"><a accesskey="p" href="concept_checking.html">Prev</a> </td><th width="60%" align="center">Part II. 
+Index: libstdc++-v3/doc/doxygen/mainpage.html
+===================================================================
+--- a/src/libstdc++-v3/doc/doxygen/mainpage.html	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/doc/doxygen/mainpage.html	(.../branches/gcc-6-branch)
+@@ -28,7 +28,7 @@
+ 
+ <p>There are two types of documentation for libstdc++.  One is the
+    distribution documentation, which can be read online
+-   <a href="http://gcc.gnu.org/onlinedocs/libstdc++/index.html">here</a>
++   <a href="https://gcc.gnu.org/onlinedocs/libstdc++/index.html">here</a>
+    or offline from the file doc/html/index.html in the library source
+    directory.
+ </p>
+@@ -78,11 +78,11 @@
+    pages.  See the section "Documentation Style"
+    in <code>doc/xml/manual/appendix_contributing.xml</code> in the
+    source tree for how to create (and write) the doxygen markup.
+-  This style guide can also be viewed on the <a href="http://gcc.gnu.org/onlinedocs/libstdc++/manual/bk01apas04.html">web</a>.
++  This style guide can also be viewed on the <a href="https://gcc.gnu.org/onlinedocs/libstdc++/manual/documentation_hacking.html">web</a>.
+ 
+ <h2>License, Copyright, and Other Lawyerly Verbosity</h2>
+ <p>The libstdc++ documentation is released under
+-   <a href="http://gcc.gnu.org/onlinedocs/libstdc++/manual/bk01pt01ch01s02.html">
++   <a href="https://gcc.gnu.org/onlinedocs/libstdc++/manual/appendix_gpl.html">
+    these terms</a>.
+ </p>
+ <p>Part of the generated documentation involved comments and notes from
+Index: libstdc++-v3/include/Makefile.in
+===================================================================
+--- a/src/libstdc++-v3/include/Makefile.in	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/Makefile.in	(.../branches/gcc-6-branch)
+@@ -1879,6 +1879,9 @@
+ $(experimental_headers): ; @:
+ $(experimental_bits_headers): ; @:
+ 
++# See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81797
++@INCLUDE_DIR_NOTPARALLEL_TRUE@.NOTPARALLEL:
++
+ # Tell versions [3.59,3.63) of GNU make to not export all variables.
+ # Otherwise a system limit (for SysV at least) may be exceeded.
+ .NOEXPORT:
+Index: libstdc++-v3/include/std/future
+===================================================================
+--- a/src/libstdc++-v3/include/std/future	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/std/future	(.../branches/gcc-6-branch)
+@@ -462,7 +462,6 @@
+ 	  // Used by std::promise to copy construct the result.
+           typename promise<_Res>::_Ptr_type operator()() const
+           {
+-            _State_baseV2::_S_check(_M_promise->_M_future);
+             _M_promise->_M_storage->_M_set(*_M_arg);
+             return std::move(_M_promise->_M_storage);
+           }
+@@ -477,7 +476,6 @@
+ 	  // Used by std::promise to move construct the result.
+           typename promise<_Res>::_Ptr_type operator()() const
+           {
+-            _State_baseV2::_S_check(_M_promise->_M_future);
+             _M_promise->_M_storage->_M_set(std::move(*_M_arg));
+             return std::move(_M_promise->_M_storage);
+           }
+@@ -485,6 +483,18 @@
+           _Res*             _M_arg;
+         };
+ 
++      // set void
++      template<typename _Res>
++	struct _Setter<_Res, void>
++	{
++	  static_assert(is_void<_Res>::value, "Only used for promise<void>");
++
++	  typename promise<_Res>::_Ptr_type operator()() const
++	  { return std::move(_M_promise->_M_storage); }
++
++	  promise<_Res>*    _M_promise;
++	};
++
+       struct __exception_ptr_tag { };
+ 
+       // set exceptions
+@@ -494,7 +504,6 @@
+ 	  // Used by std::promise to store an exception as the result.
+           typename promise<_Res>::_Ptr_type operator()() const
+           {
+-            _State_baseV2::_S_check(_M_promise->_M_future);
+             _M_promise->_M_storage->_M_error = *_M_ex;
+             return std::move(_M_promise->_M_storage);
+           }
+@@ -507,6 +516,7 @@
+         static _Setter<_Res, _Arg&&>
+         __setter(promise<_Res>* __prom, _Arg&& __arg)
+         {
++	  _S_check(__prom->_M_future);
+           return _Setter<_Res, _Arg&&>{ __prom, std::__addressof(__arg) };
+         }
+ 
+@@ -514,9 +524,18 @@
+         static _Setter<_Res, __exception_ptr_tag>
+         __setter(exception_ptr& __ex, promise<_Res>* __prom)
+         {
++	  _S_check(__prom->_M_future);
+           return _Setter<_Res, __exception_ptr_tag>{ __prom, &__ex };
+         }
+ 
++      template<typename _Res>
++	static _Setter<_Res, void>
++	__setter(promise<_Res>* __prom)
++	{
++	  _S_check(__prom->_M_future);
++	  return _Setter<_Res, void>{ __prom };
++	}
++
+       template<typename _Tp>
+         static void
+         _S_check(const shared_ptr<_Tp>& __p)
+@@ -1014,6 +1033,7 @@
+       typedef __future_base::_Result<_Res>	_Res_type;
+       typedef __future_base::_Ptr<_Res_type>	_Ptr_type;
+       template<typename, typename> friend class _State::_Setter;
++      friend _State;
+ 
+       shared_ptr<_State>                        _M_future;
+       _Ptr_type                                 _M_storage;
+@@ -1124,6 +1144,7 @@
+       typedef __future_base::_Result<_Res&>	_Res_type;
+       typedef __future_base::_Ptr<_Res_type> 	_Ptr_type;
+       template<typename, typename> friend class _State::_Setter;
++      friend _State;
+ 
+       shared_ptr<_State>                        _M_future;
+       _Ptr_type                                 _M_storage;
+@@ -1213,6 +1234,7 @@
+       typedef __future_base::_Result<void>	_Res_type;
+       typedef __future_base::_Ptr<_Res_type> 	_Ptr_type;
+       template<typename, typename> friend class _State::_Setter;
++      friend _State;
+ 
+       shared_ptr<_State>                        _M_future;
+       _Ptr_type                                 _M_storage;
+@@ -1273,7 +1295,9 @@
+       { return future<void>(_M_future); }
+ 
+       // Setting the result
+-      void set_value();
++      void
++      set_value()
++      { _M_future->_M_set_result(_State::__setter(this)); }
+ 
+       void
+       set_exception(exception_ptr __p)
+@@ -1280,7 +1304,8 @@
+       { _M_future->_M_set_result(_State::__setter(__p, this)); }
+ 
+       void
+-      set_value_at_thread_exit();
++      set_value_at_thread_exit()
++      { _M_future->_M_set_delayed_result(_State::__setter(this), _M_future); }
+ 
+       void
+       set_exception_at_thread_exit(exception_ptr __p)
+@@ -1290,30 +1315,6 @@
+       }
+     };
+ 
+-  // set void
+-  template<>
+-    struct __future_base::_State_base::_Setter<void, void>
+-    {
+-      promise<void>::_Ptr_type operator()() const
+-      {
+-        _State_base::_S_check(_M_promise->_M_future);
+-        return std::move(_M_promise->_M_storage);
+-      }
+-
+-      promise<void>*    _M_promise;
+-    };
+-
+-  inline void
+-  promise<void>::set_value()
+-  { _M_future->_M_set_result(_State::_Setter<void, void>{ this }); }
+-
+-  inline void
+-  promise<void>::set_value_at_thread_exit()
+-  {
+-    _M_future->_M_set_delayed_result(_State::_Setter<void, void>{this},
+-				     _M_future);
+-  }
+-
+   template<typename _Ptr_type, typename _Fn, typename _Res>
+     struct __future_base::_Task_setter
+     {
+Index: libstdc++-v3/include/std/chrono
+===================================================================
+--- a/src/libstdc++-v3/include/std/chrono	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/std/chrono	(.../branches/gcc-6-branch)
+@@ -558,7 +558,8 @@
+ 	{ }
+ 
+ 	// conversions
+-	template<typename _Dur2>
++	template<typename _Dur2,
++		 typename = _Require<is_convertible<_Dur2, _Dur>>>
+ 	  constexpr time_point(const time_point<clock, _Dur2>& __t)
+ 	  : __d(__t.time_since_epoch())
+ 	  { }
+Index: libstdc++-v3/include/std/functional
+===================================================================
+--- a/src/libstdc++-v3/include/std/functional	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/std/functional	(.../branches/gcc-6-branch)
+@@ -1885,7 +1885,7 @@
+        *  The newly-created %function contains the target of @a __x
+        *  (if it has one).
+        */
+-      function(function&& __x) : _Function_base()
++      function(function&& __x) noexcept : _Function_base()
+       {
+ 	__x.swap(*this);
+       }
+@@ -1944,7 +1944,7 @@
+        *  object, then this operation will not throw an %exception.
+        */
+       function&
+-      operator=(function&& __x)
++      operator=(function&& __x) noexcept
+       {
+ 	function(std::move(__x)).swap(*this);
+ 	return *this;
+Index: libstdc++-v3/include/std/istream
+===================================================================
+--- a/src/libstdc++-v3/include/std/istream	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/std/istream	(.../branches/gcc-6-branch)
+@@ -150,9 +150,9 @@
+        *  whatever data is appropriate for the type of the argument.
+        *
+        *  If an exception is thrown during extraction, ios_base::badbit
+-       *  will be turned on in the stream's error state without causing an
+-       *  ios_base::failure to be thrown.  The original exception will then
+-       *  be rethrown.
++       *  will be turned on in the stream's error state (without causing an
++       *  ios_base::failure to be thrown) and the original exception will
++       *  be rethrown if badbit is set in the exceptions mask.
+       */
+ 
+       //@{
+@@ -286,9 +286,9 @@
+        *  by gcount().
+        *
+        *  If an exception is thrown during extraction, ios_base::badbit
+-       *  will be turned on in the stream's error state without causing an
+-       *  ios_base::failure to be thrown.  The original exception will then
+-       *  be rethrown.
++       *  will be turned on in the stream's error state (without causing an
++       *  ios_base::failure to be thrown) and the original exception will
++       *  be rethrown if badbit is set in the exceptions mask.
+       */
+ 
+       /**
+Index: libstdc++-v3/include/std/complex
+===================================================================
+--- a/src/libstdc++-v3/include/std/complex	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/std/complex	(.../branches/gcc-6-branch)
+@@ -493,7 +493,7 @@
+     operator>>(basic_istream<_CharT, _Traits>& __is, complex<_Tp>& __x)
+     {
+       _Tp __re_x, __im_x;
+-      _CharT __ch;
++      _CharT __ch = _CharT();
+       __is >> __ch;
+       if (__ch == '(') 
+ 	{
+@@ -511,11 +511,13 @@
+ 	  else
+ 	    __is.setstate(ios_base::failbit);
+ 	}
+-      else 
++      else if (__is)
+ 	{
+ 	  __is.putback(__ch);
+-	  __is >> __re_x;
+-	  __x = __re_x;
++	  if (__is >> __re_x)
++	    __x = __re_x;
++	  else
++	    __is.setstate(ios_base::failbit);
+ 	}
+       return __is;
+     }
+Index: libstdc++-v3/include/std/sstream
+===================================================================
+--- a/src/libstdc++-v3/include/std/sstream	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/std/sstream	(.../branches/gcc-6-branch)
+@@ -302,12 +302,14 @@
+ 	__xfer_bufptrs(const basic_stringbuf& __from, basic_stringbuf* __to)
+ 	: _M_to{__to}, _M_goff{-1, -1, -1}, _M_poff{-1, -1, -1}
+ 	{
+-	  const _CharT* __str = __from._M_string.data();
++	  const _CharT* const __str = __from._M_string.data();
++	  const _CharT* __end = nullptr;
+ 	  if (__from.eback())
+ 	    {
+-	    _M_goff[0] = __from.eback() - __str;
+-	    _M_goff[1] = __from.gptr() - __str;
+-	    _M_goff[2] = __from.egptr() - __str;
++	      _M_goff[0] = __from.eback() - __str;
++	      _M_goff[1] = __from.gptr() - __str;
++	      _M_goff[2] = __from.egptr() - __str;
++	      __end = __from.egptr();
+ 	    }
+ 	  if (__from.pbase())
+ 	    {
+@@ -314,7 +316,18 @@
+ 	      _M_poff[0] = __from.pbase() - __str;
+ 	      _M_poff[1] = __from.pptr() - __from.pbase();
+ 	      _M_poff[2] = __from.epptr() - __str;
++	      if (__from.pptr() > __end)
++		__end = __from.pptr();
+ 	    }
++
++	  // Set _M_string length to the greater of the get and put areas.
++	  if (__end)
++	    {
++	      // The const_cast avoids changing this constructor's signature,
++	      // because it is exported from the dynamic library.
++	      auto& __mut_from = const_cast<basic_stringbuf&>(__from);
++	      __mut_from._M_string._M_length(__end - __str);
++	    }
+ 	}
+ 
+ 	~__xfer_bufptrs()
+Index: libstdc++-v3/include/experimental/bits/fs_ops.h
+===================================================================
+--- a/src/libstdc++-v3/include/experimental/bits/fs_ops.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/experimental/bits/fs_ops.h	(.../branches/gcc-6-branch)
+@@ -131,8 +131,11 @@
+   {
+     auto __s = status(__p, __ec);
+     if (status_known(__s))
+-      __ec.clear();
+-    return exists(__s);
++      {
++	__ec.clear();
++	return __s.type() != file_type::not_found;
++      }
++    return false;
+   }
+ 
+   uintmax_t file_size(const path& __p);
+Index: libstdc++-v3/include/experimental/bits/fs_path.h
+===================================================================
+--- a/src/libstdc++-v3/include/experimental/bits/fs_path.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/experimental/bits/fs_path.h	(.../branches/gcc-6-branch)
+@@ -724,10 +724,10 @@
+     pointer   operator->() const { return std::__addressof(**this); }
+ 
+     iterator& operator++();
+-    iterator  operator++(int) { auto __tmp = *this; ++_M_cur; return __tmp; }
++    iterator  operator++(int) { auto __tmp = *this; ++*this; return __tmp; }
+ 
+     iterator& operator--();
+-    iterator  operator--(int) { auto __tmp = *this; --_M_cur; return __tmp; }
++    iterator  operator--(int) { auto __tmp = *this; --*this; return __tmp; }
+ 
+     friend bool operator==(const iterator& __lhs, const iterator& __rhs)
+     { return __lhs._M_equals(__rhs); }
+Index: libstdc++-v3/include/ext/new_allocator.h
+===================================================================
+--- a/src/libstdc++-v3/include/ext/new_allocator.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/ext/new_allocator.h	(.../branches/gcc-6-branch)
+@@ -96,8 +96,8 @@
+       // NB: __n is permitted to be 0.  The C++ standard says nothing
+       // about what the return value is when __n == 0.
+       pointer
+-      allocate(size_type __n, const void* = 0)
+-      { 
++      allocate(size_type __n, const void* = static_cast<const void*>(0))
++      {
+ 	if (__n > this->max_size())
+ 	  std::__throw_bad_alloc();
+ 
+Index: libstdc++-v3/include/bits/hashtable.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/hashtable.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/bits/hashtable.h	(.../branches/gcc-6-branch)
+@@ -836,17 +836,8 @@
+ 	    _M_bucket_count = __bkt_count;
+ 	  }
+ 
+-	__try
+-	  {
+-	    for (; __f != __l; ++__f)
+-	      this->insert(*__f);
+-	  }
+-	__catch(...)
+-	  {
+-	    clear();
+-	    _M_deallocate_buckets();
+-	    __throw_exception_again;
+-	  }
++	for (; __f != __l; ++__f)
++	  this->insert(*__f);
+       }
+ 
+   template<typename _Key, typename _Value,
+Index: libstdc++-v3/include/bits/basic_ios.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/basic_ios.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/bits/basic_ios.h	(.../branches/gcc-6-branch)
+@@ -157,8 +157,8 @@
+       setstate(iostate __state)
+       { this->clear(this->rdstate() | __state); }
+ 
+-      // Flip the internal state on for the proper state bits, then re
+-      // throws the propagated exception if bit also set in
++      // Flip the internal state on for the proper state bits, then
++      // rethrows the propagated exception if bit also set in
+       // exceptions().
+       void
+       _M_setstate(iostate __state)
+Index: libstdc++-v3/include/bits/parse_numbers.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/parse_numbers.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/bits/parse_numbers.h	(.../branches/gcc-6-branch)
+@@ -197,6 +197,13 @@
+ 		    "integer literal does not fit in unsigned long long");
+     };
+ 
++  // Skip past digit separators:
++  template<unsigned _Base, unsigned long long _Pow, char _Dig, char..._Digs>
++    struct _Number_help<_Base, _Pow, '\'', _Dig, _Digs...>
++    : _Number_help<_Base, _Pow, _Dig, _Digs...>
++    { };
++
++  // Terminating case for recursion:
+   template<unsigned _Base, unsigned long long _Pow, char _Dig>
+     struct _Number_help<_Base, _Pow, _Dig>
+     {
+Index: libstdc++-v3/include/bits/locale_conv.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/locale_conv.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/bits/locale_conv.h	(.../branches/gcc-6-branch)
+@@ -431,7 +431,7 @@
+ 	streamsize __nbytes = sizeof(_M_get_buf) - _M_unconv;
+ 	__nbytes = std::min(__nbytes, _M_buf->in_avail());
+ 	if (__nbytes < 1)
+-	  __nbytes == 1;
++	  __nbytes = 1;
+ 	__nbytes = _M_buf->sgetn(_M_get_buf + _M_unconv, __nbytes);
+ 	if (__nbytes < 1)
+ 	  return false;
+Index: libstdc++-v3/include/bits/stl_stack.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/stl_stack.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/bits/stl_stack.h	(.../branches/gcc-6-branch)
+@@ -86,7 +86,7 @@
+    *
+    *  The second template parameter defines the type of the underlying
+    *  sequence/container.  It defaults to std::deque, but it can be
+-   *  any type that supports @c back, @c push_back, and @c pop_front,
++   *  any type that supports @c back, @c push_back, and @c pop_back,
+    *  such as std::list, std::vector, or an appropriate user-defined
+    *  type.
+    *
+Index: libstdc++-v3/include/bits/basic_string.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/basic_string.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/bits/basic_string.h	(.../branches/gcc-6-branch)
+@@ -2543,7 +2543,10 @@
+       int
+       compare(size_type __pos, size_type __n1, const _CharT* __s,
+ 	      size_type __n2) const;
+-  };
++
++      // Allow basic_stringbuf::__xfer_bufptrs to call _M_length:
++      template<typename, typename, typename> friend class basic_stringbuf;
++    };
+ _GLIBCXX_END_NAMESPACE_CXX11
+ #else  // !_GLIBCXX_USE_CXX11_ABI
+   // Reference-counted COW string implentation
+Index: libstdc++-v3/include/bits/istream.tcc
+===================================================================
+--- a/src/libstdc++-v3/include/bits/istream.tcc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/bits/istream.tcc	(.../branches/gcc-6-branch)
+@@ -48,28 +48,36 @@
+     {
+       ios_base::iostate __err = ios_base::goodbit;
+       if (__in.good())
+-	{
+-	  if (__in.tie())
+-	    __in.tie()->flush();
+-	  if (!__noskip && bool(__in.flags() & ios_base::skipws))
+-	    {
+-	      const __int_type __eof = traits_type::eof();
+-	      __streambuf_type* __sb = __in.rdbuf();
+-	      __int_type __c = __sb->sgetc();
++	__try
++	  {
++	    if (__in.tie())
++	      __in.tie()->flush();
++	    if (!__noskip && bool(__in.flags() & ios_base::skipws))
++	      {
++		const __int_type __eof = traits_type::eof();
++		__streambuf_type* __sb = __in.rdbuf();
++		__int_type __c = __sb->sgetc();
+ 
+-	      const __ctype_type& __ct = __check_facet(__in._M_ctype);
+-	      while (!traits_type::eq_int_type(__c, __eof)
+-		     && __ct.is(ctype_base::space, 
+-				traits_type::to_char_type(__c)))
+-		__c = __sb->snextc();
++		const __ctype_type& __ct = __check_facet(__in._M_ctype);
++		while (!traits_type::eq_int_type(__c, __eof)
++		       && __ct.is(ctype_base::space,
++				  traits_type::to_char_type(__c)))
++		  __c = __sb->snextc();
+ 
+-	      // _GLIBCXX_RESOLVE_LIB_DEFECTS
+-	      // 195. Should basic_istream::sentry's constructor ever
+-	      // set eofbit?
+-	      if (traits_type::eq_int_type(__c, __eof))
+-		__err |= ios_base::eofbit;
+-	    }
+-	}
++		// _GLIBCXX_RESOLVE_LIB_DEFECTS
++		// 195. Should basic_istream::sentry's constructor ever
++		// set eofbit?
++		if (traits_type::eq_int_type(__c, __eof))
++		  __err |= ios_base::eofbit;
++	      }
++	  }
++	__catch(__cxxabiv1::__forced_unwind&)
++	  {
++	    __in._M_setstate(ios_base::badbit);
++	    __throw_exception_again;
++	  }
++	__catch(...)
++	  { __in._M_setstate(ios_base::badbit); }
+ 
+       if (__in.good() && __err == ios_base::goodbit)
+ 	_M_ok = true;
+Index: libstdc++-v3/include/bits/sstream.tcc
+===================================================================
+--- a/src/libstdc++-v3/include/bits/sstream.tcc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/bits/sstream.tcc	(.../branches/gcc-6-branch)
+@@ -88,6 +88,25 @@
+ 	return traits_type::not_eof(__c);
+ 
+       const __size_type __capacity = _M_string.capacity();
++
++#if _GLIBCXX_USE_CXX11_ABI
++      if ((this->epptr() - this->pbase()) < __capacity)
++	{
++	  // There is additional capacity in _M_string that can be used.
++	  char_type* __base = const_cast<char_type*>(_M_string.data());
++	  _M_pbump(__base, __base + __capacity, this->pptr() - this->pbase());
++	  if (_M_mode & ios_base::in)
++	    {
++	      const __size_type __nget = this->gptr() - this->eback();
++	      const __size_type __eget = this->egptr() - this->eback();
++	      this->setg(__base, __base + __nget, __base + __eget + 1);
++	    }
++	  *this->pptr() = traits_type::to_char_type(__c);
++	  this->pbump(1);
++	  return __c;
++	}
++#endif
++
+       const __size_type __max_size = _M_string.max_size();
+       const bool __testput = this->pptr() < this->epptr();
+       if (__builtin_expect(!__testput && __capacity == __max_size, false))
+Index: libstdc++-v3/include/bits/shared_ptr_base.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/shared_ptr_base.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/bits/shared_ptr_base.h	(.../branches/gcc-6-branch)
+@@ -1082,12 +1082,12 @@
+ 
+       template<typename _Tp1>
+ 	bool
+-	owner_before(__shared_ptr<_Tp1, _Lp> const& __rhs) const
++	owner_before(__shared_ptr<_Tp1, _Lp> const& __rhs) const noexcept
+ 	{ return _M_refcount._M_less(__rhs._M_refcount); }
+ 
+       template<typename _Tp1>
+ 	bool
+-	owner_before(__weak_ptr<_Tp1, _Lp> const& __rhs) const
++	owner_before(__weak_ptr<_Tp1, _Lp> const& __rhs) const noexcept
+ 	{ return _M_refcount._M_less(__rhs._M_refcount); }
+ 
+ #if __cpp_rtti
+@@ -1444,12 +1444,12 @@
+ 
+       template<typename _Tp1>
+ 	bool
+-	owner_before(const __shared_ptr<_Tp1, _Lp>& __rhs) const
++	owner_before(const __shared_ptr<_Tp1, _Lp>& __rhs) const noexcept
+ 	{ return _M_refcount._M_less(__rhs._M_refcount); }
+ 
+       template<typename _Tp1>
+ 	bool
+-	owner_before(const __weak_ptr<_Tp1, _Lp>& __rhs) const
++	owner_before(const __weak_ptr<_Tp1, _Lp>& __rhs) const noexcept
+ 	{ return _M_refcount._M_less(__rhs._M_refcount); }
+ 
+       void
+@@ -1494,15 +1494,15 @@
+     struct _Sp_owner_less : public binary_function<_Tp, _Tp, bool>
+     {
+       bool
+-      operator()(const _Tp& __lhs, const _Tp& __rhs) const
++      operator()(const _Tp& __lhs, const _Tp& __rhs) const noexcept
+       { return __lhs.owner_before(__rhs); }
+ 
+       bool
+-      operator()(const _Tp& __lhs, const _Tp1& __rhs) const
++      operator()(const _Tp& __lhs, const _Tp1& __rhs) const noexcept
+       { return __lhs.owner_before(__rhs); }
+ 
+       bool
+-      operator()(const _Tp1& __lhs, const _Tp& __rhs) const
++      operator()(const _Tp1& __lhs, const _Tp& __rhs) const noexcept
+       { return __lhs.owner_before(__rhs); }
+     };
+ 
+Index: libstdc++-v3/include/bits/regex.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/regex.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/bits/regex.h	(.../branches/gcc-6-branch)
+@@ -1751,7 +1751,7 @@
+        */
+       const_iterator
+       end() const
+-      { return _Base_type::end() - 3; }
++      { return _Base_type::end() - (empty() ? 0 : 3); }
+ 
+       /**
+        * @brief Gets an iterator to one-past-the-end of the collection.
+Index: libstdc++-v3/include/bits/random.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/random.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/bits/random.h	(.../branches/gcc-6-branch)
+@@ -2618,7 +2618,12 @@
+        */
+       void
+       param(const param_type& __param)
+-      { _M_param = __param; }
++      {
++	_M_param = __param;
++	typedef typename std::gamma_distribution<result_type>::param_type
++	  param_type;
++	_M_gd.param(param_type{__param.n() / 2});
++      }
+ 
+       /**
+        * @brief Returns the greatest lower bound value of the distribution.
+Index: libstdc++-v3/include/bits/fstream.tcc
+===================================================================
+--- a/src/libstdc++-v3/include/bits/fstream.tcc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/bits/fstream.tcc	(.../branches/gcc-6-branch)
+@@ -699,7 +699,7 @@
+  
+  	   if (__n == 0)
+  	     {
+- 	       _M_set_buffer(0);
++	       // Set _M_reading. Buffer is already in initial 'read' mode.
+  	       _M_reading = true;
+  	     }
+  	   else if (__len == 0)
+Index: libstdc++-v3/include/Makefile.am
+===================================================================
+--- a/src/libstdc++-v3/include/Makefile.am	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/include/Makefile.am	(.../branches/gcc-6-branch)
+@@ -1459,3 +1459,8 @@
+ $(ext_headers): ; @:
+ $(experimental_headers): ; @:
+ $(experimental_bits_headers): ; @:
++
++if INCLUDE_DIR_NOTPARALLEL
++# See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81797
++.NOTPARALLEL:
++endif
+Index: libstdc++-v3/libsupc++/cxxabi.h
+===================================================================
+--- a/src/libstdc++-v3/libsupc++/cxxabi.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/libsupc++/cxxabi.h	(.../branches/gcc-6-branch)
+@@ -185,7 +185,7 @@
+    *  with GNU extensions. For example, this function is used in
+    *  __gnu_cxx::__verbose_terminate_handler.
+    *
+-   *  See http://gcc.gnu.org/onlinedocs/libstdc++/manual/bk01pt12ch39.html
++   *  See https://gcc.gnu.org/onlinedocs/libstdc++/manual/ext_demangling.html
+    *  for other examples of use.
+    *
+    *  @note The same demangling functionality is available via
+Index: libstdc++-v3/ChangeLog
+===================================================================
+--- a/src/libstdc++-v3/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,346 @@
++2018-03-02  Jonathan Wakely  <jwakely@redhat.com>
++
++	Backport from mainline
++	2018-03-02  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/84671
++	* include/bits/parse_numbers.h (_Number_help): Add partial
++	specialization to handle digit separators. Adjust partial
++	specialization for recursion temrination to require _Pow == 1ULL.
++	* testsuite/20_util/duration/literals/84671.cc: New
++
++2018-02-19  Jonathan Wakely  <jwakely@redhat.com>
++
++	Backport from mainline
++	2018-02-15  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/81797
++	* configure.ac (INCLUDE_DIR_NOTPARALLEL): Define.
++	* configure: Regenerate.
++	* include/Makefile.am (INCLUDE_DIR_NOTPARALLEL): Add .NOTPARALLEL when
++	defined.
++	* include/Makefile.in: Regenerate.
++
++2018-01-29  Jonathan Wakely  <jwakely@redhat.com>
++
++	Backport from mainline
++	2018-01-15  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/83833
++	* include/bits/random.h (chi_squared_distribution::param): Update
++	gamma distribution parameter.
++	* testsuite/26_numerics/random/chi_squared_distribution/83833.cc: New
++	test.
++
++2018-01-19  Jonathan Wakely  <jwakely@redhat.com>
++
++	Backport from mainline
++	2018-01-16  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/83834
++	* config/abi/pre/gnu.ver (GLIBCXX_3.4): Replace std::c[a-g]* wildcard
++	pattern with exact match for std::cerr.
++
++2018-01-15  Jonathan Wakely  <jwakely@redhat.com>
++
++	* python/libstdcxx/v6/printers.py (register_type_printers): Remove
++	printer for experimental::any. Fix printers for experimental::optional
++	and experimental::basic_string_view.
++
++	Backport from mainline
++	2018-01-04  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/83626
++	* src/filesystem/ops.cc (remove(const path&, error_code&))): Do not
++	return an error for non-existent paths. Remove unnecessary
++	symlink_status call.
++	(remove_all(const path&)): Fix type of result variable.
++	(remove_all(const path&, error_code&))): Use non-throwing increment
++	for directory iterator. Do not return an error for non-existent paths.
++	* testsuite/experimental/filesystem/operations/remove.cc: New test.
++	* testsuite/experimental/filesystem/operations/remove_all.cc: Fix
++	expected results for non-existent paths.
++
++2018-01-05  Jonathan Wakely  <jwakely@redhat.com>
++
++	Backport from mainline
++	2017-11-14  Jonathan Wakely  <jwakely@redhat.com>
++
++	* include/bits/locale_conv.h (wbuffer_convert::_M_conv_get): Fix typo.
++	* testsuite/22_locale/conversions/buffer/3.cc: New test.
++
++	Backport from mainline
++	2017-10-19  Jonathan Wakely  <jwakely@redhat.com>
++
++	* testsuite/experimental/filesystem/iterators/
++	recursive_directory_iterator.cc: Ensure that error_code arguments are
++	cleared when required.
++	* testsuite/experimental/filesystem/operations/create_directory.cc:
++	Remove redundant check.
++	* testsuite/experimental/filesystem/operations/temp_directory_path.cc:
++	Ensure that error_code argument is cleared when required.
++
++	Backport from mainline
++	2017-12-27  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/83600
++	* include/bits/regex.h (match_results::end()): Return valid iterator
++	when not ready.
++	* testsuite/28_regex/match_results/ctors/char/default.cc: Check that
++	unready objects are empty and have equal begin and end iterators.
++	* testsuite/28_regex/match_results/ctors/wchar_t/default.cc: Likewise.
++
++	Backport from mainline
++	2017-12-27  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/83598
++	* include/bits/regex.h (basic_regex): Don't modify flags passed to
++	constructors.
++	* testsuite/28_regex/basic_regex/ctors/83598.cc: New test.
++
++	Backport from mainline
++	2017-12-14  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/83279
++	* src/filesystem/std-ops.cc (do_copy_file): Handle sendfile not
++	copying entire file.
++
++	Backport from mainline
++	2018-01-04  Jonathan Wakely  <jwakely@redhat.com>
++
++	* include/experimental/fs_ops.h (exists(const path&, error_code&))):
++	Only check status_known once.
++
++	Backport from mainline
++	2017-10-25  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/79283
++	* src/filesystem/ops.cc (read_symlink): Handle st_size being zero.
++
++2017-12-14  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/59568
++	* include/std/complex (operator>>): Only use putback if a character
++	was successfully extracted and only set the value if a number was
++	successfully extracted.
++	* testsuite/26_numerics/complex/inserters_extractors/char/59568.cc:
++	New test.
++
++2017-11-11  John David Anglin  <danglin@gcc.gnu.org>
++
++	Backport from mainline
++	2017-08-20  John David Anglin  <danglin@gcc.gnu.org>
++
++	PR testsuite/81056
++	* testsuite/17_intro/names.cc: Undef 'd' and 'r' on __hpux__.
++
++2017-10-25  Jonathan Wakely  <jwakely@redhat.com>
++
++	* doc/xml/manual/status_cxx1998.xml: Correct statement about
++	what the doc covers.
++	* doc/xml/manual/status_cxxtr1.xml: Likewise.
++	* doc/xml/manual/status_cxxtr24733.xml: Likewise.
++	* doc/html/*: Regenerate.
++
++2017-10-23  Jonathan Wakely  <jwakely@redhat.com>
++
++	Backport from mainline
++	2017-07-18  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/81395
++	* include/bits/fstream.tcc (basic_filebuf::xsgetn): Don't set buffer
++	pointers for write mode after reading.
++	* testsuite/27_io/basic_filebuf/sgetn/char/81395.cc: New.
++
++	Backport from mainline
++	2017-10-19  Jonathan Wakely  <jwakely@redhat.com>
++
++	* include/experimental/bits/fs_path.h (path::iterator++(int))
++	(path::iterator--(int)): Fix for paths with only one component.
++	* testsuite/experimental/filesystem/path/itr/traversal.cc: Test
++	post-increment and post-decrement.
++
++2017-09-20  Jonathan Wakely  <jwakely@redhat.com>
++
++	Backport from mainline
++	2017-02-16  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/60936
++	* src/c++11/snprintf_lite.cc (__concat_size_t): Calculate length
++	written to buffer, not length remaining in buffer.
++
++	Backport from mainline
++	2017-02-08  Gerald Pfeifer  <gerald@pfeifer.com>
++
++	* src/c++11/snprintf_lite.cc (__err): Update bug reporting URL.
++
++2017-09-18  Jonathan Wakely  <jwakely@redhat.com>
++
++	Backport from mainline
++	2017-02-03  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/60936
++	* src/c++11/Makefile.am: Add new files.
++	* src/c++11/Makefile.in: Regenerate.
++	* src/c++11/cow-string-inst.cc [!_GLIBCXX_USE_CXX11_ABI]
++	(operator<<, operator>>, getline): Move explicit instantiations to ...
++	* src/c++11/cow-string-io-inst.cc: ... new file.
++	* src/c++11/cow-wstring-inst.cc [!_GLIBCXX_USE_CXX11_ABI]
++	(operator<<, operator>>, getline): Move explicit instantiations to ...
++	* src/c++11/cow-wstring-io-inst.cc: ... new file.
++	* src/c++11/functexcept.cc (__throw_ios_failure, __throw_system_error)
++	(__throw_future_error, __throw_bad_function_call):
++	(__throw_regex_error): Move functions for C++11 exceptions to the
++	files that define the exception types.
++	* src/c++11/functional.cc (__throw_bad_function_call): Move here.
++	* src/c++11/future.cc (__throw_future_error): Likewise.
++	* src/c++11/ios.cc (__throw_ios_failure): Likewise.
++	* src/c++11/regex.cc (__throw_regex_error): Likewise.
++	* src/c++11/snprintf_lite.cc (__concat_size_t): Print decimal
++	representation directly instead of calling __int_to_char.
++	* src/c++11/sso_string.cc (__sso_string): New file for definition
++	of __sso_string type.
++	* src/c++11/string-io-inst.cc [_GLIBCXX_USE_CXX11_ABI]: New file for
++	explicit instantiations of narrow string I/O functions.
++	* src/c++11/system_error.cc (__throw_system_error): Move here.
++	(__sso_string): Move to new file.
++	* src/c++11/wstring-io-inst.cc [_GLIBCXX_USE_CXX11_ABI]: New file for
++	explicit instantiations of wide string I/O functions.
++	* src/c++98/misc-inst.cc [_GLIBCXX_USE_CXX11_ABI] (operator<<)
++	(operator>>, getline): Remove explicit instantiations from here.
++
++2017-09-13  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/81468
++	* include/std/chrono (time_point(const time_point<_Dur2>&)): Add
++	missing constraint from LWG DR 1177.
++	* testsuite/20_util/duration/cons/dr1177.cc: New.
++	* testsuite/20_util/time_point/cons/81468.cc: New.
++	* testsuite/20_util/duration/literals/range.cc: Update dg-error line.
++
++	* doc/doxygen/mainpage.html: Fix broken URLs.
++
++	PR libstdc++/81835
++	* doc/xml/manual/extensions.xml: Replace unstable URL.
++	* doc/html/manual/ext_demangling.html: Regenerate.
++	* libsupc++/cxxabi.h (__cxa_demangle): Fix broken URL.
++
++2017-09-05  Jonathan Wakely  <jwakely@redhat.com>
++
++	* testsuite/20_util/owner_less/noexcept.cc: Remove owner_less<void>
++	tests.
++
++2017-09-04  Jonathan Wakely  <jwakely@redhat.com>
++
++	Backport from mainline
++	2017-08-09  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/79820
++	PR libstdc++/81751
++	* config/io/basic_file_stdio.cc (sys_open(FILE*, ios_base::openmode)):
++	Call fflush on the stream instead of calling sync() while _M_cfile is
++	null. Restore original value of errno.
++	* testsuite/ext/stdio_filebuf/char/79820.cc: New.
++	* testsuite/ext/stdio_filebuf/char/81751.cc: New.
++
++	Backport from mainline
++	2017-07-25  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/53984
++	* include/bits/basic_ios.h (basic_ios::_M_setstate): Adjust comment.
++	* include/bits/istream.tcc (basic_istream::sentry): Handle exceptions
++	during construction.
++	* include/std/istream: Adjust comments for formatted input functions
++	and unformatted input functions.
++	* testsuite/27_io/basic_fstream/53984.cc: New.
++	* testsuite/27_io/basic_istream/sentry/char/53984.cc: New.
++
++	Backport from mainline
++	2017-06-08  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/81017
++	* include/std/functional (function::function(function&&))
++	(function::operator=(function&&)): Add noexcept.
++	* testsuite/20_util/function/assign/move.cc: Check for noexcept.
++	* testsuite/20_util/function/cons/move.cc: Likewise.
++
++	Backport from mainline
++	2017-06-05  Jonathan Wakely  <jwakely@redhat.com>
++
++	* include/bits/shared_ptr_base.h (__shared_ptr::owner_before)
++	(__weak_ptr::owner_before, _Sp_owner_less::operator()): Add noexcept
++	specifiers as per LWG 2873 and LWG 2942.
++	* testsuite/20_util/owner_less/noexcept.cc: New.
++	* testsuite/20_util/shared_ptr/observers/owner_before.cc: Test
++	noexcept guarantees.
++	* testsuite/20_util/weak_ptr/observers/owner_before.cc: Likewise.
++
++	Backport from mainline
++	2017-08-31  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR c++/82039
++	* include/ext/new_allocator.h (__gnu_cxx::new_allocator::allocate):
++	Adjust null pointer constant to avoid warning.
++
++	Backport from mainline
++	2017-08-18  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/81891
++	* include/bits/hashtable.h (_Hashtable(_InputIterator, _InputIterator,
++	size_type, const _H1&, const _H2&, const _Hash&, const _Equal&,
++	const _ExtractKey&, const allocator_type&)): Let destructor do clean
++	up if an exception is thrown.
++	* testsuite/23_containers/unordered_map/cons/81891.cc: New.
++
++	Backport from mainline
++	2017-07-31  Marek Polacek  <polacek@redhat.com>
++
++	PR libstdc++/81599
++	* include/bits/stl_stack.h: Fix typo.
++
++	Backport from mainline
++	2017-07-10  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/81338
++	* include/bits/basic_string.h [_GLIBCXX_USE_CXX11_ABI] (basic_string):
++	Declare basic_stringbuf to be a friend.
++	* include/bits/sstream.tcc (basic_stringbuf::overflow)
++	[_GLIBCXX_USE_CXX11_ABI]: Use unused capacity before reallocating.
++	* include/std/sstream (basic_stringbuf::__xfer_bufptrs): Update string
++	length to buffer length.
++	* testsuite/27_io/basic_stringstream/assign/81338.cc: New.
++
++2017-07-12  Jonathan Wakely  <jwakely@redhat.com>
++
++	* testsuite/30_threads/promise/members/at_thread_exit2.cc: Require
++	atomic builtins.
++
++2017-07-11  Jonathan Wakely  <jwakely@redhat.com>
++
++	Backport from mainline
++	2017-04-21  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR libstdc++/80316
++	* include/std/future (_State_baseV2::_Setter::operator()): Remove
++	_S_check calls that are done after the pointer to the shared state is
++	already dereferenced.
++	(_State_baseV2::_Setter<_Res, void>): Define specialization for void
++	as partial specialization so it can be defined within the definition
++	of _State_baseV2.
++	(_State_baseV2::__setter): Call _S_check.
++	(_State_baseV2::__setter(promise<void>*)): Add overload for use by
++	promise<void>::set_value and promise<void>::set_value_at_thread_exit.
++	(promise<T>, promise<T&>, promise<void>): Make _State a friend.
++	(_State_baseV2::_Setter<void, void>): Remove explicit specialization.
++	(promise<void>::set_value, promise<void>::set_value_at_thread_exit):
++	Use new __setter overload.
++	* testsuite/30_threads/promise/members/at_thread_exit2.cc: New test.
++	* testsuite/30_threads/promise/members/set_exception.cc: Test
++	promise<T&> and promise<void> specializations.
++	* testsuite/30_threads/promise/members/set_exception2.cc: Likewise.
++	Test for no_state error condition.
++	* testsuite/30_threads/promise/members/set_value2.cc: Likewise.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: libstdc++-v3/testsuite/28_regex/basic_regex/ctors/83598.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/28_regex/basic_regex/ctors/83598.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/28_regex/basic_regex/ctors/83598.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,37 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do run { target c++11 } }
++
++#include <regex>
++#include <testsuite_hooks.h>
++
++void
++test01()
++{
++  // PR libstdc++83598
++  std::regex r1(".", std::regex_constants::syntax_option_type{});
++  VERIFY(r1.flags() == std::regex_constants::syntax_option_type{});
++  std::regex r2(".", std::regex_constants::icase);
++  VERIFY(r2.flags() == std::regex_constants::icase);
++}
++
++int
++main()
++{
++  test01();
++}
+Index: libstdc++-v3/testsuite/28_regex/match_results/ctors/wchar_t/default.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/28_regex/match_results/ctors/wchar_t/default.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/28_regex/match_results/ctors/wchar_t/default.cc	(.../branches/gcc-6-branch)
+@@ -32,6 +32,8 @@
+   std::wcmatch cm;
+   VERIFY( cm.size() == 0 );
+   VERIFY( !cm.ready() );
++  VERIFY( cm.empty() );
++  VERIFY( cm.begin() == cm.end() ); // PR libstdc++/83600
+ }
+ 
+ void test02()
+@@ -41,6 +43,8 @@
+   std::wsmatch sm;
+   VERIFY( sm.size() == 0 );
+   VERIFY( !sm.ready() );
++  VERIFY( sm.empty() );
++  VERIFY( sm.begin() == sm.end() ); // PR libstdc++/83600
+ }
+ 
+ int
+Index: libstdc++-v3/testsuite/28_regex/match_results/ctors/char/default.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/28_regex/match_results/ctors/char/default.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/28_regex/match_results/ctors/char/default.cc	(.../branches/gcc-6-branch)
+@@ -32,6 +32,8 @@
+   std::cmatch cm;
+   VERIFY( cm.size() == 0 );
+   VERIFY( !cm.ready() );
++  VERIFY( cm.empty() );
++  VERIFY( cm.begin() == cm.end() ); // PR libstdc++/83600
+ }
+ 
+ void test02()
+@@ -41,6 +43,8 @@
+   std::smatch sm;
+   VERIFY( sm.size() == 0 );
+   VERIFY( !sm.ready() );
++  VERIFY( sm.empty() );
++  VERIFY( sm.begin() == sm.end() ); // PR libstdc++/83600
+ }
+ 
+ int
+Index: libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc	(.../branches/gcc-6-branch)
+@@ -23,10 +23,13 @@
+ // with this library; see the file COPYING3.  If not see
+ // <http://www.gnu.org/licenses/>.
+ 
++// Test that promise::set_exception throws when required.
+ 
+ #include <future>
+ #include <testsuite_hooks.h>
+ 
++// Check for promise_already_satisfied error conditions.
++
+ void test01()
+ {
+   bool test = false;
+@@ -85,9 +88,187 @@
+   VERIFY( test );
+ }
+ 
++void test03()
++{
++  bool test = false;
++
++  std::promise<int&> p1;
++  std::future<int&> f1 = p1.get_future();
++
++  p1.set_exception(std::make_exception_ptr(0));
++
++  try
++  {
++    p1.set_exception(std::make_exception_ptr(1));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() ==
++        std::make_error_code(std::future_errc::promise_already_satisfied));
++    test = true;
++  }
++
++  try
++  {
++    f1.get();
++    test = false;
++  }
++  catch(int i)
++  {
++    VERIFY( i == 0 );
++  }
++
++  VERIFY( test );
++}
++
++void test04()
++{
++  bool test = false;
++
++  std::promise<int&> p1;
++  std::future<int&> f1 = p1.get_future();
++
++  int i = 2;
++  p1.set_value(i);
++
++  try
++  {
++    p1.set_exception(std::make_exception_ptr(0));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() ==
++        std::make_error_code(std::future_errc::promise_already_satisfied));
++    test = true;
++  }
++
++  VERIFY( test );
++}
++
++void test05()
++{
++  bool test = false;
++
++  std::promise<void> p1;
++  std::future<void> f1 = p1.get_future();
++
++  p1.set_exception(std::make_exception_ptr(0));
++
++  try
++  {
++    p1.set_exception(std::make_exception_ptr(1));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() ==
++        std::make_error_code(std::future_errc::promise_already_satisfied));
++    test = true;
++  }
++
++  try
++  {
++    f1.get();
++    test = false;
++  }
++  catch(int i)
++  {
++    VERIFY( i == 0 );
++  }
++
++  VERIFY( test );
++}
++
++void test06()
++{
++  bool test = false;
++
++  std::promise<void> p1;
++  std::future<void> f1 = p1.get_future();
++
++  p1.set_value();
++
++  try
++  {
++    p1.set_exception(std::make_exception_ptr(0));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() ==
++        std::make_error_code(std::future_errc::promise_already_satisfied));
++    test = true;
++  }
++
++  VERIFY( test );
++}
++
++// Check for no_state error condition (PR libstdc++/80316)
++
++void test07()
++{
++  using namespace std;
++
++  promise<int> p1;
++  promise<int> p2(std::move(p1));
++  try
++  {
++    p1.set_exception(std::make_exception_ptr(1));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() == make_error_code(future_errc::no_state));
++  }
++}
++
++void test08()
++{
++  using namespace std;
++
++  promise<int&> p1;
++  promise<int&> p2(std::move(p1));
++  try
++  {
++    int i = 0;
++    p1.set_exception(std::make_exception_ptr(1));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() == make_error_code(future_errc::no_state));
++  }
++}
++
++void test09()
++{
++  using namespace std;
++
++  promise<void> p1;
++  promise<void> p2(std::move(p1));
++  try
++  {
++    p1.set_exception(std::make_exception_ptr(1));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() == make_error_code(future_errc::no_state));
++  }
++}
++
+ int main()
+ {
+   test01();
+   test02();
++  test03();
++  test04();
++  test05();
++  test06();
++  test07();
++  test08();
++  test09();
+   return 0;
+ }
+Index: libstdc++-v3/testsuite/30_threads/promise/members/at_thread_exit2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/at_thread_exit2.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/at_thread_exit2.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,168 @@
++// { dg-do run { target *-*-freebsd* *-*-dragonfly* *-*-netbsd* *-*-linux* *-*-gnu* *-*-solaris* *-*-cygwin *-*-rtems* *-*-darwin* powerpc-ibm-aix* } }
++// { dg-options "-pthread" { target *-*-freebsd* *-*-dragonfly* *-*-netbsd* *-*-linux* *-*-gnu* *-*-solaris* powerpc-ibm-aix* } }
++// { dg-require-effective-target c++11 }
++// { dg-require-cstdint "" }
++// { dg-require-gthreads "" }
++// { dg-require-atomic-builtins "" }
++
++// Copyright (C) 2014-2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// Test set_value_at_thread_exit error conditions
++
++#include <future>
++#include <testsuite_hooks.h>
++
++void test01()
++{
++  std::promise<int> p1;
++  p1.set_value(1);
++  try
++  {
++    p1.set_value_at_thread_exit(2);
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY( e.code() == std::future_errc::promise_already_satisfied );
++  }
++  try
++  {
++    p1.set_exception_at_thread_exit(std::make_exception_ptr(3));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY( e.code() == std::future_errc::promise_already_satisfied );
++  }
++
++  std::promise<int> p2(std::move(p1));
++  try
++  {
++    p1.set_value_at_thread_exit(2);
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY( e.code() == std::future_errc::no_state );
++  }
++  try
++  {
++    p1.set_exception_at_thread_exit(std::make_exception_ptr(3));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY( e.code() == std::future_errc::no_state );
++  }
++}
++
++void test02()
++{
++  std::promise<int&> p1;
++  int i = 1;
++  p1.set_value(i);
++  try
++  {
++    p1.set_value_at_thread_exit(i);
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY( e.code() == std::future_errc::promise_already_satisfied );
++  }
++  try
++  {
++    p1.set_exception_at_thread_exit(std::make_exception_ptr(3));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY( e.code() == std::future_errc::promise_already_satisfied );
++  }
++
++  std::promise<int&> p2(std::move(p1));
++  try
++  {
++    int i = 0;
++    p1.set_value_at_thread_exit(i);
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY( e.code() == std::future_errc::no_state );
++  }
++  try
++  {
++    p1.set_exception_at_thread_exit(std::make_exception_ptr(3));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY( e.code() == std::future_errc::no_state );
++  }
++}
++
++void test03()
++{
++  std::promise<void> p1;
++  int i = 0;
++  p1.set_value();
++  try {
++    p1.set_value_at_thread_exit();
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY( e.code() == std::future_errc::promise_already_satisfied );
++  }
++  try
++  {
++    p1.set_exception_at_thread_exit(std::make_exception_ptr(3));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY( e.code() == std::future_errc::promise_already_satisfied );
++  }
++
++  std::promise<void> p2(std::move(p1));
++  try {
++    p1.set_value_at_thread_exit();
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY( e.code() == std::future_errc::no_state );
++  }
++  try
++  {
++    p1.set_exception_at_thread_exit(std::make_exception_ptr(3));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY( e.code() == std::future_errc::no_state );
++  }
++}
++
++int main()
++{
++  test01();
++  test02();
++  test03();
++}
+Index: libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc	(.../branches/gcc-6-branch)
+@@ -23,6 +23,7 @@
+ // with this library; see the file COPYING3.  If not see
+ // <http://www.gnu.org/licenses/>.
+ 
++// Test that promise::set_exception stores an exception.
+ 
+ #include <future>
+ #include <testsuite_hooks.h>
+@@ -50,8 +51,56 @@
+   VERIFY( !f1.valid() );
+ }
+ 
++void test02()
++{
++  bool test = false;
++
++  std::promise<int&> p1;
++  std::future<int&> f1 = p1.get_future();
++
++  VERIFY( f1.valid() );
++
++  p1.set_exception(std::make_exception_ptr(0));
++
++  try
++  {
++    f1.get();
++  }
++  catch (int)
++  {
++    test = true;
++  }
++  VERIFY( test );
++  VERIFY( !f1.valid() );
++}
++
++void test03()
++{
++  bool test = false;
++
++  std::promise<void> p1;
++  std::future<void> f1 = p1.get_future();
++
++  VERIFY( f1.valid() );
++
++  p1.set_exception(std::make_exception_ptr(0));
++
++  try
++  {
++    f1.get();
++  }
++  catch (int)
++  {
++    test = true;
++  }
++  VERIFY( test );
++  VERIFY( !f1.valid() );
++}
++
+ int main()
+ {
+   test01();
++  test02();
++  test03();
+   return 0;
+ }
+Index: libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc	(.../branches/gcc-6-branch)
+@@ -23,10 +23,13 @@
+ // with this library; see the file COPYING3.  If not see
+ // <http://www.gnu.org/licenses/>.
+ 
++// Test that promise::set_value throws when required.
+ 
+ #include <future>
+ #include <testsuite_hooks.h>
+ 
++// Check for promise_already_satisfied error conditions.
++
+ void test01()
+ {
+   bool test = false;
+@@ -81,9 +84,298 @@
+   VERIFY( test );
+ }
+ 
++void test03()
++{
++  bool test = false;
++
++  std::promise<int> p1;
++  std::future<int> f1 = p1.get_future();
++
++  p1.set_exception(std::make_exception_ptr(4));
++
++  try
++  {
++    p1.set_value(3);
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() ==
++        std::make_error_code(std::future_errc::promise_already_satisfied));
++    test = true;
++  }
++
++  std::chrono::milliseconds delay(1);
++  VERIFY( f1.wait_for(delay) == std::future_status::ready );
++  test = false;
++  try
++  {
++    f1.get();
++    VERIFY( false );
++  }
++  catch (int e)
++  {
++    VERIFY(e == 4 );
++    test = true;
++  }
++
++  VERIFY( test );
++}
++
++void test04()
++{
++  bool test = false;
++
++  std::promise<int&> p1;
++  std::future<int&> f1 = p1.get_future();
++
++  int i = 1;
++  p1.set_value(i);
++
++  try
++  {
++    p1.set_value(i);
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() ==
++        std::make_error_code(std::future_errc::promise_already_satisfied));
++    test = true;
++  }
++
++  std::chrono::milliseconds delay(1);
++  VERIFY( f1.wait_for(delay) == std::future_status::ready );
++  VERIFY( f1.get() == 1 );
++  VERIFY( test );
++}
++
++void test05()
++{
++  bool test = false;
++
++  std::promise<int&> p1;
++  std::future<int&> f1 = p1.get_future();
++
++  int i = 3;
++  p1.set_value(i);
++
++  try
++  {
++    p1.set_exception(std::make_exception_ptr(4));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() ==
++        std::make_error_code(std::future_errc::promise_already_satisfied));
++    test = true;
++  }
++
++  std::chrono::milliseconds delay(1);
++  VERIFY( f1.wait_for(delay) == std::future_status::ready );
++  VERIFY( f1.get() == 3 );
++  VERIFY( test );
++}
++
++void test06()
++{
++  bool test = false;
++
++  std::promise<int&> p1;
++  std::future<int&> f1 = p1.get_future();
++
++  p1.set_exception(std::make_exception_ptr(4));
++
++  try
++  {
++    int i = 3;
++    p1.set_value(i);
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() ==
++        std::make_error_code(std::future_errc::promise_already_satisfied));
++    test = true;
++  }
++
++  std::chrono::milliseconds delay(1);
++  VERIFY( f1.wait_for(delay) == std::future_status::ready );
++  test = false;
++  try
++  {
++    f1.get();
++    VERIFY( false );
++  }
++  catch (int e)
++  {
++    VERIFY(e == 4 );
++    test = true;
++  }
++
++  VERIFY( test );
++}
++
++void test07()
++{
++  bool test = false;
++
++  std::promise<void> p1;
++  std::future<void> f1 = p1.get_future();
++
++  p1.set_value();
++
++  try
++  {
++    p1.set_value();
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() ==
++        std::make_error_code(std::future_errc::promise_already_satisfied));
++    test = true;
++  }
++
++  std::chrono::milliseconds delay(1);
++  VERIFY( f1.wait_for(delay) == std::future_status::ready );
++  f1.get();
++  VERIFY( test );
++}
++
++void test08()
++{
++  bool test = false;
++
++  std::promise<void> p1;
++  std::future<void> f1 = p1.get_future();
++
++  p1.set_value();
++
++  try
++  {
++    p1.set_exception(std::make_exception_ptr(4));
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() ==
++        std::make_error_code(std::future_errc::promise_already_satisfied));
++    test = true;
++  }
++
++  std::chrono::milliseconds delay(1);
++  VERIFY( f1.wait_for(delay) == std::future_status::ready );
++  f1.get();
++  VERIFY( test );
++}
++
++void test09()
++{
++  bool test = false;
++
++  std::promise<void> p1;
++  std::future<void> f1 = p1.get_future();
++
++  p1.set_exception(std::make_exception_ptr(4));
++
++  try
++  {
++    p1.set_value();
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() ==
++        std::make_error_code(std::future_errc::promise_already_satisfied));
++    test = true;
++  }
++
++  std::chrono::milliseconds delay(1);
++  VERIFY( f1.wait_for(delay) == std::future_status::ready );
++  test = false;
++  try
++  {
++    f1.get();
++    VERIFY( false );
++  }
++  catch (int e)
++  {
++    VERIFY(e == 4 );
++    test = true;
++  }
++
++  VERIFY( test );
++}
++
++// Check for no_state error condition (PR libstdc++/80316)
++
++void test10()
++{
++  using namespace std;
++
++  promise<int> p1;
++  promise<int> p2(std::move(p1));
++  try
++  {
++    p1.set_value(1);
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() == make_error_code(future_errc::no_state));
++  }
++}
++
++void test11()
++{
++  using namespace std;
++
++  promise<int&> p1;
++  promise<int&> p2(std::move(p1));
++  try
++  {
++    int i = 0;
++    p1.set_value(i);
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() == make_error_code(future_errc::no_state));
++  }
++}
++
++void test12()
++{
++  using namespace std;
++
++  promise<void> p1;
++  promise<void> p2(std::move(p1));
++  try
++  {
++    p1.set_value();
++    VERIFY( false );
++  }
++  catch (std::future_error& e)
++  {
++    VERIFY(e.code() == make_error_code(future_errc::no_state));
++  }
++}
++
+ int main()
+ {
+   test01();
+   test02();
++  test03();
++  test04();
++  test05();
++  test06();
++  test07();
++  test08();
++  test09();
++  test10();
++  test11();
++  test12();
+   return 0;
+ }
+Index: libstdc++-v3/testsuite/ext/stdio_filebuf/char/81751.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/ext/stdio_filebuf/char/81751.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/ext/stdio_filebuf/char/81751.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,53 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-require-fileio "" }
++
++#include <ext/stdio_filebuf.h>
++#include <cstdio>
++#include <cerrno>
++#include <testsuite_hooks.h>
++
++void
++test01()
++{
++  FILE* out = std::fopen("81751.txt", "w");
++  std::fwrite("Some words.", 1, 10, out);
++
++  FILE* in1 = std::fopen("81751.txt", "r");
++  __gnu_cxx::stdio_filebuf<char> buf1(in1, std::ios::in, BUFSIZ);
++  int c = buf1.sgetc();
++  VERIFY( c == std::char_traits<char>::eof() ); // PR libstdc++/81751
++
++  std::fflush(out);
++  FILE* in2 = std::fopen("81751.txt", "r");
++  __gnu_cxx::stdio_filebuf<char> buf2(in2, std::ios::in, BUFSIZ);
++  c = buf2.sgetc();
++  VERIFY( c == 'S' );
++
++  buf1.close();
++  buf2.close();
++  std::fclose(in1);
++  std::fclose(in2);
++  std::fclose(out);
++}
++
++int
++main()
++{
++  test01();
++}
+Index: libstdc++-v3/testsuite/ext/stdio_filebuf/char/79820.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/ext/stdio_filebuf/char/79820.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/ext/stdio_filebuf/char/79820.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,39 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-require-fileio "" }
++
++#include <ext/stdio_filebuf.h>
++#include <cstdio>
++#include <cerrno>
++#include <testsuite_hooks.h>
++
++void
++test01()
++{
++  FILE* f = std::fopen("79820.txt", "w");
++  std::fclose(f);
++  errno = 127;
++  __gnu_cxx::stdio_filebuf<char> b(f, std::ios::out, BUFSIZ);
++  VERIFY(errno == 127); // PR libstdc++/79820
++}
++
++int
++main()
++{
++  test01();
++}
+Index: libstdc++-v3/testsuite/22_locale/conversions/buffer/3.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/22_locale/conversions/buffer/3.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/22_locale/conversions/buffer/3.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,58 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do run { target c++11 } }
++
++#include <locale>
++#include <streambuf>
++#include <testsuite_hooks.h>
++
++struct streambuf : std::streambuf
++{
++  int_type underflow() override
++  {
++    if (c != '\0')
++    {
++      this->setg(&c, &c, &c + 1);
++      return *this->gptr();
++    }
++    c = '\0';
++    return traits_type::eof();
++  }
++
++private:
++  char c = 'a';
++};
++
++struct codecvt : std::codecvt<wchar_t, char, std::mbstate_t> { };
++
++void
++test01()
++{
++  // https://gcc.gnu.org/ml/libstdc++/2017-11/msg00022.html
++  streambuf sb;
++  std::wbuffer_convert<codecvt> conv(&sb);
++  VERIFY( sb.in_avail() == 0 );
++  wchar_t c = conv.sgetc();
++  VERIFY( c == L'a' );
++}
++
++int
++main()
++{
++  test01();
++}
+Index: libstdc++-v3/testsuite/23_containers/unordered_map/cons/81891.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/23_containers/unordered_map/cons/81891.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/23_containers/unordered_map/cons/81891.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,68 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do run { target c++11 } }
++
++#include <unordered_map>
++#include <testsuite_hooks.h>
++#include <testsuite_allocator.h>
++
++struct fails_on_copy {
++  fails_on_copy() = default;
++  fails_on_copy(const fails_on_copy&) { throw 0; };
++};
++
++using value_type = std::pair<int, fails_on_copy>;
++
++void
++test01()
++{
++  value_type p;
++  try
++  {
++    std::unordered_map<int, fails_on_copy> umap(&p, &p + 1);
++  }
++  catch(...)
++  { }
++}
++
++void
++test02()
++{
++  using Alloc = __gnu_test::tracker_allocator<value_type>;
++  using std::hash;
++  using std::equal_to;
++
++  value_type p;
++  try
++  {
++    std::unordered_map<int, fails_on_copy, hash<int>, equal_to<int>, Alloc>
++	umap(&p, &p + 1);
++  }
++  catch(...)
++  { }
++
++  using counter = __gnu_test::tracker_allocator_counter;
++  VERIFY(counter::get_allocation_count() == counter::get_deallocation_count());
++}
++
++int
++main()
++{
++  test01();
++  test02();
++}
+Index: libstdc++-v3/testsuite/27_io/basic_stringstream/assign/81338.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/27_io/basic_stringstream/assign/81338.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/27_io/basic_stringstream/assign/81338.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,40 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do run { target c++11 } }
++
++#include <sstream>
++#include <testsuite_hooks.h>
++
++void
++test01()
++{
++  std::stringstream ss;
++  for (int i = 0; i < 100; ++i)
++  {
++    ss << 'a';
++    VERIFY( static_cast<bool>(ss) );
++    VERIFY( ss.str() == "a" );
++    ss = std::stringstream();
++  }
++}
++
++int
++main()
++{
++  test01();
++}
+Index: libstdc++-v3/testsuite/27_io/basic_fstream/53984.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/27_io/basic_fstream/53984.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/27_io/basic_fstream/53984.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,64 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-require-fileio "" }
++
++// PR libstdc++/53984
++
++#include <fstream>
++#include <testsuite_hooks.h>
++
++void
++test01()
++{
++  std::ifstream in(".");
++  if (in)
++  {
++    char c;
++    if (in.get(c))
++    {
++      // Reading a directory doesn't produce an error on this target
++      // so the formatted input functions below wouldn't fail anyway
++      // (see PR libstdc++/81808).
++      return;
++    }
++    int x;
++    in.clear();
++    // Formatted input function should set badbit, but not throw:
++    in >> x;
++    VERIFY( in.bad() );
++
++    in.clear();
++    in.exceptions(std::ios::badbit);
++    try
++    {
++      // Formatted input function should set badbit, and throw:
++      in >> x;
++      VERIFY( false );
++    }
++    catch (const std::exception&)
++    {
++      VERIFY( in.bad() );
++    }
++  }
++}
++
++int
++main()
++{
++  test01();
++}
+Index: libstdc++-v3/testsuite/27_io/basic_istream/sentry/char/53984.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/27_io/basic_istream/sentry/char/53984.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/27_io/basic_istream/sentry/char/53984.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,41 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++#include <streambuf>
++#include <istream>
++#include <testsuite_hooks.h>
++
++struct SB : std::streambuf
++{
++  virtual int_type underflow() { throw 1; }
++};
++
++void
++test01()
++{
++  SB sb;
++  std::istream is(&sb);
++  int i;
++  is >> i;
++  VERIFY( is.bad() );
++}
++
++int
++main()
++{
++  test01();
++}
+Index: libstdc++-v3/testsuite/27_io/basic_filebuf/sgetn/char/81395.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/27_io/basic_filebuf/sgetn/char/81395.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/27_io/basic_filebuf/sgetn/char/81395.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,46 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-require-fileio "" }
++
++// PR libstdc++/81395
++
++#include <fstream>
++#include <cstring>	// for std::memset
++#include <cstdio>	// For BUFSIZ
++
++using std::memset;
++
++int main()
++{
++  {
++    std::filebuf fb;
++    fb.open("test.txt", std::ios::out);
++    char data[BUFSIZ];
++    memset(data, 'A', sizeof(data));
++    fb.sputn(data, sizeof(data));
++  }
++
++  std::filebuf fb;
++  fb.open("test.txt", std::ios::in|std::ios::out);
++  char buf[BUFSIZ];
++  memset(buf, 0, sizeof(buf));
++  fb.sgetn(buf, sizeof(buf));
++  // Switch from reading to writing without seeking first:
++  fb.sputn("B", 1);
++  fb.pubsync();
++}
+Index: libstdc++-v3/testsuite/26_numerics/random/chi_squared_distribution/83833.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/26_numerics/random/chi_squared_distribution/83833.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/26_numerics/random/chi_squared_distribution/83833.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,40 @@
++// Copyright (C) 2018 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do run { target c++11 } }
++// { dg-additional-options "-ffloat-store" { target { m68*-*-* || ia32 } } }
++
++#include <random>
++#include <testsuite_hooks.h>
++
++void
++test01()
++{
++  std::default_random_engine r1, r2;
++  using chi = std::chi_squared_distribution<double>;
++  chi::param_type p(5);
++  chi d1(p);
++  chi d2;
++  d2.param(p);
++  VERIFY( d1(r1) == d2(r2) ); // PR libstdc++/83833
++}
++
++int
++main()
++{
++  test01();
++}
+Index: libstdc++-v3/testsuite/26_numerics/complex/inserters_extractors/char/59568.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/26_numerics/complex/inserters_extractors/char/59568.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/26_numerics/complex/inserters_extractors/char/59568.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,191 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++#include <complex>
++#include <sstream>
++#include <testsuite_hooks.h>
++
++void
++test01()
++{
++  std::istringstream in(" 1 (2) ( 2.0 , 0.5 ) ");
++  std::complex<double> c1, c2, c3;
++  in >> c1 >> c2 >> c3;
++  VERIFY( in.good() );
++  VERIFY( c1.real() == 1 && c1.imag() == 0 );
++  VERIFY( c2.real() == 2 && c2.imag() == 0 );
++  VERIFY( c3.real() == 2 && c3.imag() == 0.5 );
++}
++
++void
++test02()
++{
++  std::istringstream in;
++  std::complex<double> c(-1, -1);
++  const std::complex<double> c0 = c;
++
++  in.str("a");
++  in >> c;
++  VERIFY( in.fail() );
++  in.clear();
++  VERIFY( in.get() == 'a' );
++  VERIFY( c == c0 );
++
++  in.str(" ( ) ");
++  in >> c;
++  VERIFY( in.fail() );
++  in.clear();
++  VERIFY( in.get() == ')' );
++  VERIFY( c == c0 );
++
++  in.str("(,");
++  in >> c;
++  VERIFY( in.fail() );
++  in.clear();
++  VERIFY( in.get() == ',' );
++  VERIFY( c == c0 );
++
++  in.str("(b)");
++  in >> c;
++  VERIFY( in.fail() );
++  in.clear();
++  VERIFY( in.get() == 'b' );
++  VERIFY( c == c0 );
++
++  in.str("( c)");
++  in >> c;
++  VERIFY( in.fail() );
++  in.clear();
++  VERIFY( in.get() == 'c' );
++  VERIFY( c == c0 );
++
++  in.str("(99d");
++  in >> c;
++  VERIFY( in.fail() );
++  in.clear();
++  // VERIFY( in.get() == 'd' );
++  VERIFY( c == c0 );
++
++  in.str("(99 e");
++  in >> c;
++  VERIFY( in.fail() );
++  in.clear();
++  // VERIFY( in.get() == 'e' );
++  VERIFY( c == c0 );
++
++  in.str("(99, f");
++  in >> c;
++  VERIFY( in.fail() );
++  in.clear();
++  VERIFY( in.get() == 'f' );
++  VERIFY( c == c0 );
++
++  in.str("(99, 88g");
++  in >> c;
++  VERIFY( in.fail() );
++  in.clear();
++  // VERIFY( in.get() == 'g' );
++  VERIFY( c == c0 );
++
++  in.str("(99, 88 h");
++  in >> c;
++  VERIFY( in.fail() );
++  in.clear();
++  // VERIFY( in.get() == 'h' );
++  VERIFY( c == c0 );
++
++  in.str("(99, )");
++  in >> c;
++  VERIFY( in.fail() );
++  in.clear();
++  VERIFY( in.get() == ')' );
++  VERIFY( c == c0 );
++}
++
++void
++test03()
++{
++  // PR libstdc++/59568
++  std::istringstream in;
++  std::complex<double> c;
++
++  in.str("");
++  in >> c;
++  VERIFY( in.fail() );
++  VERIFY( in.eof() );
++  in.clear();
++
++  in.str(" ");
++  in >> c;
++  VERIFY( in.fail() );
++  VERIFY( in.eof() );
++  in.clear();
++
++  in.str("(99");
++  in >> c;
++  VERIFY( in.fail() );
++  VERIFY( in.eof() );
++  in.clear();
++
++  in.str("(99,");
++  in >> c;
++  VERIFY( in.fail() );
++  VERIFY( in.eof() );
++  in.clear();
++
++  in.str("(99,99");
++  in >> c;
++  VERIFY( in.fail() );
++  VERIFY( in.eof() );
++  in.clear();
++}
++
++void
++test04()
++{
++  // Test noskipws handling
++  std::istringstream in;
++  const char* bad_inputs[] = {
++    " 1", " (2)", "( 2)", "(2 )", "(2 ,3)", "(2,3 )", 0
++  };
++  const std::complex<double> c0(-1, -1);
++  std::complex<double> c;
++  for (int i = 0; bad_inputs[i]; ++i)
++  {
++    c = c0;
++    in.clear();
++    in.str(bad_inputs[i]);
++    in >> std::noskipws >> c;
++    VERIFY( in.fail() );
++    VERIFY( c == c0 );
++
++    in.clear();
++    in.str(bad_inputs[i]);
++    in >> std::skipws >> c;
++    VERIFY( !in.fail() );
++    VERIFY( c != c0 );
++  }
++}
++
++int
++main()
++{
++  test01();
++  test02();
++  test03();
++  test04();
++}
+Index: libstdc++-v3/testsuite/experimental/filesystem/operations/remove.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/filesystem/operations/remove.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/filesystem/operations/remove.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,100 @@
++// Copyright (C) 2018 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-options "-lstdc++fs" }
++// { dg-do run { target c++11 } }
++// { dg-require-filesystem-ts "" }
++
++#include <experimental/filesystem>
++#include <testsuite_hooks.h>
++#include <testsuite_fs.h>
++
++namespace fs = std::experimental::filesystem;
++
++void
++test01()
++{
++  std::error_code ec;
++  const std::error_code bad_ec = make_error_code(std::errc::invalid_argument);
++  bool n;
++
++  n = fs::remove("", ec);
++  VERIFY( !ec ); // This seems odd, but is what the standard requires.
++  VERIFY( !n );
++
++  auto p = __gnu_test::nonexistent_path();
++  ec = bad_ec;
++  n = remove(p, ec);
++  VERIFY( !ec );
++  VERIFY( !n );
++
++  auto link = __gnu_test::nonexistent_path();
++  create_symlink(p, link);  // dangling symlink
++  ec = bad_ec;
++  n = remove(link, ec);
++  VERIFY( !ec );
++  VERIFY( n );
++  VERIFY( !exists(symlink_status(link)) );
++
++  __gnu_test::scoped_file f(p);
++  create_symlink(p, link);
++  ec = bad_ec;
++  n = remove(link, ec);
++  VERIFY( !ec );
++  VERIFY( n );
++  VERIFY( !exists(symlink_status(link)) );  // The symlink is removed, but
++  VERIFY( exists(p) );                      // its target is not.
++
++  ec = bad_ec;
++  n = remove(p, ec);
++  VERIFY( !ec );
++  VERIFY( n );
++  VERIFY( !exists(symlink_status(p)) );
++
++  const auto dir = __gnu_test::nonexistent_path();
++  create_directories(dir/"a/b");
++  ec.clear();
++  n = remove(dir/"a", ec);
++  VERIFY( ec );
++  VERIFY( !n );
++  VERIFY( exists(dir/"a/b") );
++
++  permissions(dir, fs::perms::none, ec);
++  if (!ec)
++  {
++    ec.clear();
++    n = remove(dir/"a/b", ec);
++    VERIFY( ec );
++    VERIFY( !n );
++    permissions(dir, fs::perms::owner_all, ec);
++  }
++
++  ec = bad_ec;
++  n = remove(dir/"a/b", ec);
++  VERIFY( !ec );
++  VERIFY( n );
++  VERIFY( !exists(dir/"a/b") );
++
++  remove(dir/"a", ec);
++  remove(dir, ec);
++}
++
++int
++main()
++{
++  test01();
++}
+Index: libstdc++-v3/testsuite/experimental/filesystem/operations/temp_directory_path.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/filesystem/operations/temp_directory_path.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/filesystem/operations/temp_directory_path.cc	(.../branches/gcc-6-branch)
+@@ -44,7 +44,7 @@
+   if (!fs::exists("/tmp"))
+     return; // just give up
+ 
+-  std::error_code ec;
++  std::error_code ec = make_error_code(std::errc::invalid_argument);
+   fs::path p1 = fs::temp_directory_path(ec);
+   VERIFY( !ec );
+   VERIFY( exists(p1) );
+Index: libstdc++-v3/testsuite/experimental/filesystem/operations/remove_all.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/filesystem/operations/remove_all.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/filesystem/operations/remove_all.cc	(.../branches/gcc-6-branch)
+@@ -1,4 +1,4 @@
+-// Copyright (C) 2016 Free Software Foundation, Inc.
++// Copyright (C) 2016-2018 Free Software Foundation, Inc.
+ //
+ // This file is part of the GNU ISO C++ Library.  This library is free
+ // software; you can redistribute it and/or modify it under the
+@@ -29,19 +29,19 @@
+ test01()
+ {
+   std::error_code ec;
++  const std::error_code bad_ec = make_error_code(std::errc::invalid_argument);
+   std::uintmax_t n;
+ 
+   n = fs::remove_all("", ec);
+-  VERIFY( ec );
+-  VERIFY( n == std::uintmax_t(-1) );
++  VERIFY( !ec ); // This seems odd, but is what the TS requires.
++  VERIFY( n == 0 );
+ 
+   auto p = __gnu_test::nonexistent_path();
+-  ec.clear();
++  ec = bad_ec;
+   n = remove_all(p, ec);
+-  VERIFY( ec );
+-  VERIFY( n == std::uintmax_t(-1) );
++  VERIFY( !ec );
++  VERIFY( n == 0 );
+ 
+-  const auto bad_ec = ec;
+   auto link = __gnu_test::nonexistent_path();
+   create_symlink(p, link);  // dangling symlink
+   ec = bad_ec;
+@@ -59,7 +59,7 @@
+   VERIFY( !exists(symlink_status(link)) );  // The symlink is removed, but
+   VERIFY( exists(p) );                      // its target is not.
+ 
+-  auto dir = __gnu_test::nonexistent_path();
++  const auto dir = __gnu_test::nonexistent_path();
+   create_directories(dir/"a/b/c");
+   ec = bad_ec;
+   n = remove_all(dir/"a", ec);
+@@ -85,8 +85,28 @@
+   b2.path.clear();
+ }
+ 
++void
++test02()
++{
++  const auto dir = __gnu_test::nonexistent_path();
++  create_directories(dir/"a/b/c");
++  std::uintmax_t n = remove_all(dir/"a");
++  VERIFY( n == 3 );
++  VERIFY( exists(dir) );
++  VERIFY( !exists(dir/"a") );
++
++  n = remove_all(dir/"a");
++  VERIFY( n == 0 );
++  VERIFY( exists(dir) );
++
++  n = remove_all(dir);
++  VERIFY( n == 1 );
++  VERIFY( !exists(dir) );
++}
++
+ int
+ main()
+ {
+   test01();
++  test02();
+ }
+Index: libstdc++-v3/testsuite/experimental/filesystem/operations/create_directory.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/filesystem/operations/create_directory.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/filesystem/operations/create_directory.cc	(.../branches/gcc-6-branch)
+@@ -50,7 +50,6 @@
+   VERIFY( !ec );
+   VERIFY( !b );
+   b = create_directory(p);
+-  VERIFY( !ec );
+   VERIFY( !b );
+ 
+   remove_all(p, ec);
+Index: libstdc++-v3/testsuite/experimental/filesystem/iterators/recursive_directory_iterator.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/filesystem/iterators/recursive_directory_iterator.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/filesystem/iterators/recursive_directory_iterator.cc	(.../branches/gcc-6-branch)
+@@ -28,6 +28,7 @@
+ test01()
+ {
+   bool test __attribute__((unused)) = false;
++  const std::error_code bad_ec = make_error_code(std::errc::invalid_argument);
+   std::error_code ec;
+ 
+   // Test non-existent path.
+@@ -37,15 +38,19 @@
+   VERIFY( iter == end(iter) );
+ 
+   // Test empty directory.
++  ec = bad_ec;
+   create_directory(p, fs::current_path(), ec);
+   VERIFY( !ec );
++  ec = bad_ec;
+   iter = fs::recursive_directory_iterator(p, ec);
+   VERIFY( !ec );
+   VERIFY( iter == end(iter) );
+ 
+   // Test non-empty directory.
+-  create_directories(p / "d1/d2");
++  ec = bad_ec;
++  create_directories(p / "d1/d2", ec);
+   VERIFY( !ec );
++  ec = bad_ec;
+   iter = fs::recursive_directory_iterator(p, ec);
+   VERIFY( !ec );
+   VERIFY( iter != end(iter) );
+@@ -56,6 +61,7 @@
+   VERIFY( iter == end(iter) );
+ 
+   // Test inaccessible directory.
++  ec = bad_ec;
+   permissions(p, fs::perms::none, ec);
+   VERIFY( !ec );
+   iter = fs::recursive_directory_iterator(p, ec);
+@@ -64,15 +70,19 @@
+ 
+   // Test inaccessible directory, skipping permission denied.
+   const auto opts = fs::directory_options::skip_permission_denied;
++  ec = bad_ec;
+   iter = fs::recursive_directory_iterator(p, opts, ec);
+   VERIFY( !ec );
+   VERIFY( iter == end(iter) );
+ 
+   // Test inaccessible sub-directory.
++  ec = bad_ec;
+   permissions(p, fs::perms::owner_all, ec);
+   VERIFY( !ec );
++  ec = bad_ec;
+   permissions(p/"d1/d2", fs::perms::none, ec);
+   VERIFY( !ec );
++  ec = bad_ec;
+   iter = fs::recursive_directory_iterator(p, ec);
+   VERIFY( !ec );
+   VERIFY( iter != end(iter) );
+@@ -84,6 +94,7 @@
+   VERIFY( iter == end(iter) );
+ 
+   // Test inaccessible sub-directory, skipping permission denied.
++  ec = bad_ec;
+   iter = fs::recursive_directory_iterator(p, opts, ec);
+   VERIFY( !ec );
+   VERIFY( iter != end(iter) );
+@@ -90,6 +101,7 @@
+   VERIFY( iter->path() == p/"d1" );
+   ++iter;              // should recurse into d1
+   VERIFY( iter->path() == p/"d1/d2" );
++  ec = bad_ec;
+   iter.increment(ec);  // should fail to recurse into p/d1/d2, so skip it
+   VERIFY( !ec );
+   VERIFY( iter == end(iter) );
+@@ -103,12 +115,15 @@
+ {
+   bool test __attribute__((unused)) = false;
+ 
++  const std::error_code bad_ec = make_error_code(std::errc::invalid_argument);
+   std::error_code ec;
+   const auto p = __gnu_test::nonexistent_path();
++  ec = bad_ec;
+   create_directories(p / "d1/d2", ec);
+   VERIFY( !ec );
+ 
+   // Test post-increment (libstdc++/71005)
++  ec = bad_ec;
+   auto iter = fs::recursive_directory_iterator(p, ec);
+   VERIFY( !ec );
+   VERIFY( iter != end(iter) );
+@@ -130,7 +145,7 @@
+ {
+   bool test __attribute__((unused)) = false;
+ 
+-  std::error_code ec;
++  std::error_code ec = make_error_code(std::errc::invalid_argument);
+   const auto p = __gnu_test::nonexistent_path();
+   create_directories(p / "longer_than_small_string_buffer", ec);
+   VERIFY( !ec );
+Index: libstdc++-v3/testsuite/experimental/filesystem/path/itr/traversal.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/filesystem/path/itr/traversal.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/filesystem/path/itr/traversal.cc	(.../branches/gcc-6-branch)
+@@ -78,9 +78,27 @@
+   }
+ }
+ 
++void
++test03()
++{
++  path paths[] = { "single", "multiple/elements" };
++  for (const path& p : paths)
++    for (auto iter = p.begin(); iter != p.end(); ++iter)
++    {
++      auto iter2 = iter;
++      ++iter;
++      iter2++;
++      VERIFY( iter2 == iter );
++      --iter;
++      iter2--;
++      VERIFY( iter2 == iter );
++    }
++}
++
+ int
+ main()
+ {
+   test01();
+   test02();
++  test03();
+ }
+Index: libstdc++-v3/testsuite/17_intro/names.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/17_intro/names.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/17_intro/names.cc	(.../branches/gcc-6-branch)
+@@ -107,4 +107,9 @@
+ #undef y
+ #endif
+ 
++#ifdef __hpux__
++#undef d
++#undef r
++#endif
++
+ #include <bits/stdc++.h>
+Index: libstdc++-v3/testsuite/20_util/owner_less/noexcept.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/owner_less/noexcept.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/owner_less/noexcept.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,31 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do compile { target c++11 } }
++
++#include <memory>
++
++const std::shared_ptr<int> si;
++const std::weak_ptr<int> wi;
++const std::owner_less<std::shared_ptr<int>> osi;
++static_assert( noexcept(osi(si, si)), "" );
++static_assert( noexcept(osi(si, wi)), "" );
++static_assert( noexcept(osi(wi, si)), "" );
++const std::owner_less<std::weak_ptr<int>> owi;
++static_assert( noexcept(owi(wi, wi)), "" );
++static_assert( noexcept(owi(si, wi)), "" );
++static_assert( noexcept(owi(wi, si)), "" );
+Index: libstdc++-v3/testsuite/20_util/duration/literals/range.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/duration/literals/range.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/duration/literals/range.cc	(.../branches/gcc-6-branch)
+@@ -27,5 +27,5 @@
+ 
+   // std::numeric_limits<int64_t>::max() == 9223372036854775807;
+   auto h = 9223372036854775808h;
+-  // { dg-error "cannot be represented" "" { target *-*-* } 797 }
++  // { dg-error "cannot be represented" "" { target *-*-* } 798 }
+ }
+Index: libstdc++-v3/testsuite/20_util/duration/literals/84671.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/duration/literals/84671.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/duration/literals/84671.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,26 @@
++// Copyright (C) 2018 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do compile { target c++14 } }
++
++#include <chrono>
++
++// PR libstdc++/84671
++using namespace std::literals::chrono_literals;
++constexpr auto ns_ok = 12113ns;
++constexpr auto ns_fail = 12'11'3ns;
++static_assert(ns_ok == ns_fail, "digit separators work in duration literals");
+Index: libstdc++-v3/testsuite/20_util/duration/cons/dr1177.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/duration/cons/dr1177.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/duration/cons/dr1177.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,41 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do compile { target c++11 } }
++
++#include <chrono>
++#include <type_traits>
++
++using namespace std;
++using namespace std::chrono;
++
++// DR 1177
++static_assert(is_constructible<duration<float>, duration<double>>{},
++    "can convert duration with one floating point rep to another");
++static_assert(is_constructible<duration<float>, duration<int>>{},
++    "can convert duration with integral rep to one with floating point rep");
++static_assert(!is_constructible<duration<int>, duration<float>>{},
++    "cannot convert duration with floating point rep to one with integral rep");
++static_assert(is_constructible<duration<int>, duration<long>>{},
++    "can convert duration with one integral rep to another");
++
++static_assert(!is_constructible<duration<int>, duration<int, ratio<2,3>>>{},
++    "cannot convert duration to one with different period");
++static_assert(is_constructible<duration<float>, duration<int, ratio<2,3>>>{},
++    "unless it has a floating-point representation");
++static_assert(is_constructible<duration<float>, duration<int, ratio<1,3>>>{},
++    "or a period that is an integral multiple of the original");
+Index: libstdc++-v3/testsuite/20_util/shared_ptr/observers/owner_before.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/shared_ptr/observers/owner_before.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/shared_ptr/observers/owner_before.cc	(.../branches/gcc-6-branch)
+@@ -71,6 +71,12 @@
+   VERIFY( !a1.owner_before(w1) && !w1.owner_before(a1) );
+   std::weak_ptr<A> w2(a2);
+   VERIFY( !b1.owner_before(w2) && !w2.owner_before(b1) );
++
++  static_assert( noexcept(a1.owner_before(a0)), "" );
++  static_assert( noexcept(a1.owner_before(b1)), "" );
++  static_assert( noexcept(b1.owner_before(a1)), "" );
++  static_assert( noexcept(a1.owner_before(w1)), "" );
++  static_assert( noexcept(b1.owner_before(w1)), "" );
+ }
+ 
+ // Aliasing
+Index: libstdc++-v3/testsuite/20_util/function/assign/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/function/assign/move.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/function/assign/move.cc	(.../branches/gcc-6-branch)
+@@ -40,11 +40,12 @@
+   fo2 = (std::move(fo));
+   VERIFY( static_cast<bool>(fo2) );
+   VERIFY( fo2() == 2 );
++
++  static_assert(std::is_nothrow_move_assignable<function>::value,
++		"PR libstdc++/81017");
+ }
+ 
+ int main()
+ {
+   test01();
+-
+-  return 0;
+ }
+Index: libstdc++-v3/testsuite/20_util/function/cons/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/function/cons/move.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/function/cons/move.cc	(.../branches/gcc-6-branch)
+@@ -38,11 +38,12 @@
+   function fo2(std::move(fo));
+   VERIFY( static_cast<bool>(fo2) );
+   VERIFY( fo2() == 2 );
++
++  static_assert(std::is_nothrow_move_constructible<function>::value,
++		"PR libstdc++/81017");
+ }
+ 
+ int main()
+ {
+   test01();
+-
+-  return 0;
+ }
+Index: libstdc++-v3/testsuite/20_util/weak_ptr/observers/owner_before.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/weak_ptr/observers/owner_before.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/weak_ptr/observers/owner_before.cc	(.../branches/gcc-6-branch)
+@@ -27,7 +27,7 @@
+ 
+ // 20.6.6.3.5 weak_ptr observers [util.smartptr.weak.obs]
+ 
+-int
++void
+ test01()
+ {
+   bool test __attribute__((unused)) = true;
+@@ -40,11 +40,14 @@
+   std::shared_ptr<B> p3;
+   VERIFY( !p1.owner_before(p3) && !p3.owner_before(p1) );
+ 
+-  return 0;
++  static_assert( noexcept(p1.owner_before(p1)), "" );
++  static_assert( noexcept(p1.owner_before(p2)), "" );
++  static_assert( noexcept(p1.owner_before(p3)), "" );
++  static_assert( noexcept(p2.owner_before(p1)), "" );
+ }
+ 
+ 
+-int
++void
+ test02()
+ {
+   bool test __attribute__((unused)) = true;
+@@ -64,8 +67,6 @@
+ 
+   std::shared_ptr<B> b1(new B);
+   VERIFY( w1.owner_before(b1) || b1.owner_before(w1) );
+-
+-  return 0;
+ }
+ 
+ int 
+Index: libstdc++-v3/testsuite/20_util/time_point/cons/81468.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/time_point/cons/81468.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/time_point/cons/81468.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,34 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do compile { target c++11 } }
++
++#include <chrono>
++#include <type_traits>
++
++using namespace std;
++using namespace std::chrono;
++
++template <class Duration>
++    using sys_time = time_point<system_clock, Duration>;
++
++static_assert(is_constructible<sys_time<milliseconds>, sys_time<seconds>>{},
++    "Can construct time_point from one with lower precision duration");
++
++// PR libstdc++/81468 - DR 1177
++static_assert(!is_constructible<sys_time<seconds>, sys_time<milliseconds>>{},
++    "Cannot construct time_point from one with higher precision duration");
+Index: libstdc++-v3/config/io/basic_file_stdio.cc
+===================================================================
+--- a/src/libstdc++-v3/config/io/basic_file_stdio.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/config/io/basic_file_stdio.cc	(.../branches/gcc-6-branch)
+@@ -195,11 +195,13 @@
+     __basic_file* __ret = NULL;
+     if (!this->is_open() && __file)
+       {
+-	int __err;
+-	errno = 0;	
++	int __err, __save_errno = errno;
++	// POSIX guarantees that fflush sets errno on error, but C doesn't.
++	errno = 0;
+ 	do
+-	  __err = this->sync();
++	  __err = fflush(__file);
+ 	while (__err && errno == EINTR);
++	errno = __save_errno;
+ 	if (!__err)
+ 	  {
+ 	    _M_cfile = __file;
+Index: libstdc++-v3/config/abi/pre/gnu.ver
+===================================================================
+--- a/src/libstdc++-v3/config/abi/pre/gnu.ver	(.../tags/gcc_6_4_0_release)
++++ b/src/libstdc++-v3/config/abi/pre/gnu.ver	(.../branches/gcc-6-branch)
+@@ -60,7 +60,7 @@
+       std::basic_[t-z]*;
+       std::ba[t-z]*;
+       std::b[b-z]*;
+-      std::c[a-g]*;
++      std::cerr;
+ #     std::char_traits;
+ #     std::c[i-z]*;
+       std::c[i-n]*;
+Index: lto-plugin/ChangeLog
+===================================================================
+--- a/src/lto-plugin/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/lto-plugin/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,12 @@
++2017-07-26  Georg-Johann Lay  <avr@gjlay.de>
++
++	Backport from 2017-07-26 gcc-7-branch r250562.
++
++	PR lto/81487
++	* lto-plugin.c (claim_file_handler): Use xasprintf instead of
++	asprintf.
++	[hi!=0]: Swap hi and lo arguments supplied to xasprintf.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: lto-plugin/lto-plugin.c
+===================================================================
+--- a/src/lto-plugin/lto-plugin.c	(.../tags/gcc_6_4_0_release)
++++ b/src/lto-plugin/lto-plugin.c	(.../branches/gcc-6-branch)
+@@ -975,17 +975,16 @@
+ 
+   if (file->offset != 0)
+     {
+-      char *objname;
+       /* We pass the offset of the actual file, not the archive header.
+          Can't use PRIx64, because that's C99, so we have to print the
+-	 64-bit hex int as two 32-bit ones. */
+-      int lo, hi, t;
++	 64-bit hex int as two 32-bit ones.  Use xasprintf instead of
++	 asprintf because asprintf doesn't work as expected on some older
++	 mingw32 hosts.  */
++      int lo, hi;
+       lo = file->offset & 0xffffffff;
+       hi = ((int64_t)file->offset >> 32) & 0xffffffff;
+-      t = hi ? asprintf (&objname, "%s@0x%x%08x", file->name, lo, hi)
+-	     : asprintf (&objname, "%s@0x%x", file->name, lo);
+-      check (t >= 0, LDPL_FATAL, "asprintf failed");
+-      lto_file.name = objname;
++      lto_file.name = hi ? xasprintf ("%s@0x%x%08x", file->name, hi, lo)
++      			 : xasprintf ("%s@0x%x", file->name, lo);
+     }
+   else
+     {
+Index: contrib/ChangeLog
+===================================================================
+--- a/src/contrib/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/contrib/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,7 @@
++2017-10-02  Thomas Schwinge  <thomas@codesourcery.com>
++
++	* gcc_update (files_and_dependencies): Handle libbacktrace.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: contrib/gcc_update
+===================================================================
+--- a/src/contrib/gcc_update	(.../tags/gcc_6_4_0_release)
++++ b/src/contrib/gcc_update	(.../branches/gcc-6-branch)
+@@ -173,6 +173,10 @@
+ liboffloadmic/plugin/aclocal.m4: liboffloadmic/plugin/configure.ac
+ liboffloadmic/plugin/Makefile.in: liboffloadmic/plugin/Makefile.am
+ liboffloadmic/plugin/configure: liboffloadmic/plugin/configure.ac
++libbacktrace/aclocal.m4: libbacktrace/configure.ac
++libbacktrace/Makefile.in: libbacktrace/Makefile.am libbacktrace/aclocal.m4
++libbacktrace/configure: libbacktrace/configure.ac libbacktrace/aclocal.m4
++libbacktrace/config.h.in: libbacktrace/configure.ac libbacktrace/aclocal.m4
+ # Top level
+ Makefile.in: Makefile.tpl Makefile.def
+ configure: configure.ac config/acx.m4
+Index: libjava/include/i386-signal.h
+===================================================================
+--- a/src/libjava/include/i386-signal.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libjava/include/i386-signal.h	(.../branches/gcc-6-branch)
+@@ -29,7 +29,7 @@
+ #define HANDLE_DIVIDE_OVERFLOW						\
+ do									\
+ {									\
+-  struct ucontext *_uc = (struct ucontext *)_p;				\
++  ucontext_t *_uc = (ucontext_t *)_p;					\
+   gregset_t &_gregs = _uc->uc_mcontext.gregs;				\
+   unsigned char *_eip = (unsigned char *)_gregs[REG_EIP];		\
+ 									\
+Index: libjava/include/s390-signal.h
+===================================================================
+--- a/src/libjava/include/s390-signal.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libjava/include/s390-signal.h	(.../branches/gcc-6-branch)
+@@ -51,7 +51,7 @@
+   struct                                                                \
+   {                                                                     \
+     unsigned long int uc_flags;                                         \
+-    struct ucontext *uc_link;                                           \
++    ucontext_t *uc_link;                                                \
+     stack_t uc_stack;                                                   \
+     mcontext_t uc_mcontext;                                             \
+     unsigned long sigmask[2];                                           \
+Index: libjava/include/x86_64-signal.h
+===================================================================
+--- a/src/libjava/include/x86_64-signal.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libjava/include/x86_64-signal.h	(.../branches/gcc-6-branch)
+@@ -28,7 +28,7 @@
+ #define HANDLE_DIVIDE_OVERFLOW						\
+ do									\
+ {									\
+-  struct ucontext *_uc = (struct ucontext *)_p;				\
++  ucontext_t *_uc = (ucontext_t *)_p;					\
+   gregset_t &_gregs = _uc->uc_mcontext.gregs;				\
+   unsigned char *_rip = (unsigned char *)_gregs[REG_RIP];		\
+ 									\
+Index: libjava/ChangeLog
+===================================================================
+--- a/src/libjava/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/libjava/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,10 @@
++2017-09-07  Matthias Klose  <doko@ubuntu.com>
++
++	* include/x86_64-signal.h (HANDLE_DIVIDE_OVERFLOW): Replace
++	'struct ucontext' with ucontext_t.
++	* include/i386-signal.h (HANDLE_DIVIDE_OVERFLOW): Likewise.
++	* include/s390-signal.h (HANDLE_DIVIDE_OVERFLOW): Likewise.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: libgcc/config.host
+===================================================================
+--- a/src/libgcc/config.host	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config.host	(.../branches/gcc-6-branch)
+@@ -277,7 +277,7 @@
+   tmake_file="$tmake_file $cpu_type/t-sol2"
+   extra_parts="gmon.o crtbegin.o crtend.o"
+   if test "${libgcc_cv_solaris_crts}" = yes; then
+-    # Solaris 11.x and 12 provide crt1.o, crti.o, and crtn.o as part of the
++    # Solaris 11.4 provides crt1.o, crti.o, and crtn.o as part of the
+     # base system.  crtp.o and crtpg.o implement the compiler-dependent parts.
+     extra_parts="$extra_parts crtp.o crtpg.o"
+     # If the Solaris CRTs are present, both ld and gld will have PIE support.
+Index: libgcc/configure.ac
+===================================================================
+--- a/src/libgcc/configure.ac	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/configure.ac	(.../branches/gcc-6-branch)
+@@ -294,7 +294,7 @@
+ 
+ case ${host} in
+ *-*-solaris2*)
+-  # Check for system-provided CRTs on Solaris 11.x and Solaris 12.
++  # Check for system-provided CRTs on Solaris 11.4.
+   AC_CACHE_CHECK([system-provided CRTs on Solaris],
+     		 [libgcc_cv_solaris_crts],
+     [libgcc_cv_solaris_crts=no
+Index: libgcc/ChangeLog
+===================================================================
+--- a/src/libgcc/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,82 @@
++2018-03-11  John David Anglin  <danglin@gcc.gnu.org>
++
++	Backport from mainline
++	2018-03-06  John David Anglin  <danglin@gcc.gnu.org>
++
++	* config/pa/fptr.c (_dl_read_access_allowed): New.
++	(__canonicalize_funcptr_for_compare): Use it.
++	
++2018-02-20  Max Filippov  <jcmvbkbc@gmail.com>
++
++	Backport from mainline
++	2018-02-20  Max Filippov  <jcmvbkbc@gmail.com>
++
++	* config/xtensa/ieee754-df.S (__adddf3_aux): Add
++	.literal_position directive.
++	* config/xtensa/ieee754-sf.S (__addsf3_aux): Likewise.
++
++2018-01-23  Max Filippov  <jcmvbkbc@gmail.com>
++
++	Backport from mainline
++	2018-01-23  Max Filippov  <jcmvbkbc@gmail.com>
++
++	* config/xtensa/ieee754-df.S (__addsf3, __subsf3, __mulsf3)
++	(__divsf3): Make NaN return value quiet.
++	* config/xtensa/ieee754-sf.S (__adddf3, __subdf3, __muldf3)
++	(__divdf3): Make NaN return value quiet.
++
++2017-11-21  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	Backport from mainline
++	2017-11-14  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	* config.host (*-*-solaris2*): Adapt comment for Solaris 12
++	renaming.
++	* config/sol2/crtpg.c (__start_crt_compiler): Likewise.
++	* configure.ac (libgcc_cv_solaris_crts): Likewise.
++	* configure: Regenerate.
++
++2017-11-05  Andreas Tobler  <andreast@gcc.gnu.org>
++
++	Backport from mainline
++	2017-11-04  Andreas Tobler  <andreast@gcc.gnu.org>
++
++	PR libgcc/82635
++	* config/i386/freebsd-unwind.h (MD_FALLBACK_FRAME_STATE_FOR): Use a
++	sysctl to determine whether we're in a trampoline.
++	Keep the pattern matching method for systems without
++	KERN_PROC_SIGTRAMP sysctl.
++
++2017-10-13  Jakub Jelinek  <jakub@redhat.com>
++
++	PR target/82274
++	* libgcc2.c (__mulvDI3): If both operands have
++	the same highpart of -1 and the topmost bit of lowpart is 0,
++	multiplication overflows even if both lowparts are 0.
++
++2017-07-20  Peter Bergner  <bergner@vnet.ibm.com>
++
++	Backport from mainline
++	2017-07-07  Peter Bergner  <bergner@vnet.ibm.com>
++
++	* config/rs6000/float128-ifunc.c: Don't include auxv.h.
++	(have_ieee_hw_p): Delete function.
++	(SW_OR_HW) Use __builtin_cpu_supports().
++
++2017-07-04  Joseph Myers  <joseph@codesourcery.com>
++
++	* config/aarch64/linux-unwind.h (aarch64_fallback_frame_state),
++	config/alpha/linux-unwind.h (alpha_fallback_frame_state),
++	config/bfin/linux-unwind.h (bfin_fallback_frame_state),
++	config/i386/linux-unwind.h (x86_64_fallback_frame_state,
++	x86_fallback_frame_state), config/m68k/linux-unwind.h (struct
++	uw_ucontext), config/nios2/linux-unwind.h (struct nios2_ucontext),
++	config/pa/linux-unwind.h (pa32_fallback_frame_state),
++	config/sh/linux-unwind.h (sh_fallback_frame_state),
++	config/tilepro/linux-unwind.h (tile_fallback_frame_state),
++	config/xtensa/linux-unwind.h (xtensa_fallback_frame_state): Use
++	ucontext_t instead of struct ucontext.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: libgcc/config/alpha/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/alpha/linux-unwind.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/alpha/linux-unwind.h	(.../branches/gcc-6-branch)
+@@ -51,7 +51,7 @@
+     {
+       struct rt_sigframe {
+ 	siginfo_t info;
+-	struct ucontext uc;
++	ucontext_t uc;
+       } *rt_ = context->cfa;
+       sc = &rt_->uc.uc_mcontext;
+     }
+Index: libgcc/config/m68k/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/m68k/linux-unwind.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/m68k/linux-unwind.h	(.../branches/gcc-6-branch)
+@@ -33,7 +33,7 @@
+ /* <sys/ucontext.h> is unfortunately broken right now.  */
+ struct uw_ucontext {
+ 	unsigned long	  uc_flags;
+-	struct ucontext  *uc_link;
++	ucontext_t	 *uc_link;
+ 	stack_t		  uc_stack;
+ 	mcontext_t	  uc_mcontext;
+ 	unsigned long	  uc_filler[80];
+Index: libgcc/config/aarch64/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/aarch64/linux-unwind.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/aarch64/linux-unwind.h	(.../branches/gcc-6-branch)
+@@ -52,7 +52,7 @@
+   struct rt_sigframe
+   {
+     siginfo_t info;
+-    struct ucontext uc;
++    ucontext_t uc;
+   };
+ 
+   struct rt_sigframe *rt_;
+Index: libgcc/config/i386/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/i386/linux-unwind.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/i386/linux-unwind.h	(.../branches/gcc-6-branch)
+@@ -58,7 +58,7 @@
+   if (*(unsigned char *)(pc+0) == 0x48
+       && *(unsigned long long *)(pc+1) == RT_SIGRETURN_SYSCALL)
+     {
+-      struct ucontext *uc_ = context->cfa;
++      ucontext_t *uc_ = context->cfa;
+       /* The void * cast is necessary to avoid an aliasing warning.
+          The aliasing warning is correct, but should not be a problem
+          because it does not alias anything.  */
+@@ -138,7 +138,7 @@
+ 	siginfo_t *pinfo;
+ 	void *puc;
+ 	siginfo_t info;
+-	struct ucontext uc;
++	ucontext_t uc;
+       } *rt_ = context->cfa;
+       /* The void * cast is necessary to avoid an aliasing warning.
+          The aliasing warning is correct, but should not be a problem
+Index: libgcc/config/i386/freebsd-unwind.h
+===================================================================
+--- a/src/libgcc/config/i386/freebsd-unwind.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/i386/freebsd-unwind.h	(.../branches/gcc-6-branch)
+@@ -28,7 +28,10 @@
+ 
+ #include <sys/types.h>
+ #include <signal.h>
++#include <unistd.h>
++#include <sys/sysctl.h>
+ #include <sys/ucontext.h>
++#include <sys/user.h>
+ #include <machine/sigframe.h>
+ 
+ #define REG_NAME(reg)	sf_uc.uc_mcontext.mc_## reg
+@@ -36,6 +39,38 @@
+ #ifdef __x86_64__
+ #define MD_FALLBACK_FRAME_STATE_FOR x86_64_freebsd_fallback_frame_state
+ 
++#ifdef KERN_PROC_SIGTRAMP
++/* FreeBSD past 9.3 provides a kern.proc.sigtramp.<pid> sysctl that
++   returns the location of the signal trampoline. Use this to find
++   out whether we're in a trampoline.
++*/
++static int
++x86_64_outside_sigtramp_range (unsigned char *pc)
++{
++  static int sigtramp_range_determined = 0;
++  static unsigned char *sigtramp_start, *sigtramp_end;
++
++  if (sigtramp_range_determined == 0)
++    {
++      struct kinfo_sigtramp kst = {0};
++      size_t len = sizeof (kst);
++      int mib[4] = { CTL_KERN, KERN_PROC, KERN_PROC_SIGTRAMP, getpid() };
++
++      sigtramp_range_determined = 1;
++      if (sysctl (mib, 4, &kst, &len, NULL, 0) == 0)
++      {
++        sigtramp_range_determined = 2;
++        sigtramp_start = kst.ksigtramp_start;
++        sigtramp_end   = kst.ksigtramp_end;
++      }
++    }
++  if (sigtramp_range_determined < 2)  /* sysctl failed if < 2 */
++    return 1;
++
++  return (pc < sigtramp_start || pc >= sigtramp_end);
++}
++#endif
++
+ static _Unwind_Reason_Code
+ x86_64_freebsd_fallback_frame_state
+ (struct _Unwind_Context *context, _Unwind_FrameState *fs)
+@@ -43,6 +78,7 @@
+   struct sigframe *sf;
+   long new_cfa;
+ 
++#ifndef KERN_PROC_SIGTRAMP
+   /* Prior to FreeBSD 9, the signal trampoline was located immediately
+      before the ps_strings.  To support non-executable stacks on AMD64,
+      the sigtramp was moved to a shared page for FreeBSD 9.  Unfortunately
+@@ -62,12 +98,15 @@
+         && *(unsigned int *)(context->ra +  8) == 0x01a1c0c7
+         && *(unsigned int *)(context->ra + 12) == 0x050f0000 ))
+     return _URC_END_OF_STACK;
++#else
++  if (x86_64_outside_sigtramp_range(context->ra))
++    return _URC_END_OF_STACK;
++#endif
+ 
+   sf = (struct sigframe *) context->cfa;
+   new_cfa = sf->REG_NAME(rsp);
+   fs->regs.cfa_how = CFA_REG_OFFSET;
+-  /* Register 7 is rsp  */
+-  fs->regs.cfa_reg = 7;
++  fs->regs.cfa_reg =  __LIBGCC_STACK_POINTER_REGNUM__;
+   fs->regs.cfa_offset = new_cfa - (long) context->cfa;
+ 
+   /* The SVR4 register numbering macros aren't usable in libgcc.  */
+Index: libgcc/config/rs6000/float128-ifunc.c
+===================================================================
+--- a/src/libgcc/config/rs6000/float128-ifunc.c	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/rs6000/float128-ifunc.c	(.../branches/gcc-6-branch)
+@@ -45,48 +45,8 @@
+ #error "This module must not be compiled with IEEE 128-bit hardware support"
+ #endif
+ 
+-#include <sys/auxv.h>
++#define SW_OR_HW(SW, HW) (__builtin_cpu_supports ("ieee128") ? HW : SW)
+ 
+-/* Use the namespace clean version of getauxval.  However, not all versions of
+-   sys/auxv.h declare it, so declare it here.  This code is intended to be
+-   temporary until a suitable version of __builtin_cpu_supports is added that
+-   allows us to tell quickly if the machine supports IEEE 128-bit hardware.  */
+-extern unsigned long __getauxval (unsigned long);
+-
+-static int
+-have_ieee_hw_p (void)
+-{
+-  static int ieee_hw_p = -1;
+-
+-  if (ieee_hw_p < 0)
+-    {
+-      char *p = (char *) __getauxval (AT_PLATFORM);
+-
+-      ieee_hw_p = 0;
+-
+-      /* Don't use atoi/strtol/strncmp/etc.  These may require the normal
+-	 environment to be setup to set errno to 0, and the ifunc resolvers run
+-	 before the whole glibc environment is initialized.  */
+-      if (p && p[0] == 'p' && p[1] == 'o' && p[2] == 'w' && p[3] == 'e'
+-	  && p[4] == 'r')
+-	{
+-	  long n = 0;
+-	  char ch;
+-
+-	  p += 5;
+-	  while ((ch = *p++) >= '0' && (ch <= '9'))
+-	    n = (n * 10) + (ch - '0');
+-
+-	  if (n >= 9)
+-	    ieee_hw_p = 1;
+-	}
+-    }
+-
+-  return ieee_hw_p;
+-}
+-
+-#define SW_OR_HW(SW, HW) (have_ieee_hw_p () ? HW : SW)
+-
+ /* Resolvers.  */
+ 
+ /* We do not provide ifunc resolvers for __fixkfti, __fixunskfti, __floattikf,
+Index: libgcc/config/sh/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/sh/linux-unwind.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/sh/linux-unwind.h	(.../branches/gcc-6-branch)
+@@ -180,7 +180,7 @@
+     {
+       struct rt_sigframe {
+ 	siginfo_t info;
+-	struct ucontext uc;
++	ucontext_t uc;
+       } *rt_ = context->cfa;
+       /* The void * cast is necessary to avoid an aliasing warning.
+          The aliasing warning is correct, but should not be a problem
+Index: libgcc/config/tilepro/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/tilepro/linux-unwind.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/tilepro/linux-unwind.h	(.../branches/gcc-6-branch)
+@@ -61,7 +61,7 @@
+   struct rt_sigframe {
+     unsigned char save_area[C_ABI_SAVE_AREA_SIZE];
+     siginfo_t info;
+-    struct ucontext uc;
++    ucontext_t uc;
+   } *rt_;
+ 
+   /* Return if this is not a signal handler.  */
+Index: libgcc/config/pa/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/pa/linux-unwind.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/pa/linux-unwind.h	(.../branches/gcc-6-branch)
+@@ -80,7 +80,7 @@
+   struct sigcontext *sc;
+   struct rt_sigframe {
+     siginfo_t info;
+-    struct ucontext uc;
++    ucontext_t uc;
+   } *frame;
+ 
+   /* rt_sigreturn trampoline:
+Index: libgcc/config/pa/fptr.c
+===================================================================
+--- a/src/libgcc/config/pa/fptr.c	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/pa/fptr.c	(.../branches/gcc-6-branch)
+@@ -52,6 +52,16 @@
+ typedef int (*fixup_t) (struct link_map *, unsigned int);
+ extern unsigned int _GLOBAL_OFFSET_TABLE_;
+ 
++static inline int
++_dl_read_access_allowed (unsigned int *addr)
++{
++  int result;
++
++  asm ("proberi (%1),3,%0" : "=r" (result) : "r" (addr) : );
++
++  return result;
++}
++
+ /* __canonicalize_funcptr_for_compare must be hidden so that it is not
+    placed in the dynamic symbol table.  Like millicode functions, it
+    must be linked into all binaries in order access the got table of 
+@@ -82,6 +92,16 @@
+      The second word in the plabel contains the relocation offset for the
+      function.  */
+   plabel = (unsigned int *) ((unsigned int) fptr & ~3);
++  if (!_dl_read_access_allowed (plabel))
++    return (unsigned int) fptr;
++
++  /* Load first word of candidate descriptor.  It should be a pointer
++     with word alignment and point to memory that can be read.  */
++  got = (unsigned int *) plabel[0];
++  if (((unsigned int) got & 3) != 0
++      || !_dl_read_access_allowed (got))
++    return (unsigned int) fptr;
++
+   got = (unsigned int *) (plabel[0] + GOT_FROM_PLT_STUB);
+ 
+   /* Return the address of the function if the plabel has been resolved.  */
+Index: libgcc/config/xtensa/ieee754-df.S
+===================================================================
+--- a/src/libgcc/config/xtensa/ieee754-df.S	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/xtensa/ieee754-df.S	(.../branches/gcc-6-branch)
+@@ -55,6 +55,7 @@
+ 
+ #ifdef L_addsubdf3
+ 
++	.literal_position
+ 	/* Addition */
+ __adddf3_aux:
+ 	
+@@ -64,19 +65,28 @@
+ 
+ .Ladd_xnan_or_inf:
+ 	/* If y is neither Infinity nor NaN, return x.  */
+-	bnall	yh, a6, 1f
++	bnall	yh, a6, .Ladd_return_nan_or_inf
+ 	/* If x is a NaN, return it.  Otherwise, return y.  */
+ 	slli	a7, xh, 12
+ 	or	a7, a7, xl
+-	beqz	a7, .Ladd_ynan_or_inf
+-1:	leaf_return
++	bnez	a7, .Ladd_return_nan
+ 
+ .Ladd_ynan_or_inf:
+ 	/* Return y.  */
+ 	mov	xh, yh
+ 	mov	xl, yl
++
++.Ladd_return_nan_or_inf:
++	slli	a7, xh, 12
++	or	a7, a7, xl
++	bnez	a7, .Ladd_return_nan
+ 	leaf_return
+ 
++.Ladd_return_nan:
++	movi	a4, 0x80000	/* make it a quiet NaN */
++	or	xh, xh, a4
++	leaf_return
++
+ .Ladd_opposite_signs:
+ 	/* Operand signs differ.  Do a subtraction.  */
+ 	slli	a7, a6, 11
+@@ -319,11 +329,13 @@
+ 
+ .Lsub_xnan_or_inf:
+ 	/* If y is neither Infinity nor NaN, return x.  */
+-	bnall	yh, a6, 1f
++	bnall	yh, a6, .Lsub_return_nan_or_inf
++
++.Lsub_return_nan:
+ 	/* Both x and y are either NaN or Inf, so the result is NaN.  */
+ 	movi	a4, 0x80000	/* make it a quiet NaN */
+ 	or	xh, xh, a4
+-1:	leaf_return
++	leaf_return
+ 
+ .Lsub_ynan_or_inf:
+ 	/* Negate y and return it.  */
+@@ -330,6 +342,11 @@
+ 	slli	a7, a6, 11
+ 	xor	xh, yh, a7
+ 	mov	xl, yl
++
++.Lsub_return_nan_or_inf:
++	slli	a7, xh, 12
++	or	a7, a7, xl
++	bnez	a7, .Lsub_return_nan
+ 	leaf_return
+ 
+ .Lsub_opposite_signs:
+@@ -692,10 +709,7 @@
+ 	/* If y is zero, return NaN.  */
+ 	bnez	yl, 1f
+ 	slli	a8, yh, 1
+-	bnez	a8, 1f
+-	movi	a4, 0x80000	/* make it a quiet NaN */
+-	or	xh, xh, a4
+-	j	.Lmul_done
++	beqz	a8, .Lmul_return_nan
+ 1:
+ 	/* If y is NaN, return y.  */
+ 	bnall	yh, a6, .Lmul_returnx
+@@ -708,6 +722,9 @@
+ 	mov	xl, yl
+ 
+ .Lmul_returnx:
++	slli	a8, xh, 12
++	or	a8, a8, xl
++	bnez	a8, .Lmul_return_nan
+ 	/* Set the sign bit and return.  */
+ 	extui	a7, a7, 31, 1
+ 	slli	xh, xh, 1
+@@ -720,8 +737,11 @@
+ 	bnez	xl, .Lmul_returny
+ 	slli	a8, xh, 1
+ 	bnez	a8, .Lmul_returny
+-	movi	a7, 0x80000	/* make it a quiet NaN */
+-	or	xh, yh, a7
++	mov	xh, yh
++
++.Lmul_return_nan:
++	movi	a4, 0x80000	/* make it a quiet NaN */
++	or	xh, xh, a4
+ 	j	.Lmul_done
+ 
+ 	.align	4
+@@ -1320,10 +1340,11 @@
+ 	slli	a7, a7, 31
+ 	xor	xh, xh, a7
+ 	/* If y is NaN or Inf, return NaN.  */
+-	bnall	yh, a6, 1f
+-	movi	a4, 0x80000	/* make it a quiet NaN */
+-	or	xh, xh, a4
+-1:	leaf_return
++	ball	yh, a6, .Ldiv_return_nan
++	slli	a8, xh, 12
++	or	a8, a8, xl
++	bnez	a8, .Ldiv_return_nan
++	leaf_return
+ 
+ .Ldiv_ynan_or_inf:
+ 	/* If y is Infinity, return zero.  */
+@@ -1333,6 +1354,10 @@
+ 	/* y is NaN; return it.  */
+ 	mov	xh, yh
+ 	mov	xl, yl
++
++.Ldiv_return_nan:
++	movi	a4, 0x80000	/* make it a quiet NaN */
++	or	xh, xh, a4
+ 	leaf_return
+ 
+ .Ldiv_highequal1:
+Index: libgcc/config/xtensa/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/xtensa/linux-unwind.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/xtensa/linux-unwind.h	(.../branches/gcc-6-branch)
+@@ -67,7 +67,7 @@
+ 
+   struct rt_sigframe {
+     siginfo_t info;
+-    struct ucontext uc;
++    ucontext_t uc;
+   } *rt_;
+ 
+   /* movi a2, __NR_rt_sigreturn; syscall */
+Index: libgcc/config/xtensa/ieee754-sf.S
+===================================================================
+--- a/src/libgcc/config/xtensa/ieee754-sf.S	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/xtensa/ieee754-sf.S	(.../branches/gcc-6-branch)
+@@ -55,6 +55,7 @@
+ 
+ #ifdef L_addsubsf3
+ 
++	.literal_position
+ 	/* Addition */
+ __addsf3_aux:
+ 
+@@ -64,17 +65,25 @@
+ 
+ .Ladd_xnan_or_inf:
+ 	/* If y is neither Infinity nor NaN, return x.  */
+-	bnall	a3, a6, 1f
++	bnall	a3, a6, .Ladd_return_nan_or_inf
+ 	/* If x is a NaN, return it.  Otherwise, return y.  */
+ 	slli	a7, a2, 9
+-	beqz	a7, .Ladd_ynan_or_inf
+-1:	leaf_return
++	bnez	a7, .Ladd_return_nan
+ 
+ .Ladd_ynan_or_inf:
+ 	/* Return y.  */
+ 	mov	a2, a3
++
++.Ladd_return_nan_or_inf:
++	slli	a7, a2, 9
++	bnez	a7, .Ladd_return_nan
+ 	leaf_return
+ 
++.Ladd_return_nan:
++	movi	a6, 0x400000	/* make it a quiet NaN */
++	or	a2, a2, a6
++	leaf_return
++
+ .Ladd_opposite_signs:
+ 	/* Operand signs differ.  Do a subtraction.  */
+ 	slli	a7, a6, 8
+@@ -265,16 +274,22 @@
+ 
+ .Lsub_xnan_or_inf:
+ 	/* If y is neither Infinity nor NaN, return x.  */
+-	bnall	a3, a6, 1f
++	bnall	a3, a6, .Lsub_return_nan_or_inf
+ 	/* Both x and y are either NaN or Inf, so the result is NaN.  */
++
++.Lsub_return_nan:
+ 	movi	a4, 0x400000	/* make it a quiet NaN */
+ 	or	a2, a2, a4
+-1:	leaf_return
++	leaf_return
+ 
+ .Lsub_ynan_or_inf:
+ 	/* Negate y and return it.  */
+ 	slli	a7, a6, 8
+ 	xor	a2, a3, a7
++
++.Lsub_return_nan_or_inf:
++	slli	a7, a2, 9
++	bnez	a7, .Lsub_return_nan
+ 	leaf_return
+ 
+ .Lsub_opposite_signs:
+@@ -537,11 +552,7 @@
+ .Lmul_xnan_or_inf:
+ 	/* If y is zero, return NaN.  */
+ 	slli	a8, a3, 1
+-	bnez	a8, 1f
+-	movi	a4, 0x400000	/* make it a quiet NaN */
+-	or	a2, a2, a4
+-	j	.Lmul_done
+-1:
++	beqz	a8, .Lmul_return_nan
+ 	/* If y is NaN, return y.  */
+ 	bnall	a3, a6, .Lmul_returnx
+ 	slli	a8, a3, 9
+@@ -551,6 +562,8 @@
+ 	mov	a2, a3
+ 
+ .Lmul_returnx:
++	slli	a8, a2, 9
++	bnez	a8, .Lmul_return_nan
+ 	/* Set the sign bit and return.  */
+ 	extui	a7, a7, 31, 1
+ 	slli	a2, a2, 1
+@@ -562,8 +575,11 @@
+ 	/* If x is zero, return NaN.  */
+ 	slli	a8, a2, 1
+ 	bnez	a8, .Lmul_returny
+-	movi	a7, 0x400000	/* make it a quiet NaN */
+-	or	a2, a3, a7
++	mov	a2, a3
++
++.Lmul_return_nan:
++	movi	a4, 0x400000	/* make it a quiet NaN */
++	or	a2, a2, a4
+ 	j	.Lmul_done
+ 
+ 	.align	4
+@@ -951,10 +967,10 @@
+ 	slli	a7, a7, 31
+ 	xor	a2, a2, a7
+ 	/* If y is NaN or Inf, return NaN.  */
+-	bnall	a3, a6, 1f
+-	movi	a4, 0x400000	/* make it a quiet NaN */
+-	or	a2, a2, a4
+-1:	leaf_return
++	ball	a3, a6, .Ldiv_return_nan
++	slli	a7, a2, 9
++	bnez	a7, .Ldiv_return_nan
++	leaf_return
+ 
+ .Ldiv_ynan_or_inf:
+ 	/* If y is Infinity, return zero.  */
+@@ -962,6 +978,10 @@
+ 	beqz	a8, .Ldiv_return_zero
+ 	/* y is NaN; return it.  */
+ 	mov	a2, a3
++
++.Ldiv_return_nan:
++	movi	a4, 0x400000	/* make it a quiet NaN */
++	or	a2, a2, a4
+ 	leaf_return
+ 
+ 	.align	4
+Index: libgcc/config/sol2/crtpg.c
+===================================================================
+--- a/src/libgcc/config/sol2/crtpg.c	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/sol2/crtpg.c	(.../branches/gcc-6-branch)
+@@ -31,11 +31,10 @@
+ 
+ int __start_crt_compiler (int, char **);
+ 
+-/* Since Solaris 11.x and Solaris 12, the system-provided CRTs provide a
+-   hook to invoke initialization code early during process startup.
+-   __start_crt_compiler is documented in crt1.o(5).  We use it to perform
+-   initialization for profiling as a substitute for the earlier separate
+-   gcrt1.o.  */
++/* Since Solaris 11.4, the system-provided CRTs provide a hook to invoke
++   initialization code early during process startup.  __start_crt_compiler
++   is documented in crt1.o(5).  We use it to perform initialization for
++   profiling as a substitute for the earlier separate gcrt1.o.  */
+ 
+ int
+ __start_crt_compiler (int argc __attribute__ ((unused)),
+Index: libgcc/config/nios2/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/nios2/linux-unwind.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/nios2/linux-unwind.h	(.../branches/gcc-6-branch)
+@@ -38,7 +38,7 @@
+ 
+ struct nios2_ucontext {
+   unsigned long uc_flags;
+-  struct ucontext *uc_link;
++  ucontext_t *uc_link;
+   stack_t uc_stack;
+   struct nios2_mcontext uc_mcontext;
+   sigset_t uc_sigmask;	/* mask last for extensibility */
+Index: libgcc/config/bfin/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/bfin/linux-unwind.h	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/config/bfin/linux-unwind.h	(.../branches/gcc-6-branch)
+@@ -52,7 +52,7 @@
+ 	void *puc;
+ 	char retcode[8];
+ 	siginfo_t info;
+-	struct ucontext uc;
++	ucontext_t uc;
+       } *rt_ = context->cfa;
+ 
+       /* The void * cast is necessary to avoid an aliasing warning.
+Index: libgcc/configure
+===================================================================
+--- a/src/libgcc/configure	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/configure	(.../branches/gcc-6-branch)
+@@ -4667,7 +4667,7 @@
+ 
+ case ${host} in
+ *-*-solaris2*)
+-  # Check for system-provided CRTs on Solaris 11.x and Solaris 12.
++  # Check for system-provided CRTs on Solaris 11.4.
+   { $as_echo "$as_me:${as_lineno-$LINENO}: checking system-provided CRTs on Solaris" >&5
+ $as_echo_n "checking system-provided CRTs on Solaris... " >&6; }
+ if test "${libgcc_cv_solaris_crts+set}" = set; then :
+Index: libgcc/libgcc2.c
+===================================================================
+--- a/src/libgcc/libgcc2.c	(.../tags/gcc_6_4_0_release)
++++ b/src/libgcc/libgcc2.c	(.../branches/gcc-6-branch)
+@@ -375,7 +375,8 @@
+ 		}
+ 	      else
+ 		{
+-		  if (uu.s.high == (Wtype) -1 && vv.s.high == (Wtype) - 1)
++		  if ((uu.s.high & vv.s.high) == (Wtype) -1
++		      && (uu.s.low | vv.s.low) != 0)
+ 		    {
+ 		      DWunion ww = {.ll = (UDWtype) (UWtype) uu.s.low
+ 				    * (UDWtype) (UWtype) vv.s.low};
+Index: gcc/ipa-visibility.c
+===================================================================
+--- a/src/gcc/ipa-visibility.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ipa-visibility.c	(.../branches/gcc-6-branch)
+@@ -97,7 +97,8 @@
+ 	   && !DECL_EXTERNAL (node->decl)
+ 	   && !node->externally_visible
+ 	   && !node->used_from_other_partition
+-	   && !node->in_other_partition);
++	   && !node->in_other_partition
++	   && node->get_availability () >= AVAIL_AVAILABLE);
+ }
+ 
+ /* Return true when function can be marked local.  */
+Index: gcc/tree-ssa-tail-merge.c
+===================================================================
+--- a/src/gcc/tree-ssa-tail-merge.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/tree-ssa-tail-merge.c	(.../branches/gcc-6-branch)
+@@ -808,6 +808,9 @@
+ same_succ_flush_bb (basic_block bb)
+ {
+   same_succ *same = BB_SAME_SUCC (bb);
++  if (! same)
++    return;
++
+   BB_SAME_SUCC (bb) = NULL;
+   if (bitmap_single_bit_set_p (same->bbs))
+     same_succ_htab->remove_elt_with_hash (same, same->hashval);
+Index: gcc/tree-chkp.c
+===================================================================
+--- a/src/gcc/tree-chkp.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/tree-chkp.c	(.../branches/gcc-6-branch)
+@@ -3144,6 +3144,9 @@
+       && !flag_chkp_incomplete_type)
+       return chkp_get_zero_bounds ();
+ 
++  if (VOID_TYPE_P (TREE_TYPE (decl)))
++    return chkp_get_zero_bounds ();
++
+   if (flag_chkp_use_static_bounds
+       && TREE_CODE (decl) == VAR_DECL
+       && (TREE_STATIC (decl)
+Index: gcc/ipa-icf-gimple.c
+===================================================================
+--- a/src/gcc/ipa-icf-gimple.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ipa-icf-gimple.c	(.../branches/gcc-6-branch)
+@@ -361,10 +361,14 @@
+       }
+     case LABEL_DECL:
+       {
++	if (t1 == t2)
++	  return true;
++
+ 	int *bb1 = m_label_bb_map.get (t1);
+ 	int *bb2 = m_label_bb_map.get (t2);
+ 
+-	return return_with_debug (*bb1 == *bb2);
++	/* Labels can point to another function (non-local GOTOs).  */
++	return return_with_debug (bb1 != NULL && bb2 != NULL && *bb1 == *bb2);
+       }
+     case PARM_DECL:
+     case RESULT_DECL:
+@@ -539,11 +543,8 @@
+     }
+ }
+ 
+-/* Compares two tree list operands T1 and T2 and returns true if these
+-   two trees are semantically equivalent.  */
+-
+ bool
+-func_checker::compare_tree_list_operand (tree t1, tree t2)
++func_checker::compare_asm_inputs_outputs (tree t1, tree t2)
+ {
+   gcc_assert (TREE_CODE (t1) == TREE_LIST);
+   gcc_assert (TREE_CODE (t2) == TREE_LIST);
+@@ -556,6 +557,16 @@
+       if (!compare_operand (TREE_VALUE (t1), TREE_VALUE (t2)))
+ 	return return_false ();
+ 
++      tree p1 = TREE_PURPOSE (t1);
++      tree p2 = TREE_PURPOSE (t2);
++
++      gcc_assert (TREE_CODE (p1) == TREE_LIST);
++      gcc_assert (TREE_CODE (p2) == TREE_LIST);
++
++      if (strcmp (TREE_STRING_POINTER (TREE_VALUE (p1)),
++		  TREE_STRING_POINTER (TREE_VALUE (p2))) != 0)
++	return return_false ();
++
+       t2 = TREE_CHAIN (t2);
+     }
+ 
+@@ -1004,7 +1015,7 @@
+       tree input1 = gimple_asm_input_op (g1, i);
+       tree input2 = gimple_asm_input_op (g2, i);
+ 
+-      if (!compare_tree_list_operand (input1, input2))
++      if (!compare_asm_inputs_outputs (input1, input2))
+ 	return return_false_with_msg ("ASM input is different");
+     }
+ 
+@@ -1013,7 +1024,7 @@
+       tree output1 = gimple_asm_output_op (g1, i);
+       tree output2 = gimple_asm_output_op (g2, i);
+ 
+-      if (!compare_tree_list_operand (output1, output2))
++      if (!compare_asm_inputs_outputs (output1, output2))
+ 	return return_false_with_msg ("ASM output is different");
+     }
+ 
+Index: gcc/ipa-icf-gimple.h
+===================================================================
+--- a/src/gcc/ipa-icf-gimple.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ipa-icf-gimple.h	(.../branches/gcc-6-branch)
+@@ -215,9 +215,9 @@
+      is returned.  */
+   bool compare_operand (tree t1, tree t2);
+ 
+-  /* Compares two tree list operands T1 and T2 and returns true if these
+-     two trees are semantically equivalent.  */
+-  bool compare_tree_list_operand (tree t1, tree t2);
++  /* Compares GIMPLE ASM inputs (or outputs) where we iterate tree chain
++     and compare both TREE_PURPOSEs and TREE_VALUEs.  */
++  bool compare_asm_inputs_outputs (tree t1, tree t2);
+ 
+   /* Verifies that trees T1 and T2, representing function declarations
+      are equivalent from perspective of ICF.  */
+Index: gcc/opts-common.c
+===================================================================
+--- a/src/gcc/opts-common.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/opts-common.c	(.../branches/gcc-6-branch)
+@@ -986,7 +986,8 @@
+       {
+ 	if (!handlers->handlers[i].handler (opts, opts_set, decoded,
+ 					    lang_mask, kind, loc,
+-					    handlers, dc))
++					    handlers, dc,
++					    handlers->target_option_override_hook))
+ 	  return false;
+       }
+   
+Index: gcc/c-family/c-cppbuiltin.c
+===================================================================
+--- a/src/gcc/c-family/c-cppbuiltin.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/c-family/c-cppbuiltin.c	(.../branches/gcc-6-branch)
+@@ -891,6 +891,8 @@
+ 	cpp_define (pfile, "__cpp_transactional_memory=210500");
+       if (flag_sized_deallocation)
+ 	cpp_define (pfile, "__cpp_sized_deallocation=201309");
++      if (flag_threadsafe_statics)
++	cpp_define (pfile, "__cpp_threadsafe_static_init=200806");
+     }
+   /* Note that we define this for C as well, so that we know if
+      __attribute__((cleanup)) will interface with EH.  */
+Index: gcc/c-family/ChangeLog
+===================================================================
+--- a/src/gcc/c-family/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/c-family/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,46 @@
++2017-09-15  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-09-12  Jakub Jelinek  <jakub@redhat.com>
++
++	PR target/82112
++	* c-common.c (sync_resolve_size): Instead of c_dialect_cxx ()
++	assertion check that in the condition.
++	(get_atomic_generic_size): Likewise.  Before testing if parameter
++	has pointer type, if it has array type, call for C++
++	default_conversion to perform array-to-pointer conversion.
++
++	2017-07-27  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c/45784
++	* c-omp.c (c_finish_omp_for): If the condition is wrapped in
++	rhs of COMPOUND_EXPR(s), skip them and readd their lhs into
++	new COMPOUND_EXPRs around the rhs of the comparison.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-08-29  Martin Liska  <mliska@suse.cz>
++
++	PR other/39851
++	* c-common.c (parse_optimize_options): Add argument to function
++	call.
++	* c-pragma.c (handle_pragma_diagnostic): Likewise.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-06-28  Martin Liska  <mliska@suse.cz>
++
++	PR ipa/81128
++	* c-attribs.c (handle_alias_ifunc_attribute): Append ifunc alias
++	to a function declaration.
++
++2017-09-10  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR c++/81852
++	* c-cppbuiltin.c (c_cpp_builtins): Define __cpp_threadsafe_static_init.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: gcc/c-family/c-common.c
+===================================================================
+--- a/src/gcc/c-family/c-common.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/c-family/c-common.c	(.../branches/gcc-6-branch)
+@@ -7989,9 +7989,14 @@
+ 	TREE_STATIC (decl) = 1;
+ 
+       if (!is_alias)
+-	/* ifuncs are also aliases, so set that attribute too. */
+-	DECL_ATTRIBUTES (decl)
+-	  = tree_cons (get_identifier ("alias"), args, DECL_ATTRIBUTES (decl));
++	{
++	  /* ifuncs are also aliases, so set that attribute too.  */
++	  DECL_ATTRIBUTES (decl)
++	    = tree_cons (get_identifier ("alias"), args,
++			 DECL_ATTRIBUTES (decl));
++	  DECL_ATTRIBUTES (decl) = tree_cons (get_identifier ("ifunc"),
++					      NULL, DECL_ATTRIBUTES (decl));
++	}
+     }
+   else
+     {
+@@ -9583,7 +9588,7 @@
+ 						&decoded_options_count);
+   decode_options (&global_options, &global_options_set,
+ 		  decoded_options, decoded_options_count,
+-		  input_location, global_dc);
++		  input_location, global_dc, NULL);
+ 
+   targetm.override_options_after_change();
+ 
+@@ -10725,10 +10730,9 @@
+     }
+ 
+   argtype = type = TREE_TYPE ((*params)[0]);
+-  if (TREE_CODE (type) == ARRAY_TYPE)
++  if (TREE_CODE (type) == ARRAY_TYPE && c_dialect_cxx ())
+     {
+       /* Force array-to-pointer decay for C++.  */
+-      gcc_assert (c_dialect_cxx());
+       (*params)[0] = default_conversion ((*params)[0]);
+       type = TREE_TYPE ((*params)[0]);
+     }
+@@ -10890,10 +10894,9 @@
+ 
+   /* Get type of first parameter, and determine its size.  */
+   type_0 = TREE_TYPE ((*params)[0]);
+-  if (TREE_CODE (type_0) == ARRAY_TYPE)
++  if (TREE_CODE (type_0) == ARRAY_TYPE && c_dialect_cxx ())
+     {
+       /* Force array-to-pointer decay for C++.  */
+-      gcc_assert (c_dialect_cxx());
+       (*params)[0] = default_conversion ((*params)[0]);
+       type_0 = TREE_TYPE ((*params)[0]);
+     }
+@@ -10932,6 +10935,12 @@
+       /* __atomic_compare_exchange has a bool in the 4th position, skip it.  */
+       if (n_param == 6 && x == 3)
+         continue;
++      if (TREE_CODE (type) == ARRAY_TYPE && c_dialect_cxx ())
++	{
++	  /* Force array-to-pointer decay for C++.  */
++	  (*params)[x] = default_conversion ((*params)[x]);
++	  type = TREE_TYPE ((*params)[x]);
++	}
+       if (!POINTER_TYPE_P (type))
+ 	{
+ 	  error_at (loc, "argument %d of %qE must be a pointer type", x + 1,
+Index: gcc/c-family/c-omp.c
+===================================================================
+--- a/src/gcc/c-family/c-omp.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/c-family/c-omp.c	(.../branches/gcc-6-branch)
+@@ -518,6 +518,12 @@
+ 	{
+ 	  bool cond_ok = false;
+ 
++	  /* E.g. C sizeof (vla) could add COMPOUND_EXPRs with
++	     evaluation of the vla VAR_DECL.  We need to readd
++	     them to the non-decl operand.  See PR45784.  */
++	  while (TREE_CODE (cond) == COMPOUND_EXPR)
++	    cond = TREE_OPERAND (cond, 1);
++
+ 	  if (EXPR_HAS_LOCATION (cond))
+ 	    elocus = EXPR_LOCATION (cond);
+ 
+@@ -592,6 +598,21 @@
+ 		  else if (code != CILK_SIMD && code != CILK_FOR)
+ 		    cond_ok = false;
+ 		}
++
++	      if (cond_ok && TREE_VEC_ELT (condv, i) != cond)
++		{
++		  tree ce = NULL_TREE, *pce = &ce;
++		  tree type = TREE_TYPE (TREE_OPERAND (cond, 1));
++		  for (tree c = TREE_VEC_ELT (condv, i); c != cond;
++		       c = TREE_OPERAND (c, 1))
++		    {
++		      *pce = build2 (COMPOUND_EXPR, type, TREE_OPERAND (c, 0),
++				     TREE_OPERAND (cond, 1));
++		      pce = &TREE_OPERAND (*pce, 1);
++		    }
++		  TREE_OPERAND (cond, 1) = ce;
++		  TREE_VEC_ELT (condv, i) = cond;
++		}
+ 	    }
+ 
+ 	  if (!cond_ok)
+Index: gcc/c-family/c-pragma.c
+===================================================================
+--- a/src/gcc/c-family/c-pragma.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/c-family/c-pragma.c	(.../branches/gcc-6-branch)
+@@ -813,7 +813,7 @@
+     }
+ 
+   struct cl_option_handlers handlers;
+-  set_default_handlers (&handlers);
++  set_default_handlers (&handlers, NULL);
+   const char *arg = NULL;
+   if (cl_options[option_index].flags & CL_JOINED)
+     arg = option_string + 1 + cl_options[option_index].opt_len;
+Index: gcc/c/ChangeLog
+===================================================================
+--- a/src/gcc/c/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/c/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,12 @@
++2017-12-10  Tom de Vries  <tom@codesourcery.com>
++
++	backport from trunk:
++	PR c/81875
++	2017-09-16  Tom de Vries  <tom@codesourcery.com>
++
++	* c-parser.c (c_parser_omp_for_loop): Fold only operands of cond, not
++	cond itself.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: gcc/c/c-parser.c
+===================================================================
+--- a/src/gcc/c/c-parser.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/c/c-parser.c	(.../branches/gcc-6-branch)
+@@ -14767,7 +14767,14 @@
+ 
+ 	  cond = cond_expr.value;
+ 	  cond = c_objc_common_truthvalue_conversion (cond_loc, cond);
+-	  cond = c_fully_fold (cond, false, NULL);
++	  if (COMPARISON_CLASS_P (cond))
++	    {
++	      tree op0 = TREE_OPERAND (cond, 0), op1 = TREE_OPERAND (cond, 1);
++	      op0 = c_fully_fold (op0, false, NULL);
++	      op1 = c_fully_fold (op1, false, NULL);
++	      TREE_OPERAND (cond, 0) = op0;
++	      TREE_OPERAND (cond, 1) = op1;
++	    }
+ 	  switch (cond_expr.original_code)
+ 	    {
+ 	    case GT_EXPR:
+Index: gcc/cgraph.c
+===================================================================
+--- a/src/gcc/cgraph.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/cgraph.c	(.../branches/gcc-6-branch)
+@@ -1259,7 +1259,6 @@
+   cgraph_edge *e = this;
+ 
+   tree decl = gimple_call_fndecl (e->call_stmt);
+-  tree lhs = gimple_call_lhs (e->call_stmt);
+   gcall *new_stmt;
+   gimple_stmt_iterator gsi;
+   bool skip_bounds = false;
+@@ -1529,6 +1528,7 @@
+     gimple_call_set_fntype (new_stmt, TREE_TYPE (e->callee->decl));
+ 
+   /* If the call becomes noreturn, remove the LHS if possible.  */
++  tree lhs = gimple_call_lhs (new_stmt);
+   if (lhs
+       && (gimple_call_flags (new_stmt) & ECF_NORETURN)
+       && (VOID_TYPE_P (TREE_TYPE (gimple_call_fntype (new_stmt)))
+Index: gcc/cgraph.h
+===================================================================
+--- a/src/gcc/cgraph.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/cgraph.h	(.../branches/gcc-6-branch)
+@@ -315,6 +315,9 @@
+      or abstract function kept for debug info purposes only.  */
+   bool real_symbol_p (void);
+ 
++  /* Return true when the symbol needs to be output to the LTO symbol table.  */
++  bool output_to_lto_symbol_table_p (void);
++
+   /* Determine if symbol declaration is needed.  That is, visible to something
+      either outside this translation unit, something magic in the system
+      configury. This function is used just during symbol creation.  */
+Index: gcc/DATESTAMP
+===================================================================
+--- a/src/gcc/DATESTAMP	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/DATESTAMP	(.../branches/gcc-6-branch)
+@@ -1 +1 @@
+-20170704
++20180312
+Index: gcc/valtrack.c
+===================================================================
+--- a/src/gcc/valtrack.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/valtrack.c	(.../branches/gcc-6-branch)
+@@ -28,6 +28,7 @@
+ #include "valtrack.h"
+ #include "regs.h"
+ #include "emit-rtl.h"
++#include "rtl-iter.h"
+ 
+ /* gen_lowpart_no_emit hook implementation for DEBUG_INSNs.  In DEBUG_INSNs,
+    all lowpart SUBREGs are valid, despite what the machine requires for
+@@ -148,6 +149,7 @@
+ {
+   rtx to;
+   bool adjusted;
++  rtx_insn *insn;
+ };
+ 
+ /* DATA points to an rtx_subst_pair.  Return the value that should be
+@@ -165,6 +167,23 @@
+       pair->adjusted = true;
+       pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
+       pair->to = make_compound_operation (pair->to, SET);
++      /* Avoid propagation from growing DEBUG_INSN expressions too much.  */
++      int cnt = 0;
++      subrtx_iterator::array_type array;
++      FOR_EACH_SUBRTX (iter, array, pair->to, ALL)
++	if (REG_P (*iter) && ++cnt > 1)
++	  {
++	    rtx dval = make_debug_expr_from_rtl (old_rtx);
++	    /* Emit a debug bind insn.  */
++	    rtx bind
++	      = gen_rtx_VAR_LOCATION (GET_MODE (old_rtx),
++				      DEBUG_EXPR_TREE_DECL (dval), pair->to,
++				      VAR_INIT_STATUS_INITIALIZED);
++	    rtx_insn *bind_insn = emit_debug_insn_before (bind, pair->insn);
++	    df_insn_rescan (bind_insn);
++	    pair->to = dval;
++	    break;
++	  }
+       return pair->to;
+     }
+   return copy_rtx (pair->to);
+@@ -185,6 +204,7 @@
+   struct rtx_subst_pair p;
+   p.to = src;
+   p.adjusted = false;
++  p.insn = NEXT_INSN (insn);
+ 
+   next = NEXT_INSN (insn);
+   last = NEXT_INSN (last);
+Index: gcc/tree.c
+===================================================================
+--- a/src/gcc/tree.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/tree.c	(.../branches/gcc-6-branch)
+@@ -5445,9 +5445,10 @@
+ 	 At this point, it is not needed anymore.  */
+       DECL_SAVED_TREE (decl) = NULL_TREE;
+ 
+-      /* Clear the abstract origin if it refers to a method.  Otherwise
+-         dwarf2out.c will ICE as we clear TYPE_METHODS and thus the
+-	 origin will not be output correctly.  */
++      /* Clear the abstract origin if it refers to a method.
++         Otherwise dwarf2out.c will ICE as we splice functions out of
++         TYPE_FIELDS and thus the origin will not be output
++         correctly.  */
+       if (DECL_ABSTRACT_ORIGIN (decl)
+ 	  && DECL_CONTEXT (DECL_ABSTRACT_ORIGIN (decl))
+ 	  && RECORD_OR_UNION_TYPE_P
+Index: gcc/ipa-cp.c
+===================================================================
+--- a/src/gcc/ipa-cp.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ipa-cp.c	(.../branches/gcc-6-branch)
+@@ -544,6 +544,24 @@
+       reason = "calls comdat-local function";
+     }
+ 
++  /* Functions calling BUILT_IN_VA_ARG_PACK and BUILT_IN_VA_ARG_PACK_LEN
++     works only when inlined.  Cloning them may still lead to better code
++     becuase ipa-cp will not give up on cloning further.  If the function is
++     external this however leads to wrong code becuase we may end up producing
++     offline copy of the function.  */
++  if (DECL_EXTERNAL (node->decl))
++    for (cgraph_edge *edge = node->callees; !reason && edge;
++	 edge = edge->next_callee)
++      if (DECL_BUILT_IN (edge->callee->decl)
++	  && DECL_BUILT_IN_CLASS (edge->callee->decl) == BUILT_IN_NORMAL)
++        {
++	  if (DECL_FUNCTION_CODE (edge->callee->decl) == BUILT_IN_VA_ARG_PACK)
++	    reason = "external function which calls va_arg_pack";
++	  if (DECL_FUNCTION_CODE (edge->callee->decl)
++	      == BUILT_IN_VA_ARG_PACK_LEN)
++	    reason = "external function which calls va_arg_pack_len";
++        }
++
+   if (reason && dump_file && !node->alias && !node->thunk.thunk_p)
+     fprintf (dump_file, "Function %s/%i is not versionable, reason: %s.\n",
+ 	     node->name (), node->order, reason);
+Index: gcc/rtlanal.c
+===================================================================
+--- a/src/gcc/rtlanal.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/rtlanal.c	(.../branches/gcc-6-branch)
+@@ -2064,7 +2064,7 @@
+   if (GET_CODE (pattern) == COND_EXEC)
+     return 0;
+ 
+-  if (GET_CODE (pattern) == SET)
++  if (GET_CODE (pattern) == SET || GET_CODE (pattern) == CLOBBER)
+     return covers_regno_p (SET_DEST (pattern), test_regno);
+   else if (GET_CODE (pattern) == PARALLEL)
+     {
+Index: gcc/configure
+===================================================================
+--- a/src/gcc/configure	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/configure	(.../branches/gcc-6-branch)
+@@ -7352,10 +7352,10 @@
+ if test "${enable_coverage+set}" = set; then :
+   enableval=$enable_coverage; case "${enableval}" in
+   yes|noopt)
+-    coverage_flags="-fprofile-arcs -ftest-coverage -frandom-seed=\$@ -O0"
++    coverage_flags="-fprofile-arcs -ftest-coverage -frandom-seed=\$@ -O0 -fkeep-static-functions"
+     ;;
+   opt)
+-    coverage_flags="-fprofile-arcs -ftest-coverage -frandom-seed=\$@ -O2"
++    coverage_flags="-fprofile-arcs -ftest-coverage -frandom-seed=\$@ -O2 -fkeep-static-functions"
+     ;;
+   no)
+     # a.k.a. --disable-coverage
+@@ -23567,6 +23567,14 @@
+ $as_echo "$gcc_cv_as_shf_merge" >&6; }
+ 
+ fi
++case "$target" in
++  i?86-*-solaris2.10* | x86_64-*-solaris2.10*)
++    # SHF_MERGE support in Solaris 10/x86 ld is broken.
++    if test x"$gnu_ld" = xno; then
++      gcc_cv_as_shf_merge=no
++    fi
++    ;;
++esac
+ 
+ cat >>confdefs.h <<_ACEOF
+ #define HAVE_GAS_SHF_MERGE `if test $gcc_cv_as_shf_merge = yes; then echo 1; else echo 0; fi`
+@@ -25366,6 +25374,37 @@
+ 	;;
+     esac
+ 
++    { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for -xbrace_comment" >&5
++$as_echo_n "checking assembler for -xbrace_comment... " >&6; }
++if test "${gcc_cv_as_ix86_xbrace_comment+set}" = set; then :
++  $as_echo_n "(cached) " >&6
++else
++  gcc_cv_as_ix86_xbrace_comment=no
++  if test x$gcc_cv_as != x; then
++    $as_echo '.text' > conftest.s
++    if { ac_try='$gcc_cv_as $gcc_cv_as_flags -xbrace_comment=no -o conftest.o conftest.s >&5'
++  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
++  (eval $ac_try) 2>&5
++  ac_status=$?
++  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++  test $ac_status = 0; }; }
++    then
++	gcc_cv_as_ix86_xbrace_comment=yes
++    else
++      echo "configure: failed program was" >&5
++      cat conftest.s >&5
++    fi
++    rm -f conftest.o conftest.s
++  fi
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_ix86_xbrace_comment" >&5
++$as_echo "$gcc_cv_as_ix86_xbrace_comment" >&6; }
++if test $gcc_cv_as_ix86_xbrace_comment = yes; then
++
++$as_echo "#define HAVE_AS_XBRACE_COMMENT_OPTION 1" >>confdefs.h
++
++fi
++
+     # Test if the assembler supports the section flag 'e' for specifying
+     # an excluded section.
+     { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .section with e" >&5
+@@ -27857,7 +27896,7 @@
+   else
+     case "$target" in
+       *-*-solaris2.1[1-9]*)
+-	# Solaris 11.x and Solaris 12 added PIE support.
++	# Solaris 11.3 added PIE support.
+ 	if $gcc_cv_ld -z help 2>&1 | grep -- type.*pie > /dev/null; then
+ 	  gcc_cv_ld_pie=yes
+ 	fi
+Index: gcc/internal-fn.c
+===================================================================
+--- a/src/gcc/internal-fn.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/internal-fn.c	(.../branches/gcc-6-branch)
+@@ -1565,8 +1565,8 @@
+ 		}
+ 
+ 	      /* At this point hipart{0,1} are both in [-1, 0].  If they are
+-		 the same, overflow happened if res is negative, if they are
+-		 different, overflow happened if res is positive.  */
++		 the same, overflow happened if res is non-positive, if they
++		 are different, overflow happened if res is positive.  */
+ 	      if (op0_sign != 1 && op1_sign != 1 && op0_sign != op1_sign)
+ 		emit_jump (hipart_different);
+ 	      else if (op0_sign == 1 || op1_sign == 1)
+@@ -1574,7 +1574,7 @@
+ 					 NULL_RTX, NULL, hipart_different,
+ 					 PROB_EVEN);
+ 
+-	      do_compare_rtx_and_jump (res, const0_rtx, LT, false, mode,
++	      do_compare_rtx_and_jump (res, const0_rtx, LE, false, mode,
+ 				       NULL_RTX, NULL, do_error,
+ 				       PROB_VERY_UNLIKELY);
+ 	      emit_jump (done_label);
+Index: gcc/final.c
+===================================================================
+--- a/src/gcc/final.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/final.c	(.../branches/gcc-6-branch)
+@@ -901,7 +901,7 @@
+   char *varying_length;
+   rtx body;
+   int uid;
+-  rtx align_tab[MAX_CODE_ALIGN];
++  rtx align_tab[MAX_CODE_ALIGN + 1];
+ 
+   /* Compute maximum UID and allocate label_align / uid_shuid.  */
+   max_uid = get_max_uid ();
+@@ -1010,7 +1010,7 @@
+      alignment of n.  */
+   uid_align = XCNEWVEC (rtx, max_uid);
+ 
+-  for (i = MAX_CODE_ALIGN; --i >= 0;)
++  for (i = MAX_CODE_ALIGN + 1; --i >= 0;)
+     align_tab[i] = NULL_RTX;
+   seq = get_last_insn ();
+   for (; seq; seq = PREV_INSN (seq))
+Index: gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/gcc.c	(.../branches/gcc-6-branch)
+@@ -869,8 +869,7 @@
+ #endif
+ 
+ #ifdef ENABLE_DEFAULT_PIE
+-#define NO_PIE_SPEC		"no-pie|static"
+-#define PIE_SPEC		NO_PIE_SPEC "|r|shared:;"
++#define PIE_SPEC		"!no-pie"
+ #define NO_FPIE1_SPEC		"fno-pie"
+ #define FPIE1_SPEC		NO_FPIE1_SPEC ":;"
+ #define NO_FPIE2_SPEC		"fno-PIE"
+@@ -891,7 +890,6 @@
+ #define FPIE_OR_FPIC_SPEC	NO_FPIE_AND_FPIC_SPEC ":;"
+ #else
+ #define PIE_SPEC		"pie"
+-#define NO_PIE_SPEC		PIE_SPEC "|r|shared:;"
+ #define FPIE1_SPEC		"fpie"
+ #define NO_FPIE1_SPEC		FPIE1_SPEC ":;"
+ #define FPIE2_SPEC		"fPIE"
+@@ -920,7 +918,7 @@
+ #else
+ #define LD_PIE_SPEC ""
+ #endif
+-#define LINK_PIE_SPEC "%{no-pie:} " "%{" PIE_SPEC ":" LD_PIE_SPEC "} "
++#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
+ #endif
+ 
+ #ifndef LINK_BUILDID_SPEC
+@@ -999,8 +997,10 @@
+ #endif
+ 
+ /* -u* was put back because both BSD and SysV seem to support it.  */
+-/* %{static:} simply prevents an error message if the target machine
+-   doesn't handle -static.  */
++/* %{static|no-pie:} simply prevents an error message:
++   1. If the target machine doesn't handle -static.
++   2. If PIE isn't enabled by default.
++ */
+ /* We want %{T*} after %{L*} and %D so that it can be used to specify linker
+    scripts which exist in user specified directories, or in standard
+    directories.  */
+@@ -1017,7 +1017,7 @@
+    "%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \
+    "%X %{o*} %{e*} %{N} %{n} %{r}\
+     %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!nostartfiles:%S}} \
+-    %{static:} %{L*} %(mfwrap) %(link_libgcc) " \
++    %{static|no-pie:} %{L*} %(mfwrap) %(link_libgcc) " \
+     VTABLE_VERIFICATION_SPEC " " SANITIZER_EARLY_SPEC " %o " CHKP_SPEC " \
+     %{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\
+ 	%:include(libgomp.spec)%(link_gomp)}\
+@@ -3702,7 +3702,8 @@
+ 		      unsigned int lang_mask ATTRIBUTE_UNUSED, int kind,
+ 		      location_t loc,
+ 		      const struct cl_option_handlers *handlers ATTRIBUTE_UNUSED,
+-		      diagnostic_context *dc)
++		      diagnostic_context *dc,
++		      void (*) (void))
+ {
+   size_t opt_index = decoded->opt_index;
+   const char *arg = decoded->arg;
+Index: gcc/fold-const.c
+===================================================================
+--- a/src/gcc/fold-const.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fold-const.c	(.../branches/gcc-6-branch)
+@@ -3972,22 +3972,21 @@
+ 		      size_int (nbitsize - lbitsize - lbitpos));
+ 
+   if (! const_p)
+-    /* If not comparing with constant, just rework the comparison
+-       and return.  */
+-    return fold_build2_loc (loc, code, compare_type,
+-			fold_build2_loc (loc, BIT_AND_EXPR, unsigned_type,
+-				     make_bit_field_ref (loc, linner, lhs,
+-							 unsigned_type,
+-							 nbitsize, nbitpos,
+-							 1, lreversep),
+-				     mask),
+-			fold_build2_loc (loc, BIT_AND_EXPR, unsigned_type,
+-				     make_bit_field_ref (loc, rinner, rhs,
+-							 unsigned_type,
+-							 nbitsize, nbitpos,
+-							 1, rreversep),
+-				     mask));
++    {
++      if (nbitpos < 0)
++	return 0;
+ 
++      /* If not comparing with constant, just rework the comparison
++	 and return.  */
++      tree t1 = make_bit_field_ref (loc, linner, lhs, unsigned_type,
++				    nbitsize, nbitpos, 1, lreversep);
++      t1 = fold_build2_loc (loc, BIT_AND_EXPR, unsigned_type, t1, mask);
++      tree t2 = make_bit_field_ref (loc, rinner, rhs, unsigned_type,
++				    nbitsize, nbitpos, 1, rreversep);
++      t2 = fold_build2_loc (loc, BIT_AND_EXPR, unsigned_type, t2, mask);
++      return fold_build2_loc (loc, code, compare_type, t1, t2);
++    }
++
+   /* Otherwise, we are handling the constant case.  See if the constant is too
+      big for the field.  Warn and return a tree for 0 (false) if so.  We do
+      this not only for its own sake, but to avoid having to test for this
+@@ -4017,6 +4016,9 @@
+ 	}
+     }
+ 
++  if (nbitpos < 0)
++    return 0;
++
+   /* Single-bit compares should always be against zero.  */
+   if (lbitsize == 1 && ! integer_zerop (rhs))
+     {
+@@ -5891,7 +5893,10 @@
+ 	 results.  */
+       ll_mask = const_binop (BIT_IOR_EXPR, ll_mask, rl_mask);
+       lr_mask = const_binop (BIT_IOR_EXPR, lr_mask, rr_mask);
+-      if (lnbitsize == rnbitsize && xll_bitpos == xlr_bitpos)
++      if (lnbitsize == rnbitsize
++	  && xll_bitpos == xlr_bitpos
++	  && lnbitpos >= 0
++	  && rnbitpos >= 0)
+ 	{
+ 	  lhs = make_bit_field_ref (loc, ll_inner, ll_arg,
+ 				    lntype, lnbitsize, lnbitpos,
+@@ -5915,10 +5920,14 @@
+ 	 Note that we still must mask the lhs/rhs expressions.  Furthermore,
+ 	 the mask must be shifted to account for the shift done by
+ 	 make_bit_field_ref.  */
+-      if ((ll_bitsize + ll_bitpos == rl_bitpos
+-	   && lr_bitsize + lr_bitpos == rr_bitpos)
+-	  || (ll_bitpos == rl_bitpos + rl_bitsize
+-	      && lr_bitpos == rr_bitpos + rr_bitsize))
++      if (((ll_bitsize + ll_bitpos == rl_bitpos
++	    && lr_bitsize + lr_bitpos == rr_bitpos)
++	   || (ll_bitpos == rl_bitpos + rl_bitsize
++	       && lr_bitpos == rr_bitpos + rr_bitsize))
++	  && ll_bitpos >= 0
++	  && rl_bitpos >= 0
++	  && lr_bitpos >= 0
++	  && rr_bitpos >= 0)
+ 	{
+ 	  tree type;
+ 
+@@ -5987,6 +5996,9 @@
+ 	}
+     }
+ 
++  if (lnbitpos < 0)
++    return 0;
++
+   /* Construct the expression we will return.  First get the component
+      reference we will make.  Unless the mask is all ones the width of
+      that field, perform the mask operation.  Then compare with the
+@@ -7356,15 +7368,10 @@
+ static int
+ native_encode_string (const_tree expr, unsigned char *ptr, int len, int off)
+ {
+-  tree type = TREE_TYPE (expr);
+-  HOST_WIDE_INT total_bytes;
++  if (! can_native_encode_string_p (expr))
++    return 0;
+ 
+-  if (TREE_CODE (type) != ARRAY_TYPE
+-      || TREE_CODE (TREE_TYPE (type)) != INTEGER_TYPE
+-      || GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (type))) != BITS_PER_UNIT
+-      || !tree_fits_shwi_p (TYPE_SIZE_UNIT (type)))
+-    return 0;
+-  total_bytes = tree_to_shwi (TYPE_SIZE_UNIT (type));
++  HOST_WIDE_INT total_bytes = tree_to_shwi (TYPE_SIZE_UNIT (TREE_TYPE (expr)));
+   if ((off == -1 && total_bytes > len)
+       || off >= total_bytes)
+     return 0;
+@@ -7638,6 +7645,22 @@
+     }
+ }
+ 
++/* Return true iff a STRING_CST S is accepted by
++   native_encode_expr.  */
++
++bool
++can_native_encode_string_p (const_tree expr)
++{
++  tree type = TREE_TYPE (expr);
++
++  if (TREE_CODE (type) != ARRAY_TYPE
++      || TREE_CODE (TREE_TYPE (type)) != INTEGER_TYPE
++      || (GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (type))) != BITS_PER_UNIT)
++      || !tree_fits_shwi_p (TYPE_SIZE_UNIT (type)))
++    return false;
++  return true;
++}
++
+ /* Fold a VIEW_CONVERT_EXPR of a constant expression EXPR to type
+    TYPE at compile-time.  If we're unable to perform the conversion
+    return NULL_TREE.  */
+@@ -13980,8 +14003,8 @@
+ 	bool overflow;
+ 	wide_int val = wi::neg (arg0, &overflow);
+ 	t = force_fit_type (type, val, 1,
+-			    (overflow | TREE_OVERFLOW (arg0))
+-			    && !TYPE_UNSIGNED (type));
++			    (overflow && ! TYPE_UNSIGNED (type))
++			    || TREE_OVERFLOW (arg0));
+ 	break;
+       }
+ 
+Index: gcc/fold-const.h
+===================================================================
+--- a/src/gcc/fold-const.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fold-const.h	(.../branches/gcc-6-branch)
+@@ -27,6 +27,7 @@
+ /* Convert between trees and native memory representation.  */
+ extern int native_encode_expr (const_tree, unsigned char *, int, int off = -1);
+ extern tree native_interpret_expr (tree, const unsigned char *, int);
++extern bool can_native_encode_string_p (const_tree);
+ 
+ /* Fold constants as much as possible in an expression.
+    Returns the simplified expression.
+Index: gcc/omp-low.c
+===================================================================
+--- a/src/gcc/omp-low.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/omp-low.c	(.../branches/gcc-6-branch)
+@@ -1559,6 +1559,8 @@
+ 
+   if (TREE_CODE (var) == LABEL_DECL)
+     {
++      if (FORCED_LABEL (var) || DECL_NONLOCAL (var))
++	return var;
+       new_var = create_artificial_label (DECL_SOURCE_LOCATION (var));
+       DECL_CONTEXT (new_var) = current_function_decl;
+       insert_decl_map (&ctx->cb, var, new_var);
+@@ -10651,12 +10653,14 @@
+ 	      tree itype2 = TREE_TYPE (fd->loops[i - 1].v);
+ 	      if (POINTER_TYPE_P (itype2))
+ 		itype2 = signed_type_for (itype2);
++	      t = fold_convert (itype2, fd->loops[i - 1].step);
++	      t = force_gimple_operand_gsi (&gsi, t, true, NULL_TREE, true,
++					    GSI_SAME_STMT);
+ 	      t = build3 (COND_EXPR, itype2,
+ 			  build2 (fd->loops[i].cond_code, boolean_type_node,
+ 				  fd->loops[i].v,
+ 				  fold_convert (itype, fd->loops[i].n2)),
+-			  build_int_cst (itype2, 0),
+-			  fold_convert (itype2, fd->loops[i - 1].step));
++			  build_int_cst (itype2, 0), t);
+ 	      if (POINTER_TYPE_P (TREE_TYPE (fd->loops[i - 1].v)))
+ 		t = fold_build_pointer_plus (fd->loops[i - 1].v, t);
+ 	      else
+@@ -10663,12 +10667,14 @@
+ 		t = fold_build2 (PLUS_EXPR, itype2, fd->loops[i - 1].v, t);
+ 	      expand_omp_build_assign (&gsi, fd->loops[i - 1].v, t);
+ 
++	      t = fold_convert (itype, fd->loops[i].n1);
++	      t = force_gimple_operand_gsi (&gsi, t, true, NULL_TREE, true,
++					    GSI_SAME_STMT);
+ 	      t = build3 (COND_EXPR, itype,
+ 			  build2 (fd->loops[i].cond_code, boolean_type_node,
+ 				  fd->loops[i].v,
+ 				  fold_convert (itype, fd->loops[i].n2)),
+-			  fd->loops[i].v,
+-			  fold_convert (itype, fd->loops[i].n1));
++			  fd->loops[i].v, t);
+ 	      expand_omp_build_assign (&gsi, fd->loops[i].v, t);
+ 	    }
+ 	}
+@@ -15175,10 +15181,14 @@
+       rhs_p = gimple_omp_for_initial_ptr (stmt, i);
+       if (!is_gimple_min_invariant (*rhs_p))
+ 	*rhs_p = get_formal_tmp_var (*rhs_p, &body);
++      else if (TREE_CODE (*rhs_p) == ADDR_EXPR)
++	recompute_tree_invariant_for_addr_expr (*rhs_p);
+ 
+       rhs_p = gimple_omp_for_final_ptr (stmt, i);
+       if (!is_gimple_min_invariant (*rhs_p))
+ 	*rhs_p = get_formal_tmp_var (*rhs_p, &body);
++      else if (TREE_CODE (*rhs_p) == ADDR_EXPR)
++	recompute_tree_invariant_for_addr_expr (*rhs_p);
+ 
+       rhs_p = &TREE_OPERAND (gimple_omp_for_incr (stmt, i), 1);
+       if (!is_gimple_min_invariant (*rhs_p))
+@@ -18027,7 +18037,7 @@
+     }
+   if (kind == NULL)
+     {
+-      gcc_checking_assert (flag_openmp);
++      gcc_checking_assert (flag_openmp || flag_openmp_simd);
+       kind = "OpenMP";
+     }
+ 
+@@ -18446,7 +18456,7 @@
+   /* opt_pass methods: */
+   virtual bool gate (function *)
+   {
+-    return flag_cilkplus || flag_openacc || flag_openmp;
++    return flag_cilkplus || flag_openacc || flag_openmp || flag_openmp_simd;
+   }
+   virtual unsigned int execute (function *)
+     {
+Index: gcc/toplev.c
+===================================================================
+--- a/src/gcc/toplev.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/toplev.c	(.../branches/gcc-6-branch)
+@@ -2100,7 +2100,8 @@
+      enough to default flags appropriately.  */
+   decode_options (&global_options, &global_options_set,
+ 		  save_decoded_options, save_decoded_options_count,
+-		  UNKNOWN_LOCATION, global_dc);
++		  UNKNOWN_LOCATION, global_dc,
++		  targetm.target_option.override);
+ 
+   handle_common_deferred_options ();
+ 
+Index: gcc/tree-ssa-sccvn.c
+===================================================================
+--- a/src/gcc/tree-ssa-sccvn.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/tree-ssa-sccvn.c	(.../branches/gcc-6-branch)
+@@ -2169,7 +2169,7 @@
+       memset (&op, 0, sizeof (op));
+       op.type = vr->type;
+       op.opcode = MEM_REF;
+-      op.op0 = build_int_cst (ptr_type_node, at - rhs_offset);
++      op.op0 = build_int_cst (ptr_type_node, at - lhs_offset + rhs_offset);
+       op.off = at - lhs_offset + rhs_offset;
+       vr->operands[0] = op;
+       op.type = TREE_TYPE (rhs);
+Index: gcc/ChangeLog
+===================================================================
+--- a/src/gcc/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,1200 @@
++2018-03-11  John David Anglin  <danglin@gcc.gnu.org>
++
++	Backport from mainline
++	2018-02-14  John David Anglin  <danglin@gcc.gnu.org>
++
++	PR target/83984
++	* config/pa/pa.md: Load address of PIC label using the linkage table
++	if the label is nonlocal.
++
++	Backport from mainline
++	2018-03-06  John David Anglin  <danglin@gcc.gnu.org>
++
++	* config/pa/pa.h (ASM_GENERATE_INTERNAL_LABEL): Revise to use
++	sprint_ul.
++	(ASM_OUTPUT_ADDR_VEC_ELT): Revise for above change.
++	(ASM_OUTPUT_ADDR_DIFF_ELT): Likewise.
++	* config/pa/pa64-hpux.h (ASM_GENERATE_INTERNAL_LABEL): Revise as above.
++
++2018-03-08  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2016-12-14  Jakub Jelinek  <jakub@redhat.com>
++
++	PR debug/77844
++	* valtrack.c: Include rtl-iter.h.
++	(struct rtx_subst_pair): Add insn field.
++	(propagate_for_debug_subst): If pair->to contains at least 2
++	regs, create a DEBUG_INSN with a debug temp before pair->insn
++	and replace from with the debug temp instead of pair->to.
++	(propagate_for_debug): Initialize p.insn.
++	* combine.c (insn_uid_check): New inline function.
++	(INSN_COST, LOG_LINKS): Use it instead of INSN_UID.
++	(find_single_use, combine_instructions,
++	cant_combine_insn_p, try_combine): Use NONDEBUG_INSN_P instead of
++	INSN_P.
++
++2018-03-08  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-01-04  Martin Liska  <mliska@suse.cz>
++
++	PR ipa/82352
++	* ipa-icf.c (sem_function::merge): Do not cross comdat boundary.
++
++2018-03-08  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-10-31  Martin Liska  <mliska@suse.cz>
++
++	PR gcov-profile/82633
++	* doc/gcov.texi: Document -fkeep-{static,inline}-functions and
++	their interaction with GCOV infrastructure.
++	* configure.ac: Add -fkeep-static-functions to
++	coverage_flags.
++	* configure: Regenerate.
++
++2018-03-08  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-10-27  Martin Liska  <mliska@suse.cz>
++
++	PR gcov-profile/82457
++	* doc/invoke.texi: Document that one needs a non-strict ISO mode
++	for fork-like functions to be properly instrumented.
++
++2018-03-07  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2018-02-08  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
++
++	* config/s390/s390-opts.h (enum indirect_branch): Define.
++	* config/s390/s390-protos.h (s390_return_addr_from_memory)
++	(s390_indirect_branch_via_thunk)
++	(s390_indirect_branch_via_inline_thunk): Add function prototypes.
++	(enum s390_indirect_branch_type): Define.
++	* config/s390/s390.c (struct s390_frame_layout, struct
++	machine_function): Remove.
++	(indirect_branch_prez10thunk_mask, indirect_branch_z10thunk_mask)
++	(indirect_branch_table_label_no, indirect_branch_table_name):
++	Define variables.
++	(INDIRECT_BRANCH_NUM_OPTIONS): Define macro.
++	(enum s390_indirect_branch_option): Define.
++	(s390_return_addr_from_memory): New function.
++	(s390_handle_string_attribute): New function.
++	(s390_attribute_table): Add new attribute handler.
++	(s390_execute_label): Handle UNSPEC_EXECUTE_JUMP patterns.
++	(s390_indirect_branch_via_thunk): New function.
++	(s390_indirect_branch_via_inline_thunk): New function.
++	(s390_function_ok_for_sibcall): When jumping via thunk disallow
++	sibling call optimization for non z10 compiles.
++	(s390_emit_call): Force indirect branch target to be a single
++	register.  Add r1 clobber for non-z10 compiles.
++	(s390_emit_epilogue): Emit return jump via return_use expander.
++	(s390_reorg): Handle JUMP_INSNs as execute targets.
++	(s390_option_override_internal): Perform validity checks for the
++	new command line options.
++	(s390_indirect_branch_attrvalue): New function.
++	(s390_indirect_branch_settings): New function.
++	(s390_set_current_function): Invoke s390_indirect_branch_settings.
++	(s390_output_indirect_thunk_function):  New function.
++	(s390_code_end): Implement target hook.
++	(s390_case_values_threshold): Implement target hook.
++	(TARGET_ASM_CODE_END, TARGET_CASE_VALUES_THRESHOLD): Define target
++	macros.
++	* config/s390/s390.h (struct s390_frame_layout)
++	(struct machine_function): Move here from s390.c.
++	(TARGET_INDIRECT_BRANCH_NOBP_RET)
++	(TARGET_INDIRECT_BRANCH_NOBP_JUMP)
++	(TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK)
++	(TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK)
++	(TARGET_INDIRECT_BRANCH_NOBP_CALL)
++	(TARGET_DEFAULT_INDIRECT_BRANCH_TABLE)
++	(TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL)
++	(TARGET_INDIRECT_BRANCH_THUNK_NAME_EX)
++	(TARGET_INDIRECT_BRANCH_TABLE): Define macros.
++	* config/s390/s390.md (UNSPEC_EXECUTE_JUMP)
++	(INDIRECT_BRANCH_THUNK_REGNUM): Define constants.
++	(mnemonic attribute): Add values which aren't recognized
++	automatically.
++	("*cjump_long", "*icjump_long", "*basr", "*basr_r"): Disable
++	pattern for branch conversion.  Fix mnemonic attribute.
++	("*c<code>", "*sibcall_br", "*sibcall_value_br", "*return"): Emit
++	indirect branch via thunk if requested.
++	("indirect_jump", "<code>"): Expand patterns for branch conversion.
++	("*indirect_jump"): Disable for branch conversion using out of
++	line thunks.
++	("indirect_jump_via_thunk<mode>_z10")
++	("indirect_jump_via_thunk<mode>")
++
++2018-03-07  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2018-02-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
++
++	PR target/PR84295
++	* config/s390/s390.c (s390_set_current_function): Invoke
++	s390_indirect_branch_settings also if fndecl didn't change.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-02-20  Martin Liska  <mliska@suse.cz>
++
++	PR c/84310
++	PR target/79747
++	* final.c (shorten_branches): Build align_tab array with one
++	more element.
++	* opts.c (finish_options): Add alignment option limit check.
++	(MAX_CODE_ALIGN): Likewise.
++	(MAX_CODE_ALIGN_VALUE): Likewise.
++	* doc/invoke.texi: Document maximum allowed option value for
++	all -falign-* options.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-02-19  Martin Liska  <mliska@suse.cz>
++
++	PR other/80589
++	* doc/invoke.texi: Fix typo.
++	* params.def (PARAM_MAX_LOOP_HEADER_INSNS): Likewise.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-02-05  Martin Liska  <mliska@suse.cz>
++
++	PR gcov-profile/84137
++	* doc/gcov.texi: Fix typo in documentation.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-02-05  Martin Liska  <mliska@suse.cz>
++
++	PR gcov-profile/83879
++	* doc/gcov.texi: Document necessity of --dynamic-list-data when
++	using dlopen functionality.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-12-19  Martin Liska  <mliska@suse.cz>
++
++	PR rtl-optimization/82675
++	* loop-unroll.c (unroll_loop_constant_iterations): Allocate one
++	more element in sbitmap.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-03-05  Martin Liska  <mliska@suse.cz>
++
++	* ipa-utils.c (ipa_merge_profiles): Do not merge alias or
++	a function without profile.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-02-21  Jan Hubicka  <hubicka@ucw.cz>
++
++	PR c/84229
++	* ipa-cp.c (determine_versionability): Do not version functions caling
++	va_arg_pack.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-02-08  Jan Hubicka  <hubicka@ucw.cz>
++
++	PR ipa/81360
++	* cgraph.h (symtab_node::output_to_lto_symbol_table_p): Declare
++	* symtab.c: Include builtins.h
++	(symtab_node::output_to_lto_symbol_table_p): Move here
++	from lto-streamer-out.c:output_symbol_p.
++	* lto-streamer-out.c (write_symbol): Turn early exit to assert.
++	(output_symbol_p): Move all logic to symtab.c
++	(produce_symtab): Update.
++
++2017-03-02  Thomas Schwinge  <thomas@codesourcery.com>
++
++	Backport from trunk r256891:
++	2018-01-19  Cesar Philippidis  <cesar@codesourcery.com>
++
++	PR target/83790
++	* config/nvptx/nvptx.c (output_init_frag): Don't use generic address
++	spaces for function labels.
++
++2018-02-21  Sudakshina Das  <sudi.das@arm.com>
++
++	Backport from trunk
++	2018-01-10  Sudakshina Das  <sudi.das@arm.com>
++
++	PR target/82096
++	* expmed.c (emit_store_flag_force): Swap if const op0
++	and change VOIDmode to mode of op0.
++
++2018-02-15  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Back port from trunk
++	2018-02-06  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	PR target/84154
++	* config/rs6000/rs6000.md (su code attribute): Use "u" for
++	unsigned_fix, not "s".
++
++2018-02-15  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>
++
++	Back port from mainline
++	2018-01-30  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>
++
++	PR target/83758
++	* config/rs6000/rs6000.c (rs6000_internal_arg_pointer): Only return
++	a reg rtx.
++
++2018-02-10  John David Anglin  <danglin@gcc.gnu.org>
++
++	* config/pa/pa.c (hppa_profile_hook): Mark SYMBOL_REF for _mcount as
++	function label.
++
++	Backport from mainline
++	2018-02-01  Aldy Hernandez  <aldyh@redhat.com>
++
++	PR target/84089
++	* config/pa/predicates.md (base14_operand): Handle VOIDmode.
++
++2018-02-05  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	Backport from mainline
++	2018-01-30  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	PR bootstrap/84017
++	* configure.ac (gcc_cv_as_shf_merge): Disable on Solaris 10/x86.
++	* configure: Regenerate.
++
++2018-02-01  Renlin Li  <renlin.li@arm.com>
++
++	Backport from mainline
++	2018-02-01  Renlin Li  <renlin.li@arm.com>
++
++	PR target/83370
++	* config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle
++	TAILCALL_ADDR_REGS.
++	(aarch64_register_move_cost): Likewise.
++	* config/aarch64/aarch64.h (reg_class): Rename CALLER_SAVE_REGS to
++	TAILCALL_ADDR_REGS.
++	(REG_CLASS_NAMES): Likewise.
++	(REG_CLASS_CONTENTS): Rename CALLER_SAVE_REGS to
++	TAILCALL_ADDR_REGS. Remove IP registers.
++	* config/aarch64/aarch64.md (Ucs): Update register constraint.
++
++2018-02-01  Bin Cheng  <bin.cheng@arm.com>
++
++	Backport from mainline
++	2017-11-15  Bin Cheng  <bin.cheng@arm.com>
++
++	PR tree-optimization/82726
++	PR tree-optimization/70754
++	* tree-predcom.c (order_drefs_by_pos): New function.
++	(combine_chains): Move code setting has_max_use_after to...
++	(try_combine_chains): ...here.  New parameter.  Sort combined chains
++	according to position information.
++	(tree_predictive_commoning_loop): Update call to above function.
++	(update_pos_for_combined_chains, pcom_stmt_dominates_stmt_p): New.
++
++2018-01-31  Richard Biener <rguenther@suse.de>
++	    Kelvin Nilsen  <kelvin@gcc.gnu.org>
++
++	Backport from mainline
++	2018-01-29  Richard Biener <rguenther@suse.de>
++		    Kelvin Nilsen  <kelvin@gcc.gnu.org>
++
++	PR bootstrap/80867
++	* tree-vect-stmts.c (vectorizable_call): Don't call
++	targetm.vectorize_builtin_md_vectorized_function if callee is
++	NULL.
++
++2018-01-29  Alan Modra  <amodra@gmail.com>
++
++	Backport from mainline
++	2018-01-26  Alan Modra  <amodra@gmail.com>
++	PR target/84033
++	* config/rs6000/rs6000.c (rtx_is_swappable_p): Exclude
++	UNSPEC_VBPERMQ.
++
++2018-01-24  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2018-01-02  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	* config/rs6000/rs6000-p8swap.c (swap_feeds_both_load_and_store):
++	New function.
++	(rs6000_analyze_swaps): Mark a web unoptimizable if it contains a
++	swap associated with both a load and a store.
++
++2018-01-23  Peter Bergner  <bergner@vnet.ibm.com>
++
++	Back port from mainline
++	2018-01-10  Peter Bergner  <bergner@vnet.ibm.com>
++
++	PR target/83399
++	* config/rs6000/rs6000.c (print_operand) <'y'>: Use
++	VECTOR_MEM_ALTIVEC_OR_VSX_P.
++	* config/rs6000/vsx.md (*vsx_le_perm_load_<mode> for VSX_D): Use
++	indexed_or_indirect_operand predicate.
++	(*vsx_le_perm_load_<mode> for VSX_W): Likewise.
++	(*vsx_le_perm_load_v8hi): Likewise.
++	(*vsx_le_perm_load_v16qi): Likewise.
++	(*vsx_le_perm_store_<mode> for VSX_D): Likewise.
++	(*vsx_le_perm_store_<mode> for VSX_W): Likewise.
++	(*vsx_le_perm_store_v8hi): Likewise.
++	(*vsx_le_perm_store_v16qi): Likewise.
++	(eight unnamed splitters): Likewise.
++
++2018-01-23  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Back port from trunk
++	2018-01-22  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	PR target/83862
++	* config/rs6000/rs6000-protos.h (rs6000_split_signbit): Delete,
++	no longer used.
++	* config/rs6000/rs6000.c (rs6000_split_signbit): Likewise.
++	* config/rs6000/rs6000.md (signbit<mode>2): Change code for IEEE
++	128-bit to produce an UNSPEC move to get the double word with the
++	signbit and then a shift directly to do signbit.
++	(signbit<mode>2_dm): Replace old IEEE 128-bit signbit
++	implementation with a new version that just does either a direct
++	move or a regular move.  Move memory interface to separate insns.
++	Move insns so they are next to the expander.
++	(signbit<mode>2_dm_mem_be): New combiner insns to combine load
++	with signbit move.  Split big and little endian case.
++	(signbit<mode>2_dm_mem_le): Likewise.
++	(signbit<mode>2_dm_<su>ext): Delete, no longer used.
++	(signbit<mode>2_dm2): Likewise.
++
++2018-01-21  Oleg Endo  <olegendo@gcc.gnu.org>
++
++	PR target/81485
++	* config/sh/sh-protos.h (sh_find_set_of_reg): Remove assert.
++
++2018-01-21  Oleg Endo  <olegendo@gcc.gnu.org>
++
++	Backport from mainline
++	2018-01-21  Oleg Endo  <olegendo@gcc.gnu.org>
++
++	PR target/80870
++	* config/sh/sh_optimize_sett_clrt.cc:
++	Use INCLUDE_ALGORITHM and INCLUDE_VECTOR instead of direct includes.
++
++2018-01-16  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	Backport from mainline
++	2017-12-18  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	PR rtl-optimization/83424
++	* rtlanal.c (dead_or_set_regno_p): Handle CLOBBER just like SET.
++
++2018-01-14  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2018-01-08  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR target/83677
++	* config/rs6000/altivec.md (*altivec_vpermr_<mode>_internal):
++	Reverse order of second and third operands in first alternative.
++	* config/rs6000/rs6000.c (rs6000_expand_vector_set): Reverse order
++	of first and second elements in UNSPEC_VPERMR vector.
++	(altivec_expand_vec_perm_le): Likewise.
++
++2018-01-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
++
++	Backport from mainline
++	2017-12-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
++
++	PR target/82975
++	* config/arm/arm.h (TEST_REGNO): Check reg_renumber is set before
++	accessing it.  Adjust comment.
++
++2017-12-17  John David Anglin  <danglin@gcc.gnu.org>
++
++	Backport from mainline
++	2017-12-03  John David Anglin  <danglin@gcc.gnu.org>
++
++	* config/pa/pa.c (pa_legitimate_address_p): For scaled indexing,
++	require base operand is a REG_POINTER prior to reload on targets
++	with non-equivalent space registers.
++
++2017-12-15  Eric Botcazou  <ebotcazou@adacore.com>
++
++	PR target/66488
++	* ggc-page.c (HOST_BITS_PER_PTR): Do not define here...
++	* hwint.h (HOST_BITS_PER_PTR): ...but here instead.
++
++2017-12-14  Peter Bergner  <bergner@vnet.ibm.com>
++
++	Backport from mainline
++	2017-12-13  Peter Bergner  <bergner@vnet.ibm.com>
++
++	* config/rs6000/ppc-auxv.h (PPC_FEATURE2_HTM_NO_SUSPEND): New define.
++	* config/rs6000/rs6000.c (cpu_supports_info): Use it.
++
++2017-12-14  Peter Bergner  <bergner@vnet.ibm.com>
++
++	Backport from mainline
++	2017-10-02  Peter Bergner  <bergner@vnet.ibm.com>
++
++	PR target/80210
++	* config/rs6000/rs6000.c (rs6000_option_override_internal): Rewrite
++	function to not use the have_cpu variable.  Do not set cpu_index,
++	rs6000_cpu_index or rs6000_tune_index if we end up using TARGET_DEFAULT
++	or the default cpu.
++	(rs6000_valid_attribute_p): Remove duplicate initializations of
++	old_optimize and func_optimize.
++	(rs6000_pragma_target_parse): Call rs6000_activate_target_options ().
++	(rs6000_activate_target_options): Make global.
++	* config/rs6000/rs6000-protos.h (rs6000_activate_target_options): Add
++	prototype.
++
++2017-12-11  Thomas Schwinge  <thomas@codesourcery.com>
++
++	PR c++/83301
++
++	Backport trunk r243377:
++	2016-12-07  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c++/78692
++	* cgraph.c (cgraph_edge::redirect_call_stmt_to_callee): Set lhs
++	var to lhs of new_stmt right before noreturn handling rather than to
++	lhs of e->call_stmt early.
++
++2017-12-04  Sebastian Peryt  <sebastian.peryt@intel.com>
++	H.J. Lu  <hongjiu.lu@intel.com>
++
++	Bakcported from trunk
++	PR target/82941
++	PR target/82942
++	PR target/82990
++	* config/i386/i386.c (pass_insert_vzeroupper): Remove
++	TARGET_AVX512F check from gate condition.
++	(ix86_check_avx256_register): Changed to ...
++	(ix86_check_avx_upper_register): ... this. Add extra check for
++	VALID_AVX512F_REG_OR_XI_MODE.
++	(ix86_avx_u128_mode_needed): Changed
++	ix86_check_avx256_register to ix86_check_avx_upper_register.
++	(ix86_check_avx256_stores): Changed to ...
++	(ix86_check_avx_upper_stores): ... this. Changed
++	ix86_check_avx256_register to ix86_check_avx_upper_register.
++	(ix86_avx_u128_mode_after): Changed
++	avx_reg256_found to avx_upper_reg_found. Changed
++	ix86_check_avx256_stores to ix86_check_avx_upper_stores.
++	(ix86_avx_u128_mode_entry): Changed
++	ix86_check_avx256_register to ix86_check_avx_upper_register.
++	(ix86_avx_u128_mode_exit): Ditto.
++	(ix86_option_override_internal): Set MASK_VZEROUPPER if
++	neither -mzeroupper nor -mno-zeroupper is used and
++	TARGET_EMIT_VZEROUPPER is set.
++	* config/i386/i386.h: (host_detect_local_cpu): New define.
++	(TARGET_EMIT_VZEROUPPER): New.
++	* config/i386/x86-tune.def: Add X86_TUNE_EMIT_VZEROUPPER
++
++2017-12-01  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	Backport from mainline
++	2017-11-28  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	PR 81288/target
++	* config/rs6000/rs6000.c (rs6000_rtx_costs): Do not handle
++	TARGET_ISEL && !TARGET_MFCRF differently.  Simplify code.
++
++2017-11-29  Daniel Cederman  <cederman@gaisler.com>
++
++	Backport from mainline
++	* config/sparc/sparc.c (sparc_do_work_around_errata): Treat the
++        movsi_pic_gotdata_op instruction as a load for the UT699 errata
++        workaround.
++
++2017-11-24  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	Backport from mainline
++	2017-11-17  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	PR rtl-optimization/82621
++	* combine.c (try_combine): Do not split PARALLELs of two SETs if the
++	dest of one of those SETs is unused.
++
++2017-11-21  Pat Haugen  <pthaugen@us.ibm.com>
++
++	Backport from mainline
++	2017-11-21  Pat Haugen  <pthaugen@us.ibm.com>
++
++	* config/rs6000/ppc-asm.h (f50, vs50): Fix values.
++
++2017-11-21  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	Backport from mainline
++	2017-11-14  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	* config.gcc (*-*-solaris2*): Enable default_use_cxa_atexit since
++	Solaris 11.  Update comment.
++	* configure.ac (gcc_cv_ld_pid): Adapt comment for Solaris 12
++	renaming.
++	* config/sol2.h (STARTFILE_SPEC): Likewise.
++	* configure: Regenerate.
++
++2017-11-16  Uros Bizjak  <ubizjak@gmail.com>
++
++	* config/i386/i386.c (x86_print_call_or_nop): Emit 5 byte nop
++	explicitly as a stream of bytes.
++
++2017-11-13  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	Backport from mainline
++	2017-10-26  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	* configure.ac (gcc_cv_as_ix86_xbrace_comment): Check if assembler
++	supports -xbrace_comment option.
++	* configure: Regenerate.
++	* config.in: Regenerate.
++	* config/i386/sol2.h (ASM_XBRACE_COMMENT_SPEC): Define.
++	(ASM_CPU_SPEC): Use it.
++
++2017-11-09  Andre McCurdy  <armccurdy@gmail.com>
++
++	* config/arm/arm-cores.def: Fix missing FL_LPAE flag for armv7ve
++	compatible cores.
++
++2017-11-09  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	Backport from mainline
++	2017-11-01  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	PR rtl-optimization/64682
++	PR rtl-optimization/69567
++	PR rtl-optimization/69737
++	PR rtl-optimization/82683
++	* combine.c (distribute_notes) <REG_DEAD>: If the new I2 sets the same
++	register mentioned in the note, drop the note, unless it came from I3,
++	in which case it should go to I3 again.
++
++2017-10-31  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/82772
++	* config/alpha/sync.md (fetchop_constr) <and>: Change to "rINM".
++
++2017-10-20  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-03-09  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	* config/rs6000/rs6000.c (rs6000_gen_le_vsx_permute): Use rotate
++	instead of vec_select for V1TImode.
++	* conifg/rs6000/vsx.md (VSX_LE): Remove mode iterator that is no
++	longer needed.
++	(VSX_LE_128): Add V1TI to this mode iterator.
++	(*vsx_le_perm_load_<mode>): Change to use VSX_D mode iterator.
++	(*vsx_le_perm_store_<mode>): Likewise.
++	(pre-reload splitter for VSX stores): Likewise.
++	(post-reload splitter for VSX stores): Likewise.
++	(*vsx_xxpermdi2_le_<mode>): Likewise.
++	(*vsx_lxvd2x2_le_<mode>): Likewise.
++	(*vsx_stxvd2x2_le_<mode>): Likewise.
++
++2017-10-19  Richard Earnshaw  <rearnsha@arm.com>
++
++	PR target/82445
++	* config/arm/arm.c (align_ok_ldrd_strd): New function.
++	(mem_ok_for_ldrd_strd): New parameter align.  Extract the alignment of
++	the mem into it.
++	(gen_operands_ldrd_strd): Validate the alignment of the accesses.
++
++2017-10-18  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	PR rtl-optimization/82602
++	* ira.c (rtx_moveable_p): Return false for volatile asm.
++
++2017-10-17  Jakub Jelinek  <jakub@redhat.com>
++
++	PR tree-optimization/82549
++	* fold-const.c (optimize_bit_field_compare, fold_truth_andor_1):
++	Formatting fixes.  Instead of calling make_bit_field_ref with negative
++	bitpos return 0.
++
++2017-10-13  Jakub Jelinek  <jakub@redhat.com>
++
++	PR target/82274
++	* internal-fn.c (expand_mul_overflow): If both operands have
++	the same highpart of -1 or 0 and the topmost bit of lowpart
++	is different, overflow is if res <= 0 rather than res < 0.
++
++2017-10-10  Andreas Tobler  <andreast@gcc.gnu.org>
++
++	* config.gcc: (armv7*-*-freebsd*): New target.
++	Define TARGET_FREEBSD_ARMv7
++	* config/arm/freebsd.h: Use TARGET_FREEBSD_ARMv7 to define the
++	default cpu for armv7*-*-freebsd*.
++
++2017-10-02  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-09-30  Jakub Jelinek  <jakub@redhat.com>
++
++	* config/i386/i386.c (ix86_split_idivmod): Use mode instead of
++	always SImode for DIV and MOD in REG_EQUAL notes.
++
++2017-10-02  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-09-29  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR tree-optimization/82337
++	* gimple-ssa-strength-reduction.c (find_phi_def): Don't record a
++	phi definition if the PHI result appears in an abnormal PHI.
++	(find_basis_for_base_expr): Don't record a basis if the LHS of the
++	basis appears in an abnormal PHI.
++
++2017-09-21  Alan Modra  <amodra@gmail.com>
++
++	PR target/81996
++	* gcc/config/rs6000/rs6000.c (rs6000_return_addr): Use
++	stack_pointer_rtx for count 0.  Update comments.  Break up
++	large rtl expression.
++
++2017-09-21  Wilco Dijkstra  <wdijkstr@arm.com>
++
++	PR target/71951
++	* config/aarch64/aarch64.h (LIBGCC2_UNWIND_ATTRIBUTE): Define.
++
++2017-09-19  Uros Bizjak  <ubizjak@gmail.com>
++
++	* config/i386/i386.c (fold_builtin_cpu): Add M_AMDFAM17H
++	to processor_model and "amdfam17h" to arch_names_table.
++	* doc/extend.texi (__builtin_cpu_is): Document amdfam17h CPU name.
++
++2017-09-19  Martin Liska  <mliska@suse.cz>
++
++	PR c++/81355
++	* config/i386/i386.c (sorted_attr_string): Skip empty strings.
++
++2017-09-19  Martin Liska  <mliska@suse.cz>
++
++	Revert backport:
++	2017-08-10  Martin Liska  <mliska@suse.cz>
++
++	PR c++/81355
++	* c-attribs.c (handle_target_attribute):
++	Report warning for an empty string argument of target attribute.
++
++2017-09-18  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2017-08-28  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/81977
++	* tree-ssa-sccvn.c (vn_reference_lookup_3): Fix look through
++	memcpy.
++
++	2017-09-04  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/82084
++	* fold-const.h (can_native_encode_string_p): Declare.
++	* fold-const.c (can_native_encode_string_p): Factor out from ...
++	(native_encode_string): ... here.
++	* tree-vect-stmts.c (vectorizable_store): Call it to avoid
++	vectorizing stores from constants we later cannot handle.
++
++	2017-07-25  Richard Biener  <rguenther@suse.de>
++
++	PR middle-end/81505
++	* fold-const.c (fold_negate_const): TREE_OVERFLOW should be
++	sticky.
++
++2017-09-15  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-09-05  Jakub Jelinek  <jakub@redhat.com>
++
++	PR middle-end/81768
++	* omp-low.c (lower_omp_for): Recompute tree invariant if
++	gimple_omp_for_initial/final is ADDR_EXPR.
++
++	PR middle-end/81768
++	* omp-low.c (expand_omp_simd): Force second operands of COND_EXPR
++	into gimple val before gimplification fo the COND_EXPR.
++
++	2017-09-04  Jakub Jelinek  <jakub@redhat.com>
++
++	* lra-remat.c (reg_overlap_for_remat_p): Fix a pasto.
++
++	2017-08-09  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c/81687
++	* omp-low.c (omp_copy_decl): Don't remap FORCED_LABEL or DECL_NONLOCAL
++	LABEL_DECLs.
++	* tree-cfg.c (move_stmt_op): Don't adjust DECL_CONTEXT of FORCED_LABEL
++	or DECL_NONLOCAL labels.
++	(move_stmt_r) <case GIMPLE_LABEL>: Adjust DECL_CONTEXT of FORCED_LABEL
++	or DECL_NONLOCAL labels here.
++
++	2017-08-08  Richard Biener  <rguenther@suse.de>
++
++	PR middle-end/81766
++	* function.c (thread_prologue_and_epilogue_insns): Restore
++	behavior of always calling find_many_sub_basic_blocks on
++	the inserted prologue.
++
++	2017-08-03  Jakub Jelinek  <jakub@redhat.com>
++
++	PR target/81621
++	* bb-reorder.c (pass_partition_blocks::execute): Return TODO_df_finish
++	after setting changeable df flags.
++
++	PR middle-end/81052
++	* omp-low.c (diagnose_sb_0): Handle flag_openmp_simd like flag_openmp.
++	(pass_diagnose_omp_blocks::gate): Enable also for flag_openmp_simd.
++
++	2017-08-02  Jakub Jelinek  <jakub@redhat.com>
++
++	PR middle-end/79499
++	* function.c (thread_prologue_and_epilogue_insns): Determine blocks
++	for find_many_sub_basic_blocks bitmap by looking up BLOCK_FOR_INSN
++	of first NONDEBUG_INSN_P in each of the split_prologue_seq and
++	prologue_seq sequences - if any.
++
++	2017-06-30  Jakub Jelinek  <jakub@redhat.com>
++
++	PR target/81225
++	* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): For
++	V8FI, V16FI and VI8F_256 iterators, use <store_mask_predicate> instead
++	of nonimmediate_operand and <store_mask_constraint> instead of m for
++	the input operand.  For V8FI iterator, always split if input is a MEM.
++	For V16FI and V8SF_256 iterators, don't test if both operands are MEM
++	if <mask_applied>.  For VI4F_256 iterator, use <store_mask_predicate>
++	instead of register_operand and <store_mask_constraint> instead of v for
++	the input operand.  Make sure both operands aren't MEMs for if not
++	<mask_applied>.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-08-11  Martin Liska  <mliska@suse.cz>
++
++	PR tree-opt/79987
++	* tree-chkp.c (chkp_get_bounds_for_decl_addr): Do not instrument
++	variables of void type.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-06-28  Martin Liska  <mliska@suse.cz>
++
++	PR sanitizer/81224
++	* asan.c (instrument_derefs): Bail out inner references
++	that are hard register variables.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-08-30  Martin Liska  <mliska@suse.cz>
++
++	PR inline-asm/82001
++	* ipa-icf-gimple.c (func_checker::compare_tree_list_operand):
++	Rename to ...
++	(func_checker::compare_asm_inputs_outputs): ... this function.
++	(func_checker::compare_gimple_asm): Use the function to compare
++	also ASM constrains.
++	* ipa-icf-gimple.h: Rename the function.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-08-29  Martin Liska  <mliska@suse.cz>
++
++	PR other/39851
++	* gcc.c (driver_handle_option): Add new argument.
++	* opts-common.c (handle_option): Pass
++	target_option_override_hook.
++	* opts-global.c (lang_handle_option): Add new option.
++	(set_default_handlers):  Add new argument.
++	(decode_options): Likewise.
++	* opts.c (target_handle_option): Likewise.
++	(common_handle_option): Call target_option_override_hook.
++	* opts.h (struct cl_option_handler_func): Add hook for
++	target option override.
++	(struct cl_option_handlers): Likewise.
++	(set_default_handlers): Add new argument.
++	(decode_options): Likewise.
++	(common_handle_option): Likewise.
++	(target_handle_option): Likewise.
++	* toplev.c (toplev::main): Pass targetm.target_option.override
++	hook.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-08-10  Martin Liska  <mliska@suse.cz>
++
++	PR c++/81355
++	* c-attribs.c (handle_target_attribute):
++	Report warning for an empty string argument of target attribute.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-08-08  Martin Liska  <mliska@suse.cz>
++
++	PR tree-opt/81696
++	* ipa-icf-gimple.c (func_checker::compare_cst_or_decl): Consider
++	LABEL_DECLs that can be from a different function.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-06-28  Martin Liska  <mliska@suse.cz>
++
++	PR ipa/81128
++	* ipa-visibility.c (non_local_p): Handle visibility.
++
++2017-09-12  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-09-05  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR target/81833
++	* config/rs6000/altivec.md (altivec_vsum2sws): Convert from a
++	define_insn to a define_expand.
++	(altivec_vsum2sws_direct): New define_insn.
++	(altivec_vsumsws): Convert from a define_insn to a define_expand.
++
++2017-09-11  Max Filippov  <jcmvbkbc@gmail.com>
++
++	Backport from mainline
++	PR target/82181
++	* config/xtensa/xtensa.c (xtensa_mem_offset): Check that both
++	words of DImode object are reachable by xtensa_uimm8x4 access.
++
++2017-09-06  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline:
++	2017-08-30  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR tree-optimization/81987
++	* gimple-ssa-strength-reduction.c (insert_initializers): Don't
++	insert an initializer in a location not dominated by the stride
++	definition.
++
++2017-09-05  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-08-29  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++		    Jakub Jelinek  <jakub@redhat.com>
++		    Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/81503
++	* gimple-ssa-strength-reduction.c (replace_mult_candidate): Ensure
++	folded constant fits in the target type; reorder tests for clarity.
++
++2017-08-30  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Back port from trunk
++	2017-08-07  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	PR target/81593
++	* config/rs6000/vsx.md (vsx_concat_<mode>_1): New combiner insns
++	to recognize inserting into a vector from a double word element
++	that was extracted from another vector, and eliminate extra
++	XXPERMDI instructions.
++	(vsx_concat_<mode>_2): Likewise.
++	(vsx_concat_<mode>_3): Likewise.
++	(vsx_set_<mode>, VSX_D): Rewrite vector set in terms of vector
++	concat to allow optimizing inserts from previous extracts.
++
++2017-08-29  Alan Modra  <amodra@gmail.com>
++
++	Apply from mainline
++	2017-08-12  Alan Modra  <amodra@gmail.com>
++	PR target/81170
++	PR target/81295
++	* config/rs6000/sysv4.h (STARTFILE_LINUX_SPEC): Upgrade to
++	match gnu-user.h startfile.
++	(ENDFILE_LINUX_SPEC): Similarly.
++
++	2017-08-08  Alan Modra  <amodra@gmail.com>
++		    H.J. Lu  <hongjiu.lu@intel.com>
++	PR target/81170
++	PR target/81295
++	PR driver/81523
++	* gcc.c (NO_PIE_SPEC): Delete.
++	(PIE_SPEC): Define as !no-pie/pie.  Move static|shared|r
++	exclusion..
++	(LINK_PIE_SPEC): ..to here.
++	(LINK_COMMAND_SPEC): Support -no-pie.
++	* config/gnu-user.h (GNU_USER_TARGET_STARTFILE_SPEC): Correct
++	chain of crtbegin*.o selection, update for PIE_SPEC changes and
++	format.
++	(GNU_USER_TARGET_ENDFILE_SPEC): Similarly.
++	* config/sol2.h (STARTFILE_CRTBEGIN_SPEC): Similarly.
++	(ENDFILE_CRTEND_SPEC): Similarly.
++
++2017-08-24  Yvan Roux  <yvan.roux@linaro.org>
++
++	Backport from mainline
++	2017-04-17  Bernd Edlinger  <bernd.edlinger@hotmail.de>
++
++	PR c++/80287
++	* class.c (fixup_may_alias): Fix all type variants.
++
++2017-08-22  Peter Bergner  <bergner@vnet.ibm.com>
++
++	Backport from mainline
++	2017-08-17  Peter Bergner  <bergner@vnet.ibm.com>
++
++	PR target/80210
++	* config/rs6000/rs6000.c (rs6000_activate_target_options): New function.
++	(rs6000_set_current_function): Rewrite function to use it.
++
++2017-08-22  Georg-Johann Lay  <avr@gjlay.de>
++
++	Backport from 2017-08-22 trunk r251256.
++
++	PR target/81910
++	* config/avr/avr.c (avr_handle_addr_attribute): Early return if
++	not VAR_P. Filter attribute warnings with OPT_Wattributes.
++	(avr_attribute_table) <io, io_low, address>: Initialize
++	.decl_required with true.
++
++2017-08-21  Georg-Johann Lay  <avr@gjlay.de>
++
++	PR target/79883
++	* config/avr/avr.c (avr_set_current_function): Typo in diagnostic.
++
++2017-08-19  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/81894
++	* doc/extend.texi (x86 Built-in Functions): Correct the name of
++	__builtin_ia32_lzcnt_u16.
++
++2017-08-17  Uros Bizjak  <ubizjak@gmail.com>
++
++	Backport from mainline
++	2017-08-17  Maxim Ostapenko  <m.ostapenko@samsung.com>
++
++	PR target/81861
++	* config/i386/i386.c (ix86_option_override_internal): Save target
++	specific options after ix86_stack_protector_guard_reg was changed.
++
++2017-08-16  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-08-08  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR tree-optimization/81354
++	* gimple-ssa-strength-reduction.c (create_add_on_incoming_edge):
++	Insert on edges rather than explicitly creating landing pads.
++	(analyze_candidates_and_replace): Commit edge inserts.
++
++2017-08-01  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/81641
++	* config/i386/i386.c (ix86_print_operand_address_as): For -masm=intel
++	print "ds:" only for immediates in generic address space.
++
++2017-07-31  Jakub Jelinek  <jakub@redhat.com>
++
++	PR sanitizer/81604
++	* ubsan.c (ubsan_type_descriptor): For UBSAN_PRINT_ARRAY don't
++	change type to the element type, instead add eltype variable and
++	use it where we are interested in the element type.
++
++2017-07-28  Peter Bergner  <bergner@vnet.ibm.com>
++
++	Backport from mainline
++	2017-07-28  Peter Bergner  <bergner@vnet.ibm.com>
++
++	* config/rs6000/ppc-auxv.h (PPC_FEATURE2_DARN): New define.
++	(PPC_FEATURE2_SCV): Likewise.
++	* config/rs6000/rs6000.c (cpu_supports_info): Use them.
++
++2017-07-28  Bin Cheng  <bin.cheng@arm.com>
++
++	Backport from mainline r250496
++	2017-07-25  Bin Cheng  <bin.cheng@arm.com>
++
++	PR target/81414
++	* config/aarch64/cortex-a57-fma-steering.c (analyze): Skip fmul/fmac
++	instructions if no du chain is found.
++
++2017-07-27  Jakub Jelinek  <jakub@redhat.com>
++
++	PR tree-optimization/81555
++	PR tree-optimization/81556
++	* tree-ssa-reassoc.c (rewrite_expr_tree): Add NEXT_CHANGED argument,
++	if true, force CHANGED for the recursive invocation.
++	(reassociate_bb): Remember original length of ops array, pass
++	len != orig_len as NEXT_CHANGED in rewrite_expr_tree call.
++
++2017-07-26  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline r235874
++	2016-05-04  Alan Modra  <amodra@gmail.com>
++
++	* config/rs6000/rs6000.c (rs6000_elf_output_toc_section_asm_op):
++	Align .toc.
++
++2017-07-26  Georg-Johann Lay  <avr@gjlay.de>
++
++	Backport from 2016-06-15 trunk r237486.
++	Backport from 2017-07-12 trunk r250156.
++
++	PR target/79883
++	PR target/67353
++	* config/avr/avr.c (avr_set_current_function): Warn misspelled ISR
++	only if -Wmisspelled-isr is on.  In diagnostic messages: Quote
++	keywords and (parts of) identifiers.
++	[WITH_AVRLIBC]: Warn functions named "ISR", "SIGNAL" or "INTERUPT".
++	* doc/invoke.texi (AVR Options) <-Wmisspelled-isr>: Decument.
++
++2017-07-26  Georg-Johann Lay  <avr@gjlay.de>
++
++	Backport from 2017-07-05 trunk r249995.
++
++	PR target/81305
++	* config/avr/avr.c (avr_out_movhi_mr_r_xmega) [CONSTANT_ADDRESS_P]:
++	Don't depend on "optimize > 0".
++	(out_movhi_r_mr, out_movqi_mr_r): Same.
++	(out_movhi_mr_r, out_movqi_r_mr): Same.
++	(avr_address_cost) [CONSTANT_ADDRESS_P]: Don't depend cost for
++	io_address_operand on "optimize > 0".
++
++2017-07-26  Georg-Johann Lay  <avr@gjlay.de>
++
++	Backport from 2017-07-12 trunk r250151.
++
++	PR target/81407
++	* config/avr/avr.c (avr_encode_section_info)
++	[progmem && !TREE_READONLY]: Error if progmem object needs
++	constructing.
++
++2017-07-26  Georg-Johann Lay  <avr@gjlay.de>
++
++	Backport from 2017-07-26 gcc-7-branch r250562.
++
++	PR 81487
++	* hsa-brig.c (brig_init): Use xasprintf instead of asprintf.
++	* tree-ssa-structalias.c (alias_get_name): Same.
++
++2017-07-25  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2016-07-14  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR tree-optimization/81162
++	* gimple-ssa-strength-reduction.c (replace_mult_candidate): Don't
++	replace a negate with an add.
++
++2017-07-25  Georg-Johann Lay  <avr@gjlay.de>
++
++	Backport from trunk r247719.
++
++	2017-05-06  Richard Sandiford  <richard.sandiford@linaro.org>
++
++	PR rtl-optimization/75964
++	* simplify-rtx.c (simplify_const_relational_operation): Remove
++	invalid handling of comparisons of integer ABS.
++
++2017-07-24  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/80569
++	* config/i386/i386.c (ix86_option_override_internal): Disable
++	BMI, BMI2 and TBM instructions for -m16.
++
++2017-07-18  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/81471
++	* config/i386/i386.md (rorx_immediate_operand): New mode attribute.
++	(*bmi2_rorx<mode>3_1): Use rorx_immediate_operand as
++	operand 2 predicate.
++	(*bmi2_rorxsi3_1_zext): Use const_0_to_31_operand as
++	operand 2 predicate.
++	(ror,rol -> rorx splitters): Use const_int_operand as
++	operand 2 predicate.
++
++2017-07-17  Georg-Johann Lay  <avr@gjlay.de>
++
++	Backport from 2017-07-17 trunk r250258.
++
++	PR 80929
++	* config/avr/avr.c (avr_mul_highpart_cost): New static function.
++	(avr_rtx_costs_1) [TRUNCATE]: Use it to compute mul_highpart cost.
++	[LSHIFTRT, outer_code = TRUNCATE]: Same.
++
++2017-07-14  Kelvin Nilsen  <kelvin@gcc.gnu.org>
++
++	Backports from trunk
++
++	2017-03-23  Kelvin Nilsen  <kelvin@gcc.gnu.org>
++	* config/rs6000/rs6000.c (rs6000_option_override_internal): Change
++	handling of certain combinations of target options, including the
++	combinations -mpower8-vector vs. -mno-vsx, -mpower8-vector vs.
++	-mno-power8-vector, and -mpower9_dform vs. -mno-power9-vector.
++
++	2017-03-27  Kelvin Nilsen  <kelvin@gcc.gnu.org>
++	PR target/80103
++	* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
++	special handling for target option conflicts between dform options
++	(-mpower9-dform, -mpower9-dform-vector, -mpower9-dform-scalar) and
++	-mno-direct-move.
++
++	2017-05-08  Kelvin Nilsen  <kelvin@gcc.gnu.org>
++	PR target/80101
++	* config/rs6000/power6.md: Replace store_data_bypass_p calls with
++	rs6000_store_data_bypass_p in seven define_bypass directives and
++	in several comments.
++	* config/rs6000/rs6000-protos.h: Add prototype for
++	rs6000_store_data_bypass_p function.
++	* config/rs6000/rs6000.c (rs6000_store_data_bypass_p): New
++	function implements slightly different (rs6000-specific) semantics
++	than store_data_bypass_p, returning false rather than aborting
++	with assertion error when arguments do not satisfy the
++	requirements of store data bypass.
++	(rs6000_adjust_cost): Replace six calls of store_data_bypass_p with
++	rs6000_store_data_bypass_p.
++
++2017-07-14  Uros Bizjak  <ubizjak@gmail.com>
++
++	Backport from mainline
++	2017-07-10  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/81375
++	* config/i386/i386.md (divsf3): Add TARGET_SSE to TARGET_SSE_MATH.
++	(rcpps): Ditto.
++	(*rsqrtsf2_sse): Ditto.
++	(rsqrtsf2): Ditto.
++	(div<mode>3): Macroize insn from divdf3 and divsf3
++	using MODEF mode iterator.
++
++	Backport from mainline
++	2017-07-04  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/81300
++	* config/i386/i386.md (setcc + movzbl/and to xor + setcc peepholes):
++	Require dead FLAGS_REG at the beginning of a peephole.
++
++2017-07-13  Tom de Vries  <tom@codesourcery.com>
++
++	backport from mainline:
++	PR tree-optimization/81192
++	2017-07-03  Tom de Vries  <tom@codesourcery.com>
++
++	* tree-ssa-tail-merge.c (same_succ_flush_bb): Handle
++	BB_SAME_SUCC (bb) == NULL.
++
++2017-07-06  Andrew Pinski  <apinski@cavium.com>
++
++	* config/aarch64/aarch64.c (aarch64_load_symref_appropriately):
++	Access the lower part of RTX appropriately.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+@@ -83,7 +1284,7 @@
+ 	Backport from mainline
+ 	2017-05-04  Prakhar Bahuguna  <prakhar.bahuguna@arm.com>
+ 
+-	* gcc/config/arm/arm-builtins.c (arm_init_builtins): Rename
++	* config/arm/arm-builtins.c (arm_init_builtins): Rename
+ 	__builtin_arm_ldfscr to __builtin_arm_get_fpscr, and rename
+ 	__builtin_arm_stfscr to __builtin_arm_set_fpscr.
+ 
+@@ -417,7 +1618,7 @@
+ 
+ 	PR target/80968
+ 	* config/sparc/sparc.c (sparc_flat_expand_epilogue): Don't
+-        emit frame blockage here.
++	emit frame blockage here.
+ 	(sparc_expand_epilogue): Do it here.
+ 	* config/sparc/sparc.md (return expander): Emit frame blockage
+ 	for alloca here too.
+@@ -4231,6 +5432,24 @@
+ 	* gimple-fold.c (fold_builtin_memory_op): Use
+ 	get_addr_base_and_unit_offset instead of get_ref_base_and_extent.
+ 
++2017-07-19  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Back port from trunk
++	2017-07-12  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	PR target/81193
++	* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): If GLIBC
++	provides the hardware capability bits, define the macro
++	__BUILTIN_CPU_SUPPORTS__.
++	* config/rs6000/rs6000.c (cpu_expand_builtin): Generate a warning
++	if GLIBC does not provide the hardware capability bits.  Add a
++	gcc_unreachable call if the built-in cpu function is neither
++	__builtin_cpu_is nor __builtin_cpu_supports.
++	* doc/extend.texi (PowerPC built-in functions): Document that
++	GLIBC 2.23 or newer is needed by __builtin_cpu_is and
++	__builtin_cpu_supports.  Document the macros defined by GCC if the
++	newer GLIBC is available.
++
+ 2016-07-18  Michael Meissner  <meissner@linux.vnet.ibm.com>
+ 
+ 	Back port from mainline
+Index: gcc/testsuite/opt55.ads
+===================================================================
+--- a/src/gcc/testsuite/opt55.ads	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/opt55.ads	(.../branches/gcc-6-branch)
+@@ -1,22 +0,0 @@
+-package Opt55 is
+-
+-   type Date is record
+-      D : Float;
+-   end record;
+-
+-   type Rec1 (Kind : Boolean := False) is record
+-      case Kind is
+-         when True => N : Natural;
+-         when False => null;
+-      end case;
+-   end record;
+-
+-   type Rec2 (D : Positive) is record
+-      R  : Rec1;
+-      D1 : Date;
+-      D2 : Date;
+-   end record;
+-
+-   function F (C : Rec2; B : Boolean) return Date;
+-
+-end Opt55;
+Index: gcc/testsuite/opt55.adb
+===================================================================
+--- a/src/gcc/testsuite/opt55.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/opt55.adb	(.../branches/gcc-6-branch)
+@@ -1,20 +0,0 @@
+--- { dg-do compile }
+--- { dg-options "-O" }
+-
+-package body Opt55 is
+-
+-   function Cond (B : Boolean; If_True, If_False : Date) return Date is
+-   begin
+-      if B then
+-         return If_True;
+-      else
+-         return If_False;
+-      end if;
+-   end;
+-
+-   function F (C : Rec2; B : Boolean) return Date is
+-   begin
+-      return Cond (B, C.D1, C.D2);
+-   end;
+-
+-end Opt55;
+Index: gcc/testsuite/gcc.target/powerpc/pr80103-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr80103-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr80103-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,16 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-options "-mpower9-dform-vector -mno-direct-move" } */
++/* { dg-excess-errors "expect error due to conflicting target options" } */
++/* Since the error message is not associated with a particular line
++   number, we cannot use the dg-error directive and cannot specify a
++   regexp to describe the expected error message.  The expected error
++   message is: "-mpower9-dform, -mpower9-dform-vector,
++                -mpower9-dform-scalar require -mdirect-move" */
++
++int a;
++void b (__attribute__ ((__vector_size__ (16))) char c)
++{
++  a = ((__attribute__ ((__vector_size__ (2 * sizeof (long)))) long) c)[0];
++}
+Index: gcc/testsuite/gcc.target/powerpc/pr81833-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr81833-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr81833-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,59 @@
++/* PR81833: This used to fail due to improper implementation of vec_msum.  */
++/* Test case relies on -mcpu=power7 or later.  Currently we don't have
++   machinery to express that, so we have two separate tests for -mcpu=power7
++   and -mcpu=power8 to catch 32-bit BE on P7 and 64-bit BE/LE on P8.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target p8vector_hw } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
++/* { dg-options "-mcpu=power8 -O2" } */
++
++#include <altivec.h>
++
++#define vec_u8  vector unsigned char
++#define vec_s8  vector signed char
++#define vec_u16 vector unsigned short
++#define vec_s16 vector signed short
++#define vec_u32 vector unsigned int
++#define vec_s32 vector signed int
++#define vec_f   vector float
++
++#define LOAD_ZERO const vec_u8 zerov = vec_splat_u8 (0)
++
++#define zero_u8v  (vec_u8)  zerov
++#define zero_s8v  (vec_s8)  zerov
++#define zero_u16v (vec_u16) zerov
++#define zero_s16v (vec_s16) zerov
++#define zero_u32v (vec_u32) zerov
++#define zero_s32v (vec_s32) zerov
++
++signed int __attribute__((noinline))
++scalarproduct_int16_vsx (const signed short *v1, const signed short *v2,
++			 int order)
++{
++  int i;
++  LOAD_ZERO;
++  register vec_s16 vec1;
++  register vec_s32 res = vec_splat_s32 (0), t;
++  signed int ires;
++
++  for (i = 0; i < order; i += 8) {
++    vec1 = vec_vsx_ld (0, v1);
++    t    = vec_msum (vec1, vec_vsx_ld (0, v2), zero_s32v);
++    res  = vec_sums (t, res);
++    v1  += 8;
++    v2  += 8;
++  }
++  res = vec_splat (res, 3);
++  vec_ste (res, 0, &ires);
++
++  return ires;
++}
++
++int main(void)
++{
++  const signed short test_vec[] = { 1, 1, 1, 1, 1, 1, 1, 1 };
++  if (scalarproduct_int16_vsx (test_vec, test_vec, 8) != 8)
++    __builtin_abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/powerpc/vec-setup-be-long.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vec-setup-be-long.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vec-setup-be-long.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,11 @@
++/* { dg-do run { target { powerpc64le*-*-linux* } } } */
++/* { dg-require-effective-target vsx_hw } */
++/* { dg-options "-O2 -mvsx -maltivec=be" } */
++
++/* Test various ways of creating vectors with 2 double words and accessing the
++   elements.  This test uses the long (on 64-bit systems) or long long datatype
++   (on 32-bit systems).
++
++   This test explicitly tests -maltivec=be to make sure things are correct.  */
++
++#include "vec-setup.h"
+Index: gcc/testsuite/gcc.target/powerpc/pr80210-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr80210-2.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr80210-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,11 @@
++/* Test for ICE arising from GCC target pragma.  */
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++#pragma GCC target "no-powerpc-gpopt"
++double
++foo (double a)
++{
++  return __builtin_sqrt (a);
++}
++/* { dg-final { scan-assembler-not "fsqrt" } } */
+Index: gcc/testsuite/gcc.target/powerpc/pr81833-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr81833-2.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr81833-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,59 @@
++/* PR81833: This used to fail due to improper implementation of vec_msum.  */
++/* Test case relies on -mcpu=power7 or later.  Currently we don't have
++   machinery to express that, so we have two separate tests for -mcpu=power7
++   and -mcpu=power8 to catch 32-bit BE on P7 and 64-bit BE/LE on P8.  */
++
++/* { dg-do run } */
++/* { dg-require-effective-target vsx_hw } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
++/* { dg-options "-mcpu=power7 -O2" } */
++
++#include <altivec.h>
++
++#define vec_u8  vector unsigned char
++#define vec_s8  vector signed char
++#define vec_u16 vector unsigned short
++#define vec_s16 vector signed short
++#define vec_u32 vector unsigned int
++#define vec_s32 vector signed int
++#define vec_f   vector float
++
++#define LOAD_ZERO const vec_u8 zerov = vec_splat_u8 (0)
++
++#define zero_u8v  (vec_u8)  zerov
++#define zero_s8v  (vec_s8)  zerov
++#define zero_u16v (vec_u16) zerov
++#define zero_s16v (vec_s16) zerov
++#define zero_u32v (vec_u32) zerov
++#define zero_s32v (vec_s32) zerov
++
++signed int __attribute__((noinline))
++scalarproduct_int16_vsx (const signed short *v1, const signed short *v2,
++			 int order)
++{
++  int i;
++  LOAD_ZERO;
++  register vec_s16 vec1;
++  register vec_s32 res = vec_splat_s32 (0), t;
++  signed int ires;
++
++  for (i = 0; i < order; i += 8) {
++    vec1 = vec_vsx_ld (0, v1);
++    t    = vec_msum (vec1, vec_vsx_ld (0, v2), zero_s32v);
++    res  = vec_sums (t, res);
++    v1  += 8;
++    v2  += 8;
++  }
++  res = vec_splat (res, 3);
++  vec_ste (res, 0, &ires);
++
++  return ires;
++}
++
++int main(void)
++{
++  const signed short test_vec[] = { 1, 1, 1, 1, 1, 1, 1, 1 };
++  if (scalarproduct_int16_vsx (test_vec, test_vec, 8) != 8)
++    __builtin_abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/powerpc/pr82112.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr82112.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr82112.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,16 @@
++/* PR target/82112 */
++/* { dg-do compile } */
++/* { dg-require-effective-target powerpc_altivec_ok } */
++/* { dg-options "-maltivec -std=gnu90" } */
++
++#include <altivec.h>
++
++struct __attribute__((aligned (16))) S { unsigned char c[64]; } bar (void);
++vector unsigned char v;
++
++void
++foo (void)
++{
++  vec_ld (0, bar ().c);	/* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
++  vec_st (v, 0, bar ().c);	/* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
++}
+Index: gcc/testsuite/gcc.target/powerpc/vec-setup.h
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vec-setup.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vec-setup.h	(.../branches/gcc-6-branch)
+@@ -0,0 +1,366 @@
++#include <altivec.h>
++
++/* Test various ways of creating vectors with 2 double words and accessing the
++   elements.  This include files supports:
++
++	 testing double
++	 testing long on 64-bit systems
++	 testing long long on 32-bit systems.
++
++   The endian support is:
++
++	big endian
++	little endian with little endian element ordering
++	little endian with big endian element ordering.  */
++
++#ifdef DEBUG
++#include <stdio.h>
++#define DEBUG0(STR)		fputs (STR, stdout)
++#define DEBUG2(STR,A,B)		printf (STR, A, B)
++
++static int errors = 0;
++
++#else
++#include <stdlib.h>
++#define DEBUG0(STR)
++#define DEBUG2(STR,A,B)
++#endif
++
++#if defined(DO_DOUBLE)
++#define TYPE	double
++#define STYPE	"double"
++#define ZERO	0.0
++#define ONE	1.0
++#define TWO	2.0
++#define THREE	3.0
++#define FOUR	4.0
++#define FIVE	5.0
++#define SIX	6.0
++#define FMT	"g"
++
++#elif defined(_ARCH_PPC64)
++#define TYPE	long
++#define STYPE	"long"
++#define ZERO	0L
++#define ONE	1L
++#define TWO	2L
++#define THREE	3L
++#define FOUR	4L
++#define FIVE	5L
++#define SIX	6L
++#define FMT	"ld"
++
++#else
++#define TYPE	long long
++#define STYPE	"long long"
++#define ZERO	0LL
++#define ONE	1LL
++#define TWO	2LL
++#define THREE	3LL
++#define FOUR	4LL
++#define FIVE	5LL
++#define SIX	6LL
++#define FMT	"lld"
++#endif
++
++/* Macros to order the left/right values correctly.  Note, -maltivec=be does
++   not change the order for static initializations, so we have to handle it
++   specially.  */
++
++#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
++#define INIT_ORDER(A, B)	(TYPE) A, (TYPE) B
++#define ELEMENT_ORDER(A, B)	(TYPE) A, (TYPE) B
++#define ENDIAN			"-mbig"
++
++#elif __VEC_ELEMENT_REG_ORDER__ == __ORDER_BIG_ENDIAN__
++#define NO_ARRAY
++#define INIT_ORDER(A, B)	(TYPE) B, (TYPE) A
++#define ELEMENT_ORDER(A, B)	(TYPE) A, (TYPE) B
++#define ENDIAN			"-mlittle -maltivec=be"
++
++#else
++#define INIT_ORDER(A, B)	(TYPE) B, (TYPE) A
++#define ELEMENT_ORDER(A, B)	(TYPE) B, (TYPE) A
++#define ENDIAN			"-mlittle"
++#endif
++
++static volatile TYPE		five	= FIVE;
++static volatile TYPE		six	= SIX;
++static volatile vector TYPE	s_v12 = { ONE,   TWO };
++static volatile vector TYPE	g_v34 = { THREE, FOUR };
++
++
++__attribute__((__noinline__))
++static void
++vector_check (vector TYPE v, TYPE expect_hi, TYPE expect_lo)
++{
++  TYPE actual_hi, actual_lo;
++#ifdef DEBUG
++  const char *pass_fail;
++#endif
++
++  __asm__ ("xxlor %x0,%x1,%x1"		: "=&wa" (actual_hi) : "wa" (v));
++  __asm__ ("xxpermdi %x0,%x1,%x1,3"	: "=&wa" (actual_lo) : "wa" (v));
++
++#ifdef DEBUG
++  if ((actual_hi == expect_hi) && (actual_lo == expect_lo))
++    pass_fail = ", pass";
++  else
++    {
++      pass_fail = ", fail";
++      errors++;
++    }
++
++  printf ("Expected %" FMT ", %" FMT ", got %" FMT ", %" FMT "%s\n",
++	  expect_hi, expect_lo,
++	  actual_hi, actual_lo,
++	  pass_fail);
++#else
++  if ((actual_hi != expect_hi) || (actual_lo != expect_lo))
++    abort ();
++#endif
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++combine (TYPE op0, TYPE op1)
++{
++  return (vector TYPE) { op0, op1 };
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++combine_insert (TYPE op0, TYPE op1)
++{
++  vector TYPE ret = (vector TYPE) { ZERO, ZERO };
++  ret = vec_insert (op0, ret, 0);
++  ret = vec_insert (op1, ret, 1);
++  return ret;
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++concat_extract_00 (vector TYPE a, vector TYPE b)
++{
++  return (vector TYPE) { vec_extract (a, 0), vec_extract (b, 0) };
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++concat_extract_01 (vector TYPE a, vector TYPE b)
++{
++  return (vector TYPE) { vec_extract (a, 0), vec_extract (b, 1) };
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++concat_extract_10 (vector TYPE a, vector TYPE b)
++{
++  return (vector TYPE) { vec_extract (a, 1), vec_extract (b, 0) };
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++concat_extract_11 (vector TYPE a, vector TYPE b)
++{
++  return (vector TYPE) { vec_extract (a, 1), vec_extract (b, 1) };
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++concat_extract2_0s (vector TYPE a, TYPE b)
++{
++  return (vector TYPE) { vec_extract (a, 0), b };
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++concat_extract2_1s (vector TYPE a, TYPE b)
++{
++  return (vector TYPE) { vec_extract (a, 1), b };
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++concat_extract2_s0 (TYPE a, vector TYPE b)
++{
++  return (vector TYPE) { a, vec_extract (b, 0) };
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++concat_extract2_s1 (TYPE a, vector TYPE b)
++{
++  return (vector TYPE) { a, vec_extract (b, 1) };
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++concat_extract_nn (vector TYPE a, vector TYPE b, size_t i, size_t j)
++{
++  return (vector TYPE) { vec_extract (a, i), vec_extract (b, j) };
++}
++
++#ifndef NO_ARRAY
++__attribute__((__noinline__))
++static vector TYPE
++array_0 (vector TYPE v, TYPE a)
++{
++  v[0] = a;
++  return v;
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++array_1 (vector TYPE v, TYPE a)
++{
++  v[1] = a;
++  return v;
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++array_01 (vector TYPE v, TYPE a, TYPE b)
++{
++  v[0] = a;
++  v[1] = b;
++  return v;
++}
++
++__attribute__((__noinline__))
++static vector TYPE
++array_01b (TYPE a, TYPE b)
++{
++  vector TYPE v = (vector TYPE) { 0, 0 };
++  v[0] = a;
++  v[1] = b;
++  return v;
++}
++#endif
++
++int
++main (void)
++{
++  vector TYPE a = (vector TYPE) { ONE,   TWO  };
++  vector TYPE b = (vector TYPE) { THREE, FOUR };
++  size_t i, j;
++
++#ifndef NO_ARRAY
++  vector TYPE z = (vector TYPE) { ZERO,  ZERO };
++#endif
++
++  DEBUG2 ("Endian: %s, type: %s\n", ENDIAN, STYPE);
++  DEBUG0 ("\nStatic/global initialization\n");
++  vector_check (s_v12, INIT_ORDER (1, 2));
++  vector_check (g_v34, INIT_ORDER (3, 4));
++
++  DEBUG0 ("\nVector via constant runtime intiialization\n");
++  vector_check (a, INIT_ORDER (1, 2));
++  vector_check (b, INIT_ORDER (3, 4));
++
++  DEBUG0 ("\nCombine scalars using vector initialization\n");
++  vector_check (combine (1, 2), INIT_ORDER (1, 2));
++  vector_check (combine (3, 4), INIT_ORDER (3, 4));
++
++  DEBUG0 ("\nSetup with vec_insert\n");
++  a = combine_insert (1, 2);
++  b = combine_insert (3, 4);
++  vector_check (a, ELEMENT_ORDER (1, 2));
++  vector_check (b, ELEMENT_ORDER (3, 4));
++
++#ifndef NO_ARRAY
++  DEBUG0 ("\nTesting array syntax\n");
++  vector_check (array_0   (a, FIVE),      ELEMENT_ORDER (5, 2));
++  vector_check (array_1   (b, SIX),       ELEMENT_ORDER (3, 6));
++  vector_check (array_01  (z, FIVE, SIX), ELEMENT_ORDER (5, 6));
++  vector_check (array_01b (FIVE, SIX),    ELEMENT_ORDER (5, 6));
++
++  vector_check (array_0   (a, five),      ELEMENT_ORDER (5, 2));
++  vector_check (array_1   (b, six),       ELEMENT_ORDER (3, 6));
++  vector_check (array_01  (z, five, six), ELEMENT_ORDER (5, 6));
++  vector_check (array_01b (five, six),    ELEMENT_ORDER (5, 6));
++#else
++  DEBUG0 ("\nSkipping array syntax on -maltivec=be\n");
++#endif
++
++  DEBUG0 ("\nTesting concat and extract\n");
++  vector_check (concat_extract_00 (a, b), INIT_ORDER (1, 3));
++  vector_check (concat_extract_01 (a, b), INIT_ORDER (1, 4));
++  vector_check (concat_extract_10 (a, b), INIT_ORDER (2, 3));
++  vector_check (concat_extract_11 (a, b), INIT_ORDER (2, 4));
++
++  DEBUG0 ("\nTesting concat and extract #2\n");
++  vector_check (concat_extract2_0s (a, FIVE), INIT_ORDER (1, 5));
++  vector_check (concat_extract2_1s (a, FIVE), INIT_ORDER (2, 5));
++  vector_check (concat_extract2_s0 (SIX, a),  INIT_ORDER (6, 1));
++  vector_check (concat_extract2_s1 (SIX, a),  INIT_ORDER (6, 2));
++
++  DEBUG0 ("\nTesting variable concat and extract\n");
++  for (i = 0; i < 2; i++)
++    {
++      for (j = 0; j < 2; j++)
++	{
++	  static struct {
++	    TYPE hi;
++	    TYPE lo;
++	  } hilo[2][2] =
++	      { { { ONE, THREE }, { ONE, FOUR } },
++		{ { TWO, THREE }, { TWO, FOUR } } };
++
++	  vector_check (concat_extract_nn (a, b, i, j),
++			INIT_ORDER (hilo[i][j].hi, hilo[i][j].lo));
++	}
++    }
++
++  DEBUG0 ("\nTesting separate function\n");
++  vector_check (combine (vec_extract (a, 0), vec_extract (b, 0)),
++		INIT_ORDER (1, 3));
++
++  vector_check (combine (vec_extract (a, 0), vec_extract (b, 1)),
++		INIT_ORDER (1, 4));
++
++  vector_check (combine (vec_extract (a, 1), vec_extract (b, 0)),
++		INIT_ORDER (2, 3));
++
++  vector_check (combine (vec_extract (a, 1), vec_extract (b, 1)),
++		INIT_ORDER (2, 4));
++
++  vector_check (combine_insert (vec_extract (a, 0), vec_extract (b, 0)),
++		ELEMENT_ORDER (1, 3));
++
++  vector_check (combine_insert (vec_extract (a, 0), vec_extract (b, 1)),
++		ELEMENT_ORDER (1, 4));
++
++  vector_check (combine_insert (vec_extract (a, 1), vec_extract (b, 0)),
++		ELEMENT_ORDER (2, 3));
++
++  vector_check (combine_insert (vec_extract (a, 1), vec_extract (b, 1)),
++		ELEMENT_ORDER (2, 4));
++
++
++#if defined(DO_DOUBLE)
++  DEBUG0 ("\nTesting explicit 2df concat\n");
++  vector_check (__builtin_vsx_concat_2df (FIVE, SIX), INIT_ORDER (5, 6));
++  vector_check (__builtin_vsx_concat_2df (five, six), INIT_ORDER (5, 6));
++
++#elif defined(_ARCH_PPC64)
++  DEBUG0 ("\nTesting explicit 2di concat\n");
++  vector_check (__builtin_vsx_concat_2di (FIVE, SIX), INIT_ORDER (5, 6));
++  vector_check (__builtin_vsx_concat_2di (five, six), INIT_ORDER (5, 6));
++
++#else
++  DEBUG0 ("\nSkip explicit 2di concat on 32-bit\n");
++#endif
++
++#ifdef DEBUG
++  if (errors)
++    printf ("\n%d error%s were found", errors, (errors == 1) ? "" : "s");
++  else
++    printf ("\nNo errors were found.\n");
++
++  return errors;
++
++#else
++  return 0;
++#endif
++}
+Index: gcc/testsuite/gcc.target/powerpc/vec-setup-be-double.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vec-setup-be-double.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vec-setup-be-double.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,12 @@
++/* { dg-do run { target { powerpc*-*-linux* } } } */
++/* { dg-require-effective-target vsx_hw } */
++/* { dg-options "-O2 -mvsx" } */
++
++/* Test various ways of creating vectors with 2 double words and accessing the
++   elements.  This test uses the double datatype.
++
++   This test explicitly tests -maltivec=be to make sure things are correct.  */
++
++#define DO_DOUBLE
++
++#include "vec-setup.h"
+Index: gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c	(.../branches/gcc-6-branch)
+@@ -4,6 +4,11 @@
+ void
+ use_cpu_is_builtins (unsigned int *p)
+ {
++  /* If GCC was configured to use an old GLIBC (before 2.23), the
++     __builtin_cpu_is and __builtin_cpu_supports built-in functions return 0,
++     and the compiler issues a warning that you need a newer glibc to use them.
++     Use #ifdef to avoid the warning.  */
++#ifdef __BUILTIN_CPU_SUPPORTS__
+   p[0] = __builtin_cpu_is ("power9");
+   p[1] = __builtin_cpu_is ("power8");
+   p[2] = __builtin_cpu_is ("power7");
+@@ -19,11 +24,15 @@
+   p[12] = __builtin_cpu_is ("ppc440");
+   p[13] = __builtin_cpu_is ("ppc405");
+   p[14] = __builtin_cpu_is ("ppc-cell-be");
++#else
++  p[0] = 0;
++#endif
+ }
+ 
+ void
+ use_cpu_supports_builtins (unsigned int *p)
+ {
++#ifdef __BUILTIN_CPU_SUPPORTS__
+   p[0] = __builtin_cpu_supports ("4xxmac");
+   p[1] = __builtin_cpu_supports ("altivec");
+   p[2] = __builtin_cpu_supports ("arch_2_05");
+@@ -62,4 +71,10 @@
+   p[35] = __builtin_cpu_supports ("ucache");
+   p[36] = __builtin_cpu_supports ("vcrypto");
+   p[37] = __builtin_cpu_supports ("vsx");
++  p[38] = __builtin_cpu_supports ("darn");
++  p[39] = __builtin_cpu_supports ("scv");
++  p[40] = __builtin_cpu_supports ("htm-no-suspend");
++#else
++  p[0] = 0;
++#endif
+ }
+Index: gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,34 @@
++/* { dg-do run { target { powerpc64le-*-* } } } */
++/* { dg-require-effective-target powerpc_p8vector_ok } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
++/* { dg-options "-mcpu=power8 -O2 " } */
++
++typedef __attribute__ ((__aligned__ (8))) unsigned long long __m64;
++typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
++
++/* PR84033.  Extracted from xmmintrin.h but with a pointer param to
++   allow swaps to happen when not inline.  */
++int __attribute__ ((__noinline__))
++_mm_movemask_ps (__m128 *__A)
++{
++  __vector __m64 result;
++  static const __vector unsigned int perm_mask =
++    {
++      0x00204060, 0x80808080, 0x80808080, 0x80808080
++    };
++
++  result = (__vector __m64)
++    __builtin_vec_vbpermq ((__vector unsigned char) (*__A),
++			   (__vector unsigned char) perm_mask);
++  return result[1];
++}
++
++int
++main (void)
++{
++  union { unsigned int i[4]; __m128 m; } x
++    = { 0x80000000, 0x80000000, 0x7fffffff, 0x7fffffff };
++  if (_mm_movemask_ps (&x.m) != 3)
++    __builtin_abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/powerpc/vsx-extract-6.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-extract-6.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-extract-6.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,25 @@
++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } } */
++/* { dg-require-effective-target powerpc_vsx_ok } */
++/* { dg-options "-O2 -mvsx" } */
++
++vector unsigned long
++test_vpasted (vector unsigned long high, vector unsigned long low)
++{
++  vector unsigned long res;
++  res[1] = high[1];
++  res[0] = low[0];
++  return res;
++}
++
++/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1    } } */
++/* { dg-final { scan-assembler-not   {\mvspltisw\M}      } } */
++/* { dg-final { scan-assembler-not   {\mxxlor\M}         } } */
++/* { dg-final { scan-assembler-not   {\mxxlxor\M}        } } */
++/* { dg-final { scan-assembler-not   {\mxxspltib\M}      } } */
++/* { dg-final { scan-assembler-not   {\mlxvx?\M}         } } */
++/* { dg-final { scan-assembler-not   {\mlxv[dw][24]x\M}  } } */
++/* { dg-final { scan-assembler-not   {\mlvx\M}           } } */
++/* { dg-final { scan-assembler-not   {\mstxvx?\M}        } } */
++/* { dg-final { scan-assembler-not   {\mstxv[dw][24]x\M} } } */
++/* { dg-final { scan-assembler-not   {\mstvx\M}          } } */
+Index: gcc/testsuite/gcc.target/powerpc/pr83862.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr83862.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr83862.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,34 @@
++/* PR target/83862.c */
++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
++/* { dg-require-effective-target ppc_float128_sw } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-options "-mpower9-vector -O2 -mfloat128" } */
++
++/* On little endian systems, optimizing signbit of IEEE 128-bit values from
++   memory could abort if the memory address was indexed (reg+reg).  The
++   optimization is only on 64-bit machines with direct move.
++
++   Compile with -g -O2 -mabi=ieeelongdouble -Wno-psabi.  */
++
++#ifndef TYPE
++#define TYPE __float128
++#endif
++
++int sbr (TYPE a) { return __builtin_signbit (a); }
++int sbm (TYPE *a) { return __builtin_signbit (*a); }
++int sbo (TYPE *a) { return __builtin_signbit (a[4]); }
++int sbi (TYPE *a, unsigned long n) { return __builtin_signbit (a[n]); }
++void sbs (int *p, TYPE a) { *p = __builtin_signbit (a); }
++
++/* On big endian systems, this will generate 2 LDs and 1 LDX, while on
++   little endian systems, this will generate 3 LDs and an ADD.  */
++
++/* { dg-final { scan-assembler-times {\mldx?\M}    3 } } */
++/* { dg-final { scan-assembler-times {\mmfvsrd\M}  2 } } */
++/* { dg-final { scan-assembler-times {\msrdi\M}    5 } } */
++/* { dg-final { scan-assembler-not   {\mmfvsrld\M}   } } */
++/* { dg-final { scan-assembler-not   {\mstxvx?\M}    } } */
++/* { dg-final { scan-assembler-not   {\mstxvw4x\M}   } } */
++/* { dg-final { scan-assembler-not   {\mstxvd2x\M}   } } */
++/* { dg-final { scan-assembler-not   {\mstvx\M}      } } */
++
+Index: gcc/testsuite/gcc.target/powerpc/vsx-extract-7.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-extract-7.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-extract-7.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,25 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } } */
++/* { dg-require-effective-target powerpc_vsx_ok } */
++/* { dg-options "-O2 -mvsx" } */
++
++vector double
++test_vpasted (vector double high, vector double low)
++{
++  vector double res;
++  res[1] = high[1];
++  res[0] = low[0];
++  return res;
++}
++
++/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1    } } */
++/* { dg-final { scan-assembler-not   {\mvspltisw\M}      } } */
++/* { dg-final { scan-assembler-not   {\mxxlor\M}         } } */
++/* { dg-final { scan-assembler-not   {\mxxlxor\M}        } } */
++/* { dg-final { scan-assembler-not   {\mxxspltib\M}      } } */
++/* { dg-final { scan-assembler-not   {\mlxvx?\M}         } } */
++/* { dg-final { scan-assembler-not   {\mlxv[dw][24]x\M}  } } */
++/* { dg-final { scan-assembler-not   {\mlvx\M}           } } */
++/* { dg-final { scan-assembler-not   {\mstxvx?\M}        } } */
++/* { dg-final { scan-assembler-not   {\mstxv[dw][24]x\M} } } */
++/* { dg-final { scan-assembler-not   {\mstvx\M}          } } */
+Index: gcc/testsuite/gcc.target/powerpc/pr83399.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr83399.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr83399.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,15 @@
++/* PR target/83399 */
++/* { dg-do compile } */
++/* { dg-require-effective-target powerpc_vsx_ok } */
++/* { dg-options "-O1 -mabi=elfv2 -mlittle -mvsx" } */
++
++typedef __attribute__((altivec(vector__))) int v4si_t;
++int
++foo (void)
++{
++  v4si_t a, u, v, y;
++  u = __builtin_altivec_lvx (32, ((void *) &a) - 32);
++  v = __builtin_altivec_lvx (64, ((void *) &a) - 32);
++  y = u + v;
++  return y[0];
++}
+Index: gcc/testsuite/gcc.target/powerpc/pr80101-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr80101-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr80101-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,22 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */
++/* { dg-require-effective-target dfp_hw } */
++/* { dg-options "-mcpu=power6 -mno-sched-epilog -Ofast" } */
++
++/* Prior to resolving PR 80101, this test case resulted in an internal
++   compiler error.  The role of this test program is to assure that
++   dejagnu's "test for excess errors" does not find any.  */
++
++int b;
++
++void e ();
++
++int c ()
++{
++  struct
++  {
++    int a[b];
++  } d;
++  if (d.a[0])
++    e ();
++}
+Index: gcc/testsuite/gcc.target/powerpc/p9-options-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/p9-options-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/p9-options-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,28 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-options "-mcpu=power9 -mno-power9-vector" } */
++
++#include <altivec.h>
++
++/* This program's "test for excess errors" demonstrates that combining
++   the target options -mcpu=power9 and -mno-power9-vector does not
++   result in an error.  A previous version of the compiler aborted
++   with the error message:
++
++      "power9-dform requires power9-vector."
++
++   when these two options were used in combination.
++
++   The newer version of the compiler, instead, automatically disables
++   power9-dform when the -mno-power9-vector command-line option is
++   specified.  */
++int
++test_any_equal (vector bool char *arg1_p, vector bool char *arg2_p)
++{
++  vector bool char arg_1 = *arg1_p;
++  vector bool char arg_2 = *arg2_p;
++
++  return vec_any_eq (arg_1, arg_2);
++}
++
+Index: gcc/testsuite/gcc.target/powerpc/pr83677.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr83677.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr83677.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,166 @@
++/* { dg-do run { target { powerpc*-*-* && { lp64 && p9vector_hw } } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-options "-mcpu=power9 -O2 " } */
++
++/* PR83677: This test case used to fail due to mis-generation of the
++   xxpermr instruction.  It requires inlining to create enough register
++   pressure that we generate xxpermr rather than vpermr.  */
++
++#include <altivec.h>
++
++void v_expand_u8(vector unsigned char* a, vector unsigned short* b0, vector unsigned short* b1)
++{
++  *b0 = (vector unsigned short)vec_mergeh(*a, vec_splats((unsigned char)0));
++  *b1 = (vector unsigned short)vec_mergel(*a, vec_splats((unsigned char)0));
++}
++
++void v_expand_u16(vector unsigned short* a, vector unsigned int* b0, vector unsigned int* b1)
++{
++    *b0 = (vector unsigned int)vec_mergeh(*a, vec_splats((unsigned short)0));
++    *b1 = (vector unsigned int)vec_mergel(*a, vec_splats((unsigned short)0));
++}
++
++void v_load_deinterleave_u8(unsigned char *ptr, vector unsigned char* a, vector unsigned char* b, vector unsigned char* c)
++{
++    vector unsigned char v1 = vec_xl( 0, ptr);
++    vector unsigned char v2 = vec_xl(16, ptr);
++    vector unsigned char v3 = vec_xl(32, ptr);
++
++    static const vector unsigned char a12_perm = {0, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 0, 0, 0, 0, 0};
++    static const vector unsigned char a123_perm = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 17, 20, 23, 26, 29};
++    *a = vec_perm(vec_perm(v1, v2, a12_perm), v3, a123_perm);
++
++    static const vector unsigned char b12_perm = {1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 0, 0, 0, 0, 0};
++    static const vector unsigned char b123_perm = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 18, 21, 24, 27, 30};
++    *b = vec_perm(vec_perm(v1, v2, b12_perm), v3, b123_perm);
++
++    static const vector unsigned char c12_perm = {2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 0, 0, 0, 0, 0, 0};
++    static const vector unsigned char c123_perm = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16, 19, 22, 25, 28, 31};
++    *c = vec_perm(vec_perm(v1, v2, c12_perm), v3, c123_perm);
++}
++
++void v_load_deinterleave_f32(float *ptr, vector float* a, vector float* b, vector float* c)
++{
++    vector float v1 = vec_xl( 0, ptr);
++    vector float v2 = vec_xl(16, ptr);
++    vector float v3 = vec_xl(32, ptr);
++
++    static const vector unsigned char flp = {0, 1, 2, 3, 12, 13, 14, 15, 16, 17, 18, 19, 28, 29, 30, 31};
++    *a = vec_perm(v1, vec_sld(v3, v2, 8), flp);
++
++    static const vector unsigned char flp2 = {28, 29, 30, 31, 0, 1, 2, 3, 12, 13, 14, 15, 16, 17, 18, 19};
++    *b = vec_perm(v2, vec_sld(v1, v3, 8), flp2);
++
++    *c = vec_perm(vec_sld(v2, v1, 8), v3, flp);
++}
++
++void v_store_interleave_f32(float *ptr, vector float a, vector float b, vector float c)
++{
++    vector float hbc = vec_mergeh(b, c);
++
++    static const vector unsigned char ahbc = {0, 1, 2, 3, 16, 17, 18, 19, 20, 21, 22, 23, 4, 5, 6, 7};
++    vec_xst(vec_perm(a, hbc, ahbc),  0, ptr);
++
++    vector float lab = vec_mergel(a, b);
++    vec_xst(vec_sld(lab, hbc, 8), 16, ptr);
++
++    static const vector unsigned char clab = {8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31, 12, 13, 14, 15};
++    vec_xst(vec_perm(c, lab, clab), 32, ptr);
++}
++
++vector float v_cvt_f32(vector unsigned int a)
++{
++    return (vector float)vec_ctf(a, 0);
++}
++
++void acc_simd_(const unsigned char* src, float* dst, const unsigned char* mask, int len)
++{
++    int x = 0;
++    const int cVectorWidth = 16;
++
++            for ( ; x <= len - cVectorWidth; x += cVectorWidth)
++            {
++                vector unsigned char v_mask = vec_xl(0, mask + x);
++                v_mask = (vector unsigned char)vec_cmpeq(vec_splats((unsigned char)0), v_mask);
++                v_mask = (vector unsigned char)vec_nor(v_mask, v_mask);
++                vector unsigned char v_src0, v_src1, v_src2;
++                v_load_deinterleave_u8((unsigned char *)(src + (x * 3)), &v_src0, &v_src1, &v_src2);
++                v_src0 = v_src0 & v_mask;
++                v_src1 = v_src1 & v_mask;
++                v_src2 = v_src2 & v_mask;
++
++                /* expand 16 uchar to 4 vectors which contains 4 uint */
++                vector unsigned short v_src00, v_src01, v_src10, v_src11, v_src20, v_src21;
++                v_expand_u8(&v_src0, &v_src00, &v_src01);
++                v_expand_u8(&v_src1, &v_src10, &v_src11);
++                v_expand_u8(&v_src2, &v_src20, &v_src21);
++                vector unsigned int v_src000, v_src001, v_src010, v_src011;
++                vector unsigned int v_src100, v_src101, v_src110, v_src111;
++                vector unsigned int v_src200, v_src201, v_src210, v_src211;
++                v_expand_u16(&v_src00, &v_src000, &v_src001);
++                v_expand_u16(&v_src01, &v_src010, &v_src011);
++                v_expand_u16(&v_src10, &v_src100, &v_src101);
++                v_expand_u16(&v_src11, &v_src110, &v_src111);
++                v_expand_u16(&v_src20, &v_src200, &v_src201);
++                v_expand_u16(&v_src21, &v_src210, &v_src211);
++
++                vector float v_dst000, v_dst001, v_dst010, v_dst011;
++                vector float v_dst100, v_dst101, v_dst110, v_dst111;
++                vector float v_dst200, v_dst201, v_dst210, v_dst211;
++                v_load_deinterleave_f32(dst + (x * 3),        &v_dst000, &v_dst100, &v_dst200);
++                v_load_deinterleave_f32(dst + ((x + 4) * 3),  &v_dst001, &v_dst101, &v_dst201);
++                v_load_deinterleave_f32(dst + ((x + 8) * 3),  &v_dst010, &v_dst110, &v_dst210);
++                v_load_deinterleave_f32(dst + ((x + 12) * 3), &v_dst011, &v_dst111, &v_dst211);
++
++                v_store_interleave_f32(dst + (x * 3),        vec_add(v_dst000, v_cvt_f32(v_src000)), vec_add(v_dst100, v_cvt_f32(v_src100)), vec_add(v_dst200, v_cvt_f32(v_src200)));
++                v_store_interleave_f32(dst + ((x + 4) * 3),  vec_add(v_dst001, v_cvt_f32(v_src001)), vec_add(v_dst101, v_cvt_f32(v_src101)), vec_add(v_dst201, v_cvt_f32(v_src201)));
++                v_store_interleave_f32(dst + ((x + 8) * 3),  vec_add(v_dst010, v_cvt_f32(v_src010)), vec_add(v_dst110, v_cvt_f32(v_src110)), vec_add(v_dst210, v_cvt_f32(v_src210)));
++                v_store_interleave_f32(dst + ((x + 12) * 3), vec_add(v_dst011, v_cvt_f32(v_src011)), vec_add(v_dst111, v_cvt_f32(v_src111)), vec_add(v_dst211, v_cvt_f32(v_src211)));
++            }
++    return;
++}
++
++void acc_(const unsigned char* src, float* dst, const unsigned char* mask, int len)
++{
++    int x = 0;
++    src += (x * 3);
++    dst += (x * 3);
++    for( ; x < len; x++, src += 3, dst += 3 )
++    {
++        if( mask[x] ) /* if mask, R/G/B dst[] += src[] */
++        {
++            for( int k = 0; k < 3; k++ )
++            {
++                dst[k] += src[k];
++            }
++        }
++    }
++    return;
++}
++
++#define N 16
++
++int main(int argc, char *argv[])
++{
++    unsigned char __attribute__ ((aligned (16) )) mask[] = {0, 0, 0, 0,  0, 0, 0, 0,  0, 1, 0, 0,  1, 0, 0, 1};
++    unsigned char __attribute__ ((aligned (16) )) src[3*N];
++    float __attribute__ ((aligned (16) )) dst[3*N];
++    float __attribute__ ((aligned (16) )) exp[3*N];
++
++    int i;
++
++    /* initialize src and dst */
++    for (i=0; i<3*N; i++) src[i] = (unsigned char)(i*3);
++    for (i=0; i<3*N; i++) {dst[i] = i * 1.0f; exp[i] = dst[i];}
++
++    acc_(src, exp, mask, N);
++    acc_simd_(src, dst, mask, N);
++
++    for (i=0; i<N; i++)
++    {
++        if ((dst[3*i] != exp[3*i]) || (dst[3*i+1] != exp[3*i+1]) || (dst[3*i+2] != exp[3*i+2]))
++	  __builtin_abort ();
++    }
++
++    return 0;
++}
+Index: gcc/testsuite/gcc.target/powerpc/pr80210.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr80210.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr80210.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,10 @@
++/* Test for ICE arising from GCC target pragma.  */
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++double
++foo (double a)
++{
++  return __builtin_sqrt (a);
++}
++#pragma GCC target "no-powerpc-gpopt"
+Index: gcc/testsuite/gcc.target/powerpc/vec-setup-double.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vec-setup-double.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vec-setup-double.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,11 @@
++/* { dg-do run { target { powerpc*-*-linux* } } } */
++/* { dg-require-effective-target vsx_hw } */
++/* { dg-options "-O2 -mvsx" } */
++
++/* Test various ways of creating vectors with 2 double words and accessing the
++   elements.  This test uses the double datatype and the default endian
++   order.  */
++
++#define DO_DOUBLE
++
++#include "vec-setup.h"
+Index: gcc/testsuite/gcc.target/powerpc/vsxcopy.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vsxcopy.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vsxcopy.c	(.../branches/gcc-6-branch)
+@@ -1,8 +1,8 @@
+ /* { dg-do compile { target { powerpc64*-*-* } } } */
+ /* { dg-require-effective-target powerpc_vsx_ok } */
+ /* { dg-options "-O1 -mvsx" } */
+-/* { dg-final { scan-assembler "lxvd2x" } } */
+-/* { dg-final { scan-assembler "stxvd2x" } } */
++/* { dg-final { scan-assembler {\mlxvd2x\M|\mlxv\M} } } */
++/* { dg-final { scan-assembler {\mstxvd2x\M|\mstxv\M} } } */
+ /* { dg-final { scan-assembler-not "xxpermdi" } } */
+ 
+ typedef float vecf __attribute__ ((vector_size (16)));
+Index: gcc/testsuite/gcc.target/powerpc/vec-setup-long.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vec-setup-long.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vec-setup-long.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,9 @@
++/* { dg-do run { target { powerpc*-*-linux* } } } */
++/* { dg-require-effective-target vsx_hw } */
++/* { dg-options "-O2 -mvsx" } */
++
++/* Test various ways of creating vectors with 2 double words and accessing the
++   elements.  This test uses the long (on 64-bit systems) or long long datatype
++   (on 32-bit systems).  The default endian order is used.  */
++
++#include "vec-setup.h"
+Index: gcc/testsuite/gcc.target/nvptx/indirect_call.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/nvptx/indirect_call.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/nvptx/indirect_call.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,19 @@
++/* { dg-options "-O2" } */
++/* { dg-do run } */
++
++int
++f1 (int a)
++{
++  return a + 1;
++}
++  
++int (*f2)(int) = f1;
++
++int
++main ()
++{
++  if (f2 (100) != 101)
++    __builtin_abort();
++
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/arm/peep-strd-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/arm/peep-strd-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/arm/peep-strd-1.c	(.../branches/gcc-6-branch)
+@@ -6,4 +6,4 @@
+   p[2] = a;
+   p[3] = b;
+ }
+-/* { dg-final { scan-assembler "strd" } } */
++/* { dg-final { scan-assembler "strd\\t" } } */
+Index: gcc/testsuite/gcc.target/arm/peep-strd-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/arm/peep-strd-2.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/arm/peep-strd-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_prefer_ldrd_strd } */
++/* { dg-options "-O2 -mno-unaligned-access" }  */
++void foo(int a, int b, int* p)
++{
++  p[2] = a;
++  p[3] = b;
++}
++/* { dg-final { scan-assembler-not "strd\\t" } } */
+Index: gcc/testsuite/gcc.target/arm/peep-ldrd-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c	(.../branches/gcc-6-branch)
+@@ -8,4 +8,4 @@
+   *p = a;
+   return a;
+ }
+-/* { dg-final { scan-assembler "ldrd" } } */
++/* { dg-final { scan-assembler "ldrd\\t" } } */
+Index: gcc/testsuite/gcc.target/arm/peep-ldrd-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/arm/peep-ldrd-2.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/arm/peep-ldrd-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_prefer_ldrd_strd } */
++/* { dg-options "-O2 -mno-unaligned-access" }  */
++int foo(int a, int b, int* p, int *q)
++{
++  a = p[2] + p[3];
++  *q = a;
++  *p = a;
++  return a;
++}
++/* { dg-final { scan-assembler-not "ldrd\\t" } } */
+Index: gcc/testsuite/gcc.target/avr/isr-test.h
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/avr/isr-test.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/avr/isr-test.h	(.../branches/gcc-6-branch)
+@@ -0,0 +1,282 @@
++#ifndef ISR_TEST_H
++#define ISR_TEST_H
++
++#include <string.h>
++
++#define ISR(N,...)                                                      \
++__attribute__ ((used, externally_visible , ## __VA_ARGS__))             \
++    void __vector_##N (void);                                           \
++    void __vector_##N (void)
++
++#define SFR(ADDR) (*(unsigned char volatile*) (__AVR_SFR_OFFSET__ + (ADDR)))
++#define CORE_SFRS SFR (0x38)
++#define SREG      SFR (0x3F)
++#define SPL       SFR (0x3D)
++#define EIND      SFR (0x3C)
++#define RAMPZ     SFR (0x3B)
++#define RAMPY     SFR (0x3A)
++#define RAMPX     SFR (0x39)
++#define RAMPD     SFR (0x38)
++
++#ifdef __AVR_HAVE_JMP_CALL__
++#define VEC_SIZE 4
++#else
++#define VEC_SIZE 2
++#endif
++
++#ifdef __AVR_TINY__
++#define FIRST_REG 16
++#else
++#define FIRST_REG 0
++#endif
++
++#define CR "\n\t"
++
++typedef struct
++{
++  unsigned char sfrs[8];
++  unsigned char gprs[32 - FIRST_REG];
++} regs_t;
++
++regs_t reginfo1, reginfo2;
++
++__attribute__((noinline))
++static void clear_reginfo (void)
++{
++  memset (reginfo1.sfrs, 0, sizeof (reginfo1.sfrs));
++  memset (reginfo2.sfrs, 0, sizeof (reginfo2.sfrs));
++}
++
++__attribute__((noinline))
++static void compare_reginfo (unsigned long gpr_ignore)
++{
++  signed char regno;
++  const unsigned char *preg1 = &reginfo1.gprs[0];
++  const unsigned char *preg2 = &reginfo2.gprs[0];
++
++  if (memcmp (&reginfo1, &reginfo2, 8))
++    __builtin_abort();
++
++  gpr_ignore >>= FIRST_REG;
++
++    for (regno = FIRST_REG; regno < 32;
++       regno++, preg1++, preg2++, gpr_ignore >>= 1)
++    {
++      if (gpr_ignore & 1)
++        continue;
++
++      if (*preg1 != *preg2)
++        {
++          static signed char volatile failed_regno;
++          failed_regno = regno;
++          __builtin_abort();
++        }
++    }
++}
++
++/* STore GPR */
++#define ST(regno,M)                                     \
++  CR "sts %[" #M "]+8-%[first]+" #regno ", r" #regno
++
++/* STore SFR */
++#define ST_SFR(sfr, n_sfr, M)                   \
++  CR "in __tmp_reg__,%i[s_" #sfr "]"            \
++  CR "sts %[" #M "]+" #n_sfr ", __tmp_reg__"
++
++/* Named asm OPerand for SFR */
++#define OP_SFR(sfr)                             \
++  , [s_ ## sfr] "n" (&(sfr))
++
++/* Write funny value to SFR */
++#define XX_SFR(sfr)                             \
++  CR "dec r31 $ out %i[s_" #sfr "], r31"
++
++/* Write 0 to SFR */
++#define OO_SFR(sfr)                             \
++  CR "out %i[s_" #sfr "], __zero_reg__"
++
++/* Macros for SREG */
++#define ST_SREG(M) ST_SFR (SREG,0,M)
++#define OP_SREG    OP_SFR (SREG)
++#define XX_SREG    XX_SFR (SREG)
++
++/* Macros for EIND */
++#if defined __AVR_HAVE_EIJMP_EICALL__
++#define ST_EIND(M) ST_SFR (EIND,1,M)
++#define OP_EIND    OP_SFR (EIND)
++#else
++#define ST_EIND(M) /* empty */
++#define OP_EIND    /* empty */
++#endif
++
++/* Macros for RAMPX */
++#if defined (__AVR_HAVE_RAMPX__)
++#define ST_RAMPX(M) ST_SFR (RAMPX,2,M)
++#define OP_RAMPX    OP_SFR (RAMPX)
++#define XX_RAMPX    XX_SFR (RAMPX)
++#define OO_RAMPX    OO_SFR (RAMPX)
++#else
++#define ST_RAMPX(M) /* empty */
++#define OP_RAMPX    /* empty */
++#define XX_RAMPX    /* empty */
++#define OO_RAMPX    /* empty */
++#endif
++
++/* Macros for RAMPY */
++#if defined (__AVR_HAVE_RAMPY__)
++#define ST_RAMPY(M) ST_SFR (RAMPY,3,M)
++#define OP_RAMPY    OP_SFR (RAMPY)
++#define XX_RAMPY    XX_SFR (RAMPY)
++#define OO_RAMPY    OO_SFR (RAMPY)
++#else
++#define ST_RAMPY(M) /* empty */
++#define OP_RAMPY    /* empty */
++#define XX_RAMPY    /* empty */
++#define OO_RAMPY    /* empty */
++#endif
++
++/* Macros for RAMPZ */
++#if defined (__AVR_HAVE_RAMPZ__)
++#define ST_RAMPZ(M) ST_SFR (RAMPZ,4,M)
++#define OP_RAMPZ    OP_SFR (RAMPZ)
++#define XX_RAMPZ    XX_SFR (RAMPZ)
++#define OO_RAMPZ    OO_SFR (RAMPZ)
++#else
++#define ST_RAMPZ(M) /* empty */
++#define OP_RAMPZ    /* empty */
++#define XX_RAMPZ    /* empty */
++#define OO_RAMPZ    /* empty */
++#endif
++
++/* Macros for RAMPD */
++#if defined (__AVR_HAVE_RAMPD__)
++#define ST_RAMPD(M) ST_SFR (RAMPD,5,M)
++#define OP_RAMPD    OP_SFR (RAMPD)
++#else
++#define ST_RAMPD(M) /* empty */
++#define OP_RAMPD    /* empty */
++#endif
++
++/* Macros for all GPRs */
++#if defined __AVR_TINY__
++#define ST_REGS_LO(M) /* empty */
++#else
++#define ST_REGS_LO(M)                           \
++  ST(0,M)   ST(1,M)   ST(2,M)   ST(3,M)         \
++  ST(4,M)   ST(5,M)   ST(6,M)   ST(7,M)         \
++  ST(8,M)   ST(9,M)   ST(10,M)  ST(11,M)        \
++  ST(12,M)  ST(13,M)  ST(14,M)  ST(15,M)
++#endif /* AVR_TINY */
++
++#define ST_REGS_HI(M)                           \
++  ST(16,M)    ST(17,M)    ST(18,M)    ST(19,M)  \
++  ST(20,M)    ST(21,M)    ST(22,M)    ST(23,M)  \
++  ST(24,M)    ST(25,M)    ST(26,M)    ST(27,M)  \
++  ST(28,M)    ST(29,M)    ST(30,M)    ST(31,M)
++
++__attribute__((unused,naked,noinline,noclone))
++static void host_store1 (void)
++{
++  __asm __volatile__
++  ("nop"
++   CR ".global do_stores_before"
++   CR ".type   do_stores_before,@function"
++   CR "do_stores_before:"
++   /* Funny values to some SFRs */
++   CR "ldi r31, 1 + 'Z'"
++   XX_RAMPZ
++   XX_RAMPY
++   XX_RAMPX
++   CR "dec __zero_reg__"
++   CR "clr r31"
++   XX_SREG
++   /* Must set I-flag due to RETI of ISR */
++   CR "sei"
++   /* Store core regs before ISR */
++   ST_RAMPX (mem1)
++   ST_RAMPY (mem1)
++   ST_RAMPZ (mem1)
++   ST_RAMPD (mem1)
++   ST_EIND  (mem1)
++   ST_SREG  (mem1)
++   CR "ldi r31, 0xaa"
++   CR "mov __tmp_reg__, r31"
++   CR "ldi r31, 31"
++   ST_REGS_LO (mem1)
++   ST_REGS_HI (mem1)
++   CR "ret"
++   : /* No outputs */
++   : [mem1] "i" (&reginfo1), [first] "n" (FIRST_REG)
++   OP_RAMPX
++   OP_RAMPY
++   OP_RAMPZ
++   OP_RAMPD
++   OP_EIND
++   OP_SREG
++   : "memory", "r31");
++}
++
++__attribute__((unused,naked,noinline,noclone))
++static void host_store2 (void)
++{
++  __asm __volatile__
++  ("nop"
++   CR ".global do_stores_after"
++   CR ".type   do_stores_after,@function"
++   CR "do_stores_after:"
++   /* Store core regs after ISR */
++   ST_REGS_LO (mem2)
++   ST_REGS_HI (mem2)
++   ST_RAMPX (mem2)
++   ST_RAMPY (mem2)
++   ST_RAMPZ (mem2)
++   ST_RAMPD (mem2)
++   ST_EIND  (mem2)
++   ST_SREG  (mem2)
++   /* Undo funny values */
++   CR "clr __zero_reg__"
++   OO_RAMPX
++   OO_RAMPY
++   OO_RAMPZ
++   CR "ret"
++   : /* No outputs */
++   : [mem2] "i" (&reginfo2), [first] "n" (FIRST_REG)
++   OP_RAMPX
++   OP_RAMPY
++   OP_RAMPZ
++   OP_RAMPD
++   OP_EIND
++   OP_SREG
++   : "memory");
++}
++
++#define MK_CALL_ISR(vecno)                      \
++  __asm __volatile__                            \
++  (/* Funny values to some SFRs */              \
++   /* Must set I-flag due to RETI of ISR */     \
++   /* Store core regs before ISR */             \
++   CR "%~call do_stores_before"                 \
++   /* Execute ISR */                            \
++   CR "%~call __vectors + %[vect]"              \
++   /* Store core regs after ISR */              \
++   /* Undo funny values */                      \
++   CR "%~call do_stores_after"                  \
++   : /* No outputs */                           \
++   : [vect] "i" (VEC_SIZE * (vecno))            \
++   , "i" (host_store1)                          \
++   , "i" (host_store2)                          \
++   : "memory", "r31")
++
++
++#define MK_RUN_ISR(N, IGMSK)                    \
++                                                \
++__attribute__((noinline,noclone))               \
++void run_isr_ ## N (void)                       \
++{                                               \
++  clear_reginfo();                              \
++  MK_CALL_ISR (N);                              \
++  compare_reginfo (IGMSK);                      \
++}
++
++#endif /* ISR_TEST_H */
++
+Index: gcc/testsuite/gcc.target/avr/torture/isr-01-simple.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/avr/torture/isr-01-simple.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/avr/torture/isr-01-simple.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,98 @@
++/* { dg-do run } */
++/* { dg-options "-std=c99" } */
++
++#include "../isr-test.h"
++
++int volatile v;
++
++/**********************************************************************/
++
++ISR (1, signal)
++{
++}
++
++MK_RUN_ISR (1, 0)
++
++void test1 (void)
++{
++  run_isr_1();
++}
++
++/**********************************************************************/
++
++ISR (2, signal)
++{
++  v++;
++}
++
++MK_RUN_ISR (2, 0)
++
++void test2 (void)
++{
++  v = 0;
++  run_isr_2();
++  if (v != 1)
++    __builtin_abort();
++}
++
++
++/**********************************************************************/
++
++ISR (3, signal)
++{
++  __asm __volatile__ ("$ lds  r27, v"
++                      "$ swap r27"
++                      "$ sts  v, r27"
++                      ::: "memory", "r27");
++}
++
++MK_RUN_ISR (3, 0)
++
++void test3 (void)
++{
++  run_isr_3();
++  if (v != 0x10)
++    __builtin_abort();
++}
++
++/**********************************************************************/
++
++ISR (4, signal)
++{
++  __asm __volatile__ ("sts v,__zero_reg__" ::: "memory");
++}
++
++MK_RUN_ISR (4, 0)
++
++void test4 (void)
++{
++  run_isr_4();
++  if (v != 0)
++    __builtin_abort();
++}
++
++/**********************************************************************/
++
++ISR (5, signal)
++{
++  __asm __volatile__ ("clt");
++}
++
++MK_RUN_ISR (5, 0)
++
++void test5 (void)
++{
++  run_isr_5();
++}
++
++/**********************************************************************/
++
++int main (void)
++{
++  test1();
++  test2();
++  test3();
++  test4();
++  test5();
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/avr/torture/isr-02-call.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/avr/torture/isr-02-call.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/avr/torture/isr-02-call.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,60 @@
++/* { dg-do run } */
++/* { dg-options "-std=c99" } */
++
++#include "../isr-test.h"
++
++int volatile v;
++
++__attribute__((noinline,noclone))
++void inc_v (void)
++{
++  v++;
++}
++
++/**********************************************************************/
++
++ISR (1, signal)
++{
++  inc_v();
++}
++
++MK_RUN_ISR (1, 0)
++
++void test1 (void)
++{
++  run_isr_1();
++  if (v != 1)
++    __builtin_abort();
++}
++
++/**********************************************************************/
++
++ISR (2, signal)
++{
++  if (v == 1)
++    inc_v();
++  else
++    v += 2;
++}
++
++MK_RUN_ISR (2, 0)
++
++void test2 (void)
++{
++  run_isr_2();
++  if (v != 2)
++    __builtin_abort();
++  run_isr_2();
++  if (v != 4)
++    __builtin_abort();
++}
++
++
++/**********************************************************************/
++
++int main (void)
++{
++  test1();
++  test2();
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/avr/torture/isr-03-fixed.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/avr/torture/isr-03-fixed.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/avr/torture/isr-03-fixed.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,146 @@
++/* { dg-do run } */
++/* { dg-options "-std=gnu99 -fno-lto -fno-toplevel-reorder" } */
++
++// No LTO for now due to PR lto/68384.
++
++#ifdef __AVR_TINY__
++unsigned char reg2;
++#else
++register unsigned char reg2 __asm("r2");
++#endif
++
++#include "../isr-test.h"
++
++#define SET_REG(reg,val)                        \
++  do {                                          \
++    reg = (val);                                \
++    __asm __volatile__("" : "+r" (reg));        \
++  } while (0)                                   \
++
++#define GET_REG(reg)                            \
++  ({                                            \
++    __asm __volatile__("" : "+r" (reg));        \
++    reg;                                        \
++  })
++
++/**********************************************************************/
++
++ISR (1, signal)
++{
++  reg2++;
++}
++
++MK_RUN_ISR (1, 1ul << 2)
++
++void test1 (void)
++{
++  SET_REG (reg2, 0);
++  run_isr_1();
++  if (GET_REG (reg2) != 1)
++    __builtin_abort();
++}
++
++/**********************************************************************/
++
++__attribute__((noinline,noclone))
++void inc_r2 (void)
++{
++  reg2++;
++}
++
++ISR (2, signal)
++{
++  inc_r2 ();
++}
++
++MK_RUN_ISR (2, 1ul << 2)
++
++void test2 (void)
++{
++  run_isr_2();
++  if (GET_REG (reg2) != 2)
++    __builtin_abort();
++}
++
++
++/**********************************************************************/
++
++ISR (3, signal)
++{
++#ifndef __AVR_TINY__
++  register char r4 __asm ("r4");
++  __asm __volatile ("inc %0" : "+r" (r4));
++  __asm __volatile ("inc r5" ::: "r5");
++#endif
++}
++
++MK_RUN_ISR (3, 0)
++
++void test3 (void)
++{
++  run_isr_3();
++}
++
++
++/**********************************************************************/
++
++#define CLOBB(reg)                                 \
++  do {                                             \
++    __asm __volatile__ ("inc " #reg ::: #reg);     \
++  } while (0)
++
++ISR (4, signal)
++{
++  char volatile v;
++  v = 1;
++
++#ifndef __AVR_TINY__
++  CLOBB (r3);
++  CLOBB (r4);
++  CLOBB (r5);
++  CLOBB (r6);
++  CLOBB (r7);
++  CLOBB (r8);
++  CLOBB (r9);
++  CLOBB (r10);
++  CLOBB (r11);
++  CLOBB (r12);
++  CLOBB (r13);
++  CLOBB (r14);
++  CLOBB (r15);
++  CLOBB (r16);
++  CLOBB (r17);
++#endif
++
++  CLOBB (r18);
++  CLOBB (r19);
++  CLOBB (r20);
++  CLOBB (r21);
++  CLOBB (r22);
++  CLOBB (r23);
++  CLOBB (r24);
++  CLOBB (r25);
++  CLOBB (r26);
++  CLOBB (r27);
++  CLOBB (r30);
++  CLOBB (r31);
++}
++
++MK_RUN_ISR (4, 0)
++
++void test4 (void)
++{
++  run_isr_4();
++}
++
++
++/**********************************************************************/
++
++int main (void)
++{
++  test1();
++  test2();
++  test3();
++  test4();
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/s390/nobp-table-jump-z10.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-table-jump-z10.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-table-jump-z10.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,77 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z10 -mzarch --save-temps -mindirect-branch-jump=thunk -mindirect-branch-table" } */
++/* case-values-threshold will be set to 20 by the back-end when jump
++   thunk are requested.  */
++
++int __attribute__((noinline,noclone)) foo1 (void) { return 1; }
++int __attribute__((noinline,noclone)) foo2 (void) { return 2; }
++int __attribute__((noinline,noclone)) foo3 (void) { return 3; }
++int __attribute__((noinline,noclone)) foo4 (void) { return 4; }
++int __attribute__((noinline,noclone)) foo5 (void) { return 5; }
++int __attribute__((noinline,noclone)) foo6 (void) { return 6; }
++int __attribute__((noinline,noclone)) foo7 (void) { return 7; }
++int __attribute__((noinline,noclone)) foo8 (void) { return 8; }
++int __attribute__((noinline,noclone)) foo9 (void) { return 9; }
++int __attribute__((noinline,noclone)) foo10 (void) { return 10; }
++int __attribute__((noinline,noclone)) foo11 (void) { return 11; }
++int __attribute__((noinline,noclone)) foo12 (void) { return 12; }
++int __attribute__((noinline,noclone)) foo13 (void) { return 13; }
++int __attribute__((noinline,noclone)) foo14 (void) { return 14; }
++int __attribute__((noinline,noclone)) foo15 (void) { return 15; }
++int __attribute__((noinline,noclone)) foo16 (void) { return 16; }
++int __attribute__((noinline,noclone)) foo17 (void) { return 17; }
++int __attribute__((noinline,noclone)) foo18 (void) { return 18; }
++int __attribute__((noinline,noclone)) foo19 (void) { return 19; }
++int __attribute__((noinline,noclone)) foo20 (void) { return 20; }
++
++
++int __attribute__((noinline,noclone))
++bar (int a)
++{
++  int ret = 0;
++
++  switch (a)
++    {
++    case 1: ret = foo1 (); break;
++    case 2: ret = foo2 (); break;
++    case 3: ret = foo3 (); break;
++    case 4: ret = foo4 (); break;
++    case 5: ret = foo5 (); break;
++    case 6: ret = foo6 (); break;
++    case 7: ret = foo7 (); break;
++    case 8: ret = foo8 (); break;
++    case 9: ret = foo9 (); break;
++    case 10: ret = foo10 (); break;
++    case 11: ret = foo11 (); break;
++    case 12: ret = foo12 (); break;
++    case 13: ret = foo13 (); break;
++    case 14: ret = foo14 (); break;
++    case 15: ret = foo15 (); break;
++    case 16: ret = foo16 (); break;
++    case 17: ret = foo17 (); break;
++    case 18: ret = foo18 (); break;
++    case 19: ret = foo19 (); break;
++    case 20: ret = foo20 (); break;
++    default:
++      __builtin_abort ();
++    }
++
++  return ret;
++}
++
++int
++main ()
++{
++  if (bar (3) != 3)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 1 x bar
++/* { dg-final { scan-assembler-times "exrl" 1 } } */
++
++/* { dg-final { scan-assembler     "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_fromreg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_frommem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-indirect-jump-z900.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-z900.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-z900.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,43 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z900 --save-temps -mindirect-branch-jump=thunk -mindirect-branch-table" } */
++/* { dg-require-effective-target label_values } */
++
++/* This is a copy of the gcc.c-torture/execute/20040302-1.c
++   testcase.  */
++
++int code[]={0,0,0,0,1};
++
++void
++foo(int x) {
++  volatile int b;
++  b = 0xffffffff;
++}
++
++void
++bar(int *pc) {
++  static const void *l[] = {&&lab0, &&end};
++
++  foo(0);
++  goto *l[*pc];
++ lab0:
++  foo(0);
++  pc++;
++  goto *l[*pc];
++ end:
++  return;
++}
++
++int
++main() {
++  bar(code);
++  return 0;
++}
++
++/* 2 x bar
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 2 } } */
++/* { dg-final { scan-assembler "ex\t" } } */
++
++/* { dg-final { scan-assembler     "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-return-mem-attr.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-return-mem-attr.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-return-mem-attr.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,46 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z10 -mzarch --save-temps -mindirect-branch-table" } */
++
++int gl = 0;
++
++int __attribute__((noinline,noclone))
++bar (int a)
++{
++  return a + 2;
++}
++
++void __attribute__((function_return_mem("thunk"),noinline,noclone))
++foo (int a)
++{
++  int i;
++
++  if (a == 42)
++    return;
++
++  for (i = 0; i < a; i++)
++    gl += bar (i);
++}
++
++int
++main ()
++{
++  foo (3);
++  if (gl != 9)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* With -march=z10 -mzarch the shrink wrapped returns use compare and
++   swap relative to jump to the exit block instead of making use of
++   the conditional return pattern.
++   FIXME: Use compare and branch register for that!!!! */
++
++/* 2 x foo
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 2 } } */
++/* { dg-final { scan-assembler "exrl" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler     "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-function-pointer-attr.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-function-pointer-attr.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-function-pointer-attr.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,56 @@
++/* { dg-do run } */
++/* { dg-options "-O3  -march=z10 --save-temps -mindirect-branch-table" } */
++
++int gl;
++
++void __attribute__((noinline,noclone))
++foo (int a)
++{
++  gl = a + 40;
++}
++
++int __attribute__((noinline,noclone))
++foo_value (int a)
++{
++  return a + 40;
++}
++
++void* __attribute__((noinline,noclone))
++get_fptr (int a)
++{
++  switch (a)
++    {
++    case 0: return &foo; break;
++    case 1: return &foo_value; break;
++    default: __builtin_abort ();
++    }
++}
++
++void (*f) (int);
++int (*g) (int);
++
++int __attribute__((indirect_branch_call("thunk")))
++main ()
++{
++  int res;
++
++  f = get_fptr(0);
++  f (2);
++  if (gl != 42)
++    __builtin_abort ();
++
++  g = get_fptr(1);
++  if (g (2) != 42)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 2 x main
++/* { dg-final { scan-assembler-times "brasl\t%r\[0-9\]*,__s390_indirect_jump" 2 } } */
++/* { dg-final { scan-assembler "exrl" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler     "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-indirect-jump-inline-z900.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-inline-z900.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-inline-z900.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,43 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z900 --save-temps -mindirect-branch-jump=thunk-inline -mindirect-branch-table" } */
++/* { dg-require-effective-target label_values } */
++
++/* This is a copy of the gcc.c-torture/execute/20040302-1.c
++   testcase.  */
++
++int code[]={0,0,0,0,1};
++
++void
++foo(int x) {
++  volatile int b;
++  b = 0xffffffff;
++}
++
++void
++bar(int *pc) {
++  static const void *l[] = {&&lab0, &&end};
++
++  foo(0);
++  goto *l[*pc];
++ lab0:
++  foo(0);
++  pc++;
++  goto *l[*pc];
++ end:
++  return;
++}
++
++int
++main() {
++  bar(code);
++  return 0;
++}
++
++/* The two gotos in bar get merged.  */
++/* { dg-final { scan-assembler-times "\tex\t" 1 } } */
++
++/* { dg-final { scan-assembler-not "jg\t__s390_indirect_jump" } } */
++/* { dg-final { scan-assembler     "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z900.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z900.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z900.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,78 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z900 -mzarch --save-temps -mindirect-branch-jump=thunk-inline -mindirect-branch-table" } */
++
++/* case-values-threshold will be set to 20 by the back-end when jump
++   thunk are requested.  */
++
++int __attribute__((noinline,noclone)) foo1 (void) { return 1; }
++int __attribute__((noinline,noclone)) foo2 (void) { return 2; }
++int __attribute__((noinline,noclone)) foo3 (void) { return 3; }
++int __attribute__((noinline,noclone)) foo4 (void) { return 4; }
++int __attribute__((noinline,noclone)) foo5 (void) { return 5; }
++int __attribute__((noinline,noclone)) foo6 (void) { return 6; }
++int __attribute__((noinline,noclone)) foo7 (void) { return 7; }
++int __attribute__((noinline,noclone)) foo8 (void) { return 8; }
++int __attribute__((noinline,noclone)) foo9 (void) { return 9; }
++int __attribute__((noinline,noclone)) foo10 (void) { return 10; }
++int __attribute__((noinline,noclone)) foo11 (void) { return 11; }
++int __attribute__((noinline,noclone)) foo12 (void) { return 12; }
++int __attribute__((noinline,noclone)) foo13 (void) { return 13; }
++int __attribute__((noinline,noclone)) foo14 (void) { return 14; }
++int __attribute__((noinline,noclone)) foo15 (void) { return 15; }
++int __attribute__((noinline,noclone)) foo16 (void) { return 16; }
++int __attribute__((noinline,noclone)) foo17 (void) { return 17; }
++int __attribute__((noinline,noclone)) foo18 (void) { return 18; }
++int __attribute__((noinline,noclone)) foo19 (void) { return 19; }
++int __attribute__((noinline,noclone)) foo20 (void) { return 20; }
++
++
++int __attribute__((noinline,noclone))
++bar (int a)
++{
++  int ret = 0;
++
++  switch (a)
++    {
++    case 1: ret = foo1 (); break;
++    case 2: ret = foo2 (); break;
++    case 3: ret = foo3 (); break;
++    case 4: ret = foo4 (); break;
++    case 5: ret = foo5 (); break;
++    case 6: ret = foo6 (); break;
++    case 7: ret = foo7 (); break;
++    case 8: ret = foo8 (); break;
++    case 9: ret = foo9 (); break;
++    case 10: ret = foo10 (); break;
++    case 11: ret = foo11 (); break;
++    case 12: ret = foo12 (); break;
++    case 13: ret = foo13 (); break;
++    case 14: ret = foo14 (); break;
++    case 15: ret = foo15 (); break;
++    case 16: ret = foo16 (); break;
++    case 17: ret = foo17 (); break;
++    case 18: ret = foo18 (); break;
++    case 19: ret = foo19 (); break;
++    case 20: ret = foo20 (); break;
++    default:
++      __builtin_abort ();
++    }
++
++  return ret;
++}
++
++int
++main ()
++{
++  if (bar (3) != 3)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 1 x bar
++/* { dg-final { scan-assembler-times "\tex\t" 1 } } */
++
++/* { dg-final { scan-assembler     "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_fromreg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_frommem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-return-reg-nothunk.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-return-reg-nothunk.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-return-reg-nothunk.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,44 @@
++/* { dg-do compile } */
++/* { dg-options "-O3 -march=z10 --save-temps -mfunction-return-reg=thunk-extern -mindirect-branch-table" } */
++
++int gl = 0;
++
++int __attribute__((noinline,noclone))
++bar (int a)
++{
++  return a + 2;
++}
++
++void __attribute__((noinline,noclone))
++foo (int a)
++{
++  int i;
++
++  if (a == 42)
++    return;
++
++  for (i = 0; i < a; i++)
++    gl += bar (i);
++}
++
++int
++main ()
++{
++  foo (3);
++  if (gl != 9)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 1 x bar
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 1 } } */
++
++/* No thunks due to thunk-extern.  */
++/* { dg-final { scan-assembler-not "exrl" } } */
++/* { dg-final { scan-assembler-not ".globl __s390_indirect_jump" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler     "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-return-mem-nothunk.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-return-mem-nothunk.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-return-mem-nothunk.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,49 @@
++/* { dg-do compile } */
++/* { dg-options "-O3 -march=z10 -mzarch --save-temps -mfunction-return-mem=thunk-extern -mindirect-branch-table" } */
++
++int gl = 0;
++
++int __attribute__((noinline,noclone))
++bar (int a)
++{
++  return a + 2;
++}
++
++void __attribute__((noinline,noclone))
++foo (int a)
++{
++  int i;
++
++  if (a == 42)
++    return;
++
++  for (i = 0; i < a; i++)
++    gl += bar (i);
++}
++
++int
++main ()
++{
++  foo (3);
++  if (gl != 9)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* With -march=z10 -mzarch the shrink wrapped returns use compare and
++   swap relative to jump to the exit block instead of making use of
++   the conditional return pattern.
++   FIXME: Use compare and branch register for that!!!! */
++
++/* 2 x foo, 1 x main
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 3 } } */
++
++/* No thunks due to thunk-extern.  */
++/* { dg-final { scan-assembler-not "exrl" } } */
++/* { dg-final { scan-assembler-not ".globl __s390_indirect_jump" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler     "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-function-pointer-nothunk.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-function-pointer-nothunk.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-function-pointer-nothunk.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,59 @@
++/* { dg-do compile } */
++/* { dg-options "-O3  -march=z10 --save-temps -mindirect-branch-call=thunk-extern -mindirect-branch-table" } */
++
++int gl;
++
++void __attribute__((noinline,noclone))
++foo (int a)
++{
++  gl = a + 40;
++}
++
++int __attribute__((noinline,noclone))
++foo_value (int a)
++{
++  return a + 40;
++}
++
++void*  __attribute__((noinline,noclone))
++get_fptr (int a)
++{
++  switch (a)
++    {
++    case 0: return &foo; break;
++    case 1: return &foo_value; break;
++    default: __builtin_abort ();
++    }
++}
++
++void (*f) (int);
++int (*g) (int);
++
++int
++main ()
++{
++  int res;
++
++  f = get_fptr(0);
++  f (2);
++  if (gl != 42)
++    __builtin_abort ();
++
++  g = get_fptr(1);
++  if (g (2) != 42)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 2 x main
++/* { dg-final { scan-assembler-times "brasl\t%r\[0-9\]*,__s390_indirect_jump" 2 } } */
++
++/* No thunks due to thunk-extern.  */
++/* { dg-final { scan-assembler-not "exrl" } } */
++/* { dg-final { scan-assembler-not ".globl __s390_indirect_jump" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler     "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-indirect-jump-nothunk.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-nothunk.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-nothunk.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,46 @@
++/* { dg-do compile } */
++/* { dg-options "-O3 -march=z10 --save-temps -mindirect-branch-jump=thunk-extern -mindirect-branch-table" } */
++/* { dg-require-effective-target label_values } */
++
++/* This is a copy of the gcc.c-torture/execute/20040302-1.c
++   testcase.  */
++
++int code[]={0,0,0,0,1};
++
++void
++foo(int x) {
++  volatile int b;
++  b = 0xffffffff;
++}
++
++void
++bar(int *pc) {
++  static const void *l[] = {&&lab0, &&end};
++
++  foo(0);
++  goto *l[*pc];
++ lab0:
++  foo(0);
++  pc++;
++  goto *l[*pc];
++ end:
++  return;
++}
++
++int
++main() {
++  bar(code);
++  return 0;
++}
++
++/* 2 x bar
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 2 } } */
++
++/* No thunks due to thunk-extern.  */
++/* { dg-final { scan-assembler-not "exrl" } } */
++/* { dg-final { scan-assembler-not ".globl __s390_indirect_jump" } } */
++
++/* { dg-final { scan-assembler     "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-return-mem-z10.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-return-mem-z10.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-return-mem-z10.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,46 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z10 -mzarch --save-temps -mfunction-return-mem=thunk -mindirect-branch-table" } */
++
++int gl = 0;
++
++int __attribute__((noinline,noclone))
++bar (int a)
++{
++  return a + 2;
++}
++
++void __attribute__((noinline,noclone))
++foo (int a)
++{
++  int i;
++
++  if (a == 42)
++    return;
++
++  for (i = 0; i < a; i++)
++    gl += bar (i);
++}
++
++int
++main ()
++{
++  foo (3);
++  if (gl != 9)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* With -march=z10 -mzarch the shrink wrapped returns use compare and
++   swap relative to jump to the exit block instead of making use of
++   the conditional return pattern.
++   FIXME: Use compare and branch register for that!!!! */
++
++/* 2 x foo, 1 x main
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 3 } } */
++/* { dg-final { scan-assembler "exrl" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler     "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-function-pointer-z10.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-function-pointer-z10.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-function-pointer-z10.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,56 @@
++/* { dg-do run } */
++/* { dg-options "-O3  -march=z10 --save-temps -mindirect-branch-call=thunk -mindirect-branch-table" } */
++
++int gl;
++
++void __attribute__((noinline,noclone))
++foo (int a)
++{
++  gl = a + 40;
++}
++
++int __attribute__((noinline,noclone))
++foo_value (int a)
++{
++  return a + 40;
++}
++
++void*  __attribute__((noinline,noclone))
++get_fptr (int a)
++{
++  switch (a)
++    {
++    case 0: return &foo; break;
++    case 1: return &foo_value; break;
++    default: __builtin_abort ();
++    }
++}
++
++void (*f) (int);
++int (*g) (int);
++
++int
++main ()
++{
++  int res;
++
++  f = get_fptr(0);
++  f (2);
++  if (gl != 42)
++    __builtin_abort ();
++
++  g = get_fptr(1);
++  if (g (2) != 42)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 2 x main
++/* { dg-final { scan-assembler-times "brasl\t%r\[0-9\]*,__s390_indirect_jump" 2 } } */
++/* { dg-final { scan-assembler "exrl" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler     "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-return-reg-attr.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-return-reg-attr.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-return-reg-attr.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,41 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z10 --save-temps -mindirect-branch-table" } */
++
++int gl = 0;
++
++int __attribute__((function_return_reg("thunk"),noinline,noclone))
++bar (int a)
++{
++  return a + 2;
++}
++
++void __attribute__((noinline,noclone))
++foo (int a)
++{
++  int i;
++
++  if (a == 42)
++    return;
++
++  for (i = 0; i < a; i++)
++    gl += bar (i);
++}
++
++int
++main ()
++{
++  foo (3);
++  if (gl != 9)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 1 x bar
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 1 } } */
++/* { dg-final { scan-assembler "exrl" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler     "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-indirect-jump-attr.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-attr.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-attr.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z10 --save-temps -mindirect-branch-table" } */
++/* { dg-require-effective-target label_values } */
++
++/* This is a copy of the gcc.c-torture/execute/20040302-1.c
++   testcase.  */
++
++int code[]={0,0,0,0,1};
++
++void
++foo(int x) {
++  volatile int b;
++  b = 0xffffffff;
++}
++
++void __attribute__((indirect_branch_jump("thunk")))
++bar(int *pc) {
++  static const void *l[] = {&&lab0, &&end};
++
++  foo(0);
++  goto *l[*pc];
++ lab0:
++  foo(0);
++  pc++;
++  goto *l[*pc];
++ end:
++  return;
++}
++
++int main() {
++  bar(code);
++  return 0;
++}
++
++/* 2x bar */
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 2 } } */
++/* { dg-final { scan-assembler "exrl" } } */
++
++/* { dg-final { scan-assembler     "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-return-mem-z900.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-return-mem-z900.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-return-mem-z900.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,48 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z900 --save-temps -mfunction-return-mem=thunk -mindirect-branch-table" } */
++
++int gl = 0;
++
++int __attribute__((noinline,noclone))
++bar (int a)
++{
++  return a + 2;
++}
++
++void __attribute__((noinline,noclone))
++foo (int a)
++{
++  int i;
++
++  if (a == 42)
++    return;
++
++  for (i = 0; i < a; i++)
++    gl += bar (i);
++}
++
++int
++main ()
++{
++  foo (3);
++  if (gl != 9)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 1 x foo, 1 x main
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 2 } } */
++
++/* 1 x foo, conditional return, shrink wrapped
++/* { dg-final { scan-assembler "jge\t__s390_indirect_jump" } } */
++
++/* 1 x foo, conditional return, shrink wrapped
++/* { dg-final { scan-assembler "jgle\t__s390_indirect_jump" } } */
++
++/* { dg-final { scan-assembler "ex\t" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler     "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-indirect-jump-inline-z10.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-inline-z10.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-inline-z10.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,43 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z10 --save-temps -mindirect-branch-jump=thunk-inline -mindirect-branch-table" } */
++/* { dg-require-effective-target label_values } */
++
++/* This is a copy of the gcc.c-torture/execute/20040302-1.c
++   testcase.  */
++
++int code[]={0,0,0,0,1};
++
++void
++foo(int x) {
++  volatile int b;
++  b = 0xffffffff;
++}
++
++void
++bar(int *pc) {
++  static const void *l[] = {&&lab0, &&end};
++
++  foo(0);
++  goto *l[*pc];
++ lab0:
++  foo(0);
++  pc++;
++  goto *l[*pc];
++ end:
++  return;
++}
++
++int
++main() {
++  bar(code);
++  return 0;
++}
++
++/* The two gotos in bar get merged.  */
++/* { dg-final { scan-assembler-times "exrl" 1 } } */
++
++/* { dg-final { scan-assembler-not "jg\t__s390_indirect_jump" } } */
++/* { dg-final { scan-assembler     "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-return-attr-neg.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-return-attr-neg.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-return-attr-neg.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,40 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z10 -mzarch --save-temps -mfunction-return-mem=thunk -mindirect-branch-table" } */
++
++int gl = 0;
++
++int __attribute__((noinline,noclone))
++bar (int a)
++{
++  return a + 2;
++}
++
++void __attribute__((function_return("keep"),noinline,noclone))
++foo (int a)
++{
++  int i;
++
++  if (a == 42)
++    return;
++
++  for (i = 0; i < a; i++)
++    gl += bar (i);
++}
++
++int __attribute__((function_return("keep")))
++main ()
++{
++  foo (3);
++  if (gl != 9)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* { dg-final { scan-assembler-not "jg\t__s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "exrl" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-function-pointer-z900.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-function-pointer-z900.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-function-pointer-z900.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,56 @@
++/* { dg-do run } */
++/* { dg-options "-O3  -march=z900 --save-temps -mindirect-branch-call=thunk -mindirect-branch-table" } */
++
++int gl;
++
++void __attribute__((noinline,noclone))
++foo (int a)
++{
++  gl = a + 40;
++}
++
++int __attribute__((noinline,noclone))
++foo_value (int a)
++{
++  return a + 40;
++}
++
++void*  __attribute__((noinline,noclone))
++get_fptr (int a)
++{
++  switch (a)
++    {
++    case 0: return &foo; break;
++    case 1: return &foo_value; break;
++    default: __builtin_abort ();
++    }
++}
++
++void (*f) (int);
++int (*g) (int);
++
++int
++main ()
++{
++  int res;
++
++  f = get_fptr(0);
++  f (2);
++  if (gl != 42)
++    __builtin_abort ();
++
++  g = get_fptr(1);
++  if (g (2) != 42)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 2 x main
++/* { dg-final { scan-assembler-times "brasl\t%r\[0-9\]*,__s390_indirect_jump" 2 } } */
++/* { dg-final { scan-assembler "ex\t" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler     "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-indirect-jump-inline-attr.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-inline-attr.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-inline-attr.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,42 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z10 --save-temps -mindirect-branch-table" } */
++/* { dg-require-effective-target label_values } */
++
++/* This is a copy of the gcc.c-torture/execute/20040302-1.c
++   testcase.  */
++
++int code[]={0,0,0,0,1};
++
++void foo(int x) {
++  volatile int b;
++  b = 0xffffffff;
++}
++
++void __attribute__((indirect_branch_jump("thunk-inline")))
++bar(int *pc) {
++  static const void *l[] = {&&lab0, &&end};
++
++  foo(0);
++  goto *l[*pc];
++ lab0:
++  foo(0);
++  pc++;
++  goto *l[*pc];
++ end:
++  return;
++}
++
++int
++main() {
++  bar(code);
++  return 0;
++}
++
++/* The two gotos in bar get merged.  */
++/* { dg-final { scan-assembler-times "exrl" 1 } } */
++
++/* { dg-final { scan-assembler-not "jg\t__s390_indirect_jump" } } */
++/* { dg-final { scan-assembler     "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-table-jump-z900.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-table-jump-z900.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-table-jump-z900.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,78 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z900 -mzarch --save-temps -mindirect-branch-jump=thunk -mindirect-branch-table" } */
++
++/* case-values-threshold will be set to 20 by the back-end when jump
++   thunk are requested.  */
++
++int __attribute__((noinline,noclone)) foo1 (void) { return 1; }
++int __attribute__((noinline,noclone)) foo2 (void) { return 2; }
++int __attribute__((noinline,noclone)) foo3 (void) { return 3; }
++int __attribute__((noinline,noclone)) foo4 (void) { return 4; }
++int __attribute__((noinline,noclone)) foo5 (void) { return 5; }
++int __attribute__((noinline,noclone)) foo6 (void) { return 6; }
++int __attribute__((noinline,noclone)) foo7 (void) { return 7; }
++int __attribute__((noinline,noclone)) foo8 (void) { return 8; }
++int __attribute__((noinline,noclone)) foo9 (void) { return 9; }
++int __attribute__((noinline,noclone)) foo10 (void) { return 10; }
++int __attribute__((noinline,noclone)) foo11 (void) { return 11; }
++int __attribute__((noinline,noclone)) foo12 (void) { return 12; }
++int __attribute__((noinline,noclone)) foo13 (void) { return 13; }
++int __attribute__((noinline,noclone)) foo14 (void) { return 14; }
++int __attribute__((noinline,noclone)) foo15 (void) { return 15; }
++int __attribute__((noinline,noclone)) foo16 (void) { return 16; }
++int __attribute__((noinline,noclone)) foo17 (void) { return 17; }
++int __attribute__((noinline,noclone)) foo18 (void) { return 18; }
++int __attribute__((noinline,noclone)) foo19 (void) { return 19; }
++int __attribute__((noinline,noclone)) foo20 (void) { return 20; }
++
++
++int __attribute__((noinline,noclone))
++bar (int a)
++{
++  int ret = 0;
++
++  switch (a)
++    {
++    case 1: ret = foo1 (); break;
++    case 2: ret = foo2 (); break;
++    case 3: ret = foo3 (); break;
++    case 4: ret = foo4 (); break;
++    case 5: ret = foo5 (); break;
++    case 6: ret = foo6 (); break;
++    case 7: ret = foo7 (); break;
++    case 8: ret = foo8 (); break;
++    case 9: ret = foo9 (); break;
++    case 10: ret = foo10 (); break;
++    case 11: ret = foo11 (); break;
++    case 12: ret = foo12 (); break;
++    case 13: ret = foo13 (); break;
++    case 14: ret = foo14 (); break;
++    case 15: ret = foo15 (); break;
++    case 16: ret = foo16 (); break;
++    case 17: ret = foo17 (); break;
++    case 18: ret = foo18 (); break;
++    case 19: ret = foo19 (); break;
++    case 20: ret = foo20 (); break;
++    default:
++      __builtin_abort ();
++    }
++
++  return ret;
++}
++
++int
++main ()
++{
++  if (bar (3) != 3)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 1 x bar
++/* { dg-final { scan-assembler-times "ex\t" 1 } } */
++
++/* { dg-final { scan-assembler     "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_fromreg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_frommem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-return-reg-z10.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-return-reg-z10.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-return-reg-z10.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,41 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z10 --save-temps -mfunction-return-reg=thunk -mindirect-branch-table" } */
++
++int gl = 0;
++
++int __attribute__((noinline,noclone))
++bar (int a)
++{
++  return a + 2;
++}
++
++void __attribute__((noinline,noclone))
++foo (int a)
++{
++  int i;
++
++  if (a == 42)
++    return;
++
++  for (i = 0; i < a; i++)
++    gl += bar (i);
++}
++
++int
++main ()
++{
++  foo (3);
++  if (gl != 9)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 1 x bar
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 1 } } */
++/* { dg-final { scan-assembler "exrl" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler     "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-indirect-jump-z10.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-z10.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-indirect-jump-z10.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,43 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z10 --save-temps -mindirect-branch-jump=thunk -mindirect-branch-table" } */
++/* { dg-require-effective-target label_values } */
++
++/* This is a copy of the gcc.c-torture/execute/20040302-1.c
++   testcase.  */
++
++int code[]={0,0,0,0,1};
++
++void
++foo(int x) {
++  volatile int b;
++  b = 0xffffffff;
++}
++
++void
++bar(int *pc) {
++  static const void *l[] = {&&lab0, &&end};
++
++  foo(0);
++  goto *l[*pc];
++ lab0:
++  foo(0);
++  pc++;
++  goto *l[*pc];
++ end:
++  return;
++}
++
++int
++main() {
++  bar(code);
++  return 0;
++}
++
++/* 2x bar */
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 2 } } */
++/* { dg-final { scan-assembler "exrl" } } */
++
++/* { dg-final { scan-assembler     "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z10.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z10.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z10.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,78 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z10 -mzarch --save-temps -mindirect-branch-jump=thunk-inline -mindirect-branch-table" } */
++
++/* case-values-threshold will be set to 20 by the back-end when jump
++   thunk are requested.  */
++
++int __attribute__((noinline,noclone)) foo1 (void) { return 1; }
++int __attribute__((noinline,noclone)) foo2 (void) { return 2; }
++int __attribute__((noinline,noclone)) foo3 (void) { return 3; }
++int __attribute__((noinline,noclone)) foo4 (void) { return 4; }
++int __attribute__((noinline,noclone)) foo5 (void) { return 5; }
++int __attribute__((noinline,noclone)) foo6 (void) { return 6; }
++int __attribute__((noinline,noclone)) foo7 (void) { return 7; }
++int __attribute__((noinline,noclone)) foo8 (void) { return 8; }
++int __attribute__((noinline,noclone)) foo9 (void) { return 9; }
++int __attribute__((noinline,noclone)) foo10 (void) { return 10; }
++int __attribute__((noinline,noclone)) foo11 (void) { return 11; }
++int __attribute__((noinline,noclone)) foo12 (void) { return 12; }
++int __attribute__((noinline,noclone)) foo13 (void) { return 13; }
++int __attribute__((noinline,noclone)) foo14 (void) { return 14; }
++int __attribute__((noinline,noclone)) foo15 (void) { return 15; }
++int __attribute__((noinline,noclone)) foo16 (void) { return 16; }
++int __attribute__((noinline,noclone)) foo17 (void) { return 17; }
++int __attribute__((noinline,noclone)) foo18 (void) { return 18; }
++int __attribute__((noinline,noclone)) foo19 (void) { return 19; }
++int __attribute__((noinline,noclone)) foo20 (void) { return 20; }
++
++
++int __attribute__((noinline,noclone))
++bar (int a)
++{
++  int ret = 0;
++
++  switch (a)
++    {
++    case 1: ret = foo1 (); break;
++    case 2: ret = foo2 (); break;
++    case 3: ret = foo3 (); break;
++    case 4: ret = foo4 (); break;
++    case 5: ret = foo5 (); break;
++    case 6: ret = foo6 (); break;
++    case 7: ret = foo7 (); break;
++    case 8: ret = foo8 (); break;
++    case 9: ret = foo9 (); break;
++    case 10: ret = foo10 (); break;
++    case 11: ret = foo11 (); break;
++    case 12: ret = foo12 (); break;
++    case 13: ret = foo13 (); break;
++    case 14: ret = foo14 (); break;
++    case 15: ret = foo15 (); break;
++    case 16: ret = foo16 (); break;
++    case 17: ret = foo17 (); break;
++    case 18: ret = foo18 (); break;
++    case 19: ret = foo19 (); break;
++    case 20: ret = foo20 (); break;
++    default:
++      __builtin_abort ();
++    }
++
++  return ret;
++}
++
++int
++main ()
++{
++  if (bar (3) != 3)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 1 x bar
++/* { dg-final { scan-assembler-times "exrl" 1 } } */
++
++/* { dg-final { scan-assembler     "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_fromreg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_frommem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-return-reg-z900.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-return-reg-z900.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-return-reg-z900.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,41 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z900 --save-temps -mfunction-return-reg=thunk -mindirect-branch-table" } */
++
++int gl = 0;
++
++int __attribute__((noinline,noclone))
++bar (int a)
++{
++  return a + 2;
++}
++
++void __attribute__((noinline,noclone))
++foo (int a)
++{
++  int i;
++
++  if (a == 42)
++    return;
++
++  for (i = 0; i < a; i++)
++    gl += bar (i);
++}
++
++int
++main ()
++{
++  foo (3);
++  if (gl != 9)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 1 x bar
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 1 } } */
++/* { dg-final { scan-assembler "ex\t" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler     "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-return-attr-all.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-return-attr-all.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-return-attr-all.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,46 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z10 -mzarch --save-temps -mindirect-branch-table" } */
++
++int gl = 0;
++
++int __attribute__((noinline,noclone))
++bar (int a)
++{
++  return a + 2;
++}
++
++void __attribute__((function_return("thunk"),noinline,noclone))
++foo (int a)
++{
++  int i;
++
++  if (a == 42)
++    return;
++
++  for (i = 0; i < a; i++)
++    gl += bar (i);
++}
++
++int
++main ()
++{
++  foo (3);
++  if (gl != 9)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* With -march=z10 -mzarch the shrink wrapped returns use compare and
++   swap relative to jump to the exit block instead of making use of
++   the conditional return pattern.
++   FIXME: Use compare and branch register for that!!!! */
++
++/* 2 x foo
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 2 } } */
++/* { dg-final { scan-assembler "exrl" } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler     "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/s390/nobp-return-reg-mixed.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/nobp-return-reg-mixed.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/nobp-return-reg-mixed.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,44 @@
++/* { dg-do run } */
++/* { dg-options "-O3 -march=z900 --save-temps -mfunction-return-reg=thunk -mindirect-branch-table" } */
++
++/* We have to generate different thunks for indirect branches
++   depending on whether the code is compiled for pre z10 machines or
++   later.  This testcase makes sure this works within the same compile
++   unit.  */
++
++int __attribute__((noinline,noclone,target("arch=z10")))
++bar (int a)
++{
++  return a + 2;
++}
++
++int __attribute__((noinline,noclone,target("arch=z9-ec")))
++foo (int a)
++{
++  return a + 3;
++}
++
++int
++main ()
++{
++  if (bar (42) != 44)
++    __builtin_abort ();
++
++  if (foo (42) != 45)
++    __builtin_abort ();
++
++  return 0;
++}
++
++/* 1 x bar, 1 x foo */
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump" 2 } } */
++/* 1 x foo */
++/* { dg-final { scan-assembler-times "jg\t__s390_indirect_jump_r1use" 1 } } */
++
++/* { dg-final { scan-assembler-times "ex\t" 1 } } */
++/* { dg-final { scan-assembler-times "exrl\t" 1 } } */
++
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_jump" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_indirect_call" } } */
++/* { dg-final { scan-assembler     "section\t.s390_return_reg" } } */
++/* { dg-final { scan-assembler-not "section\t.s390_return_mem" } } */
+Index: gcc/testsuite/gcc.target/aarch64/pr71112.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/aarch64/pr71112.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr71112.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,10 @@
++/* PR target/71112.  */
++/* { dg-additional-options "-fpie" { target pie } } */
++
++extern int dbs[100];
++void f (int *);
++int nscd_init (void)
++{
++  f (dbs);
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/aarch64/pr81414.C
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/aarch64/pr81414.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr81414.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mcpu=cortex-a57" } */
++
++typedef __Float32x2_t float32x2_t;
++float32x2_t
++foo1 (float32x2_t __a, float32x2_t __b, float32x2_t __c) {
++  return __b * __c + __a;
++}
++
+Index: gcc/testsuite/gcc.target/aarch64/pr83370.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/aarch64/pr83370.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr83370.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,22 @@
++/* { dg-do run } */
++/* { dg-options "-O2" } */
++
++typedef void (*fun) (void);
++
++void
++f (fun x1)
++{
++  register fun x2 asm ("x16");
++  int arr[5000];
++  int *volatile ptr = arr;
++  asm ("mov %0, %1" : "=r" (x2) : "r" (x1));
++  x2 ();
++}
++
++void g (void) {}
++
++int
++main (void)
++{
++  f (g);
++}
+Index: gcc/testsuite/gcc.target/i386/pr82990-7.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr82990-7.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr82990-7.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=skylake-avx512 -mtune=generic -mtune-ctrl=^emit_vzeroupper" } */
++
++#include "pr82941-1.c"
++
++/* { dg-final { scan-assembler-not "vzeroupper" } } */
+Index: gcc/testsuite/gcc.target/i386/pr84310-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr84310-2.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr84310-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -malign-loops=16" } */
++/* { dg-warning "is obsolete" "" { target *-*-* } 0 } */
++
++void
++c (void)
++{
++  for (;;)
++    ;
++}
+Index: gcc/testsuite/gcc.target/i386/pr81471.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr81471.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr81471.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,13 @@
++/* PR target/81471 */
++/* { dg-do compile { target { ! ia32 } } } */
++/* { dg-options "-O2 -mbmi2" } */
++
++static inline unsigned int rotl (unsigned int x, int k)
++{
++  return (x << k) | (x >> (32 - k));
++}
++
++unsigned long long test (unsigned int z)
++{
++  return rotl (z, 55);
++}
+Index: gcc/testsuite/gcc.target/i386/pr82990-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr82990-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr82990-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=knl -mvzeroupper" } */
++
++#include <immintrin.h>
++
++extern __m512d y, z;
++
++void
++pr82941 ()
++{
++  z = y;
++}
++
++/* { dg-final { scan-assembler-times "vzeroupper" 1 } } */
+Index: gcc/testsuite/gcc.target/i386/pr81225.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr81225.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr81225.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,14 @@
++/* PR target/81225 */
++/* { dg-do compile } */
++/* { dg-options "-mavx512ifma -O3 -ffloat-store" } */
++
++long a[24];
++float b[4], c[24];
++int d;
++
++void
++foo ()
++{
++  for (d = 0; d < 24; d++)
++    c[d] = (float) d ? : b[a[d]];
++}
+Index: gcc/testsuite/gcc.target/i386/pr82990-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr82990-2.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr82990-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=skylake-avx512 -mno-vzeroupper" } */
++
++#include "pr82941-1.c"
++
++/* { dg-final { scan-assembler-not "vzeroupper" } } */
+Index: gcc/testsuite/gcc.target/i386/pr80569.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr80569.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr80569.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,9 @@
++/* PR target/80569 */
++/* { dg-do assemble } */
++/* { dg-options "-O2 -m16 -march=haswell" } */
++
++void load_kernel(void *setup_addr)
++{
++    unsigned int seg = (unsigned int)setup_addr >> 4;
++    asm("movl %0, %%es" : : "r"(seg));
++}
+Index: gcc/testsuite/gcc.target/i386/pr82942-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr82942-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr82942-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++/* { dg-do compile } */
++/* { dg-options "-mavx512f -mno-avx512er -O2" } */
++
++#include "pr82941-1.c"
++
++/* { dg-final { scan-assembler-times "vzeroupper" 1 } } */
+Index: gcc/testsuite/gcc.target/i386/i386.exp
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/i386.exp	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/i386.exp	(.../branches/gcc-6-branch)
+@@ -255,18 +255,6 @@
+     } "-mrtm" ]
+ }
+ 
+-# Return 1 if avx512f instructions can be compiled.
+-proc check_effective_target_avx512f { } {
+-    return [check_no_compiler_messages avx512f object {
+-	typedef long long __v8di __attribute__ ((__vector_size__ (64)));
+-	__v8di
+-	mm512_and_epi64  (__v8di __X, __v8di __Y)
+-	{
+-            return __builtin_ia32_pandq512_mask (__X, __Y, __X, -1);
+-	}
+-    } "-mavx512f" ]
+-}
+-
+ # Return 1 if avx512vl instructions can be compiled.
+ proc check_effective_target_avx512vl { } {
+     return [check_no_compiler_messages avx512vl object {
+Index: gcc/testsuite/gcc.target/i386/pr82990-3.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr82990-3.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr82990-3.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++/* { dg-do compile } */
++/* { dg-options "-mavx512f -mavx512er -mvzeroupper -O2" } */
++
++#include "pr82941-1.c"
++
++/* { dg-final { scan-assembler-times "vzeroupper" 1 } } */
+Index: gcc/testsuite/gcc.target/i386/pr82942-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr82942-2.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr82942-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++/* { dg-do compile } */
++/* { dg-options "-mavx512f -mavx512er -mtune=knl -O2" } */
++
++#include "pr82941-1.c"
++
++/* { dg-final { scan-assembler-not "vzeroupper" } } */
+Index: gcc/testsuite/gcc.target/i386/pr81641.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr81641.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr81641.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,11 @@
++/* PR target/81641 */
++/* { dg-do assemble } */
++/* { dg-options "-O -masm=intel" } */
++/* { dg-require-effective-target masm_intel } */
++
++int test(void)
++{
++  int __seg_fs *f = (int __seg_fs *)16;
++  int __seg_gs *g = (int __seg_gs *)16;
++  return *f + *g;
++}
+Index: gcc/testsuite/gcc.target/i386/pr81300.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr81300.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr81300.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,30 @@
++/* PR target/81300 */
++/* { dg-do run { target { ! ia32 } } } */
++/* { dg-options "-O2" } */
++
++int
++__attribute__((noinline, noclone))
++foo (void)
++{
++  unsigned long long _discard = 0, zero = 0, maxull = 0;
++  unsigned char zero1 = __builtin_ia32_addcarryx_u64 (0, 0, 0, &_discard);
++  unsigned char zero2 = __builtin_ia32_addcarryx_u64 (zero1, 0, 0, &zero);
++  __builtin_ia32_sbb_u64 (0x0, 2, -1, &_discard);
++  unsigned char one = __builtin_ia32_sbb_u64 (0, zero, 1, &maxull);
++  unsigned long long x = __builtin_ia32_sbb_u64 (one, zero2, 0, &_discard);
++
++  unsigned long long z1 = 0;
++  __asm__ ("mov{q}\t{%1, %0|%0, %1}" : "+r" (z1) : "r" (x));
++  unsigned long long z2 = 3;
++  __asm__ ("mov{q}\t{%1, %0|%0, %1}" : "+r" (z2) : "r" (x));
++
++  return 1 - (z1 | z2);
++}
++
++int main ()
++{
++  if (foo ())
++    __builtin_abort ();
++
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/i386/pr82990-4.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr82990-4.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr82990-4.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++/* { dg-do compile } */
++/* { dg-options "-mavx512f -mno-avx512er -mno-vzeroupper -O2" } */
++
++#include "pr82941-1.c"
++
++/* { dg-final { scan-assembler-not "vzeroupper" } } */
+Index: gcc/testsuite/gcc.target/i386/pr82941-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr82941-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr82941-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=skylake-avx512" } */
++
++#include <immintrin.h>
++
++extern __m512d y, z;
++
++void
++pr82941 ()
++{
++  z = y;
++}
++
++/* { dg-final { scan-assembler-times "vzeroupper" 1 } } */
+Index: gcc/testsuite/gcc.target/i386/pr82990-5.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr82990-5.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr82990-5.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mavx512f -mtune=generic" } */
++
++#include <immintrin.h>
++
++extern __m512d y, z;
++
++void
++pr82941 ()
++{
++  z = y;
++}
++
++/* { dg-final { scan-assembler-times "vzeroupper" 1 } } */
+Index: gcc/testsuite/gcc.target/i386/pr82941-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr82941-2.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr82941-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=knl" } */
++
++#include "pr82941-1.c"
++
++/* { dg-final { scan-assembler-not "vzeroupper" } } */
+Index: gcc/testsuite/gcc.target/i386/pr81766.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr81766.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr81766.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,5 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target lp64 } */
++/* { dg-options "-O2 -fPIE -mcmodel=large" } */
++
++int main() { return 0; }
+Index: gcc/testsuite/gcc.target/i386/pr84310.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr84310.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr84310.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -falign-functions=100000" } */
++/* { dg-error "is not between 0 and 65536" "" { target *-*-* } 0 } */
++
++void
++test_func (void)
++{
++}
+Index: gcc/testsuite/gcc.target/i386/pr82990-6.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr82990-6.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr82990-6.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=skylake-avx512 -mtune=knl" } */
++
++#include "pr82941-1.c"
++
++/* { dg-final { scan-assembler-not "vzeroupper" } } */
+Index: gcc/testsuite/gcc.target/i386/pr81128.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr81128.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr81128.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,65 @@
++/* PR ipa/81128 */
++/* { dg-do run } */
++/* { dg-options "-O3" } */
++/* { dg-require-ifunc "" } */
++
++
++#include <stdio.h>
++#include <stdlib.h>
++#include <time.h>
++
++int resolver_fn = 0;
++int resolved_fn = 0;
++
++static inline void
++do_it_right_at_runtime_A ()
++{
++  resolved_fn++;
++}
++
++static inline void
++do_it_right_at_runtime_B ()
++{
++  resolved_fn++;
++}
++
++static inline void do_it_right_at_runtime (void);
++
++void do_it_right_at_runtime (void)
++  __attribute__ ((ifunc ("resolve_do_it_right_at_runtime")));
++
++static void (*resolve_do_it_right_at_runtime (void)) (void)
++{
++  srand (time (NULL));
++  int r = rand ();
++  resolver_fn++;
++
++  /* Use intermediate variable to get a warning for non-matching
++   * prototype. */
++  typeof(do_it_right_at_runtime) *func;
++  if (r & 1)
++    func = do_it_right_at_runtime_A;
++  else
++    func = do_it_right_at_runtime_B;
++
++  return (void *) func;
++}
++
++int
++main (void)
++{
++  const unsigned int ITERS = 10;
++
++  for (int i = ITERS; i > 0; i--)
++    {
++      do_it_right_at_runtime ();
++    }
++
++  if (resolver_fn != 1)
++    __builtin_abort ();
++
++  if (resolved_fn != 10)
++    __builtin_abort ();
++
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-1-nov.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-1-nov.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-1-nov.c	(.../branches/gcc-6-branch)
+@@ -25,7 +25,7 @@
+ static __attribute__((always_inline)) int
+ foo1 (int *p1, ...)
+ {
+-  return foo2 (10, p1, __va_arg_pack ());
++  return foo2 (10, p1, __builtin_va_arg_pack ());
+ }
+ 
+ int prebuf[100];
+Index: gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-1-lbv.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-1-lbv.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-1-lbv.c	(.../branches/gcc-6-branch)
+@@ -28,7 +28,7 @@
+ static __attribute__((always_inline)) int
+ foo1 (int *p1, ...)
+ {
+-  return foo2 (10, p1, __va_arg_pack ());
++  return foo2 (10, p1, __builtin_va_arg_pack ());
+ }
+ 
+ int prebuf[100];
+Index: gcc/testsuite/gcc.target/i386/mpx/pr79987.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/mpx/pr79987.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/mpx/pr79987.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,5 @@
++/* { dg-do compile } */
++/* { dg-options "-fcheck-pointer-bounds -mmpx" } */
++
++extern void foo;
++void *bar = &foo; /* { dg-warning "taking address of expression of type .void." } */
+Index: gcc/testsuite/gcc.target/i386/mpx/mpx-os-support.h
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/mpx/mpx-os-support.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/mpx/mpx-os-support.h	(.../branches/gcc-6-branch)
+@@ -0,0 +1,16 @@
++/* Check if the OS supports executing MPX instructions.  */
++
++#define XCR_XFEATURE_ENABLED_MASK	0x0
++
++#define XSTATE_BNDREGS	0x8
++
++static int
++mpx_os_support (void)
++{
++  unsigned int eax, edx;
++  unsigned int ecx = XCR_XFEATURE_ENABLED_MASK;
++
++  __asm__ ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (ecx));
++
++  return (eax & XSTATE_BNDREGS) != 0;
++}
+Index: gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-1-ubv.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-1-ubv.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-1-ubv.c	(.../branches/gcc-6-branch)
+@@ -28,7 +28,7 @@
+ static __attribute__((always_inline)) int
+ foo1 (int *p1, ...)
+ {
+-  return foo2 (10, p1, __va_arg_pack ());
++  return foo2 (10, p1, __builtin_va_arg_pack ());
+ }
+ 
+ int prebuf[100];
+Index: gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-2-nov.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-2-nov.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-2-nov.c	(.../branches/gcc-6-branch)
+@@ -27,7 +27,7 @@
+ static __attribute__((always_inline)) int
+ foo1 (int *p1, ...)
+ {
+-  return foo2 (10, p1, __va_arg_pack ());
++  return foo2 (10, p1, __builtin_va_arg_pack ());
+ }
+ 
+ int prebuf[100];
+Index: gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-2-lbv.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-2-lbv.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-2-lbv.c	(.../branches/gcc-6-branch)
+@@ -30,7 +30,7 @@
+ static __attribute__((always_inline)) int
+ foo1 (int *p1, ...)
+ {
+-  return foo2 (10, p1, __va_arg_pack ());
++  return foo2 (10, p1, __builtin_va_arg_pack ());
+ }
+ 
+ int prebuf[100];
+Index: gcc/testsuite/gcc.target/i386/mpx/mpx-check.h
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/mpx/mpx-check.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/mpx/mpx-check.h	(.../branches/gcc-6-branch)
+@@ -1,8 +1,8 @@
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <assert.h>
+-
+ #include "cpuid.h"
++#include "mpx-os-support.h"
+ 
+ static int
+ __attribute__ ((noinline))
+@@ -16,18 +16,25 @@
+ 
+ #define DEBUG
+ 
++static int
++check_osxsave (void)
++{
++  unsigned int eax, ebx, ecx, edx;
++
++  __cpuid (1, eax, ebx, ecx, edx);
++  return (ecx & bit_OSXSAVE) != 0;
++}
++
+ int
+ main (int argc, const char **argv)
+ {
+   unsigned int eax, ebx, ecx, edx;
+ 
+-  if (__get_cpuid_max (0, NULL) < 7)
+-    return 0;
++  if (!__get_cpuid_count (7, 0, &eax, &ebx, &ecx, &edx))
++    return NORUNRES;
+ 
+-  __cpuid_count (7, 0, eax, ebx, ecx, edx);
+-
+   /* Run MPX test only if host has MPX support.  */
+-  if (ebx & bit_MPX)
++  if (check_osxsave () && (ebx & bit_MPX) && mpx_os_support ())
+     mpx_test (argc, argv);
+   else
+     {
+Index: gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-2-ubv.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-2-ubv.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/mpx/va-arg-pack-2-ubv.c	(.../branches/gcc-6-branch)
+@@ -30,7 +30,7 @@
+ static __attribute__((always_inline)) int
+ foo1 (int *p1, ...)
+ {
+-  return foo2 (10, p1, __va_arg_pack ());
++  return foo2 (10, p1, __builtin_va_arg_pack ());
+ }
+ 
+ int prebuf[100];
+Index: gcc/testsuite/gcc.target/i386/pr81375.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr81375.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr81375.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++/* PR target/81375 */
++/* { dg-do compile { target ia32 } } */
++/* { dg-options "-mno-80387 -mno-sse -mfpmath=sse" } */
++
++float foo (float a, float b)
++{
++  return a / b;
++}
+Index: gcc/testsuite/lib/prune.exp
+===================================================================
+--- a/src/gcc/testsuite/lib/prune.exp	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/lib/prune.exp	(.../branches/gcc-6-branch)
+@@ -28,7 +28,7 @@
+ 
+     #send_user "Before:$text\n"
+ 
+-    regsub -all "(^|\n)(\[^\n\]*: )?In ((static member |lambda )?function|member|method|(copy )?constructor|destructor|instantiation|substitution|program|subroutine|block-data)\[^\n\]*" $text "" text
++    regsub -all "(^|\n)(\[^\n\]*: \[iI\]|I)n ((static member |lambda )?function|member|method|(copy )?constructor|destructor|instantiation|substitution|program|subroutine|block-data)\[^\n\]*" $text "" text
+     regsub -all "(^|\n)\[^\n\]*(: )?At (top level|global scope):\[^\n\]*" $text "" text
+     regsub -all "(^|\n)\[^\n\]*:   (recursively )?required \[^\n\]*" $text "" text
+     regsub -all "(^|\n)\[^\n\]*:   . skipping \[0-9\]* instantiation contexts \[^\n\]*" $text "" text
+Index: gcc/testsuite/lib/target-supports.exp
+===================================================================
+--- a/src/gcc/testsuite/lib/target-supports.exp	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/lib/target-supports.exp	(.../branches/gcc-6-branch)
+@@ -1060,8 +1060,8 @@
+ 	return 1;
+     }
+     if { [istarget *-*-solaris2.1\[1-9\]*] } {
+-	# Full PIE support was added in Solaris 11.x and Solaris 12, but gcc
+-	# errors out if missing, so check for that.
++	# Full PIE support was added in Solaris 11.3, but gcc errors out
++	# if missing, so check for that.
+ 	return [check_no_compiler_messages pie executable {
+ 	    int main (void) { return 0; }
+ 	} "-pie -fpie"]
+@@ -6301,11 +6301,22 @@
+ proc check_effective_target_avx512f { } {
+     return [check_no_compiler_messages avx512f object {
+ 	typedef double __m512d __attribute__ ((__vector_size__ (64)));
++	typedef double __m128d __attribute__ ((__vector_size__ (16)));
+ 
+ 	__m512d _mm512_add (__m512d a)
+ 	{
+ 	  return __builtin_ia32_addpd512_mask (a, a, a, 1, 4);
+ 	}
++
++	__m128d _mm128_add (__m128d a)
++	{
++	  return __builtin_ia32_addsd_round (a, a, 8);
++	}
++
++	__m128d _mm128_getmant (__m128d a)
++	{
++	  return __builtin_ia32_getmantsd_round (a, a, 0, 8);
++	}
+     } "-O2 -mavx512f" ]
+ }
+ 
+Index: gcc/testsuite/gfortran.dg/pr83874.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/pr83874.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/pr83874.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,19 @@
++! { dg-do run }
++! PR fortran/83874
++! There was an ICE while initializing the character arrays
++!
++! Contributed by Harald Anlauf <anlauf@gmx.de>
++!
++program charinit
++  implicit none
++  type t
++     character(len=1) :: name
++  end type t
++  type(t), parameter :: z(2)= [ t ('a'), t ('b') ]
++  character(len=1), parameter :: names1(*) = z% name
++  character(len=*), parameter :: names2(2) = z% name
++  character(len=*), parameter :: names3(*) = z% name
++  if (.not. (names1(1) == "a" .and. names1(2) == "b")) call abort ()
++  if (.not. (names2(1) == "a" .and. names2(2) == "b")) call abort ()
++  if (.not. (names3(1) == "a" .and. names3(2) == "b")) call abort ()
++end program charinit
+Index: gcc/testsuite/gfortran.dg/submodule_23.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/submodule_23.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/submodule_23.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,29 @@
++! { dg-do compile }
++!
++! Test the fix for PR79402, in which the module procedure 'fun1' picked
++! up a spurious symbol for the dummy 'n' in the specification expression
++! for the result 'y'.
++!
++! Contributed by Chris Coutinho  <chrisbcoutinho@gmail.com>
++!
++module mod
++  interface myfun
++    module function fun1(n) result(y)
++      integer,  intent(in)    :: n
++      real, dimension(n)  :: y
++    end function fun1
++  end interface myfun
++
++end module mod
++
++submodule (mod) submod
++contains
++  module procedure fun1
++    integer :: i
++    y = [(float (i), i = 1, n)]
++  end procedure fun1
++end submodule
++
++  use mod
++  print *, fun1(10)
++end
+Index: gcc/testsuite/gfortran.dg/pr71085.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/pr71085.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/pr71085.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,12 @@
++! { dg-do compile }
++! PR 71085
++!
++! Testcase from PR by Vladimir Fuka <vladimir.fuka@gmail.com>
++!
++program pr71085
++  print *, f()
++contains
++  function f()
++    integer :: f(iargc()*10)
++  end
++end
+Index: gcc/testsuite/gfortran.dg/interface_40.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/interface_40.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/interface_40.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++! { dg-do compile }
++! PR fortran/78814
++! Code contributed by Gerhard Steinmetz
++program p
++   class(*) :: x  ! { dg-error " must be dummy, allocatable or pointer" }
++   print *, f(x)
++end
++
+Index: gcc/testsuite/gfortran.dg/pr70754.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/pr70754.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/pr70754.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,35 @@
++! { dg-do compile }
++! { dg-options "-Ofast" }
++module m
++  implicit none
++  private
++  save
++
++  integer, parameter, public :: &
++    ii4          = selected_int_kind(6), &
++    rr8          = selected_real_kind(13)
++
++  integer (ii4), dimension(40,40,199), public :: xyz
++  public :: foo
++contains
++  subroutine foo(a)
++    real (rr8), dimension(40,40), intent(out) :: a
++    real (rr8), dimension(40,40) :: b
++    integer (ii4), dimension(40,40) :: c
++    integer  i, j
++
++    do i=1,20
++      b(i,j) = 123 * a(i,j) + 34 * a(i,j+1) &
++             + 34 * a(i,j-1) + a(i+1,j+1) &
++             + a(i+1,j-1) + a(i-1,j+1) &
++             + a(i-1,j-1)
++      c(i,j) = 123
++    end do
++
++    where ((xyz(:,:,2) /= 0) .and. (c /= 0))
++      a = b/real(c)
++    elsewhere
++      a = 456
++    endwhere
++ end subroutine foo
++end module m
+Index: gcc/testsuite/gfortran.dg/equiv_pure.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/equiv_pure.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/equiv_pure.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,50 @@
++! { dg-do compile }
++module eq
++   implicit none
++   integer :: n1, n2
++   integer, dimension(2) :: a
++   equivalence (a(1), n1)
++   equivalence (a(2), n2)
++   common /a/ a
++end module eq
++
++module m
++   use eq
++   implicit none
++   type, public :: t
++     integer :: i
++   end type t
++end module m
++
++module p
++   implicit none
++   contains
++   pure integer function d(h)
++     use m
++     implicit none
++     integer, intent(in) :: h
++     d = h
++   end function
++end module p
++
++module q
++   implicit none
++   contains
++   pure integer function d(h)
++     use m, only : t
++     implicit none
++     integer, intent(in) :: h
++     d = h
++   end function
++end module q
++
++module r
++   implicit none
++   contains
++   pure integer function d(h)
++     use m, only : a          ! { dg-error "cannot be an EQUIVALENCE object" }
++     implicit none
++     integer, intent(in) :: h
++     d = h
++   end function
++end module r
+Index: gcc/testsuite/gfortran.dg/pr78619.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/pr78619.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/pr78619.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,21 @@
++! { dg-do compile }
++! { dg-options "-Werror -O3" }
++!
++! Tests the fix for PR78619, in which the recursive use of 'f' at line 13
++! caused an ICE.
++!
++! Contributed by Gerhard Steinmetz  <gerhard.steinmetz.fortran@t-online.de>
++!
++  print *, g(1.0) ! 'g' is OK
++contains
++  function f(x) result(z)
++    real :: x, z
++    z = sign(1.0, f) ! { dg-error "calling itself recursively|must be the same type" }
++  end
++  real function g(x)
++    real :: x
++    g = -1
++    g = -sign(1.0, g) ! This is OK.
++  end
++end
++! { dg-message "all warnings being treated as errors" "" { target *-*-* } 0 }
+Index: gcc/testsuite/gfortran.dg/warn_target_lifetime_3.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/warn_target_lifetime_3.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/warn_target_lifetime_3.f90	(.../branches/gcc-6-branch)
+@@ -3,7 +3,7 @@
+ !
+ ! PR fortran/55476
+ !
+-! Contribued by  Janus Weil
++! Contributed by Janus Weil
+ !
+ subroutine test
+   integer, pointer :: p
+Index: gcc/testsuite/gfortran.dg/transfer_simplify_11.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/transfer_simplify_11.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/transfer_simplify_11.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++! { dg-do run }
++! PR Fortran/82841
++!
++   integer, parameter :: N = 2
++   character(len=1) :: chr(N)
++   chr = transfer(repeat("x",ncopies=N),[character(len=1) ::], N)
++   if (chr(1) /= 'x' .and. chr(2) /= 'x') call abort
++end
+Index: gcc/testsuite/gfortran.dg/bad_automatic_objects_1.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/bad_automatic_objects_1.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/bad_automatic_objects_1.f90	(.../branches/gcc-6-branch)
+@@ -5,16 +5,18 @@
+ !
+ ! Contributed by Joost VandeVondele  <jv244@cam.ac.uk>
+ !
++! Error message update with patch for PR fortran/83633
++!
+ module foo
+   integer    ::  i
+ end module foo
+ module bar
+   use foo
+-  integer, dimension (i) :: j ! { dg-error "must have constant shape" }
++  integer, dimension (i) :: j ! { dg-error "array with nonconstant bounds" }
+   character (len = i) :: c1   ! { dg-error "must have constant character length" }
+ end module bar
+ program foobar
+   use foo
+-  integer, dimension (i) :: k ! { dg-error "must have constant shape" }
++  integer, dimension (i) :: k ! { dg-error "array with nonconstant bounds" }
+   character (len = i) :: c2   ! { dg-error "must have constant character length" }
+ end program foobar
+Index: gcc/testsuite/gfortran.dg/deallocate_error_4.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/deallocate_error_4.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/deallocate_error_4.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,10 @@
++! { dg-do compile }
++! PR fortran/82994
++! Code contributed by Gerhard Steinmetz
++program p
++   type t
++   end type
++   class(t) :: x  ! { dg-error "must be dummy, allocatable or pointer" }
++   allocate (x)   ! { dg-error "neither a data pointer nor an allocatable" }
++   deallocate (x) ! { dg-error "not a nonprocedure pointer nor an allocatable" }
++end
+Index: gcc/testsuite/gfortran.dg/statement_function_2.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/statement_function_2.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/statement_function_2.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,26 @@
++! { dg-do compile }
++! PR fortran/54223
++subroutine r(d)
++    implicit none
++    integer, optional :: d
++    integer :: h, q
++    q(d) = d + 1     ! statement function statement
++    h = q(d)
++end subroutine r
++
++subroutine s(x)
++    implicit none
++    integer, optional :: x
++    integer :: g, z
++    g(x) = x + 1     ! statement function statement
++    z = g()          ! { dg-error "Missing actual argument" }
++end subroutine s
++
++subroutine t(a)
++    implicit none
++    integer :: a
++    integer :: f, y
++    f(a) = a + 1     ! statement function statement
++    y = f()          ! { dg-error "Missing actual argument" }
++end subroutine t
++! { dg-prune-output " Obsolescent feature" }
+Index: gcc/testsuite/gfortran.dg/shape_9.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/shape_9.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/shape_9.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,16 @@
++! { dg-do  run }
++! { dg-require-effective-target lto }
++! { dg-options "-flto" }
++! Check that there are no warnings with LTO for a KIND argument.
++!
++program test
++   implicit none
++   real, allocatable :: x(:,:)
++
++   allocate(x(2,5))
++   if (any(shape(x) /= [ 2, 5 ])) call abort
++   if (any(shape(x,kind=1) /= [ 2, 5 ])) call abort
++   if (any(shape(x,kind=2) /= [ 2, 5 ])) call abort
++   if (any(shape(x,kind=4) /= [ 2, 5 ])) call abort
++   if (any(shape(x,kind=8) /= [ 2, 5 ])) call abort
++ end program test
+Index: gcc/testsuite/gfortran.dg/class_67.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/class_67.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/class_67.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,55 @@
++! { dg-do run }
++!
++! Test the fix for PR78990 in which the scalarization of the assignment
++! in the main program failed for two reasons: (i) The conversion of 'v1'
++! into a class actual was being done after the call to 'return_t1', giving
++! rise to the ICE reported in comment #1; and (ii) The 'info' descriptor,
++! required for scalarization was not set, which gave rise to the ICE noted
++! by the contributor.
++!
++! Contributed by Chris Macmackin  <cmacmackin@gmail.com>
++!
++module test_type
++  implicit none
++
++  type t1
++     integer :: i
++   contains
++     procedure :: assign
++     generic :: assignment(=) => assign
++  end type t1
++
++contains
++
++  elemental subroutine assign(this,rhs)
++    class(t1), intent(inout) :: this
++    class(t1), intent(in) :: rhs
++    this%i = rhs%i
++  end subroutine assign
++
++  function return_t1(arg)
++    class(t1), dimension(:), intent(in) :: arg
++    class(t1), dimension(:), allocatable :: return_t1
++    allocate(return_t1(size(arg)), source=arg)
++  end function return_t1
++
++  function return_t1_p(arg)
++    class(t1), dimension(:), intent(in), target :: arg
++    class(t1), dimension(:), pointer :: return_t1_p
++    return_t1_p => arg
++  end function return_t1_p
++end module test_type
++
++program test
++  use test_type
++  implicit none
++
++  type(t1), dimension(3) :: v1, v2
++  v1%i = [1,2,3]
++  v2 = return_t1(v1)
++  if (any (v2%i .ne. v1%i)) call abort
++
++  v1%i = [4,5,6]
++  v2 = return_t1_p(v1)
++  if (any (v2%i .ne. v1%i)) call abort
++end program test
+Index: gcc/testsuite/gfortran.dg/automatic_module_variable.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/automatic_module_variable.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/automatic_module_variable.f90	(.../branches/gcc-6-branch)
+@@ -1,10 +1,12 @@
+ ! { dg-do compile }
+ ! Tests fix for PR15976
+ !
++! Error message update with patch for PR fortran/83633
++!
+ module sd
+   integer, parameter :: n = 20
+   integer :: i(n)
+-  integer :: j(m) ! { dg-error "must have constant shape" }
++  integer :: j(m) ! { dg-error "array with nonconstant bounds" }
+   integer, pointer :: p(:)
+   integer, allocatable :: q(:)
+ contains
+Index: gcc/testsuite/gfortran.dg/allocate_assumed_charlen_1.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/allocate_assumed_charlen_1.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/allocate_assumed_charlen_1.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,28 @@
++! { dg-do run }
++!
++! PR82934: Segfault on compilation in trans-stmt.c:5919(8.0.0).
++! The original report only had one item in the allocate list. This
++! has been doubled up to verify that the correct string length is
++! is used in the allocation.
++!
++! Contributed by FortranFan on clf.
++!
++   character(len=42), allocatable :: foo
++   character(len=22), allocatable :: foofoo
++
++   call alloc( foo , foofoo)
++
++   if (len(foo) .ne. 42) call abort
++   if (len(foofoo) .ne. 22) call abort
++
++contains
++
++   subroutine alloc( bar, barbar )
++
++      character(len=*), allocatable :: bar, barbar
++
++      allocate( character(len=*) :: bar , barbar) ! <= Here!
++
++   end subroutine
++
++end
+Index: gcc/testsuite/gfortran.dg/allocate_with_typespec_7.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/allocate_with_typespec_7.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/allocate_with_typespec_7.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,14 @@
++! { dg-do compile }
++! PR Fortran/83093
++! Contributed by Gerhard Steinmetz  <gscfq at t-online dot de>
++program p
++   integer, parameter :: n(2) = [1,2]
++   real :: x = 2
++   character(:), allocatable :: z, zz, zzz
++   character(:), allocatable :: y, yy
++   allocate (character(a) :: z)     ! { dg-error "Scalar INTEGER expression" }
++   allocate (character(x) :: zz)    ! { dg-error "Scalar INTEGER expression" }
++   allocate (character((1.0)) :: z) ! { dg-error "Scalar INTEGER expression" }
++   allocate (character(y) :: y)     ! { dg-error "Scalar INTEGER expression" }
++   allocate (character(n(1:2)) :: y)! { dg-error "Scalar INTEGER expression" }
++end
+Index: gcc/testsuite/gfortran.dg/num_images_1.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/num_images_1.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/num_images_1.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,10 @@
++! { dg-do compile }
++! { dg-options "-fcoarray=single -std=f2008" }
++! PR  Fortran/80768
++!
++program foo
++   implicit none
++   integer k5
++   k5 = num_images(failed=.false.) ! { dg-error "argument to NUM_IMAGES" }
++   print *, k5
++end program foo
+Index: gcc/testsuite/gfortran.dg/coarray_8.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/coarray_8.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/coarray_8.f90	(.../branches/gcc-6-branch)
+@@ -145,7 +145,7 @@
+ 
+ subroutine tfgh()
+   integer :: i(2)
+-  DATA i/(i, i=1,2)/ ! { dg-error "Expected PARAMETER symbol" }
++  DATA i/(i, i=1,2)/ ! { dg-error "Syntax error in DATA" }
+   do i = 1, 5 ! { dg-error "cannot be an array" }
+   end do ! { dg-error "Expecting END SUBROUTINE" }
+ end subroutine tfgh
+@@ -153,7 +153,7 @@
+ subroutine tfgh2()
+   integer, save :: x[*]
+   integer :: i(2)
+-  DATA i/(x, x=1,2)/ ! { dg-error "Expected PARAMETER symbol" }
++  DATA i/(x, x=1,2)/ ! { dg-error "Syntax error in DATA" }
+   do x = 1, 5 ! { dg-error "cannot be a coarray" }
+   end do ! { dg-error "Expecting END SUBROUTINE" }
+ end subroutine tfgh2
+Index: gcc/testsuite/gfortran.dg/simplify_cshift_1.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/simplify_cshift_1.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/simplify_cshift_1.f90	(.../branches/gcc-6-branch)
+@@ -23,12 +23,12 @@
+    v = cshift(c, 2)
+    if (any(b /= v)) call abort
+ 
+-   ! Special cases shift = 0, size(a), 1-size(a)
++   ! Special cases shift = 0, size(a), size(a)
+    b = cshift([1, 2, 3, 4, 5], 0)
+    if (any(b /= a)) call abort
+    b = cshift([1, 2, 3, 4, 5], size(a))
+    if (any(b /= a)) call abort
+-   b = cshift([1, 2, 3, 4, 5], 1-size(a))
++   b = cshift([1, 2, 3, 4, 5], -size(a))
+    if (any(b /= a)) call abort
+ 
+    ! simplification of array arg.
+Index: gcc/testsuite/gfortran.dg/assumed_size_2.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/assumed_size_2.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/assumed_size_2.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,4 @@
++! { dg-do compile }
++subroutine foo(a)
++  dimension  a(*,*) ! { dg-error "Bad specification for assumed size array" }
++end
+Index: gcc/testsuite/gfortran.dg/pr81735.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/pr81735.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/pr81735.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,25 @@
++! { dg-do compile }
++! { dg-options "-fdump-tree-original" }
++!
++! Contributed by Danila  <flashmozzg@gmail.com>
++!
++program fooprog
++    implicit none
++    type FooType
++        integer, allocatable :: x
++    end type FooType
++
++    type(FooType), pointer :: bar
++
++    bar => foo()
++
++contains
++    function foo() result(res)
++        type(FooType), pointer :: res
++
++        character(:), allocatable :: rt
++        rt = ""
++        res => null()
++    end function foo
++end program fooprog
++! { dg-final { scan-tree-dump-times "__builtin_free" 1 "original" } }
+Index: gcc/testsuite/gfortran.dg/deallocate_error_3.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/deallocate_error_3.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/deallocate_error_3.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,9 @@
++! { dg-do compile }
++! PR fortran/82994
++! Code contributed by Gerhard Steinmetz
++program p
++   type t
++   end type
++   class(t) :: x  ! { dg-error "must be dummy, allocatable or pointer" }
++   deallocate (x) ! { dg-error "not a nonprocedure pointer nor an allocatable" }
++end
+Index: gcc/testsuite/gfortran.dg/statement_function_1.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/statement_function_1.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/statement_function_1.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,24 @@
++! { dg-do compile }
++! PR fortran/84276
++      subroutine stepns(hh, h, s, w)
++      real, intent(inout) :: h, hh, s
++      real, intent(out) :: w
++      real :: qofs
++      integer i
++      qofs(s) = s
++      w = qofs(hh + h)
++      i = 42
++      w = qofs(i)       ! { dg-error "Type mismatch in argument" }
++      end subroutine stepns
++
++      subroutine step(hh, h, s, w)
++      real, intent(inout) :: h, hh, s
++      real, intent(out) :: w
++      real :: qofs
++      integer i
++      qofs(s, i) = i * s
++      i = 42
++      w = qofs(hh, i)
++      w = qofs(i = i, s = hh) ! { dg-error "invalid in a statement function" }
++      end subroutine step
++! { dg-prune-output " Obsolescent feature" }
+Index: gcc/testsuite/gfortran.dg/matmul_18.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/matmul_18.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/matmul_18.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++! { dg-do run }
++program p
++   integer, parameter :: a(3,2) = 1
++   real, parameter :: b(2,3) = 2
++   real d(3,3)
++   d = 4
++   if (any(d /= matmul(a,b))) call abort
++end
+Index: gcc/testsuite/gfortran.dg/data_substring.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/data_substring.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/data_substring.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++! { dg-do compile }
++! PR fortran/30792
++character string*1025
++integer i
++data (string(i:i),i=1,1025)/1025*'?'/  ! { dg-error "Invalid substring" }
++end
+Index: gcc/testsuite/gfortran.dg/class_66.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/class_66.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/class_66.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,28 @@
++! { dg- do run }
++!
++! Test the fix for PR78641 in which an ICE occured on assignment
++! of a class array constructor to a derived type array.
++!
++! Contributed by Damian Rouson  <damian@sourceryinstitute.org>
++!
++  implicit none
++  type foo
++    integer :: i = 99
++  end type
++  type(foo) :: bar(4)
++  class(foo), allocatable :: barfoo
++
++  allocate(barfoo,source = f(11))
++  bar = [f(33), [f(22), barfoo], f(1)]
++  if (any (bar%i .ne. [33, 22, 11, 1])) call abort
++  deallocate (barfoo)
++
++contains
++
++  function f(arg) result(foobar)
++    class(foo), allocatable :: foobar
++    integer :: arg
++    allocate(foobar,source = foo(arg))
++  end function
++
++end program
+Index: gcc/testsuite/gfortran.dg/submodule_29.f08
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/submodule_29.f08	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/submodule_29.f08	(.../branches/gcc-6-branch)
+@@ -0,0 +1,56 @@
++! { dg-do run }
++!
++! Test the fix for PR80554 in which it was not recognised that the symbol 'i'
++! is host associated in the submodule 's' so that the new declaration in the
++! submodule was rejected.
++!
++! Contributed by Tamas Bela Feher  <tamas.bela.feher@ipp.mpg.de>
++!
++module M
++  implicit none
++  integer :: i = 0
++  character (100) :: buffer
++  interface
++    module subroutine write_i()
++    end subroutine
++  end interface
++  interface
++    module subroutine write_i_2()
++    end subroutine
++  end interface
++contains
++  subroutine foo
++    integer :: i
++  end
++end module
++
++submodule (M) S
++    integer :: i = 137
++  contains
++    module subroutine write_i()
++       write (buffer,*) i
++    end subroutine
++end submodule
++
++submodule (M:S) S2
++    integer :: i = 1037
++  contains
++    module subroutine write_i_2()
++       write (buffer,*) i
++    end subroutine
++end submodule
++
++program test_submod_variable
++  use M
++  implicit none
++  integer :: j
++  i = 42
++  call write_i
++  read (buffer, *) j
++  if (i .ne. 42) call abort
++  if (j .ne. 137) call abort
++  call write_i_2
++  read (buffer, *) j
++  if (i .ne. 42) call abort
++  if (j .ne. 1037) call abort
++end program
+Index: gcc/testsuite/gfortran.dg/coarray_43.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/coarray_43.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/coarray_43.f90	(.../branches/gcc-6-branch)
+@@ -1,5 +1,6 @@
+ ! { dg-do link }
+ ! { dg-options "-fcoarray=lib -lcaf_single" }
++! { dg-additional-options "-latomic" { target libatomic_available } }
+ 
+ program coarray_43
+   implicit none
+Index: gcc/testsuite/gfortran.dg/deferred_character_18.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/deferred_character_18.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/deferred_character_18.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,29 @@
++! { dg-do compile }
++! PR Fortran/82367
++! Contributed by Walter Spector <w6ws at earthlink dot net>
++module cls_allocmod
++  implicit none
++
++contains
++
++ subroutine cls_alloc (n, str)
++    integer,  intent(in) :: n
++    character(*), allocatable, intent(out) :: str
++!  Note: Star ^ should have been a colon (:)
++
++    allocate (character(n)::str)
++
++  end subroutine
++
++end module
++
++program cls
++  use cls_allocmod
++  implicit none
++
++  character(:), allocatable :: s
++
++  call cls_alloc(42, s) ! { dg-error "allocatable or pointer dummy argument" }
++  print *, 'string len =', len(s)
++
++end program
+Index: gcc/testsuite/gfortran.dg/pr84734.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/pr84734.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/pr84734.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,4 @@
++! { dg-do compile }
++! PR fortran/84734
++   integer :: b(huge(1_8)+1_8) = 0 ! { dg-error "Arithmetic overflow" }
++   end
+Index: gcc/testsuite/gfortran.dg/pr69739.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/pr69739.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/pr69739.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,39 @@
++! { dg-do run }
++!
++! Test the fix for PR69739 in which the statement
++! R = operate(A, X) caused an ICE.
++!
++! Contributed by John  <jwmwalrus@gmail.com>
++!
++module test
++
++  implicit none
++  type, public :: sometype
++    real :: a    =  0.
++  end type
++contains
++
++  function dosomething(A) result(r)
++    type(sometype), intent(IN) :: A(:,:,:)
++    integer :: N
++    real, allocatable ::   R(:), X(:)
++
++    N = PRODUCT(UBOUND(A))
++    allocate (R(N),X(N))
++    X = [(real(N), N = 1, size(X, 1))]
++    R = operate(A, X)
++  end function
++
++  function operate(A, X)
++    type(sometype), intent(IN) :: A(:,:,:)
++    real, intent(IN) :: X(:)
++    real :: operate(1:PRODUCT(UBOUND(A)))
++
++    operate = x
++  end function
++end module test
++
++  use test
++  type(sometype) :: a(2, 2, 2)
++  if (any(int (dosomething(a)) .ne. [1,2,3,4,5,6])) call abort
++end
+Index: gcc/testsuite/gfortran.dg/inquire_19.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/inquire_19.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/inquire_19.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,13 @@
++! { dg-do run }
++! PR84506  INQUIRE(pos=) always sets pos=0 with -fdefault-integer-8
++program TestInquire
++   implicit none
++   integer(8) :: iUnit
++   integer(8) :: iPos
++   open(newunit=iunit, file='output.txt', access='stream', status='replace')
++   write(iUnit) 'TEXT'
++   inquire(iUnit, pos=iPos)
++   close(iUnit, status='delete')
++   !print *, iPos
++   if (iPos.ne.5) stop 1
++end program TestInquire
+Index: gcc/testsuite/gfortran.dg/allocatable_function_10.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/allocatable_function_10.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/allocatable_function_10.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,46 @@
++! { dg-do run }
++!
++! Test the fix for PR78293. The deallocations are present at the
++! end of the main programme to aid memory leak searching. The
++! allocation in 'tt' leaked memory from an intermediate temporary
++! for the array constructor.
++!
++! Contributed by Andrew Benson  <abensonca@gmail.com>
++!
++module m
++  implicit none
++
++  type t
++     integer, allocatable, dimension(:) :: r
++  end type t
++
++contains
++
++  function tt(a,b)
++    implicit none
++    type(t), allocatable, dimension(:) :: tt
++    type(t), intent(in), dimension(:) :: a,b
++    allocate(tt, source = [a,b])
++  end function tt
++
++  function ts(arg)
++    implicit none
++    type(t), allocatable, dimension(:) :: ts
++    integer, intent(in) :: arg(:)
++    allocate(ts(1))
++    allocate(ts(1)%r, source = arg)
++    return
++  end function ts
++
++end module m
++
++program p
++  use m
++  implicit none
++  type(t), dimension(2) :: c
++  c=tt(ts([99,199,1999]),ts([42,142]))
++  if (any (c(1)%r .ne. [99,199,1999])) call abort
++  if (any (c(2)%r .ne. [42,142])) call abort
++  deallocate(c(1)%r)
++  deallocate(c(2)%r)
++end program p
+Index: gcc/testsuite/gfortran.dg/matmul_17.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/matmul_17.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/matmul_17.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,9 @@
++! { dg-do run }
++! PR Fortran/83900
++! Contributed by Gerhard Steinmetz  <gscfq t t-online dot de>
++program p
++   integer, parameter :: a(3,2) = 1
++   real, parameter :: b(2,3) = 2
++   real, parameter :: c(3,3) = matmul(a, b)
++   if (any(c /= 4.)) call abort
++end
+Index: gcc/testsuite/gfortran.dg/statement_function_3.f
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/statement_function_3.f	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/statement_function_3.f	(.../branches/gcc-6-branch)
+@@ -0,0 +1,15 @@
++! { dg-do compile }
++! PR fortran/35299
++      subroutine phtod(e,n,i,h)
++      dimension e(n)
++      hstar(e,b)=b**.4*((1.25*fun(-e/40)+.18)) ! { dg-error "must be scalar" }
++      a = 1.
++      h = hstar(e(i-1), a)
++      end
++
++      function fun(a)
++         real a(*)
++         fun = 42
++      end
++! { dg-prune-output " Obsolescent feature" }
++
+Index: gcc/testsuite/gfortran.dg/zero_sized_7.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/zero_sized_7.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/zero_sized_7.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,18 @@
++! { dg-do compile }
++! PR 80118 - this used to ICE
++! Original test case by Marco Restelli
++module m
++implicit none
++
++  integer, parameter :: not_empty(1) = 0
++  integer, parameter :: empty1(0) = (/integer :: /)
++  integer, parameter :: empty2(0) = 0
++
++contains
++
++ subroutine sub(v)
++  integer, allocatable, intent(out) :: v(:)
++   v = 2*empty2 ! internal compiler error
++ end subroutine sub
++
++end module m
+Index: gcc/testsuite/gfortran.dg/explicit_shape_1.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/explicit_shape_1.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/explicit_shape_1.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,7 @@
++! { dg-do compile }
++! PR fortran/83633
++! Original testcase by Nathan T. Weeks  <weeks at iastate dot edu>
++!
++integer :: A(command_argument_count()) = 1 ! { dg-error "nonconstant bounds" }
++write (*,*) A
++end
+Index: gcc/testsuite/gfortran.dg/assumed_charlen_parameter.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/assumed_charlen_parameter.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/assumed_charlen_parameter.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,9 @@
++! { dg-do compile }
++! PR fortran/82049
++! Original code contributed by John Harper <john dot harper at vuw dot ac dot nz>
++program ice ! f2003
++  implicit none
++  character(*), parameter:: a = 'ice', b = '*'
++  character(*), parameter:: c(2) = [character(len(a)) :: a, b]
++  print "(2A4)",adjustr(c)
++end program ice
+Index: gcc/testsuite/gfortran.dg/pr70409.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/pr70409.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/pr70409.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,23 @@
++! { dg-do run }
++! PR fortran/70409
++! Contriubted by Harald Anlauf  <anlauf at gmx dot de>
++program foo
++  integer, parameter :: huge_1 = huge(0_1)
++  character(    huge_1      ), parameter :: x = 'abc'
++  character(    huge(0_1)   ), parameter :: y = 'abc'
++  character(    huge(0_1)+0 ), parameter :: z = 'abcdef'
++  character(    huge(0_1)   )            :: a = 'abc'
++  integer, parameter :: huge_2 = huge(0_2)
++  character(    huge_2      ), parameter :: u = 'abc'
++  character(    huge(0_2)   ), parameter :: v = 'abc'
++  character(int(huge(0_2),4)), parameter :: w = 'abcdef'
++  character(    huge(0_2)   )            :: b = 'abc'
++  if (len(x) /= huge_1) stop 1
++  if (len(y) /= huge_1) stop 2
++  if (len(z) /= huge_1) stop 3
++  if (len(a) /= huge_1) stop 4
++  if (len(u) /= huge_2) stop 5
++  if (len(v) /= huge_2) stop 6
++  if (len(w) /= huge_2) stop 7
++  if (len(b) /= huge_2) stop 8
++end program foo
+Index: gcc/testsuite/gfortran.dg/derived_init_4.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/derived_init_4.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/derived_init_4.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,59 @@
++! { dg-do run }
++!
++! Test the fix for PR81048, where in the second call to 'g2' the
++! default initialization was "forgotten". 'g1', 'g1a' and 'g3' check
++! that this does not occur for scalars and explicit results.
++!
++! Contributed by David Smith  <dm577216smith@gmail.com>
++!
++program test
++   type f
++       integer :: f = -1
++   end type
++   type(f) :: a, b(3)
++   type(f), allocatable :: ans
++   b = g2(a)
++   b = g2(a)
++   ans = g1(a)
++   if (ans%f .ne. -1) call abort
++   ans = g1(a)
++   if (ans%f .ne. -1) call abort
++   ans = g1a(a)
++   if (ans%f .ne. -1) call abort
++   ans = g1a(a)
++   if (ans%f .ne. -1) call abort
++   b = g3(a)
++   b = g3(a)
++contains
++   function g3(a) result(res)
++      type(f) :: a, res(3)
++      do j = 1, 3
++         if (res(j)%f == -1) then
++             res(j)%f = a%f - 1
++         else
++             call abort
++         endif
++      enddo
++   end function g3
++
++   function g2(a)
++      type(f) :: a, g2(3)
++      do j = 1, 3
++         if (g2(j)%f == -1) then
++             g2(j)%f = a%f - 1
++         else
++             call abort
++         endif
++      enddo
++   end function g2
++
++   function g1(a)
++     type(f) :: g1, a
++     if (g1%f .ne. -1 ) call abort
++   end function
++
++   function g1a(a) result(res)
++     type(f) :: res, a
++     if (res%f .ne. -1 ) call abort
++   end function
++end program test
+Index: gcc/testsuite/gfortran.dg/implied_do_2.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/implied_do_2.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/implied_do_2.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,7 @@
++! { dg-do compile }
++! PR fortran/56667
++program error_message
++   implicit none
++   integer :: ir
++   write(*,*) ( ir, ir = 1,10    ! { dg-error "Expected a right parenthesis" }
++end program error_message 
+Index: gcc/testsuite/gfortran.dg/class_array_15.f03
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/class_array_15.f03	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/class_array_15.f03	(.../branches/gcc-6-branch)
+@@ -115,4 +115,4 @@
+   bh => bhGet(b,instance=2)
+   if (loc (b) .ne. loc(bh%hostNode)) call abort
+ end
+-! { dg-final { scan-tree-dump-times "builtin_free" 11 "original" } }
++! { dg-final { scan-tree-dump-times "builtin_free" 12 "original" } }
+Index: gcc/testsuite/gfortran.dg/execute_command_line_3.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/execute_command_line_3.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/execute_command_line_3.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,23 @@
++! { dg-do  run }
++! PR 82233 - there were program aborts for some of these commands.
++! Original test case by Urban Jost.
++program boom
++implicit none
++integer                       :: i,j 
++character(len=256)            :: msg
++character(len=:), allocatable :: command
++   command='notthere'
++   msg='' ! seems to only be defined if exitstatus.ne.0
++   ! ok -- these work
++   call execute_command_line(command , wait=.false., exitstat=i, cmdstat=j, cmdmsg=msg)
++   if (j /= 0 .or. msg /= '') call abort
++   call execute_command_line(command ,               exitstat=i, cmdstat=j, cmdmsg=msg )
++   if (j /= 3 .or. msg /= "Invalid command line" ) call abort
++   msg = ''
++   call execute_command_line(command , wait=.false., exitstat=i,            cmdmsg=msg )
++   if (j /= 3) call abort
++   call execute_command_line(command , wait=.false., exitstat=i                        )
++   if (msg /= '') call abort
++   call execute_command_line(command ,               exitstat=i, cmdstat=j             )
++
++end program boom
+Index: gcc/testsuite/gfortran.dg/pr64124.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/pr64124.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/pr64124.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,5 @@
++! { dg-do compile }
++! PR fortran/64124.f90
++  character(len=kind(1)) x
++  integer(len(x)) y
++  end
+Index: gcc/testsuite/gfortran.dg/warn_target_lifetime_4.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/warn_target_lifetime_4.f90	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/warn_target_lifetime_4.f90	(.../branches/gcc-6-branch)
+@@ -0,0 +1,28 @@
++! { dg-do compile }
++! { dg-options "-Wtarget-lifetime" }
++!
++! PR fortran/81770: [5/6/7 Regression] Bogus warning: Pointer in pointer assignment might outlive the pointer target
++!
++! Contributed by Janus Weil <janus@gcc.gnu.org>
++
++module m
++
++   type t
++      integer, allocatable :: l
++   end type
++
++contains
++
++   subroutine sub(c_in, list)
++      type(t), target, intent(in)  :: c_in
++      integer, pointer, intent(out) :: list
++
++      type(t), pointer :: container
++
++      container => c_in
++
++      list => container%l
++
++   end subroutine
++
++end
+Index: gcc/testsuite/gcc.c-torture/execute/pr81555.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr81555.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr81555.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,24 @@
++/* PR tree-optimization/81555 */
++
++unsigned int a = 1, d = 0xfaeU, e = 0xe376U;
++_Bool b = 0, f = 1;
++unsigned char g = 1;
++
++void
++foo (void)
++{
++  _Bool c = a != b;
++  if (c)
++    f = 0;
++  if (e & c & (unsigned char)d & c)
++    g = 0;
++}
++
++int
++main ()
++{
++  foo ();
++  if (f || g != 1)
++    __builtin_abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.c-torture/execute/pr81503.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr81503.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr81503.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,15 @@
++unsigned short a = 41461;
++unsigned short b = 3419;
++int c = 0;
++
++void foo() {
++  if (a + b * ~(0 != 5))
++    c = -~(b * ~(0 != 5)) + 2147483647;
++}
++
++int main() {
++  foo();
++  if (c != 2147476810)
++    return -1;
++  return 0;
++}
+Index: gcc/testsuite/gcc.c-torture/execute/pr81556.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr81556.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr81556.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,23 @@
++/* PR tree-optimization/81556 */
++
++unsigned long long int b = 0xb82ff73c5c020599ULL;
++unsigned long long int c = 0xd4e8188733a29d8eULL;
++unsigned long long int d = 2, f = 1, g = 0, h = 0;
++unsigned long long int e = 0xf27771784749f32bULL;
++
++__attribute__((noinline, noclone)) void
++foo (void)
++{
++  _Bool a = d > 1;
++  g = f % ((d > 1) << 9);
++  h = a & (e & (a & b & c));
++}
++
++int
++main ()
++{
++  foo ();
++  if (g != 1 || h != 0)
++    __builtin_abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.c-torture/compile/pr82096.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/compile/pr82096.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr82096.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,11 @@
++/* { dg-require-effective-target arm_arch_v5t_ok { target arm*-*-* } } */
++/* { dg-skip-if "Do not combine float-abi values" { arm*-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
++/* { dg-additional-options "-march=armv5t -mthumb -mfloat-abi=soft" { target arm*-*-* } } */
++
++static long long AL[24];
++
++int
++check_ok (void)
++{
++  return (__sync_bool_compare_and_swap (AL+1, 0x200000003ll, 0x1234567890ll));
++}
+Index: gcc/testsuite/gcc.c-torture/compile/pr82549.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/compile/pr82549.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr82549.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,9 @@
++/* PR tree-optimization/82549 */
++
++int a, b[1];
++
++int
++main ()
++{
++  return !a || b[-2] || b[-2];
++}
+Index: gcc/testsuite/gcc.c-torture/compile/pr82337.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/compile/pr82337.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr82337.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,25 @@
++/* PR82337: SLSR needs to prevent abnormal SSA names from
++   serving as a basis. */
++char *a, *b, *c;
++
++struct d {
++  short e;
++  char f[];
++};
++
++extern void j (void);
++
++void
++g() {
++  struct d *h;
++  char *i;
++  int d;
++  do {
++    i = h->f + d;
++    20 ? j() : 0;
++    i = c;
++    if (__builtin_setjmp (h))
++      b = h->f + d;
++    d = (int)(*i);
++  } while (a);
++}
+Index: gcc/testsuite/gnat.dg/dispatch1.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/dispatch1.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/dispatch1.adb	(.../branches/gcc-6-branch)
+@@ -1,9 +0,0 @@
+--- { dg-do run }
+-
+-with dispatch1_p; use dispatch1_p;
+-procedure dispatch1 is
+-   O   : DT_I1;
+-   Ptr : access I1'Class;
+-begin
+-   Ptr := new I1'Class'(I1'Class (O));
+-end;
+Index: gcc/testsuite/gnat.dg/generic_dispatch_p.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/generic_dispatch_p.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/generic_dispatch_p.adb	(.../branches/gcc-6-branch)
+@@ -1,7 +0,0 @@
+-package body generic_dispatch_p is
+-   function Constructor (I : not null access Integer) return DT is
+-      R : DT; 
+-  begin
+-      return R;
+-   end Constructor;
+-end;
+Index: gcc/testsuite/gnat.dg/generic_dispatch_p.ads
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/generic_dispatch_p.ads	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/generic_dispatch_p.ads	(.../branches/gcc-6-branch)
+@@ -1,13 +0,0 @@
+-with Ada.Tags.Generic_Dispatching_Constructor;
+-package generic_dispatch_p is
+-   type Iface is interface;
+-   function Constructor (I : not null access Integer) return Iface is abstract;
+-   function Dispatching_Constructor
+-      is new Ada.Tags.Generic_Dispatching_Constructor
+-               (T           => Iface,
+-                Parameters  => Integer,
+-                Constructor => Constructor);
+-   type DT is new Iface with null record; 
+-   overriding
+-   function Constructor (I : not null access Integer) return DT;
+-end;
+Index: gcc/testsuite/gnat.dg/dispatch1_p.ads
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/dispatch1_p.ads	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/dispatch1_p.ads	(.../branches/gcc-6-branch)
+@@ -1,4 +0,0 @@
+-package dispatch1_p is
+-   type I1 is interface;
+-   type DT_I1 is new I1 with null record;
+-end;
+Index: gcc/testsuite/gnat.dg/dispatch2.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/dispatch2.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/dispatch2.adb	(.../branches/gcc-6-branch)
+@@ -1,10 +0,0 @@
+---  { dg-do run }
+-
+-with dispatch2_p; use dispatch2_p;
+-procedure dispatch2 is
+-   Obj : Object_Ptr := new Object;
+-begin
+-   if Obj.Get_Ptr /= Obj.Impl_Of then
+-      raise Program_Error;
+-   end if;
+-end;
+Index: gcc/testsuite/gnat.dg/generic_dispatch.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/generic_dispatch.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/generic_dispatch.adb	(.../branches/gcc-6-branch)
+@@ -1,9 +0,0 @@
+---  { dg-do run }
+-
+-with generic_dispatch_p; use generic_dispatch_p;
+-procedure generic_dispatch is
+-   I : aliased Integer := 0;
+-   D : Iface'Class := Dispatching_Constructor (DT'Tag, I'access);
+-begin   
+-   null;   
+-end generic_dispatch;
+Index: gcc/testsuite/gnat.dg/dispatch2_p.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/dispatch2_p.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/dispatch2_p.adb	(.../branches/gcc-6-branch)
+@@ -1,7 +0,0 @@
+---
+-package body dispatch2_p is
+-  function Impl_Of (Self : access Object) return Object_Ptr is
+-  begin
+-    return Object_Ptr (Self);
+-  end Impl_Of;
+-end;
+Index: gcc/testsuite/gnat.dg/dispatch2_p.ads
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/dispatch2_p.ads	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/dispatch2_p.ads	(.../branches/gcc-6-branch)
+@@ -1,8 +0,0 @@
+-package dispatch2_p is
+-  type Object     is tagged null record;
+-  type Object_Ptr is access all Object'CLASS;
+---
+-  function Impl_Of (Self : access Object) return Object_Ptr;
+-  function Get_Ptr (Self : access Object) return Object_Ptr
+-    renames Impl_Of;
+-end;
+Index: gcc/testsuite/gnat.dg/opt55.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/opt55.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/opt55.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,20 @@
++-- { dg-do compile }
++-- { dg-options "-O" }
++
++package body Opt55 is
++
++   function Cond (B : Boolean; If_True, If_False : Date) return Date is
++   begin
++      if B then
++         return If_True;
++      else
++         return If_False;
++      end if;
++   end;
++
++   function F (C : Rec2; B : Boolean) return Date is
++   begin
++      return Cond (B, C.D1, C.D2);
++   end;
++
++end Opt55;
+Index: gcc/testsuite/gnat.dg/array29.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/array29.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/array29.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,26 @@
++-- { dg-do compile }
++-- { dg-options "-O" }
++
++package body Array29 is
++
++  procedure Copy (Src : in Matrix; Dst : out Matrix) is
++  begin
++    for I in Src'Range (1) loop
++      for J in Src'Range (2) loop
++        Dst (I, J) := Src (I, J);
++      end loop;
++    end loop;
++  end;
++
++  procedure Proc is
++    N : constant := 2;
++    FM1 : constant Matrix (1 .. N, 1 .. N) := ((1.0, 2.0), (3.0, 4.0));
++    FM2 : constant Matrix (1 .. N, 1 .. N) := ((1.0, 2.0), (3.0, 4.0));
++    A : constant array (1 .. 2) of Matrix (1 .. N, 1 .. N)
++      := (Matrix (FM1), Matrix (FM2));
++    Final : Matrix (1 .. N, 1 .. N);
++  begin
++    Copy (Src => A (1), Dst => Final);
++  end;
++
++end Array29;
+Index: gcc/testsuite/gnat.dg/opt55.ads
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/opt55.ads	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/opt55.ads	(.../branches/gcc-6-branch)
+@@ -0,0 +1,22 @@
++package Opt55 is
++
++   type Date is record
++      D : Float;
++   end record;
++
++   type Rec1 (Kind : Boolean := False) is record
++      case Kind is
++         when True => N : Natural;
++         when False => null;
++      end case;
++   end record;
++
++   type Rec2 (D : Positive) is record
++      R  : Rec1;
++      D1 : Date;
++      D2 : Date;
++   end record;
++
++   function F (C : Rec2; B : Boolean) return Date;
++
++end Opt55;
+Index: gcc/testsuite/gnat.dg/array29.ads
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/array29.ads	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/array29.ads	(.../branches/gcc-6-branch)
+@@ -0,0 +1,7 @@
++package Array29 is
++
++  type Matrix is array (Integer range <>, Integer range <>) of Long_Float;
++
++  procedure Proc;
++
++end Array29;
+Index: gcc/testsuite/gnat.dg/generic_disp.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/generic_disp.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/generic_disp.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,10 @@
++--  { dg-do run }
++
++with Generic_Disp_Pkg; use Generic_Disp_Pkg;
++
++procedure Generic_Disp is
++   I : aliased Integer := 0;
++   D : Iface'Class := Dispatching_Constructor (DT'Tag, I'access);
++begin   
++   null;   
++end Generic_Disp;
+Index: gcc/testsuite/gnat.dg/disp1.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/disp1.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/disp1.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,10 @@
++-- { dg-do run }
++
++with Disp1_Pkg; use Disp1_Pkg;
++
++procedure Disp1 is
++   O   : DT_I1;
++   Ptr : access I1'Class;
++begin
++   Ptr := new I1'Class'(I1'Class (O));
++end;
+Index: gcc/testsuite/gnat.dg/generic_disp_pkg.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/generic_disp_pkg.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/generic_disp_pkg.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,9 @@
++package body Generic_Disp_Pkg is
++
++   function Constructor (I : not null access Integer) return DT is
++      R : DT; 
++   begin
++      return R;
++   end Constructor;
++
++end Generic_Disp_Pkg;
+Index: gcc/testsuite/gnat.dg/object_overflow1.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/object_overflow1.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/object_overflow1.adb	(.../branches/gcc-6-branch)
+@@ -1,10 +1,12 @@
+ -- { dg-do compile }
+ 
++with Interfaces.C; use Interfaces.C;
++
+ procedure Object_Overflow1 is
+ 
+   procedure Proc (x : Boolean) is begin null; end;
+ 
+-  type Arr is array(Long_Integer) of Boolean;
++  type Arr is array(ptrdiff_t) of Boolean;
+   Obj : Arr; -- { dg-warning "Storage_Error" }
+ 
+ begin
+Index: gcc/testsuite/gnat.dg/generic_disp_pkg.ads
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/generic_disp_pkg.ads	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/generic_disp_pkg.ads	(.../branches/gcc-6-branch)
+@@ -0,0 +1,14 @@
++with Ada.Tags.Generic_Dispatching_Constructor;
++
++package Generic_Disp_Pkg is
++   type Iface is interface;
++   function Constructor (I : not null access Integer) return Iface is abstract;
++   function Dispatching_Constructor
++      is new Ada.Tags.Generic_Dispatching_Constructor
++               (T           => Iface,
++                Parameters  => Integer,
++                Constructor => Constructor);
++   type DT is new Iface with null record; 
++   overriding
++   function Constructor (I : not null access Integer) return DT;
++end Generic_Disp_Pkg;
+Index: gcc/testsuite/gnat.dg/disp2.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/disp2.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/disp2.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,11 @@
++--  { dg-do run }
++
++with Disp2_Pkg; use Disp2_Pkg;
++
++procedure Disp2 is
++   Obj : Object_Ptr := new Object;
++begin
++   if Obj.Get_Ptr /= Obj.Impl_Of then
++      raise Program_Error;
++   end if;
++end;
+Index: gcc/testsuite/gnat.dg/object_overflow2.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/object_overflow2.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/object_overflow2.adb	(.../branches/gcc-6-branch)
+@@ -1,10 +1,12 @@
+ -- { dg-do compile }
+ 
++with Interfaces.C; use Interfaces.C;
++
+ procedure Object_Overflow2 is
+ 
+   procedure Proc (x : Boolean) is begin null; end;
+ 
+-  type Arr is array(0 .. Long_Integer'Last) of Boolean;
++  type Arr is array(0 .. ptrdiff_t'Last) of Boolean;
+   Obj : Arr; -- { dg-warning "Storage_Error" }
+ 
+ begin
+Index: gcc/testsuite/gnat.dg/object_overflow3.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/object_overflow3.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/object_overflow3.adb	(.../branches/gcc-6-branch)
+@@ -1,10 +1,12 @@
+ -- { dg-do compile }
+ 
++with Interfaces.C; use Interfaces.C;
++
+ procedure Object_Overflow3 is
+ 
+   procedure Proc (x : Boolean) is begin null; end;
+ 
+-  type Arr is array(0 .. Long_Integer'Last) of Boolean;
++  type Arr is array(0 .. ptrdiff_t'Last) of Boolean;
+ 
+   type Rec is record
+     A : Arr;
+Index: gcc/testsuite/gnat.dg/opt69.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/opt69.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/opt69.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,28 @@
++-- { dg-do compile }
++-- { dg-options "-O" }
++
++with Ada.Text_IO;
++
++procedure Opt69 is
++
++   procedure Inner
++     (A : String := (1 .. 15 => ASCII.NUL);
++      B : String := (1 .. 5 => ASCII.NUL);
++      C : String := (1 .. 5 => ASCII.NUL))
++   is
++      Aa : String (1 .. 15);
++      Bb : String (1 .. 5);
++      Cc : String (1 .. 5);
++   begin
++      Aa := A;
++      Bb := B;
++      Cc := C;
++
++      Ada.Text_IO.Put_Line (Aa);
++      Ada.Text_IO.Put_Line (Bb);
++      Ada.Text_IO.Put_Line (Cc);
++   end;
++
++begin
++   Inner;
++end;
+Index: gcc/testsuite/gnat.dg/object_overflow4.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/object_overflow4.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/object_overflow4.adb	(.../branches/gcc-6-branch)
+@@ -1,14 +1,16 @@
+ -- { dg-do compile }
+ 
++with Interfaces.C; use Interfaces.C;
++
+ procedure Object_Overflow4 is
+ 
+   procedure Proc (x : Integer) is begin null; end;
+ 
+-  type Index is new Long_Integer range 0 .. Long_Integer'Last;
++  type Index_T is new ptrdiff_t range 0 .. ptrdiff_t'Last;
+ 
+-  type Arr is array(Index range <>) of Integer;
++  type Arr is array(Index_T range <>) of Integer;
+ 
+-  type Rec (Size: Index := 6) is record -- { dg-warning "Storage_Error" }
++  type Rec (Size: Index_T := 6) is record -- { dg-warning "Storage_Error" }
+     A: Arr (0..Size);
+   end record;
+ 
+Index: gcc/testsuite/gnat.dg/object_overflow5.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/object_overflow5.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/object_overflow5.adb	(.../branches/gcc-6-branch)
+@@ -1,14 +1,16 @@
+ -- { dg-do compile }
+ 
++with Interfaces.C; use Interfaces.C;
++
+ procedure Object_Overflow5 is
+ 
+   procedure Proc (c : Character) is begin null; end;
+ 
+-  type Index is new Long_Integer range 0 .. Long_Integer'Last;
++  type Index_T is new ptrdiff_t range 0 .. ptrdiff_t'Last;
+ 
+-  type Arr is array(Index range <>) of Character;
++  type Arr is array(Index_T range <>) of Character;
+ 
+-  type Rec (Size: Index := 6) is record -- { dg-warning "Storage_Error" }
++  type Rec (Size: Index_T := 6) is record -- { dg-warning "Storage_Error" }
+     A: Arr (0..Size);
+   end record;
+ 
+Index: gcc/testsuite/gnat.dg/array11.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/array11.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/array11.adb	(.../branches/gcc-6-branch)
+@@ -1,15 +1,17 @@
+ -- { dg-do compile }
+ 
++with System;
++
+ procedure Array11 is
+ 
+   type Rec is null record;
+-  type Ptr is access all Rec;
++  type Index_T is mod System.Memory_Size;
+ 
+-  type Arr1 is array (1..8) of aliased Rec; -- { dg-warning "padded" }
+-  type Arr2 is array (Long_Integer) of aliased Rec; -- { dg-warning "padded" }
++  type Arr1 is array (1 .. 8) of aliased Rec; -- { dg-warning "padded" }
++  type Arr2 is array (Index_T) of aliased Rec; -- { dg-warning "padded" }
+ 
+   A1 : Arr1;
+-  A2 : Arr2; -- { dg-warning "Storage_Error" }
++  A2 : Arr2;
+ 
+ begin
+   null;
+Index: gcc/testsuite/gnat.dg/alignment13.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/alignment13.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/alignment13.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,21 @@
++-- { dg-do run }
++-- { dg-options "-gnatws" }
++
++procedure Alignment13 is
++
++  type Rec is record
++    I1 : aliased Short_Integer;
++    I2 : Integer;
++  end record;
++
++  for Rec use record
++    I1 at 0 range 0 .. 15;
++  end record;
++
++  R : Rec;
++
++begin
++  if R.I2'Bit_Position /= 32 then
++    raise Program_Error;
++  end if;
++end;
+Index: gcc/testsuite/gnat.dg/disp1_pkg.ads
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/disp1_pkg.ads	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/disp1_pkg.ads	(.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++package Disp1_Pkg is
++
++   type I1 is interface;
++   type DT_I1 is new I1 with null record;
++
++end Disp1_Pkg;
+Index: gcc/testsuite/gnat.dg/disp2_pkg.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/disp2_pkg.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/disp2_pkg.adb	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++package body Disp2_Pkg is
++
++  function Impl_Of (Self : access Object) return Object_Ptr is
++  begin
++    return Object_Ptr (Self);
++  end Impl_Of;
++
++end Disp2_Pkg;
+Index: gcc/testsuite/gnat.dg/disp2_pkg.ads
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/disp2_pkg.ads	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/disp2_pkg.ads	(.../branches/gcc-6-branch)
+@@ -0,0 +1,11 @@
++package Disp2_Pkg is
++
++  type Object     is tagged null record;
++  type Object_Ptr is access all Object'CLASS;
++
++  function Impl_Of (Self : access Object) return Object_Ptr;
++  function Get_Ptr (Self : access Object) return Object_Ptr
++    renames Impl_Of;
++
++end Disp2_Pkg;
++
+Index: gcc/testsuite/gnat.dg/null_pointer_deref1.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/null_pointer_deref1.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/null_pointer_deref1.adb	(.../branches/gcc-6-branch)
+@@ -17,5 +17,5 @@
+ begin
+    Data.all := 1;
+ exception
+-   when Constraint_Error | Storage_Error => null;
++   when others => null;
+ end;
+Index: gcc/testsuite/gnat.dg/specs/uc2.ads
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/specs/uc2.ads	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/specs/uc2.ads	(.../branches/gcc-6-branch)
+@@ -0,0 +1,18 @@
++-- { dg-do compile }
++-- { dg-options "-O" }
++
++with Ada.Unchecked_Conversion;
++
++package UC2 is
++
++  subtype Word_Type is Integer range 0 .. 0;
++  type Arr is array (1 .. Word_Type'Size) of Boolean;
++  pragma Pack(Arr);
++
++  function Conv is
++     new Ada.Unchecked_Conversion (Source => Arr, Target => Word_Type);
++
++  A : Arr;
++  W : Word_Type := Conv(A);
++
++end UC2;
+Index: gcc/testsuite/gnat.dg/null_pointer_deref2.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/null_pointer_deref2.adb	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gnat.dg/null_pointer_deref2.adb	(.../branches/gcc-6-branch)
+@@ -20,7 +20,7 @@
+    begin
+       Data.all := 1;
+    exception
+-      when Constraint_Error | Storage_Error => null;
++      when others => null;
+    end T;
+ 
+ begin
+Index: gcc/testsuite/gcc.dg/pr82112.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr82112.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/pr82112.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,21 @@
++/* PR target/82112 */
++/* { dg-do compile } */
++/* { dg-options "-std=gnu90" } */
++
++struct S { int a[10]; } bar (void);
++int b, c;
++
++void
++foo (void)
++{
++  __atomic_load (bar ().a, &b, __ATOMIC_ACQUIRE);	/* { dg-error "argument 1 of .__atomic_load. must be a non-void pointer type" } */
++  __atomic_load (&b, bar ().a, __ATOMIC_ACQUIRE);	/* { dg-error "argument 2 of .__atomic_load. must be a pointer type" } */
++  __atomic_store (bar ().a, &b, __ATOMIC_SEQ_CST);	/* { dg-error "argument 1 of .__atomic_store. must be a non-void pointer type" } */
++  __atomic_store (&b, bar ().a, __ATOMIC_SEQ_CST);	/* { dg-error "argument 2 of .__atomic_store. must be a pointer type" } */
++  __atomic_exchange (bar ().a, &b, &c, __ATOMIC_RELAXED);	/* { dg-error "argument 1 of .__atomic_exchange. must be a non-void pointer type" } */
++  __atomic_exchange (&b, bar ().a, &c, __ATOMIC_RELAXED);	/* { dg-error "argument 2 of .__atomic_exchange. must be a pointer type" } */
++  __atomic_exchange (&b, &c, bar ().a, __ATOMIC_RELAXED);	/* { dg-error "argument 3 of .__atomic_exchange. must be a pointer type" } */
++  __atomic_compare_exchange (bar ().a, &b, &c, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED);	/* { dg-error "argument 1 of .__atomic_compare_exchange. must be a non-void pointer type" } */
++  __atomic_compare_exchange (&b, bar ().a, &c, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED);	/* { dg-error "argument 2 of .__atomic_compare_exchange. must be a pointer type" } */
++  __atomic_compare_exchange (&b, &c, bar ().a, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED);	/* { dg-error "argument 3 of .__atomic_compare_exchange. must be a pointer type" } */
++}
+Index: gcc/testsuite/gcc.dg/gomp/pr81768-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/gomp/pr81768-2.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/gomp/pr81768-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,15 @@
++/* PR middle-end/81768 */
++/* { dg-do compile } */
++
++float b[10][15][10];
++
++void
++foo (void)
++{
++  float *i;
++#pragma omp target parallel for schedule(static, 32) collapse(3)
++  for (i = &b[0][0][0]; i < &b[0][0][10]; i++)
++    for (float *j = &b[0][15][0]; j > &b[0][0][0]; j -= 10)
++      for (float *k = &b[0][0][10]; k > &b[0][0][0]; --k)
++        b[i - &b[0][0][0]][(j - &b[0][0][0]) / 10 - 1][(k - &b[0][0][0]) - 1] -= 3.5;
++}
+Index: gcc/testsuite/gcc.dg/gomp/pr81768-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/gomp/pr81768-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/gomp/pr81768-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,15 @@
++/* PR middle-end/81768 */
++/* { dg-do compile } */
++
++float b[10][15][10];
++
++void
++foo (void)
++{
++  float *i;
++#pragma omp target parallel for simd schedule(static, 32) collapse(3)
++  for (i = &b[0][0][0]; i < &b[0][0][10]; i++)
++    for (float *j = &b[0][15][0]; j > &b[0][0][0]; j -= 10)
++      for (float *k = &b[0][0][10]; k > &b[0][0][0]; --k)
++	b[i - &b[0][0][0]][(j - &b[0][0][0]) / 10 - 1][(k - &b[0][0][0]) - 1] -= 3.5;
++}
+Index: gcc/testsuite/gcc.dg/pr82274-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr82274-2.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/pr82274-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,22 @@
++/* PR target/82274 */
++/* { dg-do run } */
++/* { dg-options "-O2" } */
++
++int
++main ()
++{
++#ifdef __SIZEOF_INT128__
++  __int128 m = -(((__int128) 1) << (__CHAR_BIT__ * __SIZEOF_INT128__ / 2));
++  volatile __int128 mv = m;
++  __int128 r;
++#else
++  long long m = -(1LL << (__CHAR_BIT__ * __SIZEOF_LONG_LONG__ / 2));
++  volatile long long mv = m;
++  long long r;
++#endif
++  if (!__builtin_mul_overflow (mv, mv, &r))
++    __builtin_abort ();
++  if (!__builtin_mul_overflow (m, m, &r))
++    __builtin_abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.dg/debug/dwarf2/prod-options.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/debug/dwarf2/prod-options.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/debug/dwarf2/prod-options.c	(.../branches/gcc-6-branch)
+@@ -3,9 +3,8 @@
+    the build not reproducible.  Other skipped options could be tested here
+    as well.  */
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -gdwarf -dA -fdebug-prefix-map=a=b" } */
+-/* { dg-final { scan-assembler "DW_AT_producer: \"GNU C" { target { { { ! *-*-solaris2* } || gas } && { ! hppa*64*-*-* } } } } } */
+-/* { dg-final { scan-assembler "\"GNU C\[^\\n\\r\]+ DW_AT_producer" { target { { *-*-solaris2* && { ! gas } } || { hppa*64*-*-* } } } } } */
++/* { dg-options "-O2 -gdwarf -dA -fno-merge-debug-strings -fdebug-prefix-map=a=b" } */
++/* { dg-final { scan-assembler "\"GNU C\[^\\n\\r\]+ DW_AT_producer" } } */
+ /* { dg-final { scan-assembler-not "debug-prefix-map" } } */
+ 
+ void func (void)
+Index: gcc/testsuite/gcc.dg/ubsan/pr81162.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/ubsan/pr81162.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/ubsan/pr81162.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,17 @@
++/* PR tree-optimization/81162 */
++/* { dg-do run } */
++/* { dg-options "-fsanitize=undefined -O2" } */
++
++short s;
++int i1 = 1;
++int i2 = 1;
++unsigned char uc = 147;
++
++int main() {
++  s = (-uc + 2147483647) << 0;
++  if (9031239389974324562ULL >= (-((i1 && i2) + uc) ^ -21096) ) {
++    return 0;
++  } else {
++    return -1;
++  }
++}
+Index: gcc/testsuite/gcc.dg/ubsan/pr81505.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/ubsan/pr81505.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/ubsan/pr81505.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O3 -fsanitize=signed-integer-overflow" } */
++
++int a, b, c, h;
++
++int i[5][5];
++
++void
++fn1 ()
++{
++  int l = 0;
++
++  for (a = 0; a <= 3; a++)
++    for (b = 1; b >= 0; b -= 1)
++      l |= i[0][b];
++  c = l;
++}
+Index: gcc/testsuite/gcc.dg/pr83424.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr83424.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/pr83424.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,30 @@
++/* PR rtl-optimization/83424 */
++/* { dg-do run { target int128 } } */
++/* { dg-options "-O -fno-tree-ccp -fno-tree-coalesce-vars" } */
++
++typedef unsigned char u8;
++typedef unsigned int u32;
++typedef unsigned __int128 u128;
++
++u32 a, c;
++u8 b;
++
++static u128 __attribute__ ((noinline, noclone))
++foo (u128 p)
++{
++  u8 x = ~b;
++  p &= c;
++  x *= -p;
++  x &= a == 0;
++  x >>= 1;
++  return p + x;
++}
++
++int
++main (void)
++{
++  u128 x = foo (0);
++  if (x != 0)
++    __builtin_abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.dg/pr79499.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr79499.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/pr79499.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,13 @@
++/* PR middle-end/79499 */
++/* { dg-do compile { target split_stack } } */
++/* { dg-options "-O2 -fsplit-stack -fno-omit-frame-pointer" } */
++
++struct S { struct S *a, *b; };
++
++void
++foo (struct S *x)
++{
++  do
++    x->b = x->a;
++  while (x = x->a);
++}
+Index: gcc/testsuite/gcc.dg/pr81621.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr81621.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/pr81621.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,5 @@
++/* PR target/81621 */
++/* { dg-do compile { target freorder } } */
++/* { dg-options "-Og -fno-split-wide-types -freorder-blocks-and-partition" } */
++
++#include "graphite/scop-10.c"
+Index: gcc/testsuite/gcc.dg/lto/pr81440.h
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/lto/pr81440.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/lto/pr81440.h	(.../branches/gcc-6-branch)
+@@ -0,0 +1,4 @@
++typedef struct {
++  int i;
++  int ints[];
++} struct_t;
+Index: gcc/testsuite/gcc.dg/lto/pr81440_0.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/lto/pr81440_0.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/lto/pr81440_0.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,9 @@
++/* { dg-lto-do link } */
++
++#include "pr81440.h"
++
++extern struct_t my_struct;
++
++int main() {
++ return my_struct.ints[0];
++}
+Index: gcc/testsuite/gcc.dg/lto/pr83954_0.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/lto/pr83954_0.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/lto/pr83954_0.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++/* { dg-lto-do link } */
++#include "pr83954.h"
++
++int main() {
++  // just to prevent symbol removal
++  FOO_PTR_ARR[1] = 0;
++  return 0;
++}
+Index: gcc/testsuite/gcc.dg/lto/pr81440_1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/lto/pr81440_1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/lto/pr81440_1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++#include "pr81440.h"
++
++struct_t my_struct = {
++ 20,
++ { 1, 2 }
++};
+Index: gcc/testsuite/gcc.dg/lto/pr83954.h
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/lto/pr83954.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/lto/pr83954.h	(.../branches/gcc-6-branch)
+@@ -0,0 +1,3 @@
++struct foo;
++extern struct foo *FOO_PTR_ARR[1];
++
+Index: gcc/testsuite/gcc.dg/lto/pr83954_1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/lto/pr83954_1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/lto/pr83954_1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,7 @@
++#include "pr83954.h"
++
++struct foo {
++ int x;
++};
++struct foo *FOO_PTR_ARR[1] = { 0 };
++
+Index: gcc/testsuite/gcc.dg/pr81192.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr81192.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/pr81192.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,22 @@
++/* { dg-options "-Os -fdump-tree-pre-details" } */
++
++unsigned a;
++int b, c;
++
++static int
++fn1 (int p1, int p2)
++{
++  return p1 > 2147483647 - p2 ? p1 : p1 + p2;
++}
++
++void
++fn2 (void)
++{
++  int j;
++  a = 30;
++  for (; a;)
++    for (; c; b = fn1 (j, 1))
++      ;
++}
++
++/* { dg-final { scan-tree-dump-times "(?n)find_duplicates: <bb .*> duplicate of <bb .*>" 1 "pre" } } */
+Index: gcc/testsuite/gcc.dg/torture/pr75964.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/pr75964.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/torture/pr75964.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,28 @@
++/* { dg-do run } */
++
++typedef __UINT8_TYPE__ uint8_t;
++
++uint8_t __attribute__ ((noinline, noclone))
++abs8 (uint8_t x)
++{
++  if (x & 0x80)
++    x = -x;
++
++  if (x & 0x80)
++    x = 0x7f;
++
++  return x;
++}
++
++int
++main (void)
++{
++  if (abs8 (0) != 0
++      || abs8 (1) != 1
++      || abs8 (127) != 127
++      || abs8 (128) != 127
++      || abs8 (129) != 127
++      || abs8 (255) != 1)
++    __builtin_abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.dg/torture/pr60092.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/pr60092.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/torture/pr60092.c	(.../branches/gcc-6-branch)
+@@ -4,7 +4,6 @@
+ /* { dg-skip-if "No undefined weak" { nvptx-*-* } { "*" } { "" } } */
+ /* { dg-additional-options "-Wl,-undefined,dynamic_lookup" { target *-*-darwin* } } */
+ /* { dg-additional-options "-Wl,-flat_namespace" { target *-*-darwin[89]* } } */
+-/* { dg-xfail-run-if "posix_memalign modifies first arg on error" { *-*-solaris2.11* } { "-O0" } } */
+ 
+ typedef __SIZE_TYPE__ size_t;
+ extern int posix_memalign(void **memptr, size_t alignment, size_t size) __attribute__((weak));
+Index: gcc/testsuite/gcc.dg/torture/pr80341.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/pr80341.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/torture/pr80341.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,20 @@
++/* { dg-do run } */
++/* { dg-additional-options "-Wno-overflow" } */
++/* { dg-require-effective-target int32plus } */
++
++const signed char c = -84;
++signed char s;
++
++void
++foo ()
++{
++  s = (unsigned short) c / -55;
++}
++
++int
++main ()
++{
++  foo ();
++  if (s != 90)
++    __builtin_abort ();
++}
+Index: gcc/testsuite/gcc.dg/torture/pr80281.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/pr80281.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/torture/pr80281.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,14 @@
++/* { dg-run } */
++/* { dg-require-effective-target int32plus } */
++
++int
++main ()
++{
++  volatile int a = 0;
++  long long b = 2147483648LL;
++  int c = a % 2;
++  int x = ((int) -b + c) % -2147483647;
++  if (x != -1)
++    __builtin_abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.dg/torture/pr79732.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/pr79732.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/torture/pr79732.c	(.../branches/gcc-6-branch)
+@@ -1,4 +1,5 @@
+ /* { dg-do link } */
++/* { dg-require-alias "" } */
+ 
+ int bar () __attribute__ ((alias ("foo")));
+ void foo () { }
+Index: gcc/testsuite/gcc.dg/pr82975.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr82975.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/pr82975.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,20 @@
++/* PR target/82975.  */
++/* { dg-do compile } */
++/* { dg-options "-fno-sched-pressure -O2" } */
++/* { dg-additional-options "-mtune=cortex-a57" { target arm*-*-* aarch64*-*-* } } */
++
++typedef __SIZE_TYPE__ size_t;
++
++struct S1
++{
++  char pad1;
++  char val;
++  short pad2;
++};
++
++extern char t[256];
++
++void foo (struct S1 a, size_t i)
++{
++  t[i] = a.val;
++}
+Index: gcc/testsuite/gcc.dg/tree-ssa/pr82726.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr82726.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr82726.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,26 @@
++/* { dg-do compile } */
++/* { dg-options "-O3 --param tree-reassoc-width=4" } */
++/* { dg-additional-options "-mavx2" { target { x86_64-*-* i?86-*-* } } } */
++
++#define N 40
++#define M 128
++unsigned int in[N+M];
++unsigned short out[N];
++
++/* Outer-loop vectorization. */
++
++void
++foo (){
++  int i,j;
++  unsigned int diff;
++
++  for (i = 0; i < N; i++) {
++    diff = 0;
++    for (j = 0; j < M; j+=8) {
++      diff += in[j+i];
++    }
++    out[i]=(unsigned short)diff;
++  }
++
++  return;
++}
+Index: gcc/testsuite/gcc.dg/ipa/pr82001.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/ipa/pr82001.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/ipa/pr82001.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,21 @@
++/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
++/* { dg-options "-O2 -fdump-ipa-icf-details"  } */
++
++int
++mullo (int a, int b)
++{
++  asm("mul %%edx   # %%1 was %1"
++      : "+"
++	"a"(a),
++	"+d"(b));
++  return a;
++}
++
++int
++mulhi (int a, int b)
++{
++  asm("mul %%edx   # %%1 was %1" : "+d"(a), "+a"(b));
++  return a;
++}
++
++/* { dg-final { scan-ipa-dump "Equal symbols: 0" "icf"  } } */
+Index: gcc/testsuite/gcc.dg/ipa/pr81696.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/ipa/pr81696.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/ipa/pr81696.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,26 @@
++/* { dg-options "-O2 -fdump-ipa-icf-details"  } */
++
++int
++main (int argc, char **argv)
++{
++  __label__ lab4, lab5, lab6;
++
++  void foo (void) { goto lab4; }
++  void foo2 (void) { goto lab4; }
++  void bar (void) { goto lab5; }
++  void baz (void) { goto lab6; }
++
++  if (argc)
++    foo ();
++  else
++    foo2 ();
++
++ lab4:;
++  bar ();
++ lab5:;
++  baz ();
++ lab6:;
++  return 0;
++}
++
++/* { dg-final { scan-ipa-dump "Equal symbols: 1" "icf"  } } */
+Index: gcc/testsuite/gcc.dg/loop-8.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/loop-8.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/loop-8.c	(.../branches/gcc-6-branch)
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-options "-O1 -fdump-rtl-loop2_invariant" } */
+-/* { dg-skip-if "unexpected IV" { "hppa*-*-* visium-*-*" } { "*" } { "" } } */
++/* { dg-skip-if "unexpected IV" { "hppa*-*-* visium-*-* powerpc*-*-*" } { "*" } { "" } } */
+ 
+ void
+ f (int *a, int *b)
+Index: gcc/testsuite/gcc.dg/pr82274-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr82274-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/gcc.dg/pr82274-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,16 @@
++/* PR target/82274 */
++/* { dg-do run } */
++/* { dg-shouldfail "trapv" } */
++/* { dg-options "-ftrapv" } */
++
++int
++main ()
++{
++#ifdef __SIZEOF_INT128__
++  volatile __int128 m = -(((__int128) 1) << (__CHAR_BIT__ * __SIZEOF_INT128__ / 2));
++#else
++  volatile long long m = -(1LL << (__CHAR_BIT__ * __SIZEOF_LONG_LONG__ / 2));
++#endif
++  m = m * m;
++  return 0;
++}
+Index: gcc/testsuite/ChangeLog
+===================================================================
+--- a/src/gcc/testsuite/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,957 @@
++2018-03-10  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/84734
++	* gfortran.dg/pr84734.f90: New test.
++
++2018-03-10  H.J. Lu  <hongjiu.lu@intel.com>
++
++	Backport from mainline
++	2018-01-04  Jakub Jelinek  <jakub@redhat.com>
++
++	PR ipa/82352
++	* g++.dg/ipa/pr82352.C (size_t): Define to __SIZE_TYPE__ instead of
++	long unsigned int.
++
++2018-03-08  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/64124
++	PR fortran/70409
++	* gfortran.dg/pr64124.f90: New tests.
++	* gfortran.dg/pr70409.f90: New tests.
++
++2018-03-08  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2016-12-14  Jakub Jelinek  <jakub@redhat.com>
++
++	PR debug/77844
++	* g++.dg/opt/pr77844.C: New test.
++
++2018-03-08  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-01-04  Martin Liska  <mliska@suse.cz>
++
++	PR ipa/82352
++	* g++.dg/ipa/pr82352.C: New test.
++
++2018-03-07  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2018-02-08  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
++
++	* gcc.target/s390/nobp-function-pointer-attr.c: New test.
++	* gcc.target/s390/nobp-function-pointer-nothunk.c: New test.
++	* gcc.target/s390/nobp-function-pointer-z10.c: New test.
++	* gcc.target/s390/nobp-function-pointer-z900.c: New test.
++	* gcc.target/s390/nobp-indirect-jump-attr.c: New test.
++	* gcc.target/s390/nobp-indirect-jump-inline-attr.c: New test.
++	* gcc.target/s390/nobp-indirect-jump-inline-z10.c: New test.
++	* gcc.target/s390/nobp-indirect-jump-inline-z900.c: New test.
++	* gcc.target/s390/nobp-indirect-jump-nothunk.c: New test.
++	* gcc.target/s390/nobp-indirect-jump-z10.c: New test.
++	* gcc.target/s390/nobp-indirect-jump-z900.c: New test.
++	* gcc.target/s390/nobp-return-attr-all.c: New test.
++	* gcc.target/s390/nobp-return-attr-neg.c: New test.
++	* gcc.target/s390/nobp-return-mem-attr.c: New test.
++	* gcc.target/s390/nobp-return-mem-nothunk.c: New test.
++	* gcc.target/s390/nobp-return-mem-z10.c: New test.
++	* gcc.target/s390/nobp-return-mem-z900.c: New test.
++	* gcc.target/s390/nobp-return-reg-attr.c: New test.
++	* gcc.target/s390/nobp-return-reg-mixed.c: New test.
++	* gcc.target/s390/nobp-return-reg-nothunk.c: New test.
++	* gcc.target/s390/nobp-return-reg-z10.c: New test.
++	* gcc.target/s390/nobp-return-reg-z900.c: New test.
++	* gcc.target/s390/nobp-table-jump-inline-z10.c: New test.
++	* gcc.target/s390/nobp-table-jump-inline-z900.c: New test.
++	* gcc.target/s390/nobp-table-jump-z10.c: New test.
++	* gcc.target/s390/nobp-table-jump-z900.c: New test.
++
++2018-03-07  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2018-02-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
++
++	PR target/PR84295
++	* gcc.target/s390/pr84295.c: New test.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-02-20  Martin Liska  <mliska@suse.cz>
++
++	PR c/84310
++	PR target/79747
++	* gcc.target/i386/pr84310.c: New test.
++	* gcc.target/i386/pr84310-2.c: Likewise.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-01-23  Martin Liska  <mliska@suse.cz>
++
++	PR lto/81440
++	* gcc.dg/lto/pr81440.h: New test.
++	* gcc.dg/lto/pr81440_0.c: New test.
++	* gcc.dg/lto/pr81440_1.c: New test.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-01-30  Jan Hubicka  <hubicka@ucw.cz>
++
++	PR lto/83954
++	* gcc.dg/lto/pr83954.h: New testcase.
++	* gcc.dg/lto/pr83954_0.c: New testcase.
++	* gcc.dg/lto/pr83954_1.c: New testcase.
++
++2018-03-06  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/56667
++	* gfortran.dg/implied_do_2.f90: New test.
++	* gfortran.dg/coarray_8.f90: Update for new error message.
++
++2018-03-03  Harald Anlauf  <anlauf@gmx.de>
++
++	PR fortran/71085
++	* gfortran.dg/pr71085.f90: New test.
++
++2018-03-03  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk.
++	PR fortran/78990
++	* gfortran.dg/class_67.f90: New test.
++
++2017-03-02  Thomas Schwinge  <thomas@codesourcery.com>
++
++	Backport from trunk r256891:
++	2018-01-19  Cesar Philippidis  <cesar@codesourcery.com>
++
++	PR target/83790
++	* gcc.target/nvptx/indirect_call.c: New test.
++
++2018-02-28  Alan Modra  <amodra@gmail.com>
++
++	* lib/prune.exp (prune_gcc_output): Match lower case "in function"
++	GNU ld message.
++	* g++.dg/other/anon5.C: Match lower case "bad value" GNU ld message.
++
++2018-02-25  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/83633
++	* gfortran.dg/explicit_shape_1.f90: New test.
++	* gfortran.dg/automatic_module_variable.f90: Update regex.
++	* gfortran.dg/bad_automatic_objects_1.f90: Ditto.
++
++2018-02-24  Steven G. Kargl <kargl@gcc.gnu.org>
++
++	PR fortran/30792
++	* gfortran.dg/data_substring.f90: New test.
++
++2018-02-23  Jerry DeLisle  <jvdelisle@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/84506
++	* gfortran.dg/inquire_19.f90: New test.
++
++2018-02-23  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/84346
++	* gfortran.dg/statement_function_1.f90: Update test.
++
++2018-02-21  Sudakshina Das  <sudi.das@arm.com>
++
++	Backport from trunk
++	2018-01-12  Sudakshina Das  <sudi.das@arm.com>
++
++	* gcc.c-torture/compile/pr82096.c: Add dg-skip-if
++	directive.
++
++	Backport from trunk
++	2018-01-10  Sudakshina Das  <sudi.das@arm.com>
++
++	PR target/82096
++	* gcc.c-torture/compile/pr82096.c: New test.
++
++2018-02-16  Eric Botcazou  <ebotcazou@adacore.com>
++
++	PR ada/84277
++	* gnat.dg/array11.adb (Array11): Tweak index and remove warning.
++	* gnat.dg/dispatch1.adb: Rename into...
++	* gnat.dg/disp1.adb: ...this.
++	* gnat.dg/dispatch1_p.ads: Rename into...
++	* gnat.dg/disp1_pkg.ads: ...this.
++	* gnat.dg/disp2.adb: Rename into...
++	* gnat.dg/dispatch2.adb: ...this.
++	* gnat.dg/dispatch2_p.ads: Rename into...
++	* gnat.dg/disp2_pkg.ads: ...this.
++	* gnat.dg/dispatch2_p.adb: Rename into...
++	* gnat.dg/disp2_pkg.adb: this.
++	* gnat.dg/generic_dispatch.adb: Rename into...
++	* gnat.dg/generic_disp.adb: this.
++	* gnat.dg/generic_dispatch_p.ads: Rename into...
++	* gnat.dg/generic_disp_pkg.ads: ...this.
++	* gnat.dg/generic_dispatch_p.adb: Rename into...
++	* gnat.dg/generic_disp_pkg.adb: ...this.
++	* gnat.dg/null_pointer_deref1.adb (Null_Pointer_Deref1): Robustify.
++	* gnat.dg/null_pointer_deref2.adb (Null_Pointer_Deref2): Likewise.
++	* gnat.dg/object_overflow1.adb: Tweak index.
++	* gnat.dg/object_overflow2.adb: Likewise.
++	* gnat.dg/object_overflow3.adb: Likewise.
++	* gnat.dg/object_overflow4.adb: Likewise.
++	* gnat.dg/object_overflow5.adb: Likewise.
++
++2018-02-14  Peter Bergner  <bergner@vnet.ibm.com>
++
++	Backport from GCC 7 branch
++	2018-02-14  Peter Bergner  <bergner@vnet.ibm.com>
++
++	PR target/84390
++	* gcc.target/powerpc/vsxcopy.c: Also match lxv when compiling
++	with -mcpu=power9.
++
++2018-02-12  Thomas Koenig  <tkoenig@gcc.gnu.org>
++
++	PR fortran/68560
++	* gfortran.dg/shape_9.f90: New test.
++
++2018-02-12  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
++
++	PR fortran/35299
++	ChangeLog for r257566
++	* gfortran.dg/statement_function_3.f: New test.
++
++2018-02-12  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/54223
++	PR fortran/84276
++	* gfortran.dg/statement_function_1.f90: New test.
++	* gfortran.dg/statement_function_2.f90: New test.
++
++2018-02-07  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/82994
++	* gfortran.dg/deallocate_error_3.f90: New test.
++	* gfortran.dg/deallocate_error_4.f90: New test.
++
++2018-02-07  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/82049
++	* gfortran.dg/assumed_charlen_parameter.f90: New test.
++
++2018-02-01  Renlin Li  <renlin.li@arm.com>
++
++	Backport from mainline
++	2018-02-01  Richard Sandiford  <richard.sandiford@linaro.org>
++
++	PR target/83370
++	* gcc.target/aarch64/pr83370.c: New.
++
++2018-02-01  Bin Cheng  <bin.cheng@arm.com>
++
++	Backport from mainline
++	2017-11-15  Bin Cheng  <bin.cheng@arm.com>
++
++	PR tree-optimization/82726
++	* gcc.dg/tree-ssa/pr82726.c: New test.
++
++	Backport from mainline
++	2017-01-23  Bin Cheng  <bin.cheng@arm.com>
++
++	PR tree-optimization/70754
++	* gfortran.dg/pr70754.f90: New test.
++
++2018-02-01  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	Backport from mainline
++	2018-01-12  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	* lib/target-supports.exp (check_effective_target_avx512f): Also
++	check for __builtin_ia32_addsd_round,
++	__builtin_ia32_getmantsd_round.
++	* gcc.target/i386/i386.exp (check_effective_target_avx512f):
++	Remove.
++
++2018-01-29  Alan Modra  <amodra@gmail.com>
++
++	PR target/84033
++	* gcc.target/powerpc/swaps-p8-46.c: New.
++
++2018-01-23  Peter Bergner  <bergner@vnet.ibm.com>
++
++	Back port from mainline
++	2018-01-10  Peter Bergner  <bergner@vnet.ibm.com>
++
++	PR target/83399
++	* gcc.target/powerpc/pr83399.c: New test.
++
++2018-01-23  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Back port from trunk
++	2018-01-22  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	PR target/83862
++	* gcc.target/powerpc/pr83862.c: New test.
++
++2018-01-20  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/83900
++	* gfortran.dg/matmul_18.f90: New test.
++
++2018-01-19  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/83900
++	* gfortran.dg/matmul_17.f90: New test.
++
++2018-01-19  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/80768
++	* gfortran.dg/num_images_1.f90:  New test that tests fix in r250734.
++
++2018-01-17  Harald Anlauf  <anlauf@gmx.de>
++
++	Back from mainline
++	PR fortran/83874
++	* gfortran.dg/pr83874.f90: New test.
++
++2018-01-16  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	Backport from mainline
++	2017-12-18  Segher Boessenkool  <segher@kernel.crashing.org>
++
++	PR rtl-optimization/83424
++	* gcc.dg/pr83424.c: New testsuite.
++
++2018-01-14  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2018-01-08  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR target/83677
++	* gcc.target/powerpc/pr83677.c: New file.
++
++2018-01-13  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	Backport from mainline
++	PR fortran/78814
++	* gfortran.dg/interface_40.f90: New testcase.
++
++2018-01-10  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/82367
++	* gfortran.dg/deferred_character_18.f90: New test.
++
++2018-01-10  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/83093
++	* gfortran.dg/allocate_with_typespec_7.f90: New test.
++
++2018-01-10  Steven G. Kargl  <kargl@kgcc.gnu.org>
++
++	Backport r254555 from trunk
++	PR Fortran/82841
++	* gfortran.dg/transfer_simplify_11.f90: New test.
++
++2018-01-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
++
++	Backport from mainline
++	2017-12-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
++
++	PR target/82975
++	* gcc.dg/pr82975.c: New test.
++
++2018-01-02  Thomas Koenig  <tkoenig@gcc.gnu.org>
++
++	Backport from 7-branch
++	PR fortran/83650
++	* gfortran.dg/simplify_cshift_1.f90: Correct condition.
++
++2017-12-14  Peter Bergner  <bergner@vnet.ibm.com>
++
++	Backport from mainline
++	2017-12-13  Peter Bergner  <bergner@vnet.ibm.com>
++
++	* gcc.target/powerpc/cpu-builtin-1.c (htm-no-suspend): Add test.
++
++2017-12-14  Peter Bergner  <bergner@vnet.ibm.com>
++
++	Backport from mainline
++	2017-10-02  Peter Bergner  <bergner@vnet.ibm.com>
++
++	PR target/80210
++	* gcc.target/powerpc/pr80210-2.c: New test.
++
++2017-12-14  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gnat.dg/alignment13.adb: New test.
++
++2017-12-11  Thomas Schwinge  <thomas@codesourcery.com>
++
++	PR c++/83301
++
++	Backport trunk r243377:
++	2016-12-07  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c++/78692
++	* g++.dg/torture/pr78692.C: New test.
++
++2017-12-04  Sebastian Peryt  <sebastian.peryt@intel.com>
++	H.J. Lu  <hongjiu.lu@intel.com>
++
++	Backported from trunk
++	PR target/82941
++	PR target/82942
++	PR target/82990
++	* gcc.target/i386/pr82941-1.c: New test.
++	* gcc.target/i386/pr82941-2.c: Likewise.
++	* gcc.target/i386/pr82942-1.c: Likewise.
++	* gcc.target/i386/pr82942-2.c: Likewise.
++	* gcc.target/i386/pr82990-1.c: Likewise.
++	* gcc.target/i386/pr82990-2.c: Likewise.
++	* gcc.target/i386/pr82990-3.c: Likewise.
++	* gcc.target/i386/pr82990-4.c: Likewise.
++	* gcc.target/i386/pr82990-5.c: Likewise.
++	* gcc.target/i386/pr82990-6.c: Likewise.
++	* gcc.target/i386/pr82990-7.c: Likewise.
++
++2017-11-21  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	Backport from mainline
++	2017-11-14  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
++
++	* lib/target-supports.exp (check_effective_target_pie): Adapt
++	comment for Solaris 12 renaming.
++
++	* gcc.dg/torture/pr60092.c: Remove *-*-solaris2.11* dg-xfail-run-if.
++
++2017-11-13  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/82934
++	* gfortran.dg/allocate_assumed_charlen_1.f90: New test.
++
++2017-11-13  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/78619
++	* gfortran.dg/pr78619.f90: New test.
++
++2017-11-11  John David Anglin  <danglin@gcc.gnu.org>
++
++	Backport from mainline
++	2017-02-03  John David Anglin  <danglin@gcc.gnu.org>
++
++        * c-c++-common/Wunused-var-16.c: Add -fno-common additional option on
++	hppa*-*-hpux*
++        * c-c++-common/builtin-shuffle-1.c: Likewise.
++
++	2017-02-15  David Edelsohn  <dje.gcc@gmail.com>
++
++	* g++.dg/cpp0x/pr79296.C: Move dg-do compile directive first.
++
++	2017-02-24  David Edelsohn  <dje.gcc@gmail.com>
++
++	* g++.dg/ext/complit15.C: Require LTO.
++
++	2017-01-26  David Edelsohn  <dje.gcc@gmail.com>
++
++	* g++.dg/opt/declone3.C: Require LTO.
++
++	2017-03-26  John David Anglin  <danglin@gcc.gnu.org>
++
++	* gcc.dg/torture/pr79732.c: Require alias support.
++
++	2017-02-03  John David Anglin  <danglin@gcc.gnu.org>
++
++	* gfortran.dg/coarray_43.f90: Add "-latomic" option if
++	libatomic_available.
++
++2017-11-10  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gnat.dg/opt69.adb: New test.
++
++2017-11-06  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backported from trunk
++	PR fortran/78641
++	* gfortran.dg/class_66.f90: New test.
++
++2017-11-06  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backported from trunk
++	PR fortran/69739
++	* gfortran.dg/pr69739.f90: New test.
++
++2017-11-01  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/82796
++	* gfortran.dg/equiv_pure.f90: New test.
++
++2017-11-03  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from 7-branch
++	PR fortran/81735
++	* gfortran.dg/pr81735.f90: New test.
++
++2017-11-01  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/78293
++	* gfortran.dg/allocatable_function_10.f90: New test.
++	* gfortran.dg/class_array_15.f03: Increase builtin_free count
++	from 11 to 12.
++
++017-11-01  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/80554
++	* gfortran.dg/submodule_29.f08: New test.
++
++2017-10-22  Thomas Koenig  <tkoenig@gcc.gnu.org>
++
++	Backport from trunk
++	PR libfortran/82233
++	* gfortran.dg/execute_command_line_3.f90: New test.
++
++2017-10-20  Thomas Koenig  <tkoenig@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/79795
++	* gfortran.dg/assumed_size_2.f90: New test.
++
++2017-10-19  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/79402
++	* gfortran.dg/submodule_23.f90: New test.
++
++2017-10-19  Richard Earnshaw  <rearnsha@arm.com>
++
++	PR target/82445
++	* gcc.target/arm/peep-ldrd-1.c: Tighten test scan pattern.
++	* gcc.target/arm/peep-strd-1.c: Likewise.
++	* gcc.target/arm/peep-ldrd-2.c: New test.
++	* gcc.target/arm/peep-strd-2.c: New test.
++
++2017-10-19  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/81048
++	* gfortran.dg/derived_init_4.f90 : New test.
++
++2017-10-17  Jakub Jelinek  <jakub@redhat.com>
++
++	PR tree-optimization/82549
++	* gcc.c-torture/compile/pr82549.c: New test.
++
++2017-10-13  Jakub Jelinek  <jakub@redhat.com>
++
++	PR target/82274
++	* gcc.dg/pr82274-1.c: New test.
++	* gcc.dg/pr82274-2.c: New test.
++
++2017-10-06  Thomas Koenig  <tkoenig@gcc.gnu.org>
++	    Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/80118
++	* gfortran.dg/zero_sized_7.f90: New test.
++
++2017-10-02  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-09-29  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR tree-optimization/82337
++	* gcc.c-torture/compile/pr82337.c: New file.
++
++2017-10-02  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* opt55.ad[sb]: Move to...
++	* gnat.dg/opt55.ad[sb]: ...here.
++
++2017-09-19  Martin Liska  <mliska@suse.cz>
++
++	Revert backport:
++	2017-08-10  Martin Liska  <mliska@suse.cz>
++
++	PR c++/81355
++	* g++.dg/other/pr81355.C: New test.
++
++2017-09-18  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2017-04-07  Richard Biener  <rguenther@suse.de>
++
++	PR middle-end/80341
++	* gcc.dg/torture/pr80341.c: New testcase.
++
++	2017-04-04  Richard Biener  <rguenther@suse.de>
++
++	PR middle-end/80281
++	* gcc.dg/torture/pr80281.c: New testcase.
++
++2017-09-18  Richard Biener  <rguenther@suse.de>
++
++	Backport from mainline
++	2017-08-28  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/81977
++	* g++.dg/torture/pr81977.C: New testcase.
++
++	2017-09-04  Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/82084
++	* g++.dg/torture/pr82084.C: New testcase.
++
++	2017-07-25  Richard Biener  <rguenther@suse.de>
++
++	PR middle-end/81505
++	* gcc.dg/ubsan/pr81505.c: New testcase.
++
++2017-09-18  Martin Liska  <mliska@suse.cz>
++
++	* gcc.dg/asan/pr81224.c: Remove.
++
++2017-09-15  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-09-12  Jakub Jelinek  <jakub@redhat.com>
++
++	PR target/82112
++	* gcc.target/powerpc/pr82112.c: New test.
++	* g++.dg/ext/altivec-18.C: New test.
++
++	PR target/82112
++	* c-c++-common/pr82112.c: New test.
++	* gcc.dg/pr82112.c: New test.
++
++	2017-09-05  Jakub Jelinek  <jakub@redhat.com>
++
++	PR middle-end/81768
++	* gcc.dg/gomp/pr81768-2.c: New test.
++
++	PR middle-end/81768
++	* gcc.dg/gomp/pr81768-1.c: New test.
++
++	2017-08-08  Richard Biener  <rguenther@suse.de>
++
++	PR middle-end/81766
++	* gcc.target/i386/pr81766.c: New testcase.
++
++	2017-08-03  Jakub Jelinek  <jakub@redhat.com>
++
++	PR target/81621
++	* gcc.dg/pr81621.c: New test.
++
++	PR middle-end/81052
++	* c-c++-common/pr81052.c: New test.
++
++	2017-08-02  Jakub Jelinek  <jakub@redhat.com>
++
++	PR middle-end/79499
++	* gcc.dg/pr79499.c: New test.
++
++	2017-06-30  Jakub Jelinek  <jakub@redhat.com>
++
++	PR target/81225
++	* gcc.target/i386/pr81225.c: New test.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-08-11  Martin Liska  <mliska@suse.cz>
++
++	PR tree-opt/79987
++	* gcc.target/i386/mpx/pr79987.c: New test.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-06-28  Martin Liska  <mliska@suse.cz>
++
++	PR sanitizer/81224
++	* gcc.dg/asan/pr81224.c: New test.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-08-30  Martin Liska  <mliska@suse.cz>
++
++	PR inline-asm/82001
++	* gcc.dg/ipa/pr82001.c: New test.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-08-10  Martin Liska  <mliska@suse.cz>
++
++	PR c++/81355
++	* g++.dg/other/pr81355.C: New test.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-08-08  Martin Liska  <mliska@suse.cz>
++
++	PR tree-opt/81696
++	* gcc.dg/ipa/pr81696.c: New test.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-07-19  Martin Liska  <mliska@suse.cz>
++
++	PR sanitizer/63361
++	* c-c++-common/ubsan/float-cast-overflow-1.c: Add either
++	-ffloat-store or -mieee for targets that need it.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-06-28  Martin Liska  <mliska@suse.cz>
++
++	PR ipa/81128
++	* gcc.target/i386/pr81128.c: New test.
++
++2017-09-12  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-09-05  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR target/81833
++	* gcc.target/powerpc/pr81833-1.c: New file.
++	* gcc.target/powerpc/pr81833-2.c: New file.
++
++2017-09-10  Jonathan Wakely  <jwakely@redhat.com>
++
++	PR c++/81852
++	* g++.dg/cpp1y/feat-cxx11.C: Check __cpp_threadsafe_static_init.
++	* g++.dg/cpp1y/feat-cxx14.C: Likewise.
++	* g++.dg/cpp1y/feat-cxx98.C: Likewise.
++	* g++.dg/cpp1y/feat-neg.C: Likewise.
++	* g++.dg/cpp1z/feat-cxx1z.C: Likewise.
++
++2017-09-06  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline:
++	2017-08-30  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR tree-optimization/81987
++	* g++.dg/torture/pr81987.C: New file.
++
++2017-09-05  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-08-29  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++		    Jakub Jelinek  <jakub@redhat.com>
++		    Richard Biener  <rguenther@suse.de>
++
++	PR tree-optimization/81503
++	* gcc.c-torture/execute/pr81503.c: New file.
++
++2017-09-05  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gnat.dg/specs/uc2.ads: New test.
++
++2017-09-05  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* testsuite/gnat.dg/array29.ad[sb]: New test.
++
++2017-09-04  Uros Bizjak  <ubizjak@gmail.com>
++
++	* gcc.target/i386/mpx/mpx-os-support.h: New file.
++	* gcc.target/i386/mpx/mpx-check.h: Include mpx-os-support.h.
++	(check_osxsave): New function.
++	(main): Use __get_cpuid_count and return NORUNRES on failure.
++	Use check_osxsave.
++	* gcc.target/i386/mpx/va-arg-pack-1-lbv.c (foo1): Use
++	__builtin_va_arg_pack instead of __va_arg_pack.
++	* gcc.target/i386/mpx/va-arg-pack-1-nov.c (foo1): Ditto.
++	* gcc.target/i386/mpx/va-arg-pack-1-ubv.c (foo1): Ditto.
++	* gcc.target/i386/mpx/va-arg-pack-2-lbv.c (foo1): Ditto.
++	* gcc.target/i386/mpx/va-arg-pack-2-nov.c (foo1): Ditto.
++	* gcc.target/i386/mpx/va-arg-pack-2-ubv.c (foo1): Ditto.
++
++2017-09-02  Janus Weil  <janus@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/81770
++	* gfortran.dg/warn_target_lifetime_3.f90: Fix a typo.
++	* gfortran.dg/warn_target_lifetime_4.f90: New testcase.
++
++2017-08-30  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Back port from trunk
++	2017-08-07  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	PR target/81593
++	* gcc.target/powerpc/vec-setup.h: New tests to test various
++	combinations of setting up vectors of 2 double word elements.
++	* gcc.target/powerpc/vec-setup-long.c: Likewise.
++	* gcc.target/powerpc/vec-setup-double.c: Likewise.
++	* gcc.target/powerpc/vec-setup-be-long.c: Likewise.
++	* gcc.target/powerpc/vec-setup-be-double.c: Likewise.
++	* gcc.target/powerpc/vsx-extract-6.c: New tests for optimzing
++	vector inserts from vector extracts.
++	* gcc.target/powerpc/vsx-extract-7.c: Likewise.
++
++2017-08-24  Yvan Roux  <yvan.roux@linaro.org>
++
++	Backport from mainline
++	2017-08-22  Yvan Roux  <yvan.roux@linaro.org>
++
++	PR c++/80287
++	* g++.dg/pr8028.C: New test.
++
++2017-08-22  Peter Bergner  <bergner@vnet.ibm.com>
++
++	Backport from mainline
++	2017-08-17  Peter Bergner  <bergner@vnet.ibm.com>
++
++	PR target/80210
++	* gcc.target/powerpc/pr80210.c: New test.
++
++2017-08-16  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-08-08  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR tree-optimization/81354
++	* g++.dg/torture/pr81354.C: New file.
++
++2017-08-14  Paolo Carlini  <paolo.carlini@oracle.com>
++
++	PR c++/71570
++	* g++.dg/cpp0x/lambda/lambda-ice17.C: New.
++
++2017-08-01  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/81641
++	* gcc.target/i386/pr81641.c: New test.
++
++2017-07-31  Jakub Jelinek  <jakub@redhat.com>
++
++	PR sanitizer/81604
++	* c-c++-common/ubsan/pr81604.c: New test.
++
++2017-07-28  Peter Bergner  <bergner@vnet.ibm.com>
++
++	Backport from mainline
++	2017-07-28  Peter Bergner  <bergner@vnet.ibm.com>
++
++	* gcc.target/powerpc/cpu-builtin-1.c (darn, scv): Add tests.
++
++2017-07-28  Bin Cheng  <bin.cheng@arm.com>
++
++	Backport from mainline r250496
++	2017-07-25  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
++
++	PR target/81414
++	* gcc.target/aarch64/pr81414.C: New.
++
++2017-07-27  Jakub Jelinek  <jakub@redhat.com>
++
++	PR tree-optimization/81555
++	PR tree-optimization/81556
++	* gcc.c-torture/execute/pr81555.c: New test.
++	* gcc.c-torture/execute/pr81556.c: New test.
++
++2017-07-26  Georg-Johann Lay  <avr@gjlay.de>
++
++	Backport from 2017-07-05 trunk r249995, r249996.
++
++	PR target/81305
++	* gcc.target/avr/isr-test.h: New file.
++	* gcc.target/avr/torture/isr-01-simple.c: New test.
++	* gcc.target/avr/torture/isr-02-call.c: New test.
++	* gcc.target/avr/torture/isr-03-fixed.c: New test.
++
++2017-07-25  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-07-14  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
++
++	PR tree-optimization/81162
++	* gcc.dg/ubsan/pr81162.c: New file.
++
++2017-07-25  Georg-Johann Lay  <avr@gjlay.de>
++
++	Backport from trunk r247719.
++
++	2017-05-06  Richard Sandiford  <richard.sandiford@linaro.org>
++
++	PR rtl-optimization/75964
++	* gcc.dg/torture/pr75964.c: New test.
++
++2017-07-24  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/80569
++	* gcc.target/i386/pr80569.c: New test.
++
++2017-07-18  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/81471
++	* gcc.target/i386/pr81471.c: New test.
++
++2017-07-14  Kelvin Nilsen  <kelvin@gcc.gnu.org>
++
++	Backports from trunk:
++
++	2017-01-23  Kelvin Nilsen  <kelvin@gcc.gnu.org>
++	PR target/66669
++	* gcc.dg/loop-8.c: Modify dg-skip-if directive to exclude this
++	test on powerpc targets.
++
++	2017-02-08  Kelvin Nilsen  <kelvin@gcc.gnu.org>
++	PR target/68972
++	* g++.dg/cpp1y/vla-initlist1.C: Add dg-skip-if directive to
++	disable this test on power architecture.
++
++	2017-03-23  Kelvin Nilsen  <kelvin@gcc.gnu.org>
++	* gcc.target/powerpc/p9-options-1.c: New test.
++
++	2017-03-27  Kelvin Nilsen  <kelvin@gcc.gnu.org>
++	PR target/80103
++	* gcc.target/powerpc/pr80103-1.c: New test.
++
++	2017-05-08  Kelvin Nilsen  <kelvin@gcc.gnu.org>
++	PR target/80101
++	* gcc.target/powerpc/pr80101-1.c: New test.
++
++	2017-07-05  Kelvin Nilsen  <kelvin@gcc.gnu.org>
++	PR target/80103
++	* gcc.target/powerpc/pr80103-1.c (b): Correct spelling of
++	__attribute__.
++
++2017-07-14  Uros Bizjak  <ubizjak@gmail.com>
++
++	Backport from mainline
++	2017-07-10  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/81375
++	* gcc.target/i386/pr81375.c: New test.
++
++	Backport from mainline
++	2017-07-04  Uros Bizjak  <ubizjak@gmail.com>
++
++	PR target/81300
++	* gcc.target/i386/pr81300.c: New test.
++
++2017-07-13  Tom de Vries  <tom@codesourcery.com>
++
++	backport from mainline:
++	PR tree-optimization/81192
++	2017-07-03  Tom de Vries  <tom@codesourcery.com>
++
++	* gcc.dg/pr81192.c: New test.
++
++2017-07-06  Andrew Pinski  <apinski@cavium.com>
++
++	* gcc.target/aarch64/pr71112.c: New Testcase.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+@@ -509,7 +1463,7 @@
+ 	2017-02-21  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR c++/79639
+-	* g++.dg/cpp1y/constexpr-79639.C: New test. 
++	* g++.dg/cpp1y/constexpr-79639.C: New test.
+ 
+ 	PR target/79570
+ 	* gcc.dg/pr79570.c: New test.
+@@ -612,14 +1566,14 @@
+ 
+ 	Backport from trunk
+ 	PR fortran/71838
+-	* gfortran.dg/submodule_26.f08 : New test.
+-	* gfortran.dg/submodule_27.f08 : New test.
++	* gfortran.dg/submodule_26.f08: New test.
++	* gfortran.dg/submodule_27.f08: New test.
+ 
+ 2017-04-01  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	Backport from trunk
+ 	PR fortran/79676
+-	* gfortran.dg/submodule_28.f08 : New test.
++	* gfortran.dg/submodule_28.f08: New test.
+ 
+ 2017-03-31  Richard Sandiford  <richard.sandiford@arm.com>
+ 
+@@ -689,7 +1643,7 @@
+ 
+ 	Backport from trunk
+ 	PR fortran/79434
+-	* gfortran.dg/submodule_25.f08 : New test.
++	* gfortran.dg/submodule_25.f08: New test.
+ 
+ 2017-03-24  Tom de Vries  <tom@codesourcery.com>
+ 
+@@ -2843,7 +3797,7 @@
+ 
+ 	Backport from trunk
+ 	PR fortran/71883
+-	* gfortran.dg/pr71883.f90 : New test.
++	* gfortran.dg/pr71883.f90: New test.
+ 
+ 2016-07-26  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+ 
+@@ -2922,6 +3876,23 @@
+ 	* g++.dg/cpp0x/pr70869.C: New test.
+ 	* g++.dg/cpp0x/pr71054.C: New test.
+ 
++2017-07-19  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	Back port from trunk
++	2017-06-28  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	PR target/81193
++	* lib/target-supports.exp
++	(check_ppc_cpu_supports_hw_available): New test to make sure
++	__builtin_cpu_supports works on power7 and newer.
++
++	Back port from trunk
++	2017-07-12  Michael Meissner  <meissner@linux.vnet.ibm.com>
++
++	PR target/81193
++	* gcc.target/powerpc/cpu-builtin-1.c: Add guard against using
++	__builtin_cpu_supports with old GLIBC's.
++
+ 2016-07-18  Michael Meissner  <meissner@linux.vnet.ibm.com>
+ 
+ 	Back port from mainline
+@@ -6544,7 +7515,7 @@
+ 2016-02-20  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/69423
+-	* gfortran.dg/deferred_character_15.f90 : New test.
++	* gfortran.dg/deferred_character_15.f90: New test.
+ 
+ 2016-02-20  Dominique d'Humieres  <dominiq@lps.ens.fr>
+ 
+Index: gcc/testsuite/g++.dg/opt/pr77844.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/opt/pr77844.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/opt/pr77844.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,32 @@
++// PR debug/77844
++// { dg-do compile }
++// { dg-options "-O3 -g" }
++
++#include <vector>
++
++void
++foo (std::vector<bool>& v, int i, int j)
++{
++  for (int k = 0; k < 5; ++k)
++    v[5 * i + k] = v[5 * i + k] | v[5 * j + k];
++}
++
++void
++bar (std::vector<bool>& v, int i, int j)
++{
++  for (int k = 0; k < 5; ++k)
++    v[5 * i + k] = v[5 * i + k] ^ v[5 * j + k];
++}
++
++void
++baz (std::vector<bool>& v)
++{
++  foo (v, 4, 1);
++  foo (v, 4, 2);
++  foo (v, 4, 3);
++  foo (v, 4, 4);
++  bar (v, 4, 1);
++  bar (v, 4, 2);
++  bar (v, 4, 3);
++  bar (v, 4, 4);
++}
+Index: gcc/testsuite/g++.dg/opt/declone3.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/opt/declone3.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/opt/declone3.C	(.../branches/gcc-6-branch)
+@@ -1,5 +1,6 @@
+ // PR c++/79176
+ // { dg-do compile { target c++11 } }
++// { dg-require-effective-target lto }
+ // { dg-options "-flto -Os" }
+ 
+ struct A {};
+Index: gcc/testsuite/g++.dg/cpp0x/lambda/lambda-ice17.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-ice17.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-ice17.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,12 @@
++// PR c++/71570
++// { dg-do compile { target c++11 } }
++
++void foo (int);
++
++void foo (void)
++{
++  [&foo] // { dg-error "cannot capture" }
++  {
++    foo (0);
++  };
++}
+Index: gcc/testsuite/g++.dg/cpp0x/ref-qual18.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/ref-qual18.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/ref-qual18.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,18 @@
++// PR c++/71784
++// { dg-do compile { target c++11 } }
++
++template<typename T> struct A {
++  template<typename U> void f(U const&) & { }
++  template<typename U> void f(U const&) && { }
++};
++
++template void A<int>::f<int>(int const&) &;
++template void A<float>::f<int>(int const&) &&;
++
++template<typename T> struct B {
++  void f(int const&) & { }
++  void f(int const&) && { }
++};
++
++template void B<int>::f(int const&) &;
++template void B<float>::f(int const&) &&;
+Index: gcc/testsuite/g++.dg/cpp0x/alias-decl-63.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/alias-decl-63.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/alias-decl-63.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,18 @@
++// PR c++/84785
++// { dg-do compile { target c++11 } }
++
++template <typename> struct A;
++template <bool> struct B;
++template <bool B, typename> using enable_if_t = typename B<B>::type;
++template <long> using type_pack_element = int;
++struct variant {
++  variant() {}
++  template <typename Arg, long I = Arg::type::value,
++            typename = type_pack_element<I>, enable_if_t<A<Arg>::value, int>>
++  variant(Arg &&);
++};
++
++struct S {
++  variant var;
++};
++int main() { S s; }
+Index: gcc/testsuite/g++.dg/cpp0x/elision3.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/elision3.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/elision3.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,21 @@
++// PR c++/84441
++// { dg-do compile { target c++11 } }
++
++struct B {
++  int *b;
++};
++struct A {
++  B b;
++  A (A &&);
++};
++struct C {
++  A c;
++  int d;
++};
++C bar ();
++struct D : C {
++  D ()
++    : C (0 ? bar () : bar ())
++  {}
++};
++D d;
+Index: gcc/testsuite/g++.dg/cpp0x/pr79296.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/pr79296.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/pr79296.C	(.../branches/gcc-6-branch)
+@@ -1,6 +1,6 @@
++// { dg-do compile { target c++11 } }
+ // { dg-require-effective-target lto }
+ // { dg-additional-options "-flto" }
+-// { dg-do compile { target c++11 } }
+ 
+ // PR 79296 ICE mangling local class of localized instantiation
+ 
+Index: gcc/testsuite/g++.dg/cpp0x/fntmpdefarg7.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/fntmpdefarg7.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/fntmpdefarg7.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,10 @@
++// PR c++/84489
++// { dg-do compile { target c++11 } }
++
++template <class T = int, T N = T(), bool B = (N >> 1)>
++T f1() {return 0;}
++
++int main()
++{
++  f1(); // Bug here
++}
+Index: gcc/testsuite/g++.dg/torture/pr81354.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/torture/pr81354.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/torture/pr81354.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,24 @@
++// PR81354 reported this test as crashing in a limited range of revisions.
++// { dg-do compile }
++
++struct T { double a; double b; };
++
++void foo(T Ad[], int As[2])
++{
++  int j;
++  int i;
++  int Bs[2] = {0,0};
++  T Bd[16];
++
++  for (j = 0; j < 4; j++) {
++    for (i = 0; i + 1 <= j + 1; i++) {
++      Ad[i + As[0] * j] = Bd[i + Bs[0] * j];
++    }
++
++    i = j + 1;  // <- comment out this line and it does not crash
++    for (; i + 1 < 5; i++) {
++      Ad[i + As[0] * j].a = 0.0;
++      Ad[i + As[0] * j].b = 0.0;
++    }
++  }
++}
+Index: gcc/testsuite/g++.dg/torture/pr78692.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/torture/pr78692.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/torture/pr78692.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,26 @@
++// PR c++/78692
++
++int a;
++void *b;
++extern "C" {
++struct C {
++  virtual int d ();
++};
++struct E {
++  virtual int operator () (int, const void *, int) = 0;
++};
++class F {
++  int g ();
++  int h;
++  E &i;
++};
++struct : C, E {
++  int operator () (int, const void *, int) { throw int(); }
++} j;
++
++int
++F::g ()
++{
++  a = i (h, b, 0);
++}
++}
+Index: gcc/testsuite/g++.dg/torture/pr82084.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/torture/pr82084.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/torture/pr82084.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,9 @@
++// { dg-do compile }
++
++#include <string>
++int main()
++{
++  wchar_t strs[4][2]= {  L"A", L"B", L"C" , L"D"};
++  std::wstring ss(strs[0]);
++  return 0;
++}
+Index: gcc/testsuite/g++.dg/torture/pr81977.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/torture/pr81977.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/torture/pr81977.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,55 @@
++/* { dg-do run } */
++/* { dg-require-effective-target int32plus } */
++
++#include <cstdint>
++
++typedef struct
++{
++  uint16_t  x ;
++  uint16_t  y ;
++  uint64_t  z ;
++} __attribute__((packed, aligned(1))) TestMsgType;
++
++struct Payload
++{
++  uint16_t header_info[2];
++  TestMsgType _pref;
++  void Pack(uint8_t *buffer)
++    {
++      __builtin_memcpy(buffer, &_pref, sizeof(_pref));
++    }
++  void UnPack(uint8_t *buffer)
++    {
++      __builtin_memcpy(&_pref, buffer, sizeof(_pref));
++    }
++};
++
++
++struct Msg
++{
++  Payload _payload;
++  void Pack(uint8_t *buffer)
++    {
++      _payload.Pack(buffer);
++    }
++
++  void UnPack(uint8_t *buffer)
++    {
++      _payload.UnPack(buffer);
++    }
++};
++
++int main()
++{
++  uint8_t * buffer = new uint8_t [30];
++  Msg msg;
++  Msg msg1;
++  msg._payload._pref.x             = 0xabcd;
++  msg._payload._pref.y             = 0xa;
++  msg._payload._pref.z             = 0x0001020304051617;
++  msg.Pack(&buffer[0]);
++  msg1.UnPack(&buffer[0]);
++  if (msg1._payload._pref.x != 0xabcd)
++    __builtin_abort ();
++  delete [] buffer;
++}
+Index: gcc/testsuite/g++.dg/torture/pr81987.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/torture/pr81987.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/torture/pr81987.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,61 @@
++extern short var_1;
++extern const short var_3;
++extern unsigned long int var_9;
++extern short var_13;
++extern const unsigned long int var_15;
++extern const unsigned long int var_37;
++extern unsigned long int var_40;
++extern long long int var_47;
++extern short var_48;
++extern const short var_54;
++extern long long int var_79;
++extern long long int var_81;
++extern long long int var_94;
++extern long long int var_95;
++extern long long int var_701;
++extern unsigned long int var_786;
++extern short var_788;
++extern long long int var_844;
++
++struct struct_1 {
++  short member_1_2 : 15;
++  static long long int member_1_3;
++};
++
++extern struct_1 struct_obj_6;
++extern struct_1 struct_obj_8;
++
++void foo() {
++  int a = var_3 <= 602154393864UL;
++  if (var_81 ? 0 : var_3 && var_9)
++    ;
++  else {
++    var_94 = 0;
++    if (var_3 && var_48 || var_13) {
++      if (var_48)
++	var_95 = 0;
++      short b((2364461588881776511UL + var_3) * (2 ? var_13 : 0) || var_1);
++      struct_obj_8.member_1_2 = b;
++      if (var_15) {
++	if (var_81)
++	  if (var_47)
++	    ;
++	  else if (var_40)
++	    var_701 = 0;
++      } else {
++	if (var_40)
++	  var_79 = 0;
++	if (var_54) {
++	  if (var_37)
++	    var_786 = 0;
++	  else
++	    var_788 = 0;
++	            struct_obj_6.member_1_3 =
++		      (2364461588881776511UL + var_3) * (2 ? var_13 : 0);
++	}
++      }
++      if ((2364461588881776511UL + var_3) * (2 ? var_13 : 0))
++	var_844 = 0;
++    }
++  }
++}
+Index: gcc/testsuite/g++.dg/ipa/pr82352.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/ipa/pr82352.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/ipa/pr82352.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,93 @@
++// PR ipa/82352
++// { dg-do compile }
++// { dg-options "-O2" }
++
++typedef __SIZE_TYPE__ size_t;
++
++class A
++{
++public :
++  typedef enum { Zero = 0, One = 1 } tA;
++  A(tA a) { m_a = a; }
++
++private :
++  tA m_a;
++};
++
++class B
++{
++public :
++  void *operator new(size_t t) { return (void*)(42); };
++};
++
++class C
++{
++public:
++  virtual void ffff () = 0;
++};
++
++class D
++{
++ public :
++  virtual void g() = 0;
++  virtual void h() = 0;
++};
++
++template<class T> class IIII: public T, public D
++{
++public:
++ void ffff()
++ {
++   if (!m_i2) throw A(A::One);
++ };
++
++ void h()
++ {
++  if (m_i2) throw A(A::Zero);
++ }
++
++protected:
++ virtual void g()
++ {
++  if (m_i1 !=0) throw A(A::Zero);
++ };
++
++private :
++ int m_i1;
++ void *m_i2;
++};
++
++class E
++{
++private:
++    size_t m_e;
++    static const size_t Max;
++
++public:
++    E& i(size_t a, size_t b, size_t c)
++    {
++        if ((a > Max) || (c > Max)) throw A(A::Zero );
++        if (a + b > m_e) throw A(A::One );
++        return (*this);
++    }
++
++  inline E& j(const E &s)
++    {
++      return i(0,0,s.m_e);
++    }
++};
++
++class F : public C { };
++class G : public C { };
++class HHHH : public B, public F, public G { };
++
++void k()
++{
++    new IIII<HHHH>();
++}
++
++void l()
++{
++  E e1, e2;
++  e1.j(e2);
++}
+Index: gcc/testsuite/g++.dg/cpp1y/vla-initlist1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1y/vla-initlist1.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1y/vla-initlist1.C	(.../branches/gcc-6-branch)
+@@ -1,4 +1,5 @@
+ // { dg-do run { target c++11 } }
++// { dg-skip-if "power overwrites two slots of array i" { "power*-*-*" } }
+ // { dg-options "-Wno-vla" }
+ 
+ #include <initializer_list>
+Index: gcc/testsuite/g++.dg/cpp1y/feat-cxx11.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1y/feat-cxx11.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1y/feat-cxx11.C	(.../branches/gcc-6-branch)
+@@ -125,6 +125,12 @@
+ #  error "__cpp_alias_templates != 200704"
+ #endif
+ 
++#ifndef __cpp_threadsafe_static_init
++#  error "__cpp_threadsafe_static_init"
++#elif __cpp_threadsafe_static_init != 200806
++#  error "__cpp_threadsafe_static_init != 200806"
++#endif
++
+ //  C++14 features allowed in C++11 in non-ANSI modes:
+ 
+ #ifndef __cpp_binary_literals
+Index: gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C	(.../branches/gcc-6-branch)
+@@ -118,6 +118,12 @@
+ #  error "__cpp_alias_templates != 200704"
+ #endif
+ 
++#ifndef __cpp_threadsafe_static_init
++#  error "__cpp_threadsafe_static_init"
++#elif __cpp_threadsafe_static_init != 200806
++#  error "__cpp_threadsafe_static_init != 200806"
++#endif
++
+ //  C++14 features:
+ 
+ #ifndef __cpp_binary_literals
+Index: gcc/testsuite/g++.dg/cpp1y/feat-cxx98.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1y/feat-cxx98.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1y/feat-cxx98.C	(.../branches/gcc-6-branch)
+@@ -15,6 +15,14 @@
+ #  error "__cpp_exceptions != 199711"
+ #endif
+ 
++//  C++11 features allowed in C++98:
++
++#ifndef __cpp_threadsafe_static_init
++#  error "__cpp_threadsafe_static_init"
++#elif __cpp_threadsafe_static_init != 200806
++#  error "__cpp_threadsafe_static_init != 200806"
++#endif
++
+ //  C++14 features allowed in C++98 in non-ANSI modes:
+ 
+ #ifndef __cpp_binary_literals
+Index: gcc/testsuite/g++.dg/cpp1y/feat-neg.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1y/feat-neg.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1y/feat-neg.C	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ // { dg-do compile }
+-// { dg-options "-fno-rtti -fno-exceptions" }
++// { dg-options "-fno-rtti -fno-exceptions -fno-threadsafe-statics" }
+ 
+ //  C++98 features with explicit opt-out:
+ 
+@@ -10,3 +10,9 @@
+ #ifndef __cpp_exceptions
+ #  error "__cpp_exceptions" // { dg-error "error" }
+ #endif
++
++//  C++11 features with explicit opt-out:
++
++#ifndef __cpp_threadsafe_static_init
++#  error "__cpp_threadsafe_static_init" // { dg-error "error" }
++#endif
+Index: gcc/testsuite/g++.dg/cpp1y/lambda-generic-nsdmi1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1y/lambda-generic-nsdmi1.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1y/lambda-generic-nsdmi1.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++// PR c++/84520
++// { dg-do compile { target c++14 } }
++
++struct A
++{
++  static void foo(int);
++  void (*f)(int) = [](auto i) { foo(i); };
++};
+Index: gcc/testsuite/g++.dg/cpp1z/feat-cxx1z.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1z/feat-cxx1z.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1z/feat-cxx1z.C	(.../branches/gcc-6-branch)
+@@ -106,6 +106,12 @@
+ #  error "__cpp_alias_templates != 200704"
+ #endif
+ 
++#ifndef __cpp_threadsafe_static_init
++#  error "__cpp_threadsafe_static_init"
++#elif __cpp_threadsafe_static_init != 200806
++#  error "__cpp_threadsafe_static_init != 200806"
++#endif
++
+ //  C++14 features:
+ 
+ #ifndef __cpp_binary_literals
+Index: gcc/testsuite/g++.dg/ext/altivec-18.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/ext/altivec-18.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/ext/altivec-18.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,14 @@
++// PR target/82112
++// { dg-do compile { target powerpc*-*-* } }
++// { dg-require-effective-target powerpc_altivec_ok }
++// { dg-options "-maltivec" }
++
++#include <altivec.h>
++
++__attribute__((aligned (16))) extern const unsigned char c[16];
++
++void
++foo (void)
++{
++  vec_ld (0, c);
++}
+Index: gcc/testsuite/g++.dg/ext/complit15.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/ext/complit15.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/ext/complit15.C	(.../branches/gcc-6-branch)
+@@ -1,4 +1,5 @@
+ // PR c++/79580
++// { dg-require-effective-target lto }
+ // { dg-options "-flto -std=c++98" }
+ 
+ class a
+Index: gcc/testsuite/g++.dg/pr80287.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/pr80287.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/pr80287.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,13 @@
++// PR c++/80287
++// { dg-do compile { target c++11 } }
++// { dg-options "-g" }
++
++struct A {
++  operator long() {}
++} __attribute__((__may_alias__));
++
++struct {
++  A ino;
++} a;
++
++char b = a.ino;
+Index: gcc/testsuite/g++.dg/other/anon5.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/other/anon5.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/other/anon5.C	(.../branches/gcc-6-branch)
+@@ -4,7 +4,7 @@
+ // Ignore additional message on powerpc-ibm-aix
+ // { dg-prune-output "obtain more information" } */
+ // Ignore additional messages on Linux/x86 with PIE
+-// { dg-prune-output "Bad value" } */
++// { dg-prune-output "\[Bb\]ad value" } */
+ 
+ namespace {
+   struct c
+Index: gcc/testsuite/g++.dg/tree-ssa/volatile2.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/tree-ssa/volatile2.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/tree-ssa/volatile2.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,20 @@
++// PR c++/84686
++// { dg-additional-options -fdump-tree-gimple }
++// { dg-final { scan-tree-dump-times "= i" 10 "gimple" } }
++
++volatile int i;
++
++int main()
++{
++  i; //evaluated (a load is performed)
++  (i); //unevaluated => the load shall be performed
++
++  (void)i; //evaluated (a load is performed)
++  (void)(i); //unevaluated => the load shall be performed
++
++  (void)i; //evaluated (a load is performed)
++  (void)(i); //unevaluated => the load shall be performed
++
++  (i,i); // the two subexpression are evaluated
++  ((i),(i)); // no evaluation, => two loads shall happen
++}
+Index: gcc/testsuite/g++.dg/tree-ssa/volatile1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/tree-ssa/volatile1.C	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/g++.dg/tree-ssa/volatile1.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,28 @@
++// PR c++/84151
++// { dg-additional-options "-fdump-tree-gimple" }
++// { dg-final { scan-tree-dump-not {\*this} "gimple" } }
++
++struct A {
++  static int& bar(int& a) {
++    return a;
++  }
++  static int i;
++
++  int foo() volatile {
++    int v = c;
++    return i + bar(v);
++  }
++
++  int c;
++};
++
++int A::i = 0;
++
++A a;
++
++int main() {
++  a.c = 2;
++  a.foo();
++
++  return 0;
++}
+Index: gcc/testsuite/c-c++-common/ubsan/pr81604.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/ubsan/pr81604.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/c-c++-common/ubsan/pr81604.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,31 @@
++/* PR sanitizer/81604 */
++/* { dg-do run } */
++/* { dg-options "-fsanitize=bounds,signed-integer-overflow" } */
++
++long a[10];
++
++__attribute__((noinline, noclone)) long *
++foo (int i)
++{
++  return &a[i];
++}
++
++__attribute__((noinline, noclone)) long
++bar (long x, long y)
++{
++  return x * y;
++}
++
++int
++main ()
++{
++  volatile int i = -1;
++  volatile long l = __LONG_MAX__;
++  long *volatile p;
++  p = foo (i);
++  l = bar (l, l);
++  return 0;
++}
++
++/* { dg-output "index -1 out of bounds for type 'long int \\\[10\\\]'\[^\n\r]*(\n|\r\n|\r)" } */
++/* { dg-output "\[^\n\r]*signed integer overflow: \[0-9]+ \\* \[0-9]+ cannot be represented in type 'long int'" } */
+Index: gcc/testsuite/c-c++-common/ubsan/float-cast-overflow-1.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/ubsan/float-cast-overflow-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/c-c++-common/ubsan/float-cast-overflow-1.c	(.../branches/gcc-6-branch)
+@@ -1,6 +1,7 @@
+ /* { dg-do run { target { lp64 || ilp32 } } } */
+ /* { dg-options "-fsanitize=float-cast-overflow" } */
+-/* { dg-additional-options "-msse2 -mfpmath=sse" { target { sse2_runtime && ia32 } } } */
++/* { dg-additional-options "-ffloat-store" { target { ia32 } } } */
++/* { dg-additional-options "-mieee" { target { { alpha*-*-* } || { sh*-*-* } } } } */
+ 
+ #include <limits.h>
+ #include "float-cast.h"
+Index: gcc/testsuite/c-c++-common/pr82112.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/pr82112.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/c-c++-common/pr82112.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,13 @@
++/* PR target/82112 */
++/* { dg-do compile } */
++
++int c[10], d[10], e[10], f[10], g[10], h[10], i[10], j[10], k[10], l[10];
++
++void
++foo (void)
++{
++  __atomic_load (c, d, __ATOMIC_ACQUIRE);
++  __atomic_store (e, f, __ATOMIC_SEQ_CST);
++  __atomic_exchange (g, h, i, __ATOMIC_RELAXED);
++  __atomic_compare_exchange (j, k, l, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
++}
+Index: gcc/testsuite/c-c++-common/Wunused-var-16.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/Wunused-var-16.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/c-c++-common/Wunused-var-16.c	(.../branches/gcc-6-branch)
+@@ -1,6 +1,7 @@
+ /* PR c++/78949 */
+ /* { dg-do compile } */
+ /* { dg-options "-Wunused" } */
++/* { dg-additional-options "-fno-common" { target hppa*-*-hpux* } } */
+ 
+ typedef unsigned char V __attribute__((vector_size(16)));
+ V v;
+Index: gcc/testsuite/c-c++-common/pr81052.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/pr81052.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/c-c++-common/pr81052.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,28 @@
++/* PR middle-end/81052 */
++/* { dg-do compile } */
++/* { dg-options "-fopenmp-simd -O2" } */
++
++int
++foo (int x, int y)
++{
++  int i;
++#pragma omp simd
++  for (i = x; i < y; ++i)
++    return 0;			/* { dg-error "invalid branch to/from OpenMP structured block" } */
++  return 1;
++}
++
++#ifdef __cplusplus
++template <typename T>
++T
++bar (T x, T y)
++{
++  T i;
++#pragma omp simd
++  for (i = x; i < y; ++i)
++    return 0;			/* { dg-error "invalid branch to/from OpenMP structured block" "" { target c++ } } */
++  return 1;
++}
++
++int x = bar (1, 7);
++#endif
+Index: gcc/testsuite/c-c++-common/builtin-shuffle-1.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/builtin-shuffle-1.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/testsuite/c-c++-common/builtin-shuffle-1.c	(.../branches/gcc-6-branch)
+@@ -1,5 +1,6 @@
+ /* PR c++/78089 */
+ /* { dg-do run } */
++/* { dg-additional-options "-fno-common" { target hppa*-*-hpux* } } */
+ 
+ typedef int V __attribute__((vector_size (16)));
+ V a, b, c;
+Index: gcc/cp/class.c
+===================================================================
+--- a/src/gcc/cp/class.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/cp/class.c	(.../branches/gcc-6-branch)
+@@ -1999,12 +1999,14 @@
+ static void
+ fixup_may_alias (tree klass)
+ {
+-  tree t;
++  tree t, v;
+ 
+   for (t = TYPE_POINTER_TO (klass); t; t = TYPE_NEXT_PTR_TO (t))
+-    TYPE_REF_CAN_ALIAS_ALL (t) = true;
++    for (v = TYPE_MAIN_VARIANT (t); v; v = TYPE_NEXT_VARIANT (v))
++      TYPE_REF_CAN_ALIAS_ALL (v) = true;
+   for (t = TYPE_REFERENCE_TO (klass); t; t = TYPE_NEXT_REF_TO (t))
+-    TYPE_REF_CAN_ALIAS_ALL (t) = true;
++    for (v = TYPE_MAIN_VARIANT (t); v; v = TYPE_NEXT_VARIANT (v))
++      TYPE_REF_CAN_ALIAS_ALL (v) = true;
+ }
+ 
+ /* Early variant fixups: we apply attributes at the beginning of the class
+Index: gcc/cp/ChangeLog
+===================================================================
+--- a/src/gcc/cp/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/cp/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,54 @@
++2018-03-09  Jason Merrill  <jason@redhat.com>
++
++	PR c++/84785 - ICE with alias template and default targs.
++	* pt.c (type_unification_real): Set processing_template_decl if
++	saw_undeduced == 1.
++
++2018-03-03  Jason Merrill  <jason@redhat.com>
++
++	PR c++/84686 - missing volatile loads.
++	* cvt.c (convert_to_void): Call maybe_undo_parenthesized_ref.
++
++2018-03-02  Jason Merrill  <jason@redhat.com>
++
++	PR c++/84489 - dependent default template argument
++	* pt.c (type_unification_real): Handle early substitution failure.
++
++2018-02-28  Jason Merrill  <jason@redhat.com>
++
++	PR c++/71784 - ICE with ref-qualifier and explicit specialization.
++	* pt.c (determine_specialization): Check ref-qualifier.
++
++2018-02-26  Jason Merrill  <jason@redhat.com>
++
++	PR c++/84441 - ICE with base initialized from ?:
++	* call.c (unsafe_copy_elision_p): Handle COND_EXPR.
++
++	PR c++/84520 - ICE with generic lambda in NSDMI.
++	* lambda.c (lambda_expr_this_capture): Don't look for fake NSDMI
++	'this' in a generic lambda instantiation.
++
++2018-02-16  Jason Merrill  <jason@redhat.com>
++
++	PR c++/84151 - unnecessary volatile load with static member.
++	* call.c (build_new_method_call_1): Avoid loading from a volatile
++	lvalue used as the object argument for a static member function.
++
++2017-09-15  Jakub Jelinek  <jakub@redhat.com>
++
++	Backported from mainline
++	2017-09-14  Jakub Jelinek  <jakub@redhat.com>
++
++	PR c++/81314
++	* cp-gimplify.c (omp_var_to_track): Look through references.
++	(omp_cxx_notice_variable): Likewise.
++
++2017-08-14  Paolo Carlini  <paolo.carlini@oracle.com>
++
++	PR c++/71570
++	* lambda.c (add_capture): Early return if we cannot capture by
++	reference.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: gcc/cp/cp-gimplify.c
+===================================================================
+--- a/src/gcc/cp/cp-gimplify.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/cp/cp-gimplify.c	(.../branches/gcc-6-branch)
+@@ -853,6 +853,8 @@
+   tree type = TREE_TYPE (decl);
+   if (is_invisiref_parm (decl))
+     type = TREE_TYPE (type);
++  else if (TREE_CODE (type) == REFERENCE_TYPE)
++    type = TREE_TYPE (type);
+   while (TREE_CODE (type) == ARRAY_TYPE)
+     type = TREE_TYPE (type);
+   if (type == error_mark_node || !CLASS_TYPE_P (type))
+@@ -905,6 +907,8 @@
+ 	      tree type = TREE_TYPE (decl);
+ 	      if (is_invisiref_parm (decl))
+ 		type = TREE_TYPE (type);
++	      else if (TREE_CODE (type) == REFERENCE_TYPE)
++		type = TREE_TYPE (type);
+ 	      while (TREE_CODE (type) == ARRAY_TYPE)
+ 		type = TREE_TYPE (type);
+ 	      get_copy_ctor (type, tf_none);
+Index: gcc/cp/pt.c
+===================================================================
+--- a/src/gcc/cp/pt.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/cp/pt.c	(.../branches/gcc-6-branch)
+@@ -2170,11 +2170,18 @@
+ 	     that the const qualification is the same.  Since
+ 	     get_bindings does not try to merge the "this" parameter,
+ 	     we must do the comparison explicitly.  */
+-	  if (DECL_NONSTATIC_MEMBER_FUNCTION_P (fn)
+-	      && !same_type_p (TREE_VALUE (fn_arg_types),
+-			       TREE_VALUE (decl_arg_types)))
+-	    continue;
++	  if (DECL_NONSTATIC_MEMBER_FUNCTION_P (fn))
++	    {
++	      if (!same_type_p (TREE_VALUE (fn_arg_types),
++				TREE_VALUE (decl_arg_types)))
++		continue;
+ 
++	      /* And the ref-qualification.  */
++	      if (type_memfn_rqual (TREE_TYPE (decl))
++		  != type_memfn_rqual (TREE_TYPE (fn)))
++		continue;
++	    }
++
+ 	  /* Skip the "this" parameter and, for constructors of
+ 	     classes with virtual bases, the VTT parameter.  A
+ 	     full specialization of a constructor will have a VTT
+@@ -2279,6 +2286,11 @@
+ 			 decl_arg_types))
+             continue;
+ 
++	  if (DECL_NONSTATIC_MEMBER_FUNCTION_P (fn)
++	      && (type_memfn_rqual (TREE_TYPE (decl))
++		  != type_memfn_rqual (TREE_TYPE (fn))))
++	    continue;
++
+           // If the deduced arguments do not satisfy the constraints,
+           // this is not a candidate.
+           if (flag_concepts && !constraints_satisfied_p (fn))
+@@ -18590,11 +18602,17 @@
+ 	  location_t save_loc = input_location;
+ 	  if (DECL_P (parm))
+ 	    input_location = DECL_SOURCE_LOCATION (parm);
++
++	  if (saw_undeduced == 1)
++	    ++processing_template_decl;
+ 	  arg = tsubst_template_arg (arg, targs, complain, NULL_TREE);
+-	  if (!uses_template_parms (arg))
++	  if (saw_undeduced == 1)
++	    --processing_template_decl;
++
++	  if (arg != error_mark_node && !uses_template_parms (arg))
+ 	    arg = convert_template_argument (parm, arg, targs, complain,
+ 					     i, NULL_TREE);
+-	  else if (saw_undeduced < 2)
++	  else if (saw_undeduced == 1)
+ 	    arg = NULL_TREE;
+ 	  else
+ 	    arg = error_mark_node;
+Index: gcc/cp/call.c
+===================================================================
+--- a/src/gcc/cp/call.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/cp/call.c	(.../branches/gcc-6-branch)
+@@ -7189,6 +7189,15 @@
+   /* build_compound_expr pushes COMPOUND_EXPR inside TARGET_EXPR.  */
+   while (TREE_CODE (init) == COMPOUND_EXPR)
+     init = TREE_OPERAND (init, 1);
++  if (TREE_CODE (init) == COND_EXPR)
++    {
++      /* We'll end up copying from each of the arms of the COND_EXPR directly
++	 into the target, so look at them. */
++      if (tree op = TREE_OPERAND (init, 1))
++	if (unsafe_copy_elision_p (target, op))
++	  return true;
++      return unsafe_copy_elision_p (target, TREE_OPERAND (init, 2));
++    }
+   return (TREE_CODE (init) == AGGR_INIT_EXPR
+ 	  && !AGGR_INIT_VIA_CTOR_P (init));
+ }
+@@ -8437,8 +8446,14 @@
+ 	      if (TREE_CODE (TREE_TYPE (fn)) != METHOD_TYPE
+ 		  && !is_dummy_object (instance)
+ 		  && TREE_SIDE_EFFECTS (instance))
+-		call = build2 (COMPOUND_EXPR, TREE_TYPE (call),
+-			       instance, call);
++		{
++		  /* But avoid the implicit lvalue-rvalue conversion when 'a'
++		     is volatile.  */
++		  tree a = instance;
++		  if (TREE_THIS_VOLATILE (a))
++		    a = build_this (a);
++		  call = build2 (COMPOUND_EXPR, TREE_TYPE (call), a, call);
++		}
+ 	      else if (call != error_mark_node
+ 		       && DECL_DESTRUCTOR_P (cand->fn)
+ 		       && !VOID_TYPE_P (TREE_TYPE (call)))
+Index: gcc/cp/lambda.c
+===================================================================
+--- a/src/gcc/cp/lambda.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/cp/lambda.c	(.../branches/gcc-6-branch)
+@@ -491,7 +491,10 @@
+ 	{
+ 	  type = build_reference_type (type);
+ 	  if (!dependent_type_p (type) && !real_lvalue_p (initializer))
+-	    error ("cannot capture %qE by reference", initializer);
++	    {
++	      error ("cannot capture %qE by reference", initializer);
++	      return error_mark_node;
++	    }
+ 	}
+       else
+ 	{
+@@ -662,11 +665,14 @@
+                                     lambda_stack);
+ 
+ 	  if (LAMBDA_EXPR_EXTRA_SCOPE (tlambda)
++	      && !COMPLETE_TYPE_P (LAMBDA_EXPR_CLOSURE (tlambda))
+ 	      && TREE_CODE (LAMBDA_EXPR_EXTRA_SCOPE (tlambda)) == FIELD_DECL)
+ 	    {
+ 	      /* In an NSDMI, we don't have a function to look up the decl in,
+ 		 but the fake 'this' pointer that we're using for parsing is
+-		 in scope_chain.  */
++		 in scope_chain.  But if the closure is already complete, we're
++	         in an instantiation of a generic lambda, and the fake 'this'
++	         is gone.  */
+ 	      init = scope_chain->x_current_class_ptr;
+ 	      gcc_checking_assert
+ 		(init && (TREE_TYPE (TREE_TYPE (init))
+Index: gcc/cp/cvt.c
+===================================================================
+--- a/src/gcc/cp/cvt.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/cp/cvt.c	(.../branches/gcc-6-branch)
+@@ -932,6 +932,8 @@
+       || TREE_TYPE (expr) == error_mark_node)
+     return error_mark_node;
+ 
++  expr = maybe_undo_parenthesized_ref (expr);
++
+   if (implicit == ICV_CAST)
+     mark_exp_read (expr);
+   else
+Index: gcc/lto-streamer-out.c
+===================================================================
+--- a/src/gcc/lto-streamer-out.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/lto-streamer-out.c	(.../branches/gcc-6-branch)
+@@ -2517,14 +2517,10 @@
+   const char *comdat;
+   unsigned char c;
+ 
+-  /* None of the following kinds of symbols are needed in the
+-     symbol table.  */
+-  if (!TREE_PUBLIC (t)
+-      || is_builtin_fn (t)
+-      || DECL_ABSTRACT_P (t)
+-      || (TREE_CODE (t) == VAR_DECL && DECL_HARD_REGISTER (t)))
+-    return;
+-  gcc_assert (TREE_CODE (t) != RESULT_DECL);
++  gcc_checking_assert (TREE_PUBLIC (t)
++		       && !is_builtin_fn (t)
++		       && !DECL_ABSTRACT_P (t)
++		       && (!VAR_P (t) || !DECL_HARD_REGISTER (t)));
+ 
+   gcc_assert (TREE_CODE (t) == VAR_DECL
+ 	      || TREE_CODE (t) == FUNCTION_DECL);
+@@ -2614,45 +2610,6 @@
+   lto_write_data (&slot_num, 4);
+ }
+ 
+-/* Return true if NODE should appear in the plugin symbol table.  */
+-
+-bool
+-output_symbol_p (symtab_node *node)
+-{
+-  struct cgraph_node *cnode;
+-  if (!node->real_symbol_p ())
+-    return false;
+-  /* We keep external functions in symtab for sake of inlining
+-     and devirtualization.  We do not want to see them in symbol table as
+-     references unless they are really used.  */
+-  cnode = dyn_cast <cgraph_node *> (node);
+-  if (cnode && (!node->definition || DECL_EXTERNAL (cnode->decl))
+-      && cnode->callers)
+-    return true;
+-
+- /* Ignore all references from external vars initializers - they are not really
+-    part of the compilation unit until they are used by folding.  Some symbols,
+-    like references to external construction vtables can not be referred to at all.
+-    We decide this at can_refer_decl_in_current_unit_p.  */
+- if (!node->definition || DECL_EXTERNAL (node->decl))
+-    {
+-      int i;
+-      struct ipa_ref *ref;
+-      for (i = 0; node->iterate_referring (i, ref); i++)
+-	{
+-	  if (ref->use == IPA_REF_ALIAS)
+-	    continue;
+-          if (is_a <cgraph_node *> (ref->referring))
+-	    return true;
+-	  if (!DECL_EXTERNAL (ref->referring->decl))
+-	    return true;
+-	}
+-      return false;
+-    }
+-  return true;
+-}
+-
+-
+ /* Write an IL symbol table to OB.
+    SET and VSET are cgraph/varpool node sets we are outputting.  */
+ 
+@@ -2677,7 +2634,7 @@
+     {
+       symtab_node *node = lsei_node (lsei);
+ 
+-      if (!output_symbol_p (node) || DECL_EXTERNAL (node->decl))
++      if (DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ())
+ 	continue;
+       write_symbol (cache, node->decl, &seen, false);
+     }
+@@ -2686,7 +2643,7 @@
+     {
+       symtab_node *node = lsei_node (lsei);
+ 
+-      if (!output_symbol_p (node) || !DECL_EXTERNAL (node->decl))
++      if (!DECL_EXTERNAL (node->decl) || !node->output_to_lto_symbol_table_p ())
+ 	continue;
+       write_symbol (cache, node->decl, &seen, false);
+     }
+Index: gcc/ipa-utils.c
+===================================================================
+--- a/src/gcc/ipa-utils.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ipa-utils.c	(.../branches/gcc-6-branch)
+@@ -403,6 +403,8 @@
+ 
+   if (!dst->count)
+     return;
++  if (!src->count || src->alias)
++    return;
+   if (symtab->dump_file)
+     {
+       fprintf (symtab->dump_file, "Merging profiles of %s/%i to %s/%i\n",
+Index: gcc/config.in
+===================================================================
+--- a/src/gcc/config.in	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config.in	(.../branches/gcc-6-branch)
+@@ -679,6 +679,12 @@
+ #endif
+ 
+ 
++/* Define if your assembler supports -xbrace_comment option. */
++#ifndef USED_FOR_TARGET
++#undef HAVE_AS_XBRACE_COMMENT_OPTION
++#endif
++
++
+ /* Define to 1 if you have the `atoq' function. */
+ #ifndef USED_FOR_TARGET
+ #undef HAVE_ATOQ
+Index: gcc/opts.c
+===================================================================
+--- a/src/gcc/opts.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/opts.c	(.../branches/gcc-6-branch)
+@@ -216,7 +216,7 @@
+ 		      unsigned int lang_mask ATTRIBUTE_UNUSED, int kind,
+ 		      location_t loc,
+ 		      const struct cl_option_handlers *handlers ATTRIBUTE_UNUSED,
+-		      diagnostic_context *dc)
++		      diagnostic_context *dc, void (*) (void))
+ {
+   gcc_assert (dc == global_dc);
+   gcc_assert (kind == DK_UNSPECIFIED);
+@@ -972,6 +972,26 @@
+       opts->x_flag_aggressive_loop_optimizations = 0;
+       opts->x_flag_strict_overflow = 0;
+     }
++
++  /* Comes from final.c -- no real reason to change it.  */
++#define MAX_CODE_ALIGN 16
++#define MAX_CODE_ALIGN_VALUE (1 << MAX_CODE_ALIGN)
++
++  if (opts->x_align_loops > MAX_CODE_ALIGN_VALUE)
++    error_at (loc, "-falign-loops=%d is not between 0 and %d",
++	      opts->x_align_loops, MAX_CODE_ALIGN_VALUE);
++
++  if (opts->x_align_jumps > MAX_CODE_ALIGN_VALUE)
++    error_at (loc, "-falign-jumps=%d is not between 0 and %d",
++	      opts->x_align_jumps, MAX_CODE_ALIGN_VALUE);
++
++  if (opts->x_align_functions > MAX_CODE_ALIGN_VALUE)
++    error_at (loc, "-falign-functions=%d is not between 0 and %d",
++	      opts->x_align_functions, MAX_CODE_ALIGN_VALUE);
++
++  if (opts->x_align_labels > MAX_CODE_ALIGN_VALUE)
++    error_at (loc, "-falign-labels=%d is not between 0 and %d",
++	      opts->x_align_labels, MAX_CODE_ALIGN_VALUE);
+ }
+ 
+ #define LEFT_COLUMN	27
+@@ -1543,7 +1563,8 @@
+ 		      unsigned int lang_mask, int kind ATTRIBUTE_UNUSED,
+ 		      location_t loc,
+ 		      const struct cl_option_handlers *handlers,
+-		      diagnostic_context *dc)
++		      diagnostic_context *dc,
++		      void (*target_option_override_hook) (void))
+ {
+   size_t scode = decoded->opt_index;
+   const char *arg = decoded->arg;
+@@ -1570,6 +1591,7 @@
+ 	undoc_mask = ((opts->x_verbose_flag | opts->x_extra_warnings)
+ 		      ? 0
+ 		      : CL_UNDOCUMENTED);
++	target_option_override_hook ();
+ 	/* First display any single language specific options.  */
+ 	for (i = 0; i < cl_lang_count; i++)
+ 	  print_specific_help
+@@ -1589,6 +1611,7 @@
+       if (lang_mask == CL_DRIVER)
+ 	break;
+ 
++      target_option_override_hook ();
+       print_specific_help (CL_TARGET, CL_UNDOCUMENTED, 0, opts, lang_mask);
+       opts->x_exit_after_options = true;
+       break;
+@@ -1710,8 +1733,11 @@
+ 	  }
+ 
+ 	if (include_flags)
+-	  print_specific_help (include_flags, exclude_flags, 0, opts,
+-			       lang_mask);
++	  {
++	    target_option_override_hook ();
++	    print_specific_help (include_flags, exclude_flags, 0, opts,
++				 lang_mask);
++	  }
+ 	opts->x_exit_after_options = true;
+ 	break;
+       }
+Index: gcc/opts.h
+===================================================================
+--- a/src/gcc/opts.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/opts.h	(.../branches/gcc-6-branch)
+@@ -267,7 +267,8 @@
+ 		   const struct cl_decoded_option *decoded,
+ 		   unsigned int lang_mask, int kind, location_t loc,
+ 		   const struct cl_option_handlers *handlers,
+-		   diagnostic_context *dc);
++		   diagnostic_context *dc,
++		   void (*target_option_override_hook) (void));
+ 
+   /* The mask that must have some bit in common with the flags for the
+      option for this particular handler to be used.  */
+@@ -289,6 +290,9 @@
+   void (*wrong_lang_callback) (const struct cl_decoded_option *decoded,
+ 			       unsigned int lang_mask);
+ 
++  /* Target option override hook.  */
++  void (*target_option_override_hook) (void);
++
+   /* The number of individual handlers.  */
+   size_t num_handlers;
+ 
+@@ -333,13 +337,15 @@
+ 							  const char **argv, 
+ 							  struct cl_decoded_option **decoded_options,
+ 							  unsigned int *decoded_options_count);
+-extern void set_default_handlers (struct cl_option_handlers *handlers);
++extern void set_default_handlers (struct cl_option_handlers *handlers,
++				  void (*target_option_override_hook) (void));
+ extern void decode_options (struct gcc_options *opts,
+ 			    struct gcc_options *opts_set,
+ 			    struct cl_decoded_option *decoded_options,
+ 			    unsigned int decoded_options_count,
+ 			    location_t loc,
+-			    diagnostic_context *dc);
++			    diagnostic_context *dc,
++			    void (*target_option_override_hook) (void));
+ extern int option_enabled (int opt_idx, void *opts);
+ extern bool get_option_state (struct gcc_options *, int,
+ 			      struct cl_option_state *);
+@@ -384,7 +390,8 @@
+ 				  unsigned int lang_mask, int kind,
+ 				  location_t loc,
+ 				  const struct cl_option_handlers *handlers,
+-				  diagnostic_context *dc);
++				  diagnostic_context *dc,
++				  void (*target_option_override_hook) (void));
+ extern bool target_handle_option (struct gcc_options *opts,
+ 				  struct gcc_options *opts_set,
+ 				  const struct cl_decoded_option *decoded,
+@@ -391,7 +398,8 @@
+ 				  unsigned int lang_mask, int kind,
+ 				  location_t loc,
+ 				  const struct cl_option_handlers *handlers,
+-				  diagnostic_context *dc);
++				  diagnostic_context *dc,
++				  void (*target_option_override_hook) (void));
+ extern void finish_options (struct gcc_options *opts,
+ 			    struct gcc_options *opts_set,
+ 			    location_t loc);
+Index: gcc/ada/ChangeLog
+===================================================================
+--- a/src/gcc/ada/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ada/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,45 @@
++2018-03-06  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gcc-interface/trans.c (convert_with_check): Fix typo in the condition
++	guarding the overflow check emitted for the upper bound of a floating-
++	point conversion.
++
++2017-12-14  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gcc-interface/decl.c (gnat_to_gnu_field): Do not set the alignment
++	of the enclosing record type if it is not already set.
++
++2017-11-10  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gcc-interface/utils.c (convert) <RECORD_TYPE>: Add comment and do
++	not fall through to the next case.
++	<ARRAY_TYPE>: Deal specially with a dereference from another array
++	type with the same element type.
++
++2017-09-15  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-08-29  Martin Liska  <mliska@suse.cz>
++
++	PR other/39851
++	* gcc-interface/trans.c (Pragma_to_gnu): Set argument to NULL.
++
++2017-09-05  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gcc-interface/utils.c (unchecked_convert): When the result type is a
++	non-biased integral type with size 0, set the result to 0 directly.
++
++2017-09-05  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gcc-interface/trans.c (Call_to_gnu): If this is a function call and
++	there is no target, do not create a temporary for the return value for
++	an allocator either.
++
++2017-09-05  Eric Botcazou  <ebotcazou@adacore.com>
++
++	* gcc-interface/trans.c (pos_to_constructor): Skip conversions to an
++	unconstrained array type.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: gcc/ada/gcc-interface/utils.c
+===================================================================
+--- a/src/gcc/ada/gcc-interface/utils.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ada/gcc-interface/utils.c	(.../branches/gcc-6-branch)
+@@ -4642,6 +4642,7 @@
+       return fold (convert_to_real (type, expr));
+ 
+     case RECORD_TYPE:
++      /* Do a normal conversion between scalar and justified modular type.  */
+       if (TYPE_JUSTIFIED_MODULAR_P (type) && !AGGREGATE_TYPE_P (etype))
+ 	{
+ 	  vec<constructor_elt, va_gc> *v;
+@@ -4653,9 +4654,27 @@
+ 	  return gnat_build_constructor (type, v);
+ 	}
+ 
+-      /* ... fall through ... */
++      /* In these cases, assume the front-end has validated the conversion.
++	 If the conversion is valid, it will be a bit-wise conversion, so
++	 it can be viewed as an unchecked conversion.  */
++      return unchecked_convert (type, expr, false);
+ 
+     case ARRAY_TYPE:
++      /* Do a normal conversion between unconstrained and constrained array
++	 type, assuming the latter is a constrained version of the former.  */
++      if (TREE_CODE (expr) == INDIRECT_REF
++	  && ecode == ARRAY_TYPE
++	  && TREE_TYPE (etype) == TREE_TYPE (type))
++	{
++	  tree ptr_type = build_pointer_type (type);
++	  tree t = build_unary_op (INDIRECT_REF, NULL_TREE,
++				   fold_convert (ptr_type,
++						 TREE_OPERAND (expr, 0)));
++	  TREE_READONLY (t) = TREE_READONLY (expr);
++	  TREE_THIS_NOTRAP (t) = TREE_THIS_NOTRAP (expr);
++	  return t;
++	}
++
+       /* In these cases, assume the front-end has validated the conversion.
+ 	 If the conversion is valid, it will be a bit-wise conversion, so
+ 	 it can be viewed as an unchecked conversion.  */
+@@ -5207,20 +5226,26 @@
+       && !(code == INTEGER_TYPE && TYPE_BIASED_REPRESENTATION_P (type))
+       && !(TYPE_UNSIGNED (type) && TYPE_UNSIGNED (etype)))
+     {
+-      tree base_type
+-	= gnat_type_for_size (TREE_INT_CST_LOW (TYPE_SIZE (type)),
+-			      TYPE_UNSIGNED (type));
+-      tree shift_expr
+-	= convert (base_type,
+-		   size_binop (MINUS_EXPR,
+-			       TYPE_SIZE (type), TYPE_RM_SIZE (type)));
+-      expr
+-	= convert (type,
+-		   build_binary_op (RSHIFT_EXPR, base_type,
+-				    build_binary_op (LSHIFT_EXPR, base_type,
+-						     convert (base_type, expr),
+-						     shift_expr),
+-				    shift_expr));
++      if (integer_zerop (TYPE_RM_SIZE (type)))
++	expr = build_int_cst (type, 0);
++      else
++	{
++	  tree base_type
++	    = gnat_type_for_size (TREE_INT_CST_LOW (TYPE_SIZE (type)),
++				  TYPE_UNSIGNED (type));
++	  tree shift_expr
++	    = convert (base_type,
++		       size_binop (MINUS_EXPR,
++				   TYPE_SIZE (type), TYPE_RM_SIZE (type)));
++	  expr
++	    = convert (type,
++		       build_binary_op (RSHIFT_EXPR, base_type,
++				        build_binary_op (LSHIFT_EXPR, base_type,
++							 convert (base_type,
++								  expr),
++							 shift_expr),
++				        shift_expr));
++	}
+     }
+ 
+   /* An unchecked conversion should never raise Constraint_Error.  The code
+Index: gcc/ada/gcc-interface/decl.c
+===================================================================
+--- a/src/gcc/ada/gcc-interface/decl.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ada/gcc-interface/decl.c	(.../branches/gcc-6-branch)
+@@ -6805,7 +6805,8 @@
+ 	{
+ 	  const unsigned int type_align = TYPE_ALIGN (gnu_field_type);
+ 
+-	  if (TYPE_ALIGN (gnu_record_type) < type_align)
++	  if (TYPE_ALIGN (gnu_record_type)
++	      && TYPE_ALIGN (gnu_record_type) < type_align)
+ 	    TYPE_ALIGN (gnu_record_type) = type_align;
+ 
+ 	  /* If the position is not a multiple of the alignment of the type,
+Index: gcc/ada/gcc-interface/trans.c
+===================================================================
+--- a/src/gcc/ada/gcc-interface/trans.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ada/gcc-interface/trans.c	(.../branches/gcc-6-branch)
+@@ -1469,7 +1469,7 @@
+ 	else
+ 	  option_index = 0;
+ 
+-	set_default_handlers (&handlers);
++	set_default_handlers (&handlers, NULL);
+ 	control_warning_option (option_index, (int) kind, arg, imply, location,
+ 				lang_mask, &handlers, &global_options,
+ 				&global_options_set, global_dc);
+@@ -4303,11 +4303,11 @@
+ 	  parameters.
+ 
+        2. There is no target and the call is made for neither an object nor a
+-	  renaming declaration, nor a return statement, and the return type has
+-	  variable size, because in this case the gimplifier cannot create the
+-	  temporary, or more generally is simply an aggregate type, because the
+-	  gimplifier would create the temporary in the outermost scope instead
+-	  of locally.
++	  renaming declaration, nor a return statement, nor an allocator, and
++	  the return type has variable size because in this case the gimplifier
++	  cannot create the temporary, or more generally is simply an aggregate
++	  type, because the gimplifier would then create the temporary in the
++	  outermost scope instead of locally.
+ 
+        3. There is a target and it is a slice or an array with fixed size,
+ 	  and the return type has variable size, because the gimplifier
+@@ -4326,6 +4326,8 @@
+ 	      && Nkind (Parent (gnat_node)) != N_Object_Declaration
+ 	      && Nkind (Parent (gnat_node)) != N_Object_Renaming_Declaration
+ 	      && Nkind (Parent (gnat_node)) != N_Simple_Return_Statement
++	      && !(Nkind (Parent (gnat_node)) == N_Qualified_Expression
++		   && Nkind (Parent (Parent (gnat_node))) == N_Allocator)
+ 	      && AGGREGATE_TYPE_P (gnu_result_type)
+ 	      && !TYPE_IS_FAT_POINTER_P (gnu_result_type))
+ 	  || (gnu_target
+@@ -9213,7 +9215,7 @@
+ 	  ? tree_int_cst_lt (gnu_out_ub, gnu_in_ub)
+ 	  : (FLOAT_TYPE_P (gnu_base_type)
+ 	     ? real_less (&TREE_REAL_CST (gnu_out_ub),
+-			  &TREE_REAL_CST (gnu_in_lb))
++			  &TREE_REAL_CST (gnu_in_ub))
+ 	     : 1))
+ 	gnu_cond
+ 	  = build_binary_op (TRUTH_ORIF_EXPR, boolean_type_node, gnu_cond,
+@@ -9649,7 +9651,14 @@
+ 				       gnat_component_type);
+       else
+ 	{
+-	  gnu_expr = gnat_to_gnu (gnat_expr);
++	  /* If the expression is a conversion to an unconstrained array type,
++	     skip it to avoid spilling to memory.  */
++	  if (Nkind (gnat_expr) == N_Type_Conversion
++	      && Is_Array_Type (Etype (gnat_expr))
++	      && !Is_Constrained (Etype (gnat_expr)))
++	    gnu_expr = gnat_to_gnu (Expression (gnat_expr));
++	  else
++	    gnu_expr = gnat_to_gnu (gnat_expr);
+ 
+ 	  /* Before assigning the element to the array, make sure it is
+ 	     in range.  */
+Index: gcc/asan.c
+===================================================================
+--- a/src/gcc/asan.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/asan.c	(.../branches/gcc-6-branch)
+@@ -1800,6 +1800,9 @@
+       || bitsize != size_in_bytes * BITS_PER_UNIT)
+     return;
+ 
++  if (TREE_CODE (inner) == VAR_DECL && DECL_HARD_REGISTER (inner))
++    return;
++
+   if (TREE_CODE (inner) == VAR_DECL
+       && offset == NULL_TREE
+       && bitpos >= 0
+Index: gcc/lra-remat.c
+===================================================================
+--- a/src/gcc/lra-remat.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/lra-remat.c	(.../branches/gcc-6-branch)
+@@ -753,7 +753,7 @@
+ 
+ 	if (regno2 >= FIRST_PSEUDO_REGISTER && reg_renumber[regno2] >= 0)
+ 	  regno2 = reg_renumber[regno2];
+-	if (regno >= FIRST_PSEUDO_REGISTER)
++	if (regno2 >= FIRST_PSEUDO_REGISTER)
+ 	  nregs2 = 1;
+ 	else
+ 	  nregs2 = hard_regno_nregs[regno2][reg->biggest_mode];
+Index: gcc/gimple-ssa-strength-reduction.c
+===================================================================
+--- a/src/gcc/gimple-ssa-strength-reduction.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/gimple-ssa-strength-reduction.c	(.../branches/gcc-6-branch)
+@@ -469,7 +469,8 @@
+ 
+   c = base_cand_from_table (base);
+ 
+-  if (!c || c->kind != CAND_PHI)
++  if (!c || c->kind != CAND_PHI
++      || SSA_NAME_OCCURS_IN_ABNORMAL_PHI (gimple_phi_result (c->cand_stmt)))
+     return 0;
+ 
+   return c->cand_num;
+@@ -507,6 +508,11 @@
+ 			      gimple_bb (one_basis->cand_stmt)))
+ 	continue;
+ 
++      tree lhs = gimple_assign_lhs (one_basis->cand_stmt);
++      if (lhs && TREE_CODE (lhs) == SSA_NAME
++	  && SSA_NAME_OCCURS_IN_ABNORMAL_PHI (lhs))
++	continue;
++
+       if (!basis || basis->cand_num < one_basis->cand_num)
+ 	basis = one_basis;
+     }
+@@ -2005,91 +2011,92 @@
+   tree target_type = TREE_TYPE (gimple_assign_lhs (c->cand_stmt));
+   enum tree_code cand_code = gimple_assign_rhs_code (c->cand_stmt);
+ 
+-  /* It is highly unlikely, but possible, that the resulting
+-     bump doesn't fit in a HWI.  Abandon the replacement
+-     in this case.  This does not affect siblings or dependents
+-     of C.  Restriction to signed HWI is conservative for unsigned
+-     types but allows for safe negation without twisted logic.  */
+-  if (wi::fits_shwi_p (bump)
+-      && bump.to_shwi () != HOST_WIDE_INT_MIN
+-      /* It is not useful to replace casts, copies, or adds of
+-	 an SSA name and a constant.  */
+-      && cand_code != MODIFY_EXPR
+-      && !CONVERT_EXPR_CODE_P (cand_code)
+-      && cand_code != PLUS_EXPR
+-      && cand_code != POINTER_PLUS_EXPR
+-      && cand_code != MINUS_EXPR)
++  /* It is not useful to replace casts, copies, negates, or adds of
++     an SSA name and a constant.  */
++  if (cand_code == MODIFY_EXPR
++      || CONVERT_EXPR_CODE_P (cand_code)
++      || cand_code == PLUS_EXPR
++      || cand_code == POINTER_PLUS_EXPR
++      || cand_code == MINUS_EXPR
++      || cand_code == NEGATE_EXPR)
++    return;
++
++  enum tree_code code = PLUS_EXPR;
++  tree bump_tree;
++  gimple *stmt_to_print = NULL;
++
++  /* If the basis name and the candidate's LHS have incompatible
++     types, introduce a cast.  */
++  if (!useless_type_conversion_p (target_type, TREE_TYPE (basis_name)))
++    basis_name = introduce_cast_before_cand (c, target_type, basis_name);
++  if (wi::neg_p (bump))
+     {
+-      enum tree_code code = PLUS_EXPR;
+-      tree bump_tree;
+-      gimple *stmt_to_print = NULL;
++      code = MINUS_EXPR;
++      bump = -bump;
++    }
+ 
+-      /* If the basis name and the candidate's LHS have incompatible
+-	 types, introduce a cast.  */
+-      if (!useless_type_conversion_p (target_type, TREE_TYPE (basis_name)))
+-	basis_name = introduce_cast_before_cand (c, target_type, basis_name);
+-      if (wi::neg_p (bump))
+-	{
+-	  code = MINUS_EXPR;
+-	  bump = -bump;
+-	}
++ /* It is possible that the resulting bump doesn't fit in target_type.
++    Abandon the replacement in this case.  This does not affect
++    siblings or dependents of C.  */
++  if (bump != wi::ext (bump, TYPE_PRECISION (target_type),
++		       TYPE_SIGN (target_type)))
++    return;
+ 
+-      bump_tree = wide_int_to_tree (target_type, bump);
++  bump_tree = wide_int_to_tree (target_type, bump);
+ 
++  if (dump_file && (dump_flags & TDF_DETAILS))
++    {
++      fputs ("Replacing: ", dump_file);
++      print_gimple_stmt (dump_file, c->cand_stmt, 0, 0);
++    }
++
++  if (bump == 0)
++    {
++      tree lhs = gimple_assign_lhs (c->cand_stmt);
++      gassign *copy_stmt = gimple_build_assign (lhs, basis_name);
++      gimple_stmt_iterator gsi = gsi_for_stmt (c->cand_stmt);
++      gimple_set_location (copy_stmt, gimple_location (c->cand_stmt));
++      gsi_replace (&gsi, copy_stmt, false);
++      c->cand_stmt = copy_stmt;
+       if (dump_file && (dump_flags & TDF_DETAILS))
++	stmt_to_print = copy_stmt;
++    }
++  else
++    {
++      tree rhs1, rhs2;
++      if (cand_code != NEGATE_EXPR) {
++	rhs1 = gimple_assign_rhs1 (c->cand_stmt);
++	rhs2 = gimple_assign_rhs2 (c->cand_stmt);
++      }
++      if (cand_code != NEGATE_EXPR
++	  && ((operand_equal_p (rhs1, basis_name, 0)
++	       && operand_equal_p (rhs2, bump_tree, 0))
++	      || (operand_equal_p (rhs1, bump_tree, 0)
++		  && operand_equal_p (rhs2, basis_name, 0))))
+ 	{
+-	  fputs ("Replacing: ", dump_file);
+-	  print_gimple_stmt (dump_file, c->cand_stmt, 0, 0);
++	  if (dump_file && (dump_flags & TDF_DETAILS))
++	    {
++	      fputs ("(duplicate, not actually replacing)", dump_file);
++	      stmt_to_print = c->cand_stmt;
++	    }
+ 	}
+-
+-      if (bump == 0)
++      else
+ 	{
+-	  tree lhs = gimple_assign_lhs (c->cand_stmt);
+-	  gassign *copy_stmt = gimple_build_assign (lhs, basis_name);
+ 	  gimple_stmt_iterator gsi = gsi_for_stmt (c->cand_stmt);
+-	  gimple_set_location (copy_stmt, gimple_location (c->cand_stmt));
+-	  gsi_replace (&gsi, copy_stmt, false);
+-	  c->cand_stmt = copy_stmt;
++	  gimple_assign_set_rhs_with_ops (&gsi, code,
++					  basis_name, bump_tree);
++	  update_stmt (gsi_stmt (gsi));
++	  c->cand_stmt = gsi_stmt (gsi);
+ 	  if (dump_file && (dump_flags & TDF_DETAILS))
+-	    stmt_to_print = copy_stmt;
++	    stmt_to_print = gsi_stmt (gsi);
+ 	}
+-      else
+-	{
+-	  tree rhs1, rhs2;
+-	  if (cand_code != NEGATE_EXPR) {
+-	    rhs1 = gimple_assign_rhs1 (c->cand_stmt);
+-	    rhs2 = gimple_assign_rhs2 (c->cand_stmt);
+-	  }
+-	  if (cand_code != NEGATE_EXPR
+-	      && ((operand_equal_p (rhs1, basis_name, 0)
+-		   && operand_equal_p (rhs2, bump_tree, 0))
+-		  || (operand_equal_p (rhs1, bump_tree, 0)
+-		      && operand_equal_p (rhs2, basis_name, 0))))
+-	    {
+-	      if (dump_file && (dump_flags & TDF_DETAILS))
+-		{
+-		  fputs ("(duplicate, not actually replacing)", dump_file);
+-		  stmt_to_print = c->cand_stmt;
+-		}
+-	    }
+-	  else
+-	    {
+-	      gimple_stmt_iterator gsi = gsi_for_stmt (c->cand_stmt);
+-	      gimple_assign_set_rhs_with_ops (&gsi, code,
+-					      basis_name, bump_tree);
+-	      update_stmt (gsi_stmt (gsi));
+-              c->cand_stmt = gsi_stmt (gsi);
+-	      if (dump_file && (dump_flags & TDF_DETAILS))
+-		stmt_to_print = gsi_stmt (gsi);
+-	    }
+-	}
++    }
+   
+-      if (dump_file && (dump_flags & TDF_DETAILS))
+-	{
+-	  fputs ("With: ", dump_file);
+-	  print_gimple_stmt (dump_file, stmt_to_print, 0, 0);
+-	  fputs ("\n", dump_file);
+-  	}
++  if (dump_file && (dump_flags & TDF_DETAILS))
++    {
++      fputs ("With: ", dump_file);
++      print_gimple_stmt (dump_file, stmt_to_print, 0, 0);
++      fputs ("\n", dump_file);
+     }
+ }
+ 
+@@ -2141,8 +2148,6 @@
+ 			     widest_int increment, edge e, location_t loc,
+ 			     bool known_stride)
+ {
+-  basic_block insert_bb;
+-  gimple_stmt_iterator gsi;
+   tree lhs, basis_type;
+   gassign *new_stmt;
+ 
+@@ -2197,19 +2202,13 @@
+ 	gcc_unreachable ();
+     }
+ 
+-  insert_bb = single_succ_p (e->src) ? e->src : split_edge (e);
+-  gsi = gsi_last_bb (insert_bb);
+-
+-  if (!gsi_end_p (gsi) && is_ctrl_stmt (gsi_stmt (gsi)))
+-    gsi_insert_before (&gsi, new_stmt, GSI_NEW_STMT);
+-  else
+-    gsi_insert_after (&gsi, new_stmt, GSI_NEW_STMT);
+-
+   gimple_set_location (new_stmt, loc);
++  gsi_insert_on_edge (e, new_stmt);
+ 
+   if (dump_file && (dump_flags & TDF_DETAILS))
+     {
+-      fprintf (dump_file, "Inserting in block %d: ", insert_bb->index);
++      fprintf (dump_file, "Inserting on edge %d->%d: ", e->src->index,
++	       e->dest->index);
+       print_gimple_stmt (dump_file, new_stmt, 0, 0);
+     }
+ 
+@@ -3136,6 +3135,23 @@
+ 	 that block, the earliest one will be returned in WHERE.  */
+       bb = nearest_common_dominator_for_cands (c, incr, &where);
+ 
++      /* If the NCD is not dominated by the block containing the
++	 definition of the stride, we can't legally insert a
++	 single initializer.  Mark the increment as unprofitable
++	 so we don't make any replacements.  FIXME: Multiple
++	 initializers could be placed with more analysis.  */
++      gimple *stride_def = SSA_NAME_DEF_STMT (c->stride);
++      basic_block stride_bb = gimple_bb (stride_def);
++
++      if (stride_bb && !dominated_by_p (CDI_DOMINATORS, bb, stride_bb))
++	{
++	  if (dump_file && (dump_flags & TDF_DETAILS))
++	    fprintf (dump_file,
++		     "Initializer #%d cannot be legally placed\n", i);
++	  incr_vec[i].cost = COST_INFINITE;
++	  continue;
++	}
++
+       /* Create a new SSA name to hold the initializer's value.  */
+       stride_type = TREE_TYPE (c->stride);
+       new_name = make_temp_ssa_name (stride_type, NULL, "slsr");
+@@ -3577,6 +3593,10 @@
+ 	  free (incr_vec);
+ 	}
+     }
++
++  /* For conditional candidates, we may have uncommitted insertions
++     on edges to clean up.  */
++  gsi_commit_edge_inserts ();
+ }
+ 
+ namespace {
+Index: gcc/fortran/interface.c
+===================================================================
+--- a/src/gcc/fortran/interface.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/interface.c	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ /* Deal with interfaces.
+-   Copyright (C) 2000-2016 Free Software Foundation, Inc.
++   Copyright (C) 2000-2016,2018 Free Software Foundation, Inc.
+    Contributed by Andy Vaught
+ 
+ This file is part of GCC.
+@@ -1165,8 +1165,13 @@
+ static int
+ symbol_rank (gfc_symbol *sym)
+ {
+-  gfc_array_spec *as;
+-  as = (sym->ts.type == BT_CLASS) ? CLASS_DATA (sym)->as : sym->as;
++  gfc_array_spec *as = NULL;
++
++  if (sym->ts.type == BT_CLASS && CLASS_DATA (sym) && CLASS_DATA (sym)->as)
++    as = CLASS_DATA (sym)->as;
++  else
++    as = sym->as;
++
+   return as ? as->rank : 0;
+ }
+ 
+@@ -2705,7 +2710,8 @@
+ 
+ static int
+ compare_actual_formal (gfc_actual_arglist **ap, gfc_formal_arglist *formal,
+-	 	       int ranks_must_agree, int is_elemental, locus *where)
++	 	       int ranks_must_agree, int is_elemental,
++		       bool in_statement_function, locus *where)
+ {
+   gfc_actual_arglist **new_arg, *a, *actual;
+   gfc_formal_arglist *f;
+@@ -2733,6 +2739,13 @@
+ 
+   for (a = actual; a; a = a->next, f = f->next)
+     {
++      if (a->name != NULL && in_statement_function)
++	{
++	  gfc_error ("Keyword argument %qs at %L is invalid in "
++		     "a statement function", a->name, &a->expr->where);
++	  return false;
++	}
++
+       /* Look for keywords but ignore g77 extensions like %VAL.  */
+       if (a->name != NULL && a->name[0] != '%')
+ 	{
+@@ -3053,8 +3066,9 @@
+ 	}
+ 
+       /* Check intent = OUT/INOUT for definable actual argument.  */
+-      if ((f->sym->attr.intent == INTENT_OUT
+-	  || f->sym->attr.intent == INTENT_INOUT))
++      if (!in_statement_function
++	  && (f->sym->attr.intent == INTENT_OUT
++	      || f->sym->attr.intent == INTENT_INOUT))
+ 	{
+ 	  const char* context = (where
+ 				 ? _("actual argument to INTENT = OUT/INOUT")
+@@ -3152,7 +3166,8 @@
+ 		       "at %L", where);
+ 	  return 0;
+ 	}
+-      if (!f->sym->attr.optional)
++      if (!f->sym->attr.optional
++	  || (in_statement_function && f->sym->attr.optional))
+ 	{
+ 	  if (where)
+ 	    gfc_error ("Missing actual argument for argument %qs at %L",
+@@ -3438,6 +3453,7 @@
+ bool
+ gfc_procedure_use (gfc_symbol *sym, gfc_actual_arglist **ap, locus *where)
+ {
++  gfc_actual_arglist *a;
+   gfc_formal_arglist *dummy_args;
+ 
+   /* Warn about calls with an implicit interface.  Special case
+@@ -3464,8 +3480,6 @@
+ 
+   if (sym->attr.if_source == IFSRC_UNKNOWN)
+     {
+-      gfc_actual_arglist *a;
+-
+       if (sym->attr.pointer)
+ 	{
+ 	  gfc_error ("The pointer object %qs at %L must have an explicit "
+@@ -3557,9 +3571,12 @@
+ 
+   dummy_args = gfc_sym_get_dummy_args (sym);
+ 
+-  if (!compare_actual_formal (ap, dummy_args, 0, sym->attr.elemental, where))
++  /* For a statement function, check that types and type parameters of actual
++     arguments and dummy arguments match.  */
++  if (!compare_actual_formal (ap, dummy_args, 0, sym->attr.elemental,
++			      sym->attr.proc == PROC_ST_FUNCTION, where))
+     return false;
+-
++ 
+   if (!check_intents (dummy_args, *ap))
+     return false;
+ 
+@@ -3606,7 +3623,7 @@
+     }
+ 
+   if (!compare_actual_formal (ap, comp->ts.interface->formal, 0,
+-			      comp->attr.elemental, where))
++			      comp->attr.elemental, false, where))
+     return;
+ 
+   check_intents (comp->ts.interface->formal, *ap);
+@@ -3631,7 +3648,7 @@
+   dummy_args = gfc_sym_get_dummy_args (sym);
+ 
+   r = !sym->attr.elemental;
+-  if (compare_actual_formal (args, dummy_args, r, !r, NULL))
++  if (compare_actual_formal (args, dummy_args, r, !r, false, NULL))
+     {
+       check_intents (dummy_args, *args);
+       if (warn_aliasing)
+Index: gcc/fortran/trans-expr.c
+===================================================================
+--- a/src/gcc/fortran/trans-expr.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/trans-expr.c	(.../branches/gcc-6-branch)
+@@ -890,6 +890,7 @@
+     }
+ 
+   if ((ref == NULL || class_ref == ref)
++      && !(gfc_is_class_array_function (e) && parmse->class_vptr != NULL_TREE)
+       && (!class_ts.u.derived->components->as
+ 	  || class_ts.u.derived->components->as->rank != -1))
+     return;
+@@ -960,8 +961,11 @@
+      First we have to find the corresponding class reference.  */
+ 
+   tmp = NULL_TREE;
+-  if (class_ref == NULL
+-	&& e->symtree && e->symtree->n.sym->ts.type == BT_CLASS)
++  if (gfc_is_class_array_function (e)
++      && parmse->class_vptr != NULL_TREE)
++    tmp = parmse->class_vptr;
++  else if (class_ref == NULL
++	   && e->symtree && e->symtree->n.sym->ts.type == BT_CLASS)
+     {
+       tmp = e->symtree->n.sym->backend_decl;
+       if (DECL_LANG_SPECIFIC (tmp) && GFC_DECL_SAVED_DESCRIPTOR (tmp))
+@@ -988,7 +992,11 @@
+   if (TREE_CODE (TREE_TYPE (tmp)) == REFERENCE_TYPE)
+     tmp = build_fold_indirect_ref_loc (input_location, tmp);
+ 
+-  vptr = gfc_class_vptr_get (tmp);
++  if (!(gfc_is_class_array_function (e) && parmse->class_vptr))
++    vptr = gfc_class_vptr_get (tmp);
++  else
++    vptr = tmp;
++
+   gfc_add_modify (&block, ctree,
+ 		  fold_convert (TREE_TYPE (ctree), vptr));
+ 
+@@ -2348,7 +2356,7 @@
+      On the other hand, if the context is a UNION or a MAP (a
+      RECORD_TYPE within a UNION_TYPE) always use the given FIELD_DECL.  */
+ 
+-  if (context != TREE_TYPE (decl) 
++  if (context != TREE_TYPE (decl)
+       && !(   TREE_CODE (TREE_TYPE (field)) == UNION_TYPE /* Field is union */
+            || TREE_CODE (context) == UNION_TYPE))         /* Field is map */
+     {
+@@ -4150,9 +4158,7 @@
+       if (arg2 && arg2->expr_type == EXPR_CONSTANT)
+ 	d = mpz_get_si (arg2->value.integer) - 1;
+       else
+-	/* TODO: If the need arises, this could produce an array of
+-	   ubound/lbounds.  */
+-	gcc_unreachable ();
++	return false;
+ 
+       if (expr->value.function.isym->id == GFC_ISYM_LBOUND)
+ 	{
+@@ -4281,6 +4287,8 @@
+ 
+       if (expr->value.function.esym == NULL
+ 	    && expr->value.function.isym != NULL
++	    && expr->value.function.actual
++	    && expr->value.function.actual->expr
+ 	    && expr->value.function.actual->expr->symtree
+ 	    && gfc_map_intrinsic_function (expr, mapping))
+ 	break;
+@@ -4409,7 +4417,7 @@
+   /* Reset the offset for the function call since the loop
+      is zero based on the data pointer.  Note that the temp
+      comes first in the loop chain since it is added second.  */
+-  if (gfc_is_alloc_class_array_function (expr))
++  if (gfc_is_class_array_function (expr))
+     {
+       tmp = loop.ss->loop_chain->info->data.array.descriptor;
+       gfc_conv_descriptor_offset_set (&loop.pre, tmp,
+@@ -4458,7 +4466,7 @@
+   dimen = rse.ss->dimen;
+ 
+   /* Skip the write-out loop for this case.  */
+-  if (gfc_is_alloc_class_array_function (expr))
++  if (gfc_is_class_array_function (expr))
+     goto class_array_fcn;
+ 
+   /* Calculate the bounds of the scalarization.  */
+@@ -4751,7 +4759,7 @@
+ 	      gcc_assert ((!comp && gfc_return_by_reference (sym)
+ 			   && sym->result->attr.dimension)
+ 			  || (comp && comp->attr.dimension)
+-			  || gfc_is_alloc_class_array_function (expr));
++			  || gfc_is_class_array_function (expr));
+ 	      gcc_assert (se->loop != NULL);
+ 	      /* Access the previously obtained result.  */
+ 	      gfc_conv_tmp_array_ref (se);
+@@ -5404,7 +5412,7 @@
+ 				fsym ? fsym->attr.intent : INTENT_INOUT,
+ 				fsym && fsym->attr.pointer);
+ 
+-	      else if (gfc_is_alloc_class_array_function (e)
++	      else if (gfc_is_class_array_function (e)
+ 			 && fsym && fsym->ts.type == BT_DERIVED)
+ 		/* See previous comment.  For function actual argument,
+ 		   the write out is not needed so the intent is set as
+@@ -5554,7 +5562,7 @@
+ 
+ 	  tmp = gfc_deallocate_alloc_comp (e->ts.u.derived, tmp, parm_rank);
+ 
+-	  gfc_add_expr_to_block (&se->post, tmp);
++	  gfc_prepend_expr_to_block (&post, tmp);
+         }
+ 
+       /* Add argument checking of passing an unallocated/NULL actual to
+@@ -6193,7 +6201,7 @@
+ 	 call the finalization function of the temporary. Note that the
+ 	 nullification of allocatable components needed by the result
+ 	 is done in gfc_trans_assignment_1.  */
+-      if (expr && ((gfc_is_alloc_class_array_function (expr)
++      if (expr && ((gfc_is_class_array_function (expr)
+ 		    && se->ss && se->ss->loop)
+ 		   || gfc_is_alloc_class_scalar_function (expr))
+ 	  && se->expr && GFC_CLASS_TYPE_P (TREE_TYPE (se->expr))
+@@ -6204,6 +6212,7 @@
+ 	  int n;
+ 	  if (se->ss && se->ss->loop)
+ 	    {
++	      gfc_add_block_to_block (&se->ss->loop->pre, &se->pre);
+ 	      se->expr = gfc_evaluate_now (se->expr, &se->ss->loop->pre);
+ 	      tmp = gfc_class_data_get (se->expr);
+ 	      info->descriptor = tmp;
+@@ -6226,6 +6235,11 @@
+ 			CLASS_DATA (expr->value.function.esym->result)->attr);
+ 	    }
+ 
++	  if ((gfc_is_class_array_function (expr)
++	       || gfc_is_alloc_class_scalar_function (expr))
++	      && CLASS_DATA (expr->value.function.esym->result)->attr.pointer)
++	    goto no_finalization;
++
+ 	  final_fndecl = gfc_class_vtab_final_get (se->expr);
+ 	  is_final = fold_build2_loc (input_location, NE_EXPR,
+ 				      boolean_type_node,
+@@ -6256,6 +6270,8 @@
+ 	      tmp = gfc_call_free (tmp);
+ 	      gfc_add_expr_to_block (&se->post, tmp);
+ 	    }
++
++no_finalization:
+ 	  expr->must_finalize = 0;
+ 	}
+ 
+@@ -8394,7 +8410,7 @@
+   gfc_symbol *sym = expr1->symtree->n.sym;
+ 
+   /* Play it safe with class functions assigned to a derived type.  */
+-  if (gfc_is_alloc_class_array_function (expr2)
++  if (gfc_is_class_array_function (expr2)
+       && expr1->ts.type == BT_DERIVED)
+     return true;
+ 
+@@ -9273,7 +9289,7 @@
+   rss = NULL;
+ 
+   if ((expr1->ts.type == BT_DERIVED)
+-      && (gfc_is_alloc_class_array_function (expr2)
++      && (gfc_is_class_array_function (expr2)
+ 	  || gfc_is_alloc_class_scalar_function (expr2)))
+     expr2->must_finalize = 1;
+ 
+@@ -9444,9 +9460,9 @@
+      nullification occurs before the call to the finalizer. In the case of
+      a scalar to array assignment, this is done in gfc_trans_scalar_assign
+      as part of the deep copy.  */
+-  if (!scalar_to_array && (expr1->ts.type == BT_DERIVED)
+-					      && (gfc_is_alloc_class_array_function (expr2)
+-						      || gfc_is_alloc_class_scalar_function (expr2)))
++  if (!scalar_to_array
++      && (expr1->ts.type == BT_DERIVED)
++      && (gfc_is_class_array_function (expr2) || gfc_is_alloc_class_scalar_function (expr2)))
+     {
+       tmp = rse.expr;
+       tmp = gfc_nullify_alloc_comp (expr1->ts.u.derived, rse.expr, 0);
+Index: gcc/fortran/trans-array.c
+===================================================================
+--- a/src/gcc/fortran/trans-array.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/trans-array.c	(.../branches/gcc-6-branch)
+@@ -1431,6 +1431,17 @@
+ 	    }
+ 	}
+     }
++  else if (GFC_CLASS_TYPE_P (TREE_TYPE (se->expr))
++	   && !GFC_CLASS_TYPE_P (gfc_get_element_type (TREE_TYPE (desc))))
++    {
++      /* Assignment of a CLASS array constructor to a derived type array.  */
++      if (expr->expr_type == EXPR_FUNCTION)
++	se->expr = gfc_evaluate_now (se->expr, pblock);
++      se->expr = gfc_class_data_get (se->expr);
++      se->expr = build_fold_indirect_ref_loc (input_location, se->expr);
++      se->expr = fold_convert (TREE_TYPE (tmp), se->expr);
++      gfc_add_modify (&se->pre, tmp, se->expr);
++    }
+   else
+     {
+       /* TODO: Should the frontend already have done this conversion?  */
+@@ -2604,6 +2615,8 @@
+ 	  gfc_init_se (&se, NULL);
+ 	  se.loop = loop;
+ 	  se.ss = ss;
++	  if (gfc_is_class_array_function (expr))
++	    expr->must_finalize = 1;
+ 	  gfc_conv_expr (&se, expr);
+ 	  gfc_add_block_to_block (&outer_loop->pre, &se.pre);
+ 	  gfc_add_block_to_block (&outer_loop->post, &se.post);
+@@ -3034,7 +3047,7 @@
+ 
+   if (expr == NULL
+       || (expr->ts.type != BT_CLASS
+-	  && !gfc_is_alloc_class_array_function (expr)))
++	  && !gfc_is_class_array_function (expr)))
+     return false;
+ 
+   if (expr->symtree && expr->symtree->n.sym->ts.type == BT_CLASS)
+@@ -3063,12 +3076,12 @@
+     return false;
+ 
+   if (class_ref == NULL && expr->symtree->n.sym->attr.function
+-      && expr->symtree->n.sym == expr->symtree->n.sym->result)
++      && expr->symtree->n.sym == expr->symtree->n.sym->result
++      && expr->symtree->n.sym->backend_decl == current_function_decl)
+     {
+-      gcc_assert (expr->symtree->n.sym->backend_decl == current_function_decl);
+       decl = gfc_get_fake_result_decl (expr->symtree->n.sym, 0);
+     }
+-  else if (gfc_is_alloc_class_array_function (expr))
++  else if (gfc_is_class_array_function (expr))
+     {
+       size = NULL_TREE;
+       decl = NULL_TREE;
+@@ -3091,6 +3104,8 @@
+ 
+       if (decl == NULL_TREE)
+ 	return false;
++
++      se->class_vptr = gfc_evaluate_now (gfc_class_vptr_get (decl), &se->pre);
+     }
+   else if (class_ref == NULL)
+     {
+@@ -9526,7 +9541,7 @@
+   if (!sym)
+     sym = expr->symtree->n.sym;
+ 
+-  if (gfc_is_alloc_class_array_function (expr))
++  if (gfc_is_class_array_function (expr))
+     return gfc_get_array_ss (ss, expr,
+ 			     CLASS_DATA (expr->value.function.esym->result)->as->rank,
+ 			     GFC_SS_FUNCTION);
+Index: gcc/fortran/decl.c
+===================================================================
+--- a/src/gcc/fortran/decl.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/decl.c	(.../branches/gcc-6-branch)
+@@ -573,6 +573,20 @@
+       if (m != MATCH_YES)
+ 	goto cleanup;
+ 
++      if (new_data->var->iter.var
++	  && new_data->var->iter.var->ts.type == BT_INTEGER
++	  && new_data->var->iter.var->symtree->n.sym->attr.implied_index == 1
++	  && new_data->var->list
++	  && new_data->var->list->expr
++	  && new_data->var->list->expr->ts.type == BT_CHARACTER
++	  && new_data->var->list->expr->ref
++	  && new_data->var->list->expr->ref->type == REF_SUBSTRING)
++	{
++	  gfc_error ("Invalid substring in data-implied-do at %L in DATA "
++		     "statement", &new_data->var->list->expr->where);
++	  goto cleanup;
++	}
++
+       m = top_val_list (new_data);
+       if (m != MATCH_YES)
+ 	goto cleanup;
+@@ -1383,8 +1397,28 @@
+   symbol_attribute attr;
+   gfc_symbol *sym;
+   int upper;
++  gfc_symtree *st;
+ 
+-  if (gfc_get_symbol (name, NULL, &sym))
++  /* Symbols in a submodule are host associated from the parent module or
++     submodules. Therefore, they can be overridden by declarations in the
++     submodule scope. Deal with this by attaching the existing symbol to
++     a new symtree and recycling the old symtree with a new symbol...  */
++  st = gfc_find_symtree (gfc_current_ns->sym_root, name);
++  if (st != NULL && gfc_state_stack->state == COMP_SUBMODULE
++      && st->n.sym != NULL
++      && st->n.sym->attr.host_assoc && st->n.sym->attr.used_in_submodule)
++    {
++      gfc_symtree *s = gfc_get_unique_symtree (gfc_current_ns);
++      s->n.sym = st->n.sym;
++      sym = gfc_new_symbol (name, gfc_current_ns);
++
++
++      st->n.sym = sym;
++      sym->refs++;
++      gfc_set_sym_referenced (sym);
++    }
++  /* ...Otherwise generate a new symtree and new symbol.  */
++  else if (gfc_get_symbol (name, NULL, &sym))
+     return false;
+ 
+   /* Check if the name has already been defined as a type.  The
+@@ -1672,7 +1706,7 @@
+ 		    }
+ 		  else if (init->expr_type == EXPR_ARRAY)
+ 		    {
+-		      if (init->ts.u.cl)
++		      if (init->ts.u.cl && init->ts.u.cl->length)
+ 			clen = mpz_get_si (init->ts.u.cl->length->value.integer);
+ 		      else if (init->value.constructor)
+ 			{
+@@ -2186,7 +2220,10 @@
+   /* At this point, we know for sure if the symbol is PARAMETER and can thus
+      determine (and check) whether it can be implied-shape.  If it
+      was parsed as assumed-size, change it because PARAMETERs can not
+-     be assumed-size.  */
++     be assumed-size.
++
++     An explicit-shape-array cannot appear under several conditions.
++     That check is done here as well.  */
+   if (as)
+     {
+       if (as->type == AS_IMPLIED_SHAPE && current_attr.flavor != FL_PARAMETER)
+@@ -2208,6 +2245,50 @@
+ 	  m = MATCH_ERROR;
+ 	  goto cleanup;
+ 	}
++
++      /* F2018:C830 (R816) An explicit-shape-spec whose bounds are not
++	 constant expressions shall appear only in a subprogram, derived
++	 type definition, BLOCK construct, or interface body.  */
++      if (as->type == AS_EXPLICIT
++	  && gfc_current_state () != COMP_BLOCK
++	  && gfc_current_state () != COMP_DERIVED
++	  && gfc_current_state () != COMP_FUNCTION
++	  && gfc_current_state () != COMP_INTERFACE
++	  && gfc_current_state () != COMP_SUBROUTINE)
++	{
++	  gfc_expr *e;
++	  bool not_constant = false;
++
++	  for (int i = 0; i < as->rank; i++)
++	    {
++	      e = gfc_copy_expr (as->lower[i]);
++	      gfc_resolve_expr (e);
++	      gfc_simplify_expr (e, 0);
++	      if (e && (e->expr_type != EXPR_CONSTANT))
++		{
++		  not_constant = true;
++		  break;
++		}
++	      gfc_free_expr (e);
++
++	      e = gfc_copy_expr (as->upper[i]);
++	      gfc_resolve_expr (e);
++	      gfc_simplify_expr (e, 0);
++	      if (e && (e->expr_type != EXPR_CONSTANT))
++		{
++		  not_constant = true;
++		  break;
++		}
++	      gfc_free_expr (e);
++	    }
++
++	  if (not_constant)
++	    { 
++	      gfc_error ("Explicit shaped array with nonconstant bounds at %C");
++	      m = MATCH_ERROR;
++	      goto cleanup;
++	    }
++	}
+     }
+ 
+   char_len = NULL;
+@@ -2926,7 +3007,24 @@
+   if (seen_length == 0)
+     cl->length = gfc_get_int_expr (gfc_default_integer_kind, NULL, 1);
+   else
+-    cl->length = len;
++    {
++      /* If gfortran ends up here, then the len may be reducible to a
++	 constant.  Try to do that here.  If it does not reduce, simply
++	 assign len to the charlen.  */
++      if (len && len->expr_type != EXPR_CONSTANT)
++	{
++	  gfc_expr *e;
++	  e = gfc_copy_expr (len);
++	  gfc_reduce_init_expr (e);
++	  if (e->expr_type == EXPR_CONSTANT)
++	    gfc_replace_expr (len, e);
++	  else
++	    gfc_free_expr (e);
++	  cl->length = len;
++	}
++      else
++	cl->length = len;
++    }
+ 
+   ts->u.cl = cl;
+   ts->kind = kind == 0 ? gfc_default_character_kind : kind;
+Index: gcc/fortran/gfortran.h
+===================================================================
+--- a/src/gcc/fortran/gfortran.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/gfortran.h	(.../branches/gcc-6-branch)
+@@ -3057,7 +3057,7 @@
+ gfc_component * gfc_get_proc_ptr_comp (gfc_expr *);
+ bool gfc_is_proc_ptr_comp (gfc_expr *);
+ bool gfc_is_alloc_class_scalar_function (gfc_expr *);
+-bool gfc_is_alloc_class_array_function (gfc_expr *);
++bool gfc_is_class_array_function (gfc_expr *);
+ 
+ bool gfc_ref_this_image (gfc_ref *ref);
+ bool gfc_is_coindexed (gfc_expr *);
+Index: gcc/fortran/ChangeLog
+===================================================================
+--- a/src/gcc/fortran/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,297 @@
++2018-03-10  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/84734
++	* arith.c (check_result, eval_intrinsic):  If result overflows, pass
++	the expression up the chain instead of a NULL pointer.
++
++2018-03-08 Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/64124
++	PR fortran/70409
++	* decl.c (gfc_match_char_spec): Try to reduce a charlen to a constant.
++
++2018-03-06  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/56667
++	* primary.c (match_sym_complex_part): Give the matcher for an implied
++	do-loop a chance to run.
++
++2018-03-03  Harald Anlauf  <anlauf@gmx.de>
++
++	PR fortran/71085
++	* trans-expr.c (gfc_apply_interface_mapping_to_expr): Do not
++	dereference NULL pointer.
++
++2018-03-03  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk.
++	PR fortran/78990
++	* expr.c (gfc_is_class_array_function): Renamed from
++	'gfc_is_alloc_class_array_function' and modified to return true
++	for pointers as well as allocatable results.
++	* gfortran.h : Change of name for prototype of above function.
++	* trans-array.c (gfc_add_loop_ss_code): Force finalization of
++	class array results.
++	(build_class_array_ref): Change assertion into a condition.
++	(build_class_array_ref): Set the se class_vptr for class array
++	function results.
++	(gfc_walk_function_expr): Reference gfc_is_class_array_function
++	as above.
++	* trans-decl.c (get_proc_result): Move it up before
++	gfc_trans_deferred_vars.
++	(gfc_trans_deferred_vars): Nullify explicit return class arrays
++	on entry.
++	* trans-expr.c (gfc_conv_class_to_class): Allow conversion of
++	class array functions that have an se class_vptr and use it
++	for the result vptr.
++	(gfc_conv_subref_array_arg): Rename reference to the above
++	function.
++	(gfc_conv_procedure_call): Ditto. Add the se pre block to the
++	loop pre block before the function is evaluated. Do not
++	finalize class pointer results.
++	(arrayfunc_assign_needs_temporary, gfc_trans_assignment_1) More
++	renamed references.
++	* trans-intrinsic.c (gfc_conv_intrinsic_size): Ditto.
++
++2018-02-25  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/83633
++	* decl.c (variable_decl): Check that an explicit-shape-array with
++	nonconstant bounds is allowed.
++
++2018-02-24  Steven G. Kargl <kargl@gcc.gnu.org>
++
++	PR fortran/30792
++	* decl.c (gfc_match_data): Check for invalid substring in
++	data-implied-do
++
++2018-02-23  Jerry DeLisle  <jvdelisle@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/84506
++	* trans-io.c (set_parameter_value_inquire): Adjust range check of
++	negative unit values for kind=8 units to the kind=4 negative limit.
++
++2018-02-23  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/84511
++	* trans-io.c (transfer_expr): Deal with C_LOC in transfer statement.
++
++2018-02-23  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/84346
++	* interface.c (compare_actual_formal): Issue error if keyword is
++	used in a statement function.
++
++2018-02-13  Alastair McKinstry  <alastair.mckinstry@sceal.ie>
++	    Janne Blomqvist  <jb@gcc.gnu.org>
++
++	* module.c (dump_module): Use lbasename to ensure that module
++	files are reproducible.
++
++2018-02-12  Thomas Koenig  <tkoenig@gcc.gnu.org>
++
++	PR fortran/68560
++	* gfortran.dg/shape_9.f90: New test.
++
++2018-02-12  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
++
++	PR fortran/35299
++	ChangeLog for r257566
++	* resolve.c (resolve_formal_arglist): Update error message.
++
++2018-02-12  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/54223
++	PR fortran/84276
++	* interface.c (compare_actual_formal): Add in_statement_function
++	bool parameter.  Skip check of INTENT attribute for statement
++	functions.  Arguments to a statement function cannot be optional,
++	issue error for missing argument.
++	(gfc_procedure_use, gfc_ppc_use, gfc_arglist_matches_symbol): Use
++	in_statement_function.
++
++2018-02-07  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/82994
++	* match.c (gfc_match_deallocate): Check for NULL pointer.
++
++2018-02-07  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/82049
++	* match.c (gfc_match_type_spec): If the charlen is non-NULL, then
++	try to resolve it.  While here return early if possible.
++
++2018-01-20  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/83900
++    * simplify.c (gfc_simplify_matmul): Set return type correctly.
++
++2018-01-19  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/83900
++	* simplify.c (gfc_simplify_matmul): Delete bogus assertion.
++
++2018-01-19  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	Backport of r250734 from mainline
++	PR fortran/80768
++	* check.c (gfc_check_num_images): Fix typo.
++
++2018-01-17  Harald Anlauf  <anlauf@gmx.de>
++
++	Back from mainline
++	PR fortran/83874
++	* decl.c (add_init_expr_to_sym): Do not dereference NULL pointer.
++
++2018-01-13  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	Backport from mainline
++	PR fortran/78814
++	* interface.c (symbol_rank): Check for NULL pointer.
++
++2018-01-10  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/82367
++	* resolve.c (resolve_allocate_expr): Check for NULL pointer.
++
++2018-01-10 Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/83093
++	* resolve.c (resolve_charlen): Check the type of cl->length
++	after resolution.
++
++2018-01-10  Steven G. Kargl  <kargl@kgcc.gnu.org>
++
++	Backport r254555 from trunk
++	PR Fortran/82841
++	* simplify.c(gfc_simplify_transfer): Do not dereference a NULL pointer.
++	Unwrap a short line.
++
++2018-01-04  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR Fortran/83679
++	* simplify.c (gfc_simplify_cshift): Restore early return for zero-sized
++	array.  Update Copyright year while here.
++
++2018-01-02  Thomas Koenig  <tkoenig@gcc.gnu.org>
++
++	Backport from 7-branch
++	PR fortran/83650
++	* simplify.c (gfc_simplify_cshift): Correct contition for
++	negative shifts.
++
++2017-11-13  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/82934
++	* trans-stmt.c (gfc_trans_allocate): Remove the gcc_assert on
++	null string length for assumed length typespec and set
++	expr3_esize to NULL_TREE;
++
++2017-11-13  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/78619
++	* check.c (same_type_check): Introduce a new argument 'assoc'
++	with default value false. If this is true, use the symbol type
++	spec of BT_PROCEDURE expressions.
++	(gfc_check_associated): Set 'assoc' true in the call to
++	'same_type_check'.
++
++2017-11-06  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backported from trunk
++	PR fortran/78641
++	* resolve.c (resolve_ordinary_assign): Do not add the _data
++	component for class valued array constructors being assigned
++	to derived type arrays.
++	* trans-array.c (gfc_trans_array_ctor_element): Take the _data
++	of class valued elements for assignment to derived type arrays.
++
++2017-11-06  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backported from trunk
++	PR fortran/69739
++	* trans-expr.c (gfc_map_intrinsic_function): Return false for
++	bounds without the DIM argument instead of ICEing.
++
++2017-11-01  Steven G. Kargl  <kargl@gcc.gnu.org>
++
++	PR fortran/82796
++	* resolve.c (resolve_equivalence): An entity in a common block within
++ 	a module cannot appear in an equivalence statement if the entity is
++	with a pure procedure.
++
++2017-11-03  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from 7-branch
++	PR fortran/81735
++	* trans-decl.c (gfc_trans_deferred_vars): Correct case where
++	'tmp' can be used unititialized.
++
++2017-11-01  Andre Vehreschild  <vehre@gcc.gnu.org>
++	Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/78293
++	* trans-expr.c (gfc_conv_procedure_call): Prepend deallocation
++	of alloctable components to post, rather than adding to
++	se->post.
++	* trans-stmt.c (gfc_trans_allocate): Move deallocation of expr3
++	allocatable components so that all expr3s are visited.
++
++2017-11-01  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/80554
++	* decl.c (build_sym): In a submodule allow overriding of host
++	associated symbols from the ancestor module with a new
++	declaration.
++
++2017-11-01  Paul Thomas  <pault@gcc.gnu.org>
++
++	PR fortran/80554
++	* gfortran.dg/submodule_29.f08: New test.
++
++2017-10-20  Thomas Koenig  <tkoenig@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/79795
++	* resolve.c (resovle_symbol): Change gcc_assert to
++	sensible error message.
++
++2017-10-19  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/79402
++	* resolve.c (fixup_unique_dummy): New function.
++	(gfc_resolve_expr): Call it for dummy variables with a unique
++	symtree name.
++
++2017-10-19  Paul Thomas  <pault@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/81048
++	* resolve.c (resolve_symbol): Ensure that derived type array
++	results get default initialization.
++
++2017-10-06  Thomas Koenig <tkoenig@gcc.gnu.org>
++	    Steven G. Kargl <kargl@gcc.gnu.org>
++
++	Backport from trunk
++	* expr.c (gfc_get_full_arrayspec_from_expr): If there is
++	no symtree, set array spec to NULL.
++
++2017-09-02  Janus Weil  <janus@gcc.gnu.org>
++
++	Backport from trunk
++	PR fortran/81770
++	* expr.c (gfc_check_pointer_assign): Improve the check whether pointer
++	may outlive pointer target.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: gcc/fortran/trans-stmt.c
+===================================================================
+--- a/src/gcc/fortran/trans-stmt.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/trans-stmt.c	(.../branches/gcc-6-branch)
+@@ -5492,17 +5492,6 @@
+ 	    }
+ 	  gfc_add_modify_loc (input_location, &block, var, tmp);
+ 
+-	  /* Deallocate any allocatable components after all the allocations
+-	     and assignments of expr3 have been completed.  */
+-	  if (code->expr3->ts.type == BT_DERIVED
+-	      && code->expr3->rank == 0
+-	      && code->expr3->ts.u.derived->attr.alloc_comp)
+-	    {
+-	      tmp = gfc_deallocate_alloc_comp (code->expr3->ts.u.derived,
+-					       var, 0);
+-	      gfc_add_expr_to_block (&post, tmp);
+-	    }
+-
+ 	  expr3 = var;
+ 	  if (se.string_length)
+ 	    /* Evaluate it assuming that it also is complicated like expr3.  */
+@@ -5513,6 +5502,19 @@
+ 	  expr3 = se.expr;
+ 	  expr3_len = se.string_length;
+ 	}
++
++      /* Deallocate any allocatable components after all the allocations
++	 and assignments of expr3 have been completed.  */
++      if ((code->expr3->ts.type == BT_DERIVED
++	   || code->expr3->ts.type == BT_CLASS)
++	  && (code->expr3->expr_type != EXPR_VARIABLE || temp_var_needed)
++	  && code->expr3->ts.u.derived->attr.alloc_comp)
++	{
++	  tmp = gfc_deallocate_alloc_comp (code->expr3->ts.u.derived,
++					   expr3, code->expr3->rank);
++	  gfc_prepend_expr_to_block (&post, tmp);
++	}
++
+       /* Store what the expr3 is to be used for.  */
+       if (e3_is == E3_UNSET)
+ 	e3_is = expr3 != NULL_TREE ?
+@@ -5691,10 +5693,9 @@
+       if (code->ext.alloc.ts.type != BT_CHARACTER)
+ 	expr3_esize = TYPE_SIZE_UNIT (
+ 	      gfc_typenode_for_spec (&code->ext.alloc.ts));
+-      else
++      else if (code->ext.alloc.ts.u.cl->length != NULL)
+ 	{
+ 	  gfc_expr *sz;
+-	  gcc_assert (code->ext.alloc.ts.u.cl->length != NULL);
+ 	  sz = gfc_copy_expr (code->ext.alloc.ts.u.cl->length);
+ 	  gfc_init_se (&se_sz, NULL);
+ 	  gfc_conv_expr (&se_sz, sz);
+@@ -5708,6 +5709,8 @@
+ 					 tmp, se_sz.expr);
+ 	  expr3_esize = gfc_evaluate_now (expr3_esize, &block);
+ 	}
++      else
++	expr3_esize = NULL_TREE;
+     }
+ 
+   /* Loop over all objects to allocate.  */
+Index: gcc/fortran/expr.c
+===================================================================
+--- a/src/gcc/fortran/expr.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/expr.c	(.../branches/gcc-6-branch)
+@@ -3768,7 +3768,8 @@
+   if (warn_target_lifetime
+       && rvalue->expr_type == EXPR_VARIABLE
+       && !rvalue->symtree->n.sym->attr.save
+-      && !attr.pointer && !rvalue->symtree->n.sym->attr.host_assoc
++      && !rvalue->symtree->n.sym->attr.pointer && !attr.pointer
++      && !rvalue->symtree->n.sym->attr.host_assoc
+       && !rvalue->symtree->n.sym->attr.in_common
+       && !rvalue->symtree->n.sym->attr.use_assoc
+       && !rvalue->symtree->n.sym->attr.dummy)
+@@ -4101,7 +4102,11 @@
+   if (expr->expr_type == EXPR_VARIABLE
+       || expr->expr_type == EXPR_CONSTANT)
+     {
+-      as = expr->symtree->n.sym->as;
++      if (expr->symtree)
++	as = expr->symtree->n.sym->as;
++      else
++	as = NULL;
++
+       for (ref = expr->ref; ref; ref = ref->next)
+ 	{
+ 	  switch (ref->type)
+@@ -4343,7 +4348,7 @@
+ /* Determine if an expression is a function with an allocatable class array
+    result.  */
+ bool
+-gfc_is_alloc_class_array_function (gfc_expr *expr)
++gfc_is_class_array_function (gfc_expr *expr)
+ {
+   if (expr->expr_type == EXPR_FUNCTION
+       && expr->value.function.esym
+@@ -4350,7 +4355,8 @@
+       && expr->value.function.esym->result
+       && expr->value.function.esym->result->ts.type == BT_CLASS
+       && CLASS_DATA (expr->value.function.esym->result)->attr.dimension
+-      && CLASS_DATA (expr->value.function.esym->result)->attr.allocatable)
++      && (CLASS_DATA (expr->value.function.esym->result)->attr.allocatable
++	  || CLASS_DATA (expr->value.function.esym->result)->attr.pointer))
+     return true;
+ 
+   return false;
+Index: gcc/fortran/module.c
+===================================================================
+--- a/src/gcc/fortran/module.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/module.c	(.../branches/gcc-6-branch)
+@@ -6080,8 +6080,10 @@
+     gfc_fatal_error ("Can't open module file %qs for writing at %C: %s",
+ 		     filename_tmp, xstrerror (errno));
+ 
++  /* Use lbasename to ensure module files are reproducible regardless
++     of the build path (see the reproducible builds project).  */
+   gzprintf (module_fp, "GFORTRAN module version '%s' created from %s\n",
+-	    MOD_VERSION, gfc_source_file);
++	    MOD_VERSION, lbasename (gfc_source_file));
+ 
+   /* Write the module itself.  */
+   iomode = IO_OUTPUT;
+Index: gcc/fortran/resolve.c
+===================================================================
+--- a/src/gcc/fortran/resolve.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/resolve.c	(.../branches/gcc-6-branch)
+@@ -506,8 +506,11 @@
+ 	{
+ 	  if (sym->as != NULL)
+ 	    {
+-	      gfc_error ("Argument %qs of statement function at %L must "
+-			 "be scalar", sym->name, &sym->declared_at);
++	      /* F03:C1263 (R1238) The function-name and each dummy-arg-name
++		 shall be specified, explicitly or implicitly, to be scalar.  */
++	      gfc_error ("Argument '%s' of statement function '%s' at %L "
++			 "must be scalar", sym->name, proc->name,
++			 &proc->declared_at);
+ 	      continue;
+ 	    }
+ 
+@@ -6313,6 +6316,31 @@
+   return false;
+ }
+ 
++
++/* Sometimes variables in specification expressions of the result
++   of module procedures in submodules wind up not being the 'real'
++   dummy.  Find this, if possible, in the namespace of the first
++   formal argument.  */
++
++static void
++fixup_unique_dummy (gfc_expr *e)
++{
++  gfc_symtree *st = NULL;
++  gfc_symbol *s = NULL;
++
++  if (e->symtree->n.sym->ns->proc_name
++      && e->symtree->n.sym->ns->proc_name->formal)
++    s = e->symtree->n.sym->ns->proc_name->formal->sym;
++
++  if (s != NULL)
++    st = gfc_find_symtree (s->ns->sym_root, e->symtree->n.sym->name);
++
++  if (st != NULL
++      && st->n.sym != NULL
++      && st->n.sym->attr.dummy)
++    e->symtree = st;
++}
++
+ /* Resolve an expression.  That is, make sure that types of operands agree
+    with their operators, intrinsic operators are converted to function calls
+    for overloaded types and unresolved function references are resolved.  */
+@@ -6337,6 +6365,14 @@
+       actual_arg = false;
+       first_actual_arg = false;
+     }
++  else if (e->symtree != NULL
++	   && *e->symtree->name == '@'
++	   && e->symtree->n.sym->attr.dummy)
++    {
++      /* Deal with submodule specification expressions that are not
++	 found to be referenced in module.c(read_cleanup).  */
++      fixup_unique_dummy (e);
++    }
+ 
+   switch (e->expr_type)
+     {
+@@ -7103,8 +7139,13 @@
+   if (code->ext.alloc.ts.type == BT_CHARACTER && !e->ts.deferred
+       && !UNLIMITED_POLY (e))
+     {
+-      int cmp = gfc_dep_compare_expr (e->ts.u.cl->length,
+-				      code->ext.alloc.ts.u.cl->length);
++      int cmp;
++
++      if (!e->ts.u.cl->length)
++	goto failure;
++
++      cmp = gfc_dep_compare_expr (e->ts.u.cl->length,
++				  code->ext.alloc.ts.u.cl->length);
+       if (cmp == 1 || cmp == -1 || cmp == -3)
+ 	{
+ 	  gfc_error ("Allocating %s at %L with type-spec requires the same "
+@@ -8303,6 +8344,9 @@
+ 	code->expr1->symtree->n.sym->ts = code->expr2->ts;
+       selector_type = CLASS_DATA (code->expr2)->ts.u.derived;
+ 
++      if (code->expr2->rank && CLASS_DATA (code->expr1)->as)
++	CLASS_DATA (code->expr1)->as->rank = code->expr2->rank;
++
+       /* F2008: C803 The selector expression must not be coindexed.  */
+       if (gfc_is_coindexed (code->expr2))
+ 	{
+@@ -9758,7 +9802,8 @@
+ 
+   /* Assign the 'data' of a class object to a derived type.  */
+   if (lhs->ts.type == BT_DERIVED
+-      && rhs->ts.type == BT_CLASS)
++      && rhs->ts.type == BT_CLASS
++      && rhs->expr_type != EXPR_ARRAY)
+     gfc_add_data_component (rhs);
+ 
+   /* Insert a GFC_ISYM_CAF_SEND intrinsic, when the LHS is a coindexed variable.
+@@ -11043,10 +11088,17 @@
+ 	  specification_expr = saved_specification_expr;
+ 	  return false;
+ 	}
++
++      /* cl->length has been resolved.  It should have an integer type.  */
++      if (cl->length && cl->length->ts.type != BT_INTEGER)
++	{
++	  gfc_error ("Scalar INTEGER expression expected at %L",
++		     &cl->length->where);
++	  return false;
++	}
+     }
+   else
+     {
+-
+       if (!resolve_index_expr (cl->length))
+ 	{
+ 	  specification_expr = saved_specification_expr;
+@@ -13932,7 +13984,23 @@
+ 
+   if (as)
+     {
+-      gcc_assert (as->type != AS_IMPLIED_SHAPE);
++      /* If AS_IMPLIED_SHAPE makes it to here, it must be a bad
++	 specification expression.  */
++      if (as->type == AS_IMPLIED_SHAPE)
++	{
++	  int i;
++	  for (i=0; i<as->rank; i++)
++	    {
++	      if (as->lower[i] != NULL && as->upper[i] == NULL)
++		{
++		  gfc_error ("Bad specification for assumed size array at %L",
++			     &as->lower[i]->where);
++		  return;
++		}
++	    }
++	  gcc_unreachable();
++	}
++
+       if (((as->type == AS_ASSUMED_SIZE && !as->cp_was_assumed)
+ 	   || as->type == AS_ASSUMED_SHAPE)
+ 	  && !sym->attr.dummy && !sym->attr.select_type_temporary)
+@@ -14493,7 +14561,12 @@
+ 
+       if ((!a->save && !a->dummy && !a->pointer
+ 	   && !a->in_common && !a->use_assoc
+-	   && !a->result && !a->function)
++	   && a->referenced
++	   && !((a->function || a->result)
++		&& (!a->dimension
++		    || sym->ts.u.derived->attr.alloc_comp
++		    || sym->ts.u.derived->attr.pointer_comp))
++	   && !(a->function && sym != sym->result))
+ 	  || (a->dummy && a->intent == INTENT_OUT && !a->pointer))
+ 	apply_default_init (sym);
+       else if (a->function && sym->result && a->access != ACCESS_PRIVATE
+@@ -15321,9 +15394,22 @@
+ 	  && sym->ns->proc_name->attr.pure
+ 	  && sym->attr.in_common)
+ 	{
+-	  gfc_error ("Common block member %qs at %L cannot be an EQUIVALENCE "
+-		     "object in the pure procedure %qs",
+-		     sym->name, &e->where, sym->ns->proc_name->name);
++	  /* Need to check for symbols that may have entered the pure
++	     procedure via a USE statement.  */
++	  bool saw_sym = false;
++	  if (sym->ns->use_stmts)
++	    {
++	      gfc_use_rename *r;
++	      for (r = sym->ns->use_stmts->rename; r; r = r->next)
++		if (strcmp(r->use_name, sym->name) == 0) saw_sym = true; 
++	    }
++	  else
++	    saw_sym = true;
++
++	  if (saw_sym)
++	    gfc_error ("COMMON block member %qs at %L cannot be an "
++		       "EQUIVALENCE object in the pure procedure %qs",
++		       sym->name, &e->where, sym->ns->proc_name->name);
+ 	  break;
+ 	}
+ 
+Index: gcc/fortran/trans-decl.c
+===================================================================
+--- a/src/gcc/fortran/trans-decl.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/trans-decl.c	(.../branches/gcc-6-branch)
+@@ -4007,6 +4007,24 @@
+   return tmp;
+ }
+ 
++
++/* Get the result expression for a procedure.  */
++
++static tree
++get_proc_result (gfc_symbol* sym)
++{
++  if (sym->attr.subroutine || sym == sym->result)
++    {
++      if (current_fake_result_decl != NULL)
++	return TREE_VALUE (current_fake_result_decl);
++
++      return NULL_TREE;
++    }
++
++  return sym->result->backend_decl;
++}
++
++
+ /* Generate function entry and exit code, and add it to the function body.
+    This includes:
+     Allocation and initialization of array variables.
+@@ -4116,7 +4134,22 @@
+       else
+ 	gcc_assert (flag_f2c && proc_sym->ts.type == BT_COMPLEX);
+     }
++  else if (proc_sym == proc_sym->result && IS_CLASS_ARRAY (proc_sym))
++    {
++      /* Nullify explicit return class arrays on entry.  */
++      tree type;
++      tmp = get_proc_result (proc_sym);
++	if (tmp && GFC_CLASS_TYPE_P (TREE_TYPE (tmp)))
++	  {
++	    gfc_start_block (&init);
++	    tmp = gfc_class_data_get (tmp);
++	    type = TREE_TYPE (gfc_conv_descriptor_data_get (tmp));
++	    gfc_conv_descriptor_data_set (&init, tmp, build_int_cst (type, 0));
++	    gfc_add_init_cleanup (block, gfc_finish_block (&init), NULL_TREE);
++	  }
++    }
+ 
++
+   /* Initialize the INTENT(OUT) derived type dummy arguments.  This
+      should be done here so that the offsets and lbounds of arrays
+      are available.  */
+@@ -4364,7 +4397,10 @@
+ 		    && sym->ts.u.cl->passed_length)
+ 		tmp = gfc_null_and_pass_deferred_len (sym, &init, &loc);
+ 	      else
+-		gfc_restore_backend_locus (&loc);
++		{
++		  gfc_restore_backend_locus (&loc);
++		  tmp = NULL_TREE;
++		}
+ 
+ 	      /* Deallocate when leaving the scope. Nullifying is not
+ 		 needed.  */
+@@ -5827,23 +5863,6 @@
+ }
+ 
+ 
+-/* Get the result expression for a procedure.  */
+-
+-static tree
+-get_proc_result (gfc_symbol* sym)
+-{
+-  if (sym->attr.subroutine || sym == sym->result)
+-    {
+-      if (current_fake_result_decl != NULL)
+-	return TREE_VALUE (current_fake_result_decl);
+-
+-      return NULL_TREE;
+-    }
+-
+-  return sym->result->backend_decl;
+-}
+-
+-
+ /* Generate an appropriate return-statement for a procedure.  */
+ 
+ tree
+Index: gcc/fortran/match.c
+===================================================================
+--- a/src/gcc/fortran/match.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/match.c	(.../branches/gcc-6-branch)
+@@ -1983,11 +1983,17 @@
+ {
+   match m;
+   locus old_locus;
++  char c;
+ 
+   gfc_clear_ts (ts);
+   gfc_gobble_whitespace ();
+   old_locus = gfc_current_locus;
+ 
++  /* If c isn't in [a-z], then return immediately.  */
++  c = gfc_peek_ascii_char ();
++  if (!ISALPHA(c))
++    return MATCH_NO;
++
+   if (match_derived_type_spec (ts) == MATCH_YES)
+     {
+       /* Enforce F03:C401.  */
+@@ -2033,6 +2039,8 @@
+       ts->type = BT_CHARACTER;
+ 
+       m = gfc_match_char_spec (ts);
++      if (ts->u.cl && ts->u.cl->length)
++	gfc_resolve_expr (ts->u.cl->length);
+ 
+       if (m == MATCH_NO)
+ 	m = MATCH_YES;
+@@ -4267,8 +4275,8 @@
+ 	   && (tail->expr->ref->type == REF_COMPONENT
+ 	       || tail->expr->ref->type == REF_ARRAY));
+       if (sym && sym->ts.type == BT_CLASS)
+-	b2 = !(CLASS_DATA (sym)->attr.allocatable
+-	       || CLASS_DATA (sym)->attr.class_pointer);
++	b2 = !(CLASS_DATA (sym) && (CLASS_DATA (sym)->attr.allocatable
++	       || CLASS_DATA (sym)->attr.class_pointer));
+       else
+ 	b2 = sym && !(sym->attr.allocatable || sym->attr.pointer
+ 		      || sym->attr.proc_pointer);
+Index: gcc/fortran/trans-io.c
+===================================================================
+--- a/src/gcc/fortran/trans-io.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/trans-io.c	(.../branches/gcc-6-branch)
+@@ -611,12 +611,12 @@
+       /* Don't evaluate the UNIT number multiple times.  */
+       se.expr = gfc_evaluate_now (se.expr, &se.pre);
+ 
+-      /* UNIT numbers should be greater than zero.  */
++      /* UNIT numbers should be greater than the min.  */
+       i = gfc_validate_kind (BT_INTEGER, 4, false);
++      val = gfc_conv_mpz_to_tree (gfc_integer_kinds[i].pedantic_min_int, 4);
+       cond1 = build2_loc (input_location, LT_EXPR, boolean_type_node,
+ 			  se.expr,
+-			  fold_convert (TREE_TYPE (se.expr),
+-			  integer_zero_node));
++			  fold_convert (TREE_TYPE (se.expr), val));
+       /* UNIT numbers should be less than the max.  */
+       val = gfc_conv_mpz_to_tree (gfc_integer_kinds[i].huge, 4);
+       cond2 = build2_loc (input_location, GT_EXPR, boolean_type_node,
+@@ -2104,6 +2104,16 @@
+       ts->kind = gfc_index_integer_kind;
+     }
+ 
++  /* gfortran reaches here for "print *, c_loc(xxx)".  */
++  if (ts->type == BT_VOID
++      && code->expr1 && code->expr1->ts.type == BT_VOID
++      && code->expr1->symtree
++      && strcmp (code->expr1->symtree->name, "c_loc") == 0)
++    {
++      ts->type = BT_INTEGER;
++      ts->kind = gfc_index_integer_kind;
++    }
++
+   kind = ts->kind;
+   function = NULL;
+   arg2 = NULL;
+Index: gcc/fortran/arith.c
+===================================================================
+--- a/src/gcc/fortran/arith.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/arith.c	(.../branches/gcc-6-branch)
+@@ -555,10 +555,10 @@
+       val = ARITH_OK;
+     }
+ 
+-  if (val != ARITH_OK)
++  if (val == ARITH_OK || val == ARITH_OVERFLOW)
++    *rp = r;
++  else
+     gfc_free_expr (r);
+-  else
+-    *rp = r;
+ 
+   return val;
+ }
+@@ -1599,9 +1599,13 @@
+   if (rc != ARITH_OK)
+     {
+       gfc_error (gfc_arith_error (rc), &op1->where);
++      if (rc == ARITH_OVERFLOW)
++	goto done;
+       return NULL;
+     }
+ 
++done:
++
+   gfc_free_expr (op1);
+   gfc_free_expr (op2);
+   return result;
+Index: gcc/fortran/check.c
+===================================================================
+--- a/src/gcc/fortran/check.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/check.c	(.../branches/gcc-6-branch)
+@@ -404,15 +404,22 @@
+ /* Make sure two expressions have the same type.  */
+ 
+ static bool
+-same_type_check (gfc_expr *e, int n, gfc_expr *f, int m)
++same_type_check (gfc_expr *e, int n, gfc_expr *f, int m, bool assoc = false)
+ {
+   gfc_typespec *ets = &e->ts;
+   gfc_typespec *fts = &f->ts;
+ 
+-  if (e->ts.type == BT_PROCEDURE && e->symtree->n.sym)
+-    ets = &e->symtree->n.sym->ts;
+-  if (f->ts.type == BT_PROCEDURE && f->symtree->n.sym)
+-    fts = &f->symtree->n.sym->ts;
++  if (assoc)
++    {
++      /* Procedure pointer component expressions have the type of the interface
++	 procedure. If they are being tested for association with a procedure
++	 pointer (ie. not a component), the type of the procedure must be
++	 determined.  */
++      if (e->ts.type == BT_PROCEDURE && e->symtree->n.sym)
++	ets = &e->symtree->n.sym->ts;
++      if (f->ts.type == BT_PROCEDURE && f->symtree->n.sym)
++	fts = &f->symtree->n.sym->ts;
++    }
+ 
+   if (gfc_compare_types (ets, fts))
+     return true;
+@@ -968,7 +975,7 @@
+     }
+ 
+   t = true;
+-  if (!same_type_check (pointer, 0, target, 1))
++  if (!same_type_check (pointer, 0, target, 1, true))
+     t = false;
+   if (!rank_check (target, 0, pointer->rank))
+     t = false;
+@@ -5021,7 +5028,7 @@
+ 	return false;
+ 
+       if (!gfc_notify_std (GFC_STD_F2008_TS, "FAILED= argument to "
+-			   "NUM_IMAGES at %L", &distance->where))
++			   "NUM_IMAGES at %L", &failed->where))
+ 	return false;
+     }
+ 
+Index: gcc/fortran/primary.c
+===================================================================
+--- a/src/gcc/fortran/primary.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/primary.c	(.../branches/gcc-6-branch)
+@@ -1250,8 +1250,22 @@
+ 
+   if (sym->attr.flavor != FL_PARAMETER)
+     {
+-      gfc_error ("Expected PARAMETER symbol in complex constant at %C");
+-      return MATCH_ERROR;
++      /* Give the matcher for implied do-loops a chance to run.  This yields
++	 a much saner error message for "write(*,*) (i, i=1, 6" where the 
++	 right parenthesis is missing.  */
++      char c;
++      gfc_gobble_whitespace ();
++      c = gfc_peek_ascii_char ();
++      if (c == '=' || c == ',')
++	{
++	  m = MATCH_NO;
++	}
++      else
++	{
++	  gfc_error ("Expected PARAMETER symbol in complex constant at %C");
++	  m = MATCH_ERROR;
++	}
++      return m;
+     }
+ 
+   if (!sym->value)
+Index: gcc/fortran/trans-intrinsic.c
+===================================================================
+--- a/src/gcc/fortran/trans-intrinsic.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/trans-intrinsic.c	(.../branches/gcc-6-branch)
+@@ -4693,6 +4693,22 @@
+ }
+ 
+ static void
++gfc_conv_intrinsic_shape (gfc_se *se, gfc_expr *expr)
++{
++  gfc_actual_arglist *s, *k;
++  gfc_expr *e;
++
++  /* Remove the KIND argument, if present. */
++  s = expr->value.function.actual;
++  k = s->next;
++  e = k->expr;
++  gfc_free_expr (e);
++  k->expr = NULL;
++
++  gfc_conv_intrinsic_funcall (se, expr);
++}
++
++static void
+ gfc_conv_intrinsic_shift (gfc_se * se, gfc_expr * expr, bool right_shift,
+ 			  bool arithmetic)
+ {
+@@ -5816,7 +5832,7 @@
+     gfc_add_class_array_ref (actual->expr);
+ 
+   argse.data_not_needed = 1;
+-  if (gfc_is_alloc_class_array_function (actual->expr))
++  if (gfc_is_class_array_function (actual->expr))
+     {
+       /* For functions that return a class array conv_expr_descriptor is not
+ 	 able to get the descriptor right.  Therefore this special case.  */
+@@ -7753,6 +7769,10 @@
+ 	      conv_generic_with_optional_char_arg (se, expr, 1, 3);
+ 	      break;
+ 
++	    case GFC_ISYM_SHAPE:
++	      gfc_conv_intrinsic_shape (se, expr);
++	      break;
++
+ 	    default:
+ 	      gfc_conv_intrinsic_funcall (se, expr);
+ 	      break;
+Index: gcc/fortran/simplify.c
+===================================================================
+--- a/src/gcc/fortran/simplify.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/fortran/simplify.c	(.../branches/gcc-6-branch)
+@@ -1,5 +1,5 @@
+ /* Simplify intrinsic functions at compile-time.
+-   Copyright (C) 2000-2016 Free Software Foundation, Inc.
++   Copyright (C) 2000-2016, 2018 Free Software Foundation, Inc.
+    Contributed by Andy Vaught & Katherine Holcomb
+ 
+ This file is part of GCC.
+@@ -1838,11 +1838,17 @@
+       sz = mpz_get_si (size);
+       mpz_clear (size);
+ 
++      /* Special case: Zero-sized array.  */
++      if (sz == 0)
++	return a;
++
+       /* Adjust shft to deal with right or left shifts. */
+-      shft = shft < 0 ? 1 - shft : shft;
++      shft = shft % sz;
++      if (shft < 0)
++	shft += sz;
+ 
+       /* Special case: Shift to the original order!  */
+-      if (sz == 0 || shft % sz == 0)
++      if (shft % sz == 0)
+ 	return a;
+ 
+       result = gfc_copy_expr (a);
+@@ -4011,10 +4017,23 @@
+       || !is_constant_array_expr (matrix_b))
+     return NULL;
+ 
+-  gcc_assert (gfc_compare_types (&matrix_a->ts, &matrix_b->ts));
+-  result = gfc_get_array_expr (matrix_a->ts.type,
+-			       matrix_a->ts.kind,
+-			       &matrix_a->where);
++  /* MATMUL should do mixed-mode arithmetic.  Set the result type.  */
++  if (matrix_a->ts.type != matrix_b->ts.type)
++    {
++      gfc_expr e;
++      e.expr_type = EXPR_OP;
++      gfc_clear_ts (&e.ts);
++      e.value.op.op = INTRINSIC_NONE;
++      e.value.op.op1 = matrix_a;
++      e.value.op.op2 = matrix_b;
++      gfc_type_convert_binary (&e, 1);
++      result = gfc_get_array_expr (e.ts.type, e.ts.kind, &matrix_a->where);
++    }
++  else
++    {
++      result = gfc_get_array_expr (matrix_a->ts.type, matrix_a->ts.kind,
++				   &matrix_a->where);
++    }
+ 
+   if (matrix_a->rank == 1 && matrix_b->rank == 2)
+     {
+@@ -6355,8 +6374,7 @@
+     return NULL;
+ 
+   /* Calculate the size of the source.  */
+-  if (source->expr_type == EXPR_ARRAY
+-      && !gfc_array_size (source, &tmp))
++  if (source->expr_type == EXPR_ARRAY && !gfc_array_size (source, &tmp))
+     gfc_internal_error ("Failure getting length of a constant array.");
+ 
+   /* Create an empty new expression with the appropriate characteristics.  */
+@@ -6364,7 +6382,7 @@
+ 				  &source->where);
+   result->ts = mold->ts;
+ 
+-  mold_element = mold->expr_type == EXPR_ARRAY
++  mold_element = (mold->expr_type == EXPR_ARRAY && mold->value.constructor)
+ 		 ? gfc_constructor_first (mold->value.constructor)->expr
+ 		 : mold;
+ 
+Index: gcc/configure.ac
+===================================================================
+--- a/src/gcc/configure.ac	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/configure.ac	(.../branches/gcc-6-branch)
+@@ -717,10 +717,10 @@
+ 		 default is noopt])],
+ [case "${enableval}" in
+   yes|noopt)
+-    coverage_flags="-fprofile-arcs -ftest-coverage -frandom-seed=\$@ -O0"
++    coverage_flags="-fprofile-arcs -ftest-coverage -frandom-seed=\$@ -O0 -fkeep-static-functions"
+     ;;
+   opt)
+-    coverage_flags="-fprofile-arcs -ftest-coverage -frandom-seed=\$@ -O2"
++    coverage_flags="-fprofile-arcs -ftest-coverage -frandom-seed=\$@ -O2 -fkeep-static-functions"
+     ;;
+   no)
+     # a.k.a. --disable-coverage
+@@ -2933,6 +2933,14 @@
+     [elf,2,12,0], [--fatal-warnings],
+     [.section .rodata.str, "aMS", %progbits, 1])
+ fi
++case "$target" in
++  i?86-*-solaris2.10* | x86_64-*-solaris2.10*)
++    # SHF_MERGE support in Solaris 10/x86 ld is broken.
++    if test x"$gnu_ld" = xno; then
++      gcc_cv_as_shf_merge=no
++    fi
++    ;;
++esac
+ AC_DEFINE_UNQUOTED(HAVE_GAS_SHF_MERGE,
+   [`if test $gcc_cv_as_shf_merge = yes; then echo 1; else echo 0; fi`],
+ [Define 0/1 if your assembler supports marking sections with SHF_MERGE flag.])
+@@ -4017,6 +4025,11 @@
+ 	;;
+     esac
+ 
++    gcc_GAS_CHECK_FEATURE([-xbrace_comment], gcc_cv_as_ix86_xbrace_comment,,
++      [-xbrace_comment=no], [.text],,
++      [AC_DEFINE(HAVE_AS_XBRACE_COMMENT_OPTION, 1,
++		[Define if your assembler supports -xbrace_comment option.])])
++
+     # Test if the assembler supports the section flag 'e' for specifying
+     # an excluded section.
+     gcc_GAS_CHECK_FEATURE([.section with e], gcc_cv_as_section_has_e,
+@@ -4927,7 +4940,7 @@
+   else
+     case "$target" in
+       *-*-solaris2.1[[1-9]]*)
+-	# Solaris 11.x and Solaris 12 added PIE support.
++	# Solaris 11.3 added PIE support.
+ 	if $gcc_cv_ld -z help 2>&1 | grep -- type.*pie > /dev/null; then
+ 	  gcc_cv_ld_pie=yes
+ 	fi
+Index: gcc/function.c
+===================================================================
+--- a/src/gcc/function.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/function.c	(.../branches/gcc-6-branch)
+@@ -6068,13 +6068,19 @@
+ 
+   try_shrink_wrapping (&entry_edge, &bb_flags, prologue_seq);
+ 
++  rtx_insn *split_prologue_insn = split_prologue_seq;
+   if (split_prologue_seq != NULL_RTX)
+     {
++      while (split_prologue_insn && !NONDEBUG_INSN_P (split_prologue_insn))
++	split_prologue_insn = NEXT_INSN (split_prologue_insn);
+       insert_insn_on_edge (split_prologue_seq, orig_entry_edge);
+       inserted = true;
+     }
++  rtx_insn *prologue_insn = prologue_seq;
+   if (prologue_seq != NULL_RTX)
+     {
++      while (prologue_insn && !NONDEBUG_INSN_P (prologue_insn))
++	prologue_insn = NEXT_INSN (prologue_insn);
+       insert_insn_on_edge (prologue_seq, entry_edge);
+       inserted = true;
+     }
+@@ -6215,8 +6221,19 @@
+       commit_edge_insertions ();
+ 
+       /* Look for basic blocks within the prologue insns.  */
++      if (split_prologue_insn
++	  && BLOCK_FOR_INSN (split_prologue_insn) == NULL)
++	split_prologue_insn = NULL;
++      if (prologue_insn
++	  && BLOCK_FOR_INSN (prologue_insn) == NULL)
++	prologue_insn = NULL;
+       blocks = sbitmap_alloc (last_basic_block_for_fn (cfun));
+       bitmap_clear (blocks);
++      if (split_prologue_insn)
++	bitmap_set_bit (blocks,
++			BLOCK_FOR_INSN (split_prologue_insn)->index);
++      if (prologue_insn)
++	bitmap_set_bit (blocks, BLOCK_FOR_INSN (prologue_insn)->index);
+       bitmap_set_bit (blocks, entry_edge->dest->index);
+       bitmap_set_bit (blocks, orig_entry_edge->dest->index);
+       find_many_sub_basic_blocks (blocks);
+Index: gcc/loop-unroll.c
+===================================================================
+--- a/src/gcc/loop-unroll.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/loop-unroll.c	(.../branches/gcc-6-branch)
+@@ -477,7 +477,7 @@
+ 
+   exit_mod = niter % (max_unroll + 1);
+ 
+-  wont_exit = sbitmap_alloc (max_unroll + 1);
++  wont_exit = sbitmap_alloc (max_unroll + 2);
+   bitmap_ones (wont_exit);
+ 
+   auto_vec<edge> remove_edges;
+Index: gcc/expmed.c
+===================================================================
+--- a/src/gcc/expmed.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/expmed.c	(.../branches/gcc-6-branch)
+@@ -5917,6 +5917,18 @@
+   if (tem != 0)
+     return tem;
+ 
++  /* If one operand is constant, make it the second one.  Only do this
++     if the other operand is not constant as well.  */
++
++  if (swap_commutative_operands_p (op0, op1))
++    {
++      std::swap (op0, op1);
++      code = swap_condition (code);
++    }
++
++  if (mode == VOIDmode)
++    mode = GET_MODE (op0);
++
+   if (!target)
+     target = gen_reg_rtx (word_mode);
+ 
+Index: gcc/simplify-rtx.c
+===================================================================
+--- a/src/gcc/simplify-rtx.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/simplify-rtx.c	(.../branches/gcc-6-branch)
+@@ -5235,34 +5235,14 @@
+ 	{
+ 	case LT:
+ 	  /* Optimize abs(x) < 0.0.  */
+-	  if (!HONOR_SNANS (mode)
+-	      && (!INTEGRAL_MODE_P (mode)
+-		  || (!flag_wrapv && !flag_trapv && flag_strict_overflow)))
+-	    {
+-	      if (INTEGRAL_MODE_P (mode)
+-		  && (issue_strict_overflow_warning
+-		      (WARN_STRICT_OVERFLOW_CONDITIONAL)))
+-		warning (OPT_Wstrict_overflow,
+-			 ("assuming signed overflow does not occur when "
+-			  "assuming abs (x) < 0 is false"));
+-	       return const0_rtx;
+-	    }
++	  if (!INTEGRAL_MODE_P (mode) && !HONOR_SNANS (mode))
++	    return const0_rtx;
+ 	  break;
+ 
+ 	case GE:
+ 	  /* Optimize abs(x) >= 0.0.  */
+-	  if (!HONOR_NANS (mode)
+-	      && (!INTEGRAL_MODE_P (mode)
+-		  || (!flag_wrapv && !flag_trapv && flag_strict_overflow)))
+-	    {
+-	      if (INTEGRAL_MODE_P (mode)
+-	          && (issue_strict_overflow_warning
+-	    	  (WARN_STRICT_OVERFLOW_CONDITIONAL)))
+-	        warning (OPT_Wstrict_overflow,
+-			 ("assuming signed overflow does not occur when "
+-			  "assuming abs (x) >= 0 is true"));
+-	      return const_true_rtx;
+-	    }
++	  if (!INTEGRAL_MODE_P (mode) && !HONOR_NANS (mode))
++	    return const_true_rtx;
+ 	  break;
+ 
+ 	case UNGE:
+Index: gcc/tree-predcom.c
+===================================================================
+--- a/src/gcc/tree-predcom.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/tree-predcom.c	(.../branches/gcc-6-branch)
+@@ -943,6 +943,17 @@
+   return (*da)->pos - (*db)->pos;
+ }
+ 
++/* Compares two drefs A and B by their position.  Callback for qsort.  */
++
++static int
++order_drefs_by_pos (const void *a, const void *b)
++{
++  const dref *const da = (const dref *) a;
++  const dref *const db = (const dref *) b;
++
++  return (*da)->pos - (*db)->pos;
++}
++
+ /* Returns root of the CHAIN.  */
+ 
+ static inline dref
+@@ -2250,7 +2261,6 @@
+   bool swap = false;
+   chain_p new_chain;
+   unsigned i;
+-  gimple *root_stmt;
+   tree rslt_type = NULL_TREE;
+ 
+   if (ch1 == ch2)
+@@ -2292,31 +2302,55 @@
+       new_chain->refs.safe_push (nw);
+     }
+ 
+-  new_chain->has_max_use_after = false;
+-  root_stmt = get_chain_root (new_chain)->stmt;
+-  for (i = 1; new_chain->refs.iterate (i, &nw); i++)
+-    {
+-      if (nw->distance == new_chain->length
+-	  && !stmt_dominates_stmt_p (nw->stmt, root_stmt))
+-	{
+-	  new_chain->has_max_use_after = true;
+-	  break;
+-	}
+-    }
+-
+   ch1->combined = true;
+   ch2->combined = true;
+   return new_chain;
+ }
+ 
+-/* Try to combine the CHAINS.  */
++/* Recursively update position information of all offspring chains to ROOT
++   chain's position information.  */
+ 
+ static void
+-try_combine_chains (vec<chain_p> *chains)
++update_pos_for_combined_chains (chain_p root)
+ {
++  chain_p ch1 = root->ch1, ch2 = root->ch2;
++  dref ref, ref1, ref2;
++  for (unsigned j = 0; (root->refs.iterate (j, &ref)
++			&& ch1->refs.iterate (j, &ref1)
++			&& ch2->refs.iterate (j, &ref2)); ++j)
++    ref1->pos = ref2->pos = ref->pos;
++
++  if (ch1->type == CT_COMBINATION)
++    update_pos_for_combined_chains (ch1);
++  if (ch2->type == CT_COMBINATION)
++    update_pos_for_combined_chains (ch2);
++}
++
++/* Returns true if statement S1 dominates statement S2.  */
++
++static bool
++pcom_stmt_dominates_stmt_p (gimple *s1, gimple *s2)
++{
++  basic_block bb1 = gimple_bb (s1), bb2 = gimple_bb (s2);
++
++  if (!bb1 || s1 == s2)
++    return true;
++
++  if (bb1 == bb2)
++    return gimple_uid (s1) < gimple_uid (s2);
++
++  return dominated_by_p (CDI_DOMINATORS, bb2, bb1);
++}
++
++/* Try to combine the CHAINS in LOOP.  */
++
++static void
++try_combine_chains (struct loop *loop, vec<chain_p> *chains)
++{
+   unsigned i, j;
+   chain_p ch1, ch2, cch;
+   auto_vec<chain_p> worklist;
++  bool combined_p = false;
+ 
+   FOR_EACH_VEC_ELT (*chains, i, ch1)
+     if (chain_can_be_combined_p (ch1))
+@@ -2338,10 +2372,82 @@
+ 	    {
+ 	      worklist.safe_push (cch);
+ 	      chains->safe_push (cch);
++	      combined_p = true;
+ 	      break;
+ 	    }
+ 	}
+     }
++  if (!combined_p)
++    return;
++
++  /* Setup UID for all statements in dominance order.  */
++  basic_block *bbs = get_loop_body (loop);
++  renumber_gimple_stmt_uids_in_blocks (bbs, loop->num_nodes);
++  free (bbs);
++
++  /* Re-association in combined chains may generate statements different to
++     order of references of the original chain.  We need to keep references
++     of combined chain in dominance order so that all uses will be inserted
++     after definitions.  Note:
++       A) This is necessary for all combined chains.
++       B) This is only necessary for ZERO distance references because other
++	  references inherit value from loop carried PHIs.
++
++     We first update position information for all combined chains.  */
++  dref ref;
++  for (i = 0; chains->iterate (i, &ch1); ++i)
++    {
++      if (ch1->type != CT_COMBINATION || ch1->combined)
++	continue;
++
++      for (j = 0; ch1->refs.iterate (j, &ref); ++j)
++	ref->pos = gimple_uid (ref->stmt);
++
++      update_pos_for_combined_chains (ch1);
++    }
++  /* Then sort references according to newly updated position information.  */
++  for (i = 0; chains->iterate (i, &ch1); ++i)
++    {
++      if (ch1->type != CT_COMBINATION && !ch1->combined)
++	continue;
++
++      /* Find the first reference with non-ZERO distance.  */
++      if (ch1->length == 0)
++	j = ch1->refs.length();
++      else
++	{
++	  for (j = 0; ch1->refs.iterate (j, &ref); ++j)
++	    if (ref->distance != 0)
++	      break;
++	}
++
++      /* Sort all ZERO distance references by position.  */
++      qsort (&ch1->refs[0], j, sizeof (ch1->refs[0]), order_drefs_by_pos);
++
++      if (ch1->combined)
++	continue;
++
++      /* For ZERO length chain, has_max_use_after must be true since root
++	 combined stmt must dominates others.  */
++      if (ch1->length == 0)
++	{
++	  ch1->has_max_use_after = true;
++	  continue;
++	}
++      /* Check if there is use at max distance after root for combined chains
++	 and set flag accordingly.  */
++      ch1->has_max_use_after = false;
++      gimple *root_stmt = get_chain_root (ch1)->stmt;
++      for (j = 1; ch1->refs.iterate (j, &ref); ++j)
++	{
++	  if (ref->distance == ch1->length
++	      && !pcom_stmt_dominates_stmt_p (ref->stmt, root_stmt))
++	    {
++	      ch1->has_max_use_after = true;
++	      break;
++	    }
++	}
++    }
+ }
+ 
+ /* Prepare initializers for CHAIN in LOOP.  Returns false if this is
+@@ -2490,7 +2596,7 @@
+   prepare_initializers (loop, chains);
+ 
+   /* Try to combine the chains that are always worked with together.  */
+-  try_combine_chains (&chains);
++  try_combine_chains (loop, &chains);
+ 
+   if (dump_file && (dump_flags & TDF_DETAILS))
+     {
+Index: gcc/ubsan.c
+===================================================================
+--- a/src/gcc/ubsan.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ubsan.c	(.../branches/gcc-6-branch)
+@@ -380,6 +380,7 @@
+     /* We weren't able to determine the type name.  */
+     tname = "<unknown>";
+ 
++  tree eltype = type;
+   if (pstyle == UBSAN_PRINT_POINTER)
+     {
+       pp_printf (&pretty_name, "'%s%s%s%s%s%s%s",
+@@ -430,12 +431,12 @@
+       pp_quote (&pretty_name);
+ 
+       /* Save the tree with stripped types.  */
+-      type = t;
++      eltype = t;
+     }
+   else
+     pp_printf (&pretty_name, "'%s'", tname);
+ 
+-  switch (TREE_CODE (type))
++  switch (TREE_CODE (eltype))
+     {
+     case BOOLEAN_TYPE:
+     case ENUMERAL_TYPE:
+@@ -445,9 +446,9 @@
+     case REAL_TYPE:
+       /* FIXME: libubsan right now only supports float, double and
+ 	 long double type formats.  */
+-      if (TYPE_MODE (type) == TYPE_MODE (float_type_node)
+-	  || TYPE_MODE (type) == TYPE_MODE (double_type_node)
+-	  || TYPE_MODE (type) == TYPE_MODE (long_double_type_node))
++      if (TYPE_MODE (eltype) == TYPE_MODE (float_type_node)
++	  || TYPE_MODE (eltype) == TYPE_MODE (double_type_node)
++	  || TYPE_MODE (eltype) == TYPE_MODE (long_double_type_node))
+ 	tkind = 0x0001;
+       else
+ 	tkind = 0xffff;
+@@ -456,7 +457,7 @@
+       tkind = 0xffff;
+       break;
+     }
+-  tinfo = get_ubsan_type_info_for_type (type);
++  tinfo = get_ubsan_type_info_for_type (eltype);
+ 
+   /* Create a new VAR_DECL of type descriptor.  */
+   const char *tmp = pp_formatted_text (&pretty_name);
+Index: gcc/lto/lto.c
+===================================================================
+--- a/src/gcc/lto/lto.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/lto/lto.c	(.../branches/gcc-6-branch)
+@@ -52,6 +52,7 @@
+ #include "lto-symtab.h"
+ #include "stringpool.h"
+ #include "fold-const.h"
++#include "builtins.h"
+ 
+ 
+ /* Number of parallel tasks to run, -1 if we want to use GNU Make jobserver.  */
+@@ -828,12 +829,19 @@
+ register_resolution (struct lto_file_decl_data *file_data, tree decl,
+ 		     enum ld_plugin_symbol_resolution resolution)
+ {
++  bool existed;
+   if (resolution == LDPR_UNKNOWN)
+     return;
+   if (!file_data->resolution_map)
+     file_data->resolution_map
+       = new hash_map<tree, ld_plugin_symbol_resolution>;
+-  file_data->resolution_map->put (decl, resolution);
++  ld_plugin_symbol_resolution_t &res
++     = file_data->resolution_map->get_or_insert (decl, &existed);
++  if (!existed
++      || resolution == LDPR_PREVAILING_DEF_IRONLY
++      || resolution == LDPR_PREVAILING_DEF
++      || resolution == LDPR_PREVAILING_DEF_IRONLY_EXP)
++    res = resolution;
+ }
+ 
+ /* Register DECL with the global symbol table and change its
+@@ -876,7 +884,19 @@
+ 			 decl, get_resolution (data_in, ix));
+ }
+ 
++/* Check if T is a decl and needs register its resolution info.  */
+ 
++static void
++lto_maybe_register_decl (struct data_in *data_in, tree t, unsigned ix)
++{
++  if (TREE_CODE (t) == VAR_DECL)
++    lto_register_var_decl_in_symtab (data_in, t, ix);
++  else if (TREE_CODE (t) == FUNCTION_DECL
++	   && !DECL_BUILT_IN (t))
++    lto_register_function_decl_in_symtab (data_in, t, ix);
++}
++
++
+ /* For the type T re-materialize it in the type variant list and
+    the pointer/reference-to chains.  */
+ 
+@@ -1611,7 +1631,10 @@
+ 	  /* Fixup the streamer cache with the prevailing nodes according
+ 	     to the tree node mapping computed by compare_tree_sccs.  */
+ 	  if (len == 1)
+-	    streamer_tree_cache_replace_tree (cache, pscc->entries[0], from);
++	    {
++	      lto_maybe_register_decl (data_in, pscc->entries[0], from);
++	      streamer_tree_cache_replace_tree (cache, pscc->entries[0], from);
++	    }
+ 	  else
+ 	    {
+ 	      tree *map2 = XALLOCAVEC (tree, 2 * len);
+@@ -1623,8 +1646,12 @@
+ 	      qsort (map2, len, 2 * sizeof (tree), cmp_tree);
+ 	      qsort (map, len, 2 * sizeof (tree), cmp_tree);
+ 	      for (unsigned i = 0; i < len; ++i)
+-		streamer_tree_cache_replace_tree (cache, map[2*i],
+-						  (uintptr_t)map2[2*i]);
++		{
++		  lto_maybe_register_decl (data_in, map[2*i],
++					   (uintptr_t)map2[2*i]);
++		  streamer_tree_cache_replace_tree (cache, map[2*i],
++						    (uintptr_t)map2[2*i]);
++		}
+ 	    }
+ 
+ 	  /* Free the tree nodes from the read SCC.  */
+@@ -1764,13 +1791,7 @@
+ 		}
+ 	      if (!flag_ltrans)
+ 		{
+-		  /* Register variables and functions with the
+-		     symbol table.  */
+-		  if (TREE_CODE (t) == VAR_DECL)
+-		    lto_register_var_decl_in_symtab (data_in, t, from + i);
+-		  else if (TREE_CODE (t) == FUNCTION_DECL
+-			   && !DECL_BUILT_IN (t))
+-		    lto_register_function_decl_in_symtab (data_in, t, from + i);
++		  lto_maybe_register_decl (data_in, t, from + i);
+ 		  /* Scan the tree for references to global functions or
+ 		     variables and record those for later fixup.  */
+ 		  if (mentions_vars_p (t))
+@@ -2861,13 +2882,25 @@
+ 
+   /* Store resolutions into the symbol table.  */
+ 
+-  ld_plugin_symbol_resolution_t *res;
+   FOR_EACH_SYMBOL (snode)
+-    if (snode->real_symbol_p ()
+-	&& snode->lto_file_data
+-	&& snode->lto_file_data->resolution_map
+-	&& (res = snode->lto_file_data->resolution_map->get (snode->decl)))
+-      snode->resolution = *res;
++    if (snode->externally_visible && snode->real_symbol_p ()
++	&& snode->lto_file_data && snode->lto_file_data->resolution_map
++	&& !is_builtin_fn (snode->decl)
++	&& !(VAR_P (snode->decl) && DECL_HARD_REGISTER (snode->decl)))
++      {
++	ld_plugin_symbol_resolution_t *res;
++
++	res = snode->lto_file_data->resolution_map->get (snode->decl);
++	if (!res || *res == LDPR_UNKNOWN)
++	  {
++	    if (snode->output_to_lto_symbol_table_p ())
++	      fatal_error (input_location, "missing resolution data for %s",
++		           IDENTIFIER_POINTER
++			     (DECL_ASSEMBLER_NAME (snode->decl)));
++	  }
++	else
++          snode->resolution = *res;
++      }
+   for (i = 0; all_file_decl_data[i]; i++)
+     if (all_file_decl_data[i]->resolution_map)
+       {
+Index: gcc/lto/lto-partition.c
+===================================================================
+--- a/src/gcc/lto/lto-partition.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/lto/lto-partition.c	(.../branches/gcc-6-branch)
+@@ -751,7 +751,8 @@
+ 	  if (npartitions < n_lto_partitions)
+ 	    partition_size = total_size / (n_lto_partitions - npartitions);
+ 	  else
+-	    partition_size = INT_MAX;
++	    /* Watch for overflow.  */
++	    partition_size = INT_MAX / 16;
+ 
+ 	  if (partition_size < PARAM_VALUE (MIN_PARTITION_SIZE))
+ 	    partition_size = PARAM_VALUE (MIN_PARTITION_SIZE);
+Index: gcc/lto/ChangeLog
+===================================================================
+--- a/src/gcc/lto/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/lto/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,76 @@
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-01-23  Martin Liska  <mliska@suse.cz>
++
++	PR lto/81440
++	* lto-symtab.c (lto_symtab_merge): Handle and do not warn about
++	trailing arrays at the end of a struct.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-02-08  Jan Hubicka  <hubicka@ucw.cz>
++
++	* lto-partition.c (lto_balanced_map): Watch overflow.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-02-08  Jan Hubicka  <hubicka@ucw.cz>
++
++	PR ipa/81360
++	* lto.c (unify_scc): Register prevailing trees, not trees to be freed.
++	(read_cgraph_and_symbols): Use
++	symtab_node::output_to_lto_symbol_table_p.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-01-30  Jan Hubicka  <hubicka@ucw.cz>
++
++	* lto.c (register_resolution): Remove forgotten sanity check.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-01-30  Jan Hubicka  <hubicka@ucw.cz>
++
++	PR lto/81004
++	* lto.c: Include builtins.h
++	(register_resolution): Merge resolutions in case trees was
++	merged across units.
++	(lto_maybe_register_decl): Break out from ...
++	(lto_read_decls): ... here.
++	(unify_scc): Also register decls here.
++	(read_cgraph_and_symbols): Sanity check that all resolutions was
++	read.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-02-02  Eric Botcazou  <ebotcazou@adacore.com>
++
++	PR lto/83954
++	* lto-symtab.c (warn_type_compatibility_p): Do not recurse into the
++	component type of array types with non-aliased component.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2018-01-30  Jan Hubicka  <hubicka@ucw.cz>
++
++	PR lto/83954
++	* lto-symtab.c (warn_type_compatibility_p): Silence false positive
++	for type match warning on arrays of pointers.
++
++2018-03-07  Martin Liska  <mliska@suse.cz>
++
++	Backport from mainline
++	2017-10-13  Jan Hubicka  <hubicka@ucw.cz>
++
++	* lto-lang.c (lto_post_options): Clean shlib flag when not doing PIC.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: gcc/lto/lto-lang.c
+===================================================================
+--- a/src/gcc/lto/lto-lang.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/lto/lto-lang.c	(.../branches/gcc-6-branch)
+@@ -837,11 +837,13 @@
+          flag_pie is 2.  */
+       flag_pie = MAX (flag_pie, flag_pic);
+       flag_pic = flag_pie;
++      flag_shlib = 0;
+       break;
+ 
+     case LTO_LINKER_OUTPUT_EXEC: /* Normal executable */
+       flag_pic = 0;
+       flag_pie = 0;
++      flag_shlib = 0;
+       break;
+ 
+     case LTO_LINKER_OUTPUT_UNKNOWN:
+Index: gcc/lto/lto-symtab.c
+===================================================================
+--- a/src/gcc/lto/lto-symtab.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/lto/lto-symtab.c	(.../branches/gcc-6-branch)
+@@ -280,11 +280,25 @@
+       alias_set_type set1 = get_alias_set (type);
+       alias_set_type set2 = get_alias_set (prevailing_type);
+ 
+-      if (set1 && set2 && set1 != set2 
+-          && (!POINTER_TYPE_P (type) || !POINTER_TYPE_P (prevailing_type)
++      if (set1 && set2 && set1 != set2)
++	{
++          tree t1 = type, t2 = prevailing_type;
++
++	  /* Alias sets of arrays with aliased components are the same as alias
++	     sets of the inner types.  */
++	  while (TREE_CODE (t1) == ARRAY_TYPE
++		 && !TYPE_NONALIASED_COMPONENT (t1)
++		 && TREE_CODE (t2) == ARRAY_TYPE
++		 && !TYPE_NONALIASED_COMPONENT (t2))
++	    {
++	      t1 = TREE_TYPE (t1);
++	      t2 = TREE_TYPE (t2);
++	    }
++          if ((!POINTER_TYPE_P (t1) || !POINTER_TYPE_P (t2))
+ 	      || (set1 != TYPE_ALIAS_SET (ptr_type_node)
+-		  && set2 != TYPE_ALIAS_SET (ptr_type_node))))
+-        lev |= 5;
++		  && set2 != TYPE_ALIAS_SET (ptr_type_node)))
++             lev |= 5;
++	}
+     }
+ 
+   return lev;
+@@ -348,7 +362,22 @@
+     return false;
+ 
+   if (DECL_SIZE (decl) && DECL_SIZE (prevailing_decl)
+-      && !tree_int_cst_equal (DECL_SIZE (decl), DECL_SIZE (prevailing_decl))
++      && !tree_int_cst_equal (DECL_SIZE (decl), DECL_SIZE (prevailing_decl)))
++      {
++	if (!DECL_COMMON (decl) && !DECL_EXTERNAL (decl))
++	  return false;
++
++	tree type = TREE_TYPE (decl);
++
++	/* For record type, check for array at the end of the structure.  */
++	if (TREE_CODE (type) == RECORD_TYPE)
++	  {
++	    tree field = TYPE_FIELDS (type);
++	    while (DECL_CHAIN (field) != NULL_TREE)
++	      field = DECL_CHAIN (field);
++
++	    return TREE_CODE (TREE_TYPE (field)) == ARRAY_TYPE;
++	  }
+       /* As a special case do not warn about merging
+ 	 int a[];
+ 	 and
+@@ -355,11 +384,9 @@
+ 	 int a[]={1,2,3};
+ 	 here the first declaration is COMMON
+ 	 and sizeof(a) == sizeof (int).  */
+-      && ((!DECL_COMMON (decl) && !DECL_EXTERNAL (decl))
+-	  || TREE_CODE (TREE_TYPE (decl)) != ARRAY_TYPE
+-	  || TYPE_SIZE (TREE_TYPE (decl))
+-	     != TYPE_SIZE (TREE_TYPE (TREE_TYPE (decl)))))
+-    return false;
++	else if (TREE_CODE (type) == ARRAY_TYPE)
++	  return (TYPE_SIZE (decl) == TYPE_SIZE (TREE_TYPE (type)));
++      }
+ 
+   return true;
+ }
+Index: gcc/ggc-page.c
+===================================================================
+--- a/src/gcc/ggc-page.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ggc-page.c	(.../branches/gcc-6-branch)
+@@ -91,11 +91,6 @@
+      4: Object marks as well.  */
+ #define GGC_DEBUG_LEVEL (0)
+ 
+-#ifndef HOST_BITS_PER_PTR
+-#define HOST_BITS_PER_PTR  HOST_BITS_PER_LONG
+-#endif
+-
+-
+ /* A two-level tree is used to look up the page-entry for a given
+    pointer.  Two chunks of the pointer's bits are extracted to index
+    the first and second levels of the tree, as follows:
+Index: gcc/ira.c
+===================================================================
+--- a/src/gcc/ira.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ira.c	(.../branches/gcc-6-branch)
+@@ -4405,6 +4405,12 @@
+ 	 for a reason.  */
+       return false;
+ 
++    case ASM_OPERANDS:
++      /* The same is true for volatile asm: it has unknown side effects, it
++         cannot be moved at will.  */
++      if (MEM_VOLATILE_P (x))
++	return false;
++
+     default:
+       break;
+     }
+Index: gcc/tree-vect-stmts.c
+===================================================================
+--- a/src/gcc/tree-vect-stmts.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/tree-vect-stmts.c	(.../branches/gcc-6-branch)
+@@ -2320,7 +2320,7 @@
+       if (cfn != CFN_LAST)
+ 	fndecl = targetm.vectorize.builtin_vectorized_function
+ 	  (cfn, vectype_out, vectype_in);
+-      else
++      else if (callee)
+ 	fndecl = targetm.vectorize.builtin_md_vectorized_function
+ 	  (callee, vectype_out, vectype_in);
+     }
+@@ -5317,6 +5317,12 @@
+ 
+   op = gimple_assign_rhs1 (stmt);
+ 
++  /* In the case this is a store from a STRING_CST make sure
++     native_encode_expr can handle it.  */
++  if (TREE_CODE (op) == STRING_CST
++      && ! can_native_encode_string_p (op))
++    return false;
++
+   if (!vect_is_simple_use (op, vinfo, &def_stmt, &dt, &rhs_vectype))
+     {
+       if (dump_enabled_p ())
+Index: gcc/symtab.c
+===================================================================
+--- a/src/gcc/symtab.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/symtab.c	(.../branches/gcc-6-branch)
+@@ -35,6 +35,7 @@
+ #include "output.h"
+ #include "ipa-utils.h"
+ #include "calls.h"
++#include "builtins.h"
+ 
+ static const char *ipa_ref_use_name[] = {"read","write","addr","alias","chkp"};
+ 
+@@ -2207,3 +2208,58 @@
+   return '_';
+ #endif
+ }
++
++/* Return true if symbol should be output to the symbol table.  */
++
++bool
++symtab_node::output_to_lto_symbol_table_p (void)
++{
++  /* Only externally visible symbols matter.  */
++  if (!TREE_PUBLIC (decl))
++    return false;
++  if (!real_symbol_p ())
++    return false;
++  /* FIXME: variables probably should not be considered as real symbols at
++     first place.  */
++  if (VAR_P (decl) && DECL_HARD_REGISTER (decl))
++    return false;
++  /* FIXME: Builtins corresponding to real functions probably should have
++     symbol table entries.  */
++  if (is_builtin_fn (decl))
++    return false;
++
++  /* We have real symbol that should be in symbol table.  However try to trim
++     down the refernces to libraries bit more because linker will otherwise
++     bring unnecesary object files into the final link.
++     FIXME: The following checks can easily be confused i.e. by self recursive
++     function or self-referring variable.  */
++
++  /* We keep external functions in symtab for sake of inlining
++     and devirtualization.  We do not want to see them in symbol table as
++     references unless they are really used.  */
++  cgraph_node *cnode = dyn_cast <cgraph_node *> (this);
++  if (cnode && (!definition || DECL_EXTERNAL (decl))
++      && cnode->callers)
++    return true;
++
++ /* Ignore all references from external vars initializers - they are not really
++    part of the compilation unit until they are used by folding.  Some symbols,
++    like references to external construction vtables can not be referred to at
++    all.  We decide this at can_refer_decl_in_current_unit_p.  */
++ if (!definition || DECL_EXTERNAL (decl))
++    {
++      int i;
++      struct ipa_ref *ref;
++      for (i = 0; iterate_referring (i, ref); i++)
++	{
++	  if (ref->use == IPA_REF_ALIAS)
++	    continue;
++          if (is_a <cgraph_node *> (ref->referring))
++	    return true;
++	  if (!DECL_EXTERNAL (ref->referring->decl))
++	    return true;
++	}
++      return false;
++    }
++  return true;
++}
+Index: gcc/combine.c
+===================================================================
+--- a/src/gcc/combine.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/combine.c	(.../branches/gcc-6-branch)
+@@ -329,9 +329,17 @@
+ 
+ static struct insn_link **uid_log_links;
+ 
+-#define INSN_COST(INSN)		(uid_insn_cost[INSN_UID (INSN)])
+-#define LOG_LINKS(INSN)		(uid_log_links[INSN_UID (INSN)])
++static inline int
++insn_uid_check (const_rtx insn)
++{
++  int uid = INSN_UID (insn);
++  gcc_checking_assert (uid <= max_uid_known);
++  return uid;
++}
+ 
++#define INSN_COST(INSN)		(uid_insn_cost[insn_uid_check (INSN)])
++#define LOG_LINKS(INSN)		(uid_log_links[insn_uid_check (INSN)])
++
+ #define FOR_EACH_LOG_LINK(L, INSN)				\
+   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
+ 
+@@ -678,7 +686,7 @@
+   for (next = NEXT_INSN (insn);
+        next && BLOCK_FOR_INSN (next) == bb;
+        next = NEXT_INSN (next))
+-    if (INSN_P (next) && dead_or_set_p (next, dest))
++    if (NONDEBUG_INSN_P (next) && dead_or_set_p (next, dest))
+       {
+ 	FOR_EACH_LOG_LINK (link, next)
+ 	  if (link->insn == insn && link->regno == REGNO (dest))
+@@ -1129,7 +1137,7 @@
+ 
+   int new_direct_jump_p = 0;
+ 
+-  for (first = f; first && !INSN_P (first); )
++  for (first = f; first && !NONDEBUG_INSN_P (first); )
+     first = NEXT_INSN (first);
+   if (!first)
+     return 0;
+@@ -2277,7 +2285,7 @@
+   /* If this isn't really an insn, we can't do anything.
+      This can occur when flow deletes an insn that it has merged into an
+      auto-increment address.  */
+-  if (! INSN_P (insn))
++  if (!NONDEBUG_INSN_P (insn))
+     return 1;
+ 
+   /* Never combine loads and stores involving hard regs that are likely
+@@ -2947,7 +2955,8 @@
+       && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
+       && can_split_parallel_of_n_reg_sets (i2, 2)
+       && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
+-      && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
++      && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)
++      && !find_reg_note (i2, REG_UNUSED, 0))
+     {
+       /* If there is no I1, there is no I0 either.  */
+       i0 = i1;
+@@ -4171,7 +4180,8 @@
+ 		    || insn != BB_HEAD (this_basic_block->next_bb));
+ 	   insn = NEXT_INSN (insn))
+ 	{
+-	  if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
++	  if (NONDEBUG_INSN_P (insn)
++	      && reg_referenced_p (ni2dest, PATTERN (insn)))
+ 	    {
+ 	      FOR_EACH_LOG_LINK (link, insn)
+ 		if (link->insn == i3)
+@@ -4312,9 +4322,9 @@
+ 	    for (temp_insn = NEXT_INSN (i2);
+ 		 temp_insn
+ 		 && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
+-			  || BB_HEAD (this_basic_block) != temp_insn);
++		     || BB_HEAD (this_basic_block) != temp_insn);
+ 		 temp_insn = NEXT_INSN (temp_insn))
+-	      if (temp_insn != i3 && INSN_P (temp_insn))
++	      if (temp_insn != i3 && NONDEBUG_INSN_P (temp_insn))
+ 		FOR_EACH_LOG_LINK (link, temp_insn)
+ 		  if (link->insn == i2)
+ 		    link->insn = i3;
+@@ -13941,6 +13951,17 @@
+ 		  && CALL_P (from_insn)
+ 		  && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
+ 		place = from_insn;
++	      else if (i2 && reg_set_p (XEXP (note, 0), PATTERN (i2)))
++		{
++		  /* If the new I2 sets the same register that is marked
++		     dead in the note, we do not in general know where to
++		     put the note.  One important case we _can_ handle is
++		     when the note comes from I3.  */
++		  if (from_insn == i3)
++		    place = i3;
++		  else
++		    break;
++		}
+ 	      else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
+ 		place = i3;
+ 	      else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
+@@ -13954,11 +13975,6 @@
+ 		       || rtx_equal_p (XEXP (note, 0), elim_i0))
+ 		break;
+ 	      tem_insn = i3;
+-	      /* If the new I2 sets the same register that is marked dead
+-		 in the note, we do not know where to put the note.
+-		 Give up.  */
+-	      if (i2 != 0 && reg_set_p (XEXP (note, 0), PATTERN (i2)))
+-		break;
+ 	    }
+ 
+ 	  if (place == 0)
+Index: gcc/bb-reorder.c
+===================================================================
+--- a/src/gcc/bb-reorder.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/bb-reorder.c	(.../branches/gcc-6-branch)
+@@ -2905,7 +2905,8 @@
+ 
+   crossing_edges = find_rarely_executed_basic_blocks_and_crossing_edges ();
+   if (!crossing_edges.exists ())
+-    return 0;
++    /* Make sure to process deferred rescans and clear changeable df flags.  */
++    return TODO_df_finish;
+ 
+   crtl->has_bb_partition = true;
+ 
+@@ -2971,7 +2972,8 @@
+       df_analyze ();
+     }
+ 
+-  return 0;
++  /* Make sure to process deferred rescans and clear changeable df flags.  */
++  return TODO_df_finish;
+ }
+ 
+ } // anon namespace
+Index: gcc/hsa-brig.c
+===================================================================
+--- a/src/gcc/hsa-brig.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/hsa-brig.c	(.../branches/gcc-6-branch)
+@@ -492,7 +492,7 @@
+ 	  else
+ 	    part++;
+ 	  char *modname2;
+-	  asprintf (&modname2, "%s_%s", modname, part);
++	  modname2 = xasprintf ("%s_%s", modname, part);
+ 	  free (modname);
+ 	  modname = modname2;
+ 	}
+Index: gcc/config.gcc
+===================================================================
+--- a/src/gcc/config.gcc	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config.gcc	(.../branches/gcc-6-branch)
+@@ -850,8 +850,8 @@
+   sol2_tm_file_tail="${cpu_type}/sol2.h sol2.h"
+   sol2_tm_file="${sol2_tm_file_head} ${sol2_tm_file_tail}"
+   case ${target} in
+-    *-*-solaris2.1[2-9]*)
+-      # __cxa_atexit was introduced in Solaris 12.
++    *-*-solaris2.1[1-9]*)
++      # __cxa_atexit was introduced in Solaris 11.4.
+       default_use_cxa_atexit=yes
+       ;;
+   esac
+@@ -1072,6 +1072,10 @@
+                tm_defines="${tm_defines} TARGET_FREEBSD_ARM_HARD_FLOAT=1"
+             fi
+ 	    ;;
++	armv7*-*-freebsd*)
++	    tm_defines="${tm_defines} TARGET_FREEBSD_ARMv7=1"
++	    tm_defines="${tm_defines} TARGET_FREEBSD_ARM_HARD_FLOAT=1"
++	    ;;
+ 	esac
+ 	with_tls=${with_tls:-gnu}
+ 	;;
+Index: gcc/opts-global.c
+===================================================================
+--- a/src/gcc/opts-global.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/opts-global.c	(.../branches/gcc-6-branch)
+@@ -167,7 +167,8 @@
+ 		    unsigned int lang_mask ATTRIBUTE_UNUSED, int kind,
+ 		    location_t loc,
+ 		    const struct cl_option_handlers *handlers,
+-		    diagnostic_context *dc)
++		    diagnostic_context *dc,
++		    void (*) (void))
+ {
+   gcc_assert (opts == &global_options);
+   gcc_assert (opts_set == &global_options_set);
+@@ -267,10 +268,12 @@
+ /* Set *HANDLERS to the default set of option handlers for use in the
+    compilers proper (not the driver).  */
+ void
+-set_default_handlers (struct cl_option_handlers *handlers)
++set_default_handlers (struct cl_option_handlers *handlers,
++		      void (*target_option_override_hook) (void))
+ {
+   handlers->unknown_option_callback = unknown_option_callback;
+   handlers->wrong_lang_callback = complain_wrong_lang;
++  handlers->target_option_override_hook = target_option_override_hook;
+   handlers->num_handlers = 3;
+   handlers->handlers[0].handler = lang_handle_option;
+   handlers->handlers[0].mask = initial_lang_mask;
+@@ -288,7 +291,8 @@
+ decode_options (struct gcc_options *opts, struct gcc_options *opts_set,
+ 		struct cl_decoded_option *decoded_options,
+ 		unsigned int decoded_options_count,
+-		location_t loc, diagnostic_context *dc)
++		location_t loc, diagnostic_context *dc,
++		void (*target_option_override_hook) (void))
+ {
+   struct cl_option_handlers handlers;
+ 
+@@ -296,7 +300,7 @@
+ 
+   lang_mask = initial_lang_mask;
+ 
+-  set_default_handlers (&handlers);
++  set_default_handlers (&handlers, target_option_override_hook);
+ 
+   default_options_optimization (opts, opts_set,
+ 				decoded_options, decoded_options_count,
+Index: gcc/tree-ssa-structalias.c
+===================================================================
+--- a/src/gcc/tree-ssa-structalias.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/tree-ssa-structalias.c	(.../branches/gcc-6-branch)
+@@ -2833,7 +2833,6 @@
+ {
+   const char *res = NULL;
+   char *temp;
+-  int num_printed = 0;
+ 
+   if (!dump_file)
+     return "NULL";
+@@ -2842,14 +2841,11 @@
+     {
+       res = get_name (decl);
+       if (res)
+-	num_printed = asprintf (&temp, "%s_%u", res, SSA_NAME_VERSION (decl));
++	temp = xasprintf ("%s_%u", res, SSA_NAME_VERSION (decl));
+       else
+-	num_printed = asprintf (&temp, "_%u", SSA_NAME_VERSION (decl));
+-      if (num_printed > 0)
+-	{
+-	  res = ggc_strdup (temp);
+-	  free (temp);
+-	}
++	temp = xasprintf ("_%u", SSA_NAME_VERSION (decl));
++      res = ggc_strdup (temp);
++      free (temp);
+     }
+   else if (DECL_P (decl))
+     {
+@@ -2860,12 +2856,9 @@
+ 	  res = get_name (decl);
+ 	  if (!res)
+ 	    {
+-	      num_printed = asprintf (&temp, "D.%u", DECL_UID (decl));
+-	      if (num_printed > 0)
+-		{
+-		  res = ggc_strdup (temp);
+-		  free (temp);
+-		}
++	      temp = xasprintf ("D.%u", DECL_UID (decl));
++	      res = ggc_strdup (temp);
++	      free (temp);
+ 	    }
+ 	}
+     }
+Index: gcc/tree-cfg.c
+===================================================================
+--- a/src/gcc/tree-cfg.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/tree-cfg.c	(.../branches/gcc-6-branch)
+@@ -6527,7 +6527,15 @@
+ 		*tp = t = out->to;
+ 	    }
+ 
+-	  DECL_CONTEXT (t) = p->to_context;
++	  /* For FORCED_LABELs we can end up with references from other
++	     functions if some SESE regions are outlined.  It is UB to
++	     jump in between them, but they could be used just for printing
++	     addresses etc.  In that case, DECL_CONTEXT on the label should
++	     be the function containing the glabel stmt with that LABEL_DECL,
++	     rather than whatever function a reference to the label was seen
++	     last time.  */
++	  if (!FORCED_LABEL (t) && !DECL_NONLOCAL (t))
++	    DECL_CONTEXT (t) = p->to_context;
+ 	}
+       else if (p->remap_decls_p)
+ 	{
+@@ -6646,6 +6654,21 @@
+     case GIMPLE_OMP_RETURN:
+     case GIMPLE_OMP_CONTINUE:
+       break;
++
++    case GIMPLE_LABEL:
++      {
++	/* For FORCED_LABEL, move_stmt_op doesn't adjust DECL_CONTEXT,
++	   so that such labels can be referenced from other regions.
++	   Make sure to update it when seeing a GIMPLE_LABEL though,
++	   that is the owner of the label.  */
++	walk_gimple_op (stmt, move_stmt_op, wi);
++	*handled_ops_p = true;
++	tree label = gimple_label_label (as_a <glabel *> (stmt));
++	if (FORCED_LABEL (label) || DECL_NONLOCAL (label))
++	  DECL_CONTEXT (label) = p->to_context;
++      }
++      break;
++
+     default:
+       if (is_gimple_omp (stmt))
+ 	{
+Index: gcc/hwint.h
+===================================================================
+--- a/src/gcc/hwint.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/hwint.h	(.../branches/gcc-6-branch)
+@@ -14,6 +14,7 @@
+ #define HOST_BITS_PER_SHORT (CHAR_BIT * SIZEOF_SHORT)
+ #define HOST_BITS_PER_INT   (CHAR_BIT * SIZEOF_INT)
+ #define HOST_BITS_PER_LONG  (CHAR_BIT * SIZEOF_LONG)
++#define HOST_BITS_PER_PTR   (CHAR_BIT * SIZEOF_VOID_P)
+ 
+ /* The string that should be inserted into a printf style format to
+    indicate a "long" operand.  */
+Index: gcc/tree-ssa-reassoc.c
+===================================================================
+--- a/src/gcc/tree-ssa-reassoc.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/tree-ssa-reassoc.c	(.../branches/gcc-6-branch)
+@@ -3710,11 +3710,15 @@
+ 
+ /* Recursively rewrite our linearized statements so that the operators
+    match those in OPS[OPINDEX], putting the computation in rank
+-   order.  Return new lhs.  */
++   order.  Return new lhs.
++   CHANGED is true if we shouldn't reuse the lhs SSA_NAME both in
++   the current stmt and during recursive invocations.
++   NEXT_CHANGED is true if we shouldn't reuse the lhs SSA_NAME in
++   recursive invocations.  */
+ 
+ static tree
+ rewrite_expr_tree (gimple *stmt, unsigned int opindex,
+-		   vec<operand_entry *> ops, bool changed)
++		   vec<operand_entry *> ops, bool changed, bool next_changed)
+ {
+   tree rhs1 = gimple_assign_rhs1 (stmt);
+   tree rhs2 = gimple_assign_rhs2 (stmt);
+@@ -3794,7 +3798,8 @@
+      be the non-leaf side.  */
+   tree new_rhs1
+     = rewrite_expr_tree (SSA_NAME_DEF_STMT (rhs1), opindex + 1, ops,
+-			 changed || oe->op != rhs2);
++			 changed || oe->op != rhs2 || next_changed,
++			 false);
+ 
+   if (oe->op != rhs2 || new_rhs1 != rhs1)
+     {
+@@ -5115,6 +5120,7 @@
+ 	      gimple_set_visited (stmt, true);
+ 	      linearize_expr_tree (&ops, stmt, true, true);
+ 	      ops.qsort (sort_by_operand_rank);
++	      int orig_len = ops.length ();
+ 	      optimize_ops_list (rhs_code, &ops);
+ 	      if (undistribute_ops_list (rhs_code, &ops,
+ 					 loop_containing_stmt (stmt)))
+@@ -5179,7 +5185,8 @@
+                         swap_ops_for_binary_stmt (ops, len - 3, stmt);
+ 
+ 		      new_lhs = rewrite_expr_tree (stmt, 0, ops,
+-						   powi_result != NULL);
++						   powi_result != NULL,
++						   len != orig_len);
+                     }
+ 
+ 		  /* If we combined some repeated factors into a 
+Index: gcc/config/nvptx/nvptx.c
+===================================================================
+--- a/src/gcc/config/nvptx/nvptx.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/nvptx/nvptx.c	(.../branches/gcc-6-branch)
+@@ -1483,9 +1483,15 @@
+   
+   if (sym)
+     {
+-      fprintf (asm_out_file, "generic(");
++      bool function = (SYMBOL_REF_DECL (sym)
++		       && (TREE_CODE (SYMBOL_REF_DECL (sym)) == FUNCTION_DECL));
++      if (!function)
++	fprintf (asm_out_file, "generic(");
+       output_address (VOIDmode, sym);
+-      fprintf (asm_out_file, val ? ") + " : ")");
++      if (!function)
++	fprintf (asm_out_file, ")");
++      if (val)
++	fprintf (asm_out_file, " + ");
+     }
+ 
+   if (!sym || val)
+Index: gcc/config/alpha/sync.md
+===================================================================
+--- a/src/gcc/config/alpha/sync.md	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/alpha/sync.md	(.../branches/gcc-6-branch)
+@@ -24,7 +24,7 @@
+   [(plus "add_operand") (minus "reg_or_8bit_operand")
+    (ior "or_operand") (xor "or_operand") (and "and_operand")])
+ (define_code_attr fetchop_constr
+-  [(plus "rKL") (minus "rI") (ior "rIN") (xor "rIN") (and "riNM")])
++  [(plus "rKL") (minus "rI") (ior "rIN") (xor "rIN") (and "rINM")])
+ 
+ 
+ (define_expand "memory_barrier"
+Index: gcc/config/s390/s390.md
+===================================================================
+--- a/src/gcc/config/s390/s390.md	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/s390/s390.md	(.../branches/gcc-6-branch)
+@@ -89,6 +89,7 @@
+    UNSPEC_LTREF
+    UNSPEC_INSN
+    UNSPEC_EXECUTE
++   UNSPEC_EXECUTE_JUMP
+ 
+    ; Atomic Support
+    UNSPEC_MB
+@@ -292,6 +293,8 @@
+   [
+    ; Sibling call register.
+    (SIBCALL_REGNUM		 1)
++   ; A call-clobbered reg which can be used in indirect branch thunks
++   (INDIRECT_BRANCH_THUNK_REGNUM 1)
+    ; Literal pool base register.
+    (BASE_REGNUM			13)
+    ; Return address register.
+@@ -461,7 +464,10 @@
+                          z196_cracked"
+              (const_string "none"))
+ 
+-(define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
++; mnemonics which only get defined through if_then_else currently
++; don't get added to the list values automatically and hence need to
++; be listed here.
++(define_attr "mnemonic" "b,br,bas,bc,bcr,bcr_flush,unknown" (const_string "unknown"))
+ 
+ ;; Length in bytes.
+ 
+@@ -8631,7 +8637,7 @@
+           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
+           (match_operand 0 "address_operand" "ZQZR")
+           (pc)))]
+-  ""
++  "!TARGET_INDIRECT_BRANCH_NOBP_JUMP"
+ {
+   if (get_attr_op_type (insn) == OP_TYPE_RR)
+     return "b%C1r\t%0";
+@@ -8641,6 +8647,9 @@
+   [(set (attr "op_type")
+         (if_then_else (match_operand 0 "register_operand" "")
+                       (const_string "RR") (const_string "RX")))
++   (set (attr "mnemonic")
++        (if_then_else (match_operand 0 "register_operand" "")
++                      (const_string "bcr") (const_string "bc")))
+    (set_attr "type"  "branch")
+    (set_attr "atype" "agen")])
+ 
+@@ -8652,8 +8661,26 @@
+           (ANY_RETURN)
+           (pc)))]
+   "s390_can_use_<code>_insn ()"
+-  "b%C0r\t%%r14"
+-  [(set_attr "op_type" "RR")
++{
++  if (TARGET_INDIRECT_BRANCH_NOBP_RET)
++    {
++      s390_indirect_branch_via_thunk (RETURN_REGNUM,
++				      INVALID_REGNUM,
++				      operands[0],
++				      s390_indirect_branch_type_return);
++      return "";
++    }
++  else
++    return "b%C0r\t%%r14";
++}
++  [(set (attr "op_type")
++	(if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
++		      (const_string "RIL")
++		      (const_string "RR")))
++   (set (attr "mnemonic")
++	(if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
++		      (const_string "brcl")
++		      (const_string "bcr")))
+    (set_attr "type"  "jsr")
+    (set_attr "atype" "agen")])
+ 
+@@ -8706,7 +8733,7 @@
+           (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
+           (pc)
+           (match_operand 0 "address_operand" "ZQZR")))]
+-  ""
++  "!TARGET_INDIRECT_BRANCH_NOBP_JUMP"
+ {
+   if (get_attr_op_type (insn) == OP_TYPE_RR)
+     return "b%D1r\t%0";
+@@ -8716,6 +8743,9 @@
+   [(set (attr "op_type")
+         (if_then_else (match_operand 0 "register_operand" "")
+                       (const_string "RR") (const_string "RX")))
++   (set (attr "mnemonic")
++        (if_then_else (match_operand 0 "register_operand" "")
++                      (const_string "bcr") (const_string "bc")))
+    (set_attr "type"  "branch")
+    (set_attr "atype" "agen")])
+ 
+@@ -9208,30 +9238,220 @@
+ ; indirect-jump instruction pattern(s).
+ ;
+ 
+-(define_insn "indirect_jump"
++(define_expand "indirect_jump"
+  [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
+   ""
+ {
++  if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK)
++    {
++      operands[0] = force_reg (Pmode, operands[0]);
++      if (TARGET_CPU_Z10)
++	{
++	  if (TARGET_64BIT)
++	    emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0]));
++	  else
++	    emit_jump_insn (gen_indirect_jump_via_thunksi_z10 (operands[0]));
++	}
++      else
++	{
++	  if (TARGET_64BIT)
++	    emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0]));
++	  else
++	    emit_jump_insn (gen_indirect_jump_via_thunksi (operands[0]));
++	}
++      DONE;
++    }
++
++  if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK)
++    {
++      operands[0] = force_reg (Pmode, operands[0]);
++      rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
++      if (TARGET_CPU_Z10)
++	{
++	  if (TARGET_64BIT)
++	    emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0],
++								     label_ref));
++	  else
++	    emit_jump_insn (gen_indirect_jump_via_inlinethunksi_z10 (operands[0],
++								     label_ref));
++	}
++      else
++	{
++	  if (TARGET_64BIT)
++	    emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0],
++								 label_ref,
++								 force_reg (Pmode, label_ref)));
++	  else
++	    emit_jump_insn (gen_indirect_jump_via_inlinethunksi (operands[0],
++								 label_ref,
++								 force_reg (Pmode, label_ref)));
++	}
++      DONE;
++    }
++})
++
++(define_insn "*indirect_jump"
++  [(set (pc)
++	(match_operand 0 "address_operand" "ZR"))]
++ "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK"
++{
+   if (get_attr_op_type (insn) == OP_TYPE_RR)
+     return "br\t%0";
+   else
+     return "b\t%a0";
+ }
+-  [(set (attr "op_type")
+-        (if_then_else (match_operand 0 "register_operand" "")
+-                      (const_string "RR") (const_string "RX")))
+-   (set_attr "type"  "branch")
+-   (set_attr "atype" "agen")])
++ [(set (attr "op_type")
++       (if_then_else (match_operand 0 "register_operand" "")
++		     (const_string "RR") (const_string "RX")))
++  (set (attr "mnemonic")
++       (if_then_else (match_operand 0 "register_operand" "")
++		     (const_string "br") (const_string "b")))
++  (set_attr "type"  "branch")
++  (set_attr "atype" "agen")])
+ 
++(define_insn "indirect_jump_via_thunk<mode>_z10"
++  [(set (pc)
++	(match_operand:P 0 "register_operand" "a"))]
++ "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK
++  && TARGET_CPU_Z10"
++{
++  s390_indirect_branch_via_thunk (REGNO (operands[0]),
++				  INVALID_REGNUM,
++				  NULL_RTX,
++				  s390_indirect_branch_type_jump);
++  return "";
++}
++ [(set_attr "op_type"  "RIL")
++  (set_attr "mnemonic" "jg")
++  (set_attr "type"  "branch")
++  (set_attr "atype" "agen")])
++
++(define_insn "indirect_jump_via_thunk<mode>"
++  [(set (pc)
++	(match_operand:P 0 "register_operand" " a"))
++   (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
++ "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK
++  && !TARGET_CPU_Z10"
++{
++  s390_indirect_branch_via_thunk (REGNO (operands[0]),
++				  INVALID_REGNUM,
++				  NULL_RTX,
++				  s390_indirect_branch_type_jump);
++  return "";
++}
++ [(set_attr "op_type"  "RIL")
++  (set_attr "mnemonic" "jg")
++  (set_attr "type"  "branch")
++  (set_attr "atype" "agen")])
++
++
++; The label_ref is wrapped into an if_then_else in order to hide it
++; from mark_jump_label.  Without this the label_ref would become the
++; ONLY jump target of that jump breaking the control flow graph.
++(define_insn "indirect_jump_via_inlinethunk<mode>_z10"
++  [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X")
++			  (const_int 0)
++			  (const_int 0))
++	    (const_int 0)] UNSPEC_EXECUTE_JUMP)
++   (set (pc) (match_operand:P 0 "register_operand" "a"))]
++  "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK
++   && TARGET_CPU_Z10"
++{
++  s390_indirect_branch_via_inline_thunk (operands[1]);
++  return "";
++}
++  [(set_attr "op_type" "RIL")
++   (set_attr "type"    "branch")
++   (set_attr "length"  "10")])
++
++(define_insn "indirect_jump_via_inlinethunk<mode>"
++  [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X")
++			  (const_int 0)
++			  (const_int 0))
++	    (match_operand:P 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP)
++   (set (pc) (match_operand:P 0 "register_operand" "a"))]
++  "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK
++   && !TARGET_CPU_Z10"
++{
++  s390_indirect_branch_via_inline_thunk (operands[2]);
++  return "";
++}
++  [(set_attr "op_type" "RX")
++   (set_attr "type"    "branch")
++   (set_attr "length"  "8")])
++
+ ;
+ ; casesi instruction pattern(s).
+ ;
+ 
+-(define_insn "casesi_jump"
+- [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
+-   (use (label_ref (match_operand 1 "" "")))]
++(define_expand "casesi_jump"
++  [(parallel
++    [(set (pc) (match_operand 0 "address_operand"))
++     (use (label_ref (match_operand 1 "")))])]
+   ""
+ {
++  if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK)
++    {
++      operands[0] = force_reg (GET_MODE (operands[0]), operands[0]);
++
++      if (TARGET_CPU_Z10)
++	{
++	  if (TARGET_64BIT)
++	    emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0],
++							     operands[1]));
++	  else
++	    emit_jump_insn (gen_casesi_jump_via_thunksi_z10 (operands[0],
++							     operands[1]));
++	}
++      else
++	{
++	  if (TARGET_64BIT)
++	    emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0],
++							 operands[1]));
++	  else
++	    emit_jump_insn (gen_casesi_jump_via_thunksi (operands[0],
++							 operands[1]));
++	}
++      DONE;
++    }
++
++    if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK)
++    {
++      operands[0] = force_reg (Pmode, operands[0]);
++      rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
++      if (TARGET_CPU_Z10)
++	{
++	  if (TARGET_64BIT)
++	    emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0],
++								   operands[1],
++								   label_ref));
++	  else
++	    emit_jump_insn (gen_casesi_jump_via_inlinethunksi_z10 (operands[0],
++								   operands[1],
++								   label_ref));
++	}
++      else
++	{
++	  if (TARGET_64BIT)
++	    emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0],
++							       operands[1],
++							       label_ref,
++							       force_reg (Pmode, label_ref)));
++	  else
++	    emit_jump_insn (gen_casesi_jump_via_inlinethunksi (operands[0],
++							       operands[1],
++							       label_ref,
++							       force_reg (Pmode, label_ref)));
++	}
++      DONE;
++    }
++})
++
++(define_insn "*casesi_jump"
++ [(set (pc) (match_operand 0 "address_operand" "ZR"))
++  (use (label_ref (match_operand 1 "" "")))]
++ "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK"
++{
+   if (get_attr_op_type (insn) == OP_TYPE_RR)
+     return "br\t%0";
+   else
+@@ -9240,9 +9460,85 @@
+   [(set (attr "op_type")
+         (if_then_else (match_operand 0 "register_operand" "")
+                       (const_string "RR") (const_string "RX")))
++   (set (attr "mnemonic")
++        (if_then_else (match_operand 0 "register_operand" "")
++                      (const_string "br") (const_string "b")))
+    (set_attr "type"  "branch")
+    (set_attr "atype" "agen")])
+ 
++(define_insn "casesi_jump_via_thunk<mode>_z10"
++ [(set (pc) (match_operand:P 0 "register_operand" "a"))
++  (use (label_ref (match_operand 1 "" "")))]
++ "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK
++  && TARGET_CPU_Z10"
++{
++  s390_indirect_branch_via_thunk (REGNO (operands[0]),
++				  INVALID_REGNUM,
++				  NULL_RTX,
++				  s390_indirect_branch_type_jump);
++  return "";
++}
++  [(set_attr "op_type" "RIL")
++   (set_attr "mnemonic" "jg")
++   (set_attr "type"  "branch")
++   (set_attr "atype" "agen")])
++
++(define_insn "casesi_jump_via_thunk<mode>"
++ [(set (pc) (match_operand:P 0 "register_operand" "a"))
++  (use (label_ref (match_operand 1 "" "")))
++  (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
++ "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK
++  && !TARGET_CPU_Z10"
++{
++  s390_indirect_branch_via_thunk (REGNO (operands[0]),
++				  INVALID_REGNUM,
++				  NULL_RTX,
++				  s390_indirect_branch_type_jump);
++  return "";
++}
++  [(set_attr "op_type" "RIL")
++   (set_attr "mnemonic" "jg")
++   (set_attr "type"  "branch")
++   (set_attr "atype" "agen")])
++
++
++; The label_ref is wrapped into an if_then_else in order to hide it
++; from mark_jump_label.  Without this the label_ref would become the
++; ONLY jump target of that jump breaking the control flow graph.
++(define_insn "casesi_jump_via_inlinethunk<mode>_z10"
++  [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X")
++			  (const_int 0)
++			  (const_int 0))
++	    (const_int 0)] UNSPEC_EXECUTE_JUMP)
++   (set (pc) (match_operand:P 0 "register_operand" "a"))
++   (use (label_ref (match_operand 1 "" "")))]
++  "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK
++   && TARGET_CPU_Z10"
++{
++  s390_indirect_branch_via_inline_thunk (operands[2]);
++  return "";
++}
++  [(set_attr "op_type" "RIL")
++   (set_attr "type"    "cs")
++   (set_attr "length"  "10")])
++
++(define_insn "casesi_jump_via_inlinethunk<mode>"
++  [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X")
++			  (const_int 0)
++			  (const_int 0))
++	    (match_operand:P 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP)
++   (set (pc) (match_operand:P 0 "register_operand" "a"))
++   (use (label_ref (match_operand 1 "" "")))]
++  "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK
++   && !TARGET_CPU_Z10"
++{
++  s390_indirect_branch_via_inline_thunk (operands[3]);
++  return "";
++}
++  [(set_attr "op_type" "RX")
++   (set_attr "type"    "cs")
++   (set_attr "length"  "8")])
++
+ (define_expand "casesi"
+   [(match_operand:SI 0 "general_operand" "")
+    (match_operand:SI 1 "general_operand" "")
+@@ -9347,8 +9643,27 @@
+          (match_operand 0 "const_int_operand" "n"))]
+   "SIBLING_CALL_P (insn)
+    && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
+-  "br\t%%r1"
+-  [(set_attr "op_type" "RR")
++{
++  if (TARGET_INDIRECT_BRANCH_NOBP_CALL)
++    {
++      gcc_assert (TARGET_CPU_Z10);
++      s390_indirect_branch_via_thunk (SIBCALL_REGNUM,
++				      INVALID_REGNUM,
++				      NULL_RTX,
++				      s390_indirect_branch_type_call);
++      return "";
++    }
++  else
++    return "br\t%%r1";
++}
++ [(set (attr "op_type")
++       (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL")
++		     (const_string "RIL")
++		     (const_string "RR")))
++  (set (attr "mnemonic")
++       (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL")
++		     (const_string "jg")
++		     (const_string "br")))
+    (set_attr "type"  "branch")
+    (set_attr "atype" "agen")])
+ 
+@@ -9388,8 +9703,27 @@
+ 	      (match_operand 1 "const_int_operand" "n")))]
+   "SIBLING_CALL_P (insn)
+    && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
+-  "br\t%%r1"
+-  [(set_attr "op_type" "RR")
++{
++  if (TARGET_INDIRECT_BRANCH_NOBP_CALL)
++    {
++      gcc_assert (TARGET_CPU_Z10);
++      s390_indirect_branch_via_thunk (SIBCALL_REGNUM,
++				      INVALID_REGNUM,
++				      NULL_RTX,
++				      s390_indirect_branch_type_call);
++      return "";
++    }
++  else
++    return "br\t%%r1";
++}
++  [(set (attr "op_type")
++       (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL")
++		     (const_string "RIL")
++		     (const_string "RR")))
++   (set (attr "mnemonic")
++       (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL")
++		     (const_string "jg")
++		     (const_string "br")))
+    (set_attr "type"  "branch")
+    (set_attr "atype" "agen")])
+ 
+@@ -9455,7 +9789,9 @@
+   [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
+          (match_operand 1 "const_int_operand" "n"))
+    (clobber (match_operand 2 "register_operand" "=r"))]
+-  "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
++  "!TARGET_INDIRECT_BRANCH_NOBP_CALL
++   && !SIBLING_CALL_P (insn)
++   && GET_MODE (operands[2]) == Pmode"
+ {
+   if (get_attr_op_type (insn) == OP_TYPE_RR)
+     return "basr\t%2,%0";
+@@ -9465,10 +9801,54 @@
+   [(set (attr "op_type")
+         (if_then_else (match_operand 0 "register_operand" "")
+                       (const_string "RR") (const_string "RX")))
++   (set (attr "mnemonic")
++        (if_then_else (match_operand 0 "register_operand" "")
++                      (const_string "basr") (const_string "bas")))
+    (set_attr "type"  "jsr")
+    (set_attr "atype" "agen")
+    (set_attr "z196prop" "z196_cracked")])
+ 
++(define_insn "*basr_via_thunk<mode>_z10"
++  [(call (mem:QI (match_operand:P 0 "register_operand" "a"))
++         (match_operand 1 "const_int_operand"          "n"))
++   (clobber (match_operand:P 2 "register_operand"    "=&r"))]
++  "TARGET_INDIRECT_BRANCH_NOBP_CALL
++   && TARGET_CPU_Z10
++   && !SIBLING_CALL_P (insn)"
++{
++  s390_indirect_branch_via_thunk (REGNO (operands[0]),
++				  REGNO (operands[2]),
++				  NULL_RTX,
++				  s390_indirect_branch_type_call);
++  return "";
++}
++  [(set_attr "op_type" "RIL")
++   (set_attr "mnemonic" "brasl")
++   (set_attr "type"  "jsr")
++   (set_attr "atype" "agen")
++   (set_attr "z196prop" "z196_cracked")])
++
++(define_insn "*basr_via_thunk<mode>"
++  [(call (mem:QI (match_operand:P 0 "register_operand" "a"))
++         (match_operand 1 "const_int_operand"          "n"))
++   (clobber (match_operand:P 2 "register_operand"    "=&r"))
++   (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
++  "TARGET_INDIRECT_BRANCH_NOBP_CALL
++   && !TARGET_CPU_Z10
++   && !SIBLING_CALL_P (insn)"
++{
++  s390_indirect_branch_via_thunk (REGNO (operands[0]),
++				  REGNO (operands[2]),
++				  NULL_RTX,
++				  s390_indirect_branch_type_call);
++  return "";
++}
++  [(set_attr "op_type" "RIL")
++   (set_attr "mnemonic" "brasl")
++   (set_attr "type"  "jsr")
++   (set_attr "atype" "agen")
++   (set_attr "z196prop" "z196_cracked")])
++
+ ;
+ ; call_value instruction pattern(s).
+ ;
+@@ -9516,7 +9896,9 @@
+         (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
+               (match_operand 2 "const_int_operand" "n")))
+    (clobber (match_operand 3 "register_operand" "=r"))]
+-  "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
++  "!TARGET_INDIRECT_BRANCH_NOBP_CALL
++   && !SIBLING_CALL_P (insn)
++   && GET_MODE (operands[3]) == Pmode"
+ {
+   if (get_attr_op_type (insn) == OP_TYPE_RR)
+     return "basr\t%3,%1";
+@@ -9526,10 +9908,58 @@
+   [(set (attr "op_type")
+         (if_then_else (match_operand 1 "register_operand" "")
+                       (const_string "RR") (const_string "RX")))
++   (set (attr "mnemonic")
++        (if_then_else (match_operand 1 "register_operand" "")
++                      (const_string "basr") (const_string "bas")))
+    (set_attr "type"  "jsr")
+    (set_attr "atype" "agen")
+    (set_attr "z196prop" "z196_cracked")])
+ 
++(define_insn "*basr_r_via_thunk_z10"
++  [(set (match_operand 0 "" "")
++        (call (mem:QI (match_operand 1 "register_operand" "a"))
++              (match_operand 2 "const_int_operand"        "n")))
++   (clobber (match_operand 3 "register_operand"         "=&r"))]
++  "TARGET_INDIRECT_BRANCH_NOBP_CALL
++   && TARGET_CPU_Z10
++   && !SIBLING_CALL_P (insn)
++   && GET_MODE (operands[3]) == Pmode"
++{
++  s390_indirect_branch_via_thunk (REGNO (operands[1]),
++				  REGNO (operands[3]),
++				  NULL_RTX,
++				  s390_indirect_branch_type_call);
++  return "";
++}
++  [(set_attr "op_type" "RIL")
++   (set_attr "mnemonic" "brasl")
++   (set_attr "type"  "jsr")
++   (set_attr "atype" "agen")
++   (set_attr "z196prop" "z196_cracked")])
++
++(define_insn "*basr_r_via_thunk"
++  [(set (match_operand 0 "" "")
++        (call (mem:QI (match_operand 1 "register_operand" "a"))
++              (match_operand 2 "const_int_operand"        "n")))
++   (clobber (match_operand 3 "register_operand"         "=&r"))
++   (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
++  "TARGET_INDIRECT_BRANCH_NOBP_CALL
++   && !TARGET_CPU_Z10
++   && !SIBLING_CALL_P (insn)
++   && GET_MODE (operands[3]) == Pmode"
++{
++  s390_indirect_branch_via_thunk (REGNO (operands[1]),
++				  REGNO (operands[3]),
++				  NULL_RTX,
++				  s390_indirect_branch_type_call);
++  return "";
++}
++  [(set_attr "op_type" "RIL")
++   (set_attr "mnemonic"  "brasl")
++   (set_attr "type"  "jsr")
++   (set_attr "atype" "agen")
++   (set_attr "z196prop" "z196_cracked")])
++
+ ;;
+ ;;- Thread-local storage support.
+ ;;
+@@ -10282,21 +10712,105 @@
+ (define_insn "<code>"
+   [(ANY_RETURN)]
+   "s390_can_use_<code>_insn ()"
+-  "br\t%%r14"
+-  [(set_attr "op_type" "RR")
++{
++  if (TARGET_INDIRECT_BRANCH_NOBP_RET)
++    {
++      /* The target is always r14 so there is no clobber
++	 of r1 needed for pre z10 targets.  */
++      s390_indirect_branch_via_thunk (RETURN_REGNUM,
++				      INVALID_REGNUM,
++				      NULL_RTX,
++				      s390_indirect_branch_type_return);
++      return "";
++    }
++  else
++    return "br\t%%r14";
++}
++  [(set (attr "op_type")
++	(if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
++		      (const_string "RIL")
++		      (const_string "RR")))
++   (set (attr "mnemonic")
++	(if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
++		      (const_string "jg")
++		      (const_string "br")))
+    (set_attr "type"    "jsr")
+    (set_attr "atype"   "agen")])
+ 
+-(define_insn "*return"
++
++(define_expand "return_use"
++  [(parallel
++    [(return)
++     (use (match_operand 0 "register_operand" "a"))])]
++  ""
++{
++  if (!TARGET_CPU_Z10
++      && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION)
++    {
++      if (TARGET_64BIT)
++        emit_jump_insn (gen_returndi_prez10 (operands[0]));
++      else
++        emit_jump_insn (gen_returnsi_prez10 (operands[0]));
++      DONE;
++    }
++})
++
++(define_insn "*return<mode>"
+   [(return)
+-   (use (match_operand 0 "register_operand" "a"))]
+-  "GET_MODE (operands[0]) == Pmode"
+-  "br\t%0"
+-  [(set_attr "op_type" "RR")
++   (use (match_operand:P 0 "register_operand" "a"))]
++  "TARGET_CPU_Z10 || !TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION"
++{
++  if (TARGET_INDIRECT_BRANCH_NOBP_RET)
++    {
++      s390_indirect_branch_via_thunk (REGNO (operands[0]),
++                                      INVALID_REGNUM,
++                                      NULL_RTX,
++                                      s390_indirect_branch_type_return);
++      return "";
++    }
++  else
++    return "br\t%0";
++}
++  [(set (attr "op_type")
++       (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
++                     (const_string "RIL")
++                     (const_string "RR")))
++   (set (attr "mnemonic")
++       (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
++                     (const_string "jg")
++                     (const_string "br")))
+    (set_attr "type"    "jsr")
+    (set_attr "atype"   "agen")])
+ 
++(define_insn "return<mode>_prez10"
++  [(return)
++   (use (match_operand:P 0 "register_operand" "a"))
++   (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
++  "!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION"
++{
++  if (TARGET_INDIRECT_BRANCH_NOBP_RET)
++    {
++      s390_indirect_branch_via_thunk (REGNO (operands[0]),
++                                      INVALID_REGNUM,
++                                      NULL_RTX,
++                                      s390_indirect_branch_type_return);
++      return "";
++    }
++  else
++    return "br\t%0";
++}
++  [(set (attr "op_type")
++       (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
++                     (const_string "RIL")
++                     (const_string "RR")))
++   (set (attr "mnemonic")
++       (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
++                     (const_string "jg")
++                     (const_string "br")))
++   (set_attr "type"    "jsr")
++   (set_attr "atype"   "agen")])
+ 
++
+ ;; Instruction definition to extend a 31-bit pointer into a 64-bit
+ ;; pointer. This is used for compatibility.
+ 
+Index: gcc/config/s390/s390.opt
+===================================================================
+--- a/src/gcc/config/s390/s390.opt	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/s390/s390.opt	(.../branches/gcc-6-branch)
+@@ -199,3 +199,62 @@
+ mlra
+ Target Report Var(s390_lra_flag) Init(1) Save
+ Use LRA instead of reload.
++
++mindirect-branch=
++Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch) Init(indirect_branch_keep)
++Wrap all indirect branches into execute in order to disable branch
++prediction.
++
++mindirect-branch-jump=
++Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_jump) Init(indirect_branch_keep)
++Wrap indirect table jumps and computed gotos into execute in order to
++disable branch prediction.  Using thunk or thunk-extern with this
++option requires the thunks to be considered signal handlers to order to
++generate correct CFI.  For environments where unwinding (e.g. for
++exceptions) is required please use thunk-inline instead.
++
++mindirect-branch-call=
++Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_call) Init(indirect_branch_keep)
++Wrap all indirect calls into execute in order to disable branch prediction.
++
++mfunction-return=
++Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_function_return) Init(indirect_branch_keep)
++Wrap all indirect return branches into execute in order to disable branch
++prediction.
++
++mfunction-return-mem=
++Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_mem) Init(indirect_branch_keep)
++Wrap indirect return branches into execute in order to disable branch
++prediction. This affects only branches where the return address is
++going to be restored from memory.
++
++mfunction-return-reg=
++Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_reg) Init(indirect_branch_keep)
++Wrap indirect return branches into execute in order to disable branch
++prediction. This affects only branches where the return address
++doesn't need to be restored from memory.
++
++Enum
++Name(indirect_branch) Type(enum indirect_branch)
++Known indirect branch choices (for use with the -mindirect-branch=/-mfunction-return= options):
++
++EnumValue
++Enum(indirect_branch) String(keep) Value(indirect_branch_keep)
++
++EnumValue
++Enum(indirect_branch) String(thunk) Value(indirect_branch_thunk)
++
++EnumValue
++Enum(indirect_branch) String(thunk-inline) Value(indirect_branch_thunk_inline)
++
++EnumValue
++Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern)
++
++mindirect-branch-table
++Target Report Var(s390_indirect_branch_table) Init(TARGET_DEFAULT_INDIRECT_BRANCH_TABLE)
++Generate sections .s390_indirect_jump, .s390_indirect_call,
++.s390_return_reg, and .s390_return_mem to contain the indirect branch
++locations which have been patched as part of using one of the
++-mindirect-branch* or -mfunction-return* options.  The sections
++consist of an array of 32 bit elements. Each entry holds the offset
++from the entry to the patched location.
+Index: gcc/config/s390/s390-opts.h
+===================================================================
+--- a/src/gcc/config/s390/s390-opts.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/s390/s390-opts.h	(.../branches/gcc-6-branch)
+@@ -42,4 +42,13 @@
+   PROCESSOR_max
+ };
+ 
++
++/* Values for -mindirect-branch and -mfunction-return options.  */
++enum indirect_branch {
++  indirect_branch_unset = 0,
++  indirect_branch_keep,
++  indirect_branch_thunk,
++  indirect_branch_thunk_inline,
++  indirect_branch_thunk_extern
++};
+ #endif
+Index: gcc/config/s390/s390-protos.h
+===================================================================
+--- a/src/gcc/config/s390/s390-protos.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/s390/s390-protos.h	(.../branches/gcc-6-branch)
+@@ -53,6 +53,7 @@
+ extern int s390_cannot_change_mode_class (machine_mode, machine_mode,
+ 					  enum reg_class);
+ extern bool s390_function_arg_vector (machine_mode, const_tree);
++extern bool s390_return_addr_from_memory(void);
+ #if S390_USE_TARGET_ATTRIBUTE
+ extern tree s390_valid_target_attribute_tree (tree args,
+ 					      struct gcc_options *opts,
+@@ -146,6 +147,17 @@
+ extern bool s390_extzv_shift_ok (int, int, unsigned HOST_WIDE_INT);
+ extern void s390_asm_output_function_label (FILE *, const char *, tree);
+ 
++enum s390_indirect_branch_type
++  {
++    s390_indirect_branch_type_jump = 0,
++    s390_indirect_branch_type_call,
++    s390_indirect_branch_type_return
++  };
++extern void s390_indirect_branch_via_thunk (unsigned int regno,
++					    unsigned int return_addr_regno,
++					    rtx comparison_operator,
++					    enum s390_indirect_branch_type type);
++extern void s390_indirect_branch_via_inline_thunk (rtx execute_target);
+ #endif /* RTX_CODE */
+ 
+ /* s390-c.c routines */
+Index: gcc/config/s390/s390.c
+===================================================================
+--- a/src/gcc/config/s390/s390.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/s390/s390.c	(.../branches/gcc-6-branch)
+@@ -372,84 +372,6 @@
+   bool literal_pool;
+ };
+ 
+-/* The following structure is embedded in the machine
+-   specific part of struct function.  */
+-
+-struct GTY (()) s390_frame_layout
+-{
+-  /* Offset within stack frame.  */
+-  HOST_WIDE_INT gprs_offset;
+-  HOST_WIDE_INT f0_offset;
+-  HOST_WIDE_INT f4_offset;
+-  HOST_WIDE_INT f8_offset;
+-  HOST_WIDE_INT backchain_offset;
+-
+-  /* Number of first and last gpr where slots in the register
+-     save area are reserved for.  */
+-  int first_save_gpr_slot;
+-  int last_save_gpr_slot;
+-
+-  /* Location (FP register number) where GPRs (r0-r15) should
+-     be saved to.
+-      0 - does not need to be saved at all
+-     -1 - stack slot  */
+-#define SAVE_SLOT_NONE   0
+-#define SAVE_SLOT_STACK -1
+-  signed char gpr_save_slots[16];
+-
+-  /* Number of first and last gpr to be saved, restored.  */
+-  int first_save_gpr;
+-  int first_restore_gpr;
+-  int last_save_gpr;
+-  int last_restore_gpr;
+-
+-  /* Bits standing for floating point registers. Set, if the
+-     respective register has to be saved. Starting with reg 16 (f0)
+-     at the rightmost bit.
+-     Bit 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+-     fpr 15 13 11  9 14 12 10  8  7  5  3  1  6  4  2  0
+-     reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16  */
+-  unsigned int fpr_bitmap;
+-
+-  /* Number of floating point registers f8-f15 which must be saved.  */
+-  int high_fprs;
+-
+-  /* Set if return address needs to be saved.
+-     This flag is set by s390_return_addr_rtx if it could not use
+-     the initial value of r14 and therefore depends on r14 saved
+-     to the stack.  */
+-  bool save_return_addr_p;
+-
+-  /* Size of stack frame.  */
+-  HOST_WIDE_INT frame_size;
+-};
+-
+-/* Define the structure for the machine field in struct function.  */
+-
+-struct GTY(()) machine_function
+-{
+-  struct s390_frame_layout frame_layout;
+-
+-  /* Literal pool base register.  */
+-  rtx base_reg;
+-
+-  /* True if we may need to perform branch splitting.  */
+-  bool split_branches_pending_p;
+-
+-  bool has_landing_pad_p;
+-
+-  /* True if the current function may contain a tbegin clobbering
+-     FPRs.  */
+-  bool tbegin_p;
+-
+-  /* For -fsplit-stack support: A stack local which holds a pointer to
+-     the stack arguments for a function with a variable number of
+-     arguments.  This is set at the start of the function and is used
+-     to initialize the overflow_arg_area field of the va_list
+-     structure.  */
+-  rtx split_stack_varargs_pointer;
+-};
+-
+ /* Few accessor macros for struct cfun->machine->s390_frame_layout.  */
+ 
+ #define cfun_frame_layout (cfun->machine->frame_layout)
+@@ -490,7 +412,34 @@
+    bytes on a z10 (or higher) CPU.  */
+ #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
+ 
++/* Masks per jump target register indicating which thunk need to be
++   generated.  */
++static GTY(()) int indirect_branch_prez10thunk_mask = 0;
++static GTY(()) int indirect_branch_z10thunk_mask = 0;
+ 
++#define INDIRECT_BRANCH_NUM_OPTIONS 4
++
++enum s390_indirect_branch_option
++  {
++    s390_opt_indirect_branch_jump = 0,
++    s390_opt_indirect_branch_call,
++    s390_opt_function_return_reg,
++    s390_opt_function_return_mem
++  };
++
++static GTY(()) int indirect_branch_table_label_no[INDIRECT_BRANCH_NUM_OPTIONS] = { 0 };
++const char *indirect_branch_table_label[INDIRECT_BRANCH_NUM_OPTIONS] = \
++  { "LJUMP", "LCALL", "LRETREG", "LRETMEM" };
++const char *indirect_branch_table_name[INDIRECT_BRANCH_NUM_OPTIONS] =	\
++  { ".s390_indirect_jump", ".s390_indirect_call",
++    ".s390_return_reg", ".s390_return_mem" };
++
++bool
++s390_return_addr_from_memory ()
++{
++  return cfun_gpr_save_slot(RETURN_REGNUM) == SAVE_SLOT_STACK;
++}
++
+ /* Indicate which ABI has been used for passing vector args.
+    0 - no vector type arguments have been passed where the ABI is relevant
+    1 - the old ABI has been used
+@@ -1124,9 +1073,83 @@
+   return NULL_TREE;
+ }
+ 
++/* Check syntax of function decl attributes having a string type value.  */
++
++static tree
++s390_handle_string_attribute (tree *node, tree name ATTRIBUTE_UNUSED,
++			      tree args ATTRIBUTE_UNUSED,
++			      int flags ATTRIBUTE_UNUSED,
++			      bool *no_add_attrs)
++{
++  tree cst;
++
++  if (TREE_CODE (*node) != FUNCTION_DECL)
++    {
++      warning (OPT_Wattributes, "%qE attribute only applies to functions",
++	       name);
++      *no_add_attrs = true;
++    }
++
++  cst = TREE_VALUE (args);
++
++  if (TREE_CODE (cst) != STRING_CST)
++    {
++      warning (OPT_Wattributes,
++	       "%qE attribute requires a string constant argument",
++	       name);
++      *no_add_attrs = true;
++    }
++
++  if (is_attribute_p ("indirect_branch", name)
++      || is_attribute_p ("indirect_branch_call", name)
++      || is_attribute_p ("function_return", name)
++      || is_attribute_p ("function_return_reg", name)
++      || is_attribute_p ("function_return_mem", name))
++    {
++      if (strcmp (TREE_STRING_POINTER (cst), "keep") != 0
++	  && strcmp (TREE_STRING_POINTER (cst), "thunk") != 0
++	  && strcmp (TREE_STRING_POINTER (cst), "thunk-extern") != 0)
++      {
++	warning (OPT_Wattributes,
++		 "argument to %qE attribute is not "
++		 "(keep|thunk|thunk-extern)", name);
++	*no_add_attrs = true;
++      }
++    }
++
++  if (is_attribute_p ("indirect_branch_jump", name)
++      && strcmp (TREE_STRING_POINTER (cst), "keep") != 0
++      && strcmp (TREE_STRING_POINTER (cst), "thunk") != 0
++      && strcmp (TREE_STRING_POINTER (cst), "thunk-inline") != 0
++      && strcmp (TREE_STRING_POINTER (cst), "thunk-extern") != 0)
++    {
++      warning (OPT_Wattributes,
++	       "argument to %qE attribute is not "
++	       "(keep|thunk|thunk-inline|thunk-extern)", name);
++      *no_add_attrs = true;
++    }
++
++  return NULL_TREE;
++}
++
+ static const struct attribute_spec s390_attribute_table[] = {
+-  { "hotpatch", 2, 2, true, false, false, s390_handle_hotpatch_attribute, false },
+-  { "s390_vector_bool", 0, 0, false, true, false, s390_handle_vectorbool_attribute, true },
++  { "hotpatch", 2, 2, true, false, false,
++    s390_handle_hotpatch_attribute, false },
++  { "s390_vector_bool", 0, 0, false, true, false,
++    s390_handle_vectorbool_attribute, true },
++  { "indirect_branch", 1, 1, true, false, false,
++    s390_handle_string_attribute, false },
++  { "indirect_branch_jump", 1, 1, true, false, false,
++    s390_handle_string_attribute, false },
++  { "indirect_branch_call", 1, 1, true, false, false,
++    s390_handle_string_attribute, false },
++  { "function_return", 1, 1, true, false, false,
++    s390_handle_string_attribute, false },
++  { "function_return_reg", 1, 1, true, false, false,
++    s390_handle_string_attribute, false },
++  { "function_return_mem", 1, 1, true, false, false,
++    s390_handle_string_attribute, false },
++
+   /* End element.  */
+   { NULL,        0, 0, false, false, false, NULL, false }
+ };
+@@ -8266,11 +8289,25 @@
+ static rtx
+ s390_execute_label (rtx insn)
+ {
+-  if (NONJUMP_INSN_P (insn)
++  if (INSN_P (insn)
+       && GET_CODE (PATTERN (insn)) == PARALLEL
+       && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
+-      && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
+-    return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
++      && (XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE
++	  || XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE_JUMP))
++    {
++      if (XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
++	return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
++      else
++	{
++	  gcc_assert (JUMP_P (insn));
++	  /* For jump insns as execute target:
++	     - There is one operand less in the parallel (the
++	       modification register of the execute is always 0).
++	     - The execute target label is wrapped into an
++	       if_then_else in order to hide it from jump analysis.  */
++	  return XEXP (XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 0), 0);
++	}
++    }
+ 
+   return NULL_RTX;
+ }
+@@ -10942,7 +10979,6 @@
+   rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
+   int area_bottom, area_top, offset = 0;
+   int next_offset;
+-  rtvec p;
+   int i;
+ 
+   if (TARGET_TPF_PROFILING)
+@@ -11096,10 +11132,15 @@
+ 	  if (cfun_gpr_save_slot (RETURN_REGNUM) == SAVE_SLOT_STACK)
+ 	    {
+ 	      int return_regnum = find_unused_clobbered_reg();
+-	      if (!return_regnum)
+-		return_regnum = 4;
++	      if (!return_regnum
++		  || (TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION
++		      && !TARGET_CPU_Z10
++		      && return_regnum == INDIRECT_BRANCH_THUNK_REGNUM))
++		{
++		  gcc_assert (INDIRECT_BRANCH_THUNK_REGNUM != 4);
++		  return_regnum = 4;
++		}
+ 	      return_reg = gen_rtx_REG (Pmode, return_regnum);
+-
+ 	      addr = plus_constant (Pmode, frame_pointer,
+ 				    offset + cfun_frame_layout.gprs_offset
+ 				    + (RETURN_REGNUM
+@@ -11135,16 +11176,7 @@
+   s390_restore_gprs_from_fprs ();
+ 
+   if (! sibcall)
+-    {
+-
+-      /* Return to caller.  */
+-
+-      p = rtvec_alloc (2);
+-
+-      RTVEC_ELT (p, 0) = ret_rtx;
+-      RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
+-      emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
+-    }
++    emit_jump_insn (gen_return_use (return_reg));
+ }
+ 
+ /* Implement TARGET_SET_UP_BY_PROLOGUE.  */
+@@ -12722,6 +12754,112 @@
+   final_end_function ();
+ }
+ 
++/* Output either an indirect jump or a an indirect call
++   (RETURN_ADDR_REGNO != INVALID_REGNUM) with target register REGNO
++   using a branch trampoline disabling branch target prediction.  */
++
++void
++s390_indirect_branch_via_thunk (unsigned int regno,
++				unsigned int return_addr_regno,
++				rtx comparison_operator,
++				enum s390_indirect_branch_type type)
++{
++  enum s390_indirect_branch_option option;
++
++  if (type == s390_indirect_branch_type_return)
++    {
++      if (s390_return_addr_from_memory ())
++	option = s390_opt_function_return_mem;
++      else
++	option = s390_opt_function_return_reg;
++    }
++  else if (type == s390_indirect_branch_type_jump)
++    option = s390_opt_indirect_branch_jump;
++  else if (type == s390_indirect_branch_type_call)
++    option = s390_opt_indirect_branch_call;
++  else
++    gcc_unreachable ();
++
++  if (TARGET_INDIRECT_BRANCH_TABLE)
++    {
++      char label[32];
++
++      ASM_GENERATE_INTERNAL_LABEL (label,
++				   indirect_branch_table_label[option],
++				   indirect_branch_table_label_no[option]++);
++      ASM_OUTPUT_LABEL (asm_out_file, label);
++    }
++
++  if (return_addr_regno != INVALID_REGNUM)
++    {
++      gcc_assert (comparison_operator == NULL_RTX);
++      fprintf (asm_out_file, " \tbrasl\t%%r%d,", return_addr_regno);
++    }
++  else
++    {
++      fputs (" \tjg", asm_out_file);
++      if (comparison_operator != NULL_RTX)
++	print_operand (asm_out_file, comparison_operator, 'C');
++
++      fputs ("\t", asm_out_file);
++    }
++
++  if (TARGET_CPU_Z10)
++    fprintf (asm_out_file,
++	     TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL "\n",
++	     regno);
++  else
++    fprintf (asm_out_file,
++	     TARGET_INDIRECT_BRANCH_THUNK_NAME_EX "\n",
++	     INDIRECT_BRANCH_THUNK_REGNUM, regno);
++
++  if ((option == s390_opt_indirect_branch_jump
++       && cfun->machine->indirect_branch_jump == indirect_branch_thunk)
++      || (option == s390_opt_indirect_branch_call
++	  && cfun->machine->indirect_branch_call == indirect_branch_thunk)
++      || (option == s390_opt_function_return_reg
++	  && cfun->machine->function_return_reg == indirect_branch_thunk)
++      || (option == s390_opt_function_return_mem
++	  && cfun->machine->function_return_mem == indirect_branch_thunk))
++    {
++      if (TARGET_CPU_Z10)
++	indirect_branch_z10thunk_mask |= (1 << regno);
++      else
++	indirect_branch_prez10thunk_mask |= (1 << regno);
++    }
++}
++
++/* Output an inline thunk for indirect jumps.  EXECUTE_TARGET can
++   either be an address register or a label pointing to the location
++   of the jump instruction.  */
++
++void
++s390_indirect_branch_via_inline_thunk (rtx execute_target)
++{
++  if (TARGET_INDIRECT_BRANCH_TABLE)
++    {
++      char label[32];
++
++      ASM_GENERATE_INTERNAL_LABEL (label,
++				   indirect_branch_table_label[s390_opt_indirect_branch_jump],
++				   indirect_branch_table_label_no[s390_opt_indirect_branch_jump]++);
++      ASM_OUTPUT_LABEL (asm_out_file, label);
++    }
++
++  if (!TARGET_ZARCH)
++    fputs ("\t.machinemode zarch\n", asm_out_file);
++
++  if (REG_P (execute_target))
++    fprintf (asm_out_file, "\tex\t%%r0,0(%%r%d)\n", REGNO (execute_target));
++  else
++    output_asm_insn ("exrl\t%%r0,%0", &execute_target);
++
++  if (!TARGET_ZARCH)
++    fputs ("\t.machinemode esa\n", asm_out_file);
++
++  fputs ("0:\tj\t0b\n", asm_out_file);
++}
++
+ static bool
+ s390_valid_pointer_mode (machine_mode mode)
+ {
+@@ -12827,6 +12965,14 @@
+   if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
+     return false;
+ 
++  /* The thunks for indirect branches require r1 if no exrl is
++     available.  r1 might not be available when doing a sibling
++     call.  */
++  if (TARGET_INDIRECT_BRANCH_NOBP_CALL
++      && !TARGET_CPU_Z10
++      && !decl)
++    return false;
++
+   /* Register 6 on s390 is available as an argument register but unfortunately
+      "caller saved". This makes functions needing this register for arguments
+      not suitable for sibcalls.  */
+@@ -12860,9 +13006,13 @@
+ {
+   bool plt_call = false;
+   rtx_insn *insn;
+-  rtx call;
+-  rtx clobber;
+-  rtvec vec;
++  rtx vec[4] = { NULL_RTX };
++  int elts = 0;
++  rtx *call = &vec[0];
++  rtx *clobber_ret_reg = &vec[1];
++  rtx *use = &vec[2];
++  rtx *clobber_thunk_reg = &vec[3];
++  int i;
+ 
+   /* Direct function calls need special treatment.  */
+   if (GET_CODE (addr_location) == SYMBOL_REF)
+@@ -12914,26 +13064,58 @@
+       addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
+     }
+ 
++  if (TARGET_INDIRECT_BRANCH_NOBP_CALL
++      && GET_CODE (addr_location) != SYMBOL_REF
++      && !plt_call)
++    {
++      /* Indirect branch thunks require the target to be a single GPR.  */
++      addr_location = force_reg (Pmode, addr_location);
++
++      /* Without exrl the indirect branch thunks need an additional
++	 register for larl;ex */
++      if (!TARGET_CPU_Z10)
++	{
++	  *clobber_thunk_reg = gen_rtx_REG (Pmode, INDIRECT_BRANCH_THUNK_REGNUM);
++	  *clobber_thunk_reg = gen_rtx_CLOBBER (VOIDmode, *clobber_thunk_reg);
++	}
++    }
++
+   addr_location = gen_rtx_MEM (QImode, addr_location);
+-  call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
++  *call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
+ 
+   if (result_reg != NULL_RTX)
+-    call = gen_rtx_SET (result_reg, call);
++    *call = gen_rtx_SET (result_reg, *call);
+ 
+   if (retaddr_reg != NULL_RTX)
+     {
+-      clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
++      *clobber_ret_reg = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
+ 
+       if (tls_call != NULL_RTX)
+-	vec = gen_rtvec (3, call, clobber,
+-			 gen_rtx_USE (VOIDmode, tls_call));
+-      else
+-	vec = gen_rtvec (2, call, clobber);
++	*use = gen_rtx_USE (VOIDmode, tls_call);
++    }
+ 
+-      call = gen_rtx_PARALLEL (VOIDmode, vec);
++
++  for (i = 0; i < 4; i++)
++    if (vec[i] != NULL_RTX)
++      elts++;
++
++  if (elts > 1)
++    {
++      rtvec v;
++      int e = 0;
++
++      v = rtvec_alloc (elts);
++      for (i = 0; i < 4; i++)
++	if (vec[i] != NULL_RTX)
++	  {
++	    RTVEC_ELT (v, e) = vec[i];
++	    e++;
++	  }
++
++      *call = gen_rtx_PARALLEL (VOIDmode, v);
+     }
+ 
+-  insn = emit_call_insn (call);
++  insn = emit_call_insn (*call);
+ 
+   /* 31-bit PLT stubs and tls calls use the GOT register implicitly.  */
+   if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
+@@ -13563,7 +13745,16 @@
+ 	  target = emit_label (XEXP (label, 0));
+ 	  INSN_ADDRESSES_NEW (target, -1);
+ 
+-	  target = emit_insn (s390_execute_target (insn));
++	  if (JUMP_P (insn))
++	    {
++	      target = emit_jump_insn (s390_execute_target (insn));
++	      /* This is important in order to keep a table jump
++		 pointing at the jump table label.  Only this makes it
++		 being recognized as table jump.  */
++	      JUMP_LABEL (target) = JUMP_LABEL (insn);
++	    }
++	  else
++	    target = emit_insn (s390_execute_target (insn));
+ 	  INSN_ADDRESSES_NEW (target, -1);
+ 	}
+     }
+@@ -14213,6 +14404,42 @@
+   if (TARGET_64BIT && !TARGET_ZARCH_P (opts->x_target_flags))
+     error ("64-bit ABI not supported in ESA/390 mode");
+ 
++  if (opts->x_s390_indirect_branch == indirect_branch_thunk_inline
++      || opts->x_s390_indirect_branch_call == indirect_branch_thunk_inline
++      || opts->x_s390_function_return == indirect_branch_thunk_inline
++      || opts->x_s390_function_return_reg == indirect_branch_thunk_inline
++      || opts->x_s390_function_return_mem == indirect_branch_thunk_inline)
++    error ("thunk-inline is only supported with -mindirect-branch-jump");
++
++  if (opts->x_s390_indirect_branch != indirect_branch_keep)
++    {
++      if (!opts_set->x_s390_indirect_branch_call)
++	opts->x_s390_indirect_branch_call = opts->x_s390_indirect_branch;
++
++      if (!opts_set->x_s390_indirect_branch_jump)
++	opts->x_s390_indirect_branch_jump = opts->x_s390_indirect_branch;
++    }
++
++  if (opts->x_s390_function_return != indirect_branch_keep)
++    {
++      if (!opts_set->x_s390_function_return_reg)
++	opts->x_s390_function_return_reg = opts->x_s390_function_return;
++
++      if (!opts_set->x_s390_function_return_mem)
++	opts->x_s390_function_return_mem = opts->x_s390_function_return;
++    }
++
++  if (!TARGET_CPU_ZARCH)
++    {
++      if (opts->x_s390_indirect_branch_call != indirect_branch_keep
++	  || opts->x_s390_indirect_branch_jump != indirect_branch_keep)
++	error ("-mindirect-branch* options require -march=z900 or higher");
++      if (opts->x_s390_function_return_reg != indirect_branch_keep
++	  || opts->x_s390_function_return_mem != indirect_branch_keep)
++	error ("-mfunction-return* options require -march=z900 or higher");
++    }
++
++
+   /* Enable hardware transactions if available and not explicitly
+      disabled by user.  E.g. with -m31 -march=zEC12 -mzarch */
+   if (!TARGET_OPT_HTM_P (opts_set->x_target_flags))
+@@ -14777,6 +15004,79 @@
+   return ret;
+ }
+ 
++/* Set VAL to correct enum value according to the indirect-branch or
++   function-return attribute in ATTR.  */
++
++static inline void
++s390_indirect_branch_attrvalue (tree attr, enum indirect_branch *val)
++{
++  const char *str = TREE_STRING_POINTER (TREE_VALUE (TREE_VALUE (attr)));
++  if (strcmp (str, "keep") == 0)
++    *val = indirect_branch_keep;
++  else if (strcmp (str, "thunk") == 0)
++    *val = indirect_branch_thunk;
++  else if (strcmp (str, "thunk-inline") == 0)
++    *val = indirect_branch_thunk_inline;
++  else if (strcmp (str, "thunk-extern") == 0)
++    *val = indirect_branch_thunk_extern;
++}
++
++/* Memorize the setting for -mindirect-branch* and -mfunction-return*
++   from either the cmdline or the function attributes in
++   cfun->machine.  */
++
++static void
++s390_indirect_branch_settings (tree fndecl)
++{
++  tree attr;
++
++  if (!fndecl)
++    return;
++
++  /* Initialize with the cmdline options and let the attributes
++     override it.  */
++  cfun->machine->indirect_branch_jump = s390_indirect_branch_jump;
++  cfun->machine->indirect_branch_call = s390_indirect_branch_call;
++
++  cfun->machine->function_return_reg = s390_function_return_reg;
++  cfun->machine->function_return_mem = s390_function_return_mem;
++
++  if ((attr = lookup_attribute ("indirect_branch",
++				DECL_ATTRIBUTES (fndecl))))
++    {
++      s390_indirect_branch_attrvalue (attr,
++				      &cfun->machine->indirect_branch_jump);
++      s390_indirect_branch_attrvalue (attr,
++				      &cfun->machine->indirect_branch_call);
++    }
++
++  if ((attr = lookup_attribute ("indirect_branch_jump",
++				DECL_ATTRIBUTES (fndecl))))
++    s390_indirect_branch_attrvalue (attr, &cfun->machine->indirect_branch_jump);
++
++  if ((attr = lookup_attribute ("indirect_branch_call",
++				DECL_ATTRIBUTES (fndecl))))
++    s390_indirect_branch_attrvalue (attr, &cfun->machine->indirect_branch_call);
++
++  if ((attr = lookup_attribute ("function_return",
++				DECL_ATTRIBUTES (fndecl))))
++    {
++      s390_indirect_branch_attrvalue (attr,
++				      &cfun->machine->function_return_reg);
++      s390_indirect_branch_attrvalue (attr,
++				      &cfun->machine->function_return_mem);
++    }
++
++  if ((attr = lookup_attribute ("function_return_reg",
++				DECL_ATTRIBUTES (fndecl))))
++    s390_indirect_branch_attrvalue (attr, &cfun->machine->function_return_reg);
++
++  if ((attr = lookup_attribute ("function_return_mem",
++				DECL_ATTRIBUTES (fndecl))))
++    s390_indirect_branch_attrvalue (attr, &cfun->machine->function_return_mem);
++}
++
++
+ /* Restore targets globals from NEW_TREE and invalidate s390_previous_fndecl
+    cache.  */
+ 
+@@ -14803,7 +15103,10 @@
+      several times in the course of compiling a function, and we don't want to
+      slow things down too much or call target_reinit when it isn't safe.  */
+   if (fndecl == s390_previous_fndecl)
+-    return;
++    {
++      s390_indirect_branch_settings (fndecl);
++      return;
++    }
+ 
+   tree old_tree;
+   if (s390_previous_fndecl == NULL_TREE)
+@@ -14827,6 +15130,8 @@
+   if (old_tree != new_tree)
+     s390_activate_target_options (new_tree);
+   s390_previous_fndecl = fndecl;
++
++  s390_indirect_branch_settings (fndecl);
+ }
+ #endif
+ 
+@@ -15062,6 +15367,186 @@
+   return NULL;
+ }
+ 
++#ifdef HAVE_GAS_HIDDEN
++# define USE_HIDDEN_LINKONCE 1
++#else
++# define USE_HIDDEN_LINKONCE 0
++#endif
++
++/* Output an indirect branch trampoline for target register REGNO.  */
++
++static void
++s390_output_indirect_thunk_function (unsigned int regno, bool z10_p)
++{
++  tree decl;
++  char thunk_label[32];
++  int i;
++
++  if (z10_p)
++    sprintf (thunk_label, TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL, regno);
++  else
++    sprintf (thunk_label, TARGET_INDIRECT_BRANCH_THUNK_NAME_EX,
++	     INDIRECT_BRANCH_THUNK_REGNUM, regno);
++
++  decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
++		     get_identifier (thunk_label),
++		     build_function_type_list (void_type_node, NULL_TREE));
++  DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
++				   NULL_TREE, void_type_node);
++  TREE_PUBLIC (decl) = 1;
++  TREE_STATIC (decl) = 1;
++  DECL_IGNORED_P (decl) = 1;
++
++  if (USE_HIDDEN_LINKONCE)
++    {
++      cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
++
++      targetm.asm_out.unique_section (decl, 0);
++      switch_to_section (get_named_section (decl, NULL, 0));
++
++      targetm.asm_out.globalize_label (asm_out_file, thunk_label);
++      fputs ("\t.hidden\t", asm_out_file);
++      assemble_name (asm_out_file, thunk_label);
++      putc ('\n', asm_out_file);
++      ASM_DECLARE_FUNCTION_NAME (asm_out_file, thunk_label, decl);
++    }
++  else
++    {
++      switch_to_section (text_section);
++      ASM_OUTPUT_LABEL (asm_out_file, thunk_label);
++    }
++
++  DECL_INITIAL (decl) = make_node (BLOCK);
++  current_function_decl = decl;
++  allocate_struct_function (decl, false);
++  init_function_start (decl);
++  cfun->is_thunk = true;
++  first_function_block_is_cold = false;
++  final_start_function (emit_barrier (), asm_out_file, 1);
++
++  /* This makes CFI at least usable for indirect jumps.
++
++     Stopping in the thunk: backtrace will point to the thunk target
++     is if it was interrupted by a signal.  For a call this means that
++     the call chain will be: caller->callee->thunk   */
++  if (flag_asynchronous_unwind_tables)
++    {
++      fputs ("\t.cfi_signal_frame\n", asm_out_file);
++      fprintf (asm_out_file, "\t.cfi_return_column %d\n", regno);
++      for (i = 0; i < FPR15_REGNUM; i++)
++	fprintf (asm_out_file, "\t.cfi_same_value %s\n", reg_names[i]);
++    }
++
++  if (z10_p)
++    {
++      /* exrl  0,1f  */
++
++      /* We generate a thunk for z10 compiled code although z10 is
++	 currently not enabled.  Tell the assembler to accept the
++	 instruction.  */
++      if (!TARGET_CPU_Z10)
++	{
++	  fputs ("\t.machine push\n", asm_out_file);
++	  fputs ("\t.machine z10\n", asm_out_file);
++	}
++      /* We use exrl even if -mzarch hasn't been specified on the
++	 command line so we have to tell the assembler to accept
++	 it.  */
++      if (!TARGET_ZARCH)
++	fputs ("\t.machinemode zarch\n", asm_out_file);
++
++      fputs ("\texrl\t0,1f\n", asm_out_file);
++
++      if (!TARGET_ZARCH)
++	fputs ("\t.machinemode esa\n", asm_out_file);
++
++      if (!TARGET_CPU_Z10)
++	fputs ("\t.machine pop\n", asm_out_file);
++    }
++  else if (TARGET_CPU_ZARCH)
++    {
++      /* larl %r1,1f  */
++      fprintf (asm_out_file, "\tlarl\t%%r%d,1f\n",
++	       INDIRECT_BRANCH_THUNK_REGNUM);
++
++      /* ex 0,0(%r1)  */
++      fprintf (asm_out_file, "\tex\t0,0(%%r%d)\n",
++	       INDIRECT_BRANCH_THUNK_REGNUM);
++    }
++  else
++    gcc_unreachable ();
++
++  /* 0:    j 0b  */
++  fputs ("0:\tj\t0b\n", asm_out_file);
++
++  /* 1:    br <regno>  */
++  fprintf (asm_out_file, "1:\tbr\t%%r%d\n", regno);
++
++  final_end_function ();
++  init_insn_lengths ();
++  free_after_compilation (cfun);
++  set_cfun (NULL);
++  current_function_decl = NULL;
++}
++
++/* Implement the asm.code_end target hook.  */
++
++static void
++s390_code_end (void)
++{
++  int i;
++
++  for (i = 1; i < 16; i++)
++    {
++      if (indirect_branch_z10thunk_mask & (1 << i))
++	s390_output_indirect_thunk_function (i, true);
++
++      if (indirect_branch_prez10thunk_mask & (1 << i))
++	s390_output_indirect_thunk_function (i, false);
++    }
++
++  if (TARGET_INDIRECT_BRANCH_TABLE)
++    {
++      int o;
++      int i;
++
++      for (o = 0; o < INDIRECT_BRANCH_NUM_OPTIONS; o++)
++	{
++	  if (indirect_branch_table_label_no[o] == 0)
++	    continue;
++
++	  switch_to_section (get_section (indirect_branch_table_name[o],
++					  0,
++					  NULL_TREE));
++	  for (i = 0; i < indirect_branch_table_label_no[o]; i++)
++	    {
++	      char label_start[32];
++
++	      ASM_GENERATE_INTERNAL_LABEL (label_start,
++					   indirect_branch_table_label[o], i);
++
++	      fputs ("\t.long\t", asm_out_file);
++	      assemble_name_raw (asm_out_file, label_start);
++	      fputs ("-.\n", asm_out_file);
++	    }
++	  switch_to_section (current_function_section ());
++	}
++    }
++}
++
++/* Implement the TARGET_CASE_VALUES_THRESHOLD target hook.  */
++
++unsigned int
++s390_case_values_threshold (void)
++{
++  /* Disabling branch prediction for indirect jumps makes jump tables
++     much more expensive.  */
++  if (TARGET_INDIRECT_BRANCH_NOBP_JUMP)
++    return 20;
++
++  return default_case_values_threshold ();
++}
++
+ /* Initialize GCC target structure.  */
+ 
+ #undef  TARGET_ASM_ALIGNED_HI_OP
+@@ -15301,6 +15786,12 @@
+ #undef TARGET_OPTION_RESTORE
+ #define TARGET_OPTION_RESTORE s390_function_specific_restore
+ 
++#undef TARGET_ASM_CODE_END
++#define TARGET_ASM_CODE_END s390_code_end
++
++#undef TARGET_CASE_VALUES_THRESHOLD
++#define TARGET_CASE_VALUES_THRESHOLD s390_case_values_threshold
++
+ struct gcc_target targetm = TARGET_INITIALIZER;
+ 
+ #include "gt-s390.h"
+Index: gcc/config/s390/s390.h
+===================================================================
+--- a/src/gcc/config/s390/s390.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/s390/s390.h	(.../branches/gcc-6-branch)
+@@ -1094,4 +1094,124 @@
+     s390_register_target_pragmas ();		\
+   } while (0)
+ 
++#ifndef USED_FOR_TARGET
++/* The following structure is embedded in the machine
++   specific part of struct function.  */
++
++struct GTY (()) s390_frame_layout
++{
++  /* Offset within stack frame.  */
++  HOST_WIDE_INT gprs_offset;
++  HOST_WIDE_INT f0_offset;
++  HOST_WIDE_INT f4_offset;
++  HOST_WIDE_INT f8_offset;
++  HOST_WIDE_INT backchain_offset;
++
++  /* Number of first and last gpr where slots in the register
++     save area are reserved for.  */
++  int first_save_gpr_slot;
++  int last_save_gpr_slot;
++
++  /* Location (FP register number) where GPRs (r0-r15) should
++     be saved to.
++      0 - does not need to be saved at all
++     -1 - stack slot  */
++#define SAVE_SLOT_NONE   0
++#define SAVE_SLOT_STACK -1
++  signed char gpr_save_slots[16];
++
++  /* Number of first and last gpr to be saved, restored.  */
++  int first_save_gpr;
++  int first_restore_gpr;
++  int last_save_gpr;
++  int last_restore_gpr;
++
++  /* Bits standing for floating point registers. Set, if the
++     respective register has to be saved. Starting with reg 16 (f0)
++     at the rightmost bit.
++     Bit 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
++     fpr 15 13 11  9 14 12 10  8  7  5  3  1  6  4  2  0
++     reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16  */
++  unsigned int fpr_bitmap;
++
++  /* Number of floating point registers f8-f15 which must be saved.  */
++  int high_fprs;
++
++  /* Set if return address needs to be saved.
++     This flag is set by s390_return_addr_rtx if it could not use
++     the initial value of r14 and therefore depends on r14 saved
++     to the stack.  */
++  bool save_return_addr_p;
++
++  /* Size of stack frame.  */
++  HOST_WIDE_INT frame_size;
++};
++
++
++/* Define the structure for the machine field in struct function.  */
++
++struct GTY(()) machine_function
++{
++  struct s390_frame_layout frame_layout;
++
++  /* Literal pool base register.  */
++  rtx base_reg;
++
++  /* True if we may need to perform branch splitting.  */
++  bool split_branches_pending_p;
++
++  bool has_landing_pad_p;
++
++  /* True if the current function may contain a tbegin clobbering
++     FPRs.  */
++  bool tbegin_p;
++
++  /* For -fsplit-stack support: A stack local which holds a pointer to
++     the stack arguments for a function with a variable number of
++     arguments.  This is set at the start of the function and is used
++     to initialize the overflow_arg_area field of the va_list
++     structure.  */
++  rtx split_stack_varargs_pointer;
++
++  enum indirect_branch indirect_branch_jump;
++  enum indirect_branch indirect_branch_call;
++
++  enum indirect_branch function_return_mem;
++  enum indirect_branch function_return_reg;
++};
++#endif
++
++#define TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION				\
++  (cfun->machine->function_return_reg != indirect_branch_keep		\
++   || cfun->machine->function_return_mem != indirect_branch_keep)
++
++#define TARGET_INDIRECT_BRANCH_NOBP_RET					\
++  ((cfun->machine->function_return_reg != indirect_branch_keep		\
++    && !s390_return_addr_from_memory ())				\
++   || (cfun->machine->function_return_mem != indirect_branch_keep	\
++       && s390_return_addr_from_memory ()))
++
++#define TARGET_INDIRECT_BRANCH_NOBP_JUMP				\
++  (cfun->machine->indirect_branch_jump != indirect_branch_keep)
++
++#define TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK				\
++  (cfun->machine->indirect_branch_jump == indirect_branch_thunk		\
++   || cfun->machine->indirect_branch_jump == indirect_branch_thunk_extern)
++
++#define TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK			\
++  (cfun->machine->indirect_branch_jump == indirect_branch_thunk_inline)
++
++#define TARGET_INDIRECT_BRANCH_NOBP_CALL			\
++  (cfun->machine->indirect_branch_call != indirect_branch_keep)
++
++#ifndef TARGET_DEFAULT_INDIRECT_BRANCH_TABLE
++#define TARGET_DEFAULT_INDIRECT_BRANCH_TABLE 0
++#endif
++
++#define TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL "__s390_indirect_jump_r%d"
++#define TARGET_INDIRECT_BRANCH_THUNK_NAME_EX   "__s390_indirect_jump_r%duse_r%d"
++
++#define TARGET_INDIRECT_BRANCH_TABLE s390_indirect_branch_table
++
++
+ #endif /* S390_H */
+Index: gcc/config/sparc/sparc.c
+===================================================================
+--- a/src/gcc/config/sparc/sparc.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/sparc/sparc.c	(.../branches/gcc-6-branch)
+@@ -969,7 +969,8 @@
+ 	       && NONJUMP_INSN_P (insn)
+ 	       && (set = single_set (insn)) != NULL_RTX
+ 	       && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) <= 4
+-	       && mem_ref (SET_SRC (set)) != NULL_RTX
++	       && (mem_ref (SET_SRC (set)) != NULL_RTX
++		   || INSN_CODE (insn) == CODE_FOR_movsi_pic_gotdata_op)
+ 	       && REG_P (SET_DEST (set))
+ 	       && REGNO (SET_DEST (set)) < 32)
+ 	{
+@@ -1007,6 +1008,11 @@
+ 			       && REGNO (src) != REGNO (x)))
+ 		       && !reg_mentioned_p (x, XEXP (dest, 0)))
+ 		insert_nop = true;
++
++	      /* GOT accesses uses LD.  */
++	      else if (INSN_CODE (next) == CODE_FOR_movsi_pic_gotdata_op
++		       && !reg_mentioned_p (x, XEXP (XEXP (src, 0), 1)))
++		insert_nop = true;
+ 	    }
+ 	}
+ 
+Index: gcc/config/i386/i386.h
+===================================================================
+--- a/src/gcc/config/i386/i386.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/i386/i386.h	(.../branches/gcc-6-branch)
+@@ -501,6 +501,8 @@
+ 	ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]
+ #define TARGET_ONE_IF_CONV_INSN \
+ 	ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN]
++#define TARGET_EMIT_VZEROUPPER \
++	ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER]
+ 
+ /* Feature tests against the various architecture variations.  */
+ enum ix86_arch_indices {
+@@ -1124,6 +1126,9 @@
+    || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \
+    || (MODE) == V4TImode)
+ 
++#define VALID_AVX512F_REG_OR_XI_MODE(MODE)				\
++  (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode)
++
+ #define VALID_AVX512VL_128_REG_MODE(MODE)				\
+   ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode	\
+    || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode)
+Index: gcc/config/i386/i386.md
+===================================================================
+--- a/src/gcc/config/i386/i386.md	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/i386/i386.md	(.../branches/gcc-6-branch)
+@@ -5393,7 +5393,7 @@
+ (define_expand "floatunsdisf2"
+   [(use (match_operand:SF 0 "register_operand"))
+    (use (match_operand:DI 1 "nonimmediate_operand"))]
+-  "TARGET_64BIT && TARGET_SSE_MATH"
++  "TARGET_64BIT && TARGET_SSE && TARGET_SSE_MATH"
+   "x86_emit_floatuns (operands); DONE;")
+ 
+ (define_expand "floatunsdidf2"
+@@ -7415,21 +7415,15 @@
+ 		(match_operand:XF 2 "register_operand")))]
+   "TARGET_80387")
+ 
+-(define_expand "divdf3"
+-  [(set (match_operand:DF 0 "register_operand")
+- 	(div:DF (match_operand:DF 1 "register_operand")
+- 		(match_operand:DF 2 "nonimmediate_operand")))]
+-   "(TARGET_80387 && X87_ENABLE_ARITH (DFmode))
+-    || (TARGET_SSE2 && TARGET_SSE_MATH)")
+-
+-(define_expand "divsf3"
+-  [(set (match_operand:SF 0 "register_operand")
+-	(div:SF (match_operand:SF 1 "register_operand")
+-		(match_operand:SF 2 "nonimmediate_operand")))]
+-  "(TARGET_80387 && X87_ENABLE_ARITH (SFmode))
+-    || TARGET_SSE_MATH"
++(define_expand "div<mode>3"
++  [(set (match_operand:MODEF 0 "register_operand")
++	(div:MODEF (match_operand:MODEF 1 "register_operand")
++		   (match_operand:MODEF 2 "nonimmediate_operand")))]
++  "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
++    || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+ {
+-  if (TARGET_SSE_MATH
++  if (<MODE>mode == SFmode
++      && TARGET_SSE && TARGET_SSE_MATH
+       && TARGET_RECIP_DIV
+       && optimize_insn_for_speed_p ()
+       && flag_finite_math_only && !flag_trapping_math
+@@ -10863,10 +10857,15 @@
+   split_double_mode (<DWI>mode, &operands[0], 1, &operands[4], &operands[5]);
+ })
+ 
++(define_mode_attr rorx_immediate_operand
++	[(SI "const_0_to_31_operand")
++	 (DI "const_0_to_63_operand")])
++
+ (define_insn "*bmi2_rorx<mode>3_1"
+   [(set (match_operand:SWI48 0 "register_operand" "=r")
+-	(rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
+-			(match_operand:QI 2 "immediate_operand" "<S>")))]
++	(rotatert:SWI48
++	  (match_operand:SWI48 1 "nonimmediate_operand" "rm")
++	  (match_operand:QI 2 "<rorx_immediate_operand>" "<S>")))]
+   "TARGET_BMI2"
+   "rorx\t{%2, %1, %0|%0, %1, %2}"
+   [(set_attr "type" "rotatex")
+@@ -10909,7 +10908,7 @@
+ (define_split
+   [(set (match_operand:SWI48 0 "register_operand")
+ 	(rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+-		      (match_operand:QI 2 "immediate_operand")))
++		      (match_operand:QI 2 "const_int_operand")))
+    (clobber (reg:CC FLAGS_REG))]
+   "TARGET_BMI2 && reload_completed"
+   [(set (match_dup 0)
+@@ -10923,7 +10922,7 @@
+ (define_split
+   [(set (match_operand:SWI48 0 "register_operand")
+ 	(rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+-			(match_operand:QI 2 "immediate_operand")))
++			(match_operand:QI 2 "const_int_operand")))
+    (clobber (reg:CC FLAGS_REG))]
+   "TARGET_BMI2 && reload_completed"
+   [(set (match_dup 0)
+@@ -10933,7 +10932,7 @@
+   [(set (match_operand:DI 0 "register_operand" "=r")
+ 	(zero_extend:DI
+ 	  (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "rm")
+-		       (match_operand:QI 2 "immediate_operand" "I"))))]
++		       (match_operand:QI 2 "const_0_to_31_operand" "I"))))]
+   "TARGET_64BIT && TARGET_BMI2"
+   "rorx\t{%2, %1, %k0|%k0, %1, %2}"
+   [(set_attr "type" "rotatex")
+@@ -10977,7 +10976,7 @@
+   [(set (match_operand:DI 0 "register_operand")
+ 	(zero_extend:DI
+ 	  (rotate:SI (match_operand:SI 1 "nonimmediate_operand")
+-		     (match_operand:QI 2 "immediate_operand"))))
++		     (match_operand:QI 2 "const_int_operand"))))
+    (clobber (reg:CC FLAGS_REG))]
+   "TARGET_64BIT && TARGET_BMI2 && reload_completed"
+   [(set (match_dup 0)
+@@ -10992,7 +10991,7 @@
+   [(set (match_operand:DI 0 "register_operand")
+ 	(zero_extend:DI
+ 	  (rotatert:SI (match_operand:SI 1 "nonimmediate_operand")
+-		       (match_operand:QI 2 "immediate_operand"))))
++		       (match_operand:QI 2 "const_int_operand"))))
+    (clobber (reg:CC FLAGS_REG))]
+   "TARGET_64BIT && TARGET_BMI2 && reload_completed"
+   [(set (match_dup 0)
+@@ -11879,7 +11878,8 @@
+ 	(zero_extend (match_dup 1)))]
+   "(peep2_reg_dead_p (3, operands[1])
+     || operands_match_p (operands[1], operands[3]))
+-   && ! reg_overlap_mentioned_p (operands[3], operands[0])"
++   && ! reg_overlap_mentioned_p (operands[3], operands[0])
++   && peep2_regno_dead_p (0, FLAGS_REG)"
+   [(set (match_dup 4) (match_dup 0))
+    (set (strict_low_part (match_dup 5))
+ 	(match_dup 2))]
+@@ -11900,7 +11900,8 @@
+   "(peep2_reg_dead_p (3, operands[1])
+     || operands_match_p (operands[1], operands[3]))
+    && ! reg_overlap_mentioned_p (operands[3], operands[0])
+-   && ! reg_set_p (operands[3], operands[4])"
++   && ! reg_set_p (operands[3], operands[4])
++   && peep2_regno_dead_p (0, FLAGS_REG)"
+   [(parallel [(set (match_dup 5) (match_dup 0))
+ 	      (match_dup 4)])
+    (set (strict_low_part (match_dup 6))
+@@ -11922,7 +11923,8 @@
+ 		   (and:SI (match_dup 3) (const_int 255)))
+ 	      (clobber (reg:CC FLAGS_REG))])]
+   "REGNO (operands[1]) == REGNO (operands[3])
+-   && ! reg_overlap_mentioned_p (operands[3], operands[0])"
++   && ! reg_overlap_mentioned_p (operands[3], operands[0])
++   && peep2_regno_dead_p (0, FLAGS_REG)"
+   [(set (match_dup 4) (match_dup 0))
+    (set (strict_low_part (match_dup 5))
+ 	(match_dup 2))]
+@@ -11944,7 +11946,8 @@
+   "(peep2_reg_dead_p (3, operands[1])
+     || operands_match_p (operands[1], operands[3]))
+    && ! reg_overlap_mentioned_p (operands[3], operands[0])
+-   && ! reg_set_p (operands[3], operands[4])"
++   && ! reg_set_p (operands[3], operands[4])
++   && peep2_regno_dead_p (0, FLAGS_REG)"
+   [(parallel [(set (match_dup 5) (match_dup 0))
+ 	      (match_dup 4)])
+    (set (strict_low_part (match_dup 6))
+@@ -14223,7 +14226,7 @@
+   [(set (match_operand:SF 0 "register_operand" "=x")
+ 	(unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
+ 		   UNSPEC_RCP))]
+-  "TARGET_SSE_MATH"
++  "TARGET_SSE && TARGET_SSE_MATH"
+   "%vrcpss\t{%1, %d0|%d0, %1}"
+   [(set_attr "type" "sse")
+    (set_attr "atom_sse_attr" "rcp")
+@@ -14548,7 +14551,7 @@
+   [(set (match_operand:SF 0 "register_operand" "=x")
+ 	(unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
+ 		   UNSPEC_RSQRT))]
+-  "TARGET_SSE_MATH"
++  "TARGET_SSE && TARGET_SSE_MATH"
+   "%vrsqrtss\t{%1, %d0|%d0, %1}"
+   [(set_attr "type" "sse")
+    (set_attr "atom_sse_attr" "rcp")
+@@ -14560,7 +14563,7 @@
+   [(set (match_operand:SF 0 "register_operand")
+ 	(unspec:SF [(match_operand:SF 1 "nonimmediate_operand")]
+ 		   UNSPEC_RSQRT))]
+-  "TARGET_SSE_MATH"
++  "TARGET_SSE && TARGET_SSE_MATH"
+ {
+   ix86_emit_swsqrtsf (operands[0], operands[1], SFmode, 1);
+   DONE;
+@@ -14589,7 +14592,7 @@
+    || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+ {
+   if (<MODE>mode == SFmode
+-      && TARGET_SSE_MATH
++      && TARGET_SSE && TARGET_SSE_MATH
+       && TARGET_RECIP_SQRT
+       && !optimize_function_for_size_p (cfun)
+       && flag_finite_math_only && !flag_trapping_math
+Index: gcc/config/i386/sol2.h
+===================================================================
+--- a/src/gcc/config/i386/sol2.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/i386/sol2.h	(.../branches/gcc-6-branch)
+@@ -65,8 +65,16 @@
+ #define ASM_CPU64_DEFAULT_SPEC "-xarch=generic64"
+ #endif
+ 
++/* Since Studio 12.6, as needs -xbrace_comment=no so its AVX512 syntax is
++   fully compatible with gas.  */
++#ifdef HAVE_AS_XBRACE_COMMENT_OPTION
++#define ASM_XBRACE_COMMENT_SPEC "-xbrace_comment=no"
++#else
++#define ASM_XBRACE_COMMENT_SPEC ""
++#endif
++
+ #undef ASM_CPU_SPEC
+-#define ASM_CPU_SPEC "%(asm_cpu_default)"
++#define ASM_CPU_SPEC "%(asm_cpu_default) " ASM_XBRACE_COMMENT_SPEC
+ 
+ /* Don't include ASM_PIC_SPEC.  While the Solaris 10+ assembler accepts -K PIC,
+    it gives many warnings: 
+Index: gcc/config/i386/x86-tune.def
+===================================================================
+--- a/src/gcc/config/i386/x86-tune.def	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/i386/x86-tune.def	(.../branches/gcc-6-branch)
+@@ -555,3 +555,7 @@
+    if-converted to one.  */
+ DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
+ 	  m_SILVERMONT | m_KNL | m_INTEL | m_CORE_ALL | m_GENERIC)
++
++/* X86_TUNE_EMIT_VZEROUPPER: This enables vzeroupper instruction insertion
++   before a transfer of control flow out of the function.  */
++DEF_TUNE (X86_TUNE_EMIT_VZEROUPPER, "emit_vzeroupper", ~m_KNL)
+Index: gcc/config/i386/sse.md
+===================================================================
+--- a/src/gcc/config/i386/sse.md	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/i386/sse.md	(.../branches/gcc-6-branch)
+@@ -7230,12 +7230,13 @@
+ (define_insn "vec_extract_lo_<mode><mask_name>"
+   [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=<store_mask_constraint>,v")
+ 	(vec_select:<ssehalfvecmode>
+-	  (match_operand:V8FI 1 "nonimmediate_operand" "v,m")
++	  (match_operand:V8FI 1 "<store_mask_predicate>" "v,<store_mask_constraint>")
+ 	  (parallel [(const_int 0) (const_int 1)
+             (const_int 2) (const_int 3)])))]
+-  "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
++  "TARGET_AVX512F
++   && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
+ {
+-  if (<mask_applied> || !TARGET_AVX512VL)
++  if (<mask_applied> || (!TARGET_AVX512VL && !MEM_P (operands[1])))
+     return "vextract<shuffletype>64x4\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
+   else
+     return "#";
+@@ -7374,7 +7375,8 @@
+ (define_insn "vec_extract_lo_<mode><mask_name>"
+   [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,m")
+ 	(vec_select:<ssehalfvecmode>
+-	  (match_operand:V16FI 1 "nonimmediate_operand" "vm,v")
++	  (match_operand:V16FI 1 "<store_mask_predicate>"
++				 "<store_mask_constraint>,v")
+ 	  (parallel [(const_int 0) (const_int 1)
+                      (const_int 2) (const_int 3)
+                      (const_int 4) (const_int 5)
+@@ -7381,7 +7383,7 @@
+                      (const_int 6) (const_int 7)])))]
+   "TARGET_AVX512F
+    && <mask_mode512bit_condition>
+-   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
++   && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
+ {
+   if (<mask_applied>)
+     return "vextract<shuffletype>32x8\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
+@@ -7413,11 +7415,12 @@
+ (define_insn "vec_extract_lo_<mode><mask_name>"
+   [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,m")
+ 	(vec_select:<ssehalfvecmode>
+-	  (match_operand:VI8F_256 1 "nonimmediate_operand" "vm,v")
++	  (match_operand:VI8F_256 1 "<store_mask_predicate>"
++				    "<store_mask_constraint>,v")
+ 	  (parallel [(const_int 0) (const_int 1)])))]
+   "TARGET_AVX
+    && <mask_avx512vl_condition> && <mask_avx512dq_condition>
+-   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
++   && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
+ {
+   if (<mask_applied>)
+     return "vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}";
+@@ -7493,12 +7496,16 @@
+ 
+ 
+ (define_insn "vec_extract_lo_<mode><mask_name>"
+-  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=<store_mask_constraint>")
++  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
++					  "=<store_mask_constraint>,v")
+ 	(vec_select:<ssehalfvecmode>
+-	  (match_operand:VI4F_256 1 "register_operand" "v")
++	  (match_operand:VI4F_256 1 "<store_mask_predicate>"
++				    "v,<store_mask_constraint>")
+ 	  (parallel [(const_int 0) (const_int 1)
+ 		     (const_int 2) (const_int 3)])))]
+-  "TARGET_AVX && <mask_avx512vl_condition> && <mask_avx512dq_condition>"
++  "TARGET_AVX
++   && <mask_avx512vl_condition> && <mask_avx512dq_condition>
++   && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
+ {
+   if (<mask_applied>)
+     return "vextract<shuffletype>32x4\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
+Index: gcc/config/i386/i386.c
+===================================================================
+--- a/src/gcc/config/i386/i386.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/i386/i386.c	(.../branches/gcc-6-branch)
+@@ -2675,7 +2675,7 @@
+   int i;
+ 
+   /* vzeroupper instructions are inserted immediately after reload to
+-     account for possible spills from 256bit registers.  The pass
++     account for possible spills from 256bit or 512bit registers.  The pass
+      reuses mode switching infrastructure by re-running mode insertion
+      pass, so disable entities that have already been processed.  */
+   for (i = 0; i < MAX_386_ENTITIES; i++)
+@@ -3650,7 +3650,7 @@
+   /* opt_pass methods: */
+   virtual bool gate (function *)
+     {
+-      return TARGET_AVX && !TARGET_AVX512F
++      return TARGET_AVX
+ 	     && TARGET_VZEROUPPER && flag_expensive_optimizations
+ 	     && !optimize_size;
+     }
+@@ -5196,6 +5196,12 @@
+     opts->x_ix86_isa_flags
+       |= OPTION_MASK_ISA_LZCNT & ~opts->x_ix86_isa_flags_explicit;
+ 
++  /* Disable BMI, BMI2 and TBM instructions for -m16.  */
++  if (TARGET_16BIT_P(opts->x_ix86_isa_flags))
++    opts->x_ix86_isa_flags
++      &= ~((OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_BMI2 | OPTION_MASK_ISA_TBM)
++	   & ~opts->x_ix86_isa_flags_explicit);
++
+   /* Validate -mpreferred-stack-boundary= value or default it to
+      PREFERRED_STACK_BOUNDARY_DEFAULT.  */
+   ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
+@@ -5464,7 +5470,8 @@
+ #endif
+    }
+ 
+-  if (!(opts_set->x_target_flags & MASK_VZEROUPPER))
++  if (!(opts_set->x_target_flags & MASK_VZEROUPPER)
++      && TARGET_EMIT_VZEROUPPER)
+     opts->x_target_flags |= MASK_VZEROUPPER;
+   if (!(opts_set->x_target_flags & MASK_STV))
+     opts->x_target_flags |= MASK_STV;
+@@ -5552,12 +5559,6 @@
+   gcc_assert ((opts->x_target_flags & MASK_LONG_DOUBLE_64) == 0
+ 	      || (opts->x_target_flags & MASK_LONG_DOUBLE_128) == 0);
+ 
+-  /* Save the initial options in case the user does function specific
+-     options.  */
+-  if (main_args_p)
+-    target_option_default_node = target_option_current_node
+-      = build_target_option_node (opts);
+-
+   /* Handle stack protector */
+   if (!opts_set->x_ix86_stack_protector_guard)
+     opts->x_ix86_stack_protector_guard
+@@ -5577,6 +5578,12 @@
+       ix86_parse_stringop_strategy_string (str, true);
+       free (str);
+     }
++
++  /* Save the initial options in case the user does function specific
++     options.  */
++  if (main_args_p)
++    target_option_default_node = target_option_current_node
++      = build_target_option_node (opts);
+ }
+ 
+ /* Implement the TARGET_OPTION_OVERRIDE hook.  */
+@@ -17521,7 +17528,7 @@
+       /* Displacement only requires special attention.  */
+       if (CONST_INT_P (disp))
+ 	{
+-	  if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == ADDR_SPACE_GENERIC)
++	  if (ASSEMBLER_DIALECT == ASM_INTEL && ADDR_SPACE_GENERIC_P (as))
+ 	    fputs ("ds:", file);
+ 	  fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
+ 	}
+@@ -18019,16 +18026,17 @@
+   return buf;
+ }
+ 
+-/* Check if a 256bit AVX register is referenced inside of EXP.   */
++/* Check if a 256bit or 512 bit AVX register is referenced inside of EXP.   */
+ 
+ static bool
+-ix86_check_avx256_register (const_rtx exp)
++ix86_check_avx_upper_register (const_rtx exp)
+ {
+   if (SUBREG_P (exp))
+     exp = SUBREG_REG (exp);
+ 
+   return (REG_P (exp)
+-	  && VALID_AVX256_REG_OR_OI_MODE (GET_MODE (exp)));
++	&& (VALID_AVX256_REG_OR_OI_MODE (GET_MODE (exp))
++	|| VALID_AVX512F_REG_OR_XI_MODE (GET_MODE (exp))));
+ }
+ 
+ /* Return needed mode for entity in optimize_mode_switching pass.  */
+@@ -18041,7 +18049,7 @@
+       rtx link;
+ 
+       /* Needed mode is set to AVX_U128_CLEAN if there are
+-	 no 256bit modes used in function arguments.  */
++	 no 256bit or 512bit modes used in function arguments. */
+       for (link = CALL_INSN_FUNCTION_USAGE (insn);
+ 	   link;
+ 	   link = XEXP (link, 1))
+@@ -18050,7 +18058,7 @@
+ 	    {
+ 	      rtx arg = XEXP (XEXP (link, 0), 0);
+ 
+-	      if (ix86_check_avx256_register (arg))
++	      if (ix86_check_avx_upper_register (arg))
+ 		return AVX_U128_DIRTY;
+ 	    }
+ 	}
+@@ -18058,13 +18066,13 @@
+       return AVX_U128_CLEAN;
+     }
+ 
+-  /* Require DIRTY mode if a 256bit AVX register is referenced.  Hardware
+-     changes state only when a 256bit register is written to, but we need
+-     to prevent the compiler from moving optimal insertion point above
+-     eventual read from 256bit register.  */
++  /* Require DIRTY mode if a 256bit or 512bit AVX register is referenced.
++     Hardware changes state only when a 256bit register is written to,
++     but we need to prevent the compiler from moving optimal insertion
++     point above eventual read from 256bit or 512 bit register.  */
+   subrtx_iterator::array_type array;
+   FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST)
+-    if (ix86_check_avx256_register (*iter))
++    if (ix86_check_avx_upper_register (*iter))
+       return AVX_U128_DIRTY;
+ 
+   return AVX_U128_ANY;
+@@ -18144,12 +18152,12 @@
+   return 0;
+ }
+ 
+-/* Check if a 256bit AVX register is referenced in stores.   */
++/* Check if a 256bit or 512bit AVX register is referenced in stores.   */
+  
+ static void
+-ix86_check_avx256_stores (rtx dest, const_rtx, void *data)
++ix86_check_avx_upper_stores (rtx dest, const_rtx, void *data)
+  {
+-   if (ix86_check_avx256_register (dest))
++   if (ix86_check_avx_upper_register (dest))
+     {
+       bool *used = (bool *) data;
+       *used = true;
+@@ -18168,18 +18176,18 @@
+     return AVX_U128_CLEAN;
+ 
+   /* We know that state is clean after CALL insn if there are no
+-     256bit registers used in the function return register.  */
++     256bit or 512bit registers used in the function return register. */
+   if (CALL_P (insn))
+     {
+-      bool avx_reg256_found = false;
+-      note_stores (pat, ix86_check_avx256_stores, &avx_reg256_found);
++      bool avx_upper_reg_found = false;
++      note_stores (pat, ix86_check_avx_upper_stores, &avx_upper_reg_found);
+ 
+-      return avx_reg256_found ? AVX_U128_DIRTY : AVX_U128_CLEAN;
++      return avx_upper_reg_found ? AVX_U128_DIRTY : AVX_U128_CLEAN;
+     }
+ 
+   /* Otherwise, return current mode.  Remember that if insn
+-     references AVX 256bit registers, the mode was already changed
+-     to DIRTY from MODE_NEEDED.  */
++     references AVX 256bit or 512bit registers, the mode was already
++     changed to DIRTY from MODE_NEEDED.  */
+   return mode;
+ }
+ 
+@@ -18208,13 +18216,13 @@
+   tree arg;
+ 
+   /* Entry mode is set to AVX_U128_DIRTY if there are
+-     256bit modes used in function arguments.  */
++     256bit or 512bit modes used in function arguments.  */
+   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
+        arg = TREE_CHAIN (arg))
+     {
+       rtx incoming = DECL_INCOMING_RTL (arg);
+ 
+-      if (incoming && ix86_check_avx256_register (incoming))
++      if (incoming && ix86_check_avx_upper_register (incoming))
+ 	return AVX_U128_DIRTY;
+     }
+ 
+@@ -18246,9 +18254,9 @@
+ {
+   rtx reg = crtl->return_rtx;
+ 
+-  /* Exit mode is set to AVX_U128_DIRTY if there are
+-     256bit modes used in the function return register.  */
+-  if (reg && ix86_check_avx256_register (reg))
++  /* Exit mode is set to AVX_U128_DIRTY if there are 256bit
++     or 512 bit modes used in the function return register. */
++  if (reg && ix86_check_avx_upper_register (reg))
+     return AVX_U128_DIRTY;
+ 
+   return AVX_U128_CLEAN;
+@@ -19666,13 +19674,13 @@
+ 
+   if (signed_p)
+     {
+-      div = gen_rtx_DIV (SImode, operands[2], operands[3]);
+-      mod = gen_rtx_MOD (SImode, operands[2], operands[3]);
++      div = gen_rtx_DIV (mode, operands[2], operands[3]);
++      mod = gen_rtx_MOD (mode, operands[2], operands[3]);
+     }
+   else
+     {
+-      div = gen_rtx_UDIV (SImode, operands[2], operands[3]);
+-      mod = gen_rtx_UMOD (SImode, operands[2], operands[3]);
++      div = gen_rtx_UDIV (mode, operands[2], operands[3]);
++      mod = gen_rtx_UMOD (mode, operands[2], operands[3]);
+     }
+ 
+   /* Extract remainder from AH.  */
+@@ -36760,6 +36768,9 @@
+     {
+       const char *str = TREE_STRING_POINTER (TREE_VALUE (arg));
+       size_t len = strlen (str);
++      /* Skip empty string.  */
++      if (len == 0)
++	continue;
+       str_len_sum += len + 1;
+       if (arg != arglist)
+ 	argnum++;
+@@ -36774,11 +36785,21 @@
+     {
+       const char *str = TREE_STRING_POINTER (TREE_VALUE (arg));
+       size_t len = strlen (str);
++      /* Skip empty string.  */
++      if (len == 0)
++	continue;
+       memcpy (attr_str + str_len_sum, str, len);
+       attr_str[str_len_sum + len] = TREE_CHAIN (arg) ? ',' : '\0';
+       str_len_sum += len + 1;
+     }
+ 
++  /* Strip ',' character at the end.  */
++  if (str_len_sum > 0 && attr_str[str_len_sum - 1] == ',')
++    {
++      attr_str[str_len_sum - 1] = '\0';
++      str_len_sum--;
++    }
++
+   /* Replace "=,-" with "_".  */
+   for (i = 0; i < strlen (attr_str); i++)
+     if (attr_str[i] == '=' || attr_str[i]== '-')
+@@ -37395,6 +37416,7 @@
+     M_INTEL_KNL,
+     M_AMD_BTVER1,
+     M_AMD_BTVER2,    
++    M_AMDFAM17H,
+     M_CPU_SUBTYPE_START,
+     M_INTEL_COREI7_NEHALEM,
+     M_INTEL_COREI7_WESTMERE,
+@@ -37449,6 +37471,7 @@
+       {"bdver3", M_AMDFAM15H_BDVER3},
+       {"bdver4", M_AMDFAM15H_BDVER4},
+       {"btver2", M_AMD_BTVER2},
++      {"amdfam17h", M_AMDFAM17H},
+       {"znver1", M_AMDFAM17H_ZNVER1},
+     };
+ 
+@@ -45190,7 +45213,8 @@
+ x86_print_call_or_nop (FILE *file, const char *target)
+ {
+   if (flag_nop_mcount)
+-    fprintf (file, "1:\tnopl 0x00(%%eax,%%eax,1)\n"); /* 5 byte nop.  */
++    /* 5 byte nop: nopl 0(%[re]ax,%[re]ax,1) */
++    fprintf (file, "1:" ASM_BYTE "0x0f, 0x1f, 0x44, 0x00, 0x00\n");
+   else
+     fprintf (file, "1:\tcall\t%s\n", target);
+ }
+Index: gcc/config/sol2.h
+===================================================================
+--- a/src/gcc/config/sol2.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/sol2.h	(.../branches/gcc-6-branch)
+@@ -159,9 +159,9 @@
+ 			    %{!ansi:values-Xa.o%s}"
+ 
+ #if defined(HAVE_LD_PIE) && defined(HAVE_SOLARIS_CRTS)
+-#define STARTFILE_CRTBEGIN_SPEC "%{shared:crtbeginS.o%s} \
+-				 %{" PIE_SPEC ":crtbeginS.o%s} \
+-				 %{" NO_PIE_SPEC ":crtbegin.o%s}"
++#define STARTFILE_CRTBEGIN_SPEC "%{static:crtbegin.o%s; \
++				   shared|" PIE_SPEC ":crtbeginS.o%s; \
++				   :crtbegin.o%s}"
+ #else
+ #define STARTFILE_CRTBEGIN_SPEC	"crtbegin.o%s"
+ #endif
+@@ -185,8 +185,8 @@
+ /* We don't use the standard svr4 STARTFILE_SPEC because it's wrong for us.  */
+ #undef STARTFILE_SPEC
+ #ifdef HAVE_SOLARIS_CRTS
+-/* Since Solaris 11.x and Solaris 12, the OS delivers crt1.o, crti.o, and
+-   crtn.o, with a hook for compiler-dependent stuff like profile handling.  */
++/* Since Solaris 11.4, the OS delivers crt1.o, crti.o, and crtn.o, with a hook
++   for compiler-dependent stuff like profile handling.  */
+ #define STARTFILE_SPEC "%{!shared:%{!symbolic: \
+ 			  crt1.o%s \
+ 			  %{p:%e-p is not supported; \
+@@ -204,9 +204,9 @@
+ #endif
+ 
+ #if defined(HAVE_LD_PIE) && defined(HAVE_SOLARIS_CRTS)
+-#define ENDFILE_CRTEND_SPEC "%{shared:crtendS.o%s;: \
+-			       %{" PIE_SPEC ":crtendS.o%s} \
+-			       %{" NO_PIE_SPEC ":crtend.o%s}}"
++#define ENDFILE_CRTEND_SPEC "%{static:crtend.o%s; \
++			       shared|" PIE_SPEC ":crtendS.o%s; \
++			       :crtend.o%s}"
+ #else
+ #define ENDFILE_CRTEND_SPEC "crtend.o%s"
+ #endif
+Index: gcc/config/sh/sh-protos.h
+===================================================================
+--- a/src/gcc/config/sh/sh-protos.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/sh/sh-protos.h	(.../branches/gcc-6-branch)
+@@ -228,9 +228,13 @@
+ 	}
+     }
+ 
+-  if (result.set_src != NULL)
+-    gcc_assert (result.insn != NULL && result.set_rtx != NULL);
+-
++  /* If the searched reg is found inside a (mem (post_inc:SI (reg))), set_of
++     will return NULL and set_rtx will be NULL.
++     In this case report a 'not found'.  result.insn will always be non-null
++     at this point, so no need to check it.  */
++  if (result.set_src != NULL && result.set_rtx == NULL)
++    result.set_src = NULL;
++ 
+   return result;
+ }
+ 
+Index: gcc/config/sh/sh_optimize_sett_clrt.cc
+===================================================================
+--- a/src/gcc/config/sh/sh_optimize_sett_clrt.cc	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/sh/sh_optimize_sett_clrt.cc	(.../branches/gcc-6-branch)
+@@ -18,6 +18,8 @@
+ <http://www.gnu.org/licenses/>.  */
+ 
+ #include "config.h"
++#define INCLUDE_ALGORITHM
++#define INCLUDE_VECTOR
+ #include "system.h"
+ #include "coretypes.h"
+ #include "backend.h"
+@@ -27,9 +29,6 @@
+ #include "cfgrtl.h"
+ #include "tree-pass.h"
+ 
+-#include <vector>
+-#include <algorithm>
+-
+ /*
+ This pass tries to eliminate unnecessary sett or clrt instructions in cases
+ where the ccreg value is already known to be the same as the constant set
+Index: gcc/config/avr/avr.opt
+===================================================================
+--- a/src/gcc/config/avr/avr.opt	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/avr/avr.opt	(.../branches/gcc-6-branch)
+@@ -91,6 +91,10 @@
+ Warning C Report Var(avr_warn_addr_space_convert) Init(0)
+ Warn if the address space of an address is changed.
+ 
++Wmisspelled-isr
++Warning C C++ Report Var(avr_warn_misspelled_isr) Init(1)
++Warn if the ISR is misspelled, i.e. without __vector prefix. Enabled by default.
++
+ mfract-convert-truncate
+ Target Report Mask(FRACT_CONV_TRUNC)
+ Allow to use truncation instead of rounding towards 0 for fractional int types.
+Index: gcc/config/avr/avr.c
+===================================================================
+--- a/src/gcc/config/avr/avr.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/avr/avr.c	(.../branches/gcc-6-branch)
+@@ -735,12 +735,6 @@
+ 
+       name = default_strip_name_encoding (name);
+ 
+-      /* Silently ignore 'signal' if 'interrupt' is present.  AVR-LibC startet
+-         using this when it switched from SIGNAL and INTERRUPT to ISR.  */
+-
+-      if (cfun->machine->is_interrupt)
+-        cfun->machine->is_signal = 0;
+-
+       /* Interrupt handlers must be  void __vector (void)  functions.  */
+ 
+       if (args && TREE_CODE (TREE_VALUE (args)) != VOID_TYPE)
+@@ -749,15 +743,37 @@
+       if (TREE_CODE (ret) != VOID_TYPE)
+         error_at (loc, "%qs function cannot return a value", isr);
+ 
++#if defined WITH_AVRLIBC
++      /* Silently ignore 'signal' if 'interrupt' is present.  AVR-LibC startet
++         using this when it switched from SIGNAL and INTERRUPT to ISR.  */
++
++      if (cfun->machine->is_interrupt)
++        cfun->machine->is_signal = 0;
++
+       /* If the function has the 'signal' or 'interrupt' attribute, ensure
+          that the name of the function is "__vector_NN" so as to catch
+          when the user misspells the vector name.  */
+ 
+       if (!STR_PREFIX_P (name, "__vector"))
+-        warning_at (loc, 0, "%qs appears to be a misspelled %s handler",
+-                    name, isr);
++        warning_at (loc, OPT_Wmisspelled_isr, "%qs appears to be a misspelled "
++                    "%qs handler, missing %<__vector%> prefix", name, isr);
++#endif // AVR-LibC naming conventions
+     }
+ 
++#if defined WITH_AVRLIBC
++  // Common problem is using "ISR" without first including avr/interrupt.h.
++  const char *name = IDENTIFIER_POINTER (DECL_NAME (decl));
++  name = default_strip_name_encoding (name);
++  if (0 == strcmp ("ISR", name)
++      || 0 == strcmp ("INTERRUPT", name)
++      || 0 == strcmp ("SIGNAL", name))
++    {
++      warning_at (loc, OPT_Wmisspelled_isr, "%qs is a reserved identifier"
++                  " in AVR-LibC.  Consider %<#include <avr/interrupt.h>%>"
++                  " before using the %qs macro", name, name);
++    }
++#endif // AVR-LibC naming conventions
++
+   /* Don't print the above diagnostics more than once.  */
+ 
+   cfun->machine->attributes_checked_p = 1;
+@@ -3490,7 +3506,7 @@
+   if (CONSTANT_ADDRESS_P (x))
+     {
+       int n_words = AVR_TINY ? 1 : 2;
+-      return optimize > 0 && io_address_operand (x, QImode)
++      return io_address_operand (x, QImode)
+         ? avr_asm_len ("in %0,%i1", op, plen, -1)
+         : avr_asm_len ("lds %0,%m1", op, plen, -n_words);
+     }
+@@ -3745,7 +3761,7 @@
+   else if (CONSTANT_ADDRESS_P (base))
+     {
+       int n_words = AVR_TINY ? 2 : 4;
+-      return optimize > 0 && io_address_operand (base, HImode)
++      return io_address_operand (base, HImode)
+         ? avr_asm_len ("in %A0,%i1" CR_TAB
+                        "in %B0,%i1+1", op, plen, -2)
+ 
+@@ -4873,7 +4889,7 @@
+   if (CONSTANT_ADDRESS_P (x))
+     {
+       int n_words = AVR_TINY ? 1 : 2;
+-      return optimize > 0 && io_address_operand (x, QImode)
++      return io_address_operand (x, QImode)
+         ? avr_asm_len ("out %i0,%1", op, plen, -1)
+         : avr_asm_len ("sts %m0,%1", op, plen, -n_words);
+     }
+@@ -4949,13 +4965,12 @@
+ 
+   if (CONSTANT_ADDRESS_P (base))
+     {
+-      int n_words = AVR_TINY ? 2 : 4;
+-      return optimize > 0 && io_address_operand (base, HImode)
++      return io_address_operand (base, HImode)
+         ? avr_asm_len ("out %i0,%A1" CR_TAB
+                        "out %i0+1,%B1", op, plen, -2)
+ 
+         : avr_asm_len ("sts %m0,%A1" CR_TAB
+-                       "sts %m0+1,%B1", op, plen, -n_words);
++                       "sts %m0+1,%B1", op, plen, -4);
+     }
+ 
+   if (reg_base > 0)
+@@ -5132,7 +5147,7 @@
+   if (CONSTANT_ADDRESS_P (base))
+     {
+       int n_words = AVR_TINY ? 2 : 4;
+-      return optimize > 0 && io_address_operand (base, HImode)
++      return io_address_operand (base, HImode)
+         ? avr_asm_len ("out %i0+1,%B1" CR_TAB
+                        "out %i0,%A1", op, plen, -2)
+ 
+@@ -9055,10 +9070,12 @@
+   bool io_p = (strncmp (IDENTIFIER_POINTER (name), "io", 2) == 0);
+   location_t loc = DECL_SOURCE_LOCATION (*node);
+ 
+-  if (TREE_CODE (*node) != VAR_DECL)
++  if (!VAR_P (*node))
+     {
+-      warning_at (loc, 0, "%qE attribute only applies to variables", name);
++      warning_at (loc, OPT_Wattributes, "%qE attribute only applies to "
++		  "variables", name);
+       *no_add = true;
++      return NULL_TREE;
+     }
+ 
+   if (args != NULL_TREE)
+@@ -9068,8 +9085,8 @@
+       tree arg = TREE_VALUE (args);
+       if (TREE_CODE (arg) != INTEGER_CST)
+ 	{
+-	  warning (0, "%qE attribute allows only an integer constant argument",
+-		   name);
++	  warning_at (loc, OPT_Wattributes, "%qE attribute allows only an "
++		      "integer constant argument", name);
+ 	  *no_add = true;
+ 	}
+       else if (io_p
+@@ -9078,19 +9095,20 @@
+ 			? low_io_address_operand : io_address_operand)
+ 			 (GEN_INT (TREE_INT_CST_LOW (arg)), QImode)))
+ 	{
+-	  warning_at (loc, 0, "%qE attribute address out of range", name);
++	  warning_at (loc, OPT_Wattributes, "%qE attribute address "
++		      "out of range", name);
+ 	  *no_add = true;
+ 	}
+       else
+ 	{
+ 	  tree attribs = DECL_ATTRIBUTES (*node);
+-	  const char *names[] = { "io", "io_low", "address", NULL } ;
++	  const char *names[] = { "io", "io_low", "address", NULL };
+ 	  for (const char **p = names; *p; p++)
+ 	    {
+ 	      tree other = lookup_attribute (*p, attribs);
+ 	      if (other && TREE_VALUE (other))
+ 		{
+-		  warning_at (loc, 0,
++		  warning_at (loc, OPT_Wattributes,
+ 			      "both %s and %qE attribute provide address",
+ 			      *p, name);
+ 		  *no_add = true;
+@@ -9101,7 +9119,8 @@
+     }
+ 
+   if (*no_add == false && io_p && !TREE_THIS_VOLATILE (*node))
+-    warning_at (loc, 0, "%qE attribute on non-volatile variable", name);
++    warning_at (loc, OPT_Wattributes, "%qE attribute on non-volatile variable",
++		name);
+ 
+   return NULL_TREE;
+ }
+@@ -9149,11 +9168,11 @@
+     false },
+   { "OS_main",   0, 0, false, true,  true,   avr_handle_fntype_attribute,
+     false },
+-  { "io",        0, 1, false, false, false,  avr_handle_addr_attribute,
++  { "io",        0, 1, true, false, false,  avr_handle_addr_attribute,
+     false },
+-  { "io_low",    0, 1, false, false, false,  avr_handle_addr_attribute,
++  { "io_low",    0, 1, true, false, false,  avr_handle_addr_attribute,
+     false },
+-  { "address",   1, 1, false, false, false,  avr_handle_addr_attribute,
++  { "address",   1, 1, true, false, false,  avr_handle_addr_attribute,
+     false },
+   { NULL,        0, 0, false, false, false, NULL, false }
+ };
+@@ -9591,18 +9610,26 @@
+ 
+   if (new_decl_p
+       && decl && DECL_P (decl)
+-      && NULL_TREE == DECL_INITIAL (decl)
+       && !DECL_EXTERNAL (decl)
+       && avr_progmem_p (decl, DECL_ATTRIBUTES (decl)))
+     {
+-      // Don't warn for (implicit) aliases like in PR80462.
+-      tree asmname = DECL_ASSEMBLER_NAME (decl);
+-      varpool_node *node = varpool_node::get_for_asmname (asmname);
+-      bool alias_p = node && node->alias;
++      if (!TREE_READONLY (decl))
++        {
++          // This might happen with C++ if stuff needs constructing.
++          error ("variable %q+D with dynamic initialization put "
++                 "into program memory area", decl);
++        }
++      else if (NULL_TREE == DECL_INITIAL (decl))
++        {
++          // Don't warn for (implicit) aliases like in PR80462.
++          tree asmname = DECL_ASSEMBLER_NAME (decl);
++          varpool_node *node = varpool_node::get_for_asmname (asmname);
++          bool alias_p = node && node->alias;
+ 
+-      if (!alias_p)
+-        warning (OPT_Wuninitialized, "uninitialized variable %q+D put into "
+-                 "program memory area", decl);
++          if (!alias_p)
++            warning (OPT_Wuninitialized, "uninitialized variable %q+D put "
++                     "into program memory area", decl);
++        }
+     }
+ 
+   default_encode_section_info (decl, rtl, new_decl_p);
+@@ -9864,6 +9891,33 @@
+ }
+ 
+ 
++/* Cost for mul highpart.  X is a LSHIFTRT, i.e. the outer TRUNCATE is
++   already stripped off.  */
++
++static int
++avr_mul_highpart_cost (rtx x, int)
++{
++  if (AVR_HAVE_MUL
++      && LSHIFTRT == GET_CODE (x)
++      && MULT == GET_CODE (XEXP (x, 0))
++      && CONST_INT_P (XEXP (x, 1)))
++    {
++      // This is the wider mode.
++      machine_mode mode = GET_MODE (x);
++  
++      // The middle-end might still have PR81444, i.e. it is calling the cost
++      // functions with strange modes.  Fix this now by also considering
++      // PSImode (should actually be SImode instead).
++      if (HImode == mode || PSImode == mode || SImode == mode)
++        {
++          return COSTS_N_INSNS (2);
++        }
++    }
++
++  return 10000;
++}
++
++
+ /* Mutually recursive subroutine of avr_rtx_cost for calculating the
+    cost of an RTX operand given its context.  X is the rtx of the
+    operand, MODE is its mode, and OUTER is the rtx_code of this
+@@ -9903,7 +9957,7 @@
+    In either case, *TOTAL contains the cost result.  */
+ 
+ static bool
+-avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
++avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
+                  int opno ATTRIBUTE_UNUSED, int *total, bool speed)
+ {
+   enum rtx_code code = GET_CODE (x);
+@@ -10544,6 +10598,12 @@
+       return true;
+ 
+     case LSHIFTRT:
++      if (outer_code == TRUNCATE)
++        {
++          *total = avr_mul_highpart_cost (x, speed);
++          return true;
++        }
++
+       switch (mode)
+ 	{
+ 	case QImode:
+@@ -10721,16 +10781,10 @@
+       return true;
+ 
+     case TRUNCATE:
+-      if (AVR_HAVE_MUL
+-          && LSHIFTRT == GET_CODE (XEXP (x, 0))
+-          && MULT == GET_CODE (XEXP (XEXP (x, 0), 0))
+-          && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
++      if (LSHIFTRT == GET_CODE (XEXP (x, 0)))
+         {
+-          if (QImode == mode || HImode == mode)
+-            {
+-              *total = COSTS_N_INSNS (2);
+-              return true;
+-            }
++          *total = avr_mul_highpart_cost (XEXP (x, 0), speed);
++          return true;
+         }
+       break;
+ 
+@@ -10779,8 +10833,7 @@
+     }
+   else if (CONSTANT_ADDRESS_P (x))
+     {
+-      if (optimize > 0
+-          && io_address_operand (x, QImode))
++      if (io_address_operand (x, QImode))
+         cost = 2;
+     }
+ 
+Index: gcc/config/xtensa/xtensa.c
+===================================================================
+--- a/src/gcc/config/xtensa/xtensa.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/xtensa/xtensa.c	(.../branches/gcc-6-branch)
+@@ -601,6 +601,7 @@
+     case HImode:
+       return xtensa_uimm8x2 (v);
+ 
++    case DImode:
+     case DFmode:
+       return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4));
+ 
+Index: gcc/config/gnu-user.h
+===================================================================
+--- a/src/gcc/config/gnu-user.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/gnu-user.h	(.../branches/gcc-6-branch)
+@@ -50,11 +50,15 @@
+ 
+ #if defined HAVE_LD_PIE
+ #define GNU_USER_TARGET_STARTFILE_SPEC \
+-  "%{!shared: %{pg|p|profile:gcrt1.o%s;: \
+-    %{" PIE_SPEC ":Scrt1.o%s} %{" NO_PIE_SPEC ":crt1.o%s}}} \
+-   crti.o%s %{static:crtbeginT.o%s;: %{shared:crtbeginS.o%s} \
+-	      %{" PIE_SPEC ":crtbeginS.o%s} \
+-	      %{" NO_PIE_SPEC ":crtbegin.o%s}} \
++  "%{shared:; \
++     pg|p|profile:gcrt1.o%s; \
++     static:crt1.o%s; \
++     " PIE_SPEC ":Scrt1.o%s; \
++     :crt1.o%s} \
++   crti.o%s \
++   %{static:crtbeginT.o%s; \
++     shared|" PIE_SPEC ":crtbeginS.o%s; \
++     :crtbegin.o%s} \
+    %{fvtable-verify=none:%s; \
+      fvtable-verify=preinit:vtv_start_preinit.o%s; \
+      fvtable-verify=std:vtv_start.o%s} \
+@@ -61,8 +65,13 @@
+    " CRTOFFLOADBEGIN
+ #else
+ #define GNU_USER_TARGET_STARTFILE_SPEC \
+-  "%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \
+-   crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \
++  "%{shared:; \
++     pg|p|profile:gcrt1.o%s; \
++     :crt1.o%s} \
++   crti.o%s \
++   %{static:crtbeginT.o%s; \
++     shared|pie:crtbeginS.o%s; \
++     :crtbegin.o%s} \
+    %{fvtable-verify=none:%s; \
+      fvtable-verify=preinit:vtv_start_preinit.o%s; \
+      fvtable-verify=std:vtv_start.o%s} \
+@@ -82,8 +91,10 @@
+   "%{fvtable-verify=none:%s; \
+      fvtable-verify=preinit:vtv_end_preinit.o%s; \
+      fvtable-verify=std:vtv_end.o%s} \
+-   %{shared:crtendS.o%s;: %{" PIE_SPEC ":crtendS.o%s} \
+-   %{" NO_PIE_SPEC ":crtend.o%s}} crtn.o%s \
++   %{static:crtend.o%s; \
++     shared|" PIE_SPEC ":crtendS.o%s; \
++     :crtend.o%s} \
++   crtn.o%s \
+    " CRTOFFLOADEND
+ #else
+ #define GNU_USER_TARGET_ENDFILE_SPEC \
+@@ -90,7 +101,10 @@
+   "%{fvtable-verify=none:%s; \
+      fvtable-verify=preinit:vtv_end_preinit.o%s; \
+      fvtable-verify=std:vtv_end.o%s} \
+-   %{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s \
++   %{static:crtend.o%s; \
++     shared|pie:crtendS.o%s; \
++     :crtend.o%s} \
++   crtn.o%s \
+    " CRTOFFLOADEND
+ #endif
+ #undef  ENDFILE_SPEC
+Index: gcc/config/aarch64/cortex-a57-fma-steering.c
+===================================================================
+--- a/src/gcc/config/aarch64/cortex-a57-fma-steering.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/aarch64/cortex-a57-fma-steering.c	(.../branches/gcc-6-branch)
+@@ -973,10 +973,17 @@
+ 		break;
+ 	    }
+ 
+-	  /* We didn't find a chain with a def for this instruction.  */
+-	  gcc_assert (i < dest_op_info->n_chains);
+-
+-	  this->analyze_fma_fmul_insn (forest, chain, head);
++	  /* Due to implementation of regrename, dest register can slip away
++	     from regrename's analysis.  As a result, there is no chain for
++	     the destination register of insn.  We simply skip the insn even
++	     it is a fmul/fmac instruction.  This can happen when the dest
++	     register is also a source register of insn and one of the below
++	     conditions is satisfied:
++	       1) the source reg is setup in larger mode than this insn;
++	       2) the source reg is uninitialized;
++	       3) the source reg is passed in as parameter.  */
++	  if (i < dest_op_info->n_chains)
++	    this->analyze_fma_fmul_insn (forest, chain, head);
+ 	}
+     }
+   free (bb_dfs_preorder);
+Index: gcc/config/aarch64/constraints.md
+===================================================================
+--- a/src/gcc/config/aarch64/constraints.md	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/aarch64/constraints.md	(.../branches/gcc-6-branch)
+@@ -21,8 +21,8 @@
+ (define_register_constraint "k" "STACK_REG"
+   "@internal The stack register.")
+ 
+-(define_register_constraint "Ucs" "CALLER_SAVE_REGS"
+-  "@internal The caller save registers.")
++(define_register_constraint "Ucs" "TAILCALL_ADDR_REGS"
++  "@internal Registers suitable for an indirect tail call")
+ 
+ (define_register_constraint "w" "FP_REGS"
+   "Floating point and SIMD vector registers.")
+Index: gcc/config/aarch64/aarch64.c
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/aarch64/aarch64.c	(.../branches/gcc-6-branch)
+@@ -1110,7 +1110,7 @@
+ 	    emit_move_insn (gp_rtx, gen_rtx_HIGH (Pmode, s));
+ 
+ 	    if (mode != GET_MODE (gp_rtx))
+-	      gp_rtx = simplify_gen_subreg (mode, gp_rtx, GET_MODE (gp_rtx), 0);
++             gp_rtx = gen_lowpart (mode, gp_rtx);
+ 	  }
+ 
+ 	if (mode == ptr_mode)
+@@ -5337,7 +5337,7 @@
+ {
+   switch (regclass)
+     {
+-    case CALLER_SAVE_REGS:
++    case TAILCALL_ADDR_REGS:
+     case POINTER_REGS:
+     case GENERAL_REGS:
+     case ALL_REGS:
+@@ -7383,10 +7383,10 @@
+     = aarch64_tune_params.regmove_cost;
+ 
+   /* Caller save and pointer regs are equivalent to GENERAL_REGS.  */
+-  if (to == CALLER_SAVE_REGS || to == POINTER_REGS)
++  if (to == TAILCALL_ADDR_REGS || to == POINTER_REGS)
+     to = GENERAL_REGS;
+ 
+-  if (from == CALLER_SAVE_REGS || from == POINTER_REGS)
++  if (from == TAILCALL_ADDR_REGS || from == POINTER_REGS)
+     from = GENERAL_REGS;
+ 
+   /* Moving between GPR and stack cost is the same as GP2GP.  */
+Index: gcc/config/aarch64/aarch64.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/aarch64/aarch64.h	(.../branches/gcc-6-branch)
+@@ -420,7 +420,7 @@
+ enum reg_class
+ {
+   NO_REGS,
+-  CALLER_SAVE_REGS,
++  TAILCALL_ADDR_REGS,
+   GENERAL_REGS,
+   STACK_REG,
+   POINTER_REGS,
+@@ -435,7 +435,7 @@
+ #define REG_CLASS_NAMES				\
+ {						\
+   "NO_REGS",					\
+-  "CALLER_SAVE_REGS",				\
++  "TAILCALL_ADDR_REGS",				\
+   "GENERAL_REGS",				\
+   "STACK_REG",					\
+   "POINTER_REGS",				\
+@@ -447,7 +447,7 @@
+ #define REG_CLASS_CONTENTS						\
+ {									\
+   { 0x00000000, 0x00000000, 0x00000000 },	/* NO_REGS */		\
+-  { 0x0007ffff, 0x00000000, 0x00000000 },	/* CALLER_SAVE_REGS */	\
++  { 0x0004ffff, 0x00000000, 0x00000000 },	/* TAILCALL_ADDR_REGS */\
+   { 0x7fffffff, 0x00000000, 0x00000003 },	/* GENERAL_REGS */	\
+   { 0x80000000, 0x00000000, 0x00000000 },	/* STACK_REG */		\
+   { 0xffffffff, 0x00000000, 0x00000003 },	/* POINTER_REGS */	\
+@@ -935,4 +935,12 @@
+ extern tree aarch64_fp16_type_node;
+ extern tree aarch64_fp16_ptr_type_node;
+ 
++/* The generic unwind code in libgcc does not initialize the frame pointer.
++   So in order to unwind a function using a frame pointer, the very first
++   function that is unwound must save the frame pointer.  That way the frame
++   pointer is restored and its value is now valid - otherwise _Unwind_GetGR
++   crashes.  Libgcc can now be safely built with -fomit-frame-pointer.  */
++#define LIBGCC2_UNWIND_ATTRIBUTE \
++  __attribute__((optimize ("no-omit-frame-pointer")))
++
+ #endif /* GCC_AARCH64_H */
+Index: gcc/config/rs6000/power6.md
+===================================================================
+--- a/src/gcc/config/rs6000/power6.md	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/rs6000/power6.md	(.../branches/gcc-6-branch)
+@@ -108,7 +108,7 @@
+                   power6-store-update-indexed,\
+                   power6-fpstore,\
+                   power6-fpstore-update"
+-  "store_data_bypass_p")
++  "rs6000_store_data_bypass_p")
+ 
+ (define_insn_reservation "power6-load-ext" 4 ; fx
+   (and (eq_attr "type" "load")
+@@ -128,7 +128,7 @@
+                   power6-store-update-indexed,\
+                   power6-fpstore,\
+                   power6-fpstore-update"
+-  "store_data_bypass_p")
++  "rs6000_store_data_bypass_p")
+ 
+ (define_insn_reservation "power6-load-update" 2 ; fx
+   (and (eq_attr "type" "load")
+@@ -276,7 +276,7 @@
+                   power6-store-update-indexed,\
+                   power6-fpstore,\
+                   power6-fpstore-update"
+-  "store_data_bypass_p")
++  "rs6000_store_data_bypass_p")
+ 
+ (define_insn_reservation "power6-cntlz" 2
+   (and (eq_attr "type" "cntlz")
+@@ -289,7 +289,7 @@
+                   power6-store-update-indexed,\
+                   power6-fpstore,\
+                   power6-fpstore-update"
+-  "store_data_bypass_p")
++  "rs6000_store_data_bypass_p")
+ 
+ (define_insn_reservation "power6-var-rotate" 4
+   (and (eq_attr "type" "shift")
+@@ -355,7 +355,7 @@
+                   power6-store-update-indexed,\
+                   power6-fpstore,\
+                   power6-fpstore-update"
+-  "store_data_bypass_p")
++  "rs6000_store_data_bypass_p")
+ 
+ (define_insn_reservation "power6-delayed-compare" 2 ; N/A
+   (and (eq_attr "type" "shift")
+@@ -420,7 +420,7 @@
+                   power6-store-update-indexed,\
+                   power6-fpstore,\
+                   power6-fpstore-update"
+-  "store_data_bypass_p")
++  "rs6000_store_data_bypass_p")
+ 
+ (define_insn_reservation "power6-idiv" 44
+   (and (eq_attr "type" "div")
+@@ -436,7 +436,7 @@
+ ;                  power6-store-update-indexed,\
+ ;                  power6-fpstore,\
+ ;                  power6-fpstore-update"
+-;  "store_data_bypass_p")
++;  "rs6000_store_data_bypass_p")
+ 
+ (define_insn_reservation "power6-ldiv" 56
+   (and (eq_attr "type" "div")
+@@ -452,7 +452,7 @@
+ ;                  power6-store-update-indexed,\
+ ;                  power6-fpstore,\
+ ;                  power6-fpstore-update"
+-;  "store_data_bypass_p")
++;  "rs6000_store_data_bypass_p")
+ 
+ (define_insn_reservation "power6-mtjmpr" 2
+   (and (eq_attr "type" "mtjmpr,mfjmpr")
+@@ -510,7 +510,7 @@
+ 
+ (define_bypass 1 "power6-fp"
+                  "power6-fpstore,power6-fpstore-update"
+-  "store_data_bypass_p")
++  "rs6000_store_data_bypass_p")
+ 
+ (define_insn_reservation "power6-fpcompare" 8
+   (and (eq_attr "type" "fpcompare")
+Index: gcc/config/rs6000/ppc-asm.h
+===================================================================
+--- a/src/gcc/config/rs6000/ppc-asm.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/rs6000/ppc-asm.h	(.../branches/gcc-6-branch)
+@@ -120,7 +120,7 @@
+ #define f47	47
+ #define f48	48
+ #define f49	49
+-#define f50	30
++#define f50	50
+ #define f51	51
+ #define f52	52
+ #define f53	53
+@@ -222,7 +222,7 @@
+ #define vs47	47
+ #define vs48	48
+ #define vs49	49
+-#define vs50	30
++#define vs50	50
+ #define vs51	51
+ #define vs52	52
+ #define vs53	53
+Index: gcc/config/rs6000/rs6000-protos.h
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000-protos.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/rs6000/rs6000-protos.h	(.../branches/gcc-6-branch)
+@@ -136,7 +136,6 @@
+ extern int rs6000_emit_cmove (rtx, rtx, rtx, rtx);
+ extern int rs6000_emit_vector_cond_expr (rtx, rtx, rtx, rtx, rtx, rtx);
+ extern void rs6000_emit_minmax (rtx, enum rtx_code, rtx, rtx);
+-extern void rs6000_split_signbit (rtx, rtx);
+ extern void rs6000_expand_atomic_compare_and_swap (rtx op[]);
+ extern void rs6000_expand_atomic_exchange (rtx op[]);
+ extern void rs6000_expand_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
+@@ -216,6 +215,7 @@
+ extern void rs6000_aix_asm_output_dwarf_table_ref (char *);
+ extern void get_ppc476_thunk_name (char name[32]);
+ extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins);
++extern int rs6000_store_data_bypass_p (rtx_insn *, rtx_insn *);
+ extern HOST_WIDE_INT rs6000_builtin_mask_calculate (void);
+ extern void rs6000_asm_output_dwarf_pcrel (FILE *file, int size,
+ 					   const char *label);
+@@ -229,6 +229,7 @@
+ #ifdef TREE_CODE
+ extern bool rs6000_pragma_target_parse (tree, tree);
+ #endif
++extern void rs6000_activate_target_options (tree new_tree);
+ extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT, HOST_WIDE_INT);
+ extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT,
+ 						HOST_WIDE_INT);
+Index: gcc/config/rs6000/ppc-auxv.h
+===================================================================
+--- a/src/gcc/config/rs6000/ppc-auxv.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/rs6000/ppc-auxv.h	(.../branches/gcc-6-branch)
+@@ -89,6 +89,9 @@
+ #define PPC_FEATURE2_HTM_NOSC       0x01000000
+ #define PPC_FEATURE2_ARCH_3_00      0x00800000
+ #define PPC_FEATURE2_HAS_IEEE128    0x00400000
++#define PPC_FEATURE2_DARN           0x00200000
++#define PPC_FEATURE2_SCV            0x00100000
++#define PPC_FEATURE2_HTM_NO_SUSPEND 0x00080000
+ 
+ 
+ /* Thread Control Block (TCB) offsets of the AT_PLATFORM, AT_HWCAP and
+Index: gcc/config/rs6000/rs6000-c.c
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000-c.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/rs6000/rs6000-c.c	(.../branches/gcc-6-branch)
+@@ -428,6 +428,9 @@
+     builtin_define ("__FLOAT128__");
+   if (TARGET_FLOAT128_HW)
+     builtin_define ("__FLOAT128_HARDWARE__");
++#ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
++  builtin_define ("__BUILTIN_CPU_SUPPORTS__");
++#endif
+ 
+   if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM)
+     {
+Index: gcc/config/rs6000/rs6000.c
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/rs6000/rs6000.c	(.../branches/gcc-6-branch)
+@@ -361,11 +361,14 @@
+   { "ebb",		PPC_FEATURE2_HAS_EBB,		1 },
+   { "htm",		PPC_FEATURE2_HAS_HTM,		1 },
+   { "htm-nosc",		PPC_FEATURE2_HTM_NOSC,		1 },
++  { "htm-no-suspend",	PPC_FEATURE2_HTM_NO_SUSPEND,	1 },
+   { "isel",		PPC_FEATURE2_HAS_ISEL,		1 },
+   { "tar",		PPC_FEATURE2_HAS_TAR,		1 },
+   { "vcrypto",		PPC_FEATURE2_HAS_VEC_CRYPTO,	1 },
+   { "arch_3_00",	PPC_FEATURE2_ARCH_3_00,		1 },
+-  { "ieee128",		PPC_FEATURE2_HAS_IEEE128,	1 }
++  { "ieee128",		PPC_FEATURE2_HAS_IEEE128,	1 },
++  { "darn",		PPC_FEATURE2_DARN,		1 },
++  { "scv",		PPC_FEATURE2_SCV,		1 }
+ };
+ 
+ /* Newer LIBCs explicitly export this symbol to declare that they provide
+@@ -494,6 +497,91 @@
+ 	  != 0);
+ }
+ 
++/* Given that there exists at least one variable that is set (produced)
++   by OUT_INSN and read (consumed) by IN_INSN, return true iff
++   IN_INSN represents one or more memory store operations and none of
++   the variables set by OUT_INSN is used by IN_INSN as the address of a
++   store operation.  If either IN_INSN or OUT_INSN does not represent
++   a "single" RTL SET expression (as loosely defined by the
++   implementation of the single_set function) or a PARALLEL with only
++   SETs, CLOBBERs, and USEs inside, this function returns false.
++
++   This rs6000-specific version of store_data_bypass_p checks for
++   certain conditions that result in assertion failures (and internal
++   compiler errors) in the generic store_data_bypass_p function and
++   returns false rather than calling store_data_bypass_p if one of the
++   problematic conditions is detected.  */
++
++int
++rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
++{
++  rtx out_set, in_set;
++  rtx out_pat, in_pat;
++  rtx out_exp, in_exp;
++  int i, j;
++
++  in_set = single_set (in_insn);
++  if (in_set)
++    {
++      if (MEM_P (SET_DEST (in_set)))
++	{
++	  out_set = single_set (out_insn);
++	  if (!out_set)
++	    {
++	      out_pat = PATTERN (out_insn);
++	      if (GET_CODE (out_pat) == PARALLEL)
++		{
++		  for (i = 0; i < XVECLEN (out_pat, 0); i++)
++		    {
++		      out_exp = XVECEXP (out_pat, 0, i);
++		      if ((GET_CODE (out_exp) == CLOBBER)
++			  || (GET_CODE (out_exp) == USE))
++			continue;
++		      else if (GET_CODE (out_exp) != SET)
++			return false;
++		    }
++		}
++	    }
++	}
++    }
++  else
++    {
++      in_pat = PATTERN (in_insn);
++      if (GET_CODE (in_pat) != PARALLEL)
++	return false;
++
++      for (i = 0; i < XVECLEN (in_pat, 0); i++)
++	{
++	  in_exp = XVECEXP (in_pat, 0, i);
++	  if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
++	    continue;
++	  else if (GET_CODE (in_exp) != SET)
++	    return false;
++
++	  if (MEM_P (SET_DEST (in_exp)))
++	    {
++	      out_set = single_set (out_insn);
++	      if (!out_set)
++		{
++		  out_pat = PATTERN (out_insn);
++		  if (GET_CODE (out_pat) != PARALLEL)
++		    return false;
++		  for (j = 0; j < XVECLEN (out_pat, 0); j++)
++		    {
++		      out_exp = XVECEXP (out_pat, 0, j);
++		      if ((GET_CODE (out_exp) == CLOBBER)
++			  || (GET_CODE (out_exp) == USE))
++			continue;
++		      else if (GET_CODE (out_exp) != SET)
++			return false;
++		    }
++		}
++	    }
++	}
++    }
++  return store_data_bypass_p (out_insn, in_insn);
++}
++
+ /* Return true if we have D-form addressing in altivec registers.  */
+ static inline bool
+ mode_supports_vmx_dform (machine_mode mode)
+@@ -3717,13 +3805,8 @@
+ rs6000_option_override_internal (bool global_init_p)
+ {
+   bool ret = true;
+-  bool have_cpu = false;
+-
+-  /* The default cpu requested at configure time, if any.  */
+-  const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT;
+-
+   HOST_WIDE_INT set_masks;
+-  int cpu_index;
++  int cpu_index = -1;
+   int tune_index;
+   struct cl_target_option *main_target_opt
+     = ((global_init_p || target_option_default_node == NULL)
+@@ -3800,42 +3883,20 @@
+      with -mtune on the command line.  Process a '--with-cpu' configuration
+      request as an implicit --cpu.  */
+   if (rs6000_cpu_index >= 0)
+-    {
+-      cpu_index = rs6000_cpu_index;
+-      have_cpu = true;
+-    }
++    cpu_index = rs6000_cpu_index;
+   else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
+-    {
+-      rs6000_cpu_index = cpu_index = main_target_opt->x_rs6000_cpu_index;
+-      have_cpu = true;
+-    }
+-  else if (implicit_cpu)
+-    {
+-      rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (implicit_cpu);
+-      have_cpu = true;
+-    }
+-  else
+-    {
+-      /* PowerPC 64-bit LE requires at least ISA 2.07.  */
+-      const char *default_cpu = ((!TARGET_POWERPC64)
+-				 ? "powerpc"
+-				 : ((BYTES_BIG_ENDIAN)
+-				    ? "powerpc64"
+-				    : "powerpc64le"));
++    cpu_index = main_target_opt->x_rs6000_cpu_index;
++  else if (OPTION_TARGET_CPU_DEFAULT)
++    cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
+ 
+-      rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu);
+-      have_cpu = false;
+-    }
+-
+-  gcc_assert (cpu_index >= 0);
+-
+   /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
+      compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
+      with those from the cpu, except for options that were explicitly set.  If
+      we don't have a cpu, do not override the target bits set in
+      TARGET_DEFAULT.  */
+-  if (have_cpu)
++  if (cpu_index >= 0)
+     {
++      rs6000_cpu_index = cpu_index;
+       rs6000_isa_flags &= ~set_masks;
+       rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
+ 			   & set_masks);
+@@ -3849,14 +3910,26 @@
+ 
+ 	 If there is a TARGET_DEFAULT, use that.  Otherwise fall back to using
+ 	 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults.  */
+-      HOST_WIDE_INT flags = ((TARGET_DEFAULT) ? TARGET_DEFAULT
+-			     : processor_target_table[cpu_index].target_enable);
++      HOST_WIDE_INT flags;
++      if (TARGET_DEFAULT)
++	flags = TARGET_DEFAULT;
++      else
++	{
++	  /* PowerPC 64-bit LE requires at least ISA 2.07.  */
++	  const char *default_cpu = (!TARGET_POWERPC64
++				     ? "powerpc"
++				     : (BYTES_BIG_ENDIAN
++					? "powerpc64"
++					: "powerpc64le"));
++	  int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
++	  flags = processor_target_table[default_cpu_index].target_enable;
++	}
+       rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
+     }
+ 
+   if (rs6000_tune_index >= 0)
+     tune_index = rs6000_tune_index;
+-  else if (have_cpu)
++  else if (cpu_index >= 0)
+     rs6000_tune_index = tune_index = cpu_index;
+   else
+     {
+@@ -3868,7 +3941,7 @@
+       for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
+ 	if (processor_target_table[i].processor == tune_proc)
+ 	  {
+-	    rs6000_tune_index = tune_index = i;
++	    tune_index = i;
+ 	    break;
+ 	  }
+     }
+@@ -4075,9 +4148,22 @@
+ 
+   if (TARGET_P8_VECTOR && !TARGET_VSX)
+     {
+-      if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
++      if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
++	  && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
+ 	error ("-mpower8-vector requires -mvsx");
+-      rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
++      else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
++	{
++	  rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
++	  if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
++	    rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
++	}
++      else
++	{
++	  /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
++	     not explicit.  */
++	  rs6000_isa_flags |= OPTION_MASK_VSX;
++	  rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
++	}
+     }
+ 
+   if (TARGET_VSX_TIMODE && !TARGET_VSX)
+@@ -4258,9 +4344,22 @@
+ 	 error messages.  However, if users have managed to select
+ 	 power9-vector without selecting power8-vector, they
+ 	 already know about undocumented flags.  */
+-      if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
++      if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
++	  (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
+ 	error ("-mpower9-vector requires -mpower8-vector");
+-      rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
++      else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
++	{
++	  rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
++	  if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
++	    rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
++	}
++      else
++	{
++	  /* OPTION_MASK_P9_VECTOR is explicit and
++	     OPTION_MASK_P8_VECTOR is not explicit.  */
++	  rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
++	  rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
++	}
+     }
+ 
+   /* -mpower9-dform turns on both -mpower9-dform-scalar and
+@@ -4289,12 +4388,54 @@
+ 	 error messages.  However, if users have managed to select
+ 	 power9-dform without selecting power9-vector, they
+ 	 already know about undocumented flags.  */
+-      if (rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR)
++      if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR)
++	  && (rs6000_isa_flags_explicit & (OPTION_MASK_P9_DFORM_SCALAR
++					   | OPTION_MASK_P9_DFORM_VECTOR)))
+ 	error ("-mpower9-dform requires -mpower9-vector");
+-      rs6000_isa_flags &= ~(OPTION_MASK_P9_DFORM_SCALAR
+-			    | OPTION_MASK_P9_DFORM_VECTOR);
++      else if (rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR)
++	{
++	  rs6000_isa_flags &=
++	    ~(OPTION_MASK_P9_DFORM_SCALAR | OPTION_MASK_P9_DFORM_VECTOR);
++	  rs6000_isa_flags_explicit |=
++	    (OPTION_MASK_P9_DFORM_SCALAR | OPTION_MASK_P9_DFORM_VECTOR);
++	}
++      else
++	{
++	  /* We know that OPTION_MASK_P9_VECTOR is not explicit and
++	     OPTION_MASK_P9_DFORM_SCALAR or OPTION_MASK_P9_DORM_VECTOR
++	     may be explicit.  */
++	  rs6000_isa_flags |= OPTION_MASK_P9_VECTOR;
++	  rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
++	}
+     }
+ 
++  if ((TARGET_P9_DFORM_SCALAR || TARGET_P9_DFORM_VECTOR)
++      && !TARGET_DIRECT_MOVE)
++    {
++      /* We prefer to not mention undocumented options in
++	 error messages.  However, if users have managed to select
++	 power9-dform without selecting power9-vector, they
++	 already know about undocumented flags.  */
++      if ((rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
++	  && ((rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR) ||
++	      (rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_SCALAR) ||
++	      (TARGET_P9_DFORM_BOTH == 1)))
++	error ("-mpower9-dform, -mpower9-dform-vector, -mpower9-dform-scalar"
++	       " require -mdirect-move");
++      else if ((rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE) == 0)
++	{
++	  rs6000_isa_flags |= OPTION_MASK_DIRECT_MOVE;
++	  rs6000_isa_flags_explicit |= OPTION_MASK_DIRECT_MOVE;
++	}
++      else
++	{
++	  rs6000_isa_flags &=
++	    ~(OPTION_MASK_P9_DFORM_SCALAR | OPTION_MASK_P9_DFORM_VECTOR);
++	  rs6000_isa_flags_explicit |=
++	    (OPTION_MASK_P9_DFORM_SCALAR | OPTION_MASK_P9_DFORM_VECTOR);
++	}
++    }
++
+   if (TARGET_P9_DFORM_SCALAR && !TARGET_UPPER_REGS_DF)
+     {
+       /* We prefer to not mention undocumented options in
+@@ -4588,7 +4729,7 @@
+ 
+     default:
+ 
+-      if (have_cpu && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL))
++      if (cpu_index >= 0 && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL))
+ 	rs6000_isa_flags &= ~OPTION_MASK_ISEL;
+ 
+       break;
+@@ -6923,7 +7064,7 @@
+     {
+       if (TARGET_P9_VECTOR)
+ 	x = gen_rtx_UNSPEC (mode,
+-			    gen_rtvec (3, target, reg,
++			    gen_rtvec (3, reg, target,
+ 				       force_reg (V16QImode, x)),
+ 			    UNSPEC_VPERMR);
+       else
+@@ -9436,7 +9577,7 @@
+ {
+   /* Use ROTATE instead of VEC_SELECT on IEEE 128-bit floating point, and
+      128-bit integers if they are allowed in VSX registers.  */
+-  if (FLOAT128_VECTOR_P (mode) || mode == TImode)
++  if (FLOAT128_VECTOR_P (mode) || mode == TImode || mode == V1TImode)
+     return gen_rtx_ROTATE (mode, source, GEN_INT (64));
+   else
+     {
+@@ -14162,6 +14303,8 @@
+       emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
+       emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
+     }
++  else
++    gcc_unreachable ();
+ 
+   /* Record that we have expanded a CPU builtin, so that we can later
+      emit a reference to the special symbol exported by LIBC to ensure we
+@@ -14169,6 +14312,9 @@
+   cpu_builtin_p = true;
+ 
+ #else
++  warning (0, "%s needs GLIBC (2.23 and newer) that exports hardware "
++	   "capability bits", rs6000_builtin_info[(size_t) fcode].name);
++  
+   /* For old LIBCs, always return FALSE.  */
+   emit_move_insn (target, GEN_INT (0));
+ #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
+@@ -21196,7 +21342,7 @@
+ 
+ 	    /* Fall through.  Must be [reg+reg].  */
+ 	  }
+-	if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x))
++	if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x))
+ 	    && GET_CODE (tmp) == AND
+ 	    && GET_CODE (XEXP (tmp, 1)) == CONST_INT
+ 	    && INTVAL (XEXP (tmp, 1)) == -16)
+@@ -23159,49 +23305,6 @@
+     emit_move_insn (dest, target);
+ }
+ 
+-/* Split a signbit operation on 64-bit machines with direct move.  Also allow
+-   for the value to come from memory or if it is already loaded into a GPR.  */
+-
+-void
+-rs6000_split_signbit (rtx dest, rtx src)
+-{
+-  machine_mode d_mode = GET_MODE (dest);
+-  machine_mode s_mode = GET_MODE (src);
+-  rtx dest_di = (d_mode == DImode) ? dest : gen_lowpart (DImode, dest);
+-  rtx shift_reg = dest_di;
+-
+-  gcc_assert (FLOAT128_IEEE_P (s_mode) && TARGET_POWERPC64);
+-
+-  if (MEM_P (src))
+-    {
+-      rtx mem = (WORDS_BIG_ENDIAN
+-		 ? adjust_address (src, DImode, 0)
+-		 : adjust_address (src, DImode, 8));
+-      emit_insn (gen_rtx_SET (dest_di, mem));
+-    }
+-
+-  else
+-    {
+-      unsigned int r = reg_or_subregno (src);
+-
+-      if (INT_REGNO_P (r))
+-	shift_reg = gen_rtx_REG (DImode, r + (BYTES_BIG_ENDIAN == 0));
+-
+-      else
+-	{
+-	  /* Generate the special mfvsrd instruction to get it in a GPR.  */
+-	  gcc_assert (VSX_REGNO_P (r));
+-	  if (s_mode == KFmode)
+-	    emit_insn (gen_signbitkf2_dm2 (dest_di, src));
+-	  else
+-	    emit_insn (gen_signbittf2_dm2 (dest_di, src));
+-	}
+-    }
+-
+-  emit_insn (gen_lshrdi3 (dest_di, shift_reg, GEN_INT (63)));
+-  return;
+-}
+-
+ /* A subroutine of the atomic operation splitters.  Jump to LABEL if
+    COND is true.  Mark the jump as unlikely to be taken.  */
+ 
+@@ -25020,24 +25123,23 @@
+ rtx
+ rs6000_return_addr (int count, rtx frame)
+ {
+-  /* Currently we don't optimize very well between prolog and body
+-     code and for PIC code the code can be actually quite bad, so
+-     don't try to be too clever here.  */
++  /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
++     is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin.  */
+   if (count != 0
+       || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
+     {
+       cfun->machine->ra_needs_full_frame = 1;
+ 
+-      return
+-	gen_rtx_MEM
+-	  (Pmode,
+-	   memory_address
+-	   (Pmode,
+-	    plus_constant (Pmode,
+-			   copy_to_reg
+-			   (gen_rtx_MEM (Pmode,
+-					 memory_address (Pmode, frame))),
+-			   RETURN_ADDRESS_OFFSET)));
++      if (count == 0)
++	/* FRAME is set to frame_pointer_rtx by the generic code, but that
++	   is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD.  */
++	frame = stack_pointer_rtx;
++      rtx prev_frame_addr = memory_address (Pmode, frame);
++      rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
++      rtx lr_save_off = plus_constant (Pmode,
++				       prev_frame, RETURN_ADDRESS_OFFSET);
++      rtx lr_save_addr = memory_address (Pmode, lr_save_off);
++      return gen_rtx_MEM (Pmode, lr_save_addr);
+     }
+ 
+   cfun->machine->ra_need_lr = 1;
+@@ -29012,8 +29114,9 @@
+ 	  emit_insn_after (pat, get_insns ());
+ 	  pop_topmost_sequence ();
+ 	}
+-      return plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
+-			    FIRST_PARM_OFFSET (current_function_decl));
++      rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
++			       FIRST_PARM_OFFSET (current_function_decl));
++      return copy_to_reg (ret);
+     }
+   return virtual_incoming_args_rtx;
+ }
+@@ -30187,7 +30290,7 @@
+                   case TYPE_LOAD:
+                   case TYPE_CNTLZ:
+                     {
+-                      if (! store_data_bypass_p (dep_insn, insn))
++                      if (! rs6000_store_data_bypass_p (dep_insn, insn))
+                         return get_attr_sign_extend (dep_insn)
+                                == SIGN_EXTEND_YES ? 6 : 4;
+                       break;
+@@ -30194,7 +30297,7 @@
+                     }
+                   case TYPE_SHIFT:
+                     {
+-                      if (! store_data_bypass_p (dep_insn, insn))
++                      if (! rs6000_store_data_bypass_p (dep_insn, insn))
+                         return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
+                                6 : 3;
+                       break;
+@@ -30205,7 +30308,7 @@
+                   case TYPE_EXTS:
+                   case TYPE_INSERT:
+                     {
+-                      if (! store_data_bypass_p (dep_insn, insn))
++                      if (! rs6000_store_data_bypass_p (dep_insn, insn))
+                         return 3;
+                       break;
+                     }
+@@ -30214,19 +30317,19 @@
+                   case TYPE_FPSTORE:
+                     {
+                       if (get_attr_update (dep_insn) == UPDATE_YES
+-                          && ! store_data_bypass_p (dep_insn, insn))
++                          && ! rs6000_store_data_bypass_p (dep_insn, insn))
+                         return 3;
+                       break;
+                     }
+                   case TYPE_MUL:
+                     {
+-                      if (! store_data_bypass_p (dep_insn, insn))
++                      if (! rs6000_store_data_bypass_p (dep_insn, insn))
+                         return 17;
+                       break;
+                     }
+                   case TYPE_DIV:
+                     {
+-                      if (! store_data_bypass_p (dep_insn, insn))
++                      if (! rs6000_store_data_bypass_p (dep_insn, insn))
+                         return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
+                       break;
+                     }
+@@ -32541,8 +32644,8 @@
+     {
+       if (!toc_initialized)
+ 	{
+-	  toc_initialized = 1;
+ 	  fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
++	  ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
+ 	  (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
+ 	  fprintf (asm_out_file, "\t.tc ");
+ 	  ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
+@@ -32550,8 +32653,10 @@
+ 	  fprintf (asm_out_file, "\n");
+ 
+ 	  fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
++	  ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
+ 	  ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
+ 	  fprintf (asm_out_file, " = .+32768\n");
++	  toc_initialized = 1;
+ 	}
+       else
+ 	fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
+@@ -32558,12 +32663,20 @@
+     }
+   else if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
+ 	   && !TARGET_RELOCATABLE)
+-    fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
++    {
++      fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
++      if (!toc_initialized)
++	{
++	  ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
++	  toc_initialized = 1;
++	}
++    }
+   else
+     {
+       fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
+       if (!toc_initialized)
+ 	{
++	  ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
+ 	  ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
+ 	  fprintf (asm_out_file, " = .+32768\n");
+ 	  toc_initialized = 1;
+@@ -34214,14 +34327,16 @@
+ 	  *total = COSTS_N_INSNS (1);
+ 	  return true;
+ 	}
++      /* FALLTHRU */
++
++    case GT:
++    case LT:
++    case UNORDERED:
+       if (outer_code == SET)
+ 	{
+ 	  if (XEXP (x, 1) == const0_rtx)
+ 	    {
+-	      if (TARGET_ISEL && !TARGET_MFCRF)
+-		*total = COSTS_N_INSNS (8);
+-	      else
+-		*total = COSTS_N_INSNS (2);
++	      *total = COSTS_N_INSNS (2);
+ 	      return true;
+ 	    }
+ 	  else
+@@ -34230,19 +34345,6 @@
+ 	      return false;
+ 	    }
+ 	}
+-      /* FALLTHRU */
+-
+-    case GT:
+-    case LT:
+-    case UNORDERED:
+-      if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
+-	{
+-	  if (TARGET_ISEL && !TARGET_MFCRF)
+-	    *total = COSTS_N_INSNS (8);
+-	  else
+-	    *total = COSTS_N_INSNS (2);
+-	  return true;
+-	}
+       /* CC COMPARE.  */
+       if (outer_code == COMPARE)
+ 	{
+@@ -34901,7 +35003,7 @@
+ 
+   if (TARGET_P9_VECTOR)
+     {
+-      unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op0, op1, sel),
++      unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, sel),
+ 			       UNSPEC_VPERMR);
+     }
+   else
+@@ -36224,9 +36326,9 @@
+ {
+   struct cl_target_option cur_target;
+   bool ret;
+-  tree old_optimize = build_optimization_node (&global_options);
++  tree old_optimize;
+   tree new_target, new_optimize;
+-  tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
++  tree func_optimize;
+ 
+   gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
+ 
+@@ -36353,6 +36455,7 @@
+     }
+ 
+   target_option_current_node = cur_tree;
++  rs6000_activate_target_options (target_option_current_node);
+ 
+   /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
+      change the macros that are defined.  */
+@@ -36390,6 +36493,22 @@
+ /* Remember the last target of rs6000_set_current_function.  */
+ static GTY(()) tree rs6000_previous_fndecl;
+ 
++/* Restore target's globals from NEW_TREE and invalidate the
++   rs6000_previous_fndecl cache.  */
++
++void
++rs6000_activate_target_options (tree new_tree)
++{
++  cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
++  if (TREE_TARGET_GLOBALS (new_tree))
++    restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
++  else if (new_tree == target_option_default_node)
++    restore_target_globals (&default_target_globals);
++  else
++    TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
++  rs6000_previous_fndecl = NULL_TREE;
++}
++
+ /* Establish appropriate back-end context for processing the function
+    FNDECL.  The argument might be NULL to indicate processing at top
+    level, outside of any function scope.  */
+@@ -36396,17 +36515,8 @@
+ static void
+ rs6000_set_current_function (tree fndecl)
+ {
+-  tree old_tree = (rs6000_previous_fndecl
+-		   ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl)
+-		   : NULL_TREE);
+-
+-  tree new_tree = (fndecl
+-		   ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
+-		   : NULL_TREE);
+-
+   if (TARGET_DEBUG_TARGET)
+     {
+-      bool print_final = false;
+       fprintf (stderr, "\n==================== rs6000_set_current_function");
+ 
+       if (fndecl)
+@@ -36419,11 +36529,43 @@
+ 	fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
+ 
+       fprintf (stderr, "\n");
++    }
++
++  /* Only change the context if the function changes.  This hook is called
++     several times in the course of compiling a function, and we don't want to
++     slow things down too much or call target_reinit when it isn't safe.  */
++  if (fndecl == rs6000_previous_fndecl)
++    return;
++
++  tree old_tree;
++  if (rs6000_previous_fndecl == NULL_TREE)
++    old_tree = target_option_current_node;
++  else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
++    old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
++  else
++    old_tree = target_option_default_node;
++
++  tree new_tree;
++  if (fndecl == NULL_TREE)
++    {
++      if (old_tree != target_option_current_node)
++	new_tree = target_option_current_node;
++      else
++	new_tree = NULL_TREE;
++    }
++  else
++    {
++      new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
++      if (new_tree == NULL_TREE)
++	new_tree = target_option_default_node;
++    }
++
++  if (TARGET_DEBUG_TARGET)
++    {
+       if (new_tree)
+ 	{
+ 	  fprintf (stderr, "\nnew fndecl target specific options:\n");
+ 	  debug_tree (new_tree);
+-	  print_final = true;
+ 	}
+ 
+       if (old_tree)
+@@ -36430,47 +36572,17 @@
+ 	{
+ 	  fprintf (stderr, "\nold fndecl target specific options:\n");
+ 	  debug_tree (old_tree);
+-	  print_final = true;
+ 	}
+ 
+-      if (print_final)
++      if (old_tree != NULL_TREE || new_tree != NULL_TREE)
+ 	fprintf (stderr, "--------------------\n");
+     }
+ 
+-  /* Only change the context if the function changes.  This hook is called
+-     several times in the course of compiling a function, and we don't want to
+-     slow things down too much or call target_reinit when it isn't safe.  */
+-  if (fndecl && fndecl != rs6000_previous_fndecl)
+-    {
+-      rs6000_previous_fndecl = fndecl;
+-      if (old_tree == new_tree)
+-	;
++  if (new_tree && old_tree != new_tree)
++    rs6000_activate_target_options (new_tree);
+ 
+-      else if (new_tree && new_tree != target_option_default_node)
+-	{
+-	  cl_target_option_restore (&global_options,
+-				    TREE_TARGET_OPTION (new_tree));
+-	  if (TREE_TARGET_GLOBALS (new_tree))
+-	    restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
+-	  else
+-	    TREE_TARGET_GLOBALS (new_tree)
+-	      = save_target_globals_default_opts ();
+-	}
+-
+-      else if (old_tree && old_tree != target_option_default_node)
+-	{
+-	  new_tree = target_option_current_node;
+-	  cl_target_option_restore (&global_options,
+-				    TREE_TARGET_OPTION (new_tree));
+-	  if (TREE_TARGET_GLOBALS (new_tree))
+-	    restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
+-	  else if (new_tree == target_option_default_node)
+-	    restore_target_globals (&default_target_globals);
+-	  else
+-	    TREE_TARGET_GLOBALS (new_tree)
+-	      = save_target_globals_default_opts ();
+-	}
+-    }
++  if (fndecl)
++    rs6000_previous_fndecl = fndecl;
+ }
+ 
+ 
+@@ -38353,6 +38465,38 @@
+   return 1;
+ }
+ 
++/* Return 1 iff UID, known to reference a swap, is both fed by a load
++   and a feeder of a store.  */
++static unsigned int
++swap_feeds_both_load_and_store (swap_web_entry *insn_entry)
++{
++  rtx insn = insn_entry->insn;
++  struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn);
++  df_ref def, use;
++  struct df_link *link = 0;
++  rtx_insn *load = 0, *store = 0;
++  bool fed_by_load = 0;
++  bool feeds_store = 0;
++
++  FOR_EACH_INSN_INFO_USE (use, insn_info)
++    {
++      link = DF_REF_CHAIN (use);
++      load = DF_REF_INSN (link->ref);
++      if (insn_is_load_p (load) && insn_is_swap_p (load))
++	fed_by_load = 1;
++    }
++
++  FOR_EACH_INSN_INFO_DEF (def, insn_info)
++    {
++      link = DF_REF_CHAIN (def);
++      store = DF_REF_INSN (link->ref);
++      if (insn_is_store_p (store) && insn_is_swap_p (store))
++	feeds_store = 1;
++    }
++
++  return fed_by_load && feeds_store;
++}
++
+ /* Return TRUE if insn is a swap fed by a load from the constant pool.  */
+ static bool
+ const_load_sequence_p (swap_web_entry *insn_entry, rtx insn)
+@@ -38551,6 +38695,7 @@
+ 	  {
+ 	  default:
+ 	    break;
++	  case UNSPEC_VBPERMQ:
+ 	  case UNSPEC_VMRGH_DIRECT:
+ 	  case UNSPEC_VMRGL_DIRECT:
+ 	  case UNSPEC_VPACK_SIGN_SIGN_SAT:
+@@ -39509,6 +39654,14 @@
+ 	  && !insn_entry[i].is_swap && !insn_entry[i].is_swappable)
+ 	root->web_not_optimizable = 1;
+ 
++      /* If we have a swap that is both fed by a permuting load
++	 and a feeder of a permuting store, then the optimization
++	 isn't appropriate.  (Consider vec_xl followed by vec_xst_be.)  */
++      else if (insn_entry[i].is_swap && !insn_entry[i].is_load
++	       && !insn_entry[i].is_store
++	       && swap_feeds_both_load_and_store (&insn_entry[i]))
++	root->web_not_optimizable = 1;
++
+       /* If we have permuting loads or stores that are not accompanied
+ 	 by a register swap, the optimization isn't appropriate.  */
+       else if (insn_entry[i].is_load && insn_entry[i].is_swap)
+Index: gcc/config/rs6000/vsx.md
+===================================================================
+--- a/src/gcc/config/rs6000/vsx.md	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/rs6000/vsx.md	(.../branches/gcc-6-branch)
+@@ -24,15 +24,12 @@
+ ;; Iterator for the 2 64-bit vector types
+ (define_mode_iterator VSX_D [V2DF V2DI])
+ 
+-;; Iterator for the 2 64-bit vector types + 128-bit types that are loaded with
+-;; lxvd2x to properly handle swapping words on little endian
+-(define_mode_iterator VSX_LE [V2DF V2DI V1TI])
+-
+ ;; Mode iterator to handle swapping words on little endian for the 128-bit
+ ;; types that goes in a single vector register.
+ (define_mode_iterator VSX_LE_128 [(KF   "FLOAT128_VECTOR_P (KFmode)")
+ 				  (TF   "FLOAT128_VECTOR_P (TFmode)")
+-				  (TI	"TARGET_VSX_TIMODE")])
++				  (TI	"TARGET_VSX_TIMODE")
++				  V1TI])
+ 
+ ;; Iterator for the 2 32-bit vector types
+ (define_mode_iterator VSX_W [V4SF V4SI])
+@@ -300,8 +297,8 @@
+ ;; The patterns for LE permuted loads and stores come before the general
+ ;; VSX moves so they match first.
+ (define_insn_and_split "*vsx_le_perm_load_<mode>"
+-  [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>")
+-        (match_operand:VSX_LE 1 "memory_operand" "Z"))]
++  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>")
++        (match_operand:VSX_D 1 "indexed_or_indirect_operand" "Z"))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
+   "#"
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
+@@ -324,7 +321,7 @@
+ 
+ (define_insn_and_split "*vsx_le_perm_load_<mode>"
+   [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>")
+-        (match_operand:VSX_W 1 "memory_operand" "Z"))]
++        (match_operand:VSX_W 1 "indexed_or_indirect_operand" "Z"))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
+   "#"
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
+@@ -349,7 +346,7 @@
+ 
+ (define_insn_and_split "*vsx_le_perm_load_v8hi"
+   [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa")
+-        (match_operand:V8HI 1 "memory_operand" "Z"))]
++        (match_operand:V8HI 1 "indexed_or_indirect_operand" "Z"))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
+   "#"
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
+@@ -378,7 +375,7 @@
+ 
+ (define_insn_and_split "*vsx_le_perm_load_v16qi"
+   [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
+-        (match_operand:V16QI 1 "memory_operand" "Z"))]
++        (match_operand:V16QI 1 "indexed_or_indirect_operand" "Z"))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
+   "#"
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
+@@ -414,8 +411,8 @@
+    (set_attr "length" "8")])
+ 
+ (define_insn "*vsx_le_perm_store_<mode>"
+-  [(set (match_operand:VSX_LE 0 "memory_operand" "=Z")
+-        (match_operand:VSX_LE 1 "vsx_register_operand" "+<VSa>"))]
++  [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "=Z")
++        (match_operand:VSX_D 1 "vsx_register_operand" "+<VSa>"))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
+   "#"
+   [(set_attr "type" "vecstore")
+@@ -422,8 +419,8 @@
+    (set_attr "length" "12")])
+ 
+ (define_split
+-  [(set (match_operand:VSX_LE 0 "memory_operand" "")
+-        (match_operand:VSX_LE 1 "vsx_register_operand" ""))]
++  [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "")
++        (match_operand:VSX_D 1 "vsx_register_operand" ""))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
+   [(set (match_dup 2)
+         (vec_select:<MODE>
+@@ -441,8 +438,8 @@
+ ;; The post-reload split requires that we re-permute the source
+ ;; register in case it is still live.
+ (define_split
+-  [(set (match_operand:VSX_LE 0 "memory_operand" "")
+-        (match_operand:VSX_LE 1 "vsx_register_operand" ""))]
++  [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "")
++        (match_operand:VSX_D 1 "vsx_register_operand" ""))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
+   [(set (match_dup 1)
+         (vec_select:<MODE>
+@@ -459,7 +456,7 @@
+   "")
+ 
+ (define_insn "*vsx_le_perm_store_<mode>"
+-  [(set (match_operand:VSX_W 0 "memory_operand" "=Z")
++  [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "=Z")
+         (match_operand:VSX_W 1 "vsx_register_operand" "+<VSa>"))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
+   "#"
+@@ -467,7 +464,7 @@
+    (set_attr "length" "12")])
+ 
+ (define_split
+-  [(set (match_operand:VSX_W 0 "memory_operand" "")
++  [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "")
+         (match_operand:VSX_W 1 "vsx_register_operand" ""))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
+   [(set (match_dup 2)
+@@ -488,7 +485,7 @@
+ ;; The post-reload split requires that we re-permute the source
+ ;; register in case it is still live.
+ (define_split
+-  [(set (match_operand:VSX_W 0 "memory_operand" "")
++  [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "")
+         (match_operand:VSX_W 1 "vsx_register_operand" ""))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
+   [(set (match_dup 1)
+@@ -509,7 +506,7 @@
+   "")
+ 
+ (define_insn "*vsx_le_perm_store_v8hi"
+-  [(set (match_operand:V8HI 0 "memory_operand" "=Z")
++  [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "=Z")
+         (match_operand:V8HI 1 "vsx_register_operand" "+wa"))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
+   "#"
+@@ -517,7 +514,7 @@
+    (set_attr "length" "12")])
+ 
+ (define_split
+-  [(set (match_operand:V8HI 0 "memory_operand" "")
++  [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "")
+         (match_operand:V8HI 1 "vsx_register_operand" ""))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
+   [(set (match_dup 2)
+@@ -542,7 +539,7 @@
+ ;; The post-reload split requires that we re-permute the source
+ ;; register in case it is still live.
+ (define_split
+-  [(set (match_operand:V8HI 0 "memory_operand" "")
++  [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "")
+         (match_operand:V8HI 1 "vsx_register_operand" ""))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
+   [(set (match_dup 1)
+@@ -569,7 +566,7 @@
+   "")
+ 
+ (define_insn "*vsx_le_perm_store_v16qi"
+-  [(set (match_operand:V16QI 0 "memory_operand" "=Z")
++  [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "=Z")
+         (match_operand:V16QI 1 "vsx_register_operand" "+wa"))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
+   "#"
+@@ -577,7 +574,7 @@
+    (set_attr "length" "12")])
+ 
+ (define_split
+-  [(set (match_operand:V16QI 0 "memory_operand" "")
++  [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "")
+         (match_operand:V16QI 1 "vsx_register_operand" ""))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
+   [(set (match_dup 2)
+@@ -610,7 +607,7 @@
+ ;; The post-reload split requires that we re-permute the source
+ ;; register in case it is still live.
+ (define_split
+-  [(set (match_operand:V16QI 0 "memory_operand" "")
++  [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "")
+         (match_operand:V16QI 1 "vsx_register_operand" ""))]
+   "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
+   [(set (match_dup 1)
+@@ -1908,6 +1905,80 @@
+ }
+   [(set_attr "type" "vecperm")])
+ 
++;; Combiner patterns to allow creating XXPERMDI's to access either double
++;; word element in a vector register.
++(define_insn "*vsx_concat_<mode>_1"
++  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>")
++	(vec_concat:VSX_D
++	 (vec_select:<VS_scalar>
++	  (match_operand:VSX_D 1 "gpc_reg_operand" "<VSa>")
++	  (parallel [(match_operand:QI 2 "const_0_to_1_operand" "n")]))
++	 (match_operand:<VS_scalar> 3 "gpc_reg_operand" "<VSa>")))]
++  "VECTOR_MEM_VSX_P (<MODE>mode)"
++{
++  HOST_WIDE_INT dword = INTVAL (operands[2]);
++  if (BYTES_BIG_ENDIAN)
++    {
++      operands[4] = GEN_INT (2*dword);
++      return "xxpermdi %x0,%x1,%x3,%4";
++    }
++  else
++    {
++      operands[4] = GEN_INT (!dword);
++      return "xxpermdi %x0,%x3,%x1,%4";
++    }
++}
++  [(set_attr "type" "vecperm")])
++
++(define_insn "*vsx_concat_<mode>_2"
++  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>")
++	(vec_concat:VSX_D
++	 (match_operand:<VS_scalar> 1 "gpc_reg_operand" "<VSa>")
++	 (vec_select:<VS_scalar>
++	  (match_operand:VSX_D 2 "gpc_reg_operand" "<VSa>")
++	  (parallel [(match_operand:QI 3 "const_0_to_1_operand" "n")]))))]
++  "VECTOR_MEM_VSX_P (<MODE>mode)"
++{
++  HOST_WIDE_INT dword = INTVAL (operands[3]);
++  if (BYTES_BIG_ENDIAN)
++    {
++      operands[4] = GEN_INT (dword);
++      return "xxpermdi %x0,%x1,%x2,%4";
++    }
++  else
++    {
++      operands[4] = GEN_INT (2 * !dword);
++      return "xxpermdi %x0,%x2,%x1,%4";
++    }
++}
++  [(set_attr "type" "vecperm")])
++
++(define_insn "*vsx_concat_<mode>_3"
++  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>")
++	(vec_concat:VSX_D
++	 (vec_select:<VS_scalar>
++	  (match_operand:VSX_D 1 "gpc_reg_operand" "<VSa>")
++	  (parallel [(match_operand:QI 2 "const_0_to_1_operand" "n")]))
++	 (vec_select:<VS_scalar>
++	  (match_operand:VSX_D 3 "gpc_reg_operand" "<VSa>")
++	  (parallel [(match_operand:QI 4 "const_0_to_1_operand" "n")]))))]
++  "VECTOR_MEM_VSX_P (<MODE>mode)"
++{
++  HOST_WIDE_INT dword1 = INTVAL (operands[2]);
++  HOST_WIDE_INT dword2 = INTVAL (operands[4]);
++  if (BYTES_BIG_ENDIAN)
++    {
++      operands[5] = GEN_INT ((2 * dword1) + dword2);
++      return "xxpermdi %x0,%x1,%x3,%5";
++    }
++  else
++    {
++      operands[5] = GEN_INT ((2 * !dword2) + !dword1);
++      return "xxpermdi %x0,%x3,%x1,%5";
++    }
++}
++  [(set_attr "type" "vecperm")])
++
+ ;; Special purpose concat using xxpermdi to glue two single precision values
+ ;; together, relying on the fact that internally scalar floats are represented
+ ;; as doubles.  This is used to initialize a V4SF vector with 4 floats
+@@ -1929,9 +2000,9 @@
+ ;; xxpermdi for little endian loads and stores.  We need several of
+ ;; these since the form of the PARALLEL differs by mode.
+ (define_insn "*vsx_xxpermdi2_le_<mode>"
+-  [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>")
+-        (vec_select:VSX_LE
+-          (match_operand:VSX_LE 1 "vsx_register_operand" "<VSa>")
++  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>")
++        (vec_select:VSX_D
++          (match_operand:VSX_D 1 "vsx_register_operand" "<VSa>")
+           (parallel [(const_int 1) (const_int 0)])))]
+   "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
+   "xxpermdi %x0,%x1,%x1,2"
+@@ -1978,9 +2049,9 @@
+ ;; lxvd2x for little endian loads.  We need several of
+ ;; these since the form of the PARALLEL differs by mode.
+ (define_insn "*vsx_lxvd2x2_le_<mode>"
+-  [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>")
+-        (vec_select:VSX_LE
+-          (match_operand:VSX_LE 1 "memory_operand" "Z")
++  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>")
++        (vec_select:VSX_D
++          (match_operand:VSX_D 1 "memory_operand" "Z")
+           (parallel [(const_int 1) (const_int 0)])))]
+   "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) && !TARGET_P9_VECTOR"
+   "lxvd2x %x0,%y1"
+@@ -2027,9 +2098,9 @@
+ ;; stxvd2x for little endian stores.  We need several of
+ ;; these since the form of the PARALLEL differs by mode.
+ (define_insn "*vsx_stxvd2x2_le_<mode>"
+-  [(set (match_operand:VSX_LE 0 "memory_operand" "=Z")
+-        (vec_select:VSX_LE
+-          (match_operand:VSX_LE 1 "vsx_register_operand" "<VSa>")
++  [(set (match_operand:VSX_D 0 "memory_operand" "=Z")
++        (vec_select:VSX_D
++          (match_operand:VSX_D 1 "vsx_register_operand" "<VSa>")
+           (parallel [(const_int 1) (const_int 0)])))]
+   "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) && !TARGET_P9_VECTOR"
+   "stxvd2x %x1,%y0"
+@@ -2088,25 +2159,35 @@
+   DONE;
+ })
+ 
+-;; Set the element of a V2DI/VD2F mode
+-(define_insn "vsx_set_<mode>"
+-  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?<VSa>")
+-	(unspec:VSX_D
+-	 [(match_operand:VSX_D 1 "vsx_register_operand" "wd,<VSa>")
+-	  (match_operand:<VS_scalar> 2 "vsx_register_operand" "<VS_64reg>,<VSa>")
+-	  (match_operand:QI 3 "u5bit_cint_operand" "i,i")]
+-	 UNSPEC_VSX_SET))]
++;; Rewrite V2DF/V2DI set in terms of VEC_CONCAT
++(define_expand "vsx_set_<mode>"
++  [(use (match_operand:VSX_D 0 "vsx_register_operand"))
++   (use (match_operand:VSX_D 1 "vsx_register_operand"))
++   (use (match_operand:<VS_scalar> 2 "gpc_reg_operand"))
++   (use (match_operand:QI 3 "const_0_to_1_operand"))]
+   "VECTOR_MEM_VSX_P (<MODE>mode)"
+ {
+-  int idx_first = BYTES_BIG_ENDIAN ? 0 : 1;
+-  if (INTVAL (operands[3]) == idx_first)
+-    return \"xxpermdi %x0,%x2,%x1,1\";
+-  else if (INTVAL (operands[3]) == 1 - idx_first)
+-    return \"xxpermdi %x0,%x1,%x2,0\";
++  rtx dest = operands[0];
++  rtx vec_reg = operands[1];
++  rtx value = operands[2];
++  rtx ele = operands[3];
++  rtx tmp = gen_reg_rtx (<VS_scalar>mode);
++
++  if (ele == const0_rtx)
++    {
++      emit_insn (gen_vsx_extract_<mode> (tmp, vec_reg, const1_rtx));
++      emit_insn (gen_vsx_concat_<mode> (dest, value, tmp));
++      DONE;
++    }
++  else if (ele == const1_rtx)
++    {
++      emit_insn (gen_vsx_extract_<mode> (tmp, vec_reg, const0_rtx));
++      emit_insn (gen_vsx_concat_<mode> (dest, tmp, value));
++      DONE;
++    }
+   else
+     gcc_unreachable ();
+-}
+-  [(set_attr "type" "vecperm")])
++})
+ 
+ ;; Extract a DF/DI element from V2DF/V2DI
+ (define_expand "vsx_extract_<mode>"
+Index: gcc/config/rs6000/altivec.md
+===================================================================
+--- a/src/gcc/config/rs6000/altivec.md	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/rs6000/altivec.md	(.../branches/gcc-6-branch)
+@@ -1714,51 +1714,61 @@
+   "vsum4s<VI_char>s %0,%1,%2"
+   [(set_attr "type" "veccomplex")])
+ 
+-;; FIXME: For the following two patterns, the scratch should only be
+-;; allocated for !VECTOR_ELT_ORDER_BIG, and the instructions should
+-;; be emitted separately.
+-(define_insn "altivec_vsum2sws"
+-  [(set (match_operand:V4SI 0 "register_operand" "=v")
+-        (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
+-                      (match_operand:V4SI 2 "register_operand" "v")]
+-		     UNSPEC_VSUM2SWS))
+-   (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
+-   (clobber (match_scratch:V4SI 3 "=v"))]
++(define_expand "altivec_vsum2sws"
++  [(use (match_operand:V4SI 0 "register_operand"))
++   (use (match_operand:V4SI 1 "register_operand"))
++   (use (match_operand:V4SI 2 "register_operand"))]
+   "TARGET_ALTIVEC"
+ {
+   if (VECTOR_ELT_ORDER_BIG)
+-    return "vsum2sws %0,%1,%2";
++    emit_insn (gen_altivec_vsum2sws_direct (operands[0], operands[1],
++                                            operands[2]));
+   else
+-    return "vsldoi %3,%2,%2,12\n\tvsum2sws %3,%1,%3\n\tvsldoi %0,%3,%3,4";
+-}
+-  [(set_attr "type" "veccomplex")
+-   (set (attr "length")
+-     (if_then_else
+-       (match_test "VECTOR_ELT_ORDER_BIG")
+-       (const_string "4")
+-       (const_string "12")))])
++    {
++      rtx tmp1 = gen_reg_rtx (V4SImode);
++      rtx tmp2 = gen_reg_rtx (V4SImode);
++      emit_insn (gen_altivec_vsldoi_v4si (tmp1, operands[2],
++                                          operands[2], GEN_INT (12)));
++      emit_insn (gen_altivec_vsum2sws_direct (tmp2, operands[1], tmp1));
++      emit_insn (gen_altivec_vsldoi_v4si (operands[0], tmp2, tmp2,
++                                          GEN_INT (4)));
++    }
++  DONE;
++})
+ 
+-(define_insn "altivec_vsumsws"
++; FIXME: This can probably be expressed without an UNSPEC.
++(define_insn "altivec_vsum2sws_direct"
+   [(set (match_operand:V4SI 0 "register_operand" "=v")
+         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
+-                      (match_operand:V4SI 2 "register_operand" "v")]
+-		     UNSPEC_VSUMSWS))
+-   (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
+-   (clobber (match_scratch:V4SI 3 "=v"))]
++	              (match_operand:V4SI 2 "register_operand" "v")]
++		     UNSPEC_VSUM2SWS))
++   (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+   "TARGET_ALTIVEC"
++  "vsum2sws %0,%1,%2"
++  [(set_attr "type" "veccomplex")])
++
++(define_expand "altivec_vsumsws"
++  [(use (match_operand:V4SI 0 "register_operand"))
++   (use (match_operand:V4SI 1 "register_operand"))
++   (use (match_operand:V4SI 2 "register_operand"))]
++  "TARGET_ALTIVEC"
+ {
+   if (VECTOR_ELT_ORDER_BIG)
+-    return "vsumsws %0,%1,%2";
++    emit_insn (gen_altivec_vsumsws_direct (operands[0], operands[1],
++                                           operands[2]));
+   else
+-    return "vspltw %3,%2,0\n\tvsumsws %3,%1,%3\n\tvsldoi %0,%3,%3,12";
+-}
+-  [(set_attr "type" "veccomplex")
+-   (set (attr "length")
+-     (if_then_else
+-       (match_test "(VECTOR_ELT_ORDER_BIG)")
+-       (const_string "4")
+-       (const_string "12")))])
++    {
++      rtx tmp1 = gen_reg_rtx (V4SImode);
++      rtx tmp2 = gen_reg_rtx (V4SImode);
++      emit_insn (gen_altivec_vspltw_direct (tmp1, operands[2], const0_rtx));
++      emit_insn (gen_altivec_vsumsws_direct (tmp2, operands[1], tmp1));
++      emit_insn (gen_altivec_vsldoi_v4si (operands[0], tmp2, tmp2,
++                                          GEN_INT (12)));
++    }
++  DONE;
++})
+ 
++; FIXME: This can probably be expressed without an UNSPEC.
+ (define_insn "altivec_vsumsws_direct"
+   [(set (match_operand:V4SI 0 "register_operand" "=v")
+         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
+@@ -2072,7 +2082,7 @@
+ 		   UNSPEC_VPERMR))]
+   "TARGET_P9_VECTOR"
+   "@
+-   vpermr %0,%2,%1,%3
++   vpermr %0,%1,%2,%3
+    xxpermr %x0,%x1,%x3"
+   [(set_attr "type" "vecperm")
+    (set_attr "length" "4")])
+Index: gcc/config/rs6000/rs6000.md
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.md	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/rs6000/rs6000.md	(.../branches/gcc-6-branch)
+@@ -535,7 +535,7 @@
+ (define_code_attr su [(sign_extend	"s")
+ 		      (zero_extend	"u")
+ 		      (fix		"s")
+-		      (unsigned_fix	"s")
++		      (unsigned_fix	"u")
+ 		      (float		"s")
+ 		      (unsigned_float	"u")])
+ 
+@@ -4556,12 +4556,19 @@
+ {
+   if (FLOAT128_IEEE_P (<MODE>mode))
+     {
++      rtx dest = operands[0];
++      rtx src = operands[1];
++      rtx tmp = gen_reg_rtx (DImode);
++      rtx dest_di = gen_lowpart (DImode, dest);
++
+       if (<MODE>mode == KFmode)
+-	emit_insn (gen_signbitkf2_dm (operands[0], operands[1]));
++	emit_insn (gen_signbitkf2_dm (tmp, src));
+       else if (<MODE>mode == TFmode)
+-	emit_insn (gen_signbittf2_dm (operands[0], operands[1]));
++	emit_insn (gen_signbittf2_dm (tmp, src));
+       else
+ 	gcc_unreachable ();
++
++      emit_insn (gen_lshrdi3 (dest_di, tmp, GEN_INT (63)));
+       DONE;
+     }
+   operands[2] = gen_reg_rtx (DFmode);
+@@ -4582,6 +4589,66 @@
+     }
+ })
+ 
++;; Optimize IEEE 128-bit signbit on 64-bit systems with direct move to avoid
++;; multiple direct moves.  If we used a SUBREG:DI of the Floa128 type, the
++;; register allocator would typically move the entire _Float128 item to GPRs (2
++;; instructions on ISA 3.0, 3-4 instructions on ISA 2.07).
++;;
++;; After register allocation, if the _Float128 had originally been in GPRs, the
++;; split allows the post reload phases to eliminate the move, and do the shift
++;; directly with the register that contains the signbit.
++(define_insn_and_split "signbit<mode>2_dm"
++  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
++	(unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "wa,r")]
++		   UNSPEC_SIGNBIT))]
++  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
++  "@
++   mfvsrd %0,%x1
++   #"
++  "&& reload_completed && int_reg_operand (operands[1], <MODE>mode)"
++  [(set (match_dup 0)
++	(match_dup 2))]
++{
++  operands[2] = gen_highpart (DImode, operands[1]);
++}
++ [(set_attr "type" "mftgpr,*")])
++
++;; Optimize IEEE 128-bit signbit on to avoid loading the value into a vector
++;; register and then doing a direct move if the value comes from memory.  On
++;; little endian, we have to load the 2nd double-word to get the sign bit.
++(define_insn_and_split "*signbit<mode>2_dm_mem"
++  [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
++	(unspec:DI [(match_operand:SIGNBIT 1 "memory_operand" "m")]
++		   UNSPEC_SIGNBIT))]
++  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
++  "#"
++  "&& 1"
++  [(set (match_dup 0)
++	(match_dup 2))]
++{
++  rtx dest = operands[0];
++  rtx src = operands[1];
++  rtx addr = XEXP (src, 0);
++
++  if (WORDS_BIG_ENDIAN)
++    operands[2] = adjust_address (src, DImode, 0);
++
++  else if (REG_P (addr) || SUBREG_P (addr))
++    operands[2] = adjust_address (src, DImode, 8);
++
++  else if (GET_CODE (addr) == PLUS && REG_P (XEXP (addr, 0))
++	   && CONST_INT_P (XEXP (addr, 1)) && mem_operand_gpr (src, DImode))
++    operands[2] = adjust_address (src, DImode, 8);
++
++  else
++    {
++      rtx tmp = can_create_pseudo_p () ? gen_reg_rtx (DImode) : dest;
++      emit_insn (gen_rtx_SET (tmp, addr));
++      operands[2] = change_address (src, DImode,
++				    gen_rtx_PLUS (DImode, tmp, GEN_INT (8)));
++    }
++})
++
+ (define_expand "copysign<mode>3"
+   [(set (match_dup 3)
+         (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
+@@ -4611,54 +4678,6 @@
+    operands[5] = CONST0_RTX (<MODE>mode);
+   })
+ 
+-;; Optimize signbit on 64-bit systems with direct move to avoid doing the store
+-;; and load.
+-(define_insn_and_split "signbit<mode>2_dm"
+-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
+-	(unspec:SI
+-	 [(match_operand:SIGNBIT 1 "input_operand" "wa,m,r")]
+-	 UNSPEC_SIGNBIT))]
+-  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
+-  "#"
+-  "&& reload_completed"
+-  [(const_int 0)]
+-{
+-  rs6000_split_signbit (operands[0], operands[1]);
+-  DONE;
+-}
+- [(set_attr "length" "8,8,4")
+-  (set_attr "type" "mftgpr,load,integer")])
+-
+-(define_insn_and_split "*signbit<mode>2_dm_<su>ext"
+-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
+-	(any_extend:DI
+-	 (unspec:SI
+-	  [(match_operand:SIGNBIT 1 "input_operand" "wa,m,r")]
+-	  UNSPEC_SIGNBIT)))]
+-  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
+-  "#"
+-  "&& reload_completed"
+-  [(const_int 0)]
+-{
+-  rs6000_split_signbit (operands[0], operands[1]);
+-  DONE;
+-}
+- [(set_attr "length" "8,8,4")
+-  (set_attr "type" "mftgpr,load,integer")])
+-
+-;; MODES_TIEABLE_P doesn't allow DImode to be tied with the various floating
+-;; point types, which makes normal SUBREG's problematical. Instead use a
+-;; special pattern to avoid using a normal movdi.
+-(define_insn "signbit<mode>2_dm2"
+-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+-	(unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "wa")
+-		    (const_int 0)]
+-		   UNSPEC_SIGNBIT))]
+-  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
+-  "mfvsrd %0,%x1"
+- [(set_attr "type" "mftgpr")])
+-
+-
+ ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
+ ;; compiler from optimizing -0.0
+ (define_insn "copysign<mode>3_fcpsgn"
+Index: gcc/config/rs6000/sysv4.h
+===================================================================
+--- a/src/gcc/config/rs6000/sysv4.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/rs6000/sysv4.h	(.../branches/gcc-6-branch)
+@@ -752,24 +752,34 @@
+ #define CRTOFFLOADEND ""
+ #endif
+ 
+-#ifdef HAVE_LD_PIE
+-#define	STARTFILE_LINUX_SPEC "\
+-%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \
+-%{mnewlib:ecrti.o%s;:crti.o%s} \
+-%{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \
+-" CRTOFFLOADBEGIN
+-#else
+-#define	STARTFILE_LINUX_SPEC "\
+-%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \
+-%{mnewlib:ecrti.o%s;:crti.o%s} \
+-%{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \
+-" CRTOFFLOADBEGIN
+-#endif
++/* STARTFILE_LINUX_SPEC should be the same as GNU_USER_TARGET_STARTFILE_SPEC
++   but with the mnewlib ecrti.o%s selection substituted for crti.o%s.  */
++#define	STARTFILE_LINUX_SPEC \
++  "%{shared:; \
++     pg|p|profile:gcrt1.o%s; \
++     static:crt1.o%s; \
++     " PIE_SPEC ":Scrt1.o%s; \
++     :crt1.o%s} \
++   %{mnewlib:ecrti.o%s;:crti.o%s} \
++   %{static:crtbeginT.o%s; \
++     shared|" PIE_SPEC ":crtbeginS.o%s; \
++     :crtbegin.o%s} \
++   %{fvtable-verify=none:%s; \
++     fvtable-verify=preinit:vtv_start_preinit.o%s; \
++     fvtable-verify=std:vtv_start.o%s} \
++   " CRTOFFLOADBEGIN
+ 
+-#define	ENDFILE_LINUX_SPEC "\
+-%{shared|pie:crtendS.o%s;:crtend.o%s} \
+-%{mnewlib:ecrtn.o%s;:crtn.o%s} \
+-" CRTOFFLOADEND
++/* ENDFILE_LINUX_SPEC should be the same as GNU_USER_TARGET_ENDFILE_SPEC
++   but with the mnewlib ecrtn.o%s selection substituted for crtn.o%s.  */
++#define ENDFILE_LINUX_SPEC \
++  "%{fvtable-verify=none:%s; \
++     fvtable-verify=preinit:vtv_end_preinit.o%s; \
++     fvtable-verify=std:vtv_end.o%s} \
++   %{static:crtend.o%s; \
++     shared|" PIE_SPEC ":crtendS.o%s; \
++     :crtend.o%s} \
++   %{mnewlib:ecrtn.o%s;:crtn.o%s} \
++   " CRTOFFLOADEND
+ 
+ #define LINK_START_LINUX_SPEC ""
+ 
+Index: gcc/config/arm/arm.c
+===================================================================
+--- a/src/gcc/config/arm/arm.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/arm/arm.c	(.../branches/gcc-6-branch)
+@@ -15926,12 +15926,23 @@
+   return true;
+ }
+ 
++/* Return true if a 64-bit access with alignment ALIGN and with a
++   constant offset OFFSET from the base pointer is permitted on this
++   architecture.  */
++static bool
++align_ok_ldrd_strd (HOST_WIDE_INT align, HOST_WIDE_INT offset)
++{
++  return (unaligned_access
++	  ? (align >= BITS_PER_WORD && (offset & 3) == 0)
++	  : (align >= 2 * BITS_PER_WORD && (offset & 7) == 0));
++}
++
+ /* Helper for gen_operands_ldrd_strd.  Returns true iff the memory
+    operand MEM's address contains an immediate offset from the base
+-   register and has no side effects, in which case it sets BASE and
+-   OFFSET accordingly.  */
++   register and has no side effects, in which case it sets BASE,
++   OFFSET and ALIGN accordingly.  */
+ static bool
+-mem_ok_for_ldrd_strd (rtx mem, rtx *base, rtx *offset)
++mem_ok_for_ldrd_strd (rtx mem, rtx *base, rtx *offset, HOST_WIDE_INT *align)
+ {
+   rtx addr;
+ 
+@@ -15950,6 +15961,7 @@
+   gcc_assert (MEM_P (mem));
+ 
+   *offset = const0_rtx;
++  *align = MEM_ALIGN (mem);
+ 
+   addr = XEXP (mem, 0);
+ 
+@@ -15990,7 +16002,7 @@
+                         bool const_store, bool commute)
+ {
+   int nops = 2;
+-  HOST_WIDE_INT offsets[2], offset;
++  HOST_WIDE_INT offsets[2], offset, align[2];
+   rtx base = NULL_RTX;
+   rtx cur_base, cur_offset, tmp;
+   int i, gap;
+@@ -16002,7 +16014,8 @@
+      registers, and the corresponding memory offsets.  */
+   for (i = 0; i < nops; i++)
+     {
+-      if (!mem_ok_for_ldrd_strd (operands[nops+i], &cur_base, &cur_offset))
++      if (!mem_ok_for_ldrd_strd (operands[nops+i], &cur_base, &cur_offset,
++				 &align[i]))
+         return false;
+ 
+       if (i == 0)
+@@ -16114,6 +16127,7 @@
+       /* Swap the instructions such that lower memory is accessed first.  */
+       std::swap (operands[0], operands[1]);
+       std::swap (operands[2], operands[3]);
++      std::swap (align[0], align[1]);
+       if (const_store)
+         std::swap (operands[4], operands[5]);
+     }
+@@ -16127,6 +16141,9 @@
+   if (gap != 4)
+     return false;
+ 
++  if (!align_ok_ldrd_strd (align[0], offset))
++    return false;
++
+   /* Make sure we generate legal instructions.  */
+   if (operands_ok_ldrd_strd (operands[0], operands[1], base, offset,
+                              false, load))
+Index: gcc/config/arm/arm.h
+===================================================================
+--- a/src/gcc/config/arm/arm.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/arm/arm.h	(.../branches/gcc-6-branch)
+@@ -1677,12 +1677,10 @@
+ 
+ /* These assume that REGNO is a hard or pseudo reg number.
+    They give nonzero only if REGNO is a hard reg of the suitable class
+-   or a pseudo reg currently allocated to a suitable hard reg.
+-   Since they use reg_renumber, they are safe only once reg_renumber
+-   has been allocated, which happens in reginfo.c during register
+-   allocation.  */
++   or a pseudo reg currently allocated to a suitable hard reg.  */
+ #define TEST_REGNO(R, TEST, VALUE) \
+-  ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
++  ((R TEST VALUE)	\
++    || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE)))
+ 
+ /* Don't allow the pc to be used.  */
+ #define ARM_REGNO_OK_FOR_BASE_P(REGNO)			\
+Index: gcc/config/arm/arm-cores.def
+===================================================================
+--- a/src/gcc/config/arm/arm-cores.def	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/arm/arm-cores.def	(.../branches/gcc-6-branch)
+@@ -145,12 +145,12 @@
+ /* V7 Architecture Processors */
+ ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex)
+ ARM_CORE("cortex-a5",		cortexa5, cortexa5,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a5)
+-ARM_CORE("cortex-a7",		cortexa7, cortexa7,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7)
++ARM_CORE("cortex-a7",		cortexa7, cortexa7,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a7)
+ ARM_CORE("cortex-a8",		cortexa8, cortexa8,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a8)
+ ARM_CORE("cortex-a9",		cortexa9, cortexa9,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a9)
+-ARM_CORE("cortex-a12",		cortexa12, cortexa17,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+-ARM_CORE("cortex-a15",		cortexa15, cortexa15,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
+-ARM_CORE("cortex-a17",		cortexa17, cortexa17,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
++ARM_CORE("cortex-a12",		cortexa12, cortexa17,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a12)
++ARM_CORE("cortex-a15",		cortexa15, cortexa15,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a15)
++ARM_CORE("cortex-a17",		cortexa17, cortexa17,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a12)
+ ARM_CORE("cortex-r4",		cortexr4, cortexr4,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex)
+ ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex)
+ ARM_CORE("cortex-r5",		cortexr5, cortexr5,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+@@ -162,8 +162,8 @@
+ ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), marvell_pj4)
+ 
+ /* V7 big.LITTLE implementations */
+-ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
+-ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
++ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a15)
++ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a12)
+ 
+ /* V8 Architecture Processors */
+ ARM_CORE("cortex-a32",	cortexa32, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
+Index: gcc/config/arm/freebsd.h
+===================================================================
+--- a/src/gcc/config/arm/freebsd.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/arm/freebsd.h	(.../branches/gcc-6-branch)
+@@ -112,8 +112,11 @@
+ #undef  WCHAR_TYPE_SIZE
+ #define WCHAR_TYPE_SIZE BITS_PER_WORD
+ 
+-#if defined (TARGET_FREEBSD_ARMv6)
++#if defined (TARGET_FREEBSD_ARMv7)
+ #undef  SUBTARGET_CPU_DEFAULT
++#define SUBTARGET_CPU_DEFAULT TARGET_CPU_genericv7a
++#elif defined (TARGET_FREEBSD_ARMv6)
++#undef  SUBTARGET_CPU_DEFAULT
+ #define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm1176jzs
+ #else
+ #undef  SUBTARGET_CPU_DEFAULT
+Index: gcc/config/pa/predicates.md
+===================================================================
+--- a/src/gcc/config/pa/predicates.md	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/pa/predicates.md	(.../branches/gcc-6-branch)
+@@ -277,6 +277,9 @@
+     case HImode:
+       return true;
+ 
++    case VOIDmode:
++      return false;
++
+     default:
+       return (INTVAL (op) % GET_MODE_SIZE (mode)) == 0;
+     }
+Index: gcc/config/pa/pa64-hpux.h
+===================================================================
+--- a/src/gcc/config/pa/pa64-hpux.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/pa/pa64-hpux.h	(.../branches/gcc-6-branch)
+@@ -247,9 +247,19 @@
+ 
+ /* We need to use the HP style for internal labels.  */
+ #undef ASM_GENERATE_INTERNAL_LABEL
+-#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)	\
+-  sprintf (LABEL, "*%c$%s%04ld", (PREFIX)[0], (PREFIX) + 1, (long)(NUM))
++#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)		\
++  do								\
++    {								\
++      char *__p;						\
++      (LABEL)[0] = '*';						\
++      (LABEL)[1] = (PREFIX)[0];					\
++      (LABEL)[2] = '$';						\
++      __p = stpcpy (&(LABEL)[3], &(PREFIX)[1]);			\
++      sprint_ul (__p, (unsigned long) (NUM));			\
++    }								\
++  while (0)
+ 
++
+ #else /* USING_ELFOS_H */
+ 
+ /* We are not using GAS.  */
+Index: gcc/config/pa/pa.md
+===================================================================
+--- a/src/gcc/config/pa/pa.md	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/pa/pa.md	(.../branches/gcc-6-branch)
+@@ -2536,24 +2536,40 @@
+ 
+   xoperands[0] = operands[0];
+   xoperands[1] = operands[1];
+-  xoperands[2] = gen_label_rtx ();
+ 
+-  (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
+-				     CODE_LABEL_NUMBER (xoperands[2]));
+-  output_asm_insn (\"mfia %0\", xoperands);
++  if (GET_CODE (operands[1]) == LABEL_REF
++      && !LABEL_REF_NONLOCAL_P (operands[1]))
++    {
++      xoperands[2] = gen_label_rtx ();
++      (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
++					 CODE_LABEL_NUMBER (xoperands[2]));
++      output_asm_insn (\"mfia %0\", xoperands);
+ 
+-  /* If we're trying to load the address of a label that happens to be
+-     close, then we can use a shorter sequence.  */
+-  if (GET_CODE (operands[1]) == LABEL_REF
+-      && !LABEL_REF_NONLOCAL_P (operands[1])
+-      && INSN_ADDRESSES_SET_P ()
+-      && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
+-	        - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
+-    output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
++      /* If we're trying to load the address of a label that happens to be
++	 close, then we can use a shorter sequence.  */
++      if (INSN_ADDRESSES_SET_P ()
++	  && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
++		  - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
++	output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
++      else
++	{
++	  output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
++	  output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
++	}
++    }
+   else
+     {
+-      output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
+-      output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
++      /* Load using linkage table.  */
++      if (TARGET_64BIT)
++	{
++	  output_asm_insn (\"addil LT%%%1,%%r27\", xoperands);
++	  output_asm_insn (\"ldd RT%%%1(%0),%0\", xoperands);
++	}
++      else
++	{
++	  output_asm_insn (\"addil LT%%%1,%%r19\", xoperands);
++	  output_asm_insn (\"ldw RT%%%1(%0),%0\", xoperands);
++	}
+     }
+   return \"\";
+ }"
+@@ -2570,25 +2586,33 @@
+ 
+   xoperands[0] = operands[0];
+   xoperands[1] = operands[1];
+-  xoperands[2] = gen_label_rtx ();
+ 
+-  output_asm_insn (\"bl .+8,%0\", xoperands);
+-  output_asm_insn (\"depi 0,31,2,%0\", xoperands);
+-  (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
+-				     CODE_LABEL_NUMBER (xoperands[2]));
++  if (GET_CODE (operands[1]) == LABEL_REF
++      && !LABEL_REF_NONLOCAL_P (operands[1]))
++    {
++      xoperands[2] = gen_label_rtx ();
++      output_asm_insn (\"bl .+8,%0\", xoperands);
++      output_asm_insn (\"depi 0,31,2,%0\", xoperands);
++      (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
++					 CODE_LABEL_NUMBER (xoperands[2]));
+ 
+-  /* If we're trying to load the address of a label that happens to be
+-     close, then we can use a shorter sequence.  */
+-  if (GET_CODE (operands[1]) == LABEL_REF
+-      && !LABEL_REF_NONLOCAL_P (operands[1])
+-      && INSN_ADDRESSES_SET_P ()
+-      && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
+-	        - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
+-    output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
++      /* If we're trying to load the address of a label that happens to be
++	 close, then we can use a shorter sequence.  */
++      if (INSN_ADDRESSES_SET_P ()
++	  && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
++		  - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
++	output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
++      else
++	{
++	  output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
++	  output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
++	}
++    }
+   else
+     {
+-      output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
+-      output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
++      /* Load using linkage table.  */
++      output_asm_insn (\"addil LT%%%1,%%r19\", xoperands);
++      output_asm_insn (\"ldw RT%%%1(%0),%0\", xoperands);
+     }
+   return \"\";
+ }"
+Index: gcc/config/pa/pa.c
+===================================================================
+--- a/src/gcc/config/pa/pa.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/pa/pa.c	(.../branches/gcc-6-branch)
+@@ -4565,13 +4565,17 @@
+      lcla2 and load_offset_label_address insn patterns.  */
+   rtx reg = gen_reg_rtx (SImode);
+   rtx_code_label *label_rtx = gen_label_rtx ();
+-  rtx mcount = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "_mcount"));
+   int reg_parm_stack_space = REG_PARM_STACK_SPACE (NULL_TREE);
+-  rtx arg_bytes, begin_label_rtx;
++  rtx arg_bytes, begin_label_rtx, mcount, sym;
+   rtx_insn *call_insn;
+   char begin_label_name[16];
+   bool use_mcount_pcrel_call;
+ 
++  /* Set up call destination.  */
++  sym = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
++  pa_encode_label (sym);
++  mcount = gen_rtx_MEM (Pmode, sym);
++
+   /* If we can reach _mcount with a pc-relative call, we can optimize
+      loading the address of the current function.  This requires linker
+      long branch stub support.  */
+@@ -10462,9 +10466,16 @@
+ 
+       if (!TARGET_DISABLE_INDEXING
+ 	  && GET_CODE (index) == MULT
+-	  && MODE_OK_FOR_SCALED_INDEXING_P (mode)
++	  /* Only accept base operands with the REG_POINTER flag prior to
++	     reload on targets with non-equivalent space registers.  */
++	  && (TARGET_NO_SPACE_REGS
++	      || (base == XEXP (x, 1)
++		  && (reload_completed
++		      || (reload_in_progress && HARD_REGISTER_P (base))
++		      || REG_POINTER (base))))
+ 	  && REG_P (XEXP (index, 0))
+ 	  && GET_MODE (XEXP (index, 0)) == Pmode
++	  && MODE_OK_FOR_SCALED_INDEXING_P (mode)
+ 	  && (strict ? STRICT_REG_OK_FOR_INDEX_P (XEXP (index, 0))
+ 		     : REG_OK_FOR_INDEX_P (XEXP (index, 0)))
+ 	  && GET_CODE (XEXP (index, 1)) == CONST_INT
+Index: gcc/config/pa/pa.h
+===================================================================
+--- a/src/gcc/config/pa/pa.h	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/config/pa/pa.h	(.../branches/gcc-6-branch)
+@@ -1159,9 +1159,19 @@
+    PREFIX is the class of label and NUM is the number within the class.
+    This is suitable for output with `assemble_name'.  */
+ 
+-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
+-  sprintf (LABEL, "*%c$%s%04ld", (PREFIX)[0], (PREFIX) + 1, (long)(NUM))
++#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)		\
++  do								\
++    {								\
++      char *__p;						\
++      (LABEL)[0] = '*';						\
++      (LABEL)[1] = (PREFIX)[0];					\
++      (LABEL)[2] = '$';						\
++      __p = stpcpy (&(LABEL)[3], &(PREFIX)[1]);			\
++      sprint_ul (__p, (unsigned long) (NUM));			\
++    }								\
++  while (0)
+ 
++
+ /* Output the definition of a compiler-generated label named NAME.  */
+ 
+ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,NAME) \
+@@ -1199,7 +1209,7 @@
+ /* This is how to output an element of a case-vector that is absolute.  */
+ 
+ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
+-  fprintf (FILE, "\t.word L$%04d\n", VALUE)
++  fprintf (FILE, "\t.word L$%d\n", VALUE)
+ 
+ /* This is how to output an element of a case-vector that is relative. 
+    Since we always place jump tables in the text section, the difference
+@@ -1206,7 +1216,7 @@
+    is absolute and requires no relocation.  */
+ 
+ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
+-  fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL)
++  fprintf (FILE, "\t.word L$%d-L$%d\n", VALUE, REL)
+ 
+ /* This is how to output an absolute case-vector.  */
+ 
+Index: gcc/ipa-icf.c
+===================================================================
+--- a/src/gcc/ipa-icf.c	(.../tags/gcc_6_4_0_release)
++++ b/src/gcc/ipa-icf.c	(.../branches/gcc-6-branch)
+@@ -1116,6 +1116,17 @@
+       return false;
+     }
+ 
++  if (!original->in_same_comdat_group_p (alias)
++      || original->comdat_local_p ())
++    {
++      if (dump_file)
++	fprintf (dump_file,
++		 "Not unifying; alias nor wrapper cannot be created; "
++		 "across comdat group boundary\n\n");
++
++      return false;
++    }
++
+   /* See if original is in a section that can be discarded if the main
+      symbol is not used.  */
+ 
+Index: libgo/mksysinfo.sh
+===================================================================
+--- a/src/libgo/mksysinfo.sh	(.../tags/gcc_6_4_0_release)
++++ b/src/libgo/mksysinfo.sh	(.../branches/gcc-6-branch)
+@@ -1503,22 +1503,22 @@
+     sed -e 's/_in6_addr/[16]byte/' \
+     >> ${OUT}
+ 
+-# The Solaris 12 _flow_arp_desc_t struct.
++# The Solaris 11.4 _flow_arp_desc_t struct.
+ grep '^type _flow_arp_desc_t ' gen-sysinfo.go | \
+     sed -e 's/_in6_addr_t/[16]byte/g' \
+     >> ${OUT}
+ 
+-# The Solaris 12 _flow_l3_desc_t struct.
++# The Solaris 11.4 _flow_l3_desc_t struct.
+ grep '^type _flow_l3_desc_t ' gen-sysinfo.go | \
+     sed -e 's/_in6_addr_t/[16]byte/g' \
+     >> ${OUT}
+ 
+-# The Solaris 12 _mac_ipaddr_t struct.
++# The Solaris 11.3 _mac_ipaddr_t struct.
+ grep '^type _mac_ipaddr_t ' gen-sysinfo.go | \
+     sed -e 's/_in6_addr_t/[16]byte/g' \
+     >> ${OUT}
+ 
+-# The Solaris 12 _mactun_info_t struct.
++# The Solaris 11.3 _mactun_info_t struct.
+ grep '^type _mactun_info_t ' gen-sysinfo.go | \
+     sed -e 's/_in6_addr_t/[16]byte/g' \
+     >> ${OUT}
+Index: libgo/configure.ac
+===================================================================
+--- a/src/libgo/configure.ac	(.../tags/gcc_6_4_0_release)
++++ b/src/libgo/configure.ac	(.../branches/gcc-6-branch)
+@@ -684,7 +684,7 @@
+ AC_SUBST(STRUCT_EPOLL_EVENT_FD_OFFSET)
+ 
+ dnl Check if <sys/stat.h> uses timespec_t for st_?tim members.  Introduced
+-dnl in Solaris 12 for XPG7 compatibility.
++dnl in Solaris 11.4 for XPG7 compatibility.
+ AC_EGREP_HEADER([timespec_t.*st_atim], [sys/stat.h],
+ 		[have_stat_timespec=yes], [have_stat_timespec=no])
+ AM_CONDITIONAL(HAVE_STAT_TIMESPEC, test $have_stat_timespec = yes)
+Index: libgo/go/syscall/syscall_linux_s390x.go
+===================================================================
+--- a/src/libgo/go/syscall/syscall_linux_s390x.go	(.../tags/gcc_6_4_0_release)
++++ b/src/libgo/go/syscall/syscall_linux_s390x.go	(.../branches/gcc-6-branch)
+@@ -12,10 +12,29 @@
+ 
+ func (r *PtraceRegs) SetPC(pc uint64) { r.Psw.Addr = pc }
+ 
+-func PtraceGetRegs(pid int, regsout *PtraceRegs) (err error) {
+-	return ptrace(PTRACE_GETREGS, pid, 0, uintptr(unsafe.Pointer(regsout)))
++const syscall_PTRACE_PEEKUSR_AREA = 0x5000
++const syscall_PTRACE_POKEUSR_AREA = 0x5001
++
++type syscall_ptrace_area struct {
++	len          uint32
++	kernel_addr  uint64
++	process_addr uint64
+ }
+ 
++func PtraceGetRegs(pid int, regs *PtraceRegs) (err error) {
++	parea := syscall_ptrace_area{
++		24,
++		0,
++		uint64(uintptr(unsafe.Pointer(regs))),
++	}
++	return ptrace(syscall_PTRACE_PEEKUSR_AREA, pid, uintptr(unsafe.Pointer(&parea)), 0)
++}
++
+ func PtraceSetRegs(pid int, regs *PtraceRegs) (err error) {
+-	return ptrace(PTRACE_SETREGS, pid, 0, uintptr(unsafe.Pointer(regs)))
++	parea := syscall_ptrace_area{
++		24,
++		0,
++		uint64(uintptr(unsafe.Pointer(regs))),
++	}
++	return ptrace(syscall_PTRACE_POKEUSR_AREA, pid, uintptr(unsafe.Pointer(&parea)), 0)
+ }
+Index: libgo/go/syscall/syscall_linux_s390.go
+===================================================================
+--- a/src/libgo/go/syscall/syscall_linux_s390.go	(.../tags/gcc_6_4_0_release)
++++ b/src/libgo/go/syscall/syscall_linux_s390.go	(.../branches/gcc-6-branch)
+@@ -12,10 +12,29 @@
+ 
+ func (r *PtraceRegs) SetPC(pc uint64) { r.Psw.Addr = uint32(pc) }
+ 
+-func PtraceGetRegs(pid int, regsout *PtraceRegs) (err error) {
+-	return ptrace(PTRACE_GETREGS, pid, 0, uintptr(unsafe.Pointer(regsout)))
++const syscall_PTRACE_PEEKUSR_AREA = 0x5000
++const syscall_PTRACE_POKEUSR_AREA = 0x5001
++
++type syscall_ptrace_area struct {
++	len          uint32
++	kernel_addr  uint32
++	process_addr uint32
+ }
+ 
++func PtraceGetRegs(pid int, regs *PtraceRegs) (err error) {
++	parea := syscall_ptrace_area{
++		12,
++		0,
++		uint32(uintptr(unsafe.Pointer(regs))),
++	}
++	return ptrace(syscall_PTRACE_PEEKUSR_AREA, pid, uintptr(unsafe.Pointer(&parea)), 0)
++}
++
+ func PtraceSetRegs(pid int, regs *PtraceRegs) (err error) {
+-	return ptrace(PTRACE_SETREGS, pid, 0, uintptr(unsafe.Pointer(regs)))
++	parea := syscall_ptrace_area{
++		12,
++		0,
++		uint32(uintptr(unsafe.Pointer(regs))),
++	}
++	return ptrace(syscall_PTRACE_POKEUSR_AREA, pid, uintptr(unsafe.Pointer(&parea)), 0)
+ }
+Index: libgfortran/intrinsics/execute_command_line.c
+===================================================================
+--- a/src/libgfortran/intrinsics/execute_command_line.c	(.../tags/gcc_6_4_0_release)
++++ b/src/libgfortran/intrinsics/execute_command_line.c	(.../branches/gcc-6-branch)
+@@ -126,15 +126,9 @@
+   free (cmd);
+ 
+   /* Now copy back to the Fortran string if needed.  */
+-  if (cmdstat && *cmdstat > EXEC_NOERROR)
+-    {
+-      if (cmdmsg)
+-	fstrcpy (cmdmsg, cmdmsg_len, cmdmsg_values[*cmdstat],
++  if (cmdstat && *cmdstat > EXEC_NOERROR && cmdmsg)
++    fstrcpy (cmdmsg, cmdmsg_len, cmdmsg_values[*cmdstat],
+ 		strlen (cmdmsg_values[*cmdstat]));
+-      else
+-	runtime_error ("Failure in EXECUTE_COMMAND_LINE: %s",
+-		       cmdmsg_values[*cmdstat]);
+-    }
+ }
+ 
+ 
+Index: libgfortran/ChangeLog
+===================================================================
+--- a/src/libgfortran/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/libgfortran/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,26 @@
++2018-01-03  Janne Blomqvist  <jb@gcc.gnu.org>
++
++	Backport from trunk
++	PR libgfortran/83649
++	* io/unix.c (MAX_CHUNK): New define.
++	(raw_read): For reads larger than MAX_CHUNK, loop.
++	(raw_write): Write no more than MAX_CHUNK bytes per iteration.
++
++2017-12-16  Jerry DeLisle  <jvdelisle@gcc.gnu.org>
++
++	Backport from trunk
++	PR libgfortran/81937
++	* io/list_read.c (next_char_internal): Don't attempt to read
++	from the internal unit stream if no bytes are left. Decrement
++	bytes_left in the right place.
++
++2017-10-22  Thomas Koenig  <tkoenig@gcc.gnu.org>
++
++	Backport from trunk
++	PR libfortran/82233
++	* intrinsics/execute_command_line.c (execute_command_line):
++	No call to runtime_error if cmdstat is present.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: libgfortran/io/list_read.c
+===================================================================
+--- a/src/libgfortran/io/list_read.c	(.../tags/gcc_6_4_0_release)
++++ b/src/libgfortran/io/list_read.c	(.../branches/gcc-6-branch)
+@@ -266,15 +266,19 @@
+     }
+ 
+   /* Get the next character and handle end-of-record conditions.  */
+-
+-  if (dtp->common.unit) /* Check for kind=4 internal unit.  */
+-   length = sread (dtp->u.p.current_unit->s, &c, 1);
++  if (likely (dtp->u.p.current_unit->bytes_left > 0))
++    {
++      if (dtp->common.unit) /* Check for kind=4 internal unit.  */
++	length = sread (dtp->u.p.current_unit->s, &c, 1);
++      else
++	{
++	  char cc;
++	  length = sread (dtp->u.p.current_unit->s, &cc, 1);
++	  c = cc;
++	}
++    }
+   else
+-   {
+-     char cc;
+-     length = sread (dtp->u.p.current_unit->s, &cc, 1);
+-     c = cc;
+-   }
++    length = 0;
+ 
+   if (unlikely (length < 0))
+     {
+@@ -290,7 +294,6 @@
+ 	  generate_error (&dtp->common, LIBERROR_INTERNAL_UNIT, NULL);
+ 	  return '\0';
+ 	}
+-      dtp->u.p.current_unit->bytes_left--;
+     }
+   else
+     {
+@@ -302,6 +305,7 @@
+ 	  dtp->u.p.at_eof = 1;
+ 	}
+     }
++  dtp->u.p.current_unit->bytes_left--;
+ 
+ done:
+   dtp->u.p.at_eol = (c == '\n' || c == EOF);
+Index: libgfortran/io/unix.c
+===================================================================
+--- a/src/libgfortran/io/unix.c	(.../tags/gcc_6_4_0_release)
++++ b/src/libgfortran/io/unix.c	(.../branches/gcc-6-branch)
+@@ -294,12 +294,50 @@
+   return 0;
+ }
+ 
++/* Write/read at most 2 GB - 4k chunks at a time. Linux never reads or
++   writes more than this, and there are reports that macOS fails for
++   larger than 2 GB as well.  */
++#define MAX_CHUNK 2147479552
++
+ static ssize_t
+ raw_read (unix_stream * s, void * buf, ssize_t nbyte)
+ {
+   /* For read we can't do I/O in a loop like raw_write does, because
+-     that will break applications that wait for interactive I/O.  */
+-  return read (s->fd, buf, nbyte);
++     that will break applications that wait for interactive I/O.  We
++     still can loop around EINTR, though.  This however causes a
++     problem for large reads which must be chunked, see comment above.
++     So assume that if the size is larger than the chunk size, we're
++     reading from a file and not the terminal.  */
++  if (nbyte <= MAX_CHUNK)
++    {
++      while (true)
++	{
++	  ssize_t trans = read (s->fd, buf, nbyte);
++	  if (trans == -1 && errno == EINTR)
++	    continue;
++	  return trans;
++	}
++    }
++  else
++    {
++      ssize_t bytes_left = nbyte;
++      char *buf_st = buf;
++      while (bytes_left > 0)
++	{
++	  ssize_t to_read = bytes_left < MAX_CHUNK ? bytes_left: MAX_CHUNK;
++	  ssize_t trans = read (s->fd, buf_st, to_read);
++	  if (trans == -1)
++	    {
++	      if (errno == EINTR)
++		continue;
++	      else
++		return trans;
++	    }
++	  buf_st += trans;
++	  bytes_left -= trans;
++	}
++      return nbyte - bytes_left;
++    }
+ }
+ 
+ static ssize_t
+@@ -312,10 +350,13 @@
+   buf_st = (char *) buf;
+ 
+   /* We must write in a loop since some systems don't restart system
+-     calls in case of a signal.  */
++     calls in case of a signal.  Also some systems might fail outright
++     if we try to write more than 2 GB in a single syscall, so chunk
++     up large writes.  */
+   while (bytes_left > 0)
+     {
+-      trans = write (s->fd, buf_st, bytes_left);
++      ssize_t to_write = bytes_left < MAX_CHUNK ? bytes_left: MAX_CHUNK;
++      trans = write (s->fd, buf_st, to_write);
+       if (trans < 0)
+ 	{
+ 	  if (errno == EINTR)
+Index: fixincludes/ChangeLog
+===================================================================
+--- a/src/fixincludes/ChangeLog	(.../tags/gcc_6_4_0_release)
++++ b/src/fixincludes/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,14 @@
++2017-11-11  John David Anglin  <danglin@gcc.gnu.org>
++
++	Backport from mainline
++	2017-02-25  John David Anglin  <danglin@gcc.gnu.org>
++
++	PR target/68739
++	* inclhack.def (hpux11_pthread_pointer): New fix.
++	(hpux11_pthread_const): Adjust to remove void * cast from define.
++	* fixincl.x: Regenerate.
++	* tests/base/sys/pthread.h [HPUX11_PTHREAD_CONST_CHECK]: Update tests.
++
+ 2017-07-04  Release Manager
+ 
+ 	* GCC 6.4.0 released.
+Index: fixincludes/tests/base/sys/pthread.h
+===================================================================
+--- a/src/fixincludes/tests/base/sys/pthread.h	(.../tags/gcc_6_4_0_release)
++++ b/src/fixincludes/tests/base/sys/pthread.h	(.../branches/gcc-6-branch)
+@@ -14,8 +14,13 @@
+ #endif  /* HPUX11_LWP_RWLOCK_VALID_CHECK */
+ 
+ 
++#if defined( HPUX11_PTHREAD_POINTER_CHECK )
++#define __MPOINTER		long	m_ptr
++#endif  /* HPUX11_PTHREAD_POINTER_CHECK */
++
++
+ #if defined( HPUX11_PTHREAD_CONST_CHECK )
+-#define __POINTER_SET		((void *) 1L)
++#define __POINTER_SET		1
+ #endif  /* HPUX11_PTHREAD_CONST_CHECK */
+ 
+ 
+Index: fixincludes/fixincl.x
+===================================================================
+--- a/src/fixincludes/fixincl.x	(.../tags/gcc_6_4_0_release)
++++ b/src/fixincludes/fixincl.x	(.../branches/gcc-6-branch)
+@@ -2,11 +2,11 @@
+  * 
+  * DO NOT EDIT THIS FILE   (fixincl.x)
+  * 
+- * It has been AutoGen-ed  January  5, 2017 at 06:03:22 PM by AutoGen 5.16.2
++ * It has been AutoGen-ed  Saturday November 11, 2017 at 10:44:14 AM EST
+  * From the definitions    inclhack.def
+  * and the template file   fixincl
+  */
+-/* DO NOT SVN-MERGE THIS FILE, EITHER Thu Jan  5 18:03:22 CET 2017
++/* DO NOT SVN-MERGE THIS FILE, EITHER Sat 11 Nov 2017 10:44:14 EST
+  *
+  * You must regenerate it.  Use the ./genfixes script.
+  *
+@@ -15,7 +15,7 @@
+  * certain ANSI-incompatible system header files which are fixed to work
+  * correctly with ANSI C and placed in a directory that GNU C will search.
+  *
+- * This file contains 240 fixup descriptions.
++ * This file contains 241 fixup descriptions.
+  *
+  * See README for more information.
+  *
+@@ -4326,6 +4326,43 @@
+ 
+ /* * * * * * * * * * * * * * * * * * * * * * * * * *
+  *
++ *  Description of Hpux11_Pthread_Pointer fix
++ */
++tSCC zHpux11_Pthread_PointerName[] =
++     "hpux11_pthread_pointer";
++
++/*
++ *  File name selection pattern
++ */
++tSCC zHpux11_Pthread_PointerList[] =
++  "sys/pthread.h\0";
++/*
++ *  Machine/OS name selection pattern
++ */
++tSCC* apzHpux11_Pthread_PointerMachs[] = {
++        "*-hp-hpux11.[0-3]*",
++        (const char*)NULL };
++
++/*
++ *  content selection pattern - do fix if pattern found
++ */
++tSCC zHpux11_Pthread_PointerSelect0[] =
++       "(void[ \t]*\\*)(m|c|rw)(_ptr)";
++
++#define    HPUX11_PTHREAD_POINTER_TEST_CT  1
++static tTestDesc aHpux11_Pthread_PointerTests[] = {
++  { TT_EGREP,    zHpux11_Pthread_PointerSelect0, (regex_t*)NULL }, };
++
++/*
++ *  Fix Command Arguments for Hpux11_Pthread_Pointer
++ */
++static const char* apzHpux11_Pthread_PointerPatch[] = {
++    "format",
++    "long\t%2%3",
++    (char*)NULL };
++
++/* * * * * * * * * * * * * * * * * * * * * * * * * *
++ *
+  *  Description of Hpux11_Pthread_Const fix
+  */
+ tSCC zHpux11_Pthread_ConstName[] =
+@@ -4347,7 +4384,7 @@
+  *  content selection pattern - do fix if pattern found
+  */
+ tSCC zHpux11_Pthread_ConstSelect0[] =
+-       "^#define[ \t]*__POINTER_SET[ \t]*\\(\\(void \\*\\) 1LL\\)";
++       "^(#define[ \t]+__POINTER_SET[ \t0,]*)(.*\\))";
+ 
+ #define    HPUX11_PTHREAD_CONST_TEST_CT  1
+ static tTestDesc aHpux11_Pthread_ConstTests[] = {
+@@ -4358,7 +4395,7 @@
+  */
+ static const char* apzHpux11_Pthread_ConstPatch[] = {
+     "format",
+-    "#define __POINTER_SET\t\t((void *) 1L)",
++    "%11",
+     (char*)NULL };
+ 
+ /* * * * * * * * * * * * * * * * * * * * * * * * * *
+@@ -9818,9 +9855,9 @@
+  *
+  *  List of all fixes
+  */
+-#define REGEX_COUNT          276
++#define REGEX_COUNT          277
+ #define MACH_LIST_SIZE_LIMIT 187
+-#define FIX_COUNT            240
++#define FIX_COUNT            241
+ 
+ /*
+  *  Enumerate the fixes
+@@ -9926,6 +9963,7 @@
+     HPUX11_EXTERN_SENDFILE_FIXIDX,
+     HPUX11_EXTERN_SENDPATH_FIXIDX,
+     HPUX11_FABSF_FIXIDX,
++    HPUX11_PTHREAD_POINTER_FIXIDX,
+     HPUX11_PTHREAD_CONST_FIXIDX,
+     HPUX11_SIZE_T_FIXIDX,
+     HPUX11_SNPRINTF_FIXIDX,
+@@ -10569,6 +10607,11 @@
+      HPUX11_FABSF_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
+      aHpux11_FabsfTests,   apzHpux11_FabsfPatch, 0 },
+ 
++  {  zHpux11_Pthread_PointerName,    zHpux11_Pthread_PointerList,
++     apzHpux11_Pthread_PointerMachs,
++     HPUX11_PTHREAD_POINTER_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
++     aHpux11_Pthread_PointerTests,   apzHpux11_Pthread_PointerPatch, 0 },
++
+   {  zHpux11_Pthread_ConstName,    zHpux11_Pthread_ConstList,
+      apzHpux11_Pthread_ConstMachs,
+      HPUX11_PTHREAD_CONST_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
+Index: fixincludes/inclhack.def
+===================================================================
+--- a/src/fixincludes/inclhack.def	(.../tags/gcc_6_4_0_release)
++++ b/src/fixincludes/inclhack.def	(.../branches/gcc-6-branch)
+@@ -2251,16 +2251,34 @@
+ };
+ 
+ /*
+- *  Fix C99 constant in __POINTER_SET define.
++ *  The definitions for PTHREAD_MUTEX_INITIALIZER and similar initializers
++ *  in pthread.h need to be constant expressions to be standard complient.
++ *  As a result, we need to remove the void * casts in the initializers
++ *  (see hpux11_pthread_const) and to change the __(M|C|RW)POINTER defines
++ *  to use the long type.
+  */
+ fix = {
++    hackname  = hpux11_pthread_pointer;
++    mach      = "*-hp-hpux11.[0-3]*";
++    files     = sys/pthread.h;
++    select    = "(void[ \t]*\\*)(m|c|rw)(_ptr)";
++
++    c_fix     = format;
++    c_fix_arg = "long\t%2%3";
++    test_text = "#define __MPOINTER\t\tvoid\t *m_ptr";
++};
++
++/*
++ *  Remove void pointer cast and fix C99 constant in __POINTER_SET defines.
++ */
++fix = {
+     hackname  = hpux11_pthread_const;
+     mach      = "*-hp-hpux11.[0-3]*";
+     files     = sys/pthread.h;
+-    select    = "^#define[ \t]*__POINTER_SET[ \t]*\\(\\(void \\*\\) 1LL\\)";
++    select    = "^(#define[ \t]+__POINTER_SET[ \t0,]*)(.*\\))";
+ 
+     c_fix     = format;
+-    c_fix_arg = "#define __POINTER_SET\t\t((void *) 1L)";
++    c_fix_arg = "%11";
+     test_text = "#define __POINTER_SET\t\t((void *) 1LL)";
+ };
+ 
--- gcc-6-6.4.0.orig/debian/patches/sys-auxv-header.diff
+++ gcc-6-6.4.0/debian/patches/sys-auxv-header.diff
@@ -0,0 +1,46 @@
+# DP: Check for the sys/auxv.h header file.
+
+Index: b/src/gcc/configure.ac
+===================================================================
+--- a/src/gcc/configure.ac
++++ b/src/gcc/configure.ac
+@@ -1093,6 +1093,7 @@ AC_HEADER_TIOCGWINSZ
+ AC_CHECK_HEADERS(limits.h stddef.h string.h strings.h stdlib.h time.h iconv.h \
+ 		 fcntl.h ftw.h unistd.h sys/file.h sys/time.h sys/mman.h \
+ 		 sys/resource.h sys/param.h sys/times.h sys/stat.h \
++		 sys/auxv.h \
+ 		 direct.h malloc.h langinfo.h ldfcn.h locale.h wchar.h)
+ 
+ # Check for thread headers.
+Index: b/src/gcc/config.in
+===================================================================
+--- a/src/gcc/config.in
++++ b/src/gcc/config.in
+@@ -1736,6 +1736,12 @@
+ #endif
+ 
+ 
++/* Define to 1 if you have the <sys/auxv.h> header file. */
++#ifndef USED_FOR_TARGET
++#undef HAVE_SYS_AUXV_H
++#endif
++
++
+ /* Define to 1 if you have the <sys/file.h> header file. */
+ #ifndef USED_FOR_TARGET
+ #undef HAVE_SYS_FILE_H
+Index: b/src/gcc/config/rs6000/driver-rs6000.c
+===================================================================
+--- a/src/gcc/config/rs6000/driver-rs6000.c
++++ b/src/gcc/config/rs6000/driver-rs6000.c
+@@ -31,6 +31,10 @@ along with GCC; see the file COPYING3.
+ # include <link.h>
+ #endif
+ 
++#ifdef HAVE_SYS_AUXV_H
++# include <sys/auxv.h>
++#endif
++
+ #if defined (__APPLE__) || (__FreeBSD__)
+ # include <sys/types.h>
+ # include <sys/sysctl.h>
--- gcc-6-6.4.0.orig/debian/patches/testsuite-glibc-warnings.diff
+++ gcc-6-6.4.0/debian/patches/testsuite-glibc-warnings.diff
@@ -0,0 +1,29 @@
+# DP: fix testcases that triggered -Wunused-result with glibc
+# DP: Author: Steve Beattie <steve.beattie@canonical.com>
+---
+ src/gcc/testsuite/c-c++-common/cilk-plus/AN/comma_exp.c |    2 +-
+ src/gcc/testsuite/c-c++-common/tsan/fd_pipe_race.c      |    1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+Index: b/src/gcc/testsuite/c-c++-common/tsan/fd_pipe_race.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/tsan/fd_pipe_race.c
++++ b/src/gcc/testsuite/c-c++-common/tsan/fd_pipe_race.c
+@@ -1,5 +1,5 @@
+ /* { dg-shouldfail "tsan" } */
+-/* { dg-additional-options "-ldl" } */
++/* { dg-additional-options "-Wno-unused-result -ldl" } */
+ 
+ #include <pthread.h>
+ #include <unistd.h>
+Index: b/src/gcc/testsuite/c-c++-common/cilk-plus/AN/comma_exp.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/cilk-plus/AN/comma_exp.c
++++ b/src/gcc/testsuite/c-c++-common/cilk-plus/AN/comma_exp.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-fcilkplus" } */
++/* { dg-options "-fcilkplus -Wno-unused-result" } */
+ 
+ #include <stdlib.h>
+ 
--- gcc-6-6.4.0.orig/debian/patches/testsuite-hardening-format.diff
+++ gcc-6-6.4.0/debian/patches/testsuite-hardening-format.diff
@@ -0,0 +1,371 @@
+#! /bin/sh -e
+
+# All lines beginning with `# DPATCH:' are a description of the patch.
+# DP: Description: use -Wno-format on tests that cannot be adjusted other ways.
+# DP: Author: Kees Cook <kees@ubuntu.com>
+# DP: Ubuntu: https://bugs.launchpad.net/bugs/344502
+
+dir=
+if [ $# -eq 3 -a "$2" = '-d' ]; then
+    pdir="-d $3"
+    dir="$3/"
+elif [ $# -ne 1 ]; then
+    echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
+    exit 1
+fi
+case "$1" in
+    -patch)
+        patch $pdir -f --no-backup-if-mismatch -p1 < $0
+        #cd ${dir}gcc && autoconf
+        ;;
+    -unpatch)
+        patch $pdir -f --no-backup-if-mismatch -R -p1 < $0
+        #rm ${dir}gcc/configure
+        ;;
+    *)
+        echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
+        exit 1
+esac
+exit 0
+
+---
+ src/boehm-gc/testsuite/boehm-gc.c/middle.c                 |    3 +++
+ src/gcc/testsuite/c-c++-common/torture/vector-compare-1.c  |    1 +
+ src/gcc/testsuite/g++.dg/abi/pragma-pack1.C                |    2 ++
+ src/gcc/testsuite/g++.dg/abi/regparm1.C                    |    1 +
+ src/gcc/testsuite/g++.dg/cpp0x/constexpr-tuple.C           |    1 +
+ src/gcc/testsuite/g++.dg/torture/pr51436.C                 |    1 +
+ src/gcc/testsuite/g++.old-deja/g++.law/weak.C              |    2 +-
+ src/gcc/testsuite/g++.old-deja/g++.other/std1.C            |    1 +
+ src/gcc/testsuite/gcc.c-torture/execute/vfprintf-chk-1.x   |    5 +++++
+ src/gcc/testsuite/gcc.c-torture/execute/vprintf-chk-1.x    |    5 +++++
+ src/gcc/testsuite/gcc.dg/charset/builtin2.c                |    2 +-
+ src/gcc/testsuite/gcc.dg/format/format.exp                 |    2 +-
+ src/gcc/testsuite/gcc.dg/ipa/ipa-sra-1.c                   |    2 +-
+ src/gcc/testsuite/gcc.dg/lto/20090218-2_0.c                |    2 ++
+ src/gcc/testsuite/gcc.dg/pr30473.c                         |    2 +-
+ src/gcc/testsuite/gcc.dg/pr38902.c                         |    2 +-
+ src/gcc/testsuite/gcc.dg/pr59418.c                         |    2 +-
+ src/gcc/testsuite/gcc.dg/torture/tls/tls-test.c            |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-1.c      |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-chk-1.c  |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-1.c       |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-chk-1.c   |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-1.c     |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-chk-1.c |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-1.c      |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-chk-1.c  |    2 +-
+ src/gcc/testsuite/gcc.dg/tree-ssa/isolate-4.c              |    2 +-
+ src/gcc/testsuite/objc.dg/torture/strings/const-str-3.m    |    2 +-
+ 28 files changed, 40 insertions(+), 18 deletions(-)
+
+Index: b/src/gcc/testsuite/gcc.c-torture/execute/vfprintf-chk-1.x
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/execute/vfprintf-chk-1.x
+@@ -0,0 +1,5 @@
++# Implement "/* { dg-options "-U_FORITFY_SOURCE" } */", due to
++# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=20567
++
++set additional_flags "-U_FORTIFY_SOURCE"
++return 0
+Index: b/src/gcc/testsuite/gcc.c-torture/execute/vprintf-chk-1.x
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/execute/vprintf-chk-1.x
+@@ -0,0 +1,5 @@
++# Implement "/* { dg-options "-U_FORITFY_SOURCE" } */", due to
++# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=20567
++
++set additional_flags "-U_FORTIFY_SOURCE"
++return 0
+Index: b/src/gcc/testsuite/gcc.dg/charset/builtin2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/charset/builtin2.c
++++ b/src/gcc/testsuite/gcc.dg/charset/builtin2.c
+@@ -3,7 +3,7 @@
+ 
+ /* { dg-do compile } */
+ /* { dg-require-iconv "IBM1047" } */
+-/* { dg-options "-O2 -fexec-charset=IBM1047" } */
++/* { dg-options "-O2 -fexec-charset=IBM1047 -Wno-format" } */
+ /* { dg-final { scan-assembler-not "printf" } } */
+ /* { dg-final { scan-assembler-not "fprintf" } } */
+ /* { dg-final { scan-assembler-not "sprintf" } } */
+Index: b/src/gcc/testsuite/gcc.dg/format/format.exp
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/format/format.exp
++++ b/src/gcc/testsuite/gcc.dg/format/format.exp
+@@ -26,7 +26,7 @@ load_lib gcc-dg.exp
+ load_lib torture-options.exp
+ 
+ torture-init
+-set-torture-options [list { } { -DWIDE } ]
++set-torture-options [list { -Wformat=0 } { -DWIDE -Wformat=0 } ]
+ 
+ dg-init
+ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] "" ""
+Index: b/src/gcc/testsuite/gcc.dg/pr30473.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr30473.c
++++ b/src/gcc/testsuite/gcc.dg/pr30473.c
+@@ -1,7 +1,7 @@
+ /* PR middle-end/30473 */
+ /* Make sure this doesn't ICE.  */
+ /* { dg-do compile } */
+-/* { dg-options "-O2" } */
++/* { dg-options "-O2 -Wno-format" } */
+ 
+ extern int sprintf (char *, const char *, ...);
+ 
+Index: b/src/gcc/testsuite/gcc.dg/pr38902.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr38902.c
++++ b/src/gcc/testsuite/gcc.dg/pr38902.c
+@@ -1,6 +1,6 @@
+ /* PR target/38902 */
+ /* { dg-do run } */
+-/* { dg-options "-O2 -fstack-protector" } */
++/* { dg-options "-O2 -fstack-protector -Wno-format" } */
+ /* { dg-require-effective-target fstack_protector } */
+ 
+ #ifdef DEBUG
+Index: b/src/gcc/testsuite/gcc.dg/pr59418.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr59418.c
++++ b/src/gcc/testsuite/gcc.dg/pr59418.c
+@@ -2,7 +2,7 @@
+ /* Reported by Ryan Mansfield <rmansfield@qnx.com> */
+ 
+ /* { dg-do compile } */
+-/* { dg-options "-Os -g" } */
++/* { dg-options "-Os -g -Wno-format-zero-length" } */
+ /* { dg-options "-march=armv7-a -mfloat-abi=hard -Os -g" { target { arm*-*-* && { ! arm_thumb1 } } } } */
+ 
+ extern int printf (const char *__format, ...);
+Index: b/src/gcc/testsuite/gcc.dg/ipa/ipa-sra-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/ipa/ipa-sra-1.c
++++ b/src/gcc/testsuite/gcc.dg/ipa/ipa-sra-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-O2 -fipa-sra -fdump-tree-eipa_sra-details"  } */
++/* { dg-options "-O2 -fipa-sra -fdump-tree-eipa_sra-details -Wformat=0"  } */
+ 
+ struct bovid
+ {
+Index: b/src/gcc/testsuite/gcc.dg/lto/20090218-2_0.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/lto/20090218-2_0.c
++++ b/src/gcc/testsuite/gcc.dg/lto/20090218-2_0.c
+@@ -1,3 +1,5 @@
++/* { dg-lto-options "-Wno-nonnull" } */
++
+ void set_mem_alias_set ();
+ void emit_push_insn () {
+   set_mem_alias_set ();
+Index: b/src/gcc/testsuite/c-c++-common/torture/vector-compare-1.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/torture/vector-compare-1.c
++++ b/src/gcc/testsuite/c-c++-common/torture/vector-compare-1.c
+@@ -1,4 +1,5 @@
+ /* { dg-do run } */
++/* { dg-options "-Wformat=0" } */
+ #define vector(elcount, type)  \
+ __attribute__((vector_size((elcount)*sizeof(type)))) type
+ 
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-chk-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-chk-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-chk-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ #include <stdarg.h>
+ 
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vprintf-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ #include <stdarg.h>
+ 
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ extern int printf (const char *, ...);
+ volatile int vi0, vi1, vi2, vi3, vi4, vi5, vi6, vi7, vi8, vi9, via;
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-chk-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-chk-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-printf-chk-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ extern int __printf_chk (int, const char *, ...);
+ volatile int vi0, vi1, vi2, vi3, vi4, vi5, vi6, vi7, vi8, vi9, via;
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ typedef struct { int i; } FILE;
+ FILE *fp;
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-chk-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-chk-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-fprintf-chk-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ typedef struct { int i; } FILE;
+ FILE *fp;
+Index: b/src/gcc/testsuite/gcc.dg/torture/tls/tls-test.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/tls/tls-test.c
++++ b/src/gcc/testsuite/gcc.dg/torture/tls/tls-test.c
+@@ -1,7 +1,7 @@
+ /* { dg-do run }  */
+ /* { dg-require-effective-target tls  }  */
+ /* { dg-require-effective-target pthread } */
+-/* { dg-options "-pthread" } */
++/* { dg-options "-pthread -Wformat=0" } */
+ 
+ #include <pthread.h>
+ extern int printf (char *,...);
+Index: b/src/boehm-gc/testsuite/boehm-gc.c/middle.c
+===================================================================
+--- a/src/boehm-gc/testsuite/boehm-gc.c/middle.c
++++ b/src/boehm-gc/testsuite/boehm-gc.c/middle.c
+@@ -2,6 +2,9 @@
+  * Test at the boundary between small and large objects.
+  * Inspired by a test case from Zoltan Varga.
+  */
++
++/* { dg-options "-Wformat=0" } */
++
+ #include <gc.h>
+ #include <stdio.h>
+ 
+Index: b/src/gcc/testsuite/objc.dg/torture/strings/const-str-3.m
+===================================================================
+--- a/src/gcc/testsuite/objc.dg/torture/strings/const-str-3.m
++++ b/src/gcc/testsuite/objc.dg/torture/strings/const-str-3.m
+@@ -2,7 +2,7 @@
+ /* Developed by Markus Hitter <mah@jump-ing.de>.  */
+ /* { dg-do run } */
+ /* { dg-xfail-run-if "Needs OBJC2 ABI" { *-*-darwin* && { lp64 && { ! objc2 } } } { "-fnext-runtime" } { "" } } */
+-/* { dg-options "-fconstant-string-class=Foo" } */
++/* { dg-options "-fconstant-string-class=Foo -Wno-format-security" } */
+ /* { dg-options "-mno-constant-cfstrings -fconstant-string-class=Foo" { target *-*-darwin* } } */
+ 
+ #include "../../../objc-obj-c++-shared/objc-test-suite-types.h"
+Index: b/src/gcc/testsuite/g++.dg/abi/pragma-pack1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/abi/pragma-pack1.C
++++ b/src/gcc/testsuite/g++.dg/abi/pragma-pack1.C
+@@ -1,5 +1,7 @@
+ // PR c++/7046
+ 
++// { dg-options "-Wformat=0" }
++
+ extern "C" int printf (const char *, ...);
+ 
+ #pragma pack(4)
+Index: b/src/gcc/testsuite/g++.dg/abi/regparm1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/abi/regparm1.C
++++ b/src/gcc/testsuite/g++.dg/abi/regparm1.C
+@@ -1,6 +1,7 @@
+ // PR c++/29911 (9381)
+ // { dg-do run { target i?86-*-* x86_64-*-* } }
+ // { dg-require-effective-target c++11 }
++// { dg-options "-Wformat=0" }
+ 
+ extern "C" int printf(const char *, ...);
+ 
+Index: b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-tuple.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-tuple.C
++++ b/src/gcc/testsuite/g++.dg/cpp0x/constexpr-tuple.C
+@@ -1,5 +1,6 @@
+ // PR c++/53202
+ // { dg-do run { target c++11 } }
++// { dg-options "-Wformat=0" }
+ 
+ #include <tuple>
+ 
+Index: b/src/gcc/testsuite/g++.dg/torture/pr51436.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/torture/pr51436.C
++++ b/src/gcc/testsuite/g++.dg/torture/pr51436.C
+@@ -1,4 +1,5 @@
+ /* { dg-do compile } */
++/* { dg-options "-Wno-nonnull" } */
+ 
+ typedef __SIZE_TYPE__ size_t;
+ extern "C" void *memcpy (void *, __const void *, size_t);
+Index: b/src/gcc/testsuite/g++.old-deja/g++.law/weak.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.law/weak.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.law/weak.C
+@@ -1,6 +1,6 @@
+ // { dg-do link { target i?86-*-linux* i?86-*-gnu* x86_64-*-linux* } }
+ // { dg-require-effective-target static }
+-// { dg-options "-static" }
++// { dg-options "-static -Wno-nonnull" }
+ // Bug: g++ fails to instantiate operator<<.
+ 
+ // libc-5.4.xx has __IO_putc in its static C library, which can conflict
+Index: b/src/gcc/testsuite/g++.old-deja/g++.other/std1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.other/std1.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.other/std1.C
+@@ -1,4 +1,5 @@
+ // { dg-do assemble  }
++// { dg-options "-Wno-nonnull" }
+ // Origin: Mark Mitchell <mark@codesourcery.com>
+ 
+ extern "C" int memcmp (const void * __s1,
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ #include <stdarg.h>
+ 
+Index: b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-chk-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-chk-1.c
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/builtin-vfprintf-chk-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-fab1" } */
++/* { dg-options "-O2 -fdump-tree-fab1 -Wno-format-zero-length" } */
+ 
+ #include <stdarg.h>
+ 
--- gcc-6-6.4.0.orig/debian/patches/testsuite-hardening-printf-types.diff
+++ gcc-6-6.4.0/debian/patches/testsuite-hardening-printf-types.diff
@@ -0,0 +1,667 @@
+# DP: Description: adjust/standardize printf types to avoid -Wformat warnings.
+# DP: Author: Kees Cook <kees@ubuntu.com>
+# DP: Ubuntu: https://bugs.launchpad.net/bugs/344502
+
+Index: b/src/gcc/testsuite/g++.dg/ext/align1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/ext/align1.C
++++ b/src/gcc/testsuite/g++.dg/ext/align1.C
+@@ -16,6 +16,7 @@ float f1 __attribute__ ((aligned));
+ int
+ main (void)
+ {
+-  printf ("%d %d\n", __alignof (a1), __alignof (f1));
++  // "%td" is not allowed by ISO C++, so use %p with a void * cast
++  printf ("%p %p\n", (void*)__alignof (a1), (void*)__alignof (f1));
+   return (__alignof (a1) < __alignof (f1));
+ }
+Index: b/src/gcc/testsuite/g++.old-deja/g++.law/operators28.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.law/operators28.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.law/operators28.C
+@@ -14,7 +14,8 @@ void* new_test::operator new(size_t sz,
+ {
+   void *p;
+ 
+-  printf("%d %d %d\n", sz, count, type);
++  // ISO C++ does not support format size modifier "z", so use a cast
++  printf("%u %d %d\n", (unsigned int)sz, count, type);
+ 
+   p = new char[sz * count];
+   ((new_test *)p)->type = type;
+Index: b/src/gcc/testsuite/gcc.dg/torture/matrix-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/matrix-2.c
++++ b/src/gcc/testsuite/gcc.dg/torture/matrix-2.c
+@@ -42,7 +42,7 @@ main (int argc, char **argv)
+     }
+   for (i = 0; i < ARCHnodes; i++)
+     for (j = 0; j < 3; j++)
+-      printf ("%x\n",vel[i][j]);
++      printf ("%p\n",vel[i][j]);
+       /*if (i!=1 || j!=1)*/
+       /*if (i==1 && j==1)
+         continue;
+@@ -82,14 +82,14 @@ mem_init (void)
+       for (j = 0; j < 3; j++)
+ 	{
+ 	  vel[i][j] = (int *) malloc (ARCHnodes1 * sizeof (int));
+-          printf ("%x %d %d\n",vel[i][j], ARCHnodes1, sizeof (int));
++          printf ("%p %d %d\n",vel[i][j], ARCHnodes1, (int)sizeof (int));
+ 	}
+     }
+    for (i = 0; i < ARCHnodes; i++)
+     {
+       for (j = 0; j < 3; j++)
+         {
+-          printf ("%x\n",vel[i][j]);
++          printf ("%p\n",vel[i][j]);
+         }
+     }
+ 
+@@ -98,7 +98,7 @@ mem_init (void)
+     {
+       for (j = 0; j < 3; j++)
+ 	{
+-	  printf ("%x\n",vel[i][j]);
++	  printf ("%p\n",vel[i][j]);
+           /*for (k = 0; k < ARCHnodes1; k++)
+ 	    {
+ 	      vel[i][j][k] = d;
+Index: b/src/gcc/testsuite/gcc.dg/packed-vla.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/packed-vla.c
++++ b/src/gcc/testsuite/gcc.dg/packed-vla.c
+@@ -18,8 +18,8 @@ int func(int levels)
+     int			b[4];
+   } __attribute__ ((__packed__)) foo;
+ 
+-  printf("foo %d\n", sizeof(foo));
+-  printf("bar %d\n", sizeof(bar));
++  printf("foo %d\n", (int)sizeof(foo));
++  printf("bar %d\n", (int)sizeof(bar));
+ 
+   if (sizeof (foo) != sizeof (bar))
+     abort ();
+Index: b/src/gcc/testsuite/g++.dg/opt/alias2.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/opt/alias2.C
++++ b/src/gcc/testsuite/g++.dg/opt/alias2.C
+@@ -30,14 +30,14 @@ public:
+ 
+ 
+ _Deque_base::~_Deque_base() {
+-  printf ("bb %x %x\n", this, *_M_start._M_node);
++  printf ("bb %p %x\n", this, *_M_start._M_node);
+ }
+ 
+ void
+ _Deque_base::_M_initialize_map()
+ {
+   yy = 0x123;
+-  printf ("aa %x %x\n", this, yy);
++  printf ("aa %p %x\n", this, yy);
+ 
+   _M_start._M_node = &yy;
+   _M_start._M_cur = yy;
+Index: b/src/gcc/testsuite/g++.old-deja/g++.abi/vbase1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.abi/vbase1.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.abi/vbase1.C
+@@ -33,7 +33,7 @@ struct VBase
+   void Offset () const
+   {
+     printf ("VBase\n");
+-    printf ("  VBase::member %d\n", &this->VBase::member - (int *)this);
++    printf ("  VBase::member %d\n", (int)(&this->VBase::member - (int *)this));
+   }
+ };
+ 
+@@ -55,8 +55,8 @@ struct VDerived : virtual VBase
+   void Offset () const
+   {
+     printf ("VDerived\n");
+-    printf ("  VBase::member %d\n", &this->VBase::member - (int *)this);
+-    printf ("  VDerived::member %d\n", &this->VDerived::member - (int *)this);
++    printf ("  VBase::member %d\n", (int)(&this->VBase::member - (int *)this));
++    printf ("  VDerived::member %d\n", (int)(&this->VDerived::member - (int *)this));
+   }
+ };
+ struct B : virtual VBase
+@@ -65,8 +65,8 @@ struct B : virtual VBase
+   void Offset () const
+   {
+     printf ("B\n");
+-    printf ("  VBase::member %d\n", &this->VBase::member - (int *)this);
+-    printf ("  B::member %d\n", &this->B::member - (int *)this);
++    printf ("  VBase::member %d\n", (int)(&this->VBase::member - (int *)this));
++    printf ("  B::member %d\n", (int)(&this->B::member - (int *)this));
+   }
+ };
+ struct MostDerived : B, virtual VDerived
+@@ -75,10 +75,10 @@ struct MostDerived : B, virtual VDerived
+   void Offset () const
+   {
+     printf ("MostDerived\n");
+-    printf ("  VBase::member %d\n", &this->VBase::member - (int *)this);
+-    printf ("  B::member %d\n", &this->B::member - (int *)this);
+-    printf ("  VDerived::member %d\n", &this->VDerived::member - (int *)this);
+-    printf ("  MostDerived::member %d\n", &this->MostDerived::member - (int *)this);
++    printf ("  VBase::member %d\n", (int)(&this->VBase::member - (int *)this));
++    printf ("  B::member %d\n", (int)(&this->B::member - (int *)this));
++    printf ("  VDerived::member %d\n", (int)(&this->VDerived::member - (int *)this));
++    printf ("  MostDerived::member %d\n", (int)(&this->MostDerived::member - (int *)this));
+   }
+ };
+ 
+@@ -95,10 +95,10 @@ int main ()
+     if (ctorVDerived != &dum.VDerived::member)
+       return 24;
+     
+-    printf ("  VBase::member %d\n", &dum.VBase::member - this_);
+-    printf ("  B::member %d\n", &dum.B::member - this_);
+-    printf ("  VDerived::member %d\n", &dum.VDerived::member - this_);
+-    printf ("  MostDerived::member %d\n", &dum.MostDerived::member - this_);
++    printf ("  VBase::member %d\n", (int)(&dum.VBase::member - this_));
++    printf ("  B::member %d\n", (int)(&dum.B::member - this_));
++    printf ("  VDerived::member %d\n", (int)(&dum.VDerived::member - this_));
++    printf ("  MostDerived::member %d\n", (int)(&dum.MostDerived::member - this_));
+     dum.MostDerived::Offset ();
+     dum.B::Offset ();
+     dum.VDerived::Offset ();
+Index: b/src/gcc/testsuite/g++.old-deja/g++.brendan/template8.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.brendan/template8.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.brendan/template8.C
+@@ -15,6 +15,6 @@ int main(){
+ 	
+ 	Double_alignt<20000> heap;
+ 
+-	printf(" &heap.array[0] = %d, &heap.for_alignt = %d\n", &heap.array[0], &heap.for_alignt);
++	printf(" &heap.array[0] = %p, &heap.for_alignt = %p\n", (void*)&heap.array[0], (void*)&heap.for_alignt);
+ 
+ }
+Index: b/src/gcc/testsuite/g++.old-deja/g++.eh/ptr1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.eh/ptr1.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.eh/ptr1.C
+@@ -16,7 +16,7 @@ int main()
+   }
+ 
+   catch (E *&e) {
+-    printf ("address of e is 0x%lx\n", (__SIZE_TYPE__)e);
++    printf ("address of e is %p\n", (void *)e);
+     return !((__SIZE_TYPE__)e != 5 && e->x == 5);
+   }
+   return 2;
+Index: b/src/gcc/testsuite/g++.old-deja/g++.jason/access23.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.jason/access23.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.jason/access23.C
+@@ -42,19 +42,19 @@ public:
+   void DoSomething() {
+     PUB_A = 0;
+     Foo::A = 0;
+-    printf("%x\n",pX);  
++    printf("%p\n",pX);  
+     Foo::PUB.A = 0;
+-    printf("%x\n",PUB.pX);  
++    printf("%p\n",PUB.pX);  
+     B = 0;			
+-    printf("%x\n",Foo::pY);  
++    printf("%p\n",Foo::pY);  
+     PRT_A = 0;
+     PRT.B = 0;		
+-    printf("%x\n",Foo::PRT.pY);	
++    printf("%p\n",Foo::PRT.pY);	
+     PRV_A = 0;			// { dg-error "" } 
+     Foo::C = 0;			// { dg-error "" } 
+-    printf("%x\n",pZ);  	// { dg-error "" } 
++    printf("%p\n",pZ);  	// { dg-error "" } 
+     Foo::PRV.C = 0;		// { dg-error "" } 
+-    printf("%x\n",PRV.pZ); 	// { dg-error "" } 
++    printf("%p\n",PRV.pZ); 	// { dg-error "" } 
+   }
+ };
+ 
+@@ -64,17 +64,17 @@ int main()
+ 
+   a.PUB_A = 0;
+   a.A = 0;
+-  printf("%x\n",a.pX);  
++  printf("%p\n",a.pX);  
+   a.PRT_A = 0;			// { dg-error "" } 
+   a.B = 0;			// { dg-error "" } 
+-  printf("%x\n",a.pY);  	// { dg-error "" } 
++  printf("%p\n",a.pY);  	// { dg-error "" } 
+   a.PRV_A = 0;			// { dg-error "" } 
+   a.C = 0;			// { dg-error "" } 
+-  printf("%x\n",a.pZ);  	// { dg-error "" } 
++  printf("%p\n",a.pZ);  	// { dg-error "" } 
+   a.PUB.A = 0;
+-  printf("%x\n",a.PUB.pX);  
++  printf("%p\n",a.PUB.pX);  
+   a.PRT.B = 0;			// { dg-error "" } 
+-  printf("%x\n",a.PRT.pY);  	// { dg-error "" } 
++  printf("%p\n",a.PRT.pY);  	// { dg-error "" } 
+   a.PRV.C = 0;			// { dg-error "" } 
+-  printf("%x\n",a.PRV.pZ);  	// { dg-error "" } 
++  printf("%p\n",a.PRV.pZ);  	// { dg-error "" } 
+ }
+Index: b/src/gcc/testsuite/g++.old-deja/g++.law/cvt8.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.law/cvt8.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.law/cvt8.C
+@@ -20,12 +20,12 @@ struct B {
+ B::operator const A&() const {
+         static A a;
+         a.i = i;
+-        printf("convert B to A at %x\n", &a);
++        printf("convert B to A at %p\n", (void*)&a);
+         return a;
+ }
+ 
+ void f(A &a) { // { dg-message "" } in passing argument
+-        printf("A at %x is %d\n", &a, a.i);
++  printf("A at %p is %d\n", (void*)&a, a.i);
+ }
+ 
+ int main() {
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/net35.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/net35.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/net35.C
+@@ -17,10 +17,10 @@ public:
+ 
+ int main() {
+   C c;
+-  printf("&c.x = %x\n", &c.x);
+-  printf("&c.B1::x = %x\n", &c.B1::x);
+-  printf("&c.B2::x = %x\n", &c.B2::x);
+-  printf("&c.A::x = %x\n", &c.A::x);
++  printf("&c.x = %p\n", (void*)&c.x);
++  printf("&c.B1::x = %p\n", (void*)&c.B1::x);
++  printf("&c.B2::x = %p\n", (void*)&c.B2::x);
++  printf("&c.A::x = %p\n", (void*)&c.A::x);
+   if (&c.x != &c.B1::x
+       || &c.x != &c.B2::x
+       || &c.x != &c.A::x)
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/offset1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/offset1.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/offset1.C
+@@ -6,7 +6,7 @@ int fail = 0;
+ class Foo {
+ public:
+    virtual void setName() {
+-     printf("Foo at %x\n", this);
++     printf("Foo at %p\n", (void*)this);
+      if (vp != (void*)this)
+        fail = 1;
+    }
+@@ -15,7 +15,7 @@ public:
+ class Bar : public Foo {
+ public:
+   virtual void init(int argc, char **argv) {
+-    printf("Bar's Foo at %x\n", (Foo*)this);
++    printf("Bar's Foo at %p\n", (void*)(Foo*)this);
+     vp = (void*)(Foo*)this;
+     setName();
+   }
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p12306.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p12306.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p12306.C
+@@ -18,7 +18,7 @@ public:
+     if (ptr2 != &(*this).slist)
+       fail = 6;
+ 
+-    if (0) printf("at %x %x\n", (RWSlistIterator*)this, &(*this).slist);
++    if (0) printf("at %p %p\n", (void*)(RWSlistIterator*)this, (void*)&(*this).slist);
+   }
+ };
+ 
+@@ -54,14 +54,14 @@ Sim_Event_Manager::Sim_Event_Manager ()
+ void Sim_Event_Manager::post_event () {
+   ptr1 = (RWSlistIterator*)&last_posted_event_position_;
+   ptr2 = &((RWSlistIterator*)&last_posted_event_position_)->slist;
+-  if (0) printf("at %x %x\n", (RWSlistIterator*)&last_posted_event_position_,
+-		&((RWSlistIterator*)&last_posted_event_position_)->slist);
++  if (0) printf("at %p %p\n", (void*)(RWSlistIterator*)&last_posted_event_position_,
++		(void*)&((RWSlistIterator*)&last_posted_event_position_)->slist);
+   if (ptr1 != (RWSlistIterator*)&last_posted_event_position_)
+     fail = 1;
+   if (ptr2 != &((RWSlistIterator&)last_posted_event_position_).slist)
+     fail = 2;
+-  if (0) printf("at %x ?%x\n", (RWSlistIterator*)&last_posted_event_position_,
+-		&((RWSlistIterator&)last_posted_event_position_).slist);
++  if (0) printf("at %p ?%p\n", (void*)(RWSlistIterator*)&last_posted_event_position_,
++		(void*)&((RWSlistIterator&)last_posted_event_position_).slist);
+   if (ptr1 != (RWSlistIterator*)&last_posted_event_position_)
+     fail = 3;
+   if (ptr2 != &((RWSlistIterator&)last_posted_event_position_).slist)
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p3579.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p3579.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p3579.C
+@@ -7,26 +7,26 @@ int num_x;
+ 
+ class Y {
+ public:
+-  Y () { printf("Y()            this: %x\n", this); }
+-  ~Y () { printf("~Y()           this: %x\n", this); }
++  Y () { printf("Y()            this: %p\n", (void*)this); }
++  ~Y () { printf("~Y()           this: %p\n", (void*)this); }
+ };
+ 
+ class X {
+ public:
+   X () {
+     ++num_x;
+-    printf("X()            this: %x\n", this);
++    printf("X()            this: %p\n", (void*)this);
+     Y y;
+     *this = (X) y;
+   }
+ 
+-  X (const Y & yy) { printf("X(const Y&)    this: %x\n", this); ++num_x; }
++  X (const Y & yy) { printf("X(const Y&)    this: %p\n", (void*)this); ++num_x; }
+   X & operator = (const X & xx) {
+-    printf("X.op=(X&)      this: %x\n", this);
++    printf("X.op=(X&)      this: %p\n", (void*)this);
+     return *this;
+   }
+ 
+-  ~X () { printf("~X()           this: %x\n", this); --num_x; }
++  ~X () { printf("~X()           this: %p\n", (void*)this); --num_x; }
+ };
+ 
+ int main (int, char **) {
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708a.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p3708a.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708a.C
+@@ -38,7 +38,7 @@ public:
+   virtual void xx(int doit) {
+     --num;
+     if (ptr != this)
+-      printf("FAIL\n%x != %x\n", ptr, this);
++      printf("FAIL\n%p != %p\n", ptr, (void*)this);
+     printf ("C is destructed.\n");
+     B::xx (0);
+     if (doit) A::xx (1);
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708b.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p3708b.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708b.C
+@@ -48,7 +48,7 @@ public:
+   virtual void xx(int doit) {
+     --num;
+     if (ptr != this) {
+-      printf("FAIL\n%x != %x\n", ptr, this);
++      printf("FAIL\n%p != %p\n", ptr, (void*)this);
+       exit(1);
+     }
+     printf ("D is destructed.\n");
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p3708.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p3708.C
+@@ -38,7 +38,7 @@ public:
+   virtual void xx(int doit) {
+     --num;
+     if (ptr != this)
+-      printf("FAIL\n%x != %x\n", ptr, this);
++      printf("FAIL\n%p != %p\n", ptr, (void*)this);
+     printf ("C is destructed.\n");
+     B::xx (0);
+     if (doit) A::xx (1);
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p646.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p646.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p646.C
+@@ -35,20 +35,20 @@ int foo::si = 0;
+ foo::foo ()
+ {
+   si++;
+-  printf ("new foo @ 0x%x; now %d foos\n", this, si);
++  printf ("new foo @ %p; now %d foos\n", (void*)this, si);
+ }
+ 
+ foo::foo (const foo &other)
+ {
+   si++;
+-  printf ("another foo @ 0x%x; now %d foos\n", this, si);
++  printf ("another foo @ %p; now %d foos\n", (void*)this, si);
+   *this = other;
+ }
+ 
+ foo::~foo ()
+ {
+   si--;
+-  printf ("deleted foo @ 0x%x; now %d foos\n", this, si);
++  printf ("deleted foo @ %p; now %d foos\n", (void*)this, si);
+ }
+ 
+ int
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p710.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p710.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p710.C
+@@ -30,7 +30,7 @@ class B
+    virtual ~B() {}
+    void operator delete(void*,size_t s)
+   {
+-      printf("B::delete() %d\n",s);
++      printf("B::delete() %u\n",(unsigned int)s);
+    }
+    void operator delete(void*){}
+ };
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/p789a.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/p789a.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/p789a.C
+@@ -13,10 +13,10 @@ struct foo
+   int x;
+   foo () {
+     x = count++;
+-    printf("this %d = %x\n", x, (void *)this);
++    printf("this %d = %p\n", x, (void *)this);
+   }
+   virtual ~foo () {
+-    printf("this %d = %x\n", x, (void *)this);
++    printf("this %d = %p\n", x, (void *)this);
+     --count;
+   }
+ };
+@@ -31,7 +31,7 @@ int main ()
+       {
+ 	for (int j = 0; j < 3; j++)
+ 	  {
+-	    printf("&a[%d][%d] = %x\n", i, j, (void *)&array[i][j]);
++	    printf("&a[%d][%d] = %p\n", i, j, (void *)&array[i][j]);
+ 	  }
+       }
+       // The count should be nine, if not, fail the test.
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/pmf2.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/pmf2.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/pmf2.C
+@@ -42,7 +42,7 @@ B_table b;
+ bar jar;
+ 
+ int main() {
+-  printf("ptr to B_table=%x, ptr to A_table=%x\n",&b,(A_table*)&b);
++  printf("ptr to B_table=%p, ptr to A_table=%p\n",(void*)&b,(void*)(A_table*)&b);
+   B_table::B_ti_fn z = &B_table::func1;
+   int j = 1;
+   jar.call_fn_fn1(j,(void *)&z);
+Index: b/src/gcc/testsuite/g++.old-deja/g++.mike/temp.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.mike/temp.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.mike/temp.C
+@@ -7,11 +7,11 @@ class T {
+ public:
+   T() {
+     i = 1;
+-    printf("T() at %x\n", this);
++    printf("T() at %p\n", (void*)this);
+   }
+   T(const T& o) {
+     i = o.i;
+-    printf("T(const T&) at %x <-- %x\n", this, &o);
++    printf("T(const T&) at %p <-- %p\n", (void*)this, (void*)&o);
+   }
+   T operator +(const T& o) {
+     T r;
+@@ -21,7 +21,7 @@ public:
+   operator int () {
+     return i;
+   }
+-  ~T() { printf("~T() at %x\n", this); }
++  ~T() { printf("~T() at %p\n", (void*)this); }
+ } s, b;
+ 
+ int foo() { return getenv("TEST") == 0; }
+Index: b/src/gcc/testsuite/g++.old-deja/g++.other/temporary1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.other/temporary1.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.other/temporary1.C
+@@ -5,16 +5,16 @@ int c, d;
+ class Foo 
+ {
+ public:
+-   Foo() { printf("Foo() 0x%08lx\n", (__SIZE_TYPE__)this); ++c; }
+-   Foo(Foo const &) { printf("Foo(Foo const &) 0x%08lx\n", (__SIZE_TYPE__)this); }
+-   ~Foo() { printf("~Foo() 0x%08lx\n", (__SIZE_TYPE__)this); ++d; }
++   Foo() { printf("Foo() %p\n", (void*)this); ++c; }
++   Foo(Foo const &) { printf("Foo(Foo const &) %p\n", (void*)this); }
++   ~Foo() { printf("~Foo() %p\n", (void*)this); ++d; }
+ };
+ 
+ // Bar creates constructs a temporary Foo() as a default
+ class Bar 
+ {
+ public:
+-   Bar(Foo const & = Foo()) { printf("Bar(Foo const &) 0x%08lx\n", (__SIZE_TYPE__)this); }
++   Bar(Foo const & = Foo()) { printf("Bar(Foo const &) %p\n", (void*)this); }
+ };
+ 
+ void fakeRef(Bar *)
+Index: b/src/gcc/testsuite/g++.old-deja/g++.other/virtual8.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.other/virtual8.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.other/virtual8.C
+@@ -4,7 +4,7 @@ extern "C" int printf (const char*, ...)
+ struct A
+ {
+   virtual void f () {
+-    printf ("%x\n", this);
++    printf ("%p\n", (void*)this);
+   }
+ };
+ 
+Index: b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp23.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp23.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp23.C
+@@ -13,7 +13,7 @@ struct S
+ 
+   template <class U>
+   void f(U u)
+-  { printf ("In S::f(U)\nsizeof(U) == %d\n", sizeof(u)); }
++  { printf ("In S::f(U)\nsizeof(U) == %d\n", (int)sizeof(u)); }
+ 
+   int c[16];
+ };
+Index: b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp24.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp24.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp24.C
+@@ -13,7 +13,7 @@ struct S
+ 
+   template <class U>
+   void f(U u)
+-  { printf ("In S::f(U)\nsizeof(U) == %d\n", sizeof(u)); }
++  { printf ("In S::f(U)\nsizeof(U) == %d\n", (int)sizeof(u)); }
+ 
+   int c[16];
+ };
+Index: b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp25.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp25.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp25.C
+@@ -6,7 +6,7 @@ template <class X>
+ struct S
+ {
+   template <class U>
+-  void f(U u) { printf ("%d\n", sizeof (U)); }
++  void f(U u) { printf ("%d\n", (int)sizeof (U)); }
+ 
+   int i[4];
+ };
+Index: b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp26.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp26.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/memtemp26.C
+@@ -16,7 +16,7 @@ template <class X>
+ template <class U>
+ void S<X>::f(U u)
+ {
+-  printf ("%d\n", sizeof (U));
++  printf ("%d\n", (int)sizeof (U));
+ }
+ 
+ 
+Index: b/src/gcc/testsuite/g++.old-deja/g++.pt/t39.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.pt/t39.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.pt/t39.C
+@@ -10,9 +10,9 @@ struct frob {
+ 
+ template <class T>
+ void frob<T>::print () {
+-  printf ("this = %08x\n", this);
+-  printf (" ptr = %08x\n", ptr);
+-  printf (" values = %x %x %x ...\n", ptr[0], ptr[1], ptr[2]);
++  printf ("this = %p\n", (void*)this);
++  printf (" ptr = %p\n", (void*)ptr);
++  printf (" values = %x %x %x ...\n", (int)ptr[0], (int)ptr[1], (int)ptr[2]);
+ }
+ 
+   static int x[10];
+Index: b/src/gcc/testsuite/g++.old-deja/g++.robertl/eb17.C
+===================================================================
+--- a/src/gcc/testsuite/g++.old-deja/g++.robertl/eb17.C
++++ b/src/gcc/testsuite/g++.old-deja/g++.robertl/eb17.C
+@@ -44,15 +44,15 @@ int main()
+     A * a = new B;
+     B * b = dynamic_cast<B *>(a);
+ 
+-    printf("%p\n",b);                // (*2*)
++    printf("%p\n",(void*)b);                // (*2*)
+     b->print();
+ 
+     a = b;
+-    printf("%p\n",a);
++    printf("%p\n",(void*)a);
+     a->print();
+ 
+     a = a->clone();
+-    printf("%p\n",a);
++    printf("%p\n",(void*)a);
+     a->print();                      // (*1*)
+ 
+     return 0;
+Index: b/src/gcc/testsuite/gcc.dg/pch/inline-4.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pch/inline-4.c
++++ b/src/gcc/testsuite/gcc.dg/pch/inline-4.c
+@@ -1,6 +1,6 @@
+ #include "inline-4.h"
+ extern int printf (const char *, ...);
+ int main(void) {
+-  printf (getstring());
++  printf ("%s", getstring());
+   return 0;
+ }
--- gcc-6-6.4.0.orig/debian/patches/testsuite-hardening-updates.diff
+++ gcc-6-6.4.0/debian/patches/testsuite-hardening-updates.diff
@@ -0,0 +1,143 @@
+# DP: Fix some gcc and g++ testcases to pass with hardening defaults
+
+---
+ src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c     |    2 +-
+ src/gcc/testsuite/c-c++-common/cilk-plus/CK/spawnee_inline.c |    2 +-
+ src/gcc/testsuite/g++.dg/asan/asan_test.C                    |    2 +-
+ src/gcc/testsuite/g++.dg/asan/interception-malloc-test-1.C   |    2 +-
+ src/gcc/testsuite/g++.dg/fstack-protector-strong.C           |    2 +-
+ src/gcc/testsuite/gcc.c-torture/execute/memset-1.c           |    1 -
+ src/gcc/testsuite/gcc.c-torture/execute/memset-1.x           |    5 +++++
+ src/gcc/testsuite/gcc.dg/fstack-protector-strong.c           |    2 +-
+ src/gcc/testsuite/gcc.dg/stack-usage-1.c                     |    2 +-
+ src/gcc/testsuite/gcc.dg/superblock.c                        |    2 +-
+ src/gcc/testsuite/gcc.target/i386/sw-1.c                     |    2 +-
+ 11 files changed, 14 insertions(+), 10 deletions(-)
+
+Index: b/src/gcc/testsuite/g++.dg/asan/asan_test.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/asan/asan_test.C
++++ b/src/gcc/testsuite/g++.dg/asan/asan_test.C
+@@ -2,7 +2,7 @@
+ // { dg-skip-if "" { *-*-* } { "*" } { "-O2" } }
+ // { dg-skip-if "" { *-*-* } { "-flto" } { "" } }
+ // { dg-additional-sources "asan_globals_test-wrapper.cc" }
+-// { dg-options "-std=c++11 -fsanitize=address -fno-builtin -Wall -Wno-format -Werror -g -DASAN_UAR=0 -DASAN_HAS_EXCEPTIONS=1 -DASAN_HAS_BLACKLIST=0 -DSANITIZER_USE_DEJAGNU_GTEST=1 -lasan -lpthread -ldl" }
++// { dg-options "-std=c++11 -fsanitize=address -fno-builtin -Wall -Wno-format -Wno-unused-result -Werror -g -DASAN_UAR=0 -DASAN_HAS_EXCEPTIONS=1 -DASAN_HAS_BLACKLIST=0 -DSANITIZER_USE_DEJAGNU_GTEST=1 -lasan -lpthread -ldl" }
+ // { dg-additional-options "-DASAN_NEEDS_SEGV=1" { target { ! arm*-*-* } } }
+ // { dg-additional-options "-DASAN_LOW_MEMORY=1 -DASAN_NEEDS_SEGV=0" { target arm*-*-* } }
+ // { dg-additional-options "-DASAN_AVOID_EXPENSIVE_TESTS=1" { target { ! run_expensive_tests } } }
+Index: b/src/gcc/testsuite/g++.dg/asan/interception-malloc-test-1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/asan/interception-malloc-test-1.C
++++ b/src/gcc/testsuite/g++.dg/asan/interception-malloc-test-1.C
+@@ -1,7 +1,7 @@
+ // ASan interceptor can be accessed with __interceptor_ prefix.
+ 
+ // { dg-do run { target *-*-linux* } }
+-// { dg-options "-fno-builtin-free" }
++// { dg-options "-fno-builtin-free -Wno-unused-result" }
+ // { dg-additional-options "-D__NO_INLINE__" { target { *-*-linux-gnu } } }
+ // { dg-shouldfail "asan" }
+ 
+Index: b/src/gcc/testsuite/gcc.c-torture/execute/memset-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/memset-1.c
++++ b/src/gcc/testsuite/gcc.c-torture/execute/memset-1.c
+@@ -1,3 +1,5 @@
++/* { dg-prune-output ".*warning: memset used with constant zero length parameter.*" } */
++
+ /* Copyright (C) 2002  Free Software Foundation.
+ 
+    Test memset with various combinations of pointer alignments and lengths to
+Index: b/src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c
++++ b/src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run } */
+-/* { dg-options "-fno-builtin-malloc -fno-builtin-strncpy" } */
++/* { dg-options "-fno-builtin-malloc -fno-builtin-strncpy -U_FORTIFY_SOURCE" } */
+ /* { dg-shouldfail "asan" } */
+ 
+ #include <string.h>
+Index: b/src/gcc/testsuite/gcc.dg/superblock.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/superblock.c
++++ b/src/gcc/testsuite/gcc.dg/superblock.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fno-asynchronous-unwind-tables -fsched2-use-superblocks -fdump-rtl-sched2 -fdump-rtl-bbro" } */
++/* { dg-options "-O2 -fno-asynchronous-unwind-tables -fsched2-use-superblocks -fdump-rtl-sched2 -fdump-rtl-bbro -fno-stack-protector" } */
+ /* { dg-require-effective-target scheduling } */
+ 
+ typedef int aligned __attribute__ ((aligned (64)));
+Index: b/src/gcc/testsuite/gcc.dg/stack-usage-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/stack-usage-1.c
++++ b/src/gcc/testsuite/gcc.dg/stack-usage-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-fstack-usage" } */
++/* { dg-options "-fstack-usage -fno-stack-protector" } */
+ /* nvptx doesn't have a reg allocator, and hence no stack usage data.  */
+ /* { dg-skip-if "" { nvptx-*-* } { "*" } { "" } } */
+ 
+Index: b/src/gcc/testsuite/gcc.target/i386/sw-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/sw-1.c
++++ b/src/gcc/testsuite/gcc.target/i386/sw-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -mtune=generic -fshrink-wrap -fdump-rtl-pro_and_epilogue" } */
++/* { dg-options "-O2 -mtune=generic -fshrink-wrap -fdump-rtl-pro_and_epilogue -fno-stack-protector" } */
+ /* { dg-skip-if "No shrink-wrapping preformed" { x86_64-*-mingw* } { "*" } { "" } } */
+ 
+ #include <string.h>
+Index: b/src/gcc/testsuite/c-c++-common/cilk-plus/CK/spawnee_inline.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/cilk-plus/CK/spawnee_inline.c
++++ b/src/gcc/testsuite/c-c++-common/cilk-plus/CK/spawnee_inline.c
+@@ -1,5 +1,5 @@
+ /* { dg-do run  { target { i?86-*-* x86_64-*-* } } } */
+-/* { dg-options "-fcilkplus -w" } */
++/* { dg-options "-fcilkplus -w -U_FORTIFY_SOURCE" } */
+ /* { dg-additional-options "-lcilkrts" { target { i?86-*-* x86_64-*-* } } } */
+ 
+ #include <stdio.h>
+Index: b/src/gcc/testsuite/gcc.dg/fstack-protector-strong.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/fstack-protector-strong.c
++++ b/src/gcc/testsuite/gcc.dg/fstack-protector-strong.c
+@@ -1,7 +1,7 @@
+ /* Test that stack protection is done on chosen functions. */
+ 
+ /* { dg-do compile { target i?86-*-* x86_64-*-* rs6000-*-* s390x-*-* } } */
+-/* { dg-options "-O2 -fstack-protector-strong" } */
++/* { dg-options "-O2 -fstack-protector-strong -U_FORTIFY_SOURCE" } */
+ 
+ /* This test checks the presence of __stack_chk_fail function in assembler.
+  * Compiler generates _stack_chk_fail_local (wrapper) calls instead for PIC.
+Index: b/src/gcc/testsuite/g++.dg/fstack-protector-strong.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/fstack-protector-strong.C
++++ b/src/gcc/testsuite/g++.dg/fstack-protector-strong.C
+@@ -1,7 +1,7 @@
+ /* Test that stack protection is done on chosen functions. */
+ 
+ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+-/* { dg-options "-O2 -fstack-protector-strong" } */
++/* { dg-options "-O2 -fstack-protector-strong -U_FORTIFY_SOURCE" } */
+ 
+ /* This test checks the presence of __stack_chk_fail function in assembler.
+  * Compiler generates _stack_chk_fail_local (wrapper) calls instead for PIC.
+Index: b/src/gcc/testsuite/gcc.c-torture/execute/memset-1.x
+===================================================================
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/execute/memset-1.x
+@@ -0,0 +1,5 @@
++# Implement "/* { dg-options "-U_FORITFY_SOURCE" } */", due to
++# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=20567
++
++set additional_flags "-U_FORTIFY_SOURCE"
++return 0
--- gcc-6-6.4.0.orig/debian/patches/vulcan-costs.diff
+++ gcc-6-6.4.0/debian/patches/vulcan-costs.diff
@@ -0,0 +1,259 @@
+# DP: Add cost model for vulcan CPU
+
+From: jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Fri, 15 Jul 2016 11:17:53 +0000
+Subject: [PATCH] [PATCH/AARCH64] Add rtx_costs routine for vulcan.
+
+gcc/ChangeLog:
+
+2016-07-15  Virendra Pathak  <virendra.pathak@broadcom.com>
+	    Julian Brown  <julian@codesourcery.com>
+
+	* config/aarch64/aarch64-cores.def: Update vulcan COSTS.
+	* config/aarch64/aarch64-cost-tables.h
+	(vulcan_extra_costs): New variable.
+	* config/aarch64/aarch64.c
+	(vulcan_addrcost_table): Likewise.
+	(vulcan_regmove_cost): Likewise.
+	(vulcan_vector_cost): Likewise.
+	(vulcan_branch_cost): Likewise.
+	(vulcan_tunings): Likewise.
+
+[dannf: backported by removing approx_modes function pointer]
+
+diff -urpN a/src/gcc/config/aarch64/aarch64.c b/src/gcc/config/aarch64/aarch64.c
+--- a/src/gcc/config/aarch64/aarch64.c	2016-07-15 16:14:24.268328586 +0000
++++ b/src/gcc/config/aarch64/aarch64.c	2016-07-15 16:15:52.603299822 +0000
+@@ -250,6 +250,22 @@ static const struct cpu_addrcost_table x
+   0, /* imm_offset  */
+ };
+ 
++static const struct cpu_addrcost_table vulcan_addrcost_table =
++{
++    {
++      0, /* hi  */
++      0, /* si  */
++      0, /* di  */
++      2, /* ti  */
++    },
++  0, /* pre_modify  */
++  0, /* post_modify  */
++  2, /* register_offset  */
++  3, /* register_sextend  */
++  3, /* register_zextend  */
++  0, /* imm_offset  */
++};
++
+ static const struct cpu_regmove_cost generic_regmove_cost =
+ {
+   1, /* GP2GP  */
+@@ -308,6 +324,15 @@ static const struct cpu_regmove_cost xge
+   2 /* FP2FP  */
+ };
+ 
++static const struct cpu_regmove_cost vulcan_regmove_cost =
++{
++  1, /* GP2GP  */
++  /* Avoid the use of int<->fp moves for spilling.  */
++  8, /* GP2FP  */
++  8, /* FP2GP  */
++  4  /* FP2FP  */
++};
++
+ /* Generic costs for vector insn classes.  */
+ static const struct cpu_vector_cost generic_vector_cost =
+ {
+@@ -379,6 +404,24 @@ static const struct cpu_vector_cost xgen
+   1 /* cond_not_taken_branch_cost  */
+ };
+ 
++/* Costs for vector insn classes for Vulcan.  */
++static const struct cpu_vector_cost vulcan_vector_cost =
++{
++  6, /* scalar_stmt_cost  */
++  4, /* scalar_load_cost  */
++  1, /* scalar_store_cost  */
++  6, /* vec_stmt_cost  */
++  3, /* vec_permute_cost  */
++  6, /* vec_to_scalar_cost  */
++  5, /* scalar_to_vec_cost  */
++  8, /* vec_align_load_cost  */
++  8, /* vec_unalign_load_cost  */
++  4, /* vec_unalign_store_cost  */
++  4, /* vec_store_cost  */
++  2, /* cond_taken_branch_cost  */
++  1  /* cond_not_taken_branch_cost  */
++};
++
+ /* Generic costs for branch instructions.  */
+ static const struct cpu_branch_cost generic_branch_cost =
+ {
+@@ -393,6 +436,13 @@ static const struct cpu_branch_cost cort
+   3   /* Unpredictable.  */
+ };
+ 
++/* Branch costs for Vulcan.  */
++static const struct cpu_branch_cost vulcan_branch_cost =
++{
++  1,  /* Predictable.  */
++  3   /* Unpredictable.  */
++};
++
+ static const struct tune_params generic_tunings =
+ {
+   &cortexa57_extra_costs,
+@@ -589,6 +639,30 @@ static const struct tune_params xgene1_t
+   (AARCH64_EXTRA_TUNE_APPROX_RSQRT)	/* tune_flags.  */
+ };
+ 
++static const struct tune_params vulcan_tunings =
++{
++  &vulcan_extra_costs,
++  &vulcan_addrcost_table,
++  &vulcan_regmove_cost,
++  &vulcan_vector_cost,
++  &vulcan_branch_cost,
++  4, /* memmov_cost.  */
++  4, /* issue_rate.  */
++  AARCH64_FUSE_NOTHING, /* fuseable_ops.  */
++  16,	/* function_align.  */
++  8,	/* jump_align.  */
++  16,	/* loop_align.  */
++  3,	/* int_reassoc_width.  */
++  2,	/* fp_reassoc_width.  */
++  2,	/* vec_reassoc_width.  */
++  2,	/* min_div_recip_mul_sf.  */
++  2,	/* min_div_recip_mul_df.  */
++  0,	/* max_case_values.  */
++  0,	/* cache_line_size.  */
++  tune_params::AUTOPREFETCHER_OFF,	/* autoprefetcher_model.  */
++  (AARCH64_EXTRA_TUNE_NONE)	/* tune_flags.  */
++};
++
+ /* Support for fine-grained override of the tuning structures.  */
+ struct aarch64_tuning_override_function
+ {
+diff -urpN a/src/gcc/config/aarch64/aarch64-cores.def b/src/gcc/config/aarch64/aarch64-cores.def
+--- a/src/gcc/config/aarch64/aarch64-cores.def	2016-07-15 16:14:24.272328721 +0000
++++ b/src/gcc/config/aarch64/aarch64-cores.def	2016-07-15 16:15:26.730430056 +0000
+@@ -51,7 +51,7 @@ AARCH64_CORE("xgene1",      xgene1,    x
+ 
+ /* V8.1 Architecture Processors.  */
+ 
+-AARCH64_CORE("vulcan",  vulcan, cortexa57, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, cortexa57, "0x42", "0x516")
++AARCH64_CORE("vulcan",  vulcan, cortexa57, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, vulcan, "0x42", "0x516")
+ 
+ /* V8 big.LITTLE implementations.  */
+ 
+diff -urpN a/src/gcc/config/aarch64/aarch64-cost-tables.h b/src/gcc/config/aarch64/aarch64-cost-tables.h
+--- a/src/gcc/config/aarch64/aarch64-cost-tables.h	2016-07-15 16:14:24.272328721 +0000
++++ b/src/gcc/config/aarch64/aarch64-cost-tables.h	2016-07-15 16:15:26.730430056 +0000
+@@ -127,6 +127,108 @@ const struct cpu_cost_table thunderx_ext
+   }
+ };
+ 
++const struct cpu_cost_table vulcan_extra_costs =
++{
++  /* ALU */
++  {
++    0,			/* Arith.  */
++    0,			/* Logical.  */
++    0,			/* Shift.  */
++    0,			/* Shift_reg.  */
++    COSTS_N_INSNS (1),	/* Arith_shift.  */
++    COSTS_N_INSNS (1),	/* Arith_shift_reg.  */
++    COSTS_N_INSNS (1),	/* Log_shift.  */
++    COSTS_N_INSNS (1),	/* Log_shift_reg.  */
++    0,			/* Extend.  */
++    COSTS_N_INSNS (1),	/* Extend_arith.  */
++    0,			/* Bfi.  */
++    0,			/* Bfx.  */
++    COSTS_N_INSNS (3),	/* Clz.  */
++    0,			/* Rev.  */
++    0,			/* Non_exec.  */
++    true		/* Non_exec_costs_exec.  */
++  },
++  {
++    /* MULT SImode */
++    {
++      COSTS_N_INSNS (4),	/* Simple.  */
++      COSTS_N_INSNS (4),	/* Flag_setting.  */
++      COSTS_N_INSNS (4),	/* Extend.  */
++      COSTS_N_INSNS (5),	/* Add.  */
++      COSTS_N_INSNS (5),	/* Extend_add.  */
++      COSTS_N_INSNS (18)	/* Idiv.  */
++    },
++    /* MULT DImode */
++    {
++      COSTS_N_INSNS (4),       /* Simple.  */
++      0,                       /* Flag_setting.  */
++      COSTS_N_INSNS (4),       /* Extend.  */
++      COSTS_N_INSNS (5),       /* Add.  */
++      COSTS_N_INSNS (5),       /* Extend_add.  */
++      COSTS_N_INSNS (26)       /* Idiv.  */
++    }
++  },
++  /* LD/ST */
++  {
++    COSTS_N_INSNS (4),	/* Load.  */
++    COSTS_N_INSNS (4),	/* Load_sign_extend.  */
++    COSTS_N_INSNS (5),	/* Ldrd.  */
++    COSTS_N_INSNS (4),	/* Ldm_1st.  */
++    1,			/* Ldm_regs_per_insn_1st.  */
++    1,			/* Ldm_regs_per_insn_subsequent.  */
++    COSTS_N_INSNS (4),	/* Loadf.  */
++    COSTS_N_INSNS (4),	/* Loadd.  */
++    COSTS_N_INSNS (4),	/* Load_unaligned.  */
++    0,			/* Store.  */
++    0,			/* Strd.  */
++    0,			/* Stm_1st.  */
++    1,			/* Stm_regs_per_insn_1st.  */
++    1,			/* Stm_regs_per_insn_subsequent.  */
++    0,			/* Storef.  */
++    0,			/* Stored.  */
++    0,			/* Store_unaligned.  */
++    COSTS_N_INSNS (1),	/* Loadv.  */
++    COSTS_N_INSNS (1)	/* Storev.  */
++  },
++  {
++    /* FP SFmode */
++    {
++      COSTS_N_INSNS (4),	/* Div.  */
++      COSTS_N_INSNS (1),	/* Mult.  */
++      COSTS_N_INSNS (1),	/* Mult_addsub. */
++      COSTS_N_INSNS (1),	/* Fma.  */
++      COSTS_N_INSNS (1),	/* Addsub.  */
++      COSTS_N_INSNS (1),	/* Fpconst. */
++      COSTS_N_INSNS (1),	/* Neg.  */
++      COSTS_N_INSNS (1),	/* Compare.  */
++      COSTS_N_INSNS (2),	/* Widen.  */
++      COSTS_N_INSNS (2),	/* Narrow.  */
++      COSTS_N_INSNS (2),	/* Toint.  */
++      COSTS_N_INSNS (2),	/* Fromint.  */
++      COSTS_N_INSNS (2) 	/* Roundint.  */
++    },
++    /* FP DFmode */
++    {
++      COSTS_N_INSNS (6),	/* Div.  */
++      COSTS_N_INSNS (1),	/* Mult.  */
++      COSTS_N_INSNS (1),	/* Mult_addsub.  */
++      COSTS_N_INSNS (1),	/* Fma.  */
++      COSTS_N_INSNS (1),	/* Addsub.  */
++      COSTS_N_INSNS (1),	/* Fpconst.  */
++      COSTS_N_INSNS (1),	/* Neg.  */
++      COSTS_N_INSNS (1),	/* Compare.  */
++      COSTS_N_INSNS (2),	/* Widen.  */
++      COSTS_N_INSNS (2),	/* Narrow.  */
++      COSTS_N_INSNS (2),	/* Toint.  */
++      COSTS_N_INSNS (2),	/* Fromint.  */
++      COSTS_N_INSNS (2) 	/* Roundint.  */
++    }
++  },
++  /* Vector */
++  {
++    COSTS_N_INSNS (1)	/* Alu.  */
++  }
++};
+ 
+ 
+ #endif
--- gcc-6-6.4.0.orig/debian/patches/vulcan-cpu-doc.diff
+++ gcc-6-6.4.0/debian/patches/vulcan-cpu-doc.diff
@@ -0,0 +1,27 @@
+# DP: Accept vulcan as a cpu name for the AArch64 port of GCC (documentation)
+
+From: jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Tue, 21 Jun 2016 13:43:29 +0000 (+0000)
+Subject: [PATCH/AARCH64] Accept vulcan as a cpu name for the AArch64 port of GCC
+X-Git-Url: https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff_plain;h=2c6ac78145ac8ff2fd83271d093e23ab80a15e4f
+
+[PATCH/AARCH64] Accept vulcan as a cpu name for the AArch64 port of GCC
+
+gcc/ChangeLog
+
+	* config/aarch64/aarch64-cores.def (vulcan): New core.
+	* config/aarch64/aarch64-tune.md: Regenerate.
+	* doc/invoke.texi: Document vulcan as an available option.
+
+diff -urpN a/src/gcc/doc/invoke.texi b/src/gcc/doc/invoke.texi
+--- a/src/gcc/doc/invoke.texi	2016-06-21 10:31:29.994143994 -0600
++++ b/src/gcc/doc/invoke.texi	2016-06-21 10:35:51.136081208 -0600
+@@ -12988,7 +12988,7 @@ Specify the name of the target processor
+ performance of the code.  Permissible values for this option are:
+ @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
+ @samp{cortex-a72}, @samp{exynos-m1}, @samp{qdf24xx}, @samp{thunderx},
+-@samp{xgene1}.
++@samp{vulcan}, @samp{xgene1}.
+ 
+ Additionally, this option can specify that GCC should tune the performance
+ of the code for a big.LITTLE system.  Permissible values for this
--- gcc-6-6.4.0.orig/debian/patches/vulcan-cpu.diff
+++ gcc-6-6.4.0/debian/patches/vulcan-cpu.diff
@@ -0,0 +1,39 @@
+# DP: Accept vulcan as a cpu name for the AArch64 port of GCC
+
+From: jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Tue, 21 Jun 2016 13:43:29 +0000 (+0000)
+Subject: [PATCH/AARCH64] Accept vulcan as a cpu name for the AArch64 port of GCC
+X-Git-Url: https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff_plain;h=2c6ac78145ac8ff2fd83271d093e23ab80a15e4f
+
+[PATCH/AARCH64] Accept vulcan as a cpu name for the AArch64 port of GCC
+
+gcc/ChangeLog
+
+	* config/aarch64/aarch64-cores.def (vulcan): New core.
+	* config/aarch64/aarch64-tune.md: Regenerate.
+	* doc/invoke.texi: Document vulcan as an available option.
+
+diff -urpN a/src/gcc/config/aarch64/aarch64-cores.def b/src/gcc/config/aarch64/aarch64-cores.def
+--- a/src/gcc/config/aarch64/aarch64-cores.def	2016-01-04 07:30:50.000000000 -0700
++++ b/src/gcc/config/aarch64/aarch64-cores.def	2016-06-21 10:32:59.191974071 -0600
+@@ -49,6 +49,10 @@ AARCH64_CORE("qdf24xx",     qdf24xx,   c
+ AARCH64_CORE("thunderx",    thunderx,  thunderx,  8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx,  "0x43", "0x0a1")
+ AARCH64_CORE("xgene1",      xgene1,    xgene1,    8A,  AARCH64_FL_FOR_ARCH8, xgene1, "0x50", "0x000")
+ 
++/* V8.1 Architecture Processors.  */
++
++AARCH64_CORE("vulcan",  vulcan, cortexa57, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, cortexa57, "0x42", "0x516")
++
+ /* V8 big.LITTLE implementations.  */
+ 
+ AARCH64_CORE("cortex-a57.cortex-a53",  cortexa57cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07.0xd03")
+diff -urpN a/src/gcc/config/aarch64/aarch64-tune.md b/src/gcc/config/aarch64/aarch64-tune.md
+--- a/src/gcc/config/aarch64/aarch64-tune.md	2016-04-27 02:22:11.000000000 -0600
++++ b/src/gcc/config/aarch64/aarch64-tune.md	2016-06-21 10:32:59.191974071 -0600
+@@ -1,5 +1,5 @@
+ ;; -*- buffer-read-only: t -*-
+ ;; Generated automatically by gentune.sh from aarch64-cores.def
+ (define_attr "tune"
+-	"cortexa35,cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
++	"cortexa35,cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,thunderx,xgene1,vulcan,cortexa57cortexa53,cortexa72cortexa53"
+ 	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
--- gcc-6-6.4.0.orig/debian/porting.html
+++ gcc-6-6.4.0/debian/porting.html
@@ -0,0 +1,30 @@
+<html lang="en">
+<head>
+<title>Porting libstdc++-v3</title>
+<meta http-equiv="Content-Type" content="text/html">
+<meta name="description" content="Porting libstdc++-v3">
+<meta name="generator" content="makeinfo 4.6">
+<meta http-equiv="Content-Style-Type" content="text/css">
+<style type="text/css"><!--
+  pre.display { font-family:inherit }
+  pre.format  { font-family:inherit }
+  pre.smalldisplay { font-family:inherit; font-size:smaller }
+  pre.smallformat  { font-family:inherit; font-size:smaller }
+  pre.smallexample { font-size:smaller }
+  pre.smalllisp    { font-size:smaller }
+--></style>
+</head>
+<body>
+<h1 class="settitle">Porting libstdc++-v3</h1>
+<div class="node">
+<p><hr>
+Node:&nbsp;<a name="Top">Top</a>,
+Next:&nbsp;<a rel="next" accesskey="n" href="#Operating%20system">Operating system</a>,
+Up:&nbsp;<a rel="up" accesskey="u" href="#dir">(dir)</a>
+<br>
+</div>
+
+The documentation in this file was removed, because it is licencensed
+under a non DFSG conforming licencse.
+
+</body></html>
--- gcc-6-6.4.0.orig/debian/reduce-test-diff.awk
+++ gcc-6-6.4.0/debian/reduce-test-diff.awk
@@ -0,0 +1,33 @@
+#! /usr/bin/gawk -f
+
+BEGIN {
+	skip=0
+	warn=0
+}
+
+/^-(FAIL|ERROR|UNRESOLVED|WARNING)/ {
+	next
+}
+
+# only compare gcc, g++, g77 and objc results
+/=== treelang tests ===/ {
+	skip=1
+}
+
+# omit extra files appended to test-summary
+/^\+Compiler version/ {
+	skip=1
+}
+
+skip == 0 {
+	print
+	next
+}
+
+/^\+(FAIL|ERROR|UNRESOLVED|WARNING)/ {
+	warn=1
+}
+
+END {
+	exit warn
+}
--- gcc-6-6.4.0.orig/debian/relink
+++ gcc-6-6.4.0/debian/relink
@@ -0,0 +1,74 @@
+#! /bin/sh
+#
+# Relink GNAT utilities using the shared library
+#
+
+set -e
+
+pwd=`pwd`
+
+# why?
+chmod a-w build/gcc/ada/rts/*.ali
+
+rm -rf tmp
+ln -s $pwd/build/gcc/ada/rts/libgnat.so.1 tmp/libgnat.so
+
+LD_LIBRARY_PATH=$pwd/tmp
+export LD_LIBRARY_PATH
+
+PATH=$pwd/debian:$pwd/tmp:$PATH
+export PATH
+
+echo "#! /bin/sh" > tmp/dgcc
+echo "$pwd/build/gcc/xgcc -B$pwd/build/gcc/ "'"$@"' >> tmp/dgcc
+chmod 755 tmp/dgcc
+
+echo "#! /bin/sh" > tmp/dgnatlink
+echo "$pwd/build/gcc/gnatlink --GCC=dgcc "'"$@"' >> tmp/dgnatlink
+chmod 755 tmp/dgnatlink
+
+GMCMD="$pwd/build/gcc/gnatmake -I- -Irts -I. -a -m --GNATBIND=$pwd/build/gcc/gnatbind --GNATLINK=dgnatlink --GCC=dgcc"
+
+#cd $pwd/build/gcc/ada
+#make CFLAGS="-O2" CC="../xgcc -B../" STAGE_PREFIX=../ a-link.o a-gmem.o
+#cd $pwd
+
+[ -f build/gcc/gnatmake.old ] || cp -p build/gcc/gnatmake build/gcc/gnatmake.old
+[ -f build/gcc/gnatlink.old ] || cp -p build/gcc/gnatlink build/gcc/gnatlink.old
+
+make -C build/gcc/ada \
+	CFLAGS='-gnatp -gnata -O2 ' \
+	ADA_INCLUDES="-I." \
+	CC="../xgcc -B../" \
+	STAGE_PREFIX=../ \
+    ../gnatmake ../gnatlink
+
+mv gnatmake bgnatmake
+mv gnatlink bgnatlink
+exit 0
+
+cd build/gcc/ada
+for i in ../gnatchop ../gnatcmd \
+    ../gnatkr ../gnatlbr \
+    ../gnatls ../gnatmake \
+    ../gnatprep ../gnatpsys \
+    ../gnatxref ../gnatfind
+do
+  rm -f $i
+  $GMCMD -O2 -gnatp -o $i `basename $i`.adb -largs -L..
+done
+
+rm -f ../gnatmem
+$GMCMD -O2 -gnatp -o ../gnatmem gnatmem.adb -largs -L.. a-gmem.o
+$GMCMD -O2 -gnatp -o ../gnatlink gnatlink -largs -L.. a-link.o
+rm -f ../gnatpsta
+
+make CFLAGS="-O2" CC="../xgcc -B../" a-gettty.o a-deftar.o
+$GMCMD -O2 -gnatp -o ../gnatpsta gnatpsta -largs -L.. a-gettty.o a-deftar.o
+rm -f ../gnatbl
+
+make CFLAGS="-O2" CC="../xgcc -B../" gnatbl.o
+../xgcc -B../ -o ../gnatbl gnatbl.o -L.. -lgnat
+rm -f ../bgnatmake ../bgnatlink ../debian/dgcc ../debian/dgnatlink
+
+chmod +w rts/*.ali
--- gcc-6-6.4.0.orig/debian/rules
+++ gcc-6-6.4.0/debian/rules
@@ -0,0 +1,83 @@
+#! /usr/bin/make -f
+# -*- makefile -*-
+# Build rules for gcc (>= 2.95) and gcc-snapshot
+# Targets found in this makefile:
+#	- unpack tarballs
+#	- patch sources
+#	- (re)create the control file
+#	- create a debian/rules.parameters file, which is included
+#	  by debian/rules2
+# All other targets are passed to the debian/rules2 file
+
+# Uncomment this to turn on verbose mode.
+#export DH_VERBOSE=1
+
+unexport LANG LC_ALL LC_CTYPE LC_COLLATE LC_TIME LC_NUMERIC LC_MESSAGES
+
+default: build
+
+include debian/rules.defs
+include debian/rules.unpack
+include debian/rules.patch
+
+control: $(control_dependencies)
+	-mkdir -p $(stampdir)
+	$(MAKE) -f debian/rules.conf $@
+
+configure: control $(unpack_stamp) $(patch_stamp)
+	$(MAKE) -f debian/rules2 $@
+
+pre-build:
+#ifneq (,$(filter $(distrelease),squeeze sid))
+#ifeq (,$(filter $(DEB_TARGET_ARCH),amd64 i386))
+#	@echo explicitely fail the build for $(DEB_TARGET_ARCH)
+#	@echo no bug report required. please ask the port maintainers if they support gcc-4.5.
+#	false
+#endif
+#endif
+
+build: pre-build control
+	$(MAKE) $(NJOBS) -f debian/rules2 $@
+build-arch: pre-build control
+	$(MAKE) $(NJOBS) -f debian/rules2 $@
+build-indep: pre-build control
+	$(MAKE) $(NJOBS) -f debian/rules2 $@
+
+check: $(check_stamp)
+$(check_stamp): $(build_stamp)
+	$(MAKE) -f debian/rules2 $@
+
+clean:
+	rm -rf $(stampdir)
+# remove temporary dirs used for unpacking
+	rm -rf $(gcc_srcdir) $(gdc_srcdir)
+	-$(MAKE) -f debian/rules2 $@
+	rm -rf $(srcdir)* $(builddir)* debian/tmp* html
+	rm -f bootstrap-* first-move-stamp
+	rm -f debian/*.tmp
+	rm -f debian/soname-cache
+	find debian -name '.#*' | xargs -r rm -f
+	rm -f $(series_file)*
+	dh_clean
+
+install:
+	$(MAKE) -f debian/rules2 $@
+
+html-docs doxygen-docs update-doxygen-docs update-ada-files xxx:
+	$(MAKE) -f debian/rules2 $@
+
+binary-indep binary-arch binary:
+	$(MAKE) -f debian/rules2 $@
+
+source diff:
+	@echo >&2 'source and diff are obsolete - use dpkg-source -b'; false
+
+release:
+	foo=$(shell basename $(CURDIR)); \
+		if [ "$$foo" != "gcc-3.4" ]; then \
+			find -name CVS -o -name .cvsignore -o -name '.#*' | \
+				xargs rm -rf; \
+		fi
+
+.NOTPARALLEL:
+.PHONY: build clean binary-indep binary-arch binary release
--- gcc-6-6.4.0.orig/debian/rules.conf
+++ gcc-6-6.4.0/debian/rules.conf
@@ -0,0 +1,1520 @@
+# -*- makefile -*-
+# rules.conf
+#	- used to build debian/control and debian/rules.parameters
+#	- assumes unpacked sources
+
+include debian/rules.defs
+include debian/rules.sonames
+
+# manual ...
+ifeq ($(DEB_TARGET_GNU_CPU), $(findstring $(DEB_TARGET_GNU_CPU),hppa m68k))
+  ifeq ($(DEB_TARGET_ARCH),m68k)
+    GCC_SONAME := 2
+  endif
+  ifeq ($(DEB_TARGET_ARCH),hppa)
+    GCC_SONAME := 4
+  endif
+else
+  GCC_SONAME := 1
+endif
+DEB_LIBGCC_SOVERSION := $(DEB_SOEVERSION)
+DEB_LIBGCC_VERSION := $(DEB_EVERSION)
+
+_soname_map = gcc=$(GCC_SONAME) stdc++=$(CXX_SONAME) gomp=$(GOMP_SONAME) \
+	ssp=$(SSP_SONAME) gfortran=$(FORTRAN_SONAME) \
+	itm=$(ITM_SONAME) objc=$(OBJC_SONAME) quadmath=$(QUADMATH_SONAME) \
+	go=$(GO_SONAME) backtrace=$(BTRACE_SONAME) \
+	atomic=$(ATOMIC_SONAME) asan=$(ASAN_SONAME) lsan=$(LSAN_SONAME) \
+	tsan=$(TSAN_SONAME) ubsan=$(UBSAN_SONAME) \
+	vtv=$(VTV_SONAME) cilkrts=$(CILKRTS_SONAME) mpx=$(MPX_SONAME) \
+	gphobos=$(GPHOBOS_SONAME)
+_soname = $(patsubst $(1)=%,%,$(filter $(1)=%,$(_soname_map)))
+
+rel_on_dev := $(if $(cross_lib_arch),>=,=)
+# $(call _lib_name,<name>,<biarch>,<ext>)
+_lib_name = $(subst $(SPACE),, \
+  lib$(2)$(1) \
+  $(if $(filter dev,$(3)),,$(call _soname,$(1))) \
+  $(if $(or $(filter $(3),dev),$(and $(filter $(3),dbg),$(filter $(1),stdc++))),-$(BASE_VERSION)) \
+  $(if $(3),-$(3))$(LS)$(AQ))
+# $(call _lib_vers,<ext>,<vers>) 
+_lib_vers = ($(if $(filter $(1),dev),$(rel_on_dev),>=) $(2))
+
+# Helper to generate biarch/triarch dependencies.
+# For example, $(eval $(call gen_multilib_deps,gomp)) will create the
+# libgompbiarch variable, and make it contains the libgompbiarch{32,64,n32}
+# variables if biarch{32,64,n32} is set to yes.
+
+define gen_multilib_deps
+  lib$1biarch64$2  := $(call _lib_name,$(1),64,$(2)) $(call _lib_vers,$(2),$(3))
+  lib$1biarch32$2  := $(call _lib_name,$(1),32,$(2)) $(call _lib_vers,$(2),$(3))
+  lib$1biarchn32$2 := $(call _lib_name,$(1),n32,$(2)) $(call _lib_vers,$(2),$(3))
+  lib$1biarchx32$2 := $(call _lib_name,$(1),x32,$(2)) $(call _lib_vers,$(2),$(3))
+  lib$1biarchhf$2  := $(call _lib_name,$(1),hf,$(2)) $(call _lib_vers,$(2),$(3))
+  lib$1biarchsf$2  := $(call _lib_name,$(1),sf,$(2)) $(call _lib_vers,$(2),$(3))
+  ifeq ($$(biarch64),yes)
+    lib$1biarch$2 := $$(lib$1biarch64$2)
+  endif
+  ifeq ($$(biarch32),yes)
+    ifeq ($$(biarch64),yes)
+      lib$1biarch$2 := $$(lib$1biarch64$2), $$(lib$1biarch32$2)
+    else
+      lib$1biarch$2 := $$(lib$1biarch32$2)
+    endif
+  endif
+  ifeq ($$(biarchx32),yes)
+    ifeq ($1,mpx)
+      ifeq ($$(biarch64),yes)
+        lib$1biarch$2 := $$(lib$1biarch64$2)
+      else ifeq ($$(biarch32),yes)
+        lib$1biarch$2 := $$(lib$1biarch32$2)
+      else
+        lib$1biarch$2 :=
+      endif
+    else ifeq ($$(biarch64),yes)
+      lib$1biarch$2 := $$(lib$1biarch64$2), $$(lib$1biarchx32$2)
+    else ifeq ($$(biarch32),yes)
+      lib$1biarch$2 := $$(lib$1biarch32$2), $$(lib$1biarchx32$2)
+    else
+      lib$1biarch$2 := $$(lib$1biarchx32$2)
+    endif
+  endif
+  ifeq ($$(biarchn32),yes)
+    ifeq ($$(biarch64),yes)
+      lib$1biarch$2 := $$(lib$1biarch64$2), $$(lib$1biarchn32$2)
+    else ifeq ($$(biarch32),yes)
+      lib$1biarch$2 := $$(lib$1biarch32$2), $$(lib$1biarchn32$2)
+    else
+      lib$1biarch$2 := $$(lib$1biarchn32$2)
+    endif
+  endif
+  ifeq ($$(biarchhf),yes)
+    lib$1biarch$2 := $$(lib$1biarchhf$2) | $(call _lib_name,$(1),hf,$(2))
+  endif
+  ifeq ($$(biarchsf),yes)
+    lib$1biarch$2 := $$(lib$1biarchsf$2) | $(call _lib_name,$(1),sf,$(2))
+  endif
+endef
+ifeq ($(with_shared_libgcc),yes)
+  LIBGCC_DEP := libgcc$(GCC_SONAME)$(LS)$(AQ) (>= $(DEB_LIBGCC_VERSION))
+  $(eval $(call gen_multilib_deps,gcc,,$(DEB_LIBGCC_VERSION)))
+endif
+LIBGCC_DEV_DEP := libgcc-$(BASE_VERSION)-dev$(LS)$(AQ) ($(rel_on_dev) $(DEB_VERSION))
+$(foreach x,stdc++ gomp ssp gfortran itm objc atomic asan lsan mpx ubsan quadmath go vtv cilkrts, \
+	$(eval $(call gen_multilib_deps,$(x),,$$$${gcc:Version})))
+$(foreach x,gcc stdc++ gfortran objc go gphobos, \
+	$(eval $(call gen_multilib_deps,$(x),dev,$$$${gcc:Version})))
+$(foreach x,gcc stdc++ gfortran objc go gphobos, \
+	$(eval $(call gen_multilib_deps,$(x),dbg,$$$${gcc:Version})))
+
+# Helper to generate _no_archs variables.
+# For example, $(eval $(call gen_no_archs,java)) will create the java_no_archs
+# variable, using the java_no_cpu and java_no_systems variables.
+define gen_no_archs
+  $1_no_archs :=
+  ifneq (,$$($1_no_cpus))
+    $1_no_archs += $$(foreach cpu,$$(filter-out i386 amd64 alpha arm,$$($1_no_cpus)),!$$(cpu))
+    ifneq (,$$(filter i386,$$($1_no_cpus)))
+      $1_no_archs += !i386 !hurd-i386 !kfreebsd-i386
+    endif
+    ifneq (,$$(filter amd64,$$($1_no_cpus)))
+      $1_no_archs += !amd64 !kfreebsd-amd64
+    endif
+    ifneq (,$$(filter alpha,$$($1_no_cpus)))
+      $1_no_archs += !alpha !hurd-alpha
+    endif
+    ifneq (,$$(filter arm,$$($1_no_cpus)))
+      $1_no_archs += !arm !armel !armhf
+    endif
+    ifneq (,$$(strip $3))
+      $1_no_systems_tmp := $$(subst $$(SPACE)gnu$$(SPACE),$$(SPACE)hurd-gnu$$(SPACE),$$(SPACE)$3$$(SPACE))
+      $1_no_archs += $$(foreach cpu,$$($1_no_cpus),$$(foreach system,$$($1_no_systems_tmp),!$$(subst gnu,$$(cpu),$$(system))))
+    endif
+  endif
+  ifneq (,$$($1_no_systems))
+    $1_no_systems_tmp := $$(subst $$(SPACE)gnu$$(SPACE),$$(SPACE)hurd-gnu$$(SPACE),$$(SPACE)$$($1_no_systems)$$(SPACE))
+    $1_no_archs += $$(foreach system,$$($1_no_systems_tmp),$$(foreach cpu,$2,!$$(subst gnu,$$(cpu),$$(system))))
+  endif
+  $1_no_archs := $$(strip $$($1_no_archs))
+endef
+base_deb_cpus := amd64 i386 alpha
+base_deb_systems :=
+$(foreach x,ada java java_plugin fortran libgphobos libgc check locale,$(eval $(call gen_no_archs,$(x),$(base_deb_cpus),$(base_deb_systems))))
+linux_no_archs := !hurd-any !kfreebsd-any
+
+GCC_VERSION := $(strip $(shell cat $(firstword $(wildcard $(srcdir)/gcc/FULL-VER $(srcdir)/gcc/BASE-VER))))
+NEXT_GCC_VERSION := $(shell echo $(GCC_VERSION) | \
+	awk -F. '{OFS="."; $$2 += 1; $$3=0; print}')
+GCC_MAJOR_VERSION := $(shell echo $(GCC_VERSION)   | sed -r 's/([0-9])\.[0-9]\.[0-9]/\1/')
+GCC_MINOR_VERSION := $(shell echo $(GCC_VERSION)   | sed -r 's/[0-9]\.([0-9])\.[0-9]/\1/')
+GCC_RELEASE_VERSION := $(shell echo $(GCC_VERSION) | sed -r 's/[0-9]\.[0-9]\.([0-9])/\1/')
+NEXT_GCC_MAJOR_VERSION := $(shell expr $(echo $(GCC_MAJOR_VERSION)) + 1)
+NEXT_GCC_MINOR_VERSION := $(shell expr $(echo $(GCC_MINOR_VERSION)) + 1)
+NEXT_GCC_RELEASE_VERSION := $(shell expr $(echo $(GCC_MAJOR_VERSION)) + 1)
+
+ifeq ($(single_package),yes)
+  BASE_VERSION := $(shell echo $(GCC_VERSION) | sed -e 's/\([1-9]*\).*/\1/')
+endif
+
+GCC_SOURCE_VERSION := $(shell echo $(DEB_VERSION) | sed 's/-.*//')
+NEXT_GCC_SOURCE_VERSION := $(shell echo $(GCC_SOURCE_VERSION) | \
+	awk -F. '{OFS="."; $$2 += 1; $$3=0; print}')
+
+MAINTAINER = Debian GCC Maintainers <debian-gcc@lists.debian.org>
+ifeq ($(distribution),Ubuntu)
+  ifneq (,$(findstring $(PKGSOURCE),gnat gdc))
+    MAINTAINER = Ubuntu MOTU Developers <ubuntu-motu@lists.ubuntu.com>
+  else
+    MAINTAINER = Ubuntu Core developers <ubuntu-devel-discuss@lists.ubuntu.com>
+  endif
+endif
+
+UPLOADERS = Matthias Klose <doko@debian.org>
+ifneq (,$(findstring $(PKGSOURCE),gnat))
+  UPLOADERS = Ludovic Brenta <lbrenta@debian.org>
+endif
+ifneq (,$(findstring $(PKGSOURCE),gdc))
+  UPLOADERS = Iain Buclaw <ibuclaw@ubuntu.com>, Matthias Klose <doko@debian.org>
+endif
+
+DPKGV = 1.14.15
+ifeq ($(with_multiarch_lib),yes)
+  DPKGV = 1.16.0~ubuntu4
+endif
+ifeq ($(multiarch_stage1),yes)
+  DPKGV = 1.16.0~ubuntu4
+endif
+ifeq (,$(filter $(distrelease),lenny etch squeeze wheezy dapper hardy jaunty karmic lucid maverick natty oneiric precise quantal raring saucy trusty utopic))
+  DPKGV = 1.17.14
+endif
+DPKG_BUILD_DEP = dpkg-dev (>= $(DPKGV)),
+
+MIPS_R6_ENABLED = no
+ifeq (,$(filter $(distrelease),lenny etch squeeze wheezy jessie dapper hardy jaunty karmic lucid maverick natty oneiric precise quantal raring saucy trusty utopic vivid wily xenial yakkety zesty artful))
+  MIPS_R6_ENABLED = yes
+endif
+
+ifeq ($(DEB_HOST_ARCH),$(DEB_TARGET_ARCH))
+  TARGET_QUAL = :$(DEB_TARGET_ARCH)
+endif
+
+# The binutils version needed.
+# The oldest suitable versions for the various platforms can be found in
+# INSTALL/specific.html ; we take a tighter dependency if possible to be on
+# the safe side (something like newest( version in stable, versions for the
+# various platforms in INSTALL/specific.html) ).
+# We need binutils (>= 2.19.1) for a new dwarf unwind expression opcode.
+# See http://gcc.gnu.org/ml/gcc-patches/2008-09/msg01713.html
+ifeq ($(trunk_build),yes)
+  BINUTILSBDV = 2.23
+else
+  BINUTILSBDV = 2.22
+  ifneq (,$(filter $(distrelease),vivid))
+    BINUTILSBDV = 2.25-3~
+  else ifneq (,$(filter $(distrelease),jessie))
+    BINUTILSBDV = 2.25-7~
+  else ifneq (,$(filter $(distrelease),xenial))
+    BINUTILSBDV = 2.26.1
+  else ifneq (,$(filter $(distrelease),stretch zesty ))
+    BINUTILSBDV = 2.28-3
+  else ifneq (,$(filter $(distrelease),artful))
+    BINUTILSBDV = 2.29.1
+  else ifneq (,$(filter $(distrelease),sid buster bionic))
+    BINUTILSBDV = 2.30
+  endif
+endif
+ifeq ($(DEB_CROSS),yes)
+  BINUTILS_BUILD_DEP = binutils$(TS)$(NT) (>= $(BINUTILSBDV)), binutils-multiarch$(NT) (>= $(BINUTILSBDV))
+  BINUTILSV := $(shell dpkg -l binutils$(TS) \
+			| awk '/^ii/{print $$3;exit}' | sed 's/-.*//')
+else
+  BINUTILS_BUILD_DEP = binutils$(NT) (>= $(BINUTILSBDV)) | binutils-multiarch$(NT) (>= $(BINUTILSBDV))
+  ifneq (,$(findstring cross-build-,$(build_type)))
+    BINUTILSV := $(shell dpkg -l binutils$(TS) \
+			| awk '/^ii/{print $$3;exit}' | sed 's/-.*//')
+  else
+    BINUTILSV := $(shell dpkg -l binutils binutils-multiarch \
+			| awk '/^ii/{print $$3;exit}' | sed 's/-.*//')
+  endif
+endif
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+  ifeq (,$(filter gccgo% gcj% gnat%, $(PKGSOURCE)))
+    ifeq ($(hppa64_archs),hppa)
+      BINUTILS_BUILD_DEP += , binutils-hppa64$(NT) (>= $(BINUTILSBDV)) [$(hppa64_archs)]
+    else
+      BINUTILS_BUILD_DEP += , binutils-hppa64-linux-gnu$(NT) (>= $(BINUTILSBDV)) [$(hppa64_archs)]
+    endif
+  endif
+endif
+ifeq (,$(BINUTILSV))
+  BINUTILSV := $(BINUTILSBDV)
+endif
+
+# FIXME; stripping doesn't work with gold
+#BINUTILS_BUILD_DEP += , binutils-gold (>= $(BINUTILSV)) [$(gold_archs)]
+
+# libc-dev dependencies
+libc_ver := 2.11
+libc_dev_ver := $(libc_ver)
+ifeq ($(with_multiarch_lib),yes)
+  ifeq ($(derivative),Debian)
+    libc_dev_ver := 2.13-5
+  else
+    libc_dev_ver := 2.13-0ubuntu6
+  endif
+endif
+# first set LIBC_DEP/LIBC_DEV_DEP for native builds only
+ifeq ($(DEB_TARGET_ARCH_OS),linux)
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),alpha ia64))
+    LIBC_DEP = libc6.1
+  else
+    LIBC_DEP = libc6
+  endif
+  ifneq (,$(findstring musl-linux-,$(DEB_TARGET_ARCH)))
+    LIBC_DEP = musl
+    libc_ver = 0.9
+    libc_dev_ver = 0.9
+  endif
+else
+  ifeq ($(DEB_TARGET_ARCH_OS),hurd)
+    LIBC_DEP = libc0.3
+  endif
+  ifeq ($(DEB_TARGET_ARCH_OS),kfreebsd)
+    LIBC_DEP = libc0.1
+  endif
+  ifeq ($(DEB_TARGET_ARCH),uclibc)
+       LIBC_DEP = libuclibc
+  endif
+endif
+LIBC_DEV_DEP := $(LIBC_DEP)-dev
+
+# this is about Debian archs name, *NOT* GNU target triplet
+biarch_deb_map := \
+	i386=amd64 amd64=i386 \
+	mips=mips64 mipsel=mips64el \
+	mipsn32=mips mipsn32el=mipsel \
+	mips64=mips mips64el=mipsel \
+	powerpc=ppc64 ppc64=powerpc \
+	sparc=sparc64 sparc64=sparc\
+	s390=s390x s390x=s390 \
+	kfreebsd-amd64=i386 \
+	armel=armhf \
+	armhf=armel
+ifeq (yes,$(MIPS_R6_ENABLED))
+  biarch_deb_map += mipsr6=mips64r6 mipsr6el=mips64r6el \
+	mipsn32r6=mipsr6 mipsn32r6el=mipsr6el \
+	mips64r6=mipsr6 mips64r6el=mipsr6el
+endif
+biarch_deb_arch := $(patsubst $(DEB_TARGET_ARCH)=%,%, \
+	$(filter $(DEB_TARGET_ARCH)=%,$(biarch_deb_map)))
+
+LIBC_BIARCH_DEP :=
+LIBC_BIARCH_DEV_DEP :=
+ifneq (,$(findstring yes,$(biarch64) $(biarch32) $(biarchn32) $(biarchx32)$(biarchhf)$(biarchsf)))
+  LIBC_BIARCH_DEP := $${shlibs:Depends}
+  LIBC_BIARCH_DEV_DEP := $(LIBC_DEV_DEP)-$(biarch_deb_arch)$(LS)$(AQ) (>= $(libc_ver))
+  # amd64, x32, i386
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),amd64 x32 i386))
+  ifeq ($(biarch64)$(biarch32),yesyes)
+    LIBC_BIARCH_DEV_DEP := $(LIBC_DEV_DEP)-amd64$(LS)$(AQ) (>= $(libc_ver)), $(LIBC_DEV_DEP)-i386$(LS)$(AQ) (>= $(libc_ver))
+  endif
+  ifeq ($(biarch64)$(biarchx32),yesyes)
+    LIBC_BIARCH_DEV_DEP := $(LIBC_DEV_DEP)-amd64$(LS)$(AQ) (>= $(libc_ver)), $(LIBC_DEV_DEP)-x32$(LS)$(AQ) (>= $(libc_ver))
+  endif
+  ifeq ($(biarch32)$(biarchx32),yesyes)
+    LIBC_BIARCH_DEV_DEP := $(LIBC_DEV_DEP)-i386$(LS)$(AQ) (>= $(libc_ver)), $(LIBC_DEV_DEP)-x32$(LS)$(AQ) (>= $(libc_ver))
+  endif
+  endif
+  # mips*
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),mips mipsel mipsn32 mipsn32el mips64 mips64el mipsr6 mipsr6el mipsn32r6 mipsn32r6el mips64r6 mips64r6el))
+  ifeq ($(biarchn32)$(biarch32),yesyes)
+      LIBC_BIARCH_DEV_DEP := libc6-dev-mips32$(LS)$(AQ) (>= $(libc_ver)), libc6-dev-mipsn32$(LS)$(AQ) (>= $(libc_ver))
+  endif
+  ifeq ($(biarch64)$(biarch32),yesyes)
+      triarch := $(COMMA)$(SPACE)
+      LIBC_BIARCH_DEV_DEP := libc6-dev-mips32$(LS)$(AQ) (>= $(libc_ver)), libc6-dev-mips64$(LS)$(AQ) (>= $(libc_ver))
+  endif
+  ifeq ($(biarchn32)$(biarch64),yesyes)
+      triarch := $(COMMA)$(SPACE)
+      LIBC_BIARCH_DEV_DEP := libc6-dev-mips64$(LS)$(AQ) (>= $(libc_ver)), libc6-dev-mipsn32$(LS)$(AQ) (>= $(libc_ver))
+  endif
+  endif
+
+  ifeq ($(biarchhf),yes)
+    LIBC_BIARCH_DEP := $(LIBC_DEP)-$(biarch_deb_arch)$(LS)$(AQ) (>= $(libc_ver))
+    LIBC_BIARCH_DEP += | $(LIBC_DEP)-$(biarch_deb_arch)$(LS)$(AQ)
+    LIBC_BIARCH_DEV_DEP += | $(LIBC_DEV_DEP)-$(biarch_deb_arch)$(LS)$(AQ)
+  endif
+  ifeq ($(biarchsf),yes)
+    LIBC_BIARCH_DEP := $(LIBC_DEP)-$(biarch_deb_arch)$(LS)$(AQ) (>= $(libc_ver))
+    LIBC_BIARCH_DEP += | $(LIBC_DEP)-$(biarch_deb_arch)$(LS)$(AQ)
+    LIBC_BIARCH_DEV_DEP += | $(LIBC_DEV_DEP)-$(biarch_deb_arch)$(LS)$(AQ)
+  endif
+endif
+
+# now add the cross suffix and required version
+LIBC_DEP := $(LIBC_DEP)$(LS)$(AQ)
+LIBC_DEV_DEP := $(LIBC_DEV_DEP)$(LS)$(AQ) (>= $(libc_dev_ver))
+
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+  LIBC_DBG_DEP = libc6.1-dbg [alpha ia64] | libc0.3-dbg [hurd-i386] | libc0.1-dbg [kfreebsd-i386 kfreebsd-amd64] | libc6-dbg,
+endif
+
+# TODO: make this automatic, there must be a better way to define LIBC_DEP.
+ifneq ($(DEB_CROSS),yes)
+  LIBC_BUILD_DEP = libc6.1-dev (>= $(libc_dev_ver)) [alpha ia64] | libc0.3-dev (>= $(libc_dev_ver)) [hurd-i386] | libc0.1-dev (>= $(libc_dev_ver)) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= $(libc_dev_ver))
+  ifeq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid maverick natty oneiric))
+    LIBC_BUILD_DEP += , libc6-dev (>= 2.13-31) [armel armhf]
+  endif
+  LIBC_BIARCH_BUILD_DEP = libc6-dev-amd64 [i386 x32], libc6-dev-sparc64 [sparc], libc6-dev-sparc [sparc64], libc6-dev-s390 [s390x], libc6-dev-s390x [s390], libc6-dev-i386 [amd64 x32], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64 mipsn32 mipsn32el mips64 mips64el s390x sparc64 x32], libn32gcc1 [mips mipsel mips64 mips64el], lib64gcc1 [i386 mips mipsel mipsn32 mipsn32el powerpc sparc s390 x32], libc6-dev-mips64 [mips mipsel mipsn32 mipsn32el], libc6-dev-mipsn32 [mips mipsel mips64 mips64el], libc6-dev-mips32 [mipsn32 mipsn32el mips64 mips64el],
+  ifeq (yes,$(MIPS_R6_ENABLED))
+    LIBC_BIARCH_BUILD_DEP = libc6-dev-amd64 [i386 x32], libc6-dev-sparc64 [sparc], libc6-dev-sparc [sparc64], libc6-dev-s390 [s390x], libc6-dev-s390x [s390], libc6-dev-i386 [amd64 x32], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64 mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el s390x sparc64 x32], libn32gcc1 [mips mipsel mips64 mips64el mipsr6 mipsr6el mips64r6 mips64r6el], lib64gcc1 [i386 mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el powerpc sparc s390 x32], libc6-dev-mips64 [mips mipsel mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el], libc6-dev-mipsn32 [mips mipsel mips64 mips64el mipsr6 mipsr6el mips64r6 mips64r6el], libc6-dev-mips32 [mipsn32 mipsn32el mips64 mips64el mipsn32r6 mipsn32r6el mips64r6 mips64r6el],
+  endif
+ifneq (,$(findstring amd64,$(biarchx32archs)))
+  LIBC_BIARCH_BUILD_DEP += libc6-dev-x32 [amd64 i386], libx32gcc1 [amd64 i386],
+endif
+ifneq (,$(findstring armel,$(biarchhfarchs)))
+  LIBC_BIARCH_BUILD_DEP += libc6-dev-armhf [armel], libhfgcc1 [armel],
+endif
+ifneq (,$(findstring armhf,$(biarchsfarchs)))
+  LIBC_BIARCH_BUILD_DEP += libc6-dev-armel [armhf], libsfgcc1 [armhf],
+endif
+else
+  LIBC_BUILD_DEP = $(LIBC_DEV_DEP),
+  ifneq ($(LIBC_BIARCH_DEV_DEP),)
+    LIBC_BIARCH_BUILD_DEP = $(LIBC_BIARCH_DEV_DEP),
+  else
+    LIBC_BIARCH_BUILD_DEP =
+  endif
+endif
+
+# needed for the include/asm symlink to run the testsuite for
+# non default multilibs
+ifneq (,$(multilib_archs))
+  GCC_MULTILIB_BUILD_DEP = g++-multilib [$(multilib_archs)]$(pf_ncross),
+endif
+GCC_MULTILIB_BUILD_DEP += g++-6 [arm64]$(pf_ncross),
+
+LIBUNWIND_DEV_DEP := libunwind8-dev$(LS)$(AQ)
+LIBUNWIND_BUILD_DEP := $(LIBUNWIND_DEV_DEP) [ia64],
+LIBATOMIC_OPS_BUILD_DEP := libatomic-ops-dev$(LS) [ia64],
+ifneq ($(DEB_TARGET_ARCH),ia64)
+  LIBUNWIND_DEV_DEP := # nothing
+else ifneq (,$(filter $(DEB_STAGE),stage1 stage2))
+  LIBUNWIND_DEV_DEP := # nothing
+endif
+
+ifneq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid maverick natty))
+  GMP_BUILD_DEP = libgmp3-dev | libgmp-dev (>= 2:5.0.1~),
+  MPFR_BUILD_DEP = libmpfr-dev,
+else
+  GMP_BUILD_DEP = libgmp-dev (>= 2:5.0.1~),
+  MPFR_BUILD_DEP = libmpfr-dev (>= 3.0.0-9~),
+endif
+
+ISL_BUILD_DEP = libisl-dev,
+ifneq (,$(filter $(distrelease),jessie stretch sid experimental))
+  ISL_BUILD_DEP = libisl-dev (>= 0.14),
+endif
+
+ifneq (,$(filter $(distrelease),lenny etch squeeze wheezy dapper hardy jaunty karmic lucid maverick natty oneiric precise quantal raring))
+  MPC_BUILD_DEP = libmpc-dev,
+else ifneq (,$(filter $(distrelease),sid buster bionic))
+  MPC_BUILD_DEP = libmpc-dev (>= 1.1),
+else
+  MPC_BUILD_DEP = libmpc-dev (>= 1.0),
+endif
+
+SOURCE_BUILD_DEP :=
+ifeq (,$(findstring gcc,$(PKGSOURCE)))
+  SOURCE_BUILD_DEP := gcc-$(BASE_VERSION)-source (>= $(GCC_SOURCE_VERSION)), gcc-$(BASE_VERSION)-source (<< $(NEXT_GCC_SOURCE_VERSION)),
+endif
+
+CHECK_BUILD_DEP := dejagnu [$(check_no_archs)],
+
+AUTO_BUILD_DEP := m4, libtool,
+AUTO_BUILD_DEP += autoconf2.64,
+
+ifeq (,$(filter $(distrelease),lenny etch squeeze wheezy dapper hardy jaunty karmic lucid maverick natty oneiric precise quantal raring saucy trusty))
+  SDT_BUILD_DEP = systemtap-sdt-dev [linux-any kfreebsd-any hurd-any],
+endif
+
+# ensure that the common libs, built from the next GCC version are available
+ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+  ifneq ($(with_common_libs),yes)
+    BASE_BUILD_DEP = gcc-7-base,
+  endif
+endif
+
+PHOBOS_BUILD_DEP = lib32z1-dev [amd64 kfreebsd-amd64], lib64z1-dev [i386],
+ifeq ($(derivative),Ubuntu)
+  PHOBOS_BUILD_DEP += libx32z1-dev [amd64 kfreebsd-amd64 i386],
+endif
+
+ifneq ($(DEB_CROSS),yes)
+# all archs for which to create b-d's
+any_archs = alpha amd64 armel armhf arm64 i386 mips mipsel mips64 mips64el mipsn32 powerpc ppc64 ppc64el m68k sh4 sparc64 s390x x32
+ifeq (yes,$(MIPS_R6_ENABLED))
+  any_archs +=  mipsn32el mipsr6 mipsr6el mips64r6 mips64r6el mipsn32r6 mipsn32r6el
+endif
+arch_gnutype_map = \
+	alpha=alpha-linux-gnu \
+	amd64=x86-64-linux-gnu \
+	armel=arm-linux-gnueabi \
+	armhf=arm-linux-gnueabihf \
+	arm64=aarch64-linux-gnu \
+	i386=i686-linux-gnu \
+	mips=mips-linux-gnu \
+	mipsel=mipsel-linux-gnu \
+	mipsn32=mips64-linux-gnuabin32 \
+	mipsn32el=mips64el-linux-gnuabin32 \
+	mips64=mips64-linux-gnuabi64 \
+	mips64el=mips64el-linux-gnuabi64 \
+	powerpc=powerpc-linux-gnu \
+	ppc64=powerpc64-linux-gnu \
+	ppc64el=powerpc64le-linux-gnu \
+	m68k=m68k-linux-gnu \
+	sh4=sh4-linux-gnu \
+	sparc64=sparc64-linux-gnu \
+	s390x=s390x-linux-gnu \
+	x32=x86-64-linux-gnux32
+
+ifeq (yes,$(MIPS_R6_ENABLED))
+  arch_gnutype_map +=  mipsr6=mipsisa32r6-linux-gnu \
+	mipsr6el=mipsisa32r6el-linux-gnu \
+	mipsn32r6=mipsisa64r6-linux-gnuabin32 \
+	mipsn32r6el=mipsisa64r6el-linux-gnuabin32 \
+	mips64r6=mipsisa64r6-linux-gnuabi64 \
+	mips64r6el=mipsisa64r6el-linux-gnuabi64
+endif
+
+_element = $(filter $1=%,$(arch_gnutype_map))
+_gnu_type = $(subst $1=,,$(filter $1=%,$(arch_gnutype_map)))
+
+ifneq (,$(filter $(distrelease),lenny etch squeeze wheezy wheezy dapper hardy jaunty karmic lucid maverick natty oneiric precise quantal raring saucy trusty utopic vivid))
+  DEBHELPER_BUILD_DEP = debhelper (>= 9),
+  TARGET_TOOL_BUILD_DEP = bash, # non-empty line
+  pf_cross =
+  pf_ncross =
+else
+  DEBHELPER_BUILD_DEP = debhelper (>= 9.20141010),
+  TARGET_TOOL_BUILD_DEP = \
+	$(foreach a, $(any_archs), \
+	  g++-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>, \
+	  $(if $(filter $(a), avr),, \
+	    gobjc-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>,) \
+	  gfortran-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>, \
+	  $(if $(filter $(a), avr),, \
+	    gcj-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>,) \
+	  $(if $(filter $(a), s390 sh4),, \
+	    gdc-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>,) \
+	  $(if $(filter $(a), hppa m68k sh4),, \
+	    gccgo-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>,) \
+	  $(if $(filter $(a), m68k mips64 powerpcspe sh4 sparc64 x32),, \
+	    gnat-$(BASE_VERSION)-$(call _gnu_type,$(a)) [$(a)] <cross>,) \
+	)
+  pf_cross = $(SPACE)<cross>
+  pf_ncross = $(SPACE)<!cross>
+  NT = :native
+endif
+
+JAVA_BUILD_DEP := zlib1g-dev, libantlr-java, python$(NT), libffi-dev,
+
+ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+  bd_java_archs =
+else ifeq ($(single_package)-$(with_java),yes-yes)
+  bd_java_archs =
+else
+  bd_java_archs = $(if $(java_no_archs),$(EMPTY) [$(java_no_archs)])
+endif
+
+ifneq (,$(java_awt_peers))
+  JAVA_BUILD_DEP += fastjar$(bd_java_archs), libmagic-dev$(bd_java_archs),
+  JAVA_BUILD_DEP += libecj-java (>= 3.3.0-2)$(bd_java_archs), zip$(bd_java_archs),
+  ifeq ($(with_java_maintainer_mode),yes)
+    # gcj-6 needed for gjavah-6.
+    JAVA_BUILD_DEP += gcj-6$(bd_java_archs), ecj (>= 3.3.0-2)$(bd_java_archs),
+  endif
+  JAVA_BUILD_DEP += libasound2-dev [$(java_no_archs) $(linux_no_archs)],
+  ifneq (,$(findstring gtk,$(java_awt_peers)))
+    JAVA_BUILD_DEP += libxtst-dev$(bd_java_archs), libxt-dev$(bd_java_archs), libgtk2.0-dev (>= 2.4.4-2)$(bd_java_archs), libart-2.0-dev$(bd_java_archs), libcairo2-dev$(bd_java_archs),
+  endif
+  ifneq (,$(findstring qt,$(java_awt_peers)))
+    JAVA_BUILD_DEP += libqt4-dev (>= 4.1.0)$(bd_java_archs),
+  endif
+  # gconf peer, disabled by default
+  #JAVA_BUILD_DEP += libgconf2-dev$(bd_java_archs),
+  # gstreamer peer
+  #JAVA_BUILD_DEP += libgstreamer-plugins-base0.10-dev$(bd_java_archs),
+endif
+ifneq ($(with_standalone_gcj),yes)
+  ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+    JAVA_BUILD_DEP += $(SOURCE_BUILD_DEP)
+  endif
+endif
+#JAVA_BUILD_INDEP := gcj-$(BASE_VERSION)-jdk
+ifeq ($(single_package),yes)
+  LIBSTDCXX_BUILD_INDEP = doxygen (>= 1.7.2), graphviz (>= 2.2), ghostscript, texlive-latex-base
+  LIBSTDCXX_BUILD_INDEP +=, xsltproc, libxml2-utils, docbook-xsl-ns
+  JAVA_BUILD_INDEP :=
+endif
+ifeq ($(with_separate_libgcj),yes)
+  ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+    JAVA_BUILD_DEP :=
+    JAVA_BUILD_INDEP :=
+  endif
+endif
+
+ifeq ($(with_ecj),yes)
+  ifneq (./,$(dir $(ecj_jar)))
+    ECJ_DEP = libecj-java (>= 3.5.1)
+  endif
+else
+  ECJ_DEP = ecj, libecj-java (>= 3.5.1)
+  ECJ_DEP = ecj-gcj, libecj-java-gcj (>= 3.5.1)
+  ifeq ($(with_external_ecj1),yes)
+    ECJ_DEP +=, ecj1
+  endif
+endif
+
+ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+  LIBSTDCXX_BUILD_INDEP = doxygen (>= 1.7.2), graphviz (>= 2.2), ghostscript, texlive-latex-base
+  ifeq (,$(filter $(distrelease),lenny etch dapper hardy jaunty karmic lucid maverick natty oneiric))
+    LIBSTDCXX_BUILD_INDEP +=, xsltproc, libxml2-utils, docbook-xsl-ns
+  endif
+  JAVA_BUILD_INDEP :=, $(JAVA_BUILD_INDEP)
+endif
+
+GO_BUILD_DEP := netbase,
+
+# try to build with itself, or with the last version
+ifneq (,$(filter $(distrelease), jessie))
+  gnat_build_dep := gnat-4.9$(NT) [$(ada_no_archs)], g++-4.9$(NT)
+else ifneq (,$(filter $(distrelease), wheezy precise trusty wily xenial))
+  gnat_build_dep := gnat-5$(NT) [$(ada_no_archs)], g++-5$(NT)
+else ifneq (,$(filter $(distrelease), stretch sid yakkety zesty artful bionic))
+  gnat_build_dep := gnat-6$(NT) [$(ada_no_archs)], g++-6$(NT)
+else ifneq (,$(filter $(distrelease), squeeze lucid))
+  gnat_build_dep :=
+else
+  gnat_build_dep := gnat$(NT) [$(ada_no_archs)]
+endif
+
+ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+  ifneq ($(with_separate_gnat),yes)
+    # Build gnat as part of the combined gcc-x.y source package.  Do not fail
+    # if gnat is not present on unsupported architectures; the build scripts
+    # will not use gnat anyway.
+    GNAT_BUILD_DEP := $(gnat_build_dep),
+  endif
+else ifeq ($(single_package),yes)
+  # Ditto, as part of the gcc-snapshot package.
+  GNAT_BUILD_DEP := $(gnat_build_dep),
+else ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION))
+  # Special source package just for gnat. Fail early if gnat is not present,
+  # rather than waste CPU cycles and fail later.
+  # Bootstrap step needs a gnatgcc symbolic link.
+  GNAT_BUILD_DEP := $(gnat_build_dep),
+  GNAT_BUILD_DEP += $(SOURCE_BUILD_DEP)
+  JAVA_BUILD_DEP :=
+  JAVA_BUILD_INDEP :=
+  GDC_BUILD_DEP :=
+  GO_BUILD_DEP :=
+else ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+  # Special source package just for gcj.
+  GNAT_BUILD_DEP :=
+  GDC_BUILD_DEP :=
+  GO_BUILD_DEP :=
+else ifeq ($(PKGSOURCE),gdc-$(BASE_VERSION))
+  # Special source package just for gdc.
+  GNAT_BUILD_DEP :=
+  JAVA_BUILD_DEP :=
+  JAVA_BUILD_INDEP :=
+  GDC_BUILD_DEP := $(SOURCE_BUILD_DEP)
+  GO_BUILD_DEP :=
+else ifeq ($(PKGSOURCE),gccgo-$(BASE_VERSION))
+  # Special source package just for gccgo.
+  GNAT_BUILD_DEP :=
+  JAVA_BUILD_DEP :=
+  JAVA_BUILD_INDEP :=
+  GDC_BUILD_DEP := $(SOURCE_BUILD_DEP)
+endif
+
+
+else
+# build cross compiler
+  CROSS_BUILD_DEP := libc6-dev$(cross_lib_arch),
+ifneq (,$(findstring cross-build-,$(build_type)))
+  CROSS_BUILD_DEP += zlib1g-dev$(cross_lib_arch), libmpfr-dev$(cross_lib_arch),
+endif
+  SOURCE_BUILD_DEP :=
+  ifeq (,$(findstring gcc,$(PKGSOURCE)))
+    SOURCE_BUILD_DEP := gcc-$(BASE_VERSION)-source (>= $(GCC_SOURCE_VERSION)), gcc-$(BASE_VERSION)-source (<< $(NEXT_GCC_SOURCE_VERSION)),
+  endif
+  ifeq ($(with_java),yes)
+    JAVA_BUILD_DEP := zlib1g-dev, lib64z1-dev [i386 powerpc sparc s390], lib32z1-dev [amd64 ppc64 kfreebsd-amd64 s390x],
+  endif
+  JAVA_BUILD_INDEP :=
+  GNAT_BUILD_DEP :=
+endif # cross compiler
+
+BASE_BREAKS := gcc-4.4-base (<< 4.4.7), gcc-4.7-base (<< 4.7.3), gcj-4.4-base (<< 4.4.6-9~), gnat-4.4-base (<< 4.4.6-3~), gcj-4.6-base (<< 4.6.1-4~), gnat-4.6 (<< 4.6.1-5~)
+# these would need proper updates, and are only needed for upgrades
+ifneq (,$(filter $(distrelease),squeeze wheezy lucid precise trusty))
+  BASE_BREAKS :=
+endif
+
+
+# The numeric part of the gcc version number (x.yy.zz)
+NEXT_GCC_VERSION := $(shell echo $(GCC_VERSION) | \
+		awk -F. '{OFS="."; if (NF==2) $$3=1; else $$NF += 1; print}')
+# first version with a new path component in gcc_lib_dir (i.e. GCC_VERSION
+# or TARGET_ALIAS changes), or last version available for all architectures
+DEB_GCC_SOFT_VERSION := 6.3.0-1
+DEB_GCJ_SOFT_VERSION := 6.3.0-1
+DEB_GNAT_SOFT_VERSION := 6.3.0-1
+
+ifeq ($(with_d),yes)
+  GDC_VERSION := $(BASE_VERSION)
+  DEB_GDC_VERSION := $(DEB_VERSION)
+endif
+
+# semiautomatic ...
+DEB_SOVERSION		:= $(DEB_VERSION)
+DEB_SOVERSION		:= 5
+DEB_SOEVERSION		:= $(EPOCH):5
+DEB_STDCXX_SOVERSION	:= 5
+DEB_GCJ_SOVERSION	:= 5
+DEB_GOMP_SOVERSION	:= $(DEB_SOVERSION)
+
+DEB_GCC_VERSION := $(DEB_VERSION)
+DEB_GCJ_VERSION := $(DEB_VERSION)
+ifeq ($(with_separate_libgcj),yes)
+  ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+    DEB_GCC_VERSION := $(DEB_GCC_SOFT_VERSION)
+  endif
+endif
+
+DEB_GNAT_VERSION := $(DEB_VERSION)
+ifeq ($(with_separate_gnat),yes)
+  ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION))
+    DEB_GCC_VERSION := $(DEB_GCC_SOFT_VERSION)
+  endif
+endif
+
+GNAT_VERSION := $(BASE_VERSION)
+
+LIBGNAT_DEP :=
+ifeq ($(with_libgnat),yes)
+  LIBGNAT_DEP := libgnat-$(GNAT_VERSION)$(LS)$(AQ) (>= $${gcc:Version})
+endif
+
+pkg_ver := -$(BASE_VERSION)
+
+PKG_GCJ_EXT = $(GCJ_SONAME1)
+PKG_LIBGCJ_EXT = $(GCJ_SONAME1)$(if $(GCJ_SONAME2),-$(GCJ_SONAME2))
+
+ctrl_flags = \
+	-DBINUTILSV=$(BINUTILSV) \
+	-DBINUTILSBDV=$(BINUTILSBDV) \
+	-DSRCNAME=$(PKGSOURCE) \
+	-D__$(DEB_TARGET_GNU_CPU)__ \
+	-DARCH=$(DEB_TARGET_ARCH) \
+	-DDIST=$(distribution)
+
+ctrl_flags += \
+	-DLIBC_DEV_DEP="$(LIBC_DEV_DEP)" \
+	-DLIBC_BIARCH_BUILD_DEP="$(LIBC_BIARCH_BUILD_DEP)" \
+	-DLIBC_DBG_DEP="$(LIBC_DBG_DEP)" \
+	-DBASE_BUILD_DEP="$(BASE_BUILD_DEP)" \
+	-DFORTRAN_BUILD_DEP="$(FORTRAN_BUILD_DEP)" \
+	-DGNAT_BUILD_DEP="$(GNAT_BUILD_DEP)" \
+	-DJAVA_BUILD_DEP="$(JAVA_BUILD_DEP)" \
+	-DGO_BUILD_DEP="$(GO_BUILD_DEP)" \
+	-DJAVA_BUILD_INDEP="$(JAVA_BUILD_INDEP)" \
+	-DLIBSTDCXX_BUILD_INDEP="$(LIBSTDCXX_BUILD_INDEP)" \
+	-DGDC_BUILD_DEP="$(GDC_BUILD_DEP)" \
+	-DBINUTILS_BUILD_DEP="$(BINUTILS_BUILD_DEP)" \
+	-DLIBC_BUILD_DEP="$(LIBC_BUILD_DEP)" \
+	-DCHECK_BUILD_DEP="$(CHECK_BUILD_DEP)" \
+	-DAUTO_BUILD_DEP="$(AUTO_BUILD_DEP)" \
+	-DSDT_BUILD_DEP="$(SDT_BUILD_DEP)" \
+	-DISL_BUILD_DEP="$(ISL_BUILD_DEP)" \
+	-DGMP_BUILD_DEP="$(GMP_BUILD_DEP)" \
+	-DMPFR_BUILD_DEP="$(MPFR_BUILD_DEP)" \
+	-DMPC_BUILD_DEP="$(MPC_BUILD_DEP)" \
+	-DDEBHELPER_BUILD_DEP="$(DEBHELPER_BUILD_DEP)" \
+	-DDPKG_BUILD_DEP="$(DPKG_BUILD_DEP)" \
+	-DSOURCE_BUILD_DEP="$(SOURCE_BUILD_DEP)" \
+	-DCROSS_BUILD_DEP="$(CROSS_BUILD_DEP)" \
+	-DGCC_MULTILIB_BUILD_DEP='$(GCC_MULTILIB_BUILD_DEP)' \
+	-DTARGET_TOOL_BUILD_DEP='$(TARGET_TOOL_BUILD_DEP)' \
+	-DPHOBOS_BUILD_DEP="$(PHOBOS_BUILD_DEP)" \
+	-DMULTILIB_ARCHS="$(multilib_archs)" \
+	-DNEON_ARCHS="$(neon_archs)" \
+	-DTP=$(TP) \
+	-DTS=$(TS) \
+	-DLS=$(LS) \
+	-DAQ=$(AQ) \
+	-DNT=$(NT)
+
+ifeq ($(DEB_CROSS),yes)
+  ctrl_flags += \
+	-DTARGET=$(DEB_TARGET_ARCH) \
+	-DLIBUNWIND_BUILD_DEP="$(LIBUNWIND_BUILD_DEP)" \
+	-DLIBATOMIC_OPS_BUILD_DEP="$(LIBATOMIC_OPS_BUILD_DEP)"
+  ifeq ($(DEB_STAGE),rtlibs)
+    ctrl_flags += -DCROSS_ARCH=$(DEB_TARGET_ARCH)
+  endif
+else
+  # add '-DPRI=optional' to ctrl_flags if this is not the default compiler
+  # ctrl_flags += \
+  #     -DPRI=optional
+endif
+
+ifeq ($(with_base_only),yes)
+  ctrl_flags += \
+	-DBASE_ONLY=yes
+endif
+
+ifeq ($(with_multiarch_lib),yes)
+  ctrl_flags += \
+	-DMULTIARCH=yes
+endif
+
+control: control-file readme-bugs-file parameters-file symbols-files copyright-file substvars-file versioned-files check-versions
+
+# stage1 and stage2 compilers are only C
+ifneq (,$(filter $(DEB_STAGE),stage1 stage2))
+  languages = c
+  addons = gccbase cdev plugindev
+  ifeq ($(with_gcclbase),yes)
+    addons += gcclbase
+  endif
+  ifeq ($(multilib),yes)
+    addons += multilib
+  endif
+  addons += $(if $(findstring armel,$(biarchhfarchs)),armml)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),armml)
+  addons += $(if $(findstring amd64,$(biarchx32archs)),x32dev)
+  ifeq ($(DEB_STAGE),stage2)
+    addons += libgcc
+    ifeq ($(multilib),yes)
+      addons += lib32gcc lib64gcc libn32gcc
+      addons += $(if $(findstring amd64,$(biarchx32archs)),libx32gcc)
+      addons += $(if $(findstring armel,$(biarchhfarchs)),libhfgcc)
+      addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfgcc)
+    endif
+  else
+    LIBC_BIARCH_DEV_DEP :=
+  endif
+else
+languages = c c++ fortran objc objpp
+ifeq ($(DEB_STAGE),rtlibs)
+  ifeq (,$(filter libgfortran, $(with_rtlibs)))
+    languages := $(filter-out fortran, $(languages))
+  endif
+  ifeq (,$(filter libobjc, $(with_rtlibs)))
+    languages := $(filter-out objc objpp, $(languages))
+  endif
+endif
+ifeq ($(with_gccbase),yes)
+    addons += gccbase
+endif
+ifeq ($(with_gcclbase),yes)
+  addons += gcclbase
+endif
+ifneq ($(DEB_STAGE),rtlibs)
+  addons += cdev c++dev source multilib
+  ifeq ($(build_type),build-native)
+    addons += testresults
+  endif
+  ifneq (,$(filter fortran, $(languages)))
+      addons += fdev
+  endif
+  ifneq (,$(filter objc, $(languages)))
+      addons += objcdev
+  endif
+  ifneq (,$(filter objpp, $(languages)))
+      addons += objppdev
+  endif
+  addons += plugindev
+endif
+addons += $(if $(findstring armel,$(biarchhfarchs)),armml)
+addons += $(if $(findstring armhf,$(biarchsfarchs)),armml)
+addons += $(if $(findstring amd64,$(biarchx32archs)),x32dev)
+ifeq ($(with_libgcc),yes)
+  addons += libgcc lib4gcc lib32gcc lib64gcc libn32gcc
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32gcc)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfgcc)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfgcc)
+endif
+ifeq ($(with_libcxx),yes)
+  addons += libcxx lib32cxx lib64cxx libn32cxx
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32cxx)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfcxx)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfcxx)
+endif
+addons += $(if $(findstring amd64,$(biarchx32archs)),libx32dbgcxx)
+addons += $(if $(findstring armel,$(biarchhfarchs)),libhfdbgcxx)
+addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfdbgcxx)
+ifeq ($(with_libgfortran),yes)
+  addons += libgfortran lib32gfortran lib64gfortran libn32gfortran
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32gfortran)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfgfortran)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfgfortran)
+endif
+ifeq ($(with_libobjc),yes)
+  addons += libobjc lib32objc lib64objc libn32objc
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32objc)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfobjc)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfobjc)
+endif
+ifeq ($(with_libgomp),yes)
+  addons += libgomp lib32gomp lib64gomp libn32gomp
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32gomp)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfgomp)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfgomp)
+endif
+ifeq ($(with_libitm),yes)
+  addons += libitm lib32itm lib64itm libn32itm
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32itm)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfitm)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfitm)
+endif
+ifeq ($(with_libatomic),yes)
+  addons += libatomic lib32atomic lib64atomic libn32atomic
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32atomic)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfatomic)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfatomic)
+endif
+ifeq ($(with_libbacktrace),yes)
+  addons += libbtrace lib32btrace lib64btrace libn32btrace
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32btrace)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfbtrace)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfbtrace)
+endif
+ifeq ($(with_libasan),yes)
+  addons += libasan lib32asan lib64asan libn32asan
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32asan)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfasan)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfasan)
+endif
+ifeq ($(with_liblsan),yes)
+  addons += liblsan lib32lsan lib64lsan libn32lsan
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32lsan)
+  #addons += $(if $(findstring armel,$(biarchhfarchs)),libhflsan)
+  #addons += $(if $(findstring armhf,$(biarchsfarchs)),libsflsan)
+endif
+ifeq ($(with_libtsan),yes)
+  addons += libtsan
+  addons += libtsan #lib32tsan lib64tsan libn32tsan
+  #addons += $(if $(findstring amd64,$(biarchx32archs)),libx32tsan)
+  #addons += $(if $(findstring armel,$(biarchhfarchs)),libhftsan)
+  #addons += $(if $(findstring armhf,$(biarchsfarchs)),libsftsan)
+endif
+ifeq ($(with_libubsan),yes)
+  addons += libubsan lib32ubsan lib64ubsan libn32ubsan
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32ubsan)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfubsan)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfubsan)
+endif
+ifeq ($(with_vtv),yes)
+  addons += libvtv lib32vtv lib64vtv #libn32vtv
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32vtv)
+  #addons += $(if $(findstring armel,$(biarchhfarchs)),libhfvtv)
+  #addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfvtv)
+endif
+ifeq ($(with_libcilkrts),yes)
+  addons += libcilkrts
+  addons += libcilkrts lib32cilkrts lib64cilkrts #libn32cilkrts
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32cilkrts)
+  #addons += $(if $(findstring armel,$(biarchhfarchs)),libhfcilkrts)
+  #addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfcilkrts)
+endif
+ifeq ($(with_mpx),yes)
+  addons += libmpx lib32mpx lib64mpx
+endif
+ifeq ($(with_libqmath),yes)
+  addons += libqmath lib32qmath lib64qmath libn32qmath
+  addons += $(if $(findstring amd64,$(biarchx32archs)),libx32qmath)
+  addons += $(if $(findstring armel,$(biarchhfarchs)),libhfqmath)
+  addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfqmath)
+endif
+ifeq ($(with_jit),yes)
+  addons += jit
+endif
+ifeq ($(with_libgccjit),yes)
+  addons += libjit
+endif
+ifeq ($(with_libcc1),yes)
+  addons += libcc1
+endif
+ifeq ($(with_d),yes)
+  languages += d
+  ifeq ($(with_libphobos),yes)
+    addons += libphobos
+    addons += $(if $(findstring amd64,$(biarchx32archs)),libx32phobos)
+  endif
+endif
+ifeq ($(with_go),yes)
+  addons += ggo godev
+  ifeq ($(with_libgo),yes)
+    addons += libggo lib32ggo lib64ggo libn32ggo
+    addons += $(if $(findstring amd64,$(biarchx32archs)),libx32ggo)
+  endif
+endif
+ifeq ($(with_ada),yes)
+  languages += ada
+  addons += libgnat libs # libgmath libnof lib64gnat ssp
+  ifeq ($(with_gnatsjlj),yes)
+    addons += adasjlj
+  endif
+endif
+ifeq ($(with_java),yes)
+  languages += java
+  addons += gcj
+  ifneq ($(DEB_CROSS),yes)
+    addons += libgcj libgcjdev gcjdoc gcjsrc
+  endif
+endif
+
+  ifneq ($(DEB_CROSS),yes)
+  ifneq (,$(neon_archs))
+    addons += libneongcc libneongomp libneonitm libneonobjc libneongfortran libneoncxx
+  endif
+  ifeq ($(with_fixincl),yes)
+    addons += $(if $(DEB_STAGE),,fixincl)
+  endif
+  ifeq ($(with_libgcj_doc),yes)
+    addons += gcjdoc
+  endif
+  endif # DEB_CROSS
+#  ifneq (,$(findstring gtk, $(java_awt_peers)))
+#    addons += gtkpeer
+#  endif
+#  ifneq (,$(findstring qt, $(java_awt_peers)))
+#    addons += qtpeer
+#  endif
+  ifeq ($(with_separate_libgcj),yes)
+    ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+      languages := $(filter-out java,$(languages))
+      addons := $(filter-out gcj libgcj libgcjdev gcjdoc gcjsrc gtkpeer qtpeer,$(addons))
+    endif
+    ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+      languages = java
+      addons = gcj libgcj libgcjdev gcjsrc
+      addons += $(if $(filter yes,$(with_gcjbase)),gcjbase)
+      addons += $(if $(filter yes,$(with_gcjxbase)),gcjxbase)
+    ifeq ($(with_libgcj_doc),yes)
+      addons += gcjdoc
+    endif
+#      ifneq (,$(findstring gtk, $(java_awt_peers)))
+#        addons += gtkpeer
+#      endif
+#      ifneq (,$(findstring qt, $(java_awt_peers)))
+#        addons += qtpeer
+#      endif
+      ifeq ($(with_standalone_gcj),yes)
+	addons += libgcc lib4gcc lib64gcc lib32gcc libn32gcc libx32gcc
+      endif
+    endif
+  endif
+  ifeq ($(DEB_CROSS),yes)
+    addons := $(filter-out gcjdoc gcjsrc,$(addons))
+  endif
+  ifeq ($(with_standalone_gcj),yes)
+    ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+      ctrl_flags += -DSTANDALONEJAVA
+    endif
+  endif
+  ifeq ($(with_separate_libgo),yes)
+    ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+      languages := $(filter-out go,$(languages))
+      addons := $(filter-out ggo godev libggo lib64ggo lib32ggo libn32ggo libx32ggo,$(addons))
+    endif
+    ifeq ($(PKGSOURCE),gccgo-$(BASE_VERSION))
+      languages = go
+      addons = ggo godev libggo lib64ggo lib32ggo libn32ggo gccbase multilib
+      addons += $(if $(findstring amd64,$(biarchx32archs)),libx32ggo)
+      ifeq ($(with_standalone_go),yes)
+        addons += libgcc lib4gcc lib32gcc lib64gcc libn32gcc
+        addons += $(if $(findstring amd64,$(biarchx32archs)),libx32gcc)
+        addons += $(if $(findstring armel,$(biarchhfarchs)),libhfgcc)
+        addons += $(if $(findstring armhf,$(biarchsfarchs)),libsfgcc)
+        ifeq ($(with_libcc1),yes)
+          addons += libcc1
+        endif
+      endif
+    endif
+  endif
+  ifeq ($(with_standalone_go),yes)
+    ifeq ($(PKGSOURCE),gccgo-$(BASE_VERSION))
+      ctrl_flags += -DSTANDALONEGO
+    endif
+  endif
+  ifeq ($(with_separate_gnat),yes)
+    ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+      languages := $(filter-out ada,$(languages))
+      addons := $(filter-out libgnat adasjlj,$(addons))
+    endif
+    ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION))
+      languages = ada
+      addons = gnatbase libgnat
+    endif
+  endif
+  ifeq ($(with_separate_gdc),yes)
+    ifeq ($(PKGSOURCE),gcc-$(BASE_VERSION))
+      languages := $(filter-out d,$(languages))
+    endif
+    ifeq ($(PKGSOURCE),gdc-$(BASE_VERSION))
+      languages = d
+      addons = 
+      ifeq ($(with_libphobos),yes)
+        addons += libphobos
+      endif
+    endif
+  endif
+  ifneq ($(DEB_CROSS),yes) # no docs for cross compilers
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+    addons += gfdldoc
+  endif
+  endif
+endif # not stage
+
+control-file:
+	echo "addons: $(addons)"; \
+	m4 $(ctrl_flags) \
+	  -DPV=$(pkg_ver) \
+	  -DCXX_SO=$(CXX_SONAME) \
+	  -DGCC_SO=$(GCC_SONAME) \
+	  -DOBJC_SO=$(OBJC_SONAME) \
+	  -DFORTRAN_SO=$(FORTRAN_SONAME) \
+	  -DGCJ_SO=$(PKG_GCJ_EXT) \
+	  -DLIBGCJ_EXT=$(PKG_LIBGCJ_EXT) \
+	  -DGNAT_SO=$(GNAT_SONAME) \
+	  -DGNAT_V=$(GNAT_VERSION) \
+	  -DPHOBOS_V=$(GPHOBOS_SONAME) \
+	  -DGDRUNTIME_V=$(GDRUNTIME_SONAME) \
+	  -DGOMP_SO=$(GOMP_SONAME) \
+	  -DITM_SO=$(ITM_SONAME) \
+	  -DATOMIC_SO=$(ATOMIC_SONAME) \
+	  -DBTRACE_SO=$(BTRACE_SONAME) \
+	  -DASAN_SO=$(ASAN_SONAME) \
+	  -DLSAN_SO=$(LSAN_SONAME) \
+	  -DTSAN_SO=$(TSAN_SONAME) \
+	  -DUBSAN_SO=$(UBSAN_SONAME) \
+	  -DVTV_SO=$(VTV_SONAME) \
+	  -DCILKRTS_SO=$(CILKRTS_SONAME) \
+	  -DMPX_SO=$(MPX_SONAME) \
+	  -DQMATH_SO=$(QUADMATH_SONAME) \
+	  -DSSP_SO=$(SSP_SONAME) \
+	  -DGO_SO=$(GO_SONAME) \
+	  -DCC1_SO=$(CC1_SONAME) \
+	  -DGCCJIT_SO=$(GCCJIT_SONAME) \
+	  -Denabled_languages="$(languages) $(addons)" \
+	  -Dada_no_archs="$(ada_no_archs)" \
+	  -Djava_no_archs="$(java_no_archs)" \
+	  -Dfortran_no_archs="$(fortran_no_archs)" \
+	  -Dlibgc_no_archs="$(libgc_no_archs)" \
+	  -Dlibphobos_archs="$(libphobos_archs)" \
+	  -Dlibphobos_no_archs="$(libphobos_no_archs)" \
+	  -Dcheck_no_archs="$(check_no_archs)" \
+	  -Dlocale_no_archs="$(locale_no_archs)" \
+	  -Dlinux_gnu_archs="$(linux_gnu_archs)" \
+	  -Dbiarch32_archs="$(strip $(subst /, ,$(biarch32archs)))" \
+	  -Dbiarch64_archs="$(strip $(subst /, ,$(biarch64archs)))" \
+	  -Dbiarchn32_archs="$(strip $(subst /, ,$(biarchn32archs)))" \
+	  -Dbiarchx32_archs="$(strip $(subst /, ,$(biarchx32archs)))" \
+	  -Dbiarchhf_archs="$(strip $(subst /, ,$(biarchhfarchs)))" \
+	  -Dbiarchsf_archs="$(strip $(subst /, ,$(biarchsfarchs)))" \
+	  -Dadd_built_using=$(add_built_using) \
+	  -DGCC_PORTS_BUILD=$(GCC_PORTS_BUILD) \
+	  -DPR66145BREAKS="$(if $(findstring build-native,$(build_type)),$(if $(filter new,$(libstdcxx_abi)),$$(tr '\n' ' ' < debian/libstdc++-breaks.$(derivative))))" \
+		debian/control.m4 > debian/control.tmp2
+	uniq debian/control.tmp2 | sed '/^Build/s/ *, */, /g;/^  /s/ *, */, /g' \
+		$(if $(filter yes, $(with_base_only)), | awk '/^$$/ {if (p) exit; else p=1; } {print}') \
+		> debian/control.tmp
+	rm -f debian/control.tmp2
+	[ -e debian/control ] \
+	  && cmp -s debian/control debian/control.tmp \
+	  && rm -f debian/control.tmp && exit 0; \
+	  mv debian/control.tmp debian/control; touch $(control_stamp)
+
+readme-bugs-file:
+	m4 -DDIST=$(distribution) -DSRCNAME=$(PKGSOURCE) \
+		debian/README.Bugs.m4 > debian/README.Bugs
+
+copyright-file:
+	rm -f debian/copyright
+	if echo $(SOURCE_VERSION) | grep -E ^'[0-9]\.[0-9]-[0-9]{8}' ; \
+		then SVN_BRANCH="trunk" ; \
+	else \
+		SVN_BRANCH="gcc-$(subst .,_,$(BASE_VERSION))-branch" ; \
+	fi ; \
+	sed debian/copyright.in		\
+		-e "s/@BV@/$(BASE_VERSION)/g"		\
+		-e "s/@SVN_BRANCH@/$$SVN_BRANCH/g"	\
+		> debian/copyright
+
+substvars-file: control-file
+	rm -f debian/substvars.local.tmp
+	( \
+		echo 'libgcc:Version=$(DEB_LIBGCC_VERSION)'; \
+		echo 'gcc:Version=$(DEB_GCC_VERSION)'; \
+		echo 'gcc:EpochVersion=$(DEB_EVERSION)'; \
+		echo 'gcc:SoftVersion=$(DEB_GCC_SOFT_VERSION)'; \
+		echo 'gdc:Version=$(DEB_GDC_VERSION)'; \
+		echo 'gcj:Version=$(DEB_GCJ_VERSION)'; \
+		echo 'gcj:SoftVersion=$(DEB_GCJ_SOFT_VERSION)'; \
+		echo 'gcj:BaseVersion=$(BASE_VERSION)'; \
+		echo 'gnat:Version=$(DEB_GNAT_VERSION)'; \
+		echo 'gnat:SoftVersion=$(DEB_GNAT_SOFT_VERSION)'; \
+		echo 'binutils:Version=$(BINUTILSV)'; \
+		echo 'dep:libgcc=$(LIBGCC_DEP)'; \
+		echo 'dep:libgccdev=$(LIBGCC_DEV_DEP)'; \
+		echo 'dep:libgccbiarch=$(libgccbiarch)'; \
+		echo 'dep:libgccbiarchdev=$(libgccbiarchdev)'; \
+		echo 'dep:libc=$(LIBC_DEP) (>= $(libc_ver))'; \
+		echo 'dep:libcdev=$(LIBC_DEV_DEP)'; \
+		echo 'dep:libcbiarch=$(LIBC_BIARCH_DEP)'; \
+		echo 'dep:libcbiarchdev=$(LIBC_BIARCH_DEV_DEP)'; \
+		echo 'dep:libunwinddev=$(LIBUNWIND_DEV_DEP)'; \
+		echo 'dep:libcxxbiarchdev=$(libstdc++biarchdev)'; \
+		echo 'dep:libcxxbiarchdbg=$(libstdc++biarchdbg)'; \
+		echo 'dep:libgnat=$(LIBGNAT_DEP)'; \
+		echo 'dep:ecj=$(ECJ_DEP)'; \
+		echo 'base:Breaks=$(BASE_BREAKS)'; \
+	) > debian/substvars.local.tmp
+ifneq (,$(filter $(DEB_TARGET_ARCH), $(multilib_archs)))
+	( \
+		echo 'gcc:multilib=gcc-$(BASE_VERSION)-multilib$(TS)'; \
+		echo 'gxx:multilib=g++-$(BASE_VERSION)-multilib$(TS)'; \
+		echo 'gobjc:multilib=gobjc-$(BASE_VERSION)-multilib$(TS)'; \
+		echo 'gobjcxx:multilib=gobjc++-$(BASE_VERSION)-multilib$(TS)'; \
+		echo 'gfortran:multilib=gfortran-$(BASE_VERSION)-multilib$(TS)'; \
+	) >> debian/substvars.local.tmp
+endif
+ifeq ($(with_gold),yes)
+	echo 'dep:gold=binutils-gold (>= $(BINUTILSV))' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_libssp),yes)
+	echo 'dep:libssp=libssp$(SSP_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_gomp),yes)
+	echo 'dep:libgomp=libgomp$(GOMP_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_itm),yes)
+	echo 'dep:libitm=libitm$(ITM_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_atomic),yes)
+	echo 'dep:libatomic=libatomic$(ATOMIC_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_libbacktrace),yes)
+	echo 'dep:libbacktrace=libbtrace$(BTRACE_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_asan),yes)
+	echo 'dep:libasan=libasan$(ASAN_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_lsan),yes)
+	echo 'dep:liblsan=liblsan$(LSAN_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_tsan),yes)
+	echo 'dep:libtsan=libtsan$(TSAN_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_ubsan),yes)
+	echo 'dep:libubsan=libubsan$(UBSAN_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_vtv),yes)
+	echo 'dep:libvtv=libvtv$(VTV_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_cilkrts),yes)
+	echo 'dep:libcilkrts=libcilkrts$(CILKRTS_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_mpx),yes)
+	echo 'dep:libmpx=libmpx$(MPX_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_qmath),yes)
+	echo 'dep:libqmath=libquadmath$(QUADMATH_SONAME)$(LS)$(AQ) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(distribution),Debian)
+	echo 'dep:libx32z=$(if $(filter $(distribution), Debian),,libx32z1-dev)' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(multilib),yes)
+	echo 'dep:libgfortranbiarchdev=$(libgfortranbiarchdev)' \
+		>> debian/substvars.local.tmp
+	echo 'dep:libobjcbiarchdev=$(libobjcbiarchdev)' \
+		>> debian/substvars.local.tmp
+  ifeq ($(with_libphobos),yes)
+	echo 'dep:libphobosbiarchdev=$(libgphobosbiarchdev)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_libssp),yes)
+	echo 'dep:libsspbiarch=$(libsspbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_gomp),yes)
+	echo 'dep:libgompbiarch=$(libgompbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_itm),yes)
+	echo 'dep:libitmbiarch=$(libitmbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_atomic),yes)
+	echo 'dep:libatomicbiarch=$(libatomicbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_libbacktrace),yes)
+	echo 'dep:libbtracebiarch=$(libbtracebiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_asan),yes)
+	echo 'dep:libasanbiarch=$(libasanbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_lsan),yes)
+	#echo 'dep:liblsanbiarch=$(liblsanbiarch)' \
+	#	>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_tsan),yes)
+	#echo 'dep:libtsanbiarch=$(libtsanbiarch)' \
+	#	>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_ubsan),yes)
+	echo 'dep:libubsanbiarch=$(libubsanbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_vtv),yes)
+	echo 'dep:libvtvbiarch=$(libvtvbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_cilkrts),yes)
+	echo 'dep:libcilkrtsbiarch=$(libcilkrtsbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_mpx),yes)
+	echo 'dep:libmpxbiarch=$(libmpxbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_qmath),yes)
+	echo 'dep:libqmathbiarch=$(libquadmathbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_go),yes)
+	echo 'dep:libgobiarchdev=$(libgobiarchdev)' \
+		>> debian/substvars.local.tmp
+	echo 'dep:libgobiarch=$(libgobiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(with_libphobosdev),yes)
+	echo 'dep:libphobosbiarchdev=$(libgphobosbiarchdev)' \
+		>> debian/substvars.local.tmp
+	echo 'dep:libphobosbiarch=$(libgphobosbiarch)' \
+		>> debian/substvars.local.tmp
+  endif
+endif
+ifneq ($(with_standalone_gcj),yes)
+  ifneq (,$(filter $(DEB_HOST_ARCH),armel armhf))
+	echo 'dep:gcj=g++$(pkg_ver) (>= $(DEB_GCC_SOFT_VERSION))' \
+		>> debian/substvars.local.tmp
+  else
+	echo 'dep:gcj=gcc$(pkg_ver) (>= $(DEB_GCC_SOFT_VERSION))' \
+		>> debian/substvars.local.tmp
+  endif
+  ifeq ($(DEB_CROSS),yes)
+	echo 'dep:gcjcross=gcj$(pkg_ver) (>= $(DEB_GCC_SOFT_VERSION))' \
+		>> debian/substvars.local.tmp
+  endif
+endif
+ifeq ($(DEB_CROSS),yes)
+	echo 'dep:gdccross=gdc$(pkg_ver) (>= $(DEB_GCC_SOFT_VERSION))' \
+		>> debian/substvars.local.tmp
+endif
+ifeq ($(with_libphobos),yes)
+	echo 'dep:phobosdev=libgphobos$(pkg_ver)-dev$(LS)$(AQ) (>= $(DEB_GCC_SOFT_VERSION))' \
+		>> debian/substvars.local.tmp
+  ifeq ($(DEB_CROSS),yes)
+	: # FIXME: make the cross gdc aware of both include paths
+	echo 'dep:gdccross=gdc$(pkg_ver) (>= $(DEB_GCC_SOFT_VERSION))' \
+		>> debian/substvars.local.tmp
+  endif
+endif
+ifeq ($(with_cc1),yes)
+  ifneq (,$(findstring build-cross, $(build_type)))
+	echo 'dep:libcc1=libcc1-$(CC1_SONAME) (>= $${gcc:SoftVersion})' \
+		>> debian/substvars.local.tmp
+  else
+	echo 'dep:libcc1=libcc1-$(CC1_SONAME) (>= $${gcc:Version})' \
+		>> debian/substvars.local.tmp
+  endif
+endif
+#ifneq (,$(findstring gtk, $(java_awt_peers)))
+#	echo 'pkg:gcjgtk=libgcj$(subst 0,,$(GCJ_SONAME))-awt-gtk (>= $(DEB_GCJ_VERSION))' \
+#		>> debian/substvars.local.tmp
+#endif
+#ifneq (,$(findstring qt, $(java_awt_peers)))
+#	echo 'pkg:gcjqt=libgcj$(subst 0,,$(GCJ_SONAME))-awt-qt (>= $(DEB_GCJ_VERSION))' \
+#		>> debian/substvars.local.tmp
+#endif
+ifeq ($(DEB_HOST_ARCH),hppa)
+	echo 'dep:prctl=prctl' >> debian/substvars.local.tmp
+endif
+ifeq ($(derivative)-$(DEB_HOST_ARCH),Debian-amd64)
+	echo 'confl:lib32=libc6-i386 (<< 2.9-22)' >> debian/substvars.local.tmp
+endif
+ifeq ($(with_multiarch_lib),yes)
+	echo 'multiarch:breaks=gcc-4.3 (<< 4.3.6-1), gcc-4.4 (<< 4.4.6-4), gcc-4.5 (<< 4.5.3-2)' >> debian/substvars.local.tmp
+endif
+	echo 'golang:Conflicts=golang-go (<< 2:1.3.3-1ubuntu2)' >> debian/substvars.local.tmp
+ifeq ($(add_built_using),yes)
+	echo "Built-Using=$(shell dpkg-query -f '$${source:Package} (= $${source:Version}), ' -W gcc$(pkg_ver)-source)" \
+	>> debian/substvars.local.tmp
+endif
+	v=`sed -n '/^#define MOD_VERSION/s/.* "\([0-9]*\)"/\1/p' \
+		$(srcdir)/gcc/fortran/module.c`; \
+	echo "fortran:mod-version=gfortran-mod-$$v" >> debian/substvars.local.tmp
+
+	[ -e debian/substvars.local ] \
+	  && cmp -s debian/substvars.local debian/substvars.local.tmp \
+	  && rm -f debian/substvars.local.tmp && exit 0; \
+	  mv debian/substvars.local.tmp debian/substvars.local; \
+	  touch $(control_stamp)
+
+parameters-file:
+	rm -f debian/rules.parameters.tmp
+	( \
+		echo '# configuration parameters taken from upstream source files'; \
+		echo 'GCC_VERSION	:= $(GCC_VERSION)'; \
+		echo 'NEXT_GCC_VERSION	:= $(NEXT_GCC_VERSION)'; \
+		echo 'BASE_VERSION	:= $(BASE_VERSION)'; \
+		echo 'SOURCE_VERSION	:= $(SOURCE_VERSION)'; \
+		echo 'DEB_VERSION	:= $(DEB_VERSION)'; \
+		echo 'DEB_EVERSION	:= $(DEB_EVERSION)'; \
+		echo 'DEB_GDC_VERSION	:= $(DEB_GDC_VERSION)'; \
+		echo 'DEB_SOVERSION	:= $(DEB_SOVERSION)'; \
+		echo 'DEB_SOEVERSION	:= $(DEB_SOEVERSION)'; \
+		echo 'DEB_LIBGCC_SOVERSION	:= $(DEB_LIBGCC_SOVERSION)'; \
+		echo 'DEB_LIBGCC_VERSION	:= $(DEB_LIBGCC_VERSION)'; \
+		echo 'DEB_STDCXX_SOVERSION	:= $(DEB_STDCXX_SOVERSION)'; \
+		echo 'DEB_GCJ_SOVERSION	:= $(DEB_GCJ_SOVERSION)'; \
+		echo 'PKG_GCJ_EXT	:= $(PKG_GCJ_EXT)'; \
+		echo 'PKG_LIBGCJ_EXT	:= $(PKG_LIBGCJ_EXT)'; \
+		echo 'DEB_GOMP_SOVERSION	:= $(DEB_GOMP_SOVERSION)'; \
+		echo 'GCC_SONAME	:= $(GCC_SONAME)'; \
+		echo 'CXX_SONAME	:= $(CXX_SONAME)'; \
+		echo 'FORTRAN_SONAME	:= $(FORTRAN_SONAME)'; \
+		echo 'OBJC_SONAME	:= $(OBJC_SONAME)'; \
+		echo 'GCJ_SONAME	:= $(GCJ_SONAME)'; \
+		echo 'GDC_VERSION	:= $(GDC_VERSION)'; \
+		echo 'GNAT_VERSION	:= $(GNAT_VERSION)'; \
+		echo 'GNAT_SONAME	:= $(GNAT_SONAME)'; \
+		echo 'FFI_SONAME	:= $(FFI_SONAME)'; \
+		echo 'SSP_SONAME	:= $(SSP_SONAME)'; \
+		echo 'GOMP_SONAME	:= $(GOMP_SONAME)'; \
+		echo 'ITM_SONAME	:= $(ITM_SONAME)'; \
+		echo 'ATOMIC_SONAME	:= $(ATOMIC_SONAME)'; \
+		echo 'BTRACE_SONAME	:= $(BTRACE_SONAME)'; \
+		echo 'ASAN_SONAME	:= $(ASAN_SONAME)'; \
+		echo 'LSAN_SONAME	:= $(LSAN_SONAME)'; \
+		echo 'TSAN_SONAME	:= $(TSAN_SONAME)'; \
+		echo 'UBSAN_SONAME	:= $(UBSAN_SONAME)'; \
+		echo 'VTV_SONAME	:= $(VTV_SONAME)'; \
+		echo 'CILKRTS_SONAME	:= $(CILKRTS_SONAME)'; \
+		echo 'MPX_SONAME	:= $(MPX_SONAME)'; \
+		echo 'QUADMATH_SONAME	:= $(QUADMATH_SONAME)'; \
+		echo 'GO_SONAME		:= $(GO_SONAME)'; \
+		echo 'CC1_SONAME	:= $(CC1_SONAME)'; \
+		echo 'GCCJIT_SONAME	:= $(GCCJIT_SONAME)'; \
+		echo 'GPHOBOS_SONAME	:= $(GPHOBOS_SONAME)'; \
+		echo 'GDRUNTIME_SONAME	:= $(GDRUNTIME_SONAME)'; \
+		echo 'LIBC_DEP		:= $(LIBC_DEP)'; \
+	) > debian/rules.parameters.tmp
+	[ -e debian/rules.parameters ] \
+	  && cmp -s debian/rules.parameters debian/rules.parameters.tmp \
+	  && rm -f debian/rules.parameters.tmp && exit 0; \
+	  mv debian/rules.parameters.tmp debian/rules.parameters; \
+	  touch $(control_stamp)
+
+symbols-files: control-file
+ifeq ($(DEB_CROSS),yes)
+  ifneq ($(DEB_STAGE),rtlibs)
+	test -n "$(LS)"
+	set -e; \
+	for p in $$(dh_listpackages -i | grep '^lib'); do \
+	  p=$${p%$(LS)}; \
+	  if [ -f debian/$$p.symbols.$(DEB_TARGET_ARCH) ]; then \
+	    f=debian/$$p.symbols.$(DEB_TARGET_ARCH); \
+	  elif [ -f debian/$$p.symbols ]; then \
+	    f=debian/$$p.symbols; \
+	  else \
+	    continue; \
+	  fi; \
+	  link=debian/$$p$(LS).symbols; \
+	  if [ -L $$link ]; then \
+	    echo >&2 "removing left over symbols file link: $$link"; \
+	    rm -f $$link; \
+	  fi; \
+	  ln -s $$f $$link; \
+	done
+  endif
+endif
+
+versioned-files:
+	fs=`echo debian/*BV* debian/*GCJ* debian/*CXX* debian/*LC* | sort -u`; \
+	for f in $$fs debian/source.lintian-overrides.in; do \
+	  [ -f $$f ] || echo "CANNOT FIND $$f"; \
+	  [ -f $$f ] || continue; \
+	  if [ -z "$(DEB_CROSS)" ]; then case "$$f" in *-CR*) continue; esac; fi; \
+	  f2=$$(echo $$f \
+		| sed 's/BV/$(BASE_VERSION)/;s/CXX/$(CXX_SONAME)/;s/LGCJ/$(PKG_LIBGCJ_EXT)/;s/GCJ/$(PKG_GCJ_EXT)/;s/LC/$(GCC_SONAME)/;s/-CRB/$(cross_bin_arch)/;s/\.in$$//'); \
+	  sed -e 's/@BV@/$(BASE_VERSION)/g' \
+	      -e 's/@CXX@/$(CXX_SONAME)/g' \
+	      -e 's/@LGCJ@/$(PKG_LIBGCJ_EXT)/g' \
+	      -e 's/@GCJ@/$(PKG_GCJ_EXT)/g' \
+	      -e 's/@GCJSO@/$(GCJ_SONAME)/g' \
+	      -e 's/@LC@/$(GCC_SONAME)/g' \
+	      -e 's/@SRC@/$(PKGSOURCE)/g' \
+	      -e 's/@GFDL@/$(if $(filter yes,$(GFDL_INVARIANT_FREE)),#)/g' \
+	      -e 's/@java_priority@/$(java_priority)/g' \
+	      -e 's/@gcc_priority@/$(subst .,,$(BASE_VERSION))/g' \
+	      -e 's/@TARGET@/$(DEB_TARGET_GNU_TYPE)/g' \
+	      -e 's/@TARGET_QUAL@/$(TARGET_QUAL)/g' \
+	    $$f > $$f2; \
+	  touch -r $$f $$f2; \
+	done
+	for t in ar nm ranlib; do \
+	  sed "s/@BV@/$(BASE_VERSION)/g;s/@TOOL@/$$t/g" \
+	    debian/gcc-XX-BV.1 > debian/gcc-$$t-$(BASE_VERSION).1; \
+	done
+
+# don't encode versioned build dependencies in the control file, but check
+# these here instead.
+check-versions:
+	v=$$(dpkg-query -l dpkg-dev | awk '/^.i/ {print $$3}'); \
+	if dpkg --compare-versions "$$v" lt "$(DPKGV)"; then \
+	  echo "dpkg-dev (>= $(DPKGV)) required, found $$v"; \
+	  exit 1; \
+	fi
+	v=$$(dpkg-query -l binutils binutils-multiarch 2>/dev/null | awk '/^.i/ {print $$3;exit}'); \
+	if dpkg --compare-versions "$$v" lt "$(BINUTILSBDV)"; then \
+	  echo "binutils (>= $(BINUTILSBDV)) required, found $$v"; \
+	  exit 1; \
+	fi
+
+.PRECIOUS: $(stampdir)/%-stamp
--- gcc-6-6.4.0.orig/debian/rules.d/binary-ada.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-ada.mk
@@ -0,0 +1,410 @@
+ifeq ($(with_separate_gnat),yes)
+  $(lib_binaries) += gnatbase
+endif
+
+ifeq ($(with_libgnat),yes)
+  $(lib_binaries) += libgnat libgnatvsn libgnatprj
+endif
+
+arch_binaries := $(arch_binaries) ada
+ifneq ($(DEB_CROSS),yes)
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+    indep_binaries := $(indep_binaries) ada-doc
+  endif
+endif
+
+p_gbase		= $(p_xbase)
+p_glbase	= $(p_lbase)
+ifeq ($(with_separate_gnat),yes)
+  p_gbase	= gnat$(pkg_ver)$(cross_bin_arch)-base
+  p_glbase	= gnat$(pkg_ver)$(cross_bin_arch)-base
+endif
+
+p_gnat	= gnat-$(GNAT_VERSION)$(cross_bin_arch)
+p_gnatsjlj= gnat-$(GNAT_VERSION)-sjlj$(cross_bin_arch)
+p_lgnat	= libgnat-$(GNAT_VERSION)$(cross_lib_arch)
+p_lgnat_dbg = libgnat-$(GNAT_VERSION)-dbg$(cross_lib_arch)
+p_lgnatvsn = libgnatvsn$(GNAT_VERSION)$(cross_lib_arch)
+p_lgnatvsn_dev = libgnatvsn$(GNAT_VERSION)-dev$(cross_lib_arch)
+p_lgnatvsn_dbg = libgnatvsn$(GNAT_VERSION)-dbg$(cross_lib_arch)
+p_lgnatprj = libgnatprj$(GNAT_VERSION)$(cross_lib_arch)
+p_lgnatprj_dev = libgnatprj$(GNAT_VERSION)-dev$(cross_lib_arch)
+p_lgnatprj_dbg = libgnatprj$(GNAT_VERSION)-dbg$(cross_lib_arch)
+p_gnatd	= $(p_gnat)-doc
+
+d_gbase	= debian/$(p_gbase)
+d_gnat	= debian/$(p_gnat)
+d_gnatsjlj	= debian/$(p_gnatsjlj)
+d_lgnat	= debian/$(p_lgnat)
+d_lgnatvsn = debian/$(p_lgnatvsn)
+d_lgnatvsn_dev = debian/$(p_lgnatvsn_dev)
+d_lgnatprj = debian/$(p_lgnatprj)
+d_lgnatprj_dev = debian/$(p_lgnatprj_dev)
+d_gnatd	= debian/$(p_gnatd)
+
+GNAT_TOOLS = gnat gnatbind gnatchop gnatclean gnatfind gnatkr gnatlink \
+	     gnatls gnatmake gnatname gnatprep gnatxref gnathtml
+
+ifeq ($(with_gnatsjlj),yes)
+	rts_subdir = 
+endif
+
+dirs_gnat = \
+	$(docdir)/$(p_gbase) \
+	$(PF)/bin \
+	$(PF)/share/man/man1 \
+	$(gcc_lib_dir)/{adalib,adainclude} \
+	$(gcc_lexec_dir)
+
+files_gnat = \
+	$(gcc_lexec_dir)/gnat1 \
+	$(gcc_lib_dir)/adainclude/*.ad[bs] \
+	$(gcc_lib_dir)/adalib/*.ali \
+	$(gcc_lib_dir)/adalib/lib*.a \
+	$(foreach i,$(GNAT_TOOLS),$(PF)/bin/$(cmd_prefix)$(i)$(pkg_ver))
+
+dirs_lgnat = \
+	$(docdir) \
+	$(PF)/lib
+files_lgnat = \
+	$(usr_lib)/lib{gnat,gnarl}-$(GNAT_SONAME).so.1
+
+$(binary_stamp)-gnatbase: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	dh_installdocs -p$(p_gbase) debian/README.gnat debian/README.maintainers
+	: # $(p_gbase)
+ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION))
+	mkdir -p $(d_gbase)/$(docdir)/$(p_xbase)
+	ln -sf ../$(p_gbase) $(d_gbase)/$(docdir)/$(p_xbase)/Ada
+endif
+	dh_installchangelogs -p$(p_gbase) src/gcc/ada/ChangeLog
+	dh_compress -p$(p_gbase)
+	dh_fixperms -p$(p_gbase)
+	dh_gencontrol -p$(p_gbase) -- -v$(DEB_VERSION) $(common_substvars)
+	dh_installdeb -p$(p_gbase)
+	dh_md5sums -p$(p_gbase)
+	dh_builddeb -p$(p_gbase)
+	touch $@
+
+
+$(binary_stamp)-libgnat: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	: # libgnat
+	rm -rf $(d_lgnat)
+	dh_installdirs -p$(p_lgnat) $(dirs_lgnat)
+
+	for lib in lib{gnat,gnarl}; do \
+	  vlib=$$lib-$(GNAT_SONAME); \
+	  mv $(d)/$(gcc_lib_dir)/$(rts_subdir)/adalib/$$vlib.so.1 $(d)/$(usr_lib)/. ; \
+	  rm -f $(d)/$(gcc_lib_dir)/adalib/$$lib.so.1; \
+	done
+	$(dh_compat2) dh_movefiles -p$(p_lgnat) $(files_lgnat)
+
+	debian/dh_doclink -p$(p_lgnat) $(p_glbase)
+
+	debian/dh_rmemptydirs -p$(p_lgnat)
+
+	b=libgnat; \
+	v=$(GNAT_VERSION); \
+	for ext in preinst postinst prerm postrm; do \
+	  for t in '' -dev -dbg; do \
+	    if [ -f debian/$$b$$t.$$ext ]; then \
+	      cp -pf debian/$$b$$t.$$ext debian/$$b$$v$$t.$$ext; \
+	    fi; \
+	  done; \
+	done
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_lgnat) -V '$(p_lgnat) (>= $(DEB_VERSION))'
+	$(call cross_mangle_shlibs,$(p_lgnat))
+
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	mkdir -p $(d_lgnat)/usr/share/lintian/overrides
+	cp -p debian/$(p_lgnat).overrides \
+		$(d_lgnat)/usr/share/lintian/overrides/$(p_lgnat)
+endif
+
+	dh_strip -p$(p_lgnat) --dbg-package=$(p_lgnat_dbg)
+	$(cross_shlibdeps) dh_shlibdeps -p$(p_lgnat) \
+		$(call shlibdirs_to_search, \
+			$(subst gnat-$(GNAT_SONAME),gcc$(GCC_SONAME),$(p_lgnat)) \
+			$(subst gnat-$(GNAT_SONAME),atomic$(ATOMIC_SONAME),$(p_lgnat)) \
+		,) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common)
+	$(call cross_mangle_substvars,$(p_lgnat))
+
+	: # $(p_lgnat_dbg)
+	debian/dh_doclink -p$(p_lgnat_dbg) $(p_glbase)
+
+	echo $(p_lgnat) $(p_lgnat_dbg) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+
+$(binary_stamp)-libgnatvsn: $(install_stamp)
+	: # $(p_lgnatvsn_dev)
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	$(dh_compat2) dh_movefiles -p$(p_lgnatvsn_dev) usr/lib/ada/adalib/gnatvsn
+	$(dh_compat2) dh_movefiles -p$(p_lgnatvsn_dev) usr/share/ada/adainclude/gnatvsn
+	dh_install -p$(p_lgnatvsn_dev) \
+	   debian/gnatvsn.gpr usr/share/ada/adainclude
+else
+	mkdir -p $(d_lgnatvsn_dev)/$(gcc_lib_dir)/{adalib,adainclude}/gnatvsn
+	mv $(d)/usr/lib/ada/adalib/gnatvsn $(d_lgnatvsn_dev)/$(gcc_lib_dir)/adalib/.
+	mv $(d)/usr/share/ada/adainclude/gnatvsn $(d_lgnatvsn_dev)/$(gcc_lib_dir)/adainclude/.
+	dh_install -p$(p_lgnatvsn_dev) \
+	   debian/gnatvsn.gpr $(gcc_lib_dir)/adainclude
+endif
+	$(dh_compat2) dh_movefiles -p$(p_lgnatvsn_dev) $(usr_lib)/libgnatvsn.a
+	dh_link -p$(p_lgnatvsn_dev) \
+	   $(usr_lib)/libgnatvsn.so.$(GNAT_VERSION) \
+	   $(usr_lib)/libgnatvsn.so
+	debian/dh_doclink -p$(p_lgnatvsn_dev) $(p_glbase)
+	dh_strip -p$(p_lgnatvsn_dev) -X.a --keep-debug
+
+	: # $(p_lgnatvsn)
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	mkdir -p $(d_lgnatvsn)/usr/share/lintian/overrides
+	cp -p debian/$(p_lgnatvsn).overrides \
+		$(d_lgnatvsn)/usr/share/lintian/overrides/$(p_lgnatvsn)
+endif
+	$(dh_compat2) dh_movefiles -p$(p_lgnatvsn) $(usr_lib)/libgnatvsn.so.$(GNAT_VERSION)
+	debian/dh_doclink -p$(p_lgnatvsn) $(p_glbase)
+	dh_strip -p$(p_lgnatvsn) --dbg-package=$(p_lgnatvsn_dbg)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_lgnatvsn) \
+		-V '$(p_lgnatvsn) (>= $(DEB_VERSION))'
+	$(call cross_mangle_shlibs,$(p_lgnatvsn))
+	cat debian/$(p_lgnatvsn)/DEBIAN/shlibs >> debian/shlibs.local
+	$(cross_shlibdeps) dh_shlibdeps -p$(p_lgnatvsn) \
+		$(call shlibdirs_to_search, \
+			$(subst gnatvsn$(GNAT_SONAME),gcc$(GCC_SONAME),$(p_lgnatvsn)) \
+			$(subst gnatvsn$(GNAT_SONAME),atomic$(ATOMIC_SONAME),$(p_lgnatvsn)) \
+			$(subst gnatvsn$(GNAT_SONAME),gnat-$(GNAT_SONAME),$(p_lgnatvsn)) \
+		,) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common)
+	$(call cross_mangle_substvars,$(p_lgnatvsn))
+
+	: # $(p_lgnatvsn_dbg)
+	debian/dh_doclink -p$(p_lgnatvsn_dbg) $(p_glbase)
+
+	echo $(p_lgnatvsn) $(p_lgnatvsn_dev) $(p_lgnatvsn_dbg) >> debian/$(lib_binaries)
+	touch $@
+
+$(binary_stamp)-libgnatprj: $(install_stamp)
+	: # $(p_lgnatprj_dev)
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	$(dh_compat2) dh_movefiles -p$(p_lgnatprj_dev) usr/lib/ada/adalib/gnatprj
+	$(dh_compat2) dh_movefiles -p$(p_lgnatprj_dev) usr/share/ada/adainclude/gnatprj
+	dh_install -p$(p_lgnatprj_dev) \
+	   debian/gnatprj.gpr usr/share/ada/adainclude
+else
+	mkdir -p $(d_lgnatprj_dev)/$(gcc_lib_dir)/{adalib,adainclude}/gnatvsn
+	mv $(d)/usr/lib/ada/adalib/gnatprj $(d_lgnatprj_dev)/$(gcc_lib_dir)/adalib/.
+	mv $(d)/usr/share/ada/adainclude/gnatprj $(d_lgnatprj_dev)/$(gcc_lib_dir)/adainclude/.
+	dh_install -p$(p_lgnatprj_dev) \
+	   debian/gnatprj.gpr $(gcc_lib_dir)/adainclude
+endif
+	$(dh_compat2) dh_movefiles -p$(p_lgnatprj_dev) $(usr_lib)/libgnatprj.a
+	dh_link -p$(p_lgnatprj_dev) \
+	   $(usr_lib)/libgnatprj.so.$(GNAT_VERSION) \
+	   $(usr_lib)/libgnatprj.so
+	dh_strip -p$(p_lgnatprj_dev) -X.a --keep-debug
+	debian/dh_doclink -p$(p_lgnatprj_dev) $(p_glbase)
+
+	: # $(p_lgnatprj)
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	mkdir -p $(d_lgnatprj)/usr/share/lintian/overrides
+	cp -p debian/$(p_lgnatprj).overrides \
+		$(d_lgnatprj)/usr/share/lintian/overrides/$(p_lgnatprj)
+endif
+	$(dh_compat2) dh_movefiles -p$(p_lgnatprj) $(usr_lib)/libgnatprj.so.$(GNAT_VERSION)
+	debian/dh_doclink -p$(p_lgnatprj) $(p_glbase)
+	dh_strip -p$(p_lgnatprj) --dbg-package=$(p_lgnatprj_dbg)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_lgnatprj) \
+		-V '$(p_lgnatprj) (>= $(DEB_VERSION))'
+	$(call cross_mangle_shlibs,$(p_lgnatprj))
+	cat debian/$(p_lgnatprj)/DEBIAN/shlibs >> debian/shlibs.local
+	$(cross_shlibdeps) dh_shlibdeps -p$(p_lgnatprj) \
+		$(call shlibdirs_to_search, \
+			$(subst gnatprj$(GNAT_SONAME),gcc$(GCC_SONAME),$(p_lgnatprj)) \
+			$(subst gnatprj$(GNAT_SONAME),gnat-$(GNAT_SONAME),$(p_lgnatprj)) \
+			$(subst gnatprj$(GNAT_SONAME),gnatvsn$(GNAT_SONAME),$(p_lgnatprj)) \
+		,) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_lgnatprj))
+
+	: # $(p_lgnatprj_dbg)
+	debian/dh_doclink -p$(p_lgnatprj_dbg) $(p_glbase)
+
+	echo $(p_lgnatprj) $(p_lgnatprj_dev) $(p_lgnatprj_dbg) >> debian/$(lib_binaries)
+	touch $@
+
+$(binary_stamp)-ada: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+	: # $(p_gnat)
+	rm -rf $(d_gnat)
+	dh_installdirs -p$(p_gnat) $(dirs_gnat)
+	: # Upstream does not install gnathtml.
+	cp src/gcc/ada/gnathtml.pl debian/tmp/$(PF)/bin/$(cmd_prefix)gnathtml$(pkg_ver)
+	chmod 755 debian/tmp/$(PF)/bin/$(cmd_prefix)gnathtml$(pkg_ver)
+	$(dh_compat2) dh_movefiles -p$(p_gnat) $(files_gnat)
+
+ifeq ($(with_gnatsjlj),yes)
+	dh_installdirs -p$(p_gnatsjlj) $(gcc_lib_dir)
+	$(dh_compat2) dh_movefiles -p$(p_gnatsjlj) $(gcc_lib_dir)/rts-sjlj/adalib $(gcc_lib_dir)/rts-sjlj/adainclude
+endif
+
+ifeq ($(with_libgnat),yes)
+	for lib in lib{gnat,gnarl}; do \
+	  vlib=$$lib-$(GNAT_SONAME); \
+	  dh_link -p$(p_gnat) \
+	    /$(usr_lib)/$$vlib.so.1 /$(usr_lib)/$$vlib.so \
+	    /$(usr_lib)/$$vlib.so.1 /$(usr_lib)/$$lib.so; \
+	done
+	for lib in lib{gnat,gnarl}; do \
+	  vlib=$$lib-$(GNAT_SONAME); \
+	  dh_link -p$(p_gnat) \
+	    /$(usr_lib)/$$vlib.so.1 $(gcc_lib_dir)/$(rts_subdir)adalib/$$lib.so; \
+	done
+endif
+	debian/dh_doclink -p$(p_gnat)      $(p_gbase)
+ifeq ($(with_gnatsjlj),yes)
+	debian/dh_doclink -p$(p_gnatsjlj) $(p_gbase)
+endif
+ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION))
+  ifeq ($(with_check),yes)
+	cp -p test-summary $(d_gnat)/$(docdir)/$(p_gbase)/.
+  endif
+else
+	mkdir -p $(d_gnat)/$(docdir)/$(p_gbase)/ada
+	cp -p src/gcc/ada/ChangeLog $(d_gnat)/$(docdir)/$(p_gbase)/ada/.
+endif
+
+	for i in $(GNAT_TOOLS); do \
+	  case "$$i" in \
+	    gnat) cp -p debian/gnat.1 $(d_gnat)/$(PF)/share/man/man1/$(cmd_prefix)gnat$(pkg_ver).1 ;; \
+	    *) ln -sf $(cmd_prefix)gnat$(pkg_ver).1 $(d_gnat)/$(PF)/share/man/man1/$(cmd_prefix)$$i$(pkg_ver).1; \
+	  esac; \
+	done
+
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	: # see #814977, work around it for now ...
+	ln -sf gcc$(pkg_ver) $(d_gnat)/$(PF)/bin/gcc$(pkg_ver)$(pkg_ver)
+endif
+
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	: # still ship the unversioned prefixed names in the gnat package.
+	for i in $(GNAT_TOOLS); do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_gnat)/$(PF)/bin/$(cmd_prefix)$$i; \
+	  ln -sf $(cmd_prefix)gnat$(pkg_ver).1.gz \
+	    $(d_gnat)/$(PF)/share/man/man1/$(cmd_prefix)$$i.1.gz; \
+	done
+  ifeq ($(unprefixed_names),yes)
+	: # ship the versioned prefixed names in the gnat package.
+	for i in $(GNAT_TOOLS); do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_gnat)/$(PF)/bin/$$i$(pkg_ver); \
+	  ln -sf $(cmd_prefix)gnat$(pkg_ver).1.gz \
+	    $(d_gnat)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+
+	: # still ship the unversioned names in the gnat package.
+	for i in $(GNAT_TOOLS); do \
+	  ln -sf $$i$(pkg_ver) \
+	    $(d_gnat)/$(PF)/bin/$$i; \
+	  ln -sf gnat$(pkg_ver).1.gz \
+	    $(d_gnat)/$(PF)/share/man/man1/$$i.1.gz; \
+	done
+
+  endif
+else
+	: # still ship the unversioned prefixed names in the gnat package.
+	for i in $(GNAT_TOOLS); do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_gnat)/$(PF)/bin/$(cmd_prefix)$$i; \
+	  ln -sf $(cmd_prefix)gnat$(pkg_ver).1.gz \
+	    $(d_gnat)/$(PF)/share/man/man1/$(cmd_prefix)$$i.1.gz; \
+	done
+endif
+
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	dh_install -p$(p_gnat) debian/ada/debian_packaging.mk usr/share/ada
+	mv $(d_gnat)/usr/share/ada/debian_packaging.mk \
+	    $(d_gnat)/usr/share/ada/debian_packaging-$(GNAT_VERSION).mk
+endif
+	: # keep this one unversioned, see Debian #802838.
+	dh_link -p$(p_gnat) \
+		usr/bin/$(cmd_prefix)gcc$(pkg_ver) usr/bin/$(cmd_prefix)gnatgcc
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+	dh_link -p$(p_gnat) \
+		usr/share/man/man1/$(cmd_prefix)gcc$(pkg_ver).1.gz \
+		usr/share/man/man1/$(cmd_prefix)gnatgcc.1.gz
+endif
+ifeq ($(unprefixed_names),yes)
+	dh_link -p$(p_gnat) \
+		usr/bin/$(cmd_prefix)gcc$(pkg_ver) usr/bin/gnatgcc
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	dh_link -p$(p_gnat) \
+		usr/share/man/man1/$(cmd_prefix)gcc$(pkg_ver).1.gz \
+		usr/share/man/man1/gnatgcc.1.gz
+  endif
+endif
+	debian/dh_rmemptydirs -p$(p_gnat)
+
+	dh_strip -p$(p_gnat)
+	find $(d_gnat) -name '*.ali' | xargs chmod 444
+	$(cross_shlibdeps) dh_shlibdeps -p$(p_gnat) \
+		$(call shlibdirs_to_search, \
+			$(p_lgcc) $(p_lgnat) $(p_lgnatvsn) $(p_lgnatprj) \
+		,)
+	mkdir -p $(d_gnat)/usr/share/lintian/overrides
+	echo '$(p_gnat) binary: hardening-no-pie' \
+	  > $(d_gnat)/usr/share/lintian/overrides/$(p_gnat)
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	echo '$(p_gnat) binary: binary-without-manpage' \
+	  >> $(d_gnat)/usr/share/lintian/overrides/$(p_gnat)
+endif
+
+	echo $(p_gnat) >> debian/arch_binaries
+
+ifeq ($(with_gnatsjlj),yes)
+	dh_strip -p$(p_gnatsjlj)
+	find $(d_gnatsjlj) -name '*.ali' | xargs chmod 444
+	$(cross_makeshlibs) dh_shlibdeps -p$(p_gnatsjlj)
+	echo $(p_gnatsjlj) >> debian/arch_binaries
+endif
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+
+$(build_gnatdoc_stamp): $(build_stamp)
+	mkdir -p html
+	rm -f html/*.info
+	echo -n gnat_ugn gnat_rm gnat-style | xargs -d ' ' -L 1 -P $(USE_CPUS) -I{} \
+	  sh -c 'cd html && \
+	    echo "generating {}-$(GNAT_VERSION).info"; \
+	    makeinfo -I $(srcdir)/gcc/doc/include -I $(srcdir)/gcc/ada \
+		-I $(builddir)/gcc \
+		-o {}-$(GNAT_VERSION).info \
+		$(srcdir)/gcc/ada/{}.texi'
+	touch $@
+
+$(binary_stamp)-ada-doc: $(build_html_stamp) $(build_gnatdoc_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_gnatd)
+	dh_installdirs -p$(p_gnatd) \
+		$(PF)/share/info
+	cp -p html/gnat*info* $(d_gnatd)/$(PF)/share/info/.
+	dh_installdocs -p$(p_gnatd) \
+	    html/gnat_ugn.html html/gnat_rm.html html/gnat-style.html
+	echo $(p_gnatd) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-base.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-base.mk
@@ -0,0 +1,75 @@
+arch_binaries += base
+ifeq ($(with_gcclbase),yes)
+  ifneq ($(with_base_only),yes)
+    indep_binaries += lbase
+  endif
+endif
+
+# ---------------------------------------------------------------------------
+# gcc-base
+
+ifneq (,$(filter $(distrelease),oneiric precise wheezy sid))
+  additional_links =
+else ifneq (,$(filter $(distrelease),))
+  additional_links =
+else
+  additional_links =
+endif
+
+$(binary_stamp)-base: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	rm -rf $(d_base)
+	dh_installdirs -p$(p_base) \
+		$(gcc_lexec_dir)
+
+ifneq ($(DEB_STAGE),rtlibs)
+	ln -sf $(BASE_VERSION) \
+	    $(d_base)/$(subst /$(BASE_VERSION),/$(GCC_VERSION),$(gcc_lib_dir))
+	for link in $(additional_links); do \
+	  ln -sf $(BASE_VERSION) \
+	    $(d_base)/$$(dirname $(gcc_lib_dir))/$$link; \
+        done
+  ifneq ($(gcc_lib_dir),$(gcc_lexec_dir))
+	ln -sf $(BASE_VERSION) \
+	    $(d_base)/$(subst /$(BASE_VERSION),/$(GCC_VERSION),$(gcc_lexec_dir))
+	for link in $(additional_links); do \
+	  ln -sf $(BASE_VERSION) \
+	    $(d_base)/$$(dirname $(gcc_lexec_dir))/$$link; \
+        done
+  endif
+endif
+
+ifeq ($(with_base_only),yes)
+	dh_installdocs -p$(p_base) debian/README.Debian
+else
+	dh_installdocs -p$(p_base) debian/README.Debian.$(DEB_TARGET_ARCH)
+endif
+	rm -f $(d_base)/usr/share/doc/$(p_base)/README.Debian
+	dh_installchangelogs -p$(p_base)
+	dh_compress -p$(p_base)
+	dh_fixperms -p$(p_base)
+ifeq ($(DEB_STAGE)-$(DEB_CROSS),rtlibs-yes)
+	$(cross_gencontrol) dh_gencontrol -p$(p_base) -- -v$(DEB_VERSION) $(common_substvars)
+else
+	dh_gencontrol -p$(p_base) -- -v$(DEB_VERSION) $(common_substvars)
+endif
+	dh_installdeb -p$(p_base)
+	dh_md5sums -p$(p_base)
+	dh_builddeb -p$(p_base)
+	touch $@
+
+$(binary_stamp)-lbase: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	rm -rf $(d_lbase)
+	dh_installdocs -p$(p_lbase) debian/README.Debian
+	rm -f debian/$(p_lbase)/usr/share/doc/$(p_lbase)/README.Debian
+	dh_installchangelogs -p$(p_lbase)
+	dh_compress -p$(p_lbase)
+	dh_fixperms -p$(p_lbase)
+	dh_gencontrol -p$(p_lbase) -- -v$(DEB_VERSION) $(common_substvars)
+	dh_installdeb -p$(p_lbase)
+	dh_md5sums -p$(p_lbase)
+	dh_builddeb -p$(p_lbase)
+	touch $@
--- gcc-6-6.4.0.orig/debian/rules.d/binary-cpp.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-cpp.mk
@@ -0,0 +1,82 @@
+ifneq ($(DEB_STAGE),rtlibs)
+  arch_binaries  := $(arch_binaries) cpp
+  ifneq ($(DEB_CROSS),yes)
+    ifneq ($(GFDL_INVARIANT_FREE),yes)
+      indep_binaries := $(indep_binaries) cpp-doc
+    endif
+  endif
+endif
+
+dirs_cpp = \
+	$(docdir) \
+	$(PF)/share/man/man1 \
+	$(PF)/bin \
+	$(gcc_lexec_dir)
+
+files_cpp = \
+	$(PF)/bin/$(cmd_prefix)cpp$(pkg_ver) \
+	$(gcc_lexec_dir)/cc1
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_cpp += \
+	$(PF)/share/man/man1/$(cmd_prefix)cpp$(pkg_ver).1
+endif
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-cpp: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_cpp)
+	dh_installdirs -p$(p_cpp) $(dirs_cpp)
+	$(dh_compat2) dh_movefiles -p$(p_cpp) $(files_cpp)
+
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)cpp$(pkg_ver) \
+	    $(d_cpp)/$(PF)/bin/cpp$(pkg_ver)
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	ln -sf $(cmd_prefix)cpp$(pkg_ver).1 \
+	    $(d_cpp)/$(PF)/share/man/man1/cpp$(pkg_ver).1
+  endif
+endif
+
+	mkdir -p $(d_cpp)/usr/share/lintian/overrides
+	echo '$(p_cpp) binary: hardening-no-pie' \
+	  > $(d_cpp)/usr/share/lintian/overrides/$(p_cpp)
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	echo '$(p_cpp) binary: binary-without-manpage' \
+	  >> $(d_cpp)/usr/share/lintian/overrides/$(p_cpp)
+endif
+
+	debian/dh_doclink -p$(p_cpp) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_cpp)
+
+	dh_strip -p$(p_cpp) \
+	  $(if $(unstripped_exe),-X/cc1)
+	dh_shlibdeps -p$(p_cpp)
+
+	echo $(p_cpp) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-cpp-doc: $(build_html_stamp) $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_cppd)
+	dh_installdirs -p$(p_cppd) \
+		$(docdir)/$(p_xbase) \
+		$(PF)/share/info
+	$(dh_compat2) dh_movefiles -p$(p_cppd) \
+		$(PF)/share/info/cpp*
+
+	debian/dh_doclink -p$(p_cppd) $(p_xbase)
+	dh_installdocs -p$(p_cppd) html/cpp.html html/cppinternals.html
+	rm -f $(d_cppd)/$(docdir)/$(p_xbase)/copyright
+	debian/dh_rmemptydirs -p$(p_cppd)
+	echo $(p_cppd) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-cxx.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-cxx.mk
@@ -0,0 +1,81 @@
+ifneq ($(DEB_STAGE),rtlibs)
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32) $(biarchhf) $(biarchsf)))
+    arch_binaries  := $(arch_binaries) cxx-multi
+  endif
+  arch_binaries  := $(arch_binaries) cxx
+endif
+
+dirs_cxx = \
+	$(docdir)/$(p_xbase)/C++ \
+	$(PF)/bin \
+	$(PF)/share/info \
+	$(gcc_lexec_dir) \
+	$(PF)/share/man/man1
+files_cxx = \
+	$(PF)/bin/$(cmd_prefix)g++$(pkg_ver) \
+	$(gcc_lexec_dir)/cc1plus
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_cxx += \
+	$(PF)/share/man/man1/$(cmd_prefix)g++$(pkg_ver).1
+endif
+
+p_cxx_m	= g++$(pkg_ver)-multilib$(cross_bin_arch)
+d_cxx_m	= debian/$(p_cxx_m)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-cxx: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_cxx)
+	dh_installdirs -p$(p_cxx) $(dirs_cxx)
+	$(dh_compat2) dh_movefiles -p$(p_cxx) $(files_cxx)
+
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)g++$(pkg_ver) \
+	    $(d_cxx)/$(PF)/bin/g++$(pkg_ver)
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	ln -sf $(cmd_prefix)g++$(pkg_ver).1.gz \
+	    $(d_cxx)/$(PF)/share/man/man1/g++$(pkg_ver).1.gz
+  endif
+endif
+
+	mkdir -p $(d_cxx)/usr/share/lintian/overrides
+	echo '$(p_cxx) binary: hardening-no-pie' \
+	  > $(d_cxx)/usr/share/lintian/overrides/$(p_cxx)
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	echo '$(p_cxx) binary: binary-without-manpage' \
+	  >> $(d_cxx)/usr/share/lintian/overrides/$(p_cxx)
+endif
+
+	debian/dh_doclink -p$(p_cxx) $(p_xbase)
+	cp -p debian/README.C++ $(d_cxx)/$(docdir)/$(p_xbase)/C++/
+	cp -p $(srcdir)/gcc/cp/ChangeLog \
+		$(d_cxx)/$(docdir)/$(p_xbase)/C++/changelog
+	debian/dh_rmemptydirs -p$(p_cxx)
+
+	dh_shlibdeps -p$(p_cxx)
+	dh_strip -p$(p_cxx) $(if $(unstripped_exe),-X/cc1plus)
+	echo $(p_cxx) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+$(binary_stamp)-cxx-multi: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_cxx_m)
+	dh_installdirs -p$(p_cxx_m) \
+		$(docdir)
+
+	debian/dh_doclink -p$(p_cxx_m) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_cxx_m)
+
+	dh_strip -p$(p_cxx_m)
+	dh_shlibdeps -p$(p_cxx_m)
+	echo $(p_cxx_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-d.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-d.mk
@@ -0,0 +1,269 @@
+ifneq ($(DEB_STAGE),rtlibs)
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32) $(biarchsf)))
+    arch_binaries  := $(arch_binaries) gdc-multi
+  endif
+  arch_binaries := $(arch_binaries) gdc
+
+  ifeq ($(with_libphobos),yes)
+    $(lib_binaries) += libphobos-dev
+    $(lib_binaries) += libphobos
+  endif
+
+  ifeq ($(with_lib64phobosdev),yes)
+    $(lib_binaries)	+= lib64phobos-dev
+  endif
+  ifeq ($(with_lib32phobosdev),yes)
+    $(lib_binaries)	+= lib32phobos-dev
+  endif
+  ifeq ($(with_libn32phobosdev),yes)
+    $(lib_binaries)	+= libn32phobos-dev
+  endif
+  ifeq ($(with_libx32phobosdev),yes)
+    $(lib_binaries)	+= libx32phobos-dev
+  endif
+  ifeq ($(with_libhfphobosdev),yes)
+    $(lib_binaries)	+= libhfphobos-dev
+  endif
+  ifeq ($(with_libsfphobosdev),yes)
+    $(lib_binaries)	+= libsfphobos-dev
+  endif
+
+  ifeq ($(with_lib64phobos),yes)
+    $(lib_binaries)	+= lib64phobos
+  endif
+  ifeq ($(with_lib32phobos),yes)
+    $(lib_binaries)	+= lib32phobos
+  endif
+  ifeq ($(with_libn32phobos),yes)
+    $(lib_binaries)	+= libn32phobos
+  endif
+  ifeq ($(with_libx32phobos),yes)
+    $(lib_binaries)	+= libx32phobos
+  endif
+  ifeq ($(with_libhfphobos),yes)
+    $(lib_binaries)	+= libhfphobos
+  endif
+  ifeq ($(with_libsfphobos),yes)
+    $(lib_binaries)	+= libsfphobos
+  endif
+endif
+
+p_gdc           = gdc$(pkg_ver)$(cross_bin_arch)
+p_gdc_m		= gdc$(pkg_ver)-multilib$(cross_bin_arch)
+p_libphobos     = libgphobos$(GPHOBOS_SONAME)
+p_libphobosdev  = libgphobos$(pkg_ver)-dev
+
+d_gdc           = debian/$(p_gdc)
+d_gdc_m		= debian/$(p_gdc_m)
+d_libphobos     = debian/$(p_libphobos)
+d_libphobosdev  = debian/$(p_libphobosdev)
+
+ifeq ($(DEB_CROSS),yes)
+  gdc_include_dir := $(gcc_lib_dir)/include/d
+else
+  gdc_include_dir := $(PF)/include/d/$(BASE_VERSION)
+endif
+# FIXME: always here?
+gdc_include_dir := $(gcc_lib_dir)/include/d
+
+dirs_gdc = \
+	$(PF)/bin \
+	$(PF)/share/man/man1 \
+	$(gcc_lexec_dir)
+ifneq ($(DEB_CROSS),yes)
+  dirs_gdc += \
+	$(gdc_include_dir)
+endif
+
+files_gdc = \
+	$(PF)/bin/$(cmd_prefix)gdc$(pkg_ver) \
+	$(gcc_lexec_dir)/cc1d
+ifneq ($(GFDL_INVARIANT_FREE),yes-now-pure-gfdl)
+    files_gdc += \
+	$(PF)/share/man/man1/$(cmd_prefix)gdc$(pkg_ver).1
+endif
+
+dirs_libphobos = \
+	$(PF)/lib \
+	$(gdc_include_dir) \
+	$(gcc_lib_dir)
+
+$(binary_stamp)-gdc: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_gdc)
+	dh_installdirs -p$(p_gdc) $(dirs_gdc)
+
+	dh_installdocs -p$(p_gdc) src/gcc/d/README
+	dh_installchangelogs -p$(p_gdc) src/gcc/d/ChangeLog
+
+	$(dh_compat2) dh_movefiles -p$(p_gdc) -X/zlib/ $(files_gdc)
+
+ifeq ($(with_libphobos),yes)
+	mv $(d)/$(usr_lib)/libgphobos.spec $(d_gdc)/$(gcc_lib_dir)/
+endif
+
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)gdc$(pkg_ver) \
+	    $(d_gdc)/$(PF)/bin/gdc$(pkg_ver)
+  ifneq ($(GFDL_INVARIANT_FREE),yes-now-pure-gfdl)
+	ln -sf $(cmd_prefix)gdc$(pkg_ver).1 \
+	    $(d_gdc)/$(PF)/share/man/man1/gdc$(pkg_ver).1
+  endif
+endif
+
+# FIXME: __entrypoint.di needs to go into a libgdc-dev Multi-Arch: same package
+	# Always needed by gdc.
+	mkdir -p $(d_gdc)/$(gdc_include_dir)
+	cp $(srcdir)/libphobos/libdruntime/__entrypoint.di \
+	    $(d_gdc)/$(gdc_include_dir)/.
+#ifneq ($(DEB_CROSS),yes)
+#	dh_link -p$(p_gdc) \
+#		/$(gdc_include_dir) \
+#		/$(dir $(gdc_include_dir))/$(GCC_VERSION)
+#endif
+
+	dh_link -p$(p_gdc) \
+		/$(docdir)/$(p_gcc)/README.Bugs \
+		/$(docdir)/$(p_gdc)/README.Bugs
+
+	dh_strip -p$(p_gdc) \
+	  $(if $(unstripped_exe),-X/cc1d)
+	dh_shlibdeps -p$(p_gdc)
+
+	mkdir -p $(d_gdc)/usr/share/lintian/overrides
+	echo '$(p_gdc) binary: hardening-no-pie' \
+	  > $(d_gdc)/usr/share/lintian/overrides/$(p_gdc)
+
+	echo $(p_gdc) >> debian/arch_binaries
+
+	find $(d_gdc) -type d -empty -delete
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+$(binary_stamp)-gdc-multi: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_gdc_m)
+	dh_installdirs -p$(p_gdc_m) $(docdir)
+
+	debian/dh_doclink -p$(p_gdc_m) $(p_xbase)
+
+	dh_strip -p$(p_gdc_m)
+	dh_shlibdeps -p$(p_gdc_m)
+	echo $(p_gdc_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+define __do_libphobos
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) \
+		$(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(usr_lib$(2))/libgphobos.so.* \
+		$(usr_lib$(2))/libgdruntime.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libgphobos.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l) \
+		-- -a$(call mlib_to_arch,$(2)) || echo XXXXXXXXXXX ERROR $(p_l)
+	rm -f debian/$(p_l).symbols
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst gphobos$(GPHOBOS_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	dh_lintian -p$(p_l)
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+define __do_libphobos_dev
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l)
+	dh_installdirs -p$(p_l) \
+		$(gcc_lib_dir$(2))
+
+	$(call install_gcc_lib,libgdruntime,$(GDRUNTIME_SONAME),$(2),$(p_l))
+	$(call install_gcc_lib,libgphobos,$(GPHOBOS_SONAME),$(2),$(p_l))
+
+	$(if $(2),,
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(gdc_include_dir)
+	)
+
+	: # included in gdc package
+	rm -f $(d_l)/$(gdc_include_dir)/__entrypoint.di
+
+	debian/dh_doclink -p$(p_l) \
+		$(if $(filter yes,$(with_separate_gdc)),$(p_gdc),$(p_lbase))
+	echo $(p_l) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# don't put this as a comment within define/endef
+#	$(call install_gcc_lib,libphobos,$(PHOBOS_SONAME),$(2),$(p_l))
+
+do_libphobos = $(call __do_libphobos,lib$(1)gphobos$(GPHOBOS_SONAME),$(1))
+do_libphobos_dev = $(call __do_libphobos_dev,lib$(1)gphobos-$(BASE_VERSION)-dev,$(1))
+
+$(binary_stamp)-libphobos: $(install_stamp)
+	$(call do_libphobos,)
+
+$(binary_stamp)-lib64phobos: $(install_stamp)
+	$(call do_libphobos,64)
+
+$(binary_stamp)-lib32phobos: $(install_stamp)
+	$(call do_libphobos,32)
+
+$(binary_stamp)-libn32phobos: $(install_stamp)
+	$(call do_libphobos,n32)
+
+$(binary_stamp)-libx32phobos: $(install_stamp)
+	$(call do_libphobos,x32)
+
+$(binary_stamp)-libhfphobos: $(install_stamp)
+	$(call do_libphobos,hf)
+
+$(binary_stamp)-libsfphobos: $(install_stamp)
+	$(call do_libphobos,sf)
+
+
+$(binary_stamp)-libphobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,)
+
+$(binary_stamp)-lib64phobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,64)
+
+$(binary_stamp)-lib32phobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,32)
+
+$(binary_stamp)-libx32phobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,x32)
+
+$(binary_stamp)-libn32phobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,n32)
+
+$(binary_stamp)-libhfphobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,hf)
+
+$(binary_stamp)-libsfphobos-dev: $(install_stamp)
+	$(call do_libphobos_dev,sf)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-fixincl.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-fixincl.mk
@@ -0,0 +1,42 @@
+arch_binaries  := $(arch_binaries) fixincl
+
+p_fix	= fixincludes
+d_fix	= debian/$(p_fix)
+
+dirs_fix = \
+	$(docdir)/$(p_xbase)/fixincludes \
+	$(PF)/share/man/man1 \
+	$(PF)/bin \
+	$(gcc_lexec_dir) \
+	$(gcc_lib_dir)
+files_fix = \
+	$(gcc_lexec_dir)/install-tools \
+	$(gcc_lib_dir)/install-tools
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-fixincl: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_fix)
+	dh_installdirs -p$(p_fix) $(dirs_fix)
+	$(dh_compat2) dh_movefiles -p$(p_fix) $(files_fix)
+
+#	$(IP) $(builddir)/gcc/fixinc/fixincl $(d_fix)/$(PF)/lib/fixincludes/
+#	sed -e "s,^FIXINCL=\(.*\),FIXINCL=/$(PF)/lib/fixincludes/fixincl," \
+#	    $(builddir)/gcc/fixinc.sh \
+#		> $(d_fix)/$(PF)/lib/fixincludes/fixinc.sh
+#	chmod 755 $(d_fix)/$(PF)/lib/fixincludes/fixinc.sh
+	$(IR) $(srcdir)/fixincludes/README \
+	    $(d_fix)/$(docdir)/$(p_xbase)/fixincludes
+	sed -e 's,@LIBEXECDIR@,$(gcc_lexec_dir),g' debian/fixincludes.in \
+	    > $(d_fix)/$(PF)/bin/fixincludes
+	chmod 755 $(d_fix)/$(PF)/bin/fixincludes
+
+	debian/dh_doclink -p$(p_fix) $(p_xbase)
+	dh_strip -p$(p_fix)
+	dh_shlibdeps -p$(p_fix)
+	echo $(p_fix) >> debian/arch_binaries.epoch
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-fortran.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-fortran.mk
@@ -0,0 +1,269 @@
+ifeq ($(with_libgfortran),yes)
+  $(lib_binaries) += libgfortran
+endif
+ifeq ($(with_fdev),yes)
+  $(lib_binaries) += libgfortran-dev
+endif
+ifeq ($(with_lib64gfortran),yes)
+  $(lib_binaries) += lib64fortran
+endif
+ifeq ($(with_lib64gfortrandev),yes)
+  $(lib_binaries) += lib64gfortran-dev
+endif
+ifeq ($(with_lib32gfortran),yes)
+  $(lib_binaries) += lib32fortran
+endif
+ifeq ($(with_lib32gfortrandev),yes)
+  $(lib_binaries) += lib32gfortran-dev
+endif
+ifeq ($(with_libn32gfortran),yes)
+  $(lib_binaries) += libn32fortran
+endif
+ifeq ($(with_libn32gfortrandev),yes)
+  $(lib_binaries) += libn32gfortran-dev
+endif
+ifeq ($(with_libx32gfortran),yes)
+  $(lib_binaries) += libx32fortran
+endif
+ifeq ($(with_libx32gfortrandev),yes)
+  $(lib_binaries) += libx32gfortran-dev
+endif
+ifeq ($(with_libhfgfortran),yes)
+  $(lib_binaries) += libhffortran
+endif
+ifeq ($(with_libhfgfortrandev),yes)
+  $(lib_binaries) += libhfgfortran-dev
+endif
+ifeq ($(with_libsfgfortran),yes)
+  $(lib_binaries) += libsffortran
+endif
+ifeq ($(with_libsfgfortrandev),yes)
+  $(lib_binaries) += libsfgfortran-dev
+endif
+
+ifeq ($(with_fdev),yes)
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32) $(biarchhf) $(biarchsf)))
+    arch_binaries  := $(arch_binaries) fdev-multi
+  endif
+  arch_binaries  := $(arch_binaries) fdev
+  ifneq ($(DEB_CROSS),yes)
+    ifneq ($(GFDL_INVARIANT_FREE),yes)
+      indep_binaries := $(indep_binaries) fortran-doc
+    endif
+  endif
+endif
+
+p_g95	= gfortran$(pkg_ver)$(cross_bin_arch)
+p_g95_m	= gfortran$(pkg_ver)-multilib$(cross_bin_arch)
+p_g95d	= gfortran$(pkg_ver)-doc
+p_flib	= libgfortran$(FORTRAN_SONAME)$(cross_lib_arch)
+
+d_g95	= debian/$(p_g95)
+d_g95_m	= debian/$(p_g95_m)
+d_g95d	= debian/$(p_g95d)
+
+dirs_g95 = \
+	$(docdir)/$(p_xbase)/fortran \
+	$(PF)/bin \
+	$(gcc_lexec_dir) \
+	$(gcc_lib_dir) \
+	$(PF)/include \
+	$(PF)/share/man/man1
+files_g95 = \
+	$(PF)/bin/$(cmd_prefix)gfortran$(pkg_ver) \
+	$(gcc_lib_dir)/finclude \
+	$(gcc_lexec_dir)/f951 
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_g95 += \
+	$(PF)/share/man/man1/$(cmd_prefix)gfortran$(pkg_ver).1
+endif
+
+# ----------------------------------------------------------------------
+define __do_fortran
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libgfortran.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libgfortran.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst gfortran$(FORTRAN_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst gfortran$(FORTRAN_SONAME),gcc$(QUADMATH_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+do_fortran = $(call __do_fortran,lib$(1)gfortran$(FORTRAN_SONAME),$(1))
+
+
+define __do_libgfortran_dev
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l)
+	dh_installdirs -p$(p_l) $(gcc_lib_dir$(2))
+
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(gcc_lib_dir$(2))/libcaf_single.a
+	$(call install_gcc_lib,libgfortran,$(FORTRAN_SONAME),$(2),$(p_l))
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_rmemptydirs -p$(p_l)
+
+	dh_strip -p$(p_l)
+	$(cross_shlibdeps) dh_shlibdeps -p$(p_l)
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+# ----------------------------------------------------------------------
+
+do_libgfortran_dev = $(call __do_libgfortran_dev,lib$(1)gfortran-$(BASE_VERSION)-dev,$(1))
+
+$(binary_stamp)-libgfortran: $(install_stamp)
+	$(call do_fortran,)
+
+$(binary_stamp)-lib64fortran: $(install_stamp)
+	$(call do_fortran,64)
+
+$(binary_stamp)-lib32fortran: $(install_stamp)
+	$(call do_fortran,32)
+
+$(binary_stamp)-libn32fortran: $(install_stamp)
+	$(call do_fortran,n32)
+
+$(binary_stamp)-libx32fortran: $(install_stamp)
+	$(call do_fortran,x32)
+
+$(binary_stamp)-libhffortran: $(install_stamp)
+	$(call do_fortran,hf)
+
+$(binary_stamp)-libsffortran: $(install_stamp)
+	$(call do_fortran,sf)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-fdev: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_g95)
+	dh_installdirs -p$(p_g95) $(dirs_g95)
+
+	$(dh_compat2) dh_movefiles -p$(p_g95) $(files_g95)
+
+	mv $(d)/$(usr_lib)/libgfortran.spec $(d_g95)/$(gcc_lib_dir)/
+
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)gfortran$(pkg_ver) \
+	    $(d_g95)/$(PF)/bin/gfortran$(pkg_ver)
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	ln -sf $(cmd_prefix)gfortran$(pkg_ver).1 \
+	    $(d_g95)/$(PF)/share/man/man1/gfortran$(pkg_ver).1
+  endif
+endif
+
+	mkdir -p $(d_g95)/usr/share/lintian/overrides
+	echo '$(p_g95) binary: hardening-no-pie' \
+	  > $(d_g95)/usr/share/lintian/overrides/$(p_g95)
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	echo '$(p_g95) binary: binary-without-manpage' \
+	  >> $(d_g95)/usr/share/lintian/overrides/$(p_g95)
+endif
+
+	debian/dh_doclink -p$(p_g95) $(p_xbase)
+
+	cp -p $(srcdir)/gcc/fortran/ChangeLog \
+		$(d_g95)/$(docdir)/$(p_xbase)/fortran/changelog
+	debian/dh_rmemptydirs -p$(p_g95)
+
+	dh_strip -p$(p_g95) \
+	  $(if $(unstripped_exe),-X/f951)
+	dh_shlibdeps -p$(p_g95)
+	echo $(p_g95) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-fdev-multi: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_g95_m)
+	dh_installdirs -p$(p_g95_m) $(docdir)
+
+	debian/dh_doclink -p$(p_g95_m) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_g95_m)
+	dh_strip -p$(p_g95_m)
+	dh_shlibdeps -p$(p_g95_m)
+	echo $(p_g95_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-fortran-doc: $(build_html_stamp) $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_g95d)
+	dh_installdirs -p$(p_g95d) \
+		$(docdir)/$(p_xbase)/fortran \
+		$(PF)/share/info
+	$(dh_compat2) dh_movefiles -p$(p_g95d) \
+		$(PF)/share/info/gfortran*
+
+	debian/dh_doclink -p$(p_g95d) $(p_xbase)
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+	dh_installdocs -p$(p_g95d)
+	rm -f $(d_g95d)/$(docdir)/$(p_xbase)/copyright
+	cp -p html/gfortran.html $(d_g95d)/$(docdir)/$(p_xbase)/fortran/
+endif
+	echo $(p_g95d) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+$(binary_stamp)-libgfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,)
+
+$(binary_stamp)-lib64gfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,64)
+
+$(binary_stamp)-lib32gfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,32)
+
+$(binary_stamp)-libn32gfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,n32)
+
+$(binary_stamp)-libx32gfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,x32)
+
+$(binary_stamp)-libhfgfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,hf)
+
+$(binary_stamp)-libsfgfortran-dev: $(install_stamp)
+	$(call do_libgfortran_dev,sf)
+
--- gcc-6-6.4.0.orig/debian/rules.d/binary-gcc.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-gcc.mk
@@ -0,0 +1,368 @@
+ifneq ($(DEB_STAGE),rtlibs)
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32) $(biarchhf) $(biarchsf)))
+    arch_binaries  := $(arch_binaries) gcc-multi
+  endif
+  ifeq ($(with_plugins),yes)
+    arch_binaries  := $(arch_binaries) gcc-plugindev
+  endif
+
+  arch_binaries  := $(arch_binaries) gcc
+
+  ifneq ($(DEB_CROSS),yes)
+    ifneq ($(GFDL_INVARIANT_FREE),yes)
+      indep_binaries := $(indep_binaries) gcc-doc
+    endif
+    ifeq ($(with_nls),yes)
+      indep_binaries := $(indep_binaries) gcc-locales
+    endif
+  endif
+
+  ifeq ($(build_type),build-native)
+    arch_binaries  := $(arch_binaries) testresults
+  endif
+endif
+
+# gcc must be moved after g77 and g++
+# not all files $(PF)/include/*.h are part of gcc,
+# but it becomes difficult to name all these files ...
+
+dirs_gcc = \
+	$(docdir)/$(p_xbase)/{gcc,libssp,gomp,itm,quadmath,sanitizer,cilkrts,mpx} \
+	$(PF)/bin \
+	$(gcc_lexec_dir) \
+	$(gcc_lib_dir)/{include,include-fixed} \
+	$(PF)/share/man/man1 $(libgcc_dir)
+
+# XXX: what about triarch mapping?
+files_gcc = \
+	$(PF)/bin/$(cmd_prefix){gcc,gcov,gcov-tool,gcov-dump}$(pkg_ver) \
+	$(PF)/bin/$(cmd_prefix)gcc-{ar,ranlib,nm}$(pkg_ver) \
+	$(PF)/share/man/man1/$(cmd_prefix)gcc-{ar,nm,ranlib}$(pkg_ver).1 \
+	$(gcc_lexec_dir)/{collect2,lto1,lto-wrapper} \
+	$(shell test -e $(d)/$(gcc_lib_dir)/SYSCALLS.c.X \
+		&& echo $(gcc_lib_dir)/SYSCALLS.c.X)
+
+ifeq ($(with_libcc1_plugin),yes)
+    files_gcc += \
+	$(gcc_lib_dir)/plugin/libcc1plugin.so{,.0,.0.0.0}
+endif
+
+files_gcc += \
+	$(gcc_lexec_dir)/liblto_plugin.so{,.0,.0.0.0}
+
+ifeq ($(DEB_STAGE),stage1)
+    files_gcc += \
+	$(gcc_lib_dir)/include \
+	$(shell for h in \
+		  README limits.h syslimits.h; \
+		do \
+		  test -e $(d)/$(gcc_lib_dir)/include-fixed/$$h \
+		    && echo $(gcc_lib_dir)/include-fixed/$$h; \
+		done)
+endif
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+    files_gcc += \
+	$(PF)/share/man/man1/$(cmd_prefix){gcc,gcov}$(pkg_ver).1 \
+	$(PF)/share/man/man1/$(cmd_prefix)gcov-{dump,tool}$(pkg_ver).1
+endif
+
+usr_doc_files = debian/README.Bugs \
+	$(shell test -f $(srcdir)/FAQ && echo $(srcdir)/FAQ)
+
+p_loc	= gcc$(pkg_ver)-locales
+d_loc	= debian/$(p_loc)
+
+p_gcc_m	= gcc$(pkg_ver)-multilib$(cross_bin_arch)
+d_gcc_m	= debian/$(p_gcc_m)
+
+p_pld	= gcc$(pkg_ver)-plugin-dev$(cross_bin_arch)
+d_pld	= debian/$(p_pld)
+
+p_tst	= gcc$(pkg_ver)-test-results
+d_tst	= debian/$(p_tst)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcc: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_gcc)
+	dh_installdirs -p$(p_gcc) $(dirs_gcc)
+
+ifeq ($(with_linaro_branch),yes)
+	if [ -f $(srcdir)/gcc/ChangeLog.linaro ]; then \
+	  cp -p $(srcdir)/gcc/ChangeLog.linaro \
+		$(d_gcc)/$(docdir)/$(p_xbase)/changelog.linaro; \
+	fi
+endif
+ifeq ($(with_libssp),yes)
+	cp -p $(srcdir)/libssp/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/libssp/changelog
+endif
+ifeq ($(with_gomp),yes)
+	mv $(d)/$(usr_lib)/libgomp*.spec $(d_gcc)/$(gcc_lib_dir)/
+	cp -p $(srcdir)/libgomp/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/gomp/changelog
+endif
+ifeq ($(with_itm),yes)
+	mv $(d)/$(usr_lib)/libitm*.spec $(d_gcc)/$(gcc_lib_dir)/
+	cp -p $(srcdir)/libitm/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/itm/changelog
+endif
+ifeq ($(with_qmath),yes)
+	cp -p $(srcdir)/libquadmath/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/quadmath/changelog
+endif
+ifeq ($(with_asan),yes)
+	mv $(d)/$(usr_lib)/libsanitizer*.spec $(d_gcc)/$(gcc_lib_dir)/
+	cp -p $(srcdir)/libsanitizer/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/sanitizer/changelog
+endif
+ifeq ($(with_cilkrts),yes)
+	mv $(d)/$(usr_lib)/libcilkrts.spec $(d_gcc)/$(gcc_lib_dir)/
+	cp -p $(srcdir)/libcilkrts/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/cilkrts/changelog
+endif
+ifeq ($(with_mpx),yes)
+	mv $(d)/$(usr_lib)/libmpx.spec $(d_gcc)/$(gcc_lib_dir)/
+	cp -p $(srcdir)/libmpx/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/mpx/changelog
+endif
+ifeq ($(with_cc1),yes)
+	rm -f $(d)/$(PF)/lib/$(DEB_HOST_MULTIARCH)/libcc1.so
+	dh_link -p$(p_gcc) \
+	    /$(PF)/lib/$(DEB_HOST_MULTIARCH)/libcc1.so.$(CC1_SONAME) \
+	    /$(gcc_lib_dir)/libcc1.so
+endif
+
+	$(dh_compat2) dh_movefiles -p$(p_gcc) $(files_gcc)
+
+ifeq ($(unprefixed_names),yes)
+	for i in gcc gcov gcov-dump gcov-tool gcc-ar gcc-nm gcc-ranlib; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_gcc)/$(PF)/bin/$$i$(pkg_ver); \
+	done
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	for i in gcc gcov gcov-dump gcov-tool; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver).1.gz \
+	    $(d_gcc)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+  endif
+	for i in gcc-ar gcc-nm gcc-ranlib; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver).1.gz \
+	    $(d_gcc)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+endif
+
+#	dh_installdebconf
+	debian/dh_doclink -p$(p_gcc) $(p_xbase)
+	cp -p $(usr_doc_files) $(d_gcc)/$(docdir)/$(p_xbase)/.
+	cp -p debian/README.ssp $(d_gcc)/$(docdir)/$(p_xbase)/
+	cp -p debian/NEWS.gcc $(d_gcc)/$(docdir)/$(p_xbase)/NEWS
+	cp -p debian/NEWS.html $(d_gcc)/$(docdir)/$(p_xbase)/NEWS.html
+	cp -p $(srcdir)/ChangeLog $(d_gcc)/$(docdir)/$(p_xbase)/changelog
+	cp -p $(srcdir)/gcc/ChangeLog \
+		$(d_gcc)/$(docdir)/$(p_xbase)/gcc/changelog
+	if [ -f $(builddir)/gcc/.bad_compare ]; then \
+	  ( \
+	    echo "The comparision of the stage2 and stage3 object files shows differences."; \
+	    echo "The Debian package was modified to ignore these differences."; \
+	    echo ""; \
+	    echo "The following files differ:"; \
+	    echo ""; \
+	    cat $(builddir)/gcc/.bad_compare; \
+	  ) > $(d_gcc)/$(docdir)/$(p_xbase)/BOOTSTRAP_COMPARISION_FAILURE; \
+	else \
+	  true; \
+	fi
+
+	mkdir -p $(d_gcc)/usr/share/lintian/overrides
+	echo '$(p_gcc) binary: hardening-no-pie' \
+	  > $(d_gcc)/usr/share/lintian/overrides/$(p_gcc)
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	echo '$(p_gcc) binary: binary-without-manpage' \
+	  >> $(d_gcc)/usr/share/lintian/overrides/$(p_gcc)
+endif
+
+	debian/dh_rmemptydirs -p$(p_gcc)
+	dh_strip -p$(p_gcc) \
+	  $(if $(unstripped_exe),-X/lto1)
+	dh_shlibdeps -p$(p_gcc)
+	echo $(p_gcc) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+
+$(binary_stamp)-gcc-multi: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_gcc_m)
+	dh_installdirs -p$(p_gcc_m) $(docdir)
+
+	debian/dh_doclink -p$(p_gcc_m) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_gcc_m)
+
+	dh_strip -p$(p_gcc_m)
+	dh_shlibdeps -p$(p_gcc_m)
+	echo $(p_gcc_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcc-plugindev: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_pld)
+	dh_installdirs -p$(p_pld) \
+		$(docdir) \
+		$(gcc_lib_dir)/plugin
+	$(dh_compat2) dh_movefiles -p$(p_pld) \
+		$(gcc_lib_dir)/plugin/include \
+		$(gcc_lib_dir)/plugin/gtype.state \
+		$(gcc_lexec_dir)/plugin/gengtype
+
+	debian/dh_doclink -p$(p_pld) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_pld)
+	dh_strip -p$(p_pld)
+	dh_shlibdeps -p$(p_pld)
+	mkdir -p $(d_pld)/usr/share/lintian/overrides
+	echo '$(p_pld) binary: hardening-no-pie' \
+	  > $(d_pld)/usr/share/lintian/overrides/$(p_pld)
+	echo $(p_pld) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcc-locales: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_loc)
+	dh_installdirs -p$(p_loc) \
+		$(docdir)
+	$(dh_compat2) dh_movefiles -p$(p_loc) \
+		$(PF)/share/locale/*/*/cpplib*.* \
+		$(PF)/share/locale/*/*/gcc*.*
+
+	debian/dh_doclink -p$(p_loc) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_loc)
+	echo $(p_loc) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+
+# ----------------------------------------------------------------------
+
+$(binary_stamp)-testresults: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_tst)
+	dh_installdirs -p$(p_tst) $(docdir)
+
+	debian/dh_doclink -p$(p_tst) $(p_xbase)
+
+	mkdir -p $(d_tst)/$(docdir)/$(p_xbase)/test
+	echo "TEST COMPARE BEGIN"
+ifeq ($(with_check),yes)
+	for i in test-summary testsuite-comparision; do \
+	  [ -f $$i ] || continue; \
+	  cp -p $$i $(d_tst)/$(docdir)/$(p_xbase)/$$i; \
+	done
+# more than one libgo.sum, avoid it
+	cp -p $$(find $(builddir)/gcc/testsuite -maxdepth 2 \( -name '*.sum' -o -name '*.log' \)) \
+	      $$(find $(buildlibdir)/*/testsuite -maxdepth 1 \( -name '*.sum'  -o -name '*.log' \) ! -name 'libgo.*') \
+		$(d_tst)/$(docdir)/$(p_xbase)/test/
+  ifeq ($(with_go),yes)
+	cp -p $(buildlibdir)/libgo/libgo.sum \
+		$(d_tst)/$(docdir)/$(p_xbase)/test/
+  endif
+  ifeq (0,1)
+	cd $(builddir); \
+	for i in $(CURDIR)/$(d_tst)/$(docdir)/$(p_xbase)/test/*.sum; do \
+	  b=$$(basename $$i); \
+	  if [ -f /usr/share/doc/$(p_xbase)/test/$$b.gz ]; then \
+	    zcat /usr/share/doc/$(p_xbase)/test/$$b.gz > /tmp/$$b; \
+	    if sh $(srcdir)/contrib/test_summary /tmp/$$b $$i; then \
+	      echo "$$b: OK"; \
+	    else \
+	      echo "$$b: FAILURES"; \
+	    fi; \
+	    rm -f /tmp/$$b; \
+	  else \
+	    echo "Test summary for $$b is not available"; \
+	  fi; \
+	done
+  endif
+	if which xz 2>&1 >/dev/null; then \
+	  echo -n $(d_tst)/$(docdir)/$(p_xbase)/test/* \
+	    | xargs -d ' ' -L 1 -P $(USE_CPUS)	xz -7v; \
+	fi
+else
+	echo "Nothing to compare (testsuite not run)"
+	echo 'Test run disabled, reason: $(with_check)' \
+	  > $(d_tst)/$(docdir)/$(p_xbase)/test-run-disabled
+endif
+	echo "TEST COMPARE END"
+
+	debian/dh_rmemptydirs -p$(p_tst)
+
+	echo $(p_tst) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcc-doc: $(build_html_stamp) $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_doc)
+	dh_installdirs -p$(p_doc) \
+		$(docdir)/$(p_xbase) \
+		$(PF)/share/info
+	$(dh_compat2) dh_movefiles -p$(p_doc) \
+		$(PF)/share/info/cpp{,internals}-* \
+		$(PF)/share/info/gcc{,int}-* \
+		$(PF)/share/info/lib{gomp,itm}-* \
+		$(if $(with_qmath),$(PF)/share/info/libquadmath-*)
+	rm -f $(d_doc)/$(PF)/share/info/gccinst*
+
+ifeq ($(with_gomp),yes)
+	$(MAKE) -C $(buildlibdir)/libgomp stamp-build-info
+	cp -p $(buildlibdir)/libgomp/$(cmd_prefix)libgomp$(pkg_ver).info \
+		$(d_doc)/$(PF)/share/info/libgomp$(pkg_ver).info
+endif
+ifeq ($(with_itm),yes)
+	-$(MAKE) -C $(buildlibdir)/libitm stamp-build-info
+	if [ -f $(buildlibdir)/libitm/libitm$(pkg_ver).info ]; then \
+	  cp -p $(buildlibdir)/libitm/$(cmd_prefix)libitm$(pkg_ver).info \
+		$(d_doc)/$(PF)/share/info/; \
+	fi
+endif
+
+	debian/dh_doclink -p$(p_doc) $(p_xbase)
+	dh_installdocs -p$(p_doc) html/gcc.html html/gccint.html
+ifeq ($(with_gomp),yes)
+	cp -p html/libgomp.html $(d_doc)/usr/share/doc/$(p_doc)/
+endif
+ifeq ($(with_itm),yes)
+	cp -p html/libitm.html $(d_doc)/usr/share/doc/$(p_doc)/
+endif
+ifeq ($(with_qmath),yes)
+	cp -p html/libquadmath.html $(d_doc)/usr/share/doc/$(p_doc)/
+endif
+	rm -f $(d_doc)/$(docdir)/$(p_xbase)/copyright
+	debian/dh_rmemptydirs -p$(p_doc)
+	echo $(p_doc) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-go.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-go.mk
@@ -0,0 +1,332 @@
+ifeq ($(with_libgo),yes)
+  $(lib_binaries) += libgo
+endif
+ifeq ($(with_lib64go),yes)
+  $(lib_binaries) += lib64go
+endif
+ifeq ($(with_lib32go),yes)
+  $(lib_binaries) += lib32go
+endif
+ifeq ($(with_libn32go),yes)
+  $(lib_binaries) += libn32go
+endif
+ifeq ($(with_libx32go),yes)
+  $(lib_binaries) += libx32go
+endif
+
+ifneq ($(DEB_STAGE),rtlibs)
+  arch_binaries  := $(arch_binaries) gccgo
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32)))
+    arch_binaries  := $(arch_binaries) gccgo-multi
+  endif
+  ifneq ($(DEB_CROSS),yes)
+    ifneq ($(GFDL_INVARIANT_FREE),yes)
+      indep_binaries := $(indep_binaries) go-doc
+    endif
+  endif
+endif
+
+p_go	= gccgo$(pkg_ver)$(cross_bin_arch)
+p_go_m	= gccgo$(pkg_ver)-multilib$(cross_bin_arch)
+p_god	= gccgo$(pkg_ver)-doc
+p_golib	= libgo$(GO_SONAME)$(cross_lib_arch)
+
+d_go	= debian/$(p_go)
+d_go_m	= debian/$(p_go_m)
+d_god	= debian/$(p_god)
+d_golib	= debian/$(p_golib)
+
+dirs_go = \
+	$(docdir)/$(p_xbase)/go \
+	$(PF)/bin \
+	$(gcc_lexec_dir) \
+	$(gcc_lib_dir) \
+	$(PF)/include \
+	$(PF)/share/man/man1
+files_go = \
+	$(PF)/bin/$(cmd_prefix)gccgo$(pkg_ver) \
+	$(gcc_lexec_dir)/go1
+
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+  files_go += \
+	$(PF)/bin/$(cmd_prefix){go,gofmt}$(pkg_ver) \
+	$(gcc_lexec_dir)/cgo \
+	$(PF)/share/man/man1/$(cmd_prefix){go,gofmt}$(pkg_ver).1
+endif
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_go += \
+	$(PF)/share/man/man1/$(cmd_prefix)gccgo$(pkg_ver).1
+endif
+
+ifeq ($(with_standalone_go),yes)
+
+  dirs_go += \
+	$(gcc_lib_dir)/include \
+	$(PF)/share/man/man1
+
+# XXX: what about triarch mapping?
+  files_go += \
+	$(PF)/bin/$(cmd_prefix){cpp,gcc,gcov,gcov-tool}$(pkg_ver) \
+	$(PF)/bin/$(cmd_prefix)gcc-{ar,ranlib,nm}$(pkg_ver) \
+	$(PF)/share/man/man1/$(cmd_prefix)gcc-{ar,nm,ranlib}$(pkg_ver).1 \
+	$(gcc_lexec_dir)/{cc1,collect2,lto1,lto-wrapper} \
+	$(gcc_lexec_dir)/liblto_plugin.so{,.0,.0.0.0} \
+	$(gcc_lib_dir)/{libgcc*,libgcov.a,*.o} \
+	$(header_files) \
+	$(shell test -e $(d)/$(gcc_lib_dir)/SYSCALLS.c.X \
+		&& echo $(gcc_lib_dir)/SYSCALLS.c.X)
+
+  ifeq ($(with_cc1),yes)
+    files_go += \
+	$(gcc_lib_dir)/plugin/libcc1plugin.so{,.0,.0.0.0}
+  endif
+
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+    files_go += \
+	$(PF)/share/man/man1/$(cmd_prefix){cpp,gcc,gcov,gcov-tool}$(pkg_ver).1
+  endif
+
+  ifeq ($(biarch64),yes)
+    files_go += $(gcc_lib_dir)/$(biarch64subdir)/{libgcc*,libgcov.a,*.o}
+  endif
+  ifeq ($(biarch32),yes)
+    files_go += $(gcc_lib_dir)/$(biarch32subdir)/{libgcc*,*.o}
+  endif
+  ifeq ($(biarchn32),yes)
+    files_go += $(gcc_lib_dir)/$(biarchn32subdir)/{libgcc*,libgcov.a,*.o}
+  endif
+  ifeq ($(biarchx32),yes)
+    files_go += $(gcc_lib_dir)/$(biarchx32subdir)/{libgcc*,libgcov.a,*.o}
+  endif
+endif
+
+# ----------------------------------------------------------------------
+define __do_gccgo
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(usr_lib$(2))/libgo.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	mkdir -p debian/$(p_l)/usr/share/lintian/overrides
+	echo '$(p_l) binary: unstripped-binary-or-object' \
+	  >> debian/$(p_l)/usr/share/lintian/overrides/$(p_l)
+
+	: # don't strip: https://gcc.gnu.org/ml/gcc-patches/2015-02/msg01722.html
+	: # dh_strip -p$(p_l) --dbg-package=$(p_d)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst go$(GO_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst go$(GO_SONAME),atomic$(ATOMIC_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+do_gccgo = $(call __do_gccgo,lib$(1)go$(GO_SONAME),$(1))
+
+define install_gccgo_lib
+	mv $(d)/$(usr_lib$(3))/$(1).a debian/$(4)/$(gcc_lib_dir$(3))/
+	if [ -f $(d)/$(usr_lib$(3))/$(1)libbegin.a ]; then \
+	  mv $(d)/$(usr_lib$(3))/$(1)libbegin.a debian/$(4)/$(gcc_lib_dir$(3))/; \
+	fi
+	rm -f $(d)/$(usr_lib$(3))/$(1)*.{la,so}
+	dh_link -p$(4) \
+	  /$(usr_lib$(3))/$(1).so.$(2) /$(gcc_lib_dir$(3))/$(1).so
+endef
+
+# __do_gccgo_libgcc(flavour,package,todir,fromdir)
+define __do_gccgo_libgcc
+	$(if $(findstring gccgo,$(PKGSOURCE)),
+		: # libgcc_s.so may be a linker script on some architectures
+		set -e; \
+		if [ -h $(4)/libgcc_s.so ]; then \
+		  rm -f $(4)/libgcc_s.so; \
+		  dh_link -p$(2) /$(libgcc_dir$(1))/libgcc_s.so.$(GCC_SONAME) \
+		    $(3)/libgcc_s.so; \
+		else \
+		  mv $(4)/libgcc_s.so $(d)/$(3)/libgcc_s.so; \
+		  dh_link -p$(2) /$(libgcc_dir$(1))/libgcc_s.so.$(GCC_SONAME) \
+		    $(3)/libgcc_s.so.$(GCC_SONAME); \
+		fi; \
+		$(if $(1), dh_link -p$(2) /$(3)/libgcc_s.so \
+		    $(gcc_lib_dir)/libgcc_s_$(1).so;)
+	)
+endef
+
+define do_go_dev
+	dh_installdirs -p$(2) $(gcc_lib_dir$(1)) $(usr_lib$(1))
+	$(dh_compat2) dh_movefiles -p$(2) \
+		$(gcc_lib_dir$(1))/{libgobegin,libnetgo}.a \
+		$(usr_lib$(1))/go
+	$(if $(filter yes, $(with_standalone_go)), \
+	  $(call install_gccgo_lib,libgomp,$(GOMP_SONAME),$(1),$(2)))
+	$(call install_gccgo_lib,libgo,$(GO_SONAME),$(1),$(2))
+	$(call __do_gccgo_libgcc,$(1),$(2),$(gcc_lib_dir$(1)),$(d)/$(usr_lib$(1)))
+endef
+# ----------------------------------------------------------------------
+$(binary_stamp)-libgo: $(install_stamp)
+	$(call do_gccgo,)
+
+$(binary_stamp)-lib64go: $(install_stamp)
+	$(call do_gccgo,64)
+
+$(binary_stamp)-lib32go: $(install_stamp)
+	$(call do_gccgo,32)
+
+$(binary_stamp)-libn32go: $(install_stamp)
+	$(call do_gccgo,n32)
+
+$(binary_stamp)-libx32go: $(install_stamp)
+	$(call do_gccgo,x32)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gccgo: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_go)
+	dh_installdirs -p$(p_go) $(dirs_go)
+
+	mv $(d)/$(usr_lib)/{libgobegin,libnetgo}.a \
+		$(d)/$(gcc_lib_dir)/
+	if [ -f $(d)/$(usr_lib64)/libgobegin.a ]; then \
+	    mv $(d)/$(usr_lib64)/{libgobegin,libnetgo}.a \
+		$(d)/$(gcc_lib_dir)/64/; \
+	fi
+	if [ -f $(d)/$(usr_lib32)/libgobegin.a ]; then \
+	    mv $(d)/$(usr_lib32)/{libgobegin,libnetgo}.a \
+		$(d)/$(gcc_lib_dir)/32/; \
+	fi
+	if [ -f $(d)/$(usr_libn32)/libgobegin.a ]; then \
+	    mv $(d)/$(usr_libn32)/{libgobegin,libnetgo}.a \
+		$(d)/$(gcc_lib_dir)/n32/; \
+	fi
+	if [ -f $(d)/$(usr_libx32)/libgobegin.a ]; then \
+	    mv $(d)/$(usr_libx32)/{libgobegin,libnetgo}.a \
+		$(d)/$(gcc_lib_dir)/x32/; \
+	fi
+
+	$(call do_go_dev,,$(p_go))
+
+	$(dh_compat2) dh_movefiles -p$(p_go) $(files_go)
+
+ifneq (,$(findstring gccgo,$(PKGSOURCE)))
+	rm -rf $(d_go)/$(gcc_lib_dir)/include/cilk
+	rm -rf $(d_go)/$(gcc_lib_dir)/include/openacc.h
+endif
+
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)gccgo$(pkg_ver) \
+	    $(d_go)/$(PF)/bin/gccgo$(pkg_ver)
+	ln -sf $(cmd_prefix)go$(pkg_ver) \
+	    $(d_go)/$(PF)/bin/go$(pkg_ver)
+	ln -sf $(cmd_prefix)gofmt$(pkg_ver) \
+	    $(d_go)/$(PF)/bin/gofmt$(pkg_ver)
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	ln -sf $(cmd_prefix)gccgo$(pkg_ver).1 \
+	    $(d_go)/$(PF)/share/man/man1/gccgo$(pkg_ver).1
+  endif
+	ln -sf $(cmd_prefix)go$(pkg_ver).1 \
+	    $(d_go)/$(PF)/share/man/man1/go$(pkg_ver).1
+	ln -sf $(cmd_prefix)gofmt$(pkg_ver).1 \
+	    $(d_go)/$(PF)/share/man/man1/gofmt$(pkg_ver).1
+endif
+
+ifeq ($(with_standalone_go),yes)
+  ifeq ($(unprefixed_names),yes)
+	for i in gcc gcov gcov-tool gcc-ar gcc-nm gcc-ranlib; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_go)/$(PF)/bin/$$i$(pkg_ver); \
+	done
+    ifneq ($(GFDL_INVARIANT_FREE),yes)
+	for i in gcc gcov gcov-tool gcc-ar gcc-nm gcc-ranlib; do \
+	  ln -sf $(cmd_prefix)gcc$(pkg_ver).1 \
+	    $(d_go)/$(PF)/share/man/man1/$$i$(pkg_ver).1; \
+	done
+    endif
+  endif
+  ifeq ($(with_gomp),yes)
+	mv $(d)/$(usr_lib)/libgomp*.spec $(d_go)/$(gcc_lib_dir)/
+  endif
+  ifeq ($(with_cc1),yes)
+	rm -f $(d)/$(usr_lib)/libcc1.so
+	dh_link -p$(p_go) \
+		/$(usr_lib)/libcc1.so.$(CC1_SONAME) /$(gcc_lib_dir)/libcc1.so
+  endif
+endif
+
+	mkdir -p $(d_go)/usr/share/lintian/overrides
+	echo '$(p_go) binary: hardening-no-pie' \
+	  > $(d_go)/usr/share/lintian/overrides/$(p_go)
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	echo '$(p_go) binary: binary-without-manpage' \
+	  >> $(d_go)/usr/share/lintian/overrides/$(p_go)
+endif
+
+	debian/dh_doclink -p$(p_go) $(p_xbase)
+
+#	cp -p $(srcdir)/gcc/go/ChangeLog \
+#		$(d_go)/$(docdir)/$(p_base)/go/changelog
+	debian/dh_rmemptydirs -p$(p_go)
+
+	dh_strip -v -p$(p_go) -X/cgo -X/go$(pkg_ver) -X/gofmt$(pkg_ver) \
+	  $(if $(unstripped_exe),-X/go1)
+	dh_shlibdeps -p$(p_go)
+	echo $(p_go) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gccgo-multi: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_go_m)
+	dh_installdirs -p$(p_go_m) $(docdir)
+
+	$(foreach flavour,$(flavours), \
+		$(call do_go_dev,$(flavour),$(p_go_m)))
+
+	debian/dh_doclink -p$(p_go_m) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_go_m)
+	dh_strip -p$(p_go_m)
+	dh_shlibdeps -p$(p_go_m)
+	echo $(p_go_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-go-doc: $(build_html_stamp) $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_god)
+	dh_installdirs -p$(p_god) \
+		$(docdir)/$(p_xbase)/go \
+		$(PF)/share/info
+	$(dh_compat2) dh_movefiles -p$(p_god) \
+		$(PF)/share/info/gccgo*
+
+	debian/dh_doclink -p$(p_god) $(p_xbase)
+	dh_installdocs -p$(p_god)
+	rm -f $(d_god)/$(docdir)/$(p_xbase)/copyright
+	cp -p html/gccgo.html $(d_god)/$(docdir)/$(p_xbase)/go/
+	echo $(p_god) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-hppa64.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-hppa64.mk
@@ -0,0 +1,32 @@
+arch_binaries  := $(arch_binaries) hppa64
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-hppa64: $(install_hppa64_stamp)
+	dh_testdir
+	dh_testroot
+
+#	dh_installdirs -p$(p_hppa64)
+
+	rm -f $(d_hppa64)/usr/lib/libiberty.a
+	-find $(d_hppa64) ! -type d
+
+	: # provide as and ld links
+	dh_link -p $(p_hppa64) \
+		/usr/bin/hppa64-linux-gnu-as \
+		/$(hppa64libexecdir)/gcc/hppa64-linux-gnu/$(versiondir)/as \
+		/usr/bin/hppa64-linux-gnu-ld \
+		/$(hppa64libexecdir)/gcc/hppa64-linux-gnu/$(versiondir)/ld
+
+	debian/dh_doclink -p$(p_hppa64) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_hppa64)
+
+	dh_strip -p$(p_hppa64) -X.o -Xlibgcc.a -Xlibgcov.a
+	dh_shlibdeps -p$(p_hppa64)
+
+	mkdir -p $(d_hppa64)/usr/share/lintian/overrides
+	cp -p debian/$(p_hppa64).overrides \
+		$(d_hppa64)/usr/share/lintian/overrides/$(p_hppa64)
+
+	echo $(p_hppa64) >> debian/arch_binaries
+
+	touch $@
--- gcc-6-6.4.0.orig/debian/rules.d/binary-java.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-java.mk
@@ -0,0 +1,769 @@
+ifeq ($(with_gcj_base_only),yes)
+  arch_binaries  := $(arch_binaries) jbase
+else
+ifeq ($(with_separate_libgcj),yes)
+  ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+    arch_binaries  := $(arch_binaries) jbase
+  endif
+endif
+
+ifeq ($(with_libgcj),yes)
+  ifeq ($(with_java),yes)
+    arch_binaries  := $(arch_binaries) java gcjjre
+    indep_binaries  := $(indep_binaries) libgcjjar
+  endif
+
+  ifeq ($(with_javadev),yes)
+    arch_binaries  := $(arch_binaries) gcjjdk libgcjdev libgcjdbg
+    ifneq ($(DEB_CROSS),yes)
+      indep_binaries := $(indep_binaries) libgcjsrc
+      ifeq ($(with_libgcj_doc),yes)
+        indep_binaries := $(indep_binaries) libgcjdoc
+      endif
+    endif
+  endif
+endif
+
+ifeq ($(with_gcj),yes)
+    arch_binaries  := $(arch_binaries) gcj
+endif
+endif
+
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+  p_jbase = gcj$(pkg_ver)-base
+  ifeq ($(with_separate_libgcj)-$(with_standalone_gcj),no-no)
+    p_jbase = gcc$(pkg_ver)-base
+  endif
+else
+  p_jbase = gcj$(pkg_ver)$(cross_bin_arch)-base
+  ifeq ($(with_separate_libgcj)-$(with_standalone_gcj),no-no)
+    p_jbase = gcc$(pkg_ver)$(cross_bin_arch)-base
+  endif
+endif
+
+p_gcj	= gcj$(pkg_ver)$(cross_bin_arch)
+p_jdk	= gcj$(pkg_ver)-jdk$(cross_bin_arch)
+p_jrehl	= gcj$(pkg_ver)-jre-headless$(cross_bin_arch)
+p_jre	= gcj$(pkg_ver)-jre$(cross_bin_arch)
+p_jar	= gcj$(pkg_ver)-jre-lib$(cross_bin_arch)
+p_jsrc	= gcj$(pkg_ver)-source
+p_jlib	= libgcj$(PKG_LIBGCJ_EXT)$(cross_lib_arch)
+p_jdbg	= libgcj$(PKG_GCJ_EXT)-dbg$(cross_lib_arch)
+p_jlibx	= libgcj$(PKG_LIBGCJ_EXT)-awt$(cross_lib_arch)
+p_jgtk	= libgcj$(PKG_GCJ_EXT)-awt-gtk$(cross_lib_arch)
+p_jqt	= libgcj$(PKG_GCJ_EXT)-awt-qt$(cross_lib_arch)
+p_jdev	= libgcj$(PKG_GCJ_EXT)-dev$(cross_lib_arch)
+p_jdoc	= libgcj-doc
+
+d_jbase	= debian/$(p_jbase)
+d_gcj	= debian/$(p_gcj)
+d_jdk	= debian/$(p_jdk)
+d_jrehl	= debian/$(p_jrehl)
+d_jar	= debian/$(p_jar)
+d_jsrc	= debian/$(p_jsrc)
+d_jlib	= debian/$(p_jlib)
+d_jdbg	= debian/$(p_jdbg)
+d_jlibx	= debian/$(p_jlibx)
+d_jgtk	= debian/$(p_jgtk)
+d_jqt	= debian/$(p_jqt)
+d_jdev	= debian/$(p_jdev)
+d_jdoc	= debian/$(p_jdoc)
+d_jre	= debian/$(p_jre)
+
+GCJ_BASE_VERSION = $(BASE_VERSION)
+
+gcj_vlibdir	= $(PF)/$(libdir)/gcj-$(BASE_VERSION)-$(GCJ_SONAME)
+
+jre_tools = java keytool orbd rmid rmiregistry tnameserv
+jdk_tools = appletviewer jar jarsigner javac javadoc javah native2ascii rmic serialver
+
+dirs_gcj = \
+	$(docdir)/$(p_jbase) \
+	$(PF)/bin \
+	$(PF)/share/man/man1 \
+	$(gcc_lexec_dir)
+
+files_gcj = \
+	$(PF)/bin/$(cmd_prefix)gcj$(pkg_ver) \
+	$(gcc_lexec_dir)/{jc1,jvgenmain}
+
+# FIXME: this really should be included, or else the cross compiler
+# can only be used to build libjava itself.
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+  files_gcj += \
+	$(PF)/$(libdir)/libgcj.spec
+endif
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_gcj += \
+	$(PF)/share/man/man1/$(cmd_prefix)gcj$(pkg_ver).1
+endif
+
+dirs_jdk = \
+	$(docdir)/$(p_jbase) \
+	$(PF)/bin \
+	$(PF)/share/man/man1 \
+	$(PF)/share/info \
+	$(gcc_lexec_dir) \
+	$(jvm_dir)/bin
+
+files_jdk = \
+	$(PF)/bin/$(cmd_prefix){gappletviewer,gjdoc,gc-analyze,gjar,gjarsigner,gcjh,gjavah,gnative2ascii,grmic,gserialver,jv-convert,jcf-dump}$(pkg_ver) \
+	$(PF)/share/man/man1/$(cmd_prefix){gappletviewer,gjdoc,gjar,gjarsigner,gcjh,gjavah,gnative2ascii,gserialver}$(pkg_ver).1 \
+	$(gcc_lib_dir)/include/{jni.h,jni_md.h,jvmpi.h} \
+	$(gcc_lib_dir)/include/{jawt.h,jawt_md.h} \
+	$(gcc_lib_dir)/include/gcj/libgcj-config.h \
+	$(PF)/$(libdir)/lib{gij,gcj,gcj-tools}.so \
+	$(jvm_dir)/include \
+	$(jvm_dir)/bin/{appletviewer,jar,jarsigner,javadoc,javah,native2ascii,rmic,serialver} \
+	$(PF)/lib/jvm-exports
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_jdk += \
+	$(PF)/share/info/gcj* \
+	$(PF)/share/man/man1/$(cmd_prefix){gc-analyze,grmic,jv-convert,jcf-dump}$(pkg_ver).1
+endif
+
+dirs_jrehl = \
+	$(docdir)/$(p_jbase) \
+	$(PF)/bin \
+	$(PF)/share/man/man1 \
+	$(jvm_dir)/bin \
+	$(jvm_dir)/jre/lib \
+	$(jvm_dir)/lib \
+	var/lib/gcj$(pkg_ver)
+
+files_jrehl = \
+	$(PF)/bin/$(cmd_prefix){gij,gcj-dbtool,gorbd,grmid,grmiregistry,gkeytool,gtnameserv}$(pkg_ver) \
+	$(PF)/share/man/man1/$(cmd_prefix){gorbd,grmid,grmiregistry,gkeytool,gtnameserv}$(pkg_ver).1 \
+	$(jvm_dir)/jre/bin \
+	$(jvm_dir)/bin/{java,keytool,orbd,rmid,rmiregistry,tnameserv} \
+	$(jvm_dir)/jre/lib/rt.jar \
+	$(jvm_dir)/jre/lib/$(java_cpu)/{client,server} \
+	$(jvm_dir)/lib/tools.jar
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  files_jrehl += \
+	$(PF)/share/man/man1/$(cmd_prefix){gij,gcj-dbtool}$(pkg_ver).1
+endif
+
+dirs_jre = \
+	$(docdir)/$(p_jbase) \
+	$(jvm_dir)/jre/lib/$(java_cpu)
+
+files_jre = \
+	$(jvm_dir)/jre/lib/$(java_cpu)/libjawt.so
+
+dirs_jlib = \
+	$(docdir)/$(p_jbase) \
+	$(gcj_vlibdir) \
+	$(PF)/$(libdir) \
+	$(jvm_dir)/jre/lib
+
+files_jlib = \
+	$(PF)/$(libdir)/libgij.so.* \
+	$(PF)/$(libdir)/libgcj-tools.so.* \
+	$(PF)/$(libdir)/libgcj.so.* \
+	$(gcj_vlibdir)/libjvm.so \
+	$(gcj_vlibdir)/libjavamath.so \
+	$(jvm_dir)/jre/lib/security
+
+#	$(gcj_vlibdir)/libgconfpeer.so
+
+ifeq ($(with_java_alsa),yes)
+  files_jlib += \
+	$(gcj_vlibdir)/libgjsmalsa.so
+endif
+
+dirs_jar = \
+	$(PF)/share/java
+
+files_jar = \
+	$(PF)/share/java/libgcj-$(BASE_VERSION).jar \
+	$(PF)/share/java/libgcj-tools-$(BASE_VERSION).jar
+
+dirs_jlibx = \
+	$(PF)/$(libdir) \
+	$(gcj_vlibdir) \
+	$(PF)/share/java
+
+files_jlibx = \
+	$(gcj_vlibdir)/libjawt.so \
+	$(gcj_vlibdir)/libgtkpeer.so
+
+#files_jgtk = \
+#	$(gcj_vlibdir)/libgtkpeer.so
+#files_jqt = \
+#	$(gcj_vlibdir)/libqtpeer.so
+
+dirs_jdev = \
+	$(PF)/{include,lib} \
+	$(jvm_dir)/include
+
+files_jdev = \
+	$(PF)/include/c++/$(BASE_VERSION)/{org,gcj,java,javax} \
+	$(PF)/include/c++/$(BASE_VERSION)/gnu/{awt,classpath,gcj,java,javax} \
+	$(PF)/$(libdir)/pkgconfig/libgcj-$(BASE_VERSION).pc \
+	$(gcj_vlibdir)/lib*peer.so
+
+ifeq ($(with_static_java),yes)
+  files_jdev += \
+	$(PF)/$(libdir)/libgij.a \
+	$(PF)/$(libdir)/libgcj.a \
+	$(PF)/$(libdir)/libgcj-tools.a
+endif
+
+ifeq (,$(p_l64gcc))
+  p_l64gcc = lib64gcc$(GCC_SONAME)
+  d_l64gcc = debian/$(p_l64gcc)
+endif
+
+ifeq ($(with_standalone_gcj),yes)
+
+  dirs_gcj += \
+	$(gcc_lib_dir)/include \
+	$(PF)/share/man/man1
+
+# XXX: what about triarch mapping?
+  files_gcj += \
+	$(PF)/bin/$(cmd_prefix){cpp,gcc,gcov}$(pkg_ver) \
+	$(gcc_lexec_dir)/{collect2,lto1,lto-wrapper} \
+	$(gcc_lexec_dir)/liblto_plugin.so{,.0,.0.0.0} \
+	$(gcc_lib_dir)/{libgcc*,libgcov.a,*.o} \
+	$(header_files) \
+	$(shell test -e $(d)/$(gcc_lib_dir)/SYSCALLS.c.X \
+		&& echo $(gcc_lib_dir)/SYSCALLS.c.X)
+
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+    files_gcj += \
+	$(PF)/share/man/man1/$(cmd_prefix){cpp,gcc,gcov}$(pkg_ver).1
+  endif
+
+  ifeq ($(biarch64),yes)
+    files_gcj += $(gcc_lib_dir)/$(biarch64subdir)/{libgcc*,libgcov.a,*.o}
+  endif
+  ifeq ($(biarch32),yes)
+    files_gcj += $(gcc_lib_dir)/$(biarch32subdir)/{libgcc*,*.o}
+  endif
+  ifeq ($(biarchn32),yes)
+    files_gcj += $(gcc_lib_dir)/$(biarchn32subdir)/{libgcc*,libgcov.a,*.o}
+  endif
+  ifeq ($(biarchx32),yes)
+    files_gcj += $(gcc_lib_dir)/$(biarchx32subdir)/{libgcc*,libgcov.a,*.o}
+  endif
+endif
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-jbase: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	rm -rf $(d_jbase)
+	dh_installdirs -p$(p_jbase)
+	dh_installdocs -p$(p_jbase)
+	dh_installchangelogs -p$(p_jbase)
+	dh_compress -p$(p_jbase)
+	dh_fixperms -p$(p_jbase)
+	dh_gencontrol -p$(p_jbase) -- -v$(DEB_VERSION) $(common_substvars)
+	dh_installdeb -p$(p_jbase)
+	dh_md5sums -p$(p_jbase)
+	dh_builddeb -p$(p_jbase)
+	touch $@
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcj: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_gcj)
+	dh_installdirs -p$(p_gcj)  $(dirs_gcj)
+
+	$(dh_compat2) dh_movefiles -p$(p_gcj)  $(files_gcj)
+ifneq (,$(filter $(build_type), build-native cross-build-native))
+	mv $(d_gcj)/$(PF)/$(libdir)/libgcj.spec $(d_gcj)/$(gcc_lib_dir)/
+endif
+
+ifeq ($(with_external_ecj1),yes)
+	dh_link -p$(p_gcj) \
+		/$(PF)/lib/$(DEB_HOST_MULTIARCH)/gcc/ecj1 /$(gcc_lexec_dir)/ecj1
+endif
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)gcj$(pkg_ver) \
+	    $(d_gcj)/$(PF)/bin/gcj$(pkg_ver)
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	ln -sf $(cmd_prefix)gcj$(pkg_ver).1.gz \
+	    $(d_gcj)/$(PF)/share/man/man1/gcj$(pkg_ver).1.gz
+  endif
+endif
+
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	mkdir -p $(d_gcj)/usr/share/lintian/overrides
+	echo '$(p_gcj) binary: binary-without-manpage' \
+	  >> $(d_gcj)/usr/share/lintian/overrides/$(p_gcj)
+endif
+
+	debian/dh_doclink -p$(p_gcj) $(p_jbase)
+	debian/dh_rmemptydirs -p$(p_gcj)
+
+	dh_strip -p$(p_gcj) \
+	  $(if $(unstripped_exe),-X/jc1)
+	dh_shlibdeps -p$(p_gcj) -Xecj1
+	echo $(p_gcj) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libgcjjar: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	dh_installdirs -p$(p_jar) $(dirs_jar)
+	$(dh_compat2) dh_movefiles -p$(p_jar) $(files_jar)
+
+	ln -sf libgcj-$(BASE_VERSION).jar \
+		$(d_jar)/$(PF)/share/java/libgcj-$(GCC_VERSION).jar
+	ln -sf libgcj-tools-$(BASE_VERSION).jar \
+		$(d_jar)/$(PF)/share/java/libgcj-tools-$(GCC_VERSION).jar
+	debian/dh_doclink -p$(p_jar) $(p_jbase)
+	debian/dh_rmemptydirs -p$(p_jar)
+	echo $(p_jar) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(build_javasrc_stamp): $(build_stamp)
+	PATH=$(CURDIR)/bin:$$PATH \
+	  $(MAKE) -C $(buildlibdir)/libjava src.zip
+	touch $@
+
+$(binary_stamp)-libgcjsrc: $(install_stamp) $(build_javasrc_stamp)
+	dh_testdir
+	dh_testroot
+
+	dh_installdirs -p$(p_jsrc) $(PF)/share/java $(jvm_dir)
+	cp -p $(buildlibdir)/libjava/src.zip \
+	   $(d_jsrc)/$(PF)/share/java/libgcj-src-$(BASE_VERSION).zip
+	dh_link -p$(p_jsrc) \
+		$(PF)/share/java/libgcj-src-$(BASE_VERSION).zip \
+		$(jvm_dir)/src.zip
+	debian/dh_doclink -p$(p_jsrc) $(p_jbase)
+	debian/dh_rmemptydirs -p$(p_jsrc)
+	echo $(p_jsrc) >> debian/indep_binaries
+
+	touch $@
+
+# ----------------------------------------------------------------------
+libgcj_version = $$($(builddir)/gcc/xgcc -B$(builddir)/gcc/ --version \
+			 | sed -n '/^xgcc/s/[^)]*) *\(.*\)/\1/p' | sed 's/ \[[^[]*$$//')
+libgcj_title = LibGCJ Classpath
+libgcjhbox_href = http://gcc.gnu.org/java
+libgcjhbox = <span class='logo'><a href='$(libgcjhbox_href)' target='_top'>$(title)</a> ($(libgcj_version))
+
+$(build_javadoc_stamp): $(build_stamp) $(build_javasrc_stamp)
+	mkdir -p $(builddir)/java-src
+	cd $(builddir)/java-src && fastjar -xf $(buildlibdir)/libjava/src.zip
+
+	mkdir -p $(builddir)/html
+	$(buildlibdir)/libjava/gjdoc \
+	    -licensetext \
+	    -use \
+	    -sourcepath "$(builddir)/java-src" \
+	    -encoding UTF-8 \
+	    -breakiterator \
+	    -linksource \
+	    -splitindex \
+	    -d $(builddir)/html \
+	    -doctitle "$(libgcj_title) $(libgcj_version)" \
+	    -windowtitle "$(libgcj_title) $(libgcj_version) Documentation" \
+	    -header "$(classpathbox)" \
+	    -footer "$(classpathbox)" \
+	    -subpackages gnu:java:javax:org
+
+	touch $@
+
+$(binary_stamp)-libgcjdoc: $(install_stamp) $(build_javadoc_stamp)
+	dh_testdir
+	dh_testroot
+
+	dh_installdocs -p$(p_jdoc)
+	sed -i 's/gcc$(pkg_ver)-base/$(p_jbase)/' $(d_jdoc)/usr/share/doc-base/libgcj-doc
+	dh_installchangelogs -p$(p_jdoc)
+	mkdir -p $(d_jdoc)/usr/share/doc/$(p_jbase)
+	cp -al $(builddir)/html $(d_jdoc)/usr/share/doc/$(p_jbase)/api
+	ln -sf api $(d_jdoc)/usr/share/doc/$(p_jbase)/html
+	ln -sf ../$(p_jbase)/api $(d_jdoc)/usr/share/doc/$(p_jdoc)/api
+	ln -sf ../$(p_jbase)/html $(d_jdoc)/usr/share/doc/$(p_jdoc)/html
+	echo $(p_jdoc) >> debian/indep_binaries
+
+	touch $@
+
+# ----------------------------------------------------------------------
+
+#peer_pkgs =
+#ifneq (,$(findstring gtk, $(java_awt_peers)))
+#  peer_pkgs += -p$(p_jgtk)
+#endif
+#ifneq (,$(findstring qt, $(java_awt_peers)))
+#  peer_pkgs += -p$(p_jqt)
+#endif
+
+$(binary_stamp)-java: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	dh_installdirs -p$(p_jrehl)   $(dirs_jrehl)
+	dh_installdirs -p$(p_jlib)  $(dirs_jlib)
+	dh_installdirs -p$(p_jlibx) $(dirs_jlibx)
+
+	$(dh_compat2) dh_movefiles -p$(p_jrehl)   $(files_jrehl)
+	$(dh_compat2) dh_movefiles -p$(p_jlib)  $(files_jlib)
+	$(dh_compat2) dh_movefiles -p$(p_jlibx) $(files_jlibx)
+#ifneq (,$(findstring gtk, $(java_awt_peers)))
+#	$(dh_compat2) dh_movefiles -p$(p_jgtk) $(files_jgtk)
+#endif
+#ifneq (,$(findstring qt, $(java_awt_peers)))
+#	$(dh_compat2) dh_movefiles -p$(p_jqt) $(files_jqt)
+#endif
+
+ifeq ($(unprefixed_names),yes)
+	for i in gij gcj-dbtool gorbd grmid grmiregistry gkeytool gtnameserv; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_jrehl)/$(PF)/bin/$$i$(pkg_ver); \
+	done
+	for i in gorbd grmid grmiregistry gkeytool gtnameserv; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver).1.gz \
+	    $(d_jrehl)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	for i in gij gcj-dbtool; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver).1.gz \
+	    $(d_jrehl)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+  endif
+endif
+
+	dh_link -p$(p_jrehl) \
+	  $(jvm_dir) $(PF)/lib/jvm/java-gcj$(pkg_ver) \
+	  $(PF)/bin/$(cmd_prefix)gij$(pkg_ver) $(jvm_dir)/bin/gij \
+	  $(PF)/bin/$(cmd_prefix)gij$(pkg_ver) $(jvm_dir)/jre/bin/gij \
+	  $(PF)/bin/$(cmd_prefix)gcj-dbtool$(pkg_ver) $(jvm_dir)/bin/gcj-dbtool \
+	  $(PF)/bin/$(cmd_prefix)gcj-dbtool$(pkg_ver) $(jvm_dir)/jre/bin/gcj-dbtool \
+	  $(PF)/share/man/man1/$(cmd_prefix)gkeytool$(pkg_ver).1 $(jvm_dir)/man/man1/keytool.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)gorbd$(pkg_ver).1 $(jvm_dir)/man/man1/orbd.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)grmid$(pkg_ver).1 $(jvm_dir)/man/man1/rmid.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)grmiregistry$(pkg_ver).1 $(jvm_dir)/man/man1/rmiregistry.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)gtnameserv$(pkg_ver).1 $(jvm_dir)/man/man1/tnameserv.1 \
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+	dh_link -p$(p_jrehl) \
+	  $(PF)/share/man/man1/$(cmd_prefix)gij$(pkg_ver).1 $(jvm_dir)/man/man1/java.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)grmic$(pkg_ver).1 $(jvm_dir)/man/man1/rmiregistry.1
+endif
+
+ifneq ($(DEB_TARGET_ARCH_CPU),$(java_cpu))
+	ln -sf $(java_cpu) $(d_jlib)/$(jvm_dir)/jre/lib/$(DEB_TARGET_ARCH_CPU)
+endif
+
+	dh_link -p$(p_jlib) \
+	  /etc/java/cacerts-gcj /$(jvm_dir)/jre/lib/cacerts \
+	  $(foreach i, jvm javamath, \
+		/$(gcj_vlibdir)/lib$(i).so /$(jvm_dir)/lib/lib$(i).so)
+
+	dh_link -p$(p_jlib) \
+	  /etc/java/security/classpath.security \
+	  /$(jvm_dir)/jre/lib/security/java.security
+
+	dh_link -p$(p_jlibx) \
+	  $(foreach i, jawt, $(gcj_vlibdir)/lib$(i).so $(jvm_dir)/lib/lib$(i).so)
+
+ifeq ($(DEB_HOST_ARCH),hppa)
+	mv $(d_jrehl)/$(PF)/bin/$(cmd_prefix)gij$(pkg_ver) \
+		$(d_jrehl)/$(PF)/bin/$(cmd_prefix)gij$(pkg_ver).bin
+	install -m755 debian/gij-hppa $(d_jrehl)/$(PF)/bin/$(cmd_prefix)gij$(pkg_ver)
+  ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)gij$(pkg_ver) \
+	    $(d_jrehl)/$(PF)/bin/gij$(pkg_ver)
+	ln -sf $(cmd_prefix)gij$(pkg_ver).bin \
+	    $(d_jrehl)/$(PF)/bin/gij$(pkg_ver).bin
+  endif
+endif
+
+	ln -s ../libgcj.so.$(GCJ_SONAME) \
+		$(d_jlib)/$(gcj_vlibdir)/libgcj_bc.so.1
+
+	: # provide .jinfo file
+	( \
+	  echo 'name=$(jvm_name_short)'; \
+	  echo 'alias=java-gcj$(pkg_ver)'; \
+	  echo 'priority=$(priority)'; \
+	  echo 'section=main'; \
+	  echo ''; \
+	  for i in $(jre_tools); do \
+	    echo "jre $$i /$(jvm_dir)/jre/bin/$$i"; \
+	  done; \
+	  for i in $(jdk_tools); do \
+	    echo "jdk $$i /$(jvm_dir)/bin/$$i"; \
+	  done; \
+	) > $(d_jrehl)/usr/lib/jvm/.java-gcj$(pkg_ver).jinfo
+
+ifneq (,$(findstring gcj,$(p_jbase)))
+	cp -p $(srcdir)/libjava/{NEWS,README,THANKS} \
+		$(d_jrehl)/usr/share/doc/$(p_jbase)/
+endif
+	debian/dh_doclink -p$(p_jrehl) $(p_jbase)
+	debian/dh_doclink -p$(p_jlib)  $(p_jbase)
+	debian/dh_doclink -p$(p_jlibx) $(p_jbase)
+
+#ifneq (,$(findstring gtk, $(java_awt_peers)))
+#	debian/dh_doclink -p$(p_jgtk) $(p_jbase)
+#endif
+#ifneq (,$(findstring qt, $(java_awt_peers)))
+#	debian/dh_doclink -p$(p_jqt) $(p_jbase)
+#endif
+
+ifeq ($(with_separate_libgcj),yes)
+  ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+    ifeq ($(with_check),yes)
+	cp -p test-summary $(d_jrehl)/usr/share/doc/$(p_jbase)/test-summary
+    endif
+  endif
+endif
+	debian/dh_rmemptydirs -p$(p_jrehl)
+	debian/dh_rmemptydirs -p$(p_jlib)
+	debian/dh_rmemptydirs -p$(p_jlibx)
+
+	mkdir -p $(d_jrehl)/var/lib/gcj$(pkg_ver)
+
+	dh_makeshlibs $(ldconfig_arg) -p$(p_jlib) -V '$(p_jlib) (>= $(DEB_GCJ_SOVERSION))'
+	echo "libgcj_bc 1 libgcj-bc (>= 4.2.2-1)" >> debian/$(p_jlib)/DEBIAN/shlibs
+	cat debian/$(p_jlib)/DEBIAN/shlibs >> debian/shlibs.local
+
+	dh_makeshlibs $(ldconfig_arg) -p$(p_jlibx) -V '$(p_jlibx) (>= $(DEB_GCJ_SOVERSION))'
+
+#ifneq (,$(findstring gtk, $(java_awt_peers)))
+#	dh_makeshlibs $(ldconfig_arg) -p$(p_jgtk) -V '$(p_jgtk) (>= $(DEB_GCJ_SOVERSION))'
+#endif
+#ifneq (,$(findstring qt, $(java_awt_peers)))
+#	dh_makeshlibs $(ldconfig_arg) -p$(p_jqt) -V '$(p_jqt) (>= $(DEB_GCJ_SOVERSION))'
+#endif
+
+	dh_strip -X/bin/ --dbg-package=$(p_jdbg) \
+		-p$(p_jrehl) -p$(p_jlib) -p$(p_jlibx) $(peer_pkgs)
+	rm -f $(d_jdbg)/$(gcc_lib_dir)/libgcj_bc.so
+
+	mkdir -p $(d_jlib)/usr/share/lintian/overrides
+	cp -p debian/$(p_jlib).overrides \
+		$(d_jlib)/usr/share/lintian/overrides/$(p_jlib)
+	mkdir -p $(d_jlibx)/usr/share/lintian/overrides
+	cp -p debian/$(p_jlibx).overrides \
+		$(d_jlibx)/usr/share/lintian/overrides/$(p_jlibx)
+	mkdir -p $(d_jrehl)/usr/share/lintian/overrides
+	cp -p debian/$(p_jrehl).overrides \
+		$(d_jrehl)/usr/share/lintian/overrides/$(p_jrehl)
+
+# the libstdc++ binary packages aren't built yet ...
+	echo 'libstdc++ $(CXX_SONAME) libstdc++$(CXX_SONAME) (>= $(DEB_STDCXX_SOVERSION))' \
+	    >> debian/shlibs.local
+	-[ -d $(d_l64gcc) ] && mv $(d_l64gcc) $(d_l64gcc).saved
+ifeq ($(with_separate_libgcj)-$(with_standalone_gcj),yes-no)
+	dh_shlibdeps \
+		-L$(p_jlib) \
+		-l$(d_lib)/$(PF)/$(libdir):$(d_jlib)/$(PF)/$(libdir) \
+		-p$(p_jrehl) -p$(p_jlib) -p$(p_jlibx) $(peer_pkgs)
+else
+	dh_shlibdeps \
+		-L$(p_lgcc) \
+		-L$(p_jlib) \
+		-l:$(d)/$(PF)/$(libdir):$(d_lib)/$(PF)/$(libdir):$(d_jlib)/$(PF)/$(libdir):$(d_lgcc)/lib \
+		-p$(p_jrehl) -p$(p_jlib) -p$(p_jlibx) $(peer_pkgs)
+endif
+	-[ -d $(d_l64gcc).saved ] && mv $(d_l64gcc).saved $(d_l64gcc)
+	sed -e 's/$(p_jlib)[^,]*//' -e 's/, *,/,/' debian/$(p_jlib).substvars \
+		>> debian/$(p_jlib).substvars.tmp \
+	    && mv -f debian/$(p_jlib).substvars.tmp debian/$(p_jlib).substvars
+	rm -f debian/shlibs.local
+
+	echo $(p_jrehl) $(p_jlib) $(p_jlibx) $(subst -p,,$(peer_pkgs)) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcjjdk: $(build_html_stamp) $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_jdk)
+	dh_installdirs -p$(p_jdk)  $(dirs_jdk)
+
+#	mkdir -p $(d_jdk)/usr/share/lintian/overrides
+#	cp -p debian/$(p_jdk).overrides \
+#		$(d_jdk)/usr/share/lintian/overrides/$(p_jdk)
+	cp -p $(srcdir)/gcc/java/ChangeLog \
+		$(d_jdk)/usr/share/doc/$(p_jbase)/changelog.gcj
+	cp -p $(srcdir)/libjava/ChangeLog \
+		$(d_jdk)/usr/share/doc/$(p_jbase)/changelog.libjava
+
+ifeq ($(with_standalone_gcj),yes)
+	rm -f $(d)/$(PF)/$(libdir)/libgcc_s.so
+	ln -sf /$(libdir)/libgcc_s.so.$(GCC_SONAME) $(d)/$(gcc_lib_dir)/libgcc_s.so
+endif
+	$(dh_compat2) dh_movefiles -p$(p_jdk)  $(files_jdk)
+
+	for i in libgij libgcj libgcj-tools; do \
+	  dh_link -p$(p_jdk) \
+	    /$(PF)/$(libdir)/$$i.so.$(GCJ_SONAME) /$(gcc_lib_dir)/$$i.so \
+	    /$(PF)/$(libdir)/$$i.so.$(GCJ_SONAME) /$(jvm_dir)/lib/$$i.so; \
+	  rm -f $(d_jdk)/$(PF)/$(libdir)/$$i.{la,so}; \
+	done
+
+	install -m755 debian/jdb.sh $(d_jdk)/$(jvm_dir)/bin/jdb
+
+	install -m 755 $(d)/$(PF)/$(libdir)/libgcj_bc.so.1 \
+		$(d_jdk)/$(gcc_lib_dir)/libgcj_bc.so
+	$(CC_FOR_TARGET) $(LDFLAGS_FOR_TARGET) -shared -fpic -xc /dev/null \
+		-o build/libgcj.so -Wl,-soname,libgcj.so.$(GCJ_SONAME) -nostdlib
+	$(CC_FOR_TARGET) $(LDFLAGS_FOR_TARGET) -shared -fpic \
+		$(srcdir)/libjava/libgcj_bc.c \
+		-o $(d_jdk)/$(gcc_lib_dir)/libgcj_bc.so \
+		-Wl,-soname,libgcj_bc.so.1 $(builddir)/libgcj.so -shared-libgcc 
+
+	dh_link -p$(p_jdk) \
+	  $(gcc_lib_dir)/include/gcj $(jvm_dir)/include/gcj \
+	  usr/bin/ecj $(jvm_dir)/bin/javac \
+	  usr/bin/fastjar $(jvm_dir)/bin/jar \
+	  $(PF)/share/man/man1/ecj.1.gz $(jvm_dir)/man/man1/javac.1.gz \
+	  $(PF)/share/man/man1/fastjar.1.gz $(jvm_dir)/man/man1/jar.1.gz
+
+ifeq ($(unprefixed_names),yes)
+	for i in gappletviewer gjdoc gc-analyze gjar gjarsigner gcjh gjavah gnative2ascii grmic gserialver jv-convert jcf-dump; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver) \
+	    $(d_jdk)/$(PF)/bin/$$i$(pkg_ver); \
+	done
+	for i in gappletviewer gjdoc gjar gjarsigner gcjh gjavah gnative2ascii gserialver; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver).1.gz \
+	    $(d_jdk)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+	for i in gc-analyze gnative2ascii grmic jv-convert jcf-dump; do \
+	  ln -sf $(cmd_prefix)$$i$(pkg_ver).1.gz \
+	    $(d_jdk)/$(PF)/share/man/man1/$$i$(pkg_ver).1.gz; \
+	done
+  endif
+endif
+
+	dh_link -p$(p_jdk) \
+	  $(PF)/bin/$(cmd_prefix)gcj$(pkg_ver) $(jvm_dir)/bin/gcj \
+	  $(PF)/share/man/man1/$(cmd_prefix)gjarsigner$(pkg_ver).1 $(jvm_dir)/man/man1/jarsigner.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)gjdoc$(pkg_ver).1 $(jvm_dir)/man/man1/javadoc.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)gjavah$(pkg_ver).1 $(jvm_dir)/man/man1/javah.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)gserialver$(pkg_ver).1 $(jvm_dir)/man/man1/serialver.1 \
+	  $(PF)/share/man/man1/$(cmd_prefix)gappletviewer$(pkg_ver).1 $(jvm_dir)/man/man1/appletviewer.1
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+	cp -p html/gcj.html $(d_jdk)/$(docdir)/$(p_jbase)/
+endif
+	debian/dh_doclink -p$(p_jdk) $(p_jbase)
+
+	cp -p debian/FAQ.gcj $(d_jdk)/$(docdir)/$(p_jbase)/
+
+	cp -p debian/gcj-wrapper$(pkg_ver) \
+		$(d_jdk)/$(PF)/bin/$(cmd_prefix)gcj-wrapper$(pkg_ver)
+	chmod 755 $(d_jdk)/$(PF)/bin/$(cmd_prefix)gcj-wrapper$(pkg_ver)
+	cp -p debian/gcj-wrapper$(pkg_ver).1 \
+		$(d_jdk)/$(PF)/share/man/man1/$(cmd_prefix)gcj-wrapper$(pkg_ver).1
+ifeq ($(unprefixed_names),yes)
+	ln -sf $(cmd_prefix)gcj-wrapper$(pkg_ver) \
+	    $(d_jdk)/$(PF)/bin/gcj-wrapper$(pkg_ver)
+	  ln -sf $(cmd_prefix)gcj-wrapper$(pkg_ver).1.gz \
+	    $(d_jdk)/$(PF)/share/man/man1/gcj-wrapper$(pkg_ver).1.gz
+endif
+
+	debian/dh_rmemptydirs -p$(p_jdk)
+
+	dh_strip -p$(p_jdk)
+	dh_shlibdeps -p$(p_jdk) -l$(d_lib)/$(PF)/$(libdir):$(d_jlib)/$(PF)/lib -Xecj1
+	echo $(p_jdk) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libgcjdev: $(build_html_stamp) $(install_stamp) $(binary_stamp)-java
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	dh_installdirs -p$(p_jdev) $(dirs_jdev)
+
+	$(dh_compat2) dh_movefiles -p$(p_jdev) $(files_jdev)
+
+ifeq ($(with_static_java),yes)
+	for i in libgij libgcj libgcj-tools; do \
+	  mv $(d_jdev)/$(PF)/$(libdir)/$$i.a $(d_jdev)/$(gcc_lib_dir)/; \
+	done
+endif
+
+	ln -sf libgcj-$(BASE_VERSION).pc \
+		$(d_jdev)/$(PF)/$(libdir)/pkgconfig/libgcj$(PKG_GCJ_EXT).pc
+	sed -i -e 's,-[IL][^ ]* *,,' \
+		$(d_jdev)/$(PF)/$(libdir)/pkgconfig/libgcj-$(BASE_VERSION).pc
+
+	debian/dh_doclink -p$(p_jdev) $(p_jbase)
+
+	debian/dh_rmemptydirs -p$(p_jdev)
+
+#	mkdir -p $(d_jdev)/usr/share/lintian/overrides
+#	cp -p debian/libgcj$(PKG_GCJ_EXT)-dev.overrides \
+#		$(d_jdev)/usr/share/lintian/overrides/$(p_jdev)
+
+	DH_COMPAT=5 dh_strip -p$(p_jdev) --dbg-package=$(p_jdbg)
+ifeq ($(with_separate_libgcj)-$(with_standalone_gcj),yes-no)
+	dh_shlibdeps \
+		-l$(d_lib)/$(PF)/$(libdir):$(d_jlib)/$(PF)/$(libdir) \
+		-p$(p_jdev)
+else
+	dh_shlibdeps \
+		-L$(p_lgcc) \
+		-l:$(d)/$(PF)/$(libdir):$(d_lib)/$(PF)/$(libdir):$(d_jlib)/$(PF)/$(libdir):$(d_lgcc)/lib \
+		-p$(p_jdev)
+endif
+	echo $(p_jdev) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libgcjdbg: $(install_stamp) $(binary_stamp)-java $(binary_stamp)-libgcjdev $(binary_stamp)-gcjjre
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	debian/dh_doclink -p$(p_jdbg) $(p_jbase)
+
+	for i in libgij libgcj libgcj-tools; do \
+	  if [ -f $(d_jdbg)/usr/lib/debug/usr/lib/$$i.so.$(GCJ_SONAME).0.0 ]; then \
+	    ln -sf $$i.so.$(GCJ_SONAME).0.0 \
+	      $(d_jdbg)/usr/lib/debug/usr/lib/$$i.so.$(GCJ_SONAME); \
+	  fi; \
+	done
+#	ln -sf libgconfpeer.so.0.0.0 \
+#	  $(d_jdbg)/usr/lib/debug/$(gcj_vlibdir)/libgconfpeer.so.0
+	echo $(p_jdbg) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-gcjjre: $(install_stamp) $(binary_stamp)-java
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	dh_installdirs -p$(p_jre) $(dirs_jre)
+	$(dh_compat2) dh_movefiles -p$(p_jre)   $(files_jre)
+
+	debian/dh_doclink -p$(p_jre) $(p_jbase)
+	DH_COMPAT=5 dh_strip -p$(p_jre) --dbg-package=$(p_jdbg)
+	echo $(p_jre) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libasan.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libasan.mk
@@ -0,0 +1,76 @@
+$(lib_binaries)  += libasan
+ifeq ($(with_lib64asan),yes)
+  $(lib_binaries)  += lib64asan
+endif
+ifeq ($(with_lib32asan),yes)
+  $(lib_binaries)	+= lib32asan
+endif
+ifeq ($(with_libn32asan),yes)
+  $(lib_binaries)	+= libn32asan
+endif
+ifeq ($(with_libx32asan),yes)
+  $(lib_binaries)	+= libx32asan
+endif
+ifeq ($(with_libhfasan),yes)
+  $(lib_binaries)	+= libhfasan
+endif
+ifeq ($(with_libsfasan),yes)
+  $(lib_binaries)	+= libsfasan
+endif
+
+define __do_asan
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libasan.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l) || echo XXXXXXXXXXXXXX ERROR $(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst asan$(ASAN_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst asan$(ASAN_SONAME),stdc++$(CXX_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_asan = $(call __do_asan,lib$(1)asan$(ASAN_SONAME),$(1))
+
+$(binary_stamp)-libasan: $(install_stamp)
+	$(call do_asan,)
+
+$(binary_stamp)-lib64asan: $(install_stamp)
+	$(call do_asan,64)
+
+$(binary_stamp)-lib32asan: $(install_stamp)
+	$(call do_asan,32)
+
+$(binary_stamp)-libn32asan: $(install_stamp)
+	$(call do_asan,n32)
+
+$(binary_stamp)-libx32asan: $(install_stamp)
+	$(call do_asan,x32)
+
+$(binary_stamp)-libhfasan: $(install_dependencies)
+	$(call do_asan,hf)
+
+$(binary_stamp)-libsfasan: $(install_dependencies)
+	$(call do_asan,sf)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libatomic.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libatomic.mk
@@ -0,0 +1,68 @@
+$(lib_binaries)  += libatomic
+ifeq ($(with_lib64atomic),yes)
+  $(lib_binaries)  += lib64atomic
+endif
+ifeq ($(with_lib32atomic),yes)
+  $(lib_binaries)	+= lib32atomic
+endif
+ifeq ($(with_libn32atomic),yes)
+  $(lib_binaries)	+= libn32atomic
+endif
+ifeq ($(with_libx32atomic),yes)
+  $(lib_binaries)	+= libx32atomic
+endif
+ifeq ($(with_libhfatomic),yes)
+  $(lib_binaries)	+= libhfatomic
+endif
+ifeq ($(with_libsfatomic),yes)
+  $(lib_binaries)	+= libsfatomic
+endif
+
+define __do_atomic
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libatomic.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libatomic.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,,$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_atomic = $(call __do_atomic,lib$(1)atomic$(ATOMIC_SONAME),$(1))
+
+$(binary_stamp)-libatomic: $(install_stamp)
+	$(call do_atomic,)
+
+$(binary_stamp)-lib64atomic: $(install_stamp)
+	$(call do_atomic,64)
+
+$(binary_stamp)-lib32atomic: $(install_stamp)
+	$(call do_atomic,32)
+
+$(binary_stamp)-libn32atomic: $(install_stamp)
+	$(call do_atomic,n32)
+
+$(binary_stamp)-libx32atomic: $(install_stamp)
+	$(call do_atomic,x32)
+
+$(binary_stamp)-libhfatomic: $(install_dependencies)
+	$(call do_atomic,hf)
+
+$(binary_stamp)-libsfatomic: $(install_dependencies)
+	$(call do_atomic,sf)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libcc1.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libcc1.mk
@@ -0,0 +1,31 @@
+ifeq ($(with_libcc1),yes)
+  ifneq ($(DEB_CROSS),yes)
+    arch_binaries  := $(arch_binaries) libcc1
+  endif
+endif
+
+p_cc1	= libcc1-$(CC1_SONAME)
+d_cc1	= debian/$(p_cc1)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libcc1: $(install_dependencies)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_cc1)
+	dh_installdirs -p$(p_cc1) \
+		$(docdir) \
+		$(usr_lib)
+	$(dh_compat2) dh_movefiles -p$(p_cc1) \
+		$(usr_lib)/libcc1.so.*
+
+	debian/dh_doclink -p$(p_cc1) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_cc1)
+
+	dh_strip -p$(p_cc1)
+	dh_makeshlibs -p$(p_cc1)
+	dh_shlibdeps -p$(p_cc1)
+	echo $(p_cc1) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libcilkrts.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libcilkrts.mk
@@ -0,0 +1,76 @@
+$(lib_binaries)  += libcilkrts
+ifeq ($(with_lib64cilkrts),yes)
+  $(lib_binaries)  += lib64cilkrts
+endif
+ifeq ($(with_lib32cilkrts),yes)
+  $(lib_binaries)	+= lib32cilkrts
+endif
+ifeq ($(with_libn32cilkrts),yes)
+  $(lib_binaries)	+= libn32cilkrts
+endif
+ifeq ($(with_libx32cilkrts),yes)
+  $(lib_binaries)	+= libx32cilkrts
+endif
+ifeq ($(with_libhfcilkrts),yes)
+  $(lib_binaries)	+= libhfcilkrts
+endif
+ifeq ($(with_libsfcilkrts),yes)
+  $(lib_binaries)	+= libsfcilkrts
+endif
+
+define __do_cilkrts
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libcilkrts.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libcilkrts.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst cilkrts$(CILKRTS_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst cilkrts$(CILKRTS_SONAME),stdc++$(CXX_SONAME),$(p_l)) \
+		,$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_cilkrts = $(call __do_cilkrts,lib$(1)cilkrts$(CILKRTS_SONAME),$(1))
+
+$(binary_stamp)-libcilkrts: $(install_stamp)
+	$(call do_cilkrts,)
+
+$(binary_stamp)-lib64cilkrts: $(install_stamp)
+	$(call do_cilkrts,64)
+
+$(binary_stamp)-lib32cilkrts: $(install_stamp)
+	$(call do_cilkrts,32)
+
+$(binary_stamp)-libn32cilkrts: $(install_stamp)
+	$(call do_cilkrts,n32)
+
+$(binary_stamp)-libx32cilkrts: $(install_stamp)
+	$(call do_cilkrts,x32)
+
+$(binary_stamp)-libhfcilkrts: $(install_dependencies)
+	$(call do_cilkrts,hf)
+
+$(binary_stamp)-libsfcilkrts: $(install_dependencies)
+	$(call do_cilkrts,sf)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libgcc.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libgcc.mk
@@ -0,0 +1,383 @@
+ifeq ($(with_libgcc),yes)
+  $(lib_binaries)	+= libgcc
+endif
+ifeq ($(with_lib64gcc),yes)
+  $(lib_binaries)	+= lib64gcc
+endif
+ifeq ($(with_lib32gcc),yes)
+  $(lib_binaries)	+= lib32gcc
+endif
+ifeq ($(with_libn32gcc),yes)
+  $(lib_binaries)	+= libn32gcc
+endif
+ifeq ($(with_libx32gcc),yes)
+  $(lib_binaries)	+= libx32gcc
+endif
+ifeq ($(with_libhfgcc),yes)
+  $(lib_binaries)	+= libhfgcc
+endif
+ifeq ($(with_libsfgcc),yes)
+  $(lib_binaries)	+= libsfgcc
+endif
+
+ifneq ($(DEB_STAGE),rtlibs)
+  ifeq ($(with_cdev),yes)
+    $(lib_binaries)  += libgcc-dev
+  endif
+  ifeq ($(with_lib64gccdev),yes)
+    $(lib_binaries)  += lib64gcc-dev
+  endif
+  ifeq ($(with_lib32gccdev),yes)
+    $(lib_binaries)  += lib32gcc-dev
+  endif
+  ifeq ($(with_libn32gccdev),yes)
+    $(lib_binaries)  += libn32gcc-dev
+  endif
+  ifeq ($(with_libx32gccdev),yes)
+    $(lib_binaries)  += libx32gcc-dev
+  endif
+  ifeq ($(with_libhfgccdev),yes)
+    $(lib_binaries)  += libhfgcc-dev
+  endif
+  ifeq ($(with_libsfgccdev),yes)
+    $(lib_binaries)  += libsfgcc-dev
+  endif
+endif
+
+header_files = \
+	$(gcc_lib_dir)/include/std*.h \
+	$(shell for h in \
+		    README features.h arm_fp16.h arm_neon.h loongson.h \
+		    {cpuid,decfloat,float,iso646,limits,mm3dnow,mm_malloc}.h \
+		    {ppu_intrinsics,paired,spu2vmx,vec_types,si2vmx}.h \
+		    {,a,b,e,i,n,p,s,t,w,x}mmintrin.h mmintrin-common.h \
+		    {abm,adx,avx,avx2,bmi,bmi2,f16c,fma,fma4,fxsr,ia32,}intrin.h \
+		    {lwp,lzcnt,popcnt,prfchw,rdseed,rtm,tbm,x86,xop,xsave{,opt},xtest,}intrin.h \
+		    {htm,htmxl,mwaitx,pku,sha,vec}intrin.h \
+		    avx512{bw,er,cd,dq,f,ifma,ifmavl,pf,vlbw,vbmi,vldq,vbmivl,vl}intrin.h \
+		    {clflushopt,clwb,clzero,pcommit,xsavec,xsaves}intrin.h \
+		    {arm_acle,unwind-arm-common,s390intrin}.h \
+		    msa.h \
+		    {cross-stdarg,syslimits,unwind,varargs}.h; \
+		do \
+		  test -e $(d)/$(gcc_lib_dir)/include/$$h \
+		    && echo $(gcc_lib_dir)/include/$$h; \
+		  test -e $(d)/$(gcc_lib_dir)/include-fixed/$$h \
+		    && echo $(gcc_lib_dir)/include-fixed/$$h; \
+		done) \
+	$(shell for d in \
+		  asm bits cilk gnu linux sanitizer $(TARGET_ALIAS) \
+		  $(subst $(DEB_TARGET_GNU_CPU),$(biarch_cpu),$(TARGET_ALIAS)); \
+		do \
+		  test -e $(d)/$(gcc_lib_dir)/include/$$d \
+		    && echo $(gcc_lib_dir)/include/$$d; \
+		  test -e $(d)/$(gcc_lib_dir)/include-fixed/$$d \
+		    && echo $(gcc_lib_dir)/include-fixed/$$d; \
+		done)
+
+ifeq ($(with_libssp),yes)
+    header_files += $(gcc_lib_dir)/include/ssp
+endif
+ifeq ($(with_gomp),yes)
+    header_files += $(gcc_lib_dir)/include/{omp,openacc}.h
+endif
+ifeq ($(with_qmath),yes)
+    header_files += $(gcc_lib_dir)/include/quadmath{,_weak}.h
+endif
+
+ifeq ($(DEB_TARGET_ARCH),ia64)
+    header_files += $(gcc_lib_dir)/include/ia64intrin.h
+endif
+
+ifeq ($(DEB_TARGET_ARCH),m68k)
+    header_files += $(gcc_lib_dir)/include/math-68881.h
+endif
+
+ifeq ($(DEB_TARGET_ARCH),$(findstring $(DEB_TARGET_ARCH),powerpc ppc64 ppc64el powerpcspe))
+    header_files += $(gcc_lib_dir)/include/{altivec.h,ppc-asm.h,spe.h}
+endif
+
+ifeq ($(DEB_TARGET_ARCH),tilegx)
+    header_files += $(gcc_lib_dir)/include/feedback.h
+endif
+
+p_lgcc		= libgcc$(GCC_SONAME)$(cross_lib_arch)
+p_lgccdbg	= libgcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_lgccdev	= libgcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_lgcc		= debian/$(p_lgcc)
+d_lgccdbg	= debian/$(p_lgccdbg)
+d_lgccdev	= debian/$(p_lgccdev)
+
+p_l32gcc	= lib32gcc$(GCC_SONAME)$(cross_lib_arch)
+p_l32gccdbg	= lib32gcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_l32gccdev	= lib32gcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_l32gcc	= debian/$(p_l32gcc)
+d_l32gccdbg	= debian/$(p_l32gccdbg)
+d_l32gccdev	= debian/$(p_l32gccdev)
+
+p_l64gcc	= lib64gcc$(GCC_SONAME)$(cross_lib_arch)
+p_l64gccdbg	= lib64gcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_l64gccdev	= lib64gcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_l64gcc	= debian/$(p_l64gcc)
+d_l64gccdbg	= debian/$(p_l64gccdbg)
+d_l64gccdev	= debian/$(p_l64gccdev)
+
+p_ln32gcc	= libn32gcc$(GCC_SONAME)$(cross_lib_arch)
+p_ln32gccdbg	= libn32gcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_ln32gccdev	= libn32gcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_ln32gcc	= debian/$(p_ln32gcc)
+d_ln32gccdbg	= debian/$(p_ln32gccdbg)
+d_ln32gccdev	= debian/$(p_ln32gccdev)
+
+p_lx32gcc	= libx32gcc$(GCC_SONAME)$(cross_lib_arch)
+p_lx32gccdbg	= libx32gcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_lx32gccdev	= libx32gcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_lx32gcc	= debian/$(p_lx32gcc)
+d_lx32gccdbg	= debian/$(p_lx32gccdbg)
+d_lx32gccdev	= debian/$(p_lx32gccdev)
+
+p_lhfgcc	= libhfgcc$(GCC_SONAME)$(cross_lib_arch)
+p_lhfgccdbg	= libhfgcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_lhfgccdev	= libhfgcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_lhfgcc	= debian/$(p_lhfgcc)
+d_lhfgccdbg	= debian/$(p_lhfgccdbg)
+d_lhfgccdev	= debian/$(p_lhfgccdev)
+
+p_lsfgcc	= libsfgcc$(GCC_SONAME)$(cross_lib_arch)
+p_lsfgccdbg	= libsfgcc$(GCC_SONAME)-dbg$(cross_lib_arch)
+p_lsfgccdev	= libsfgcc-$(BASE_VERSION)-dev$(cross_lib_arch)
+d_lsfgcc	= debian/$(p_lsfgcc)
+d_lsfgccdbg	= debian/$(p_lsfgccdbg)
+d_lsfgccdev	= debian/$(p_lsfgccdev)
+
+# __do_gcc_devels(flavour,package,todir,fromdir)
+define __do_gcc_devels
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	test -n "$(2)"
+	rm -rf debian/$(2)
+	dh_installdirs -p$(2) $(docdir) #TODO
+	dh_installdirs -p$(2) $(3)
+
+	$(call __do_gcc_devels2,$(1),$(2),$(3),$(4))
+
+	debian/dh_doclink -p$(2) $(p_lbase)
+	debian/dh_rmemptydirs -p$(2)
+
+	dh_strip -p$(2)
+	$(cross_shlibdeps) dh_shlibdeps -p$(2)
+	$(call cross_mangle_substvars,$(2))
+	echo $(2) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# __do_gcc_devels2(flavour,package,todir,fromdir)
+define __do_gcc_devels2
+# stage1 builds static libgcc only
+	$(if $(filter $(DEB_STAGE),stage1),,
+		: # libgcc_s.so may be a linker script on some architectures
+		set -e; \
+		if [ -h $(4)/libgcc_s.so ]; then \
+		  rm -f $(4)/libgcc_s.so; \
+		  dh_link -p$(2) /$(libgcc_dir$(1))/libgcc_s.so.$(GCC_SONAME) \
+		    /$(3)/libgcc_s.so; \
+		else \
+		  mv $(4)/libgcc_s.so $(d)/$(3)/libgcc_s.so; \
+		  dh_link -p$(2) /$(libgcc_dir$(1))/libgcc_s.so.$(GCC_SONAME) \
+		    /$(3)/libgcc_s.so.$(GCC_SONAME); \
+		fi; \
+		$(if $(1), dh_link -p$(2) /$(3)/libgcc_s.so \
+		    /$(gcc_lib_dir)/libgcc_s_$(1).so;)
+	)
+	$(dh_compat2) dh_movefiles -p$(2) \
+		$(3)/{libgcc*,libgcov.a,*.o} \
+		$(if $(1),,$(header_files)) # Only move headers for the "main" package
+
+	: # libbacktrace not installed by default
+	$(if $(filter yes, $(with_backtrace)),
+	if [ -f $(buildlibdir)/$(1)/libbacktrace/.libs/libbacktrace.a ]; then \
+	  install -m644 $(buildlibdir)/$(1)/libbacktrace/.libs/libbacktrace.a \
+	      debian/$(2)/$(gcc_lib_dir)/$(1); \
+	fi; \
+	$(if $(1),,
+	if [ -f $(buildlibdir)/libbacktrace/backtrace-supported.h ]; then \
+	  install -m644 $(buildlibdir)/libbacktrace/backtrace-supported.h \
+	    debian/$(2)/$(gcc_lib_dir)/include/; \
+	  install -m644 $(srcdir)/libbacktrace/backtrace.h \
+	    debian/$(2)/$(gcc_lib_dir)/include/; \
+	fi
+	))
+
+	: # If building a flavour, add a lintian override
+	$(if $(1),
+		#TODO: use a file instead of a hacky echo
+		# bu do we want to use one override file (in the source package) per
+		# flavour or not since they are essentially the same?
+		mkdir -p debian/$(2)/usr/share/lintian/overrides
+		echo "$(2) binary: binary-from-other-architecture" \
+			>> debian/$(2)/usr/share/lintian/overrides/$(2)
+	)
+	$(if $(filter yes, $(with_lib$(1)gmath)),
+		$(call install_gcc_lib,libgcc-math,$(GCC_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_libssp)),
+		$(call install_gcc_lib,libssp,$(SSP_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_ssp)),
+		mv $(4)/libssp_nonshared.a debian/$(2)/$(3)/;
+	)
+	$(if $(filter yes, $(with_gomp)),
+		$(call install_gcc_lib,libgomp,$(GOMP_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_itm)),
+		$(call install_gcc_lib,libitm,$(ITM_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_atomic)),
+		$(call install_gcc_lib,libatomic,$(ATOMIC_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_asan)),
+		$(call install_gcc_lib,libasan,$(ASAN_SONAME),$(1),$(2))
+		mv $(4)/libasan_preinit.o debian/$(2)/$(3)/;
+	)
+	$(if $(1),,$(if $(filter yes, $(with_lsan)),
+		$(call install_gcc_lib,liblsan,$(LSAN_SONAME),$(1),$(2))
+	))
+	$(if $(1),,$(if $(filter yes, $(with_tsan)),
+		$(call install_gcc_lib,libtsan,$(TSAN_SONAME),$(1),$(2))
+	))
+	$(if $(filter yes, $(with_ubsan)),
+		$(call install_gcc_lib,libubsan,$(UBSAN_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_vtv)),
+		$(call install_gcc_lib,libvtv,$(VTV_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_cilkrts)),
+		$(call install_gcc_lib,libcilkrts,$(CILKRTS_SONAME),$(1),$(2))
+	)
+	$(if $(filter yes, $(with_mpx)),
+	    $(if $(filter x32, $(1)),,
+		$(call install_gcc_lib,libmpxwrappers,$(MPX_SONAME),$(1),$(2))
+		$(call install_gcc_lib,libmpx,$(MPX_SONAME),$(1),$(2))
+	    )
+	)
+	$(if $(filter yes, $(with_qmath)),
+		$(call install_gcc_lib,libquadmath,$(QUADMATH_SONAME),$(1),$(2))
+	)
+endef
+
+# do_gcc_devels(flavour)
+define do_gcc_devels
+	$(call __do_gcc_devels,$(1),$(p_l$(1)gccdev),$(gcc_lib_dir$(1)),$(d)/$(usr_lib$(1)))
+endef
+
+
+define __do_libgcc
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+
+	dh_installdirs -p$(p_l) \
+		$(docdir)/$(p_l) \
+		$(libgcc_dir$(2))
+
+	$(if $(filter yes,$(with_shared_libgcc)),
+		mv $(d)/$(usr_lib$(2))/libgcc_s.so.$(GCC_SONAME) \
+			$(d_l)/$(libgcc_dir$(2))/.
+	)
+
+	debian/dh_doclink -p$(p_l) $(if $(3),$(3),$(p_lbase))
+	debian/dh_doclink -p$(p_d) $(if $(3),$(3),$(p_lbase))
+	debian/dh_rmemptydirs -p$(p_l)
+	debian/dh_rmemptydirs -p$(p_d)
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+
+	# see Debian #533843 for the __aeabi symbol handling; this construct is
+	# just to include the symbols for dpkg versions older than 1.15.3 which
+	# didn't allow bypassing the symbol blacklist
+	$(if $(filter yes,$(with_shared_libgcc)),
+		$(if $(findstring gcc1,$(p_l)), \
+		ln -sf libgcc.symbols debian/$(p_l).symbols \
+		)
+		$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l) -p$(p_d) \
+			-- -v$(DEB_LIBGCC_VERSION) -a$(call mlib_to_arch,$(2)) || echo XXXXXXXXXXXXXX ERROR $(p_l)
+		$(call cross_mangle_shlibs,$(p_l))
+		$(if $(filter arm-linux-gnueabi%,$(DEB_TARGET_GNU_TYPE)),
+			if head -1 $(d_l)/DEBIAN/symbols 2>/dev/null | grep -q '^lib'; then \
+			  grep -q '^ __aeabi' $(d_l)/DEBIAN/symbols \
+			    || cat debian/libgcc.symbols.aeabi \
+				>> $(d_l)/DEBIAN/symbols; \
+			fi
+		)
+	)
+
+	$(if $(DEB_STAGE),,
+	    $(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,,$(2))
+	)
+	$(call cross_mangle_substvars,$(p_l))
+
+	$(if $(2),,	# only for native
+		mkdir -p $(d_l)/usr/share/lintian/overrides
+		echo '$(p_l): package-name-doesnt-match-sonames' \
+			> $(d_l)/usr/share/lintian/overrides/$(p_l)
+	)
+
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries).epoch
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+do_libgcc = $(call __do_libgcc,lib$(1)gcc$(GCC_SONAME),$(1),$(2))
+# ----------------------------------------------------------------------
+
+$(binary_stamp)-libgcc: $(install_dependencies)
+ifeq ($(with_standalone_gcj),yes)
+	$(call do_libgcc,,$(p_jbase))
+else
+	$(call do_libgcc,,)
+endif
+
+$(binary_stamp)-lib64gcc: $(install_dependencies)
+	$(call do_libgcc,64,)
+
+$(binary_stamp)-lib32gcc: $(install_dependencies)
+	$(call do_libgcc,32,)
+
+$(binary_stamp)-libn32gcc: $(install_dependencies)
+	$(call do_libgcc,n32,)
+
+$(binary_stamp)-libx32gcc: $(install_dependencies)
+	$(call do_libgcc,x32,)
+
+$(binary_stamp)-libhfgcc: $(install_dependencies)
+	$(call do_libgcc,hf)
+
+$(binary_stamp)-libsfgcc: $(install_dependencies)
+	$(call do_libgcc,sf)
+
+$(binary_stamp)-libgcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,)
+
+$(binary_stamp)-lib64gcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,64)
+
+$(binary_stamp)-lib32gcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,32)
+
+$(binary_stamp)-libn32gcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,n32)
+
+$(binary_stamp)-libx32gcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,x32)
+
+$(binary_stamp)-libhfgcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,hf)
+
+$(binary_stamp)-libsfgcc-dev: $(install_dependencies)
+	$(call do_gcc_devels,sf)
+
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libgccjit.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libgccjit.mk
@@ -0,0 +1,89 @@
+ifeq ($(with_libgccjit),yes)
+  $(lib_binaries)  += libgccjit
+endif
+
+$(lib_binaries)  += libgccjitdev
+
+ifneq ($(DEB_CROSS),yes)
+  indep_binaries := $(indep_binaries) libgccjitdoc
+endif
+
+p_jitlib	= libgccjit$(GCCJIT_SONAME)
+p_jitdbg	= libgccjit$(GCCJIT_SONAME)-dbg
+p_jitdev	= libgccjit$(pkg_ver)-dev
+p_jitdoc	= libgccjit$(pkg_ver)-doc
+
+d_jitlib	= debian/$(p_jitlib)
+d_jitdev	= debian/$(p_jitdev)
+d_jitdbg	= debian/$(p_jitdbg)
+d_jitdoc	= debian/$(p_jitdoc)
+
+$(binary_stamp)-libgccjit: $(install_jit_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_jitlib) $(d_jitdbg)
+	dh_installdirs -p$(p_jitlib) \
+		$(usr_lib)
+	dh_installdirs -p$(p_jitdbg)
+
+	$(dh_compat2) dh_movefiles -p$(p_jitlib) \
+		$(usr_lib)/libgccjit.so.*
+	rm -f $(d)/$(usr_lib)/libgccjit.so
+
+	debian/dh_doclink -p$(p_jitlib) $(p_base)
+	debian/dh_doclink -p$(p_jitdbg) $(p_base)
+
+	dh_strip -p$(p_jitlib) --dbg-package=$(p_jitdbg)
+	$(cross_makeshlibs) dh_makeshlibs -p$(p_jitlib)
+	$(call cross_mangle_shlibs,$(p_jitlib))
+	$(ignshld)$(cross_shlibdeps) dh_shlibdeps -p$(p_jitlib) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_jitlib))
+	echo $(p_jitlib) $(p_jitdbg) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+	touch $@
+
+$(binary_stamp)-libgccjitdev: $(install_jit_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_jitdev)
+	dh_installdirs -p$(p_jitdev) \
+		$(usr_lib) \
+		$(gcc_lib_dir)/include
+
+	rm -f $(d)/$(usr_lib)/libgccjit.so
+
+	$(dh_compat2) dh_movefiles -p$(p_jitdev) \
+		$(gcc_lib_dir)/include/libgccjit*.h
+	dh_link -p$(p_jitdev) \
+		$(usr_lib)/libgccjit.so.$(GCCJIT_SONAME) $(gcc_lib_dir)/libgccjit.so
+
+	debian/dh_doclink -p$(p_jitdev) $(p_base)
+
+	echo $(p_jitdev) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+	touch $@
+
+$(binary_stamp)-libgccjitdoc: $(install_jit_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_jitdoc)
+	dh_installdirs -p$(p_jitdoc) \
+		$(PF)/share/info
+
+	$(dh_compat2) dh_movefiles -p$(p_jitdoc) \
+		$(PF)/share/info/libgccjit*
+
+	debian/dh_doclink -p$(p_jitdoc) $(p_base)
+	echo $(p_jitdoc) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+	touch $@
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libgomp.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libgomp.mk
@@ -0,0 +1,68 @@
+$(lib_binaries)  += libgomp
+ifeq ($(with_lib64gomp),yes)
+  $(lib_binaries)  += lib64gomp
+endif
+ifeq ($(with_lib32gomp),yes)
+  $(lib_binaries)	+= lib32gomp
+endif
+ifeq ($(with_libn32gomp),yes)
+  $(lib_binaries)	+= libn32gomp
+endif
+ifeq ($(with_libx32gomp),yes)
+  $(lib_binaries)	+= libx32gomp
+endif
+ifeq ($(with_libhfgomp),yes)
+  $(lib_binaries)	+= libhfgomp
+endif
+ifeq ($(with_libsfgomp),yes)
+  $(lib_binaries)	+= libsfgomp
+endif
+
+define __do_gomp
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libgomp.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libgomp.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,$(subst gomp$(GOMP_SONAME),gcc$(GCC_SONAME),$(p_l)),$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_gomp = $(call __do_gomp,lib$(1)gomp$(GOMP_SONAME),$(1))
+
+$(binary_stamp)-libgomp: $(install_stamp)
+	$(call do_gomp,)
+
+$(binary_stamp)-lib64gomp: $(install_stamp)
+	$(call do_gomp,64)
+
+$(binary_stamp)-lib32gomp: $(install_stamp)
+	$(call do_gomp,32)
+
+$(binary_stamp)-libn32gomp: $(install_stamp)
+	$(call do_gomp,n32)
+
+$(binary_stamp)-libx32gomp: $(install_stamp)
+	$(call do_gomp,x32)
+
+$(binary_stamp)-libhfgomp: $(install_dependencies)
+	$(call do_gomp,hf)
+
+$(binary_stamp)-libsfgomp: $(install_dependencies)
+	$(call do_gomp,sf)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libitm.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libitm.mk
@@ -0,0 +1,68 @@
+$(lib_binaries)  += libitm
+ifeq ($(with_lib64itm),yes)
+  $(lib_binaries)  += lib64itm
+endif
+ifeq ($(with_lib32itm),yes)
+  $(lib_binaries)	+= lib32itm
+endif
+ifeq ($(with_libn32itm),yes)
+  $(lib_binaries)	+= libn32itm
+endif
+ifeq ($(with_libx32itm),yes)
+  $(lib_binaries)	+= libx32itm
+endif
+ifeq ($(with_libhfitm),yes)
+  $(lib_binaries)	+= libhfitm
+endif
+ifeq ($(with_libsfitm),yes)
+  $(lib_binaries)	+= libsfitm
+endif
+
+define __do_itm
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libitm.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libitm.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,,$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_itm = $(call __do_itm,lib$(1)itm$(ITM_SONAME),$(1))
+
+$(binary_stamp)-libitm: $(install_stamp)
+	$(call do_itm,)
+
+$(binary_stamp)-lib64itm: $(install_stamp)
+	$(call do_itm,64)
+
+$(binary_stamp)-lib32itm: $(install_stamp)
+	$(call do_itm,32)
+
+$(binary_stamp)-libn32itm: $(install_stamp)
+	$(call do_itm,n32)
+
+$(binary_stamp)-libx32itm: $(install_stamp)
+	$(call do_itm,x32)
+
+$(binary_stamp)-libhfitm: $(install_dependencies)
+	$(call do_itm,hf)
+
+$(binary_stamp)-libsfitm: $(install_dependencies)
+	$(call do_itm,sf)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-liblsan.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-liblsan.mk
@@ -0,0 +1,76 @@
+$(lib_binaries)  += liblsan
+ifeq ($(with_lib64lsan),yes)
+  $(lib_binaries)  += lib64lsan
+endif
+ifeq ($(with_lib32lsan),yes)
+  $(lib_binaries)	+= lib32lsan
+endif
+ifeq ($(with_libn32lsan),yes)
+  $(lib_binaries)	+= libn32lsan
+endif
+ifeq ($(with_libx32lsan),yes)
+  $(lib_binaries)	+= libx32lsan
+endif
+ifeq ($(with_libhflsan),yes)
+  $(lib_binaries)	+= libhflsan
+endif
+ifeq ($(with_libsflsan),yes)
+  $(lib_binaries)	+= libsflsan
+endif
+
+define __do_lsan
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/liblsan.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst lsan$(LSAN_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst lsan$(LSAN_SONAME),stdc++$(CXX_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_lsan = $(call __do_lsan,lib$(1)lsan$(LSAN_SONAME),$(1))
+
+$(binary_stamp)-liblsan: $(install_stamp)
+	$(call do_lsan,)
+
+$(binary_stamp)-lib64lsan: $(install_stamp)
+	$(call do_lsan,64)
+
+$(binary_stamp)-lib32lsan: $(install_stamp)
+	$(call do_lsan,32)
+
+$(binary_stamp)-libn32lsan: $(install_stamp)
+	$(call do_lsan,n32)
+
+$(binary_stamp)-libx32lsan: $(install_stamp)
+	$(call do_lsan,x32)
+
+$(binary_stamp)-libhflsan: $(install_dependencies)
+	$(call do_lsan,hf)
+
+$(binary_stamp)-libsflsan: $(install_dependencies)
+	$(call do_lsan,sf)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libmpx.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libmpx.mk
@@ -0,0 +1,78 @@
+$(lib_binaries)  += libmpx
+ifeq ($(with_lib64mpx),yes)
+  $(lib_binaries)  += lib64mpx
+endif
+ifeq ($(with_lib32mpx),yes)
+  $(lib_binaries)	+= lib32mpx
+endif
+ifeq ($(with_libn32mpx),yes)
+  $(lib_binaries)	+= libn32mpx
+endif
+ifeq ($(with_libx32mpx),yes)
+  $(lib_binaries)	+= libx32mpx
+endif
+ifeq ($(with_libhfmpx),yes)
+  $(lib_binaries)	+= libhfmpx
+endif
+ifeq ($(with_libsfmpx),yes)
+  $(lib_binaries)	+= libsfmpx
+endif
+
+define __do_mpx
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(usr_lib$(2))/libmpx.so.* \
+		$(usr_lib$(2))/libmpxwrappers.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libmpx.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst mpx$(MPX_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_mpx = $(call __do_mpx,lib$(1)mpx$(MPX_SONAME),$(1))
+
+$(binary_stamp)-libmpx: $(install_stamp)
+	$(call do_mpx,)
+
+$(binary_stamp)-lib64mpx: $(install_stamp)
+	$(call do_mpx,64)
+
+$(binary_stamp)-lib32mpx: $(install_stamp)
+	$(call do_mpx,32)
+
+$(binary_stamp)-libn32mpx: $(install_stamp)
+	$(call do_mpx,n32)
+
+$(binary_stamp)-libx32mpx: $(install_stamp)
+	$(call do_mpx,x32)
+
+$(binary_stamp)-libhfmpx: $(install_dependencies)
+	$(call do_mpx,hf)
+
+$(binary_stamp)-libsfmpx: $(install_dependencies)
+	$(call do_mpx,sf)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libobjc.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libobjc.mk
@@ -0,0 +1,161 @@
+ifeq ($(with_libobjc),yes)
+  $(lib_binaries) += libobjc
+endif
+ifeq ($(with_objcdev),yes)
+  $(lib_binaries) += libobjc-dev
+endif
+ifeq ($(with_lib64objc),yes)
+  $(lib_binaries)	+= lib64objc
+endif
+ifeq ($(with_lib64objcdev),yes)
+  $(lib_binaries)	+= lib64objc-dev
+endif
+ifeq ($(with_lib32objc),yes)
+  $(lib_binaries)	+= lib32objc
+endif
+ifeq ($(with_lib32objcdev),yes)
+  $(lib_binaries)	+= lib32objc-dev
+endif
+ifeq ($(with_libn32objc),yes)
+  $(lib_binaries)	+= libn32objc
+endif
+ifeq ($(with_libn32objcdev),yes)
+  $(lib_binaries)	+= libn32objc-dev
+endif
+ifeq ($(with_libx32objc),yes)
+  $(lib_binaries)	+= libx32objc
+endif
+ifeq ($(with_libx32objcdev),yes)
+  $(lib_binaries)	+= libx32objc-dev
+endif
+ifeq ($(with_libhfobjc),yes)
+  $(lib_binaries)	+= libhfobjc
+endif
+ifeq ($(with_libhfobjcdev),yes)
+  $(lib_binaries)	+= libhfobjc-dev
+endif
+ifeq ($(with_libsfobjc),yes)
+  $(lib_binaries)	+= libsfobjc
+endif
+ifeq ($(with_libsfobjcdev),yes)
+  $(lib_binaries)	+= libsfobjc-dev
+endif
+
+files_lobjcdev= \
+	$(gcc_lib_dir)/include/objc
+
+files_lobjc = \
+	$(usr_lib$(2))/libobjc.so.*
+ifeq ($(with_objc_gc),yes)
+  files_lobjc += \
+	$(usr_lib$(2))/libobjc_gc.so.*
+endif
+
+define __do_libobjc
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) \
+		$(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(files_lobjc)
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	rm -f debian/$(p_l).symbols
+	$(if $(2),
+	  ln -sf libobjc.symbols debian/$(p_l).symbols ,
+	  fgrep -v libobjc.symbols.gc debian/libobjc.symbols > debian/$(p_l).symbols
+	)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l) \
+		-- -a$(call mlib_to_arch,$(2)) || echo XXXXXXXXXXXXXX ERROR $(p_l)
+	rm -f debian/$(p_l).symbols
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,$(subst objc$(OBJC_SONAME),gcc$(GCC_SONAME),$(p_l)),$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+
+define __do_libobjc_dev
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l)
+	dh_installdirs -p$(p_l) \
+		$(gcc_lib_dir$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(files_lobjcdev)
+
+	$(call install_gcc_lib,libobjc,$(OBJC_SONAME),$(2),$(p_l))
+	$(if $(filter yes,$(with_objc_gc)),
+	  $(if $(2),,
+		dh_link -p$(p_l) \
+		  /$(usr_lib$(2))/libobjc_gc.so.$(OBJC_SONAME) \
+		  /$(gcc_lib_dir$(2))/libobjc_gc.so
+	))
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	echo $(p_l) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+
+
+# ----------------------------------------------------------------------
+
+do_libobjc = $(call __do_libobjc,lib$(1)objc$(OBJC_SONAME),$(1))
+do_libobjc_dev = $(call __do_libobjc_dev,lib$(1)objc-$(BASE_VERSION)-dev,$(1))
+
+$(binary_stamp)-libobjc: $(install_stamp)
+	$(call do_libobjc,)
+
+$(binary_stamp)-lib64objc: $(install_stamp)
+	$(call do_libobjc,64)
+
+$(binary_stamp)-lib32objc: $(install_stamp)
+	$(call do_libobjc,32)
+
+$(binary_stamp)-libn32objc: $(install_stamp)
+	$(call do_libobjc,n32)
+
+$(binary_stamp)-libx32objc: $(install_stamp)
+	$(call do_libobjc,x32)
+
+$(binary_stamp)-libhfobjc: $(install_stamp)
+	$(call do_libobjc,hf)
+
+$(binary_stamp)-libsfobjc: $(install_stamp)
+	$(call do_libobjc,sf)
+
+
+$(binary_stamp)-libobjc-dev: $(install_stamp)
+	$(call do_libobjc_dev,)
+
+$(binary_stamp)-lib64objc-dev: $(install_stamp)
+	$(call do_libobjc_dev,64)
+
+$(binary_stamp)-lib32objc-dev: $(install_stamp)
+	$(call do_libobjc_dev,32)
+
+$(binary_stamp)-libx32objc-dev: $(install_stamp)
+	$(call do_libobjc_dev,x32)
+
+$(binary_stamp)-libn32objc-dev: $(install_stamp)
+	$(call do_libobjc_dev,n32)
+
+$(binary_stamp)-libhfobjc-dev: $(install_stamp)
+	$(call do_libobjc_dev,hf)
+
+$(binary_stamp)-libsfobjc-dev: $(install_stamp)
+	$(call do_libobjc_dev,sf)
+
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libquadmath.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libquadmath.mk
@@ -0,0 +1,68 @@
+$(lib_binaries)  += libqmath
+ifeq ($(with_lib64qmath),yes)
+  $(lib_binaries)  += lib64qmath
+endif
+ifeq ($(with_lib32qmath),yes)
+  $(lib_binaries)	+= lib32qmath
+endif
+ifeq ($(with_libn32qmath),yes)
+  $(lib_binaries)	+= libn32qmath
+endif
+ifeq ($(with_libx32qmath),yes)
+  $(lib_binaries)	+= libx32qmath
+endif
+ifeq ($(with_libhfqmath),yes)
+  $(lib_binaries)	+= libhfqmath
+endif
+ifeq ($(with_libsfqmath),yes)
+  $(lib_binaries)	+= libsfqmath
+endif
+
+define __do_qmath
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libquadmath.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	ln -sf libquadmath.symbols debian/$(p_l).symbols
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,,$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_qmath = $(call __do_qmath,lib$(1)quadmath$(QUADMATH_SONAME),$(1))
+
+$(binary_stamp)-libqmath: $(install_stamp)
+	$(call do_qmath,)
+
+$(binary_stamp)-lib64qmath: $(install_stamp)
+	$(call do_qmath,64)
+
+$(binary_stamp)-lib32qmath: $(install_stamp)
+	$(call do_qmath,32)
+
+$(binary_stamp)-libn32qmath: $(install_stamp)
+	$(call do_qmath,n32)
+
+$(binary_stamp)-libx32qmath: $(install_stamp)
+	$(call do_qmath,x32)
+
+$(binary_stamp)-libhfqmath: $(install_stamp)
+	$(call do_qmath,hf)
+
+$(binary_stamp)-libsfqmath: $(install_stamp)
+	$(call do_qmath,sf)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libssp.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libssp.mk
@@ -0,0 +1,155 @@
+arch_binaries  := $(arch_binaries) libssp
+ifeq ($(with_lib64ssp),yes)
+  arch_binaries  := $(arch_binaries) lib64ssp
+endif
+ifeq ($(with_lib32ssp),yes)
+  arch_binaries	:= $(arch_binaries) lib32ssp
+endif
+ifeq ($(with_libn32ssp),yes)
+  arch_binaries	:= $(arch_binaries) libn32ssp
+endif
+ifeq ($(with_libx32ssp),yes)
+  arch_binaries := $(arch_binaries) libx32ssp
+endif
+
+p_ssp	= libssp$(SSP_SONAME)
+p_ssp32	= lib32ssp$(SSP_SONAME)
+p_ssp64	= lib64ssp$(SSP_SONAME)
+p_sspx32 = libx32ssp$(SSP_SONAME)
+p_sspd	= libssp$(SSP_SONAME)-dev
+
+d_ssp	= debian/$(p_ssp)
+d_ssp32	= debian/$(p_ssp32)
+d_ssp64	= debian/$(p_ssp64)
+d_sspx32 = debian/$(p_sspx32)
+d_sspd	= debian/$(p_sspd)
+
+dirs_ssp = \
+	$(docdir)/$(p_base) \
+	$(PF)/$(libdir)
+files_ssp = \
+	$(PF)/$(libdir)/libssp.so.*
+
+dirs_sspd = \
+	$(docdir) \
+	$(PF)/include \
+	$(PF)/$(libdir)
+files_sspd = \
+	$(gcc_lib_dir)/include/ssp \
+	$(PF)/$(libdir)/libssp.{a,so} \
+	$(PF)/$(libdir)/libssp_nonshared.a
+
+ifeq ($(with_lib32ssp),yes)
+	dirs_sspd  += $(lib32)
+	files_sspd += $(lib32)/libssp.{a,so}
+	files_sspd += $(lib32)/libssp_nonshared.a
+endif
+ifeq ($(with_lib64ssp),yes)
+	dirs_sspd  += $(PF)/lib64
+	files_sspd += $(PF)/lib64/libssp.{a,so}
+	files_sspd += $(PF)/lib64/libssp_nonshared.a
+endif
+
+$(binary_stamp)-libssp: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_ssp)
+	dh_installdirs -p$(p_ssp)
+
+	$(dh_compat2) dh_movefiles -p$(p_ssp) $(files_ssp)
+	debian/dh_doclink -p$(p_ssp) $(p_lbase)
+
+	debian/dh_rmemptydirs -p$(p_ssp)
+
+	dh_strip -p$(p_ssp)
+	dh_makeshlibs $(ldconfig_arg) -p$(p_ssp) -V '$(p_ssp) (>= $(DEB_SOVERSION))'
+	dh_shlibdeps -p$(p_ssp)
+	echo $(p_ssp) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-lib64ssp: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_ssp64)
+	dh_installdirs -p$(p_ssp64) \
+		$(PF)/lib64
+	$(dh_compat2) dh_movefiles -p$(p_ssp64) \
+		$(PF)/lib64/libssp.so.*
+
+	debian/dh_doclink -p$(p_ssp64) $(p_lbase)
+
+	dh_strip -p$(p_ssp64)
+	dh_makeshlibs $(ldconfig_arg) -p$(p_ssp64) -V '$(p_ssp64) (>= $(DEB_SOVERSION))'
+#	dh_shlibdeps -p$(p_ssp64)
+	echo $(p_ssp64) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-lib32ssp: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_ssp32)
+	dh_installdirs -p$(p_ssp32) \
+		$(lib32)
+	$(dh_compat2) dh_movefiles -p$(p_ssp32) \
+		$(lib32)/libssp.so.*
+
+	debian/dh_doclink -p$(p_ssp32) $(p_lbase)
+
+	dh_strip -p$(p_ssp32)
+	dh_makeshlibs $(ldconfig_arg) -p$(p_ssp32) -V '$(p_ssp32) (>= $(DEB_SOVERSION))'
+#	dh_shlibdeps -p$(p_ssp32)
+	echo $(p_ssp32) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libn32ssp: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_sspn32)
+	dh_installdirs -p$(p_sspn32) \
+		$(PF)/$(libn32)
+	$(dh_compat2) dh_movefiles -p$(p_sspn32) \
+		$(PF)/$(libn32)/libssp.so.*
+
+	debian/dh_doclink -p$(p_sspn32) $(p_lbase)
+
+	dh_strip -p$(p_sspn32)
+	dh_makeshlibs $(ldconfig_arg) -p$(p_sspn32) -V '$(p_sspn32) (>= $(DEB_SOVERSION))'
+#	dh_shlibdeps -p$(p_sspn32)
+	echo $(p_sspn32) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libx32ssp: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_sspx32)
+	dh_installdirs -p$(p_sspx32) \
+		$(PF)/$(libx32)
+	$(dh_compat2) dh_movefiles -p$(p_sspx32) \
+		$(PF)/$(libx32)/libssp.so.*
+
+	debian/dh_doclink -p$(p_sspx32) $(p_lbase)
+
+	dh_strip -p$(p_sspx32)
+	dh_makeshlibs $(ldconfig_arg) -p$(p_sspx32) -V '$(p_sspx32) (>= $(DEB_SOVERSION))'
+#	dh_shlibdeps -p$(p_sspx32)
+	echo $(p_sspx32) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libstdcxx.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libstdcxx.mk
@@ -0,0 +1,527 @@
+ifeq ($(with_libcxx),yes)
+  $(lib_binaries)  += libstdcxx
+endif
+ifeq ($(with_lib64cxx),yes)
+  $(lib_binaries)  += lib64stdcxx
+endif
+ifeq ($(with_lib32cxx),yes)
+  $(lib_binaries)	+= lib32stdcxx
+endif
+ifeq ($(with_libn32cxx),yes)
+  $(lib_binaries)	+= libn32stdcxx
+endif
+ifeq ($(with_libx32cxx),yes)
+  $(lib_binaries)	+= libx32stdcxx
+endif
+ifeq ($(with_libhfcxx),yes)
+  $(lib_binaries)	+= libhfstdcxx
+endif
+ifeq ($(with_libsfcxx),yes)
+  $(lib_binaries)	+= libsfstdcxx
+endif
+
+ifneq ($(DEB_STAGE),rtlibs)
+  ifeq ($(with_lib64cxxdev),yes)
+    $(lib_binaries)	+= lib64stdcxx-dev
+  endif
+  ifeq ($(with_lib64cxxdbg),yes)
+    $(lib_binaries)	+= lib64stdcxxdbg
+  endif
+  ifeq ($(with_lib32cxxdev),yes)
+    $(lib_binaries)	+= lib32stdcxx-dev
+  endif
+  ifeq ($(with_lib32cxxdbg),yes)
+    $(lib_binaries)	+= lib32stdcxxdbg
+  endif
+  ifeq ($(with_libn32cxxdev),yes)
+    $(lib_binaries)	+= libn32stdcxx-dev
+  endif
+  ifeq ($(with_libn32cxxdbg),yes)
+    $(lib_binaries)	+= libn32stdcxxdbg
+  endif
+  ifeq ($(with_libx32cxxdev),yes)
+    $(lib_binaries)	+= libx32stdcxx-dev
+  endif
+  ifeq ($(with_libx32cxxdbg),yes)
+    $(lib_binaries)	+= libx32stdcxxdbg
+  endif
+  ifeq ($(with_libhfcxxdev),yes)
+    $(lib_binaries)	+= libhfstdcxx-dev
+  endif
+  ifeq ($(with_libhfcxxdbg),yes)
+    $(lib_binaries)	+= libhfstdcxxdbg
+  endif
+  ifeq ($(with_libsfcxxdev),yes)
+    $(lib_binaries)	+= libsfstdcxx-dev
+  endif
+  ifeq ($(with_libsfcxxdbg),yes)
+    $(lib_binaries)	+= libsfstdcxxdbg
+  endif
+
+  ifeq ($(with_cxxdev),yes)
+    $(lib_binaries)  += libstdcxx-dev
+    ifneq ($(DEB_CROSS),yes)
+      indep_binaries := $(indep_binaries) libstdcxx-doc
+    endif
+  endif
+endif
+
+libstdc_ext = -$(BASE_VERSION)
+
+p_lib	= libstdc++$(CXX_SONAME)$(cross_lib_arch)
+p_lib64	= lib64stdc++$(CXX_SONAME)$(cross_lib_arch)
+p_lib32	= lib32stdc++$(CXX_SONAME)$(cross_lib_arch)
+p_libn32= libn32stdc++$(CXX_SONAME)$(cross_lib_arch)
+p_libx32= libx32stdc++$(CXX_SONAME)$(cross_lib_arch)
+p_libhf	= libhfstdc++$(CXX_SONAME)$(cross_lib_arch)
+p_libsf	= libsfstdc++$(CXX_SONAME)$(cross_lib_arch)
+p_dev	= libstdc++$(libstdc_ext)-dev$(cross_lib_arch)
+p_pic	= libstdc++$(libstdc_ext)-pic$(cross_lib_arch)
+p_dbg	= libstdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_dbg64	= lib64stdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_dbg32	= lib32stdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_dbgn32= libn32stdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_dbgx32= libx32stdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_dbghf	= libhfstdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_dbgsf	= libsfstdc++$(CXX_SONAME)$(libstdc_ext)-dbg$(cross_lib_arch)
+p_libd	= libstdc++$(libstdc_ext)-doc
+
+d_lib	= debian/$(p_lib)
+d_lib64	= debian/$(p_lib64)
+d_lib32	= debian/$(p_lib32)
+d_libn32= debian/$(p_libn32)
+d_libx32= debian/$(p_libx32)
+d_libhf	= debian/$(p_libhf)
+d_libsf	= debian/$(p_libsf)
+d_dev	= debian/$(p_dev)
+d_pic	= debian/$(p_pic)
+d_dbg	= debian/$(p_dbg)
+d_dbg64	= debian/$(p_dbg64)
+d_dbg32	= debian/$(p_dbg32)
+d_dbghf	= debian/$(p_dbghf)
+d_dbgsf	= debian/$(p_dbgsf)
+d_libd	= debian/$(p_libd)
+
+dirs_dev = \
+	$(docdir)/$(p_base)/C++ \
+	$(usr_lib) \
+	$(gcc_lib_dir)/include \
+	$(PFL)/include/c++
+
+files_dev = \
+	$(PFL)/include/c++/$(BASE_VERSION) \
+	$(gcc_lib_dir)/libstdc++.{a,so} \
+	$(gcc_lib_dir)/libsupc++.a \
+	$(gcc_lib_dir)/libstdc++fs.a
+
+ifeq ($(with_multiarch_cxxheaders),yes)
+  dirs_dev += \
+	$(PF)/include/$(DEB_TARGET_MULTIARCH)/c++/$(BASE_VERSION)
+  files_dev += \
+	$(PF)/include/$(DEB_TARGET_MULTIARCH)/c++/$(BASE_VERSION)/{bits,ext}
+endif
+
+dirs_dbg = \
+	$(docdir) \
+	$(PF)/lib/debug/$(usr_lib) \
+	$(usr_lib)/debug \
+	$(PF)/share/gdb/auto-load/$(usr_lib)/debug \
+	$(gcc_lib_dir)
+files_dbg = \
+	$(usr_lib)/debug/libstdc++.{a,so*} \
+	$(usr_lib)/debug/libstdc++fs.a
+
+dirs_pic = \
+	$(docdir) \
+	$(gcc_lib_dir)
+files_pic = \
+	$(gcc_lib_dir)/libstdc++_pic.a
+
+# ----------------------------------------------------------------------
+
+gxx_baseline_dir = $(shell \
+			sed -n '/^baseline_dir *=/s,.*= *\(.*\)$$,\1,p' \
+			    $(buildlibdir)/libstdc++-v3/testsuite/Makefile)
+gxx_baseline_file = $(gxx_baseline_dir)/baseline_symbols.txt
+
+debian/README.libstdc++-baseline:
+	cat debian/README.libstdc++-baseline.in \
+		> debian/README.libstdc++-baseline
+
+	baseline_name=`basename $(gxx_baseline_dir)`; \
+	baseline_parentdir=`dirname $(gxx_baseline_dir)`; \
+	compat_baseline_name=""; \
+	if [ -f "$(gxx_baseline_file)" ]; then \
+	  ( \
+	    echo "A baseline file for $$baseline_name was found."; \
+	    echo "Running the check-abi script ..."; \
+	    echo ""; \
+	    $(MAKE) -C $(buildlibdir)/libstdc++-v3/testsuite \
+		check-abi; \
+	  ) >> debian/README.libstdc++-baseline; \
+	else \
+	  ( \
+	    echo "No baseline file found for $$baseline_name."; \
+	    echo "Generating a new baseline file ..."; \
+	    echo ""; \
+	  ) >> debian/README.libstdc++-baseline; \
+	  mkdir -p $(gxx_baseline_dir); \
+	  $(MAKE) -C $(buildlibdir)/libstdc++-v3/testsuite new-abi-baseline; \
+	  if [ -f $(gxx_baseline_file) ]; then \
+	    cat $(gxx_baseline_file); \
+	  else \
+	    cat $$(find $(buildlibdir)/libstdc++-v3 $(srcdir)/libstdc++-v3 -name '.new') || true; \
+	  fi >> debian/README.libstdc++-baseline; \
+	fi
+
+# ----------------------------------------------------------------------
+# FIXME: see #792204, libstdc++ symbols on sparc64, for now ignore errors
+# for the 32bit multilib build
+
+define __do_libstdcxx
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l)
+
+	dh_installdirs -p$(p_l) \
+		$(docdir) \
+		$(usr_lib$(2)) \
+		$(PF)/share/gdb/auto-load/$(usr_lib$(2))
+
+	$(if $(DEB_CROSS),,$(if $(2),,
+	dh_installdirs -p$(p_l) \
+		$(PF)/share/gcc-$(BASE_VERSION)/python
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(PF)/share/gcc-$(BASE_VERSION)/python/libstdcxx
+	))
+	cp -p $(d)/$(usr_lib$(2))/libstdc++.so.*.py \
+		$(d_l)/$(PF)/share/gdb/auto-load/$(usr_lib$(2))/.
+	sed -i -e "/^libdir *=/s,=.*,= '/$(usr_lib$(2))'," \
+		$(d_l)/$(PF)/share/gdb/auto-load/$(usr_lib$(2))/libstdc++.so.*.py
+
+	cp -a $(d)/$(usr_lib$(2))/libstdc++.so.*[0-9] \
+		$(d_l)/$(usr_lib$(2))/.
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_rmemptydirs -p$(p_l)
+
+	dh_strip -p$(p_l) $(if $(filter rtlibs,$(DEB_STAGE)),,--dbg-package=$(1)-$(BASE_VERSION)-dbg$(cross_lib_arch))
+
+	$(if $(filter $(DEB_TARGET_ARCH), armel hppa sparc64), \
+	  -$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l) \
+	  @echo "FIXME: libstdc++ not feature complete (https://gcc.gnu.org/ml/gcc/2014-07/msg00000.html)", \
+	  $(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l) \
+	)
+
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,$(subst stdc++$(CXX_SONAME),gcc$(GCC_SONAME),$(p_l)),$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+define __do_libstdcxx_dbg
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_d)
+	dh_installdirs -p$(p_d) \
+		$(PF)/lib/debug/$(usr_lib$(2)) \
+		$(usr_lib$(2))
+
+	$(if $(filter yes,$(with_lib$(2)cxx)),
+		cp -a $(d)/$(usr_lib$(2))/libstdc++.so.*[0-9] \
+			$(d_d)/$(usr_lib$(2))/.;
+		dh_strip -p$(p_d) --keep-debug;
+		$(if $(filter yes,$(with_common_libs)),, # if !with_common_libs
+			# remove the debug symbols for libstdc++
+			# built by a newer version of GCC
+			rm -rf $(d_d)/usr/lib/debug/$(PF);
+		)
+		rm -f $(d_d)/$(usr_lib$(2))/libstdc++.so.*[0-9]
+	)
+
+	$(if $(filter yes,$(with_cxx_debug)),
+		mkdir -p $(d_d)/$(usr_lib$(2))/debug;
+		mv $(d)/$(usr_lib$(2))/debug/libstdc++* $(d_d)/$(usr_lib$(2))/debug;
+		rm -f $(d_d)/$(usr_lib$(2))/debug/libstdc++_pic.a
+	)
+
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_d) \
+		$(call shlibdirs_to_search,$(subst $(pkg_ver),,$(subst stdc++$(CXX_SONAME),gcc$(GCC_SONAME),$(p_l))),$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_d))
+
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+	debian/dh_rmemptydirs -p$(p_d)
+	echo $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+define __do_libstdcxx_dev
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	mv $(d)/$(usr_lib$(2))/libstdc++.a $(d)/$(usr_lib$(2))/libstdc++fs.a $(d)/$(usr_lib$(2))/libsupc++.a \
+		$(d)/$(gcc_lib_dir$(2))/
+
+	rm -rf $(d_l)
+	dh_installdirs -p$(p_l) $(gcc_lib_dir$(2))
+
+	$(dh_compat2) dh_movefiles -p$(p_l) \
+		$(gcc_lib_dir$(2))/libstdc++.a \
+		$(gcc_lib_dir$(2))/libstdc++fs.a \
+		$(gcc_lib_dir$(2))/libsupc++.a \
+		$(if $(with_multiarch_cxxheaders),$(PF)/include/$(DEB_TARGET_MULTIARCH)/c++/$(BASE_VERSION)/$(2))
+	$(call install_gcc_lib,libstdc++,$(CXX_SONAME),$(2),$(p_l))
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_rmemptydirs -p$(p_l)
+	dh_strip -p$(p_l)
+	dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search,$(subst stdc++$(CXX_SONAME),gcc$(GCC_SONAME),$(p_l)),$(2))
+	echo $(p_l) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+do_libstdcxx = $(call __do_libstdcxx,lib$(1)stdc++$(CXX_SONAME),$(1))
+do_libstdcxx_dbg = $(call __do_libstdcxx_dbg,lib$(1)stdc++$(CXX_SONAME)$(libstdc_ext),$(1))
+do_libstdcxx_dev = $(call __do_libstdcxx_dev,lib$(1)stdc++-$(BASE_VERSION)-dev,$(1))
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-libstdcxx: $(install_stamp)
+	$(call do_libstdcxx,)
+
+$(binary_stamp)-lib64stdcxx: $(install_stamp)
+	$(call do_libstdcxx,64)
+
+$(binary_stamp)-lib32stdcxx: $(install_stamp)
+	$(call do_libstdcxx,32)
+
+$(binary_stamp)-libn32stdcxx: $(install_stamp)
+	$(call do_libstdcxx,n32)
+
+$(binary_stamp)-libx32stdcxx: $(install_stamp)
+	$(call do_libstdcxx,x32)
+
+$(binary_stamp)-libhfstdcxx: $(install_stamp)
+	$(call do_libstdcxx,hf)
+
+$(binary_stamp)-libsfstdcxx: $(install_stamp)
+	$(call do_libstdcxx,sf)
+
+$(binary_stamp)-lib64stdcxxdbg: $(install_stamp)
+	$(call do_libstdcxx_dbg,64)
+
+$(binary_stamp)-lib32stdcxxdbg: $(install_stamp)
+	$(call do_libstdcxx_dbg,32)
+
+$(binary_stamp)-libn32stdcxxdbg: $(install_stamp)
+	$(call do_libstdcxx_dbg,n32)
+
+$(binary_stamp)-libx32stdcxxdbg: $(install_stamp)
+	$(call do_libstdcxx_dbg,x32)
+
+$(binary_stamp)-libhfstdcxxdbg: $(install_stamp)
+	$(call do_libstdcxx_dbg,hf)
+
+$(binary_stamp)-libsfstdcxxdbg: $(install_stamp)
+	$(call do_libstdcxx_dbg,sf)
+
+$(binary_stamp)-lib64stdcxx-dev: $(install_stamp)
+	$(call do_libstdcxx_dev,64)
+
+$(binary_stamp)-lib32stdcxx-dev: $(install_stamp)
+	$(call do_libstdcxx_dev,32)
+
+$(binary_stamp)-libn32stdcxx-dev: $(install_stamp)
+	$(call do_libstdcxx_dev,n32)
+
+$(binary_stamp)-libx32stdcxx-dev: $(install_stamp)
+	$(call do_libstdcxx_dev,x32)
+
+$(binary_stamp)-libhfstdcxx-dev: $(install_stamp)
+	$(call do_libstdcxx_dev,hf)
+
+$(binary_stamp)-libsfstdcxx-dev: $(install_stamp)
+	$(call do_libstdcxx_dev,sf)
+
+# ----------------------------------------------------------------------
+libcxxdev_deps = $(install_stamp)
+ifeq ($(with_libcxx),yes)
+  libcxxdev_deps += $(binary_stamp)-libstdcxx
+endif
+ifeq ($(with_check),yes)
+  libcxxdev_deps += debian/README.libstdc++-baseline
+endif
+$(binary_stamp)-libstdcxx-dev: $(libcxxdev_deps)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_dev) $(d_pic)
+	dh_installdirs -p$(p_dev) $(dirs_dev)
+	dh_installdirs -p$(p_pic) $(dirs_pic)
+	dh_installdirs -p$(p_dbg) $(dirs_dbg)
+
+	: # - correct libstdc++-v3 file locations
+	mv $(d)/$(usr_lib)/libsupc++.a $(d)/$(gcc_lib_dir)/
+	mv $(d)/$(usr_lib)/libstdc++fs.a $(d)/$(gcc_lib_dir)/
+	mv $(d)/$(usr_lib)/libstdc++.{a,so} $(d)/$(gcc_lib_dir)/
+	ln -sf ../../../$(DEB_TARGET_GNU_TYPE)/libstdc++.so.$(CXX_SONAME) \
+		$(d)/$(gcc_lib_dir)/libstdc++.so
+	mv $(d)/$(usr_lib)/libstdc++_pic.a $(d)/$(gcc_lib_dir)/
+
+	rm -f $(d)/$(usr_lib)/debug/libstdc++_pic.a
+	rm -f $(d)/$(usr_lib64)/debug/libstdc++_pic.a
+
+	: # remove precompiled headers
+	-find $(d) -type d -name '*.gch' | xargs rm -rf
+
+	for i in $(d)/$(PF)/include/c++/$(GCC_VERSION)/*-linux; do \
+	  if [ -d $$i ]; then mv $$i $$i-gnu; fi; \
+	done
+
+	$(dh_compat2) dh_movefiles -p$(p_dev) $(files_dev)
+	$(dh_compat2) dh_movefiles -p$(p_pic) $(files_pic)
+ifeq ($(with_cxx_debug),yes)
+	$(dh_compat2) dh_movefiles -p$(p_dbg) $(files_dbg)
+endif
+
+	dh_link -p$(p_dev) \
+		/$(usr_lib)/libstdc++.so.$(CXX_SONAME) \
+		/$(gcc_lib_dir)/libstdc++.so \
+		/$(PFL)/include/c++/$(BASE_VERSION) /$(PFL)/include/c++/$(GCC_VERSION)
+ifeq ($(with_multiarch_cxxheaders),yes)
+	dh_link -p$(p_dev) \
+		/$(PFL)/include/$(DEB_TARGET_MULTIARCH)/c++/$(BASE_VERSION) \
+		/$(PFL)/include/$(DEB_TARGET_MULTIARCH)/c++/$(GCC_VERSION)
+endif
+
+	debian/dh_doclink -p$(p_dev) $(p_lbase)
+	debian/dh_doclink -p$(p_pic) $(p_lbase)
+	debian/dh_doclink -p$(p_dbg) $(p_lbase)
+	cp -p $(srcdir)/libstdc++-v3/ChangeLog \
+		$(d_dev)/$(docdir)/$(p_base)/C++/changelog.libstdc++
+ifeq ($(with_check),yes)
+	cp -p debian/README.libstdc++-baseline \
+		$(d_dev)/$(docdir)/$(p_base)/C++/README.libstdc++-baseline.$(DEB_TARGET_ARCH)
+	if [ -f $(buildlibdir)/libstdc++-v3/testsuite/current_symbols.txt ]; \
+	then \
+	  cp -p $(buildlibdir)/libstdc++-v3/testsuite/current_symbols.txt \
+	    $(d_dev)/$(docdir)/$(p_base)/C++/libstdc++_symbols.txt.$(DEB_TARGET_ARCH); \
+	fi
+endif
+	cp -p $(buildlibdir)/libstdc++-v3/src/libstdc++-symbols.ver \
+		$(d_pic)/$(gcc_lib_dir)/libstdc++_pic.map
+
+	cp -p $(d)/$(usr_lib)/libstdc++.so.*.py \
+		$(d_dbg)/$(PF)/share/gdb/auto-load/$(usr_lib)/debug/.
+	sed -i -e "/^libdir *=/s,=.*,= '/$(usr_lib)'," \
+		$(d_dbg)/$(PF)/share/gdb/auto-load/$(usr_lib)/debug/libstdc++.so.*.py
+
+ifeq ($(with_libcxx),yes)
+	cp -a $(d)/$(usr_lib)/libstdc++.so.*[0-9] \
+		$(d_dbg)/$(usr_lib)/
+	dh_strip -p$(p_dbg) --keep-debug
+	rm -f $(d_dbg)/$(usr_lib)/libstdc++.so.*[0-9]
+endif
+
+	dh_strip -p$(p_dev) --dbg-package=$(p_dbg)
+ifneq ($(with_common_libs),yes)
+	: # remove the debug symbols for libstdc++ built by a newer version of GCC
+	rm -rf $(d_dbg)/usr/lib/debug/$(PF)
+endif
+	dh_strip -p$(p_pic)
+
+ifeq ($(with_cxxdev),yes)
+	debian/dh_rmemptydirs -p$(p_dev)
+	debian/dh_rmemptydirs -p$(p_pic)
+	debian/dh_rmemptydirs -p$(p_dbg)
+endif
+
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_dev) -p$(p_pic) -p$(p_dbg) \
+		$(call shlibdirs_to_search,,) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_dbg))
+	echo $(p_dev) $(p_pic) $(p_dbg) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+# ----------------------------------------------------------------------
+
+doxygen_doc_dir = $(buildlibdir)/libstdc++-v3/doc
+
+doxygen-docs: $(build_doxygen_stamp)
+$(build_doxygen_stamp): $(build_stamp)
+	$(MAKE) -C $(buildlibdir)/libstdc++-v3/doc SHELL=/bin/bash doc-html-doxygen
+	$(MAKE) -C $(buildlibdir)/libstdc++-v3/doc SHELL=/bin/bash doc-man-doxygen
+	-find $(doxygen_doc_dir)/doxygen/html -name 'struct*' -empty | xargs rm -f
+
+	touch $@
+
+$(binary_stamp)-libstdcxx-doc: $(install_stamp) doxygen-docs
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_libd)
+	dh_installdirs -p$(p_libd) \
+		$(docdir)/$(p_base)/libstdc++ \
+		$(PF)/share/man
+
+#	debian/dh_doclink -p$(p_libd) $(p_base)
+	dh_link -p$(p_libd) /usr/share/doc/$(p_base) /usr/share/doc/$(p_libd)
+	dh_installdocs -p$(p_libd)
+	rm -f $(d_libd)/$(docdir)/$(p_base)/copyright
+
+	cp -a $(srcdir)/libstdc++-v3/doc/html/* \
+		$(d_libd)/$(docdir)/$(p_base)/libstdc++/.
+	cp -a $(doxygen_doc_dir)/doxygen/html \
+		$(d_libd)/$(docdir)/$(p_base)/libstdc++/user
+	find $(d_libd)/$(docdir)/$(p_base)/libstdc++ -name '*.md5' \
+		| xargs -r rm -f
+
+# Broken docs ... see #766499
+#	rm -f $(d_libd)/$(docdir)/$(p_base)/libstdc++/*/jquery.js
+#	dh_link -p$(p_libd) \
+#		/usr/share/javascript/jquery/jquery.js \
+#		/$(docdir)/$(p_base)/libstdc++/html/jquery.js \
+#		/usr/share/javascript/jquery/jquery.js \
+#		/$(docdir)/$(p_base)/libstdc++/user/jquery.js
+
+	: FIXME: depending on the doxygen version
+	if [ -d $(doxygen_doc_dir)/doxygen/man/man3cxx ]; then \
+	  cp -a $(doxygen_doc_dir)/doxygen/man/man3cxx \
+	    $(d_libd)/$(PF)/share/man/man3; \
+	  if [ -d $(doxygen_doc_dir)/doxygen/man/man3 ]; then \
+	    cp -a $(doxygen_doc_dir)/doxygen/man/man3/* \
+	      $(d_libd)/$(PF)/share/man/man3/; \
+	  fi; \
+	elif [ -d $(doxygen_doc_dir)/doxygen/man/man3 ]; then \
+	  cp -a $(doxygen_doc_dir)/doxygen/man/man3 \
+	    $(d_libd)/$(PF)/share/man/man3; \
+	fi
+
+	for i in $(d_libd)/$(PF)/share/man/man3/*.3; do \
+	  [ -f $${i} ] || continue; \
+	  mv $${i} $${i}cxx; \
+	done
+	rm -f $(d_libd)/$(PF)/share/man/man3/todo.3*
+
+	mkdir -p $(d_libd)/usr/share/lintian/overrides
+	cp -p debian/$(p_libd).overrides \
+		$(d_libd)/usr/share/lintian/overrides/$(p_libd)
+
+	echo $(p_libd) >> debian/indep_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libtsan.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libtsan.mk
@@ -0,0 +1,78 @@
+$(lib_binaries)  += libtsan
+ifeq (0,1)
+ifeq ($(with_lib64tsan),yes)
+  $(lib_binaries)  += lib64tsan
+endif
+ifeq ($(with_lib32tsan),yes)
+  $(lib_binaries)	+= lib32tsan
+endif
+ifeq ($(with_libn32tsan),yes)
+  $(lib_binaries)	+= libn32tsan
+endif
+ifeq ($(with_libx32tsan),yes)
+  $(lib_binaries)	+= libx32tsan
+endif
+ifeq ($(with_libhftsan),yes)
+  $(lib_binaries)	+= libhftsan
+endif
+ifeq ($(with_libsftsan),yes)
+  $(lib_binaries)	+= libsftsan
+endif
+endif
+
+define __do_tsan
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libtsan.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst tsan$(TSAN_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst tsan$(TSAN_SONAME),stdc++$(CXX_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_tsan = $(call __do_tsan,lib$(1)tsan$(TSAN_SONAME),$(1))
+
+$(binary_stamp)-libtsan: $(install_stamp)
+	$(call do_tsan,)
+
+$(binary_stamp)-lib64tsan: $(install_stamp)
+	$(call do_tsan,64)
+
+$(binary_stamp)-lib32tsan: $(install_stamp)
+	$(call do_tsan,32)
+
+$(binary_stamp)-libn32tsan: $(install_stamp)
+	$(call do_tsan,n32)
+
+$(binary_stamp)-libx32tsan: $(install_stamp)
+	$(call do_tsan,x32)
+
+$(binary_stamp)-libhftsan: $(install_dependencies)
+	$(call do_tsan,hf)
+
+$(binary_stamp)-libsftsan: $(install_dependencies)
+	$(call do_tsan,sf)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libubsan.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libubsan.mk
@@ -0,0 +1,76 @@
+$(lib_binaries)  += libubsan
+ifeq ($(with_lib64ubsan),yes)
+  $(lib_binaries)  += lib64ubsan
+endif
+ifeq ($(with_lib32ubsan),yes)
+  $(lib_binaries)	+= lib32ubsan
+endif
+ifeq ($(with_libn32ubsan),yes)
+  $(lib_binaries)	+= libn32ubsan
+endif
+ifeq ($(with_libx32ubsan),yes)
+  $(lib_binaries)	+= libx32ubsan
+endif
+ifeq ($(with_libhfubsan),yes)
+  $(lib_binaries)	+= libhfubsan
+endif
+ifeq ($(with_libsfubsan),yes)
+  $(lib_binaries)	+= libsfubsan
+endif
+
+define __do_ubsan
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libubsan.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst ubsan$(UBSAN_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst ubsan$(UBSAN_SONAME),stdc++$(CXX_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_ubsan = $(call __do_ubsan,lib$(1)ubsan$(UBSAN_SONAME),$(1))
+
+$(binary_stamp)-libubsan: $(install_stamp)
+	$(call do_ubsan,)
+
+$(binary_stamp)-lib64ubsan: $(install_stamp)
+	$(call do_ubsan,64)
+
+$(binary_stamp)-lib32ubsan: $(install_stamp)
+	$(call do_ubsan,32)
+
+$(binary_stamp)-libn32ubsan: $(install_stamp)
+	$(call do_ubsan,n32)
+
+$(binary_stamp)-libx32ubsan: $(install_stamp)
+	$(call do_ubsan,x32)
+
+$(binary_stamp)-libhfubsan: $(install_dependencies)
+	$(call do_ubsan,hf)
+
+$(binary_stamp)-libsfubsan: $(install_dependencies)
+	$(call do_ubsan,sf)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-libvtv.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-libvtv.mk
@@ -0,0 +1,76 @@
+$(lib_binaries)  += libvtv
+ifeq ($(with_lib64vtv),yes)
+  $(lib_binaries)  += lib64vtv
+endif
+ifeq ($(with_lib32vtv),yes)
+  $(lib_binaries)	+= lib32vtv
+endif
+ifeq ($(with_libn32vtv),yes)
+  $(lib_binaries)	+= libn32vtv
+endif
+ifeq ($(with_libx32vtv),yes)
+  $(lib_binaries)	+= libx32vtv
+endif
+ifeq ($(with_libhfvtv),yes)
+  $(lib_binaries)	+= libhfvtv
+endif
+ifeq ($(with_libsfvtv),yes)
+  $(lib_binaries)	+= libsfvtv
+endif
+
+define __do_vtv
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_l) $(d_d)
+	dh_installdirs -p$(p_l) $(usr_lib$(2))
+	$(dh_compat2) dh_movefiles -p$(p_l) $(usr_lib$(2))/libvtv.so.*
+
+	debian/dh_doclink -p$(p_l) $(p_lbase)
+	debian/dh_doclink -p$(p_d) $(p_lbase)
+
+	if [ -f debian/$(p_l).overrides ]; then \
+		mkdir -p debian/$(p_l)/usr/share/lintian/overrides; \
+		cp debian/$(p_l).overrides debian/$(p_l)/usr/share/lintian/overrides/$(p_l); \
+	fi
+
+	dh_strip -p$(p_l) --dbg-package=$(p_d)
+	$(cross_makeshlibs) dh_makeshlibs $(ldconfig_arg) -p$(p_l)
+	$(call cross_mangle_shlibs,$(p_l))
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps) dh_shlibdeps -p$(p_l) \
+		$(call shlibdirs_to_search, \
+			$(subst vtv$(VTV_SONAME),gcc$(GCC_SONAME),$(p_l)) \
+			$(subst vtv$(VTV_SONAME),stdc++$(CXX_SONAME),$(p_l)) \
+		,$(2)) \
+		$(if $(filter yes, $(with_common_libs)),,-- -Ldebian/shlibs.common$(2))
+	$(call cross_mangle_substvars,$(p_l))
+	echo $(p_l) $(p_d) >> debian/$(lib_binaries)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+endef
+
+# ----------------------------------------------------------------------
+
+do_vtv = $(call __do_vtv,lib$(1)vtv$(VTV_SONAME),$(1))
+
+$(binary_stamp)-libvtv: $(install_stamp)
+	$(call do_vtv,)
+
+$(binary_stamp)-lib64vtv: $(install_stamp)
+	$(call do_vtv,64)
+
+$(binary_stamp)-lib32vtv: $(install_stamp)
+	$(call do_vtv,32)
+
+$(binary_stamp)-libn32vtv: $(install_stamp)
+	$(call do_vtv,n32)
+
+$(binary_stamp)-libx32vtv: $(install_stamp)
+	$(call do_vtv,x32)
+
+$(binary_stamp)-libhfvtv: $(install_dependencies)
+	$(call do_vtv,hf)
+
+$(binary_stamp)-libsfvtv: $(install_dependencies)
+	$(call do_vtv,sf)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-neon.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-neon.mk
@@ -0,0 +1,47 @@
+arch_binaries  := $(arch_binaries) neon
+
+p_nlgcc		= libgcc$(GCC_SONAME)-neon
+p_ngomp		= libgomp$(GOMP_SONAME)-neon
+p_nlobjc	= libobjc$(OBJC_SONAME)-neon
+p_nflib		= libgfortran$(FORTRAN_SONAME)-neon
+p_nlcxx		= libstdc++$(CXX_SONAME)-neon
+
+d_nlgcc		= debian/$(p_nlgcc)
+d_ngomp		= debian/$(p_ngomp)
+d_nlobjc	= debian/$(p_nlobjc)
+d_nflib		= debian/$(p_nflib)
+d_nlcxx		= debian/$(p_nlcxx)
+
+neon_pkgs = -p$(p_nlgcc) -p$(p_ngomp) -p$(p_nlobjc) -p$(p_nflib) -p$(p_nlcxx)
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-neon: $(install_neon_stamp)
+	dh_testdir
+	dh_testroot
+
+	dh_installdirs -p$(p_nlgcc) \
+		$(PF)/share/doc \
+		lib/neon
+	dh_installdirs -A -p$(p_ngomp) -p$(p_nlobjc) -p$(p_nflib) -p$(p_nlcxx) \
+		$(PF)/share/doc \
+		$(PF)/lib/neon
+
+	cp -a $(d_neon)/$(PF)/lib/libgcc*.so.* \
+		$(d_nlgcc)/lib/neon/
+	cp -a $(d_neon)/$(PF)/lib/libgomp*.so.* \
+		$(d_ngomp)/$(PF)/lib/neon/
+	cp -a $(d_neon)/$(PF)/lib/libobjc*.so.* \
+		$(d_nlobjc)/$(PF)/lib/neon/
+	cp -a $(d_neon)/$(PF)/lib/libgfortran*.so.* \
+		$(d_nflib)/$(PF)/lib/neon/
+	cp -a $(d_neon)/$(PF)/lib/libstdc++*.so.* \
+		$(d_nlcxx)/$(PF)/lib/neon/
+
+	for p in $(p_nlgcc) $(p_ngomp) $(p_nlobjc) $(p_nflib) $(p_nlcxx); do \
+	  ln -s ../$(p_base) debian/$$p/usr/share/doc/$$p; \
+	done
+	dh_strip $(neon_pkgs)
+	dh_shlibdeps $(neon_pkgs)
+	echo $(p_nlgcc) $(p_ngomp) $(p_nlobjc) $(p_nflib) $(p_nlcxx) >> debian/arch_binaries
+
+	touch $@
--- gcc-6-6.4.0.orig/debian/rules.d/binary-nof.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-nof.mk
@@ -0,0 +1,51 @@
+arch_binaries  := $(arch_binaries) nof
+
+p_nof  = gcc$(pkg_ver)-nof
+d_nof  = debian/$(p_nof)
+
+dirs_nof = \
+	$(docdir) \
+	$(usr_lib)/nof
+ifeq ($(with_cdev),yes)
+  dirs_nof += \
+	$(gcc_lib_dir)/nof
+endif
+
+ifeq ($(with_cdev),yes)
+  files_nof = \
+	$(libgcc_dir)/libgcc_s_nof.so.$(GCC_SONAME) \
+	$(gcc_lib_dir)/libgcc_s_nof.so \
+	$(usr_lib)/nof \
+	$(gcc_lib_dir)/nof
+else
+  files_nof = \
+	$(usr_lib)/libgcc_s_nof.so.$(GCC_SONAME)
+endif
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-nof: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	mv $(d)/$(usr_lib)/libgcc_s_nof.so.$(GCC_SONAME) $(d)/$(libgcc_dir)/.
+	rm -f $(d)/$(usr_lib)/libgcc_s_nof.so
+	ln -sf $(libgcc_dir)/libgcc_s_nof.so.$(GCC_SONAME) \
+		$(d)/$(gcc_lib_dir)/libgcc_s_nof.so
+
+	rm -rf $(d_nof)
+	dh_installdirs -p$(p_nof) $(dirs_nof)
+	$(dh_compat2) dh_movefiles -p$(p_nof) $(files_nof)
+	debian/dh_doclink -p$(p_nof) $(p_xbase)
+	dh_strip -p$(p_nof)
+	dh_shlibdeps -p$(p_nof)
+
+	dh_makeshlibs $(ldconfig_arg) -p$(p_nof)
+	: # Only keep the shlibs file for the libgcc_s_nof library
+	fgrep libgcc_s_nof debian/$(p_nof)/DEBIAN/shlibs \
+		> debian/$(p_nof)/DEBIAN/shlibs.tmp
+	mv -f debian/$(p_nof)/DEBIAN/shlibs.tmp debian/$(p_nof)/DEBIAN/shlibs
+
+	echo $(p_nof) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-objc.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-objc.mk
@@ -0,0 +1,69 @@
+ifneq ($(DEB_STAGE),rtlibs)
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32) $(biarchhf) $(biarchsf)))
+    arch_binaries  := $(arch_binaries) objc-multi
+  endif
+  arch_binaries := $(arch_binaries) objc
+endif
+
+p_objc	= gobjc$(pkg_ver)$(cross_bin_arch)
+d_objc	= debian/$(p_objc)
+
+p_objc_m= gobjc$(pkg_ver)-multilib$(cross_bin_arch)
+d_objc_m= debian/$(p_objc_m)
+
+dirs_objc = \
+	$(docdir)/$(p_xbase)/ObjC \
+	$(gcc_lexec_dir)
+
+files_objc = \
+	$(gcc_lexec_dir)/cc1obj
+
+$(binary_stamp)-objc: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_objc)
+	dh_installdirs -p$(p_objc) $(dirs_objc)
+	$(dh_compat2) dh_movefiles -p$(p_objc) $(files_objc)
+
+	cp -p $(srcdir)/libobjc/{README*,THREADS*} \
+		$(d_objc)/$(docdir)/$(p_xbase)/ObjC/.
+
+	cp -p $(srcdir)/libobjc/ChangeLog \
+		$(d_objc)/$(docdir)/$(p_xbase)/ObjC/changelog.libobjc
+
+	mkdir -p $(d_objc)/usr/share/lintian/overrides
+	echo '$(p_objc) binary: hardening-no-pie' \
+	  > $(d_objc)/usr/share/lintian/overrides/$(p_objc)
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	echo '$(p_objc) binary: binary-without-manpage' \
+	  >> $(d_objc)/usr/share/lintian/overrides/$(p_objc)
+endif
+
+	debian/dh_doclink -p$(p_objc) $(p_xbase)
+
+	debian/dh_rmemptydirs -p$(p_objc)
+
+	dh_strip -p$(p_objc) \
+	  $(if $(unstripped_exe),-X/cc1obj)
+	dh_shlibdeps -p$(p_objc)
+	echo $(p_objc) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+$(binary_stamp)-objc-multi: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_objc_m)
+	dh_installdirs -p$(p_objc_m) $(docdir)
+
+	debian/dh_doclink -p$(p_objc_m) $(p_xbase)
+
+	dh_strip -p$(p_objc_m)
+	dh_shlibdeps -p$(p_objc_m)
+	echo $(p_objc_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-objcxx.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-objcxx.mk
@@ -0,0 +1,62 @@
+ifneq ($(DEB_STAGE),rtlibs)
+  ifneq (,$(filter yes, $(biarch64) $(biarch32) $(biarchn32) $(biarchx32) $(biarchhf) $(biarchsf)))
+    arch_binaries  := $(arch_binaries) objcxx-multi
+  endif
+  arch_binaries := $(arch_binaries) objcxx
+endif
+
+p_objcx		= gobjc++$(pkg_ver)$(cross_bin_arch)
+d_objcx		= debian/$(p_objcx)
+
+p_objcx_m	= gobjc++$(pkg_ver)-multilib$(cross_bin_arch)
+d_objcx_m	= debian/$(p_objcx_m)
+
+dirs_objcx = \
+	$(docdir)/$(p_xbase)/Obj-C++ \
+	$(gcc_lexec_dir)
+
+files_objcx = \
+	$(gcc_lexec_dir)/cc1objplus
+
+$(binary_stamp)-objcxx: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_objcx)
+	dh_installdirs -p$(p_objcx) $(dirs_objcx)
+	$(dh_compat2) dh_movefiles -p$(p_objcx) $(files_objcx)
+
+	debian/dh_doclink -p$(p_objcx) $(p_xbase)
+	cp -p $(srcdir)/gcc/objcp/ChangeLog \
+		$(d_objcx)/$(docdir)/$(p_xbase)/Obj-C++/changelog
+
+	mkdir -p $(d_objcx)/usr/share/lintian/overrides
+	echo '$(p_objcx) binary: hardening-no-pie' \
+	  > $(d_objcx)/usr/share/lintian/overrides/$(p_objcx)
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	echo '$(p_objcx) binary: binary-without-manpage' \
+	  >> $(d_objcx)/usr/share/lintian/overrides/$(p_objcx)
+endif
+
+	debian/dh_rmemptydirs -p$(p_objcx)
+
+	dh_strip -p$(p_objcx) \
+	  $(if $(unstripped_exe),-X/cc1objplus)
+	dh_shlibdeps -p$(p_objcx)
+	echo $(p_objcx) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
+
+$(binary_stamp)-objcxx-multi: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+	rm -rf $(d_objcx_m)
+	debian/dh_doclink -p$(p_objcx_m) $(p_xbase)
+	debian/dh_rmemptydirs -p$(p_objcx_m)
+	dh_strip -p$(p_objcx_m)
+	dh_shlibdeps -p$(p_objcx_m)
+	echo $(p_objcx_m) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-snapshot.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-snapshot.mk
@@ -0,0 +1,234 @@
+arch_binaries  := $(arch_binaries) snapshot
+
+ifneq (,$(findstring gcc-snapshot, $(PKGSOURCE)))
+  p_snap = gcc-snapshot
+else ifneq (,$(findstring gcc-linaro, $(PKGSOURCE)))
+  p_snap = gcc-linaro
+else
+  $(error unknown build for single gcc package)
+endif
+
+ifeq ($(DEB_CROSS),yes)
+  p_snap := $(p_snap)$(cross_bin_arch)
+endif
+d_snap	= debian/$(p_snap)
+
+dirs_snap = \
+	$(docdir)/$(p_snap) \
+	usr/lib
+
+ifeq ($(with_hppa64),yes)
+  snapshot_depends = binutils-hppa64
+endif
+
+$(stampdir)/ecj_binaries: $(install_snap_stamp)
+	mkdir -p $(builddir)/aot/jar $(builddir)/aot/bin
+	cp $(ecj_jar) $(builddir)/aot/jar/ecj-standalone.jar
+	zip -d $(builddir)/aot/jar/ecj-standalone.jar \
+		'org/eclipse/jdt/core/JDTCompilerAdapter*'
+
+	cd $(builddir)/aot/jar \
+	  && fastjar xf ecj-standalone.jar \
+	  && find -name '*.rsc' -o -name '*.properties' \
+		| fastjar -c -@ - -f ../resources.jar
+	rm -rf $(builddir)/aot/jar/META-INF $(builddir)/aot/jar/org
+	$(d)/$(PF)/bin/gcj \
+	    -c -O2 -g -fPIC -fjni -findirect-dispatch \
+	    -o $(builddir)/aot/bin/resources.o $(builddir)/aot/resources.jar
+
+	cp $(srcdir)/libjava/contrib/classfile.py $(builddir)/aot/
+	cp $(buildlibdir)/libjava/contrib/*.py $(builddir)/aot/
+	grep -v '^sys.path.insert' $(buildlibdir)/libjava/contrib/aot-compile \
+	    > $(builddir)/aot/aot-compile
+	chmod 755 $(builddir)/aot/aot-compile
+	patch -p1 < debian/patches/aotcompile.diff
+	LD_LIBRARY_PATH=$${LD_LIBRARY_PATH:+$$LD_LIBRARY_PATH:}$(CURDIR)/$(d)/$(PF)/lib \
+	RPATH=-Wl,-rpath,/$(PF)/lib \
+	PYTHONPATH=$(builddir)/aot \
+	  python $(builddir)/aot/aot-compile \
+	    --gcj=$(CURDIR)/$(d)/$(PF)/bin/gcj \
+	    --dbtool=$(CURDIR)/$(d)/$(PF)/bin/gcj-dbtool \
+	    --makeflags="$(NJOBS)" \
+	    --ldflags="$(LDFLAGS)" \
+	    $(builddir)/aot/jar $(builddir)/aot/bin
+	touch $@
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-snapshot: $(install_snap_stamp) \
+    $(if $(filter $(with_ecj),yes),$(stampdir)/ecj_binaries)
+	dh_testdir
+	dh_testroot
+	mv $(install_snap_stamp) $(install_snap_stamp)-tmp
+
+	rm -rf $(d_snap)
+	dh_installdirs -p$(p_snap) $(dirs_snap)
+
+	mv $(d)/$(PF) $(d_snap)/usr/lib/
+
+	find $(d_snap) -name '*.gch' -type d | xargs -r rm -rf
+	find $(d_snap) -name '*.la' -o -name '*.lai' | xargs -r rm -f
+
+	: # FIXME: libbacktrace is not installed by default
+	for d in . 32 n32 64 sf hf; do \
+	  if [ -f $(buildlibdir)/$$d/libbacktrace/.libs/libbacktrace.a ]; then \
+	    install -m644 $(buildlibdir)/$$d/libbacktrace/.libs/libbacktrace.a \
+	      $(d_snap)/$(gcc_lib_dir)/$$d; \
+	  fi; \
+	done
+	if [ -f $(buildlibdir)/libbacktrace/backtrace-supported.h ]; then \
+	  install -m644 $(buildlibdir)/libbacktrace/backtrace-supported.h \
+	    $(d_snap)/$(gcc_lib_dir)/include/; \
+	  install -m644 $(srcdir)/libbacktrace/backtrace.h \
+	    $(d_snap)/$(gcc_lib_dir)/include/; \
+	fi
+
+	rm -rf $(d_snap)/$(PF)/lib/nof
+ifeq ($(with_java),yes)
+	mv $(d)/usr/lib/jvm $(d_snap)/usr/lib/
+
+	dh_link -p$(p_snap) \
+	  $(gcc_lib_dir)/include/gcj $(jvm_dir)/include/gcj \
+	  usr/bin/ecj $(jvm_dir)/bin/javac
+
+  ifneq ($(DEB_TARGET_ARCH_CPU),$(java_cpu))
+	ln -sf $(java_cpu) $(d_snap)/$(jvm_dir)/jre/lib/$(DEB_TARGET_ARCH_CPU)
+  endif
+  ifeq ($(with_ecj),yes)
+	install -m755 $(builddir)/aot/bin/javac $(d_snap)/$(jvm_dir)/bin/javac
+	install -m755 $(builddir)/aot/bin/ecj1 $(d_snap)/$(gcc_lexec_dir)/ecj1
+
+    ifeq (./,$(dir $(ecj_jar)))
+	install -m 644 $(ecj_jar) $(d_snap)/$(jvm_dir)/lib/ecj.jar
+    else
+	dh_link -p$(p_snap) \
+	  $(ecj_jar) $(jvm_dir)/lib/ecj.jar
+    endif
+  endif
+
+	: # provide .jinfo file
+	( \
+	  echo 'name=$(jvm_name_short)'; \
+	  echo 'alias=java-gcj$(pkg_ver)'; \
+	  echo 'priority=$(priority)'; \
+	  echo 'section=main'; \
+	  echo ''; \
+	  for i in $(jre_tools); do \
+	    echo "jre $$i /$(jvm_dir)/jre/bin/$$i"; \
+	  done; \
+	  for i in $(jdk_tools); do \
+	    echo "jdk $$i /$(jvm_dir)/bin/$$i"; \
+	  done; \
+	) > $(d_snap)/usr/lib/jvm/.java-gcj$(pkg_ver)-snap.jinfo
+endif
+
+ifeq ($(with_ada),yes FIXME: apply our ada patches)
+	dh_link -p$(p_snap) \
+	   $(gcc_lib_dir)/rts-sjlj/adalib/libgnat.a \
+	   $(gcc_lib_dir)/rts-sjlj/adalib/libgnat-$(GNAT_VERSION).a
+	dh_link -p$(p_snap) \
+	   $(gcc_lib_dir)/rts-sjlj/adalib/libgnarl.a \
+	   $(gcc_lib_dir)/rts-sjlj/adalib/libgnarl-$(GNAT_VERSION).a
+
+	set -e; \
+	for lib in lib{gnat,gnarl}; do \
+	  vlib=$$lib-$(GNAT_SONAME); \
+	  mv $(d_snap)/$(gcc_lib_dir)/adalib/$$vlib.so.1 $(d_snap)/$(PF)/$(libdir)/. ; \
+	  rm -f $(d_snap)/$(gcc_lib_dir)/adalib/$$lib.so.1; \
+	  dh_link -p$(p_snap) \
+	    /$(PF)/$(libdir)/$$vlib.so.1 /$(PF)/$(libdir)/$$vlib.so \
+	    /$(PF)/$(libdir)/$$vlib.so.1 /$(PF)/$(libdir)/$$lib.so \
+	    /$(PF)/$(libdir)/$$vlib.so.1 /$(gcc_lib_dir)/rts-native/adalib/$$lib.so; \
+	done
+endif
+ifeq ($(with_ada),yes)
+	ln -sf gcc $(d_snap)/$(PF)/bin/gnatgcc
+endif
+
+ifeq ($(with_hppa64),yes)
+	: # provide as and ld links
+	dh_link -p $(p_snap) \
+		/usr/bin/hppa64-linux-gnu-as \
+		/$(PF)/libexec/gcc/hppa64-linux-gnu/$(GCC_VERSION)/as \
+		/usr/bin/hppa64-linux-gnu-ld \
+		/$(PF)/libexec/gcc/hppa64-linux-gnu/$(GCC_VERSION)/ld
+endif
+
+ifeq ($(with_check),yes)
+	dh_installdocs -p$(p_snap) test-summary
+# more than one libgo.sum, avoid it 
+	mkdir -p $(d_snap)/$(docdir)/$(p_snap)/test-summaries
+	cp -p $$(find $(builddir)/gcc/testsuite -maxdepth 2 \( -name '*.sum' -o -name '*.log' \)) \
+	      $$(find $(buildlibdir)/*/testsuite -maxdepth 1 \( -name '*.sum'  -o -name '*.log' \) ! -name 'libgo.*') \
+		$(d_snap)/$(docdir)/$(p_snap)/test-summaries/
+  ifeq ($(with_go),yes)
+	cp -p $(buildlibdir)/libgo/libgo.sum \
+		$(d_snap)/$(docdir)/$(p_snap)/test-summaries/
+  endif
+	if which xz 2>&1 >/dev/null; then \
+	  echo -n $(d_snap)/$(docdir)/$(p_snap)/test-summaries/* \
+	    | xargs -d ' ' -L 1 -P $(USE_CPUS)	xz -7v; \
+	fi
+else
+	dh_installdocs -p$(p_snap)
+endif
+	if [ -f $(buildlibdir)/libstdc++-v3/testsuite/current_symbols.txt ]; \
+	then \
+	  cp -p $(buildlibdir)/libstdc++-v3/testsuite/current_symbols.txt \
+	    $(d_snap)/$(docdir)/$(p_snap)/libstdc++6_symbols.txt; \
+	fi
+	cp -p debian/README.snapshot \
+		$(d_snap)/$(docdir)/$(p_snap)/README.Debian
+	cp -p debian/README.Bugs \
+		$(d_snap)/$(docdir)/$(p_snap)/
+	dh_installchangelogs -p$(p_snap)
+ifeq ($(DEB_TARGET_ARCH),hppa)
+	dh_strip -p$(p_snap) -Xdebug -X.o -X.a -X/cgo -Xbin/go -Xbin/gofmt \
+	  $(if $(unstripped_exe),$(foreach i,cc1 cc1obj cc1objplus cc1plus cc1d f951 go1 jc1 lto1, -X/$(i)))
+else
+	dh_strip -p$(p_snap) -Xdebug -X/cgo -Xbin/go -Xbin/gofmt \
+	  $(if $(unstripped_exe),$(foreach i,cc1 cc1obj cc1objplus cc1plus cc1d f951 go1 jc1 lto1, -X/$(i)))
+endif
+	dh_compress -p$(p_snap) -X README.Bugs -X.log.xz -X.sum.xz
+	-find $(d_snap) -type d ! -perm 755 -exec chmod 755 {} \;
+	dh_fixperms -p$(p_snap)
+ifeq ($(with_ada),yes)
+	find $(d_snap)/$(gcc_lib_dir) -name '*.ali' | xargs -r chmod 444
+endif
+
+	mkdir -p $(d_snap)/usr/share/lintian/overrides
+	cp -p debian/gcc-snapshot.overrides \
+		$(d_snap)/usr/share/lintian/overrides/$(p_snap)
+
+	( \
+	  echo 'libgcc_s $(GCC_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libobjc $(OBJC_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgfortran $(FORTRAN_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libffi $(FFI_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgcj $(GCJ_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgcj-tools $(GCJ_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgij $(GCJ_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgcj_bc 1 ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgomp $(GOMP_SONAME) ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgnat-$(GNAT_SONAME) 1 ${p_snap} (>= $(DEB_VERSION))'; \
+	  echo 'libgnarl-$(GNAT_SONAME) 1 ${p_snap} (>= $(DEB_VERSION))'; \
+	) > debian/shlibs.local
+
+	$(ignshld)DIRNAME=$(subst n,,$(2)) $(cross_shlibdeps)  \
+	  dh_shlibdeps -p$(p_snap) -l$(CURDIR)/$(d_snap)/$(PF)/lib:$(CURDIR)/$(d_snap)/$(PF)/$(if $(filter $(DEB_TARGET_ARCH),amd64 ppc64),lib32,lib64):/usr/$(DEB_TARGET_GNU_TYPE)/lib -Xlibgcj-tools
+	-sed -i -e 's/$(p_snap)[^,]*, //g' debian/$(p_snap).substvars
+
+ifeq ($(with_multiarch_lib),yes)
+	: # paths needed for relative lookups from startfile_prefixes
+	for ma in $(xarch_multiarch_names); do \
+	  mkdir -p $(d_snap)/lib/$$ma; \
+	  mkdir -p $(d_snap)/usr/lib/$$ma; \
+	done
+endif
+
+	dh_gencontrol -p$(p_snap) -- $(common_substvars) \
+		'-Vsnap:depends=$(snapshot_depends)' '-Vsnap:recommends=$(snapshot_recommends)'
+	dh_installdeb -p$(p_snap)
+	dh_md5sums -p$(p_snap)
+	dh_builddeb -p$(p_snap)
+
+	trap '' 1 2 3 15; touch $@; mv $(install_snap_stamp)-tmp $(install_snap_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-softfloat.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-softfloat.mk
@@ -0,0 +1,31 @@
+arch_binaries  := $(arch_binaries) softfloat
+
+p_softfloat  = gcc$(pkg_ver)-soft-float
+d_softfloat  = debian/$(p_softfloat)
+
+dirs_softfloat = \
+	$(PFL)/$(libdir) \
+	$(gcc_lib_dir)
+
+files_softfloat = \
+	$(PFL)/$(libdir)/soft-float \
+	$(gcc_lib_dir)/soft-float
+
+# ----------------------------------------------------------------------
+$(binary_stamp)-softfloat: $(install_stamp)
+	dh_testdir
+	dh_testroot
+	mv $(install_stamp) $(install_stamp)-tmp
+
+	rm -rf $(d_softfloat)
+	dh_installdirs -p$(p_softfloat) $(dirs_softfloat)
+	$(dh_compat2) dh_movefiles -p$(p_softfloat) $(files_softfloat)
+	rm -rf $(d_softfloat)/$(PFL)/$(libdir)/soft-float/libssp.so*
+	mv $(d_softfloat)/$(PFL)/$(libdir)/soft-float/libssp.a \
+		$(d_softfloat)/$(PFL)/$(libdir)/soft-float/libssp_nonshared.a
+	debian/dh_doclink -p$(p_softfloat) $(p_xbase)
+	dh_strip -p$(p_softfloat) -Xlibgcj.a
+	dh_shlibdeps -p$(p_softfloat)
+	echo $(p_softfloat) >> debian/arch_binaries
+
+	trap '' 1 2 3 15; touch $@; mv $(install_stamp)-tmp $(install_stamp)
--- gcc-6-6.4.0.orig/debian/rules.d/binary-source.mk
+++ gcc-6-6.4.0/debian/rules.d/binary-source.mk
@@ -0,0 +1,52 @@
+indep_binaries := $(indep_binaries) gcc-source
+
+ifeq ($(BACKPORT),true)
+  p_source = gcc$(pkg_ver)-$(GCC_VERSION)-source
+else
+  p_source = gcc$(pkg_ver)-source
+endif
+d_source= debian/$(p_source)
+
+$(binary_stamp)-gcc-source: $(install_stamp)
+	dh_testdir
+	dh_testroot
+
+	dh_installdocs -p$(p_source)
+	dh_installchangelogs -p$(p_source)
+
+	dh_install -p$(p_source) $(gcc_tarball) usr/src/gcc$(pkg_ver)
+ifneq (,$(gdc_tarball))
+	dh_install -p$(p_source) $(gdc_tarball) usr/src/gcc$(pkg_ver)
+endif
+	tar cf - $$(find './debian' -mindepth 1 \( \
+		-name .svn -prune -o \
+		-path './debian/gcc-*' -type d -prune -o \
+		-path './debian/cpp-*' -type d -prune -o \
+		-path './debian/*fortran*' -type d -prune -o \
+		-path './debian/lib*' -type d -prune -o \
+		-path './debian/patches/*' -prune -o \
+		-path './debian/tmp*' -prune -o \
+		-path './debian/files' -prune -o \
+		-path './debian/rules.d/*' -prune -o \
+		-path './debian/rules.parameters' -prune -o \
+		-path './debian/soname-cache' -prune -o \
+		-path './debian/*substvars*' -prune -o \
+		-path './debian/gcc-snapshot*' -prune -o \
+		-path './debian/*[0-9]*.p*' -prune -o \
+		-path './debian/*$(pkg_ver)[.-]*' -prune -o \
+		-print \) ) \
+	  | tar -x -C $(d_source)/usr/src/gcc$(pkg_ver)  -f -
+	# FIXME: Remove generated files
+	find $(d_source)/usr/src/gcc$(pkg_ver) -name '*.debhelper.log' -o -name .svn | xargs rm -rf
+
+	touch $(d_source)/usr/src/gcc$(pkg_ver)/debian/rules.parameters
+
+	dh_link -p$(p_source) \
+		/usr/src/gcc$(pkg_ver)/debian/patches /usr/src/gcc$(pkg_ver)/patches
+
+	mkdir -p $(d_source)/usr/share/lintian/overrides
+	cp -p debian/$(p_source).overrides \
+		$(d_source)/usr/share/lintian/overrides/$(p_source)
+	echo $(p_source) >> debian/indep_binaries
+
+	touch $@
--- gcc-6-6.4.0.orig/debian/rules.defs
+++ gcc-6-6.4.0/debian/rules.defs
@@ -0,0 +1,2164 @@
+# -*- makefile -*-
+# definitions used in more than one Makefile / rules file
+
+NJOBS :=
+USE_CPUS := 1
+ifneq (,$(filter parallel=%,$(subst $(COMMA), ,$(DEB_BUILD_OPTIONS))))
+  USE_CPUS := $(subst parallel=,,$(filter parallel=%,$(subst $(COMMA), ,$(DEB_BUILD_OPTIONS))))
+  NJOBS := -j $(USE_CPUS)
+endif
+
+# common vars
+SHELL		= /bin/bash -e	# brace expansion used in rules file
+srcdir		= $(CURDIR)/src
+builddir	= $(CURDIR)/build
+builddir_jit	= $(CURDIR)/build-jit
+builddir_hppa64	= $(CURDIR)/build-hppa64
+stampdir	= stamps
+
+distribution	:= $(shell lsb_release -is)
+distrelease	:= $(shell lsb_release -cs)
+derivative	:= $(shell if dpkg-vendor --derives-from Ubuntu; then echo Ubuntu; \
+			elif dpkg-vendor --derives-from Debian; then echo Debian; \
+			else echo Unknown; fi)
+
+# On non official archives, "lsb_release -cs" default to "n/a". Assume
+# sid in that case 
+ifeq ($(distrelease),n/a)
+distrelease	:= sid
+endif
+
+on_buildd := $(shell [ -f /CurrentlyBuilding -o "$$LOGNAME" = buildd ] && echo yes)
+
+# creates {srcdir,builddir}_{hppa64,neon}
+$(foreach x,srcdir builddir,$(foreach target,hppa64 neon,$(eval \
+  $(x)_$(target) := $($(x))-$(target))))
+
+# for architecture dependent variables and changelog vars
+vafilt = $(subst $(2)=,,$(filter $(2)=%,$(1)))
+# for rules.sonames
+vafilt_defined = 1
+
+dpkg_target_vars := $(shell (dpkg-architecture | grep -q DEB_TARGET) && echo yes)
+ifeq ($(dpkg_target_vars),yes)
+  DEB_TARGET_ARCH=
+  DEB_TARGET_ARCH_BITS=
+  DEB_TARGET_ARCH_CPU=
+  DEB_TARGET_ARCH_ENDIAN=
+  DEB_TARGET_ARCH_OS=
+  DEB_TARGET_GNU_CPU=
+  DEB_TARGET_GNU_SYSTEM=
+  DEB_TARGET_GNU_TYPE=
+  DEB_TARGET_MULTIARCH=
+endif
+
+DPKG_VARS		:= $(shell dpkg-architecture)
+ifeq ($(dpkg_target_vars),yes)
+  DPKG_VARS		:= $(filter-out DEB_TARGET_%, $(DPKG_VARS))
+endif
+DEB_BUILD_ARCH		?= $(call vafilt,$(DPKG_VARS),DEB_BUILD_ARCH)
+DEB_BUILD_GNU_TYPE	?= $(call vafilt,$(DPKG_VARS),DEB_BUILD_GNU_TYPE)
+DEB_BUILD_MULTIARCH	?= $(call vafilt,$(DPKG_VARS),DEB_BUILD_MULTIARCH)
+DEB_HOST_ARCH		?= $(call vafilt,$(DPKG_VARS),DEB_HOST_ARCH)
+DEB_HOST_GNU_CPU	?= $(call vafilt,$(DPKG_VARS),DEB_HOST_GNU_CPU)
+DEB_HOST_GNU_SYSTEM	?= $(call vafilt,$(DPKG_VARS),DEB_HOST_GNU_SYSTEM)
+DEB_HOST_GNU_TYPE	?= $(call vafilt,$(DPKG_VARS),DEB_HOST_GNU_TYPE)
+DEB_HOST_MULTIARCH	?= $(call vafilt,$(DPKG_VARS),DEB_HOST_MULTIARCH)
+
+ifeq ($(derivative),Ubuntu)
+  ifeq (,$(filter $(distrelease),dapper hardy lucid precise quantal raring saucy trusty))
+    ifeq ($(DEB_BUILD_GNU_TYPE),i486-linux-gnu)
+      DEB_BUILD_GNU_TYPE = i686-linux-gnu
+    endif
+    ifeq ($(DEB_HOST_GNU_TYPE),i486-linux-gnu)
+      DEB_HOST_GNU_TYPE	= i686-linux-gnu
+    endif
+  endif
+else
+  ifneq (,$(filter $(distrelease),lenny etch squeeze wheezy))
+    # keep dpkg defaults
+  else ifneq (,$(filter $(distrelease),jessie))
+    ifeq ($(DEB_BUILD_GNU_TYPE),i486-linux-gnu)
+      DEB_BUILD_GNU_TYPE = i586-linux-gnu
+    endif
+    ifeq ($(DEB_HOST_GNU_TYPE),i486-linux-gnu)
+      DEB_HOST_GNU_TYPE	= i586-linux-gnu
+    endif
+  else
+    # stretch and newer ...
+    DEB_BUILD_GNU_TYPE := $(subst i586,i686,$(DEB_BUILD_GNU_TYPE))
+    DEB_HOST_GNU_TYPE := $(subst i586,i686,$(DEB_HOST_GNU_TYPE))
+  endif
+endif
+
+CHANGELOG_VARS := $(shell dpkg-parsechangelog | \
+	sed -n 's/ /_/g;/^[^_]/s/^\([^:]*\):_\(.*\)/\1=\2/p')
+
+# the name of the source package
+PKGSOURCE := $(call vafilt,$(CHANGELOG_VARS),Source)
+# those are required here too
+SOURCE_VERSION := $(call vafilt,$(CHANGELOG_VARS),Version)
+DEB_VERSION := $(strip $(shell echo $(SOURCE_VERSION) | \
+        sed -e 's/.*://' -e 's/ds[0-9]*//'))
+# epoch used for gcc versions up to 3.3.x, now used for some remaining
+# libraries: libgcc1, libobjc1
+EPOCH := 1
+DEB_EVERSION := $(EPOCH):$(DEB_VERSION)
+BASE_VERSION := $(shell echo $(DEB_VERSION) | sed -e 's/\([1-9]\).*-.*/\1/')
+
+ifneq (,$(findstring gcc-snapshot, $(PKGSOURCE)))
+  single_package = yes
+  trunk_build = yes
+else ifneq (,$(findstring gcc-linaro, $(PKGSOURCE)))
+  single_package = yes
+  trunk_build = no
+else
+  # --program-suffix=-$(BASE_VERSION)
+  versioned_packages := yes
+endif
+
+# push glibc stack traces into stderr
+export LIBC_FATAL_STDERR_=1
+
+# ---------------------------------------------------------------------------
+# set target
+# - GNU triplet via DEB_TARGET_GNU_TYPE
+# - Debian arch in debian/target
+# - Debian arch via DEB_GCC_TARGET or GCC_TARGET
+#
+# alias
+ifdef GCC_TARGET
+  DEB_GCC_TARGET := $(GCC_TARGET)
+endif
+ifdef DEB_TARGET_GNU_TYPE
+  TARGET_VARS := $(shell dpkg-architecture -f -t$(DEB_TARGET_GNU_TYPE) 2>/dev/null)
+else
+  # allow debian/target to be used instead of DEB_GCC_TARGET - this was requested
+  # by toolchain-source maintainer
+  DEBIAN_TARGET_FILE := $(strip $(if $(wildcard debian/target),$(shell cat debian/target 2>/dev/null)))
+  ifndef DEB_TARGET_ARCH
+    ifneq (,$(DEBIAN_TARGET_FILE))
+      DEB_TARGET_ARCH := $(DEBIAN_TARGET_FILE)
+    else
+      ifdef DEB_GCC_TARGET
+        DEB_TARGET_ARCH := $(DEB_GCC_TARGET)
+      else
+        DEB_TARGET_ARCH := $(DEB_HOST_ARCH)
+      endif
+    endif
+  endif
+  TARGET_VARS := $(shell dpkg-architecture -f -a$(DEB_TARGET_ARCH) 2>/dev/null)
+endif
+ifeq ($(dpkg_target_vars),yes)
+  TARGET_VARS		:= $(filter-out DEB_TARGET_%, $(TARGET_VARS))
+endif
+
+DEB_TARGET_ARCH		:= $(call vafilt,$(TARGET_VARS),DEB_HOST_ARCH)
+DEB_TARGET_ARCH_OS	:= $(call vafilt,$(TARGET_VARS),DEB_HOST_ARCH_OS)
+DEB_TARGET_ARCH_CPU	:= $(call vafilt,$(TARGET_VARS),DEB_HOST_ARCH_CPU)
+DEB_TARGET_GNU_CPU	:= $(call vafilt,$(TARGET_VARS),DEB_HOST_GNU_CPU)
+DEB_TARGET_GNU_TYPE	:= $(call vafilt,$(TARGET_VARS),DEB_HOST_GNU_TYPE)
+DEB_TARGET_GNU_SYSTEM	:= $(call vafilt,$(TARGET_VARS),DEB_HOST_GNU_SYSTEM)
+DEB_TARGET_MULTIARCH	:= $(call vafilt,$(TARGET_VARS),DEB_HOST_MULTIARCH)
+
+ifeq ($(derivative),Ubuntu)
+  ifeq (,$(filter $(distrelease),dapper lucid))
+    ifeq ($(DEB_TARGET_GNU_TYPE),i486-linux-gnu)
+      DEB_TARGET_GNU_TYPE = i586-linux-gnu
+    endif
+  endif
+else
+  ifneq (,$(filter $(distrelease),stretch sid))
+    DEB_TARGET_GNU_TYPE := $(subst i586,i686,$(DEB_TARGET_GNU_TYPE))
+    i586_symlinks = $(if $(findstring i686,$(DEB_TARGET_GNU_TYPE)),yes)
+  endif
+endif
+
+ifeq ($(DEB_TARGET_ARCH),)
+  $(error Invalid architecure.)
+endif
+
+# Force this, people get confused about the default. See #760770.
+override with_deps_on_target_arch_pkgs :=
+
+# including unversiond symlinks for binaries
+#with_unversioned = yes
+
+# ---------------------------------------------------------------------------
+# cross-compiler config
+ifneq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE))
+  ifneq ($(DEB_HOST_GNU_TYPE),$(DEB_TARGET_GNU_TYPE))
+    # cross building a cross compiler, untested.
+    DEB_CROSS = yes
+    build_type = cross-build-cross
+  else
+    # cross building the native compiler
+    ifeq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid))
+      with_sysroot = /
+    endif
+    build_type = cross-build-native
+  endif
+else
+  ifneq ($(DEB_HOST_GNU_TYPE),$(DEB_TARGET_GNU_TYPE))
+    # cross compiler, sets WITH_SYSROOT on it's own
+    DEB_CROSS = yes
+    build_type = build-cross
+  else
+    # native build
+    # first ones are wheezy and maverick
+    ifeq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid))
+      with_sysroot = /
+    endif
+    build_type = build-native
+  endif
+endif
+
+# ---------------------------------------------------------------------------
+# cross compiler support
+ifeq ($(DEB_CROSS),yes)
+  # TARGET: Alias to DEB_TARGET_ARCH (Debian arch name)
+  # TP: Target Prefix. Used primarily as a prefix for cross tool
+  #     names (e.g. powerpc-linux-gcc).
+  # TS: Target Suffix. Used primarily at the end of cross compiler
+  #     package names (e.g. gcc-powerpc).
+  # LS: Library Suffix. Used primarily at the end of cross compiler
+  #     library package names (e.g. libgcc-powerpc-cross).
+  # AQ: Arch Qualifier. Used for cross-arch dependencies
+  DEB_TARGET_ALIAS ?= $(DEB_TARGET_GNU_TYPE)
+  TARGET := $(DEB_TARGET_ARCH)
+  TP :=  $(subst _,-,$(DEB_TARGET_GNU_TYPE))-
+  TS := -$(subst _,-,$(DEB_TARGET_ALIAS))
+  LS := -$(subst _,-,$(DEB_TARGET_ARCH))-cross
+  AQ :=
+
+  cross_bin_arch := -$(subst _,-,$(DEB_TARGET_ALIAS))
+  cross_lib_arch := -$(subst _,-,$(DEB_TARGET_ARCH))-cross
+  cmd_prefix := $(DEB_TARGET_GNU_TYPE)-
+
+  TARGET_ALIAS := $(DEB_TARGET_ALIAS)
+
+  lib_binaries := indep_binaries
+  cross_shlibdeps =  DEB_HOST_ARCH=$(TARGET) ARCH=$(DEB_TARGET_ARCH) MAKEFLAGS="CC=something"
+  cross_gencontrol = DEB_HOST_ARCH=$(TARGET)
+  cross_makeshlibs = DEB_HOST_ARCH=$(TARGET)
+  cross_clean = DEB_HOST_ARCH=$(TARGET)
+else
+  TARGET_ALIAS := $(DEB_TARGET_GNU_TYPE)
+
+  ifeq ($(TARGET_ALIAS),i386-gnu)
+    TARGET_ALIAS := i586-gnu
+  endif
+
+  ifeq ($(single_package),yes)
+    cmd_prefix :=
+    unprefixed_names :=
+  else
+    cmd_prefix := $(DEB_TARGET_GNU_TYPE)-
+    unprefixed_names := yes
+  endif
+
+  #ifeq ($(TARGET_ALIAS),i486-linux-gnu)
+  #  TARGET_ALIAS := i686-linux-gnu
+  #endif
+
+  TARGET_ALIAS := $(subst i386,i486,$(TARGET_ALIAS))
+
+  # configure as linux-gnu, not linux
+  #ifeq ($(findstring linux,$(TARGET_ALIAS))/$(findstring linux-gnu,$(TARGET_ALIAS)),linux/)
+  #  TARGET_ALIAS := $(TARGET_ALIAS)-gnu
+  #endif
+
+  # configure as linux, not linux-gnu
+  #TARGET_ALIAS := $(subst linux-gnu,linux,$(TARGET_ALIAS))
+
+  lib_binaries := arch_binaries
+  cross_shlibdeps :=
+  cross_gencontrol :=
+  cross_makeshlibs :=
+  cross_clean :=
+endif
+
+printarch:
+	@echo DEB_TARGET_ARCH: $(DEB_TARGET_ARCH)
+	@echo DEB_TARGET_ARCH_OS: $(DEB_TARGET_ARCH_OS)
+	@echo DEB_TARGET_ARCH_CPU: $(DEB_TARGET_ARCH_CPU)
+	@echo DEB_TARGET_GNU_SYSTEM: $(DEB_TARGET_GNU_SYSTEM)
+	@echo DEB_TARGET_MULTIARCH: $(DEB_TARGET_MULTIARCH)
+	@echo MULTIARCH_CONFARG: $(MULTIARCH_CONFARG)
+	@echo TARGET_ALIAS: $(TARGET_ALIAS)
+	@echo TP: $(TP)
+	@echo TS: $(TS)
+
+# -------------------------------------------------------------------
+# bootstrap options
+ifdef WITH_BOOTSTRAP
+  # "yes" is the default and causes a 3-stage bootstrap.
+  # "off" runs a complete build with --disable-bootstrap
+  # "no" means to just build the first stage, and not create the stage1
+  # directory.
+  # "lean" means a lean 3-stage bootstrap, i.e. delete each stage when no
+  # longer needed.
+  with_bootstrap = $(WITH_BOOTSTRAP)
+endif
+ifneq ($(findstring nostrap, $(DEB_BUILD_OPTIONS)),)
+  with_bootstrap := off
+endif
+
+ifneq ($(findstring gccdebug, $(DEB_BUILD_OPTIONS)),)
+  with_bootstrap := off
+  DEB_BUILD_OPTIONS := $(DEB_BUILD_OPTIONS) nostrip
+  export DEB_BUILD_OPTIONS
+endif
+
+# -------------------------------------------------------------------
+# stage options
+ifdef DEB_STAGE
+  with_cdev := yes
+  separate_lang := yes
+  # "stage1" is minimal compiler with static libgcc
+  # "stage2" is minimal compiler with shared libgcc
+  # "rtlibs" is a subset of target libraries, without compilers
+  ifeq ($(DEB_STAGE),stage1)
+    with_shared_libgcc := no
+  endif
+  ifeq ($(DEB_STAGE),stage2)
+    with_libgcc := yes
+    with_shared_libgcc := yes
+  endif
+  ifeq ($(DEB_STAGE),rtlibs)
+    with_rtlibs := libgcc libgomp libstdc++ libgfortran libquadmath
+    ifeq ($(DEB_CROSS),yes)
+      LS :=
+      TS :=
+      cross_lib_arch :=
+    endif
+  endif
+endif
+
+ifeq ($(BACKPORT),true)
+  with_dev := no
+  with_source := yes
+  with_base_only := yes
+endif
+
+# -------------------------------------------------------------------
+# sysroot options
+ifdef WITH_SYSROOT
+  with_sysroot = $(WITH_SYSROOT)
+endif
+ifdef WITH_BUILD_SYSROOT
+  with_build_sysroot = $(WITH_BUILD_SYSROOT)
+endif
+
+# -------------------------------------------------------------------
+# for components configuration
+
+COMMA = ,
+SPACE = $(EMPTY) $(EMPTY)
+
+# lang= overwrites all of nolang=, overwrites all of WITHOUT_LANG
+
+DEB_LANG_OPT	:= $(filter lang=%,$(DEB_BUILD_OPTIONS))
+DEB_LANG	:= $(strip $(subst $(COMMA), ,$(patsubst lang=%,%,$(DEB_LANG_OPT))))
+DEB_NOLANG_OPT	:= $(filter nolang=%,$(DEB_BUILD_OPTIONS))
+DEB_NOLANG	:= $(strip $(subst $(COMMA), ,$(patsubst nolang=%,%,$(DEB_NOLANG_OPT))))
+lfilt	= $(strip $(if $(DEB_LANG), \
+		$(if $(filter $(1) $(2),$(DEB_LANG)),yes),$(3)))
+nlfilt	= $(strip $(if $(DEB_NOLANG), \
+		$(if $(filter $(1) $(2),$(DEB_NOLANG)),disabled by $(DEB_NOLANG_OPT),$(3))))
+wlfilt	= $(strip $(if $(filter $(1) $(2), $(subst $(COMMA), ,$(WITHOUT_LANG))), \
+		disabled by WITHOUT_LANG=$(WITHOUT_LANG),$(3)))
+envfilt	= $(strip $(or $(call lfilt,$(1),$(2)),$(call nlfilt,$(1),$(3)),$(call wlfilt,$(1),$(3)),$(4)))
+
+# -------------------------------------------------------------------
+# architecture specific config
+
+# FIXME: libjava is not ported for thumb, this hack only works for
+# separate gcj builds
+ifeq (,$(findstring gcj,$(PKGSOURCE)))
+  ifeq ($(DEB_TARGET_ARCH),armhf)
+    ifeq ($(distribution),Raspbian)
+      with_arm_thumb := no
+    else
+      with_arm_thumb := yes
+    endif
+  else
+    ifeq ($(derivative)-$(DEB_TARGET_ARCH),Ubuntu-armel)
+      ifneq (,$(filter $(distrelease),lucid maverick natty oneiric precise))
+        with_arm_thumb := yes
+      endif
+    endif
+  endif
+endif
+
+# build using fsf or linaro
+ifeq ($(distribution),Ubuntu)
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),arm64 armel armhf))
+    with_linaro_branch = yes
+  endif
+endif
+
+# build using fsf or the ibm branch
+ifeq ($(distribution),Ubuntu)
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),ppc64el))
+    #with_ibm_branch = yes
+  endif
+endif
+
+ifneq (,$(findstring gcc-snapshot, $(PKGSOURCE)))
+  with_linaro_branch =
+  with_ibm_branch =
+else ifneq (,$(findstring gcc-linaro, $(PKGSOURCE)))
+  with_ibm_branch =
+endif
+
+# check if we're building for armel or armhf
+ifneq (,$(filter %eabihf,$(DEB_TARGET_GNU_SYSTEM)))
+  float_abi := hard
+else ifneq (,$(filter $(distribution)-$(DEB_TARGET_ARCH), Ubuntu-armel))
+  ifneq (,$(filter $(distrelease),lucid maverick natty oneiric precise))
+    float_abi := softfp
+  else
+    float_abi := soft
+  endif
+else ifneq (,$(filter $(DEB_TARGET_ARCH), arm armel))
+  float_abi := soft
+endif
+
+# -------------------------------------------------------------------
+# basic config
+
+# allows to wrote backtraces for ICEs
+#unstripped_exe = yes
+
+# common things ---------------
+# build common packages, where package names don't differ in different
+# gcc versions (fixincludes, libgcj-common) ...
+with_common_pkgs :=
+# ... and some libraries, which do not change (libgcc1, libssp0).
+with_common_libs :=
+# XXX: should with_common_libs be "yes" only if this is the default compiler
+# version on the targeted arch?
+
+# is this a multiarch-enabled build?
+ifeq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid maverick))
+  with_multiarch_lib := yes
+endif
+
+ifeq ($(with_multiarch_lib),yes)
+  ifneq ($(single_package),yes)
+    ifneq ($(DEB_CROSS),yes)
+      with_multiarch_cxxheaders := yes
+    endif
+  endif
+endif
+
+ifeq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid maverick))
+  multiarch_stage1 := yes
+endif
+
+# mapping for the non-default biarch multilib / multiarch names
+multiarch_xarch_map = \
+	amd64=i386-linux-gnu,x86_64-linux-gnux32 \
+	armel=arm-linux-gnueabi \
+	armhf=arm-linux-gnueabihf \
+	i386=x86_64-linux-gnu,x86_64-linux-gnux32 \
+	powerpc=powerpc64-linux-gnu \
+	ppc64=powerpc-linux-gnu \
+	sparc=sparc64-linux-gnu \
+	sparc64=sparc-linux-gnu \
+	s390=s390x-linux-gnu \
+	s390x=s390-linux-gnu \
+	mips=mips64-linux-gnuabin32,mips64-linux-gnuabi64 \
+	mipsel=mips64el-linux-gnuabin32,mips64el-linux-gnuabi64 \
+	mipsn32=mips-linux-gnu,mips64-linux-gnuabi64 \
+	mipsn32el=mipsel-linux-gnu,mips64el-linux-gnuabi64 \
+	mips64=mips-linux-gnu,mips64-linux-gnuabin32 \
+	mips64el=mipsel-linux-gnu,mips64el-linux-gnuabin32 \
+	mipsr6=mipsisa64r6-linux-gnuabin32,mipsisa64r6-linux-gnuabi64 \
+	mipsr6el=mipsisa64r6el-linux-gnuabin32,mipsisa64r6el-linux-gnuabi64 \
+	mipsn32r6=mipsisa32r6-linux-gnu,mipsisa64r6-linux-gnuabi64 \
+	mipsn32r6el=mipsisa32r6el-linux-gnu,mipsisa64r6el-linux-gnuabi64 \
+	mips64r6=mipsisa32r6-linux-gnu,mipsisa64r6-linux-gnuabin32 \
+	mips64r6el=mipsisa32r6el-linux-gnu,mipsisa64r6el-linux-gnuabin32 \
+	x32=x86_64-linux-gnu,i386-linux-gnu \
+	kfreebsd-amd64=i386-kfreebsd-gnu
+xarch_multiarch_names = $(subst $(COMMA),$(SPACE),$(patsubst $(DEB_TARGET_ARCH)=%,%, \
+		$(filter $(DEB_TARGET_ARCH)=%,$(multiarch_xarch_map))))
+
+multilib_multiarch_map = \
+	$(DEB_TARGET_ARCH)/=$(DEB_TARGET_MULTIARCH) \
+	amd64/32=i386-linux-gnu \
+	amd64/x32=x86_64-linux-gnux32 \
+	armel/hf=arm-linux-gnueabihf \
+	armhf/sf=arm-linux-gnueabi \
+	i386/64=x86_64-linux-gnu \
+	i386/x32=x86_64-linux-gnux32 \
+	powerpc/64=powerpc64-linux-gnu \
+	ppc64/32=powerpc-linux-gnu \
+	sparc/64=sparc64-linux-gnu \
+	sparc64/32=sparc-linux-gnu \
+	s390/64=s390x-linux-gnu \
+	s390x/32=s390-linux-gnu \
+	mips/n32=mips64-linux-gnuabin32 \
+	mips/64=mips64-linux-gnuabi64 \
+	mipsel/n32=mips64el-linux-gnuabin32 \
+	mipsel/64=mips64el-linux-gnuabi64 \
+	mipsn32/32=mips-linux-gnu \
+	mipsn32/64=mips64-linux-gnuabi64 \
+	mipsn32el/32=mipsel-linux-gnu \
+	mipsn32el/64=mips64el-linux-gnuabi64 \
+	mips64/32=mips-linux-gnu \
+	mips64/n32=mips64-linux-gnuabin32 \
+	mips64el/32=mipsel-linux-gnu \
+	mips64el/n32=mips64el-linux-gnuabin32 \
+	mipsr6/n32=mipsisa64r6-linux-gnuabin32 \
+	mipsr6/64=mipsisa64r6-linux-gnuabi64 \
+	mipsr6el/n32=mipsisa64r6el-linux-gnuabin32 \
+	mipsr6el/64=mipsisa64r6el-linux-gnuabi64 \
+	mipsn32r6/32=mipsisa32r6-linux-gnu \
+	mipsn32r6/64=mipsisa64r6-linux-gnuabi64 \
+	mipsn32r6el/32=mipsisa32r6el-linux-gnu \
+	mipsn32r6el/64=mipsisa64r6el-linux-gnuabi64 \
+	mips64r6/32=mipsisa32r6-linux-gnu \
+	mips64r6/n32=mipsisa64r6-linux-gnuabin32 \
+	mips64r6el/32=mipsisa32r6el-linux-gnu \
+	mips64r6el/n32=mipsisa64r6el-linux-gnuabin32 \
+	x32/32=i386-linux-gnu \
+	x32/64=x86_64-linux-gnu \
+	kfreebsd-amd64/32=i386-kfreebsd-gnu
+# $(call mlib_to_march,<empty>|32|64|n32|x32|hf|sf)
+mlib_to_march = $(patsubst $(DEB_TARGET_ARCH)/$(1)=%,%, \
+		   $(filter $(DEB_TARGET_ARCH)/$(1)=%,$(multilib_multiarch_map)))
+
+multilib_arch_map = \
+	$(DEB_TARGET_ARCH)/=$(DEB_TARGET_ARCH) \
+	amd64/32=i386 \
+	amd64/x32=x32 \
+	armel/hf=armhf \
+	armhf/sf=armel \
+	i386/64=amd64 \
+	i386/x32=x32 \
+	powerpc/64=ppc64 \
+	ppc64/32=powerpc \
+	sparc/64=sparc64 \
+	sparc64/32=sparc \
+	s390/64=s390x \
+	s390x/32=s390 \
+	mips/n32=mipsn32 \
+	mips/64=mips64 \
+	mipsel/n32=mipsn32el \
+	mipsel/64=mips64el \
+	mipsn32/32=mips \
+	mipsn32/64=mips64 \
+	mipsn32el/32=mipsel \
+	mipsn32el/64=mips64el \
+	mips64/32=mips \
+	mips64/n32=mipsn32 \
+	mips64el/32=mipsel \
+	mips64el/n32=mipsn32el \
+	mipsr6/n32=mipsn32r6 \
+	mipsr6/64=mips64r6 \
+	mipsr6el/n32=mipsn32r6el \
+	mipsr6el/64=mips64r6el \
+	mipsn32r6/32=mipsr6 \
+	mipsn32r6/64=mips64r6 \
+	mipsn32r6el/32=mipsr6el \
+	mipsn32r6el/64=mips64r6el \
+	mips64r6/32=mipsr6 \
+	mips64r6/n32=mipsn32r6 \
+	mips64r6el/32=mipsr6el \
+	mips64r6el/n32=mipsn32r6el \
+	x32/32=i386 \
+	x32/64=amd64 \
+	kfreebsd-amd64/32=kfreebsd-i386
+# $(call mlib_to_arch,<empty>|32|64|n32|x32|hf|sf)
+mlib_to_arch = $(patsubst $(DEB_TARGET_ARCH)/$(1)=%,%, \
+		   $(filter $(DEB_TARGET_ARCH)/$(1)=%,$(multilib_arch_map)))
+
+# build -base packages
+with_gccbase := yes
+ifeq ($(build_type),build-cross)
+  ifneq ($(DEB_STAGE),rtlibs)
+    with_gcclbase := yes
+  endif
+endif
+
+# build dev packages.
+ifneq ($(DEB_STAGE),rtlibs)
+  with_dev := yes
+endif
+
+with_cpp := yes
+
+# set lang when built from a different source package.
+separate_lang := no
+
+#no_dummy_cpus := ia64 i386 hppa s390 sparc
+#ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(no_dummy_cpus)))
+#  with_base_only	:= no
+#  with_common_libs	:= yes
+#  with_common_pkgs	:= yes
+#else
+#  with_base_only	:= yes
+#  with_common_libs	:= no
+#  with_common_pkgs	:= no
+#  with_dev		:= no
+#endif
+
+ifeq ($(versioned_packages),yes)
+  pkg_ver := -$(BASE_VERSION)
+  PV := $(pkg_ver)
+endif
+
+# -------------------------------------------------------------------
+# configure languages
+
+# C ---------------------------
+enabled_languages := c
+
+with_jit = yes
+
+# FIXME: compiler bug
+jit_no_cpus	:= ia64
+
+ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(jit_no_cpus)))
+  with_jit := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+ifneq (,$(with_rtlibs))
+  with_jit := disabled for rtlibs stage
+endif
+with_jit := $(call envfilt, jit, , , $(with_jit))
+
+ifeq (,$(findstring gcc-,$(PKGSOURCE)))
+  with_jit :=
+endif
+
+ifneq (,$(findstring build-cross, $(build_type)))
+  with_jit := disabled for cross builds
+endif
+
+ifeq ($(with_jit),yes)
+    ifeq ($(with_common_libs),yes)
+      with_libgccjit := yes
+    endif
+endif
+
+with_cc1 := yes
+with_cc1 := $(call envfilt, cc1, , , $(with_cc1))
+
+ifeq ($(with_cc1),yes)
+  ifeq ($(with_common_libs),yes)
+    with_libcc1 := yes
+  endif
+  with_libcc1_plugin := yes
+endif
+
+ifneq (,$(with_rtlibs))
+  with_libcc1 := disabled for rtlibs stage
+  with_libcc1_plugin := disabled for rtlibs stage
+endif
+ifneq (,$(findstring build-cross, $(build_type)))
+  with_libcc1 := disabled for cross builds
+endif
+
+# Build all packages needed for C development
+ifneq ($(with_base_only),yes)
+  ifeq ($(with_dev),yes)
+    with_cdev := yes
+  endif
+endif
+
+ifeq (,$(filter $(DEB_STAGE),stage1 stage2))
+# Ada --------------------
+ada_no_cpus	:= m32r sh3 sh3eb sh4eb
+# no Debian builds ... some of these should exist
+ada_no_cpus += powerpcspe
+ada_no_cpus += m68k # see https://bugs.debian.org/814221
+ada_no_cpus += mips64 # see https://gcc.gnu.org/PR65337
+ada_no_cpus += x32 # see https://gcc.gnu.org/PR61954
+ada_no_systems	:= 
+ada_no_cross	:= no
+ada_no_snap	:= no
+ifeq ($(single_package),yes)
+  ada_no_cpus += powerpcspe
+  ifneq (,$(filter $(DEB_TARGET_ARCH),mips mipsel powerpcspe kfreebsd-i386 kfreebsd-amd64))
+    #ada_no_cpus += mips mipsel
+    ada_no_cpus += kfreebsd-i386 kfreebsd-amd64
+    ada_no_snap := yes
+  endif
+endif
+
+ifeq ($(with_dev),yes)
+  ifneq ($(separate_lang),yes)
+    with_ada := yes
+  endif
+endif
+ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(ada_no_cpus)))
+  with_ada := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+ifneq (,$(filter $(DEB_TARGET_ARCH),powerpcspe x32))
+  with_ada := disabled for architecture $(DEB_TARGET_ARCH)
+endif
+ifneq (,$(findstring cross,$(build_type)))
+  ifneq (,$(filter $(DEB_BUILD_ARCH),powerpcspe x32))
+    with_ada := no gnat host compiler on $(DEB_BUILD_ARCH)
+  endif
+endif
+ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(ada_no_systems)))
+  with_ada := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+endif
+ifeq ($(ada_no_cross)-$(DEB_CROSS),yes-yes)
+  with_ada := disabled for cross compiler package
+endif
+ifeq ($(ada_no_snap)-$(single_package),yes-yes)
+  with_ada := disabled for snapshot build
+endif
+ifneq (,$(findstring gccgo,$(PKGSOURCE)))
+  with_ada :=
+endif
+ifneq (,$(filter $(distrelease),lucid))
+  with_ada :=
+endif
+# disable building gnat cross compilers on 32bit archs targeting 64bit archs
+ifneq (,$(filter $(build_type), build-cross cross-build-cross))
+  ifneq (,$(filter $(DEB_HOST_ARCH), armhf armel i386 mips mipsel mipsr6 mipsr6el powerpc))
+    ifneq (,$(filter $(DEB_TARGET_ARCH), alpha amd64 arm64 mips64 mips64el mips64r6 mips64r6el ppc64 ppc64el s390x sparc64))
+      with_ada := disabled on 32bit archs targeting 64bit archs
+    endif
+  endif
+endif
+with_ada := $(call envfilt, ada, , , $(with_ada))
+
+#with_ada := disabled for GCC 6
+
+ifeq ($(DEB_STAGE)-$(filter libgnat, $(with_rtlibs)),rtlibs-)
+  with_ada := disabled for rtlibs stage
+endif
+
+#ifneq ($(single_package),yes)
+#  with_separate_gnat := yes
+#endif
+
+ifneq ($(with_separate_gnat),yes)
+  ifeq ($(with_ada),yes)
+    ifneq (,$(filter $(distrelease),squeeze lucid))
+      with_ada :=
+    endif
+  endif
+endif
+
+ifeq ($(with_ada)-$(with_separate_gnat),yes-yes)
+  ifneq (,$(findstring gnat,$(PKGSOURCE)))
+    languages := c
+    separate_lang := yes
+    with_mudflap := no
+    with_gccbase := no
+    with_cdev := no
+    with_cc1 := no
+    with_libcc1 := no
+  else
+    debian_extra_langs += ada
+    with_ada := built from separate source
+    with_libgnat := built from separate source
+  endif
+endif
+
+ifeq ($(with_ada),yes)
+  enabled_languages += ada
+  with_libgnat := yes
+  with_gnatsjlj := yes
+endif
+
+# C++ -------------------------
+cxx_no_cpus := avr
+ifneq ($(with_base_only),yes)
+  ifneq ($(separate_lang),yes)
+    with_cxx := yes
+  endif
+endif
+ifneq (,$(findstring $(DEB_TARGET_ARCH_CPU),$(cxx_no_cpus)))
+  with_cxx := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+with_cxx := $(call envfilt, c++, obj-c++ java, , $(with_cxx))
+
+# Set the default libstdc++ ABI. libstdc++ provides both ABI's.
+# Existing code still runs with the new c++11 ABI, however link
+# errors are seen when one object is compiled with the new std::string in scope,
+# another object is compiled with the old std::string in scope. both can link
+# to libstdc++.so but not to each other.
+# two objects (which might be some system library and a user's program) need to
+# agree on the version of std::string they're using
+
+libstdcxx_abi = new
+# backports default to the old ABI
+ifneq (,$(filter $(distrelease),squeeze wheezy jessie lucid precise trusty utopic vivid))
+  libstdcxx_abi = gcc4-compatible
+endif
+
+# Build all packages needed for C++ development
+ifeq ($(with_cxx),yes)
+  ifeq ($(with_dev),yes)
+    with_cxxdev := yes
+    with_libcxxdbg := yes
+  endif
+  ifeq ($(with_common_libs),yes)
+    with_libcxx := yes
+  endif
+
+  # debugging versions of libstdc++
+  ifneq (,$(findstring gcc-, $(PKGSOURCE)))
+  ifeq ($(with_cxxdev),yes)
+    with_cxx_debug := yes
+    debug_no_cpus :=
+    ifneq (,$(findstring $(DEB_TARGET_ARCH_CPU),$(debug_no_cpus)))
+      with_cxx_debug := disabled for cpu $(DEB_TARGET_GNU_CPU)
+    endif
+  endif
+  endif
+  with_cxx_debug := $(call envfilt, debug, , , $(with_cxx_debug))
+
+  enabled_languages += c++
+endif
+
+# Java --------------------
+# - To build a standalone gcj package (with no corresponding gcc
+#   package): with_separate_libgcj=yes, with_standalone_gcj=yes
+# - To build the java packages from the gcc source package:
+#   with_separate_libgcj=no, with_standalone_gcj=no
+# - To build gcc and java from separate sources:
+#   with_separate_libgcj=yes, with_standalone_gcj=no
+
+java_no_cpus := # arm64 mips mipsel
+java_no_systems :=
+
+ifneq ($(single_package),yes)
+  with_separate_libgcj := yes
+endif
+with_separate_libgcj := no
+with_standalone_gcj := no
+
+ifneq ($(separate_lang),yes)
+  with_java := yes
+endif
+
+# java converted for V3 C++ ABI for some archs
+ifeq ($(with_base_only),yes)
+  with_java := no
+endif
+ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(java_no_cpus)))
+  with_java := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+ifneq (,$(filter $(DEB_TARGET_GNU_SYSTEM),$(java_no_systems)))
+  with_java := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+endif
+ifeq ($(java_no_cross)-$(DEB_CROSS),yes-yes)
+  with_java := disabled for cross compiler package
+endif
+with_java := $(call envfilt, java, , c++, $(with_java))
+
+ifeq ($(DEB_STAGE)-$(filter libgcj, $(with_rtlibs)),rtlibs-)
+  with_java := disabled for rtlibs stage
+endif
+
+ifneq (,$(findstring gccgo, $(PKGSOURCE)))
+  with_java :=
+endif
+
+ifeq ($(with_java)-$(with_separate_libgcj),yes-yes)
+  ifneq (,$(findstring gcj, $(PKGSOURCE)))
+    languages := c c++
+    separate_lang := yes
+  else
+    debian_extra_langs += java
+    with_java := built from separate source
+    with_gcj := built from separate source
+    with_libgcj := buit from separate source
+  endif
+endif
+
+with_java_plugin := no
+
+ifeq ($(with_java),yes)
+  # use the same names as OpenJDK
+  java_cpu_map = armel=arm armhf=arm arm64=aarch64 hppa=parisc \
+	i686=i386 i586=i386 i486=i386 x32=x32 \
+	mipsel=mips mips64=mips mips64el=mips mipsn32=mips mipsn32el=mips \
+	mipsr6el=mips mips64r6=mips mips64r6el=mips mipsn32r6=mips mipsn32r6el=mips \
+	powerpc=ppc ppc64el=ppc64le sh4=sh x32=x32
+  java_cpu = $(patsubst $(DEB_TARGET_ARCH_CPU)=%,%, \
+                         $(filter $(DEB_TARGET_ARCH_CPU)=%,$(java_cpu_map)))
+  ifeq (,$(java_cpu))
+    java_cpu = $(DEB_TARGET_ARCH_CPU)
+  endif
+  java_priority = 10$(subst .,,$(BASE_VERSION))0
+
+  with_libgcj := yes
+  with_libgcjbc := no
+
+  ifneq (,$(findstring gcj-4,$(PKGSOURCE)))
+    ifneq (,$(filter $(DEB_TARGET_ARCH), arm))
+      with_gcj_base_only := yes
+    endif
+  endif
+
+  ifeq ($(single_package),yes)
+    with_ecj := yes
+  endif
+
+  #ifneq (,$(filter $(DEB_TARGET_ARCH),hppa))
+  #  with_native_ecj := yes
+  #endif
+
+  ifneq (,$(filter $(DEB_TARGET_ARCH),arm armel))
+    with_external_ecj1 := yes
+  endif
+  ifeq (,$(filter $(distrelease),squeeze wheezy jessie lucid precise trusty xenial))
+    # not yet built ...
+    ifeq (,$(filter $(DEB_TARGET_ARCH),powerpcspe sh4))
+      with_external_ecj1 := yes
+    endif
+    with_external_ecj1 := yes
+  endif
+
+  with_java_maintainer_mode := no
+
+  # used as well in debian/rules.conf to determine the build deps
+  java_awt_peers = gtk # qt # xlib
+
+  with_libgcj_doc := yes
+
+  # Build all packages needed for Java development (gcj, libgcj-dev)
+  ifeq ($(with_dev),yes)
+    with_javadev := yes
+    with_gcj := yes
+  endif
+
+  with_java_alsa := yes
+  ifeq (,$(filter $(DEB_TARGET_GNU_SYSTEM),linux-gnu))
+    with_java_alsa := no
+  endif
+
+  # Just build the cross compiler to be able to cross build a native build.
+  ifeq ($(DEB_CROSS),yes)
+    with_libgcj :=
+  endif
+
+  enabled_languages += java
+endif
+
+# Go -------------------
+# - To build a standalone gccgo package (with no corresponding gcc
+#   package): with_separate_libgo=yes, with_standalone_go=yes
+# - To build the go packages from the gcc source package:
+#   with_separate_libgo=no, with_standalone_go=no
+# - To build gcc and go from separate sources:
+#   with_separate_libgo=yes, with_standalone_go=no
+
+go_no_cross := yes
+go_no_cross := no
+
+ifneq (,$(findstring gccgo, $(PKGSOURCE)))
+  with_separate_libgo := yes
+  with_standalone_go := yes
+  with_cc1 :=
+  with_libcc1 :=
+endif
+
+go_no_cpus := avr arm hppa sh4
+ifeq (,$(filter $(distrelease),lenny etch squeeze dapper hardy jaunty karmic lucid maverick natty oneiric))
+  go_no_cpus := $(filter-out arm, $(go_no_cpus))
+endif
+go_no_systems := kfreebsd
+
+ifneq ($(with_base_only),yes)
+  ifneq ($(separate_lang),yes)
+    with_go := yes
+  endif
+endif
+ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(go_no_cpus)))
+  with_go := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+ifneq (,$(findstring $(DEB_TARGET_ARCH_OS),$(go_no_systems)))
+  with_go := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+endif
+ifeq ($(go_no_cross)-$(DEB_CROSS),yes-yes)
+  with_go := disabled for cross compiler package
+endif
+ifeq ($(DEB_STAGE)-$(filter libgo, $(with_rtlibs)),rtlibs-)
+  with_go := disabled for rtlibs stage
+endif
+with_go := $(call envfilt, go, , , $(with_go))
+
+# Build all packages needed for Go development
+ifneq (,$(findstring gcc, $(PKGSOURCE)))
+  ifeq ($(with_go),yes)
+    with_libgo := yes
+    enabled_languages += go
+  endif
+endif
+
+ifeq ($(with_go)-$(with_separate_libgo),yes-yes)
+  ifneq (,$(findstring gccgo, $(PKGSOURCE)))
+    languages := c c++ go
+    separate_lang := yes
+    with_libgcc := yes
+    with_shared_libgcc := yes
+  else
+    debian_extra_langs += go
+    with_go := built from separate source
+    with_libgo := buit from separate source
+  endif
+endif
+
+# D ---------------------------
+d_no_cross := yes
+d_no_snap := yes
+d_no_cpus := s390
+
+ifneq ($(single_package),yes)
+  with_separate_gdc := yes
+endif
+with_separate_gdc := no
+
+ifneq ($(separate_lang),yes)
+  with_d := yes
+endif
+
+ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(d_no_cpus)))
+  with_d := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+ifeq ($(d_no_snap)-$(single_package),yes-yes)
+  with_d := disabled for snapshot build
+endif
+ifeq ($(DEB_STAGE)-$(filter libphobos, $(with_rtlibs)),rtlibs-)
+  with_d := disabled for rtlibs stage
+endif
+with_d := $(call envfilt, d, , , $(with_d))
+
+#with_d := not yet built for GCC 6
+
+ifeq ($(with_base_only),yes)
+  with_d := no
+endif
+
+ifeq ($(with_d)-$(with_separate_gdc),yes-yes)
+  ifneq (,$(findstring gdc,$(PKGSOURCE)))
+    languages := c c++
+    separate_lang := yes
+
+    # FIXME: language selection needs improvement.
+    with_go := disabled for d
+  else
+    debian_extra_langs += d
+    with_d := built from separate source
+  endif
+endif
+
+ifeq ($(with_d),yes)
+  libphobos_archs = amd64 armel armhf i386 x32 kfreebsd-amd64 kfreebsd-i386
+  ifneq (,$(filter $(DEB_TARGET_ARCH), $(libphobos_archs)))
+    with_libphobos := yes
+  endif
+
+  libphobos_no_cpus := alpha avr arm64 hppa ia64 m68k \
+	mips mipsel mips64 mips64el mipsn32 mipsn32el \
+	mipsr6 mipsr6el mips64r6 mips64r6el mipsn32r6 mipsn32r6el \
+	powerpc powerpcspe ppc64 s390 s390x sh4 sparc sparc64
+  libphobos_no_systems := gnu kfreebsd-gnu
+  ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(libphobos_no_cpus)))
+    with_libphobos := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+  endif
+  ifneq (,$(filter $(DEB_TARGET_GNU_SYSTEM),$(libphobos_no_systems)))
+    with_libphobos := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+  endif
+  with_libphobosdev := $(with_libphobos)
+
+  enabled_languages += d
+endif
+
+# Fortran 95 -------------------
+fortran_no_cross := yes
+fortran_no_cross := no
+
+ifneq ($(with_base_only),yes)
+  ifneq ($(separate_lang),yes)
+    with_fortran := yes
+  endif
+endif
+ifeq ($(fortran_no_cross)-$(DEB_CROSS),yes-yes)
+  with_fortran := disabled for cross compiler package
+endif
+ifeq ($(DEB_STAGE)-$(filter libgfortran libquadmath, $(with_rtlibs)),rtlibs-)
+  with_fortran := disabled for rtlibs stage
+endif
+
+with_fortran := $(call envfilt, fortran, , , $(with_fortran))
+
+# Build all packages needed for Fortran development
+ifeq ($(with_fortran),yes)
+  ifeq ($(with_dev),yes)
+    ifneq ($(DEB_STAGE)-$(filter libgfortran libquadmath, $(with_rtlibs)),rtlibs-)
+      with_fdev := yes
+    endif
+  endif
+  with_libgfortran := yes
+  enabled_languages += fortran
+endif
+
+# libquadmath -------------------
+
+ifneq (,$(findstring $(DEB_TARGET_ARCH_CPU), ia64 i386 i486 i586 i686 amd64))
+  # FIXME: upstream build tied to gfortran build
+  ifeq ($(with_fortran),yes)
+    with_qmath := yes
+    ifneq (,$(findstring gcc-6,$(PKGSOURCE)))
+      ifeq ($(with_common_libs),yes)
+        with_libqmath := yes
+      endif
+    endif
+  endif
+endif
+
+# ObjC ------------------------
+objc_no_cross := no
+
+ifneq ($(with_base_only),yes)
+  ifneq ($(separate_lang),yes)
+    with_objc := yes
+    objc_no_archs =
+    ifneq (,$(filter $(DEB_TARGET_ARCH),$(objc_no_archs)))
+      with_objc :=
+    endif
+  endif
+endif
+ifeq ($(objc_no_cross)-$(DEB_CROSS),yes-yes)
+  with_objc := disabled for cross compiler package
+endif
+ifeq ($(DEB_STAGE)-$(filter libobjc, $(with_rtlibs)),rtlibs-)
+  with_objc := disabled for rtlibs stage
+endif
+with_objc := $(call envfilt, objc, obj-c++, , $(with_objc))
+
+ifeq ($(with_objc),yes)
+  # the ObjC runtime with garbage collection enabled needs the Boehm GC
+  with_objc_gc := yes
+
+  # disable ObjC garbage collection library (needs libgc)
+  libgc_no_cpus := arm64 avr mips mipsel # alpha amd64 arm armel armhf hppa i386 ia64 m68k mips mipsel powerpc ppc64 s390 s390x sparc
+  libgc_no_systems := knetbsd-gnu
+  ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(libgc_no_cpus)))
+    with_objc_gc := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+  endif
+  ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(libgc_no_systems)))
+    with_objc_gc := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+  endif
+  ifneq (,$(findstring build-cross, $(build_type)))
+    with_objc_gc := disabled for cross builds
+  endif
+
+  # Build all packages needed for Objective-C development
+  ifeq ($(with_dev),yes)
+    with_objcdev := yes
+  endif
+  ifeq ($(with_common_libs),yes)
+    with_libobjc := yes
+  endif
+
+  enabled_languages += objc
+endif
+
+# ObjC++ ----------------------
+objcxx_no_cross := no
+
+ifeq ($(with_objc),yes)
+  ifneq ($(with_base_only),yes)
+    ifneq ($(separate_lang),yes)
+      with_objcxx := yes
+    endif
+  endif
+endif
+ifeq ($(objcxx_no_cross)-$(DEB_CROSS),yes-yes)
+  with_objcxx := disabled for cross compiler package
+endif
+with_objcxx := $(call envfilt, obj-c++, , c++ objc, $(with_objcxx))
+
+ifeq ($(with_objcxx),yes)
+  enabled_languages += obj-c++
+endif
+
+# -------------------------------------------------------------------
+# other config
+
+# not built from the main source package
+ifeq (,$(findstring gcc-,$(PKGSOURCE)))
+  extra_package := yes
+endif
+
+with_nls := yes
+ifeq ($(trunk_build),yes)
+  with_nls := no
+endif
+with_nls := $(call envfilt, nls, , , $(with_nls))
+
+# powerpc nof libraries -----
+with_libnof := no
+
+ifneq (,$(findstring gcc-6,$(PKGSOURCE)))
+  ifeq (,$(with_rtlibs))
+    with_source := yes
+  endif
+endif
+with_source := $(call envfilt, source, , , $(with_source))
+
+ifeq ($(with_cdev),yes)
+
+# ssp & libssp -------------------------
+with_ssp := yes
+ssp_no_archs = alpha hppa ia64 m68k
+ifneq (, $(filter $(DEB_TARGET_ARCH),$(ssp_no_archs) $(ssp_no_archs:%=uclibc-%)))
+  with_ssp := not available on $(DEB_TARGET_ARCH)
+endif
+with_ssp := $(call envfilt, ssp, , , $(with_ssp))
+
+ifeq ($(with_ssp),yes)
+  ifneq ($(derivative),Debian)
+    ifneq (,$(findstring gcc-6, $(PKGSOURCE)))
+      with_ssp_default := yes
+    endif
+  endif
+endif
+
+# gomp --------------------
+with_gomp := yes
+with_gomp := $(call envfilt, gomp, , , $(with_gomp))
+gomp_no_archs =
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(gomp_no_archs)))
+  with_gomp :=
+endif
+
+# itm --------------------
+itm_archs = alpha amd64 arm64 i386 x32 ppc64 ppc64el s390x sh4 sparc64
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(itm_archs)))
+  with_itm := yes
+endif
+with_itm := $(call envfilt, itm, , , $(with_itm))
+
+# atomic --------------------
+with_atomic := yes
+atomic_no_archs =
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(atomic_no_archs)))
+  with_atomic :=
+endif
+
+# backtrace --------------------
+with_backtrace := yes
+backtrace_no_archs = m68k
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(backtrace_no_archs)))
+  with_backtrace :=
+endif
+
+# asan / sanitizer --------------------
+with_asan :=
+with_asan := $(call envfilt, asan, , , $(with_asan))
+asan_archs = amd64 armel armhf arm64 i386 powerpc ppc64 ppc64el x32 sparc sparc64
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(asan_archs)))
+  with_asan := yes
+endif
+
+# lsan / sanitizer --------------------
+with_lsan :=
+with_lsan := $(call envfilt, lsan, , , $(with_lsan))
+lsan_archs = amd64
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(lsan_archs)))
+  with_lsan := yes
+endif
+
+# tsan / sanitizer --------------------
+with_tsan :=
+with_tsan := $(call envfilt, tsan, , , $(with_tsan))
+tsan_archs = amd64
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(tsan_archs)))
+  with_tsan := yes
+endif
+
+endif # with_cdev
+
+# ubsan / sanitizer --------------------
+with_ubsan :=
+with_ubsan := $(call envfilt, ubsan, , , $(with_ubsan))
+ubsan_archs = amd64 armel armhf arm64 i386 powerpc ppc64 ppc64el x32 sparc sparc64
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(ubsan_archs)))
+  with_ubsan := yes
+endif
+
+# libvtv --------------------
+with_vtv :=
+with_vtv := $(call envfilt, vtv, , , $(with_vtv))
+vtv_archs = amd64 i386 x32
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(vtv_archs)))
+  with_vtv := yes
+  with_libvtv := yes
+endif
+# libvtv builds a modified libstdc++, don't enable it by default
+with_vtv :=
+with_libvtv :=
+
+# libcilkrts --------------------
+with_cilkrts :=
+with_cilkrts := $(call envfilt, cilkrts, , , $(with_cilkrts))
+cilkrts_archs = amd64 i386 x32
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(cilkrts_archs)))
+  with_cilkrts := yes
+endif
+
+# libmpx --------------------
+with_mpx :=
+with_mpx := $(call envfilt, mpx, , , $(with_mpx))
+mpx_archs = amd64 i386
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(mpx_archs)))
+  # requires newer binutils, or else libmpxwrappers isn't built
+  ifeq (,$(filter $(distrelease),squeeze lucid precise))
+    with_mpx := yes
+    ifeq ($(with_common_libs),yes)
+      ifneq (,$(findstring gcc-, $(PKGSOURCE)))
+        with_libmpx := yes
+      endif
+    endif
+  endif
+endif
+
+# pie by default --------------------
+with_pie :=
+ifeq ($(distribution),Debian)
+  ifeq (,$(filter $(distrelease),wheezy squeeze jessie))
+    pie_archs = amd64 arm64 armel armhf i386 \
+		mips mipsel mips64 mips64el mipsn32 mipsn32el \
+		mipsr6 mipsr6el mips64r6 mips64r6el mipsn32r6 mipsn32r6el \
+		ppc64el s390x sparc sparc64 kfreebsd-amd64 kfreebsd-i386
+  endif
+  ifeq (,$(filter $(distrelease),wheezy squeeze jessie stretch))
+    pie_archs += powerpc ppc64
+  endif
+else ifeq ($(distribution),Ubuntu)
+  ifeq (,$(filter $(distrelease),lucid precise trusty utopic vivid wily))
+    pie_archs = s390x
+  endif
+  ifeq (,$(filter $(distrelease),lucid precise trusty utopic vivid wily xenial))
+    pie_archs += amd64 ppc64el
+  endif
+  ifeq (,$(filter $(distrelease),lucid precise trusty utopic vivid wily xenial yakkety zesty))
+    pie_archs += armhf arm64 i386
+  endif
+endif
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(pie_archs)))
+  with_pie := yes
+endif
+
+# gold --------------------
+# armel with binutils 2.20.51 only
+gold_archs = amd64 armel armhf i386 powerpc powerpcspe ppc64 ppc64el sparc sparc64 x32 hurd-i386
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(gold_archs)))
+  with_gold := yes
+endif
+
+# plugins --------------------
+with_plugins := yes
+ifneq (,$(with_rtlibs))
+  with_plugins := disabled for rtlibs stage
+endif
+
+endif # ifeq (,$(filter $(DEB_STAGE),stage1 stage2))
+
+# Don't include docs with GFDL invariant sections
+GFDL_INVARIANT_FREE := yes
+ifeq ($(derivative),Ubuntu)
+  GFDL_INVARIANT_FREE := no
+endif
+
+# -------------------------------------------------------------------
+# non-extra config
+ifeq ($(extra_package),yes)
+  ifeq ($(with_separate_libgcj)-$(with_standalone_gcj),yes-no)
+    # package stuff
+    with_gccbase := no
+    with_cdev := no
+    with_cxx := no
+    with_cxxdev := no
+
+    ifneq ($(DEB_CROSS),yes)
+      with_gcjbase := yes
+    else
+      with_gcjxbase := yes
+    endif
+  endif
+  ifeq ($(with_separate_libgo),yes)
+    # package stuff
+    with_gccbase := yes
+    with_cdev := no
+    with_cxx := no
+    with_cxxdev := no
+  endif
+else
+  # libssp ------------------
+  ifeq ($(with_ssp)-$(with_common_libs),yes-yes)
+    #ifneq ($(DEB_CROSS),yes)
+      with_libssp := $(if $(wildcard $(builddir)/gcc/auto-host.h),$(shell if grep -qs '^\#define TARGET_LIBC_PROVIDES_SSP 1' $(builddir)/gcc/auto-host.h; then echo 'libc provides ssp'; else echo 'yes'; fi))
+    #endif
+    with_libssp := libc provides ssp
+  endif
+
+  # libgomp -----------------
+  ifeq ($(with_gomp)-$(with_common_libs),yes-yes)
+      with_libgomp := yes
+  endif
+
+  # libitm -----------------
+  ifeq ($(with_itm)-$(with_common_libs),yes-yes)
+      with_libitm := yes
+  endif
+
+  # libatomic -----------------
+  ifeq ($(with_atomic)-$(with_common_libs),yes-yes)
+      with_libatomic := yes
+  endif
+
+  # libbacktrace -----------------
+  ifeq ($(with_backtrace)-$(with_common_libs),yes-yes)
+      # currently not a shared library
+      #with_libbacktrace := yes
+  endif
+
+  # libasan -----------------
+  # asan changes soname in GCC 6
+  #ifeq ($(with_asan)-$(with_common_libs),yes-yes)
+    ifeq ($(with_asan),yes)
+      with_libasan := yes
+    endif
+  #endif
+
+  # liblsan -----------------
+  ifeq ($(with_lsan)-$(with_common_libs),yes-yes)
+    #ifneq ($(DEB_CROSS),yes)
+      with_liblsan := yes
+    #endif
+  endif
+
+  # libtsan -----------------
+  ifeq ($(with_tsan)-$(with_common_libs),yes-yes)
+      with_libtsan := yes
+  endif
+
+  # libubsan -----------------
+  ifeq ($(with_ubsan)-$(with_common_libs),yes-yes)
+      with_libubsan := yes
+  endif
+
+  # libvtv -----------------
+  ifeq ($(with_vtv)-$(with_common_libs),yes-yes)
+      with_libvtv := yes
+  endif
+
+  # libmpx -----------------
+  ifeq ($(with_mpx)-$(with_common_libs),yes-yes)
+      with_libmpx := yes
+  endif
+
+  # libcilkrts -----------------
+  ifeq ($(with_cilkrts)-$(with_common_libs),yes-yes)
+      with_libcilkrts := yes
+  endif
+
+  # libquadmath -----------------
+  ifeq ($(with_qmath)-$(with_common_libs),yes-yes)
+      with_libqmath := yes
+  endif
+
+  # fixincludes -------
+  ifneq ($(DEB_CROSS),yes)
+    ifeq ($(with_common_pkgs),yes)
+      with_fixincl	:= yes
+    endif
+  endif
+
+  # Shared libgcc --------------------
+  ifneq ($(DEB_STAGE),stage1)
+    with_shared_libgcc := yes
+    ifeq ($(with_common_libs),yes)
+      with_libgcc := yes
+    endif
+  endif
+
+  # libgcc-math --------------------
+  with_libgmath := no
+  ifneq (,$(findstring i486,$(DEB_TARGET_ARCH)))
+    #with_libgccmath := yes
+    #with_lib64gmath := yes
+    #with_libgmathdev := yes
+  endif
+  ifeq ($(DEB_TARGET_ARCH),amd64)
+    #with_libgccmath := yes
+    #with_lib32gmath := yes
+    #with_libgmathdev := yes
+  endif
+
+  # hppa64 build ----------------
+  hppa64_no_snap := no
+  hppa64_archs := hppa
+  ifneq (,$(filter $(build_type), build-native cross-build-native))
+    ifeq (,$(filter $(distrelease),wheezy squeeze jessie lucid precise trusty utopic vivid wily))
+      hppa64_archs += amd64 i386 x32
+    endif
+    ifneq (,$(filter $(DEB_TARGET_ARCH),$(hppa64_archs)))
+      with_hppa64 := yes
+    endif
+  endif
+  ifeq ($(hppa64_no_snap)-$(trunk_build),yes-yes)
+    with_hppa64 := disabled for snapshot build
+  endif
+  with_hppa64 := $(call envfilt, hppa64, , , $(with_hppa64))
+
+  ifeq ($(DEB_STAGE),rtlibs)
+    with_libatomic := disabled for rtlibs stage
+    with_libasan := disabled for rtlibs stage
+    with_liblsan := disabled for rtlibs stage
+    with_libtsan := disabled for rtlibs stage
+    with_libubsan := disabled for rtlibs stage
+    with_libcilkrts := disabled for rtlibs stage
+    with_fixincl := disabled for rtlibs stage
+    with_hppa64 := disabled for rtlibs stage
+  endif
+
+  # neon build -------------------
+  # FIXME: build as a cross compiler to build on armv4 as well
+  ifneq (,$(findstring gcc-6, $(PKGSOURCE)))
+    ifeq ($(derivative),Ubuntu)
+#      neon_archs = armel armhf
+#      ifneq (, $(filter $(DEB_TARGET_ARCH),$(neon_archs)))
+#        with_neon = yes
+#      endif
+    endif
+  endif
+endif
+
+# run testsuite ---------------
+with_check := yes
+# if you don't want to run the gcc testsuite, uncomment the next line
+#with_check := disabled by hand
+ifeq ($(with_base_only),yes)
+  with_check := no
+endif
+ifeq ($(DEB_CROSS),yes)
+  with_check := disabled for cross compiler package
+endif
+ifneq (,$(findstring cross-build-,$(build_type)))
+  with_check := disabled for cross building the compiler
+endif
+ifneq (,$(with_rtlibs))
+  with_check := disabled for rtlibs stage
+endif
+check_no_cpus := m68k
+check_no_systems := gnu kfreebsd-gnu
+ifneq (,$(filter $(DEB_TARGET_ARCH_CPU),$(check_no_cpus)))
+  with_check := disabled for cpu $(DEB_TARGET_ARCH_CPU)
+endif
+ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(check_no_systems)))
+  with_check := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+endif
+ifeq ($(derivative)-$(DEB_HOST_ARCH),Ubuntu-hppa)
+  ifneq ($(single_package),yes)
+    with_check := disabled, testsuite timeouts with expect
+  endif
+endif
+ifneq (,$(findstring gdc,$(PKGSOURCE)))
+  with_check := disabled for D
+endif
+with_check := $(call envfilt, check, , , $(with_check))
+ifdef WITHOUT_CHECK
+  with_check := disabled by environment
+endif
+ifneq ($(findstring nocheck, $(DEB_BUILD_OPTIONS)),)
+  with_check := disabled by DEB_BUILD_OPTIONS
+endif
+ifneq (,$(filter $(DEB_HOST_ARCH), hppa mips))
+  ifneq ($(single_package),yes)
+    with_check := disabled for $(DEB_HOST_ARCH), testsuite timeouts with expect
+  endif
+endif
+#with_check := disabled for this upload
+
+# not a dependency on all archs, but if available, use it for the testsuite
+ifneq (,$(wildcard /usr/bin/localedef))
+  locale_data = generate
+endif
+
+ifneq (,$(filter $(build_type), build-cross cross-build-cross))
+  ldconfig_arg = --noscripts
+endif
+
+all_enabled_languages := $(enabled_languages)
+languages_without_lang_opt := c++ objc obj-c++
+
+debian_extra_langs := $(subst obj-c++,objcp,$(debian_extra_langs))
+export debian_extra_langs
+
+# multilib
+biarch_map := i686=x86_64 powerpc=powerpc64 sparc=sparc64 sparc64=sparc s390=s390x s390x=s390 \
+		x86_64=i686 powerpc64=powerpc mips=mips64 mipsel=mips64el \
+		mips64=mips mips64el=mipsel mipsn32=mips mipsn32el=mipsel \
+		mipsr6=mips64r6 mipsr6el=mips64r6el mips64r6=mipsr6 mips64r6el=mipsr6el \
+		mipsn32r6=mipsr6 mipsn32r6el=mipsr6el
+ifneq (,$(filter $(derivative),Ubuntu))
+  ifeq (,$(filter $(distrelease),dapper hardy jaunty karmic lucid))
+    biarch_map := $(subst i686=,i486=,$(biarch_map))
+  endif
+else # Debian
+  biarch_map := $(subst i686=,i486=,$(biarch_map))
+endif
+
+ifeq ($(derivative),Ubuntu)
+  ifeq (,$(filter $(distrelease),dapper hardy jaunty karmic lucid maverick natty))
+    biarch_map += arm=arm
+  endif
+endif
+biarch_cpu := $(strip $(patsubst $(DEB_TARGET_GNU_CPU)=%,%, \
+			 $(filter $(DEB_TARGET_GNU_CPU)=%,$(biarch_map))))
+
+biarch64 := no
+biarch32 := no
+biarchn32 := no
+biarchx32 := no
+biarchhf := no
+biarchsf := no
+flavours :=
+define gen_biarch
+  ifneq (yes,$$(call envfilt, biarch, , ,yes))
+    biarch$1archs :=
+  endif
+  ifneq (,$$(findstring /$$(DEB_TARGET_ARCH)/,$$(biarch$1archs)))
+    biarch$1 := yes
+    flavours += $1
+    #biarch$1subdir = $$(biarch_cpu)-$$(DEB_TARGET_GNU_SYSTEM)
+    biarch$1subdir = $1
+    ifeq ($$(with_libgcc),yes)
+      with_lib$1gcc := yes
+    endif
+    ifeq ($$(with_cdev),yes)
+      with_lib$1gccdev := yes
+    endif
+    ifeq ($$(with_libcxx),yes)
+      with_lib$1cxx := yes
+    endif
+    ifeq ($$(with_libcxxdbg),yes)
+      with_lib$1cxxdbg := yes
+    endif
+    ifeq ($$(with_cxxdev),yes)
+      with_lib$1cxxdev := yes
+    endif
+    ifeq ($$(with_libobjc),yes)
+      with_lib$1objc := yes
+    endif
+    ifeq ($$(with_objcdev),yes)
+      with_lib$1objcdev := yes
+    endif
+    ifeq ($$(with_libgfortran),yes)
+      with_lib$1gfortran := yes
+    endif
+    ifeq ($$(with_fdev),yes)
+      with_lib$1gfortrandev := yes
+    endif
+    ifeq (,$(filter $1, hf))
+      ifeq ($$(with_libphobos),yes)
+        with_lib$1phobos := yes
+      endif
+      ifeq ($$(with_libphobosdev),yes)
+        with_lib$1phobosdev := yes
+      endif
+    endif
+    ifeq ($$(with_libssp),yes)
+      with_lib$1ssp := yes
+    endif
+    ifeq ($$(with_libgomp),yes)
+      with_lib$1gomp:= yes
+    endif
+    ifeq ($$(with_libitm),yes)
+      with_lib$1itm:= yes
+    endif
+    ifeq ($$(with_libatomic),yes)
+      with_lib$1atomic:= yes
+    endif
+    ifeq ($$(with_libbacktrace),yes)
+      with_lib$1backtrace:= yes
+    endif
+    ifeq ($$(with_libasan),yes)
+      with_lib$1asan:= yes
+    endif
+    ifeq ($$(with_liblsan),yes)
+      with_lib$1lsan := yes
+    endif
+    ifeq ($$(with_libtsan),yes)
+      with_lib$1tsan:= yes
+    endif
+    ifeq ($$(with_libubsan),yes)
+      with_lib$1ubsan := yes
+    endif
+    ifeq ($$(with_libvtv),yes)
+      with_lib$1vtv := yes
+    endif
+    ifeq ($$(with_libcilkrts),yes)
+      with_lib$1cilkrts := yes
+    endif
+    ifeq ($$(with_libmpx),yes)
+      ifneq (,$(filter $1, 32 64))
+        with_lib$1mpx := yes
+      endif
+    endif
+    ifeq ($$(with_libqmath),yes)
+      with_lib$1qmath := yes
+    endif
+    ifeq ($$(with_libgo),yes)
+      with_lib$1go := yes
+    endif
+
+    biarch_multidir_names = libiberty libgcc libbacktrace libatomic libgomp
+    ifneq (,$$(findstring gcc-, $$(PKGSOURCE)))
+      biarch_multidir_names += libstdc++-v3 libobjc libgfortran libssp \
+				zlib libitm libmpx \
+				libsanitizer \
+				libcilkrts libvtv
+      ifeq ($$(with_objc_gc),yes)
+        biarch_multidir_names += boehm-gc
+      endif
+    endif
+    ifneq (,$(findstring yes, $(with_java) $(with_go)))
+      biarch_multidir_names += libffi
+    endif
+    ifeq ($(with_fortran),yes)
+      biarch_multidir_names += libquadmath
+    endif
+    ifeq ($(with_go),yes)
+      biarch_multidir_names += libgo
+    endif
+    ifeq ($(with_libphobos),yes)
+      ifeq (,$(filter $1, hf))
+        biarch_multidir_names += libphobos
+      endif
+    endif
+    ifneq (,$$(findstring 32,$1))
+      TARGET64_MACHINE := $$(strip $$(subst $$(DEB_TARGET_GNU_CPU),$$(biarch_cpu), \
+				$$(TARGET_ALIAS)))
+      TARGET32_MACHINE := $$(TARGET_ALIAS)
+    else
+      TARGET64_MACHINE := $$(TARGET_ALIAS)
+      TARGET64_MACHINE := $$(strip $$(subst $$(DEB_TARGET_GNU_CPU),$$(biarch_cpu), \
+				$$(TARGET_ALIAS)))
+    endif
+    export TARGET32_MACHINE
+    export TARGET64_MACHINE
+  endif
+endef
+biarch32archs := /amd64/ppc64/kfreebsd-amd64/s390x/sparc64/x32/mipsn32/mipsn32el/mips64/mips64el/mipsn32r6/mipsn32r6el/mips64r6/mips64r6el/
+biarch64archs := /i386/powerpc/sparc/s390/mips/mipsel/mipsn32/mipsn32el/mipsr6/mipsr6el/mipsn32r6/mipsn32r6el/x32/
+biarchn32archs := /mips/mipsel/mips64/mips64el/mipsr6/mipsr6el/mips64r6/mips64r6el/
+ifeq ($(derivative),Ubuntu)
+  ifeq (,$(filter $(distrelease),dapper hardy jaunty karmic lucid maverick natty))
+    biarchhfarchs := /armel/
+    biarchsfarchs := /armhf/
+  endif
+  ifeq (,$(filter $(distrelease),dapper hardy jaunty karmic lucid maverick natty oneiric precise quantal))
+    biarchx32archs := /amd64/i386/
+  endif
+endif
+ifeq ($(derivative),Debian)
+  ifeq (,$(filter $(distrelease),etch squeeze wheezy))
+    biarchx32archs := /amd64/i386/
+  endif
+endif
+$(foreach x,32 64 n32 x32 hf sf,$(eval $(call gen_biarch,$(x))))
+
+ifeq ($(DEB_TARGET_ARCH),sh4)
+  biarch_multidir_names=none
+endif
+export biarch_multidir_names
+
+#ifeq ($(trunk_build),yes)
+#  no_biarch_libs := yes
+#endif
+no_biarch_libs :=
+
+ifeq ($(no_biarch_libs),yes)
+  with_lib64gcc		:= no
+  with_lib64cxx		:= no
+  with_lib64cxxdbg	:= no
+  with_lib64objc	:= no
+  with_lib64ffi		:= no
+  with_lib64gcj		:= no
+  with_lib64gfortran	:= no
+  with_lib64ssp		:= no
+  with_lib64go		:= no
+  with_lib64gomp	:= no
+  with_lib64itm		:= no
+  with_lib64qmath	:= no
+  with_lib64atomic	:= no
+  with_lib64backtrace	:= no
+  with_lib64asan	:= no
+  with_lib64lsan	:= no
+  with_lib64tsan	:= no
+  with_lib64ubsan	:= no
+  with_lib64vtv		:= no
+  with_lib64cilkrts	:= no
+  with_lib64mpx		:= no
+  with_lib64gccdev	:= no
+  with_lib64cxxdev	:= no
+  with_lib64objcdev	:= no
+  with_lib64gfortrandev	:= no
+  with_lib64phobosdev	:= no
+
+  with_lib32gcc		:= no
+  with_lib32cxx		:= no
+  with_lib32cxxdbg	:= no
+  with_lib32objc	:= no
+  with_lib32ffi		:= no
+  with_lib32gcj		:= no
+  with_lib32gfortran	:= no
+  with_lib32ssp		:= no
+  with_lib32go		:= no
+  with_lib32gomp	:= no
+  with_lib32itm		:= no
+  with_lib32qmath	:= no
+  with_lib32atomic	:= no
+  with_lib32backtrace	:= no
+  with_lib32asan	:= no
+  with_lib32lsan	:= no
+  with_lib32tsan	:= no
+  with_lib32ubsan	:= no
+  with_lib32vtv		:= no
+  with_lib32cilkrts	:= no
+  with_lib32mpx		:= no
+  with_lib32gccdev	:= no
+  with_lib32cxxdev	:= no
+  with_lib32objcdev	:= no
+  with_lib32gfortrandev	:= no
+  with_lib32phobosdev	:= no
+
+  with_libn32gcc	:= no
+  with_libn32cxx	:= no
+  with_libn32cxxdbg	:= no
+  with_libn32objc	:= no
+  with_libn32ffi	:= no
+  with_libn32gcj	:= no
+  with_libn32gfortran	:= no
+  with_libn32ssp	:= no
+  with_libn32go		:= no
+  with_libn32gomp	:= no
+  with_libn32itm	:= no
+  with_libn32qmath	:= no
+  with_libn32atomic	:= no
+  with_libn32backtrace	:= no
+  with_libn32asan	:= no
+  with_libn32lsan	:= no
+  with_libn32tsan	:= no
+  with_libn32ubsan	:= no
+  with_libn32gccdev	:= no
+  with_libn32cxxdev	:= no
+  with_libn32objcdev	:= no
+  with_libn32gfortrandev:= no
+  with_libn32phobosdev	:= no
+
+  with_libx32gcc	:= no
+  with_libx32cxx	:= no
+  with_libx32cxxdbg	:= no
+  with_libx32objc	:= no
+  with_libx32ffi	:= no
+  with_libx32gcj	:= no
+  with_libx32gfortran	:= no
+  with_libx32ssp	:= no
+  with_libx32go		:= no
+  with_libx32gomp	:= no
+  with_libx32itm	:= no
+  with_libx32qmath	:= no
+  with_libx32atomic	:= no
+  with_libx32backtrace	:= no
+  with_libx32asan	:= no
+  with_libx32lsan	:= no
+  with_libx32tsan	:= no
+  with_libx32ubsan	:= no
+  with_libx32vtv	:= no
+  with_libx32cilkrts	:= no
+  with_libx32gccdev	:= no
+  with_libx32cxxdev	:= no
+  with_libx32objcdev	:= no
+  with_libx32gfortrandev:= no
+  with_libx32phobosdev	:= no
+
+  with_libhfgcc		:= no
+  with_libhfcxx		:= no
+  with_libhfcxxdbg	:= no
+  with_libhfobjc	:= no
+  with_libhfffi		:= no
+  with_libhfgcj		:= no
+  with_libhfgfortran	:= no
+  with_libhfssp		:= no
+  with_libhfgo		:= no
+  with_libhfgomp	:= no
+  with_libhfitm		:= no
+  with_libhfqmath	:= no
+  with_libhfatomic	:= no
+  with_libhfbacktrace	:= no
+  with_libhfasan	:= no
+  with_libhflsan	:= no
+  with_libhftsan	:= no
+  with_libhfubsan	:= no
+  with_libhfgccdev	:= no
+  with_libhfcxxdev	:= no
+  with_libhfobjcdev	:= no
+  with_libhfgfortrandev	:= no
+  with_libhfphobosdev	:= no
+
+  with_libsfgcc		:= no
+  with_libsfcxx		:= no
+  with_libsfcxxdbg	:= no
+  with_libsfobjc	:= no
+  with_libsfffi		:= no
+  with_libsfgcj		:= no
+  with_libsfgfortran	:= no
+  with_libsfssp		:= no
+  with_libsfgo		:= no
+  with_libsfgomp	:= no
+  with_libsfitm		:= no
+  with_libsfqmath	:= no
+  with_libsfatomic	:= no
+  with_libsfbacktrace	:= no
+  with_libsfasan	:= no
+  with_libsflsan	:= no
+  with_libsftsan	:= no
+  with_libsfubsan	:= no
+  with_libsfgccdev	:= no
+  with_libsfcxxdev	:= no
+  with_libsfobjcdev	:= no
+  with_libsfgfortrandev	:= no
+  with_libsfphobosdev	:= no
+
+  with_java_plugin := no
+
+  ifeq ($(with_ada)-$(with_separate_gnat),yes-yes)
+    biarchhf	:= disabled for Ada
+    biarchsf	:= disabled for Ada
+  endif
+
+endif
+
+ifneq (,$(filter yes,$(biarch32) $(biarch64) $(biarchn32) $(biarchx32) $(biarchhf) $(biarchsf)))
+  multilib := yes
+endif
+
+multilib_archs = $(sort $(subst /, , $(biarch64archs) $(biarch32archs) $(biarchn32archs) $(biarchx32archs) $(biarchhfarchs) $(biarchsfarchs)))
+
+biarchsubdirs := \
+  $(if $(filter yes,$(biarch64)),$(biarch64subdir),) \
+  $(if $(filter yes,$(biarch32)),$(biarch32subdir),) \
+  $(if $(filter yes,$(biarchn32)),$(biarchn32subdir),) \
+  $(if $(filter yes,$(biarchx32)),$(biarchx32subdir),) \
+  $(if $(filter yes,$(biarchhf)),$(biarchhfsubdir),) \
+  $(if $(filter yes,$(biarchsf)),$(biarchsfsubdir),)
+biarchsubdirs := {$(strip $(shell echo $(biarchsubdirs) | tr " " ","))}
+
+# GNU locales
+force_gnu_locales := yes
+locale_no_cpus :=
+locale_no_systems :=
+ifneq (,$(findstring $(DEB_TARGET_GNU_SYSTEM),$(locale_no_systems)))
+  force_gnu_locales := disabled for system $(DEB_TARGET_GNU_SYSTEM)
+endif
+
+gcc_tarpath		:= $(firstword $(wildcard gcc-*.tar.* /usr/src/gcc-6/gcc-*.tar.*))
+gcc_tarball		:= $(notdir $(gcc_tarpath))
+gcc_srcdir		:= $(subst -dfsg,,$(patsubst %.tar.xz,%,$(patsubst %.tar.lzma,%,$(patsubst %.tar.gz,%,$(gcc_tarball:.tar.bz2=)))))
+
+ifeq ($(with_d),yes)
+  gdc_tarpath		:= $(firstword $(wildcard gdc-*.tar.* /usr/src/gcc-$(BASE_VERSION)/gdc-*.tar.*))
+  gdc_tarball		:= $(notdir $(gdc_tarpath))
+  gdc_srcdir		:= $(patsubst %.tar.xz,%,$(patsubst %.tar.lzma,%,$(patsubst %.tar.gz,%,$(gdc_tarball:.tar.bz2=))))
+endif
+
+# NOTE: This is not yet used. when building gcj, gdc or gnat using the
+# gcc-source package, we don't require an exact binary dependency.
+ifneq ($(dir $(gcc_tarpath)),./)
+  built_using_external_source := yes
+else
+  built_using_external_source :=
+endif
+ifeq ($(DEB_CROSS),yes)
+  add_built_using = yes
+endif
+ifeq ($(with_ada)-$(with_separate_gnat),yes-yes)
+  add_built_using = yes
+endif
+
+ecj_jar := $(firstword $(wildcard ecj.jar /usr/share/java/eclipse-ecj.jar /usr/share/java/ecj.jar))
+
+unpack_stamp		:= $(stampdir)/01-unpack-stamp
+pre_patch_stamp		:= $(stampdir)/02-pre-patch-stamp
+patch_stamp		:= $(stampdir)/02-patch-stamp
+control_stamp		:= $(stampdir)/03-control-stamp
+configure_stamp		:= $(stampdir)/04-configure-stamp
+build_stamp		:= $(stampdir)/05-build-stamp
+build_arch_stamp	:= $(stampdir)/05-build-arch-stamp
+build_indep_stamp	:= $(stampdir)/05-build-indep-stamp
+build_html_stamp	:= $(stampdir)/05-build-html-stamp
+build_locale_stamp	:= $(stampdir)/05-build-locale-stamp
+build_doxygen_stamp	:= $(stampdir)/05-build-doxygen-stamp
+build_javasrc_stamp	:= $(stampdir)/05-build-javasrc-stamp
+build_javadoc_stamp	:= $(stampdir)/05-build-javadoc-stamp
+build_gnatdoc_stamp	:= $(stampdir)/05-build-gnatdoc-stamp
+check_stamp		:= $(stampdir)/06-check-stamp
+check_inst_stamp	:= $(stampdir)/06-check-inst-stamp
+install_stamp		:= $(stampdir)/07-install-stamp
+install_snap_stamp	:= $(stampdir)/07-install-snap-stamp
+binary_stamp		:= $(stampdir)/08-binary-stamp
+
+configure_dummy_stamp	:= $(stampdir)/04-configure-dummy-stamp
+build_dummy_stamp	:= $(stampdir)/05-build-dummy-stamp
+install_dummy_stamp	:= $(stampdir)/07-install-dummy-stamp
+
+configure_jit_stamp	:= $(stampdir)/04-configure-jit-stamp
+build_jit_stamp		:= $(stampdir)/05-build-jit-stamp
+install_jit_stamp	:= $(stampdir)/07-install-jit-stamp
+
+configure_hppa64_stamp	:= $(stampdir)/04-configure-hppa64-stamp
+build_hppa64_stamp	:= $(stampdir)/05-build-hppa64-stamp
+install_hppa64_stamp	:= $(stampdir)/07-install-hppa64-stamp
+
+configure_neon_stamp	:= $(stampdir)/04-configure-neon-stamp
+build_neon_stamp		:= $(stampdir)/05-build-neon-stamp
+install_neon_stamp	:= $(stampdir)/07-install-neon-stamp
+
+control_dependencies	:= $(patch_stamp)
+
+ifeq ($(single_package),yes)
+    configure_dependencies = $(configure_stamp)
+    build_dependencies = $(build_stamp)
+    install_dependencies = $(install_snap_stamp)
+    ifeq ($(with_check),yes)
+      check_dependencies += $(check_stamp)
+    endif
+else
+  ifeq ($(with_base_only),yes)
+    configure_dependencies = $(configure_dummy_stamp)
+    build_dependencies = $(build_dummy_stamp)
+    install_dependencies = $(install_dummy_stamp)
+  else
+    configure_dependencies = $(configure_stamp)
+    build_dependencies = $(build_stamp)
+    install_dependencies = $(install_stamp)
+    ifeq ($(with_check),yes)
+      check_dependencies += $(check_stamp)
+    endif
+  endif
+endif
+
+ifneq (,$(findstring gcj-, $(PKGSOURCE)))
+  ifeq ($(with_gcj_base_only),yes)
+    configure_dependencies = $(configure_dummy_stamp)
+    build_dependencies = $(build_dummy_stamp)
+    install_dependencies = $(install_dummy_stamp)
+  endif
+endif
+
+ifeq ($(with_jit),yes)
+  build_dependencies += $(build_jit_stamp)
+  install_dependencies += $(install_jit_stamp)
+endif
+
+ifeq ($(with_neon),yes)
+  build_dependencies += $(build_neon_stamp)
+  install_dependencies += $(install_neon_stamp)
+endif
+
+ifeq ($(with_hppa64),yes)
+  build_dependencies += $(build_hppa64_stamp)
+  ifneq ($(trunk_build),yes)
+    install_dependencies += $(install_hppa64_stamp)
+  endif
+endif
+
+build_dependencies += $(check_dependencies)
+
+build_arch_dependencies = $(build_dependencies)
+build_indep_dependencies = $(build_dependencies)
+
+ifneq (,$(findstring build-native, $(build_type)))
+  ifneq ($(single_package),yes)
+    build_indep_dependencies += $(build_html_stamp)
+    ifeq ($(with_cxx),yes)
+      build_indep_dependencies += $(build_doxygen_stamp)
+    endif
+    ifeq ($(with_java),yes)
+      build_arch_dependencies += $(build_html_stamp)
+      build_indep_dependencies += $(build_javasrc_stamp)
+      build_indep_dependencies += $(build_javadoc_stamp)
+    endif
+    ifeq ($(with_ada),yes)
+      build_indep_dependencies += $(build_gnatdoc_stamp)
+    endif
+  endif
+endif
+
+stamp-dir:
+	mkdir -p $(stampdir)
+
+ifeq ($(DEB_CROSS),yes)
+  define cross_mangle_shlibs
+	if [ -f debian/$(1)/DEBIAN/shlibs ]; then \
+	  sed -i s/$(cross_lib_arch)/:$(DEB_TARGET_ARCH)/g debian/$(1)/DEBIAN/shlibs; \
+	fi
+  endef
+  define cross_mangle_substvars
+	if [ -f debian/$(1).substvars ]; then \
+	  sed -i \
+	    -e 's/:$(DEB_TARGET_ARCH)/$(cross_lib_arch)/g' \
+	    -e 's/\(libc[.0-9]*-[^:]*\):\([a-z0-9-]*\)/\1-\2-cross/g' \
+	    $(if $(filter armel,$(DEB_TARGET_ARCH)),-e 's/:armhf/-armhf-cross/g') \
+	    $(if $(filter armhf,$(DEB_TARGET_ARCH)),-e 's/:armel/-armel-cross/g') \
+	    debian/$(1).substvars; \
+	fi
+  endef
+else
+  define cross_mangle_shlibs
+  endef
+  define cross_mangle_substvars
+  endef
+  # precise's dh_shlibdeps doesn't work well for ARM multilibs
+  # and dh_shlibdeps doesn't work well for cross builds, see #698881.
+  ifneq (,$(filter $(distrelease),precise quantal raring))
+    ifneq (,$(filter $(DEB_TARGET_ARCH), armel armhf arm64))
+      ignshld = -
+    endif
+  endif
+endif
+ifeq ($(DEB_STAGE),rtlibs)
+  define cross_mangle_shlibs
+  endef
+  define cross_mangle_substvars
+  endef
+endif
+
+# takes a *list* of package names as $1, the multilib dirname as $2
+_shlibdirs = \
+	$(if $(strip $(1)), \
+	  $(shell find $(foreach p,$(1),$(CURDIR)/debian/$(p)) \
+		-name '*.so.*' -printf '%h ' | uniq)) \
+	$(with_build_sysroot)/lib/$(call mlib_to_march,$(2)) \
+	$(with_build_sysroot)/usr/lib/$(call mlib_to_march,$(2)) \
+	$(with_build_sysroot)$(subst /usr,,/$(usr_lib$(2))) \
+	$(with_build_sysroot)/$(usr_lib$(2)) \
+	$(if $(findstring mips64,$(DEB_TARGET_ARCH)), \
+	  $(with_build_sysroot)/$(usr_lib64)) \
+	$(if $(findstring mipsn32,$(DEB_TARGET_ARCH)), \
+	  $(with_build_sysroot)/$(usr_libn32)) \
+	$(if $(filter yes,$(biarchsf) $(biarchhf)), \
+	  $(with_build_sysroot)/usr/$(call mlib_to_march,$(2))/lib) \
+	$(if $(filter yes, $(with_common_libs)),, \
+	  $(CURDIR)/$(d)/$(usr_lib$(2)) \
+	  $(CURDIR)/$(d)/usr/$(call mlib_to_march,$(2))/lib)
+shlibdirs_to_search = -l$(subst $(SPACE),:,$(foreach d,$(_shlibdirs),$(d)))
--- gcc-6-6.4.0.orig/debian/rules.parameters
+++ gcc-6-6.4.0/debian/rules.parameters
@@ -0,0 +1,45 @@
+# configuration parameters taken from upstream source files
+GCC_VERSION	:= 6.4.0
+NEXT_GCC_VERSION	:= 6.4.1
+BASE_VERSION	:= 6
+SOURCE_VERSION	:= 6.4.0-13ubuntu1
+DEB_VERSION	:= 6.4.0-13ubuntu1
+DEB_EVERSION	:= 1:6.4.0-13ubuntu1
+DEB_GDC_VERSION	:= 6.4.0-13ubuntu1
+DEB_SOVERSION	:= 5
+DEB_SOEVERSION	:= 1:5
+DEB_LIBGCC_SOVERSION	:= 
+DEB_LIBGCC_VERSION	:= 1:6.4.0-13ubuntu1
+DEB_STDCXX_SOVERSION	:= 5
+DEB_GCJ_SOVERSION	:= 5
+PKG_GCJ_EXT	:= 17
+PKG_LIBGCJ_EXT	:= 17
+DEB_GOMP_SOVERSION	:= 5
+GCC_SONAME	:= 1
+CXX_SONAME	:= 6
+FORTRAN_SONAME	:= 3
+OBJC_SONAME	:= 4
+GCJ_SONAME	:= 17
+GDC_VERSION	:= 6
+GNAT_VERSION	:= 6
+GNAT_SONAME	:= 6
+FFI_SONAME	:= 7
+SSP_SONAME	:= 0
+GOMP_SONAME	:= 1
+ITM_SONAME	:= 1
+ATOMIC_SONAME	:= 1
+BTRACE_SONAME	:= 1
+ASAN_SONAME	:= 3
+LSAN_SONAME	:= 0
+TSAN_SONAME	:= 0
+UBSAN_SONAME	:= 0
+VTV_SONAME	:= 0
+CILKRTS_SONAME	:= 5
+MPX_SONAME	:= 2
+QUADMATH_SONAME	:= 0
+GO_SONAME		:= 9
+CC1_SONAME	:= 0
+GCCJIT_SONAME	:= 0
+GPHOBOS_SONAME	:= 68
+GDRUNTIME_SONAME	:= 68
+LIBC_DEP		:= libc6
--- gcc-6-6.4.0.orig/debian/rules.patch
+++ gcc-6-6.4.0/debian/rules.patch
@@ -0,0 +1,484 @@
+# -*- makefile -*-
+# rules to patch the unpacked files in the source directory
+# ---------------------------------------------------------------------------
+# various rules to unpack addons and (un)apply patches.
+# 	- patch / apply-patches
+#	- unpatch / reverse-patches
+
+.NOTPARALLEL:
+
+patchdir	?= debian/patches
+series_file	?= $(patchdir)/series
+
+# which patches should be applied?
+
+debian_patches = \
+	svn-updates \
+	libiberty-updates \
+	$(if $(with_linaro_branch),gcc-linaro) \
+	$(if $(with_linaro_branch),gcc-linaro-no-macros) \
+	pr79041$(if $(with_linaro_branch),-linaro) \
+
+#	svn-updates \
+
+ifeq ($(with_java),yes)
+#  debian_patches += \
+#	svn-class-updates
+endif
+
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+  debian_patches += \
+	$(if $(with_linaro_branch),gcc-linaro-doc) \
+	rename-info-files \
+	gcc-SOURCE_DATE_EPOCH-doc \
+	gcc-SOURCE_DATE_EPOCH-2-doc \
+	$(if $(with_linaro_branch),,vulcan-cpu-doc) \
+	gcc-fuse-ld-lld-doc \
+
+#	svn-doc-updates \
+#	$(if $(with_linaro_branch),,svn-doc-updates) \
+
+else
+endif
+debian_patches += \
+	gcc-gfdl-build
+
+#	boehm-gc-nocheck: seems to work on the buildds \
+
+debian_patches += \
+	gcc-textdomain \
+	gcc-driver-extra-langs$(if $(with_linaro_branch),-linaro)
+
+ifneq (,$(filter $(distrelease),etch lenny squeeze wheezy dapper hardy intrepid jaunty karmic lucid))
+  debian_patches += gcc-hash-style-both
+else
+  debian_patches += gcc-hash-style-gnu
+endif
+
+debian_patches += \
+	libstdc++-pic \
+	libstdc++-doclink \
+	libstdc++-man-3cxx \
+	libstdc++-test-installed \
+	libjava-stacktrace \
+	libjava-jnipath \
+	libjava-sjlj \
+	libjava-disable-plugin \
+	alpha-no-ev4-directive \
+	boehm-gc-getnprocs \
+	note-gnu-stack \
+	libgomp-omp_h-multilib \
+	gccgo-version \
+	pr47818 \
+	gcc-base-version \
+	libgo-testsuite \
+	gcc-target-include-asm \
+	libgo-revert-timeout-exp \
+	libgo-setcontext-config \
+	gcc-auto-build \
+	kfreebsd-unwind \
+	libitm-no-fortify-source \
+	sparc64-biarch-long-double-128 \
+	gcc-ia64-bootstrap-ignore \
+	gotools-configury \
+	pr66368 \
+	pr67590 \
+	ada-gnattools-ldflags \
+	libjit-ldflags \
+	gcc-SOURCE_DATE_EPOCH \
+	gcc-SOURCE_DATE_EPOCH-2 \
+	cmd-go-combine-gccgo-s-ld-and-ldShared-methods \
+	libjava-mips64el \
+	gccgo-issue16780 \
+	$(if $(with_linaro_branch),,vulcan-cpu) \
+	$(if $(with_linaro_branch),,vulcan-costs) \
+	libffi-pax \
+	libffi-race-condition \
+	libgo-add-getrandom-mips-sparc \
+	libgo-fix-getrandom-clone-sparc64 \
+	libgo-rawClone-no_split_stack \
+	libgo-rawClone-no-pt_regs \
+	libgo-elf-relocations-sparc64 \
+	libobjc-system-gc \
+	compress-debug-check \
+	pr77267 \
+	pr78774 \
+	CVE-2016-9840 \
+	CVE-2016-9841 \
+	CVE-2016-9842 \
+	CVE-2016-9843 \
+	libcc1-compiler-name \
+	mips-pr78176-add-mlxc1-sxc1 \
+	mips-loongson3a-use-fused-madd.d \
+	mips-madd4 \
+	gcc-fuse-ld-lld \
+	pr72813 \
+	pr70909 \
+	pr77857 \
+	pr80533 \
+	sanitizer-Fix-a-crash-in-SizeClassAllocator32-with-a \
+	asan-Enable-48-bit-VMA-support-on-aarch64 \
+	libffi-mipsen-r6 \
+
+#	$(if $(filter yes, $(DEB_CROSS)),,gcc-print-file-name) \
+#	libstdc++-nothumb-check \
+# TODO: update ...
+#	libjava-rpath \
+
+hardening_patches =
+ifeq ($(with_ssp)-$(with_ssp_default),yes-yes)
+  hardening_patches += gcc-default-ssp
+  hardening_patches += gcc-default-format-security
+  ifeq (,$(filter $(distrelease),dapper hardy lucid maverick natty oneiric precise quantal raring saucy trusty))
+    hardening_patches += gcc-default-ssp-strong
+  endif
+endif
+ifneq (,$(filter $(derivative),Ubuntu))
+  ifneq (,$(findstring gcc-6, $(PKGSOURCE)))
+    hardening_patches += \
+	gcc-default-fortify-source \
+	gcc-default-relro \
+	testsuite-hardening-format \
+	testsuite-hardening-printf-types \
+	testsuite-hardening-updates \
+	testsuite-glibc-warnings
+    ifeq ($(with_pie),yes)
+      hardening_patches += \
+	bind_now_when_pie
+#    else
+#      hardening_patches += \
+#	ignore-pie-specs-when-not-enabled
+    endif
+  endif
+else ifneq (,$(filter $(derivative),Debian))
+  ifneq (,$(findstring gcc-6, $(PKGSOURCE)))
+#    ifneq ($(with_pie),yes)
+#      hardening_patches += \
+#	ignore-pie-specs-when-not-enabled
+#    endif
+  endif
+endif
+
+# FIXME 4.5: Drop and adjust symbols files
+ifneq (,$(findstring 4.4, $(PKGSOURCE)))
+  debian_patches += pr39491
+endif
+
+debian_patches += ada-arm
+debian_patches += ada-kfreebsd
+debian_patches += ada-revert-pr63225
+
+ifeq (,$(DEB_STAGE))
+# there should be no harm to always apply these, except for new GCC versions
+#ifeq ($(with_ada),yes)
+  debian_patches += \
+	ada-driver-check \
+	ada-default-project-path \
+	ada-library-project-files-soname
+
+	# FIXME: needs update
+	#ada-symbolic-tracebacks \
+
+  ifeq ($(biarch64),yes)
+    debian_patches += \
+	ada-nobiarch-check
+  endif
+
+  #ifeq ($(with_libgnat),yes)
+    debian_patches += \
+	ada-link-lib \
+	ada-libgnatvsn \
+	ada-libgnatprj \
+	ada-gnattools-cross \
+	ada-acats \
+	libgnatprj-cross-hack
+    ifneq (,$(filter $(distrelease),lucid precise))
+      debian_patches += \
+	libgnatprj-link
+    endif
+  #endif
+  #ifeq ($(with_gnatsjlj),yes)
+    debian_patches += \
+	ada-sjlj
+  #endif
+
+  debian_patches += ada-link-shlib
+  debian_patches += ada-gcc-name
+#endif
+endif # DEB_STAGE
+
+
+ifeq ($(with_d),yes)
+  debian_patches += \
+	gdc-6 \
+	gdc-updates \
+	libphobos-zlib \
+	gdc-versym-cpu \
+	gdc-versym-os \
+	gdc-frontend-posix \
+	gdc-base-version \
+	gdc-profiledbuild \
+#	gdc-multiarch
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+    debian_patches += gdc-6-doc
+  else
+    debian_patches += gdc-texinfo
+  endif
+  ifeq ($(with_libphobos),yes)
+    debian_patches += gdc-libphobos-build
+  else
+    debian_patches += gdc-driver-nophobos
+  endif
+  ifeq (,$(filter $(DEB_TARGET_ARCH),amd64 i386))
+    debian_patches += disable-gdc-tests
+  endif
+else
+  debian_patches += gcc-d-lang
+endif
+
+ifeq ($(DEB_TARGET_ARCH),alpha)
+  debian_patches += alpha-ieee
+  ifneq ($(GFDL_INVARIANT_FREE),yes)
+    debian_patches += alpha-ieee-doc
+  endif
+endif
+
+ifeq (,$(filter $(derivative),Ubuntu))
+  debian_patches += pr64735-headers
+  ifeq ($(DEB_TARGET_ARCH),armel)
+    debian_patches += pr64735
+  endif
+endif
+
+ifneq (,$(findstring $(DEB_TARGET_ARCH),arm armel armhf))
+  debian_patches += libjava-armel-unwind
+endif
+
+ifeq ($(DEB_TARGET_ARCH),armhf)
+ debian_patches += gcj-arm-mode
+else ifeq ($(DEB_TARGET_ARCH),armel)
+  ifneq (,$(filter $(distrelease),lucid maverick natty oneiric precise))
+    debian_patches += gcj-arm-mode
+  endif
+endif
+
+ifneq (,$(findstring mips, $(DEB_TARGET_ARCH)))
+  debian_patches += pr65618
+endif
+
+ifeq ($(DEB_TARGET_ARCH),powerpcspe)
+  debian_patches += powerpc_remove_many
+  debian_patches += powerpc_nofprs
+endif
+
+#debian_patches += link-libs
+
+# all patches below this line are applied for gcc-snapshot builds as well
+
+ifeq ($(single_package),yes)
+  debian_patches =
+endif
+
+debian_patches += \
+	sys-auxv-header \
+	libcilkrts-targets \
+
+ifeq ($(with_ibm_branch),yes)
+  debian_patches += ibm-branch
+endif
+
+ifeq ($(with_softfloat),yes)
+  debian_patches += arm-multilib-soft-float
+else ifeq ($(multilib),yes)
+  ifneq (,$(filter $(distrelease),lucid maverick natty oneiric precise))
+    debian_patches += arm-multilib-softfp$(if $(filter yes,$(DEB_CROSS)),-cross)
+  else
+    debian_patches += arm-multilib-soft$(if $(filter yes,$(DEB_CROSS)),-cross)
+  endif
+endif
+debian_patches += arm-multilib-defaults
+
+ifeq ($(DEB_CROSS),yes)
+  debian_patches += cross-fixes
+  debian_patches += cross-install-location
+  ifeq ($(with_d),yes)
+    debian_patches += gdc-cross-install-location
+  endif
+endif
+
+ifeq ($(DEB_TARGET_ARCH_OS),hurd)
+  debian_patches += hurd-changes
+  debian_patches += \
+		src_gcc_config_i386_gnu.h \
+		src_libgo_configure.ac \
+		src_libgo_runtime_go-caller.c \
+		src_libgo_go_net_sendfile_gnu.go \
+		src_libgo_go_net_sock_gnu.go \
+		src_libgo_go_net_sockopt_gnu.go \
+		src_libgo_go_net_sockoptip_gnu.go \
+		src_libgo_go_syscall_libcall_gnu_386.go \
+		src_libgo_go_syscall_libcall_gnu.go \
+		src_libgo_go_syscall_libcall_posix-1.go \
+		src_libgo_go_syscall_socket_gnu.go \
+		src_libgo_go_syscall_wait.c \
+		src_libgo_Makefile.am \
+		src_libgo_Makefile.in \
+		src_libgo_mksysinfo.sh \
+		src_libgo_runtime_getncpu-gnu.c \
+		src_libgo_runtime_netpoll.goc \
+		src_libgo_go_os_os_test.go \
+		src_libgo_go_syscall_syscall_gnu_test.go \
+		src_libgo_testsuite_gotest \
+		add-gnu-to-libgo-headers
+endif
+
+debian_patches += gcc-ice-dump
+debian_patches += gcc-ice-apport
+debian_patches += skip-bootstrap-multilib
+debian_patches += libjava-fixed-symlinks
+debian_patches += libffi-ro-eh_frame_sect
+debian_patches += libffi-mips
+
+debian_patches += gcc-multiarch
+ifeq ($(with_multiarch_lib),yes)
+  ifneq ($(single_package),yes)
+    debian_patches += libjava-multiarch
+  endif
+endif
+debian_patches += libjava-nobiarch-check
+debian_patches += config-ml
+ifneq ($(single_package),yes)
+  ifeq ($(with_multiarch_cxxheaders),yes)
+    debian_patches += g++-multiarch-incdir
+    debian_patches += canonical-cpppath
+  endif
+endif
+ifneq (,$(filter $(build_type), build-cross cross-build-cross))
+  debian_patches += cross-no-locale-include
+  debian_patches += cross-biarch
+  ifeq ($(with_libphobos),yes)
+    debian_patches += gdc-cross-biarch
+  endif
+endif
+debian_patches += gcc-multilib-multiarch
+
+ifneq (,$(filter $(derivative),Ubuntu))
+  ifeq (,$(filter $(distrelease),dapper hardy intrepid jaunty karmic lucid maverick))
+    debian_patches += gcc-as-needed
+    ifeq (,$(filter $(distrelease),dapper hardy intrepid jaunty karmic lucid maverick precise trusty utopic vivid wily xenial yakkety))
+      debian_patches += gcc-as-needed-gold
+    endif
+  endif
+else # Debian
+    #debian_patches += gcc-as-needed
+endif
+
+debian_patches += libgomp-kfreebsd-testsuite
+debian_patches += go-testsuite
+
+# Ada patches needed for both the stable package and snapshot builds
+debian_patches += ada-749574
+debian_patches += ada-mips
+ifeq ($(DEB_TARGET_ARCH),m68k)
+  debian_patches += ada-m68k
+  ifeq ($(with_ada),yes)
+    debian_patches += m68k-revert-pr45144
+  endif
+endif
+
+# don't remove, this is regularly overwritten, see PR sanitizer/63958.
+#debian_patches += libasan-sparc
+
+debian_patches += 0001-i386-Move-struct-ix86_frame-to-machine_function
+debian_patches += 0002-i386-Use-reference-of-struct-ix86_frame-to-avoid-copy
+debian_patches += 0003-i386-Use-const-reference-of-struct-ix86_frame-to-avoi
+debian_patches += 0004-x86-Add-mindirect-branch
+debian_patches += 0005-x86-Add-mfunction-return
+debian_patches += 0006-x86-Add-mindirect-branch-register
+debian_patches += 0007-x86-Add-V-register-operand-modifier
+debian_patches += 0008-x86-Disallow-mindirect-branch-mfunction-return-with-m
+debian_patches += 0009-Use-INVALID_REGNUM-in-indirect-thunk-processing
+
+series_stamp = $(stampdir)/02-series-stamp
+series: $(series_stamp)
+$(series_stamp):
+	echo $(strip $(addsuffix .diff,$(debian_patches))) \
+	  | sed -r 's/  +/ /g' | tr " " "\n" > $(series_file)
+ifneq (,$(strip $(hardening_patches)))
+  ifneq ($(trunk_build),yes)
+	echo $(strip $(addsuffix .diff,$(hardening_patches))) \
+	  | sed -r 's/  +/ /g' | tr " " "\n" >> $(series_file)
+  endif
+endif
+	sed -r 's/(.)$$/\1 -p1/' -i $(series_file)
+	touch $@
+
+autoconf_files = $(filter-out src/libjava/classpath/m4/acinclude.m4, \
+	  $(shell lsdiff --no-filename $(foreach patch,$(debian_patches),$(patchdir)/$(patch).diff) \
+	    | sed -rn '/(configure\.ac|acinclude.m4)$$/s:[^/]+/src/:src/:p' | sort -u))
+autoconf_dirs = $(sort $(dir $(autoconf_files)))
+
+automake_files = $(addprefix ./, $(filter-out none, \
+	  $(shell lsdiff --no-filename $(foreach patch,$(debian_patches),$(patchdir)/$(patch).diff) \
+	    | sed -rn '/Makefile\.(am|in)$$/s:[^/]+/src/:src/:p' | sort -u)))
+
+autoconf_version = 2.64
+ifeq ($(trunk_build),yes)
+  # The actual version depends on the build-dependencies set by
+  # variable AUTO_BUILD_DEP in rules.conf.  Here, we assume the
+  # correct version is installed.
+  #autoconf_version =
+endif
+
+# FIXME: the auto* stuff is done every time for every subdir, which
+# leads to build errors. Idea: record the auto* calls in the patch
+# files (AUTO <dir> <auto-command with options>) and run them separately,
+# maybe only once per directory).
+$(patch_stamp): $(unpack_stamp) $(series_stamp)
+	sync
+	QUILT_PATCHES=$(patchdir) \
+	  quilt --quiltrc /dev/null push -a || test $$? = 2
+
+ifneq (,$(filter svn-updates, $(debian_patches)))
+	awk '/^EOF/ {exit} p==1 {print} /EOF$$/ {p=1}' \
+	  $(patchdir)/svn-updates.diff > src/LAST_UPDATED
+endif
+
+ifneq (,$(filter libgo-elf-relocations-sparc64, $(debian_patches)))
+	uudecode $(patchdir)/../go-relocation-test-gcc620-sparc64.obj.uue
+endif
+
+	: # only needed when we have changes, and currently fails with autogen 5.18
+	: #cd $(srcdir)/fixincludes && ./genfixes
+
+	sync
+	echo -n $(autoconf_dirs) | xargs -d ' ' -L 1 -P $(USE_CPUS) -I{} \
+	  sh -c 'echo "Running autoconf$(autoconf_version) in {}..." ; \
+	  cd $(CURDIR)/{} && \
+	  AUTOM4TE=/usr/bin/autom4te$(autoconf_version) autoconf$(autoconf_version)'
+
+	for i in $(debian_patches) $(hardening_patches); do \
+	  echo -e "\n$$i:" >> pxxx; \
+	  sed -n 's/^# *DP: */  /p' $(patchdir)/$$i.diff >> pxxx; \
+	done
+#	-$(srcdir)/move-if-change pxxx $@
+	mv pxxx $@
+
+unpatch:
+ifneq (,$(filter libgo-elf-relocations-sparc64, $(debian_patches)))
+	# uudecoded in $(patch_stamp) rule
+	rm -f $(srcdir)/libgo/go/debug/elf/testdata/go-relocation-test-gcc620-sparc64.obj
+endif
+
+	QUILT_PATCHES=$(patchdir) \
+	  quilt --quiltrc /dev/null pop -a -R || test $$? = 2
+	rm -rf .pc
+
+update-patches: $(series_stamp)
+	export QUILT_PATCHES=$(patchdir); \
+	export QUILT_REFRESH_ARGS="--no-timestamps --no-index -pab"; \
+	export QUILT_DIFF_ARGS="--no-timestamps --no-index -pab"; \
+	while quilt push; do quilt refresh; done
+
+patch: $(patch_stamp)
+.PHONY: patch series quilt autotools
--- gcc-6-6.4.0.orig/debian/rules.sonames
+++ gcc-6-6.4.0/debian/rules.sonames
@@ -0,0 +1,101 @@
+ifneq ($(vafilt_defined),1)
+  $(error rules.defs must be included before rules.sonames)
+endif
+
+ifeq (,$(wildcard debian/soname-cache))
+  SONAME_VARS := $(shell \
+	cache=debian/soname-cache; \
+	rm -f $$cache; \
+	v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libstdc++-v3/acinclude.m4`; \
+	echo CXX_SONAME=$$v >> $$cache; \
+	v=`awk -F= '/^VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libobjc/configure.ac`; \
+	echo OBJC_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libgfortran/libtool-version | cut -d: -f1`; \
+	echo FORTRAN_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libssp/libtool-version | cut -d: -f1`; \
+	echo SSP_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libjava/libtool-version | cut -d: -f1`; \
+	echo GCJ_SONAME=$$v >> $$cache; \
+	if [ "$$v" -ge 70 ]; then \
+	  echo GCJ_SONAME1=`echo $$v | sed 's/.$$//'` >> $$cache; \
+	  echo GCJ_SONAME2=`echo $$v | sed 's/.*\(.\)$$/\1/'` >> $$cache; \
+	else \
+	  echo GCJ_SONAME1=$$v >> $$cache; \
+	  echo GCJ_SONAME2= >> $$cache; \
+	fi; \
+	v=`tail -1 $(srcdir)/libffi/libtool-version | cut -d: -f1`; \
+	echo FFI_SONAME=$$v >> $$cache; \
+	v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libgomp/configure.ac`; \
+	echo GOMP_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libsanitizer/asan/libtool-version | cut -d: -f1`; \
+	echo ASAN_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libsanitizer/lsan/libtool-version | cut -d: -f1`; \
+	echo LSAN_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libsanitizer/tsan/libtool-version | cut -d: -f1`; \
+	echo TSAN_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libsanitizer/ubsan/libtool-version | cut -d: -f1`; \
+	echo UBSAN_SONAME=$$v >> $$cache; \
+	v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libatomic/configure.ac`; \
+        v=1; \
+	echo ATOMIC_SONAME=$$v >> $$cache; \
+	v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libbacktrace/configure.ac`; \
+	echo BTRACE_SONAME=$$v >> $$cache; \
+	v=`tail -1 $(srcdir)/libquadmath/libtool-version | cut -d: -f1`; \
+	  echo QUADMATH_SONAME=$$v >> $$cache; \
+	v=`grep '[^_]Library_Version.*:' $(srcdir)/gcc/ada/gnatvsn.ads \
+		| sed -e 's/.*"\([^"]*\)".*/\1/'`; \
+	echo GNAT_SONAME=$$v >> $$cache; \
+	v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libgo/configure.ac`; \
+	echo GO_SONAME=$$v >> $$cache; \
+	echo ITM_SONAME=1 >> $$cache; \
+	v=`awk -F= '/^libtool_VERSION/ {split($$2,v,":"); print v[1]}' \
+		$(srcdir)/libvtv/configure.ac`; \
+	v=0; \
+	echo VTV_SONAME=$$v >> $$cache; \
+	echo CILKRTS_SONAME=5 >> $$cache; \
+	echo CC1_SONAME=0 >> $$cache; \
+	echo GCCJIT_SONAME=0 >> $$cache; \
+	v=`tail -1 $(srcdir)/libmpx/mpxrt/libtool-version | cut -d: -f1`; \
+	echo MPX_SONAME=$$v >> $$cache; \
+	echo GPHOBOS_SONAME=68 >> $$cache; \
+	echo GDRUNTIME_SONAME=68 >> $$cache; \
+	cat $$cache)
+else
+  SONAME_VARS := $(shell cat debian/soname-cache)
+endif
+CXX_SONAME	= $(call vafilt,$(SONAME_VARS),CXX_SONAME)
+OBJC_SONAME	= $(call vafilt,$(SONAME_VARS),OBJC_SONAME)
+FORTRAN_SONAME	= $(call vafilt,$(SONAME_VARS),FORTRAN_SONAME)
+SSP_SONAME	= $(call vafilt,$(SONAME_VARS),SSP_SONAME)
+GCJ_SONAME	= $(call vafilt,$(SONAME_VARS),GCJ_SONAME)
+GCJ_SONAME1	= $(call vafilt,$(SONAME_VARS),GCJ_SONAME1)
+GCJ_SONAME2	= $(call vafilt,$(SONAME_VARS),GCJ_SONAME2)
+FFI_SONAME	= $(call vafilt,$(SONAME_VARS),FFI_SONAME)
+GOMP_SONAME	= $(call vafilt,$(SONAME_VARS),GOMP_SONAME)
+ATOMIC_SONAME	= $(call vafilt,$(SONAME_VARS),ATOMIC_SONAME)
+BTRACE_SONAME	= $(call vafilt,$(SONAME_VARS),BTRACE_SONAME)
+ASAN_SONAME	= $(call vafilt,$(SONAME_VARS),ASAN_SONAME)
+LSAN_SONAME	= $(call vafilt,$(SONAME_VARS),LSAN_SONAME)
+TSAN_SONAME	= $(call vafilt,$(SONAME_VARS),TSAN_SONAME)
+UBSAN_SONAME	= $(call vafilt,$(SONAME_VARS),UBSAN_SONAME)
+VTV_SONAME	= $(call vafilt,$(SONAME_VARS),VTV_SONAME)
+CILKRTS_SONAME	= $(call vafilt,$(SONAME_VARS),CILKRTS_SONAME)
+QUADMATH_SONAME	= $(call vafilt,$(SONAME_VARS),QUADMATH_SONAME)
+GNAT_SONAME	= $(call vafilt,$(SONAME_VARS),GNAT_SONAME)
+GO_SONAME	= $(call vafilt,$(SONAME_VARS),GO_SONAME)
+ITM_SONAME	= $(call vafilt,$(SONAME_VARS),ITM_SONAME)
+CC1_SONAME	= $(call vafilt,$(SONAME_VARS),CC1_SONAME)
+GCCJIT_SONAME	= $(call vafilt,$(SONAME_VARS),GCCJIT_SONAME)
+MPX_SONAME	= $(call vafilt,$(SONAME_VARS),MPX_SONAME)
+GPHOBOS_SONAME	= $(call vafilt,$(SONAME_VARS),GPHOBOS_SONAME)
+GDRUNTIME_SONAME= $(call vafilt,$(SONAME_VARS),GDRUNTIME_SONAME)
+
+# alias
+GFORTRAN_SONAME = $(FORTRAN_SONAME)
+STDC++_SONAME = $(CXX_SONAME)
--- gcc-6-6.4.0.orig/debian/rules.source
+++ gcc-6-6.4.0/debian/rules.source
@@ -0,0 +1,15 @@
+SOURCE_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
+patchdir = $(SOURCE_DIR)/patches
+
+include $(SOURCE_DIR)/debian/rules.defs
+include $(SOURCE_DIR)/debian/rules.patch
+include $(SOURCE_DIR)/debian/rules.unpack
+
+patch-source: $(patch_stamp)
+
+clean-source:
+	rm -rf $(stampdir)
+	rm -rf $(gcc_srcdir) $(gdc_srcdir)
+	rm -rf bin
+	rm -rf $(srcdir)
+
--- gcc-6-6.4.0.orig/debian/rules.unpack
+++ gcc-6-6.4.0/debian/rules.unpack
@@ -0,0 +1,248 @@
+# -*- makefile -*-
+# rules to unpack the source tarballs in $(srcdir); if the source dir already
+# exists, the rule exits with an error to prevent deletion of modified
+# source files. It has to be deleted manually.
+
+tarballs = $(gcc_tarball) # $(gcj_tarball)
+ifeq ($(with_d),yes)
+  tarballs += $(gdc_tarball)
+endif
+
+unpack_stamps = $(foreach i,$(tarballs),$(unpack_stamp)-$(i))
+
+unpack: stamp-dir $(unpack_stamp) debian-chmod
+$(unpack_stamp): $(unpack_stamps)
+$(unpack_stamp): $(foreach p,$(debian_tarballs),unpacked-$(p))
+	echo -e "\nBuilt from Debian source package $(PKGSOURCE)-$(SOURCE_VERSION)" \
+		> pxxx
+	echo -e "Integrated upstream packages in this version:\n" >> pxxx
+	for i in $(tarballs); do echo "  $$i" >> pxxx; done
+	mv -f pxxx $@
+
+debian-chmod:
+	@chmod 755 debian/dh_*
+
+# ---------------------------------------------------------------------------
+
+gfdl_texinfo_files = \
+	gcc/doc/avr-mmcu.texi \
+	gcc/doc/bugreport.texi \
+	gcc/doc/cfg.texi \
+	gcc/doc/collect2.texi \
+	gcc/doc/compat.texi \
+	gcc/doc/configfiles.texi \
+	gcc/doc/configterms.texi \
+	gcc/doc/contrib.texi \
+	gcc/doc/contribute.texi \
+	gcc/doc/cpp.texi \
+	gcc/doc/cppenv.texi \
+	gcc/doc/cppinternals.texi \
+	gcc/doc/cppopts.texi \
+	gcc/doc/extend.texi \
+	gcc/doc/fragments.texi \
+	gcc/doc/frontends.texi \
+	gcc/doc/gccint.texi \
+	gcc/doc/gcov.texi \
+	gcc/doc/gcov-dump.texi \
+	gcc/doc/gcov-tool.texi \
+	gcc/doc/generic.texi \
+	gcc/doc/gimple.texi \
+	gcc/doc/gnu.texi \
+	gcc/doc/gty.texi \
+	gcc/doc/headerdirs.texi \
+	gcc/doc/hostconfig.texi \
+	gcc/doc/implement-c.texi \
+	gcc/doc/implement-cxx.texi \
+	gcc/doc/install-old.texi \
+	gcc/doc/install.texi \
+	gcc/doc/interface.texi \
+	gcc/doc/invoke.texi \
+	gcc/doc/languages.texi \
+	gcc/doc/libgcc.texi \
+	gcc/doc/loop.texi \
+	gcc/doc/lto.texi \
+	gcc/doc/makefile.texi \
+	gcc/doc/match-and-simplify.texi \
+	gcc/doc/md.texi \
+	gcc/doc/objc.texi \
+	gcc/doc/optinfo.texi \
+	gcc/doc/options.texi \
+	gcc/doc/passes.texi \
+	gcc/doc/plugins.texi \
+	gcc/doc/portability.texi \
+	gcc/doc/rtl.texi \
+	gcc/doc/service.texi \
+	gcc/doc/sourcebuild.texi \
+	gcc/doc/standards.texi \
+	gcc/doc/tm.texi.in \
+	gcc/doc/tm.texi \
+	gcc/doc/tree-ssa.texi \
+	gcc/doc/trouble.texi \
+	gcc/doc/include/gcc-common.texi \
+	gcc/doc/include/funding.texi \
+	gcc/fortran/gfc-internals.texi \
+	gcc/fortran/invoke.texi \
+	gcc/fortran/intrinsic.texi \
+
+
+gfdl_toplevel_texinfo_files = \
+	gcc/doc/gcc.texi \
+	gcc/java/gcj.texi \
+	gcc/ada/gnat-style.texi \
+	gcc/ada/gnat_rm.texi \
+	gcc/ada/gnat_ugn.texi \
+	gcc/fortran/gfortran.texi \
+	gcc/go/gccgo.texi \
+	libgomp/libgomp.texi \
+	libquadmath/libquadmath.texi \
+
+gfdl_manpages = \
+	gcc/doc/cpp.1 \
+	gcc/doc/g++.1 \
+	gcc/doc/gc-analyze.1 \
+	gcc/doc/gcc.1 \
+	gcc/doc/gccgo.1 \
+	gcc/doc/gcj.1 \
+	gcc/doc/gcj-dbtool.1 \
+	gcc/doc/gcjh.1 \
+	gcc/doc/gcov.1 \
+	gcc/doc/gcov-dump.1 \
+	gcc/doc/gcov-tool.1 \
+	gcc/doc/gfortran.1 \
+	gcc/doc/gij.1 \
+	gcc/doc/grmic.1 \
+	gcc/doc/grmiregistry.1 \
+	gcc/doc/jcf-dump.1 \
+	gcc/doc/jv-convert.1 \
+	gcc/doc/fsf-funding.7 \
+
+# ---------------------------------------------------------------------------
+$(unpack_stamp)-$(gcc_tarball): $(gcc_tarpath)
+	: # unpack gcc tarball
+	mkdir -p $(stampdir)
+	if [ -d $(srcdir) ]; then \
+	  echo >&2 "Source directory $(srcdir) exists. Delete by hand"; \
+	  false; \
+	fi
+	rm -rf $(gcc_srcdir)
+	tar -x -f $(gcc_tarpath)
+	mv $(gcc_srcdir) $(srcdir)
+	ln -sf libsanitizer $(srcdir)/libasan
+ifneq (,$(wildcard java-class-files.tar.xz.uue))
+# work around #533356
+#	uudecode -o - java-class-files.tar.xz.uue | tar -C src -xvz
+	uudecode java-class-files.tar.xz.uue
+	xzcat java-class-files.tar.xz | tar -C src -xv -f -
+	rm -f java-class-files.tar.xz
+endif
+#ifeq ($(with_java),yes)
+#	tar -x -C $(srcdir)/libjava/testsuite/libmauve.exp \
+#		$(wildcard /usr/src/mauve*.tar.*)
+#endif
+ifeq (0,1)
+	cd $(srcdir) && tar cfj ../gcc-4.1.1-doc.tar.bz2 \
+		$(gfdl_texinfo_files) \
+		$(gfdl_toplevel_texinfo_files) \
+		$(gfdl_manpages)
+endif
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+  ifneq ($(single_package),yes)
+	rm -f $(srcdir)/gcc/doc/*.1
+	rm -f $(srcdir)/gcc/doc/fsf-funding.7
+	rm -f $(srcdir)/gcc/doc/*.info
+	rm -f $(srcdir)/gcc/fortran/*.info
+	rm -f $(srcdir)/libgomp/*.info
+	rm -f $(srcdir)/gcc/java/*.1
+	rm -f $(srcdir)/gcc/java/*.info
+	for i in $(gfdl_texinfo_files); do \
+	  if [ -f $(srcdir)/$$i ]; then \
+	    cp $(SOURCE_DIR)debian/dummy.texi $(srcdir)/$$i; \
+	  else \
+	    cp $(SOURCE_DIR)debian/dummy.texi $(srcdir)/$$i; \
+	    echo >&2 "$$i does not exist, fix debian/rules.unpack"; \
+	  fi; \
+	done
+	for i in $(gfdl_toplevel_texinfo_files); do \
+	  n=$$(basename $$i .texi); \
+	  if [ -f $(srcdir)/$$i ]; then \
+	    sed "s/@name@/$$n/g" $(SOURCE_DIR)debian/gcc-dummy.texi \
+	      > $(srcdir)/$$i; \
+	  else \
+	    sed "s/@name@/$$n/g" $(SOURCE_DIR)debian/gcc-dummy.texi \
+	      > $(srcdir)/$$i; \
+	    echo >&2 "$$i does not exist, fix debian/rules.unpack"; \
+	  fi; \
+	done
+	for i in $(gfdl_manpages); do \
+	  touch $(srcdir)/$$i; \
+	done
+	rm -f $(srcdir)/INSTALL/*.html
+	rm -f $(srcdir)/zlib/contrib/dotzlib/DotZLib.chm
+  endif
+endif
+	echo "$(gcc_tarball) unpacked." > $@
+
+# ---------------------------------------------------------------------------
+ifneq (,$(gcj_tarball))
+$(unpack_stamp)-$(gcj_tarball): $(gcj_tarpath) $(unpack_stamp)-$(gcc_tarball)
+	: # unpack gcj tarball
+	rm -rf $(srcdir)/gcc/java $(srcdir)/libjava
+	tar -x -C $(srcdir) -f $(gcj_tarpath)
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+  ifneq ($(single_package),yes)
+	rm -f $(srcdir)/gcc/java/*.1
+	rm -f $(srcdir)/gcc/java/*.info
+	for i in $(gfdl_texinfo_files); do \
+	  if [ -f $(srcdir)/$$i ]; then \
+	    cp $(SOURCE_DIR)debian/dummy.texi $(srcdir)/$$i; \
+	  else \
+	    echo >&2 "$$i does not exist, fix debian/rules.unpack"; \
+	  fi; \
+	done
+	for i in $(gfdl_toplevel_texinfo_files); do \
+	  n=$$(basename $$i .texi); \
+	  if [ -f $(srcdir)/$$i ]; then \
+	    sed "s/@name@/$$n/g" $(SOURCE_DIR)debian/gcc-dummy.texi \
+	      > $(srcdir)/$$i; \
+	  else \
+	    echo >&2 "$$i does not exist, fix debian/rules.unpack"; \
+	  fi; \
+	done
+  endif
+endif
+	echo "$(gcj_tarball) unpacked." > $@
+endif
+
+# ---------------------------------------------------------------------------
+ifneq (,$(gdc_tarball))
+$(unpack_stamp)-$(gdc_tarball): $(gdc_tarpath) $(unpack_stamp)-$(gcc_tarball)
+	: # unpack gdc tarball
+	mkdir -p $(stampdir)
+	if [ -d $(srcdir)/gcc/d ]; then \
+	  echo >&2 "Source directory $(srcdir)/gcc/d exists. Delete by hand";\
+	  false; \
+	fi
+	#rm -rf $(gdc_srcdir)
+	rm -rf $(srcdir)/gcc/d
+	rm -rf $(srcdir)/gcc/testsuite/gdc.test
+	rm -f $(srcdir)/gcc/testsuite/lib/gdc*.exp
+	rm -rf $(srcdir)/libphobos
+	tar -x -C $(srcdir) --strip-components=1 -f $(gdc_tarpath)
+ifeq ($(GFDL_INVARIANT_FREE),yes-now-purge-gfdl)
+  ifneq ($(single_package),yes)
+	for i in gcc/d/gdc.texi; do \
+	  n=$$(basename $$i .texi); \
+	  if [ -f $(srcdir)/$$i ]; then \
+	    sed "s/@name@/$$n/g" $(SOURCE_DIR)debian/gcc-dummy.texi \
+	      > $(srcdir)/$$i; \
+	  else \
+	    echo >&2 "$$i does not exist, fix debian/rules.unpack"; \
+	  fi; \
+	done
+	for i in gcc/d/gdc.1; do \
+	  touch $(srcdir)/$$i; \
+	done
+  endif
+endif
+	echo "$(gdc_tarball) unpacked." > $@
+endif
--- gcc-6-6.4.0.orig/debian/rules2
+++ gcc-6-6.4.0/debian/rules2
@@ -0,0 +1,2662 @@
+#! /usr/bin/make -f
+# -*- makefile -*-
+
+# Uncomment this to turn on verbose mode.
+#export DH_VERBOSE=1
+
+.SUFFIXES:
+
+include debian/rules.defs
+include debian/rules.parameters
+
+dh_compat2 := $(shell dpkg --compare-versions "$$(dpkg-query -f '$${Version}' -W debhelper)" lt 9.20150811ubuntu2 \
+			&& echo DH_COMPAT=2)
+
+# some tools
+SHELL	= /bin/bash -e		# brace expansion in rules file
+IR	= install -m 644	# Install regular file
+IP	= install -m 755	# Install program
+IS	= install -m 755	# Install script
+
+# kernel-specific ulimit hack
+ifeq ($(findstring linux,$(DEB_HOST_GNU_SYSTEM)),linux)
+  ULIMIT_M =  if [ -e /proc/meminfo ]; then \
+	    m=`awk '/^((Mem|Swap)Free|Cached)/{m+=$$2}END{print int(m*.9)}' \
+		/proc/meminfo`; \
+	  else \
+	    m=`vmstat --free --swap-free --kilobytes|awk '{m+=$$2}END{print int(m*.9)}'`; \
+	  fi; \
+	  echo "Limiting memory for test runs to $${m}kB"; \
+	  if ulimit -m $$m; then \
+	    echo "  limited to `ulimit -m`kB"; \
+	  else \
+	    echo "  failed"; \
+	  fi
+else
+  ULIMIT_M = true
+endif
+
+ifeq ($(locale_data),generate)
+  SET_LOCPATH = LOCPATH=$(CURDIR)/locales
+endif
+
+SET_PATH = PATH=$(CURDIR)/bin:/usr/$(libdir)/gcc/bin:$$PATH
+ifeq ($(trunk_build),yes)
+  ifneq (,$(findstring sparc64-linux,$(DEB_TARGET_GNU_TYPE)))
+    SET_PATH = PATH=/usr/lib/gcc-snapshot/bin:$(CURDIR)/bin:/usr/$(libdir)/gcc/bin:$$PATH
+  endif
+  ifneq (,$(findstring ppc64-linux,$(DEB_TARGET_GNU_TYPE)))
+    SET_PATH = PATH=/usr/lib/gcc-snapshot/bin:$(CURDIR)/bin:/usr/$(libdir)/gcc/bin:$$PATH
+  endif
+endif
+
+# the recipient for the test summaries. Send with: debian/rules mail-summary
+S_EMAIL = gcc@packages.debian.org gcc-testresults@gcc.gnu.org
+
+# build not yet prepared to take variables from the environment
+define unsetenv
+  unexport $(1)
+  $(1) =
+endef
+$(foreach v, CPPFLAGS CFLAGS CXXFLAGS DFLAGS FFLAGS FCFLAGS LDFLAGS OBJCFLAGS OBJCXXFLAGS GCJFLAGS, $(if $(filter environment,$(origin $(v))),$(eval $(call unsetenv, $(v)))))
+
+CC = $(notdir $(firstword $(wildcard \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-gcc-6 \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-gcc-5 \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-gcc)))
+CXX = $(notdir $(firstword $(wildcard \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-g++-6 \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-g++-5 \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-g++)))
+ifeq ($(with_ada),yes)
+  GNAT = $(notdir $(firstword $(wildcard \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-gnat-6 \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-gnat-5 \
+	/usr/bin/$(DEB_HOST_GNU_TYPE)-gnat /usr/bin/gnatgcc)))
+  ifeq ($(GNAT),gnatgcc)
+    CC := $(shell readlink /usr/bin/gnatgcc)
+  else ifneq (,$(GNAT))
+    CC = $(subst gnat,gcc,$(GNAT))
+  else ifneq (,$(filter $(distrelease), trusty))
+    CC = gcc-4.8
+  else ifneq (,$(wildcard /usr/bin/$(DEB_HOST_GNU_TYPE)-gcc))
+    CC = $(DEB_HOST_GNU_TYPE)-gcc
+  else
+    CC = gcc
+  endif
+  CXX = $(subst gcc,g++,$(CC))
+endif
+
+ifneq (,$(filter $(build_type),cross-build-native cross-build-cross))
+  SET_TARGET_TOOLS = \
+	CC_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-gcc-$(BASE_VERSION) \
+	CXX_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-g++-$(BASE_VERSION) \
+	GFORTRAN_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-gfortran-$(BASE_VERSION) \
+	GCJ_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-gcj-$(BASE_VERSION) \
+	GOC_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-gccgo-$(BASE_VERSION) \
+	GNAT_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-gnat-$(BASE_VERSION) \
+	GDC_FOR_TARGET=$(DEB_TARGET_GNU_TYPE)-gdc-$(BASE_VERSION)
+endif
+
+ifeq ($(DEB_BUILD_GNU_TYPE),$(DEB_TARGET_GNU_TYPE))
+  CC_FOR_TARGET = $(builddir)/gcc/xgcc -B$(builddir)/gcc/
+else
+  CC_FOR_TARGET = $(DEB_TARGET_GNU_TYPE)-gcc
+endif
+
+ifneq ($(derivative),Ubuntu)
+  ifneq (,$(filter $(DEB_TARGET_ARCH), arm armel mips mipsel))
+    STAGE1_CFLAGS = -g -O2
+  endif
+endif
+
+# work around PR 57689
+ifeq ($(DEB_TARGET_ARCH),ia64)
+  BOOT_CFLAGS	= -g -O1
+endif
+
+ifeq ($(with_ssp_default),yes)
+  STAGE1_CFLAGS	= -g
+  ifeq (,$(BOOT_CFLAGS))
+    BOOT_CFLAGS	= -g -O2
+  endif
+  LIBCFLAGS		= -g -O2
+  LIBCXXFLAGS	= -g -O2 -fno-implicit-templates
+  # Only use -fno-stack-protector when known to the stage1 compiler.
+  cc-fno-stack-protector := $(shell if $(CC) $(CFLAGS) -fno-stack-protector \
+                             -S -o /dev/null -xc /dev/null > /dev/null 2>&1; \
+							 then echo "-fno-stack-protector"; fi;)
+  $(foreach var,STAGE1_CFLAGS BOOT_CFLAGS LIBCFLAGS LIBCXXFLAGS,$(eval \
+    $(var) += $(cc-fno-stack-protector)))
+endif
+
+# FIXME: passing LDFLAGS for native doesn't do anything
+ifneq (,$(filter $(build_type), build-cross cross-build-cross))
+  CFLAGS	= -g -O2
+  LDFLAGS	= -Wl,-z,relro
+  ifeq ($(DEB_TARGET_ARCH),alpha)
+    LDFLAGS += -Wl,--no-relax
+  endif
+else
+  BOOT_LDFLAGS	= -Wl,-z,relro
+  ifeq ($(DEB_TARGET_ARCH),alpha)
+    BOOT_LDFLAGS += -Wl,--no-relax
+  endif
+endif
+LDFLAGS_FOR_TARGET = -Wl,-z,relro
+ifeq ($(DEB_TARGET_ARCH),alpha)
+  LDFLAGS := $(filter-out -Wl$(COMMA)--no-relax, $(LDFLAGS)) -Wl,--no-relax
+endif
+
+ifneq (,$(findstring static,$(DEB_BUILD_OPTIONS)))
+  LDFLAGS	+= -static
+endif
+
+ifneq ($(findstring gccdebug, $(DEB_BUILD_OPTIONS)),)
+  CFLAGS		= -O0 -g3 -fno-inline
+  CXXFLAGS		= -O0 -g3 -fno-inline
+  CFLAGS_FOR_BUILD	= -O0 -g3 -fno-inline
+  CXXFLAGS_FOR_BUILD	= -O0 -g3 -fno-inline
+  CFLAGS_FOR_TARGET	= -O0 -g3 -fno-inline
+  CXXFLAGS_FOR_TARGET	= -O0 -g3 -fno-inline
+  BOOT_CFLAGS		=
+  BOOT_LDFLAGS		=
+  STAGE1_CFLAGS		=
+  STAGE1_LDFLAGS	=
+endif
+
+# set CFLAGS/LDFLAGS for the configure step only, maybe be modifed for some target
+# all other flags are passed to the make step.
+CFLAGS_TO_PASS = \
+	$(if $(CFLAGS),CFLAGS="$(CFLAGS)") \
+	$(if $(CXXFLAGS),CXXFLAGS="$(CXXFLAGS)") \
+	$(if $(LIBCFLAGS),LIBCFLAGS="$(LIBCFLAGS)") \
+	$(if $(LIBCXXFLAGS),LIBCXXFLAGS="$(LIBCXXFLAGS)")
+LDFLAGS_TO_PASS = \
+	$(if $(LDFLAGS),LDFLAGS="$(LDFLAGS)")
+
+STAGE1_CFLAGS_TO_PASS = \
+	$(if $(STAGE1_CFLAGS),STAGE1_CFLAGS="$(STAGE1_CFLAGS)")
+STAGE1_LDFLAGS_TO_PASS = \
+	$(if $(STAGE1_LDFLAGS),STAGE1_LDFLAGS="$(STAGE1_LDFLAGS)")
+
+BOOT_CFLAGS_TO_PASS = \
+	$(if $(BOOT_CFLAGS),BOOT_CFLAGS="$(BOOT_CFLAGS)")
+BOOT_LDFLAGS_TO_PASS = \
+	$(if $(BOOT_LDFLAGS),BOOT_LDFLAGS="$(BOOT_LDFLAGS)")
+
+CFLAGS_FOR_BUILD_TO_PASS = \
+	$(if $(CFLAGS_FOR_BUILD),CFLAGS_FOR_BUILD="$(CFLAGS_FOR_BUILD)")
+CXXFLAGS_FOR_BUILD_TO_PASS = \
+	$(if $(CXXFLAGS_FOR_BUILD),CXXFLAGS_FOR_BUILD="$(CXXFLAGS_FOR_BUILD)")
+LDFLAGS_FOR_BUILD_TO_PASS = \
+	$(if $(LDFLAGS_FOR_BUILD),LDFLAGS_FOR_BUILD="$(LDFLAGS_FOR_BUILD)")
+
+CFLAGS_FOR_TARGET_TO_PASS = \
+	$(if $(CFLAGS_FOR_TARGET),CFLAGS_FOR_TARGET="$(CFLAGS_FOR_TARGET)")
+CXXFLAGS_FOR_TARGET_TO_PASS = \
+	$(if $(CXXFLAGS_FOR_TARGET),CXXFLAGS_FOR_TARGET="$(CXXFLAGS_FOR_TARGET)")
+LDFLAGS_FOR_TARGET_TO_PASS = \
+	$(if $(LDFLAGS_FOR_TARGET),LDFLAGS_FOR_TARGET="$(LDFLAGS_FOR_TARGET)")
+
+docdir		= usr/share/doc
+
+CONFARGS = -v \
+	--with-pkgversion='$(distribution)$(if $(with_linaro_branch),/Linaro)$(if $(with_ibm_branch),/IBM)___$(DEB_VERSION)' \
+	--with-bugurl='file:///usr/share/doc/$(subst gcj,gcc,$(PKGSOURCE))/README.Bugs'
+
+CONFARGS += \
+	--enable-languages=$(subst $(SPACE),$(COMMA),$(enabled_languages)) \
+	--prefix=/$(PF)
+
+ifeq ($(versioned_packages),yes)
+  CONFARGS += --program-suffix=-$(BASE_VERSION)
+endif
+ifeq ($(build_type),build-native)
+  CONFARGS += --program-prefix=$(cmd_prefix)
+endif
+
+ifneq (,$(filter $(DEB_STAGE),stage1 stage2))
+  CONFARGS += \
+	--disable-decimal-float \
+	--disable-libatomic \
+	--disable-libgomp \
+	--disable-libmpx \
+	--disable-libssp \
+	--disable-libquadmath \
+	--disable-libsanitizer \
+	--disable-threads \
+	--libexecdir=/$(libexecdir) \
+	--libdir=/$(PF)/$(configured_libdir) \
+	$(if $(with_build_sysroot),--with-build-sysroot=$(with_build_sysroot)) \
+	$(if $(with_sysroot),--with-sysroot=$(with_sysroot)) \
+	--enable-linker-build-id
+
+  ifeq ($(with_multiarch_lib),yes)
+    CONFARGS += \
+	--enable-multiarch
+  endif
+
+  ifeq ($(DEB_STAGE),stage1)
+    CONFARGS += \
+	--disable-shared  \
+	--with-newlib  \
+	--without-headers
+  else
+    # stage2
+    CONFARGS += \
+	--enable-shared
+  endif
+else
+  CONFARGS += \
+	--enable-shared \
+	--enable-linker-build-id \
+
+ifneq ($(single_package),yes)
+  CONFARGS += \
+        --libexecdir=/$(libexecdir) \
+        --without-included-gettext \
+        --enable-threads=posix \
+	--libdir=/$(PF)/$(configured_libdir)
+endif
+
+ifneq ($(with_cpp),yes)
+  CONFARGS += --disable-cpp
+endif
+
+ifeq ($(with_nls),yes)
+  CONFARGS += --enable-nls
+else
+  CONFARGS += --disable-nls
+endif
+
+ifeq ($(with_bootstrap),off)
+  CONFARGS += --disable-bootstrap
+else ifneq ($(with_bootstrap),)
+  CONFARGS += --enable-bootstrap=$(with_bootstrap)
+endif
+
+ifneq ($(with_sysroot),)
+  CONFARGS += --with-sysroot=$(with_sysroot)
+endif
+ifneq ($(with_build_sysroot),)
+  CONFARGS += --with-build-sysroot=$(with_build_sysroot)
+endif
+
+ifeq ($(force_gnu_locales),yes)
+  CONFARGS += --enable-clocale=gnu
+endif
+
+ifeq ($(with_cxx)-$(with_cxx_debug),yes-yes)
+  CONFARGS += --enable-libstdcxx-debug
+endif
+CONFARGS += --enable-libstdcxx-time=yes
+CONFARGS += --with-default-libstdcxx-abi=$(libstdcxx_abi)
+ifeq ($(libstdcxx_abi),gcc4-compatible)
+  CONFARGS += --disable-libstdcxx-dual-abi
+endif
+
+ifeq (,$(filter $(DEB_TARGET_ARCH), hurd-i386 kfreebsd-i386 kfreebsd-amd64))
+  CONFARGS += --enable-gnu-unique-object
+endif
+
+ifneq ($(with_ssp),yes)
+  CONFARGS += --disable-libssp
+endif
+
+ifneq ($(with_gomp),yes)
+  CONFARGS += --disable-libgomp
+endif
+
+ifneq ($(with_itm),yes)
+  CONFARGS += --disable-libitm
+endif
+
+ifneq ($(with_atomic),yes)
+  CONFARGS += --disable-libatomic
+endif
+
+ifneq (,$(filter $(DEB_TARGET_ARCH),$(vtv_archs)))
+  ifeq ($(with_vtv),yes)
+    CONFARGS += --enable-vtable-verify
+  else
+    CONFARGS += --disable-vtable-verify
+  endif
+endif
+
+ifneq ($(with_asan),yes)
+  CONFARGS += --disable-libsanitizer
+endif
+
+ifneq ($(with_qmath),yes)
+  CONFARGS += --disable-libquadmath
+endif
+
+ifeq ($(with_mpx),yes)
+  CONFARGS += --enable-libmpx
+endif
+
+ifeq ($(with_plugins),yes)
+  CONFARGS += --enable-plugin
+endif
+
+#ifeq ($(with_gold),yes)
+#  CONFARGS += --enable-gold --enable-ld=default
+#endif
+
+#CONFARGS += --with-plugin-ld=ld.gold
+#CONFARGS += --with-plugin-ld
+
+# enable pie-by-default on pie_archs
+ifeq ($(with_pie),yes)
+  CONFARGS += --enable-default-pie
+endif
+
+endif # !DEB_STAGE
+
+CONFARGS += --with-system-zlib
+
+jvm_name_short = java-1.5.0-gcj-$(BASE_VERSION)$(if $(findstring snap,$(PKGSOURCE)),-snap)
+jvm_name_long = $(jvm_name_short)-1.5.0.0
+
+ifeq ($(with_java),yes)
+  CONFARGS += --disable-browser-plugin
+  ifeq ($(with_java_maintainer_mode),yes)
+    CONFARGS += --enable-java-maintainer-mode
+  endif
+  ifeq ($(with_java_biarch_awt),yes)
+    CONFARGS += --enable-java-awt=$(subst $(SPACE),$(COMMA),$(foreach p,$(java_awt_peers),$(p)-default))
+  else
+    CONFARGS += --enable-java-awt=$(subst $(SPACE),$(COMMA),$(foreach p,$(java_awt_peers),$(p)))
+  endif
+  ifneq (,$(findstring gtk,$(java_awt_peers)))
+    CONFARGS += --enable-gtk-cairo
+  endif
+  jvm_ext = -$(DEB_TARGET_ARCH)$(if $(filter yes,$(DEB_CROSS)),-cross)
+  jvm_dir = /usr/lib/jvm/$(jvm_name_short)$(jvm_ext)
+  CONFARGS += --with-java-home=$(jvm_dir)/jre
+  CONFARGS += --enable-java-home \
+	--with-jvm-root-dir=$(jvm_dir) \
+	--with-jvm-jar-dir=/usr/lib/jvm-exports/$(jvm_name_short)$(jvm_ext)
+  CONFARGS += --with-arch-directory=$(java_cpu)
+  ifeq (./,$(dir $(ecj_jar)))
+    CONFARGS += --with-ecj-jar=$(jvm_dir)/lib/ecj.jar
+  else
+    CONFARGS += --with-ecj-jar=$(ecj_jar)
+  endif
+  ifneq ($(with_libgcj),yes)
+    CONFARGS += --disable-libgcj
+  endif
+endif
+
+ifeq ($(with_gcj),yes)
+  ifeq ($(DEB_HOST_GNU_CPU),m32r)
+    CONFARGS += --enable-libgcj
+  endif
+endif
+
+ifeq ($(with_libphobos),yes)
+  CONFARGS += --with-target-system-zlib
+endif
+
+ifeq ($(with_objc)-$(with_objc_gc),yes-yes)
+  CONFARGS += --enable-objc-gc=auto
+endif
+
+ifneq (,$(filter $(DEB_TARGET_GNU_TYPE), i486-linux-gnu i586-linux-gnu i686-linux-gnu))
+    ifeq ($(multilib),yes)
+      ifeq ($(biarch64),yes)
+        CONFARGS += --enable-targets=all
+      endif
+    endif
+endif
+
+ifneq (,$(filter $(DEB_TARGET_GNU_TYPE), x86_64-linux-gnu x86_64-linux-gnux32 x86_64-kfreebsd-gnu s390x-linux-gnu sparc64-linux-gnu))
+    ifneq ($(biarch32),yes)
+      CONFARGS += --disable-multilib
+    endif
+endif
+
+ifneq (,$(filter $(DEB_TARGET_GNU_TYPE), powerpc-linux-gnu powerpc-linux-gnuspe))
+    CONFARGS += --enable-secureplt
+    ifeq ($(biarch64),yes)
+      CONFARGS += --disable-softfloat --with-cpu=default32
+      ifeq ($(multilib),yes)
+        CONFARGS += --disable-softfloat \
+	  --enable-targets=powerpc-linux,powerpc64-linux
+      endif
+    else
+      CONFARGS += --disable-multilib
+    endif
+endif
+
+ifneq (,$(findstring powerpc64le-linux,$(DEB_TARGET_GNU_TYPE)))
+    CONFARGS += --enable-secureplt
+    ifneq (,$(filter $(distrelease),jessie trusty utopic vivid wily))
+      CONFARGS += --with-cpu=power7 --with-tune=power8
+    else
+      CONFARGS += --with-cpu=power8
+    endif
+    CONFARGS += --enable-targets=powerpcle-linux
+    CONFARGS += --disable-multilib
+endif
+
+ifneq (,$(findstring powerpc64-linux,$(DEB_TARGET_GNU_TYPE)))
+    CONFARGS += --enable-secureplt
+    ifeq ($(biarch32),yes)
+      ifeq ($(multilib),yes)
+        CONFARGS += --disable-softfloat --enable-targets=powerpc64-linux,powerpc-linux
+      endif
+    else
+      CONFARGS += --disable-multilib
+    endif
+    ifeq ($(derivative),Ubuntu)
+      CONFARGS += --with-cpu-32=power7 --with-cpu-64=power7
+    endif
+endif
+
+# FIXME: only needed for isl-0.13 for now
+#CONFARGS += --disable-isl-version-check
+
+ifneq (,$(findstring cross-build-,$(build_type)))
+  # FIXME: requires isl headers for the target
+  #CONFARGS += --without-isl
+  # FIXME: build currently fails build the precompiled headers
+  CONFARGS += --disable-libstdcxx-pch
+endif
+
+ifeq ($(with_multiarch_lib),yes)
+  CONFARGS += --enable-multiarch
+endif
+
+ifneq (,$(findstring aarch64,$(DEB_TARGET_GNU_CPU)))
+  # requires binutils 2.25.90 or newer
+  ifeq (,$(filter $(distrelease),squeeze precise trusty utopic vivid wily))
+    CONFARGS += --enable-fix-cortex-a53-843419
+  endif
+endif
+
+ifeq ($(findstring powerpcspe,$(DEB_TARGET_ARCH)),powerpcspe)
+  CONFARGS += --with-cpu=8548 --enable-e500_double
+endif
+
+ifneq (,$(findstring softfloat,$(DEB_TARGET_GNU_CPU)))
+  CONFARGS += --with-float=soft
+endif
+
+ifneq (,$(findstring arm-vfp,$(DEB_TARGET_GNU_CPU)))
+  CONFARGS += --with-fpu=vfp
+endif
+
+ifneq (,$(findstring arm, $(DEB_TARGET_GNU_CPU)))
+  ifeq ($(multilib),yes)
+    CONFARGS += --enable-multilib
+  endif
+  CONFARGS += --disable-sjlj-exceptions
+  # FIXME: libjava is not ported for thumb, this hack only works for
+  # separate gcj builds
+  ifneq (,$(filter %armhf,$(DEB_TARGET_ARCH)))
+    ifeq ($(distribution),Raspbian)
+      with_arm_arch = armv6
+      with_arm_fpu = vfp
+    else
+      ifneq (,$(findstring gcj,$(PKGSOURCE)))
+        with_arm_arch = armv6
+      else
+        with_arm_arch = armv7-a
+      endif
+      with_arm_fpu = vfpv3-d16
+    endif
+  else
+    # armel
+    ifeq ($(derivative),Debian)
+      with_arm_arch = armv4t
+    else ifneq (,$(filter $(distrelease),karmic))
+      with_arm_arch = armv6
+      with_arm_fpu = vfpv3-d16
+    else ifneq (,$(filter $(distrelease),lucid maverick natty oneiric precise))
+      ifneq (,$(findstring gcj,$(PKGSOURCE)))
+        with_arm_arch = armv6
+      else
+        with_arm_arch = armv7-a
+      endif
+      with_arm_fpu = vfpv3-d16
+    else
+      with_arm_arch = armv5t  # starting with quantal
+    endif
+  endif
+  CONFARGS += --with-arch=$(with_arm_arch)
+  ifneq (,$(with_arm_fpu))
+    CONFARGS += --with-fpu=$(with_arm_fpu)
+  endif
+  CONFARGS += --with-float=$(float_abi)
+  ifeq ($(with_arm_thumb),yes)
+    CONFARGS += --with-mode=thumb
+  endif
+endif
+
+ifeq ($(DEB_TARGET_GNU_CPU),$(findstring $(DEB_TARGET_GNU_CPU),m68k))
+  CONFARGS += --disable-werror
+endif
+# FIXME: correct fix-warnings.dpatch
+ifeq ($(derivative),Ubuntu)
+  CONFARGS += --disable-werror
+endif
+
+ifneq (,$(findstring sparc-linux,$(DEB_TARGET_GNU_TYPE)))
+  ifeq ($(biarch64),yes)
+    CONFARGS += --enable-targets=all
+    CONFARGS += --with-cpu-32=ultrasparc
+  else
+    CONFARGS += --with-cpu=ultrasparc
+  endif
+endif
+
+ifneq (,$(findstring sparc64-linux,$(DEB_TARGET_GNU_TYPE)))
+  ifeq ($(biarch32),yes)
+    CONFARGS += --enable-targets=all
+    CONFARGS += --with-cpu-32=ultrasparc
+  endif
+endif
+
+ifneq (,$(findstring ia64-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-system-libunwind
+endif
+
+ifneq (,$(findstring sh4-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-cpu=sh4 --with-multilib-list=m4,m4-nofpu
+endif
+
+ifneq (,$(findstring m68k-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --disable-multilib
+endif
+
+ifneq (,$(filter tilegx,$(DEB_TARGET_GNU_CPU)))
+  CONFARGS += --disable-multilib
+endif
+
+ifneq (,$(findstring s390x-linux,$(DEB_TARGET_GNU_TYPE)))
+  ifeq ($(derivative),Ubuntu)
+    CONFARGS += --with-arch=zEC12
+  else # Debian
+    CONFARGS += --with-arch=z196
+  endif
+endif
+
+ifeq ($(DEB_TARGET_ARCH_OS),linux)
+  ifneq (,$(findstring $(DEB_TARGET_ARCH), alpha powerpc powerpcspe ppc64 ppc64el s390 s390x sparc sparc64))
+    CONFARGS += --with-long-double-128
+  endif
+endif
+
+ifneq (,$(filter $(DEB_TARGET_ARCH), amd64 i386 kfreebsd-i386 kfreebsd-amd64))
+  ifneq (,$(filter $(derivative),Ubuntu))
+    ifneq (,$(filter $(distrelease),dapper hardy))
+      CONFARGS += --with-arch-32=i486
+    else ifneq (,$(filter $(distrelease),jaunty karmic lucid))
+      CONFARGS += --with-arch-32=i586
+    else
+      CONFARGS += --with-arch-32=i686
+    endif
+  else # Debian
+    ifneq (,$(filter $(distrelease),etch lenny))
+      CONFARGS += --with-arch-32=i486
+    else ifneq (,$(filter $(distrelease),squeeze wheezy jessie))
+      CONFARGS += --with-arch-32=i586
+    else
+      CONFARGS += --with-arch-32=i686
+    endif
+  endif
+endif
+
+ifeq ($(DEB_TARGET_ARCH),amd64)
+  CONFARGS += --with-abi=m64
+endif
+ifeq ($(DEB_TARGET_ARCH),x32)
+  CONFARGS += --with-abi=mx32
+endif
+ifeq ($(multilib),yes)
+  ifneq (,$(filter $(DEB_TARGET_ARCH), amd64 i386))
+    CONFARGS += --with-multilib-list=m32,m64$(if $(filter yes,$(biarchx32)),$(COMMA)mx32)
+  else ifeq ($(DEB_TARGET_ARCH),x32)
+    CONFARGS += --with-multilib-list=mx32,m64,m32
+  endif
+  CONFARGS += --enable-multilib
+endif
+
+ifneq (,$(filter $(DEB_TARGET_ARCH), hurd-i386))
+  CONFARGS += --with-arch=i586
+endif
+
+ifeq ($(DEB_TARGET_ARCH),lpia)
+  CONFARGS += --with-arch=pentium-m --with-tune=i586
+endif
+
+ifneq (,$(filter $(DEB_TARGET_ARCH), amd64 i386 hurd-i386 kfreebsd-i386 kfreebsd-amd64))
+  CONFARGS += --with-tune=generic
+endif
+
+ifneq (,$(findstring mips-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-arch-32=mips32r2 --with-fp-32=xx
+  CONFARGS += --with-lxc1-sxc1=no
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch64),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-64=mips64r2
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mipsel-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-arch-32=mips32r2 --with-fp-32=xx
+  CONFARGS += --with-madd4=no
+  CONFARGS += --with-lxc1-sxc1=no
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch64),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-64=mips64r2
+    endif
+  endif
+endif
+
+#FIXME: howto for mipsn32?
+ifneq (,$(findstring mips64el-linux-gnuabin32,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-madd4=no
+  ifeq ($(multilib),yes)
+    ifeq ($(biarch64)-$(biarch32),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-64=mips64r2
+      CONFARGS += --with-arch-32=mips32r2 --with-fp-32=xx
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mips64-linux-gnuabin32,$(DEB_TARGET_GNU_TYPE)))
+  ifeq ($(multilib),yes)
+    ifeq ($(biarch64)-$(biarch32),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-64=mips64r2
+      CONFARGS += --with-arch-32=mips32r2 --with-fp-32=xx
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mips64el-linux-gnuabi64,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-mips-plt
+  CONFARGS += --with-arch-64=mips64r2
+  CONFARGS += --with-madd4=no
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch32),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-32=mips32r2 --with-fp-32=xx
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mips64-linux-gnuabi64,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-mips-plt
+  CONFARGS += --with-arch-64=mips64r2
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch32),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-32=mips32r2 --with-fp-32=xx
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mipsisa32r6-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-arch-32=mips32r6 --with-tune-32=mips32r6
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch64),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-64=mips64r6 --with-tune-64=mips64r6
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mipsisa32r6el-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-arch-32=mips32r6 --with-tune-32=mips32r6
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch64),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-64=mips64r6 --with-tune-64=mips64r6
+    endif
+  endif
+endif
+
+#FIXME: howto for mipsn32?
+ifneq (,$(findstring mipsisa64r6el-linux-gnuabin32,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-mips-plt
+  ifeq ($(multilib),yes)
+    ifeq ($(biarch64)-$(biarch32),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-64=mips64r6 --with-tune-64=mips64r6
+      CONFARGS += --with-arch-32=mips32r6 --with-tune-32=mips32r6
+    endif
+  endif
+endif
+ 
+ifneq (,$(findstring mipsisa64r6-linux-gnuabin32,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-mips-plt
+  ifeq ($(multilib),yes)
+    ifeq ($(biarch64)-$(biarch32),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-64=mips64r6 --with-tune-64=mips64r6
+      CONFARGS += --with-arch-32=mips32r6 --with-tune-32=mips32r6
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mipsisa64r6el-linux-gnuabi64,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-mips-plt
+  CONFARGS += --with-arch-64=mips64r6 --with-tune-64=mips64r6
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch32),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-32=mips32r6 --with-tune-32=mips32r6
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mipsisa64r6-linux-gnuabi64,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --with-mips-plt
+  CONFARGS += --with-arch-64=mips64r6 --with-tune-64=mips64r6
+  ifeq ($(multilib),yes)
+    ifeq ($(biarchn32)-$(biarch32),yes-yes)
+      CONFARGS += --enable-targets=all
+      CONFARGS += --with-arch-32=mips32r6 --with-tune-32=mips32r6
+    endif
+  endif
+endif
+
+ifneq (,$(findstring mips,$(DEB_TARGET_GNU_TYPE)))
+  ifeq (,$(filter yes,$(biarch32) $(biarchn32) $(biarch64)))
+      CONFARGS += --disable-multilib
+  endif
+endif
+
+ifneq (,$(findstring s390-linux,$(DEB_TARGET_GNU_TYPE)))
+  ifeq ($(multilib),yes)
+    ifeq ($(biarch64),yes)
+      CONFARGS += --enable-targets=all
+    endif
+  endif
+endif
+
+ifneq (,$(findstring hppa-linux,$(DEB_TARGET_GNU_TYPE)))
+  CONFARGS += --disable-libstdcxx-pch
+endif
+
+ifneq (,$(findstring gdc, $(PKGSOURCE)))
+    CONFARGS += --disable-libquadmath
+endif
+
+ifeq ($(trunk_build),yes)
+  ifeq ($(findstring --disable-werror, $(CONFARGS)),)
+    CONFARGS += --disable-werror
+  endif
+  CONFARGS += --enable-checking=yes
+else
+  CONFARGS += --enable-checking=release
+endif
+
+CONFARGS += \
+	--build=$(DEB_BUILD_GNU_TYPE) \
+	--host=$(DEB_HOST_GNU_TYPE) \
+	--target=$(TARGET_ALIAS)
+
+ifeq ($(DEB_CROSS),yes)
+  CONFARGS += \
+	--program-prefix=$(TARGET_ALIAS)- \
+	--includedir=/$(PFL)/include
+endif
+
+ifeq ($(with_bootstrap),off)
+  bootstrap_target =
+else ifeq ($(with_bootstrap),)
+  bootstrap_target = bootstrap
+  # no profiledbootstrap on the following architectures
+  # - m68k: we're happy that it builds at all
+  no_profiled_bs_archs := alpha arm hppa m68k mips mipsel mips64 mips64el \
+	powerpcspe s390 sh4 sparc sparc64
+  ifeq (,$(filter $(DEB_TARGET_ARCH),$(no_profiled_bs_archs)))
+    bootstrap_target = profiledbootstrap
+  endif
+  ifneq (, $(filter $(PKGSOURCE),gcc-$(BASE_VERSION) gcj-$(BASE_VERSION) gnat-$(BASE_VERSION) gcc-snapshot))
+    bootstrap_target = bootstrap
+  endif
+  ifneq (,$(DEB_STAGE))
+    bootstrap_target = bootstrap
+  endif
+
+  ifeq ($(derivative),Debian)
+    # disable profiled bootstrap for backports
+    ifneq (,$(filter $(distrelease),squeeze wheezy jessie))
+      bootstrap_target = bootstrap
+    endif
+    # disable profiled bootstrap on slow archs, get to testing first ...
+    ifneq (,$(filter $(DEB_TARGET_ARCH), arm arm64 armel armhf mips mipsel sparc))
+      bootstrap_target = bootstrap
+    endif
+  endif
+  ifeq ($(derivative),Ubuntu)
+    ifneq (,$(filter $(distrelease),lucid precise trusty utopic vivid wily))
+      bootstrap_target = bootstrap
+    endif
+    ifeq ($(with_linaro_branch),yes)
+      bootstrap_target = bootstrap
+    endif
+  endif
+endif
+
+DEJAGNU_TIMEOUT=300
+# Increase the timeout for one testrun on slow architectures
+ifeq ($(derivative),Debian)
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),arm64))
+    DEJAGNU_TIMEOUT=240
+  else ifneq (,$(findstring $(DEB_TARGET_ARCH),arm armel armhf hppa m68k sparc))
+    DEJAGNU_TIMEOUT=600
+  else ifneq (,$(findstring $(DEB_TARGET_GNU_CPU),amd64 i386 i486 i686 lpia))
+    DEJAGNU_TIMEOUT=180
+  endif
+  ifeq ($(DEB_TARGET_GNU_SYSTEM),gnu)
+    DEJAGNU_TIMEOUT=900
+  endif
+else ifeq ($(derivative),Ubuntu)
+  ifneq (,$(findstring $(DEB_TARGET_ARCH),arm64))
+    DEJAGNU_TIMEOUT=240
+  else ifneq (,$(findstring $(DEB_TARGET_ARCH),armel armhf hppa ia64 sparc))
+    DEJAGNU_TIMEOUT=600
+  else ifneq (,$(findstring $(DEB_TARGET_GNU_CPU),amd64 i386 i486 i686 lpia))
+    DEJAGNU_TIMEOUT=180
+  endif
+endif
+
+DEJAGNU_RUNS =
+ifneq ($(trunk_build),yes)
+ifeq ($(with_ssp),yes)
+  # the buildds are just slow ... don't check the non-default
+  ifneq (,$(findstring $(DEB_TARGET_GNU_CPU),sh4 mips))
+    DEJAGNU_RUNS =
+  else ifneq (,$(filter $(DEB_TARGET_ARCH),armel))
+    DEJAGNU_RUNS =
+  else
+    ifneq ($(single_package),yes)
+      DEJAGNU_RUNS += $(if $(filter yes,$(with_ssp_default)),-fno-stack-protector,-fstack-protector)
+    endif
+  endif
+  ifeq ($(derivative),Ubuntu)
+    # the buildds are just slow ... don't check the non-default
+    ifneq (,$(findstring $(DEB_TARGET_GNU_CPU),ia64 sparc))
+      DEJAGNU_RUNS =
+    endif
+    # FIXME Ubuntu armel buildd hangs
+    ifneq (,$(findstring arm, $(DEB_TARGET_GNU_CPU)))
+      DEJAGNU_RUNS =
+    endif
+  endif
+endif
+endif
+
+ifeq ($(derivative),Ubuntu)
+  ifneq (,$(findstring arm, $(DEB_TARGET_GNU_CPU)))
+    ifeq ($(with_arm_thumb),yes)
+      #DEJAGNU_RUNS += -marm
+    else
+      DEJAGNU_RUNS += -mthumb
+    endif
+  endif
+endif
+
+# no b-d on g++-multilib, this is run by the built compiler
+abi_run_check = $(strip $(if $(wildcard build/runcheck$(1).out), \
+				$(shell cat build/runcheck$(1).out), \
+				$(shell CC="$(builddir)/gcc/xg++ -B$(builddir)/gcc/ -static-libgcc $(1)" bash debian/runcheck.sh)))
+ifeq ($(biarch32),yes)
+  DEJAGNU_RUNS += $(call abi_run_check,$(if $(filter $(DEB_TARGET_ARCH_CPU),mips64 mips64el mipsn32 mipsn32el),-mabi=32,-m32))
+endif
+ifeq ($(biarch64),yes)
+  DEJAGNU_RUNS += $(call abi_run_check,$(if $(filter $(DEB_TARGET_ARCH_CPU),mips mipsel),-mabi=64,-m64))
+endif
+ifeq ($(biarchn32),yes)
+  DEJAGNU_RUNS += $(call abi_run_check,-mabi=n32)
+endif
+ifeq ($(biarchx32),yes)
+  DEJAGNU_RUNS += $(call abi_run_check,-mx32)
+endif
+
+# gdc is not multilib'd
+ifneq (,$(findstring gdc, $(PKGSOURCE)))
+  DEJAGNU_RUNS =
+endif
+
+ifneq (,$(findstring gcj, $(PKGSOURCE)))
+  DEJAGNU_RUNS =
+endif
+
+# neither is gnat
+ifneq (,$(findstring gnat, $(PKGSOURCE)))
+  DEJAGNU_RUNS =
+endif
+
+ifneq (,$(strip $(value DEJAGNU_RUNS)))
+  RUNTESTFLAGS = RUNTESTFLAGS="--target_board=unix\{,$(subst $(SPACE),$(COMMA),$(strip $(DEJAGNU_RUNS)))\}"
+endif
+
+# PF is the installation prefix for the package without the leading slash.
+# It's "usr" for gcc releases.
+ifneq (,$(PF))
+  # use value set in the environment
+else ifeq ($(trunk_build),yes)
+  PF		= usr/lib/gcc-snapshot
+else ifeq ($(PKGSOURCE),gcc-linaro)
+  PF		= usr/lib/gcc-linaro
+else
+  PF		= usr
+endif
+
+# PFL is the installation prefix with DEB_TARGET_GNU_TYPE attached for cross builds
+ifeq ($(DEB_CROSS),yes)
+  PFL		= $(PF)/$(DEB_TARGET_GNU_TYPE)
+else
+  PFL		= $(PF)
+endif
+
+# RPF is the base prefix or installation prefix with DEB_TARGET_GNU_TYPE attached for cross builds
+ifeq ($(DEB_CROSS),yes)
+  RPF		= $(PF)/$(DEB_TARGET_GNU_TYPE)
+else
+  RPF		=
+endif
+
+ifeq ($(with_multiarch_lib),yes)
+  ifeq ($(DEB_CROSS),yes)
+    libdir	= lib
+  else
+    libdir	= lib/$(DEB_TARGET_MULTIARCH)
+  endif
+else
+  libdir	= lib
+endif
+configured_libdir = lib
+
+hppa64libexecdir= $(PF)/lib
+
+# /usr/libexec doesn't follow the FHS
+ifeq ($(single_package),yes)
+  libdir	= lib
+  libexecdir	= $(PF)/libexec
+  versiondir	= $(GCC_VERSION)
+else
+  libexecdir	= $(PF)/$(configured_libdir)
+  versiondir	= $(BASE_VERSION)
+endif
+buildlibdir	= $(builddir)/$(TARGET_ALIAS)
+
+# install cross compilers in /usr/lib/gcc-cross, native ones in /usr/lib/gcc
+gcc_subdir_name = gcc
+ifneq ($(single_package),yes)
+  ifeq ($(DEB_CROSS),yes)
+    gcc_subdir_name = gcc-cross
+  endif
+endif
+
+gcc_lib_dir	= $(PF)/$(configured_libdir)/$(gcc_subdir_name)/$(TARGET_ALIAS)/$(versiondir)
+gcc_lexec_dir	= $(libexecdir)/$(gcc_subdir_name)/$(TARGET_ALIAS)/$(versiondir)
+
+lib32loc   = lib32
+ifneq (,$(findstring mips,$(DEB_TARGET_GNU_TYPE)))
+lib32loc   = libo32
+endif
+lib32      = $(PF)/$(lib32loc)
+lib64		= lib64
+libn32		= lib32
+libx32		= libx32
+
+p_l= $(1)$(cross_lib_arch)
+p_d= $(1)-dbg$(cross_lib_arch)
+d_l= debian/$(p_l)
+d_d= debian/$(p_d)
+
+ifeq ($(DEB_CROSS),yes)
+  usr_lib = $(PFL)/lib
+else
+  usr_lib = $(PFL)/$(libdir)
+endif
+usr_lib32 = $(PFL)/$(lib32loc)
+usr_libn32 = $(PFL)/lib32
+usr_libx32 = $(PFL)/libx32
+usr_lib64 = $(PFL)/lib64
+# FIXME: Move to the new location for native builds too
+ifeq ($(DEB_CROSS),yes)
+  usr_libhf = $(PFL)/libhf
+  usr_libsf = $(PFL)/libsf
+else
+  usr_libhf = $(PFL)/lib/arm-linux-gnueabihf
+  usr_libsf = $(PFL)/lib/arm-linux-gnueabi
+endif
+
+ifeq ($(DEB_STAGE)-$(DEB_CROSS),rtlibs-yes)
+  PFL		= $(PF)
+  RPF		=
+  libdir	= lib/$(DEB_TARGET_MULTIARCH)
+  usr_lib	= $(PF)/lib/$(DEB_TARGET_MULTIARCH)
+endif
+
+gcc_lib_dir32 = $(gcc_lib_dir)/$(biarch32subdir)
+gcc_lib_dirn32 = $(gcc_lib_dir)/$(biarchn32subdir)
+gcc_lib_dirx32 = $(gcc_lib_dir)/$(biarchx32subdir)
+gcc_lib_dir64 = $(gcc_lib_dir)/$(biarch64subdir)
+gcc_lib_dirhf = $(gcc_lib_dir)/$(biarchhfsubdir)
+gcc_lib_dirsf = $(gcc_lib_dir)/$(biarchsfsubdir)
+
+libgcc_dir = $(RPF)/$(libdir)
+# yes, really; lib32gcc_s ends up in usr
+libgcc_dir32 = $(PFL)/$(lib32loc)
+libgcc_dirn32 = $(RPF)/lib32
+# libx32gcc_s also ends up in usr
+libgcc_dirx32 = $(PFL)/libx32
+libgcc_dir64 = $(RPF)/lib64
+# FIXME: Move to the new location for native builds too
+ifeq ($(DEB_CROSS),yes)
+  libgcc_dirhf = $(RPF)/libhf
+  libgcc_dirsf = $(RPF)/libsf
+else
+  libgcc_dirhf = $(RPF)/lib/arm-linux-gnueabihf
+  libgcc_dirsf = $(RPF)/lib/arm-linux-gnueabi
+endif
+
+# install_gcc_lib(lib,soname,flavour,package)
+define install_gcc_lib
+	mv $(d)/$(usr_lib$(3))/$(1)*.a debian/$(4)/$(gcc_lib_dir$(3))/
+	rm -f $(d)/$(usr_lib$(3))/$(1)*.{la,so}
+	dh_link -p$(4) \
+	  /$(usr_lib$(3))/$(1).so.$(2) /$(gcc_lib_dir$(3))/$(1).so
+
+endef
+
+checkdirs = $(builddir)
+ifeq ($(with_separate_libgcj),yes)
+  ifeq ($(PKGSOURCE),gcj-$(BASE_VERSION))
+    ifneq ($(with_standalone_gcj),yes)
+      checkdirs = $(buildlibdir)/libffi $(buildlibdir)/libjava
+    endif
+  endif
+endif
+ifeq ($(with_separate_go),yes)
+  ifeq ($(PKGSOURCE),gccgo-$(BASE_VERSION))
+    checkdirs = $(buildlibdir)/libgo
+  endif
+endif
+ifeq ($(with_separate_gnat),yes)
+  ifeq ($(PKGSOURCE),gnat-$(BASE_VERSION))
+    checkdirs = $(builddir)/gcc
+  endif
+endif
+
+# FIXME: MULTIARCH_DIRNAME needed for g++-multiarch-incdir.diff
+MULTIARCH_DIRNAME := $(DEB_TARGET_MULTIARCH)
+export MULTIARCH_DIRNAME
+
+default: build
+
+configure: $(configure_dependencies)
+
+$(configure_dummy_stamp):
+	touch $(configure_dummy_stamp)
+
+$(configure_stamp):
+	dh_testdir
+	: # give information about the build process
+	@echo "------------------------ Build process variables ------------------------"
+	@echo "Memory on this machine:"
+	@egrep '^(Mem|Swap)' /proc/meminfo || true
+	@echo "Number of parallel processes used for the build: $(USE_CPUS)"
+	@echo "DEB_BUILD_OPTIONS: $$DEB_BUILD_OPTIONS"
+	@echo "Package source: $(PKGSOURCE)"
+	@echo "GCC version: $(GCC_VERSION)"
+	@echo "Base Debian version: $(BASE_VERSION)"
+	@echo -e "Configured with: $(subst ___, ,$(foreach i,$(CONFARGS),$(i)\n\t))"
+ifeq ($(DEB_CROSS),yes)
+	@echo "Building cross compiler for $(DEB_TARGET_ARCH)"
+endif
+	@echo "Using shell $(SHELL)"
+	@echo "Architecture: $(DEB_TARGET_ARCH) (GNU: $(TARGET_ALIAS))"
+	@echo "CPPFLAGS: $(CPPFLAGS)"
+	@echo "CFLAGS: $(CFLAGS)"
+	@echo "LDFLAGS: $(LDFLAGS)"
+	@echo "BOOT_CFLAGS: $(BOOT_CFLAGS)"
+	@echo "DEBIAN_BUILDARCH: $(DEBIAN_BUILDARCH)"
+	@echo "Install prefix: /$(PF)"
+ifeq ($(biarchn32)-$(biarch64),yes-yes)
+	@echo "Will build the triarch compilers (o32/n32/64, defaulting to o32)"
+else ifeq ($(biarchn32)-$(biarch32),yes-yes)
+	@echo "Will build the triarch compilers (o32/n32/64, defaulting to 64)"
+else ifeq ($(biarch64)-$(biarch32),yes-yes)
+	@echo "Will build the triarch compilers (x32/64/32, defaulting to x32)"
+else ifeq ($(biarch64)-$(biarchx32),yes-yes)
+	@echo "Will build the triarch compilers (32/64/x32, defaulting to 32bit)"
+else ifeq ($(biarch32)-$(biarchx32),yes-yes)
+	@echo "Will build the triarch compilers (64/32/x32, defaulting to 64bit)"
+else
+  ifeq ($(biarch64),yes)
+	@echo "Will build the biarch compilers (32/64, defaulting to 32bit)"
+  else
+    ifeq ($(biarch32),yes)
+	@echo "Will build the biarch compilers (64/32, defaulting to 64bit)"
+    else
+	@echo "Will not build the biarch compilers"
+    endif
+  endif
+endif
+
+ifeq ($(with_cxx),yes)
+	@echo "Will build the C++ compiler"
+else
+	@echo "Will not build the C++ compiler: $(with_cxx)"
+endif
+ifeq ($(with_objc),yes)
+	@echo "Will build the ObjC compiler."
+    ifeq ($(with_objc_gc),yes)
+	@echo "Will build the extra ObjC runtime for garbage collection."
+    else
+	@echo "Will not build the extra ObjC runtime for garbage collection."
+    endif
+else
+	@echo "Will not build the ObjC compiler: $(with_objc)"
+endif
+ifeq ($(with_objcxx),yes)
+	@echo "Will build the Obj-C++ compiler"
+else
+	@echo "Will not build the Obj-C++ compiler: $(with_objcxx)"
+endif
+ifeq ($(with_fortran),yes)
+	@echo "Will build the Fortran 95 compiler."
+else
+	@echo "Will not build the Fortran 95 compiler: $(with_fortran)"
+endif
+ifeq ($(with_java),yes)
+	@echo "Will build the Java compiler."
+else
+	@echo "Will not build the Java compiler: $(with_java)"
+endif
+ifeq ($(with_ada),yes)
+	@echo "Will build the Ada compiler."
+  ifeq ($(with_libgnat),yes)
+	@echo "Will build the shared Ada libraries."
+  else
+	@echo "Will not build the shared Ada libraries."
+  endif
+else
+	@echo "Will not build the Ada compiler: $(with_ada)"
+endif
+ifeq ($(with_go),yes)
+	@echo "Will build the Go compiler."
+else
+	@echo "Will not build the Go compiler: $(with_go)"
+endif
+ifeq ($(with_d),yes)
+	@echo "Will build the D compiler"
+  ifeq ($(with_libphobos),yes)
+	@echo "Will build the phobos D runtime library."
+  else
+	@echo "Will not build the phobos D runtime library: $(with_libphobos)"
+  endif
+else
+	@echo "Will not build the D compiler: $(with_d)"
+endif
+ifeq ($(with_ssp),yes)
+	@echo "Will build with SSP support."
+else
+	@echo "Will build without SSP support: $(with_ssp)"
+endif
+ifeq ($(with_check),yes)
+	@echo "Will run the testsuite."
+else
+	@echo "Will not run the testsuite: $(with_check)"
+endif
+ifeq ($(with_nls),yes)
+	@echo "Will enable national language support."
+else
+	@echo "Will disable national language support: $(with_nls)"
+endif
+	@echo "-----------------------------------------------------------------------------"
+	@echo ""
+ifeq ($(with_check),yes)
+	@if echo "spawn true" | /usr/bin/expect -f - >/dev/null; then \
+	  : ; \
+	else \
+	  echo "expect is failing on your system with the above error, which means the GCC"; \
+	  echo "testsuite will fail.  Please resolve the above issues and retry the build."; \
+	  echo "-----------------------------------------------------------------------------"; \
+	  exit 1; \
+	fi
+endif
+	rm -f $(configure_stamp) $(build_stamp)
+	cat debian/README.Debian $(patch_stamp) > debian/README.Debian.$(DEB_TARGET_ARCH)
+
+	rm -rf $(builddir)
+	mkdir $(builddir)
+
+	: # some tools like gettext are built with a newer libstdc++
+	mkdir -p bin
+	for i in msgfmt; do \
+	  install -m755 debian/bin-wrapper.in bin/$$i; \
+	done
+
+	: # configure
+	cd $(builddir) \
+	  && $(SET_PATH) \
+		CC="$(CC)" \
+		CXX="$(CXX)" \
+		$(CFLAGS_TO_PASS) \
+		$(CXXFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS) \
+		$(CFLAGS_FOR_BUILD_TO_PASS) \
+		$(CXXFLAGS_FOR_BUILD_TO_PASS) \
+		$(LDFLAGS_FOR_BUILD_TO_PASS) \
+		$(CFLAGS_FOR_TARGET_TO_PASS) \
+		$(CXXFLAGS_FOR_TARGET_TO_PASS) \
+		$(LDFLAGS_FOR_TARGET_TO_PASS) \
+		$(SET_SHELL) $(SET_TARGET_TOOLS) \
+	LD_LIBRARY_PATH=$${LD_LIBRARY_PATH:+$$LD_LIBRARY_PATH:}$(builddir)/gcc/ada/rts \
+		../src/configure $(subst ___, ,$(CONFARGS))
+
+	: # multilib builds without b-d on gcc-multilib (used in FLAGS_FOR_TARGET)
+	if [ -d /usr/include/$(DEB_TARGET_MULTIARCH)/asm ]; then \
+	  mkdir -p $(builddir)/sys-include; \
+	  ln -sf /usr/include/$(DEB_TARGET_MULTIARCH)/asm $(builddir)/sys-include/asm; \
+	fi
+
+	touch $(configure_stamp)
+
+build: $(sort $(build_arch_dependencies) $(build_indep_dependencies))
+build-arch: $(build_arch_dependencies)
+build-indep: $(build_indep_dependencies)
+
+$(build_dummy_stamp):
+	touch $(build_dummy_stamp)
+
+$(build_locale_stamp):
+ifeq ($(locale_data)-$(with_cxx),generate-yes)
+	: # build locales needed by libstdc++ testsuite
+	rm -rf locales
+	mkdir locales
+	-USE_CPUS=$(USE_CPUS) sh debian/locale-gen
+endif
+	touch $(build_locale_stamp)
+
+
+$(build_stamp): $(configure_stamp) $(build_locale_stamp)
+	dh_testdir
+	rm -f bootstrap-protocol
+	@echo TTTTT $$(date -R)
+ifeq ($(build_type),build-native)
+	: # native build
+  ifeq ($(with_java),yes)
+	mkdir -p bin
+	ln -sf /usr/bin/fastjar bin/jar
+    ifeq ($(with_native_ecj),yes)
+	: # prepare the standalone ecj jar
+	cp /usr/share/java/ecj.jar $(srcdir)/ecj-standalone.jar
+	zip -d $(srcdir)/ecj-standalone.jar 'org/eclipse/jdt/core/JDTCompilerAdapter*'
+    endif
+    ifeq ($(with_java_maintainer_mode),yes)
+	( \
+	  echo '#!/bin/sh'; \
+	  echo 'exec gij-6 -cp /usr/share/java/ecj.jar org.eclipse.jdt.internal.compiler.batch.GCCMain "$$@"'; \
+	) > bin/ecj1
+	chmod +x bin/ecj1
+	: # If we don't have gjavah in PATH, try to build it with the old gij
+	mkdir -p bin
+	if [ -x /usr/bin/gjavah-6 ]; then \
+	  ln -sf /usr/bin/gjavah-6 bin/gjavah; \
+	elif [ -x bin/gjavah ]; then \
+	  : ; \
+	else \
+	  mkdir -p $(builddir)/java_hacks; \
+	  cd $(builddir)/java_hacks; \
+	  cp -a $(srcdir)/libjava/classpath/tools/external external; \
+	  mkdir -p gnu/classpath/tools; \
+	  cp -a $(srcdir)/libjava/classpath/tools/gnu/classpath/tools/{common,javah,getopt} \
+	    gnu/classpath/tools/; \
+	  cp -a $(srcdir)/libjava/classpath/tools/resource/gnu/classpath/tools/common/Messages.properties \
+	    gnu/classpath/tools/common; \
+	  cd external/asm; \
+	  for i in `find . -name \*.java`; do gcj-6 --encoding ISO-8859-1 -C $$i -I.; done; \
+	  cd ../..; \
+	  for i in `find gnu -name \*.java`; do gcj-6 -C $$i -I. -Iexternal/asm/; done; \
+	  gcj-6 -findirect-dispatch -O2 -fmain=gnu.classpath.tools.javah.Main \
+	    -I. -Iexternal/asm/ `find . -name \*.class` -o $(CURDIR)/bin/gjavah.real; \
+	  ( \
+	    echo '#!/bin/sh'; \
+	    echo 'export CLASSPATH='`pwd`'$${CLASSPATH:+:$$CLASSPATH}'; \
+	    echo 'exec $(CURDIR)/bin/gjavah.real "$$@"'; \
+	  ) > $(CURDIR)/bin/gjavah; \
+	  chmod +x $(CURDIR)/bin/gjavah; \
+	fi
+    endif
+  endif
+	: # build native compiler
+	( \
+	  set +e; \
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  $(SET_LOCPATH) \
+	    $(MAKE) -C $(builddir) $(bootstrap_target) \
+		CC="$(CC)" \
+		$(STAGE1_CFLAGS_TO_PASS) \
+		$(STAGE1_LDFLAGS_TO_PASS) \
+		$(BOOT_CFLAGS_TO_PASS) \
+		$(BOOT_LDFLAGS_TO_PASS) \
+		$(CFLAGS_TO_PASS) \
+		$(CXXFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS) \
+		$(CFLAGS_FOR_BUILD_TO_PASS) \
+		$(CXXFLAGS_FOR_BUILD_TO_PASS) \
+		$(LDFLAGS_FOR_BUILD_TO_PASS) \
+		$(CFLAGS_FOR_TARGET_TO_PASS) \
+		$(CXXFLAGS_FOR_TARGET_TO_PASS) \
+		$(LDFLAGS_FOR_TARGET_TO_PASS) \
+		; \
+	  echo $$? > status; \
+	) 2>&1 | tee bootstrap-protocol
+else ifneq (,$(filter $(build_type),build-cross cross-build-native cross-build-cross))
+	: # build cross compiler for $(TARGET_ALIAS)
+	( \
+	  set +e; \
+	  $(SET_PATH) \
+	  $(SET_LOCPATH) \
+	    $(MAKE) -C $(builddir) \
+		$(BOOT_CFLAGS_TO_PASS) \
+		$(BOOT_LDFLAGS_TO_PASS) \
+		$(CFLAGS_FOR_TARGET_TO_PASS) \
+		$(LDFLAGS_FOR_TARGET_TO_PASS) \
+		; \
+	  echo $$? > status; \
+	) 2>&1 | tee bootstrap-protocol
+endif
+	@echo TTTTT $$(date -R)
+	s=`cat status`; rm -f status; \
+	if [ $$s -ne 0 ] && [ -z "$$NO_CONFIG_LOG_DUMP$$NO_CONFIG_LOG_DUMPS" ]; then \
+	  for log in $$(find $(builddir) -name config.log); do \
+	    case "$$log" in */build/build-*|*/stage1-*|*/prev-*) continue; esac; \
+	    echo LOGFILE START $$log; \
+	    cat $$log; \
+	    echo LOGFILE END $$log; \
+	  done; \
+	fi; \
+	test $$s -eq 0
+
+	if [ -f $(srcdir)/contrib/warn_summary ]; then \
+	  rm -f bootstrap-summary; \
+	  /bin/sh $(srcdir)/contrib/warn_summary bootstrap-protocol \
+	    > bootstrap-summary; \
+	fi
+
+	touch $(build_stamp)
+
+ifneq ($(build_type),build-native)
+  BUILT_CC = $(CC)
+  BUILT_CXX = $(CXX)
+else
+  BUILT_CC = $(builddir)/gcc/xgcc -B$(builddir)/gcc/
+  BUILT_CXX = $(builddir)/gcc/xg++ -B$(builddir)/gcc/ \
+	-B$(builddir)/$(TARGET_ALIAS)/libatomic/.libs \
+	-B$(builddir)/$(TARGET_ALIAS)/libstdc++-v3/src/.libs \
+	-B$(builddir)/$(TARGET_ALIAS)/libstdc++-v3/libsupc++/.libs \
+	-I$(builddir)/$(TARGET_ALIAS)/libstdc++-v3/include \
+	-I$(builddir)/$(TARGET_ALIAS)/libstdc++-v3/include/$(TARGET_ALIAS) \
+	-I$(srcdir)/libstdc++-v3/libsupc++ \
+	-L$(builddir)/$(TARGET_ALIAS)/libatomic/.libs \
+	-L$(builddir)/$(TARGET_ALIAS)/libstdc++-v3/src/.libs \
+	-L$(builddir)/$(TARGET_ALIAS)/libstdc++-v3/libsupc++/.libs
+endif
+
+CONFARGS_JIT := \
+	$(filter-out --enable-languages=% \
+		--enable-libstdcxx-debug %bootstrap,\
+	  $(CONFARGS)) \
+	--enable-languages=c++,jit \
+	--enable-host-shared \
+	--disable-bootstrap
+
+$(configure_jit_stamp): $(build_stamp)
+	dh_testdir
+	rm -f $(configure_jit_stamp) $(build_jit_stamp)
+	rm -rf $(builddir_jit)
+	mkdir $(builddir_jit)
+
+	: # configure jit
+	cd $(builddir_jit) && \
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  CC="$(BUILT_CC)" \
+	  CXX="$(BUILT_CXX)" \
+	     ../src/configure $(subst ___, ,$(CONFARGS_JIT))
+	touch $(configure_jit_stamp)
+
+$(build_jit_stamp): $(configure_jit_stamp)
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  $(SET_LOCPATH) \
+	  LD_LIBRARY_PATH=$${LD_LIBRARY_PATH:+$$LD_LIBRARY_PATH:}$(builddir)/gcc \
+	  biarch_multidir_names=none \
+		$(MAKE) -C $(builddir_jit) \
+		$(BOOT_CFLAGS_TO_PASS) \
+		$(BOOT_LDFLAGS_TO_PASS) \
+		$(CFLAGS_FOR_TARGET_TO_PASS) \
+		$(LDFLAGS_FOR_TARGET_TO_PASS)
+
+ifeq ($(with_check),yes)
+  # FIXME: #782444
+  ifeq (,$(filter $(DEB_TARGET_ARCH), kfreebsd-i386 kfreebsd-amd64))
+	-$(MAKE) -C $(builddir_jit)/gcc check-jit \
+		RUNTESTFLAGS="-v -v"
+  endif
+endif
+
+	touch $(build_jit_stamp)
+
+ifeq ($(versioned_packages),yes)
+  hppa64_configure_flags += --program-suffix=-$(BASE_VERSION)
+endif
+
+$(configure_hppa64_stamp): $(build_stamp)
+	dh_testdir
+	rm -f $(configure_hppa64_stamp) $(build_hppa64_stamp)
+	rm -rf $(builddir_hppa64)
+	mkdir $(builddir_hppa64)
+	: # configure hppa64
+	cd $(builddir_hppa64) && \
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  CC="$(BUILT_CC)" \
+	  CXX="$(BUILT_CXX)" \
+	  $(CFLAGS_TO_PASS) \
+	  $(LDFLAGS_TO_PASS) \
+	     ../src/configure \
+		--enable-languages=c \
+		--prefix=/$(PF) \
+		--libexecdir=/$(hppa64libexecdir) \
+		--disable-shared \
+		--disable-nls \
+		--disable-threads \
+		--disable-libatomic \
+		--disable-libgomp \
+		--disable-libitm \
+		--disable-libssp \
+		--disable-libquadmath \
+		--enable-plugin \
+		--with-system-zlib \
+		--with-as=/usr/bin/hppa64-linux-gnu-as \
+		--with-ld=/usr/bin/hppa64-linux-gnu-ld \
+		--includedir=/usr/hppa64-linux-gnu/include \
+		--build=$(DEB_BUILD_GNU_TYPE) \
+		--host=$(DEB_HOST_GNU_TYPE) \
+		--target=hppa64-linux-gnu
+	touch $(configure_hppa64_stamp)
+
+$(build_hppa64_stamp): $(configure_hppa64_stamp)
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  $(SET_LOCPATH) \
+	  LD_LIBRARY_PATH=$${LD_LIBRARY_PATH:+$$LD_LIBRARY_PATH:}$(builddir)/gcc \
+	    $(MAKE) -C $(builddir_hppa64) \
+		$(if $(CFLAGS_FOR_TARGET),CFLAGS="$(CFLAGS_FOR_TARGET)") \
+		$(if $(CXXFLAGS_FOR_TARGET),CXXFLAGS="$(CXXFLAGS_FOR_TARGET)") \
+		$(if $(LDFLAGS_FOR_TARGET),LDFLAGS="$(LDFLAGS_FOR_TARGET)") \
+		$(CFLAGS_FOR_TARGET_TO_PASS) \
+		$(LDFLAGS_FOR_TARGET_TO_PASS)
+	touch $(build_hppa64_stamp)
+
+$(configure_neon_stamp): $(build_stamp)
+	dh_testdir
+	rm -f $(configure_neon_stamp) $(build_neon_stamp)
+	rm -rf $(builddir_neon)
+	mkdir $(builddir_neon)
+	: # configure neon
+	cd $(builddir_neon) && \
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  $(CFLAGS_TO_PASS) \
+	  $(LDFLAGS_TO_PASS) \
+	  CC="$(builddir)/gcc/xg++ -B$(builddir)/gcc/" \
+	     ../src/configure \
+		--disable-bootstrap \
+		--enable-languages=c,c++,objc,fortran \
+		--prefix=/$(PF) \
+		--libexecdir=/$(libexecdir) \
+		--program-suffix=-$(BASE_VERSION) \
+		--disable-nls \
+		--enable-plugin \
+		--with-arch=armv7-a --with-tune=cortex-a8 \
+		--with-float=$(float_abi) --with-fpu=neon \
+		--host=arm-linux-gnueabi \
+		--build=arm-linux-gnueabi \
+		--target=arm-linux-gnueabi
+	touch $(configure_neon_stamp)
+
+$(build_neon_stamp): $(configure_neon_stamp)
+	  $(SET_PATH) \
+	  $(SET_SHELL) \
+	  $(SET_LOCPATH) \
+	    $(MAKE) -C $(builddir_neon) \
+		$(BOOT_CFLAGS_TO_PASS) \
+		$(BOOT_LDFLAGS_TO_PASS) \
+		$(CFLAGS_FOR_TARGET_TO_PASS) \
+		$(LDFLAGS_FOR_TARGET_TO_PASS)
+	touch $(build_neon_stamp)
+
+
+ifeq ($(with_ada),yes)
+  MANUALS = \
+	$(srcdir)/gcc/ada/gnat_ugn.texi \
+	$(srcdir)/gcc/ada/gnat_rm.texi
+endif
+MANUALS += \
+	$(srcdir)/gcc/doc/gccint.texi \
+	$(srcdir)/gcc/doc/gcc.texi \
+	$(srcdir)/gcc/doc/cpp.texi \
+	$(srcdir)/gcc/doc/cppinternals.texi
+ifeq ($(with_fortran),yes)
+  MANUALS += $(srcdir)/gcc/fortran/gfortran.texi
+endif
+ifeq ($(with_java),yes)
+  MANUALS += $(srcdir)/gcc/java/gcj.texi
+endif
+ifeq ($(with_ada),yes)
+  MANUALS += $(srcdir)/gcc/ada/gnat-style.texi
+endif
+ifeq ($(with_gomp),yes)
+  MANUALS += $(srcdir)/libgomp/libgomp.texi
+endif
+ifeq ($(with_itm),yes)
+  MANUALS += $(srcdir)/libitm/libitm.texi
+endif
+ifeq ($(with_qmath),yes)
+  MANUALS += $(srcdir)/libquadmath/libquadmath.texi
+endif
+ifeq ($(with_go),yes)
+  MANUALS += $(srcdir)/gcc/go/gccgo.texi
+endif
+
+html-docs: $(build_html_stamp)
+#$(build_html_stamp): $(stampdir)/05-build-html-split
+$(build_html_stamp): $(stampdir)/05-build-html-nosplit
+
+html-makeinfo-split: $(stampdir)/05-build-html-split
+$(stampdir)/05-build-html-split: $(build_stamp)
+	mkdir -p html
+	rm -f html/*.html
+	cd $(builddir)/gcc; \
+	echo -n $(MANUALS) | xargs -d ' ' -L 1 -P $(USE_CPUS) -I{} \
+	  sh -c 'outname=`basename {} .texi`.html; \
+	  outname=`basename {} .texi`; \
+	  echo "generating $$outname ..."; \
+	  makeinfo --html --number-sections \
+		-I $(srcdir)/gcc/doc/include -I `dirname {}` \
+		-I $(srcdir)/gcc/p/doc \
+		-I $(srcdir)/gcc/p/doc/generated \
+		-I $(builddir)/gcc \
+		-I $(buildlibdir)/libquadmath \
+		-o $${outname} \
+		{}'
+	touch $@
+
+html-makeinfo-nosplit: $(stampdir)/05-build-html-nosplit
+$(stampdir)/05-build-html-nosplit: $(build_stamp)
+	mkdir -p html
+	rm -f html/*.html
+	cd $(builddir)/gcc; \
+	echo -n $(MANUALS) | xargs -d ' ' -L 1 -P $(USE_CPUS) -I{} \
+	  sh -c 'outname=`basename {} .texi`.html; \
+	  echo "generating $$outname ..."; \
+	  makeinfo --html --number-sections --no-split \
+		-I $(srcdir)/gcc/doc/include -I `dirname {}` \
+		-I $(srcdir)/gcc/p/doc \
+		-I $(srcdir)/gcc/p/doc/generated \
+		-I $(builddir)/gcc \
+		-I $(buildlibdir)/libquadmath \
+		-o $(CURDIR)/html/$${outname} \
+		{}'
+	touch $@
+
+# start the script only on architectures known to have slow autobuilders ...
+logwatch_archs := alpha arm m68k mips mipsel mips64el sparc
+ifeq ($(DEB_HOST_GNU_CPU), $(findstring $(DEB_HOST_GNU_CPU),$(logwatch_archs)))
+  start_logwatch = yes
+endif
+ifeq ($(DEB_HOST_GNU_SYSTEM),gnu)
+  start_logwatch = yes
+endif
+
+stamps/mauve-build: stamps/build
+	rm -rf mauve
+	mkdir -p mauve
+ifeq ($(with_mauve_check),yes)
+	tar xf $(wildcard /usr/src/mauve*.tar.*)
+	cd mauve \
+	    && aclocal \
+	    && automake \
+	    && autoconf2.59 \
+	    && PATH=$(CURDIR)/$(sdkimg)/bin:$$PATH ./configure --host=$(DEB_HOST_GNU_TYPE) --build=$(DEB_BUILD_GNU_TYPE)
+	PATH=$(CURDIR)/$(sdkimg)/bin:$$PATH $(MAKE) -C mauve
+endif
+	touch $@
+
+stamps/mauve-check: stamps/build stamps/mauve-build
+ifeq ($(with_mauve_check),yes)
+	-cd mauve && \
+	    JAVA_HOME=$(CURDIR)/$(sdkimg) \
+	    PATH=$(CURDIR)/$(sdkimg)/bin:$$PATH \
+		xvfb-run -s "-extension GLX" java Harness \
+		    -vm $(CURDIR)/$(sdkimg)/bin/java \
+		    -file $(CURDIR)/debian/mauve_tests \
+		    -timeout 30000 2>&1 \
+		| tee mauve_output
+	@sleep 5
+else
+	echo "mauve testsuite not run for this build" > mauve/mauve_output
+endif
+	touch $@
+
+check: $(check_stamp) # $(if $(filter yes, $(with_java)),stamps/05-build-mauve-stamp) #$(check_inst_stamp)
+$(check_stamp): $(filter $(build_stamp) $(build_jit_stamp) $(build_hppa64_stamp), $(build_dependencies))
+	rm -f test-protocol
+	rm -f $(builddir)/runcheck*
+
+	-chmod 755 $(srcdir)/contrib/test_summary
+
+	: # needed for the plugin tests to succeed
+	ln -sf gcc $(builddir)/prev-gcc
+	ln -sf $(DEB_TARGET_GNU_TYPE) $(builddir)/prev-$(DEB_TARGET_GNU_TYPE)
+
+ifneq ($(with_common_libs),yes)
+  ifeq ($(with_cxx),yes)
+	: # libstdc++6 built from newer gcc-X source, run testsuite against the installed lib
+
+	sed 's/-L[^ ]*//g' $(buildlibdir)/libstdc++-v3/scripts/testsuite_flags \
+	  > $(buildlibdir)/libstdc++-v3/scripts/testsuite_flags.installed
+	-$(ULIMIT_M); \
+	    set +e; \
+	    for d in $(buildlibdir)/libstdc++-v3/testsuite; do \
+	      echo "Running testsuite in $$d ..."; \
+	      TEST_INSTALLED=1 \
+	      $(SET_SHELL) \
+	      $(SET_LOCPATH) \
+	      $(SET_PATH) \
+	      DEJAGNU_TIMEOUT=$(DEJAGNU_TIMEOUT) \
+	      DEB_GCC_NO_O3=1 \
+		$(MAKE) -k -C $$d $(NJOBS) check $(RUNTESTFLAGS); \
+	    done 2>&1 | tee test-protocol2
+
+	BOOT_CFLAGS="$(BOOT_CFLAGS)" \
+	  $(srcdir)/contrib/test_summary -m "$(S_EMAIL)" > raw-test-summary
+	-( \
+	  sed -n '/^Mail/s/.*"\([^"][^"]*\)".*/\1/p' raw-test-summary; \
+	  awk '/^cat/, /^EOF/' raw-test-summary | grep -v EOF; \
+	) > libstdc++-test-summary
+	echo 'BEGIN installed libstdc++-v3 test-summary'
+	cat libstdc++-test-summary
+	echo 'END installed libstdc++-v3 test-summary'
+	find $(buildlibdir)/libstdc++-v3/testsuite -name '*.log' -o -name '*.sum' \
+	  | xargs -r rm -f
+  endif
+endif
+
+ifeq ($(start_logwatch),yes)
+	: # start logwatch script for regular output during test runs
+	chmod +x debian/logwatch.sh
+	-debian/logwatch.sh -t 900 -p $(builddir)/logwatch.pid \
+		-m '\ntestsuite still running ...\n' \
+		test-protocol \
+		$(builddir)/gcc/testsuite/gcc/gcc.log \
+		$(builddir)/gcc/testsuite/g++/g++.log \
+		$(builddir)/gcc/testsuite/gfortran/gfortran.log \
+		$(builddir)/gcc/testsuite/objc/objc.log \
+		$(builddir)/gcc/testsuite/obj-c++/obj-c++.log \
+		$(builddir)/gcc/testsuite/gnat/gnat.log \
+		$(builddir)/gcc/testsuite/ada/acats/acats.log \
+		$(builddir)/gcc/testsuite/gfortran/gfortran.log \
+		$(builddir)/gcc/p/test/test_log \
+		$(buildlibdir)/libstdc++-v3/testsuite/libstdc++.log \
+		$(buildlibdir)/libjava/testsuite/libjava.log \
+		$(buildlibdir)/libgomp/testsuite/libgomp.log \
+		$(buildlibdir)/libffi/testsuite/libffi.log \
+		&
+endif
+
+ifeq ($(with_ada),yes)
+	chmod +x debian/acats-killer.sh
+	-debian/acats-killer.sh -p $(builddir)/acats-killer.pid \
+		$(builddir)/gcc/testsuite/ada/acats/acats.log \
+		$(builddir)/gcc/testsuite/g++.log \
+		&
+endif
+
+	-$(ULIMIT_M); \
+	    set +e; \
+	    for d in $(checkdirs); do \
+	      echo "Running testsuite in $$d ..."; \
+	      $(SET_SHELL) \
+	      $(SET_LOCPATH) \
+	      $(SET_PATH) \
+	      EXTRA_TEST_PFLAGS=-g0 \
+	      DEJAGNU_TIMEOUT=$(DEJAGNU_TIMEOUT) \
+	      DEB_GCC_NO_O3=1 \
+		$(MAKE) -k -C $$d $(NJOBS) check $(RUNTESTFLAGS); \
+	    done 2>&1 | tee test-protocol
+
+	-ps aux | fgrep logwatch | fgrep -v fgrep
+	-if [ -f $(builddir)/logwatch.pid ]; then \
+	  kill -1 `cat $(builddir)/logwatch.pid`; \
+	  sleep 1; \
+	  kill -9 `cat $(builddir)/logwatch.pid`; \
+	  rm -f $(builddir)/logwatch.pid; \
+	fi
+	-ps aux | fgrep logwatch | fgrep -v fgrep
+
+ifeq ($(with_ada),yes)
+	-if [ -f $(builddir)/acats-killer.pid ]; then \
+	  kill -1 `cat $(builddir)/acats-killer.pid`; \
+	  sleep 1; \
+	  kill -9 `cat $(builddir)/acats-killer.pid`; \
+	  rm -f $(builddir)/acats-killer.pid; \
+	fi
+endif
+
+	: # running the libjava testsuite alone is missing this information
+	$(builddir)/gcc/xgcc -B$(builddir)/gcc/ -v > $(builddir)/compiler_version.sum 2>&1
+
+	if [ -x $(srcdir)/contrib/test_summary ]; then \
+	  rm -f test-summary; \
+	  ( \
+	    cd $(builddir); \
+	    echo '' > ts-include; \
+	    echo '' >> ts-include; \
+	    if [ -f $(builddir)/gcc/.bad_compare ]; then \
+	      echo 'Bootstrap comparison failure:' >> ts-include; \
+	      cat $(builddir)/gcc/.bad_compare >> ts-include; \
+	      echo '' >> ts-include; \
+	      echo '' >> ts-include; \
+	    fi; \
+	    echo "Build Dependencies:" >> ts-include; \
+	    dpkg -l g++-* binutils* `echo '$(LIBC_DEP)' | awk '{print $$1}'` \
+		libgmp*-dev libmpfr-dev libmpc-dev libisl-dev \
+	        | fgrep -v '<none>' >> ts-include; \
+	    echo '' >> ts-include; \
+	    cat ../$(patch_stamp) >> ts-include; \
+	    BOOT_CFLAGS="$(BOOT_CFLAGS)" \
+	      $(srcdir)/contrib/test_summary \
+		-i ts-include -m "$(S_EMAIL)" \
+	  ) > raw-test-summary; \
+	  if [ -n "$(testsuite_tarball)" ]; then \
+	    echo "Test suite used: $(testsuite_srcdir)" > test-summary; \
+	    echo "  Do not interpret the results on its own" >> test-summary; \
+	    echo "  but compare them with the results from" >> test-summary; \
+	    echo "  the gcc-snapshot package." >> test-summary; \
+	  fi; \
+	  sed -n '/^Mail/s/.*"\([^"][^"]*\)".*/\1/p' raw-test-summary \
+		>> test-summary; \
+	  awk '/^cat/, /^EOF/' raw-test-summary | grep -v EOF >> test-summary; \
+	  if [ -f bootstrap-summary -a "$(bootstrap_target)" != profiledbootstrap ]; then \
+	    echo '' >> test-summary; \
+	    cat bootstrap-summary >> test-summary; \
+	  fi; \
+	  echo 'BEGIN test-summary'; \
+	  cat test-summary; \
+	  echo 'END test-summary'; \
+	fi
+ifeq ($(with_d),yes)
+	: # the D test failures for the non-default multilibs are known, ignore them
+	egrep -v '^(FAIL|UNRESOLVED): (runnable|fail_c|comp)' test-summary > test-summary.tmp
+	mv -f test-summary.tmp test-summary
+endif
+
+	touch $(check_stamp)
+
+$(check_inst_stamp): $(check_stamp)
+	rm -f test-inst-protocol
+
+ifeq ($(start_logwatch),yes)
+	: # start logwatch script for regular output during test runs
+	chmod +x debian/logwatch.sh
+	-debian/logwatch.sh -t 900 -p $(builddir)/logwatch-inst.pid \
+		-m '\ntestsuite (3.3) still running ...\n' \
+		test-inst-protocol \
+		check-inst/{gcc,g++,g77,objc}.log \
+		&
+endif
+
+	rm -rf check-inst
+	mkdir check-inst
+
+	echo "Running testsuite ..."
+	-$(ULIMIT_M) ; \
+	    $(SET_SHELL) \
+	    $(SET_LOCPATH) \
+	    EXTRA_TEST_PFLAGS=-g0 \
+	    DEJAGNU_TIMEOUT=$(DEJAGNU_TIMEOUT) \
+	  cd check-inst && $(srcdir)/contrib/test_installed \
+	    --with-gcc=gcc-3.3 --with-g++=g++-3.3 --with-g77=g77-3.3 \
+		2>&1 | tee test-inst-protocol
+
+	-ps aux | fgrep logwatch | fgrep -v fgrep
+	if [ -f $(builddir)/logwatch-inst.pid ]; then \
+	  kill -1 `cat $(builddir)/logwatch-inst.pid`; \
+	else \
+	  true; \
+	fi
+	-ps aux | fgrep logwatch | fgrep -v fgrep
+
+	-chmod 755 $(srcdir)/contrib/test_summary
+	if [ -x $(srcdir)/contrib/test_summary ]; then \
+	  rm -f test-inst-summary; \
+	  ( \
+	    cd check-inst; \
+	    echo '' > ts-include; \
+	    echo '' >> ts-include; \
+	    echo "Build Dependencies:" >> ts-include; \
+	    dpkg -l g++-* binutils* `echo '$(LIBC_DEP)' | awk '{print $$1}'` \
+		libgmp*-dev libmpfr-dev libmpc-dev libisl*-dev \
+	        | fgrep -v '<none>' >> ts-include; \
+	    echo '' >> ts-include; \
+	    echo 'Results for the installed GCC-3.3 compilers' >> ts-include; \
+	    $(srcdir)/contrib/test_summary \
+		-i ts-include -m "$(S_EMAIL)" \
+	  ) > raw-test-inst-summary; \
+	  sed -n '/^Mail/s/.*"\([^"][^"]*\)".*/\1/p' raw-test-inst-summary \
+		>> test-inst-summary; \
+	  awk '/^cat/, /^EOF/' raw-test-inst-summary \
+		| grep -v EOF >> test-inst-summary; \
+	  echo 'BEGIN test-installed-summary'; \
+	  cat test-inst-summary; \
+	  echo 'END test-installed-summary'; \
+	fi
+
+	chmod 755 debian/reduce-test-diff.awk
+	if diff -u test-inst-summary test-summary \
+		| debian/reduce-test-diff.awk > diff-summary; \
+	then \
+	  mv -f diff-summary testsuite-comparision; \
+	else \
+	  ( \
+	    echo "WARNING: New failures in gcc-3.4 compared to gcc-3.3"; \
+	    echo ''; \
+	    cat diff-summary; \
+	  ) > testsuite-comparision; \
+	  rm -f diff-summary; \
+	fi
+	touch $(check_inst_stamp)
+
+clean: debian/control
+	dh_testdir
+	rm -f pxxx status
+	rm -f *-summary *-protocol testsuite-comparision summary-diff
+	rm -f $(srcdir)/gcc/po/*.gmo
+	rm -f debian/lib{gcc,gcj,objc,stdc++}{-v3,[0-9]}*.{{pre,post}{inst,rm},shlibs}
+	fs=`echo debian/*BV* debian/*GCJ* debian/*CXX* debian/*LC* debian/*MF* | sort -u`; \
+	for f in $$fs; do \
+	  [ -f $$f ] || continue; \
+	  f2=$$(echo $$f \
+		| sed 's/BV/$(BASE_VERSION)/;s/CXX/$(CXX_SONAME)/;s/LGCJ/$(PKG_LIBGCJ_EXT)/;s/GCJ/$(PKG_GCJ_EXT)/;s/LC/$(GCC_SONAME)/;s/-CRB/$(cross_bin_arch)/;s/\.in$$//'); \
+	  rm -f $$f2; \
+	done
+	rm -f debian/lib*gcc1.symbols
+	rm -f debian/lib*{atomic$(ATOMIC_SONAME),cilkrts$(CILKRTS_SONAME),gfortran$(FORTRAN_SONAME),gomp$(GOMP_SONAME),itm$(ITM_SONAME),mpx$(MPX_SONAME),quadmath$(QUADMATH_SONAME)}.symbols
+	find debian -maxdepth 1 -name '*-cross.symbols' -type l | xargs -r rm -f
+	rm -f debian/gcc-{XX,ar,nm,ranlib}-$(BASE_VERSION).1
+	rm -f debian/shlibs.local debian/shlibs.common* debian/substvars.local
+	rm -f debian/*.debhelper
+	-[ -d debian/bugs ] && $(MAKE) -C debian/bugs clean
+	rm -f debian/README.libstdc++-baseline debian/README.Bugs debian/README.Debian.$(DEB_TARGET_ARCH)
+	rm -f debian/lib*gcj-bc.shlibs
+	rm -f debian/arch_binaries* debian/indep_binaries*
+	rm -rf bin locales share
+	rm -rf check-inst
+	rm -rf .pc
+	dh_clean
+ifneq (,$(filter $(build_type), build-cross cross-build-cross))
+	$(cross_clean) dh_clean
+endif
+
+# -----------------------------------------------------------------------------
+# some abbrevations for the package names and directories;
+# p_XXX is the package name, d_XXX is the package directory
+# these macros are only used in the binary-* targets.
+
+ifeq ($(versioned_packages),yes)
+  pkg_ver := -$(BASE_VERSION)
+endif
+
+ifneq ($(DEB_CROSS),yes)
+  p_base = gcc$(pkg_ver)-base
+  p_lbase = $(p_base)
+  p_xbase = gcc$(pkg_ver)-base
+  p_gcc  = gcc$(pkg_ver)
+  p_cpp  = cpp$(pkg_ver)
+  p_cppd = cpp$(pkg_ver)-doc
+  p_cxx  = g++$(pkg_ver)
+  p_doc  = gcc$(pkg_ver)-doc
+else
+  # only triggered if DEB_CROSS set
+  p_base = gcc$(pkg_ver)$(cross_bin_arch)-base
+  p_lbase = gcc$(pkg_ver)-cross-base$(GCC_PORTS_BUILD)
+  p_xbase = gcc$(pkg_ver)$(cross_bin_arch)-base
+  p_cpp  = cpp$(pkg_ver)$(cross_bin_arch)
+  p_gcc  = gcc$(pkg_ver)$(cross_bin_arch)
+  p_cxx  = g++$(pkg_ver)$(cross_bin_arch)
+endif
+p_hppa64 = gcc$(pkg_ver)-hppa64-linux-gnu
+
+# needed for shlibs.common* generation
+ifeq (,$(p_lgcc))
+  p_lgcc = libgcc$(GCC_SONAME)$(cross_lib_arch)
+endif
+ifeq (,$(p_lib))
+  p_lib = libstdc++$(CXX_SONAME)$(cross_lib_arch)
+endif
+
+d	= debian/tmp
+d_base	= debian/$(p_base)
+d_xbase = debian/$(p_xbase)
+d_gcc	= debian/$(p_gcc)
+d_cpp	= debian/$(p_cpp)
+d_cppd	= debian/$(p_cppd)
+d_cxx	= debian/$(p_cxx)
+d_doc	= debian/$(p_doc)
+d_lgcc	= debian/$(p_lgcc)
+d_hppa64= debian/$(p_hppa64)
+
+d_neon   = debian/tmp-neon
+
+common_substvars = \
+	$(shell awk "{printf \"'-V%s' \", \$$0}" debian/substvars.local)
+
+ifeq ($(DEB_CROSS),yes)
+  lib_binaries := indep_binaries
+else
+  lib_binaries := arch_binaries
+endif
+
+# ---------------------------------------------------------------------------
+
+ifeq ($(single_package),yes)
+  include debian/rules.d/binary-snapshot.mk
+else
+
+ifneq ($(with_base_only),yes)
+ifneq ($(DEB_CROSS),yes)
+ifeq ($(with_source),yes)
+  include debian/rules.d/binary-source.mk
+endif
+endif
+endif
+
+ifneq ($(BACKPORT),true)
+
+ifeq ($(with_gccbase),yes)
+  include debian/rules.d/binary-base.mk
+endif
+
+ifneq ($(with_base_only),yes)
+
+# always include to get some definitions
+include debian/rules.d/binary-libgcc.mk
+
+ifeq ($(with_libqmath),yes)
+  include debian/rules.d/binary-libquadmath.mk
+endif
+
+ifeq ($(with_libgmath),yes)
+  include debian/rules.d/binary-libgccmath.mk
+endif
+
+ifeq ($(with_libgomp),yes)
+  include debian/rules.d/binary-libgomp.mk
+endif
+
+ifeq ($(with_libitm),yes)
+  include debian/rules.d/binary-libitm.mk
+endif
+
+ifeq ($(with_libatomic),yes)
+  include debian/rules.d/binary-libatomic.mk
+endif
+
+ifeq ($(with_libbacktrace),yes)
+  include debian/rules.d/binary-libbacktrace.mk
+endif
+
+ifeq ($(with_cdev),yes)
+  include debian/rules.d/binary-cpp.mk
+endif
+
+ifeq ($(with_fixincl),yes)
+  include debian/rules.d/binary-fixincl.mk
+endif
+
+ifeq ($(with_libssp),yes)
+  include debian/rules.d/binary-libssp.mk
+endif
+
+ifeq ($(with_objcxx),yes)
+  include debian/rules.d/binary-objcxx.mk
+endif
+
+ifeq ($(with_objc),yes)
+  include debian/rules.d/binary-objc.mk
+  include debian/rules.d/binary-libobjc.mk
+endif
+
+ifeq ($(with_go),yes)
+  include debian/rules.d/binary-go.mk
+endif
+
+# include before cxx
+ifeq ($(with_java),yes)
+  include debian/rules.d/binary-java.mk
+endif
+
+ifeq ($(with_cxxdev),yes)
+  include debian/rules.d/binary-cxx.mk
+endif
+ifeq ($(with_cxx),yes)
+  include debian/rules.d/binary-libstdcxx.mk
+endif
+
+ifeq ($(with_libasan),yes)
+  include debian/rules.d/binary-libasan.mk
+endif
+
+ifeq ($(with_liblsan),yes)
+  include debian/rules.d/binary-liblsan.mk
+endif
+
+ifeq ($(with_libtsan),yes)
+  include debian/rules.d/binary-libtsan.mk
+endif
+
+ifeq ($(with_libubsan),yes)
+  include debian/rules.d/binary-libubsan.mk
+endif
+
+ifeq ($(with_libvtv),yes)
+  include debian/rules.d/binary-libvtv.mk
+endif
+
+ifeq ($(with_libcilkrts),yes)
+  include debian/rules.d/binary-libcilkrts.mk
+endif
+
+ifeq ($(with_libmpx),yes)
+  include debian/rules.d/binary-libmpx.mk
+endif
+
+ifeq ($(with_f77),yes)
+  include debian/rules.d/binary-f77.mk
+endif
+
+ifeq ($(with_fortran),yes)
+  include debian/rules.d/binary-fortran.mk
+endif
+
+ifeq ($(with_ada),yes)
+  include debian/rules.d/binary-ada.mk
+endif
+
+ifeq ($(with_d),yes)
+  include debian/rules.d/binary-d.mk
+endif
+
+ifeq ($(with_libcc1),yes)
+  include debian/rules.d/binary-libcc1.mk
+endif
+
+ifeq ($(with_jit),yes)
+  include debian/rules.d/binary-libgccjit.mk
+endif
+
+ifeq ($(with_libnof),yes)
+  ifeq ($(DEB_TARGET_GNU_CPU),powerpc)
+    include debian/rules.d/binary-nof.mk
+  endif
+endif
+
+ifeq ($(with_softfloat),yes)
+  include debian/rules.d/binary-softfloat.mk
+endif
+
+# gcc must be moved/built after g77 and g++
+ifeq ($(with_cdev),yes)
+  include debian/rules.d/binary-gcc.mk
+endif
+
+ifeq ($(with_hppa64),yes)
+  include debian/rules.d/binary-hppa64.mk
+endif
+
+ifeq ($(with_neon),yes)
+  include debian/rules.d/binary-neon.mk
+endif
+
+endif # with_base_only
+endif # BACKPORT
+endif # ($(single_package),yes)
+
+# ----------------------------------------------------------------------
+install: $(install_dependencies)
+
+$(install_dummy_stamp): $(build_dummy_stamp)
+	touch $(install_dummy_stamp)
+
+$(install_snap_stamp): $(build_dependencies)
+	dh_testdir
+	dh_testroot
+	dh_prep
+
+	: # Install directories
+	rm -rf $(d)
+	mkdir -p $(d)/$(PF)
+
+ifeq ($(with_hppa64),yes)
+	: # Install hppa64
+	$(SET_PATH) \
+	    $(MAKE) -C $(builddir_hppa64) \
+		CC="$(CC)" \
+		$(CFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS) \
+		DESTDIR=$(CURDIR)/$(d) \
+		    install
+
+	ls -l $(d)/$(PF)/bin
+	if [ ! -x $(d)/$(PF)/bin/hppa64-linux-gnu-gcc ]; then \
+	  mv $(d)/$(PF)/bin/hppa64-linux-gnu-gcc-6* $(d)/$(PF)/bin/hppa64-linux-gnu-gcc; \
+	else \
+	  rm -f $(d)/$(PF)/bin/hppa64-linux-gnu-gcc-6*; \
+	fi
+
+	for i in ar nm ranlib; do \
+	  cp debian/gcc-$$i-$(BASE_VERSION).1 \
+	    $(d)/$(PF)/share/man/man1/hppa64-linux-gnu-gcc-$$i.1; \
+	done
+
+	: # remove files not needed from the hppa64 build
+	rm -rf $(d)/$(PF)/share/info
+	rm -rf $(d)/$(PF)/share/man
+	rm -f $(d)/$(PF)/$(libdir)/libiberty.a
+	rm -f $(d)/$(PF)/bin/*{gcov,gcov-dump,gcov-tool,gccbug,gcc}
+
+	rm -rf $(d)/$(PF)/hppa64-linux-gnu/include
+	rm -rf $(d)/$(PF)/hppa64-linux-gnu/lib
+	set -e; \
+	  cd $(d)/$(PF)/$(libdir)/gcc/hppa64-linux-gnu/$(versiondir)/include-fixed; \
+	  for i in *; do \
+	    case "$$i" in \
+	      README|features.h|syslimits.h|limits.h) ;; \
+	      linux|$(TARGET_ALIAS)) ;; \
+	      $(subst $(DEB_TARGET_GNU_CPU),$(biarch_cpu),$(TARGET_ALIAS))) ;; \
+	      *) echo "remove include-fixed/$$i"; rm -rf $$i; \
+	    esac; \
+	  done
+endif
+
+	: # Work around PR lto/41569
+	ln -sf gcc $(builddir)/prev-gcc
+	ln -sf $(DEB_TARGET_GNU_TYPE) $(builddir)/prev-$(DEB_TARGET_GNU_TYPE)
+
+	: # Install everything
+	$(SET_PATH) \
+	$(SET_SHELL) \
+	  $(MAKE) -C $(builddir) \
+	    $(CFLAGS_TO_PASS) \
+	    $(LDFLAGS_TO_PASS) \
+	    DESTDIR=$(CURDIR)/$(d) \
+	    infodir=/$(PF)/share/info \
+	    mandir=/$(PF)/share/man \
+		install
+
+	ls -l $(d)/$(PF)/bin
+
+	for i in ar nm ranlib; do \
+	  cp debian/gcc-$$i-$(BASE_VERSION).1 \
+	    $(d)/$(PF)/share/man/man1/$(cmd_prefix)gcc-$$i.1; \
+	done
+
+	if [ ! -x $(d)/$(PF)/bin/$(TARGET_ALIAS)-gcc ]; then \
+	  mv $(d)/$(PF)/bin/$(TARGET_ALIAS)-gcc-6* $(d)/$(PF)/bin/$(TARGET_ALIAS)-gcc; \
+	else \
+	  rm -f $(d)/$(PF)/bin/$(TARGET_ALIAS)-gcc-6*; \
+	fi
+	set -e; \
+	  cd $(d)/$(gcc_lib_dir)/include-fixed; \
+	  for i in *; do \
+	    case "$$i" in \
+	      README|features.h|syslimits.h|limits.h) ;; \
+	      linux|$(TARGET_ALIAS)) ;; \
+	      $(subst $(DEB_TARGET_GNU_CPU),$(biarch_cpu),$(TARGET_ALIAS))) ;; \
+	      *) echo "remove include-fixed/$$i"; rm -rf $$i; \
+	    esac; \
+	  done
+
+ifneq ($(configured_libdir),$(libdir))
+	for i in debug go pkgconfig '*.so' '*.so.*' '*.a' '*.la' '*.py' '*.spec'; do \
+	  mv $(d)/$(PF)/$(configured_libdir)/$$i \
+		$(d)/$(PF)/$(libdir)/. || true; \
+	done
+endif
+
+# FIXME: libjava/classpath not correctly patched
+ifeq ($(with_java),yes)
+	-if [ -d $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME) ]; then \
+	  ls -l $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME); \
+	  mv $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME)/* \
+	    $(d)/$(PF)/lib/gcj-$(BASE_VERSION)-$(GCJ_SONAME)/; \
+	  rmdir $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME); \
+	fi
+
+	ln -sf libgcj.so.$(GCJ_SONAME).0.0 $(d)/$(PF)/lib/libgcj_bc.so.1.0.0
+
+	install -m 755 $(d)/$(PF)/lib/libgcj_bc.so.1 \
+		$(d)/$(gcc_lib_dir)/libgcj_bc.so
+	$(builddir)/gcc/xgcc -B$(builddir)/gcc/ -shared -fpic -xc /dev/null \
+		-o build/libgcj.so -Wl,-soname,libgcj.so.$(GCJ_SONAME) -nostdlib
+	$(builddir)/gcc/xgcc -B$(builddir)/gcc/ -shared -fpic \
+		$(srcdir)/libjava/libgcj_bc.c \
+		-o $(d)/$(gcc_lib_dir)/libgcj_bc.so \
+		-Wl,-soname,libgcj_bc.so.1 $(builddir)/libgcj.so -shared-libgcc
+endif
+
+	-ls -l $(d)/usr
+	if [ -d $(d)/usr/man/man1 ]; then \
+	  mv $(d)/usr/man/man1/* $(d)/usr/share/man/man1/; \
+	fi
+
+	chmod 755 debian/dh_*
+	touch $(install_snap_stamp)
+
+$(install_stamp): $(build_stamp)
+	dh_testdir
+	dh_testroot
+	dh_prep $(if $(filter yes,$(with_hppa64)),-N$(p_hppa64))
+
+	if [ -f $(binary_stamp)-hppa64 ]; then \
+	  mv $(binary_stamp)-hppa64 saved-stamp-hppa64; \
+	fi
+	rm -f $(binary_stamp)*
+	if [ -f saved-stamp-hppa64 ]; then \
+	  mv saved-stamp-hppa64 $(binary_stamp)-hppa64; \
+	fi
+
+	: # Install directories
+	rm -rf $(d)
+	mkdir -p $(d)/$(libdir) $(d)/$(PF) $(d)/$(PF)/$(libdir)/debug
+ifeq ($(biarch32),yes)
+	mkdir -p $(d)/$(PF)/$(lib32loc)/debug
+endif
+ifeq ($(biarch64),yes)
+	mkdir -p $(d)/$(PF)/lib64/debug
+endif
+ifeq ($(biarchn32),yes)
+	mkdir -p $(d)/$(PF)/$(libn32)/debug
+endif
+ifeq ($(biarchx32),yes)
+	mkdir -p $(d)/$(PF)/libx32/debug
+endif
+
+ifneq (,$(filter $(DEB_TARGET_GNU_CPU),x86_64 sparc64 s390x powerpc64))
+ifneq ($(DEB_TARGET_ARCH),x32)
+	: # link lib to lib64 and $(PF)/lib to $(PF)/lib64
+	: # (this works when CONFARGS contains '--disable-multilib')
+	ln -s $(configured_libdir) $(d)/lib64
+	mkdir -p $(d)/$(PF)/$(configured_libdir)
+	ln -s $(configured_libdir) $(d)/$(PF)/lib64
+endif
+endif
+ifeq ($(DEB_TARGET_ARCH),x32)
+	: # link lib to libx32 and $(PF)/lib to $(PF)/libx32
+	ln -s $(configured_libdir) $(d)/libx32
+	mkdir -p $(d)/$(PF)/$(configured_libdir)
+	ln -s $(configured_libdir) $(d)/$(PF)/libx32
+endif
+
+	: # Work around PR lto/41569
+	ln -sf gcc $(builddir)/prev-gcc
+
+	: # Install everything
+	$(SET_PATH) \
+	$(SET_SHELL) \
+	  $(MAKE) -C $(builddir) \
+	    $(CFLAGS_TO_PASS) \
+	    $(LDFLAGS_TO_PASS) \
+	    DESTDIR=$(CURDIR)/$(d) \
+	    infodir=/$(PF)/share/info \
+	    mandir=/$(PF)/share/man \
+		install
+
+ifeq ($(DEB_STAGE)-$(DEB_CROSS),rtlibs-yes)
+	@echo configured_libdir=$(configured_libdir) / libdir=$(libdir) / usr_lib=$(usr_lib)
+	ls $(d)/$(PF)/$(TARGET_ALIAS)/lib
+	set -x; \
+	if [ -d $(d)/$(PF)/$(TARGET_ALIAS)/lib ]; then \
+	  cp -a $(d)/$(PF)/$(TARGET_ALIAS)/lib/* $(d)/$(PF)/lib/$(DEB_TARGET_MULTIARCH)/.; \
+	fi
+	for d in $$(cd $(d)/$(PF)/$(TARGET_ALIAS); echo lib?*); do \
+	  [ -d $(d)/$(PF)/$(TARGET_ALIAS)/$$d ] || continue; \
+	  cp -a $(d)/$(PF)/$(TARGET_ALIAS)/$$d/* $(d)/$(PF)/$$d/.; \
+	done
+else
+  ifneq ($(configured_libdir),$(libdir))
+	for i in debug go pkgconfig '*.so' '*.so.*' '*.a' '*.la' '*.o' '*.py' '*.spec'; do \
+	  mv $(d)/$(PF)/$(configured_libdir)/$$i \
+		$(d)/$(PF)/$(libdir)/. || true; \
+	done
+  endif
+endif
+
+ifneq (,$(cmd_prefix))
+	for i in $(d)/$(PF)/share/info/$(cmd_prefix)*; do \
+	  [ -f "$$i" ] || continue; \
+	  mv $$i $$(echo $$i | sed 's/$(cmd_prefix)//'); \
+	done
+endif
+
+ifeq ($(with_libcxxdbg),yes)
+	: # FIXME: the libstdc++ gdb.py file is installed with a wrong name
+	for i in $$(find $(d)/$(PF) -name libstdc++_pic.a-gdb.py); do \
+	  [ -f $$i ] || continue; \
+	  d=$$(dirname $$i); \
+	  b=$$(basename $$i); \
+	  t=$$(cd $$d; echo libstdc++.so.*.*.*)-gdb.py; \
+	  mv $$i $$d/$$t; \
+	done
+endif
+
+	if [ -d $(d)/$(PF)/include/cilk ]; then \
+	  mv $(d)/$(PF)/include/cilk $(d)/$(gcc_lib_dir)/include/. ;\
+	fi
+
+ifeq ($(with_java),yes)
+# FIXME: libjava/classpath not correctly patched
+	-if [ -d $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME) ]; then \
+	  ls -l $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME); \
+	  mv $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME)/* \
+	    $(d)/$(PF)/lib/gcj-$(BASE_VERSION)-$(GCJ_SONAME)/; \
+	  rmdir $(d)/$(PF)/lib/gcj-$(GCC_VERSION)-$(GCJ_SONAME); \
+	fi
+endif
+
+	: # remove rpath settings from binaries and shared libs
+	for i in $$(chrpath -k $(d)/$(PF)/bin/* $(d)/$(PFL)/lib*/lib*.so.* \
+			$(d)/$(gcc_lib_dir)/plugin/* \
+			$(if $(filter $(with_multiarch_lib),yes), \
+			  $(d)/$(PF)/lib/$(DEB_TARGET_MULTIARCH)/lib*.so.*) \
+			$(d)/$(PF)/lib*/gcj$(pkg_ver)*/lib*.so.* \
+			2>/dev/null | awk -F: '/R(UN)?PATH=/ {print $$1}'); \
+	do \
+	  case "$$i" in ecj1|*gij-*|*libjawt*|*libjvm*) continue; esac; \
+	  [ -h $$i ] && continue; \
+	  chrpath --delete $$i; \
+	  echo "removed RPATH/RUNPATH: $$i"; \
+	done
+
+	: # remove '*.la' and '*.lai' files, not shipped in any package.
+	find $(d) -name '*.la' -o -name '*.lai' | xargs -r rm -f
+
+ifeq ($(GFDL_INVARIANT_FREE),yes)
+	for i in gcc gcov; do \
+	  I=`echo $$i | tr a-z A-Z`; \
+	  sed -e "s/@NAME@/$$I$(pkg_ver)/g" -e "s/@name@/$$i$(pkg_ver)/g" \
+	    debian/dummy-man.1 > $(d)/$(PF)/share/man/man1/$$i.1; \
+	done
+
+  ifeq ($(with_fortran),yes)
+	for i in g77; do \
+	  I=`echo $$i | tr a-z A-Z`; \
+	  sed -e "s/@NAME@/$$I$(pkg_ver)/g" -e "s/@name@/$$i$(pkg_ver)/g" \
+	    debian/dummy-man.1 > $(d)/$(PF)/share/man/man1/$$i.1; \
+	done
+  endif
+  ifeq ($(with_java),yes)
+	for i in gcj gcjh gij jv-convert jv-scan jcf-dump grmic grmiregistry; \
+	do \
+	  I=`echo $$i | tr a-z A-Z`; \
+	  sed -e "s/@NAME@/$$I$(pkg_ver)/g" -e "s/@name@/$$i$(pkg_ver)/g" \
+	    debian/dummy-man.1 > $(d)/$(PF)/share/man/man1/$$i.1; \
+	done
+  endif
+endif
+
+ifneq ($(with_libgnat),yes)
+	rm -f $(d)/$(gcc_lib_dir)/adalib/lib*.so*
+endif
+
+# FIXME: libgnatprj and libgnatvsn need proper configury/Makefiles
+ifeq ($(DEB_CROSS),yes)
+  ifeq ($(with_ada),yes)
+	for i in 'libgnatprj*' 'libgnatvsn*'; do \
+	  mv $(d)/$(PF)/lib/$$i $(d)/$(usr_lib)/. || true; \
+	done
+  endif
+endif
+
+#  ifeq ($(with_ada),yes)
+#	: # rename files (versioned ada binaries)
+#	for i in ; do \
+#	  mv $(d)/$(PF)/bin/$$i $(d)/$(PF)/bin/$$i-$(GNAT_VERSION); \
+#	  mv $(d)/$(PF)/share/man/man1/$$i.1 \
+#		$(d)/$(PF)/share/man/man1/$$i-$(GNAT_VERSION).1; \
+#	done
+#	for i in $(GNAT_TOOLS); do \
+#	  mv $(d)/$(PF)/bin/$$i $(d)/$(PF)/bin/$$i-$(GNAT_VERSION); \
+#	done
+#  endif
+
+	for i in ar nm ranlib; do \
+	  cp debian/gcc-$$i-$(BASE_VERSION).1 \
+	    $(d)/$(PF)/share/man/man1/$(cmd_prefix)gcc-$$i$(pkg_ver).1; \
+	done
+
+	chmod 755 debian/dh_*
+
+ifneq ($(with_common_libs),yes)
+# for native builds, the default ml libs are always available; no need for a placeholder
+# apparently this changed with newer dpkg versions (1.18.7?) ...
+	echo 'libgcc_s $(GCC_SONAME) $(p_lgcc)' > debian/shlibs.common
+	echo 'libstdc++ $(CXX_SONAME) $(p_lib)' >> debian/shlibs.common
+	echo 'libquadmath $(QUADMATH_SONAME) libquadmath$(QUADMATH_SONAME)' >> debian/shlibs.common
+	echo 'libatomic $(ATOMIC_SONAME) libatomic$(ATOMIC_SONAME)' >> debian/shlibs.common
+	$(foreach ml,32 64 n32 x32 hf sf, \
+	  echo 'libgcc_s $(GCC_SONAME) $(subst lib,lib$(ml),$(p_lgcc))' > debian/shlibs.common$(ml); \
+	  echo 'libstdc++ $(CXX_SONAME) $(subst lib,lib$(ml),$(p_lib))' >> debian/shlibs.common$(ml); \
+	  echo 'libquadmath $(QUADMATH_SONAME) lib$(ml)quadmath$(QUADMATH_SONAME)' >> debian/shlibs.common$(ml); \
+	  echo 'libatomic $(ATOMIC_SONAME) lib$(ml)atomic$(ATOMIC_SONAME)' >> debian/shlibs.common$(ml); \
+	)
+endif
+
+	@echo XXXXX `date -R`
+	find $(d) ! -type d -print
+	@echo XXXXX
+	touch $(install_stamp)
+
+$(install_jit_stamp): $(build_jit_stamp) $(install_stamp)
+	dh_testdir
+	dh_testroot
+	rm -rf $(d)-jit
+	mkdir -p $(d)-jit/$(PF)
+
+	$(SET_PATH) \
+	  biarch_multidir_names=none \
+	    $(MAKE) -C $(builddir_jit) \
+		CC="$(CC_FOR_JIT)" \
+		$(CFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS) \
+		DESTDIR=$(CURDIR)/$(d)-jit \
+		    install
+
+	: # copy files to the standard build
+	cp -a $(d)-jit/$(PF)/include/libgccjit*.h \
+		$(d)/$(gcc_lib_dir)/include/.
+	cp -a $(d)-jit/$(PF)/lib/libgccjit.so* \
+		$(d)/$(usr_lib)/.
+	cp -a $(d)-jit/$(PF)/share/info/libgccjit* \
+		$(d)/$(PF)/share/info/.
+
+	@echo XXXXX `date -R`
+	touch $(install_jit_stamp)
+
+$(install_hppa64_stamp): $(build_hppa64_stamp)
+	dh_testdir
+	dh_testroot
+	rm -rf $(d_hppa64)
+	mkdir -p $(d_hppa64)/$(PF)
+
+	$(SET_PATH) \
+	    $(MAKE) -C $(builddir_hppa64) \
+		CC="$(CC)" \
+		$(CFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS) \
+		DESTDIR=$(CURDIR)/$(d_hppa64) \
+		    install
+
+	: # remove files not needed
+	rm -rf $(d_hppa64)/$(PF)/info $(d_hppa64)/$(PF)/share/info
+	rm -rf $(d_hppa64)/$(PF)/man $(d_hppa64)/$(PF)/share/man
+	rm -rf $(d_hppa64)/$(PF)/lib/gcc/hppa64-linux-gnu/$(BASE_VERSION)/plugin
+	rm -f $(d_hppa64)/$(PF)/lib/libiberty.a
+	rm -f $(d_hppa64)/$(PF)/lib/libcc1.*
+	rm -f $(d_hppa64)/$(PF)/bin/*{gcov,gcov-dump,gcov-tool,gccbug,gcc}
+
+	rm -rf $(d_hppa64)/$(PF)/hppa64-linux-gnu
+	rm -rf $(d_hppa64)/$(PF)/lib/gcc/hppa64-linux-gnu/$(BASE_VERSION)/install-tools
+
+ifeq ($(versioned_packages),yes)
+	for i in cpp gcc-ar gcc-nm gcc-ranlib; do \
+	  mv -f $(d_hppa64)/$(PF)/bin/hppa64-linux-gnu-$$i \
+		$(d_hppa64)/$(PF)/bin/hppa64-linux-gnu-$$i$(pkg_ver); \
+	done
+endif
+	mkdir -p $(d_hppa64)/$(PF)/share/man/man1
+	for i in gcc-ar gcc-nm gcc-ranlib; do \
+	  ln -sf $$i$(pkg_ver).1.gz \
+	    $(d_hppa64)/$(PF)/share/man/man1/hppa64-linux-gnu-$$i$(pkg_ver).1.gz; \
+	done
+ifneq ($(GFDL_INVARIANT_FREE),yes)
+	for i in cpp gcc; do \
+	  ln -sf $$i$(pkg_ver).1.gz \
+	    $(d_hppa64)/$(PF)/share/man/man1/hppa64-linux-gnu-$$i$(pkg_ver).1.gz; \
+	done
+endif
+
+	touch $(install_hppa64_stamp)
+
+$(install_neon_stamp): $(build_neon_stamp)
+	dh_testdir
+	dh_testroot
+	rm -rf $(d_neon)
+	mkdir -p $(d_neon)/$(PF)
+
+	$(SET_PATH) \
+	    $(MAKE) -C $(builddir_neon) \
+		CC="$(CC)" \
+		$(CFLAGS_TO_PASS) \
+		$(LDFLAGS_TO_PASS) \
+		DESTDIR=$(CURDIR)/$(d_neon) \
+		    install
+	touch $(install_neon_stamp)
+
+# ----------------------------------------------------------------------
+# Build architecture-dependent files here.
+debian/arch_binaries.all: $(foreach i,$(arch_binaries),$(binary_stamp)-$(i))
+	cd debian; xargs -r du -s < arch_binaries | sort -nr | awk '{print $$2}' \
+		> arch_binaries.tmp
+	mv debian/arch_binaries.tmp debian/arch_binaries
+	sed -i 's/ /\n/g' debian/arch_binaries.epoch || touch debian/arch_binaries.epoch
+	cat debian/arch_binaries debian/arch_binaries.epoch > debian/arch_binaries.all
+
+binary-arch: debian/arch_binaries.all
+	dh_compress $(foreach p,$(shell echo `cat debian/arch_binaries.all`),-p$(p)) \
+	  -X.log.xz -X.sum.xz -X.java -X.c -X.txt -X.tag -X.map -XREADME.Bugs
+ifeq ($(i586_symlinks),yes)
+	cd debian; \
+	for x in $$(find `cat arch_binaries` -type l -name 'i686-*'); do \
+	  link=$$(echo $$x | sed 's/i686-/i586-/'); \
+	  tgt=$$(basename $$x); \
+	  echo "Adding symlink: $$link -> $$tgt"; \
+	  rm -f $$link; cp -a $$x $$link; \
+	done
+endif
+	dh_fixperms $(foreach p,$(shell echo `cat debian/arch_binaries.all`),-p$(p))
+	dh_gencontrol $(foreach p,$(shell echo `cat debian/arch_binaries`),-p$(p)) \
+	  -- -v$(DEB_VERSION) $(common_substvars)
+	@set -e; \
+	pkgs='$(strip $(foreach p,$(shell echo `cat debian/arch_binaries.epoch`),-p$(p)))'; \
+	if [ -n "$$pkgs" ]; then \
+	  echo dh_gencontrol $$pkgs -- -v$(DEB_EVERSION) $(common_substvars); \
+	  dh_gencontrol $$pkgs -- -v$(DEB_EVERSION) $(common_substvars); \
+	fi
+	dh_installdeb $(foreach p,$(shell echo `cat debian/arch_binaries.all`),-p$(p))
+	dh_md5sums $(foreach p,$(shell echo `cat debian/arch_binaries.all`),-p$(p))
+	dh_builddeb $(foreach p,$(shell echo `cat debian/arch_binaries.all`),-p$(p))
+ifeq ($(with_check),yes)
+	@echo Done
+#	: # Send Email about sucessfull build.
+#	# cat raw-test-summary | sh; echo "Sent mail to $(S_EMAIL)"
+endif
+
+	: # remove empty directories, when all components are in place
+	-find $(d) -type d -empty -delete
+
+	@echo "Listing installed files not included in any package:"
+	-find $(d) ! -type d
+
+	@echo XXXXX `date -R`
+
+# ----------------------------------------------------------------------
+# Build architecture-independent files here.
+debian/indep_binaries.all: $(foreach i,$(indep_binaries),$(binary_stamp)-$(i))
+	cd debian; xargs -r du -s < indep_binaries | sort -nr | awk '{print $$2}' \
+		> indep_binaries.tmp
+	mv debian/indep_binaries.tmp debian/indep_binaries
+	sed -i 's/ /\n/g' debian/indep_binaries.epoch || touch debian/indep_binaries.epoch
+	cat debian/indep_binaries debian/indep_binaries.epoch > debian/indep_binaries.all
+
+binary-indep: debian/indep_binaries.all
+	dh_compress $(foreach p,$(shell echo `cat debian/indep_binaries.all`),-p$(p)) \
+	  -X.log.xz -X.sum.xz -X.java -X.c -X.txt -X.tag -X.map -XREADME.Bugs
+	dh_fixperms $(foreach p,$(shell echo `cat debian/indep_binaries.all`),-p$(p))
+	: # the export should be harmless for the binary indep packages of a native build
+	export DEB_HOST_ARCH=$(TARGET); \
+	dh_gencontrol $(foreach p,$(shell echo `cat debian/indep_binaries`),-p$(p)) \
+	  -- -v$(DEB_VERSION) $(common_substvars)
+	@set -e; \
+	export DEB_HOST_ARCH=$(TARGET); \
+	pkgs='$(strip $(foreach p,$(shell echo `cat debian/indep_binaries.epoch`),-p$(p)))'; \
+	if [ -n "$$pkgs" ]; then \
+	  echo dh_gencontrol $$pkgs -- -v$(DEB_EVERSION) $(common_substvars); \
+	  dh_gencontrol $$pkgs -- -v$(DEB_EVERSION) $(common_substvars); \
+	fi
+
+ifneq (,$(filter $(DEB_TARGET_ARCH), mips mipsel mips64 mips64el mipsn32 mipsn32el))
+	for p in `cat debian/indep_binaries debian/indep_binaries.epoch`; do \
+	  p=$${p#-p*}; \
+	  case "$$p" in \
+	    lib64*)  echo mangle $$p; sed -i -r '/^(Dep|Rec|Sug)/s/libn?32[^,]+(, *|$$)//g;/^(Dep|Rec|Sug)/s/$(p_lgcc)/$(p_l64gcc)/;/^(Dep|Rec|Sug)/s/ *, *$$//' debian/$$p/DEBIAN/control;; \
+	    libn32*) echo mangle $$p; sed -i -r '/^(Dep|Rec|Sug)/s/lib64[^,]+(, *|$$)//g;/^(Dep|Rec|Sug)/s/$(p_lgcc)/$(p_ln32gcc)/;/^(Dep|Rec|Sug)/s/ *, *$$//' debian/$$p/DEBIAN/control;; \
+	  esac; \
+	done
+endif
+
+	dh_installdeb $(foreach p,$(shell echo `cat debian/indep_binaries.all`),-p$(p))
+	dh_md5sums $(foreach p,$(shell echo `cat debian/indep_binaries.all`),-p$(p))
+	dh_builddeb $(foreach p,$(shell echo `cat debian/indep_binaries.all`),-p$(p))
+
+	@echo XXXXX `date -R`
+
+source diff:
+	@echo >&2 'source and diff are obsolete - use dpkg-source -b'; false
+
+binary: binary-indep binary-arch
+.PHONY: build clean binary-indep binary-arch binary 
+.PRECIOUS: $(stampdir)/%-stamp debian/indep_binaries.all debian/arch_binaries.all
--- gcc-6-6.4.0.orig/debian/runcheck.sh
+++ gcc-6-6.4.0/debian/runcheck.sh
@@ -0,0 +1,23 @@
+#! /bin/sh
+
+mkdir -p build
+
+abi=${CC##* }
+base=build/runcheck$abi
+
+cat >$base.c <<EOF
+#include <stdio.h>
+int main()
+{
+	printf("$abi");
+	return 0;
+}
+EOF
+
+
+if ${CC:-gcc} -o $base $base.c 2>/dev/null; then
+  if [ "$($base 2>&1)" = "$abi" ]; then
+    printf "%s" $abi > $base.out
+    printf "%s" $abi
+  fi
+fi
--- gcc-6-6.4.0.orig/debian/source.lintian-overrides
+++ gcc-6-6.4.0/debian/source.lintian-overrides
@@ -0,0 +1,4 @@
+gcc-6 source: invalid-arch-string-in-source-relation
+gcc-6 source: quilt-build-dep-but-no-series-file
+# lintian can't handle (>= ${gcc:Version})
+gcc-6 source: weak-library-dev-dependency
--- gcc-6-6.4.0.orig/debian/source.lintian-overrides.in
+++ gcc-6-6.4.0/debian/source.lintian-overrides.in
@@ -0,0 +1,4 @@
+@SRC@ source: invalid-arch-string-in-source-relation
+@SRC@ source: quilt-build-dep-but-no-series-file
+# lintian can't handle (>= ${gcc:Version})
+@SRC@ source: weak-library-dev-dependency
--- gcc-6-6.4.0.orig/debian/source/format
+++ gcc-6-6.4.0/debian/source/format
@@ -0,0 +1 @@
+1.0
--- gcc-6-6.4.0.orig/debian/watch
+++ gcc-6-6.4.0/debian/watch
@@ -0,0 +1,3 @@
+version=2
+ftp://gcc.gnu.org/pub/gcc/releases/gcc-(6\.[\d\.]*)/ \
+	gcc-([\d\.]+)\.tar\.xz debian uupdate